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1/*
2 * drivers/amvdec_ports/decoder/aml_hevc_parser.h
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18
19#ifndef AML_HEVC_PARSER_H
20#define AML_HEVC_PARSER_H
21
22#define MAX_DPB_SIZE 16 // A.4.1
23#define MAX_REFS 16
24
25#define MAX_NB_THREADS 16
26#define SHIFT_CTB_WPP 2
27
28/**
29 * 7.4.2.1
30 */
31#define MAX_SUB_LAYERS 7
32#define MAX_VPS_COUNT 16
33#define MAX_SPS_COUNT 32
34#define MAX_PPS_COUNT 256
35#define MAX_SHORT_TERM_RPS_COUNT 64
36#define MAX_CU_SIZE 128
37
38//TODO: check if this is really the maximum
39#define MAX_TRANSFORM_DEPTH 5
40
41#define MAX_TB_SIZE 32
42#define MAX_PB_SIZE 64
43#define MAX_LOG2_CTB_SIZE 6
44#define MAX_QP 51
45#define DEFAULT_INTRA_TC_OFFSET 2
46
47#define HEVC_CONTEXTS 183
48
49#define MRG_MAX_NUM_CANDS 5
50
51#define L0 0
52#define L1 1
53
54#define EPEL_EXTRA_BEFORE 1
55#define EPEL_EXTRA_AFTER 2
56#define EPEL_EXTRA 3
57
58/**
59 * Value of the luma sample at position (x, y) in the 2D array tab.
60 */
61#define SAMPLE(tab, x, y) ((tab)[(y) * s->sps->width + (x)])
62#define SAMPLE_CTB(tab, x, y) ((tab)[(y) * min_cb_width + (x)])
63#define SAMPLE_CBF(tab, x, y) ((tab)[((y) & ((1<<log2_trafo_size)-1)) * MAX_CU_SIZE + ((x) & ((1<<log2_trafo_size)-1))])
64
65#define IS_IDR(s) (s->nal_unit_type == NAL_IDR_W_RADL || s->nal_unit_type == NAL_IDR_N_LP)
66#define IS_BLA(s) (s->nal_unit_type == NAL_BLA_W_RADL || s->nal_unit_type == NAL_BLA_W_LP || \
67 s->nal_unit_type == NAL_BLA_N_LP)
68#define IS_IRAP(s) (s->nal_unit_type >= 16 && s->nal_unit_type <= 23)
69
70/**
71 * Table 7-3: NAL unit type codes
72 */
73enum HEVCNALUnitType {
74 HEVC_NAL_TRAIL_N = 0,
75 HEVC_NAL_TRAIL_R = 1,
76 HEVC_NAL_TSA_N = 2,
77 HEVC_NAL_TSA_R = 3,
78 HEVC_NAL_STSA_N = 4,
79 HEVC_NAL_STSA_R = 5,
80 HEVC_NAL_RADL_N = 6,
81 HEVC_NAL_RADL_R = 7,
82 HEVC_NAL_RASL_N = 8,
83 HEVC_NAL_RASL_R = 9,
84 HEVC_NAL_VCL_N10 = 10,
85 HEVC_NAL_VCL_R11 = 11,
86 HEVC_NAL_VCL_N12 = 12,
87 HEVC_NAL_VCL_R13 = 13,
88 HEVC_NAL_VCL_N14 = 14,
89 HEVC_NAL_VCL_R15 = 15,
90 HEVC_NAL_BLA_W_LP = 16,
91 HEVC_NAL_BLA_W_RADL = 17,
92 HEVC_NAL_BLA_N_LP = 18,
93 HEVC_NAL_IDR_W_RADL = 19,
94 HEVC_NAL_IDR_N_LP = 20,
95 HEVC_NAL_CRA_NUT = 21,
96 HEVC_NAL_IRAP_VCL22 = 22,
97 HEVC_NAL_IRAP_VCL23 = 23,
98 HEVC_NAL_RSV_VCL24 = 24,
99 HEVC_NAL_RSV_VCL25 = 25,
100 HEVC_NAL_RSV_VCL26 = 26,
101 HEVC_NAL_RSV_VCL27 = 27,
102 HEVC_NAL_RSV_VCL28 = 28,
103 HEVC_NAL_RSV_VCL29 = 29,
104 HEVC_NAL_RSV_VCL30 = 30,
105 HEVC_NAL_RSV_VCL31 = 31,
106 HEVC_NAL_VPS = 32,
107 HEVC_NAL_SPS = 33,
108 HEVC_NAL_PPS = 34,
109 HEVC_NAL_AUD = 35,
110 HEVC_NAL_EOS_NUT = 36,
111 HEVC_NAL_EOB_NUT = 37,
112 HEVC_NAL_FD_NUT = 38,
113 HEVC_NAL_SEI_PREFIX = 39,
114 HEVC_NAL_SEI_SUFFIX = 40,
115};
116
117enum HEVCSliceType {
118 HEVC_SLICE_B = 0,
119 HEVC_SLICE_P = 1,
120 HEVC_SLICE_I = 2,
121};
122
123enum {
124 // 7.4.3.1: vps_max_layers_minus1 is in [0, 62].
125 HEVC_MAX_LAYERS = 63,
126 // 7.4.3.1: vps_max_sub_layers_minus1 is in [0, 6].
127 HEVC_MAX_SUB_LAYERS = 7,
128 // 7.4.3.1: vps_num_layer_sets_minus1 is in [0, 1023].
129 HEVC_MAX_LAYER_SETS = 1024,
130
131 // 7.4.2.1: vps_video_parameter_set_id is u(4).
132 HEVC_MAX_VPS_COUNT = 16,
133 // 7.4.3.2.1: sps_seq_parameter_set_id is in [0, 15].
134 HEVC_MAX_SPS_COUNT = 16,
135 // 7.4.3.3.1: pps_pic_parameter_set_id is in [0, 63].
136 HEVC_MAX_PPS_COUNT = 64,
137
138 // A.4.2: MaxDpbSize is bounded above by 16.
139 HEVC_MAX_DPB_SIZE = 16,
140 // 7.4.3.1: vps_max_dec_pic_buffering_minus1[i] is in [0, MaxDpbSize - 1].
141 HEVC_MAX_REFS = HEVC_MAX_DPB_SIZE,
142
143 // 7.4.3.2.1: num_short_term_ref_pic_sets is in [0, 64].
144 HEVC_MAX_SHORT_TERM_REF_PIC_SETS = 64,
145 // 7.4.3.2.1: num_long_term_ref_pics_sps is in [0, 32].
146 HEVC_MAX_LONG_TERM_REF_PICS = 32,
147
148 // A.3: all profiles require that CtbLog2SizeY is in [4, 6].
149 HEVC_MIN_LOG2_CTB_SIZE = 4,
150 HEVC_MAX_LOG2_CTB_SIZE = 6,
151
152 // E.3.2: cpb_cnt_minus1[i] is in [0, 31].
153 HEVC_MAX_CPB_CNT = 32,
154
155 // A.4.1: in table A.6 the highest level allows a MaxLumaPs of 35 651 584.
156 HEVC_MAX_LUMA_PS = 35651584,
157 // A.4.1: pic_width_in_luma_samples and pic_height_in_luma_samples are
158 // constrained to be not greater than sqrt(MaxLumaPs * 8). Hence height/
159 // width are bounded above by sqrt(8 * 35651584) = 16888.2 samples.
160 HEVC_MAX_WIDTH = 16888,
161 HEVC_MAX_HEIGHT = 16888,
162
163 // A.4.1: table A.6 allows at most 22 tile rows for any level.
164 HEVC_MAX_TILE_ROWS = 22,
165 // A.4.1: table A.6 allows at most 20 tile columns for any level.
166 HEVC_MAX_TILE_COLUMNS = 20,
167
168 // 7.4.7.1: in the worst case (tiles_enabled_flag and
169 // entropy_coding_sync_enabled_flag are both set), entry points can be
170 // placed at the beginning of every Ctb row in every tile, giving an
171 // upper bound of (num_tile_columns_minus1 + 1) * PicHeightInCtbsY - 1.
172 // Only a stream with very high resolution and perverse parameters could
173 // get near that, though, so set a lower limit here with the maximum
174 // possible value for 4K video (at most 135 16x16 Ctb rows).
175 HEVC_MAX_ENTRY_POINT_OFFSETS = HEVC_MAX_TILE_COLUMNS * 135,
176};
177
178struct ShortTermRPS {
179 u32 num_negative_pics;
180 int num_delta_pocs;
181 int rps_idx_num_delta_pocs;
182 int delta_poc[32];
183 u8 used[32];
184};
185
186struct LongTermRPS {
187 int poc[32];
188 u8 used[32];
189 u8 nb_refs;
190};
191
192struct SliceHeader {
193 u32 pps_id;
194
195 ///< address (in raster order) of the first block in the current slice segment
196 u32 slice_segment_addr;
197 ///< address (in raster order) of the first block in the current slice
198 u32 slice_addr;
199
200 enum HEVCSliceType slice_type;
201
202 int pic_order_cnt_lsb;
203
204 u8 first_slice_in_pic_flag;
205 u8 dependent_slice_segment_flag;
206 u8 pic_output_flag;
207 u8 colour_plane_id;
208
209 ///< RPS coded in the slice header itself is stored here
210 int short_term_ref_pic_set_sps_flag;
211 int short_term_ref_pic_set_size;
212 struct ShortTermRPS slice_rps;
213 const struct ShortTermRPS *short_term_rps;
214 int long_term_ref_pic_set_size;
215 struct LongTermRPS long_term_rps;
216 u32 list_entry_lx[2][32];
217
218 u8 rpl_modification_flag[2];
219 u8 no_output_of_prior_pics_flag;
220 u8 slice_temporal_mvp_enabled_flag;
221
222 u32 nb_refs[2];
223
224 u8 slice_sample_adaptive_offset_flag[3];
225 u8 mvd_l1_zero_flag;
226
227 u8 cabac_init_flag;
228 u8 disable_deblocking_filter_flag; ///< slice_header_disable_deblocking_filter_flag
229 u8 slice_loop_filter_across_slices_enabled_flag;
230 u8 collocated_list;
231
232 u32 collocated_ref_idx;
233
234 int slice_qp_delta;
235 int slice_cb_qp_offset;
236 int slice_cr_qp_offset;
237
238 u8 cu_chroma_qp_offset_enabled_flag;
239
240 int beta_offset; ///< beta_offset_div2 * 2
241 int tc_offset; ///< tc_offset_div2 * 2
242
243 u32 max_num_merge_cand; ///< 5 - 5_minus_max_num_merge_cand
244
245 u8 *entry_point_offset;
246 int * offset;
247 int * size;
248 int num_entry_point_offsets;
249
250 char slice_qp;
251
252 u8 luma_log2_weight_denom;
253 s16 chroma_log2_weight_denom;
254
255 s16 luma_weight_l0[16];
256 s16 chroma_weight_l0[16][2];
257 s16 chroma_weight_l1[16][2];
258 s16 luma_weight_l1[16];
259
260 s16 luma_offset_l0[16];
261 s16 chroma_offset_l0[16][2];
262
263 s16 luma_offset_l1[16];
264 s16 chroma_offset_l1[16][2];
265
266 int slice_ctb_addr_rs;
267};
268
269struct HEVCWindow {
270 u32 left_offset;
271 u32 right_offset;
272 u32 top_offset;
273 u32 bottom_offset;
274};
275
276struct AVRational{
277 int num; ///< numerator
278 int den; ///< denominator
279};
280
281struct VUI {
282 struct AVRational sar;
283
284 int overscan_info_present_flag;
285 int overscan_appropriate_flag;
286
287 int video_signal_type_present_flag;
288 int video_format;
289 int video_full_range_flag;
290 int colour_description_present_flag;
291 u8 colour_primaries;
292 u8 transfer_characteristic;
293 u8 matrix_coeffs;
294
295 int chroma_loc_info_present_flag;
296 int chroma_sample_loc_type_top_field;
297 int chroma_sample_loc_type_bottom_field;
298 int neutra_chroma_indication_flag;
299
300 int field_seq_flag;
301 int frame_field_info_present_flag;
302
303 int default_display_window_flag;
304 struct HEVCWindow def_disp_win;
305
306 int vui_timing_info_present_flag;
307 u32 vui_num_units_in_tick;
308 u32 vui_time_scale;
309 int vui_poc_proportional_to_timing_flag;
310 int vui_num_ticks_poc_diff_one_minus1;
311 int vui_hrd_parameters_present_flag;
312
313 int bitstream_restriction_flag;
314 int tiles_fixed_structure_flag;
315 int motion_vectors_over_pic_boundaries_flag;
316 int restricted_ref_pic_lists_flag;
317 int min_spatial_segmentation_idc;
318 int max_bytes_per_pic_denom;
319 int max_bits_per_min_cu_denom;
320 int log2_max_mv_length_horizontal;
321 int log2_max_mv_length_vertical;
322};
323
324struct PTLCommon {
325 u8 profile_space;
326 u8 tier_flag;
327 u8 profile_idc;
328 u8 profile_compatibility_flag[32];
329 u8 level_idc;
330 u8 progressive_source_flag;
331 u8 interlaced_source_flag;
332 u8 non_packed_constraint_flag;
333 u8 frame_only_constraint_flag;
334};
335
336struct PTL {
337 int general_profile_space;
338 u8 general_tier_flag;
339 int general_profile_idc;
340 int general_profile_compatibility_flag[32];
341 int general_level_idc;
342
343 u8 sub_layer_profile_present_flag[MAX_SUB_LAYERS];
344 u8 sub_layer_level_present_flag[MAX_SUB_LAYERS];
345
346 int sub_layer_profile_space[MAX_SUB_LAYERS];
347 u8 sub_layer_tier_flag[MAX_SUB_LAYERS];
348 int sub_layer_profile_idc[MAX_SUB_LAYERS];
349 u8 sub_layer_profile_compatibility_flags[MAX_SUB_LAYERS][32];
350 int sub_layer_level_idc[MAX_SUB_LAYERS];
351};
352
353struct HEVCVPS {
354 u8 vps_temporal_id_nesting_flag;
355 int vps_max_layers;
356 int vps_max_sub_layers; ///< vps_max_temporal_layers_minus1 + 1
357
358 struct PTL ptl;
359 int vps_sub_layer_ordering_info_present_flag;
360 u32 vps_max_dec_pic_buffering[HEVC_MAX_SUB_LAYERS];
361 u32 vps_num_reorder_pics[HEVC_MAX_SUB_LAYERS];
362 u32 vps_max_latency_increase[HEVC_MAX_SUB_LAYERS];
363 int vps_max_layer_id;
364 int vps_num_layer_sets; ///< vps_num_layer_sets_minus1 + 1
365 u8 vps_timing_info_present_flag;
366 u32 vps_num_units_in_tick;
367 u32 vps_time_scale;
368 u8 vps_poc_proportional_to_timing_flag;
369 int vps_num_ticks_poc_diff_one; ///< vps_num_ticks_poc_diff_one_minus1 + 1
370 int vps_num_hrd_parameters;
371
372 u8 data[4096];
373 int data_size;
374};
375
376struct ScalingList {
377 /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
378 * and size ID 3 only has 2 arrays, not 6. */
379 u8 sl[4][6][64];
380 u8 sl_dc[2][6];
381};
382
383struct HEVCSPS {
384 u8 vps_id;
385 int chroma_format_idc;
386 u8 separate_colour_plane_flag;
387
388 struct HEVCWindow output_window;
389 struct HEVCWindow pic_conf_win;
390
391 int bit_depth;
392 int bit_depth_chroma;
393 int pixel_shift;
394 int pix_fmt;
395
396 u32 log2_max_poc_lsb;
397 int pcm_enabled_flag;
398
399 int max_sub_layers;
400 struct {
401 int max_dec_pic_buffering;
402 int num_reorder_pics;
403 int max_latency_increase;
404 } temporal_layer[HEVC_MAX_SUB_LAYERS];
405 u8 temporal_id_nesting_flag;
406
407 struct VUI vui;
408 struct PTL ptl;
409
410 u8 scaling_list_enable_flag;
411 struct ScalingList scaling_list;
412
413 u32 nb_st_rps;
414 struct ShortTermRPS st_rps[HEVC_MAX_SHORT_TERM_REF_PIC_SETS];
415
416 u8 amp_enabled_flag;
417 u8 sao_enabled;
418
419 u8 long_term_ref_pics_present_flag;
420 u16 lt_ref_pic_poc_lsb_sps[HEVC_MAX_LONG_TERM_REF_PICS];
421 u8 used_by_curr_pic_lt_sps_flag[HEVC_MAX_LONG_TERM_REF_PICS];
422 u8 num_long_term_ref_pics_sps;
423
424 struct {
425 u8 bit_depth;
426 u8 bit_depth_chroma;
427 u32 log2_min_pcm_cb_size;
428 u32 log2_max_pcm_cb_size;
429 u8 loop_filter_disable_flag;
430 } pcm;
431 u8 sps_temporal_mvp_enabled_flag;
432 u8 sps_strong_intra_smoothing_enable_flag;
433
434 u32 log2_min_cb_size;
435 u32 log2_diff_max_min_coding_block_size;
436 u32 log2_min_tb_size;
437 u32 log2_max_trafo_size;
438 u32 log2_ctb_size;
439 u32 log2_min_pu_size;
440
441 int max_transform_hierarchy_depth_inter;
442 int max_transform_hierarchy_depth_intra;
443
444 int transform_skip_rotation_enabled_flag;
445 int transform_skip_context_enabled_flag;
446 int implicit_rdpcm_enabled_flag;
447 int explicit_rdpcm_enabled_flag;
448 int intra_smoothing_disabled_flag;
449 int high_precision_offsets_enabled_flag;
450 int persistent_rice_adaptation_enabled_flag;
451
452 ///< coded frame dimension in various units
453 int width;
454 int height;
455 int ctb_width;
456 int ctb_height;
457 int ctb_size;
458 int min_cb_width;
459 int min_cb_height;
460 int min_tb_width;
461 int min_tb_height;
462 int min_pu_width;
463 int min_pu_height;
464 int tb_mask;
465
466 int hshift[3];
467 int vshift[3];
468
469 int qp_bd_offset;
470
471 u8 data[4096];
472 int data_size;
473};
474
475struct HEVCPPS {
476 u32 sps_id; ///< seq_parameter_set_id
477
478 u8 sign_data_hiding_flag;
479
480 u8 cabac_init_present_flag;
481
482 int num_ref_idx_l0_default_active; ///< num_ref_idx_l0_default_active_minus1 + 1
483 int num_ref_idx_l1_default_active; ///< num_ref_idx_l1_default_active_minus1 + 1
484 int pic_init_qp_minus26;
485
486 u8 constrained_intra_pred_flag;
487 u8 transform_skip_enabled_flag;
488
489 u8 cu_qp_delta_enabled_flag;
490 int diff_cu_qp_delta_depth;
491
492 int cb_qp_offset;
493 int cr_qp_offset;
494 u8 pic_slice_level_chroma_qp_offsets_present_flag;
495 u8 weighted_pred_flag;
496 u8 weighted_bipred_flag;
497 u8 output_flag_present_flag;
498 u8 transquant_bypass_enable_flag;
499
500 u8 dependent_slice_segments_enabled_flag;
501 u8 tiles_enabled_flag;
502 u8 entropy_coding_sync_enabled_flag;
503
504 int num_tile_columns; ///< num_tile_columns_minus1 + 1
505 int num_tile_rows; ///< num_tile_rows_minus1 + 1
506 u8 uniform_spacing_flag;
507 u8 loop_filter_across_tiles_enabled_flag;
508
509 u8 seq_loop_filter_across_slices_enabled_flag;
510
511 u8 deblocking_filter_control_present_flag;
512 u8 deblocking_filter_override_enabled_flag;
513 u8 disable_dbf;
514 int beta_offset; ///< beta_offset_div2 * 2
515 int tc_offset; ///< tc_offset_div2 * 2
516
517 u8 scaling_list_data_present_flag;
518 struct ScalingList scaling_list;
519
520 u8 lists_modification_present_flag;
521 int log2_parallel_merge_level; ///< log2_parallel_merge_level_minus2 + 2
522 int num_extra_slice_header_bits;
523 u8 slice_header_extension_present_flag;
524 u8 log2_max_transform_skip_block_size;
525 u8 cross_component_prediction_enabled_flag;
526 u8 chroma_qp_offset_list_enabled_flag;
527 u8 diff_cu_chroma_qp_offset_depth;
528 u8 chroma_qp_offset_list_len_minus1;
529 char cb_qp_offset_list[6];
530 char cr_qp_offset_list[6];
531 u8 log2_sao_offset_scale_luma;
532 u8 log2_sao_offset_scale_chroma;
533
534 // Inferred parameters
535 u32 *column_width; ///< ColumnWidth
536 u32 *row_height; ///< RowHeight
537 u32 *col_bd; ///< ColBd
538 u32 *row_bd; ///< RowBd
539 int *col_idxX;
540
541 int *ctb_addr_rs_to_ts; ///< CtbAddrRSToTS
542 int *ctb_addr_ts_to_rs; ///< CtbAddrTSToRS
543 int *tile_id; ///< TileId
544 int *tile_pos_rs; ///< TilePosRS
545 int *min_tb_addr_zs; ///< MinTbAddrZS
546 int *min_tb_addr_zs_tab;///< MinTbAddrZS
547
548 u8 data[4096];
549 int data_size;
550};
551
552struct HEVCParamSets {
553 bool vps_parsed;
554 bool sps_parsed;
555 bool pps_parsed;
556 /* currently active parameter sets */
557 struct HEVCVPS vps;
558 struct HEVCSPS sps;
559 struct HEVCPPS pps;
560};
561
562#endif /* AML_HEVC_PARSER_H */
563
564
generated by cgit at 2024-05-17 07:56:21 (GMT)