blob: 7c1e5eba93b9f29102dda030671ff201e57932ac
1 | /* |
2 | * Copyright (C) 2017 Amlogic, Inc. All rights reserved. |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License as published by |
6 | * the Free Software Foundation; either version 2 of the License, or |
7 | * (at your option) any later version. |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
12 | * more details. |
13 | * |
14 | * You should have received a copy of the GNU General Public License along |
15 | * with this program; if not, write to the Free Software Foundation, Inc., |
16 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
17 | * |
18 | * Description: |
19 | */ |
20 | #include <linux/module.h> |
21 | #include <linux/slab.h> |
22 | #include <linux/timer.h> |
23 | #include <linux/delay.h> |
24 | #include <linux/kernel.h> |
25 | #include <uapi/linux/swab.h> |
26 | #include "../vdec_drv_if.h" |
27 | #include "../aml_vcodec_util.h" |
28 | #include "../aml_vcodec_dec.h" |
29 | #include "../aml_vcodec_drv.h" |
30 | #include "../aml_vcodec_adapt.h" |
31 | #include "../vdec_drv_base.h" |
32 | #include "../aml_vcodec_vfm.h" |
33 | #include "aml_hevc_parser.h" |
34 | |
35 | #define HEVC_NAL_TYPE(value) ((value >> 1) & 0x3F) |
36 | #define HEADER_BUFFER_SIZE (32 * 1024) |
37 | |
38 | /** |
39 | * struct hevc_fb - hevc decode frame buffer information |
40 | * @vdec_fb_va : virtual address of struct vdec_fb |
41 | * @y_fb_dma : dma address of Y frame buffer (luma) |
42 | * @c_fb_dma : dma address of C frame buffer (chroma) |
43 | * @poc : picture order count of frame buffer |
44 | * @reserved : for 8 bytes alignment |
45 | */ |
46 | struct hevc_fb { |
47 | uint64_t vdec_fb_va; |
48 | uint64_t y_fb_dma; |
49 | uint64_t c_fb_dma; |
50 | int32_t poc; |
51 | uint32_t reserved; |
52 | }; |
53 | |
54 | /** |
55 | * struct vdec_hevc_dec_info - decode information |
56 | * @dpb_sz : decoding picture buffer size |
57 | * @resolution_changed : resoltion change happen |
58 | * @reserved : for 8 bytes alignment |
59 | * @bs_dma : Input bit-stream buffer dma address |
60 | * @y_fb_dma : Y frame buffer dma address |
61 | * @c_fb_dma : C frame buffer dma address |
62 | * @vdec_fb_va : VDEC frame buffer struct virtual address |
63 | */ |
64 | struct vdec_hevc_dec_info { |
65 | uint32_t dpb_sz; |
66 | uint32_t resolution_changed; |
67 | uint32_t reserved; |
68 | uint64_t bs_dma; |
69 | uint64_t y_fb_dma; |
70 | uint64_t c_fb_dma; |
71 | uint64_t vdec_fb_va; |
72 | }; |
73 | |
74 | /** |
75 | * struct vdec_hevc_vsi - shared memory for decode information exchange |
76 | * between VPU and Host. |
77 | * The memory is allocated by VPU then mapping to Host |
78 | * in vpu_dec_init() and freed in vpu_dec_deinit() |
79 | * by VPU. |
80 | * AP-W/R : AP is writer/reader on this item |
81 | * VPU-W/R: VPU is write/reader on this item |
82 | * @hdr_buf : Header parsing buffer (AP-W, VPU-R) |
83 | * @list_free : free frame buffer ring list (AP-W/R, VPU-W) |
84 | * @list_disp : display frame buffer ring list (AP-R, VPU-W) |
85 | * @dec : decode information (AP-R, VPU-W) |
86 | * @pic : picture information (AP-R, VPU-W) |
87 | * @crop : crop information (AP-R, VPU-W) |
88 | */ |
89 | struct vdec_hevc_vsi { |
90 | char *header_buf; |
91 | int sps_size; |
92 | int pps_size; |
93 | int sei_size; |
94 | int head_offset; |
95 | struct vdec_hevc_dec_info dec; |
96 | struct vdec_pic_info pic; |
97 | struct vdec_pic_info cur_pic; |
98 | struct v4l2_rect crop; |
99 | bool is_combine; |
100 | int nalu_pos; |
101 | struct h265_param_sets ps; |
102 | }; |
103 | |
104 | /** |
105 | * struct vdec_hevc_inst - hevc decoder instance |
106 | * @num_nalu : how many nalus be decoded |
107 | * @ctx : point to aml_vcodec_ctx |
108 | * @vsi : VPU shared information |
109 | */ |
110 | struct vdec_hevc_inst { |
111 | unsigned int num_nalu; |
112 | struct aml_vcodec_ctx *ctx; |
113 | struct aml_vdec_adapt vdec; |
114 | struct vdec_hevc_vsi *vsi; |
115 | struct vcodec_vfm_s vfm; |
116 | struct aml_dec_params parms; |
117 | struct completion comp; |
118 | }; |
119 | |
120 | static void get_pic_info(struct vdec_hevc_inst *inst, |
121 | struct vdec_pic_info *pic) |
122 | { |
123 | *pic = inst->vsi->pic; |
124 | |
125 | aml_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", |
126 | pic->visible_width, pic->visible_height, |
127 | pic->coded_width, pic->coded_height); |
128 | aml_vcodec_debug(inst, "Y(%d, %d), C(%d, %d)", pic->y_bs_sz, |
129 | pic->y_len_sz, pic->c_bs_sz, pic->c_len_sz); |
130 | } |
131 | |
132 | static void get_crop_info(struct vdec_hevc_inst *inst, struct v4l2_rect *cr) |
133 | { |
134 | cr->left = inst->vsi->crop.left; |
135 | cr->top = inst->vsi->crop.top; |
136 | cr->width = inst->vsi->crop.width; |
137 | cr->height = inst->vsi->crop.height; |
138 | |
139 | aml_vcodec_debug(inst, "l=%d, t=%d, w=%d, h=%d", |
140 | cr->left, cr->top, cr->width, cr->height); |
141 | } |
142 | |
143 | static void get_dpb_size(struct vdec_hevc_inst *inst, unsigned int *dpb_sz) |
144 | { |
145 | *dpb_sz = inst->vsi->dec.dpb_sz; |
146 | aml_vcodec_debug(inst, "sz=%d", *dpb_sz); |
147 | } |
148 | |
149 | static u32 vdec_config_default_parms(u8 *parm) |
150 | { |
151 | u8 *pbuf = parm; |
152 | |
153 | pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;"); |
154 | pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:7;"); |
155 | pbuf += sprintf(pbuf, "hevc_double_write_mode:16;"); |
156 | pbuf += sprintf(pbuf, "hevc_buf_width:4096;"); |
157 | pbuf += sprintf(pbuf, "hevc_buf_height:2304;"); |
158 | pbuf += sprintf(pbuf, "save_buffer_mode:0;"); |
159 | pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:0;"); |
160 | pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:0;"); |
161 | |
162 | return parm - pbuf; |
163 | } |
164 | |
165 | static void vdec_parser_parms(struct vdec_hevc_inst *inst) |
166 | { |
167 | struct aml_vcodec_ctx *ctx = inst->ctx; |
168 | |
169 | if (ctx->config.parm.dec.parms_status & |
170 | V4L2_CONFIG_PARM_DECODE_CFGINFO) { |
171 | u8 *pbuf = ctx->config.buf; |
172 | |
173 | pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;"); |
174 | pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:%d;", |
175 | ctx->config.parm.dec.cfg.ref_buf_margin); |
176 | pbuf += sprintf(pbuf, "hevc_double_write_mode:%d;", |
177 | ctx->config.parm.dec.cfg.double_write_mode); |
178 | pbuf += sprintf(pbuf, "hevc_buf_width:4096;"); |
179 | pbuf += sprintf(pbuf, "hevc_buf_height:2304;"); |
180 | pbuf += sprintf(pbuf, "save_buffer_mode:0;"); |
181 | pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_mode:%d;", |
182 | ctx->config.parm.dec.cfg.canvas_mem_mode); |
183 | pbuf += sprintf(pbuf, "parm_v4l_canvas_mem_endian:%d;", |
184 | ctx->config.parm.dec.cfg.canvas_mem_endian); |
185 | ctx->config.length = pbuf - ctx->config.buf; |
186 | } else { |
187 | ctx->config.parm.dec.cfg.double_write_mode = 16; |
188 | ctx->config.length = vdec_config_default_parms(ctx->config.buf); |
189 | } |
190 | |
191 | inst->vdec.config = ctx->config; |
192 | inst->parms.cfg = ctx->config.parm.dec.cfg; |
193 | inst->parms.parms_status |= V4L2_CONFIG_PARM_DECODE_CFGINFO; |
194 | } |
195 | |
196 | static int vdec_hevc_init(struct aml_vcodec_ctx *ctx, unsigned long *h_vdec) |
197 | { |
198 | struct vdec_hevc_inst *inst = NULL; |
199 | int ret = -1; |
200 | |
201 | inst = kzalloc(sizeof(*inst), GFP_KERNEL); |
202 | if (!inst) |
203 | return -ENOMEM; |
204 | |
205 | inst->vdec.video_type = VFORMAT_HEVC; |
206 | inst->vdec.dev = ctx->dev->vpu_plat_dev; |
207 | inst->vdec.filp = ctx->dev->filp; |
208 | inst->vdec.ctx = ctx; |
209 | inst->ctx = ctx; |
210 | |
211 | vdec_parser_parms(inst); |
212 | |
213 | /* set play mode.*/ |
214 | if (ctx->is_drm_mode) |
215 | inst->vdec.port.flag |= PORT_FLAG_DRM; |
216 | |
217 | /* to eable hevc hw.*/ |
218 | inst->vdec.port.type = PORT_TYPE_HEVC; |
219 | |
220 | /* init vfm */ |
221 | inst->vfm.ctx = ctx; |
222 | inst->vfm.ada_ctx = &inst->vdec; |
223 | ret = vcodec_vfm_init(&inst->vfm); |
224 | if (ret) { |
225 | pr_err("%s, init vfm failed.\n", __func__); |
226 | goto err; |
227 | } |
228 | |
229 | ret = video_decoder_init(&inst->vdec); |
230 | if (ret) { |
231 | aml_vcodec_err(inst, "vdec_hevc init err=%d", ret); |
232 | goto err; |
233 | } |
234 | |
235 | /* probe info from the stream */ |
236 | inst->vsi = kzalloc(sizeof(struct vdec_hevc_vsi), GFP_KERNEL); |
237 | if (!inst->vsi) { |
238 | ret = -ENOMEM; |
239 | goto err; |
240 | } |
241 | |
242 | /* alloc the header buffer to be used cache sps or spp etc.*/ |
243 | inst->vsi->header_buf = kzalloc(HEADER_BUFFER_SIZE, GFP_KERNEL); |
244 | if (!inst->vsi) { |
245 | ret = -ENOMEM; |
246 | goto err; |
247 | } |
248 | |
249 | init_completion(&inst->comp); |
250 | |
251 | aml_vcodec_debug(inst, "hevc Instance >> %p", inst); |
252 | |
253 | ctx->ada_ctx = &inst->vdec; |
254 | *h_vdec = (unsigned long)inst; |
255 | |
256 | //dump_init(); |
257 | |
258 | return 0; |
259 | err: |
260 | if (inst) |
261 | vcodec_vfm_release(&inst->vfm); |
262 | if (inst && inst->vsi && inst->vsi->header_buf) |
263 | kfree(inst->vsi->header_buf); |
264 | if (inst && inst->vsi) |
265 | kfree(inst->vsi); |
266 | if (inst) |
267 | kfree(inst); |
268 | *h_vdec = 0; |
269 | |
270 | return ret; |
271 | } |
272 | |
273 | |
274 | static int refer_buffer_num(struct h265_SPS_t *sps) |
275 | { |
276 | int used_buf_num = 0; |
277 | int sps_pic_buf_diff = 0; |
278 | |
279 | if ((!sps->temporal_layer[0].num_reorder_pics) && |
280 | (sps->temporal_layer[0].max_dec_pic_buffering)) { |
281 | /* the range of sps_num_reorder_pics_0 is in |
282 | [0, sps_max_dec_pic_buffering_minus1_0] */ |
283 | used_buf_num = sps->temporal_layer[0].max_dec_pic_buffering; |
284 | } else |
285 | used_buf_num = sps->temporal_layer[0].num_reorder_pics; |
286 | |
287 | sps_pic_buf_diff = sps->temporal_layer[0].max_dec_pic_buffering - |
288 | sps->temporal_layer[0].num_reorder_pics + 1; |
289 | |
290 | if (sps_pic_buf_diff >= 4) |
291 | used_buf_num += 1; |
292 | |
293 | /*need one more for multi instance, as |
294 | apply_ref_pic_set() has no chanch to run to |
295 | to clear referenced flag in some case */ |
296 | used_buf_num++; |
297 | |
298 | /* for eos add more buffer to flush.*/ |
299 | used_buf_num++; |
300 | |
301 | return used_buf_num; |
302 | } |
303 | |
304 | static int vdec_get_dw_mode(struct vdec_hevc_inst *inst, int dw_mode) |
305 | { |
306 | u32 valid_dw_mode = inst->parms.cfg.double_write_mode; |
307 | int w = inst->parms.cfg.init_width; |
308 | int h = inst->parms.cfg.init_height; |
309 | u32 dw = 0x1; /*1:1*/ |
310 | |
311 | switch (valid_dw_mode) { |
312 | case 0x100: |
313 | if (w > 1920 && h > 1088) |
314 | dw = 0x4; /*1:2*/ |
315 | break; |
316 | case 0x200: |
317 | if (w > 1920 && h > 1088) |
318 | dw = 0x2; /*1:4*/ |
319 | break; |
320 | case 0x300: |
321 | if (w > 1280 && h > 720) |
322 | dw = 0x4; /*1:2*/ |
323 | break; |
324 | default: |
325 | dw = valid_dw_mode; |
326 | break; |
327 | } |
328 | |
329 | return dw; |
330 | } |
331 | |
332 | static int vdec_pic_scale(struct vdec_hevc_inst *inst, int length, int dw_mode) |
333 | { |
334 | int ret = 64; |
335 | |
336 | switch (vdec_get_dw_mode(inst, dw_mode)) { |
337 | case 0x0: /* only afbc, output afbc */ |
338 | ret = 64; |
339 | break; |
340 | case 0x1: /* afbc and (w x h), output YUV420 */ |
341 | ret = length; |
342 | break; |
343 | case 0x2: /* afbc and (w/4 x h/4), output YUV420 */ |
344 | case 0x3: /* afbc and (w/4 x h/4), output afbc and YUV420 */ |
345 | ret = length >> 2; |
346 | break; |
347 | case 0x4: /* afbc and (w/2 x h/2), output YUV420 */ |
348 | ret = length >> 1; |
349 | break; |
350 | case 0x10: /* (w x h), output YUV420-8bit)*/ |
351 | default: |
352 | ret = length; |
353 | break; |
354 | } |
355 | |
356 | return ret; |
357 | } |
358 | |
359 | static void fill_vdec_params(struct vdec_hevc_inst *inst, struct h265_SPS_t *sps) |
360 | { |
361 | struct vdec_pic_info *pic = &inst->vsi->pic; |
362 | struct vdec_hevc_dec_info *dec = &inst->vsi->dec; |
363 | struct v4l2_rect *rect = &inst->vsi->crop; |
364 | int dw = inst->parms.cfg.double_write_mode; |
365 | int margin = inst->parms.cfg.ref_buf_margin; |
366 | |
367 | /* fill visible area size that be used for EGL. */ |
368 | pic->visible_width = sps->width - (sps->output_window.left_offset + |
369 | sps->output_window.right_offset); |
370 | pic->visible_height = sps->height - (sps->output_window.top_offset + |
371 | sps->output_window.bottom_offset); |
372 | pic->visible_width = vdec_pic_scale(inst, pic->visible_width, dw); |
373 | pic->visible_height = vdec_pic_scale(inst, pic->visible_height, dw); |
374 | |
375 | /* calc visible ares. */ |
376 | rect->left = 0; |
377 | rect->top = 0; |
378 | rect->width = pic->visible_width; |
379 | rect->height = pic->visible_height; |
380 | |
381 | /* config canvas size that be used for decoder. */ |
382 | pic->coded_width = vdec_pic_scale(inst, ALIGN(sps->width, 32), dw); |
383 | pic->coded_height = vdec_pic_scale(inst, ALIGN(sps->height, 32), dw); |
384 | |
385 | pic->y_len_sz = pic->coded_width * pic->coded_height; |
386 | pic->c_len_sz = pic->y_len_sz >> 1; |
387 | |
388 | /* calc DPB size */ |
389 | dec->dpb_sz = refer_buffer_num(sps) + margin; |
390 | |
391 | inst->parms.ps.visible_width = pic->visible_width; |
392 | inst->parms.ps.visible_height = pic->visible_height; |
393 | inst->parms.ps.coded_width = pic->coded_width; |
394 | inst->parms.ps.coded_height = pic->coded_height; |
395 | inst->parms.ps.dpb_size = dec->dpb_sz; |
396 | inst->parms.parms_status |= V4L2_CONFIG_PARM_DECODE_PSINFO; |
397 | |
398 | pr_info("[%d] The stream infos, dw: %d, coded:(%d x %d), visible:(%d x %d), DPB: %d, margin: %d\n", |
399 | inst->ctx->id, dw, pic->coded_width, pic->coded_height, |
400 | pic->visible_width, pic->visible_height, |
401 | dec->dpb_sz - margin, margin); |
402 | } |
403 | |
404 | static int stream_parse_by_ucode(struct vdec_hevc_inst *inst, u8 *buf, u32 size) |
405 | { |
406 | int ret = 0; |
407 | struct aml_vdec_adapt *vdec = &inst->vdec; |
408 | |
409 | ret = vdec_vframe_write(vdec, buf, size, 0); |
410 | if (ret < 0) { |
411 | pr_err("write frame data failed. err: %d\n", ret); |
412 | return ret; |
413 | } |
414 | |
415 | /* wait ucode parse ending. */ |
416 | wait_for_completion_timeout(&inst->comp, |
417 | msecs_to_jiffies(1000)); |
418 | |
419 | return inst->vsi->dec.dpb_sz ? 0 : -1; |
420 | } |
421 | |
422 | static int stream_parse(struct vdec_hevc_inst *inst, u8 *buf, u32 size) |
423 | { |
424 | int ret = 0; |
425 | struct h265_param_sets *ps = NULL; |
426 | |
427 | ps = kzalloc(sizeof(struct h265_param_sets), GFP_KERNEL); |
428 | if (ps == NULL) |
429 | return -ENOMEM; |
430 | |
431 | ret = h265_decode_extradata_ps(buf, size, ps); |
432 | if (ret) { |
433 | pr_err("parse extra data failed. err: %d\n", ret); |
434 | goto out; |
435 | } |
436 | |
437 | if (ps->sps_parsed) |
438 | fill_vdec_params(inst, &ps->sps); |
439 | |
440 | ret = ps->sps_parsed ? 0 : -1; |
441 | out: |
442 | kfree(ps); |
443 | |
444 | return ret; |
445 | } |
446 | |
447 | static int vdec_hevc_probe(unsigned long h_vdec, |
448 | struct aml_vcodec_mem *bs, void *out) |
449 | { |
450 | struct vdec_hevc_inst *inst = |
451 | (struct vdec_hevc_inst *)h_vdec; |
452 | struct stream_info *st; |
453 | u8 *buf = (u8 *)bs->vaddr; |
454 | u32 size = bs->size; |
455 | int ret = 0; |
456 | |
457 | st = (struct stream_info *)buf; |
458 | if (inst->ctx->is_drm_mode && (st->magic == DRMe || st->magic == DRMn)) |
459 | return 0; |
460 | |
461 | if (st->magic == NORe || st->magic == NORn) |
462 | ret = stream_parse(inst, st->data, st->length); |
463 | else { |
464 | if (inst->ctx->param_sets_from_ucode) |
465 | ret = stream_parse_by_ucode(inst, buf, size); |
466 | else |
467 | ret = stream_parse(inst, buf, size); |
468 | } |
469 | |
470 | inst->vsi->cur_pic = inst->vsi->pic; |
471 | |
472 | return ret; |
473 | } |
474 | |
475 | static void vdec_hevc_deinit(unsigned long h_vdec) |
476 | { |
477 | ulong flags; |
478 | struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec; |
479 | struct aml_vcodec_ctx *ctx = inst->ctx; |
480 | |
481 | aml_vcodec_debug_enter(inst); |
482 | |
483 | video_decoder_release(&inst->vdec); |
484 | |
485 | vcodec_vfm_release(&inst->vfm); |
486 | |
487 | //dump_deinit(); |
488 | |
489 | spin_lock_irqsave(&ctx->slock, flags); |
490 | if (inst->vsi && inst->vsi->header_buf) |
491 | kfree(inst->vsi->header_buf); |
492 | |
493 | if (inst->vsi) |
494 | kfree(inst->vsi); |
495 | |
496 | kfree(inst); |
497 | |
498 | ctx->drv_handle = 0; |
499 | spin_unlock_irqrestore(&ctx->slock, flags); |
500 | } |
501 | |
502 | static int vdec_hevc_get_fb(struct vdec_hevc_inst *inst, struct vdec_v4l2_buffer **out) |
503 | { |
504 | return get_fb_from_queue(inst->ctx, out); |
505 | } |
506 | |
507 | static void vdec_hevc_get_vf(struct vdec_hevc_inst *inst, struct vdec_v4l2_buffer **out) |
508 | { |
509 | struct vframe_s *vf = NULL; |
510 | struct vdec_v4l2_buffer *fb = NULL; |
511 | |
512 | vf = peek_video_frame(&inst->vfm); |
513 | if (!vf) { |
514 | aml_vcodec_debug(inst, "there is no vframe."); |
515 | *out = NULL; |
516 | return; |
517 | } |
518 | |
519 | vf = get_video_frame(&inst->vfm); |
520 | if (!vf) { |
521 | aml_vcodec_debug(inst, "the vframe is avalid."); |
522 | *out = NULL; |
523 | return; |
524 | } |
525 | |
526 | atomic_set(&vf->use_cnt, 1); |
527 | |
528 | fb = (struct vdec_v4l2_buffer *)vf->v4l_mem_handle; |
529 | fb->vf_handle = (unsigned long)vf; |
530 | fb->status = FB_ST_DISPLAY; |
531 | |
532 | *out = fb; |
533 | |
534 | //pr_info("%s, %d\n", __func__, fb->base_y.bytes_used); |
535 | //dump_write(fb->base_y.vaddr, fb->base_y.bytes_used); |
536 | //dump_write(fb->base_c.vaddr, fb->base_c.bytes_used); |
537 | |
538 | /* convert yuv format. */ |
539 | //swap_uv(fb->base_c.vaddr, fb->base_c.size); |
540 | } |
541 | |
542 | static int vdec_write_nalu(struct vdec_hevc_inst *inst, |
543 | u8 *buf, u32 size, u64 ts) |
544 | { |
545 | int ret = 0; |
546 | struct aml_vdec_adapt *vdec = &inst->vdec; |
547 | |
548 | ret = vdec_vframe_write(vdec, buf, size, ts); |
549 | |
550 | return ret; |
551 | } |
552 | |
553 | static bool monitor_res_change(struct vdec_hevc_inst *inst, u8 *buf, u32 size) |
554 | { |
555 | int ret = 0, i = 0, j = 0; |
556 | u8 *p = buf; |
557 | int len = size; |
558 | u32 type; |
559 | |
560 | for (i = 4; i < size; i++) { |
561 | j = find_start_code(p, len); |
562 | if (j > 0) { |
563 | len = size - (p - buf); |
564 | type = HEVC_NAL_TYPE(p[j]); |
565 | if (type != HEVC_NAL_AUD && |
566 | (type > HEVC_NAL_PPS || type < HEVC_NAL_VPS)) |
567 | break; |
568 | |
569 | if (type == HEVC_NAL_SPS) { |
570 | ret = stream_parse(inst, p, len); |
571 | if (ret) |
572 | break; |
573 | } |
574 | p += j; |
575 | } |
576 | p++; |
577 | } |
578 | |
579 | if (!ret && (inst->vsi->cur_pic.coded_width != |
580 | inst->vsi->pic.coded_width || |
581 | inst->vsi->cur_pic.coded_height != |
582 | inst->vsi->pic.coded_height)) { |
583 | inst->vsi->cur_pic = inst->vsi->pic; |
584 | return true; |
585 | } |
586 | |
587 | return false; |
588 | } |
589 | |
590 | static int vdec_hevc_decode(unsigned long h_vdec, struct aml_vcodec_mem *bs, |
591 | u64 timestamp, bool *res_chg) |
592 | { |
593 | struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec; |
594 | struct aml_vdec_adapt *vdec = &inst->vdec; |
595 | struct stream_info *st; |
596 | u8 *buf; |
597 | u32 size; |
598 | int ret = -1; |
599 | |
600 | if (bs == NULL) |
601 | return -1; |
602 | |
603 | if (vdec_input_full(vdec)) |
604 | return -EAGAIN; |
605 | |
606 | buf = (u8 *)bs->vaddr; |
607 | size = bs->size; |
608 | st = (struct stream_info *)buf; |
609 | |
610 | if (inst->ctx->is_drm_mode && (st->magic == DRMe || st->magic == DRMn)) |
611 | ret = vdec_vbuf_write(vdec, st->m.buf, sizeof(st->m.drm)); |
612 | else if (st->magic == NORe) |
613 | ret = vdec_vbuf_write(vdec, st->data, st->length); |
614 | else if (st->magic == NORn) |
615 | ret = vdec_write_nalu(inst, st->data, st->length, timestamp); |
616 | else if (inst->ctx->is_stream_mode) |
617 | ret = vdec_vbuf_write(vdec, buf, size); |
618 | else { |
619 | /*checked whether the resolution changes.*/ |
620 | if ((*res_chg = monitor_res_change(inst, buf, size))) |
621 | return 0; |
622 | |
623 | ret = vdec_write_nalu(inst, buf, size, timestamp); |
624 | } |
625 | |
626 | return ret; |
627 | } |
628 | |
629 | static void get_param_config_info(struct vdec_hevc_inst *inst, |
630 | struct aml_dec_params *parms) |
631 | { |
632 | if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_CFGINFO) |
633 | parms->cfg = inst->parms.cfg; |
634 | if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_PSINFO) |
635 | parms->ps = inst->parms.ps; |
636 | if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_HDRINFO) |
637 | parms->hdr = inst->parms.hdr; |
638 | if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_CNTINFO) |
639 | parms->cnt = inst->parms.cnt; |
640 | |
641 | parms->parms_status |= inst->parms.parms_status; |
642 | |
643 | aml_vcodec_debug(inst, "parms status: %u", parms->parms_status); |
644 | } |
645 | |
646 | static int vdec_hevc_get_param(unsigned long h_vdec, |
647 | enum vdec_get_param_type type, void *out) |
648 | { |
649 | int ret = 0; |
650 | struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec; |
651 | |
652 | if (!inst) { |
653 | pr_err("the hevc inst of dec is invalid.\n"); |
654 | return -1; |
655 | } |
656 | |
657 | switch (type) { |
658 | case GET_PARAM_DISP_FRAME_BUFFER: |
659 | vdec_hevc_get_vf(inst, out); |
660 | break; |
661 | |
662 | case GET_PARAM_FREE_FRAME_BUFFER: |
663 | ret = vdec_hevc_get_fb(inst, out); |
664 | break; |
665 | |
666 | case GET_PARAM_PIC_INFO: |
667 | get_pic_info(inst, out); |
668 | break; |
669 | |
670 | case GET_PARAM_DPB_SIZE: |
671 | get_dpb_size(inst, out); |
672 | break; |
673 | |
674 | case GET_PARAM_CROP_INFO: |
675 | get_crop_info(inst, out); |
676 | break; |
677 | |
678 | case GET_PARAM_CONFIG_INFO: |
679 | get_param_config_info(inst, out); |
680 | break; |
681 | default: |
682 | aml_vcodec_err(inst, "invalid get parameter type=%d", type); |
683 | ret = -EINVAL; |
684 | } |
685 | |
686 | return ret; |
687 | } |
688 | |
689 | static void set_param_write_sync(struct vdec_hevc_inst *inst) |
690 | { |
691 | complete(&inst->comp); |
692 | } |
693 | |
694 | static void set_param_ps_info(struct vdec_hevc_inst *inst, |
695 | struct aml_vdec_ps_infos *ps) |
696 | { |
697 | struct vdec_pic_info *pic = &inst->vsi->pic; |
698 | struct vdec_hevc_dec_info *dec = &inst->vsi->dec; |
699 | struct v4l2_rect *rect = &inst->vsi->crop; |
700 | |
701 | /* fill visible area size that be used for EGL. */ |
702 | pic->visible_width = ps->visible_width; |
703 | pic->visible_height = ps->visible_height; |
704 | |
705 | /* calc visible ares. */ |
706 | rect->left = 0; |
707 | rect->top = 0; |
708 | rect->width = pic->visible_width; |
709 | rect->height = pic->visible_height; |
710 | |
711 | /* config canvas size that be used for decoder. */ |
712 | pic->coded_width = ALIGN(ps->coded_width, 64); |
713 | pic->coded_height = ALIGN(ps->coded_height, 64); |
714 | pic->y_len_sz = pic->coded_width * pic->coded_height; |
715 | pic->c_len_sz = pic->y_len_sz >> 1; |
716 | |
717 | dec->dpb_sz = ps->dpb_size; |
718 | |
719 | inst->parms.ps = *ps; |
720 | inst->parms.parms_status |= |
721 | V4L2_CONFIG_PARM_DECODE_PSINFO; |
722 | |
723 | /*wake up*/ |
724 | complete(&inst->comp); |
725 | |
726 | pr_info("Parse from ucode, crop(%d x %d), coded(%d x %d) dpb: %d\n", |
727 | pic->visible_width, pic->visible_height, |
728 | pic->coded_width, pic->coded_height, |
729 | dec->dpb_sz); |
730 | } |
731 | |
732 | static void set_param_hdr_info(struct vdec_hevc_inst *inst, |
733 | struct aml_vdec_hdr_infos *hdr) |
734 | { |
735 | if (!(inst->parms.parms_status & |
736 | V4L2_CONFIG_PARM_DECODE_HDRINFO)) { |
737 | inst->parms.hdr = *hdr; |
738 | inst->parms.parms_status |= |
739 | V4L2_CONFIG_PARM_DECODE_HDRINFO; |
740 | aml_vdec_dispatch_event(inst->ctx, |
741 | V4L2_EVENT_SRC_CH_HDRINFO); |
742 | pr_info("H265 set HDR infos\n"); |
743 | } |
744 | } |
745 | |
746 | static void set_param_post_event(struct vdec_hevc_inst *inst, u32 *event) |
747 | { |
748 | aml_vdec_dispatch_event(inst->ctx, *event); |
749 | pr_info("H265 post event: %d\n", *event); |
750 | } |
751 | |
752 | static int vdec_hevc_set_param(unsigned long h_vdec, |
753 | enum vdec_set_param_type type, void *in) |
754 | { |
755 | int ret = 0; |
756 | struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec; |
757 | |
758 | if (!inst) { |
759 | pr_err("the hevc inst of dec is invalid.\n"); |
760 | return -1; |
761 | } |
762 | |
763 | switch (type) { |
764 | case SET_PARAM_WRITE_FRAME_SYNC: |
765 | set_param_write_sync(inst); |
766 | break; |
767 | |
768 | case SET_PARAM_PS_INFO: |
769 | set_param_ps_info(inst, in); |
770 | break; |
771 | |
772 | case SET_PARAM_HDR_INFO: |
773 | set_param_hdr_info(inst, in); |
774 | break; |
775 | |
776 | case SET_PARAM_POST_EVENT: |
777 | set_param_post_event(inst, in); |
778 | break; |
779 | default: |
780 | aml_vcodec_err(inst, "invalid set parameter type=%d", type); |
781 | ret = -EINVAL; |
782 | } |
783 | |
784 | return ret; |
785 | } |
786 | |
787 | static struct vdec_common_if vdec_hevc_if = { |
788 | .init = vdec_hevc_init, |
789 | .probe = vdec_hevc_probe, |
790 | .decode = vdec_hevc_decode, |
791 | .get_param = vdec_hevc_get_param, |
792 | .set_param = vdec_hevc_set_param, |
793 | .deinit = vdec_hevc_deinit, |
794 | }; |
795 | |
796 | struct vdec_common_if *get_hevc_dec_comm_if(void); |
797 | |
798 | struct vdec_common_if *get_hevc_dec_comm_if(void) |
799 | { |
800 | return &vdec_hevc_if; |
801 | } |
802 |