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path: root/drivers/amvdec_ports/decoder/vdec_hevc_if.c (plain)
blob: 1b06d776848f92dbeadb639d467b5f177ec3f614
1/*
2* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify
5* it under the terms of the GNU General Public License as published by
6* the Free Software Foundation; either version 2 of the License, or
7* (at your option) any later version.
8*
9* This program is distributed in the hope that it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*
14* You should have received a copy of the GNU General Public License along
15* with this program; if not, write to the Free Software Foundation, Inc.,
16* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*
18* Description:
19*/
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/timer.h>
23#include <linux/delay.h>
24#include <linux/kernel.h>
25#include <uapi/linux/swab.h>
26#include "../vdec_drv_if.h"
27#include "../aml_vcodec_util.h"
28#include "../aml_vcodec_dec.h"
29#include "../aml_vcodec_drv.h"
30#include "../aml_vcodec_adapt.h"
31#include "../vdec_drv_base.h"
32#include "../aml_vcodec_vfm.h"
33#include "aml_hevc_parser.h"
34
35#define HEVC_NAL_TYPE(value) ((value >> 1) & 0x3F)
36#define HEADER_BUFFER_SIZE (32 * 1024)
37
38/**
39 * struct hevc_fb - hevc decode frame buffer information
40 * @vdec_fb_va : virtual address of struct vdec_fb
41 * @y_fb_dma : dma address of Y frame buffer (luma)
42 * @c_fb_dma : dma address of C frame buffer (chroma)
43 * @poc : picture order count of frame buffer
44 * @reserved : for 8 bytes alignment
45 */
46struct hevc_fb {
47 uint64_t vdec_fb_va;
48 uint64_t y_fb_dma;
49 uint64_t c_fb_dma;
50 int32_t poc;
51 uint32_t reserved;
52};
53
54/**
55 * struct vdec_hevc_dec_info - decode information
56 * @dpb_sz : decoding picture buffer size
57 * @resolution_changed : resoltion change happen
58 * @reserved : for 8 bytes alignment
59 * @bs_dma : Input bit-stream buffer dma address
60 * @y_fb_dma : Y frame buffer dma address
61 * @c_fb_dma : C frame buffer dma address
62 * @vdec_fb_va : VDEC frame buffer struct virtual address
63 */
64struct vdec_hevc_dec_info {
65 uint32_t dpb_sz;
66 uint32_t resolution_changed;
67 uint32_t reserved;
68 uint64_t bs_dma;
69 uint64_t y_fb_dma;
70 uint64_t c_fb_dma;
71 uint64_t vdec_fb_va;
72};
73
74/**
75 * struct vdec_hevc_vsi - shared memory for decode information exchange
76 * between VPU and Host.
77 * The memory is allocated by VPU then mapping to Host
78 * in vpu_dec_init() and freed in vpu_dec_deinit()
79 * by VPU.
80 * AP-W/R : AP is writer/reader on this item
81 * VPU-W/R: VPU is write/reader on this item
82 * @hdr_buf : Header parsing buffer (AP-W, VPU-R)
83 * @list_free : free frame buffer ring list (AP-W/R, VPU-W)
84 * @list_disp : display frame buffer ring list (AP-R, VPU-W)
85 * @dec : decode information (AP-R, VPU-W)
86 * @pic : picture information (AP-R, VPU-W)
87 * @crop : crop information (AP-R, VPU-W)
88 */
89struct vdec_hevc_vsi {
90 char *header_buf;
91 int sps_size;
92 int pps_size;
93 int sei_size;
94 int head_offset;
95 struct vdec_hevc_dec_info dec;
96 struct vdec_pic_info pic;
97 struct vdec_pic_info cur_pic;
98 struct v4l2_rect crop;
99 bool is_combine;
100 int nalu_pos;
101 struct h265_param_sets ps;
102};
103
104/**
105 * struct vdec_hevc_inst - hevc decoder instance
106 * @num_nalu : how many nalus be decoded
107 * @ctx : point to aml_vcodec_ctx
108 * @vsi : VPU shared information
109 */
110struct vdec_hevc_inst {
111 unsigned int num_nalu;
112 struct aml_vcodec_ctx *ctx;
113 struct aml_vdec_adapt vdec;
114 struct vdec_hevc_vsi *vsi;
115 struct vcodec_vfm_s vfm;
116 struct aml_dec_params parms;
117 struct completion comp;
118};
119
120static void get_pic_info(struct vdec_hevc_inst *inst,
121 struct vdec_pic_info *pic)
122{
123 *pic = inst->vsi->pic;
124
125 aml_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)",
126 pic->visible_width, pic->visible_height,
127 pic->coded_width, pic->coded_height);
128 aml_vcodec_debug(inst, "Y(%d, %d), C(%d, %d)", pic->y_bs_sz,
129 pic->y_len_sz, pic->c_bs_sz, pic->c_len_sz);
130}
131
132static void get_crop_info(struct vdec_hevc_inst *inst, struct v4l2_rect *cr)
133{
134 cr->left = inst->vsi->crop.left;
135 cr->top = inst->vsi->crop.top;
136 cr->width = inst->vsi->crop.width;
137 cr->height = inst->vsi->crop.height;
138
139 aml_vcodec_debug(inst, "l=%d, t=%d, w=%d, h=%d",
140 cr->left, cr->top, cr->width, cr->height);
141}
142
143static void get_dpb_size(struct vdec_hevc_inst *inst, unsigned int *dpb_sz)
144{
145 *dpb_sz = inst->vsi->dec.dpb_sz;
146 aml_vcodec_debug(inst, "sz=%d", *dpb_sz);
147}
148
149static u32 vdec_config_default_parms(u8 *parm)
150{
151 u8 *pbuf = parm;
152
153 pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;");
154 pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:7;");
155 pbuf += sprintf(pbuf, "hevc_double_write_mode:16;");
156 pbuf += sprintf(pbuf, "hevc_buf_width:4096;");
157 pbuf += sprintf(pbuf, "hevc_buf_height:2304;");
158 pbuf += sprintf(pbuf, "save_buffer_mode:0;");
159
160 return parm - pbuf;
161}
162
163static void vdec_parser_parms(struct vdec_hevc_inst *inst)
164{
165 struct aml_vcodec_ctx *ctx = inst->ctx;
166
167 if (ctx->config.parm.dec.parms_status &
168 V4L2_CONFIG_PARM_DECODE_CFGINFO) {
169 u8 *pbuf = ctx->config.buf;
170
171 pbuf += sprintf(pbuf, "parm_v4l_codec_enable:1;");
172 pbuf += sprintf(pbuf, "parm_v4l_buffer_margin:%d;",
173 ctx->config.parm.dec.cfg.ref_buf_margin);
174 pbuf += sprintf(pbuf, "hevc_double_write_mode:%d;",
175 ctx->config.parm.dec.cfg.double_write_mode);
176 pbuf += sprintf(pbuf, "hevc_buf_width:4096;");
177 pbuf += sprintf(pbuf, "hevc_buf_height:2304;");
178 pbuf += sprintf(pbuf, "save_buffer_mode:0;");
179 ctx->config.length = pbuf - ctx->config.buf;
180 } else {
181 ctx->config.parm.dec.cfg.double_write_mode = 16;
182 ctx->config.length = vdec_config_default_parms(ctx->config.buf);
183 }
184
185 inst->vdec.config = ctx->config;
186 inst->parms.cfg = ctx->config.parm.dec.cfg;
187 inst->parms.parms_status |= V4L2_CONFIG_PARM_DECODE_CFGINFO;
188}
189
190static int vdec_hevc_init(struct aml_vcodec_ctx *ctx, unsigned long *h_vdec)
191{
192 struct vdec_hevc_inst *inst = NULL;
193 int ret = -1;
194
195 inst = kzalloc(sizeof(*inst), GFP_KERNEL);
196 if (!inst)
197 return -ENOMEM;
198
199 inst->vdec.video_type = VFORMAT_HEVC;
200 inst->vdec.dev = ctx->dev->vpu_plat_dev;
201 inst->vdec.filp = ctx->dev->filp;
202 inst->vdec.ctx = ctx;
203 inst->ctx = ctx;
204
205 vdec_parser_parms(inst);
206
207 /* set play mode.*/
208 if (ctx->is_drm_mode)
209 inst->vdec.port.flag |= PORT_FLAG_DRM;
210
211 /* to eable hevc hw.*/
212 inst->vdec.port.type = PORT_TYPE_HEVC;
213
214 /* init vfm */
215 inst->vfm.ctx = ctx;
216 inst->vfm.ada_ctx = &inst->vdec;
217 ret = vcodec_vfm_init(&inst->vfm);
218 if (ret) {
219 pr_err("%s, init vfm failed.\n", __func__);
220 goto err;
221 }
222
223 ret = video_decoder_init(&inst->vdec);
224 if (ret) {
225 aml_vcodec_err(inst, "vdec_hevc init err=%d", ret);
226 goto err;
227 }
228
229 /* probe info from the stream */
230 inst->vsi = kzalloc(sizeof(struct vdec_hevc_vsi), GFP_KERNEL);
231 if (!inst->vsi) {
232 ret = -ENOMEM;
233 goto err;
234 }
235
236 /* alloc the header buffer to be used cache sps or spp etc.*/
237 inst->vsi->header_buf = kzalloc(HEADER_BUFFER_SIZE, GFP_KERNEL);
238 if (!inst->vsi) {
239 ret = -ENOMEM;
240 goto err;
241 }
242
243 init_completion(&inst->comp);
244
245 aml_vcodec_debug(inst, "hevc Instance >> %p", inst);
246
247 ctx->ada_ctx = &inst->vdec;
248 *h_vdec = (unsigned long)inst;
249
250 //dump_init();
251
252 return 0;
253err:
254 if (inst)
255 vcodec_vfm_release(&inst->vfm);
256 if (inst && inst->vsi && inst->vsi->header_buf)
257 kfree(inst->vsi->header_buf);
258 if (inst && inst->vsi)
259 kfree(inst->vsi);
260 if (inst)
261 kfree(inst);
262 *h_vdec = 0;
263
264 return ret;
265}
266
267
268static int refer_buffer_num(struct h265_SPS_t *sps)
269{
270 int used_buf_num = 0;
271 int sps_pic_buf_diff = 0;
272
273 if ((!sps->temporal_layer[0].num_reorder_pics) &&
274 (sps->temporal_layer[0].max_dec_pic_buffering)) {
275 /* the range of sps_num_reorder_pics_0 is in
276 [0, sps_max_dec_pic_buffering_minus1_0] */
277 used_buf_num = sps->temporal_layer[0].max_dec_pic_buffering;
278 } else
279 used_buf_num = sps->temporal_layer[0].num_reorder_pics;
280
281 sps_pic_buf_diff = sps->temporal_layer[0].max_dec_pic_buffering -
282 sps->temporal_layer[0].num_reorder_pics + 1;
283
284 if (sps_pic_buf_diff >= 4)
285 used_buf_num += 1;
286
287 /*need one more for multi instance, as
288 apply_ref_pic_set() has no chanch to run to
289 to clear referenced flag in some case */
290 used_buf_num++;
291
292 /* for eos add more buffer to flush.*/
293 used_buf_num++;
294
295 return used_buf_num;
296}
297
298static int vdec_get_dw_mode(struct vdec_hevc_inst *inst, int dw_mode)
299{
300 u32 valid_dw_mode = inst->parms.cfg.double_write_mode;
301 int w = inst->parms.cfg.init_width;
302 int h = inst->parms.cfg.init_height;
303 u32 dw = 0x1; /*1:1*/
304
305 switch (valid_dw_mode) {
306 case 0x100:
307 if (w > 1920 && h > 1088)
308 dw = 0x4; /*1:2*/
309 break;
310 case 0x200:
311 if (w > 1920 && h > 1088)
312 dw = 0x2; /*1:4*/
313 break;
314 case 0x300:
315 if (w > 1280 && h > 720)
316 dw = 0x4; /*1:2*/
317 break;
318 default:
319 dw = valid_dw_mode;
320 break;
321 }
322
323 return dw;
324}
325
326static int vdec_pic_scale(struct vdec_hevc_inst *inst, int length, int dw_mode)
327{
328 int ret = 64;
329
330 switch (vdec_get_dw_mode(inst, dw_mode)) {
331 case 0x0: /* only afbc, output afbc */
332 ret = 64;
333 break;
334 case 0x1: /* afbc and (w x h), output YUV420 */
335 ret = length;
336 break;
337 case 0x2: /* afbc and (w/4 x h/4), output YUV420 */
338 case 0x3: /* afbc and (w/4 x h/4), output afbc and YUV420 */
339 ret = length >> 2;
340 break;
341 case 0x4: /* afbc and (w/2 x h/2), output YUV420 */
342 ret = length >> 1;
343 break;
344 case 0x10: /* (w x h), output YUV420-8bit)*/
345 default:
346 ret = length;
347 break;
348 }
349
350 return ret;
351}
352
353static void fill_vdec_params(struct vdec_hevc_inst *inst, struct h265_SPS_t *sps)
354{
355 struct vdec_pic_info *pic = &inst->vsi->pic;
356 struct vdec_hevc_dec_info *dec = &inst->vsi->dec;
357 struct v4l2_rect *rect = &inst->vsi->crop;
358 int dw = inst->parms.cfg.double_write_mode;
359 int margin = inst->parms.cfg.ref_buf_margin;
360
361 /* fill visible area size that be used for EGL. */
362 pic->visible_width = sps->width - (sps->output_window.left_offset +
363 sps->output_window.right_offset);
364 pic->visible_height = sps->height - (sps->output_window.top_offset +
365 sps->output_window.bottom_offset);
366 pic->visible_width = vdec_pic_scale(inst, pic->visible_width, dw);
367 pic->visible_height = vdec_pic_scale(inst, pic->visible_height, dw);
368
369 /* calc visible ares. */
370 rect->left = 0;
371 rect->top = 0;
372 rect->width = pic->visible_width;
373 rect->height = pic->visible_height;
374
375 /* config canvas size that be used for decoder. */
376 pic->coded_width = vdec_pic_scale(inst, ALIGN(sps->width, 32), dw);
377 pic->coded_height = vdec_pic_scale(inst, ALIGN(sps->height, 32), dw);
378
379 pic->y_len_sz = pic->coded_width * pic->coded_height;
380 pic->c_len_sz = pic->y_len_sz >> 1;
381
382 /* calc DPB size */
383 dec->dpb_sz = refer_buffer_num(sps) + margin;
384
385 inst->parms.ps.visible_width = pic->visible_width;
386 inst->parms.ps.visible_height = pic->visible_height;
387 inst->parms.ps.coded_width = pic->coded_width;
388 inst->parms.ps.coded_height = pic->coded_height;
389 inst->parms.ps.dpb_size = dec->dpb_sz;
390 inst->parms.parms_status |= V4L2_CONFIG_PARM_DECODE_PSINFO;
391
392 pr_info("[%d] The stream infos, dw: %d, coded:(%d x %d), visible:(%d x %d), DPB: %d, margin: %d\n",
393 inst->ctx->id, dw, pic->coded_width, pic->coded_height,
394 pic->visible_width, pic->visible_height,
395 dec->dpb_sz - margin, margin);
396}
397
398static int stream_parse_by_ucode(struct vdec_hevc_inst *inst, u8 *buf, u32 size)
399{
400 int ret = 0;
401 struct aml_vdec_adapt *vdec = &inst->vdec;
402
403 ret = vdec_vframe_write(vdec, buf, size, 0);
404 if (ret < 0) {
405 pr_err("write frame data failed. err: %d\n", ret);
406 return ret;
407 }
408
409 /* wait ucode parse ending. */
410 wait_for_completion_timeout(&inst->comp,
411 msecs_to_jiffies(1000));
412
413 return inst->vsi->dec.dpb_sz ? 0 : -1;
414}
415
416static int stream_parse(struct vdec_hevc_inst *inst, u8 *buf, u32 size)
417{
418 int ret = 0;
419 struct h265_param_sets *ps = NULL;
420
421 ps = kzalloc(sizeof(struct h265_param_sets), GFP_KERNEL);
422 if (ps == NULL)
423 return -ENOMEM;
424
425 ret = h265_decode_extradata_ps(buf, size, ps);
426 if (ret) {
427 pr_err("parse extra data failed. err: %d\n", ret);
428 goto out;
429 }
430
431 if (ps->sps_parsed)
432 fill_vdec_params(inst, &ps->sps);
433
434 ret = ps->sps_parsed ? 0 : -1;
435out:
436 kfree(ps);
437
438 return ret;
439}
440
441static int vdec_hevc_probe(unsigned long h_vdec,
442 struct aml_vcodec_mem *bs, void *out)
443{
444 struct vdec_hevc_inst *inst =
445 (struct vdec_hevc_inst *)h_vdec;
446 struct stream_info *st;
447 u8 *buf = (u8 *)bs->vaddr;
448 u32 size = bs->size;
449 int ret = 0;
450
451 st = (struct stream_info *)buf;
452 if (inst->ctx->is_drm_mode && (st->magic == DRMe || st->magic == DRMn))
453 return 0;
454
455 if (st->magic == NORe || st->magic == NORn)
456 ret = stream_parse(inst, st->data, st->length);
457 else {
458 if (inst->ctx->param_sets_from_ucode)
459 ret = stream_parse_by_ucode(inst, buf, size);
460 else
461 ret = stream_parse(inst, buf, size);
462 }
463
464 inst->vsi->cur_pic = inst->vsi->pic;
465
466 return ret;
467}
468
469static void vdec_hevc_deinit(unsigned long h_vdec)
470{
471 ulong flags;
472 struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec;
473 struct aml_vcodec_ctx *ctx = inst->ctx;
474
475 aml_vcodec_debug_enter(inst);
476
477 video_decoder_release(&inst->vdec);
478
479 vcodec_vfm_release(&inst->vfm);
480
481 //dump_deinit();
482
483 spin_lock_irqsave(&ctx->slock, flags);
484 if (inst->vsi && inst->vsi->header_buf)
485 kfree(inst->vsi->header_buf);
486
487 if (inst->vsi)
488 kfree(inst->vsi);
489
490 kfree(inst);
491
492 ctx->drv_handle = 0;
493 spin_unlock_irqrestore(&ctx->slock, flags);
494}
495
496static int vdec_hevc_get_fb(struct vdec_hevc_inst *inst, struct vdec_v4l2_buffer **out)
497{
498 return get_fb_from_queue(inst->ctx, out);
499}
500
501static void vdec_hevc_get_vf(struct vdec_hevc_inst *inst, struct vdec_v4l2_buffer **out)
502{
503 struct vframe_s *vf = NULL;
504 struct vdec_v4l2_buffer *fb = NULL;
505
506 vf = peek_video_frame(&inst->vfm);
507 if (!vf) {
508 aml_vcodec_debug(inst, "there is no vframe.");
509 *out = NULL;
510 return;
511 }
512
513 vf = get_video_frame(&inst->vfm);
514 if (!vf) {
515 aml_vcodec_debug(inst, "the vframe is avalid.");
516 *out = NULL;
517 return;
518 }
519
520 atomic_set(&vf->use_cnt, 1);
521
522 fb = (struct vdec_v4l2_buffer *)vf->v4l_mem_handle;
523 fb->vf_handle = (unsigned long)vf;
524 fb->status = FB_ST_DISPLAY;
525
526 *out = fb;
527
528 //pr_info("%s, %d\n", __func__, fb->base_y.bytes_used);
529 //dump_write(fb->base_y.vaddr, fb->base_y.bytes_used);
530 //dump_write(fb->base_c.vaddr, fb->base_c.bytes_used);
531
532 /* convert yuv format. */
533 //swap_uv(fb->base_c.vaddr, fb->base_c.size);
534}
535
536static int vdec_write_nalu(struct vdec_hevc_inst *inst,
537 u8 *buf, u32 size, u64 ts)
538{
539 int ret = 0;
540 struct aml_vdec_adapt *vdec = &inst->vdec;
541
542 ret = vdec_vframe_write(vdec, buf, size, ts);
543
544 return ret;
545}
546
547static bool monitor_res_change(struct vdec_hevc_inst *inst, u8 *buf, u32 size)
548{
549 int ret = 0, i = 0, j = 0;
550 u8 *p = buf;
551 int len = size;
552 u32 type;
553
554 for (i = 4; i < size; i++) {
555 j = find_start_code(p, len);
556 if (j > 0) {
557 len = size - (p - buf);
558 type = HEVC_NAL_TYPE(p[j]);
559 if (type != HEVC_NAL_AUD &&
560 (type > HEVC_NAL_PPS || type < HEVC_NAL_VPS))
561 break;
562
563 if (type == HEVC_NAL_SPS) {
564 ret = stream_parse(inst, p, len);
565 if (!ret && (inst->vsi->cur_pic.coded_width !=
566 inst->vsi->pic.coded_width ||
567 inst->vsi->cur_pic.coded_height !=
568 inst->vsi->pic.coded_height)) {
569 inst->vsi->cur_pic = inst->vsi->pic;
570 return true;
571 }
572 }
573 p += j;
574 }
575 p++;
576 }
577
578 return false;
579}
580
581static int vdec_hevc_decode(unsigned long h_vdec, struct aml_vcodec_mem *bs,
582 u64 timestamp, bool *res_chg)
583{
584 struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec;
585 struct aml_vdec_adapt *vdec = &inst->vdec;
586 struct stream_info *st;
587 u8 *buf;
588 u32 size;
589 int ret = -1;
590
591 /* bs NULL means flush decoder */
592 if (bs == NULL)
593 return -1;
594
595 buf = (u8 *)bs->vaddr;
596 size = bs->size;
597 st = (struct stream_info *)buf;
598
599 if (inst->ctx->is_drm_mode && (st->magic == DRMe || st->magic == DRMn))
600 ret = vdec_vbuf_write(vdec, st->m.buf, sizeof(st->m.drm));
601 else if (st->magic == NORe)
602 ret = vdec_vbuf_write(vdec, st->data, st->length);
603 else if (st->magic == NORn)
604 ret = vdec_write_nalu(inst, st->data, st->length, timestamp);
605 else if (inst->ctx->is_stream_mode)
606 ret = vdec_vbuf_write(vdec, buf, size);
607 else {
608 /*checked whether the resolution changes.*/
609 if ((*res_chg = monitor_res_change(inst, buf, size)))
610 return 0;
611
612 ret = vdec_write_nalu(inst, buf, size, timestamp);
613 }
614
615 return ret;
616}
617
618 static void get_param_config_info(struct vdec_hevc_inst *inst,
619 struct aml_dec_params *parms)
620 {
621 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_CFGINFO)
622 parms->cfg = inst->parms.cfg;
623 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_PSINFO)
624 parms->ps = inst->parms.ps;
625 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_HDRINFO)
626 parms->hdr = inst->parms.hdr;
627 if (inst->parms.parms_status & V4L2_CONFIG_PARM_DECODE_CNTINFO)
628 parms->cnt = inst->parms.cnt;
629
630 parms->parms_status |= inst->parms.parms_status;
631
632 aml_vcodec_debug(inst, "parms status: %u", parms->parms_status);
633 }
634
635static int vdec_hevc_get_param(unsigned long h_vdec,
636 enum vdec_get_param_type type, void *out)
637{
638 int ret = 0;
639 struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec;
640
641 if (!inst) {
642 pr_err("the hevc inst of dec is invalid.\n");
643 return -1;
644 }
645
646 switch (type) {
647 case GET_PARAM_DISP_FRAME_BUFFER:
648 vdec_hevc_get_vf(inst, out);
649 break;
650
651 case GET_PARAM_FREE_FRAME_BUFFER:
652 ret = vdec_hevc_get_fb(inst, out);
653 break;
654
655 case GET_PARAM_PIC_INFO:
656 get_pic_info(inst, out);
657 break;
658
659 case GET_PARAM_DPB_SIZE:
660 get_dpb_size(inst, out);
661 break;
662
663 case GET_PARAM_CROP_INFO:
664 get_crop_info(inst, out);
665 break;
666
667 case GET_PARAM_CONFIG_INFO:
668 get_param_config_info(inst, out);
669 break;
670 default:
671 aml_vcodec_err(inst, "invalid get parameter type=%d", type);
672 ret = -EINVAL;
673 }
674
675 return ret;
676}
677
678static void set_param_write_sync(struct vdec_hevc_inst *inst)
679{
680 complete(&inst->comp);
681}
682
683static void set_param_ps_info(struct vdec_hevc_inst *inst,
684 struct aml_vdec_ps_infos *ps)
685{
686 struct vdec_pic_info *pic = &inst->vsi->pic;
687 struct vdec_hevc_dec_info *dec = &inst->vsi->dec;
688 struct v4l2_rect *rect = &inst->vsi->crop;
689
690 /* fill visible area size that be used for EGL. */
691 pic->visible_width = ps->visible_width;
692 pic->visible_height = ps->visible_height;
693
694 /* calc visible ares. */
695 rect->left = 0;
696 rect->top = 0;
697 rect->width = pic->visible_width;
698 rect->height = pic->visible_height;
699
700 /* config canvas size that be used for decoder. */
701 pic->coded_width = ALIGN(ps->coded_width, 64);
702 pic->coded_height = ALIGN(ps->coded_height, 64);
703 pic->y_len_sz = pic->coded_width * pic->coded_height;
704 pic->c_len_sz = pic->y_len_sz >> 1;
705
706 dec->dpb_sz = ps->dpb_size;
707
708 inst->parms.ps = *ps;
709 inst->parms.parms_status |=
710 V4L2_CONFIG_PARM_DECODE_PSINFO;
711
712 /*wake up*/
713 complete(&inst->comp);
714
715 pr_info("Parse from ucode, crop(%d x %d), coded(%d x %d) dpb: %d\n",
716 pic->visible_width, pic->visible_height,
717 pic->coded_width, pic->coded_height,
718 dec->dpb_sz);
719}
720
721static void set_param_hdr_info(struct vdec_hevc_inst *inst,
722 struct aml_vdec_hdr_infos *hdr)
723{
724 if (!(inst->parms.parms_status &
725 V4L2_CONFIG_PARM_DECODE_HDRINFO)) {
726 inst->parms.hdr = *hdr;
727 inst->parms.parms_status |=
728 V4L2_CONFIG_PARM_DECODE_HDRINFO;
729 aml_vdec_dispatch_event(inst->ctx,
730 V4L2_EVENT_SRC_CH_HDRINFO);
731 pr_info("H265 set HDR infos\n");
732 }
733}
734
735static void set_param_post_event(struct vdec_hevc_inst *inst, u32 *event)
736{
737 aml_vdec_dispatch_event(inst->ctx, *event);
738 pr_info("H265 post event: %d\n", *event);
739}
740
741static int vdec_hevc_set_param(unsigned long h_vdec,
742 enum vdec_set_param_type type, void *in)
743{
744 int ret = 0;
745 struct vdec_hevc_inst *inst = (struct vdec_hevc_inst *)h_vdec;
746
747 if (!inst) {
748 pr_err("the hevc inst of dec is invalid.\n");
749 return -1;
750 }
751
752 switch (type) {
753 case SET_PARAM_WRITE_FRAME_SYNC:
754 set_param_write_sync(inst);
755 break;
756
757 case SET_PARAM_PS_INFO:
758 set_param_ps_info(inst, in);
759 break;
760
761 case SET_PARAM_HDR_INFO:
762 set_param_hdr_info(inst, in);
763 break;
764
765 case SET_PARAM_POST_EVENT:
766 set_param_post_event(inst, in);
767 break;
768 default:
769 aml_vcodec_err(inst, "invalid set parameter type=%d", type);
770 ret = -EINVAL;
771 }
772
773 return ret;
774}
775
776static struct vdec_common_if vdec_hevc_if = {
777 .init = vdec_hevc_init,
778 .probe = vdec_hevc_probe,
779 .decode = vdec_hevc_decode,
780 .get_param = vdec_hevc_get_param,
781 .set_param = vdec_hevc_set_param,
782 .deinit = vdec_hevc_deinit,
783};
784
785struct vdec_common_if *get_hevc_dec_comm_if(void);
786
787struct vdec_common_if *get_hevc_dec_comm_if(void)
788{
789 return &vdec_hevc_if;
790}
791
generated by cgit at 2024-05-17 10:00:45 (GMT)