path: root/drivers/frame_provider/decoder/avs2/vavs2.c (plain)
blob: f90fee6345c5dd8a3286ea027b40c1cb49d5538d

1	/*
2	* drivers/amlogic/amports/avs2.c
3	*
4	* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful, but WITHOUT
12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	* more details.
15	*
16	*/
17	#include <linux/kernel.h>
18	#include <linux/module.h>
19	#include <linux/types.h>
20	#include <linux/errno.h>
21	#include <linux/interrupt.h>
22	#include <linux/semaphore.h>
23	#include <linux/delay.h>
24	#include <linux/timer.h>
25	#include <linux/kfifo.h>
26	#include <linux/kthread.h>
27	#include <linux/spinlock.h>
28	#include <linux/platform_device.h>
29	#include <linux/amlogic/media/vfm/vframe.h>
30	#include <linux/amlogic/media/utils/amstream.h>
31	#include <linux/amlogic/media/utils/vformat.h>
32	#include <linux/amlogic/media/frame_sync/ptsserv.h>
33	#include <linux/amlogic/media/frame_sync/tsync.h>
34	#include <linux/amlogic/media/canvas/canvas.h>
35	#include <linux/amlogic/media/vfm/vframe_provider.h>
36	#include <linux/amlogic/media/vfm/vframe_receiver.h>
37	#include <linux/dma-mapping.h>
38	#include <linux/dma-contiguous.h>
39	#include <linux/slab.h>
40	#include <linux/amlogic/tee.h>
41	#include "../../../stream_input/amports/amports_priv.h"
42	#include <linux/amlogic/media/codec_mm/codec_mm.h>
43	#include "../utils/decoder_mmu_box.h"
44	#include "../utils/decoder_bmmu_box.h"
45	#include "avs2_global.h"
46
47	#define MEM_NAME "codec_avs2"
48	/* #include <mach/am_regs.h> */
49	#include <linux/amlogic/media/utils/vdec_reg.h>
50	#include "../utils/vdec.h"
51	#include "../utils/amvdec.h"
52
53	#include <linux/amlogic/media/video_sink/video.h>
54	#include <linux/amlogic/media/codec_mm/configs.h>
55	#include "../utils/config_parser.h"
56	#include "../utils/firmware.h"
57	#include "../../../common/chips/decoder_cpu_ver_info.h"
58	#include <linux/amlogic/tee.h>
59
60
61	#define I_ONLY_SUPPORT
62	#define MIX_STREAM_SUPPORT
63	#define G12A_BRINGUP_DEBUG
64	#define CONSTRAIN_MAX_BUF_NUM
65
66	#include "vavs2.h"
67	#define HEVC_SHIFT_LENGTH_PROTECT 0x313a
68	#define HEVC_MPRED_CTRL9 0x325b
69	#define HEVC_DBLK_CFGD 0x350d
70
71
72	#define HEVC_CM_HEADER_START_ADDR 0x3628
73	#define HEVC_DBLK_CFGB 0x350b
74	#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
75	#define HEVC_SAO_MMU_VH1_ADDR 0x363b
76	#define HEVC_SAO_MMU_VH0_ADDR 0x363a
77
78
79	/*
80	* AVS2_DEC_STATUS define
81	*/
82	/*internal*/
83	#define AVS2_DEC_IDLE 0
84	#define AVS2_SEQUENCE 1
85	#define AVS2_I_PICTURE 2
86	#define AVS2_PB_PICTURE 3
87	#define AVS2_DISCARD_STARTCODE 4
88	#define AVS2_DISCARD_NAL 4
89
90	#define AVS2_SLICE_DECODING 6
91
92	#define SWAP_IN_CMD 0x10
93	#define SWAP_OUT_CMD 0x11
94	#define SWAP_OUTIN_CMD 0x12
95	#define SWAP_DONE 0x13
96	#define SWAP_POST_INIT 0x14
97
98	/*head*/
99	#define AVS2_HEAD_SEQ_READY 0x21
100	#define AVS2_HEAD_PIC_I_READY 0x22
101	#define AVS2_HEAD_PIC_PB_READY 0x23
102	#define AVS2_HEAD_SEQ_END_READY 0x24
103	#define AVS2_STARTCODE_SEARCH_DONE 0x25
104
105	/*pic done*/
106	#define HEVC_DECPIC_DATA_DONE 0x30
107	#define HEVC_DECPIC_DATA_ERROR 0x31
108	#define HEVC_NAL_DECODE_DONE 0x32
109	#define AVS2_DECODE_BUFEMPTY 0x33
110	#define AVS2_DECODE_TIMEOUT 0x34
111	#define AVS2_DECODE_OVER_SIZE 0x35
112	#define AVS2_EOS 0x36
113
114	/*cmd*/
115	#define AVS2_10B_DISCARD_NAL 0xf0
116	#define AVS2_SEARCH_NEW_PIC 0xf1
117	#define AVS2_ACTION_ERROR 0xfe
118	#define HEVC_ACTION_ERROR 0xfe
119	#define AVS2_ACTION_DONE 0xff
120	/*AVS2_DEC_STATUS end*/
121
122
123	#define VF_POOL_SIZE 32
124
125	#undef pr_info
126	#define pr_info printk
127
128	#define DECODE_MODE_SINGLE (0 | (0x80 << 24))
129	#define DECODE_MODE_MULTI_STREAMBASE (1 | (0x80 << 24))
130	#define DECODE_MODE_MULTI_FRAMEBASE (2 | (0x80 << 24))
131
132
133	#define VP9_TRIGGER_FRAME_DONE 0x100
134	#define VP9_TRIGGER_FRAME_ENABLE 0x200
135
136	/*#define MV_MEM_UNIT 0x240*/
137	#define MV_MEM_UNIT 0x200
138	/*---------------------------------------------------
139	Include "parser_cmd.h"
140	---------------------------------------------------*/
141	#define PARSER_CMD_SKIP_CFG_0 0x0000090b
142
143	#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
144
145	#define PARSER_CMD_SKIP_CFG_2 0x001b1910
146
147
148	#define PARSER_CMD_NUMBER 37
149
150	static unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
151	0x0401,
152	0x8401,
153	0x0800,
154	0x0402,
155	0x9002,
156	0x1423,
157	0x8CC3,
158	0x1423,
159	0x8804,
160	0x9825,
161	0x0800,
162	0x04FE,
163	0x8406,
164	0x8411,
165	0x1800,
166	0x8408,
167	0x8409,
168	0x8C2A,
169	0x9C2B,
170	0x1C00,
171	0x840F,
172	0x8407,
173	0x8000,
174	0x8408,
175	0x2000,
176	0xA800,
177	0x8410,
178	0x04DE,
179	0x840C,
180	0x840D,
181	0xAC00,
182	0xA000,
183	0x08C0,
184	0x08E0,
185	0xA40E,
186	0xFC00,
187	0x7C00
188	};
189
190	static int32_t g_WqMDefault4x4[16] = {
191	64, 64, 64, 68,
192	64, 64, 68, 72,
193	64, 68, 76, 80,
194	72, 76, 84, 96
195	};
196
197
198	static int32_t g_WqMDefault8x8[64] = {
199	64, 64, 64, 64, 68, 68, 72, 76,
200	64, 64, 64, 68, 72, 76, 84, 92,
201	64, 64, 68, 72, 76, 80, 88, 100,
202	64, 68, 72, 80, 84, 92, 100, 112,
203	68, 72, 80, 84, 92, 104, 112, 128,
204	76, 80, 84, 92, 104, 116, 132, 152,
205	96, 100, 104, 116, 124, 140, 164, 188,
206	104, 108, 116, 128, 152, 172, 192, 216
207	};
208	/*#define HEVC_PIC_STRUCT_SUPPORT*/
209	/* to remove, fix build error */
210
211	/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
212
213	#define MULTI_INSTANCE_SUPPORT
214	/* #define ERROR_HANDLE_DEBUG */
215
216	#ifndef STAT_KTHREAD
217	#define STAT_KTHREAD 0x40
218	#endif
219
220	#ifdef MULTI_INSTANCE_SUPPORT
221	#define MAX_DECODE_INSTANCE_NUM 12
222	#define MULTI_DRIVER_NAME "ammvdec_avs2"
223
224	#define lock_buffer(dec, flags) \
225	spin_lock_irqsave(&dec->buffer_lock, flags)
226
227	#define unlock_buffer(dec, flags) \
228	spin_unlock_irqrestore(&dec->buffer_lock, flags)
229
230	static unsigned int max_decode_instance_num
231	= MAX_DECODE_INSTANCE_NUM;
232	static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
233	static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
234	static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
235	static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
236	static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
237	static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
238
239	#ifdef G12A_BRINGUP_DEBUG
240	static u32 decode_timeout_val = 200;
241	#else
242	static u32 decode_timeout_val = 200;
243	#endif
244	static int start_decode_buf_level = 0x8000;
245	#ifdef AVS2_10B_MMU
246	static u32 work_buf_size; /* = 24 * 1024 * 1024*/;
247	#else
248	static u32 work_buf_size = 32 * 1024 * 1024;
249	#endif
250
251	static u32 mv_buf_margin;
252	static int pre_decode_buf_level = 0x1000;
253	static u32 again_threshold;
254
255
256	/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
257	/* double_write_mode:
258	* 0, no double write;
259	* 1, 1:1 ratio;
260	* 2, (1/4):(1/4) ratio;
261	* 3, (1/4):(1/4) ratio, with both compressed frame included
262	* 4, (1/2):(1/2) ratio;
263	* 0x10, double write only
264	* 0x100, if > 1080p,use mode 4,else use mode 1;
265	* 0x200, if > 1080p,use mode 2,else use mode 1;
266	* 0x300, if > 720p, use mode 4, else use mode 1;
267	*/
268	static u32 double_write_mode;
269	static u32 without_display_mode;
270
271	#define DRIVER_NAME "amvdec_avs2"
272	#define MODULE_NAME "amvdec_avs2"
273	#define DRIVER_HEADER_NAME "amvdec_avs2_header"
274
275
276	#define PUT_INTERVAL (HZ/100)
277	#define ERROR_SYSTEM_RESET_COUNT 200
278
279	#define PTS_NORMAL 0
280	#define PTS_NONE_REF_USE_DURATION 1
281
282	#define PTS_MODE_SWITCHING_THRESHOLD 3
283	#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
284
285	#define DUR2PTS(x) ((x)*90/96)
286
287	struct AVS2Decoder_s;
288	static int vavs2_vf_states(struct vframe_states *states, void *);
289	static struct vframe_s *vavs2_vf_peek(void *);
290	static struct vframe_s *vavs2_vf_get(void *);
291	static void vavs2_vf_put(struct vframe_s *, void *);
292	static int vavs2_event_cb(int type, void *data, void *private_data);
293	static void set_vframe(struct AVS2Decoder_s *dec,
294	struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy);
295
296	static int vavs2_stop(struct AVS2Decoder_s *dec);
297	static s32 vavs2_init(struct vdec_s *vdec);
298	static void vavs2_prot_init(struct AVS2Decoder_s *dec);
299	static int vavs2_local_init(struct AVS2Decoder_s *dec);
300	static void vavs2_put_timer_func(unsigned long arg);
301	static void dump_data(struct AVS2Decoder_s *dec, int size);
302	static unsigned char get_data_check_sum
303	(struct AVS2Decoder_s *dec, int size);
304	static void dump_pic_list(struct AVS2Decoder_s *dec);
305
306	static const char vavs2_dec_id[] = "vavs2-dev";
307
308	#define PROVIDER_NAME "decoder.avs2"
309	#define MULTI_INSTANCE_PROVIDER_NAME "vdec.avs2"
310
311	static const struct vframe_operations_s vavs2_vf_provider = {
312	.peek = vavs2_vf_peek,
313	.get = vavs2_vf_get,
314	.put = vavs2_vf_put,
315	.event_cb = vavs2_event_cb,
316	.vf_states = vavs2_vf_states,
317	};
318
319	static struct vframe_provider_s vavs2_vf_prov;
320
321	static u32 bit_depth_luma;
322	static u32 bit_depth_chroma;
323	static u32 frame_width;
324	static u32 frame_height;
325	static u32 video_signal_type;
326	static u32 pts_unstable;
327	static u32 on_no_keyframe_skiped;
328
329	static u32 force_video_signal_type;
330	static u32 enable_force_video_signal_type;
331	#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
332
333	static const char * const video_format_names[] = {
334	"component", "PAL", "NTSC", "SECAM",
335	"MAC", "unspecified", "Reserved", "Reserved"
336	};
337
338	static inline int div_r32(int64_t m, int n)
339	{
340	/*
341	return (int)(m/n)
342	*/
343	#ifndef CONFIG_ARM64
344	int64_t qu = 0;
345	qu = div_s64(m, n);
346	return (int)qu;
347	#else
348	return (int)(m/n);
349	#endif
350	}
351
352	enum vpx_bit_depth_t {
353	AVS2_BITS_8 = 8, /**< 8 bits */
354	AVS2_BITS_10 = 10, /**< 10 bits */
355	AVS2_BITS_12 = 12, /**< 12 bits */
356	};
357
358	/*USE_BUF_BLOCK*/
359	struct BUF_s {
360	int index;
361	unsigned int alloc_flag;
362	/*buffer */
363	unsigned int cma_page_count;
364	unsigned long alloc_addr;
365	unsigned long start_adr;
366	unsigned int size;
367
368	unsigned int free_start_adr;
369	} /*BUF_t */;
370
371	struct MVBUF_s {
372	unsigned long start_adr;
373	unsigned int size;
374	int used_flag;
375	} /*MVBUF_t */;
376
377	/* #undef BUFMGR_ONLY to enable hardware configuration */
378
379	/*#define TEST_WR_PTR_INC*/
380	#define WR_PTR_INC_NUM 128
381
382	#define SIMULATION
383	#define DOS_PROJECT
384	#undef MEMORY_MAP_IN_REAL_CHIP
385
386	/*#undef DOS_PROJECT*/
387	/*#define MEMORY_MAP_IN_REAL_CHIP*/
388
389	/*#define BUFFER_MGR_ONLY*/
390	/*#define CONFIG_HEVC_CLK_FORCED_ON*/
391	/*#define ENABLE_SWAP_TEST*/
392
393	#ifdef AVS2_10B_NV21
394	#define MEM_MAP_MODE 2 /* 0:linear 1:32x32 2:64x32*/
395	#else
396	#define MEM_MAP_MODE 0 /* 0:linear 1:32x32 2:64x32*/
397	#endif
398
399	#ifdef AVS2_10B_NV21
400	#else
401	#define LOSLESS_COMPRESS_MODE
402	#endif
403
404	#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
405	#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
406
407
408
409	typedef unsigned int u32;
410	typedef unsigned short u16;
411
412	#define AVS2_DBG_BUFMGR 0x01
413	#define AVS2_DBG_BUFMGR_MORE 0x02
414	#define AVS2_DBG_BUFMGR_DETAIL 0x04
415	#define AVS2_DBG_IRQ_EVENT 0x08
416	#define AVS2_DBG_OUT_PTS 0x10
417	#define AVS2_DBG_PRINT_SOURCE_LINE 0x20
418	#define AVS2_DBG_PRINT_PARAM 0x40
419	#define AVS2_DBG_PRINT_PIC_LIST 0x80
420	#define AVS2_DBG_SEND_PARAM_WITH_REG 0x100
421	#define AVS2_DBG_MERGE 0x200
422	#define AVS2_DBG_DBG_LF_PRINT 0x400
423	#define AVS2_DBG_REG 0x800
424	#define AVS2_DBG_PIC_LEAK 0x1000
425	#define AVS2_DBG_PIC_LEAK_WAIT 0x2000
426	#define AVS2_DBG_HDR_INFO 0x4000
427	#define AVS2_DBG_DIS_LOC_ERROR_PROC 0x10000
428	#define AVS2_DBG_DIS_SYS_ERROR_PROC 0x20000
429	#define AVS2_DBG_DUMP_PIC_LIST 0x40000
430	#define AVS2_DBG_TRIG_SLICE_SEGMENT_PROC 0x80000
431	#define AVS2_DBG_FORCE_UNCOMPRESS 0x100000
432	#define AVS2_DBG_LOAD_UCODE_FROM_FILE 0x200000
433	#define AVS2_DBG_FORCE_SEND_AGAIN 0x400000
434	#define AVS2_DBG_DUMP_DATA 0x800000
435	#define AVS2_DBG_DUMP_LMEM_BUF 0x1000000
436	#define AVS2_DBG_DUMP_RPM_BUF 0x2000000
437	#define AVS2_DBG_CACHE 0x4000000
438	#define IGNORE_PARAM_FROM_CONFIG 0x8000000
439	/*MULTI_INSTANCE_SUPPORT*/
440	#define PRINT_FLAG_ERROR 0
441	#define PRINT_FLAG_VDEC_STATUS 0x20000000
442	#define PRINT_FLAG_VDEC_DETAIL 0x40000000
443	#define PRINT_FLAG_VDEC_DATA 0x80000000
444
445	#define PRINT_LINE() \
446	do { \
447	if (debug & AVS2_DBG_PRINT_SOURCE_LINE)\
448	pr_info("%s line %d\n", __func__, __LINE__);\
449	} while (0)
450
451	static u32 debug;
452
453	static u32 debug_again;
454
455	bool is_avs2_print_param(void)
456	{
457	bool ret = false;
458	if (debug & AVS2_DBG_PRINT_PARAM)
459	ret = true;
460	return ret;
461	}
462
463	bool is_avs2_print_bufmgr_detail(void)
464	{
465	bool ret = false;
466	if (debug & AVS2_DBG_BUFMGR_DETAIL)
467	ret = true;
468	return ret;
469	}
470	static bool is_reset;
471	/*for debug*/
472	/*
473	udebug_flag:
474	bit 0, enable ucode print
475	bit 1, enable ucode detail print
476	bit [31:16] not 0, pos to dump lmem
477	bit 2, pop bits to lmem
478	bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
479	*/
480	static u32 udebug_flag;
481	/*
482	when udebug_flag[1:0] is not 0
483	udebug_pause_pos not 0,
484	pause position
485	*/
486	static u32 udebug_pause_pos;
487	/*
488	when udebug_flag[1:0] is not 0
489	and udebug_pause_pos is not 0,
490	pause only when DEBUG_REG2 is equal to this val
491	*/
492	static u32 udebug_pause_val;
493
494	static u32 udebug_pause_decode_idx;
495
496	static u32 force_disp_pic_index;
497
498	#define DEBUG_REG
499	#ifdef DEBUG_REG
500	static void WRITE_VREG_DBG2(unsigned adr, unsigned val)
501	{
502	if (debug & AVS2_DBG_REG)
503	pr_info("%s(%x, %x)\n", __func__, adr, val);
504	if (adr != 0)
505	WRITE_VREG(adr, val);
506	}
507
508	#undef WRITE_VREG
509	#define WRITE_VREG WRITE_VREG_DBG2
510	#endif
511
512
513	#ifdef AVS2_10B_MMU
514	#define MMU_COMPRESS_HEADER_SIZE 0x48000
515	#define MMU_COMPRESS_8K_HEADER_SIZE 0x48000*4
516	#endif
517
518	#define INVALID_IDX -1 /* Invalid buffer index.*/
519
520
521	#define FRAME_BUFFERS (AVS2_MAX_BUFFER_NUM)
522	#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
523	#define MAX_BUF_NUM (FRAME_BUFFERS)
524
525	#define FRAME_CONTEXTS_LOG2 2
526	#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
527	/*buffer + header buffer + workspace*/
528	#ifdef MV_USE_FIXED_BUF
529	#define MAX_BMMU_BUFFER_NUM ((FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)+1)
530	#define VF_BUFFER_IDX(n) (n)
531	#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n+1)
532	#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS+1)
533	#else
534	#define MAX_BMMU_BUFFER_NUM (((FRAME_BUFFERS*2)+HEADER_FRAME_BUFFERS+1)+1)
535	#define VF_BUFFER_IDX(n) (n)
536	#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n+1)
537	#define MV_BUFFER_IDX(n) ((FRAME_BUFFERS * 2) + n+1)
538	#define WORK_SPACE_BUF_ID ((FRAME_BUFFERS * 2) + HEADER_FRAME_BUFFERS+1)
539	#endif
540	/*
541	static void set_canvas(struct AVS2Decoder_s *dec,
542	struct avs2_frame_s *pic);
543	int avs2_prepare_display_buf(struct AVS2Decoder_s *dec,
544	int pos);
545	*/
546
547
548	struct buff_s {
549	u32 buf_start;
550	u32 buf_size;
551	u32 buf_end;
552	};
553
554	struct BuffInfo_s {
555	u32 max_width;
556	u32 max_height;
557	u32 start_adr;
558	u32 end_adr;
559	struct buff_s ipp;
560	struct buff_s sao_abv;
561	struct buff_s sao_vb;
562	struct buff_s short_term_rps;
563	struct buff_s rcs;
564	struct buff_s sps;
565	struct buff_s pps;
566	struct buff_s sao_up;
567	struct buff_s swap_buf;
568	struct buff_s swap_buf2;
569	struct buff_s scalelut;
570	struct buff_s dblk_para;
571	struct buff_s dblk_data;
572	struct buff_s dblk_data2;
573	#ifdef AVS2_10B_MMU
574	struct buff_s mmu_vbh;
575	struct buff_s cm_header;
576	#endif
577	struct buff_s mpred_above;
578	#ifdef MV_USE_FIXED_BUF
579	struct buff_s mpred_mv;
580	#endif
581	struct buff_s rpm;
582	struct buff_s lmem;
583	};
584
585	#define DEC_RESULT_NONE 0
586	#define DEC_RESULT_DONE 1
587	#define DEC_RESULT_AGAIN 2
588	#define DEC_RESULT_CONFIG_PARAM 3
589	#define DEC_RESULT_ERROR 4
590	#define DEC_INIT_PICLIST 5
591	#define DEC_UNINIT_PICLIST 6
592	#define DEC_RESULT_GET_DATA 7
593	#define DEC_RESULT_GET_DATA_RETRY 8
594	#define DEC_RESULT_EOS 9
595	#define DEC_RESULT_FORCE_EXIT 10
596
597	static void avs2_work(struct work_struct *work);
598	struct loop_filter_info_n;
599	struct loopfilter;
600	struct segmentation;
601
602	struct AVS2Decoder_s {
603	int pic_list_init_flag;
604	unsigned char index;
605	spinlock_t buffer_lock;
606	struct device *cma_dev;
607	struct platform_device *platform_dev;
608	void (*vdec_cb)(struct vdec_s *, void *);
609	void *vdec_cb_arg;
610	struct vframe_chunk_s *chunk;
611	int dec_result;
612	struct work_struct work;
613	u32 start_shift_bytes;
614
615	struct BuffInfo_s work_space_buf_store;
616	unsigned long buf_start;
617	u32 buf_size;
618	u32 cma_alloc_count;
619	unsigned long cma_alloc_addr;
620	uint8_t eos;
621	unsigned long int start_process_time;
622	unsigned last_lcu_idx;
623	int decode_timeout_count;
624	unsigned timeout_num;
625
626	int double_write_mode;
627
628	unsigned char m_ins_flag;
629	char *provider_name;
630	int frame_count;
631	u32 stat;
632	struct timer_list timer;
633	u32 frame_dur;
634	u32 frame_ar;
635	int fatal_error;
636	uint8_t init_flag;
637	uint8_t first_sc_checked;
638	uint8_t process_busy;
639	#define PROC_STATE_INIT 0
640	#define PROC_STATE_HEAD_DONE 1
641	#define PROC_STATE_DECODING 2
642	#define PROC_STATE_HEAD_AGAIN 3
643	#define PROC_STATE_DECODE_AGAIN 4
644	#define PROC_STATE_TEST1 5
645	uint8_t process_state;
646	u32 ucode_pause_pos;
647
648	int show_frame_num;
649	#ifndef AVS2_10B_MMU
650	struct buff_s mc_buf_spec;
651	#endif
652	struct dec_sysinfo vavs2_amstream_dec_info;
653	void *rpm_addr;
654	void *lmem_addr;
655	dma_addr_t rpm_phy_addr;
656	dma_addr_t lmem_phy_addr;
657	unsigned short *lmem_ptr;
658	unsigned short *debug_ptr;
659
660	#if 1
661	/*AVS2_10B_MMU*/
662	void *frame_mmu_map_addr;
663	dma_addr_t frame_mmu_map_phy_addr;
664	#endif
665	unsigned int use_cma_flag;
666
667	struct BUF_s m_BUF[MAX_BUF_NUM];
668	struct MVBUF_s m_mv_BUF[MAX_BUF_NUM];
669	u32 used_buf_num;
670	DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
671	DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
672	DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
673	struct vframe_s vfpool[VF_POOL_SIZE];
674	u32 vf_pre_count;
675	u32 vf_get_count;
676	u32 vf_put_count;
677	int buf_num;
678	unsigned int losless_comp_body_size;
679
680	u32 video_signal_type;
681	u32 video_ori_signal_type;
682
683	int pts_mode;
684	int last_lookup_pts;
685	int last_pts;
686	u64 last_lookup_pts_us64;
687	u64 last_pts_us64;
688	u64 shift_byte_count;
689	u32 shift_byte_count_lo;
690	u32 shift_byte_count_hi;
691	int pts_mode_switching_count;
692	int pts_mode_recovery_count;
693
694	bool get_frame_dur;
695	u32 saved_resolution;
696
697	/**/
698	int refresh_frame_flags;
699	uint8_t hold_ref_buf;
700	struct BuffInfo_s *work_space_buf;
701	#ifndef AVS2_10B_MMU
702	struct buff_s *mc_buf;
703	#endif
704	unsigned int frame_width;
705	unsigned int frame_height;
706
707	unsigned short *rpm_ptr;
708	int init_pic_w;
709	int init_pic_h;
710
711	int slice_type;
712
713	int decode_idx;
714	int slice_idx;
715	uint8_t wait_buf;
716	uint8_t error_flag;
717	unsigned int bufmgr_error_count;
718
719	/* bit 0, for decoding; bit 1, for displaying */
720	uint8_t ignore_bufmgr_error;
721	uint8_t skip_PB_before_I;
722	int PB_skip_mode;
723	int PB_skip_count_after_decoding;
724	/*hw*/
725
726	/**/
727	struct vdec_info *gvs;
728
729
730	unsigned int dec_status;
731	u32 last_put_idx;
732	int new_frame_displayed;
733	void *mmu_box;
734	void *bmmu_box;
735	struct vframe_master_display_colour_s vf_dp;
736	struct firmware_s *fw;
737	#ifdef AVS2_10B_MMU
738	int cur_fb_idx_mmu;
739	long used_4k_num;
740	#endif
741	struct avs2_decoder avs2_dec;
742	#define ALF_NUM_BIT_SHIFT 6
743	#define NO_VAR_BINS 16
744	int32_t m_filterCoeffSym[16][9];
745	int32_t m_varIndTab[NO_VAR_BINS];
746
747	struct vframe_s vframe_dummy;
748	/* start_decoding_flag,
749	bit 0, SEQ ready
750	bit 1, I ready
751	*/
752	unsigned char start_decoding_flag;
753	uint32_t mpred_abv_start_addr;
754	uint32_t mpred_abv_start_addr_bak;
755	u8 next_again_flag;
756	u32 pre_parser_wr_ptr;
757	int need_cache_size;
758	u64 sc_start_time;
759	#ifdef I_ONLY_SUPPORT
760	u32 i_only;
761	#endif
762	int frameinfo_enable;
763	struct vframe_qos_s vframe_qos;
764	u32 dynamic_buf_margin;
765	};
766
767	static int compute_losless_comp_body_size(
768	struct AVS2Decoder_s *dec, int width, int height,
769	uint8_t is_bit_depth_10);
770
771	static int avs2_print(struct AVS2Decoder_s *dec,
772	int flag, const char *fmt, ...)
773	{
774	#define HEVC_PRINT_BUF 256
775	unsigned char buf[HEVC_PRINT_BUF];
776	int len = 0;
777	if (dec == NULL ||
778	(flag == 0) ||
779	(debug & flag)) {
780	va_list args;
781	va_start(args, fmt);
782	if (dec)
783	len = sprintf(buf, "[%d]", dec->index);
784	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
785	pr_info("%s", buf);
786	va_end(args);
787	}
788	return 0;
789	}
790
791	static int avs2_print_cont(struct AVS2Decoder_s *dec,
792	int flag, const char *fmt, ...)
793	{
794	unsigned char buf[HEVC_PRINT_BUF];
795	int len = 0;
796	if (dec == NULL ||
797	(flag == 0) ||
798	(debug & flag)) {
799	va_list args;
800	va_start(args, fmt);
801	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
802	pr_info("%s", buf);
803	va_end(args);
804	}
805	return 0;
806	}
807
808	#define PROB_SIZE (496 * 2 * 4)
809	#define PROB_BUF_SIZE (0x5000)
810	#define COUNT_BUF_SIZE (0x300 * 4 * 4)
811	/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
812	#define MAX_FRAME_4K_NUM 0x1200
813	#define MAX_FRAME_8K_NUM 0x4800
814	#define MAX_SIZE_4K (4096 * 2304)
815	#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
816
817	static int get_frame_mmu_map_size(struct AVS2Decoder_s *dec)
818	{
819	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
820	(IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
821	return (MAX_FRAME_8K_NUM * 4);
822	return (MAX_FRAME_4K_NUM * 4);
823	}
824
825	static int get_compress_header_size(struct AVS2Decoder_s *dec)
826	{
827	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
828	(IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
829	return MMU_COMPRESS_8K_HEADER_SIZE;
830	return MMU_COMPRESS_HEADER_SIZE;
831	}
832
833	static void reset_process_time(struct AVS2Decoder_s *dec)
834	{
835	if (dec->start_process_time) {
836	unsigned process_time =
837	1000 * (jiffies - dec->start_process_time) / HZ;
838	dec->start_process_time = 0;
839	if (process_time > max_process_time[dec->index])
840	max_process_time[dec->index] = process_time;
841	}
842	}
843
844	static void start_process_time(struct AVS2Decoder_s *dec)
845	{
846	dec->start_process_time = jiffies;
847	dec->decode_timeout_count = 0;
848	dec->last_lcu_idx = 0;
849	}
850
851	static void update_decoded_pic(struct AVS2Decoder_s *dec);
852
853	static void timeout_process(struct AVS2Decoder_s *dec)
854	{
855	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
856	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
857	dec->timeout_num++;
858	amhevc_stop();
859	avs2_print(dec,
860	0, "%s decoder timeout\n", __func__);
861	if (cur_pic)
862	cur_pic->error_mark = 1;
863	dec->dec_result = DEC_RESULT_DONE;
864	update_decoded_pic(dec);
865	reset_process_time(dec);
866	vdec_schedule_work(&dec->work);
867	}
868
869	static u32 get_valid_double_write_mode(struct AVS2Decoder_s *dec)
870	{
871	return (dec->m_ins_flag &&
872	((double_write_mode & 0x80000000) == 0)) ?
873	dec->double_write_mode :
874	(double_write_mode & 0x7fffffff);
875	}
876
877	static int get_double_write_mode(struct AVS2Decoder_s *dec)
878	{
879	u32 valid_dw_mode = get_valid_double_write_mode(dec);
880	int w = dec->avs2_dec.img.width;
881	int h = dec->avs2_dec.img.height;
882	u32 dw = 0x1; /*1:1*/
883	switch (valid_dw_mode) {
884	case 0x100:
885	if (w > 1920 && h > 1088)
886	dw = 0x4; /*1:2*/
887	break;
888	case 0x200:
889	if (w > 1920 && h > 1088)
890	dw = 0x2; /*1:4*/
891	break;
892	case 0x300:
893	if (w > 1280 && h > 720)
894	dw = 0x4; /*1:2*/
895	break;
896	default:
897	dw = valid_dw_mode;
898	break;
899	}
900	return dw;
901	}
902
903	/* for double write buf alloc */
904	static int get_double_write_mode_init(struct AVS2Decoder_s *dec)
905	{
906	u32 valid_dw_mode = get_valid_double_write_mode(dec);
907	u32 dw;
908	int w = dec->init_pic_w;
909	int h = dec->init_pic_h;
910
911	dw = 0x1; /*1:1*/
912	switch (valid_dw_mode) {
913	case 0x100:
914	if (w > 1920 && h > 1088)
915	dw = 0x4; /*1:2*/
916	break;
917	case 0x200:
918	if (w > 1920 && h > 1088)
919	dw = 0x2; /*1:4*/
920	break;
921	case 0x300:
922	if (w > 1280 && h > 720)
923	dw = 0x4; /*1:2*/
924	break;
925	default:
926	dw = valid_dw_mode;
927	break;
928	}
929	return dw;
930	}
931
932	static int get_double_write_ratio(struct AVS2Decoder_s *dec,
933	int dw_mode)
934	{
935	int ratio = 1;
936	if ((dw_mode == 2) ||
937	(dw_mode == 3))
938	ratio = 4;
939	else if (dw_mode == 4)
940	ratio = 2;
941	return ratio;
942	}
943
944	//#define MAX_4K_NUM 0x1200
945	#ifdef AVS2_10B_MMU
946	int avs2_alloc_mmu(
947	struct AVS2Decoder_s *dec,
948	int cur_buf_idx,
949	int pic_width,
950	int pic_height,
951	unsigned short bit_depth,
952	unsigned int *mmu_index_adr)
953	{
954	int bit_depth_10 = (bit_depth == AVS2_BITS_10);
955	int picture_size;
956	int cur_mmu_4k_number, max_frame_num;
957	#ifdef DYNAMIC_ALLOC_HEAD
958	unsigned long buf_addr;
959	struct avs2_frame_s *pic = dec->avs2_dec.hc.cur_pic;
960	if (pic->header_adr == 0) {
961	if (decoder_bmmu_box_alloc_buf_phy
962	(dec->bmmu_box,
963	HEADER_BUFFER_IDX(cur_buf_idx),
964	MMU_COMPRESS_HEADER_SIZE,
965	DRIVER_HEADER_NAME,
966	&buf_addr) < 0){
967	avs2_print(dec, 0,
968	"%s malloc compress header failed %d\n",
969	DRIVER_HEADER_NAME, cur_buf_idx);
970	dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
971	return -1;
972	} else
973	pic->header_adr = buf_addr;
974	}
975	#endif
976
977	picture_size = compute_losless_comp_body_size(
978	dec, pic_width, pic_height,
979	bit_depth_10);
980	cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
981	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
982	max_frame_num = MAX_FRAME_8K_NUM;
983	else
984	max_frame_num = MAX_FRAME_4K_NUM;
985	if (cur_mmu_4k_number > max_frame_num) {
986	pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
987	cur_mmu_4k_number, pic_width, pic_height);
988	return -1;
989	}
990	return decoder_mmu_box_alloc_idx(
991	dec->mmu_box,
992	cur_buf_idx,
993	cur_mmu_4k_number,
994	mmu_index_adr);
995	}
996	#endif
997
998	#if 0
999	/*ndef MV_USE_FIXED_BUF*/
1000	static void dealloc_mv_bufs(struct AVS2Decoder_s *dec)
1001	{
1002	int i;
1003	for (i = 0; i < FRAME_BUFFERS; i++) {
1004	if (dec->m_mv_BUF[i].start_adr) {
1005	if (debug)
1006	pr_info(
1007	"dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1008	i, dec->m_mv_BUF[i].start_adr,
1009	dec->m_mv_BUF[i].size,
1010	dec->m_mv_BUF[i].used_flag);
1011	decoder_bmmu_box_free_idx(
1012	dec->bmmu_box,
1013	MV_BUFFER_IDX(i));
1014	dec->m_mv_BUF[i].start_adr = 0;
1015	dec->m_mv_BUF[i].size = 0;
1016	dec->m_mv_BUF[i].used_flag = 0;
1017	}
1018	}
1019	}
1020
1021	static int alloc_mv_buf(struct AVS2Decoder_s *dec,
1022	int i, int size)
1023	{
1024	int ret = 0;
1025	if (decoder_bmmu_box_alloc_buf_phy
1026	(dec->bmmu_box,
1027	MV_BUFFER_IDX(i), size,
1028	DRIVER_NAME,
1029	&dec->m_mv_BUF[i].start_adr) < 0) {
1030	dec->m_mv_BUF[i].start_adr = 0;
1031	ret = -1;
1032	} else {
1033	dec->m_mv_BUF[i].size = size;
1034	dec->m_mv_BUF[i].used_flag = 0;
1035	ret = 0;
1036	if (debug) {
1037	pr_info(
1038	"MV Buffer %d: start_adr %p size %x\n",
1039	i,
1040	(void *)dec->m_mv_BUF[i].start_adr,
1041	dec->m_mv_BUF[i].size);
1042	}
1043	}
1044	return ret;
1045	}
1046
1047	static int init_mv_buf_list(struct AVS2Decoder_s *dec)
1048	{
1049	int i;
1050	int ret = 0;
1051	int count = FRAME_BUFFERS;
1052	int pic_width = dec->init_pic_w;
1053	int pic_height = dec->init_pic_h;
1054	int lcu_size = 64; /*fixed 64*/
1055	int pic_width_64 = (pic_width + 63) & (~0x3f);
1056	int pic_height_32 = (pic_height + 31) & (~0x1f);
1057	int pic_width_lcu = (pic_width_64 % lcu_size) ?
1058	pic_width_64 / lcu_size + 1
1059	: pic_width_64 / lcu_size;
1060	int pic_height_lcu = (pic_height_32 % lcu_size) ?
1061	pic_height_32 / lcu_size + 1
1062	: pic_height_32 / lcu_size;
1063	int lcu_total = pic_width_lcu * pic_height_lcu;
1064	int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1065	(~0xffff);
1066	if (mv_buf_margin > 0)
1067	count = dec->avs2_dec.ref_maxbuffer + mv_buf_margin;
1068	for (i = 0; i < count; i++) {
1069	if (alloc_mv_buf(dec, i, size) < 0) {
1070	ret = -1;
1071	break;
1072	}
1073	}
1074	return ret;
1075	}
1076	#if 0
1077
1078	static int get_mv_buf(struct AVS2Decoder_s *dec,
1079	struct avs2_frame_s *pic)
1080	{
1081	int i;
1082	int ret = -1;
1083	for (i = 0; i < FRAME_BUFFERS; i++) {
1084	if (dec->m_mv_BUF[i].start_adr &&
1085	dec->m_mv_BUF[i].used_flag == 0) {
1086	dec->m_mv_BUF[i].used_flag = 1;
1087	ret = i;
1088	break;
1089	}
1090	}
1091
1092	if (ret >= 0) {
1093	pic->mv_buf_index = ret;
1094	pic->mpred_mv_wr_start_addr =
1095	(dec->m_mv_BUF[ret].start_adr + 0xffff) &
1096	(~0xffff);
1097	if (debug & AVS2_DBG_BUFMGR_MORE)
1098	pr_info(
1099	"%s => %d (%d) size 0x%x\n",
1100	__func__, ret,
1101	pic->mpred_mv_wr_start_addr,
1102	dec->m_mv_BUF[ret].size);
1103	} else {
1104	pr_info(
1105	"%s: Error, mv buf is not enough\n",
1106	__func__);
1107	}
1108	return ret;
1109	}
1110
1111	static void put_mv_buf(struct AVS2Decoder_s *dec,
1112	struct avs2_frame_s *pic)
1113	{
1114	int i = pic->mv_buf_index;
1115	if (i >= FRAME_BUFFERS) {
1116	if (debug & AVS2_DBG_BUFMGR_MORE)
1117	pr_info(
1118	"%s: index %d beyond range\n",
1119	__func__, i);
1120	return;
1121	}
1122	if (debug & AVS2_DBG_BUFMGR_MORE)
1123	pr_info(
1124	"%s(%d): used_flag(%d)\n",
1125	__func__, i,
1126	dec->m_mv_BUF[i].used_flag);
1127
1128	pic->mv_buf_index = -1;
1129	if (dec->m_mv_BUF[i].start_adr &&
1130	dec->m_mv_BUF[i].used_flag)
1131	dec->m_mv_BUF[i].used_flag = 0;
1132	}
1133
1134	static void put_un_used_mv_bufs(struct AVS2Decoder_s *dec)
1135	{
1136	struct VP9_Common_s *const cm = &dec->common;
1137	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1138	int i;
1139	for (i = 0; i < dec->used_buf_num; ++i) {
1140	if ((frame_bufs[i].ref_count == 0) &&
1141	(frame_bufs[i].buf.index != -1) &&
1142	(frame_bufs[i].buf.mv_buf_index >= 0)
1143	)
1144	put_mv_buf(dec, &frame_bufs[i].buf);
1145	}
1146	}
1147	#endif
1148
1149	#endif
1150
1151	static int get_free_buf_count(struct AVS2Decoder_s *dec)
1152	{
1153	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1154	int i;
1155	int count = 0;
1156	for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1157	if ((avs2_dec->fref[i]->imgcoi_ref < -256
1158	#if 0
1159	|| abs(avs2_dec->fref[i]->
1160	imgtr_fwRefDistance - img->tr) >= 128
1161	#endif
1162	) && avs2_dec->fref[i]->is_output == -1
1163	&& avs2_dec->fref[i]->bg_flag == 0
1164	#ifndef NO_DISPLAY
1165	&& avs2_dec->fref[i]->vf_ref == 0
1166	&& avs2_dec->fref[i]->to_prepare_disp == 0
1167	#endif
1168	) {
1169	count++;
1170	}
1171	}
1172
1173	return count;
1174	}
1175
1176	#ifdef CONSTRAIN_MAX_BUF_NUM
1177	static int get_vf_ref_only_buf_count(struct AVS2Decoder_s *dec)
1178	{
1179	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1180	int i;
1181	int count = 0;
1182	for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1183	if ((avs2_dec->fref[i]->imgcoi_ref < -256
1184	#if 0
1185	|| abs(avs2_dec->fref[i]->
1186	imgtr_fwRefDistance - img->tr) >= 128
1187	#endif
1188	) && avs2_dec->fref[i]->is_output == -1
1189	&& avs2_dec->fref[i]->bg_flag == 0
1190	#ifndef NO_DISPLAY
1191	&& avs2_dec->fref[i]->vf_ref > 0
1192	&& avs2_dec->fref[i]->to_prepare_disp == 0
1193	#endif
1194	) {
1195	count++;
1196	}
1197	}
1198
1199	return count;
1200	}
1201
1202	static int get_used_buf_count(struct AVS2Decoder_s *dec)
1203	{
1204	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1205	int i;
1206	int count = 0;
1207	for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1208	if ((avs2_dec->fref[i]->imgcoi_ref >= -256
1209	#if 0
1210	|| abs(avs2_dec->fref[i]->
1211	imgtr_fwRefDistance - img->tr) >= 128
1212	#endif
1213	) || avs2_dec->fref[i]->is_output != -1
1214	|| avs2_dec->fref[i]->bg_flag != 0
1215	#ifndef NO_DISPLAY
1216	|| avs2_dec->fref[i]->vf_ref != 0
1217	|| avs2_dec->fref[i]->to_prepare_disp != 0
1218	#endif
1219	) {
1220	count++;
1221	}
1222	}
1223
1224	return count;
1225	}
1226	#endif
1227
1228	int avs2_bufmgr_init(struct AVS2Decoder_s *dec, struct BuffInfo_s *buf_spec_i,
1229	struct buff_s *mc_buf_i) {
1230
1231	dec->frame_count = 0;
1232	#ifdef AVS2_10B_MMU
1233	dec->used_4k_num = -1;
1234	dec->cur_fb_idx_mmu = INVALID_IDX;
1235	#endif
1236
1237
1238	/* private init */
1239	dec->work_space_buf = buf_spec_i;
1240	#ifndef AVS2_10B_MMU
1241	dec->mc_buf = mc_buf_i;
1242	#endif
1243	dec->rpm_addr = NULL;
1244	dec->lmem_addr = NULL;
1245
1246	dec->use_cma_flag = 0;
1247	dec->decode_idx = 0;
1248	dec->slice_idx = 0;
1249	/*int m_uiMaxCUWidth = 1<<7;*/
1250	/*int m_uiMaxCUHeight = 1<<7;*/
1251	dec->wait_buf = 0;
1252	dec->error_flag = 0;
1253	dec->skip_PB_before_I = 0;
1254
1255	dec->pts_mode = PTS_NORMAL;
1256	dec->last_pts = 0;
1257	dec->last_lookup_pts = 0;
1258	dec->last_pts_us64 = 0;
1259	dec->last_lookup_pts_us64 = 0;
1260	dec->shift_byte_count = 0;
1261	dec->shift_byte_count_lo = 0;
1262	dec->shift_byte_count_hi = 0;
1263	dec->pts_mode_switching_count = 0;
1264	dec->pts_mode_recovery_count = 0;
1265
1266	dec->buf_num = 0;
1267
1268	dec->bufmgr_error_count = 0;
1269	return 0;
1270	}
1271
1272
1273
1274	#define HEVC_CM_BODY_START_ADDR 0x3626
1275	#define HEVC_CM_BODY_LENGTH 0x3627
1276	#define HEVC_CM_HEADER_LENGTH 0x3629
1277	#define HEVC_CM_HEADER_OFFSET 0x362b
1278
1279	#define LOSLESS_COMPRESS_MODE
1280
1281	/*#define DECOMP_HEADR_SURGENT*/
1282
1283	static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
1284	static u32 enable_mem_saving = 1;
1285	static u32 force_w_h;
1286
1287	static u32 force_fps;
1288
1289
1290	const u32 avs2_version = 201602101;
1291	static u32 debug;
1292	static u32 radr;
1293	static u32 rval;
1294	static u32 pop_shorts;
1295	static u32 dbg_cmd;
1296	static u32 dbg_skip_decode_index;
1297	static u32 endian = 0xff0;
1298	#ifdef ERROR_HANDLE_DEBUG
1299	static u32 dbg_nal_skip_flag;
1300	/* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
1301	static u32 dbg_nal_skip_count;
1302	#endif
1303	/*for debug*/
1304	static u32 decode_pic_begin;
1305	static uint slice_parse_begin;
1306	static u32 step;
1307	#ifdef MIX_STREAM_SUPPORT
1308	static u32 buf_alloc_width = 4096;
1309	static u32 buf_alloc_height = 2304;
1310
1311	static u32 dynamic_buf_num_margin;
1312	#else
1313	static u32 buf_alloc_width;
1314	static u32 buf_alloc_height;
1315	static u32 dynamic_buf_num_margin = 7;
1316	#endif
1317	#ifdef CONSTRAIN_MAX_BUF_NUM
1318	static u32 run_ready_max_vf_only_num;
1319	static u32 run_ready_display_q_num;
1320	/*0: not check
1321	0xff: avs2_dec.ref_maxbuffer
1322	*/
1323	static u32 run_ready_max_buf_num = 0xff;
1324	#endif
1325	static u32 buf_alloc_depth = 10;
1326	static u32 buf_alloc_size;
1327	/*
1328	bit[0]: 0,
1329	bit[1]: 0, always release cma buffer when stop
1330	bit[1]: 1, never release cma buffer when stop
1331	bit[0]: 1, when stop, release cma buffer if blackout is 1;
1332	do not release cma buffer is blackout is not 1
1333
1334	bit[2]: 0, when start decoding, check current displayed buffer
1335	(only for buffer decoded by vp9) if blackout is 0
1336	1, do not check current displayed buffer
1337
1338	bit[3]: 1, if blackout is not 1, do not release current
1339	displayed cma buffer always.
1340	*/
1341	/* set to 1 for fast play;
1342	set to 8 for other case of "keep last frame"
1343	*/
1344	static u32 buffer_mode = 1;
1345	/* buffer_mode_dbg: debug only*/
1346	static u32 buffer_mode_dbg = 0xffff0000;
1347	/**/
1348
1349	/*
1350	bit 0, 1: only display I picture;
1351	bit 1, 1: only decode I picture;
1352	*/
1353	static u32 i_only_flag;
1354
1355
1356	static u32 max_decoding_time;
1357	/*
1358	error handling
1359	*/
1360	/*error_handle_policy:
1361	bit 0: search seq again if buffer mgr error occur
1362	(buffer mgr error count need big than
1363	re_search_seq_threshold)
1364	bit 1: 1, display from I picture;
1365	0, display from any correct pic
1366	*/
1367
1368	static u32 error_handle_policy = 1;
1369	/*
1370	re_search_seq_threshold:
1371	bit 7~0: buffer mgr error research seq count
1372	bit 15~8: frame count threshold
1373	*/
1374	static u32 re_search_seq_threshold = 0x800; /*0x8;*/
1375	/*static u32 parser_sei_enable = 1;*/
1376
1377	static u32 max_buf_num = (REF_BUFFER + 1);
1378
1379	static u32 run_ready_min_buf_num = 2;
1380
1381	static DEFINE_MUTEX(vavs2_mutex);
1382
1383	#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
1384	#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
1385	#define AVS2_ALF_SWAP_BUFFER HEVC_ASSIST_SCRATCH_2
1386	#define HEVC_RCS_BUFFER HEVC_ASSIST_SCRATCH_3
1387	#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4
1388	#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
1389	#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
1390	#ifdef AVS2_10B_MMU
1391	#define AVS2_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7
1392	#else
1393	#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
1394	#endif
1395	#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
1396	/*
1397	#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
1398	#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
1399	#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
1400	*/
1401	#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
1402	#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
1403	#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
1404	#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_9
1405	#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
1406	/*!!!*/
1407	#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
1408	#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
1409	#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
1410	#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
1411
1412
1413	/*
1414	ucode parser/search control
1415	bit 0: 0, header auto parse; 1, header manual parse
1416	bit 1: 0, auto skip for noneseamless stream; 1, no skip
1417	bit [3:2]: valid when bit1==0;
1418	0, auto skip nal before first vps/sps/pps/idr;
1419	1, auto skip nal before first vps/sps/pps
1420	2, auto skip nal before first vps/sps/pps,
1421	and not decode until the first I slice (with slice address of 0)
1422
1423	3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
1424	bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
1425	bit [16]: for NAL_UNIT_EOS when bit0 is 0:
1426	0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
1427	bit [17]: for NAL_SEI when bit0 is 0:
1428	0, do not parse SEI in ucode; 1, parse SEI in ucode
1429	bit [31:20]: used by ucode for debug purpose
1430	*/
1431	#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
1432	/*DECODE_MODE: set before start decoder
1433	bit 7~0: decode mode
1434	bit 23~16: start_decoding_flag
1435	bit [0] - SEQ_ready
1436	bit [2:1] - I Picture Count
1437	bit 31~24: chip feature
1438	*/
1439	#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
1440	#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
1441	/*read only*/
1442	#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
1443
1444	#define RPM_BUF_SIZE (0x600 * 2)
1445	#define LMEM_BUF_SIZE (0x600 * 2)
1446
1447	#define WORK_BUF_SPEC_NUM 3
1448	static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
1449	{
1450	/* 8M bytes */
1451	.max_width = 1920,
1452	.max_height = 1088,
1453	.ipp = {
1454	/* IPP work space calculation :
1455	4096 * (Y+CbCr+Flags) = 12k, round to 16k */
1456	.buf_size = 0x4000,
1457	},
1458	.sao_abv = {
1459	.buf_size = 0x30000,
1460	},
1461	.sao_vb = {
1462	.buf_size = 0x30000,
1463	},
1464	.short_term_rps = {
1465	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1466	total 64x16x2 = 2048 bytes (0x800) */
1467	.buf_size = 0x800,
1468	},
1469	.rcs = {
1470	/* RCS STORE AREA - Max 32 RCS, each has 32 bytes,
1471	total 0x0400 bytes */
1472	.buf_size = 0x400,
1473	},
1474	.sps = {
1475	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1476	total 0x0800 bytes*/
1477	.buf_size = 0x800,
1478	},
1479	.pps = {
1480	/*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1481	total 0x2000 bytes*/
1482	.buf_size = 0x2000,
1483	},
1484	.sao_up = {
1485	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
1486	each has 16 bytes total 0x2800 bytes */
1487	.buf_size = 0x2800,
1488	},
1489	.swap_buf = {
1490	/* 256cyclex64bit = 2K bytes 0x800
1491	(only 144 cycles valid) */
1492	.buf_size = 0x800,
1493	},
1494	.swap_buf2 = {
1495	.buf_size = 0x800,
1496	},
1497	.scalelut = {
1498	/* support up to 32 SCALELUT 1024x32 =
1499	32Kbytes (0x8000) */
1500	.buf_size = 0x8000,
1501	},
1502	.dblk_para = {
1503	/* DBLK -> Max 256(4096/16) LCU,
1504	each para 1024bytes(total:0x40000),
1505	data 1024bytes(total:0x40000)*/
1506	.buf_size = 0x40000,
1507	},
1508	.dblk_data = {
1509	.buf_size = 0x40000,
1510	},
1511	.dblk_data2 = {
1512	.buf_size = 0x40000,
1513	},
1514	#ifdef AVS2_10B_MMU
1515	.mmu_vbh = {
1516	.buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
1517	},
1518	#if 0
1519	.cm_header = {
1520	/*add one for keeper.*/
1521	.buf_size = MMU_COMPRESS_HEADER_SIZE *
1522	(FRAME_BUFFERS + 1),
1523	/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
1524	},
1525	#endif
1526	#endif
1527	.mpred_above = {
1528	.buf_size = 0x8000, /* 2 * size of hevc*/
1529	},
1530	#ifdef MV_USE_FIXED_BUF
1531	.mpred_mv = {/* 1080p, 0x40000 per buffer */
1532	.buf_size = 0x40000 * FRAME_BUFFERS,
1533	},
1534	#endif
1535	.rpm = {
1536	.buf_size = RPM_BUF_SIZE,
1537	},
1538	.lmem = {
1539	.buf_size = 0x400 * 2,
1540	}
1541	},
1542	{
1543	.max_width = 4096,
1544	.max_height = 2304,
1545	.ipp = {
1546	/* IPP work space calculation :
1547	4096 * (Y+CbCr+Flags) = 12k, round to 16k */
1548	.buf_size = 0x4000,
1549	},
1550	.sao_abv = {
1551	.buf_size = 0x30000,
1552	},
1553	.sao_vb = {
1554	.buf_size = 0x30000,
1555	},
1556	.short_term_rps = {
1557	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1558	total 64x16x2 = 2048 bytes (0x800) */
1559	.buf_size = 0x800,
1560	},
1561	.rcs = {
1562	/* RCS STORE AREA - Max 16 RCS, each has 32 bytes,
1563	total 0x0400 bytes */
1564	.buf_size = 0x400,
1565	},
1566	.sps = {
1567	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1568	total 0x0800 bytes */
1569	.buf_size = 0x800,
1570	},
1571	.pps = {
1572	/* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1573	total 0x2000 bytes */
1574	.buf_size = 0x2000,
1575	},
1576	.sao_up = {
1577	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
1578	each has 16 bytes total 0x2800 bytes */
1579	.buf_size = 0x2800,
1580	},
1581	.swap_buf = {
1582	/* 256cyclex64bit = 2K bytes 0x800
1583	(only 144 cycles valid) */
1584	.buf_size = 0x800,
1585	},
1586	.swap_buf2 = {
1587	.buf_size = 0x800,
1588	},
1589	.scalelut = {
1590	/* support up to 32 SCALELUT 1024x32 = 32Kbytes
1591	(0x8000) */
1592	.buf_size = 0x8000,
1593	},
1594	.dblk_para = {
1595	/* DBLK -> Max 256(4096/16) LCU,
1596	each para 1024bytes(total:0x40000),
1597	data 1024bytes(total:0x40000)*/
1598	.buf_size = 0x80000,
1599	},
1600	.dblk_data = {
1601	/*DBLK -> Max 256(4096/16) LCU,
1602	each para 1024bytes(total:0x40000),
1603	data 1024bytes(total:0x40000)*/
1604	.buf_size = 0x80000,
1605	},
1606	.dblk_data2 = {
1607	.buf_size = 0x80000,
1608	},
1609	#ifdef AVS2_10B_MMU
1610	.mmu_vbh = {
1611	.buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
1612	},
1613	#if 0
1614	.cm_header = {
1615	/*add one for keeper.*/
1616	.buf_size = MMU_COMPRESS_HEADER_SIZE *
1617	(FRAME_BUFFERS + 1),
1618	/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
1619	},
1620	#endif
1621	#endif
1622	.mpred_above = {
1623	.buf_size = 0x10000, /* 2 * size of hevc*/
1624	},
1625	#ifdef MV_USE_FIXED_BUF
1626	.mpred_mv = {
1627	/* .buf_size = 0x100000*16,
1628	//4k2k , 0x100000 per buffer */
1629	/* 4096x2304 , 0x120000 per buffer */
1630	.buf_size = 0x120000 * FRAME_BUFFERS,
1631	},
1632	#endif
1633	.rpm = {
1634	.buf_size = RPM_BUF_SIZE,
1635	},
1636	.lmem = {
1637	.buf_size = 0x400 * 2,
1638	}
1639	},
1640	{
1641	.max_width = 4096 * 2,
1642	.max_height = 2304 * 2,
1643	.ipp = {
1644	/*IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k,
1645	round to 16k*/
1646	.buf_size = 0x4000 * 2,
1647	},
1648	.sao_abv = {
1649	.buf_size = 0x30000 * 2,
1650	},
1651	.sao_vb = {
1652	.buf_size = 0x30000 * 2,
1653	},
1654	.short_term_rps = {
1655	/*SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1656	total 64x16x2 = 2048 bytes (0x800)*/
1657	.buf_size = 0x800,
1658	},
1659	.rcs = {
1660	/*RCS STORE AREA - Max 16 RCS, each has 32 bytes,
1661	total 0x0400 bytes*/
1662	.buf_size = 0x400,
1663	},
1664	.sps = {
1665	/*SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1666	total 0x0800 bytes*/
1667	.buf_size = 0x800,
1668	},
1669	.pps = {
1670	/*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total
1671	0x2000 bytes*/
1672	.buf_size = 0x2000,
1673	},
1674	.sao_up = {
1675	/*SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes i
1676	total 0x2800 bytes*/
1677	.buf_size = 0x2800 * 2,
1678	},
1679	.swap_buf = {
1680	/*256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)*/
1681	.buf_size = 0x800,
1682	},
1683	.swap_buf2 = {
1684	.buf_size = 0x800,
1685	},
1686	.scalelut = {
1687	/*support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)*/
1688	.buf_size = 0x8000 * 2,
1689	},
1690	.dblk_para = {
1691	.buf_size = 0x40000 * 2,
1692	},
1693	.dblk_data = {
1694	.buf_size = 0x80000 * 2,
1695	},
1696	.dblk_data2 = {
1697	.buf_size = 0x80000 * 2,
1698	},
1699	#ifdef AVS2_10B_MMU
1700	.mmu_vbh = {
1701	.buf_size = 0x5000 * 2, /*2*16*2304/4, 4K*/
1702	},
1703	#if 0
1704	.cm_header = {
1705	/*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
1706	.buf_size = MMU_COMPRESS_8K_HEADER_SIZE * 17,
1707	},
1708	#endif
1709	#endif
1710	.mpred_above = {
1711	.buf_size = 0x8000 * 2,
1712	},
1713	#ifdef MV_USE_FIXED_BUF
1714	.mpred_mv = {
1715	/*4k2k , 0x100000 per buffer*/
1716	.buf_size = 0x120000 * FRAME_BUFFERS * 4,
1717	},
1718	#endif
1719	.rpm = {
1720	.buf_size = RPM_BUF_SIZE,
1721	},
1722	.lmem = {
1723	.buf_size = 0x400 * 2,
1724	}
1725	}
1726	};
1727
1728
1729	/*Losless compression body buffer size 4K per 64x32 (jt)*/
1730	static int compute_losless_comp_body_size(struct AVS2Decoder_s *dec,
1731	int width, int height,
1732	uint8_t is_bit_depth_10)
1733	{
1734	int width_x64;
1735	int height_x32;
1736	int bsize;
1737	width_x64 = width + 63;
1738	width_x64 >>= 6;
1739	height_x32 = height + 31;
1740	height_x32 >>= 5;
1741	#ifdef AVS2_10B_MMU
1742	bsize = (is_bit_depth_10 ? 4096 : 3200)
1743	* width_x64 * height_x32;
1744	#else
1745	bsize = (is_bit_depth_10 ? 4096 : 3072)
1746	* width_x64 * height_x32;
1747	#endif
1748	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
1749	"%s(%d,%d,%d)=>%d\n",
1750	__func__, width, height,
1751	is_bit_depth_10, bsize);
1752
1753	return bsize;
1754	}
1755
1756	/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
1757	static int compute_losless_comp_header_size(struct AVS2Decoder_s *dec,
1758	int width, int height)
1759	{
1760	int width_x128;
1761	int height_x64;
1762	int hsize;
1763	width_x128 = width + 127;
1764	width_x128 >>= 7;
1765	height_x64 = height + 63;
1766	height_x64 >>= 6;
1767
1768	hsize = 32 * width_x128 * height_x64;
1769	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
1770	"%s(%d,%d)=>%d\n",
1771	__func__, width, height,
1772	hsize);
1773
1774	return hsize;
1775	}
1776
1777	static void init_buff_spec(struct AVS2Decoder_s *dec,
1778	struct BuffInfo_s *buf_spec)
1779	{
1780	void *mem_start_virt;
1781	buf_spec->ipp.buf_start = buf_spec->start_adr;
1782	buf_spec->sao_abv.buf_start =
1783	buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
1784
1785	buf_spec->sao_vb.buf_start =
1786	buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
1787	buf_spec->short_term_rps.buf_start =
1788	buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
1789	buf_spec->rcs.buf_start =
1790	buf_spec->short_term_rps.buf_start +
1791	buf_spec->short_term_rps.buf_size;
1792	buf_spec->sps.buf_start =
1793	buf_spec->rcs.buf_start + buf_spec->rcs.buf_size;
1794	buf_spec->pps.buf_start =
1795	buf_spec->sps.buf_start + buf_spec->sps.buf_size;
1796	buf_spec->sao_up.buf_start =
1797	buf_spec->pps.buf_start + buf_spec->pps.buf_size;
1798	buf_spec->swap_buf.buf_start =
1799	buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
1800	buf_spec->swap_buf2.buf_start =
1801	buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
1802	buf_spec->scalelut.buf_start =
1803	buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
1804	buf_spec->dblk_para.buf_start =
1805	buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
1806	buf_spec->dblk_data.buf_start =
1807	buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
1808	buf_spec->dblk_data2.buf_start =
1809	buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
1810	#ifdef AVS2_10B_MMU
1811	buf_spec->mmu_vbh.buf_start =
1812	buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1813	buf_spec->mpred_above.buf_start =
1814	buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
1815	#else
1816	buf_spec->mpred_above.buf_start =
1817	buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1818	#endif
1819	#ifdef MV_USE_FIXED_BUF
1820	buf_spec->mpred_mv.buf_start =
1821	buf_spec->mpred_above.buf_start +
1822	buf_spec->mpred_above.buf_size;
1823
1824	buf_spec->rpm.buf_start =
1825	buf_spec->mpred_mv.buf_start +
1826	buf_spec->mpred_mv.buf_size;
1827	#else
1828	buf_spec->rpm.buf_start =
1829	buf_spec->mpred_above.buf_start +
1830	buf_spec->mpred_above.buf_size;
1831
1832	#endif
1833	buf_spec->lmem.buf_start =
1834	buf_spec->rpm.buf_start +
1835	buf_spec->rpm.buf_size;
1836	buf_spec->end_adr =
1837	buf_spec->lmem.buf_start +
1838	buf_spec->lmem.buf_size;
1839
1840	if (dec) {
1841	mem_start_virt =
1842	codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
1843	if (mem_start_virt) {
1844	memset(mem_start_virt, 0, buf_spec->dblk_para.buf_size);
1845	codec_mm_dma_flush(mem_start_virt,
1846	buf_spec->dblk_para.buf_size,
1847	DMA_TO_DEVICE);
1848	} else {
1849	/*not virt for tvp playing,
1850	may need clear on ucode.*/
1851	pr_err("mem_start_virt failed\n");
1852	}
1853	if (debug) {
1854	pr_info("%s workspace (%x %x) size = %x\n", __func__,
1855	buf_spec->start_adr, buf_spec->end_adr,
1856	buf_spec->end_adr - buf_spec->start_adr);
1857	}
1858	if (debug) {
1859	pr_info("ipp.buf_start :%x\n",
1860	buf_spec->ipp.buf_start);
1861	pr_info("sao_abv.buf_start :%x\n",
1862	buf_spec->sao_abv.buf_start);
1863	pr_info("sao_vb.buf_start :%x\n",
1864	buf_spec->sao_vb.buf_start);
1865	pr_info("short_term_rps.buf_start :%x\n",
1866	buf_spec->short_term_rps.buf_start);
1867	pr_info("rcs.buf_start :%x\n",
1868	buf_spec->rcs.buf_start);
1869	pr_info("sps.buf_start :%x\n",
1870	buf_spec->sps.buf_start);
1871	pr_info("pps.buf_start :%x\n",
1872	buf_spec->pps.buf_start);
1873	pr_info("sao_up.buf_start :%x\n",
1874	buf_spec->sao_up.buf_start);
1875	pr_info("swap_buf.buf_start :%x\n",
1876	buf_spec->swap_buf.buf_start);
1877	pr_info("swap_buf2.buf_start :%x\n",
1878	buf_spec->swap_buf2.buf_start);
1879	pr_info("scalelut.buf_start :%x\n",
1880	buf_spec->scalelut.buf_start);
1881	pr_info("dblk_para.buf_start :%x\n",
1882	buf_spec->dblk_para.buf_start);
1883	pr_info("dblk_data.buf_start :%x\n",
1884	buf_spec->dblk_data.buf_start);
1885	pr_info("dblk_data2.buf_start :%x\n",
1886	buf_spec->dblk_data2.buf_start);
1887	#ifdef AVS2_10B_MMU
1888	pr_info("mmu_vbh.buf_start :%x\n",
1889	buf_spec->mmu_vbh.buf_start);
1890	#endif
1891	pr_info("mpred_above.buf_start :%x\n",
1892	buf_spec->mpred_above.buf_start);
1893	#ifdef MV_USE_FIXED_BUF
1894	pr_info("mpred_mv.buf_start :%x\n",
1895	buf_spec->mpred_mv.buf_start);
1896	#endif
1897	if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) {
1898	pr_info("rpm.buf_start :%x\n",
1899	buf_spec->rpm.buf_start);
1900	}
1901	}
1902	}
1903
1904	}
1905
1906	static void uninit_mmu_buffers(struct AVS2Decoder_s *dec)
1907	{
1908	#if 0
1909	/*ndef MV_USE_FIXED_BUF*/
1910	dealloc_mv_bufs(dec);
1911	#endif
1912	decoder_mmu_box_free(dec->mmu_box);
1913	dec->mmu_box = NULL;
1914
1915	if (dec->bmmu_box)
1916	decoder_bmmu_box_free(dec->bmmu_box);
1917	dec->bmmu_box = NULL;
1918	}
1919
1920	#ifndef AVS2_10B_MMU
1921	static void init_buf_list(struct AVS2Decoder_s *dec)
1922	{
1923	int i;
1924	int buf_size;
1925	int mc_buffer_end = dec->mc_buf->buf_start + dec->mc_buf->buf_size;
1926	dec->used_buf_num = max_buf_num;
1927
1928	if (dec->used_buf_num > MAX_BUF_NUM)
1929	dec->used_buf_num = MAX_BUF_NUM;
1930	if (buf_alloc_size > 0) {
1931	buf_size = buf_alloc_size;
1932	avs2_print(dec, AVS2_DBG_BUFMGR,
1933	"[Buffer Management] init_buf_list:\n");
1934	} else {
1935	int pic_width = dec->init_pic_w;
1936	int pic_height = dec->init_pic_h;
1937
1938	/*SUPPORT_10BIT*/
1939	int losless_comp_header_size = compute_losless_comp_header_size
1940	(dec, pic_width, pic_height);
1941	int losless_comp_body_size = compute_losless_comp_body_size
1942	(dec, pic_width, pic_height, buf_alloc_depth == 10);
1943	int mc_buffer_size = losless_comp_header_size
1944	+ losless_comp_body_size;
1945	int mc_buffer_size_h = (mc_buffer_size + 0xffff)>>16;
1946
1947	int dw_mode = get_double_write_mode_init(dec);
1948
1949	if (dw_mode) {
1950	int pic_width_dw = pic_width /
1951	get_double_write_ratio(dec, dw_mode);
1952	int pic_height_dw = pic_height /
1953	get_double_write_ratio(dec, dw_mode);
1954	int lcu_size = 64; /*fixed 64*/
1955	int pic_width_64 = (pic_width_dw + 63) & (~0x3f);
1956	int pic_height_32 = (pic_height_dw + 31) & (~0x1f);
1957	int pic_width_lcu =
1958	(pic_width_64 % lcu_size) ? pic_width_64 / lcu_size
1959	+ 1 : pic_width_64 / lcu_size;
1960	int pic_height_lcu =
1961	(pic_height_32 % lcu_size) ? pic_height_32 / lcu_size
1962	+ 1 : pic_height_32 / lcu_size;
1963	int lcu_total = pic_width_lcu * pic_height_lcu;
1964	int mc_buffer_size_u_v = lcu_total * lcu_size * lcu_size / 2;
1965	int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
1966	/*64k alignment*/
1967	buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
1968	} else
1969	buf_size = 0;
1970
1971	if (mc_buffer_size & 0xffff) { /*64k alignment*/
1972	mc_buffer_size_h += 1;
1973	}
1974	if ((dw_mode & 0x10) == 0)
1975	buf_size += (mc_buffer_size_h << 16);
1976	avs2_print(dec, AVS2_DBG_BUFMGR,
1977	"init_buf_list num %d (width %d height %d):\n",
1978	dec->used_buf_num, pic_width, pic_height);
1979	}
1980
1981	for (i = 0; i < dec->used_buf_num; i++) {
1982	if (((i + 1) * buf_size) > dec->mc_buf->buf_size)
1983	dec->use_cma_flag = 1;
1984	#ifndef AVS2_10B_MMU
1985	dec->m_BUF[i].alloc_flag = 0;
1986	dec->m_BUF[i].index = i;
1987
1988	dec->use_cma_flag = 1;
1989	if (dec->use_cma_flag) {
1990	dec->m_BUF[i].cma_page_count =
1991	PAGE_ALIGN(buf_size) / PAGE_SIZE;
1992	if (decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box,
1993	VF_BUFFER_IDX(i), buf_size, DRIVER_NAME,
1994	&dec->m_BUF[i].alloc_addr) < 0) {
1995	dec->m_BUF[i].cma_page_count = 0;
1996	if (i <= 5) {
1997	dec->fatal_error |=
1998	DECODER_FATAL_ERROR_NO_MEM;
1999	}
2000	break;
2001	}
2002	dec->m_BUF[i].start_adr = dec->m_BUF[i].alloc_addr;
2003	} else {
2004	dec->m_BUF[i].cma_page_count = 0;
2005	dec->m_BUF[i].alloc_addr = 0;
2006	dec->m_BUF[i].start_adr =
2007	dec->mc_buf->buf_start + i * buf_size;
2008	}
2009	dec->m_BUF[i].size = buf_size;
2010	dec->m_BUF[i].free_start_adr = dec->m_BUF[i].start_adr;
2011
2012	if (((dec->m_BUF[i].start_adr + buf_size) > mc_buffer_end)
2013	&& (dec->m_BUF[i].alloc_addr == 0)) {
2014	if (debug) {
2015	avs2_print(dec, 0,
2016	"Max mc buffer or mpred_mv buffer is used\n");
2017	}
2018	break;
2019	}
2020
2021	avs2_print(dec, AVS2_DBG_BUFMGR,
2022	"Buffer %d: start_adr %p size %x\n", i,
2023	(void *)dec->m_BUF[i].start_adr,
2024	dec->m_BUF[i].size);
2025	#endif
2026	}
2027	dec->buf_num = i;
2028	}
2029	#endif
2030
2031	static int config_pic(struct AVS2Decoder_s *dec,
2032	struct avs2_frame_s *pic, int32_t lcu_size_log2)
2033	{
2034	int ret = -1;
2035	int i;
2036	int pic_width = dec->init_pic_w;
2037	int pic_height = dec->init_pic_h;
2038	/*struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2039	int32_t lcu_size_log2 = avs2_dec->lcu_size_log2;*/
2040	int32_t lcu_size = 1 << lcu_size_log2;
2041	int pic_width_64 = (pic_width + 63) & (~0x3f);
2042	int pic_height_32 = (pic_height + 31) & (~0x1f);
2043	int pic_width_lcu = (pic_width_64 % lcu_size) ?
2044	pic_width_64 / lcu_size + 1
2045	: pic_width_64 / lcu_size;
2046	int pic_height_lcu = (pic_height_32 % lcu_size) ?
2047	pic_height_32 / lcu_size + 1
2048	: pic_height_32 / lcu_size;
2049	int lcu_total = pic_width_lcu * pic_height_lcu;
2050	#if 0
2051	int32_t MV_MEM_UNIT =
2052	(lcu_size_log2 == 6) ? 0x200 :
2053	((lcu_size_log2 == 5) ? 0x80 : 0x20);
2054	#endif
2055	#ifdef MV_USE_FIXED_BUF
2056	u32 mpred_mv_end = dec->work_space_buf->mpred_mv.buf_start +
2057	dec->work_space_buf->mpred_mv.buf_size;
2058	#endif
2059	u32 y_adr = 0;
2060	int buf_size = 0;
2061
2062	int losless_comp_header_size =
2063	compute_losless_comp_header_size(
2064	dec, pic_width, pic_height);
2065	int losless_comp_body_size = compute_losless_comp_body_size(
2066	dec, pic_width,
2067	pic_height, buf_alloc_depth == 10);
2068	int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
2069	int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
2070	int mc_buffer_size_u_v = 0;
2071	int mc_buffer_size_u_v_h = 0;
2072	int dw_mode = get_double_write_mode_init(dec);
2073
2074	if (dw_mode) {
2075	int pic_width_dw = pic_width /
2076	get_double_write_ratio(dec, dw_mode);
2077	int pic_height_dw = pic_height /
2078	get_double_write_ratio(dec, dw_mode);
2079	int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
2080	int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
2081	int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
2082	pic_width_64_dw / lcu_size + 1
2083	: pic_width_64_dw / lcu_size;
2084	int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
2085	pic_height_32_dw / lcu_size + 1
2086	: pic_height_32_dw / lcu_size;
2087	int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
2088
2089	mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
2090	mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
2091	/*64k alignment*/
2092	buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
2093	buf_size = ((buf_size + 0xffff) >> 16) << 16;
2094	}
2095	if (mc_buffer_size & 0xffff) /*64k alignment*/
2096	mc_buffer_size_h += 1;
2097	#ifndef AVS2_10B_MMU
2098	if ((dw_mode & 0x10) == 0)
2099	buf_size += (mc_buffer_size_h << 16);
2100	#endif
2101
2102	#ifdef AVS2_10B_MMU
2103	#ifndef DYNAMIC_ALLOC_HEAD
2104	pic->header_adr = decoder_bmmu_box_get_phy_addr(
2105	dec->bmmu_box, HEADER_BUFFER_IDX(pic->index));
2106
2107	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
2108	"buf_size %d, MMU header_adr %d: %ld\n",
2109	buf_size, pic->index, pic->header_adr);
2110	#endif
2111	#endif
2112
2113	i = pic->index;
2114	#ifdef MV_USE_FIXED_BUF
2115	#ifdef G12A_BRINGUP_DEBUG
2116	if (1) {
2117	#else
2118	if ((dec->work_space_buf->mpred_mv.buf_start +
2119	(((i + 1) * lcu_total) * MV_MEM_UNIT))
2120	<= mpred_mv_end
2121	) {
2122	#endif
2123	#endif
2124	#ifndef AVS2_10B_MMU
2125	if (debug) {
2126	pr_err("start %x .size=%d\n",
2127	dec->mc_buf_spec.buf_start + i * buf_size,
2128	buf_size);
2129	}
2130	#endif
2131	#ifndef AVS2_10B_MMU
2132	for (i = 0; i < dec->buf_num; i++) {
2133	y_adr = ((dec->m_BUF[i].free_start_adr
2134	+ 0xffff) >> 16) << 16;
2135	/*64k alignment*/
2136	if ((y_adr+buf_size) <= (dec->m_BUF[i].start_adr+
2137	dec->m_BUF[i].size)) {
2138	dec->m_BUF[i].free_start_adr =
2139	y_adr + buf_size;
2140	break;
2141	}
2142	}
2143	if (i < dec->buf_num)
2144	#else
2145	/*if ((dec->mc_buf->buf_start + (i + 1) * buf_size) <
2146	dec->mc_buf->buf_end)
2147	y_adr = dec->mc_buf->buf_start + i * buf_size;
2148	else {*/
2149	if (buf_size > 0 && pic->cma_alloc_addr == 0) {
2150	ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box,
2151	VF_BUFFER_IDX(i),
2152	buf_size, DRIVER_NAME,
2153	&pic->cma_alloc_addr);
2154	if (ret < 0) {
2155	avs2_print(dec, 0,
2156	"decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
2157	VF_BUFFER_IDX(i),
2158	buf_size
2159	);
2160	return ret;
2161	}
2162
2163	if (pic->cma_alloc_addr)
2164	y_adr = pic->cma_alloc_addr;
2165	else {
2166	avs2_print(dec, 0,
2167	"decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
2168	VF_BUFFER_IDX(i),
2169	buf_size
2170	);
2171	return -1;
2172	}
2173	}
2174	#endif
2175	{
2176	/*ensure get_pic_by_POC()
2177	not get the buffer not decoded*/
2178	pic->BUF_index = i;
2179	pic->lcu_total = lcu_total;
2180
2181	pic->comp_body_size = losless_comp_body_size;
2182	pic->buf_size = buf_size;
2183	#ifndef AVS2_10B_MMU
2184	pic->mc_y_adr = y_adr;
2185	#endif
2186	pic->mc_canvas_y = pic->index;
2187	pic->mc_canvas_u_v = pic->index;
2188	#ifndef AVS2_10B_MMU
2189	if (dw_mode & 0x10) {
2190	pic->mc_u_v_adr = y_adr +
2191	((mc_buffer_size_u_v_h << 16) << 1);
2192
2193	pic->mc_canvas_y =
2194	(pic->index << 1);
2195	pic->mc_canvas_u_v =
2196	(pic->index << 1) + 1;
2197
2198	pic->dw_y_adr = y_adr;
2199	pic->dw_u_v_adr = pic->mc_u_v_adr;
2200	} else
2201	#endif
2202	if (dw_mode) {
2203	pic->dw_y_adr = y_adr
2204	#ifndef AVS2_10B_MMU
2205	+ (mc_buffer_size_h << 16)
2206	#endif
2207	;
2208	pic->dw_u_v_adr = pic->dw_y_adr +
2209	((mc_buffer_size_u_v_h << 16) << 1);
2210	#ifdef AVS2_10B_MMU
2211	pic->mc_y_adr = pic->dw_y_adr;
2212	pic->mc_u_v_adr = pic->dw_u_v_adr;
2213	#endif
2214	}
2215	#ifdef MV_USE_FIXED_BUF
2216	#ifdef G12A_BRINGUP_DEBUG
2217	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
2218	pic->mpred_mv_wr_start_addr =
2219	dec->work_space_buf->mpred_mv.buf_start +
2220	(pic->index * 0x120000 * 4);
2221	} else {
2222	pic->mpred_mv_wr_start_addr =
2223	dec->work_space_buf->mpred_mv.buf_start +
2224	(pic->index * 0x120000);
2225	}
2226	#else
2227	pic->mpred_mv_wr_start_addr =
2228	dec->work_space_buf->mpred_mv.buf_start +
2229	((pic->index * lcu_total)
2230	* MV_MEM_UNIT);
2231	#endif
2232	#endif
2233	if (debug) {
2234	avs2_print(dec, AVS2_DBG_BUFMGR,
2235	"%s index %d BUF_index %d mc_y_adr %x ",
2236	__func__, pic->index,
2237	pic->BUF_index,
2238	pic->mc_y_adr);
2239	avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2240	"comp_body_size %x comp_buf_size %x ",
2241	pic->comp_body_size,
2242	pic->buf_size);
2243	avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2244	"mpred_mv_wr_start_adr %d\n",
2245	pic->mpred_mv_wr_start_addr);
2246	avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2247	"dw_y_adr %d, pic->dw_u_v_adr =%d\n",
2248	pic->dw_y_adr,
2249	pic->dw_u_v_adr);
2250	}
2251	ret = 0;
2252	}
2253	#ifdef MV_USE_FIXED_BUF
2254	} else {
2255	avs2_print(dec, 0,
2256	"mv buffer alloc fail %x > %x\n",
2257	dec->work_space_buf->mpred_mv.buf_start +
2258	(((i + 1) * lcu_total) * MV_MEM_UNIT),
2259	mpred_mv_end);
2260	}
2261	#endif
2262	return ret;
2263	}
2264
2265	static void init_pic_list(struct AVS2Decoder_s *dec,
2266	int32_t lcu_size_log2)
2267	{
2268	int i;
2269	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2270	struct avs2_frame_s *pic;
2271	#ifdef AVS2_10B_MMU
2272	unsigned long buf_addr1;
2273	/*alloc AVS2 compress header first*/
2274	if (decoder_bmmu_box_alloc_buf_phy
2275	(dec->bmmu_box,
2276	HEADER_BUFFER_IDX(-1), get_compress_header_size(dec),
2277	DRIVER_HEADER_NAME,
2278	&buf_addr1) < 0){
2279	avs2_print(dec, 0,
2280	"%s malloc compress header failed %d\n",
2281	DRIVER_HEADER_NAME, -1);
2282	dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2283	return;
2284	}
2285	#ifndef DYNAMIC_ALLOC_HEAD
2286	for (i = 0; i < dec->used_buf_num; i++) {
2287	unsigned long buf_addr;
2288	if (decoder_bmmu_box_alloc_buf_phy
2289	(dec->bmmu_box,
2290	HEADER_BUFFER_IDX(i), get_compress_header_size(dec),
2291	DRIVER_HEADER_NAME,
2292	&buf_addr) < 0){
2293	avs2_print(dec, 0,
2294	"%s malloc compress header failed %d\n",
2295	DRIVER_HEADER_NAME, i);
2296	dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2297	return;
2298	}
2299	}
2300	#endif
2301	#endif
2302	dec->frame_height = avs2_dec->img.height;
2303	dec->frame_width = avs2_dec->img.width;
2304
2305	for (i = 0; i < dec->used_buf_num; i++) {
2306	if (i == (dec->used_buf_num - 1))
2307	pic = avs2_dec->m_bg;
2308	else
2309	pic = avs2_dec->fref[i];
2310	pic->index = i;
2311	pic->BUF_index = -1;
2312	pic->mv_buf_index = -1;
2313	if (config_pic(dec, pic, lcu_size_log2) < 0) {
2314	if (debug)
2315	avs2_print(dec, 0,
2316	"Config_pic %d fail\n",
2317	pic->index);
2318	pic->index = -1;
2319	break;
2320	}
2321	pic->pic_w = avs2_dec->img.width;
2322	pic->pic_h = avs2_dec->img.height;
2323	}
2324	for (; i < dec->used_buf_num; i++) {
2325	if (i == (dec->used_buf_num - 1))
2326	pic = avs2_dec->m_bg;
2327	else
2328	pic = avs2_dec->fref[i];
2329	pic->index = -1;
2330	pic->BUF_index = -1;
2331	pic->mv_buf_index = -1;
2332	}
2333	avs2_print(dec, AVS2_DBG_BUFMGR,
2334	"%s ok, used_buf_num = %d\n",
2335	__func__, dec->used_buf_num);
2336	dec->pic_list_init_flag = 1;
2337	}
2338
2339
2340	static void init_pic_list_hw(struct AVS2Decoder_s *dec)
2341	{
2342	int i;
2343	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2344	struct avs2_frame_s *pic;
2345	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
2346	#if 0
2347	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2348	(0x1 << 1) | (0x1 << 2));
2349
2350	#ifdef DUAL_CORE_64
2351	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2352	(0x1 << 1) | (0x1 << 2));
2353	#endif
2354	#endif
2355	for (i = 0; i < dec->used_buf_num; i++) {
2356	if (i == (dec->used_buf_num - 1))
2357	pic = avs2_dec->m_bg;
2358	else
2359	pic = avs2_dec->fref[i];
2360	if (pic->index < 0)
2361	break;
2362	#ifdef AVS2_10B_MMU
2363	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2364	pic->header_adr
2365	| (pic->mc_canvas_y << 8)|0x1);*/
2366	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2367	(0x1 << 1) | (pic->index << 8));
2368
2369	#ifdef DUAL_CORE_64
2370	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXLX2)
2371	WRITE_VREG(HEVC2_MPP_ANC2AXI_TBL_CONF_ADDR,
2372	(0x1 << 1) | (pic->index << 8));
2373	else
2374	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2375	(0x1 << 1) | (pic->index << 8));
2376	#endif
2377	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->header_adr >> 5);
2378	#else
2379	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2380	pic->mc_y_adr
2381	| (pic->mc_canvas_y << 8) | 0x1);*/
2382	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_y_adr >> 5);
2383	#endif
2384	#ifndef LOSLESS_COMPRESS_MODE
2385	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2386	pic->mc_u_v_adr
2387	| (pic->mc_canvas_u_v << 8)| 0x1);*/
2388	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_u_v_adr >> 5);
2389	#endif
2390	#ifdef DUAL_CORE_64
2391	#ifdef AVS2_10B_MMU
2392	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2393	pic->header_adr >> 5);
2394	#else
2395	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2396	pic->mc_y_adr >> 5);
2397	#endif
2398	#ifndef LOSLESS_COMPRESS_MODE
2399	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2400	pic->mc_u_v_adr >> 5);
2401	#endif
2402	/*DUAL_CORE_64*/
2403	#endif
2404	}
2405	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
2406	#ifdef DUAL_CORE_64
2407	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2408	0x1);
2409	#endif
2410	/*Zero out canvas registers in IPP -- avoid simulation X*/
2411	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2412	(0 << 8) | (0 << 1) | 1);
2413	for (i = 0; i < 32; i++) {
2414	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2415	#ifdef DUAL_CORE_64
2416	WRITE_VREG(HEVC2_HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2417	#endif
2418	}
2419	}
2420
2421
2422	static void dump_pic_list(struct AVS2Decoder_s *dec)
2423	{
2424	int ii;
2425	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2426	for (ii = 0; ii < avs2_dec->ref_maxbuffer; ii++) {
2427	avs2_print(dec, 0,
2428	"fref[%d]: index %d decode_id %d mvbuf %d imgcoi_ref %d imgtr_fwRefDistance %d refered %d, pre %d is_out %d, bg %d, vf_ref %d error %d lcu %d ref_pos(%d,%d,%d,%d,%d,%d,%d)\n",
2429	ii, avs2_dec->fref[ii]->index,
2430	avs2_dec->fref[ii]->decode_idx,
2431	avs2_dec->fref[ii]->mv_buf_index,
2432	avs2_dec->fref[ii]->imgcoi_ref,
2433	avs2_dec->fref[ii]->imgtr_fwRefDistance,
2434	avs2_dec->fref[ii]->refered_by_others,
2435	avs2_dec->fref[ii]->to_prepare_disp,
2436	avs2_dec->fref[ii]->is_output,
2437	avs2_dec->fref[ii]->bg_flag,
2438	avs2_dec->fref[ii]->vf_ref,
2439	avs2_dec->fref[ii]->error_mark,
2440	avs2_dec->fref[ii]->decoded_lcu,
2441	avs2_dec->fref[ii]->ref_poc[0],
2442	avs2_dec->fref[ii]->ref_poc[1],
2443	avs2_dec->fref[ii]->ref_poc[2],
2444	avs2_dec->fref[ii]->ref_poc[3],
2445	avs2_dec->fref[ii]->ref_poc[4],
2446	avs2_dec->fref[ii]->ref_poc[5],
2447	avs2_dec->fref[ii]->ref_poc[6]
2448	);
2449	}
2450	return;
2451	}
2452
2453	static int config_mc_buffer(struct AVS2Decoder_s *dec)
2454	{
2455	int32_t i;
2456	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2457	struct avs2_frame_s *pic;
2458	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2459
2460	/*if (avs2_dec->img.type == I_IMG)
2461	return 0;
2462	*/
2463	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2464	"Entered config_mc_buffer....\n");
2465	if (avs2_dec->f_bg != NULL) {
2466	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2467	"config_mc_buffer for background (canvas_y %d, canvas_u_v %d)\n",
2468	avs2_dec->f_bg->mc_canvas_y, avs2_dec->f_bg->mc_canvas_u_v);
2469	/*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2470	(7 << 8) | (0<<1) | 1); L0:BG */
2471	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2472	(15 << 8) | (0<<1) | 1); /* L0:BG*/
2473	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2474	(avs2_dec->f_bg->mc_canvas_u_v << 16) |
2475	(avs2_dec->f_bg->mc_canvas_u_v << 8) |
2476	avs2_dec->f_bg->mc_canvas_y);
2477	/*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2478	(23 << 8) | (0<<1) | 1); L1:BG*/
2479	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2480	(31 << 8) | (0<<1) | 1); /* L1:BG*/
2481	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2482	(avs2_dec->f_bg->mc_canvas_u_v << 16) |
2483	(avs2_dec->f_bg->mc_canvas_u_v << 8) |
2484	avs2_dec->f_bg->mc_canvas_y);
2485	}
2486
2487	if (avs2_dec->img.type == I_IMG)
2488	return 0;
2489
2490	if (avs2_dec->img.type == P_IMG) {
2491	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2492	"config_mc_buffer for P_IMG, img type %d\n",
2493	avs2_dec->img.type);
2494	/*refer to prepare_RefInfo()*/
2495	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2496	(0 << 8) | (0<<1) | 1);
2497	for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2498	pic = avs2_dec->fref[i];
2499	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2500	(pic->mc_canvas_u_v << 16) |
2501	(pic->mc_canvas_u_v << 8) |
2502	pic->mc_canvas_y);
2503
2504	if (pic->error_mark)
2505	cur_pic->error_mark = 1;
2506
2507	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2508	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2509	i, pic->mc_canvas_u_v, pic->mc_canvas_y,
2510	pic->error_mark);
2511	}
2512	} else if (avs2_dec->img.type == F_IMG) {
2513	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2514	"config_mc_buffer for F_IMG, img type %d\n",
2515	avs2_dec->img.type);
2516	/*refer to prepare_RefInfo()*/
2517	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2518	(0 << 8) | (0<<1) | 1);
2519	for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2520	pic = avs2_dec->fref[i];
2521	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2522	(pic->mc_canvas_u_v << 16) |
2523	(pic->mc_canvas_u_v << 8) |
2524	pic->mc_canvas_y);
2525
2526	if (pic->error_mark)
2527	cur_pic->error_mark = 1;
2528
2529	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2530	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2531	i, pic->mc_canvas_u_v, pic->mc_canvas_y,
2532	pic->error_mark);
2533	}
2534	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2535	(16 << 8) | (0<<1) | 1);
2536	for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2537	pic = avs2_dec->fref[i];
2538	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2539	(pic->mc_canvas_u_v << 16) |
2540	(pic->mc_canvas_u_v << 8) |
2541	pic->mc_canvas_y);
2542	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2543	"refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
2544	i, pic->mc_canvas_u_v, pic->mc_canvas_y);
2545	}
2546	} else {
2547	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2548	"config_mc_buffer for B_IMG\n");
2549	/*refer to prepare_RefInfo()*/
2550	pic = avs2_dec->fref[1];
2551	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2552	(0 << 8) | (0<<1) | 1);
2553	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2554	(pic->mc_canvas_u_v << 16) |
2555	(pic->mc_canvas_u_v << 8) |
2556	pic->mc_canvas_y);
2557
2558	if (pic->error_mark)
2559	cur_pic->error_mark = 1;
2560
2561	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2562	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2563	1, pic->mc_canvas_u_v, pic->mc_canvas_y,
2564	pic->error_mark);
2565
2566	pic = avs2_dec->fref[0];
2567	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2568	(16 << 8) | (0<<1) | 1);
2569	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2570	(pic->mc_canvas_u_v<<16) |
2571	(pic->mc_canvas_u_v<<8) |
2572	pic->mc_canvas_y);
2573
2574	if (pic->error_mark)
2575	cur_pic->error_mark = 1;
2576
2577	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2578	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2579	0, pic->mc_canvas_u_v, pic->mc_canvas_y,
2580	pic->error_mark);
2581	}
2582	return 0;
2583	}
2584	#if 0
2585	static void mcrcc_get_hitrate(void)
2586	{
2587	u32 tmp;
2588	u32 raw_mcr_cnt;
2589	u32 hit_mcr_cnt;
2590	u32 byp_mcr_cnt_nchoutwin;
2591	u32 byp_mcr_cnt_nchcanv;
2592	int hitrate;
2593
2594	if (debug & AVS2_DBG_CACHE)
2595	pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
2596	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
2597	raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2598	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
2599	hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2600	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
2601	byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2602	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
2603	byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2604
2605	if (debug & AVS2_DBG_CACHE) {
2606	pr_info("raw_mcr_cnt_total: %d\n",raw_mcr_cnt);
2607	pr_info("hit_mcr_cnt_total: %d\n",hit_mcr_cnt);
2608	pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",byp_mcr_cnt_nchoutwin);
2609	pr_info("byp_mcr_cnt_nchcanv_total: %d\n",byp_mcr_cnt_nchcanv);
2610	}
2611	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
2612	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2613	if (debug & AVS2_DBG_CACHE)
2614	pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
2615
2616	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
2617	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2618	if (debug & AVS2_DBG_CACHE)
2619	pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
2620
2621	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
2622	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2623	if (debug & AVS2_DBG_CACHE)
2624	pr_info("hit_mcr_0_cnt_total: %d\n",tmp);
2625
2626	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
2627	tmp= READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2628	if (debug & AVS2_DBG_CACHE)
2629	pr_info("hit_mcr_1_cnt_total: %d\n",tmp);
2630
2631	if (raw_mcr_cnt != 0) {
2632	hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2633	if (debug & AVS2_DBG_CACHE)
2634	pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
2635	hitrate = ((byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
2636	/raw_mcr_cnt) * 100;
2637	if (debug & AVS2_DBG_CACHE)
2638	pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
2639	} else if (debug & AVS2_DBG_CACHE) {
2640	pr_info("MCRCC_HIT_RATE : na\n");
2641	pr_info("MCRCC_BYP_RATE : na\n");
2642	}
2643	return;
2644	}
2645
2646
2647	static void decomp_get_hitrate(void)
2648	{
2649	u32 raw_mcr_cnt;
2650	u32 hit_mcr_cnt;
2651	int hitrate;
2652
2653	if (debug & AVS2_DBG_CACHE)
2654	pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
2655	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
2656	raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2657	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
2658	hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2659
2660	if (debug & AVS2_DBG_CACHE) {
2661	pr_info("hcache_raw_cnt_total: %d\n",raw_mcr_cnt);
2662	pr_info("hcache_hit_cnt_total: %d\n",hit_mcr_cnt);
2663	}
2664	if (raw_mcr_cnt != 0) {
2665	hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2666	if (debug & AVS2_DBG_CACHE)
2667	pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
2668	} else {
2669	if (debug & AVS2_DBG_CACHE)
2670	pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
2671	}
2672	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
2673	raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2674	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
2675	hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2676
2677	if (debug & AVS2_DBG_CACHE) {
2678	pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
2679	pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
2680	}
2681	if (raw_mcr_cnt != 0) {
2682	hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2683	if (debug & AVS2_DBG_CACHE)
2684	pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
2685	} else if (debug & AVS2_DBG_CACHE) {
2686	pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
2687	}
2688	return;
2689	}
2690
2691	static void decomp_get_comprate(void)
2692	{
2693	u32 raw_ucomp_cnt;
2694	u32 fast_comp_cnt;
2695	u32 slow_comp_cnt;
2696	int comprate;
2697
2698	if (debug & AVS2_DBG_CACHE)
2699	pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
2700	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
2701	fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2702	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
2703	slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2704	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
2705	raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2706	if (debug & AVS2_DBG_CACHE) {
2707	pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
2708	pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
2709	pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
2710	}
2711
2712	if (raw_ucomp_cnt != 0) {
2713	comprate = ((fast_comp_cnt + slow_comp_cnt)
2714	/ raw_ucomp_cnt) * 100;
2715	if (debug & AVS2_DBG_CACHE)
2716	pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
2717	} else if (debug & AVS2_DBG_CACHE) {
2718	pr_info("DECOMP_COMP_RATIO : na\n");
2719	}
2720	return;
2721	}
2722	#endif
2723
2724	static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
2725	{
2726	uint32_t rdata32;
2727	uint32_t rdata32_2;
2728	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2729
2730	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc*/
2731
2732	if (avs2_dec->img.type == I_IMG) { /* I-PIC*/
2733	/* remove reset -- disables clock */
2734	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
2735	return;
2736	}
2737	/*
2738	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
2739	mcrcc_get_hitrate();
2740	decomp_get_hitrate();
2741	decomp_get_comprate();
2742	}
2743	*/
2744	if ((avs2_dec->img.type == B_IMG) ||
2745	(avs2_dec->img.type == F_IMG)) { /*B-PIC or F_PIC*/
2746	/*Programme canvas0 */
2747	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2748	(0 << 8) | (0 << 1) | 0);
2749	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2750	rdata32 = rdata32 & 0xffff;
2751	rdata32 = rdata32 | (rdata32 << 16);
2752	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
2753
2754	/*Programme canvas1 */
2755	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2756	(16 << 8) | (1 << 1) | 0);
2757	rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2758	rdata32_2 = rdata32_2 & 0xffff;
2759	rdata32_2 = rdata32_2 | (rdata32_2 << 16);
2760	if (rdata32 == rdata32_2) {
2761	rdata32_2 =
2762	READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2763	rdata32_2 = rdata32_2 & 0xffff;
2764	rdata32_2 = rdata32_2 | (rdata32_2 << 16);
2765	}
2766	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
2767	} else { /* P-PIC */
2768	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2769	(0 << 8) | (1 << 1) | 0);
2770	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2771	rdata32 = rdata32 & 0xffff;
2772	rdata32 = rdata32 | (rdata32 << 16);
2773	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
2774
2775	/*Programme canvas1*/
2776	rdata32 =
2777	READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2778	rdata32 = rdata32 & 0xffff;
2779	rdata32 = rdata32 | (rdata32 << 16);
2780	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
2781	}
2782	/*enable mcrcc progressive-mode */
2783	WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
2784	return;
2785	}
2786
2787	static void config_mpred_hw(struct AVS2Decoder_s *dec)
2788	{
2789	uint32_t data32;
2790	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2791	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2792	struct avs2_frame_s *col_pic = avs2_dec->fref[0];
2793	int32_t mpred_mv_rd_start_addr;
2794	int32_t mpred_curr_lcu_x;
2795	int32_t mpred_curr_lcu_y;
2796	int32_t mpred_mv_rd_end_addr;
2797	int32_t above_en;
2798	int32_t mv_wr_en;
2799	int32_t mv_rd_en;
2800	int32_t col_isIntra;
2801	int mv_mem_unit;
2802	if (avs2_dec->img.type != I_IMG) {
2803	above_en = 1;
2804	mv_wr_en = 1;
2805	mv_rd_en = 1;
2806	col_isIntra = 0;
2807	} else {
2808	above_en = 1;
2809	mv_wr_en = 1;
2810	mv_rd_en = 0;
2811	col_isIntra = 0;
2812	}
2813
2814	mpred_mv_rd_start_addr =
2815	col_pic->mpred_mv_wr_start_addr;
2816	data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
2817	mpred_curr_lcu_x = data32 & 0xffff;
2818	mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
2819
2820	mv_mem_unit = avs2_dec->lcu_size_log2 == 6 ?
2821	0x200 : (avs2_dec->lcu_size_log2 == 5 ?
2822	0x80 : 0x20);
2823
2824	mpred_mv_rd_end_addr =
2825	mpred_mv_rd_start_addr +
2826	((avs2_dec->lcu_x_num *
2827	avs2_dec->lcu_y_num) * mv_mem_unit);
2828
2829	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2830	"cur pic index %d col pic index %d\n",
2831	cur_pic->index, col_pic->index);
2832
2833
2834	WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
2835	cur_pic->mpred_mv_wr_start_addr);
2836	WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
2837	col_pic->mpred_mv_wr_start_addr);
2838	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2839	"[MPRED CO_MV] write 0x%x read 0x%x\n",
2840	cur_pic->mpred_mv_wr_start_addr,
2841	col_pic->mpred_mv_wr_start_addr);
2842
2843	data32 =
2844	((avs2_dec->bk_img_is_top_field) << 13) |
2845	((avs2_dec->hd.background_picture_enable & 1) << 12) |
2846	((avs2_dec->hd.curr_RPS.num_of_ref & 7) << 8) |
2847	((avs2_dec->hd.b_pmvr_enabled & 1) << 6) |
2848	((avs2_dec->img.is_top_field & 1) << 5) |
2849	((avs2_dec->img.is_field_sequence & 1) << 4) |
2850	((avs2_dec->img.typeb & 7) << 1) |
2851	(avs2_dec->hd.background_reference_enable & 0x1);
2852	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2853	"HEVC_MPRED_CTRL9 <= 0x%x(num of ref %d)\n",
2854	data32, avs2_dec->hd.curr_RPS.num_of_ref);
2855	WRITE_VREG(HEVC_MPRED_CTRL9, data32);
2856
2857	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2858	"%s: dis %d %d %d %d %d %d %d fref0_ref_poc %d %d %d %d %d %d %d\n",
2859	__func__,
2860	avs2_dec->fref[0]->imgtr_fwRefDistance,
2861	avs2_dec->fref[1]->imgtr_fwRefDistance,
2862	avs2_dec->fref[2]->imgtr_fwRefDistance,
2863	avs2_dec->fref[3]->imgtr_fwRefDistance,
2864	avs2_dec->fref[4]->imgtr_fwRefDistance,
2865	avs2_dec->fref[5]->imgtr_fwRefDistance,
2866	avs2_dec->fref[6]->imgtr_fwRefDistance,
2867	avs2_dec->fref[0]->ref_poc[0],
2868	avs2_dec->fref[0]->ref_poc[1],
2869	avs2_dec->fref[0]->ref_poc[2],
2870	avs2_dec->fref[0]->ref_poc[3],
2871	avs2_dec->fref[0]->ref_poc[4],
2872	avs2_dec->fref[0]->ref_poc[5],
2873	avs2_dec->fref[0]->ref_poc[6]
2874	);
2875	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2876	"pic_distance %d, imgtr_next_P %d\n",
2877	avs2_dec->img.pic_distance, avs2_dec->img.imgtr_next_P);
2878
2879
2880	WRITE_VREG(HEVC_MPRED_CUR_POC, avs2_dec->img.pic_distance);
2881	WRITE_VREG(HEVC_MPRED_COL_POC, avs2_dec->img.imgtr_next_P);
2882
2883	/*below MPRED Ref_POC_xx_Lx registers
2884	must follow Ref_POC_xx_L0 ->
2885	Ref_POC_xx_L1 in pair write order!!!*/
2886	WRITE_VREG(HEVC_MPRED_L0_REF00_POC,
2887	avs2_dec->fref[0]->imgtr_fwRefDistance);
2888	WRITE_VREG(HEVC_MPRED_L1_REF00_POC,
2889	avs2_dec->fref[0]->ref_poc[0]);
2890
2891	WRITE_VREG(HEVC_MPRED_L0_REF01_POC,
2892	avs2_dec->fref[1]->imgtr_fwRefDistance);
2893	WRITE_VREG(HEVC_MPRED_L1_REF01_POC,
2894	avs2_dec->fref[0]->ref_poc[1]);
2895
2896	WRITE_VREG(HEVC_MPRED_L0_REF02_POC,
2897	avs2_dec->fref[2]->imgtr_fwRefDistance);
2898	WRITE_VREG(HEVC_MPRED_L1_REF02_POC,
2899	avs2_dec->fref[0]->ref_poc[2]);
2900
2901	WRITE_VREG(HEVC_MPRED_L0_REF03_POC,
2902	avs2_dec->fref[3]->imgtr_fwRefDistance);
2903	WRITE_VREG(HEVC_MPRED_L1_REF03_POC,
2904	avs2_dec->fref[0]->ref_poc[3]);
2905
2906	WRITE_VREG(HEVC_MPRED_L0_REF04_POC,
2907	avs2_dec->fref[4]->imgtr_fwRefDistance);
2908	WRITE_VREG(HEVC_MPRED_L1_REF04_POC,
2909	avs2_dec->fref[0]->ref_poc[4]);
2910
2911	WRITE_VREG(HEVC_MPRED_L0_REF05_POC,
2912	avs2_dec->fref[5]->imgtr_fwRefDistance);
2913	WRITE_VREG(HEVC_MPRED_L1_REF05_POC,
2914	avs2_dec->fref[0]->ref_poc[5]);
2915
2916	WRITE_VREG(HEVC_MPRED_L0_REF06_POC,
2917	avs2_dec->fref[6]->imgtr_fwRefDistance);
2918	WRITE_VREG(HEVC_MPRED_L1_REF06_POC,
2919	avs2_dec->fref[0]->ref_poc[6]);
2920
2921
2922	WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
2923	mpred_mv_rd_end_addr);
2924	}
2925
2926	static void config_dblk_hw(struct AVS2Decoder_s *dec)
2927	{
2928	/*
2929	* Picture level de-block parameter configuration here
2930	*/
2931	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2932	union param_u *rpm_param = &avs2_dec->param;
2933	uint32_t data32;
2934
2935	data32 = READ_VREG(HEVC_DBLK_CFG1);
2936	data32 = (((data32 >> 20) & 0xfff) << 20) |
2937	(((avs2_dec->input.sample_bit_depth == 10)
2938	? 0xa : 0x0) << 16) | /*[16 +: 4]: {luma_bd[1:0],
2939	chroma_bd[1:0]}*/
2940	(((data32 >> 2) & 0x3fff) << 2) |
2941	(((rpm_param->p.lcu_size == 6)
2942	? 0 : (rpm_param->p.lcu_size == 5)
2943	? 1 : 2) << 0);/*[ 0 +: 2]: lcu_size*/
2944	WRITE_VREG(HEVC_DBLK_CFG1, data32);
2945
2946	data32 = (avs2_dec->img.height << 16) |
2947	avs2_dec->img.width;
2948	WRITE_VREG(HEVC_DBLK_CFG2, data32);
2949	/*
2950	[27 +: 1]: cross_slice_loopfilter_enable_flag
2951	[26 +: 1]: loop_filter_disable
2952	[25 +: 1]: useNSQT
2953	[22 +: 3]: imgtype
2954	[17 +: 5]: alpha_c_offset (-8~8)
2955	[12 +: 5]: beta_offset (-8~8)
2956	[ 6 +: 6]: chroma_quant_param_delta_u (-16~16)
2957	[ 0 +: 6]: chroma_quant_param_delta_v (-16~16)
2958	*/
2959	data32 = ((avs2_dec->input.crossSliceLoopFilter
2960	& 0x1) << 27) |
2961	((rpm_param->p.loop_filter_disable & 0x1) << 26) |
2962	((avs2_dec->input.useNSQT & 0x1) << 25) |
2963	((avs2_dec->img.type & 0x7) << 22) |
2964	((rpm_param->p.alpha_c_offset & 0x1f) << 17) |
2965	((rpm_param->p.beta_offset & 0x1f) << 12) |
2966	((rpm_param->p.chroma_quant_param_delta_cb & 0x3f) << 6) |
2967	((rpm_param->p.chroma_quant_param_delta_cr & 0x3f) << 0);
2968
2969	WRITE_VREG(HEVC_DBLK_CFG9, data32);
2970	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2971	"[c] cfgDBLK: crossslice(%d),lfdisable(%d),bitDepth(%d),lcuSize(%d),NSQT(%d)\n",
2972	avs2_dec->input.crossSliceLoopFilter,
2973	rpm_param->p.loop_filter_disable,
2974	avs2_dec->input.sample_bit_depth,
2975	avs2_dec->lcu_size,
2976	avs2_dec->input.useNSQT);
2977	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2978	"[c] cfgDBLK: alphaCOffset(%d),betaOffset(%d),quantDeltaCb(%d),quantDeltaCr(%d)\n",
2979	rpm_param->p.alpha_c_offset,
2980	rpm_param->p.beta_offset,
2981	rpm_param->p.chroma_quant_param_delta_cb,
2982	rpm_param->p.chroma_quant_param_delta_cr);
2983	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2984	"[c] cfgDBLK: .done.\n");
2985	}
2986
2987	static void config_sao_hw(struct AVS2Decoder_s *dec)
2988	{
2989	uint32_t data32;
2990	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2991	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2992
2993	int lcu_size = 64;
2994	int mc_buffer_size_u_v =
2995	cur_pic->lcu_total * lcu_size*lcu_size/2;
2996	int mc_buffer_size_u_v_h =
2997	(mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
2998
2999	data32 = READ_VREG(HEVC_SAO_CTRL0);
3000	data32 &= (~0xf);
3001	data32 |= avs2_dec->lcu_size_log2;
3002	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3003	"%s, lcu_size_log2 = %d, config HEVC_SAO_CTRL0 0x%x\n",
3004	__func__,
3005	avs2_dec->lcu_size_log2,
3006	data32);
3007
3008	WRITE_VREG(HEVC_SAO_CTRL0, data32);
3009
3010	#ifndef AVS2_10B_MMU
3011	if ((get_double_write_mode(dec) & 0x10) == 0)
3012	WRITE_VREG(HEVC_CM_BODY_START_ADDR, cur_pic->mc_y_adr);
3013	#endif
3014	if (get_double_write_mode(dec)) {
3015	WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr);
3016	WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr);
3017	WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr);
3018	WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr);
3019	} else {
3020	WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
3021	WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
3022	}
3023	#ifdef AVS2_10B_MMU
3024	WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr);
3025	#endif
3026	data32 = (mc_buffer_size_u_v_h << 16) << 1;
3027	/*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
3028	data32, mc_buffer_size_u_v_h, cur_pic->lcu_total);*/
3029	WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
3030
3031	data32 = (mc_buffer_size_u_v_h << 16);
3032	WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
3033
3034	#ifdef AVS2_10B_NV21
3035	#ifdef DOS_PROJECT
3036	data32 = READ_VREG(HEVC_SAO_CTRL1);
3037	data32 &= (~0x3000);
3038	/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
3039	data32 |= (MEM_MAP_MODE << 12);
3040	data32 &= (~0x3);
3041	data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
3042	WRITE_VREG(HEVC_SAO_CTRL1, data32);
3043	/*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
3044	[17:16] dw_h0_ctrl*/
3045	data32 = READ_VREG(HEVC_SAO_CTRL5);
3046	/*set them all 0 for H265_NV21 (no down-scale)*/
3047	data32 &= ~(0xff << 16);
3048	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3049	ata32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3050	data32 &= (~0x30);
3051	/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
3052	data32 |= (MEM_MAP_MODE << 4);
3053	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3054	#else
3055	/*m8baby test1902*/
3056	data32 = READ_VREG(HEVC_SAO_CTRL1);
3057	data32 &= (~0x3000);
3058	/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
3059	data32 |= (MEM_MAP_MODE << 12);
3060	data32 &= (~0xff0);
3061	/*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
3062	data32 |= 0x880; /*.Big-Endian per 64-bit */
3063	data32 &= (~0x3);
3064	data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
3065	WRITE_VREG(HEVC_SAO_CTRL1, data32);
3066	/* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
3067	[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl*/
3068	data32 = READ_VREG(HEVC_SAO_CTRL5);
3069	/* set them all 0 for H265_NV21 (no down-scale)*/
3070	data32 &= ~(0xff << 16);
3071	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3072
3073	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3074	data32 &= (~0x30);
3075	/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
3076	data32 |= (MEM_MAP_MODE << 4);
3077	data32 &= (~0xF);
3078	data32 |= 0x8; /*Big-Endian per 64-bit*/
3079	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3080	#endif
3081	#else
3082	data32 = READ_VREG(HEVC_SAO_CTRL1);
3083	data32 &= (~0x3000);
3084	data32 |= (MEM_MAP_MODE <<
3085	12); /* [13:12] axi_aformat, 0-Linear,
3086	1-32x32, 2-64x32 */
3087	data32 &= (~0xff0);
3088	/* data32 |= 0x670; // Big-Endian per 64-bit */
3089	data32 |= endian; /* Big-Endian per 64-bit */
3090	data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
3091	#if 0
3092	if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
3093	if (get_double_write_mode(dec) == 0)
3094	data32 |= 0x2; /*disable double write*/
3095	#ifndef AVS2_10B_MMU
3096	else
3097	if (get_double_write_mode(dec) & 0x10)
3098	data32 |= 0x1; /*disable cm*/
3099	#endif
3100	}
3101	#endif
3102	WRITE_VREG(HEVC_SAO_CTRL1, data32);
3103
3104	if (get_double_write_mode(dec) & 0x10) {
3105	/* [23:22] dw_v1_ctrl
3106	[21:20] dw_v0_ctrl
3107	[19:18] dw_h1_ctrl
3108	[17:16] dw_h0_ctrl
3109	*/
3110	data32 = READ_VREG(HEVC_SAO_CTRL5);
3111	/*set them all 0 for H265_NV21 (no down-scale)*/
3112	data32 &= ~(0xff << 16);
3113	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3114	} else {
3115	data32 = READ_VREG(HEVC_SAO_CTRL5);
3116	data32 &= (~(0xff << 16));
3117	if (get_double_write_mode(dec) == 2 ||
3118	get_double_write_mode(dec) == 3)
3119	data32 |= (0xff<<16);
3120	else if (get_double_write_mode(dec) == 4)
3121	data32 |= (0x33<<16);
3122	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3123	}
3124
3125	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3126	data32 &= (~0x30);
3127	/* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
3128	data32 |= (mem_map_mode <<
3129	4);
3130	data32 &= (~0xF);
3131	data32 |= 0xf; /* valid only when double write only */
3132	/*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
3133	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3134	#endif
3135	}
3136
3137	static void reconstructCoefficients(struct AVS2Decoder_s *dec,
3138	struct ALFParam_s *alfParam)
3139	{
3140	int32_t g, sum, i, coeffPred;
3141	for (g = 0; g < alfParam->filters_per_group; g++) {
3142	sum = 0;
3143	for (i = 0; i < alfParam->num_coeff - 1; i++) {
3144	sum += (2 * alfParam->coeffmulti[g][i]);
3145	dec->m_filterCoeffSym[g][i] =
3146	alfParam->coeffmulti[g][i];
3147	/*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n",
3148	g, i, dec->m_filterCoeffSym[g][i]);*/
3149	}
3150	coeffPred = (1 << ALF_NUM_BIT_SHIFT) - sum;
3151	dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]
3152	= coeffPred +
3153	alfParam->coeffmulti[g][alfParam->num_coeff - 1];
3154	/*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n",
3155	g, (alfParam->num_coeff - 1),
3156	dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]);*/
3157	}
3158	}
3159
3160	static void reconstructCoefInfo(struct AVS2Decoder_s *dec,
3161	int32_t compIdx, struct ALFParam_s *alfParam)
3162	{
3163	int32_t i;
3164	if (compIdx == ALF_Y) {
3165	if (alfParam->filters_per_group > 1) {
3166	for (i = 1; i < NO_VAR_BINS; ++i) {
3167	if (alfParam->filterPattern[i])
3168	dec->m_varIndTab[i] =
3169	dec->m_varIndTab[i - 1] + 1;
3170	else
3171	dec->m_varIndTab[i] =
3172	dec->m_varIndTab[i - 1];
3173	}
3174	}
3175	}
3176	reconstructCoefficients(dec, alfParam);
3177	}
3178
3179	static void config_alf_hw(struct AVS2Decoder_s *dec)
3180	{
3181	/*
3182	* Picture level ALF parameter configuration here
3183	*/
3184	uint32_t data32;
3185	int32_t i, j;
3186	int32_t m_filters_per_group;
3187	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3188	struct ALFParam_s *m_alfPictureParam_y =
3189	&avs2_dec->m_alfPictureParam[0];
3190	struct ALFParam_s *m_alfPictureParam_cb =
3191	&avs2_dec->m_alfPictureParam[1];
3192	struct ALFParam_s *m_alfPictureParam_cr =
3193	&avs2_dec->m_alfPictureParam[2];
3194
3195	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3196	"[t]alfy,cidx(%d),flag(%d),filters_per_group(%d),filterPattern[0]=0x%x,[15]=0x%x\n",
3197	m_alfPictureParam_y->componentID,
3198	m_alfPictureParam_y->alf_flag,
3199	m_alfPictureParam_y->filters_per_group,
3200	m_alfPictureParam_y->filterPattern[0],
3201	m_alfPictureParam_y->filterPattern[15]);
3202	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3203	"[t]alfy,num_coeff(%d),coeffmulti[0][0]=0x%x,[0][1]=0x%x,[1][0]=0x%x,[1][1]=0x%x\n",
3204	m_alfPictureParam_y->num_coeff,
3205	m_alfPictureParam_y->coeffmulti[0][0],
3206	m_alfPictureParam_y->coeffmulti[0][1],
3207	m_alfPictureParam_y->coeffmulti[1][0],
3208	m_alfPictureParam_y->coeffmulti[1][1]);
3209
3210	/*Cr*/
3211	for (i = 0; i < 16; i++)
3212	dec->m_varIndTab[i] = 0;
3213	for (j = 0; j < 16; j++)
3214	for (i = 0; i < 9; i++)
3215	dec->m_filterCoeffSym[j][i] = 0;
3216	reconstructCoefInfo(dec, 2, m_alfPictureParam_cr);
3217	data32 =
3218	((dec->m_filterCoeffSym[0][4] & 0xf) << 28) |
3219	((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) |
3220	((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) |
3221	((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) |
3222	((dec->m_filterCoeffSym[0][0] & 0x7f) << 0);
3223	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3224	data32 =
3225	((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) |
3226	((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) |
3227	((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) |
3228	((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) |
3229	(((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0);
3230	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3231	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3232	"[c] pic_alf_on_cr(%d), alf_cr_coef(%d %d %d %d %d %d %d %d %d)\n",
3233	m_alfPictureParam_cr->alf_flag,
3234	dec->m_filterCoeffSym[0][0],
3235	dec->m_filterCoeffSym[0][1],
3236	dec->m_filterCoeffSym[0][2],
3237	dec->m_filterCoeffSym[0][3],
3238	dec->m_filterCoeffSym[0][4],
3239	dec->m_filterCoeffSym[0][5],
3240	dec->m_filterCoeffSym[0][6],
3241	dec->m_filterCoeffSym[0][7],
3242	dec->m_filterCoeffSym[0][8]);
3243
3244	/* Cb*/
3245	for (j = 0; j < 16; j++)
3246	for (i = 0; i < 9; i++)
3247	dec->m_filterCoeffSym[j][i] = 0;
3248	reconstructCoefInfo(dec, 1, m_alfPictureParam_cb);
3249	data32 =
3250	((dec->m_filterCoeffSym[0][4] & 0xf) << 28) |
3251	((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) |
3252	((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) |
3253	((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) |
3254	((dec->m_filterCoeffSym[0][0] & 0x7f) << 0);
3255	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3256	data32 =
3257	((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) |
3258	((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) |
3259	((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) |
3260	((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) |
3261	(((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0);
3262	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3263	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3264	"[c] pic_alf_on_cb(%d), alf_cb_coef(%d %d %d %d %d %d %d %d %d)\n",
3265	m_alfPictureParam_cb->alf_flag,
3266	dec->m_filterCoeffSym[0][0],
3267	dec->m_filterCoeffSym[0][1],
3268	dec->m_filterCoeffSym[0][2],
3269	dec->m_filterCoeffSym[0][3],
3270	dec->m_filterCoeffSym[0][4],
3271	dec->m_filterCoeffSym[0][5],
3272	dec->m_filterCoeffSym[0][6],
3273	dec->m_filterCoeffSym[0][7],
3274	dec->m_filterCoeffSym[0][8]);
3275
3276	/* Y*/
3277	for (j = 0; j < 16; j++)
3278	for (i = 0; i < 9; i++)
3279	dec->m_filterCoeffSym[j][i] = 0;
3280	reconstructCoefInfo(dec, 0, m_alfPictureParam_y);
3281	data32 =
3282	((dec->m_varIndTab[7] & 0xf) << 28) |
3283	((dec->m_varIndTab[6] & 0xf) << 24) |
3284	((dec->m_varIndTab[5] & 0xf) << 20) |
3285	((dec->m_varIndTab[4] & 0xf) << 16) |
3286	((dec->m_varIndTab[3] & 0xf) << 12) |
3287	((dec->m_varIndTab[2] & 0xf) << 8) |
3288	((dec->m_varIndTab[1] & 0xf) << 4) |
3289	((dec->m_varIndTab[0] & 0xf) << 0);
3290	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3291	data32 = ((dec->m_varIndTab[15] & 0xf) << 28) |
3292	((dec->m_varIndTab[14] & 0xf) << 24) |
3293	((dec->m_varIndTab[13] & 0xf) << 20) |
3294	((dec->m_varIndTab[12] & 0xf) << 16) |
3295	((dec->m_varIndTab[11] & 0xf) << 12) |
3296	((dec->m_varIndTab[10] & 0xf) << 8) |
3297	((dec->m_varIndTab[9] & 0xf) << 4) |
3298	((dec->m_varIndTab[8] & 0xf) << 0);
3299	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3300	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3301	"[c] pic_alf_on_y(%d), alf_y_tab(%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d)\n",
3302	m_alfPictureParam_y->alf_flag,
3303	dec->m_varIndTab[0],
3304	dec->m_varIndTab[1],
3305	dec->m_varIndTab[2],
3306	dec->m_varIndTab[3],
3307	dec->m_varIndTab[4],
3308	dec->m_varIndTab[5],
3309	dec->m_varIndTab[6],
3310	dec->m_varIndTab[7],
3311	dec->m_varIndTab[8],
3312	dec->m_varIndTab[9],
3313	dec->m_varIndTab[10],
3314	dec->m_varIndTab[11],
3315	dec->m_varIndTab[12],
3316	dec->m_varIndTab[13],
3317	dec->m_varIndTab[14],
3318	dec->m_varIndTab[15]);
3319
3320	m_filters_per_group =
3321	(m_alfPictureParam_y->alf_flag == 0) ?
3322	1 : m_alfPictureParam_y->filters_per_group;
3323	for (i = 0; i < m_filters_per_group; i++) {
3324	data32 =
3325	((dec->m_filterCoeffSym[i][4] & 0xf) << 28) |
3326	((dec->m_filterCoeffSym[i][3] & 0x7f) << 21) |
3327	((dec->m_filterCoeffSym[i][2] & 0x7f) << 14) |
3328	((dec->m_filterCoeffSym[i][1] & 0x7f) << 7) |
3329	((dec->m_filterCoeffSym[i][0] & 0x7f) << 0);
3330	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3331	data32 =
3332	/*[31] last indication*/
3333	((i == m_filters_per_group-1) << 31) |
3334	((dec->m_filterCoeffSym[i][8] & 0x7f) << 24) |
3335	((dec->m_filterCoeffSym[i][7] & 0x7f) << 17) |
3336	((dec->m_filterCoeffSym[i][6] & 0x7f) << 10) |
3337	((dec->m_filterCoeffSym[i][5] & 0x7f) << 3) |
3338	(((dec->m_filterCoeffSym[i][4] >> 4) & 0x7) << 0);
3339	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3340	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3341	"[c] alf_y_coef[%d](%d %d %d %d %d %d %d %d %d)\n",
3342	i, dec->m_filterCoeffSym[i][0],
3343	dec->m_filterCoeffSym[i][1],
3344	dec->m_filterCoeffSym[i][2],
3345	dec->m_filterCoeffSym[i][3],
3346	dec->m_filterCoeffSym[i][4],
3347	dec->m_filterCoeffSym[i][5],
3348	dec->m_filterCoeffSym[i][6],
3349	dec->m_filterCoeffSym[i][7],
3350	dec->m_filterCoeffSym[i][8]);
3351	}
3352	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3353	"[c] cfgALF .done.\n");
3354	}
3355
3356	static void config_other_hw(struct AVS2Decoder_s *dec)
3357	{
3358	uint32_t data32;
3359	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3360	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
3361	int bit_depth = cur_pic->bit_depth;
3362	int losless_comp_header_size =
3363	compute_losless_comp_header_size(
3364	dec, cur_pic->pic_w,
3365	cur_pic->pic_h);
3366	int losless_comp_body_size =
3367	compute_losless_comp_body_size(
3368	dec, cur_pic->pic_w,
3369	cur_pic->pic_h, (bit_depth == AVS2_BITS_10));
3370	cur_pic->comp_body_size = losless_comp_body_size;
3371
3372	#ifdef LOSLESS_COMPRESS_MODE
3373	data32 = READ_VREG(HEVC_SAO_CTRL5);
3374	if (bit_depth == AVS2_BITS_10)
3375	data32 &= ~(1 << 9);
3376	else
3377	data32 |= (1 << 9);
3378
3379	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3380
3381	#ifdef AVS2_10B_MMU
3382	/*bit[4] : paged_mem_mode*/
3383	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3384	#else
3385	/*bit[3] smem mdoe*/
3386	if (bit_depth == AVS2_BITS_10)
3387	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
3388	else
3389	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
3390	#endif
3391	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3392	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
3393	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3394	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3395	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3396	#else
3397	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3398	#endif
3399	}
3400
3401	static void avs2_config_work_space_hw(struct AVS2Decoder_s *dec)
3402	{
3403	struct BuffInfo_s *buf_spec = dec->work_space_buf;
3404	#ifdef LOSLESS_COMPRESS_MODE
3405	int losless_comp_header_size =
3406	compute_losless_comp_header_size(
3407	dec, dec->init_pic_w,
3408	dec->init_pic_h);
3409	int losless_comp_body_size =
3410	compute_losless_comp_body_size(dec,
3411	dec->init_pic_w,
3412	dec->init_pic_h, buf_alloc_depth == 10);
3413	#endif
3414	#ifdef AVS2_10B_MMU
3415	unsigned int data32;
3416	#endif
3417	if (debug && dec->init_flag == 0)
3418	avs2_print(dec, 0,
3419	"%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
3420	__func__,
3421	buf_spec->ipp.buf_start,
3422	buf_spec->start_adr,
3423	buf_spec->short_term_rps.buf_start,
3424	buf_spec->rcs.buf_start,
3425	buf_spec->sps.buf_start,
3426	buf_spec->pps.buf_start,
3427	buf_spec->sao_up.buf_start,
3428	buf_spec->swap_buf.buf_start,
3429	buf_spec->swap_buf2.buf_start,
3430	buf_spec->scalelut.buf_start,
3431	buf_spec->dblk_para.buf_start,
3432	buf_spec->dblk_data.buf_start,
3433	buf_spec->dblk_data2.buf_start);
3434	WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start);
3435	if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0)
3436	WRITE_VREG(HEVC_RPM_BUFFER, (u32)dec->rpm_phy_addr);
3437	WRITE_VREG(AVS2_ALF_SWAP_BUFFER, buf_spec->short_term_rps.buf_start);
3438	WRITE_VREG(HEVC_RCS_BUFFER, buf_spec->rcs.buf_start);
3439	WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);
3440	WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
3441	WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
3442	#ifdef AVS2_10B_MMU
3443	WRITE_VREG(AVS2_MMU_MAP_BUFFER, dec->frame_mmu_map_phy_addr);
3444	#else
3445	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, buf_spec->swap_buf.buf_start);
3446	#endif
3447	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start);
3448	WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
3449
3450	/* cfg_p_addr */
3451	WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
3452	/* cfg_d_addr */
3453	WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
3454
3455	WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start);
3456
3457	#ifdef LOSLESS_COMPRESS_MODE
3458	data32 = READ_VREG(HEVC_SAO_CTRL5);
3459	#if 1
3460	data32 &= ~(1<<9);
3461	#else
3462	if (params->p.bit_depth != 0x00)
3463	data32 &= ~(1<<9);
3464	else
3465	data32 |= (1<<9);
3466	#endif
3467	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3468	#ifdef AVS2_10B_MMU
3469	/*bit[4] : paged_mem_mode*/
3470	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3471	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
3472	#else
3473	/* bit[3] smem mode*/
3474	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3));
3475
3476	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3477	#endif
3478	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,(losless_comp_body_size >> 5));*/
3479	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
3480	/*8-bit mode */
3481	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3482	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3483	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3484	#else
3485	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3486	#endif
3487
3488	#ifdef AVS2_10B_MMU
3489	WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
3490	WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
3491	+ buf_spec->mmu_vbh.buf_size/2);
3492	/*data32 = READ_VREG(HEVC_SAO_CTRL9);*/
3493	/*data32 |= 0x1;*/
3494	/*WRITE_VREG(HEVC_SAO_CTRL9, data32);*/
3495
3496	/* use HEVC_CM_HEADER_START_ADDR */
3497	data32 = READ_VREG(HEVC_SAO_CTRL5);
3498	data32 |= (1<<10);
3499	#if 1
3500	if (debug & AVS2_DBG_FORCE_UNCOMPRESS)
3501	data32 |= 0x80;
3502	#endif
3503	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3504
3505	#endif
3506
3507	WRITE_VREG(LMEM_DUMP_ADR, (u32)dec->lmem_phy_addr);
3508	#if 1
3509	/*MULTI_INSTANCE_SUPPORT*/
3510	/*new added in simulation???*/
3511	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, buf_spec->mpred_above.buf_start);
3512	#endif
3513	}
3514
3515	static void decomp_perfcount_reset(void)
3516	{
3517	if (debug & AVS2_DBG_CACHE)
3518	pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3519	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3520	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3521	return;
3522	}
3523
3524	static void mcrcc_perfcount_reset(void)
3525	{
3526	if (debug & AVS2_DBG_CACHE)
3527	pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3528	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3529	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3530	return;
3531	}
3532
3533	static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec)
3534	{
3535	unsigned int data32;
3536	unsigned int decode_mode;
3537	int i;
3538
3539	/*if (debug & AVS2_DBG_BUFMGR_MORE)
3540	pr_info("%s\n", __func__);*/
3541	data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
3542	#if 1
3543	/* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
3544	data32 &= ~(7 << 29);
3545	data32 |= (3 << 29);
3546	#endif
3547	data32 = data32 |
3548	(1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
3549	(1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
3550	(1 << 7) |/*dec_done_int_cpu_enable*/
3551	(1 << 4) |/*startcode_found_int_cpu_enable*/
3552	(0 << 3) |/*startcode_found_int_amrisc_enable*/
3553	(1 << 0) /*parser_int_enable*/
3554	;
3555	WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
3556
3557	data32 = READ_VREG(HEVC_SHIFT_STATUS);
3558	data32 = data32 |
3559	(0 << 1) |/*emulation_check_off VP9
3560	do not have emulation*/
3561	(1 << 0)/*startcode_check_on*/
3562	;
3563	WRITE_VREG(HEVC_SHIFT_STATUS, data32);
3564	WRITE_VREG(HEVC_SHIFT_CONTROL,
3565	(6 << 20) | /* emu_push_bits (6-bits for AVS2)*/
3566	(0 << 19) | /* emu_3_enable, maybe turned on in microcode*/
3567	(0 << 18) | /* emu_2_enable, maybe turned on in microcode*/
3568	(0 << 17) | /* emu_1_enable, maybe turned on in microcode*/
3569	(0 << 16) | /* emu_0_enable, maybe turned on in microcode*/
3570	(0 << 14) | /*disable_start_code_protect*/
3571	(3 << 6) | /* sft_valid_wr_position*/
3572	(2 << 4) | /* emulate_code_length_sub_1*/
3573	(2 << 1) | /* start_code_length_sub_1*/
3574	(1 << 0) /* stream_shift_enable*/
3575	);
3576
3577	WRITE_VREG(HEVC_SHIFT_LENGTH_PROTECT,
3578	(0 << 30) | /*data_protect_fill_00_enable*/
3579	(1 << 29) /*data_protect_fill_ff_enable*/
3580	);
3581	WRITE_VREG(HEVC_CABAC_CONTROL,
3582	(1 << 0)/*cabac_enable*/
3583	);
3584
3585	WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
3586	(1 << 0)/* hevc_parser_core_clk_en*/
3587	);
3588
3589
3590	WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
3591
3592	/*Initial IQIT_SCALELUT memory -- just to avoid X in simulation*/
3593
3594	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
3595	for (i = 0; i < 1024; i++)
3596	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
3597
3598
3599	#ifdef ENABLE_SWAP_TEST
3600	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
3601	#else
3602	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
3603	#endif
3604	if (!dec->m_ins_flag)
3605	decode_mode = DECODE_MODE_SINGLE;
3606	else if (vdec_frame_based(hw_to_vdec(dec)))
3607	decode_mode = DECODE_MODE_MULTI_FRAMEBASE;
3608	else
3609	decode_mode = DECODE_MODE_MULTI_STREAMBASE;
3610	if (dec->avs2_dec.bufmgr_error_flag &&
3611	(error_handle_policy & 0x1)) {
3612	dec->bufmgr_error_count++;
3613	dec->avs2_dec.bufmgr_error_flag = 0;
3614	if (dec->bufmgr_error_count >
3615	(re_search_seq_threshold & 0xff)
3616	&& dec->frame_count >
3617	((re_search_seq_threshold >> 8) & 0xff)) {
3618	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3619	dec->start_decoding_flag = 0;
3620	avs2_dec->hd.vec_flag = 1;
3621	dec->skip_PB_before_I = 1;
3622	avs2_print(dec, 0,
3623	"!!Bufmgr error, search seq again (0x%x %d %d)\n",
3624	error_handle_policy,
3625	dec->frame_count,
3626	dec->bufmgr_error_count);
3627	dec->bufmgr_error_count = 0;
3628	}
3629	}
3630	decode_mode |= (dec->start_decoding_flag << 16);
3631
3632	WRITE_VREG(DECODE_MODE, decode_mode);
3633	WRITE_VREG(HEVC_DECODE_SIZE, 0);
3634	WRITE_VREG(HEVC_DECODE_COUNT, 0);
3635
3636	/*Send parser_cmd*/
3637	WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
3638	for (i = 0; i < PARSER_CMD_NUMBER; i++)
3639	WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
3640	WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
3641	WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
3642	WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
3643
3644
3645	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
3646	(1 << 9) | /* parser_alf_if_en*/
3647	/* (1 << 8) |*/ /*sao_sw_pred_enable*/
3648	(1 << 5) | /*parser_sao_if_en*/
3649	(1 << 2) | /*parser_mpred_if_en*/
3650	(1 << 0) /*parser_scaler_if_en*/
3651	);
3652
3653	#ifdef MULTI_INSTANCE_SUPPORT
3654	WRITE_VREG(HEVC_MPRED_INT_STATUS, (1<<31));
3655
3656	WRITE_VREG(HEVC_PARSER_RESULT_3, 0xffffffff);
3657
3658	for (i = 0; i < 8; i++)
3659	data32 = READ_VREG(HEVC_MPRED_ABV_START_ADDR);
3660
3661	WRITE_VREG(DOS_SW_RESET3, (1<<18)); /* reset mpred */
3662	WRITE_VREG(DOS_SW_RESET3, 0);
3663	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3664	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3665	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3666	#endif
3667	/*End of Multi-instance*/
3668	/*Changed to Start MPRED in microcode*/
3669	/*
3670	pr_info("[test.c] Start MPRED\n");
3671	WRITE_VREG(HEVC_MPRED_INT_STATUS,
3672	(1<<31)
3673	);
3674	*/
3675
3676	/*AVS2 default seq_wq_matrix config*/
3677
3678	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
3679	"Config AVS2 default seq_wq_matrix ...\n");
3680	/*4x4*/
3681	/* default seq_wq_matrix_4x4 begin address*/
3682	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 64);
3683	for (i = 0; i < 16; i++)
3684	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault4x4[i]);
3685
3686	/*8x8*/
3687	/*default seq_wq_matrix_8x8 begin address*/
3688	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);
3689	for (i = 0; i < 64; i++)
3690	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault8x8[i]);
3691
3692
3693	WRITE_VREG(HEVCD_IPP_TOP_CNTL,
3694	(0 << 1) | /*enable ipp*/
3695	(1 << 0) /*software reset ipp and mpp*/
3696	);
3697	WRITE_VREG(HEVCD_IPP_TOP_CNTL,
3698	(1 << 1) | /*enable ipp*/
3699	(0 << 0) /*software reset ipp and mpp*/
3700	);
3701	#if 0
3702	/*AVS2_10B_NV21*/
3703	/*Enable NV21 reference read mode for MC*/
3704	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3705	#endif
3706	/* Init dblk*/
3707	data32 = READ_VREG(HEVC_DBLK_CFGB);
3708	data32 |= (2 << 0);
3709	/* [3:0] cfg_video_type -> AVS2*/
3710
3711	data32 &= (~0x300); /*[8]:first write enable (compress)
3712	[9]:double write enable (uncompress)*/
3713	if (get_double_write_mode(dec) == 0)
3714	data32 |= (0x1 << 8); /*enable first write*/
3715	else if (get_double_write_mode(dec) == 0x10)
3716	data32 |= (0x1 << 9); /*double write only*/
3717	else
3718	data32 |= ((0x1 << 8) | (0x1 << 9));
3719	WRITE_VREG(HEVC_DBLK_CFGB, data32);
3720
3721	WRITE_VREG(HEVC_DBLK_CFG0, (1 << 0)); /* [0] rst_sync*/
3722	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
3723	"Bitstream level Init for DBLK .Done.\n");
3724
3725	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
3726	mcrcc_perfcount_reset();
3727	decomp_perfcount_reset();
3728	}
3729
3730	return;
3731	}
3732
3733
3734	#ifdef CONFIG_HEVC_CLK_FORCED_ON
3735	static void config_avs2_clk_forced_on(void)
3736	{
3737	unsigned int rdata32;
3738	/*IQIT*/
3739	rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
3740	WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
3741
3742	/* DBLK*/
3743	rdata32 = READ_VREG(HEVC_DBLK_CFG0);
3744	WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
3745
3746	/* SAO*/
3747	rdata32 = READ_VREG(HEVC_SAO_CTRL1);
3748	WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
3749
3750	/*MPRED*/
3751	rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
3752	WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
3753
3754	/* PARSER*/
3755	rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
3756	WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
3757	rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
3758	WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
3759	rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
3760	WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
3761	rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
3762	WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
3763	rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
3764	WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
3765	rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
3766	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
3767	rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
3768
3769	/*IPP*/
3770	rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
3771	WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
3772
3773	/* MCRCC*/
3774	rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
3775	WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
3776	}
3777	#endif
3778
3779
3780
3781
3782
3783	static struct AVS2Decoder_s gAVS2Decoder;
3784
3785	static void avs2_local_uninit(struct AVS2Decoder_s *dec)
3786	{
3787	dec->rpm_ptr = NULL;
3788	dec->lmem_ptr = NULL;
3789	if (dec->rpm_addr) {
3790	dma_free_coherent(amports_get_dma_device(),
3791	RPM_BUF_SIZE, dec->rpm_addr,
3792	dec->rpm_phy_addr);
3793	dec->rpm_addr = NULL;
3794	}
3795	if (dec->lmem_addr) {
3796	if (dec->lmem_phy_addr)
3797	dma_free_coherent(amports_get_dma_device(),
3798	LMEM_BUF_SIZE, dec->lmem_addr,
3799	dec->lmem_phy_addr);
3800	dec->lmem_addr = NULL;
3801	}
3802
3803	#ifdef AVS2_10B_MMU
3804	if (dec->frame_mmu_map_addr) {
3805	if (dec->frame_mmu_map_phy_addr)
3806	dma_free_coherent(amports_get_dma_device(),
3807	get_frame_mmu_map_size(dec), dec->frame_mmu_map_addr,
3808	dec->frame_mmu_map_phy_addr);
3809	dec->frame_mmu_map_addr = NULL;
3810	}
3811	#endif
3812	if (dec->gvs)
3813	vfree(dec->gvs);
3814	dec->gvs = NULL;
3815	}
3816
3817	static int avs2_local_init(struct AVS2Decoder_s *dec)
3818	{
3819	int ret = -1;
3820	/*int losless_comp_header_size, losless_comp_body_size;*/
3821
3822	struct BuffInfo_s *cur_buf_info = NULL;
3823
3824	cur_buf_info = &dec->work_space_buf_store;
3825
3826	if (vdec_is_support_4k()) {
3827	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
3828	memcpy(cur_buf_info, &amvavs2_workbuff_spec[2], /* 8k */
3829	sizeof(struct BuffInfo_s));
3830	else
3831	memcpy(cur_buf_info, &amvavs2_workbuff_spec[1], /* 4k */
3832	sizeof(struct BuffInfo_s));
3833	} else
3834	memcpy(cur_buf_info, &amvavs2_workbuff_spec[0],/* 1080p */
3835	sizeof(struct BuffInfo_s));
3836
3837	cur_buf_info->start_adr = dec->buf_start;
3838	#ifndef AVS2_10B_MMU
3839	dec->mc_buf_spec.buf_end = dec->buf_start + dec->buf_size;
3840	#endif
3841
3842	init_buff_spec(dec, cur_buf_info);
3843
3844	init_avs2_decoder(&dec->avs2_dec);
3845
3846	#ifdef AVS2_10B_MMU
3847	avs2_bufmgr_init(dec, cur_buf_info, NULL);
3848	#else
3849	dec->mc_buf_spec.buf_start = (cur_buf_info->end_adr + 0xffff)
3850	& (~0xffff);
3851	dec->mc_buf_spec.buf_size = (dec->mc_buf_spec.buf_end
3852	- dec->mc_buf_spec.buf_start);
3853	if (debug) {
3854	pr_err("dec->mc_buf_spec.buf_start %x-%x\n",
3855	dec->mc_buf_spec.buf_start,
3856	dec->mc_buf_spec.buf_start +
3857	dec->mc_buf_spec.buf_size);
3858	}
3859	avs2_bufmgr_init(dec, cur_buf_info, &dec->mc_buf_spec);
3860	#endif
3861
3862	if (!vdec_is_support_4k()
3863	&& (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
3864	buf_alloc_width = 1920;
3865	buf_alloc_height = 1088;
3866	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
3867	buf_alloc_width = 8192;
3868	buf_alloc_height = 4608;
3869	}
3870	dec->init_pic_w = buf_alloc_width ? buf_alloc_width :
3871	(dec->vavs2_amstream_dec_info.width ?
3872	dec->vavs2_amstream_dec_info.width :
3873	dec->work_space_buf->max_width);
3874	dec->init_pic_h = buf_alloc_height ? buf_alloc_height :
3875	(dec->vavs2_amstream_dec_info.height ?
3876	dec->vavs2_amstream_dec_info.height :
3877	dec->work_space_buf->max_height);
3878	#if 0
3879	/*ndef MV_USE_FIXED_BUF*/
3880	if (init_mv_buf_list(dec) < 0) {
3881	pr_err("%s: init_mv_buf_list fail\n", __func__);
3882	return -1;
3883	}
3884	#endif
3885
3886	#ifndef AVS2_10B_MMU
3887	init_buf_list(dec);
3888	#else
3889	dec->used_buf_num = max_buf_num + dec->dynamic_buf_margin;
3890	if (dec->used_buf_num > MAX_BUF_NUM)
3891	dec->used_buf_num = MAX_BUF_NUM;
3892	if (dec->used_buf_num > FRAME_BUFFERS)
3893	dec->used_buf_num = FRAME_BUFFERS;
3894	#endif
3895	dec->avs2_dec.ref_maxbuffer = dec->used_buf_num - 1;
3896	/*init_pic_list(dec);*/
3897
3898	pts_unstable = ((unsigned long)(dec->vavs2_amstream_dec_info.param)
3899	& 0x40) >> 6;
3900
3901	if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) {
3902	dec->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
3903	RPM_BUF_SIZE,
3904	&dec->rpm_phy_addr, GFP_KERNEL);
3905	if (dec->rpm_addr == NULL) {
3906	pr_err("%s: failed to alloc rpm buffer\n", __func__);
3907	return -1;
3908	}
3909	avs2_print(dec, AVS2_DBG_BUFMGR,
3910	"rpm_phy_addr %x\n", (u32) dec->rpm_phy_addr);
3911	dec->rpm_ptr = dec->rpm_addr;
3912	}
3913
3914	dec->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
3915	LMEM_BUF_SIZE,
3916	&dec->lmem_phy_addr, GFP_KERNEL);
3917	if (dec->lmem_addr == NULL) {
3918	pr_err("%s: failed to alloc lmem buffer\n", __func__);
3919	return -1;
3920	} else
3921	avs2_print(dec, AVS2_DBG_BUFMGR,
3922	"%s, lmem_phy_addr %x\n",
3923	__func__, (u32)dec->lmem_phy_addr);
3924
3925	dec->lmem_ptr = dec->lmem_addr;
3926
3927
3928	#ifdef AVS2_10B_MMU
3929	dec->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(),
3930	get_frame_mmu_map_size(dec),
3931	&dec->frame_mmu_map_phy_addr, GFP_KERNEL);
3932	if (dec->frame_mmu_map_addr == NULL) {
3933	pr_err("%s: failed to alloc count_buffer\n", __func__);
3934	return -1;
3935	}
3936	memset(dec->frame_mmu_map_addr, 0, get_frame_mmu_map_size(dec));
3937	#endif
3938
3939	ret = 0;
3940	return ret;
3941	}
3942
3943	/********************************************
3944	* Mailbox command
3945	********************************************/
3946	#define CMD_FINISHED 0
3947	#define CMD_ALLOC_VIEW 1
3948	#define CMD_FRAME_DISPLAY 3
3949	#define CMD_DEBUG 10
3950
3951
3952	#define DECODE_BUFFER_NUM_MAX 32
3953	#define DISPLAY_BUFFER_NUM 6
3954
3955	#define video_domain_addr(adr) (adr&0x7fffffff)
3956	#define DECODER_WORK_SPACE_SIZE 0x800000
3957
3958	#define spec2canvas(x) \
3959	(((x)->uv_canvas_index << 16) | \
3960	((x)->uv_canvas_index << 8) | \
3961	((x)->y_canvas_index << 0))
3962
3963
3964	static void set_canvas(struct AVS2Decoder_s *dec,
3965	struct avs2_frame_s *pic)
3966	{
3967	int canvas_w = ALIGN(pic->pic_w, 64)/4;
3968	int canvas_h = ALIGN(pic->pic_h, 32)/4;
3969	int blkmode = mem_map_mode;
3970	struct vdec_s *vdec = hw_to_vdec(dec);
3971	/*CANVAS_BLKMODE_64X32*/
3972	if (pic->double_write_mode) {
3973	canvas_w = pic->pic_w /
3974	get_double_write_ratio(dec,
3975	pic->double_write_mode);
3976	canvas_h = pic->pic_h /
3977	get_double_write_ratio(dec,
3978	pic->double_write_mode);
3979
3980	if (mem_map_mode == 0)
3981	canvas_w = ALIGN(canvas_w, 32);
3982	else
3983	canvas_w = ALIGN(canvas_w, 64);
3984	canvas_h = ALIGN(canvas_h, 32);
3985
3986	if (vdec->parallel_dec == 1) {
3987	if (pic->y_canvas_index == -1)
3988	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
3989	if (pic->uv_canvas_index == -1)
3990	pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
3991	} else {
3992	pic->y_canvas_index = 128 + pic->index * 2;
3993	pic->uv_canvas_index = 128 + pic->index * 2 + 1;
3994	}
3995
3996	canvas_config_ex(pic->y_canvas_index,
3997	pic->dw_y_adr, canvas_w, canvas_h,
3998	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
3999	canvas_config_ex(pic->uv_canvas_index,
4000	pic->dw_u_v_adr, canvas_w, canvas_h,
4001	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4002	#ifdef MULTI_INSTANCE_SUPPORT
4003	pic->canvas_config[0].phy_addr =
4004	pic->dw_y_adr;
4005	pic->canvas_config[0].width =
4006	canvas_w;
4007	pic->canvas_config[0].height =
4008	canvas_h;
4009	pic->canvas_config[0].block_mode =
4010	blkmode;
4011	pic->canvas_config[0].endian = 7;
4012
4013	pic->canvas_config[1].phy_addr =
4014	pic->dw_u_v_adr;
4015	pic->canvas_config[1].width =
4016	canvas_w;
4017	pic->canvas_config[1].height =
4018	canvas_h;
4019	pic->canvas_config[1].block_mode =
4020	blkmode;
4021	pic->canvas_config[1].endian = 7;
4022	#endif
4023	} else {
4024	#ifndef AVS2_10B_MMU
4025	if (vdec->parallel_dec == 1) {
4026	if (pic->y_canvas_index == -1)
4027	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
4028	if (pic->uv_canvas_index == -1)
4029	pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
4030	} else {
4031	pic->y_canvas_index = 128 + pic->index;
4032	pic->uv_canvas_index = 128 + pic->index;
4033	}
4034
4035	canvas_config_ex(pic->y_canvas_index,
4036	pic->mc_y_adr, canvas_w, canvas_h,
4037	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4038	canvas_config_ex(pic->uv_canvas_index,
4039	pic->mc_u_v_adr, canvas_w, canvas_h,
4040	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4041	#endif
4042	}
4043	}
4044
4045	static void set_frame_info(struct AVS2Decoder_s *dec, struct vframe_s *vf)
4046	{
4047	unsigned int ar;
4048
4049	vf->duration = dec->frame_dur;
4050	vf->duration_pulldown = 0;
4051	vf->flag = 0;
4052	vf->prop.master_display_colour = dec->vf_dp;
4053	vf->signal_type = dec->video_signal_type;
4054
4055	ar = min_t(u32, dec->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
4056	vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
4057
4058	return;
4059	}
4060
4061	static int vavs2_vf_states(struct vframe_states *states, void *op_arg)
4062	{
4063	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4064
4065	states->vf_pool_size = VF_POOL_SIZE;
4066	states->buf_free_num = kfifo_len(&dec->newframe_q);
4067	states->buf_avail_num = kfifo_len(&dec->display_q);
4068
4069	if (step == 2)
4070	states->buf_avail_num = 0;
4071	return 0;
4072	}
4073
4074	static struct vframe_s *vavs2_vf_peek(void *op_arg)
4075	{
4076	struct vframe_s *vf;
4077	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4078	if (step == 2)
4079	return NULL;
4080
4081	if (force_disp_pic_index & 0x100) {
4082	if (force_disp_pic_index & 0x200)
4083	return NULL;
4084	return &dec->vframe_dummy;
4085	}
4086
4087	if (kfifo_peek(&dec->display_q, &vf))
4088	return vf;
4089
4090	return NULL;
4091	}
4092
4093	static struct avs2_frame_s *get_pic_by_index(
4094	struct AVS2Decoder_s *dec, int index)
4095	{
4096	int i;
4097	struct avs2_frame_s *pic = NULL;
4098	if (index == (dec->used_buf_num - 1))
4099	pic = dec->avs2_dec.m_bg;
4100	else if (index >= 0 && index < dec->used_buf_num) {
4101	for (i = 0; i < dec->used_buf_num; i++) {
4102	if (dec->avs2_dec.fref[i]->index == index)
4103	pic = dec->avs2_dec.fref[i];
4104	}
4105	}
4106	return pic;
4107	}
4108
4109	static struct vframe_s *vavs2_vf_get(void *op_arg)
4110	{
4111	struct vframe_s *vf;
4112	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4113	if (step == 2)
4114	return NULL;
4115	else if (step == 1)
4116	step = 2;
4117
4118	if (force_disp_pic_index & 0x100) {
4119	int idx = force_disp_pic_index & 0xff;
4120	struct avs2_frame_s *pic = NULL;
4121	if (idx >= 0
4122	&& idx < dec->avs2_dec.ref_maxbuffer)
4123	pic = get_pic_by_index(dec, idx);
4124	if (pic == NULL)
4125	return NULL;
4126	if (force_disp_pic_index & 0x200)
4127	return NULL;
4128
4129	vf = &dec->vframe_dummy;
4130
4131	set_vframe(dec, vf, pic, 1);
4132
4133	force_disp_pic_index |= 0x200;
4134	return vf;
4135	}
4136
4137	if (kfifo_get(&dec->display_q, &vf)) {
4138	uint8_t index = vf->index & 0xff;
4139	if (index >= 0 && index < dec->used_buf_num) {
4140	struct avs2_frame_s *pic = get_pic_by_index(dec, index);
4141	if (pic == NULL &&
4142	(debug & AVS2_DBG_PIC_LEAK)) {
4143	int i;
4144	avs2_print(dec, 0,
4145	"%s error index 0x%x pic not exist\n",
4146	__func__, index);
4147	dump_pic_list(dec);
4148	for (i = 0; i < 10; i++) {
4149	pic = get_pic_by_index(dec, index);
4150	pr_info("pic = %p\n", pic);
4151	}
4152
4153	if (debug & AVS2_DBG_PIC_LEAK)
4154	debug |= AVS2_DBG_PIC_LEAK_WAIT;
4155	return NULL;
4156	}
4157	dec->vf_get_count++;
4158	if (pic)
4159	avs2_print(dec, AVS2_DBG_BUFMGR,
4160	"%s index 0x%x pos %d getcount %d type 0x%x w/h %d/%d, pts %d, %lld\n",
4161	__func__, index,
4162	pic->imgtr_fwRefDistance_bak,
4163	dec->vf_get_count,
4164	vf->type,
4165	vf->width, vf->height,
4166	vf->pts,
4167	vf->pts_us64);
4168	return vf;
4169	}
4170	}
4171	return NULL;
4172	}
4173
4174	static void vavs2_vf_put(struct vframe_s *vf, void *op_arg)
4175	{
4176	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4177	uint8_t index = vf->index & 0xff;
4178
4179	if (vf == (&dec->vframe_dummy))
4180	return;
4181
4182	kfifo_put(&dec->newframe_q, (const struct vframe_s *)vf);
4183	dec->vf_put_count++;
4184	avs2_print(dec, AVS2_DBG_BUFMGR,
4185	"%s index putcount 0x%x %d\n",
4186	__func__, vf->index,
4187	dec->vf_put_count);
4188
4189	if (index >= 0
4190	&& index < dec->used_buf_num) {
4191	unsigned long flags;
4192	struct avs2_frame_s *pic;
4193
4194	lock_buffer(dec, flags);
4195	pic = get_pic_by_index(dec, index);
4196	if (pic && pic->vf_ref > 0)
4197	pic->vf_ref--;
4198	else {
4199	if (pic)
4200	avs2_print(dec, 0,
4201	"%s, error pic (index %d) vf_ref is %d\n",
4202	__func__, index, pic->vf_ref);
4203	else
4204	avs2_print(dec, 0,
4205	"%s, error pic (index %d) is NULL\n",
4206	__func__, index);
4207	}
4208	if (dec->wait_buf)
4209	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
4210	0x1);
4211	dec->last_put_idx = index;
4212	dec->new_frame_displayed++;
4213	unlock_buffer(dec, flags);
4214	}
4215
4216	}
4217
4218	static int vavs2_event_cb(int type, void *data, void *private_data)
4219	{
4220	return 0;
4221	}
4222
4223	static struct avs2_frame_s *get_disp_pic(struct AVS2Decoder_s *dec)
4224	{
4225	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
4226	struct avs2_frame_s *pic = NULL;
4227	int32_t j;
4228	int32_t pre_disp_count_min = 0x7fffffff;
4229	for (j = 0; j < avs2_dec->ref_maxbuffer; j++) {
4230	if (avs2_dec->fref[j]->to_prepare_disp &&
4231	avs2_dec->fref[j]->to_prepare_disp <
4232	pre_disp_count_min) {
4233	pre_disp_count_min =
4234	avs2_dec->fref[j]->to_prepare_disp;
4235	pic = avs2_dec->fref[j];
4236	}
4237	}
4238	if (pic)
4239	pic->to_prepare_disp = 0;
4240
4241	return pic;
4242
4243	}
4244
4245
4246
4247	static void fill_frame_info(struct AVS2Decoder_s *dec,
4248	struct avs2_frame_s *pic, unsigned int framesize, unsigned int pts)
4249	{
4250	struct vframe_qos_s *vframe_qos = &dec->vframe_qos;
4251
4252	if (pic->slice_type == I_IMG)
4253	vframe_qos->type = 1;
4254	else if (pic->slice_type == P_IMG)
4255	vframe_qos->type = 2;
4256	else if (pic->slice_type == B_IMG)
4257	vframe_qos->type = 3;
4258	/*
4259	#define SHOW_QOS_INFO
4260	*/
4261	vframe_qos->size = framesize;
4262	vframe_qos->pts = pts;
4263	#ifdef SHOW_QOS_INFO
4264	avs2_print(dec, 0, "slice:%d\n", pic->slice_type);
4265	#endif
4266
4267
4268	vframe_qos->max_mv = pic->max_mv;
4269	vframe_qos->avg_mv = pic->avg_mv;
4270	vframe_qos->min_mv = pic->min_mv;
4271	#ifdef SHOW_QOS_INFO
4272	avs2_print(dec, 0, "mv: max:%d, avg:%d, min:%d\n",
4273	vframe_qos->max_mv,
4274	vframe_qos->avg_mv,
4275	vframe_qos->min_mv);
4276	#endif
4277
4278	vframe_qos->max_qp = pic->max_qp;
4279	vframe_qos->avg_qp = pic->avg_qp;
4280	vframe_qos->min_qp = pic->min_qp;
4281	#ifdef SHOW_QOS_INFO
4282	avs2_print(dec, 0, "qp: max:%d, avg:%d, min:%d\n",
4283	vframe_qos->max_qp,
4284	vframe_qos->avg_qp,
4285	vframe_qos->min_qp);
4286	#endif
4287
4288	vframe_qos->max_skip = pic->max_skip;
4289	vframe_qos->avg_skip = pic->avg_skip;
4290	vframe_qos->min_skip = pic->min_skip;
4291	#ifdef SHOW_QOS_INFO
4292	avs2_print(dec, 0, "skip: max:%d, avg:%d, min:%d\n",
4293	vframe_qos->max_skip,
4294	vframe_qos->avg_skip,
4295	vframe_qos->min_skip);
4296	#endif
4297
4298	vframe_qos->num++;
4299
4300	if (dec->frameinfo_enable)
4301	vdec_fill_frame_info(vframe_qos, 1);
4302	}
4303
4304	static void set_vframe(struct AVS2Decoder_s *dec,
4305	struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy)
4306	{
4307	unsigned long flags;
4308	int stream_offset;
4309	unsigned int frame_size;
4310	int pts_discontinue;
4311	stream_offset = pic->stream_offset;
4312	avs2_print(dec, AVS2_DBG_BUFMGR,
4313	"%s index = %d pos = %d\r\n",
4314	__func__, pic->index,
4315	pic->imgtr_fwRefDistance);
4316
4317	if (pic->double_write_mode)
4318	set_canvas(dec, pic);
4319
4320	display_frame_count[dec->index]++;
4321
4322	if (!dummy) {
4323	#ifdef MULTI_INSTANCE_SUPPORT
4324	if (vdec_frame_based(hw_to_vdec(dec))) {
4325	vf->pts = pic->pts;
4326	vf->pts_us64 = pic->pts64;
4327	} else
4328	#endif
4329	/* if (pts_lookup_offset(PTS_TYPE_VIDEO,
4330	stream_offset, &vf->pts, 0) != 0) { */
4331	if (pts_lookup_offset_us64
4332	(PTS_TYPE_VIDEO, stream_offset,
4333	&vf->pts, &frame_size, 0,
4334	&vf->pts_us64) != 0) {
4335	#ifdef DEBUG_PTS
4336	dec->pts_missed++;
4337	#endif
4338	vf->pts = 0;
4339	vf->pts_us64 = 0;
4340	}
4341	#ifdef DEBUG_PTS
4342	else
4343	dec->pts_hit++;
4344	#endif
4345	if (pts_unstable)
4346	dec->pts_mode = PTS_NONE_REF_USE_DURATION;
4347
4348	fill_frame_info(dec, pic, frame_size, vf->pts);
4349
4350	if ((dec->pts_mode == PTS_NORMAL) && (vf->pts != 0)
4351	&& dec->get_frame_dur) {
4352	int pts_diff = (int)vf->pts - dec->last_lookup_pts;
4353
4354	if (pts_diff < 0) {
4355	dec->pts_mode_switching_count++;
4356	dec->pts_mode_recovery_count = 0;
4357
4358	if (dec->pts_mode_switching_count >=
4359	PTS_MODE_SWITCHING_THRESHOLD) {
4360	dec->pts_mode =
4361	PTS_NONE_REF_USE_DURATION;
4362	pr_info
4363	("HEVC: switch to n_d mode.\n");
4364	}
4365
4366	} else {
4367	int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
4368	dec->pts_mode_recovery_count++;
4369	if (dec->pts_mode_recovery_count > p) {
4370	dec->pts_mode_switching_count = 0;
4371	dec->pts_mode_recovery_count = 0;
4372	}
4373	}
4374	}
4375
4376	pts_discontinue =
4377	(abs(dec->last_pts - vf->pts) >=
4378	tsync_vpts_discontinuity_margin());
4379
4380	if (vf->pts != 0)
4381	dec->last_lookup_pts = vf->pts;
4382	#if 1
4383	if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION)
4384	&& ((pic->slice_type != I_IMG) || (!pts_discontinue &&
4385	!first_pts_checkin_complete(PTS_TYPE_AUDIO))))
4386	vf->pts = dec->last_pts + DUR2PTS(dec->frame_dur);
4387	#endif
4388	dec->last_pts = vf->pts;
4389
4390	if (vf->pts_us64 != 0)
4391	dec->last_lookup_pts_us64 = vf->pts_us64;
4392
4393	#if 1
4394	if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION)
4395	&& ((pic->slice_type != I_IMG) || (!pts_discontinue &&
4396	!first_pts_checkin_complete(PTS_TYPE_AUDIO)))) {
4397	vf->pts_us64 =
4398	dec->last_pts_us64 +
4399	(DUR2PTS(dec->frame_dur) * 100 / 9);
4400	}
4401	#endif
4402	dec->last_pts_us64 = vf->pts_us64;
4403	avs2_print(dec, AVS2_DBG_OUT_PTS,
4404	"avs2 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n",
4405	vf->pts, vf->pts_us64);
4406	}
4407
4408	vf->index = 0xff00 | pic->index;
4409
4410	if (pic->double_write_mode & 0x10) {
4411	/* double write only */
4412	vf->compBodyAddr = 0;
4413	vf->compHeadAddr = 0;
4414	} else {
4415	#ifdef AVS2_10B_MMU
4416	vf->compBodyAddr = 0;
4417	vf->compHeadAddr = pic->header_adr;
4418	#else
4419	vf->compBodyAddr = pic->mc_y_adr; /*body adr*/
4420	vf->compHeadAddr = pic->mc_y_adr +
4421	pic->comp_body_size;
4422	/*head adr*/
4423	#endif
4424	}
4425	if (pic->double_write_mode) {
4426	vf->type = VIDTYPE_PROGRESSIVE |
4427	VIDTYPE_VIU_FIELD;
4428	vf->type |= VIDTYPE_VIU_NV21;
4429	if (pic->double_write_mode == 3) {
4430	vf->type |= VIDTYPE_COMPRESS;
4431	#ifdef AVS2_10B_MMU
4432	vf->type |= VIDTYPE_SCATTER;
4433	#endif
4434	}
4435	#ifdef MULTI_INSTANCE_SUPPORT
4436	if (dec->m_ins_flag) {
4437	vf->canvas0Addr = vf->canvas1Addr = -1;
4438	vf->plane_num = 2;
4439	vf->canvas0_config[0] =
4440	pic->canvas_config[0];
4441	vf->canvas0_config[1] =
4442	pic->canvas_config[1];
4443
4444	vf->canvas1_config[0] =
4445	pic->canvas_config[0];
4446	vf->canvas1_config[1] =
4447	pic->canvas_config[1];
4448
4449	} else
4450	#endif
4451	vf->canvas0Addr = vf->canvas1Addr =
4452	spec2canvas(pic);
4453	} else {
4454	vf->canvas0Addr = vf->canvas1Addr = 0;
4455	vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
4456	#ifdef AVS2_10B_MMU
4457	vf->type |= VIDTYPE_SCATTER;
4458	#endif
4459	}
4460
4461	switch (pic->bit_depth) {
4462	case AVS2_BITS_8:
4463	vf->bitdepth = BITDEPTH_Y8 |
4464	BITDEPTH_U8 | BITDEPTH_V8;
4465	break;
4466	case AVS2_BITS_10:
4467	case AVS2_BITS_12:
4468	vf->bitdepth = BITDEPTH_Y10 |
4469	BITDEPTH_U10 | BITDEPTH_V10;
4470	break;
4471	default:
4472	vf->bitdepth = BITDEPTH_Y10 |
4473	BITDEPTH_U10 | BITDEPTH_V10;
4474	break;
4475	}
4476	if ((vf->type & VIDTYPE_COMPRESS) == 0)
4477	vf->bitdepth =
4478	BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
4479	if (pic->bit_depth == AVS2_BITS_8)
4480	vf->bitdepth |= BITDEPTH_SAVING_MODE;
4481
4482	set_frame_info(dec, vf);
4483	/* if((vf->width!=pic->width)|
4484	(vf->height!=pic->height)) */
4485	/* pr_info("aaa: %d/%d, %d/%d\n",
4486	vf->width,vf->height, pic->width,
4487	pic->height); */
4488	vf->width = pic->pic_w /
4489	get_double_write_ratio(dec,
4490	pic->double_write_mode);
4491	vf->height = pic->pic_h /
4492	get_double_write_ratio(dec,
4493	pic->double_write_mode);
4494	if (force_w_h != 0) {
4495	vf->width = (force_w_h >> 16) & 0xffff;
4496	vf->height = force_w_h & 0xffff;
4497	}
4498	vf->compWidth = pic->pic_w;
4499	vf->compHeight = pic->pic_h;
4500	if (force_fps & 0x100) {
4501	u32 rate = force_fps & 0xff;
4502	if (rate)
4503	vf->duration = 96000/rate;
4504	else
4505	vf->duration = 0;
4506	}
4507	#ifdef AVS2_10B_MMU
4508	if (vf->type & VIDTYPE_SCATTER) {
4509	vf->mem_handle = decoder_mmu_box_get_mem_handle(
4510	dec->mmu_box,
4511	pic->index);
4512	vf->mem_head_handle = decoder_bmmu_box_get_mem_handle(
4513	dec->bmmu_box,
4514	HEADER_BUFFER_IDX(pic->index));
4515	} else {
4516	vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4517	dec->bmmu_box,
4518	VF_BUFFER_IDX(pic->index));
4519	vf->mem_head_handle = decoder_bmmu_box_get_mem_handle(
4520	dec->bmmu_box,
4521	HEADER_BUFFER_IDX(pic->index));
4522	}
4523	#else
4524	vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4525	dec->bmmu_box,
4526	VF_BUFFER_IDX(pic->index));
4527	#endif
4528
4529	if (!dummy) {
4530	lock_buffer(dec, flags);
4531	pic->vf_ref = 1;
4532	unlock_buffer(dec, flags);
4533	}
4534	dec->vf_pre_count++;
4535	}
4536
4537
4538	static int avs2_prepare_display_buf(struct AVS2Decoder_s *dec)
4539	{
4540	#ifndef NO_DISPLAY
4541	struct vframe_s *vf = NULL;
4542	/*unsigned short slice_type;*/
4543	struct avs2_frame_s *pic;
4544	while (1) {
4545	pic = get_disp_pic(dec);
4546	if (pic == NULL)
4547	break;
4548
4549	if (force_disp_pic_index & 0x100) {
4550	/*recycle directly*/
4551	continue;
4552	}
4553
4554	if (pic->error_mark) {
4555	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
4556	"!!!error pic, skip\n",
4557	0);
4558	continue;
4559	}
4560
4561	if (dec->start_decoding_flag != 0) {
4562	if (dec->skip_PB_before_I &&
4563	pic->slice_type != I_IMG) {
4564	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
4565	"!!!slice type %d (not I) skip\n",
4566	0, pic->slice_type);
4567	continue;
4568	}
4569	dec->skip_PB_before_I = 0;
4570	}
4571
4572	if (kfifo_get(&dec->newframe_q, &vf) == 0) {
4573	pr_info("fatal error, no available buffer slot.");
4574	return -1;
4575	}
4576
4577	if (vf) {
4578	set_vframe(dec, vf, pic, 0);
4579	decoder_do_frame_check(hw_to_vdec(dec), vf);
4580	kfifo_put(&dec->display_q, (const struct vframe_s *)vf);
4581	ATRACE_COUNTER(MODULE_NAME, vf->pts);
4582
4583	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
4584	/*count info*/
4585	gvs->frame_dur = dec->frame_dur;
4586	vdec_count_info(gvs, 0, stream_offset);
4587	#endif
4588	hw_to_vdec(dec)->vdec_fps_detec(hw_to_vdec(dec)->id);
4589	if (without_display_mode == 0) {
4590	vf_notify_receiver(dec->provider_name,
4591	VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
4592	} else
4593	vavs2_vf_put(vavs2_vf_get(dec), dec);
4594	}
4595	}
4596	/*!NO_DISPLAY*/
4597	#endif
4598	return 0;
4599	}
4600
4601	static void get_rpm_param(union param_u *params)
4602	{
4603	int i;
4604	unsigned int data32;
4605	if (debug & AVS2_DBG_BUFMGR)
4606	pr_info("enter %s\r\n", __func__);
4607	for (i = 0; i < (RPM_END - RPM_BEGIN); i++) {
4608	do {
4609	data32 = READ_VREG(RPM_CMD_REG);
4610	/*pr_info("%x\n", data32);*/
4611	} while ((data32 & 0x10000) == 0);
4612	params->l.data[i] = data32&0xffff;
4613	/*pr_info("%x\n", data32);*/
4614	WRITE_VREG(RPM_CMD_REG, 0);
4615	}
4616	if (debug & AVS2_DBG_BUFMGR)
4617	pr_info("leave %s\r\n", __func__);
4618	}
4619	static void debug_buffer_mgr_more(struct AVS2Decoder_s *dec)
4620	{
4621	int i;
4622	if (!(debug & AVS2_DBG_BUFMGR_MORE))
4623	return;
4624	pr_info("avs2_param: (%d)\n", dec->avs2_dec.img.number);
4625	for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
4626	pr_info("%04x ", dec->avs2_dec.param.l.data[i]);
4627	if (((i + 1) & 0xf) == 0)
4628	pr_info("\n");
4629	}
4630	}
4631
4632	#ifdef AVS2_10B_MMU
4633	static void avs2_recycle_mmu_buf_tail(struct AVS2Decoder_s *dec)
4634	{
4635	if (dec->cur_fb_idx_mmu != INVALID_IDX) {
4636	if (dec->used_4k_num == -1) {
4637	dec->used_4k_num =
4638	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
4639	if (dec->m_ins_flag)
4640	hevc_mmu_dma_check(hw_to_vdec(dec));
4641	decoder_mmu_box_free_idx_tail(dec->mmu_box,
4642	dec->cur_fb_idx_mmu, dec->used_4k_num);
4643	}
4644	dec->cur_fb_idx_mmu = INVALID_IDX;
4645	dec->used_4k_num = -1;
4646	}
4647	}
4648
4649	static void avs2_recycle_mmu_buf(struct AVS2Decoder_s *dec)
4650	{
4651	if (dec->cur_fb_idx_mmu != INVALID_IDX) {
4652	decoder_mmu_box_free_idx(dec->mmu_box,
4653	dec->cur_fb_idx_mmu);
4654
4655	dec->cur_fb_idx_mmu = INVALID_IDX;
4656	dec->used_4k_num = -1;
4657	}
4658	}
4659	#endif
4660
4661	static void dec_again_process(struct AVS2Decoder_s *dec)
4662	{
4663	amhevc_stop();
4664	dec->dec_result = DEC_RESULT_AGAIN;
4665	if (dec->process_state ==
4666	PROC_STATE_DECODING) {
4667	dec->process_state =
4668	PROC_STATE_DECODE_AGAIN;
4669	} else if (dec->process_state ==
4670	PROC_STATE_HEAD_DONE) {
4671	dec->process_state =
4672	PROC_STATE_HEAD_AGAIN;
4673	}
4674	dec->next_again_flag = 1;
4675	reset_process_time(dec);
4676	vdec_schedule_work(&dec->work);
4677	}
4678
4679	static uint32_t log2i(uint32_t val)
4680	{
4681	uint32_t ret = -1;
4682	while (val != 0) {
4683	val >>= 1;
4684	ret++;
4685	}
4686	return ret;
4687	}
4688
4689	static void check_pic_error(struct AVS2Decoder_s *dec,
4690	struct avs2_frame_s *pic)
4691	{
4692	if (pic->decoded_lcu == 0) {
4693	pic->decoded_lcu =
4694	(READ_VREG(HEVC_PARSER_LCU_START)
4695	& 0xffffff) + 1;
4696	}
4697	if (pic->decoded_lcu != dec->avs2_dec.lcu_total) {
4698	avs2_print(dec, AVS2_DBG_BUFMGR,
4699	"%s error pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4700	__func__, pic->index, pic->imgtr_fwRefDistance,
4701	pic->decoded_lcu, dec->avs2_dec.lcu_total);
4702	pic->error_mark = 1;
4703	} else {
4704	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4705	"%s pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4706	__func__, pic->index, pic->imgtr_fwRefDistance,
4707	pic->decoded_lcu, dec->avs2_dec.lcu_total);
4708
4709	}
4710	}
4711	static void update_decoded_pic(struct AVS2Decoder_s *dec)
4712	{
4713	struct avs2_frame_s *pic = dec->avs2_dec.hc.cur_pic;
4714	if (pic) {
4715	dec->avs2_dec.hc.cur_pic->decoded_lcu =
4716	(READ_VREG(HEVC_PARSER_LCU_START)
4717	& 0xffffff) + 1;
4718	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4719	"%s pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4720	__func__, pic->index, pic->imgtr_fwRefDistance,
4721	pic->decoded_lcu, dec->avs2_dec.lcu_total);
4722	}
4723	}
4724	/* +[SE] [BUG][BUG-171463][chuanqi.wang]: get frame rate by video sequeue*/
4725	static int get_frame_rate(union param_u *params, struct AVS2Decoder_s *dec)
4726	{
4727	int tmp = 0;
4728
4729	switch (params->p.frame_rate_code) {
4730	case 1:
4731	case 2:
4732	tmp = 24;
4733	break;
4734	case 3:
4735	tmp = 25;
4736	break;
4737	case 4:
4738	case 5:
4739	tmp = 30;
4740	break;
4741	case 6:
4742	tmp = 50;
4743	break;
4744	case 7:
4745	case 8:
4746	tmp = 60;
4747	break;
4748	case 9:
4749	tmp = 100;
4750	break;
4751	case 10:
4752	tmp = 120;
4753	break;
4754	default:
4755	tmp = 25;
4756	break;
4757	}
4758
4759	if (!params->p.progressive_sequence)
4760	tmp = tmp / 2;
4761	dec->frame_dur = div_u64(96000ULL, tmp);
4762	dec->get_frame_dur = true;
4763	/*avs2_print(dec, 0, "avs2 frame_dur:%d,progressive:%d\n", dec->frame_dur, params->p.progressive_sequence);*/
4764	return 0;
4765	}
4766
4767
4768	#define HEVC_MV_INFO 0x310d
4769	#define HEVC_QP_INFO 0x3137
4770	#define HEVC_SKIP_INFO 0x3136
4771
4772	/* only when we decoded one field or one frame,
4773	we can call this function to get qos info*/
4774	static void get_picture_qos_info(struct AVS2Decoder_s *dec)
4775	{
4776	struct avs2_frame_s *picture = dec->avs2_dec.hc.cur_pic;
4777	if (!picture) {
4778	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4779	"%s decode picture is none exist\n");
4780
4781	return;
4782	}
4783
4784	/*
4785	#define DEBUG_QOS
4786	*/
4787
4788	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4789	unsigned char a[3];
4790	unsigned char i, j, t;
4791	unsigned long data;
4792
4793	data = READ_VREG(HEVC_MV_INFO);
4794	if (picture->slice_type == I_IMG)
4795	data = 0;
4796	a[0] = data & 0xff;
4797	a[1] = (data >> 8) & 0xff;
4798	a[2] = (data >> 16) & 0xff;
4799
4800	for (i = 0; i < 3; i++)
4801	for (j = i+1; j < 3; j++) {
4802	if (a[j] < a[i]) {
4803	t = a[j];
4804	a[j] = a[i];
4805	a[i] = t;
4806	} else if (a[j] == a[i]) {
4807	a[i]++;
4808	t = a[j];
4809	a[j] = a[i];
4810	a[i] = t;
4811	}
4812	}
4813	picture->max_mv = a[2];
4814	picture->avg_mv = a[1];
4815	picture->min_mv = a[0];
4816	#ifdef DEBUG_QOS
4817	avs2_print(dec, 0, "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4818	data, a[0], a[1], a[2]);
4819	#endif
4820
4821	data = READ_VREG(HEVC_QP_INFO);
4822	a[0] = data & 0x1f;
4823	a[1] = (data >> 8) & 0x3f;
4824	a[2] = (data >> 16) & 0x7f;
4825
4826	for (i = 0; i < 3; i++)
4827	for (j = i+1; j < 3; j++) {
4828	if (a[j] < a[i]) {
4829	t = a[j];
4830	a[j] = a[i];
4831	a[i] = t;
4832	} else if (a[j] == a[i]) {
4833	a[i]++;
4834	t = a[j];
4835	a[j] = a[i];
4836	a[i] = t;
4837	}
4838	}
4839	picture->max_qp = a[2];
4840	picture->avg_qp = a[1];
4841	picture->min_qp = a[0];
4842	#ifdef DEBUG_QOS
4843	avs2_print(dec, 0, "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4844	data, a[0], a[1], a[2]);
4845	#endif
4846
4847	data = READ_VREG(HEVC_SKIP_INFO);
4848	a[0] = data & 0x1f;
4849	a[1] = (data >> 8) & 0x3f;
4850	a[2] = (data >> 16) & 0x7f;
4851
4852	for (i = 0; i < 3; i++)
4853	for (j = i+1; j < 3; j++) {
4854	if (a[j] < a[i]) {
4855	t = a[j];
4856	a[j] = a[i];
4857	a[i] = t;
4858	} else if (a[j] == a[i]) {
4859	a[i]++;
4860	t = a[j];
4861	a[j] = a[i];
4862	a[i] = t;
4863	}
4864	}
4865	picture->max_skip = a[2];
4866	picture->avg_skip = a[1];
4867	picture->min_skip = a[0];
4868
4869	#ifdef DEBUG_QOS
4870	avs2_print(dec, 0,
4871	"skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4872	data, a[0], a[1], a[2]);
4873	#endif
4874	} else {
4875	uint32_t blk88_y_count;
4876	uint32_t blk88_c_count;
4877	uint32_t blk22_mv_count;
4878	uint32_t rdata32;
4879	int32_t mv_hi;
4880	int32_t mv_lo;
4881	uint32_t rdata32_l;
4882	uint32_t mvx_L0_hi;
4883	uint32_t mvy_L0_hi;
4884	uint32_t mvx_L1_hi;
4885	uint32_t mvy_L1_hi;
4886	int64_t value;
4887	uint64_t temp_value;
4888	#ifdef DEBUG_QOS
4889	int pic_number = 0;
4890	#endif
4891
4892	picture->max_mv = 0;
4893	picture->avg_mv = 0;
4894	picture->min_mv = 0;
4895
4896	picture->max_skip = 0;
4897	picture->avg_skip = 0;
4898	picture->min_skip = 0;
4899
4900	picture->max_qp = 0;
4901	picture->avg_qp = 0;
4902	picture->min_qp = 0;
4903
4904
4905
4906	#ifdef DEBUG_QOS
4907	avs2_print(dec, 0, "slice_type:%d, poc:%d\n",
4908	picture->slice_type,
4909	pic_number);
4910	#endif
4911	/* set rd_idx to 0 */
4912	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
4913
4914	blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
4915	if (blk88_y_count == 0) {
4916	#ifdef DEBUG_QOS
4917	avs2_print(dec, 0,
4918	"[Picture %d Quality] NO Data yet.\n",
4919	pic_number);
4920	#endif
4921	/* reset all counts */
4922	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
4923	return;
4924	}
4925	/* qp_y_sum */
4926	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4927	#ifdef DEBUG_QOS
4928	avs2_print(dec, 0,
4929	"[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4930	pic_number, rdata32/blk88_y_count,
4931	rdata32, blk88_y_count);
4932	#endif
4933	picture->avg_qp = rdata32/blk88_y_count;
4934	/* intra_y_count */
4935	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4936	#ifdef DEBUG_QOS
4937	avs2_print(dec, 0,
4938	"[Picture %d Quality] Y intra rate : %d%c (%d)\n",
4939	pic_number, rdata32*100/blk88_y_count,
4940	'%', rdata32);
4941	#endif
4942	/* skipped_y_count */
4943	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4944	#ifdef DEBUG_QOS
4945	avs2_print(dec, 0,
4946	"[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4947	pic_number, rdata32*100/blk88_y_count,
4948	'%', rdata32);
4949	#endif
4950	picture->avg_skip = rdata32*100/blk88_y_count;
4951	/* coeff_non_zero_y_count */
4952	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4953	#ifdef DEBUG_QOS
4954	avs2_print(dec, 0,
4955	"[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4956	pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4957	'%', rdata32);
4958	#endif
4959	/* blk66_c_count */
4960	blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
4961	if (blk88_c_count == 0) {
4962	#ifdef DEBUG_QOS
4963	avs2_print(dec, 0,
4964	"[Picture %d Quality] NO Data yet.\n",
4965	pic_number);
4966	#endif
4967	/* reset all counts */
4968	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
4969	return;
4970	}
4971	/* qp_c_sum */
4972	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4973	#ifdef DEBUG_QOS
4974	avs2_print(dec, 0,
4975	"[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4976	pic_number, rdata32/blk88_c_count,
4977	rdata32, blk88_c_count);
4978	#endif
4979	/* intra_c_count */
4980	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4981	#ifdef DEBUG_QOS
4982	avs2_print(dec, 0,
4983	"[Picture %d Quality] C intra rate : %d%c (%d)\n",
4984	pic_number, rdata32*100/blk88_c_count,
4985	'%', rdata32);
4986	#endif
4987	/* skipped_cu_c_count */
4988	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4989	#ifdef DEBUG_QOS
4990	avs2_print(dec, 0,
4991	"[Picture %d Quality] C skipped rate : %d%c (%d)\n",
4992	pic_number, rdata32*100/blk88_c_count,
4993	'%', rdata32);
4994	#endif
4995	/* coeff_non_zero_c_count */
4996	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4997	#ifdef DEBUG_QOS
4998	avs2_print(dec, 0,
4999	"[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
5000	pic_number, (100 - rdata32*100/(blk88_c_count*1)),
5001	'%', rdata32);
5002	#endif
5003
5004	/* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
5005	1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
5006	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5007	#ifdef DEBUG_QOS
5008	avs2_print(dec, 0, "[Picture %d Quality] Y QP min : %d\n",
5009	pic_number, (rdata32>>0)&0xff);
5010	#endif
5011	picture->min_qp = (rdata32>>0)&0xff;
5012
5013	#ifdef DEBUG_QOS
5014	avs2_print(dec, 0, "[Picture %d Quality] Y QP max : %d\n",
5015	pic_number, (rdata32>>8)&0xff);
5016	#endif
5017	picture->max_qp = (rdata32>>8)&0xff;
5018
5019	#ifdef DEBUG_QOS
5020	avs2_print(dec, 0, "[Picture %d Quality] C QP min : %d\n",
5021	pic_number, (rdata32>>16)&0xff);
5022	avs2_print(dec, 0, "[Picture %d Quality] C QP max : %d\n",
5023	pic_number, (rdata32>>24)&0xff);
5024	#endif
5025
5026	/* blk22_mv_count */
5027	blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
5028	if (blk22_mv_count == 0) {
5029	#ifdef DEBUG_QOS
5030	avs2_print(dec, 0,
5031	"[Picture %d Quality] NO MV Data yet.\n",
5032	pic_number);
5033	#endif
5034	/* reset all counts */
5035	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5036	return;
5037	}
5038	/* mvy_L1_count[39:32], mvx_L1_count[39:32],
5039	mvy_L0_count[39:32], mvx_L0_count[39:32] */
5040	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5041	/* should all be 0x00 or 0xff */
5042	#ifdef DEBUG_QOS
5043	avs2_print(dec, 0,
5044	"[Picture %d Quality] MV AVG High Bits: 0x%X\n",
5045	pic_number, rdata32);
5046	#endif
5047	mvx_L0_hi = ((rdata32>>0)&0xff);
5048	mvy_L0_hi = ((rdata32>>8)&0xff);
5049	mvx_L1_hi = ((rdata32>>16)&0xff);
5050	mvy_L1_hi = ((rdata32>>24)&0xff);
5051
5052	/* mvx_L0_count[31:0] */
5053	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5054	temp_value = mvx_L0_hi;
5055	temp_value = (temp_value << 32) | rdata32_l;
5056
5057	if (mvx_L0_hi & 0x80)
5058	value = 0xFFFFFFF000000000 | temp_value;
5059	else
5060	value = temp_value;
5061	value = div_s64(value, blk22_mv_count);
5062	#ifdef DEBUG_QOS
5063	avs2_print(dec, 0,
5064	"[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
5065	pic_number, (int)value,
5066	value, blk22_mv_count);
5067	#endif
5068	picture->avg_mv = value;
5069
5070	/* mvy_L0_count[31:0] */
5071	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5072	temp_value = mvy_L0_hi;
5073	temp_value = (temp_value << 32) | rdata32_l;
5074
5075	if (mvy_L0_hi & 0x80)
5076	value = 0xFFFFFFF000000000 | temp_value;
5077	else
5078	value = temp_value;
5079	#ifdef DEBUG_QOS
5080	avs2_print(dec, 0,
5081	"[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
5082	pic_number, rdata32_l/blk22_mv_count,
5083	value, blk22_mv_count);
5084	#endif
5085
5086	/* mvx_L1_count[31:0] */
5087	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5088	temp_value = mvx_L1_hi;
5089	temp_value = (temp_value << 32) | rdata32_l;
5090	if (mvx_L1_hi & 0x80)
5091	value = 0xFFFFFFF000000000 | temp_value;
5092	else
5093	value = temp_value;
5094	#ifdef DEBUG_QOS
5095	avs2_print(dec, 0,
5096	"[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
5097	pic_number, rdata32_l/blk22_mv_count,
5098	value, blk22_mv_count);
5099	#endif
5100
5101	/* mvy_L1_count[31:0] */
5102	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5103	temp_value = mvy_L1_hi;
5104	temp_value = (temp_value << 32) | rdata32_l;
5105	if (mvy_L1_hi & 0x80)
5106	value = 0xFFFFFFF000000000 | temp_value;
5107	else
5108	value = temp_value;
5109	#ifdef DEBUG_QOS
5110	avs2_print(dec, 0,
5111	"[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
5112	pic_number, rdata32_l/blk22_mv_count,
5113	value, blk22_mv_count);
5114	#endif
5115
5116	/* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
5117	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5118	mv_hi = (rdata32>>16)&0xffff;
5119	if (mv_hi & 0x8000)
5120	mv_hi = 0x8000 - mv_hi;
5121	#ifdef DEBUG_QOS
5122	avs2_print(dec, 0, "[Picture %d Quality] MVX_L0 MAX : %d\n",
5123	pic_number, mv_hi);
5124	#endif
5125	picture->max_mv = mv_hi;
5126
5127	mv_lo = (rdata32>>0)&0xffff;
5128	if (mv_lo & 0x8000)
5129	mv_lo = 0x8000 - mv_lo;
5130	#ifdef DEBUG_QOS
5131	avs2_print(dec, 0, "[Picture %d Quality] MVX_L0 MIN : %d\n",
5132	pic_number, mv_lo);
5133	#endif
5134	picture->min_mv = mv_lo;
5135
5136	/* {mvy_L0_max, mvy_L0_min} */
5137	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5138	mv_hi = (rdata32>>16)&0xffff;
5139	if (mv_hi & 0x8000)
5140	mv_hi = 0x8000 - mv_hi;
5141	#ifdef DEBUG_QOS
5142	avs2_print(dec, 0, "[Picture %d Quality] MVY_L0 MAX : %d\n",
5143	pic_number, mv_hi);
5144	#endif
5145
5146	mv_lo = (rdata32>>0)&0xffff;
5147	if (mv_lo & 0x8000)
5148	mv_lo = 0x8000 - mv_lo;
5149	#ifdef DEBUG_QOS
5150	avs2_print(dec, 0, "[Picture %d Quality] MVY_L0 MIN : %d\n",
5151	pic_number, mv_lo);
5152	#endif
5153
5154	/* {mvx_L1_max, mvx_L1_min} */
5155	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5156	mv_hi = (rdata32>>16)&0xffff;
5157	if (mv_hi & 0x8000)
5158	mv_hi = 0x8000 - mv_hi;
5159	#ifdef DEBUG_QOS
5160	avs2_print(dec, 0, "[Picture %d Quality] MVX_L1 MAX : %d\n",
5161	pic_number, mv_hi);
5162	#endif
5163
5164	mv_lo = (rdata32>>0)&0xffff;
5165	if (mv_lo & 0x8000)
5166	mv_lo = 0x8000 - mv_lo;
5167	#ifdef DEBUG_QOS
5168	avs2_print(dec, 0, "[Picture %d Quality] MVX_L1 MIN : %d\n",
5169	pic_number, mv_lo);
5170	#endif
5171
5172	/* {mvy_L1_max, mvy_L1_min} */
5173	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5174	mv_hi = (rdata32>>16)&0xffff;
5175	if (mv_hi & 0x8000)
5176	mv_hi = 0x8000 - mv_hi;
5177	#ifdef DEBUG_QOS
5178	avs2_print(dec, 0, "[Picture %d Quality] MVY_L1 MAX : %d\n",
5179	pic_number, mv_hi);
5180	#endif
5181	mv_lo = (rdata32>>0)&0xffff;
5182	if (mv_lo & 0x8000)
5183	mv_lo = 0x8000 - mv_lo;
5184	#ifdef DEBUG_QOS
5185	avs2_print(dec, 0, "[Picture %d Quality] MVY_L1 MIN : %d\n",
5186	pic_number, mv_lo);
5187	#endif
5188
5189	rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
5190	#ifdef DEBUG_QOS
5191	avs2_print(dec, 0,
5192	"[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
5193	pic_number, rdata32);
5194	#endif
5195	/* reset all counts */
5196	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5197	}
5198	}
5199
5200	static irqreturn_t vavs2_isr_thread_fn(int irq, void *data)
5201	{
5202	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data;
5203	unsigned int dec_status = dec->dec_status;
5204	int i, ret;
5205	int32_t start_code = 0;
5206
5207	/*if (dec->wait_buf)
5208	pr_info("set wait_buf to 0\r\n");
5209	*/
5210
5211	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
5212	"%s decode_status 0x%x process_state %d lcu 0x%x\n",
5213	__func__, dec_status, dec->process_state,
5214	READ_VREG(HEVC_PARSER_LCU_START));
5215
5216	#ifndef G12A_BRINGUP_DEBUG
5217	if (dec->eos) {
5218	PRINT_LINE();
5219	goto irq_handled_exit;
5220	}
5221	#endif
5222	dec->wait_buf = 0;
5223	if (dec_status == AVS2_DECODE_BUFEMPTY) {
5224	PRINT_LINE();
5225	if (dec->m_ins_flag) {
5226	reset_process_time(dec);
5227	if (!vdec_frame_based(hw_to_vdec(dec)))
5228	dec_again_process(dec);
5229	else {
5230	dec->dec_result = DEC_RESULT_DONE;
5231	reset_process_time(dec);
5232	amhevc_stop();
5233	vdec_schedule_work(&dec->work);
5234	}
5235	}
5236	goto irq_handled_exit;
5237	} else if (dec_status == HEVC_DECPIC_DATA_DONE) {
5238	PRINT_LINE();
5239	dec->start_decoding_flag |= 0x3;
5240	if (dec->m_ins_flag) {
5241	update_decoded_pic(dec);
5242	get_picture_qos_info(dec);
5243	reset_process_time(dec);
5244	dec->dec_result = DEC_RESULT_DONE;
5245	amhevc_stop();
5246	#if 0 /*def AVS2_10B_MMU*/
5247	if (dec->m_ins_flag) {
5248	/*avs2_recycle_mmu_buf_tail(dec);*/
5249	dec->used_4k_num =
5250	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
5251	}
5252	#endif
5253
5254	#if 0
5255	/*keep hardware state*/
5256	WRITE_VREG(HEVC_MPRED_INT_STATUS, (1<<31));
5257	WRITE_VREG(HEVC_PARSER_RESULT_3, 0xffffffff);
5258	dec->mpred_abv_start_addr =
5259	READ_VREG(HEVC_MPRED_ABV_START_ADDR);
5260	/**/
5261	#endif
5262	vdec_schedule_work(&dec->work);
5263	}
5264	goto irq_handled_exit;
5265	}
5266	PRINT_LINE();
5267	#if 0
5268	if (dec_status == AVS2_EOS) {
5269	if (dec->m_ins_flag)
5270	reset_process_time(dec);
5271
5272	avs2_print(dec, AVS2_DBG_BUFMGR,
5273	"AVS2_EOS, flush buffer\r\n");
5274
5275	avs2_post_process(&dec->avs2_dec);
5276	avs2_prepare_display_buf(dec);
5277
5278	avs2_print(dec, AVS2_DBG_BUFMGR,
5279	"send AVS2_10B_DISCARD_NAL\r\n");
5280	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL);
5281	if (dec->m_ins_flag) {
5282	update_decoded_pic(dec);
5283	dec->dec_result = DEC_RESULT_DONE;
5284	amhevc_stop();
5285	vdec_schedule_work(&dec->work);
5286	}
5287	goto irq_handled_exit;
5288	} else
5289	#endif
5290	if (dec_status == AVS2_DECODE_OVER_SIZE) {
5291	avs2_print(dec, 0,
5292	"avs2 decode oversize !!\n");
5293	debug |= (AVS2_DBG_DIS_LOC_ERROR_PROC |
5294	AVS2_DBG_DIS_SYS_ERROR_PROC);
5295	dec->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
5296	if (dec->m_ins_flag)
5297	reset_process_time(dec);
5298	goto irq_handled_exit;
5299	}
5300	PRINT_LINE();
5301
5302	if (dec->m_ins_flag)
5303	reset_process_time(dec);
5304
5305	if (dec_status == AVS2_HEAD_SEQ_READY)
5306	start_code = SEQUENCE_HEADER_CODE;
5307	else if (dec_status == AVS2_HEAD_PIC_I_READY)
5308	start_code = I_PICTURE_START_CODE;
5309	else if (dec_status == AVS2_HEAD_PIC_PB_READY)
5310	start_code = PB_PICTURE_START_CODE;
5311	else if (dec_status == AVS2_STARTCODE_SEARCH_DONE)
5312	/*SEQUENCE_END_CODE, VIDEO_EDIT_CODE*/
5313	start_code = READ_VREG(CUR_NAL_UNIT_TYPE);
5314
5315	if (dec->process_state ==
5316	PROC_STATE_HEAD_AGAIN
5317	) {
5318	if ((start_code == I_PICTURE_START_CODE)
5319	|| (start_code == PB_PICTURE_START_CODE)) {
5320	avs2_print(dec, 0,
5321	"PROC_STATE_HEAD_AGAIN error, start_code 0x%x!!!\r\n",
5322	start_code);
5323	goto irq_handled_exit;
5324	} else {
5325	avs2_print(dec, AVS2_DBG_BUFMGR,
5326	"PROC_STATE_HEAD_AGAIN, start_code 0x%x\r\n",
5327	start_code);
5328	dec->process_state = PROC_STATE_HEAD_DONE;
5329	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5330	goto irq_handled_exit;
5331	}
5332	} else if (dec->process_state ==
5333	PROC_STATE_DECODE_AGAIN) {
5334	if ((start_code == I_PICTURE_START_CODE)
5335	|| (start_code == PB_PICTURE_START_CODE)) {
5336	avs2_print(dec, AVS2_DBG_BUFMGR,
5337	"PROC_STATE_DECODE_AGAIN=> decode_slice, start_code 0x%x\r\n",
5338	start_code);
5339	goto decode_slice;
5340	} else {
5341	avs2_print(dec, 0,
5342	"PROC_STATE_DECODE_AGAIN, start_code 0x%x!!!\r\n",
5343	start_code);
5344	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5345	goto irq_handled_exit;
5346	}
5347	}
5348
5349	if ((start_code == I_PICTURE_START_CODE)
5350	|| (start_code == PB_PICTURE_START_CODE)
5351	|| (start_code == SEQUENCE_END_CODE)
5352	|| (start_code == VIDEO_EDIT_CODE)) {
5353	PRINT_LINE();
5354
5355	if (dec->avs2_dec.hc.cur_pic != NULL) {
5356	int32_t ii;
5357	#ifdef AVS2_10B_MMU
5358	avs2_recycle_mmu_buf_tail(dec);
5359	#endif
5360	check_pic_error(dec, dec->avs2_dec.hc.cur_pic);
5361	avs2_post_process(&dec->avs2_dec);
5362
5363	if (debug & AVS2_DBG_PRINT_PIC_LIST)
5364	dump_pic_list(dec);
5365
5366	avs2_prepare_display_buf(dec);
5367	dec->avs2_dec.hc.cur_pic = NULL;
5368	for (ii = 0; ii < dec->avs2_dec.ref_maxbuffer;
5369	ii++) {
5370	if (dec->avs2_dec.fref[ii]->
5371	bg_flag == 0 &&
5372	dec->avs2_dec.fref[ii]->
5373	is_output == -1 &&
5374	dec->avs2_dec.fref[ii]->
5375	mmu_alloc_flag &&
5376	dec->avs2_dec.fref[ii]->
5377	vf_ref == 0) {
5378	struct avs2_frame_s *pic =
5379	dec->avs2_dec.fref[ii];
5380	if (dec->avs2_dec.fref[ii]->
5381	refered_by_others == 0) {
5382	#ifdef AVS2_10B_MMU
5383	dec->avs2_dec.fref[ii]->
5384	mmu_alloc_flag = 0;
5385	/*release_buffer_4k(
5386	dec->avs2_dec.fref[ii]->index);*/
5387	decoder_mmu_box_free_idx(dec->mmu_box,
5388	dec->avs2_dec.fref[ii]->index);
5389	#ifdef DYNAMIC_ALLOC_HEAD
5390	decoder_bmmu_box_free_idx(
5391	dec->bmmu_box,
5392	HEADER_BUFFER_IDX(pic->index));
5393	pic->header_adr = 0;
5394	#endif
5395	#endif
5396	#ifndef MV_USE_FIXED_BUF
5397	decoder_bmmu_box_free_idx(
5398	dec->bmmu_box,
5399	MV_BUFFER_IDX(pic->index));
5400	pic->mpred_mv_wr_start_addr = 0;
5401	#endif
5402	}
5403	decoder_bmmu_box_free_idx(
5404	dec->bmmu_box,
5405	VF_BUFFER_IDX(pic->index));
5406	dec->cma_alloc_addr = 0;
5407	}
5408	}
5409	}
5410	}
5411
5412	if ((dec_status == AVS2_HEAD_PIC_I_READY)
5413	|| (dec_status == AVS2_HEAD_PIC_PB_READY)) {
5414	PRINT_LINE();
5415
5416	if (debug & AVS2_DBG_SEND_PARAM_WITH_REG) {
5417	get_rpm_param(
5418	&dec->avs2_dec.param);
5419	} else {
5420
5421	for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
5422	int ii;
5423	for (ii = 0; ii < 4; ii++)
5424	dec->avs2_dec.param.l.data[i + ii] =
5425	dec->rpm_ptr[i + 3 - ii];
5426	}
5427	}
5428	#ifdef SANITY_CHECK
5429	if (dec->avs2_dec.param.p.num_of_ref_cur >
5430	dec->avs2_dec.ref_maxbuffer) {
5431	pr_info("Warning: Wrong num_of_ref_cur %d, force to %d\n",
5432	dec->avs2_dec.param.p.num_of_ref_cur,
5433	dec->avs2_dec.ref_maxbuffer);
5434	dec->avs2_dec.param.p.num_of_ref_cur =
5435	dec->avs2_dec.ref_maxbuffer;
5436	}
5437	#endif
5438	PRINT_LINE();
5439
5440	debug_buffer_mgr_more(dec);
5441	get_frame_rate(&dec->avs2_dec.param, dec);
5442
5443	if (dec->avs2_dec.param.p.video_signal_type
5444	& (1<<30)) {
5445	union param_u *pPara;
5446
5447	avs2_print(dec, 0,
5448	"avs2 HDR meta data present\n");
5449	pPara = &dec->avs2_dec.param;
5450
5451	/*clean this flag*/
5452	pPara->p.video_signal_type
5453	&= ~(1<<30);
5454
5455	dec->vf_dp.present_flag = 1;
5456
5457	dec->vf_dp.white_point[0]
5458	= pPara->p.white_point_x;
5459	avs2_print(dec, AVS2_DBG_HDR_INFO,
5460	"white_point[0]:0x%x\n",
5461	dec->vf_dp.white_point[0]);
5462
5463	dec->vf_dp.white_point[1]
5464	= pPara->p.white_point_y;
5465	avs2_print(dec, AVS2_DBG_HDR_INFO,
5466	"white_point[1]:0x%x\n",
5467	dec->vf_dp.white_point[1]);
5468
5469	for (i = 0; i < 3; i++) {
5470	dec->vf_dp.primaries[i][0]
5471	= pPara->p.display_primaries_x[i];
5472	avs2_print(dec, AVS2_DBG_HDR_INFO,
5473	"primaries[%d][0]:0x%x\n",
5474	i,
5475	dec->vf_dp.primaries[i][0]);
5476	}
5477
5478	for (i = 0; i < 3; i++) {
5479	dec->vf_dp.primaries[i][1]
5480	= pPara->p.display_primaries_y[i];
5481	avs2_print(dec, AVS2_DBG_HDR_INFO,
5482	"primaries[%d][1]:0x%x\n",
5483	i,
5484	dec->vf_dp.primaries[i][1]);
5485	}
5486
5487	dec->vf_dp.luminance[0]
5488	= pPara->p.max_display_mastering_luminance;
5489	avs2_print(dec, AVS2_DBG_HDR_INFO,
5490	"luminance[0]:0x%x\n",
5491	dec->vf_dp.luminance[0]);
5492
5493	dec->vf_dp.luminance[1]
5494	= pPara->p.min_display_mastering_luminance;
5495	avs2_print(dec, AVS2_DBG_HDR_INFO,
5496	"luminance[1]:0x%x\n",
5497	dec->vf_dp.luminance[1]);
5498
5499
5500	dec->vf_dp.content_light_level.present_flag
5501	= 1;
5502	dec->vf_dp.content_light_level.max_content
5503	= pPara->p.max_content_light_level;
5504	avs2_print(dec, AVS2_DBG_HDR_INFO,
5505	"max_content:0x%x\n",
5506	dec->vf_dp.content_light_level.max_content);
5507
5508	dec->vf_dp.content_light_level.max_pic_average
5509	= pPara->p.max_picture_average_light_level;
5510
5511	avs2_print(dec, AVS2_DBG_HDR_INFO,
5512	"max_pic_average:0x%x\n",
5513	dec->vf_dp.content_light_level.max_pic_average);
5514	}
5515
5516
5517	if (dec->video_ori_signal_type !=
5518	((dec->avs2_dec.param.p.video_signal_type << 16)
5519	| dec->avs2_dec.param.p.color_description)) {
5520	u32 v = dec->avs2_dec.param.p.video_signal_type;
5521	u32 c = dec->avs2_dec.param.p.color_description;
5522	u32 convert_c = c;
5523
5524	if (v & 0x2000) {
5525	avs2_print(dec, 0,
5526	"video_signal_type present:\n");
5527	avs2_print(dec, 0,
5528	" %s %s\n",
5529	video_format_names[(v >> 10) & 7],
5530	((v >> 9) & 1) ?
5531	"full_range" : "limited");
5532	if (v & 0x100) {
5533	u32 transfer;
5534	u32 maxtrix;
5535
5536	avs2_print(dec, 0,
5537	"color_description present:\n");
5538	avs2_print(dec, 0,
5539	"color_primarie = %d\n",
5540	v & 0xff);
5541	avs2_print(dec, 0,
5542	"transfer_characteristic = %d\n",
5543	(c >> 8) & 0xff);
5544	avs2_print(dec, 0,
5545	" matrix_coefficient = %d\n",
5546	c & 0xff);
5547
5548	transfer = (c >> 8) & 0xFF;
5549	if (transfer >= 15)
5550	avs2_print(dec, 0,
5551	"unsupport transfer_characteristic\n");
5552	else if (transfer == 14)
5553	transfer = 18; /* HLG */
5554	else if (transfer == 13)
5555	transfer = 32;
5556	else if (transfer == 12)
5557	transfer = 16;
5558	else if (transfer == 11)
5559	transfer = 15;
5560
5561	maxtrix = c & 0xFF;
5562	if (maxtrix >= 10)
5563	avs2_print(dec, 0,
5564	"unsupport matrix_coefficient\n");
5565	else if (maxtrix == 9)
5566	maxtrix = 10;
5567	else if (maxtrix == 8)
5568	maxtrix = 9;
5569
5570	convert_c = (transfer << 8) | (maxtrix);
5571
5572	avs2_print(dec, 0,
5573	" convered c:0x%x\n",
5574	convert_c);
5575	}
5576	}
5577
5578	if (enable_force_video_signal_type)
5579	dec->video_signal_type
5580	= force_video_signal_type;
5581	else {
5582	dec->video_signal_type
5583	= (v << 16) | convert_c;
5584
5585	dec->video_ori_signal_type
5586	= (v << 16) | c;
5587	}
5588
5589	video_signal_type = dec->video_signal_type;
5590	}
5591	}
5592	#if 0
5593	if ((debug_again & 0x4) &&
5594	dec->process_state ==
5595	PROC_STATE_INIT) {
5596	if (start_code == PB_PICTURE_START_CODE) {
5597	dec->process_state = PROC_STATE_TEST1;
5598	dec_again_process(dec);
5599	goto irq_handled_exit;
5600	}
5601	}
5602	#endif
5603	PRINT_LINE();
5604	avs2_prepare_header(&dec->avs2_dec, start_code);
5605
5606	if (start_code == SEQUENCE_HEADER_CODE ||
5607	start_code == VIDEO_EDIT_CODE ||
5608	start_code == SEQUENCE_END_CODE) {
5609	if (dec->m_ins_flag &&
5610	vdec_frame_based(hw_to_vdec(dec)))
5611	dec->start_decoding_flag |= 0x1;
5612	dec->process_state = PROC_STATE_HEAD_DONE;
5613	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5614	} else if (start_code == I_PICTURE_START_CODE ||
5615	start_code == PB_PICTURE_START_CODE) {
5616	ret = 0;
5617	if (dec->pic_list_init_flag == 0) {
5618	int32_t lcu_size_log2 =
5619	log2i(dec->avs2_dec.param.p.lcu_size);
5620
5621	avs2_init_global_buffers(&dec->avs2_dec);
5622	/*avs2_dec->m_bg->index is
5623	set to dec->used_buf_num - 1*/
5624	init_pic_list(dec, lcu_size_log2);
5625	init_pic_list_hw(dec);
5626	}
5627	ret = avs2_process_header(&dec->avs2_dec);
5628	if (!dec->m_ins_flag)
5629	dec->slice_idx++;
5630
5631	PRINT_LINE();
5632	#ifdef I_ONLY_SUPPORT
5633	if ((start_code == PB_PICTURE_START_CODE) &&
5634	(dec->i_only & 0x2))
5635	ret = -2;
5636	#endif
5637	#ifdef AVS2_10B_MMU
5638	if (ret >= 0) {
5639	ret = avs2_alloc_mmu(dec,
5640	dec->avs2_dec.hc.cur_pic->index,
5641	dec->avs2_dec.img.width,
5642	dec->avs2_dec.img.height,
5643	dec->avs2_dec.input.sample_bit_depth,
5644	dec->frame_mmu_map_addr);
5645	if (ret >= 0) {
5646	dec->cur_fb_idx_mmu =
5647	dec->avs2_dec.hc.cur_pic->index;
5648	dec->avs2_dec.hc.cur_pic->mmu_alloc_flag = 1;
5649	} else
5650	pr_err("can't alloc need mmu1,idx %d ret =%d\n",
5651	dec->avs2_dec.hc.cur_pic->index,
5652	ret);
5653	}
5654	#endif
5655
5656	#ifndef MV_USE_FIXED_BUF
5657	if (ret >= 0 &&
5658	dec->avs2_dec.hc.cur_pic->
5659	mpred_mv_wr_start_addr == 0) {
5660	unsigned long buf_addr;
5661	unsigned mv_buf_size = 0x120000;
5662	int i = dec->avs2_dec.hc.cur_pic->index;
5663	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
5664	mv_buf_size = 0x120000 * 4;
5665	if (decoder_bmmu_box_alloc_buf_phy
5666	(dec->bmmu_box,
5667	MV_BUFFER_IDX(i),
5668	mv_buf_size,
5669	DRIVER_NAME,
5670	&buf_addr) < 0)
5671	ret = -1;
5672	else
5673	dec->avs2_dec.hc.cur_pic->
5674	mpred_mv_wr_start_addr
5675	= buf_addr;
5676	}
5677	#endif
5678	if (ret < 0) {
5679	avs2_print(dec, AVS2_DBG_BUFMGR,
5680	"avs2_bufmgr_process=> %d, AVS2_10B_DISCARD_NAL\r\n",
5681	ret);
5682	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL);
5683	#ifdef AVS2_10B_MMU
5684	avs2_recycle_mmu_buf(dec);
5685	#endif
5686	if (dec->m_ins_flag) {
5687	dec->dec_result = DEC_RESULT_DONE;
5688	amhevc_stop();
5689	vdec_schedule_work(&dec->work);
5690	}
5691
5692	goto irq_handled_exit;
5693	} else {
5694	PRINT_LINE();
5695	dec->avs2_dec.hc.cur_pic->stream_offset =
5696	READ_VREG(HEVC_SHIFT_BYTE_COUNT);
5697	/*
5698	struct PIC_BUFFER_CONFIG_s *cur_pic
5699	= &cm->cur_frame->buf;
5700	cur_pic->decode_idx = dec->frame_count;
5701	*/
5702	if (!dec->m_ins_flag) {
5703	dec->frame_count++;
5704	decode_frame_count[dec->index]
5705	= dec->frame_count;
5706	}
5707	/*MULTI_INSTANCE_SUPPORT*/
5708	if (dec->chunk) {
5709	dec->avs2_dec.hc.cur_pic->pts =
5710	dec->chunk->pts;
5711	dec->avs2_dec.hc.cur_pic->pts64 =
5712	dec->chunk->pts64;
5713	}
5714	/**/
5715	dec->avs2_dec.hc.cur_pic->bit_depth
5716	= dec->avs2_dec.input.sample_bit_depth;
5717	dec->avs2_dec.hc.cur_pic->double_write_mode
5718	= get_double_write_mode(dec);
5719	decode_slice:
5720	PRINT_LINE();
5721
5722	config_mc_buffer(dec);
5723	config_mcrcc_axi_hw(dec);
5724	config_mpred_hw(dec);
5725	config_dblk_hw(dec);
5726	config_sao_hw(dec);
5727	config_alf_hw(dec);
5728	config_other_hw(dec);
5729
5730	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
5731	"=>fref0 imgtr_fwRefDistance %d, fref1 imgtr_fwRefDistance %d, dis2/dis3/dis4 %d %d %d img->tr %d\n",
5732	dec->avs2_dec.fref[0]->imgtr_fwRefDistance,
5733	dec->avs2_dec.fref[1]->imgtr_fwRefDistance,
5734	dec->avs2_dec.fref[2]->imgtr_fwRefDistance,
5735	dec->avs2_dec.fref[3]->imgtr_fwRefDistance,
5736	dec->avs2_dec.fref[4]->imgtr_fwRefDistance,
5737	dec->avs2_dec.img.tr);
5738
5739	if ((debug_again & 0x2) &&
5740	dec->process_state ==
5741	PROC_STATE_INIT) {
5742	dec->process_state = PROC_STATE_DECODING;
5743	dec_again_process(dec);
5744	goto irq_handled_exit;
5745	}
5746
5747	dec->process_state = PROC_STATE_DECODING;
5748
5749	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5750
5751	}
5752
5753	if (dec->m_ins_flag)
5754	start_process_time(dec);
5755	}
5756	irq_handled_exit:
5757	PRINT_LINE();
5758	dec->process_busy = 0;
5759	return IRQ_HANDLED;
5760	}
5761
5762	static irqreturn_t vavs2_isr(int irq, void *data)
5763	{
5764	int i;
5765	unsigned int dec_status;
5766	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data;
5767	uint debug_tag;
5768
5769	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
5770
5771	dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
5772
5773	if (!dec)
5774	return IRQ_HANDLED;
5775	if (dec->init_flag == 0)
5776	return IRQ_HANDLED;
5777	if (dec->process_busy)/*on process.*/
5778	return IRQ_HANDLED;
5779	dec->dec_status = dec_status;
5780	dec->process_busy = 1;
5781	if (debug & AVS2_DBG_IRQ_EVENT)
5782	avs2_print(dec, 0,
5783	"avs2 isr dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
5784	dec_status, READ_VREG(HEVC_PARSER_LCU_START),
5785	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
5786	READ_VREG(HEVC_STREAM_START_ADDR),
5787	READ_VREG(HEVC_STREAM_END_ADDR),
5788	READ_VREG(HEVC_STREAM_LEVEL),
5789	READ_VREG(HEVC_STREAM_WR_PTR),
5790	READ_VREG(HEVC_STREAM_RD_PTR)
5791	);
5792
5793	debug_tag = READ_HREG(DEBUG_REG1);
5794	if (debug_tag & 0x10000) {
5795	dma_sync_single_for_cpu(
5796	amports_get_dma_device(),
5797	dec->lmem_phy_addr,
5798	LMEM_BUF_SIZE,
5799	DMA_FROM_DEVICE);
5800
5801	pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
5802	for (i = 0; i < 0x400; i += 4) {
5803	int ii;
5804	if ((i & 0xf) == 0)
5805	pr_info("%03x: ", i);
5806	for (ii = 0; ii < 4; ii++) {
5807	pr_info("%04x ",
5808	dec->lmem_ptr[i + 3 - ii]);
5809	}
5810	if (((i + ii) & 0xf) == 0)
5811	pr_info("\n");
5812	}
5813
5814	if (((udebug_pause_pos & 0xffff)
5815	== (debug_tag & 0xffff)) &&
5816	(udebug_pause_decode_idx == 0 ||
5817	udebug_pause_decode_idx == dec->decode_idx) &&
5818	(udebug_pause_val == 0 ||
5819	udebug_pause_val == READ_HREG(DEBUG_REG2))) {
5820	udebug_pause_pos &= 0xffff;
5821	dec->ucode_pause_pos = udebug_pause_pos;
5822	} else if (debug_tag & 0x20000)
5823	dec->ucode_pause_pos = 0xffffffff;
5824	if (dec->ucode_pause_pos)
5825	reset_process_time(dec);
5826	else
5827	WRITE_HREG(DEBUG_REG1, 0);
5828	} else if (debug_tag != 0) {
5829	pr_info(
5830	"dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
5831	READ_HREG(DEBUG_REG2),
5832	READ_VREG(HEVC_PARSER_LCU_START));
5833	if (((udebug_pause_pos & 0xffff)
5834	== (debug_tag & 0xffff)) &&
5835	(udebug_pause_decode_idx == 0 ||
5836	udebug_pause_decode_idx == dec->decode_idx) &&
5837	(udebug_pause_val == 0 ||
5838	udebug_pause_val == READ_HREG(DEBUG_REG2))) {
5839	udebug_pause_pos &= 0xffff;
5840	dec->ucode_pause_pos = udebug_pause_pos;
5841	}
5842	if (dec->ucode_pause_pos)
5843	reset_process_time(dec);
5844	else
5845	WRITE_HREG(DEBUG_REG1, 0);
5846	dec->process_busy = 0;
5847	return IRQ_HANDLED;
5848	}
5849
5850	if (!dec->m_ins_flag) {
5851	if (dec->error_flag == 1) {
5852	dec->error_flag = 2;
5853	dec->process_busy = 0;
5854	return IRQ_HANDLED;
5855	} else if (dec->error_flag == 3) {
5856	dec->process_busy = 0;
5857	return IRQ_HANDLED;
5858	}
5859
5860	if ((dec->pic_list_init_flag) &&
5861	get_free_buf_count(dec) <= 0) {
5862	/*
5863	if (dec->wait_buf == 0)
5864	pr_info("set wait_buf to 1\r\n");
5865	*/
5866	dec->wait_buf = 1;
5867	dec->process_busy = 0;
5868	if (debug & AVS2_DBG_IRQ_EVENT)
5869	avs2_print(dec, 0, "wait_buf\n");
5870	return IRQ_HANDLED;
5871	} else if (force_disp_pic_index) {
5872	dec->process_busy = 0;
5873	return IRQ_HANDLED;
5874	}
5875	}
5876	return IRQ_WAKE_THREAD;
5877	}
5878
5879	static void vavs2_put_timer_func(unsigned long arg)
5880	{
5881	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)arg;
5882	struct timer_list *timer = &dec->timer;
5883	uint8_t empty_flag;
5884	unsigned int buf_level;
5885
5886	enum receviver_start_e state = RECEIVER_INACTIVE;
5887	if (dec->m_ins_flag) {
5888	if (hw_to_vdec(dec)->next_status
5889	== VDEC_STATUS_DISCONNECTED) {
5890	dec->dec_result = DEC_RESULT_FORCE_EXIT;
5891	vdec_schedule_work(&dec->work);
5892	avs2_print(dec, AVS2_DBG_BUFMGR,
5893	"vdec requested to be disconnected\n");
5894	return;
5895	}
5896	}
5897	if (dec->init_flag == 0) {
5898	if (dec->stat & STAT_TIMER_ARM) {
5899	timer->expires = jiffies + PUT_INTERVAL;
5900	add_timer(&dec->timer);
5901	}
5902	return;
5903	}
5904	if (dec->m_ins_flag == 0) {
5905	if (vf_get_receiver(dec->provider_name)) {
5906	state =
5907	vf_notify_receiver(dec->provider_name,
5908	VFRAME_EVENT_PROVIDER_QUREY_STATE,
5909	NULL);
5910	if ((state == RECEIVER_STATE_NULL)
5911	|| (state == RECEIVER_STATE_NONE))
5912	state = RECEIVER_INACTIVE;
5913	} else
5914	state = RECEIVER_INACTIVE;
5915
5916	empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
5917	/* error watchdog */
5918	if (empty_flag == 0) {
5919	/* decoder has input */
5920	if ((debug & AVS2_DBG_DIS_LOC_ERROR_PROC) == 0) {
5921
5922	buf_level = READ_VREG(HEVC_STREAM_LEVEL);
5923	/* receiver has no buffer to recycle */
5924	if ((state == RECEIVER_INACTIVE) &&
5925	(kfifo_is_empty(&dec->display_q) &&
5926	buf_level > 0x200)
5927	) {
5928	WRITE_VREG
5929	(HEVC_ASSIST_MBOX0_IRQ_REG,
5930	0x1);
5931	}
5932	}
5933
5934	if ((debug & AVS2_DBG_DIS_SYS_ERROR_PROC) == 0) {
5935	/* receiver has no buffer to recycle */
5936	/*if ((state == RECEIVER_INACTIVE) &&
5937	(kfifo_is_empty(&dec->display_q))) {
5938	pr_info("avs2 something error,need reset\n");
5939	}*/
5940	}
5941	}
5942	} else {
5943	if (
5944	(decode_timeout_val > 0) &&
5945	(dec->start_process_time > 0) &&
5946	((1000 * (jiffies - dec->start_process_time) / HZ)
5947	> decode_timeout_val)
5948	) {
5949	int current_lcu_idx =
5950	READ_VREG(HEVC_PARSER_LCU_START)
5951	& 0xffffff;
5952	if (dec->last_lcu_idx == current_lcu_idx) {
5953	if (dec->decode_timeout_count > 0)
5954	dec->decode_timeout_count--;
5955	if (dec->decode_timeout_count == 0) {
5956	if (input_frame_based(
5957	hw_to_vdec(dec)) ||
5958	(READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
5959	timeout_process(dec);
5960	else {
5961	avs2_print(dec, 0,
5962	"timeout & empty, again\n");
5963	dec_again_process(dec);
5964	}
5965	}
5966	} else {
5967	start_process_time(dec);
5968	dec->last_lcu_idx = current_lcu_idx;
5969	}
5970	}
5971	}
5972
5973	if ((dec->ucode_pause_pos != 0) &&
5974	(dec->ucode_pause_pos != 0xffffffff) &&
5975	udebug_pause_pos != dec->ucode_pause_pos) {
5976	dec->ucode_pause_pos = 0;
5977	WRITE_HREG(DEBUG_REG1, 0);
5978	}
5979	if (debug & AVS2_DBG_DUMP_DATA) {
5980	debug &= ~AVS2_DBG_DUMP_DATA;
5981	avs2_print(dec, 0,
5982	"%s: chunk size 0x%x off 0x%x sum 0x%x\n",
5983	__func__,
5984	dec->chunk->size,
5985	dec->chunk->offset,
5986	get_data_check_sum(dec, dec->chunk->size)
5987	);
5988	dump_data(dec, dec->chunk->size);
5989	}
5990	if (debug & AVS2_DBG_DUMP_PIC_LIST) {
5991	dump_pic_list(dec);
5992	debug &= ~AVS2_DBG_DUMP_PIC_LIST;
5993	}
5994	if (debug & AVS2_DBG_TRIG_SLICE_SEGMENT_PROC) {
5995	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
5996	debug &= ~AVS2_DBG_TRIG_SLICE_SEGMENT_PROC;
5997	}
5998	if (debug & AVS2_DBG_DUMP_RPM_BUF) {
5999	int i;
6000	pr_info("RPM:\n");
6001	for (i = 0; i < RPM_BUF_SIZE; i += 4) {
6002	int ii;
6003	if ((i & 0xf) == 0)
6004	pr_info("%03x: ", i);
6005	for (ii = 0; ii < 4; ii++) {
6006	pr_info("%04x ",
6007	dec->lmem_ptr[i + 3 - ii]);
6008	}
6009	if (((i + ii) & 0xf) == 0)
6010	pr_info("\n");
6011	}
6012	debug &= ~AVS2_DBG_DUMP_RPM_BUF;
6013	}
6014	if (debug & AVS2_DBG_DUMP_LMEM_BUF) {
6015	int i;
6016	pr_info("LMEM:\n");
6017	for (i = 0; i < LMEM_BUF_SIZE; i += 4) {
6018	int ii;
6019	if ((i & 0xf) == 0)
6020	pr_info("%03x: ", i);
6021	for (ii = 0; ii < 4; ii++) {
6022	pr_info("%04x ",
6023	dec->lmem_ptr[i + 3 - ii]);
6024	}
6025	if (((i + ii) & 0xf) == 0)
6026	pr_info("\n");
6027	}
6028	debug &= ~AVS2_DBG_DUMP_LMEM_BUF;
6029	}
6030	/*if (debug & AVS2_DBG_HW_RESET) {
6031	}*/
6032
6033	if (radr != 0) {
6034	if (rval != 0) {
6035	WRITE_VREG(radr, rval);
6036	pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6037	} else
6038	pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6039	rval = 0;
6040	radr = 0;
6041	}
6042	if (pop_shorts != 0) {
6043	int i;
6044	u32 sum = 0;
6045	pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
6046	for (i = 0; i < pop_shorts; i++) {
6047	u32 data =
6048	(READ_HREG(HEVC_SHIFTED_DATA) >> 16);
6049	WRITE_HREG(HEVC_SHIFT_COMMAND,
6050	(1<<7)|16);
6051	if ((i & 0xf) == 0)
6052	pr_info("%04x:", i);
6053	pr_info("%04x ", data);
6054	if (((i + 1) & 0xf) == 0)
6055	pr_info("\r\n");
6056	sum += data;
6057	}
6058	pr_info("\r\nsum = %x\r\n", sum);
6059	pop_shorts = 0;
6060	}
6061	if (dbg_cmd != 0) {
6062	if (dbg_cmd == 1) {
6063	u32 disp_laddr;
6064	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
6065	get_double_write_mode(dec) == 0) {
6066	disp_laddr =
6067	READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
6068	} else {
6069	struct canvas_s cur_canvas;
6070	canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
6071	& 0xff), &cur_canvas);
6072	disp_laddr = cur_canvas.addr;
6073	}
6074	pr_info("current displayed buffer address %x\r\n",
6075	disp_laddr);
6076	}
6077	dbg_cmd = 0;
6078	}
6079	/*don't changed at start.*/
6080	if (dec->get_frame_dur && dec->show_frame_num > 60 &&
6081	dec->frame_dur > 0 && dec->saved_resolution !=
6082	frame_width * frame_height *
6083	(96000 / dec->frame_dur)) {
6084	int fps = 96000 / dec->frame_dur;
6085	if (hevc_source_changed(VFORMAT_AVS2,
6086	frame_width, frame_height, fps) > 0)
6087	dec->saved_resolution = frame_width *
6088	frame_height * fps;
6089	}
6090
6091	timer->expires = jiffies + PUT_INTERVAL;
6092	add_timer(timer);
6093	}
6094
6095
6096	int vavs2_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6097	{
6098	struct AVS2Decoder_s *dec =
6099	(struct AVS2Decoder_s *)vdec->private;
6100
6101	if (!dec)
6102	return -1;
6103
6104	vstatus->frame_width = dec->frame_width;
6105	vstatus->frame_height = dec->frame_height;
6106
6107	if (dec->frame_dur != 0)
6108	vstatus->frame_rate = 96000 / dec->frame_dur;
6109	else
6110	vstatus->frame_rate = -1;
6111	vstatus->error_count = 0;
6112	vstatus->status = dec->stat | dec->fatal_error;
6113	vstatus->frame_dur = dec->frame_dur;
6114	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
6115	vstatus->bit_rate = gvs->bit_rate;
6116	vstatus->frame_data = gvs->frame_data;
6117	vstatus->total_data = gvs->total_data;
6118	vstatus->frame_count = gvs->frame_count;
6119	vstatus->error_frame_count = gvs->error_frame_count;
6120	vstatus->drop_frame_count = gvs->drop_frame_count;
6121	vstatus->total_data = gvs->total_data;
6122	vstatus->samp_cnt = gvs->samp_cnt;
6123	vstatus->offset = gvs->offset;
6124	snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6125	"%s", DRIVER_NAME);
6126	#endif
6127	return 0;
6128	}
6129
6130	int vavs2_set_isreset(struct vdec_s *vdec, int isreset)
6131	{
6132	is_reset = isreset;
6133	return 0;
6134	}
6135
6136	static void vavs2_prot_init(struct AVS2Decoder_s *dec)
6137	{
6138	unsigned int data32;
6139
6140	avs2_config_work_space_hw(dec);
6141	if (dec->pic_list_init_flag)
6142	init_pic_list_hw(dec);
6143
6144	avs2_init_decoder_hw(dec);
6145
6146	#if 1
6147	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
6148	"%s\n", __func__);
6149	data32 = READ_VREG(HEVC_STREAM_CONTROL);
6150	data32 = data32 |
6151	(1 << 0)/*stream_fetch_enable*/
6152	;
6153	WRITE_VREG(HEVC_STREAM_CONTROL, data32);
6154	#if 0
6155	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
6156	if (data32 != 0x00000100) {
6157	pr_info("avs2 prot init error %d\n", __LINE__);
6158	return;
6159	}
6160	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
6161	if (data32 != 0x00000300) {
6162	pr_info("avs2 prot init error %d\n", __LINE__);
6163	return;
6164	}
6165	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
6166	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
6167	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
6168	if (data32 != 0x12345678) {
6169	pr_info("avs2 prot init error %d\n", __LINE__);
6170	return;
6171	}
6172	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
6173	if (data32 != 0x9abcdef0) {
6174	pr_info("avs2 prot init error %d\n", __LINE__);
6175	return;
6176	}
6177	#endif
6178	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
6179	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000000);
6180	#endif
6181
6182
6183
6184	WRITE_VREG(HEVC_WAIT_FLAG, 1);
6185
6186	/* WRITE_VREG(HEVC_MPSR, 1); */
6187
6188	/* clear mailbox interrupt */
6189	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
6190
6191	/* enable mailbox interrupt */
6192	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
6193
6194	/* disable PSCALE for hardware sharing */
6195	WRITE_VREG(HEVC_PSCALE_CTRL, 0);
6196
6197	WRITE_VREG(DEBUG_REG1, 0x0);
6198	/*check vps/sps/pps/i-slice in ucode*/
6199	WRITE_VREG(NAL_SEARCH_CTL, 0x8);
6200
6201	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
6202
6203	}
6204
6205	#ifdef I_ONLY_SUPPORT
6206	static int vavs2_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6207	{
6208	struct AVS2Decoder_s *dec =
6209	(struct AVS2Decoder_s *)vdec->private;
6210	if (i_only_flag & 0x100)
6211	return 0;
6212	if (trickmode == TRICKMODE_I)
6213	dec->i_only = 0x3;
6214	else if (trickmode == TRICKMODE_NONE)
6215	dec->i_only = 0x0;
6216	return 0;
6217	}
6218	#endif
6219
6220	static int vavs2_local_init(struct AVS2Decoder_s *dec)
6221	{
6222	int i;
6223	int ret;
6224	int width, height;
6225
6226	dec->gvs = vzalloc(sizeof(struct vdec_info));
6227	if (NULL == dec->gvs) {
6228	avs2_print(dec, 0,
6229	"the struct of vdec status malloc failed.\n");
6230	return -1;
6231	}
6232	#ifdef DEBUG_PTS
6233	dec->pts_missed = 0;
6234	dec->pts_hit = 0;
6235	#endif
6236	dec->new_frame_displayed = 0;
6237	dec->last_put_idx = -1;
6238	dec->saved_resolution = 0;
6239	dec->get_frame_dur = false;
6240	on_no_keyframe_skiped = 0;
6241	width = dec->vavs2_amstream_dec_info.width;
6242	height = dec->vavs2_amstream_dec_info.height;
6243	dec->frame_dur =
6244	(dec->vavs2_amstream_dec_info.rate ==
6245	0) ? 3600 : dec->vavs2_amstream_dec_info.rate;
6246	if (width && height)
6247	dec->frame_ar = height * 0x100 / width;
6248	/*
6249	TODO:FOR VERSION
6250	*/
6251	avs2_print(dec, AVS2_DBG_BUFMGR,
6252	"avs2: ver (%d,%d) decinfo: %dx%d rate=%d\n", avs2_version,
6253	0, width, height, dec->frame_dur);
6254
6255	if (dec->frame_dur == 0)
6256	dec->frame_dur = 96000 / 24;
6257	#ifdef I_ONLY_SUPPORT
6258	if (i_only_flag & 0x100)
6259	dec->i_only = i_only_flag & 0xff;
6260	else if ((unsigned long) dec->vavs2_amstream_dec_info.param
6261	& 0x08)
6262	dec->i_only = 0x7;
6263	else
6264	dec->i_only = 0x0;
6265	#endif
6266	INIT_KFIFO(dec->display_q);
6267	INIT_KFIFO(dec->newframe_q);
6268
6269
6270	for (i = 0; i < VF_POOL_SIZE; i++) {
6271	const struct vframe_s *vf = &dec->vfpool[i];
6272	dec->vfpool[i].index = -1;
6273	kfifo_put(&dec->newframe_q, vf);
6274	}
6275
6276
6277	ret = avs2_local_init(dec);
6278
6279	return ret;
6280	}
6281
6282
6283	static s32 vavs2_init(struct vdec_s *vdec)
6284	{
6285	int ret = -1, size = -1;
6286	int fw_size = 0x1000 * 16;
6287	struct firmware_s *fw = NULL;
6288	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)vdec->private;
6289	init_timer(&dec->timer);
6290
6291	dec->stat |= STAT_TIMER_INIT;
6292	if (vavs2_local_init(dec) < 0)
6293	return -EBUSY;
6294
6295	fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6296	if (IS_ERR_OR_NULL(fw))
6297	return -ENOMEM;
6298
6299	size = get_firmware_data(VIDEO_DEC_AVS2_MMU, fw->data);
6300	if (size < 0) {
6301	pr_err("get firmware fail.\n");
6302	vfree(fw);
6303	return -1;
6304	}
6305
6306	fw->len = fw_size;
6307
6308	if (dec->m_ins_flag) {
6309	dec->timer.data = (ulong) dec;
6310	dec->timer.function = vavs2_put_timer_func;
6311	dec->timer.expires = jiffies + PUT_INTERVAL;
6312
6313	/*add_timer(&dec->timer);
6314
6315	dec->stat |= STAT_TIMER_ARM;
6316	dec->stat |= STAT_ISR_REG;*/
6317
6318	INIT_WORK(&dec->work, avs2_work);
6319	dec->fw = fw;
6320
6321	return 0;
6322	}
6323	amhevc_enable();
6324	ret = amhevc_loadmc_ex(VFORMAT_AVS2, NULL, fw->data);
6325	if (ret < 0) {
6326	amhevc_disable();
6327	vfree(fw);
6328	pr_err("AVS2: the %s fw loading failed, err: %x\n",
6329	tee_enabled() ? "TEE" : "local", ret);
6330	return -EBUSY;
6331	}
6332
6333	vfree(fw);
6334
6335	dec->stat |= STAT_MC_LOAD;
6336
6337	/* enable AMRISC side protocol */
6338	vavs2_prot_init(dec);
6339
6340	if (vdec_request_threaded_irq(VDEC_IRQ_0,
6341	vavs2_isr,
6342	vavs2_isr_thread_fn,
6343	IRQF_ONESHOT,/*run thread on this irq disabled*/
6344	"vavs2-irq", (void *)dec)) {
6345	pr_info("vavs2 irq register error.\n");
6346	amhevc_disable();
6347	return -ENOENT;
6348	}
6349
6350	dec->stat |= STAT_ISR_REG;
6351
6352	dec->provider_name = PROVIDER_NAME;
6353	vf_provider_init(&vavs2_vf_prov, PROVIDER_NAME,
6354	&vavs2_vf_provider, dec);
6355	vf_reg_provider(&vavs2_vf_prov);
6356	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
6357	if (dec->frame_dur != 0) {
6358	if (!is_reset)
6359	vf_notify_receiver(dec->provider_name,
6360	VFRAME_EVENT_PROVIDER_FR_HINT,
6361	(void *)
6362	((unsigned long)dec->frame_dur));
6363	}
6364	dec->stat |= STAT_VF_HOOK;
6365
6366	dec->timer.data = (ulong)dec;
6367	dec->timer.function = vavs2_put_timer_func;
6368	dec->timer.expires = jiffies + PUT_INTERVAL;
6369
6370
6371	add_timer(&dec->timer);
6372
6373	dec->stat |= STAT_TIMER_ARM;
6374
6375	/* dec->stat |= STAT_KTHREAD; */
6376	dec->process_busy = 0;
6377	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
6378	"%d, vavs2_init, RP=0x%x\n",
6379	__LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
6380	return 0;
6381	}
6382
6383	static int vmavs2_stop(struct AVS2Decoder_s *dec)
6384	{
6385	dec->init_flag = 0;
6386	dec->first_sc_checked = 0;
6387	if (dec->stat & STAT_TIMER_ARM) {
6388	del_timer_sync(&dec->timer);
6389	dec->stat &= ~STAT_TIMER_ARM;
6390	}
6391
6392	if (dec->stat & STAT_VF_HOOK) {
6393	if (!is_reset)
6394	vf_notify_receiver(dec->provider_name,
6395	VFRAME_EVENT_PROVIDER_FR_END_HINT,
6396	NULL);
6397
6398	vf_unreg_provider(&vavs2_vf_prov);
6399	dec->stat &= ~STAT_VF_HOOK;
6400	}
6401	avs2_local_uninit(dec);
6402	reset_process_time(dec);
6403	cancel_work_sync(&dec->work);
6404	uninit_mmu_buffers(dec);
6405	if (dec->fw) {
6406	vfree(dec->fw);
6407	dec->fw = NULL;
6408	}
6409
6410	return 0;
6411	}
6412
6413
6414	static int vavs2_stop(struct AVS2Decoder_s *dec)
6415	{
6416
6417	dec->init_flag = 0;
6418	dec->first_sc_checked = 0;
6419	if (dec->stat & STAT_VDEC_RUN) {
6420	amhevc_stop();
6421	dec->stat &= ~STAT_VDEC_RUN;
6422	}
6423
6424	if (dec->stat & STAT_ISR_REG) {
6425	if (!dec->m_ins_flag)
6426	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
6427	vdec_free_irq(VDEC_IRQ_0, (void *)dec);
6428	dec->stat &= ~STAT_ISR_REG;
6429	}
6430
6431	if (dec->stat & STAT_TIMER_ARM) {
6432	del_timer_sync(&dec->timer);
6433	dec->stat &= ~STAT_TIMER_ARM;
6434	}
6435
6436	if (dec->stat & STAT_VF_HOOK) {
6437	if (!is_reset)
6438	vf_notify_receiver(dec->provider_name,
6439	VFRAME_EVENT_PROVIDER_FR_END_HINT,
6440	NULL);
6441
6442	vf_unreg_provider(&vavs2_vf_prov);
6443	dec->stat &= ~STAT_VF_HOOK;
6444	}
6445	avs2_local_uninit(dec);
6446
6447	if (dec->m_ins_flag)
6448	cancel_work_sync(&dec->work);
6449	else
6450	amhevc_disable();
6451	uninit_mmu_buffers(dec);
6452
6453	return 0;
6454	}
6455
6456	static int amvdec_avs2_mmu_init(struct AVS2Decoder_s *dec)
6457	{
6458	int tvp_flag = vdec_secure(hw_to_vdec(dec)) ?
6459	CODEC_MM_FLAGS_TVP : 0;
6460	int buf_size = 48;
6461
6462	#ifdef AVS2_10B_MMU
6463	dec->need_cache_size = buf_size * SZ_1M;
6464	dec->sc_start_time = get_jiffies_64();
6465	dec->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
6466	dec->index, FRAME_BUFFERS,
6467	dec->need_cache_size,
6468	tvp_flag
6469	);
6470	if (!dec->mmu_box) {
6471	pr_err("avs2 alloc mmu box failed!!\n");
6472	return -1;
6473	}
6474	#endif
6475	dec->bmmu_box = decoder_bmmu_box_alloc_box(
6476	DRIVER_NAME,
6477	dec->index,
6478	MAX_BMMU_BUFFER_NUM,
6479	4 + PAGE_SHIFT,
6480	CODEC_MM_FLAGS_CMA_CLEAR |
6481	CODEC_MM_FLAGS_FOR_VDECODER |
6482	tvp_flag);
6483	if (!dec->bmmu_box) {
6484	pr_err("avs2 alloc bmmu box failed!!\n");
6485	return -1;
6486	}
6487	return 0;
6488	}
6489
6490	static int amvdec_avs2_probe(struct platform_device *pdev)
6491	{
6492	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
6493	struct BUF_s BUF[MAX_BUF_NUM];
6494	struct AVS2Decoder_s *dec = &gAVS2Decoder;
6495	int ret;
6496	pr_info("%s\n", __func__);
6497	mutex_lock(&vavs2_mutex);
6498
6499	memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
6500	memset(dec, 0, sizeof(struct AVS2Decoder_s));
6501	memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
6502
6503	dec->init_flag = 0;
6504	dec->first_sc_checked = 0;
6505	dec->eos = 0;
6506	dec->start_process_time = 0;
6507	dec->timeout_num = 0;
6508	dec->fatal_error = 0;
6509	dec->show_frame_num = 0;
6510	if (pdata == NULL) {
6511	avs2_print(dec, 0,
6512	"\namvdec_avs2 memory resource undefined.\n");
6513	mutex_unlock(&vavs2_mutex);
6514	return -EFAULT;
6515	}
6516	dec->m_ins_flag = 0;
6517	dec->platform_dev = pdev;
6518	platform_set_drvdata(pdev, pdata);
6519
6520	if (amvdec_avs2_mmu_init(dec) < 0) {
6521	mutex_unlock(&vavs2_mutex);
6522	pr_err("avs2 alloc bmmu box failed!!\n");
6523	return -1;
6524	}
6525
6526	ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID,
6527	work_buf_size, DRIVER_NAME, &pdata->mem_start);
6528	if (ret < 0) {
6529	uninit_mmu_buffers(dec);
6530	mutex_unlock(&vavs2_mutex);
6531	return ret;
6532	}
6533	dec->buf_size = work_buf_size;
6534
6535	dec->buf_start = pdata->mem_start;
6536
6537
6538	if (debug) {
6539	avs2_print(dec, 0,
6540	"===AVS2 decoder mem resource 0x%lx size 0x%x\n",
6541	pdata->mem_start, dec->buf_size);
6542	}
6543
6544	if (pdata->sys_info) {
6545	dec->vavs2_amstream_dec_info = *pdata->sys_info;
6546	dec->frame_width = dec->vavs2_amstream_dec_info.width;
6547	dec->frame_height = dec->vavs2_amstream_dec_info.height;
6548	} else {
6549	dec->vavs2_amstream_dec_info.width = 0;
6550	dec->vavs2_amstream_dec_info.height = 0;
6551	dec->vavs2_amstream_dec_info.rate = 30;
6552	}
6553	dec->cma_dev = pdata->cma_dev;
6554
6555	pdata->private = dec;
6556	pdata->dec_status = vavs2_dec_status;
6557	/*pdata->set_isreset = vavs2_set_isreset;*/
6558	is_reset = 0;
6559	if (vavs2_init(pdata) < 0) {
6560	pr_info("\namvdec_avs2 init failed.\n");
6561	avs2_local_uninit(dec);
6562	uninit_mmu_buffers(dec);
6563	pdata->dec_status = NULL;
6564	mutex_unlock(&vavs2_mutex);
6565	return -ENODEV;
6566	}
6567	/*set the max clk for smooth playing...*/
6568	hevc_source_changed(VFORMAT_AVS2,
6569	4096, 2048, 60);
6570	mutex_unlock(&vavs2_mutex);
6571
6572	return 0;
6573	}
6574
6575	static int amvdec_avs2_remove(struct platform_device *pdev)
6576	{
6577	struct AVS2Decoder_s *dec = &gAVS2Decoder;
6578	if (debug)
6579	pr_info("amvdec_avs2_remove\n");
6580
6581	mutex_lock(&vavs2_mutex);
6582
6583	vavs2_stop(dec);
6584
6585
6586	hevc_source_changed(VFORMAT_AVS2, 0, 0, 0);
6587
6588
6589	#ifdef DEBUG_PTS
6590	pr_info("pts missed %ld, pts hit %ld, duration %d\n",
6591	dec->pts_missed, dec->pts_hit, dec->frame_dur);
6592	#endif
6593
6594	mutex_unlock(&vavs2_mutex);
6595
6596	return 0;
6597	}
6598
6599	/****************************************/
6600	#ifdef CONFIG_PM
6601	static int avs2_suspend(struct device *dev)
6602	{
6603	amhevc_suspend(to_platform_device(dev), dev->power.power_state);
6604	return 0;
6605	}
6606
6607	static int avs2_resume(struct device *dev)
6608	{
6609	amhevc_resume(to_platform_device(dev));
6610	return 0;
6611	}
6612
6613	static const struct dev_pm_ops avs2_pm_ops = {
6614	SET_SYSTEM_SLEEP_PM_OPS(avs2_suspend, avs2_resume)
6615	};
6616	#endif
6617
6618	static struct platform_driver amvdec_avs2_driver = {
6619	.probe = amvdec_avs2_probe,
6620	.remove = amvdec_avs2_remove,
6621	.driver = {
6622	.name = DRIVER_NAME,
6623	#ifdef CONFIG_PM
6624	.pm = &avs2_pm_ops,
6625	#endif
6626	}
6627	};
6628
6629	static struct codec_profile_t amvdec_avs2_profile = {
6630	.name = "avs2",
6631	.profile = ""
6632	};
6633
6634	static struct codec_profile_t amvdec_avs2_profile_mult;
6635
6636	static unsigned char get_data_check_sum
6637	(struct AVS2Decoder_s *dec, int size)
6638	{
6639	int jj;
6640	int sum = 0;
6641	u8 *data = NULL;
6642
6643	if (!dec->chunk->block->is_mapped)
6644	data = codec_mm_vmap(dec->chunk->block->start +
6645	dec->chunk->offset, size);
6646	else
6647	data = ((u8 *)dec->chunk->block->start_virt) +
6648	dec->chunk->offset;
6649
6650	for (jj = 0; jj < size; jj++)
6651	sum += data[jj];
6652
6653	if (!dec->chunk->block->is_mapped)
6654	codec_mm_unmap_phyaddr(data);
6655	return sum;
6656	}
6657
6658	static void dump_data(struct AVS2Decoder_s *dec, int size)
6659	{
6660	int jj;
6661	u8 *data = NULL;
6662	int padding_size = dec->chunk->offset &
6663	(VDEC_FIFO_ALIGN - 1);
6664
6665	if (!dec->chunk->block->is_mapped)
6666	data = codec_mm_vmap(dec->chunk->block->start +
6667	dec->chunk->offset, size);
6668	else
6669	data = ((u8 *)dec->chunk->block->start_virt) +
6670	dec->chunk->offset;
6671
6672	avs2_print(dec, 0, "padding: ");
6673	for (jj = padding_size; jj > 0; jj--)
6674	avs2_print_cont(dec,
6675	0,
6676	"%02x ", *(data - jj));
6677	avs2_print_cont(dec, 0, "data adr %p\n",
6678	data);
6679
6680	for (jj = 0; jj < size; jj++) {
6681	if ((jj & 0xf) == 0)
6682	avs2_print(dec,
6683	0,
6684	"%06x:", jj);
6685	avs2_print_cont(dec,
6686	0,
6687	"%02x ", data[jj]);
6688	if (((jj + 1) & 0xf) == 0)
6689	avs2_print(dec,
6690	0,
6691	"\n");
6692	}
6693	avs2_print(dec,
6694	0,
6695	"\n");
6696
6697	if (!dec->chunk->block->is_mapped)
6698	codec_mm_unmap_phyaddr(data);
6699	}
6700
6701	static void avs2_work(struct work_struct *work)
6702	{
6703	struct AVS2Decoder_s *dec = container_of(work,
6704	struct AVS2Decoder_s, work);
6705	struct vdec_s *vdec = hw_to_vdec(dec);
6706	/* finished decoding one frame or error,
6707	* notify vdec core to switch context
6708	*/
6709	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6710	"%s dec_result %d %x %x %x\n",
6711	__func__,
6712	dec->dec_result,
6713	READ_VREG(HEVC_STREAM_LEVEL),
6714	READ_VREG(HEVC_STREAM_WR_PTR),
6715	READ_VREG(HEVC_STREAM_RD_PTR));
6716
6717	if (((dec->dec_result == DEC_RESULT_GET_DATA) ||
6718	(dec->dec_result == DEC_RESULT_GET_DATA_RETRY))
6719	&& (hw_to_vdec(dec)->next_status !=
6720	VDEC_STATUS_DISCONNECTED)) {
6721	if (!vdec_has_more_input(vdec)) {
6722	dec->dec_result = DEC_RESULT_EOS;
6723	vdec_schedule_work(&dec->work);
6724	return;
6725	}
6726
6727	if (dec->dec_result == DEC_RESULT_GET_DATA) {
6728	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6729	"%s DEC_RESULT_GET_DATA %x %x %x\n",
6730	__func__,
6731	READ_VREG(HEVC_STREAM_LEVEL),
6732	READ_VREG(HEVC_STREAM_WR_PTR),
6733	READ_VREG(HEVC_STREAM_RD_PTR));
6734	vdec_vframe_dirty(vdec, dec->chunk);
6735	vdec_clean_input(vdec);
6736	}
6737
6738	if (get_free_buf_count(dec) >=
6739	run_ready_min_buf_num) {
6740	int r;
6741	int decode_size;
6742	r = vdec_prepare_input(vdec, &dec->chunk);
6743	if (r < 0) {
6744	dec->dec_result = DEC_RESULT_GET_DATA_RETRY;
6745
6746	avs2_print(dec,
6747	PRINT_FLAG_VDEC_DETAIL,
6748	"amvdec_vh265: Insufficient data\n");
6749
6750	vdec_schedule_work(&dec->work);
6751	return;
6752	}
6753	dec->dec_result = DEC_RESULT_NONE;
6754	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6755	"%s: chunk size 0x%x sum 0x%x\n",
6756	__func__, r,
6757	(debug & PRINT_FLAG_VDEC_STATUS) ?
6758	get_data_check_sum(dec, r) : 0
6759	);
6760	if (debug & PRINT_FLAG_VDEC_DATA)
6761	dump_data(dec, dec->chunk->size);
6762
6763	decode_size = dec->chunk->size +
6764	(dec->chunk->offset & (VDEC_FIFO_ALIGN - 1));
6765
6766	WRITE_VREG(HEVC_DECODE_SIZE,
6767	READ_VREG(HEVC_DECODE_SIZE) + decode_size);
6768
6769	vdec_enable_input(vdec);
6770
6771	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
6772
6773	start_process_time(dec);
6774
6775	} else{
6776	dec->dec_result = DEC_RESULT_GET_DATA_RETRY;
6777
6778	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6779	"amvdec_vh265: Insufficient data\n");
6780
6781	vdec_schedule_work(&dec->work);
6782	}
6783	return;
6784	} else if (dec->dec_result == DEC_RESULT_DONE) {
6785	/* if (!dec->ctx_valid)
6786	dec->ctx_valid = 1; */
6787	dec->slice_idx++;
6788	dec->frame_count++;
6789	dec->process_state = PROC_STATE_INIT;
6790	decode_frame_count[dec->index] = dec->frame_count;
6791
6792	#ifdef AVS2_10B_MMU
6793	dec->used_4k_num =
6794	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
6795	#endif
6796	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6797	"%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
6798	__func__,
6799	dec->frame_count,
6800	dec->dec_result,
6801	READ_VREG(HEVC_STREAM_LEVEL),
6802	READ_VREG(HEVC_STREAM_WR_PTR),
6803	READ_VREG(HEVC_STREAM_RD_PTR),
6804	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
6805	READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
6806	dec->start_shift_bytes
6807	);
6808	vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk);
6809	} else if (dec->dec_result == DEC_RESULT_AGAIN) {
6810	/*
6811	stream base: stream buf empty or timeout
6812	frame base: vdec_prepare_input fail
6813	*/
6814	if (!vdec_has_more_input(vdec)) {
6815	dec->dec_result = DEC_RESULT_EOS;
6816	vdec_schedule_work(&dec->work);
6817	return;
6818	}
6819	} else if (dec->dec_result == DEC_RESULT_EOS) {
6820	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6821	"%s: end of stream\n",
6822	__func__);
6823	dec->eos = 1;
6824	check_pic_error(dec, dec->avs2_dec.hc.cur_pic);
6825	avs2_post_process(&dec->avs2_dec);
6826	avs2_prepare_display_buf(dec);
6827	vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk);
6828	} else if (dec->dec_result == DEC_RESULT_FORCE_EXIT) {
6829	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6830	"%s: force exit\n",
6831	__func__);
6832	if (dec->stat & STAT_VDEC_RUN) {
6833	amhevc_stop();
6834	dec->stat &= ~STAT_VDEC_RUN;
6835	}
6836
6837	if (dec->stat & STAT_ISR_REG) {
6838	if (!dec->m_ins_flag)
6839	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
6840	vdec_free_irq(VDEC_IRQ_0, (void *)dec);
6841	dec->stat &= ~STAT_ISR_REG;
6842	}
6843	}
6844
6845	if (dec->stat & STAT_TIMER_ARM) {
6846	del_timer_sync(&dec->timer);
6847	dec->stat &= ~STAT_TIMER_ARM;
6848	}
6849	/* mark itself has all HW resource released and input released */
6850	if (vdec->parallel_dec ==1)
6851	vdec_core_finish_run(vdec, CORE_MASK_HEVC);
6852	else
6853	vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
6854
6855	if (dec->vdec_cb)
6856	dec->vdec_cb(hw_to_vdec(dec), dec->vdec_cb_arg);
6857	}
6858
6859	static int avs2_hw_ctx_restore(struct AVS2Decoder_s *dec)
6860	{
6861	/* new to do ... */
6862	vavs2_prot_init(dec);
6863	return 0;
6864	}
6865
6866	static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
6867	{
6868	struct AVS2Decoder_s *dec =
6869	(struct AVS2Decoder_s *)vdec->private;
6870	int tvp = vdec_secure(hw_to_vdec(dec)) ?
6871	CODEC_MM_FLAGS_TVP : 0;
6872	unsigned long ret = 0;
6873	avs2_print(dec,
6874	PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
6875	if (debug & AVS2_DBG_PIC_LEAK_WAIT)
6876	return ret;
6877
6878	if (dec->eos)
6879	return ret;
6880	if (!dec->first_sc_checked) {
6881	int size = decoder_mmu_box_sc_check(dec->mmu_box, tvp);
6882	dec->first_sc_checked = 1;
6883	avs2_print(dec, 0, "vavs2 cached=%d need_size=%d speed= %d ms\n",
6884	size, (dec->need_cache_size >> PAGE_SHIFT),
6885	(int)(get_jiffies_64() - dec->sc_start_time) * 1000/HZ);
6886	}
6887
6888	if (dec->next_again_flag &&
6889	(!vdec_frame_based(vdec))) {
6890	u32 parser_wr_ptr =
6891	READ_PARSER_REG(PARSER_VIDEO_WP);
6892	if (parser_wr_ptr >= dec->pre_parser_wr_ptr &&
6893	(parser_wr_ptr - dec->pre_parser_wr_ptr) <
6894	again_threshold) {
6895	int r = vdec_sync_input(vdec);
6896	avs2_print(dec,
6897	PRINT_FLAG_VDEC_DETAIL, "%s buf lelvel:%x\n", __func__, r);
6898	return 0;
6899	}
6900	}
6901	/*
6902	if (vdec_stream_based(vdec) && (dec->pic_list_init_flag == 0)
6903	&& pre_decode_buf_level != 0) {
6904	u32 rp, wp, level;
6905
6906	rp = READ_PARSER_REG(PARSER_VIDEO_RP);
6907	wp = READ_PARSER_REG(PARSER_VIDEO_WP);
6908	if (wp < rp)
6909	level = vdec->input.size + wp - rp;
6910	else
6911	level = wp - rp;
6912
6913	if (level < pre_decode_buf_level)
6914	return 0;
6915	}
6916	*/
6917
6918	if ((dec->pic_list_init_flag == 0) ||
6919	get_free_buf_count(dec) >=
6920	run_ready_min_buf_num)
6921	ret = 1;
6922	#ifdef CONSTRAIN_MAX_BUF_NUM
6923	if (dec->pic_list_init_flag) {
6924	if (run_ready_max_vf_only_num > 0 &&
6925	get_vf_ref_only_buf_count(dec) >=
6926	run_ready_max_vf_only_num
6927	)
6928	ret = 0;
6929	if (run_ready_display_q_num > 0 &&
6930	kfifo_len(&dec->display_q) >=
6931	run_ready_display_q_num)
6932	ret = 0;
6933
6934	if (run_ready_max_buf_num == 0xff &&
6935	get_used_buf_count(dec) >=
6936	dec->avs2_dec.ref_maxbuffer)
6937	ret = 0;
6938	else if (run_ready_max_buf_num &&
6939	get_used_buf_count(dec) >=
6940	run_ready_max_buf_num)
6941	ret = 0;
6942	}
6943	#endif
6944	if (ret)
6945	not_run_ready[dec->index] = 0;
6946	else
6947	not_run_ready[dec->index]++;
6948
6949	if (vdec->parallel_dec == 1)
6950	return ret ? CORE_MASK_HEVC : 0;
6951	else
6952	return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
6953	}
6954
6955	static void run(struct vdec_s *vdec, unsigned long mask,
6956	void (*callback)(struct vdec_s *, void *), void *arg)
6957	{
6958	struct AVS2Decoder_s *dec =
6959	(struct AVS2Decoder_s *)vdec->private;
6960	int r;
6961
6962	run_count[dec->index]++;
6963	dec->vdec_cb_arg = arg;
6964	dec->vdec_cb = callback;
6965	/* dec->chunk = vdec_prepare_input(vdec); */
6966	hevc_reset_core(vdec);
6967	dec->pre_parser_wr_ptr =
6968	READ_PARSER_REG(PARSER_VIDEO_WP);
6969	dec->next_again_flag = 0;
6970
6971	r = vdec_prepare_input(vdec, &dec->chunk);
6972	if (r < 0) {
6973	input_empty[dec->index]++;
6974
6975	dec->dec_result = DEC_RESULT_AGAIN;
6976
6977	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6978	"ammvdec_vh265: Insufficient data\n");
6979
6980	vdec_schedule_work(&dec->work);
6981	return;
6982	}
6983	input_empty[dec->index] = 0;
6984	dec->dec_result = DEC_RESULT_NONE;
6985	dec->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
6986
6987	if (debug & PRINT_FLAG_VDEC_STATUS) {
6988	int ii;
6989	avs2_print(dec, 0,
6990	"%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
6991	__func__,
6992	dec->frame_count, r,
6993	dec->chunk ? dec->chunk->size : 0,
6994	dec->chunk ? dec->chunk->offset : 0,
6995	dec->chunk ? ((vdec_frame_based(vdec) &&
6996	(debug & PRINT_FLAG_VDEC_STATUS)) ?
6997	get_data_check_sum(dec, r) : 0) : 0,
6998	READ_VREG(HEVC_STREAM_START_ADDR),
6999	READ_VREG(HEVC_STREAM_END_ADDR),
7000	READ_VREG(HEVC_STREAM_LEVEL),
7001	READ_VREG(HEVC_STREAM_WR_PTR),
7002	READ_VREG(HEVC_STREAM_RD_PTR),
7003	dec->start_shift_bytes);
7004	if (vdec_frame_based(vdec) && dec->chunk) {
7005	u8 *data = NULL;
7006	if (!dec->chunk->block->is_mapped)
7007	data = codec_mm_vmap(dec->chunk->block->start +
7008	dec->chunk->offset, 8);
7009	else
7010	data = ((u8 *)dec->chunk->block->start_virt) +
7011	dec->chunk->offset;
7012
7013	avs2_print_cont(dec, 0, "data adr %p:",
7014	data);
7015	for (ii = 0; ii < 8; ii++)
7016	avs2_print_cont(dec, 0, "%02x ",
7017	data[ii]);
7018	if (!dec->chunk->block->is_mapped)
7019	codec_mm_unmap_phyaddr(data);
7020	}
7021	avs2_print_cont(dec, 0, "\r\n");
7022	}
7023	if (vdec->mc_loaded) {
7024	/*firmware have load before,
7025	and not changes to another.
7026	ignore reload.
7027	*/
7028	} else if (amhevc_loadmc_ex(VFORMAT_AVS2, NULL, dec->fw->data) < 0) {
7029	vdec->mc_loaded = 0;
7030	amhevc_disable();
7031	avs2_print(dec, 0,
7032	"%s: Error amvdec_loadmc fail\n", __func__);
7033	dec->dec_result = DEC_RESULT_FORCE_EXIT;
7034	vdec_schedule_work(&dec->work);
7035	return;
7036	} else {
7037	vdec->mc_loaded = 1;
7038	vdec->mc_type = VFORMAT_AVS2;
7039	}
7040
7041
7042	if (avs2_hw_ctx_restore(dec) < 0) {
7043	vdec_schedule_work(&dec->work);
7044	return;
7045	}
7046
7047	vdec_enable_input(vdec);
7048
7049	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_SEARCH_NEW_PIC);
7050
7051	if (vdec_frame_based(vdec) && dec->chunk) {
7052	if (debug & PRINT_FLAG_VDEC_DATA)
7053	dump_data(dec, dec->chunk->size);
7054
7055	WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
7056	r = dec->chunk->size +
7057	(dec->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7058	}
7059
7060	WRITE_VREG(HEVC_DECODE_SIZE, r);
7061	WRITE_VREG(HEVC_DECODE_COUNT, dec->slice_idx);
7062	dec->init_flag = 1;
7063
7064	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
7065	"%s: start hevc (%x %x %x)\n",
7066	__func__,
7067	READ_VREG(HEVC_DEC_STATUS_REG),
7068	READ_VREG(HEVC_MPC_E),
7069	READ_VREG(HEVC_MPSR));
7070
7071	start_process_time(dec);
7072	mod_timer(&dec->timer, jiffies);
7073	dec->stat |= STAT_TIMER_ARM;
7074	dec->stat |= STAT_ISR_REG;
7075	amhevc_start();
7076	dec->stat |= STAT_VDEC_RUN;
7077	}
7078
7079	static void reset(struct vdec_s *vdec)
7080	{
7081
7082	struct AVS2Decoder_s *dec =
7083	(struct AVS2Decoder_s *)vdec->private;
7084
7085	avs2_print(dec,
7086	PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
7087
7088	}
7089
7090	static irqreturn_t avs2_irq_cb(struct vdec_s *vdec, int irq)
7091	{
7092	struct AVS2Decoder_s *dec =
7093	(struct AVS2Decoder_s *)vdec->private;
7094	return vavs2_isr(0, dec);
7095	}
7096
7097	static irqreturn_t avs2_threaded_irq_cb(struct vdec_s *vdec, int irq)
7098	{
7099	struct AVS2Decoder_s *dec =
7100	(struct AVS2Decoder_s *)vdec->private;
7101	return vavs2_isr_thread_fn(0, dec);
7102	}
7103
7104	static void avs2_dump_state(struct vdec_s *vdec)
7105	{
7106	struct AVS2Decoder_s *dec =
7107	(struct AVS2Decoder_s *)vdec->private;
7108	int i;
7109	avs2_print(dec, 0, "====== %s\n", __func__);
7110
7111	avs2_print(dec, 0,
7112	"width/height (%d/%d), used_buf_num %d\n",
7113	dec->avs2_dec.img.width,
7114	dec->avs2_dec.img.height,
7115	dec->used_buf_num
7116	);
7117
7118	avs2_print(dec, 0,
7119	"is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
7120	input_frame_based(vdec),
7121	dec->eos,
7122	dec->dec_result,
7123	decode_frame_count[dec->index],
7124	display_frame_count[dec->index],
7125	run_count[dec->index],
7126	not_run_ready[dec->index],
7127	input_empty[dec->index]
7128	);
7129
7130	if (vf_get_receiver(vdec->vf_provider_name)) {
7131	enum receviver_start_e state =
7132	vf_notify_receiver(vdec->vf_provider_name,
7133	VFRAME_EVENT_PROVIDER_QUREY_STATE,
7134	NULL);
7135	avs2_print(dec, 0,
7136	"\nreceiver(%s) state %d\n",
7137	vdec->vf_provider_name,
7138	state);
7139	}
7140
7141	avs2_print(dec, 0,
7142	"%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
7143	__func__,
7144	kfifo_len(&dec->newframe_q),
7145	VF_POOL_SIZE,
7146	kfifo_len(&dec->display_q),
7147	VF_POOL_SIZE,
7148	dec->vf_pre_count,
7149	dec->vf_get_count,
7150	dec->vf_put_count,
7151	get_free_buf_count(dec),
7152	run_ready_min_buf_num
7153	);
7154
7155	dump_pic_list(dec);
7156
7157	for (i = 0; i < MAX_BUF_NUM; i++) {
7158	avs2_print(dec, 0,
7159	"mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
7160	i,
7161	dec->m_mv_BUF[i].start_adr,
7162	dec->m_mv_BUF[i].size,
7163	dec->m_mv_BUF[i].used_flag);
7164	}
7165
7166	avs2_print(dec, 0,
7167	"HEVC_DEC_STATUS_REG=0x%x\n",
7168	READ_VREG(HEVC_DEC_STATUS_REG));
7169	avs2_print(dec, 0,
7170	"HEVC_MPC_E=0x%x\n",
7171	READ_VREG(HEVC_MPC_E));
7172	avs2_print(dec, 0,
7173	"DECODE_MODE=0x%x\n",
7174	READ_VREG(DECODE_MODE));
7175	avs2_print(dec, 0,
7176	"NAL_SEARCH_CTL=0x%x\n",
7177	READ_VREG(NAL_SEARCH_CTL));
7178	avs2_print(dec, 0,
7179	"HEVC_PARSER_LCU_START=0x%x\n",
7180	READ_VREG(HEVC_PARSER_LCU_START));
7181	avs2_print(dec, 0,
7182	"HEVC_DECODE_SIZE=0x%x\n",
7183	READ_VREG(HEVC_DECODE_SIZE));
7184	avs2_print(dec, 0,
7185	"HEVC_SHIFT_BYTE_COUNT=0x%x\n",
7186	READ_VREG(HEVC_SHIFT_BYTE_COUNT));
7187	avs2_print(dec, 0,
7188	"HEVC_STREAM_START_ADDR=0x%x\n",
7189	READ_VREG(HEVC_STREAM_START_ADDR));
7190	avs2_print(dec, 0,
7191	"HEVC_STREAM_END_ADDR=0x%x\n",
7192	READ_VREG(HEVC_STREAM_END_ADDR));
7193	avs2_print(dec, 0,
7194	"HEVC_STREAM_LEVEL=0x%x\n",
7195	READ_VREG(HEVC_STREAM_LEVEL));
7196	avs2_print(dec, 0,
7197	"HEVC_STREAM_WR_PTR=0x%x\n",
7198	READ_VREG(HEVC_STREAM_WR_PTR));
7199	avs2_print(dec, 0,
7200	"HEVC_STREAM_RD_PTR=0x%x\n",
7201	READ_VREG(HEVC_STREAM_RD_PTR));
7202	avs2_print(dec, 0,
7203	"PARSER_VIDEO_RP=0x%x\n",
7204	READ_PARSER_REG(PARSER_VIDEO_RP));
7205	avs2_print(dec, 0,
7206	"PARSER_VIDEO_WP=0x%x\n",
7207	READ_PARSER_REG(PARSER_VIDEO_WP));
7208
7209	if (input_frame_based(vdec) &&
7210	(debug & PRINT_FLAG_VDEC_DATA)
7211	) {
7212	int jj;
7213	if (dec->chunk && dec->chunk->block &&
7214	dec->chunk->size > 0) {
7215	u8 *data = NULL;
7216	if (!dec->chunk->block->is_mapped)
7217	data = codec_mm_vmap(dec->chunk->block->start +
7218	dec->chunk->offset, dec->chunk->size);
7219	else
7220	data = ((u8 *)dec->chunk->block->start_virt) +
7221	dec->chunk->offset;
7222	avs2_print(dec, 0,
7223	"frame data size 0x%x\n",
7224	dec->chunk->size);
7225	for (jj = 0; jj < dec->chunk->size; jj++) {
7226	if ((jj & 0xf) == 0)
7227	avs2_print(dec, 0,
7228	"%06x:", jj);
7229	avs2_print_cont(dec, 0,
7230	"%02x ", data[jj]);
7231	if (((jj + 1) & 0xf) == 0)
7232	avs2_print_cont(dec, 0,
7233	"\n");
7234	}
7235
7236	if (!dec->chunk->block->is_mapped)
7237	codec_mm_unmap_phyaddr(data);
7238	}
7239	}
7240
7241	}
7242
7243	static int ammvdec_avs2_probe(struct platform_device *pdev)
7244	{
7245	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
7246	int ret;
7247	int config_val;
7248	struct vframe_content_light_level_s content_light_level;
7249	struct vframe_master_display_colour_s vf_dp;
7250
7251	struct BUF_s BUF[MAX_BUF_NUM];
7252	struct AVS2Decoder_s *dec = NULL;
7253	pr_info("%s\n", __func__);
7254	if (pdata == NULL) {
7255	pr_info("\nammvdec_avs2 memory resource undefined.\n");
7256	return -EFAULT;
7257	}
7258	/*dec = (struct AVS2Decoder_s *)devm_kzalloc(&pdev->dev,
7259	sizeof(struct AVS2Decoder_s), GFP_KERNEL);*/
7260	memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
7261	dec = vmalloc(sizeof(struct AVS2Decoder_s));
7262	memset(dec, 0, sizeof(struct AVS2Decoder_s));
7263	if (dec == NULL) {
7264	pr_info("\nammvdec_avs2 device data allocation failed\n");
7265	return -ENOMEM;
7266	}
7267	if (pdata->parallel_dec == 1) {
7268	int i;
7269	for (i = 0; i < AVS2_MAX_BUFFER_NUM; i++) {
7270	dec->avs2_dec.frm_pool[i].y_canvas_index = -1;
7271	dec->avs2_dec.frm_pool[i].uv_canvas_index = -1;
7272	}
7273	}
7274	pdata->private = dec;
7275	pdata->dec_status = vavs2_dec_status;
7276	#ifdef I_ONLY_SUPPORT
7277	pdata->set_trickmode = vavs2_set_trickmode;
7278	#endif
7279	pdata->run_ready = run_ready;
7280	pdata->run = run;
7281	pdata->reset = reset;
7282	pdata->irq_handler = avs2_irq_cb;
7283	pdata->threaded_irq_handler = avs2_threaded_irq_cb;
7284	pdata->dump_state = avs2_dump_state;
7285
7286	memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
7287	memset(dec, 0, sizeof(struct AVS2Decoder_s));
7288	memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
7289
7290	dec->index = pdev->id;
7291	dec->m_ins_flag = 1;
7292
7293	if (pdata->use_vfm_path) {
7294	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
7295	VFM_DEC_PROVIDER_NAME);
7296	dec->frameinfo_enable = 1;
7297	} else
7298	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
7299	MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
7300
7301	vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
7302	&vavs2_vf_provider, dec);
7303
7304	dec->provider_name = pdata->vf_provider_name;
7305	platform_set_drvdata(pdev, pdata);
7306
7307	dec->platform_dev = pdev;
7308	dec->video_signal_type = 0;
7309	dec->video_ori_signal_type = 0;
7310	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
7311	dec->stat |= VP9_TRIGGER_FRAME_ENABLE;
7312	#if 1
7313	if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
7314	pdata->config && pdata->config_len) {
7315	/*use ptr config for doubel_write_mode, etc*/
7316	avs2_print(dec, 0, "pdata->config=%s\n", pdata->config);
7317	if (get_config_int(pdata->config, "avs2_double_write_mode",
7318	&config_val) == 0)
7319	dec->double_write_mode = config_val;
7320	else
7321	dec->double_write_mode = double_write_mode;
7322
7323	if (get_config_int(pdata->config, "parm_v4l_buffer_margin",
7324	&config_val) == 0)
7325	dec->dynamic_buf_margin = config_val;
7326	else
7327	dec->dynamic_buf_margin = 0;
7328
7329	if (get_config_int(pdata->config, "HDRStaticInfo",
7330	&vf_dp.present_flag) == 0
7331	&& vf_dp.present_flag == 1) {
7332	get_config_int(pdata->config, "mG.x",
7333	&vf_dp.primaries[0][0]);
7334	get_config_int(pdata->config, "mG.y",
7335	&vf_dp.primaries[0][1]);
7336	get_config_int(pdata->config, "mB.x",
7337	&vf_dp.primaries[1][0]);
7338	get_config_int(pdata->config, "mB.y",
7339	&vf_dp.primaries[1][1]);
7340	get_config_int(pdata->config, "mR.x",
7341	&vf_dp.primaries[2][0]);
7342	get_config_int(pdata->config, "mR.y",
7343	&vf_dp.primaries[2][1]);
7344	get_config_int(pdata->config, "mW.x",
7345	&vf_dp.white_point[0]);
7346	get_config_int(pdata->config, "mW.y",
7347	&vf_dp.white_point[1]);
7348	get_config_int(pdata->config, "mMaxDL",
7349	&vf_dp.luminance[0]);
7350	get_config_int(pdata->config, "mMinDL",
7351	&vf_dp.luminance[1]);
7352	vf_dp.content_light_level.present_flag = 1;
7353	get_config_int(pdata->config, "mMaxCLL",
7354	&content_light_level.max_content);
7355	get_config_int(pdata->config, "mMaxFALL",
7356	&content_light_level.max_pic_average);
7357	vf_dp.content_light_level = content_light_level;
7358	dec->video_signal_type = (1 << 29)
7359	| (5 << 26) /* unspecified */
7360	| (0 << 25) /* limit */
7361	| (1 << 24) /* color available */
7362	| (9 << 16) /* 2020 */
7363	| (16 << 8) /* 2084 */
7364	| (9 << 0); /* 2020 */
7365	}
7366	dec->vf_dp = vf_dp;
7367	} else
7368	#endif
7369	{
7370	/*dec->vavs2_amstream_dec_info.width = 0;
7371	dec->vavs2_amstream_dec_info.height = 0;
7372	dec->vavs2_amstream_dec_info.rate = 30;*/
7373	dec->double_write_mode = double_write_mode;
7374	dec->dynamic_buf_margin = dynamic_buf_num_margin;
7375	}
7376	video_signal_type = dec->video_signal_type;
7377
7378	#if 0
7379	dec->buf_start = pdata->mem_start;
7380	dec->buf_size = pdata->mem_end - pdata->mem_start + 1;
7381	#else
7382	if (amvdec_avs2_mmu_init(dec) < 0) {
7383	pr_err("avs2 alloc bmmu box failed!!\n");
7384	/* devm_kfree(&pdev->dev, (void *)dec); */
7385	vfree((void *)dec);
7386	return -1;
7387	}
7388	dec->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
7389	ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID,
7390	dec->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
7391	&dec->cma_alloc_addr);
7392	if (ret < 0) {
7393	uninit_mmu_buffers(dec);
7394	/* devm_kfree(&pdev->dev, (void *)dec); */
7395	vfree((void *)dec);
7396	return ret;
7397	}
7398	dec->buf_start = dec->cma_alloc_addr;
7399	dec->buf_size = work_buf_size;
7400	#endif
7401	dec->init_flag = 0;
7402	dec->first_sc_checked = 0;
7403	dec->fatal_error = 0;
7404	dec->show_frame_num = 0;
7405	if (pdata == NULL) {
7406	pr_info("\namvdec_avs2 memory resource undefined.\n");
7407	uninit_mmu_buffers(dec);
7408	/* devm_kfree(&pdev->dev, (void *)dec); */
7409	vfree((void *)dec);
7410	return -EFAULT;
7411	}
7412
7413	if (debug) {
7414	pr_info("===AVS2 decoder mem resource 0x%lx size 0x%x\n",
7415	dec->buf_start,
7416	dec->buf_size);
7417	}
7418
7419	if (pdata->sys_info) {
7420	dec->vavs2_amstream_dec_info = *pdata->sys_info;
7421	dec->frame_width = dec->vavs2_amstream_dec_info.width;
7422	dec->frame_height = dec->vavs2_amstream_dec_info.height;
7423	} else {
7424	dec->vavs2_amstream_dec_info.width = 0;
7425	dec->vavs2_amstream_dec_info.height = 0;
7426	dec->vavs2_amstream_dec_info.rate = 30;
7427	}
7428
7429	dec->cma_dev = pdata->cma_dev;
7430	if (vavs2_init(pdata) < 0) {
7431	pr_info("\namvdec_avs2 init failed.\n");
7432	avs2_local_uninit(dec);
7433	uninit_mmu_buffers(dec);
7434	/* devm_kfree(&pdev->dev, (void *)dec); */
7435	vfree((void *)dec);
7436	pdata->dec_status = NULL;
7437	return -ENODEV;
7438	}
7439	vdec_set_prepare_level(pdata, start_decode_buf_level);
7440	hevc_source_changed(VFORMAT_AVS2,
7441	4096, 2048, 60);
7442	if (pdata->parallel_dec == 1)
7443	vdec_core_request(pdata, CORE_MASK_HEVC);
7444	else {
7445	vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
7446	| CORE_MASK_COMBINE);
7447	}
7448
7449	return 0;
7450	}
7451
7452	static int ammvdec_avs2_remove(struct platform_device *pdev)
7453	{
7454	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)
7455	(((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
7456	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
7457	int i;
7458
7459	if (debug)
7460	pr_info("amvdec_avs2_remove\n");
7461
7462	vmavs2_stop(dec);
7463
7464	if (pdata->parallel_dec == 1)
7465	vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC);
7466	else
7467	vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC);
7468
7469	vdec_set_status(hw_to_vdec(dec), VDEC_STATUS_DISCONNECTED);
7470	if (pdata->parallel_dec == 1) {
7471	for (i = 0; i < AVS2_MAX_BUFFER_NUM; i++) {
7472	pdata->free_canvas_ex(dec->avs2_dec.frm_pool[i].y_canvas_index, pdata->id);
7473	pdata->free_canvas_ex(dec->avs2_dec.frm_pool[i].uv_canvas_index, pdata->id);
7474	}
7475	}
7476
7477
7478	#ifdef DEBUG_PTS
7479	pr_info("pts missed %ld, pts hit %ld, duration %d\n",
7480	dec->pts_missed, dec->pts_hit, dec->frame_dur);
7481	#endif
7482	/* devm_kfree(&pdev->dev, (void *)dec); */
7483	vfree((void *)dec);
7484	return 0;
7485	}
7486
7487	static struct platform_driver ammvdec_avs2_driver = {
7488	.probe = ammvdec_avs2_probe,
7489	.remove = ammvdec_avs2_remove,
7490	.driver = {
7491	.name = MULTI_DRIVER_NAME,
7492	#ifdef CONFIG_PM
7493	.pm = &avs2_pm_ops,
7494	#endif
7495	}
7496	};
7497	#endif
7498	static struct mconfig avs2_configs[] = {
7499	MC_PU32("bit_depth_luma", &bit_depth_luma),
7500	MC_PU32("bit_depth_chroma", &bit_depth_chroma),
7501	MC_PU32("frame_width", &frame_width),
7502	MC_PU32("frame_height", &frame_height),
7503	MC_PU32("debug", &debug),
7504	MC_PU32("radr", &radr),
7505	MC_PU32("rval", &rval),
7506	MC_PU32("pop_shorts", &pop_shorts),
7507	MC_PU32("dbg_cmd", &dbg_cmd),
7508	MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
7509	MC_PU32("endian", &endian),
7510	MC_PU32("step", &step),
7511	MC_PU32("udebug_flag", &udebug_flag),
7512	MC_PU32("decode_pic_begin", &decode_pic_begin),
7513	MC_PU32("slice_parse_begin", &slice_parse_begin),
7514	MC_PU32("i_only_flag", &i_only_flag),
7515	MC_PU32("error_handle_policy", &error_handle_policy),
7516	MC_PU32("buf_alloc_width", &buf_alloc_width),
7517	MC_PU32("buf_alloc_height", &buf_alloc_height),
7518	MC_PU32("buf_alloc_depth", &buf_alloc_depth),
7519	MC_PU32("buf_alloc_size", &buf_alloc_size),
7520	MC_PU32("buffer_mode", &buffer_mode),
7521	MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
7522	MC_PU32("max_buf_num", &max_buf_num),
7523	MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
7524	MC_PU32("mem_map_mode", &mem_map_mode),
7525	MC_PU32("double_write_mode", &double_write_mode),
7526	MC_PU32("enable_mem_saving", &enable_mem_saving),
7527	MC_PU32("force_w_h", &force_w_h),
7528	MC_PU32("force_fps", &force_fps),
7529	MC_PU32("max_decoding_time", &max_decoding_time),
7530	MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
7531	MC_PU32("start_decode_buf_level", &start_decode_buf_level),
7532	MC_PU32("decode_timeout_val", &decode_timeout_val),
7533	};
7534	static struct mconfig_node avs2_node;
7535
7536	static int __init amvdec_avs2_driver_init_module(void)
7537	{
7538
7539	#ifdef AVS2_10B_MMU
7540
7541	struct BuffInfo_s *p_buf_info;
7542
7543	if (vdec_is_support_4k()) {
7544	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7545	p_buf_info = &amvavs2_workbuff_spec[2];
7546	else
7547	p_buf_info = &amvavs2_workbuff_spec[1];
7548	} else
7549	p_buf_info = &amvavs2_workbuff_spec[0];
7550
7551	init_buff_spec(NULL, p_buf_info);
7552	work_buf_size =
7553	(p_buf_info->end_adr - p_buf_info->start_adr
7554	+ 0xffff) & (~0xffff);
7555
7556	#endif
7557	pr_debug("amvdec_avs2 module init\n");
7558
7559	#ifdef ERROR_HANDLE_DEBUG
7560	dbg_nal_skip_flag = 0;
7561	dbg_nal_skip_count = 0;
7562	#endif
7563	udebug_flag = 0;
7564	decode_pic_begin = 0;
7565	slice_parse_begin = 0;
7566	step = 0;
7567	buf_alloc_size = 0;
7568	if (platform_driver_register(&ammvdec_avs2_driver))
7569	pr_err("failed to register ammvdec_avs2 driver\n");
7570
7571	if (platform_driver_register(&amvdec_avs2_driver)) {
7572	pr_err("failed to register amvdec_avs2 driver\n");
7573	return -ENODEV;
7574	}
7575
7576	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
7577	amvdec_avs2_profile.profile =
7578	"8k, 10bit, dwrite, compressed";
7579	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7580	if (vdec_is_support_4k())
7581	amvdec_avs2_profile.profile =
7582	"4k, 10bit, dwrite, compressed";
7583	else
7584	amvdec_avs2_profile.profile =
7585	"10bit, dwrite, compressed";
7586	} else {
7587	amvdec_avs2_profile.name = "avs2_unsupport";
7588	}
7589
7590	vcodec_profile_register(&amvdec_avs2_profile);
7591	amvdec_avs2_profile_mult = amvdec_avs2_profile;
7592	amvdec_avs2_profile_mult.name = "mavs2";
7593	vcodec_profile_register(&amvdec_avs2_profile_mult);
7594
7595	INIT_REG_NODE_CONFIGS("media.decoder", &avs2_node,
7596	"avs2", avs2_configs, CONFIG_FOR_RW);
7597
7598	return 0;
7599	}
7600
7601	static void __exit amvdec_avs2_driver_remove_module(void)
7602	{
7603	pr_debug("amvdec_avs2 module remove.\n");
7604	platform_driver_unregister(&ammvdec_avs2_driver);
7605	platform_driver_unregister(&amvdec_avs2_driver);
7606	}
7607
7608	/****************************************/
7609
7610	module_param(bit_depth_luma, uint, 0664);
7611	MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_avs2 bit_depth_luma\n");
7612
7613	module_param(bit_depth_chroma, uint, 0664);
7614	MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_avs2 bit_depth_chroma\n");
7615
7616	module_param(frame_width, uint, 0664);
7617	MODULE_PARM_DESC(frame_width, "\n amvdec_avs2 frame_width\n");
7618
7619	module_param(frame_height, uint, 0664);
7620	MODULE_PARM_DESC(frame_height, "\n amvdec_avs2 frame_height\n");
7621
7622	module_param(debug, uint, 0664);
7623	MODULE_PARM_DESC(debug, "\n amvdec_avs2 debug\n");
7624
7625	module_param(debug_again, uint, 0664);
7626	MODULE_PARM_DESC(debug_again, "\n amvdec_avs2 debug_again\n");
7627
7628	module_param(radr, uint, 0664);
7629	MODULE_PARM_DESC(radr, "\nradr\n");
7630
7631	module_param(rval, uint, 0664);
7632	MODULE_PARM_DESC(rval, "\nrval\n");
7633
7634	module_param(pop_shorts, uint, 0664);
7635	MODULE_PARM_DESC(pop_shorts, "\nrval\n");
7636
7637	module_param(dbg_cmd, uint, 0664);
7638	MODULE_PARM_DESC(dbg_cmd, "\ndbg_cmd\n");
7639
7640	module_param(dbg_skip_decode_index, uint, 0664);
7641	MODULE_PARM_DESC(dbg_skip_decode_index, "\ndbg_skip_decode_index\n");
7642
7643	module_param(endian, uint, 0664);
7644	MODULE_PARM_DESC(endian, "\nrval\n");
7645
7646	module_param(step, uint, 0664);
7647	MODULE_PARM_DESC(step, "\n amvdec_avs2 step\n");
7648
7649	module_param(decode_pic_begin, uint, 0664);
7650	MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_avs2 decode_pic_begin\n");
7651
7652	module_param(slice_parse_begin, uint, 0664);
7653	MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_avs2 slice_parse_begin\n");
7654
7655	module_param(i_only_flag, uint, 0664);
7656	MODULE_PARM_DESC(i_only_flag, "\n amvdec_avs2 i_only_flag\n");
7657
7658	module_param(error_handle_policy, uint, 0664);
7659	MODULE_PARM_DESC(error_handle_policy, "\n amvdec_avs2 error_handle_policy\n");
7660
7661	module_param(re_search_seq_threshold, uint, 0664);
7662	MODULE_PARM_DESC(re_search_seq_threshold, "\n amvdec_avs2 re_search_seq_threshold\n");
7663
7664	module_param(buf_alloc_width, uint, 0664);
7665	MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
7666
7667	module_param(buf_alloc_height, uint, 0664);
7668	MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
7669
7670	module_param(buf_alloc_depth, uint, 0664);
7671	MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
7672
7673	module_param(buf_alloc_size, uint, 0664);
7674	MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
7675
7676	module_param(buffer_mode, uint, 0664);
7677	MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
7678
7679	module_param(buffer_mode_dbg, uint, 0664);
7680	MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
7681	/*USE_BUF_BLOCK*/
7682	module_param(max_buf_num, uint, 0664);
7683	MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
7684
7685	module_param(dynamic_buf_num_margin, uint, 0664);
7686	MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
7687
7688	#ifdef CONSTRAIN_MAX_BUF_NUM
7689	module_param(run_ready_max_vf_only_num, uint, 0664);
7690	MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
7691
7692	module_param(run_ready_display_q_num, uint, 0664);
7693	MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
7694
7695	module_param(run_ready_max_buf_num, uint, 0664);
7696	MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
7697	#endif
7698
7699	module_param(mv_buf_margin, uint, 0664);
7700	MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
7701
7702	module_param(run_ready_min_buf_num, uint, 0664);
7703	MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
7704
7705	/**/
7706
7707	module_param(mem_map_mode, uint, 0664);
7708	MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
7709
7710	module_param(double_write_mode, uint, 0664);
7711	MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
7712
7713	module_param(enable_mem_saving, uint, 0664);
7714	MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
7715
7716	module_param(force_w_h, uint, 0664);
7717	MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
7718
7719	module_param(force_fps, uint, 0664);
7720	MODULE_PARM_DESC(force_fps, "\n force_fps\n");
7721
7722	module_param(max_decoding_time, uint, 0664);
7723	MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
7724
7725	module_param(on_no_keyframe_skiped, uint, 0664);
7726	MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
7727
7728
7729	module_param(start_decode_buf_level, int, 0664);
7730	MODULE_PARM_DESC(start_decode_buf_level,
7731	"\n avs2 start_decode_buf_level\n");
7732
7733	module_param(decode_timeout_val, uint, 0664);
7734	MODULE_PARM_DESC(decode_timeout_val,
7735	"\n avs2 decode_timeout_val\n");
7736
7737	module_param_array(decode_frame_count, uint,
7738	&max_decode_instance_num, 0664);
7739
7740	module_param_array(display_frame_count, uint,
7741	&max_decode_instance_num, 0664);
7742
7743	module_param_array(max_process_time, uint,
7744	&max_decode_instance_num, 0664);
7745
7746	module_param_array(run_count, uint,
7747	&max_decode_instance_num, 0664);
7748
7749	module_param_array(input_empty, uint,
7750	&max_decode_instance_num, 0664);
7751
7752	module_param_array(not_run_ready, uint,
7753	&max_decode_instance_num, 0664);
7754
7755	module_param(video_signal_type, uint, 0664);
7756	MODULE_PARM_DESC(video_signal_type, "\n amvdec_avs2 video_signal_type\n");
7757
7758	module_param(force_video_signal_type, uint, 0664);
7759	MODULE_PARM_DESC(force_video_signal_type, "\n amvdec_avs2 force_video_signal_type\n");
7760
7761	module_param(enable_force_video_signal_type, uint, 0664);
7762	MODULE_PARM_DESC(enable_force_video_signal_type, "\n amvdec_avs2 enable_force_video_signal_type\n");
7763
7764
7765	module_param(udebug_flag, uint, 0664);
7766	MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
7767
7768	module_param(udebug_pause_pos, uint, 0664);
7769	MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
7770
7771	module_param(udebug_pause_val, uint, 0664);
7772	MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
7773
7774	module_param(udebug_pause_decode_idx, uint, 0664);
7775	MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
7776
7777	module_param(pre_decode_buf_level, int, 0664);
7778	MODULE_PARM_DESC(pre_decode_buf_level,
7779	"\n amvdec_avs2 pre_decode_buf_level\n");
7780
7781	module_param(again_threshold, uint, 0664);
7782	MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
7783
7784
7785	module_param(force_disp_pic_index, int, 0664);
7786	MODULE_PARM_DESC(force_disp_pic_index,
7787	"\n amvdec_h265 force_disp_pic_index\n");
7788
7789	module_param(without_display_mode, uint, 0664);
7790	MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
7791
7792	module_init(amvdec_avs2_driver_init_module);
7793	module_exit(amvdec_avs2_driver_remove_module);
7794
7795	MODULE_DESCRIPTION("AMLOGIC avs2 Video Decoder Driver");
7796	MODULE_LICENSE("GPL");
7797	MODULE_AUTHOR("Tim Yao <tim.yao@amlogic.com>");
7798