path: root/drivers/frame_provider/decoder/avs2/vavs2.c (plain)
blob: 6258a75d0704c2bb2d5739b9aac6283b42155d78

1	/*
2	* drivers/amlogic/amports/avs2.c
3	*
4	* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful, but WITHOUT
12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	* more details.
15	*
16	*/
17	#include <linux/kernel.h>
18	#include <linux/module.h>
19	#include <linux/types.h>
20	#include <linux/errno.h>
21	#include <linux/interrupt.h>
22	#include <linux/semaphore.h>
23	#include <linux/delay.h>
24	#include <linux/timer.h>
25	#include <linux/kfifo.h>
26	#include <linux/kthread.h>
27	#include <linux/spinlock.h>
28	#include <linux/platform_device.h>
29	#include <linux/amlogic/media/vfm/vframe.h>
30	#include <linux/amlogic/media/utils/amstream.h>
31	#include <linux/amlogic/media/utils/vformat.h>
32	#include <linux/amlogic/media/frame_sync/ptsserv.h>
33	#include <linux/amlogic/media/frame_sync/tsync.h>
34	#include <linux/amlogic/media/canvas/canvas.h>
35	#include <linux/amlogic/media/vfm/vframe_provider.h>
36	#include <linux/amlogic/media/vfm/vframe_receiver.h>
37	#include <linux/dma-mapping.h>
38	#include <linux/dma-contiguous.h>
39	#include <linux/slab.h>
40	#include <linux/amlogic/tee.h>
41	#include "../../../stream_input/amports/amports_priv.h"
42	#include <linux/amlogic/media/codec_mm/codec_mm.h>
43	#include "../utils/decoder_mmu_box.h"
44	#include "../utils/decoder_bmmu_box.h"
45	#include "avs2_global.h"
46
47	#define MEM_NAME "codec_avs2"
48	/* #include <mach/am_regs.h> */
49	#include <linux/amlogic/media/utils/vdec_reg.h>
50	#include "../utils/vdec.h"
51	#include "../utils/amvdec.h"
52
53	#include <linux/amlogic/media/video_sink/video.h>
54	#include <linux/amlogic/media/codec_mm/configs.h>
55	#include "../utils/config_parser.h"
56	#include "../utils/firmware.h"
57	#include "../../../common/chips/decoder_cpu_ver_info.h"
58	#include <linux/amlogic/tee.h>
59
60
61	#define I_ONLY_SUPPORT
62	#define MIX_STREAM_SUPPORT
63	#define G12A_BRINGUP_DEBUG
64	#define CONSTRAIN_MAX_BUF_NUM
65
66	#include "vavs2.h"
67	#define HEVC_SHIFT_LENGTH_PROTECT 0x313a
68	#define HEVC_MPRED_CTRL9 0x325b
69	#define HEVC_DBLK_CFGD 0x350d
70
71
72	#define HEVC_CM_HEADER_START_ADDR 0x3628
73	#define HEVC_DBLK_CFGB 0x350b
74	#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
75	#define HEVC_SAO_MMU_VH1_ADDR 0x363b
76	#define HEVC_SAO_MMU_VH0_ADDR 0x363a
77
78
79	/*
80	* AVS2_DEC_STATUS define
81	*/
82	/*internal*/
83	#define AVS2_DEC_IDLE 0
84	#define AVS2_SEQUENCE 1
85	#define AVS2_I_PICTURE 2
86	#define AVS2_PB_PICTURE 3
87	#define AVS2_DISCARD_STARTCODE 4
88	#define AVS2_DISCARD_NAL 4
89
90	#define AVS2_SLICE_DECODING 6
91
92	#define SWAP_IN_CMD 0x10
93	#define SWAP_OUT_CMD 0x11
94	#define SWAP_OUTIN_CMD 0x12
95	#define SWAP_DONE 0x13
96	#define SWAP_POST_INIT 0x14
97
98	/*head*/
99	#define AVS2_HEAD_SEQ_READY 0x21
100	#define AVS2_HEAD_PIC_I_READY 0x22
101	#define AVS2_HEAD_PIC_PB_READY 0x23
102	#define AVS2_HEAD_SEQ_END_READY 0x24
103	#define AVS2_STARTCODE_SEARCH_DONE 0x25
104
105	/*pic done*/
106	#define HEVC_DECPIC_DATA_DONE 0x30
107	#define HEVC_DECPIC_DATA_ERROR 0x31
108	#define HEVC_NAL_DECODE_DONE 0x32
109	#define AVS2_DECODE_BUFEMPTY 0x33
110	#define AVS2_DECODE_TIMEOUT 0x34
111	#define AVS2_DECODE_OVER_SIZE 0x35
112	#define AVS2_EOS 0x36
113
114	/*cmd*/
115	#define AVS2_10B_DISCARD_NAL 0xf0
116	#define AVS2_SEARCH_NEW_PIC 0xf1
117	#define AVS2_ACTION_ERROR 0xfe
118	#define HEVC_ACTION_ERROR 0xfe
119	#define AVS2_ACTION_DONE 0xff
120	/*AVS2_DEC_STATUS end*/
121
122
123	#define VF_POOL_SIZE 32
124
125	#undef pr_info
126	#define pr_info printk
127
128	#define DECODE_MODE_SINGLE (0 | (0x80 << 24))
129	#define DECODE_MODE_MULTI_STREAMBASE (1 | (0x80 << 24))
130	#define DECODE_MODE_MULTI_FRAMEBASE (2 | (0x80 << 24))
131
132
133	#define VP9_TRIGGER_FRAME_DONE 0x100
134	#define VP9_TRIGGER_FRAME_ENABLE 0x200
135
136	/*#define MV_MEM_UNIT 0x240*/
137	#define MV_MEM_UNIT 0x200
138	/*---------------------------------------------------
139	Include "parser_cmd.h"
140	---------------------------------------------------*/
141	#define PARSER_CMD_SKIP_CFG_0 0x0000090b
142
143	#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
144
145	#define PARSER_CMD_SKIP_CFG_2 0x001b1910
146
147
148	#define PARSER_CMD_NUMBER 37
149
150	static unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
151	0x0401,
152	0x8401,
153	0x0800,
154	0x0402,
155	0x9002,
156	0x1423,
157	0x8CC3,
158	0x1423,
159	0x8804,
160	0x9825,
161	0x0800,
162	0x04FE,
163	0x8406,
164	0x8411,
165	0x1800,
166	0x8408,
167	0x8409,
168	0x8C2A,
169	0x9C2B,
170	0x1C00,
171	0x840F,
172	0x8407,
173	0x8000,
174	0x8408,
175	0x2000,
176	0xA800,
177	0x8410,
178	0x04DE,
179	0x840C,
180	0x840D,
181	0xAC00,
182	0xA000,
183	0x08C0,
184	0x08E0,
185	0xA40E,
186	0xFC00,
187	0x7C00
188	};
189
190	static int32_t g_WqMDefault4x4[16] = {
191	64, 64, 64, 68,
192	64, 64, 68, 72,
193	64, 68, 76, 80,
194	72, 76, 84, 96
195	};
196
197
198	static int32_t g_WqMDefault8x8[64] = {
199	64, 64, 64, 64, 68, 68, 72, 76,
200	64, 64, 64, 68, 72, 76, 84, 92,
201	64, 64, 68, 72, 76, 80, 88, 100,
202	64, 68, 72, 80, 84, 92, 100, 112,
203	68, 72, 80, 84, 92, 104, 112, 128,
204	76, 80, 84, 92, 104, 116, 132, 152,
205	96, 100, 104, 116, 124, 140, 164, 188,
206	104, 108, 116, 128, 152, 172, 192, 216
207	};
208	/*#define HEVC_PIC_STRUCT_SUPPORT*/
209	/* to remove, fix build error */
210
211	/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
212
213	#define MULTI_INSTANCE_SUPPORT
214	/* #define ERROR_HANDLE_DEBUG */
215
216	#ifndef STAT_KTHREAD
217	#define STAT_KTHREAD 0x40
218	#endif
219
220	#ifdef MULTI_INSTANCE_SUPPORT
221	#define MAX_DECODE_INSTANCE_NUM 12
222	#define MULTI_DRIVER_NAME "ammvdec_avs2"
223
224	#define lock_buffer(dec, flags) \
225	spin_lock_irqsave(&dec->buffer_lock, flags)
226
227	#define unlock_buffer(dec, flags) \
228	spin_unlock_irqrestore(&dec->buffer_lock, flags)
229
230	static unsigned int max_decode_instance_num
231	= MAX_DECODE_INSTANCE_NUM;
232	static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
233	static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
234	static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
235	static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
236	static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
237	static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
238
239	#ifdef G12A_BRINGUP_DEBUG
240	static u32 decode_timeout_val = 200;
241	#else
242	static u32 decode_timeout_val = 200;
243	#endif
244	static int start_decode_buf_level = 0x8000;
245	#ifdef AVS2_10B_MMU
246	static u32 work_buf_size; /* = 24 * 1024 * 1024*/;
247	#else
248	static u32 work_buf_size = 32 * 1024 * 1024;
249	#endif
250
251	static u32 mv_buf_margin;
252	static int pre_decode_buf_level = 0x1000;
253	static u32 again_threshold;
254
255
256	/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
257	/* double_write_mode:
258	* 0, no double write;
259	* 1, 1:1 ratio;
260	* 2, (1/4):(1/4) ratio;
261	* 3, (1/4):(1/4) ratio, with both compressed frame included
262	* 4, (1/2):(1/2) ratio;
263	* 0x10, double write only
264	* 0x100, if > 1080p,use mode 4,else use mode 1;
265	* 0x200, if > 1080p,use mode 2,else use mode 1;
266	* 0x300, if > 720p, use mode 4, else use mode 1;
267	*/
268	static u32 double_write_mode;
269	static u32 without_display_mode;
270
271	#define DRIVER_NAME "amvdec_avs2"
272	#define MODULE_NAME "amvdec_avs2"
273	#define DRIVER_HEADER_NAME "amvdec_avs2_header"
274
275
276	#define PUT_INTERVAL (HZ/100)
277	#define ERROR_SYSTEM_RESET_COUNT 200
278
279	#define PTS_NORMAL 0
280	#define PTS_NONE_REF_USE_DURATION 1
281
282	#define PTS_MODE_SWITCHING_THRESHOLD 3
283	#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
284
285	#define DUR2PTS(x) ((x)*90/96)
286
287	struct AVS2Decoder_s;
288	static int vavs2_vf_states(struct vframe_states *states, void *);
289	static struct vframe_s *vavs2_vf_peek(void *);
290	static struct vframe_s *vavs2_vf_get(void *);
291	static void vavs2_vf_put(struct vframe_s *, void *);
292	static int vavs2_event_cb(int type, void *data, void *private_data);
293	static void set_vframe(struct AVS2Decoder_s *dec,
294	struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy);
295
296	static int vavs2_stop(struct AVS2Decoder_s *dec);
297	static s32 vavs2_init(struct vdec_s *vdec);
298	static void vavs2_prot_init(struct AVS2Decoder_s *dec);
299	static int vavs2_local_init(struct AVS2Decoder_s *dec);
300	static void vavs2_put_timer_func(unsigned long arg);
301	static void dump_data(struct AVS2Decoder_s *dec, int size);
302	static unsigned char get_data_check_sum
303	(struct AVS2Decoder_s *dec, int size);
304	static void dump_pic_list(struct AVS2Decoder_s *dec);
305
306	static const char vavs2_dec_id[] = "vavs2-dev";
307
308	#define PROVIDER_NAME "decoder.avs2"
309	#define MULTI_INSTANCE_PROVIDER_NAME "vdec.avs2"
310
311	static const struct vframe_operations_s vavs2_vf_provider = {
312	.peek = vavs2_vf_peek,
313	.get = vavs2_vf_get,
314	.put = vavs2_vf_put,
315	.event_cb = vavs2_event_cb,
316	.vf_states = vavs2_vf_states,
317	};
318
319	static struct vframe_provider_s vavs2_vf_prov;
320
321	static u32 bit_depth_luma;
322	static u32 bit_depth_chroma;
323	static u32 frame_width;
324	static u32 frame_height;
325	static u32 video_signal_type;
326	static u32 pts_unstable;
327	static u32 on_no_keyframe_skiped;
328
329	static u32 force_video_signal_type;
330	static u32 enable_force_video_signal_type;
331	#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
332
333	static const char * const video_format_names[] = {
334	"component", "PAL", "NTSC", "SECAM",
335	"MAC", "unspecified", "Reserved", "Reserved"
336	};
337
338	static inline int div_r32(int64_t m, int n)
339	{
340	/*
341	return (int)(m/n)
342	*/
343	#ifndef CONFIG_ARM64
344	int64_t qu = 0;
345	qu = div_s64(m, n);
346	return (int)qu;
347	#else
348	return (int)(m/n);
349	#endif
350	}
351
352	enum vpx_bit_depth_t {
353	AVS2_BITS_8 = 8, /**< 8 bits */
354	AVS2_BITS_10 = 10, /**< 10 bits */
355	AVS2_BITS_12 = 12, /**< 12 bits */
356	};
357
358	/*USE_BUF_BLOCK*/
359	struct BUF_s {
360	int index;
361	unsigned int alloc_flag;
362	/*buffer */
363	unsigned int cma_page_count;
364	unsigned long alloc_addr;
365	unsigned long start_adr;
366	unsigned int size;
367
368	unsigned int free_start_adr;
369	} /*BUF_t */;
370
371	struct MVBUF_s {
372	unsigned long start_adr;
373	unsigned int size;
374	int used_flag;
375	} /*MVBUF_t */;
376
377	/* #undef BUFMGR_ONLY to enable hardware configuration */
378
379	/*#define TEST_WR_PTR_INC*/
380	#define WR_PTR_INC_NUM 128
381
382	#define SIMULATION
383	#define DOS_PROJECT
384	#undef MEMORY_MAP_IN_REAL_CHIP
385
386	/*#undef DOS_PROJECT*/
387	/*#define MEMORY_MAP_IN_REAL_CHIP*/
388
389	/*#define BUFFER_MGR_ONLY*/
390	/*#define CONFIG_HEVC_CLK_FORCED_ON*/
391	/*#define ENABLE_SWAP_TEST*/
392
393	#ifdef AVS2_10B_NV21
394	#define MEM_MAP_MODE 2 /* 0:linear 1:32x32 2:64x32*/
395	#else
396	#define MEM_MAP_MODE 0 /* 0:linear 1:32x32 2:64x32*/
397	#endif
398
399	#ifdef AVS2_10B_NV21
400	#else
401	#define LOSLESS_COMPRESS_MODE
402	#endif
403
404	#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
405	#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
406
407
408
409	typedef unsigned int u32;
410	typedef unsigned short u16;
411
412	#define AVS2_DBG_BUFMGR 0x01
413	#define AVS2_DBG_BUFMGR_MORE 0x02
414	#define AVS2_DBG_BUFMGR_DETAIL 0x04
415	#define AVS2_DBG_IRQ_EVENT 0x08
416	#define AVS2_DBG_OUT_PTS 0x10
417	#define AVS2_DBG_PRINT_SOURCE_LINE 0x20
418	#define AVS2_DBG_PRINT_PARAM 0x40
419	#define AVS2_DBG_PRINT_PIC_LIST 0x80
420	#define AVS2_DBG_SEND_PARAM_WITH_REG 0x100
421	#define AVS2_DBG_MERGE 0x200
422	#define AVS2_DBG_DBG_LF_PRINT 0x400
423	#define AVS2_DBG_REG 0x800
424	#define AVS2_DBG_PIC_LEAK 0x1000
425	#define AVS2_DBG_PIC_LEAK_WAIT 0x2000
426	#define AVS2_DBG_HDR_INFO 0x4000
427	#define AVS2_DBG_DIS_LOC_ERROR_PROC 0x10000
428	#define AVS2_DBG_DIS_SYS_ERROR_PROC 0x20000
429	#define AVS2_DBG_DUMP_PIC_LIST 0x40000
430	#define AVS2_DBG_TRIG_SLICE_SEGMENT_PROC 0x80000
431	#define AVS2_DBG_FORCE_UNCOMPRESS 0x100000
432	#define AVS2_DBG_LOAD_UCODE_FROM_FILE 0x200000
433	#define AVS2_DBG_FORCE_SEND_AGAIN 0x400000
434	#define AVS2_DBG_DUMP_DATA 0x800000
435	#define AVS2_DBG_DUMP_LMEM_BUF 0x1000000
436	#define AVS2_DBG_DUMP_RPM_BUF 0x2000000
437	#define AVS2_DBG_CACHE 0x4000000
438	#define IGNORE_PARAM_FROM_CONFIG 0x8000000
439	/*MULTI_INSTANCE_SUPPORT*/
440	#define PRINT_FLAG_ERROR 0
441	#define PRINT_FLAG_VDEC_STATUS 0x20000000
442	#define PRINT_FLAG_VDEC_DETAIL 0x40000000
443	#define PRINT_FLAG_VDEC_DATA 0x80000000
444
445	#define PRINT_LINE() \
446	do { \
447	if (debug & AVS2_DBG_PRINT_SOURCE_LINE)\
448	pr_info("%s line %d\n", __func__, __LINE__);\
449	} while (0)
450
451	static u32 debug;
452
453	static u32 debug_again;
454
455	bool is_avs2_print_param(void)
456	{
457	bool ret = false;
458	if (debug & AVS2_DBG_PRINT_PARAM)
459	ret = true;
460	return ret;
461	}
462
463	bool is_avs2_print_bufmgr_detail(void)
464	{
465	bool ret = false;
466	if (debug & AVS2_DBG_BUFMGR_DETAIL)
467	ret = true;
468	return ret;
469	}
470	static bool is_reset;
471	/*for debug*/
472	/*
473	udebug_flag:
474	bit 0, enable ucode print
475	bit 1, enable ucode detail print
476	bit [31:16] not 0, pos to dump lmem
477	bit 2, pop bits to lmem
478	bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
479	*/
480	static u32 udebug_flag;
481	/*
482	when udebug_flag[1:0] is not 0
483	udebug_pause_pos not 0,
484	pause position
485	*/
486	static u32 udebug_pause_pos;
487	/*
488	when udebug_flag[1:0] is not 0
489	and udebug_pause_pos is not 0,
490	pause only when DEBUG_REG2 is equal to this val
491	*/
492	static u32 udebug_pause_val;
493
494	static u32 udebug_pause_decode_idx;
495
496	static u32 force_disp_pic_index;
497
498	#define DEBUG_REG
499	#ifdef DEBUG_REG
500	static void WRITE_VREG_DBG2(unsigned adr, unsigned val)
501	{
502	if (debug & AVS2_DBG_REG)
503	pr_info("%s(%x, %x)\n", __func__, adr, val);
504	if (adr != 0)
505	WRITE_VREG(adr, val);
506	}
507
508	#undef WRITE_VREG
509	#define WRITE_VREG WRITE_VREG_DBG2
510	#endif
511
512
513	#ifdef AVS2_10B_MMU
514	#define MMU_COMPRESS_HEADER_SIZE 0x48000
515	#define MMU_COMPRESS_8K_HEADER_SIZE 0x48000*4
516	#endif
517
518	#define INVALID_IDX -1 /* Invalid buffer index.*/
519
520
521	#define FRAME_BUFFERS (AVS2_MAX_BUFFER_NUM)
522	#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
523	#define MAX_BUF_NUM (FRAME_BUFFERS)
524
525	#define FRAME_CONTEXTS_LOG2 2
526	#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
527	/*buffer + header buffer + workspace*/
528	#ifdef MV_USE_FIXED_BUF
529	#define MAX_BMMU_BUFFER_NUM ((FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)+1)
530	#define VF_BUFFER_IDX(n) (n)
531	#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n+1)
532	#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS+1)
533	#else
534	#define MAX_BMMU_BUFFER_NUM (((FRAME_BUFFERS*2)+HEADER_FRAME_BUFFERS+1)+1)
535	#define VF_BUFFER_IDX(n) (n)
536	#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n+1)
537	#define MV_BUFFER_IDX(n) ((FRAME_BUFFERS * 2) + n+1)
538	#define WORK_SPACE_BUF_ID ((FRAME_BUFFERS * 2) + HEADER_FRAME_BUFFERS+1)
539	#endif
540	/*
541	static void set_canvas(struct AVS2Decoder_s *dec,
542	struct avs2_frame_s *pic);
543	int avs2_prepare_display_buf(struct AVS2Decoder_s *dec,
544	int pos);
545	*/
546
547
548	struct buff_s {
549	u32 buf_start;
550	u32 buf_size;
551	u32 buf_end;
552	};
553
554	struct BuffInfo_s {
555	u32 max_width;
556	u32 max_height;
557	u32 start_adr;
558	u32 end_adr;
559	struct buff_s ipp;
560	struct buff_s sao_abv;
561	struct buff_s sao_vb;
562	struct buff_s short_term_rps;
563	struct buff_s rcs;
564	struct buff_s sps;
565	struct buff_s pps;
566	struct buff_s sao_up;
567	struct buff_s swap_buf;
568	struct buff_s swap_buf2;
569	struct buff_s scalelut;
570	struct buff_s dblk_para;
571	struct buff_s dblk_data;
572	struct buff_s dblk_data2;
573	#ifdef AVS2_10B_MMU
574	struct buff_s mmu_vbh;
575	struct buff_s cm_header;
576	#endif
577	struct buff_s mpred_above;
578	#ifdef MV_USE_FIXED_BUF
579	struct buff_s mpred_mv;
580	#endif
581	struct buff_s rpm;
582	struct buff_s lmem;
583	};
584
585	#define DEC_RESULT_NONE 0
586	#define DEC_RESULT_DONE 1
587	#define DEC_RESULT_AGAIN 2
588	#define DEC_RESULT_CONFIG_PARAM 3
589	#define DEC_RESULT_ERROR 4
590	#define DEC_INIT_PICLIST 5
591	#define DEC_UNINIT_PICLIST 6
592	#define DEC_RESULT_GET_DATA 7
593	#define DEC_RESULT_GET_DATA_RETRY 8
594	#define DEC_RESULT_EOS 9
595	#define DEC_RESULT_FORCE_EXIT 10
596
597	static void avs2_work(struct work_struct *work);
598	struct loop_filter_info_n;
599	struct loopfilter;
600	struct segmentation;
601
602	struct AVS2Decoder_s {
603	int pic_list_init_flag;
604	unsigned char index;
605	spinlock_t buffer_lock;
606	struct device *cma_dev;
607	struct platform_device *platform_dev;
608	void (*vdec_cb)(struct vdec_s *, void *);
609	void *vdec_cb_arg;
610	struct vframe_chunk_s *chunk;
611	int dec_result;
612	struct work_struct work;
613	u32 start_shift_bytes;
614
615	struct BuffInfo_s work_space_buf_store;
616	unsigned long buf_start;
617	u32 buf_size;
618	u32 cma_alloc_count;
619	unsigned long cma_alloc_addr;
620	uint8_t eos;
621	unsigned long int start_process_time;
622	unsigned last_lcu_idx;
623	int decode_timeout_count;
624	unsigned timeout_num;
625
626	int double_write_mode;
627
628	unsigned char m_ins_flag;
629	char *provider_name;
630	int frame_count;
631	u32 stat;
632	struct timer_list timer;
633	u32 frame_dur;
634	u32 frame_ar;
635	int fatal_error;
636	uint8_t init_flag;
637	uint8_t first_sc_checked;
638	uint8_t process_busy;
639	#define PROC_STATE_INIT 0
640	#define PROC_STATE_HEAD_DONE 1
641	#define PROC_STATE_DECODING 2
642	#define PROC_STATE_HEAD_AGAIN 3
643	#define PROC_STATE_DECODE_AGAIN 4
644	#define PROC_STATE_TEST1 5
645	uint8_t process_state;
646	u32 ucode_pause_pos;
647
648	int show_frame_num;
649	#ifndef AVS2_10B_MMU
650	struct buff_s mc_buf_spec;
651	#endif
652	struct dec_sysinfo vavs2_amstream_dec_info;
653	void *rpm_addr;
654	void *lmem_addr;
655	dma_addr_t rpm_phy_addr;
656	dma_addr_t lmem_phy_addr;
657	unsigned short *lmem_ptr;
658	unsigned short *debug_ptr;
659
660	#if 1
661	/*AVS2_10B_MMU*/
662	void *frame_mmu_map_addr;
663	dma_addr_t frame_mmu_map_phy_addr;
664	#endif
665	unsigned int use_cma_flag;
666
667	struct BUF_s m_BUF[MAX_BUF_NUM];
668	struct MVBUF_s m_mv_BUF[MAX_BUF_NUM];
669	u32 used_buf_num;
670	DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
671	DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
672	DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
673	struct vframe_s vfpool[VF_POOL_SIZE];
674	u32 vf_pre_count;
675	u32 vf_get_count;
676	u32 vf_put_count;
677	int buf_num;
678	unsigned int losless_comp_body_size;
679
680	u32 video_signal_type;
681	u32 video_ori_signal_type;
682
683	int pts_mode;
684	int last_lookup_pts;
685	int last_pts;
686	u64 last_lookup_pts_us64;
687	u64 last_pts_us64;
688	u64 shift_byte_count;
689	u32 shift_byte_count_lo;
690	u32 shift_byte_count_hi;
691	int pts_mode_switching_count;
692	int pts_mode_recovery_count;
693
694	bool get_frame_dur;
695	u32 saved_resolution;
696
697	/**/
698	int refresh_frame_flags;
699	uint8_t hold_ref_buf;
700	struct BuffInfo_s *work_space_buf;
701	#ifndef AVS2_10B_MMU
702	struct buff_s *mc_buf;
703	#endif
704	unsigned int frame_width;
705	unsigned int frame_height;
706
707	unsigned short *rpm_ptr;
708	int init_pic_w;
709	int init_pic_h;
710
711	int slice_type;
712
713	int decode_idx;
714	int slice_idx;
715	uint8_t wait_buf;
716	uint8_t error_flag;
717	unsigned int bufmgr_error_count;
718
719	/* bit 0, for decoding; bit 1, for displaying */
720	uint8_t ignore_bufmgr_error;
721	uint8_t skip_PB_before_I;
722	int PB_skip_mode;
723	int PB_skip_count_after_decoding;
724	/*hw*/
725
726	/**/
727	struct vdec_info *gvs;
728
729
730	unsigned int dec_status;
731	u32 last_put_idx;
732	int new_frame_displayed;
733	void *mmu_box;
734	void *bmmu_box;
735	struct vframe_master_display_colour_s vf_dp;
736	struct firmware_s *fw;
737	#ifdef AVS2_10B_MMU
738	int cur_fb_idx_mmu;
739	long used_4k_num;
740	#endif
741	struct avs2_decoder avs2_dec;
742	#define ALF_NUM_BIT_SHIFT 6
743	#define NO_VAR_BINS 16
744	int32_t m_filterCoeffSym[16][9];
745	int32_t m_varIndTab[NO_VAR_BINS];
746
747	struct vframe_s vframe_dummy;
748	/* start_decoding_flag,
749	bit 0, SEQ ready
750	bit 1, I ready
751	*/
752	unsigned char start_decoding_flag;
753	uint32_t mpred_abv_start_addr;
754	uint32_t mpred_abv_start_addr_bak;
755	u8 next_again_flag;
756	u32 pre_parser_wr_ptr;
757	int need_cache_size;
758	u64 sc_start_time;
759	#ifdef I_ONLY_SUPPORT
760	u32 i_only;
761	#endif
762	int frameinfo_enable;
763	struct vframe_qos_s vframe_qos;
764	};
765
766	static int compute_losless_comp_body_size(
767	struct AVS2Decoder_s *dec, int width, int height,
768	uint8_t is_bit_depth_10);
769
770	static int avs2_print(struct AVS2Decoder_s *dec,
771	int flag, const char *fmt, ...)
772	{
773	#define HEVC_PRINT_BUF 256
774	unsigned char buf[HEVC_PRINT_BUF];
775	int len = 0;
776	if (dec == NULL ||
777	(flag == 0) ||
778	(debug & flag)) {
779	va_list args;
780	va_start(args, fmt);
781	if (dec)
782	len = sprintf(buf, "[%d]", dec->index);
783	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
784	pr_info("%s", buf);
785	va_end(args);
786	}
787	return 0;
788	}
789
790	static int avs2_print_cont(struct AVS2Decoder_s *dec,
791	int flag, const char *fmt, ...)
792	{
793	unsigned char buf[HEVC_PRINT_BUF];
794	int len = 0;
795	if (dec == NULL ||
796	(flag == 0) ||
797	(debug & flag)) {
798	va_list args;
799	va_start(args, fmt);
800	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
801	pr_info("%s", buf);
802	va_end(args);
803	}
804	return 0;
805	}
806
807	#define PROB_SIZE (496 * 2 * 4)
808	#define PROB_BUF_SIZE (0x5000)
809	#define COUNT_BUF_SIZE (0x300 * 4 * 4)
810	/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
811	#define MAX_FRAME_4K_NUM 0x1200
812	#define MAX_FRAME_8K_NUM 0x4800
813	#define MAX_SIZE_4K (4096 * 2304)
814	#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
815
816	static int get_frame_mmu_map_size(struct AVS2Decoder_s *dec)
817	{
818	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
819	(IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
820	return (MAX_FRAME_8K_NUM * 4);
821	return (MAX_FRAME_4K_NUM * 4);
822	}
823
824	static int get_compress_header_size(struct AVS2Decoder_s *dec)
825	{
826	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
827	(IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
828	return MMU_COMPRESS_8K_HEADER_SIZE;
829	return MMU_COMPRESS_HEADER_SIZE;
830	}
831
832	static void reset_process_time(struct AVS2Decoder_s *dec)
833	{
834	if (dec->start_process_time) {
835	unsigned process_time =
836	1000 * (jiffies - dec->start_process_time) / HZ;
837	dec->start_process_time = 0;
838	if (process_time > max_process_time[dec->index])
839	max_process_time[dec->index] = process_time;
840	}
841	}
842
843	static void start_process_time(struct AVS2Decoder_s *dec)
844	{
845	dec->start_process_time = jiffies;
846	dec->decode_timeout_count = 0;
847	dec->last_lcu_idx = 0;
848	}
849
850	static void update_decoded_pic(struct AVS2Decoder_s *dec);
851
852	static void timeout_process(struct AVS2Decoder_s *dec)
853	{
854	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
855	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
856	dec->timeout_num++;
857	amhevc_stop();
858	avs2_print(dec,
859	0, "%s decoder timeout\n", __func__);
860	if (cur_pic)
861	cur_pic->error_mark = 1;
862	dec->dec_result = DEC_RESULT_DONE;
863	update_decoded_pic(dec);
864	reset_process_time(dec);
865	vdec_schedule_work(&dec->work);
866	}
867
868	static u32 get_valid_double_write_mode(struct AVS2Decoder_s *dec)
869	{
870	return (dec->m_ins_flag &&
871	((double_write_mode & 0x80000000) == 0)) ?
872	dec->double_write_mode :
873	(double_write_mode & 0x7fffffff);
874	}
875
876	static int get_double_write_mode(struct AVS2Decoder_s *dec)
877	{
878	u32 valid_dw_mode = get_valid_double_write_mode(dec);
879	int w = dec->avs2_dec.img.width;
880	int h = dec->avs2_dec.img.height;
881	u32 dw = 0x1; /*1:1*/
882	switch (valid_dw_mode) {
883	case 0x100:
884	if (w > 1920 && h > 1088)
885	dw = 0x4; /*1:2*/
886	break;
887	case 0x200:
888	if (w > 1920 && h > 1088)
889	dw = 0x2; /*1:4*/
890	break;
891	case 0x300:
892	if (w > 1280 && h > 720)
893	dw = 0x4; /*1:2*/
894	break;
895	default:
896	dw = valid_dw_mode;
897	break;
898	}
899	return dw;
900	}
901
902	/* for double write buf alloc */
903	static int get_double_write_mode_init(struct AVS2Decoder_s *dec)
904	{
905	u32 valid_dw_mode = get_valid_double_write_mode(dec);
906	u32 dw;
907	int w = dec->init_pic_w;
908	int h = dec->init_pic_h;
909
910	dw = 0x1; /*1:1*/
911	switch (valid_dw_mode) {
912	case 0x100:
913	if (w > 1920 && h > 1088)
914	dw = 0x4; /*1:2*/
915	break;
916	case 0x200:
917	if (w > 1920 && h > 1088)
918	dw = 0x2; /*1:4*/
919	break;
920	case 0x300:
921	if (w > 1280 && h > 720)
922	dw = 0x4; /*1:2*/
923	break;
924	default:
925	dw = valid_dw_mode;
926	break;
927	}
928	return dw;
929	}
930
931	static int get_double_write_ratio(struct AVS2Decoder_s *dec,
932	int dw_mode)
933	{
934	int ratio = 1;
935	if ((dw_mode == 2) ||
936	(dw_mode == 3))
937	ratio = 4;
938	else if (dw_mode == 4)
939	ratio = 2;
940	return ratio;
941	}
942
943	//#define MAX_4K_NUM 0x1200
944	#ifdef AVS2_10B_MMU
945	int avs2_alloc_mmu(
946	struct AVS2Decoder_s *dec,
947	int cur_buf_idx,
948	int pic_width,
949	int pic_height,
950	unsigned short bit_depth,
951	unsigned int *mmu_index_adr)
952	{
953	int bit_depth_10 = (bit_depth == AVS2_BITS_10);
954	int picture_size;
955	int cur_mmu_4k_number, max_frame_num;
956	#ifdef DYNAMIC_ALLOC_HEAD
957	unsigned long buf_addr;
958	struct avs2_frame_s *pic = dec->avs2_dec.hc.cur_pic;
959	if (pic->header_adr == 0) {
960	if (decoder_bmmu_box_alloc_buf_phy
961	(dec->bmmu_box,
962	HEADER_BUFFER_IDX(cur_buf_idx),
963	MMU_COMPRESS_HEADER_SIZE,
964	DRIVER_HEADER_NAME,
965	&buf_addr) < 0){
966	avs2_print(dec, 0,
967	"%s malloc compress header failed %d\n",
968	DRIVER_HEADER_NAME, cur_buf_idx);
969	dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
970	return -1;
971	} else
972	pic->header_adr = buf_addr;
973	}
974	#endif
975
976	picture_size = compute_losless_comp_body_size(
977	dec, pic_width, pic_height,
978	bit_depth_10);
979	cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
980	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
981	max_frame_num = MAX_FRAME_8K_NUM;
982	else
983	max_frame_num = MAX_FRAME_4K_NUM;
984	if (cur_mmu_4k_number > max_frame_num) {
985	pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
986	cur_mmu_4k_number, pic_width, pic_height);
987	return -1;
988	}
989	return decoder_mmu_box_alloc_idx(
990	dec->mmu_box,
991	cur_buf_idx,
992	cur_mmu_4k_number,
993	mmu_index_adr);
994	}
995	#endif
996
997	#if 0
998	/*ndef MV_USE_FIXED_BUF*/
999	static void dealloc_mv_bufs(struct AVS2Decoder_s *dec)
1000	{
1001	int i;
1002	for (i = 0; i < FRAME_BUFFERS; i++) {
1003	if (dec->m_mv_BUF[i].start_adr) {
1004	if (debug)
1005	pr_info(
1006	"dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1007	i, dec->m_mv_BUF[i].start_adr,
1008	dec->m_mv_BUF[i].size,
1009	dec->m_mv_BUF[i].used_flag);
1010	decoder_bmmu_box_free_idx(
1011	dec->bmmu_box,
1012	MV_BUFFER_IDX(i));
1013	dec->m_mv_BUF[i].start_adr = 0;
1014	dec->m_mv_BUF[i].size = 0;
1015	dec->m_mv_BUF[i].used_flag = 0;
1016	}
1017	}
1018	}
1019
1020	static int alloc_mv_buf(struct AVS2Decoder_s *dec,
1021	int i, int size)
1022	{
1023	int ret = 0;
1024	if (decoder_bmmu_box_alloc_buf_phy
1025	(dec->bmmu_box,
1026	MV_BUFFER_IDX(i), size,
1027	DRIVER_NAME,
1028	&dec->m_mv_BUF[i].start_adr) < 0) {
1029	dec->m_mv_BUF[i].start_adr = 0;
1030	ret = -1;
1031	} else {
1032	dec->m_mv_BUF[i].size = size;
1033	dec->m_mv_BUF[i].used_flag = 0;
1034	ret = 0;
1035	if (debug) {
1036	pr_info(
1037	"MV Buffer %d: start_adr %p size %x\n",
1038	i,
1039	(void *)dec->m_mv_BUF[i].start_adr,
1040	dec->m_mv_BUF[i].size);
1041	}
1042	}
1043	return ret;
1044	}
1045
1046	static int init_mv_buf_list(struct AVS2Decoder_s *dec)
1047	{
1048	int i;
1049	int ret = 0;
1050	int count = FRAME_BUFFERS;
1051	int pic_width = dec->init_pic_w;
1052	int pic_height = dec->init_pic_h;
1053	int lcu_size = 64; /*fixed 64*/
1054	int pic_width_64 = (pic_width + 63) & (~0x3f);
1055	int pic_height_32 = (pic_height + 31) & (~0x1f);
1056	int pic_width_lcu = (pic_width_64 % lcu_size) ?
1057	pic_width_64 / lcu_size + 1
1058	: pic_width_64 / lcu_size;
1059	int pic_height_lcu = (pic_height_32 % lcu_size) ?
1060	pic_height_32 / lcu_size + 1
1061	: pic_height_32 / lcu_size;
1062	int lcu_total = pic_width_lcu * pic_height_lcu;
1063	int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1064	(~0xffff);
1065	if (mv_buf_margin > 0)
1066	count = dec->avs2_dec.ref_maxbuffer + mv_buf_margin;
1067	for (i = 0; i < count; i++) {
1068	if (alloc_mv_buf(dec, i, size) < 0) {
1069	ret = -1;
1070	break;
1071	}
1072	}
1073	return ret;
1074	}
1075	#if 0
1076
1077	static int get_mv_buf(struct AVS2Decoder_s *dec,
1078	struct avs2_frame_s *pic)
1079	{
1080	int i;
1081	int ret = -1;
1082	for (i = 0; i < FRAME_BUFFERS; i++) {
1083	if (dec->m_mv_BUF[i].start_adr &&
1084	dec->m_mv_BUF[i].used_flag == 0) {
1085	dec->m_mv_BUF[i].used_flag = 1;
1086	ret = i;
1087	break;
1088	}
1089	}
1090
1091	if (ret >= 0) {
1092	pic->mv_buf_index = ret;
1093	pic->mpred_mv_wr_start_addr =
1094	(dec->m_mv_BUF[ret].start_adr + 0xffff) &
1095	(~0xffff);
1096	if (debug & AVS2_DBG_BUFMGR_MORE)
1097	pr_info(
1098	"%s => %d (%d) size 0x%x\n",
1099	__func__, ret,
1100	pic->mpred_mv_wr_start_addr,
1101	dec->m_mv_BUF[ret].size);
1102	} else {
1103	pr_info(
1104	"%s: Error, mv buf is not enough\n",
1105	__func__);
1106	}
1107	return ret;
1108	}
1109
1110	static void put_mv_buf(struct AVS2Decoder_s *dec,
1111	struct avs2_frame_s *pic)
1112	{
1113	int i = pic->mv_buf_index;
1114	if (i >= FRAME_BUFFERS) {
1115	if (debug & AVS2_DBG_BUFMGR_MORE)
1116	pr_info(
1117	"%s: index %d beyond range\n",
1118	__func__, i);
1119	return;
1120	}
1121	if (debug & AVS2_DBG_BUFMGR_MORE)
1122	pr_info(
1123	"%s(%d): used_flag(%d)\n",
1124	__func__, i,
1125	dec->m_mv_BUF[i].used_flag);
1126
1127	pic->mv_buf_index = -1;
1128	if (dec->m_mv_BUF[i].start_adr &&
1129	dec->m_mv_BUF[i].used_flag)
1130	dec->m_mv_BUF[i].used_flag = 0;
1131	}
1132
1133	static void put_un_used_mv_bufs(struct AVS2Decoder_s *dec)
1134	{
1135	struct VP9_Common_s *const cm = &dec->common;
1136	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1137	int i;
1138	for (i = 0; i < dec->used_buf_num; ++i) {
1139	if ((frame_bufs[i].ref_count == 0) &&
1140	(frame_bufs[i].buf.index != -1) &&
1141	(frame_bufs[i].buf.mv_buf_index >= 0)
1142	)
1143	put_mv_buf(dec, &frame_bufs[i].buf);
1144	}
1145	}
1146	#endif
1147
1148	#endif
1149
1150	static int get_free_buf_count(struct AVS2Decoder_s *dec)
1151	{
1152	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1153	int i;
1154	int count = 0;
1155	for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1156	if ((avs2_dec->fref[i]->imgcoi_ref < -256
1157	#if 0
1158	|| abs(avs2_dec->fref[i]->
1159	imgtr_fwRefDistance - img->tr) >= 128
1160	#endif
1161	) && avs2_dec->fref[i]->is_output == -1
1162	&& avs2_dec->fref[i]->bg_flag == 0
1163	#ifndef NO_DISPLAY
1164	&& avs2_dec->fref[i]->vf_ref == 0
1165	&& avs2_dec->fref[i]->to_prepare_disp == 0
1166	#endif
1167	) {
1168	count++;
1169	}
1170	}
1171
1172	return count;
1173	}
1174
1175	#ifdef CONSTRAIN_MAX_BUF_NUM
1176	static int get_vf_ref_only_buf_count(struct AVS2Decoder_s *dec)
1177	{
1178	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1179	int i;
1180	int count = 0;
1181	for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1182	if ((avs2_dec->fref[i]->imgcoi_ref < -256
1183	#if 0
1184	|| abs(avs2_dec->fref[i]->
1185	imgtr_fwRefDistance - img->tr) >= 128
1186	#endif
1187	) && avs2_dec->fref[i]->is_output == -1
1188	&& avs2_dec->fref[i]->bg_flag == 0
1189	#ifndef NO_DISPLAY
1190	&& avs2_dec->fref[i]->vf_ref > 0
1191	&& avs2_dec->fref[i]->to_prepare_disp == 0
1192	#endif
1193	) {
1194	count++;
1195	}
1196	}
1197
1198	return count;
1199	}
1200
1201	static int get_used_buf_count(struct AVS2Decoder_s *dec)
1202	{
1203	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
1204	int i;
1205	int count = 0;
1206	for (i = 0; i < avs2_dec->ref_maxbuffer; i++) {
1207	if ((avs2_dec->fref[i]->imgcoi_ref >= -256
1208	#if 0
1209	|| abs(avs2_dec->fref[i]->
1210	imgtr_fwRefDistance - img->tr) >= 128
1211	#endif
1212	) || avs2_dec->fref[i]->is_output != -1
1213	|| avs2_dec->fref[i]->bg_flag != 0
1214	#ifndef NO_DISPLAY
1215	|| avs2_dec->fref[i]->vf_ref != 0
1216	|| avs2_dec->fref[i]->to_prepare_disp != 0
1217	#endif
1218	) {
1219	count++;
1220	}
1221	}
1222
1223	return count;
1224	}
1225	#endif
1226
1227	int avs2_bufmgr_init(struct AVS2Decoder_s *dec, struct BuffInfo_s *buf_spec_i,
1228	struct buff_s *mc_buf_i) {
1229
1230	dec->frame_count = 0;
1231	#ifdef AVS2_10B_MMU
1232	dec->used_4k_num = -1;
1233	dec->cur_fb_idx_mmu = INVALID_IDX;
1234	#endif
1235
1236
1237	/* private init */
1238	dec->work_space_buf = buf_spec_i;
1239	#ifndef AVS2_10B_MMU
1240	dec->mc_buf = mc_buf_i;
1241	#endif
1242	dec->rpm_addr = NULL;
1243	dec->lmem_addr = NULL;
1244
1245	dec->use_cma_flag = 0;
1246	dec->decode_idx = 0;
1247	dec->slice_idx = 0;
1248	/*int m_uiMaxCUWidth = 1<<7;*/
1249	/*int m_uiMaxCUHeight = 1<<7;*/
1250	dec->wait_buf = 0;
1251	dec->error_flag = 0;
1252	dec->skip_PB_before_I = 0;
1253
1254	dec->pts_mode = PTS_NORMAL;
1255	dec->last_pts = 0;
1256	dec->last_lookup_pts = 0;
1257	dec->last_pts_us64 = 0;
1258	dec->last_lookup_pts_us64 = 0;
1259	dec->shift_byte_count = 0;
1260	dec->shift_byte_count_lo = 0;
1261	dec->shift_byte_count_hi = 0;
1262	dec->pts_mode_switching_count = 0;
1263	dec->pts_mode_recovery_count = 0;
1264
1265	dec->buf_num = 0;
1266
1267	dec->bufmgr_error_count = 0;
1268	return 0;
1269	}
1270
1271
1272
1273	#define HEVC_CM_BODY_START_ADDR 0x3626
1274	#define HEVC_CM_BODY_LENGTH 0x3627
1275	#define HEVC_CM_HEADER_LENGTH 0x3629
1276	#define HEVC_CM_HEADER_OFFSET 0x362b
1277
1278	#define LOSLESS_COMPRESS_MODE
1279
1280	/*#define DECOMP_HEADR_SURGENT*/
1281
1282	static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
1283	static u32 enable_mem_saving = 1;
1284	static u32 force_w_h;
1285
1286	static u32 force_fps;
1287
1288
1289	const u32 avs2_version = 201602101;
1290	static u32 debug;
1291	static u32 radr;
1292	static u32 rval;
1293	static u32 pop_shorts;
1294	static u32 dbg_cmd;
1295	static u32 dbg_skip_decode_index;
1296	static u32 endian = 0xff0;
1297	#ifdef ERROR_HANDLE_DEBUG
1298	static u32 dbg_nal_skip_flag;
1299	/* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
1300	static u32 dbg_nal_skip_count;
1301	#endif
1302	/*for debug*/
1303	static u32 decode_pic_begin;
1304	static uint slice_parse_begin;
1305	static u32 step;
1306	#ifdef MIX_STREAM_SUPPORT
1307	static u32 buf_alloc_width = 4096;
1308	static u32 buf_alloc_height = 2304;
1309
1310	static u32 dynamic_buf_num_margin;
1311	#else
1312	static u32 buf_alloc_width;
1313	static u32 buf_alloc_height;
1314	static u32 dynamic_buf_num_margin = 7;
1315	#endif
1316	#ifdef CONSTRAIN_MAX_BUF_NUM
1317	static u32 run_ready_max_vf_only_num;
1318	static u32 run_ready_display_q_num;
1319	/*0: not check
1320	0xff: avs2_dec.ref_maxbuffer
1321	*/
1322	static u32 run_ready_max_buf_num = 0xff;
1323	#endif
1324	static u32 buf_alloc_depth = 10;
1325	static u32 buf_alloc_size;
1326	/*
1327	bit[0]: 0,
1328	bit[1]: 0, always release cma buffer when stop
1329	bit[1]: 1, never release cma buffer when stop
1330	bit[0]: 1, when stop, release cma buffer if blackout is 1;
1331	do not release cma buffer is blackout is not 1
1332
1333	bit[2]: 0, when start decoding, check current displayed buffer
1334	(only for buffer decoded by vp9) if blackout is 0
1335	1, do not check current displayed buffer
1336
1337	bit[3]: 1, if blackout is not 1, do not release current
1338	displayed cma buffer always.
1339	*/
1340	/* set to 1 for fast play;
1341	set to 8 for other case of "keep last frame"
1342	*/
1343	static u32 buffer_mode = 1;
1344	/* buffer_mode_dbg: debug only*/
1345	static u32 buffer_mode_dbg = 0xffff0000;
1346	/**/
1347
1348	/*
1349	bit 0, 1: only display I picture;
1350	bit 1, 1: only decode I picture;
1351	*/
1352	static u32 i_only_flag;
1353
1354
1355	static u32 max_decoding_time;
1356	/*
1357	error handling
1358	*/
1359	/*error_handle_policy:
1360	bit 0: search seq again if buffer mgr error occur
1361	(buffer mgr error count need big than
1362	re_search_seq_threshold)
1363	bit 1: 1, display from I picture;
1364	0, display from any correct pic
1365	*/
1366
1367	static u32 error_handle_policy = 1;
1368	/*
1369	re_search_seq_threshold:
1370	bit 7~0: buffer mgr error research seq count
1371	bit 15~8: frame count threshold
1372	*/
1373	static u32 re_search_seq_threshold = 0x800; /*0x8;*/
1374	/*static u32 parser_sei_enable = 1;*/
1375
1376	static u32 max_buf_num = (REF_BUFFER + 1);
1377
1378	static u32 run_ready_min_buf_num = 2;
1379
1380	static DEFINE_MUTEX(vavs2_mutex);
1381
1382	#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
1383	#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
1384	#define AVS2_ALF_SWAP_BUFFER HEVC_ASSIST_SCRATCH_2
1385	#define HEVC_RCS_BUFFER HEVC_ASSIST_SCRATCH_3
1386	#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4
1387	#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
1388	#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
1389	#ifdef AVS2_10B_MMU
1390	#define AVS2_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7
1391	#else
1392	#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
1393	#endif
1394	#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
1395	/*
1396	#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
1397	#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
1398	#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
1399	*/
1400	#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
1401	#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
1402	#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
1403	#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_9
1404	#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
1405	/*!!!*/
1406	#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
1407	#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
1408	#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
1409	#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
1410
1411
1412	/*
1413	ucode parser/search control
1414	bit 0: 0, header auto parse; 1, header manual parse
1415	bit 1: 0, auto skip for noneseamless stream; 1, no skip
1416	bit [3:2]: valid when bit1==0;
1417	0, auto skip nal before first vps/sps/pps/idr;
1418	1, auto skip nal before first vps/sps/pps
1419	2, auto skip nal before first vps/sps/pps,
1420	and not decode until the first I slice (with slice address of 0)
1421
1422	3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
1423	bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
1424	bit [16]: for NAL_UNIT_EOS when bit0 is 0:
1425	0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
1426	bit [17]: for NAL_SEI when bit0 is 0:
1427	0, do not parse SEI in ucode; 1, parse SEI in ucode
1428	bit [31:20]: used by ucode for debug purpose
1429	*/
1430	#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
1431	/*DECODE_MODE: set before start decoder
1432	bit 7~0: decode mode
1433	bit 23~16: start_decoding_flag
1434	bit [0] - SEQ_ready
1435	bit [2:1] - I Picture Count
1436	bit 31~24: chip feature
1437	*/
1438	#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
1439	#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
1440	/*read only*/
1441	#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
1442
1443	#define RPM_BUF_SIZE (0x600 * 2)
1444	#define LMEM_BUF_SIZE (0x600 * 2)
1445
1446	#define WORK_BUF_SPEC_NUM 3
1447	static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
1448	{
1449	/* 8M bytes */
1450	.max_width = 1920,
1451	.max_height = 1088,
1452	.ipp = {
1453	/* IPP work space calculation :
1454	4096 * (Y+CbCr+Flags) = 12k, round to 16k */
1455	.buf_size = 0x4000,
1456	},
1457	.sao_abv = {
1458	.buf_size = 0x30000,
1459	},
1460	.sao_vb = {
1461	.buf_size = 0x30000,
1462	},
1463	.short_term_rps = {
1464	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1465	total 64x16x2 = 2048 bytes (0x800) */
1466	.buf_size = 0x800,
1467	},
1468	.rcs = {
1469	/* RCS STORE AREA - Max 32 RCS, each has 32 bytes,
1470	total 0x0400 bytes */
1471	.buf_size = 0x400,
1472	},
1473	.sps = {
1474	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1475	total 0x0800 bytes*/
1476	.buf_size = 0x800,
1477	},
1478	.pps = {
1479	/*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1480	total 0x2000 bytes*/
1481	.buf_size = 0x2000,
1482	},
1483	.sao_up = {
1484	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
1485	each has 16 bytes total 0x2800 bytes */
1486	.buf_size = 0x2800,
1487	},
1488	.swap_buf = {
1489	/* 256cyclex64bit = 2K bytes 0x800
1490	(only 144 cycles valid) */
1491	.buf_size = 0x800,
1492	},
1493	.swap_buf2 = {
1494	.buf_size = 0x800,
1495	},
1496	.scalelut = {
1497	/* support up to 32 SCALELUT 1024x32 =
1498	32Kbytes (0x8000) */
1499	.buf_size = 0x8000,
1500	},
1501	.dblk_para = {
1502	/* DBLK -> Max 256(4096/16) LCU,
1503	each para 1024bytes(total:0x40000),
1504	data 1024bytes(total:0x40000)*/
1505	.buf_size = 0x40000,
1506	},
1507	.dblk_data = {
1508	.buf_size = 0x40000,
1509	},
1510	.dblk_data2 = {
1511	.buf_size = 0x40000,
1512	},
1513	#ifdef AVS2_10B_MMU
1514	.mmu_vbh = {
1515	.buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
1516	},
1517	#if 0
1518	.cm_header = {
1519	/*add one for keeper.*/
1520	.buf_size = MMU_COMPRESS_HEADER_SIZE *
1521	(FRAME_BUFFERS + 1),
1522	/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
1523	},
1524	#endif
1525	#endif
1526	.mpred_above = {
1527	.buf_size = 0x8000, /* 2 * size of hevc*/
1528	},
1529	#ifdef MV_USE_FIXED_BUF
1530	.mpred_mv = {/* 1080p, 0x40000 per buffer */
1531	.buf_size = 0x40000 * FRAME_BUFFERS,
1532	},
1533	#endif
1534	.rpm = {
1535	.buf_size = RPM_BUF_SIZE,
1536	},
1537	.lmem = {
1538	.buf_size = 0x400 * 2,
1539	}
1540	},
1541	{
1542	.max_width = 4096,
1543	.max_height = 2304,
1544	.ipp = {
1545	/* IPP work space calculation :
1546	4096 * (Y+CbCr+Flags) = 12k, round to 16k */
1547	.buf_size = 0x4000,
1548	},
1549	.sao_abv = {
1550	.buf_size = 0x30000,
1551	},
1552	.sao_vb = {
1553	.buf_size = 0x30000,
1554	},
1555	.short_term_rps = {
1556	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1557	total 64x16x2 = 2048 bytes (0x800) */
1558	.buf_size = 0x800,
1559	},
1560	.rcs = {
1561	/* RCS STORE AREA - Max 16 RCS, each has 32 bytes,
1562	total 0x0400 bytes */
1563	.buf_size = 0x400,
1564	},
1565	.sps = {
1566	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1567	total 0x0800 bytes */
1568	.buf_size = 0x800,
1569	},
1570	.pps = {
1571	/* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1572	total 0x2000 bytes */
1573	.buf_size = 0x2000,
1574	},
1575	.sao_up = {
1576	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
1577	each has 16 bytes total 0x2800 bytes */
1578	.buf_size = 0x2800,
1579	},
1580	.swap_buf = {
1581	/* 256cyclex64bit = 2K bytes 0x800
1582	(only 144 cycles valid) */
1583	.buf_size = 0x800,
1584	},
1585	.swap_buf2 = {
1586	.buf_size = 0x800,
1587	},
1588	.scalelut = {
1589	/* support up to 32 SCALELUT 1024x32 = 32Kbytes
1590	(0x8000) */
1591	.buf_size = 0x8000,
1592	},
1593	.dblk_para = {
1594	/* DBLK -> Max 256(4096/16) LCU,
1595	each para 1024bytes(total:0x40000),
1596	data 1024bytes(total:0x40000)*/
1597	.buf_size = 0x80000,
1598	},
1599	.dblk_data = {
1600	/*DBLK -> Max 256(4096/16) LCU,
1601	each para 1024bytes(total:0x40000),
1602	data 1024bytes(total:0x40000)*/
1603	.buf_size = 0x80000,
1604	},
1605	.dblk_data2 = {
1606	.buf_size = 0x80000,
1607	},
1608	#ifdef AVS2_10B_MMU
1609	.mmu_vbh = {
1610	.buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
1611	},
1612	#if 0
1613	.cm_header = {
1614	/*add one for keeper.*/
1615	.buf_size = MMU_COMPRESS_HEADER_SIZE *
1616	(FRAME_BUFFERS + 1),
1617	/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
1618	},
1619	#endif
1620	#endif
1621	.mpred_above = {
1622	.buf_size = 0x10000, /* 2 * size of hevc*/
1623	},
1624	#ifdef MV_USE_FIXED_BUF
1625	.mpred_mv = {
1626	/* .buf_size = 0x100000*16,
1627	//4k2k , 0x100000 per buffer */
1628	/* 4096x2304 , 0x120000 per buffer */
1629	.buf_size = 0x120000 * FRAME_BUFFERS,
1630	},
1631	#endif
1632	.rpm = {
1633	.buf_size = RPM_BUF_SIZE,
1634	},
1635	.lmem = {
1636	.buf_size = 0x400 * 2,
1637	}
1638	},
1639	{
1640	.max_width = 4096 * 2,
1641	.max_height = 2304 * 2,
1642	.ipp = {
1643	/*IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k,
1644	round to 16k*/
1645	.buf_size = 0x4000 * 2,
1646	},
1647	.sao_abv = {
1648	.buf_size = 0x30000 * 2,
1649	},
1650	.sao_vb = {
1651	.buf_size = 0x30000 * 2,
1652	},
1653	.short_term_rps = {
1654	/*SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1655	total 64x16x2 = 2048 bytes (0x800)*/
1656	.buf_size = 0x800,
1657	},
1658	.rcs = {
1659	/*RCS STORE AREA - Max 16 RCS, each has 32 bytes,
1660	total 0x0400 bytes*/
1661	.buf_size = 0x400,
1662	},
1663	.sps = {
1664	/*SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1665	total 0x0800 bytes*/
1666	.buf_size = 0x800,
1667	},
1668	.pps = {
1669	/*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total
1670	0x2000 bytes*/
1671	.buf_size = 0x2000,
1672	},
1673	.sao_up = {
1674	/*SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes i
1675	total 0x2800 bytes*/
1676	.buf_size = 0x2800 * 2,
1677	},
1678	.swap_buf = {
1679	/*256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)*/
1680	.buf_size = 0x800,
1681	},
1682	.swap_buf2 = {
1683	.buf_size = 0x800,
1684	},
1685	.scalelut = {
1686	/*support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)*/
1687	.buf_size = 0x8000 * 2,
1688	},
1689	.dblk_para = {
1690	.buf_size = 0x40000 * 2,
1691	},
1692	.dblk_data = {
1693	.buf_size = 0x80000 * 2,
1694	},
1695	.dblk_data2 = {
1696	.buf_size = 0x80000 * 2,
1697	},
1698	#ifdef AVS2_10B_MMU
1699	.mmu_vbh = {
1700	.buf_size = 0x5000 * 2, /*2*16*2304/4, 4K*/
1701	},
1702	#if 0
1703	.cm_header = {
1704	/*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
1705	.buf_size = MMU_COMPRESS_8K_HEADER_SIZE * 17,
1706	},
1707	#endif
1708	#endif
1709	.mpred_above = {
1710	.buf_size = 0x8000 * 2,
1711	},
1712	#ifdef MV_USE_FIXED_BUF
1713	.mpred_mv = {
1714	/*4k2k , 0x100000 per buffer*/
1715	.buf_size = 0x120000 * FRAME_BUFFERS * 4,
1716	},
1717	#endif
1718	.rpm = {
1719	.buf_size = RPM_BUF_SIZE,
1720	},
1721	.lmem = {
1722	.buf_size = 0x400 * 2,
1723	}
1724	}
1725	};
1726
1727
1728	/*Losless compression body buffer size 4K per 64x32 (jt)*/
1729	static int compute_losless_comp_body_size(struct AVS2Decoder_s *dec,
1730	int width, int height,
1731	uint8_t is_bit_depth_10)
1732	{
1733	int width_x64;
1734	int height_x32;
1735	int bsize;
1736	width_x64 = width + 63;
1737	width_x64 >>= 6;
1738	height_x32 = height + 31;
1739	height_x32 >>= 5;
1740	#ifdef AVS2_10B_MMU
1741	bsize = (is_bit_depth_10 ? 4096 : 3200)
1742	* width_x64 * height_x32;
1743	#else
1744	bsize = (is_bit_depth_10 ? 4096 : 3072)
1745	* width_x64 * height_x32;
1746	#endif
1747	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
1748	"%s(%d,%d,%d)=>%d\n",
1749	__func__, width, height,
1750	is_bit_depth_10, bsize);
1751
1752	return bsize;
1753	}
1754
1755	/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
1756	static int compute_losless_comp_header_size(struct AVS2Decoder_s *dec,
1757	int width, int height)
1758	{
1759	int width_x128;
1760	int height_x64;
1761	int hsize;
1762	width_x128 = width + 127;
1763	width_x128 >>= 7;
1764	height_x64 = height + 63;
1765	height_x64 >>= 6;
1766
1767	hsize = 32 * width_x128 * height_x64;
1768	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
1769	"%s(%d,%d)=>%d\n",
1770	__func__, width, height,
1771	hsize);
1772
1773	return hsize;
1774	}
1775
1776	static void init_buff_spec(struct AVS2Decoder_s *dec,
1777	struct BuffInfo_s *buf_spec)
1778	{
1779	void *mem_start_virt;
1780	buf_spec->ipp.buf_start = buf_spec->start_adr;
1781	buf_spec->sao_abv.buf_start =
1782	buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
1783
1784	buf_spec->sao_vb.buf_start =
1785	buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
1786	buf_spec->short_term_rps.buf_start =
1787	buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
1788	buf_spec->rcs.buf_start =
1789	buf_spec->short_term_rps.buf_start +
1790	buf_spec->short_term_rps.buf_size;
1791	buf_spec->sps.buf_start =
1792	buf_spec->rcs.buf_start + buf_spec->rcs.buf_size;
1793	buf_spec->pps.buf_start =
1794	buf_spec->sps.buf_start + buf_spec->sps.buf_size;
1795	buf_spec->sao_up.buf_start =
1796	buf_spec->pps.buf_start + buf_spec->pps.buf_size;
1797	buf_spec->swap_buf.buf_start =
1798	buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
1799	buf_spec->swap_buf2.buf_start =
1800	buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
1801	buf_spec->scalelut.buf_start =
1802	buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
1803	buf_spec->dblk_para.buf_start =
1804	buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
1805	buf_spec->dblk_data.buf_start =
1806	buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
1807	buf_spec->dblk_data2.buf_start =
1808	buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
1809	#ifdef AVS2_10B_MMU
1810	buf_spec->mmu_vbh.buf_start =
1811	buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1812	buf_spec->mpred_above.buf_start =
1813	buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
1814	#else
1815	buf_spec->mpred_above.buf_start =
1816	buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1817	#endif
1818	#ifdef MV_USE_FIXED_BUF
1819	buf_spec->mpred_mv.buf_start =
1820	buf_spec->mpred_above.buf_start +
1821	buf_spec->mpred_above.buf_size;
1822
1823	buf_spec->rpm.buf_start =
1824	buf_spec->mpred_mv.buf_start +
1825	buf_spec->mpred_mv.buf_size;
1826	#else
1827	buf_spec->rpm.buf_start =
1828	buf_spec->mpred_above.buf_start +
1829	buf_spec->mpred_above.buf_size;
1830
1831	#endif
1832	buf_spec->lmem.buf_start =
1833	buf_spec->rpm.buf_start +
1834	buf_spec->rpm.buf_size;
1835	buf_spec->end_adr =
1836	buf_spec->lmem.buf_start +
1837	buf_spec->lmem.buf_size;
1838
1839	if (dec) {
1840	mem_start_virt =
1841	codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
1842	if (mem_start_virt) {
1843	memset(mem_start_virt, 0, buf_spec->dblk_para.buf_size);
1844	codec_mm_dma_flush(mem_start_virt,
1845	buf_spec->dblk_para.buf_size,
1846	DMA_TO_DEVICE);
1847	} else {
1848	/*not virt for tvp playing,
1849	may need clear on ucode.*/
1850	pr_err("mem_start_virt failed\n");
1851	}
1852	if (debug) {
1853	pr_info("%s workspace (%x %x) size = %x\n", __func__,
1854	buf_spec->start_adr, buf_spec->end_adr,
1855	buf_spec->end_adr - buf_spec->start_adr);
1856	}
1857	if (debug) {
1858	pr_info("ipp.buf_start :%x\n",
1859	buf_spec->ipp.buf_start);
1860	pr_info("sao_abv.buf_start :%x\n",
1861	buf_spec->sao_abv.buf_start);
1862	pr_info("sao_vb.buf_start :%x\n",
1863	buf_spec->sao_vb.buf_start);
1864	pr_info("short_term_rps.buf_start :%x\n",
1865	buf_spec->short_term_rps.buf_start);
1866	pr_info("rcs.buf_start :%x\n",
1867	buf_spec->rcs.buf_start);
1868	pr_info("sps.buf_start :%x\n",
1869	buf_spec->sps.buf_start);
1870	pr_info("pps.buf_start :%x\n",
1871	buf_spec->pps.buf_start);
1872	pr_info("sao_up.buf_start :%x\n",
1873	buf_spec->sao_up.buf_start);
1874	pr_info("swap_buf.buf_start :%x\n",
1875	buf_spec->swap_buf.buf_start);
1876	pr_info("swap_buf2.buf_start :%x\n",
1877	buf_spec->swap_buf2.buf_start);
1878	pr_info("scalelut.buf_start :%x\n",
1879	buf_spec->scalelut.buf_start);
1880	pr_info("dblk_para.buf_start :%x\n",
1881	buf_spec->dblk_para.buf_start);
1882	pr_info("dblk_data.buf_start :%x\n",
1883	buf_spec->dblk_data.buf_start);
1884	pr_info("dblk_data2.buf_start :%x\n",
1885	buf_spec->dblk_data2.buf_start);
1886	#ifdef AVS2_10B_MMU
1887	pr_info("mmu_vbh.buf_start :%x\n",
1888	buf_spec->mmu_vbh.buf_start);
1889	#endif
1890	pr_info("mpred_above.buf_start :%x\n",
1891	buf_spec->mpred_above.buf_start);
1892	#ifdef MV_USE_FIXED_BUF
1893	pr_info("mpred_mv.buf_start :%x\n",
1894	buf_spec->mpred_mv.buf_start);
1895	#endif
1896	if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) {
1897	pr_info("rpm.buf_start :%x\n",
1898	buf_spec->rpm.buf_start);
1899	}
1900	}
1901	}
1902
1903	}
1904
1905	static void uninit_mmu_buffers(struct AVS2Decoder_s *dec)
1906	{
1907	#if 0
1908	/*ndef MV_USE_FIXED_BUF*/
1909	dealloc_mv_bufs(dec);
1910	#endif
1911	decoder_mmu_box_free(dec->mmu_box);
1912	dec->mmu_box = NULL;
1913
1914	if (dec->bmmu_box)
1915	decoder_bmmu_box_free(dec->bmmu_box);
1916	dec->bmmu_box = NULL;
1917	}
1918
1919	#ifndef AVS2_10B_MMU
1920	static void init_buf_list(struct AVS2Decoder_s *dec)
1921	{
1922	int i;
1923	int buf_size;
1924	int mc_buffer_end = dec->mc_buf->buf_start + dec->mc_buf->buf_size;
1925	dec->used_buf_num = max_buf_num;
1926
1927	if (dec->used_buf_num > MAX_BUF_NUM)
1928	dec->used_buf_num = MAX_BUF_NUM;
1929	if (buf_alloc_size > 0) {
1930	buf_size = buf_alloc_size;
1931	avs2_print(dec, AVS2_DBG_BUFMGR,
1932	"[Buffer Management] init_buf_list:\n");
1933	} else {
1934	int pic_width = dec->init_pic_w;
1935	int pic_height = dec->init_pic_h;
1936
1937	/*SUPPORT_10BIT*/
1938	int losless_comp_header_size = compute_losless_comp_header_size
1939	(dec, pic_width, pic_height);
1940	int losless_comp_body_size = compute_losless_comp_body_size
1941	(dec, pic_width, pic_height, buf_alloc_depth == 10);
1942	int mc_buffer_size = losless_comp_header_size
1943	+ losless_comp_body_size;
1944	int mc_buffer_size_h = (mc_buffer_size + 0xffff)>>16;
1945
1946	int dw_mode = get_double_write_mode_init(dec);
1947
1948	if (dw_mode) {
1949	int pic_width_dw = pic_width /
1950	get_double_write_ratio(dec, dw_mode);
1951	int pic_height_dw = pic_height /
1952	get_double_write_ratio(dec, dw_mode);
1953	int lcu_size = 64; /*fixed 64*/
1954	int pic_width_64 = (pic_width_dw + 63) & (~0x3f);
1955	int pic_height_32 = (pic_height_dw + 31) & (~0x1f);
1956	int pic_width_lcu =
1957	(pic_width_64 % lcu_size) ? pic_width_64 / lcu_size
1958	+ 1 : pic_width_64 / lcu_size;
1959	int pic_height_lcu =
1960	(pic_height_32 % lcu_size) ? pic_height_32 / lcu_size
1961	+ 1 : pic_height_32 / lcu_size;
1962	int lcu_total = pic_width_lcu * pic_height_lcu;
1963	int mc_buffer_size_u_v = lcu_total * lcu_size * lcu_size / 2;
1964	int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
1965	/*64k alignment*/
1966	buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
1967	} else
1968	buf_size = 0;
1969
1970	if (mc_buffer_size & 0xffff) { /*64k alignment*/
1971	mc_buffer_size_h += 1;
1972	}
1973	if ((dw_mode & 0x10) == 0)
1974	buf_size += (mc_buffer_size_h << 16);
1975	avs2_print(dec, AVS2_DBG_BUFMGR,
1976	"init_buf_list num %d (width %d height %d):\n",
1977	dec->used_buf_num, pic_width, pic_height);
1978	}
1979
1980	for (i = 0; i < dec->used_buf_num; i++) {
1981	if (((i + 1) * buf_size) > dec->mc_buf->buf_size)
1982	dec->use_cma_flag = 1;
1983	#ifndef AVS2_10B_MMU
1984	dec->m_BUF[i].alloc_flag = 0;
1985	dec->m_BUF[i].index = i;
1986
1987	dec->use_cma_flag = 1;
1988	if (dec->use_cma_flag) {
1989	dec->m_BUF[i].cma_page_count =
1990	PAGE_ALIGN(buf_size) / PAGE_SIZE;
1991	if (decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box,
1992	VF_BUFFER_IDX(i), buf_size, DRIVER_NAME,
1993	&dec->m_BUF[i].alloc_addr) < 0) {
1994	dec->m_BUF[i].cma_page_count = 0;
1995	if (i <= 5) {
1996	dec->fatal_error |=
1997	DECODER_FATAL_ERROR_NO_MEM;
1998	}
1999	break;
2000	}
2001	dec->m_BUF[i].start_adr = dec->m_BUF[i].alloc_addr;
2002	} else {
2003	dec->m_BUF[i].cma_page_count = 0;
2004	dec->m_BUF[i].alloc_addr = 0;
2005	dec->m_BUF[i].start_adr =
2006	dec->mc_buf->buf_start + i * buf_size;
2007	}
2008	dec->m_BUF[i].size = buf_size;
2009	dec->m_BUF[i].free_start_adr = dec->m_BUF[i].start_adr;
2010
2011	if (((dec->m_BUF[i].start_adr + buf_size) > mc_buffer_end)
2012	&& (dec->m_BUF[i].alloc_addr == 0)) {
2013	if (debug) {
2014	avs2_print(dec, 0,
2015	"Max mc buffer or mpred_mv buffer is used\n");
2016	}
2017	break;
2018	}
2019
2020	avs2_print(dec, AVS2_DBG_BUFMGR,
2021	"Buffer %d: start_adr %p size %x\n", i,
2022	(void *)dec->m_BUF[i].start_adr,
2023	dec->m_BUF[i].size);
2024	#endif
2025	}
2026	dec->buf_num = i;
2027	}
2028	#endif
2029
2030	static int config_pic(struct AVS2Decoder_s *dec,
2031	struct avs2_frame_s *pic, int32_t lcu_size_log2)
2032	{
2033	int ret = -1;
2034	int i;
2035	int pic_width = dec->init_pic_w;
2036	int pic_height = dec->init_pic_h;
2037	/*struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2038	int32_t lcu_size_log2 = avs2_dec->lcu_size_log2;*/
2039	int32_t lcu_size = 1 << lcu_size_log2;
2040	int pic_width_64 = (pic_width + 63) & (~0x3f);
2041	int pic_height_32 = (pic_height + 31) & (~0x1f);
2042	int pic_width_lcu = (pic_width_64 % lcu_size) ?
2043	pic_width_64 / lcu_size + 1
2044	: pic_width_64 / lcu_size;
2045	int pic_height_lcu = (pic_height_32 % lcu_size) ?
2046	pic_height_32 / lcu_size + 1
2047	: pic_height_32 / lcu_size;
2048	int lcu_total = pic_width_lcu * pic_height_lcu;
2049	#if 0
2050	int32_t MV_MEM_UNIT =
2051	(lcu_size_log2 == 6) ? 0x200 :
2052	((lcu_size_log2 == 5) ? 0x80 : 0x20);
2053	#endif
2054	#ifdef MV_USE_FIXED_BUF
2055	u32 mpred_mv_end = dec->work_space_buf->mpred_mv.buf_start +
2056	dec->work_space_buf->mpred_mv.buf_size;
2057	#endif
2058	u32 y_adr = 0;
2059	int buf_size = 0;
2060
2061	int losless_comp_header_size =
2062	compute_losless_comp_header_size(
2063	dec, pic_width, pic_height);
2064	int losless_comp_body_size = compute_losless_comp_body_size(
2065	dec, pic_width,
2066	pic_height, buf_alloc_depth == 10);
2067	int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
2068	int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
2069	int mc_buffer_size_u_v = 0;
2070	int mc_buffer_size_u_v_h = 0;
2071	int dw_mode = get_double_write_mode_init(dec);
2072
2073	if (dw_mode) {
2074	int pic_width_dw = pic_width /
2075	get_double_write_ratio(dec, dw_mode);
2076	int pic_height_dw = pic_height /
2077	get_double_write_ratio(dec, dw_mode);
2078	int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
2079	int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
2080	int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
2081	pic_width_64_dw / lcu_size + 1
2082	: pic_width_64_dw / lcu_size;
2083	int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
2084	pic_height_32_dw / lcu_size + 1
2085	: pic_height_32_dw / lcu_size;
2086	int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
2087
2088	mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
2089	mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
2090	/*64k alignment*/
2091	buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
2092	buf_size = ((buf_size + 0xffff) >> 16) << 16;
2093	}
2094	if (mc_buffer_size & 0xffff) /*64k alignment*/
2095	mc_buffer_size_h += 1;
2096	#ifndef AVS2_10B_MMU
2097	if ((dw_mode & 0x10) == 0)
2098	buf_size += (mc_buffer_size_h << 16);
2099	#endif
2100
2101	#ifdef AVS2_10B_MMU
2102	#ifndef DYNAMIC_ALLOC_HEAD
2103	pic->header_adr = decoder_bmmu_box_get_phy_addr(
2104	dec->bmmu_box, HEADER_BUFFER_IDX(pic->index));
2105
2106	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
2107	"buf_size %d, MMU header_adr %d: %ld\n",
2108	buf_size, pic->index, pic->header_adr);
2109	#endif
2110	#endif
2111
2112	i = pic->index;
2113	#ifdef MV_USE_FIXED_BUF
2114	#ifdef G12A_BRINGUP_DEBUG
2115	if (1) {
2116	#else
2117	if ((dec->work_space_buf->mpred_mv.buf_start +
2118	(((i + 1) * lcu_total) * MV_MEM_UNIT))
2119	<= mpred_mv_end
2120	) {
2121	#endif
2122	#endif
2123	#ifndef AVS2_10B_MMU
2124	if (debug) {
2125	pr_err("start %x .size=%d\n",
2126	dec->mc_buf_spec.buf_start + i * buf_size,
2127	buf_size);
2128	}
2129	#endif
2130	#ifndef AVS2_10B_MMU
2131	for (i = 0; i < dec->buf_num; i++) {
2132	y_adr = ((dec->m_BUF[i].free_start_adr
2133	+ 0xffff) >> 16) << 16;
2134	/*64k alignment*/
2135	if ((y_adr+buf_size) <= (dec->m_BUF[i].start_adr+
2136	dec->m_BUF[i].size)) {
2137	dec->m_BUF[i].free_start_adr =
2138	y_adr + buf_size;
2139	break;
2140	}
2141	}
2142	if (i < dec->buf_num)
2143	#else
2144	/*if ((dec->mc_buf->buf_start + (i + 1) * buf_size) <
2145	dec->mc_buf->buf_end)
2146	y_adr = dec->mc_buf->buf_start + i * buf_size;
2147	else {*/
2148	if (buf_size > 0 && pic->cma_alloc_addr == 0) {
2149	ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box,
2150	VF_BUFFER_IDX(i),
2151	buf_size, DRIVER_NAME,
2152	&pic->cma_alloc_addr);
2153	if (ret < 0) {
2154	avs2_print(dec, 0,
2155	"decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
2156	VF_BUFFER_IDX(i),
2157	buf_size
2158	);
2159	return ret;
2160	}
2161
2162	if (pic->cma_alloc_addr)
2163	y_adr = pic->cma_alloc_addr;
2164	else {
2165	avs2_print(dec, 0,
2166	"decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
2167	VF_BUFFER_IDX(i),
2168	buf_size
2169	);
2170	return -1;
2171	}
2172	}
2173	#endif
2174	{
2175	/*ensure get_pic_by_POC()
2176	not get the buffer not decoded*/
2177	pic->BUF_index = i;
2178	pic->lcu_total = lcu_total;
2179
2180	pic->comp_body_size = losless_comp_body_size;
2181	pic->buf_size = buf_size;
2182	#ifndef AVS2_10B_MMU
2183	pic->mc_y_adr = y_adr;
2184	#endif
2185	pic->mc_canvas_y = pic->index;
2186	pic->mc_canvas_u_v = pic->index;
2187	#ifndef AVS2_10B_MMU
2188	if (dw_mode & 0x10) {
2189	pic->mc_u_v_adr = y_adr +
2190	((mc_buffer_size_u_v_h << 16) << 1);
2191
2192	pic->mc_canvas_y =
2193	(pic->index << 1);
2194	pic->mc_canvas_u_v =
2195	(pic->index << 1) + 1;
2196
2197	pic->dw_y_adr = y_adr;
2198	pic->dw_u_v_adr = pic->mc_u_v_adr;
2199	} else
2200	#endif
2201	if (dw_mode) {
2202	pic->dw_y_adr = y_adr
2203	#ifndef AVS2_10B_MMU
2204	+ (mc_buffer_size_h << 16)
2205	#endif
2206	;
2207	pic->dw_u_v_adr = pic->dw_y_adr +
2208	((mc_buffer_size_u_v_h << 16) << 1);
2209	#ifdef AVS2_10B_MMU
2210	pic->mc_y_adr = pic->dw_y_adr;
2211	pic->mc_u_v_adr = pic->dw_u_v_adr;
2212	#endif
2213	}
2214	#ifdef MV_USE_FIXED_BUF
2215	#ifdef G12A_BRINGUP_DEBUG
2216	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
2217	pic->mpred_mv_wr_start_addr =
2218	dec->work_space_buf->mpred_mv.buf_start +
2219	(pic->index * 0x120000 * 4);
2220	} else {
2221	pic->mpred_mv_wr_start_addr =
2222	dec->work_space_buf->mpred_mv.buf_start +
2223	(pic->index * 0x120000);
2224	}
2225	#else
2226	pic->mpred_mv_wr_start_addr =
2227	dec->work_space_buf->mpred_mv.buf_start +
2228	((pic->index * lcu_total)
2229	* MV_MEM_UNIT);
2230	#endif
2231	#endif
2232	if (debug) {
2233	avs2_print(dec, AVS2_DBG_BUFMGR,
2234	"%s index %d BUF_index %d mc_y_adr %x ",
2235	__func__, pic->index,
2236	pic->BUF_index,
2237	pic->mc_y_adr);
2238	avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2239	"comp_body_size %x comp_buf_size %x ",
2240	pic->comp_body_size,
2241	pic->buf_size);
2242	avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2243	"mpred_mv_wr_start_adr %d\n",
2244	pic->mpred_mv_wr_start_addr);
2245	avs2_print_cont(dec, AVS2_DBG_BUFMGR,
2246	"dw_y_adr %d, pic->dw_u_v_adr =%d\n",
2247	pic->dw_y_adr,
2248	pic->dw_u_v_adr);
2249	}
2250	ret = 0;
2251	}
2252	#ifdef MV_USE_FIXED_BUF
2253	} else {
2254	avs2_print(dec, 0,
2255	"mv buffer alloc fail %x > %x\n",
2256	dec->work_space_buf->mpred_mv.buf_start +
2257	(((i + 1) * lcu_total) * MV_MEM_UNIT),
2258	mpred_mv_end);
2259	}
2260	#endif
2261	return ret;
2262	}
2263
2264	static void init_pic_list(struct AVS2Decoder_s *dec,
2265	int32_t lcu_size_log2)
2266	{
2267	int i;
2268	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2269	struct avs2_frame_s *pic;
2270	#ifdef AVS2_10B_MMU
2271	unsigned long buf_addr1;
2272	/*alloc AVS2 compress header first*/
2273	if (decoder_bmmu_box_alloc_buf_phy
2274	(dec->bmmu_box,
2275	HEADER_BUFFER_IDX(-1), get_compress_header_size(dec),
2276	DRIVER_HEADER_NAME,
2277	&buf_addr1) < 0){
2278	avs2_print(dec, 0,
2279	"%s malloc compress header failed %d\n",
2280	DRIVER_HEADER_NAME, -1);
2281	dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2282	return;
2283	}
2284	#ifndef DYNAMIC_ALLOC_HEAD
2285	for (i = 0; i < dec->used_buf_num; i++) {
2286	unsigned long buf_addr;
2287	if (decoder_bmmu_box_alloc_buf_phy
2288	(dec->bmmu_box,
2289	HEADER_BUFFER_IDX(i), get_compress_header_size(dec),
2290	DRIVER_HEADER_NAME,
2291	&buf_addr) < 0){
2292	avs2_print(dec, 0,
2293	"%s malloc compress header failed %d\n",
2294	DRIVER_HEADER_NAME, i);
2295	dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
2296	return;
2297	}
2298	}
2299	#endif
2300	#endif
2301	dec->frame_height = avs2_dec->img.height;
2302	dec->frame_width = avs2_dec->img.width;
2303
2304	for (i = 0; i < dec->used_buf_num; i++) {
2305	if (i == (dec->used_buf_num - 1))
2306	pic = avs2_dec->m_bg;
2307	else
2308	pic = avs2_dec->fref[i];
2309	pic->index = i;
2310	pic->BUF_index = -1;
2311	pic->mv_buf_index = -1;
2312	if (config_pic(dec, pic, lcu_size_log2) < 0) {
2313	if (debug)
2314	avs2_print(dec, 0,
2315	"Config_pic %d fail\n",
2316	pic->index);
2317	pic->index = -1;
2318	break;
2319	}
2320	pic->pic_w = avs2_dec->img.width;
2321	pic->pic_h = avs2_dec->img.height;
2322	}
2323	for (; i < dec->used_buf_num; i++) {
2324	if (i == (dec->used_buf_num - 1))
2325	pic = avs2_dec->m_bg;
2326	else
2327	pic = avs2_dec->fref[i];
2328	pic->index = -1;
2329	pic->BUF_index = -1;
2330	pic->mv_buf_index = -1;
2331	}
2332	avs2_print(dec, AVS2_DBG_BUFMGR,
2333	"%s ok, used_buf_num = %d\n",
2334	__func__, dec->used_buf_num);
2335	dec->pic_list_init_flag = 1;
2336	}
2337
2338
2339	static void init_pic_list_hw(struct AVS2Decoder_s *dec)
2340	{
2341	int i;
2342	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2343	struct avs2_frame_s *pic;
2344	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
2345	#if 0
2346	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2347	(0x1 << 1) | (0x1 << 2));
2348
2349	#ifdef DUAL_CORE_64
2350	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2351	(0x1 << 1) | (0x1 << 2));
2352	#endif
2353	#endif
2354	for (i = 0; i < dec->used_buf_num; i++) {
2355	if (i == (dec->used_buf_num - 1))
2356	pic = avs2_dec->m_bg;
2357	else
2358	pic = avs2_dec->fref[i];
2359	if (pic->index < 0)
2360	break;
2361	#ifdef AVS2_10B_MMU
2362	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2363	pic->header_adr
2364	| (pic->mc_canvas_y << 8)|0x1);*/
2365	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2366	(0x1 << 1) | (pic->index << 8));
2367
2368	#ifdef DUAL_CORE_64
2369	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXLX2)
2370	WRITE_VREG(HEVC2_MPP_ANC2AXI_TBL_CONF_ADDR,
2371	(0x1 << 1) | (pic->index << 8));
2372	else
2373	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2374	(0x1 << 1) | (pic->index << 8));
2375	#endif
2376	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->header_adr >> 5);
2377	#else
2378	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2379	pic->mc_y_adr
2380	| (pic->mc_canvas_y << 8) | 0x1);*/
2381	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_y_adr >> 5);
2382	#endif
2383	#ifndef LOSLESS_COMPRESS_MODE
2384	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
2385	pic->mc_u_v_adr
2386	| (pic->mc_canvas_u_v << 8)| 0x1);*/
2387	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_u_v_adr >> 5);
2388	#endif
2389	#ifdef DUAL_CORE_64
2390	#ifdef AVS2_10B_MMU
2391	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2392	pic->header_adr >> 5);
2393	#else
2394	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2395	pic->mc_y_adr >> 5);
2396	#endif
2397	#ifndef LOSLESS_COMPRESS_MODE
2398	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA,
2399	pic->mc_u_v_adr >> 5);
2400	#endif
2401	/*DUAL_CORE_64*/
2402	#endif
2403	}
2404	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
2405	#ifdef DUAL_CORE_64
2406	WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
2407	0x1);
2408	#endif
2409	/*Zero out canvas registers in IPP -- avoid simulation X*/
2410	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2411	(0 << 8) | (0 << 1) | 1);
2412	for (i = 0; i < 32; i++) {
2413	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2414	#ifdef DUAL_CORE_64
2415	WRITE_VREG(HEVC2_HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
2416	#endif
2417	}
2418	}
2419
2420
2421	static void dump_pic_list(struct AVS2Decoder_s *dec)
2422	{
2423	int ii;
2424	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2425	for (ii = 0; ii < avs2_dec->ref_maxbuffer; ii++) {
2426	avs2_print(dec, 0,
2427	"fref[%d]: index %d decode_id %d mvbuf %d imgcoi_ref %d imgtr_fwRefDistance %d refered %d, pre %d is_out %d, bg %d, vf_ref %d error %d lcu %d ref_pos(%d,%d,%d,%d,%d,%d,%d)\n",
2428	ii, avs2_dec->fref[ii]->index,
2429	avs2_dec->fref[ii]->decode_idx,
2430	avs2_dec->fref[ii]->mv_buf_index,
2431	avs2_dec->fref[ii]->imgcoi_ref,
2432	avs2_dec->fref[ii]->imgtr_fwRefDistance,
2433	avs2_dec->fref[ii]->refered_by_others,
2434	avs2_dec->fref[ii]->to_prepare_disp,
2435	avs2_dec->fref[ii]->is_output,
2436	avs2_dec->fref[ii]->bg_flag,
2437	avs2_dec->fref[ii]->vf_ref,
2438	avs2_dec->fref[ii]->error_mark,
2439	avs2_dec->fref[ii]->decoded_lcu,
2440	avs2_dec->fref[ii]->ref_poc[0],
2441	avs2_dec->fref[ii]->ref_poc[1],
2442	avs2_dec->fref[ii]->ref_poc[2],
2443	avs2_dec->fref[ii]->ref_poc[3],
2444	avs2_dec->fref[ii]->ref_poc[4],
2445	avs2_dec->fref[ii]->ref_poc[5],
2446	avs2_dec->fref[ii]->ref_poc[6]
2447	);
2448	}
2449	return;
2450	}
2451
2452	static int config_mc_buffer(struct AVS2Decoder_s *dec)
2453	{
2454	int32_t i;
2455	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2456	struct avs2_frame_s *pic;
2457	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2458
2459	/*if (avs2_dec->img.type == I_IMG)
2460	return 0;
2461	*/
2462	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2463	"Entered config_mc_buffer....\n");
2464	if (avs2_dec->f_bg != NULL) {
2465	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2466	"config_mc_buffer for background (canvas_y %d, canvas_u_v %d)\n",
2467	avs2_dec->f_bg->mc_canvas_y, avs2_dec->f_bg->mc_canvas_u_v);
2468	/*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2469	(7 << 8) | (0<<1) | 1); L0:BG */
2470	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2471	(15 << 8) | (0<<1) | 1); /* L0:BG*/
2472	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2473	(avs2_dec->f_bg->mc_canvas_u_v << 16) |
2474	(avs2_dec->f_bg->mc_canvas_u_v << 8) |
2475	avs2_dec->f_bg->mc_canvas_y);
2476	/*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2477	(23 << 8) | (0<<1) | 1); L1:BG*/
2478	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2479	(31 << 8) | (0<<1) | 1); /* L1:BG*/
2480	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2481	(avs2_dec->f_bg->mc_canvas_u_v << 16) |
2482	(avs2_dec->f_bg->mc_canvas_u_v << 8) |
2483	avs2_dec->f_bg->mc_canvas_y);
2484	}
2485
2486	if (avs2_dec->img.type == I_IMG)
2487	return 0;
2488
2489	if (avs2_dec->img.type == P_IMG) {
2490	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2491	"config_mc_buffer for P_IMG, img type %d\n",
2492	avs2_dec->img.type);
2493	/*refer to prepare_RefInfo()*/
2494	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2495	(0 << 8) | (0<<1) | 1);
2496	for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2497	pic = avs2_dec->fref[i];
2498	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2499	(pic->mc_canvas_u_v << 16) |
2500	(pic->mc_canvas_u_v << 8) |
2501	pic->mc_canvas_y);
2502
2503	if (pic->error_mark)
2504	cur_pic->error_mark = 1;
2505
2506	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2507	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2508	i, pic->mc_canvas_u_v, pic->mc_canvas_y,
2509	pic->error_mark);
2510	}
2511	} else if (avs2_dec->img.type == F_IMG) {
2512	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2513	"config_mc_buffer for F_IMG, img type %d\n",
2514	avs2_dec->img.type);
2515	/*refer to prepare_RefInfo()*/
2516	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2517	(0 << 8) | (0<<1) | 1);
2518	for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2519	pic = avs2_dec->fref[i];
2520	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2521	(pic->mc_canvas_u_v << 16) |
2522	(pic->mc_canvas_u_v << 8) |
2523	pic->mc_canvas_y);
2524
2525	if (pic->error_mark)
2526	cur_pic->error_mark = 1;
2527
2528	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2529	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2530	i, pic->mc_canvas_u_v, pic->mc_canvas_y,
2531	pic->error_mark);
2532	}
2533	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2534	(16 << 8) | (0<<1) | 1);
2535	for (i = 0; i < avs2_dec->img.num_of_references; i++) {
2536	pic = avs2_dec->fref[i];
2537	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2538	(pic->mc_canvas_u_v << 16) |
2539	(pic->mc_canvas_u_v << 8) |
2540	pic->mc_canvas_y);
2541	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2542	"refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
2543	i, pic->mc_canvas_u_v, pic->mc_canvas_y);
2544	}
2545	} else {
2546	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2547	"config_mc_buffer for B_IMG\n");
2548	/*refer to prepare_RefInfo()*/
2549	pic = avs2_dec->fref[1];
2550	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2551	(0 << 8) | (0<<1) | 1);
2552	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2553	(pic->mc_canvas_u_v << 16) |
2554	(pic->mc_canvas_u_v << 8) |
2555	pic->mc_canvas_y);
2556
2557	if (pic->error_mark)
2558	cur_pic->error_mark = 1;
2559
2560	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2561	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2562	1, pic->mc_canvas_u_v, pic->mc_canvas_y,
2563	pic->error_mark);
2564
2565	pic = avs2_dec->fref[0];
2566	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2567	(16 << 8) | (0<<1) | 1);
2568	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
2569	(pic->mc_canvas_u_v<<16) |
2570	(pic->mc_canvas_u_v<<8) |
2571	pic->mc_canvas_y);
2572
2573	if (pic->error_mark)
2574	cur_pic->error_mark = 1;
2575
2576	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2577	"refid %x mc_canvas_u_v %x mc_canvas_y %x error_mark %x\n",
2578	0, pic->mc_canvas_u_v, pic->mc_canvas_y,
2579	pic->error_mark);
2580	}
2581	return 0;
2582	}
2583	#if 0
2584	static void mcrcc_get_hitrate(void)
2585	{
2586	u32 tmp;
2587	u32 raw_mcr_cnt;
2588	u32 hit_mcr_cnt;
2589	u32 byp_mcr_cnt_nchoutwin;
2590	u32 byp_mcr_cnt_nchcanv;
2591	int hitrate;
2592
2593	if (debug & AVS2_DBG_CACHE)
2594	pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
2595	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
2596	raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2597	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
2598	hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2599	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
2600	byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2601	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
2602	byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2603
2604	if (debug & AVS2_DBG_CACHE) {
2605	pr_info("raw_mcr_cnt_total: %d\n",raw_mcr_cnt);
2606	pr_info("hit_mcr_cnt_total: %d\n",hit_mcr_cnt);
2607	pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",byp_mcr_cnt_nchoutwin);
2608	pr_info("byp_mcr_cnt_nchcanv_total: %d\n",byp_mcr_cnt_nchcanv);
2609	}
2610	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
2611	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2612	if (debug & AVS2_DBG_CACHE)
2613	pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
2614
2615	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
2616	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2617	if (debug & AVS2_DBG_CACHE)
2618	pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
2619
2620	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
2621	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2622	if (debug & AVS2_DBG_CACHE)
2623	pr_info("hit_mcr_0_cnt_total: %d\n",tmp);
2624
2625	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
2626	tmp= READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
2627	if (debug & AVS2_DBG_CACHE)
2628	pr_info("hit_mcr_1_cnt_total: %d\n",tmp);
2629
2630	if (raw_mcr_cnt != 0) {
2631	hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2632	if (debug & AVS2_DBG_CACHE)
2633	pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
2634	hitrate = ((byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
2635	/raw_mcr_cnt) * 100;
2636	if (debug & AVS2_DBG_CACHE)
2637	pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
2638	} else if (debug & AVS2_DBG_CACHE) {
2639	pr_info("MCRCC_HIT_RATE : na\n");
2640	pr_info("MCRCC_BYP_RATE : na\n");
2641	}
2642	return;
2643	}
2644
2645
2646	static void decomp_get_hitrate(void)
2647	{
2648	u32 raw_mcr_cnt;
2649	u32 hit_mcr_cnt;
2650	int hitrate;
2651
2652	if (debug & AVS2_DBG_CACHE)
2653	pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
2654	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
2655	raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2656	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
2657	hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2658
2659	if (debug & AVS2_DBG_CACHE) {
2660	pr_info("hcache_raw_cnt_total: %d\n",raw_mcr_cnt);
2661	pr_info("hcache_hit_cnt_total: %d\n",hit_mcr_cnt);
2662	}
2663	if (raw_mcr_cnt != 0) {
2664	hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2665	if (debug & AVS2_DBG_CACHE)
2666	pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
2667	} else {
2668	if (debug & AVS2_DBG_CACHE)
2669	pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
2670	}
2671	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
2672	raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2673	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
2674	hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2675
2676	if (debug & AVS2_DBG_CACHE) {
2677	pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
2678	pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
2679	}
2680	if (raw_mcr_cnt != 0) {
2681	hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
2682	if (debug & AVS2_DBG_CACHE)
2683	pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
2684	} else if (debug & AVS2_DBG_CACHE) {
2685	pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
2686	}
2687	return;
2688	}
2689
2690	static void decomp_get_comprate(void)
2691	{
2692	u32 raw_ucomp_cnt;
2693	u32 fast_comp_cnt;
2694	u32 slow_comp_cnt;
2695	int comprate;
2696
2697	if (debug & AVS2_DBG_CACHE)
2698	pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
2699	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
2700	fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2701	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
2702	slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2703	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
2704	raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
2705	if (debug & AVS2_DBG_CACHE) {
2706	pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
2707	pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
2708	pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
2709	}
2710
2711	if (raw_ucomp_cnt != 0) {
2712	comprate = ((fast_comp_cnt + slow_comp_cnt)
2713	/ raw_ucomp_cnt) * 100;
2714	if (debug & AVS2_DBG_CACHE)
2715	pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
2716	} else if (debug & AVS2_DBG_CACHE) {
2717	pr_info("DECOMP_COMP_RATIO : na\n");
2718	}
2719	return;
2720	}
2721	#endif
2722
2723	static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
2724	{
2725	uint32_t rdata32;
2726	uint32_t rdata32_2;
2727	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2728
2729	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc*/
2730
2731	if (avs2_dec->img.type == I_IMG) { /* I-PIC*/
2732	/* remove reset -- disables clock */
2733	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
2734	return;
2735	}
2736	/*
2737	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
2738	mcrcc_get_hitrate();
2739	decomp_get_hitrate();
2740	decomp_get_comprate();
2741	}
2742	*/
2743	if ((avs2_dec->img.type == B_IMG) ||
2744	(avs2_dec->img.type == F_IMG)) { /*B-PIC or F_PIC*/
2745	/*Programme canvas0 */
2746	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2747	(0 << 8) | (0 << 1) | 0);
2748	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2749	rdata32 = rdata32 & 0xffff;
2750	rdata32 = rdata32 | (rdata32 << 16);
2751	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
2752
2753	/*Programme canvas1 */
2754	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2755	(16 << 8) | (1 << 1) | 0);
2756	rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2757	rdata32_2 = rdata32_2 & 0xffff;
2758	rdata32_2 = rdata32_2 | (rdata32_2 << 16);
2759	if (rdata32 == rdata32_2) {
2760	rdata32_2 =
2761	READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2762	rdata32_2 = rdata32_2 & 0xffff;
2763	rdata32_2 = rdata32_2 | (rdata32_2 << 16);
2764	}
2765	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
2766	} else { /* P-PIC */
2767	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
2768	(0 << 8) | (1 << 1) | 0);
2769	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2770	rdata32 = rdata32 & 0xffff;
2771	rdata32 = rdata32 | (rdata32 << 16);
2772	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
2773
2774	/*Programme canvas1*/
2775	rdata32 =
2776	READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
2777	rdata32 = rdata32 & 0xffff;
2778	rdata32 = rdata32 | (rdata32 << 16);
2779	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
2780	}
2781	/*enable mcrcc progressive-mode */
2782	WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
2783	return;
2784	}
2785
2786	static void config_mpred_hw(struct AVS2Decoder_s *dec)
2787	{
2788	uint32_t data32;
2789	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2790	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2791	struct avs2_frame_s *col_pic = avs2_dec->fref[0];
2792	int32_t mpred_mv_rd_start_addr;
2793	int32_t mpred_curr_lcu_x;
2794	int32_t mpred_curr_lcu_y;
2795	int32_t mpred_mv_rd_end_addr;
2796	int32_t above_en;
2797	int32_t mv_wr_en;
2798	int32_t mv_rd_en;
2799	int32_t col_isIntra;
2800	int mv_mem_unit;
2801	if (avs2_dec->img.type != I_IMG) {
2802	above_en = 1;
2803	mv_wr_en = 1;
2804	mv_rd_en = 1;
2805	col_isIntra = 0;
2806	} else {
2807	above_en = 1;
2808	mv_wr_en = 1;
2809	mv_rd_en = 0;
2810	col_isIntra = 0;
2811	}
2812
2813	mpred_mv_rd_start_addr =
2814	col_pic->mpred_mv_wr_start_addr;
2815	data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
2816	mpred_curr_lcu_x = data32 & 0xffff;
2817	mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
2818
2819	mv_mem_unit = avs2_dec->lcu_size_log2 == 6 ?
2820	0x200 : (avs2_dec->lcu_size_log2 == 5 ?
2821	0x80 : 0x20);
2822
2823	mpred_mv_rd_end_addr =
2824	mpred_mv_rd_start_addr +
2825	((avs2_dec->lcu_x_num *
2826	avs2_dec->lcu_y_num) * mv_mem_unit);
2827
2828	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2829	"cur pic index %d col pic index %d\n",
2830	cur_pic->index, col_pic->index);
2831
2832
2833	WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
2834	cur_pic->mpred_mv_wr_start_addr);
2835	WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
2836	col_pic->mpred_mv_wr_start_addr);
2837	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2838	"[MPRED CO_MV] write 0x%x read 0x%x\n",
2839	cur_pic->mpred_mv_wr_start_addr,
2840	col_pic->mpred_mv_wr_start_addr);
2841
2842	data32 =
2843	((avs2_dec->bk_img_is_top_field) << 13) |
2844	((avs2_dec->hd.background_picture_enable & 1) << 12) |
2845	((avs2_dec->hd.curr_RPS.num_of_ref & 7) << 8) |
2846	((avs2_dec->hd.b_pmvr_enabled & 1) << 6) |
2847	((avs2_dec->img.is_top_field & 1) << 5) |
2848	((avs2_dec->img.is_field_sequence & 1) << 4) |
2849	((avs2_dec->img.typeb & 7) << 1) |
2850	(avs2_dec->hd.background_reference_enable & 0x1);
2851	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2852	"HEVC_MPRED_CTRL9 <= 0x%x(num of ref %d)\n",
2853	data32, avs2_dec->hd.curr_RPS.num_of_ref);
2854	WRITE_VREG(HEVC_MPRED_CTRL9, data32);
2855
2856	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2857	"%s: dis %d %d %d %d %d %d %d fref0_ref_poc %d %d %d %d %d %d %d\n",
2858	__func__,
2859	avs2_dec->fref[0]->imgtr_fwRefDistance,
2860	avs2_dec->fref[1]->imgtr_fwRefDistance,
2861	avs2_dec->fref[2]->imgtr_fwRefDistance,
2862	avs2_dec->fref[3]->imgtr_fwRefDistance,
2863	avs2_dec->fref[4]->imgtr_fwRefDistance,
2864	avs2_dec->fref[5]->imgtr_fwRefDistance,
2865	avs2_dec->fref[6]->imgtr_fwRefDistance,
2866	avs2_dec->fref[0]->ref_poc[0],
2867	avs2_dec->fref[0]->ref_poc[1],
2868	avs2_dec->fref[0]->ref_poc[2],
2869	avs2_dec->fref[0]->ref_poc[3],
2870	avs2_dec->fref[0]->ref_poc[4],
2871	avs2_dec->fref[0]->ref_poc[5],
2872	avs2_dec->fref[0]->ref_poc[6]
2873	);
2874	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2875	"pic_distance %d, imgtr_next_P %d\n",
2876	avs2_dec->img.pic_distance, avs2_dec->img.imgtr_next_P);
2877
2878
2879	WRITE_VREG(HEVC_MPRED_CUR_POC, avs2_dec->img.pic_distance);
2880	WRITE_VREG(HEVC_MPRED_COL_POC, avs2_dec->img.imgtr_next_P);
2881
2882	/*below MPRED Ref_POC_xx_Lx registers
2883	must follow Ref_POC_xx_L0 ->
2884	Ref_POC_xx_L1 in pair write order!!!*/
2885	WRITE_VREG(HEVC_MPRED_L0_REF00_POC,
2886	avs2_dec->fref[0]->imgtr_fwRefDistance);
2887	WRITE_VREG(HEVC_MPRED_L1_REF00_POC,
2888	avs2_dec->fref[0]->ref_poc[0]);
2889
2890	WRITE_VREG(HEVC_MPRED_L0_REF01_POC,
2891	avs2_dec->fref[1]->imgtr_fwRefDistance);
2892	WRITE_VREG(HEVC_MPRED_L1_REF01_POC,
2893	avs2_dec->fref[0]->ref_poc[1]);
2894
2895	WRITE_VREG(HEVC_MPRED_L0_REF02_POC,
2896	avs2_dec->fref[2]->imgtr_fwRefDistance);
2897	WRITE_VREG(HEVC_MPRED_L1_REF02_POC,
2898	avs2_dec->fref[0]->ref_poc[2]);
2899
2900	WRITE_VREG(HEVC_MPRED_L0_REF03_POC,
2901	avs2_dec->fref[3]->imgtr_fwRefDistance);
2902	WRITE_VREG(HEVC_MPRED_L1_REF03_POC,
2903	avs2_dec->fref[0]->ref_poc[3]);
2904
2905	WRITE_VREG(HEVC_MPRED_L0_REF04_POC,
2906	avs2_dec->fref[4]->imgtr_fwRefDistance);
2907	WRITE_VREG(HEVC_MPRED_L1_REF04_POC,
2908	avs2_dec->fref[0]->ref_poc[4]);
2909
2910	WRITE_VREG(HEVC_MPRED_L0_REF05_POC,
2911	avs2_dec->fref[5]->imgtr_fwRefDistance);
2912	WRITE_VREG(HEVC_MPRED_L1_REF05_POC,
2913	avs2_dec->fref[0]->ref_poc[5]);
2914
2915	WRITE_VREG(HEVC_MPRED_L0_REF06_POC,
2916	avs2_dec->fref[6]->imgtr_fwRefDistance);
2917	WRITE_VREG(HEVC_MPRED_L1_REF06_POC,
2918	avs2_dec->fref[0]->ref_poc[6]);
2919
2920
2921	WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
2922	mpred_mv_rd_end_addr);
2923	}
2924
2925	static void config_dblk_hw(struct AVS2Decoder_s *dec)
2926	{
2927	/*
2928	* Picture level de-block parameter configuration here
2929	*/
2930	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2931	union param_u *rpm_param = &avs2_dec->param;
2932	uint32_t data32;
2933
2934	data32 = READ_VREG(HEVC_DBLK_CFG1);
2935	data32 = (((data32 >> 20) & 0xfff) << 20) |
2936	(((avs2_dec->input.sample_bit_depth == 10)
2937	? 0xa : 0x0) << 16) | /*[16 +: 4]: {luma_bd[1:0],
2938	chroma_bd[1:0]}*/
2939	(((data32 >> 2) & 0x3fff) << 2) |
2940	(((rpm_param->p.lcu_size == 6)
2941	? 0 : (rpm_param->p.lcu_size == 5)
2942	? 1 : 2) << 0);/*[ 0 +: 2]: lcu_size*/
2943	WRITE_VREG(HEVC_DBLK_CFG1, data32);
2944
2945	data32 = (avs2_dec->img.height << 16) |
2946	avs2_dec->img.width;
2947	WRITE_VREG(HEVC_DBLK_CFG2, data32);
2948	/*
2949	[27 +: 1]: cross_slice_loopfilter_enable_flag
2950	[26 +: 1]: loop_filter_disable
2951	[25 +: 1]: useNSQT
2952	[22 +: 3]: imgtype
2953	[17 +: 5]: alpha_c_offset (-8~8)
2954	[12 +: 5]: beta_offset (-8~8)
2955	[ 6 +: 6]: chroma_quant_param_delta_u (-16~16)
2956	[ 0 +: 6]: chroma_quant_param_delta_v (-16~16)
2957	*/
2958	data32 = ((avs2_dec->input.crossSliceLoopFilter
2959	& 0x1) << 27) |
2960	((rpm_param->p.loop_filter_disable & 0x1) << 26) |
2961	((avs2_dec->input.useNSQT & 0x1) << 25) |
2962	((avs2_dec->img.type & 0x7) << 22) |
2963	((rpm_param->p.alpha_c_offset & 0x1f) << 17) |
2964	((rpm_param->p.beta_offset & 0x1f) << 12) |
2965	((rpm_param->p.chroma_quant_param_delta_cb & 0x3f) << 6) |
2966	((rpm_param->p.chroma_quant_param_delta_cr & 0x3f) << 0);
2967
2968	WRITE_VREG(HEVC_DBLK_CFG9, data32);
2969	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2970	"[c] cfgDBLK: crossslice(%d),lfdisable(%d),bitDepth(%d),lcuSize(%d),NSQT(%d)\n",
2971	avs2_dec->input.crossSliceLoopFilter,
2972	rpm_param->p.loop_filter_disable,
2973	avs2_dec->input.sample_bit_depth,
2974	avs2_dec->lcu_size,
2975	avs2_dec->input.useNSQT);
2976	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2977	"[c] cfgDBLK: alphaCOffset(%d),betaOffset(%d),quantDeltaCb(%d),quantDeltaCr(%d)\n",
2978	rpm_param->p.alpha_c_offset,
2979	rpm_param->p.beta_offset,
2980	rpm_param->p.chroma_quant_param_delta_cb,
2981	rpm_param->p.chroma_quant_param_delta_cr);
2982	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
2983	"[c] cfgDBLK: .done.\n");
2984	}
2985
2986	static void config_sao_hw(struct AVS2Decoder_s *dec)
2987	{
2988	uint32_t data32;
2989	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
2990	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
2991
2992	int lcu_size = 64;
2993	int mc_buffer_size_u_v =
2994	cur_pic->lcu_total * lcu_size*lcu_size/2;
2995	int mc_buffer_size_u_v_h =
2996	(mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
2997
2998	data32 = READ_VREG(HEVC_SAO_CTRL0);
2999	data32 &= (~0xf);
3000	data32 |= avs2_dec->lcu_size_log2;
3001	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3002	"%s, lcu_size_log2 = %d, config HEVC_SAO_CTRL0 0x%x\n",
3003	__func__,
3004	avs2_dec->lcu_size_log2,
3005	data32);
3006
3007	WRITE_VREG(HEVC_SAO_CTRL0, data32);
3008
3009	#ifndef AVS2_10B_MMU
3010	if ((get_double_write_mode(dec) & 0x10) == 0)
3011	WRITE_VREG(HEVC_CM_BODY_START_ADDR, cur_pic->mc_y_adr);
3012	#endif
3013	if (get_double_write_mode(dec)) {
3014	WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr);
3015	WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr);
3016	WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr);
3017	WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr);
3018	} else {
3019	WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
3020	WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
3021	}
3022	#ifdef AVS2_10B_MMU
3023	WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr);
3024	#endif
3025	data32 = (mc_buffer_size_u_v_h << 16) << 1;
3026	/*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
3027	data32, mc_buffer_size_u_v_h, cur_pic->lcu_total);*/
3028	WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
3029
3030	data32 = (mc_buffer_size_u_v_h << 16);
3031	WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
3032
3033	#ifdef AVS2_10B_NV21
3034	#ifdef DOS_PROJECT
3035	data32 = READ_VREG(HEVC_SAO_CTRL1);
3036	data32 &= (~0x3000);
3037	/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
3038	data32 |= (MEM_MAP_MODE << 12);
3039	data32 &= (~0x3);
3040	data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
3041	WRITE_VREG(HEVC_SAO_CTRL1, data32);
3042	/*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
3043	[17:16] dw_h0_ctrl*/
3044	data32 = READ_VREG(HEVC_SAO_CTRL5);
3045	/*set them all 0 for H265_NV21 (no down-scale)*/
3046	data32 &= ~(0xff << 16);
3047	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3048	ata32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3049	data32 &= (~0x30);
3050	/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
3051	data32 |= (MEM_MAP_MODE << 4);
3052	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3053	#else
3054	/*m8baby test1902*/
3055	data32 = READ_VREG(HEVC_SAO_CTRL1);
3056	data32 &= (~0x3000);
3057	/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
3058	data32 |= (MEM_MAP_MODE << 12);
3059	data32 &= (~0xff0);
3060	/*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
3061	data32 |= 0x880; /*.Big-Endian per 64-bit */
3062	data32 &= (~0x3);
3063	data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
3064	WRITE_VREG(HEVC_SAO_CTRL1, data32);
3065	/* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
3066	[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl*/
3067	data32 = READ_VREG(HEVC_SAO_CTRL5);
3068	/* set them all 0 for H265_NV21 (no down-scale)*/
3069	data32 &= ~(0xff << 16);
3070	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3071
3072	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3073	data32 &= (~0x30);
3074	/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
3075	data32 |= (MEM_MAP_MODE << 4);
3076	data32 &= (~0xF);
3077	data32 |= 0x8; /*Big-Endian per 64-bit*/
3078	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3079	#endif
3080	#else
3081	data32 = READ_VREG(HEVC_SAO_CTRL1);
3082	data32 &= (~0x3000);
3083	data32 |= (MEM_MAP_MODE <<
3084	12); /* [13:12] axi_aformat, 0-Linear,
3085	1-32x32, 2-64x32 */
3086	data32 &= (~0xff0);
3087	/* data32 |= 0x670; // Big-Endian per 64-bit */
3088	data32 |= endian; /* Big-Endian per 64-bit */
3089	data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
3090	#if 0
3091	if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
3092	if (get_double_write_mode(dec) == 0)
3093	data32 |= 0x2; /*disable double write*/
3094	#ifndef AVS2_10B_MMU
3095	else
3096	if (get_double_write_mode(dec) & 0x10)
3097	data32 |= 0x1; /*disable cm*/
3098	#endif
3099	}
3100	#endif
3101	WRITE_VREG(HEVC_SAO_CTRL1, data32);
3102
3103	if (get_double_write_mode(dec) & 0x10) {
3104	/* [23:22] dw_v1_ctrl
3105	[21:20] dw_v0_ctrl
3106	[19:18] dw_h1_ctrl
3107	[17:16] dw_h0_ctrl
3108	*/
3109	data32 = READ_VREG(HEVC_SAO_CTRL5);
3110	/*set them all 0 for H265_NV21 (no down-scale)*/
3111	data32 &= ~(0xff << 16);
3112	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3113	} else {
3114	data32 = READ_VREG(HEVC_SAO_CTRL5);
3115	data32 &= (~(0xff << 16));
3116	if (get_double_write_mode(dec) == 2 ||
3117	get_double_write_mode(dec) == 3)
3118	data32 |= (0xff<<16);
3119	else if (get_double_write_mode(dec) == 4)
3120	data32 |= (0x33<<16);
3121	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3122	}
3123
3124	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
3125	data32 &= (~0x30);
3126	/* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
3127	data32 |= (mem_map_mode <<
3128	4);
3129	data32 &= (~0xF);
3130	data32 |= 0xf; /* valid only when double write only */
3131	/*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
3132	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
3133	#endif
3134	}
3135
3136	static void reconstructCoefficients(struct AVS2Decoder_s *dec,
3137	struct ALFParam_s *alfParam)
3138	{
3139	int32_t g, sum, i, coeffPred;
3140	for (g = 0; g < alfParam->filters_per_group; g++) {
3141	sum = 0;
3142	for (i = 0; i < alfParam->num_coeff - 1; i++) {
3143	sum += (2 * alfParam->coeffmulti[g][i]);
3144	dec->m_filterCoeffSym[g][i] =
3145	alfParam->coeffmulti[g][i];
3146	/*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n",
3147	g, i, dec->m_filterCoeffSym[g][i]);*/
3148	}
3149	coeffPred = (1 << ALF_NUM_BIT_SHIFT) - sum;
3150	dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]
3151	= coeffPred +
3152	alfParam->coeffmulti[g][alfParam->num_coeff - 1];
3153	/*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n",
3154	g, (alfParam->num_coeff - 1),
3155	dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]);*/
3156	}
3157	}
3158
3159	static void reconstructCoefInfo(struct AVS2Decoder_s *dec,
3160	int32_t compIdx, struct ALFParam_s *alfParam)
3161	{
3162	int32_t i;
3163	if (compIdx == ALF_Y) {
3164	if (alfParam->filters_per_group > 1) {
3165	for (i = 1; i < NO_VAR_BINS; ++i) {
3166	if (alfParam->filterPattern[i])
3167	dec->m_varIndTab[i] =
3168	dec->m_varIndTab[i - 1] + 1;
3169	else
3170	dec->m_varIndTab[i] =
3171	dec->m_varIndTab[i - 1];
3172	}
3173	}
3174	}
3175	reconstructCoefficients(dec, alfParam);
3176	}
3177
3178	static void config_alf_hw(struct AVS2Decoder_s *dec)
3179	{
3180	/*
3181	* Picture level ALF parameter configuration here
3182	*/
3183	uint32_t data32;
3184	int32_t i, j;
3185	int32_t m_filters_per_group;
3186	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3187	struct ALFParam_s *m_alfPictureParam_y =
3188	&avs2_dec->m_alfPictureParam[0];
3189	struct ALFParam_s *m_alfPictureParam_cb =
3190	&avs2_dec->m_alfPictureParam[1];
3191	struct ALFParam_s *m_alfPictureParam_cr =
3192	&avs2_dec->m_alfPictureParam[2];
3193
3194	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3195	"[t]alfy,cidx(%d),flag(%d),filters_per_group(%d),filterPattern[0]=0x%x,[15]=0x%x\n",
3196	m_alfPictureParam_y->componentID,
3197	m_alfPictureParam_y->alf_flag,
3198	m_alfPictureParam_y->filters_per_group,
3199	m_alfPictureParam_y->filterPattern[0],
3200	m_alfPictureParam_y->filterPattern[15]);
3201	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3202	"[t]alfy,num_coeff(%d),coeffmulti[0][0]=0x%x,[0][1]=0x%x,[1][0]=0x%x,[1][1]=0x%x\n",
3203	m_alfPictureParam_y->num_coeff,
3204	m_alfPictureParam_y->coeffmulti[0][0],
3205	m_alfPictureParam_y->coeffmulti[0][1],
3206	m_alfPictureParam_y->coeffmulti[1][0],
3207	m_alfPictureParam_y->coeffmulti[1][1]);
3208
3209	/*Cr*/
3210	for (i = 0; i < 16; i++)
3211	dec->m_varIndTab[i] = 0;
3212	for (j = 0; j < 16; j++)
3213	for (i = 0; i < 9; i++)
3214	dec->m_filterCoeffSym[j][i] = 0;
3215	reconstructCoefInfo(dec, 2, m_alfPictureParam_cr);
3216	data32 =
3217	((dec->m_filterCoeffSym[0][4] & 0xf) << 28) |
3218	((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) |
3219	((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) |
3220	((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) |
3221	((dec->m_filterCoeffSym[0][0] & 0x7f) << 0);
3222	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3223	data32 =
3224	((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) |
3225	((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) |
3226	((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) |
3227	((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) |
3228	(((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0);
3229	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3230	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3231	"[c] pic_alf_on_cr(%d), alf_cr_coef(%d %d %d %d %d %d %d %d %d)\n",
3232	m_alfPictureParam_cr->alf_flag,
3233	dec->m_filterCoeffSym[0][0],
3234	dec->m_filterCoeffSym[0][1],
3235	dec->m_filterCoeffSym[0][2],
3236	dec->m_filterCoeffSym[0][3],
3237	dec->m_filterCoeffSym[0][4],
3238	dec->m_filterCoeffSym[0][5],
3239	dec->m_filterCoeffSym[0][6],
3240	dec->m_filterCoeffSym[0][7],
3241	dec->m_filterCoeffSym[0][8]);
3242
3243	/* Cb*/
3244	for (j = 0; j < 16; j++)
3245	for (i = 0; i < 9; i++)
3246	dec->m_filterCoeffSym[j][i] = 0;
3247	reconstructCoefInfo(dec, 1, m_alfPictureParam_cb);
3248	data32 =
3249	((dec->m_filterCoeffSym[0][4] & 0xf) << 28) |
3250	((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) |
3251	((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) |
3252	((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) |
3253	((dec->m_filterCoeffSym[0][0] & 0x7f) << 0);
3254	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3255	data32 =
3256	((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) |
3257	((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) |
3258	((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) |
3259	((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) |
3260	(((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0);
3261	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3262	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3263	"[c] pic_alf_on_cb(%d), alf_cb_coef(%d %d %d %d %d %d %d %d %d)\n",
3264	m_alfPictureParam_cb->alf_flag,
3265	dec->m_filterCoeffSym[0][0],
3266	dec->m_filterCoeffSym[0][1],
3267	dec->m_filterCoeffSym[0][2],
3268	dec->m_filterCoeffSym[0][3],
3269	dec->m_filterCoeffSym[0][4],
3270	dec->m_filterCoeffSym[0][5],
3271	dec->m_filterCoeffSym[0][6],
3272	dec->m_filterCoeffSym[0][7],
3273	dec->m_filterCoeffSym[0][8]);
3274
3275	/* Y*/
3276	for (j = 0; j < 16; j++)
3277	for (i = 0; i < 9; i++)
3278	dec->m_filterCoeffSym[j][i] = 0;
3279	reconstructCoefInfo(dec, 0, m_alfPictureParam_y);
3280	data32 =
3281	((dec->m_varIndTab[7] & 0xf) << 28) |
3282	((dec->m_varIndTab[6] & 0xf) << 24) |
3283	((dec->m_varIndTab[5] & 0xf) << 20) |
3284	((dec->m_varIndTab[4] & 0xf) << 16) |
3285	((dec->m_varIndTab[3] & 0xf) << 12) |
3286	((dec->m_varIndTab[2] & 0xf) << 8) |
3287	((dec->m_varIndTab[1] & 0xf) << 4) |
3288	((dec->m_varIndTab[0] & 0xf) << 0);
3289	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3290	data32 = ((dec->m_varIndTab[15] & 0xf) << 28) |
3291	((dec->m_varIndTab[14] & 0xf) << 24) |
3292	((dec->m_varIndTab[13] & 0xf) << 20) |
3293	((dec->m_varIndTab[12] & 0xf) << 16) |
3294	((dec->m_varIndTab[11] & 0xf) << 12) |
3295	((dec->m_varIndTab[10] & 0xf) << 8) |
3296	((dec->m_varIndTab[9] & 0xf) << 4) |
3297	((dec->m_varIndTab[8] & 0xf) << 0);
3298	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3299	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3300	"[c] pic_alf_on_y(%d), alf_y_tab(%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d)\n",
3301	m_alfPictureParam_y->alf_flag,
3302	dec->m_varIndTab[0],
3303	dec->m_varIndTab[1],
3304	dec->m_varIndTab[2],
3305	dec->m_varIndTab[3],
3306	dec->m_varIndTab[4],
3307	dec->m_varIndTab[5],
3308	dec->m_varIndTab[6],
3309	dec->m_varIndTab[7],
3310	dec->m_varIndTab[8],
3311	dec->m_varIndTab[9],
3312	dec->m_varIndTab[10],
3313	dec->m_varIndTab[11],
3314	dec->m_varIndTab[12],
3315	dec->m_varIndTab[13],
3316	dec->m_varIndTab[14],
3317	dec->m_varIndTab[15]);
3318
3319	m_filters_per_group =
3320	(m_alfPictureParam_y->alf_flag == 0) ?
3321	1 : m_alfPictureParam_y->filters_per_group;
3322	for (i = 0; i < m_filters_per_group; i++) {
3323	data32 =
3324	((dec->m_filterCoeffSym[i][4] & 0xf) << 28) |
3325	((dec->m_filterCoeffSym[i][3] & 0x7f) << 21) |
3326	((dec->m_filterCoeffSym[i][2] & 0x7f) << 14) |
3327	((dec->m_filterCoeffSym[i][1] & 0x7f) << 7) |
3328	((dec->m_filterCoeffSym[i][0] & 0x7f) << 0);
3329	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3330	data32 =
3331	/*[31] last indication*/
3332	((i == m_filters_per_group-1) << 31) |
3333	((dec->m_filterCoeffSym[i][8] & 0x7f) << 24) |
3334	((dec->m_filterCoeffSym[i][7] & 0x7f) << 17) |
3335	((dec->m_filterCoeffSym[i][6] & 0x7f) << 10) |
3336	((dec->m_filterCoeffSym[i][5] & 0x7f) << 3) |
3337	(((dec->m_filterCoeffSym[i][4] >> 4) & 0x7) << 0);
3338	WRITE_VREG(HEVC_DBLK_CFGD, data32);
3339	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3340	"[c] alf_y_coef[%d](%d %d %d %d %d %d %d %d %d)\n",
3341	i, dec->m_filterCoeffSym[i][0],
3342	dec->m_filterCoeffSym[i][1],
3343	dec->m_filterCoeffSym[i][2],
3344	dec->m_filterCoeffSym[i][3],
3345	dec->m_filterCoeffSym[i][4],
3346	dec->m_filterCoeffSym[i][5],
3347	dec->m_filterCoeffSym[i][6],
3348	dec->m_filterCoeffSym[i][7],
3349	dec->m_filterCoeffSym[i][8]);
3350	}
3351	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
3352	"[c] cfgALF .done.\n");
3353	}
3354
3355	static void config_other_hw(struct AVS2Decoder_s *dec)
3356	{
3357	uint32_t data32;
3358	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3359	struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic;
3360	int bit_depth = cur_pic->bit_depth;
3361	int losless_comp_header_size =
3362	compute_losless_comp_header_size(
3363	dec, cur_pic->pic_w,
3364	cur_pic->pic_h);
3365	int losless_comp_body_size =
3366	compute_losless_comp_body_size(
3367	dec, cur_pic->pic_w,
3368	cur_pic->pic_h, (bit_depth == AVS2_BITS_10));
3369	cur_pic->comp_body_size = losless_comp_body_size;
3370
3371	#ifdef LOSLESS_COMPRESS_MODE
3372	data32 = READ_VREG(HEVC_SAO_CTRL5);
3373	if (bit_depth == AVS2_BITS_10)
3374	data32 &= ~(1 << 9);
3375	else
3376	data32 |= (1 << 9);
3377
3378	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3379
3380	#ifdef AVS2_10B_MMU
3381	/*bit[4] : paged_mem_mode*/
3382	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3383	#else
3384	/*bit[3] smem mdoe*/
3385	if (bit_depth == AVS2_BITS_10)
3386	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
3387	else
3388	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
3389	#endif
3390	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3391	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
3392	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3393	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3394	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3395	#else
3396	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3397	#endif
3398	}
3399
3400	static void avs2_config_work_space_hw(struct AVS2Decoder_s *dec)
3401	{
3402	struct BuffInfo_s *buf_spec = dec->work_space_buf;
3403	#ifdef LOSLESS_COMPRESS_MODE
3404	int losless_comp_header_size =
3405	compute_losless_comp_header_size(
3406	dec, dec->init_pic_w,
3407	dec->init_pic_h);
3408	int losless_comp_body_size =
3409	compute_losless_comp_body_size(dec,
3410	dec->init_pic_w,
3411	dec->init_pic_h, buf_alloc_depth == 10);
3412	#endif
3413	#ifdef AVS2_10B_MMU
3414	unsigned int data32;
3415	#endif
3416	if (debug && dec->init_flag == 0)
3417	avs2_print(dec, 0,
3418	"%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
3419	__func__,
3420	buf_spec->ipp.buf_start,
3421	buf_spec->start_adr,
3422	buf_spec->short_term_rps.buf_start,
3423	buf_spec->rcs.buf_start,
3424	buf_spec->sps.buf_start,
3425	buf_spec->pps.buf_start,
3426	buf_spec->sao_up.buf_start,
3427	buf_spec->swap_buf.buf_start,
3428	buf_spec->swap_buf2.buf_start,
3429	buf_spec->scalelut.buf_start,
3430	buf_spec->dblk_para.buf_start,
3431	buf_spec->dblk_data.buf_start,
3432	buf_spec->dblk_data2.buf_start);
3433	WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start);
3434	if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0)
3435	WRITE_VREG(HEVC_RPM_BUFFER, (u32)dec->rpm_phy_addr);
3436	WRITE_VREG(AVS2_ALF_SWAP_BUFFER, buf_spec->short_term_rps.buf_start);
3437	WRITE_VREG(HEVC_RCS_BUFFER, buf_spec->rcs.buf_start);
3438	WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);
3439	WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
3440	WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
3441	#ifdef AVS2_10B_MMU
3442	WRITE_VREG(AVS2_MMU_MAP_BUFFER, dec->frame_mmu_map_phy_addr);
3443	#else
3444	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, buf_spec->swap_buf.buf_start);
3445	#endif
3446	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start);
3447	WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
3448
3449	/* cfg_p_addr */
3450	WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
3451	/* cfg_d_addr */
3452	WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
3453
3454	WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start);
3455
3456	#ifdef LOSLESS_COMPRESS_MODE
3457	data32 = READ_VREG(HEVC_SAO_CTRL5);
3458	#if 1
3459	data32 &= ~(1<<9);
3460	#else
3461	if (params->p.bit_depth != 0x00)
3462	data32 &= ~(1<<9);
3463	else
3464	data32 |= (1<<9);
3465	#endif
3466	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3467	#ifdef AVS2_10B_MMU
3468	/*bit[4] : paged_mem_mode*/
3469	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3470	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
3471	#else
3472	/* bit[3] smem mode*/
3473	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3));
3474
3475	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3476	#endif
3477	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,(losless_comp_body_size >> 5));*/
3478	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
3479	/*8-bit mode */
3480	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3481	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3482	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3483	#else
3484	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3485	#endif
3486
3487	#ifdef AVS2_10B_MMU
3488	WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
3489	WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
3490	+ buf_spec->mmu_vbh.buf_size/2);
3491	/*data32 = READ_VREG(HEVC_SAO_CTRL9);*/
3492	/*data32 |= 0x1;*/
3493	/*WRITE_VREG(HEVC_SAO_CTRL9, data32);*/
3494
3495	/* use HEVC_CM_HEADER_START_ADDR */
3496	data32 = READ_VREG(HEVC_SAO_CTRL5);
3497	data32 |= (1<<10);
3498	#if 1
3499	if (debug & AVS2_DBG_FORCE_UNCOMPRESS)
3500	data32 |= 0x80;
3501	#endif
3502	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3503
3504	#endif
3505
3506	WRITE_VREG(LMEM_DUMP_ADR, (u32)dec->lmem_phy_addr);
3507	#if 1
3508	/*MULTI_INSTANCE_SUPPORT*/
3509	/*new added in simulation???*/
3510	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, buf_spec->mpred_above.buf_start);
3511	#endif
3512	}
3513
3514	static void decomp_perfcount_reset(void)
3515	{
3516	if (debug & AVS2_DBG_CACHE)
3517	pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3518	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3519	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3520	return;
3521	}
3522
3523	static void mcrcc_perfcount_reset(void)
3524	{
3525	if (debug & AVS2_DBG_CACHE)
3526	pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3527	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3528	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3529	return;
3530	}
3531
3532	static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec)
3533	{
3534	unsigned int data32;
3535	unsigned int decode_mode;
3536	int i;
3537
3538	/*if (debug & AVS2_DBG_BUFMGR_MORE)
3539	pr_info("%s\n", __func__);*/
3540	data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
3541	#if 1
3542	/* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
3543	data32 &= ~(7 << 29);
3544	data32 |= (3 << 29);
3545	#endif
3546	data32 = data32 |
3547	(1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
3548	(1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
3549	(1 << 7) |/*dec_done_int_cpu_enable*/
3550	(1 << 4) |/*startcode_found_int_cpu_enable*/
3551	(0 << 3) |/*startcode_found_int_amrisc_enable*/
3552	(1 << 0) /*parser_int_enable*/
3553	;
3554	WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
3555
3556	data32 = READ_VREG(HEVC_SHIFT_STATUS);
3557	data32 = data32 |
3558	(0 << 1) |/*emulation_check_off VP9
3559	do not have emulation*/
3560	(1 << 0)/*startcode_check_on*/
3561	;
3562	WRITE_VREG(HEVC_SHIFT_STATUS, data32);
3563	WRITE_VREG(HEVC_SHIFT_CONTROL,
3564	(6 << 20) | /* emu_push_bits (6-bits for AVS2)*/
3565	(0 << 19) | /* emu_3_enable, maybe turned on in microcode*/
3566	(0 << 18) | /* emu_2_enable, maybe turned on in microcode*/
3567	(0 << 17) | /* emu_1_enable, maybe turned on in microcode*/
3568	(0 << 16) | /* emu_0_enable, maybe turned on in microcode*/
3569	(0 << 14) | /*disable_start_code_protect*/
3570	(3 << 6) | /* sft_valid_wr_position*/
3571	(2 << 4) | /* emulate_code_length_sub_1*/
3572	(2 << 1) | /* start_code_length_sub_1*/
3573	(1 << 0) /* stream_shift_enable*/
3574	);
3575
3576	WRITE_VREG(HEVC_SHIFT_LENGTH_PROTECT,
3577	(0 << 30) | /*data_protect_fill_00_enable*/
3578	(1 << 29) /*data_protect_fill_ff_enable*/
3579	);
3580	WRITE_VREG(HEVC_CABAC_CONTROL,
3581	(1 << 0)/*cabac_enable*/
3582	);
3583
3584	WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
3585	(1 << 0)/* hevc_parser_core_clk_en*/
3586	);
3587
3588
3589	WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
3590
3591	/*Initial IQIT_SCALELUT memory -- just to avoid X in simulation*/
3592
3593	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
3594	for (i = 0; i < 1024; i++)
3595	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
3596
3597
3598	#ifdef ENABLE_SWAP_TEST
3599	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
3600	#else
3601	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
3602	#endif
3603	if (!dec->m_ins_flag)
3604	decode_mode = DECODE_MODE_SINGLE;
3605	else if (vdec_frame_based(hw_to_vdec(dec)))
3606	decode_mode = DECODE_MODE_MULTI_FRAMEBASE;
3607	else
3608	decode_mode = DECODE_MODE_MULTI_STREAMBASE;
3609	if (dec->avs2_dec.bufmgr_error_flag &&
3610	(error_handle_policy & 0x1)) {
3611	dec->bufmgr_error_count++;
3612	dec->avs2_dec.bufmgr_error_flag = 0;
3613	if (dec->bufmgr_error_count >
3614	(re_search_seq_threshold & 0xff)
3615	&& dec->frame_count >
3616	((re_search_seq_threshold >> 8) & 0xff)) {
3617	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
3618	dec->start_decoding_flag = 0;
3619	avs2_dec->hd.vec_flag = 1;
3620	dec->skip_PB_before_I = 1;
3621	avs2_print(dec, 0,
3622	"!!Bufmgr error, search seq again (0x%x %d %d)\n",
3623	error_handle_policy,
3624	dec->frame_count,
3625	dec->bufmgr_error_count);
3626	dec->bufmgr_error_count = 0;
3627	}
3628	}
3629	decode_mode |= (dec->start_decoding_flag << 16);
3630
3631	WRITE_VREG(DECODE_MODE, decode_mode);
3632	WRITE_VREG(HEVC_DECODE_SIZE, 0);
3633	WRITE_VREG(HEVC_DECODE_COUNT, 0);
3634
3635	/*Send parser_cmd*/
3636	WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
3637	for (i = 0; i < PARSER_CMD_NUMBER; i++)
3638	WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
3639	WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
3640	WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
3641	WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
3642
3643
3644	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
3645	(1 << 9) | /* parser_alf_if_en*/
3646	/* (1 << 8) |*/ /*sao_sw_pred_enable*/
3647	(1 << 5) | /*parser_sao_if_en*/
3648	(1 << 2) | /*parser_mpred_if_en*/
3649	(1 << 0) /*parser_scaler_if_en*/
3650	);
3651
3652	#ifdef MULTI_INSTANCE_SUPPORT
3653	WRITE_VREG(HEVC_MPRED_INT_STATUS, (1<<31));
3654
3655	WRITE_VREG(HEVC_PARSER_RESULT_3, 0xffffffff);
3656
3657	for (i = 0; i < 8; i++)
3658	data32 = READ_VREG(HEVC_MPRED_ABV_START_ADDR);
3659
3660	WRITE_VREG(DOS_SW_RESET3, (1<<18)); /* reset mpred */
3661	WRITE_VREG(DOS_SW_RESET3, 0);
3662	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3663	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3664	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, data32);
3665	#endif
3666	/*End of Multi-instance*/
3667	/*Changed to Start MPRED in microcode*/
3668	/*
3669	pr_info("[test.c] Start MPRED\n");
3670	WRITE_VREG(HEVC_MPRED_INT_STATUS,
3671	(1<<31)
3672	);
3673	*/
3674
3675	/*AVS2 default seq_wq_matrix config*/
3676
3677	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
3678	"Config AVS2 default seq_wq_matrix ...\n");
3679	/*4x4*/
3680	/* default seq_wq_matrix_4x4 begin address*/
3681	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 64);
3682	for (i = 0; i < 16; i++)
3683	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault4x4[i]);
3684
3685	/*8x8*/
3686	/*default seq_wq_matrix_8x8 begin address*/
3687	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);
3688	for (i = 0; i < 64; i++)
3689	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault8x8[i]);
3690
3691
3692	WRITE_VREG(HEVCD_IPP_TOP_CNTL,
3693	(0 << 1) | /*enable ipp*/
3694	(1 << 0) /*software reset ipp and mpp*/
3695	);
3696	WRITE_VREG(HEVCD_IPP_TOP_CNTL,
3697	(1 << 1) | /*enable ipp*/
3698	(0 << 0) /*software reset ipp and mpp*/
3699	);
3700	#if 0
3701	/*AVS2_10B_NV21*/
3702	/*Enable NV21 reference read mode for MC*/
3703	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
3704	#endif
3705	/* Init dblk*/
3706	data32 = READ_VREG(HEVC_DBLK_CFGB);
3707	data32 |= (2 << 0);
3708	/* [3:0] cfg_video_type -> AVS2*/
3709
3710	data32 &= (~0x300); /*[8]:first write enable (compress)
3711	[9]:double write enable (uncompress)*/
3712	if (get_double_write_mode(dec) == 0)
3713	data32 |= (0x1 << 8); /*enable first write*/
3714	else if (get_double_write_mode(dec) == 0x10)
3715	data32 |= (0x1 << 9); /*double write only*/
3716	else
3717	data32 |= ((0x1 << 8) | (0x1 << 9));
3718	WRITE_VREG(HEVC_DBLK_CFGB, data32);
3719
3720	WRITE_VREG(HEVC_DBLK_CFG0, (1 << 0)); /* [0] rst_sync*/
3721	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
3722	"Bitstream level Init for DBLK .Done.\n");
3723
3724	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
3725	mcrcc_perfcount_reset();
3726	decomp_perfcount_reset();
3727	}
3728
3729	return;
3730	}
3731
3732
3733	#ifdef CONFIG_HEVC_CLK_FORCED_ON
3734	static void config_avs2_clk_forced_on(void)
3735	{
3736	unsigned int rdata32;
3737	/*IQIT*/
3738	rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
3739	WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
3740
3741	/* DBLK*/
3742	rdata32 = READ_VREG(HEVC_DBLK_CFG0);
3743	WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
3744
3745	/* SAO*/
3746	rdata32 = READ_VREG(HEVC_SAO_CTRL1);
3747	WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
3748
3749	/*MPRED*/
3750	rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
3751	WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
3752
3753	/* PARSER*/
3754	rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
3755	WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
3756	rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
3757	WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
3758	rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
3759	WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
3760	rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
3761	WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
3762	rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
3763	WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
3764	rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
3765	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
3766	rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
3767
3768	/*IPP*/
3769	rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
3770	WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
3771
3772	/* MCRCC*/
3773	rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
3774	WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
3775	}
3776	#endif
3777
3778
3779
3780
3781
3782	static struct AVS2Decoder_s gAVS2Decoder;
3783
3784	static void avs2_local_uninit(struct AVS2Decoder_s *dec)
3785	{
3786	dec->rpm_ptr = NULL;
3787	dec->lmem_ptr = NULL;
3788	if (dec->rpm_addr) {
3789	dma_free_coherent(amports_get_dma_device(),
3790	RPM_BUF_SIZE, dec->rpm_addr,
3791	dec->rpm_phy_addr);
3792	dec->rpm_addr = NULL;
3793	}
3794	if (dec->lmem_addr) {
3795	if (dec->lmem_phy_addr)
3796	dma_free_coherent(amports_get_dma_device(),
3797	LMEM_BUF_SIZE, dec->lmem_addr,
3798	dec->lmem_phy_addr);
3799	dec->lmem_addr = NULL;
3800	}
3801
3802	#ifdef AVS2_10B_MMU
3803	if (dec->frame_mmu_map_addr) {
3804	if (dec->frame_mmu_map_phy_addr)
3805	dma_free_coherent(amports_get_dma_device(),
3806	get_frame_mmu_map_size(dec), dec->frame_mmu_map_addr,
3807	dec->frame_mmu_map_phy_addr);
3808	dec->frame_mmu_map_addr = NULL;
3809	}
3810	#endif
3811	if (dec->gvs)
3812	vfree(dec->gvs);
3813	dec->gvs = NULL;
3814	}
3815
3816	static int avs2_local_init(struct AVS2Decoder_s *dec)
3817	{
3818	int ret = -1;
3819	/*int losless_comp_header_size, losless_comp_body_size;*/
3820
3821	struct BuffInfo_s *cur_buf_info = NULL;
3822
3823	cur_buf_info = &dec->work_space_buf_store;
3824
3825	if (vdec_is_support_4k()) {
3826	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
3827	memcpy(cur_buf_info, &amvavs2_workbuff_spec[2], /* 8k */
3828	sizeof(struct BuffInfo_s));
3829	else
3830	memcpy(cur_buf_info, &amvavs2_workbuff_spec[1], /* 4k */
3831	sizeof(struct BuffInfo_s));
3832	} else
3833	memcpy(cur_buf_info, &amvavs2_workbuff_spec[0],/* 1080p */
3834	sizeof(struct BuffInfo_s));
3835
3836	cur_buf_info->start_adr = dec->buf_start;
3837	#ifndef AVS2_10B_MMU
3838	dec->mc_buf_spec.buf_end = dec->buf_start + dec->buf_size;
3839	#endif
3840
3841	init_buff_spec(dec, cur_buf_info);
3842
3843	init_avs2_decoder(&dec->avs2_dec);
3844
3845	#ifdef AVS2_10B_MMU
3846	avs2_bufmgr_init(dec, cur_buf_info, NULL);
3847	#else
3848	dec->mc_buf_spec.buf_start = (cur_buf_info->end_adr + 0xffff)
3849	& (~0xffff);
3850	dec->mc_buf_spec.buf_size = (dec->mc_buf_spec.buf_end
3851	- dec->mc_buf_spec.buf_start);
3852	if (debug) {
3853	pr_err("dec->mc_buf_spec.buf_start %x-%x\n",
3854	dec->mc_buf_spec.buf_start,
3855	dec->mc_buf_spec.buf_start +
3856	dec->mc_buf_spec.buf_size);
3857	}
3858	avs2_bufmgr_init(dec, cur_buf_info, &dec->mc_buf_spec);
3859	#endif
3860
3861	if (!vdec_is_support_4k()
3862	&& (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
3863	buf_alloc_width = 1920;
3864	buf_alloc_height = 1088;
3865	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
3866	buf_alloc_width = 8192;
3867	buf_alloc_height = 4608;
3868	}
3869	dec->init_pic_w = buf_alloc_width ? buf_alloc_width :
3870	(dec->vavs2_amstream_dec_info.width ?
3871	dec->vavs2_amstream_dec_info.width :
3872	dec->work_space_buf->max_width);
3873	dec->init_pic_h = buf_alloc_height ? buf_alloc_height :
3874	(dec->vavs2_amstream_dec_info.height ?
3875	dec->vavs2_amstream_dec_info.height :
3876	dec->work_space_buf->max_height);
3877	#if 0
3878	/*ndef MV_USE_FIXED_BUF*/
3879	if (init_mv_buf_list(dec) < 0) {
3880	pr_err("%s: init_mv_buf_list fail\n", __func__);
3881	return -1;
3882	}
3883	#endif
3884
3885	#ifndef AVS2_10B_MMU
3886	init_buf_list(dec);
3887	#else
3888	dec->used_buf_num = max_buf_num;
3889	if (dec->used_buf_num > MAX_BUF_NUM)
3890	dec->used_buf_num = MAX_BUF_NUM;
3891	if (dec->used_buf_num > FRAME_BUFFERS)
3892	dec->used_buf_num = FRAME_BUFFERS;
3893	#endif
3894	dec->avs2_dec.ref_maxbuffer = dec->used_buf_num - 1;
3895	/*init_pic_list(dec);*/
3896
3897	pts_unstable = ((unsigned long)(dec->vavs2_amstream_dec_info.param)
3898	& 0x40) >> 6;
3899
3900	if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) {
3901	dec->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
3902	RPM_BUF_SIZE,
3903	&dec->rpm_phy_addr, GFP_KERNEL);
3904	if (dec->rpm_addr == NULL) {
3905	pr_err("%s: failed to alloc rpm buffer\n", __func__);
3906	return -1;
3907	}
3908	avs2_print(dec, AVS2_DBG_BUFMGR,
3909	"rpm_phy_addr %x\n", (u32) dec->rpm_phy_addr);
3910	dec->rpm_ptr = dec->rpm_addr;
3911	}
3912
3913	dec->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
3914	LMEM_BUF_SIZE,
3915	&dec->lmem_phy_addr, GFP_KERNEL);
3916	if (dec->lmem_addr == NULL) {
3917	pr_err("%s: failed to alloc lmem buffer\n", __func__);
3918	return -1;
3919	} else
3920	avs2_print(dec, AVS2_DBG_BUFMGR,
3921	"%s, lmem_phy_addr %x\n",
3922	__func__, (u32)dec->lmem_phy_addr);
3923
3924	dec->lmem_ptr = dec->lmem_addr;
3925
3926
3927	#ifdef AVS2_10B_MMU
3928	dec->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(),
3929	get_frame_mmu_map_size(dec),
3930	&dec->frame_mmu_map_phy_addr, GFP_KERNEL);
3931	if (dec->frame_mmu_map_addr == NULL) {
3932	pr_err("%s: failed to alloc count_buffer\n", __func__);
3933	return -1;
3934	}
3935	memset(dec->frame_mmu_map_addr, 0, get_frame_mmu_map_size(dec));
3936	#endif
3937
3938	ret = 0;
3939	return ret;
3940	}
3941
3942	/********************************************
3943	* Mailbox command
3944	********************************************/
3945	#define CMD_FINISHED 0
3946	#define CMD_ALLOC_VIEW 1
3947	#define CMD_FRAME_DISPLAY 3
3948	#define CMD_DEBUG 10
3949
3950
3951	#define DECODE_BUFFER_NUM_MAX 32
3952	#define DISPLAY_BUFFER_NUM 6
3953
3954	#define video_domain_addr(adr) (adr&0x7fffffff)
3955	#define DECODER_WORK_SPACE_SIZE 0x800000
3956
3957	#define spec2canvas(x) \
3958	(((x)->uv_canvas_index << 16) | \
3959	((x)->uv_canvas_index << 8) | \
3960	((x)->y_canvas_index << 0))
3961
3962
3963	static void set_canvas(struct AVS2Decoder_s *dec,
3964	struct avs2_frame_s *pic)
3965	{
3966	int canvas_w = ALIGN(pic->pic_w, 64)/4;
3967	int canvas_h = ALIGN(pic->pic_h, 32)/4;
3968	int blkmode = mem_map_mode;
3969	struct vdec_s *vdec = hw_to_vdec(dec);
3970	/*CANVAS_BLKMODE_64X32*/
3971	if (pic->double_write_mode) {
3972	canvas_w = pic->pic_w /
3973	get_double_write_ratio(dec,
3974	pic->double_write_mode);
3975	canvas_h = pic->pic_h /
3976	get_double_write_ratio(dec,
3977	pic->double_write_mode);
3978
3979	if (mem_map_mode == 0)
3980	canvas_w = ALIGN(canvas_w, 32);
3981	else
3982	canvas_w = ALIGN(canvas_w, 64);
3983	canvas_h = ALIGN(canvas_h, 32);
3984
3985	if (vdec->parallel_dec == 1) {
3986	if (pic->y_canvas_index == -1)
3987	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
3988	if (pic->uv_canvas_index == -1)
3989	pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
3990	} else {
3991	pic->y_canvas_index = 128 + pic->index * 2;
3992	pic->uv_canvas_index = 128 + pic->index * 2 + 1;
3993	}
3994
3995	canvas_config_ex(pic->y_canvas_index,
3996	pic->dw_y_adr, canvas_w, canvas_h,
3997	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
3998	canvas_config_ex(pic->uv_canvas_index,
3999	pic->dw_u_v_adr, canvas_w, canvas_h,
4000	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4001	#ifdef MULTI_INSTANCE_SUPPORT
4002	pic->canvas_config[0].phy_addr =
4003	pic->dw_y_adr;
4004	pic->canvas_config[0].width =
4005	canvas_w;
4006	pic->canvas_config[0].height =
4007	canvas_h;
4008	pic->canvas_config[0].block_mode =
4009	blkmode;
4010	pic->canvas_config[0].endian = 7;
4011
4012	pic->canvas_config[1].phy_addr =
4013	pic->dw_u_v_adr;
4014	pic->canvas_config[1].width =
4015	canvas_w;
4016	pic->canvas_config[1].height =
4017	canvas_h;
4018	pic->canvas_config[1].block_mode =
4019	blkmode;
4020	pic->canvas_config[1].endian = 7;
4021	#endif
4022	} else {
4023	#ifndef AVS2_10B_MMU
4024	if (vdec->parallel_dec == 1) {
4025	if (pic->y_canvas_index == -1)
4026	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
4027	if (pic->uv_canvas_index == -1)
4028	pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
4029	} else {
4030	pic->y_canvas_index = 128 + pic->index;
4031	pic->uv_canvas_index = 128 + pic->index;
4032	}
4033
4034	canvas_config_ex(pic->y_canvas_index,
4035	pic->mc_y_adr, canvas_w, canvas_h,
4036	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4037	canvas_config_ex(pic->uv_canvas_index,
4038	pic->mc_u_v_adr, canvas_w, canvas_h,
4039	CANVAS_ADDR_NOWRAP, blkmode, 0x7);
4040	#endif
4041	}
4042	}
4043
4044	static void set_frame_info(struct AVS2Decoder_s *dec, struct vframe_s *vf)
4045	{
4046	unsigned int ar;
4047
4048	vf->duration = dec->frame_dur;
4049	vf->duration_pulldown = 0;
4050	vf->flag = 0;
4051	vf->prop.master_display_colour = dec->vf_dp;
4052	vf->signal_type = dec->video_signal_type;
4053
4054	ar = min_t(u32, dec->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
4055	vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
4056
4057	return;
4058	}
4059
4060	static int vavs2_vf_states(struct vframe_states *states, void *op_arg)
4061	{
4062	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4063
4064	states->vf_pool_size = VF_POOL_SIZE;
4065	states->buf_free_num = kfifo_len(&dec->newframe_q);
4066	states->buf_avail_num = kfifo_len(&dec->display_q);
4067
4068	if (step == 2)
4069	states->buf_avail_num = 0;
4070	return 0;
4071	}
4072
4073	static struct vframe_s *vavs2_vf_peek(void *op_arg)
4074	{
4075	struct vframe_s *vf;
4076	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4077	if (step == 2)
4078	return NULL;
4079
4080	if (force_disp_pic_index & 0x100) {
4081	if (force_disp_pic_index & 0x200)
4082	return NULL;
4083	return &dec->vframe_dummy;
4084	}
4085
4086	if (kfifo_peek(&dec->display_q, &vf))
4087	return vf;
4088
4089	return NULL;
4090	}
4091
4092	static struct avs2_frame_s *get_pic_by_index(
4093	struct AVS2Decoder_s *dec, int index)
4094	{
4095	int i;
4096	struct avs2_frame_s *pic = NULL;
4097	if (index == (dec->used_buf_num - 1))
4098	pic = dec->avs2_dec.m_bg;
4099	else if (index >= 0 && index < dec->used_buf_num) {
4100	for (i = 0; i < dec->used_buf_num; i++) {
4101	if (dec->avs2_dec.fref[i]->index == index)
4102	pic = dec->avs2_dec.fref[i];
4103	}
4104	}
4105	return pic;
4106	}
4107
4108	static struct vframe_s *vavs2_vf_get(void *op_arg)
4109	{
4110	struct vframe_s *vf;
4111	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4112	if (step == 2)
4113	return NULL;
4114	else if (step == 1)
4115	step = 2;
4116
4117	if (force_disp_pic_index & 0x100) {
4118	int idx = force_disp_pic_index & 0xff;
4119	struct avs2_frame_s *pic = NULL;
4120	if (idx >= 0
4121	&& idx < dec->avs2_dec.ref_maxbuffer)
4122	pic = get_pic_by_index(dec, idx);
4123	if (pic == NULL)
4124	return NULL;
4125	if (force_disp_pic_index & 0x200)
4126	return NULL;
4127
4128	vf = &dec->vframe_dummy;
4129
4130	set_vframe(dec, vf, pic, 1);
4131
4132	force_disp_pic_index |= 0x200;
4133	return vf;
4134	}
4135
4136	if (kfifo_get(&dec->display_q, &vf)) {
4137	uint8_t index = vf->index & 0xff;
4138	if (index >= 0 && index < dec->used_buf_num) {
4139	struct avs2_frame_s *pic = get_pic_by_index(dec, index);
4140	if (pic == NULL &&
4141	(debug & AVS2_DBG_PIC_LEAK)) {
4142	int i;
4143	avs2_print(dec, 0,
4144	"%s error index 0x%x pic not exist\n",
4145	__func__, index);
4146	dump_pic_list(dec);
4147	for (i = 0; i < 10; i++) {
4148	pic = get_pic_by_index(dec, index);
4149	pr_info("pic = %p\n", pic);
4150	}
4151
4152	if (debug & AVS2_DBG_PIC_LEAK)
4153	debug |= AVS2_DBG_PIC_LEAK_WAIT;
4154	return NULL;
4155	}
4156	dec->vf_get_count++;
4157	if (pic)
4158	avs2_print(dec, AVS2_DBG_BUFMGR,
4159	"%s index 0x%x pos %d getcount %d type 0x%x w/h %d/%d, pts %d, %lld\n",
4160	__func__, index,
4161	pic->imgtr_fwRefDistance_bak,
4162	dec->vf_get_count,
4163	vf->type,
4164	vf->width, vf->height,
4165	vf->pts,
4166	vf->pts_us64);
4167	return vf;
4168	}
4169	}
4170	return NULL;
4171	}
4172
4173	static void vavs2_vf_put(struct vframe_s *vf, void *op_arg)
4174	{
4175	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg;
4176	uint8_t index = vf->index & 0xff;
4177
4178	if (vf == (&dec->vframe_dummy))
4179	return;
4180
4181	kfifo_put(&dec->newframe_q, (const struct vframe_s *)vf);
4182	dec->vf_put_count++;
4183	avs2_print(dec, AVS2_DBG_BUFMGR,
4184	"%s index putcount 0x%x %d\n",
4185	__func__, vf->index,
4186	dec->vf_put_count);
4187
4188	if (index >= 0
4189	&& index < dec->used_buf_num) {
4190	unsigned long flags;
4191	struct avs2_frame_s *pic;
4192
4193	lock_buffer(dec, flags);
4194	pic = get_pic_by_index(dec, index);
4195	if (pic && pic->vf_ref > 0)
4196	pic->vf_ref--;
4197	else {
4198	if (pic)
4199	avs2_print(dec, 0,
4200	"%s, error pic (index %d) vf_ref is %d\n",
4201	__func__, index, pic->vf_ref);
4202	else
4203	avs2_print(dec, 0,
4204	"%s, error pic (index %d) is NULL\n",
4205	__func__, index);
4206	}
4207	if (dec->wait_buf)
4208	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
4209	0x1);
4210	dec->last_put_idx = index;
4211	dec->new_frame_displayed++;
4212	unlock_buffer(dec, flags);
4213	}
4214
4215	}
4216
4217	static int vavs2_event_cb(int type, void *data, void *private_data)
4218	{
4219	return 0;
4220	}
4221
4222	static struct avs2_frame_s *get_disp_pic(struct AVS2Decoder_s *dec)
4223	{
4224	struct avs2_decoder *avs2_dec = &dec->avs2_dec;
4225	struct avs2_frame_s *pic = NULL;
4226	int32_t j;
4227	int32_t pre_disp_count_min = 0x7fffffff;
4228	for (j = 0; j < avs2_dec->ref_maxbuffer; j++) {
4229	if (avs2_dec->fref[j]->to_prepare_disp &&
4230	avs2_dec->fref[j]->to_prepare_disp <
4231	pre_disp_count_min) {
4232	pre_disp_count_min =
4233	avs2_dec->fref[j]->to_prepare_disp;
4234	pic = avs2_dec->fref[j];
4235	}
4236	}
4237	if (pic)
4238	pic->to_prepare_disp = 0;
4239
4240	return pic;
4241
4242	}
4243
4244
4245
4246	static void fill_frame_info(struct AVS2Decoder_s *dec,
4247	struct avs2_frame_s *pic, unsigned int framesize, unsigned int pts)
4248	{
4249	struct vframe_qos_s *vframe_qos = &dec->vframe_qos;
4250
4251	if (pic->slice_type == I_IMG)
4252	vframe_qos->type = 1;
4253	else if (pic->slice_type == P_IMG)
4254	vframe_qos->type = 2;
4255	else if (pic->slice_type == B_IMG)
4256	vframe_qos->type = 3;
4257	/*
4258	#define SHOW_QOS_INFO
4259	*/
4260	vframe_qos->size = framesize;
4261	vframe_qos->pts = pts;
4262	#ifdef SHOW_QOS_INFO
4263	avs2_print(dec, 0, "slice:%d\n", pic->slice_type);
4264	#endif
4265
4266
4267	vframe_qos->max_mv = pic->max_mv;
4268	vframe_qos->avg_mv = pic->avg_mv;
4269	vframe_qos->min_mv = pic->min_mv;
4270	#ifdef SHOW_QOS_INFO
4271	avs2_print(dec, 0, "mv: max:%d, avg:%d, min:%d\n",
4272	vframe_qos->max_mv,
4273	vframe_qos->avg_mv,
4274	vframe_qos->min_mv);
4275	#endif
4276
4277	vframe_qos->max_qp = pic->max_qp;
4278	vframe_qos->avg_qp = pic->avg_qp;
4279	vframe_qos->min_qp = pic->min_qp;
4280	#ifdef SHOW_QOS_INFO
4281	avs2_print(dec, 0, "qp: max:%d, avg:%d, min:%d\n",
4282	vframe_qos->max_qp,
4283	vframe_qos->avg_qp,
4284	vframe_qos->min_qp);
4285	#endif
4286
4287	vframe_qos->max_skip = pic->max_skip;
4288	vframe_qos->avg_skip = pic->avg_skip;
4289	vframe_qos->min_skip = pic->min_skip;
4290	#ifdef SHOW_QOS_INFO
4291	avs2_print(dec, 0, "skip: max:%d, avg:%d, min:%d\n",
4292	vframe_qos->max_skip,
4293	vframe_qos->avg_skip,
4294	vframe_qos->min_skip);
4295	#endif
4296
4297	vframe_qos->num++;
4298
4299	if (dec->frameinfo_enable)
4300	vdec_fill_frame_info(vframe_qos, 1);
4301	}
4302
4303	static void set_vframe(struct AVS2Decoder_s *dec,
4304	struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy)
4305	{
4306	unsigned long flags;
4307	int stream_offset;
4308	unsigned int frame_size;
4309	int pts_discontinue;
4310	stream_offset = pic->stream_offset;
4311	avs2_print(dec, AVS2_DBG_BUFMGR,
4312	"%s index = %d pos = %d\r\n",
4313	__func__, pic->index,
4314	pic->imgtr_fwRefDistance);
4315
4316	if (pic->double_write_mode)
4317	set_canvas(dec, pic);
4318
4319	display_frame_count[dec->index]++;
4320
4321	if (!dummy) {
4322	#ifdef MULTI_INSTANCE_SUPPORT
4323	if (vdec_frame_based(hw_to_vdec(dec))) {
4324	vf->pts = pic->pts;
4325	vf->pts_us64 = pic->pts64;
4326	} else
4327	#endif
4328	/* if (pts_lookup_offset(PTS_TYPE_VIDEO,
4329	stream_offset, &vf->pts, 0) != 0) { */
4330	if (pts_lookup_offset_us64
4331	(PTS_TYPE_VIDEO, stream_offset,
4332	&vf->pts, &frame_size, 0,
4333	&vf->pts_us64) != 0) {
4334	#ifdef DEBUG_PTS
4335	dec->pts_missed++;
4336	#endif
4337	vf->pts = 0;
4338	vf->pts_us64 = 0;
4339	}
4340	#ifdef DEBUG_PTS
4341	else
4342	dec->pts_hit++;
4343	#endif
4344	if (pts_unstable)
4345	dec->pts_mode = PTS_NONE_REF_USE_DURATION;
4346
4347	fill_frame_info(dec, pic, frame_size, vf->pts);
4348
4349	if ((dec->pts_mode == PTS_NORMAL) && (vf->pts != 0)
4350	&& dec->get_frame_dur) {
4351	int pts_diff = (int)vf->pts - dec->last_lookup_pts;
4352
4353	if (pts_diff < 0) {
4354	dec->pts_mode_switching_count++;
4355	dec->pts_mode_recovery_count = 0;
4356
4357	if (dec->pts_mode_switching_count >=
4358	PTS_MODE_SWITCHING_THRESHOLD) {
4359	dec->pts_mode =
4360	PTS_NONE_REF_USE_DURATION;
4361	pr_info
4362	("HEVC: switch to n_d mode.\n");
4363	}
4364
4365	} else {
4366	int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
4367	dec->pts_mode_recovery_count++;
4368	if (dec->pts_mode_recovery_count > p) {
4369	dec->pts_mode_switching_count = 0;
4370	dec->pts_mode_recovery_count = 0;
4371	}
4372	}
4373	}
4374
4375	pts_discontinue =
4376	(abs(dec->last_pts - vf->pts) >=
4377	tsync_vpts_discontinuity_margin());
4378
4379	if (vf->pts != 0)
4380	dec->last_lookup_pts = vf->pts;
4381	#if 1
4382	if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION)
4383	&& ((pic->slice_type != I_IMG) || (!pts_discontinue &&
4384	!first_pts_checkin_complete(PTS_TYPE_AUDIO))))
4385	vf->pts = dec->last_pts + DUR2PTS(dec->frame_dur);
4386	#endif
4387	dec->last_pts = vf->pts;
4388
4389	if (vf->pts_us64 != 0)
4390	dec->last_lookup_pts_us64 = vf->pts_us64;
4391
4392	#if 1
4393	if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION)
4394	&& ((pic->slice_type != I_IMG) || (!pts_discontinue &&
4395	!first_pts_checkin_complete(PTS_TYPE_AUDIO)))) {
4396	vf->pts_us64 =
4397	dec->last_pts_us64 +
4398	(DUR2PTS(dec->frame_dur) * 100 / 9);
4399	}
4400	#endif
4401	dec->last_pts_us64 = vf->pts_us64;
4402	avs2_print(dec, AVS2_DBG_OUT_PTS,
4403	"avs2 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n",
4404	vf->pts, vf->pts_us64);
4405	}
4406
4407	vf->index = 0xff00 | pic->index;
4408
4409	if (pic->double_write_mode & 0x10) {
4410	/* double write only */
4411	vf->compBodyAddr = 0;
4412	vf->compHeadAddr = 0;
4413	} else {
4414	#ifdef AVS2_10B_MMU
4415	vf->compBodyAddr = 0;
4416	vf->compHeadAddr = pic->header_adr;
4417	#else
4418	vf->compBodyAddr = pic->mc_y_adr; /*body adr*/
4419	vf->compHeadAddr = pic->mc_y_adr +
4420	pic->comp_body_size;
4421	/*head adr*/
4422	#endif
4423	}
4424	if (pic->double_write_mode) {
4425	vf->type = VIDTYPE_PROGRESSIVE |
4426	VIDTYPE_VIU_FIELD;
4427	vf->type |= VIDTYPE_VIU_NV21;
4428	if (pic->double_write_mode == 3) {
4429	vf->type |= VIDTYPE_COMPRESS;
4430	#ifdef AVS2_10B_MMU
4431	vf->type |= VIDTYPE_SCATTER;
4432	#endif
4433	}
4434	#ifdef MULTI_INSTANCE_SUPPORT
4435	if (dec->m_ins_flag) {
4436	vf->canvas0Addr = vf->canvas1Addr = -1;
4437	vf->plane_num = 2;
4438	vf->canvas0_config[0] =
4439	pic->canvas_config[0];
4440	vf->canvas0_config[1] =
4441	pic->canvas_config[1];
4442
4443	vf->canvas1_config[0] =
4444	pic->canvas_config[0];
4445	vf->canvas1_config[1] =
4446	pic->canvas_config[1];
4447
4448	} else
4449	#endif
4450	vf->canvas0Addr = vf->canvas1Addr =
4451	spec2canvas(pic);
4452	} else {
4453	vf->canvas0Addr = vf->canvas1Addr = 0;
4454	vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
4455	#ifdef AVS2_10B_MMU
4456	vf->type |= VIDTYPE_SCATTER;
4457	#endif
4458	}
4459
4460	switch (pic->bit_depth) {
4461	case AVS2_BITS_8:
4462	vf->bitdepth = BITDEPTH_Y8 |
4463	BITDEPTH_U8 | BITDEPTH_V8;
4464	break;
4465	case AVS2_BITS_10:
4466	case AVS2_BITS_12:
4467	vf->bitdepth = BITDEPTH_Y10 |
4468	BITDEPTH_U10 | BITDEPTH_V10;
4469	break;
4470	default:
4471	vf->bitdepth = BITDEPTH_Y10 |
4472	BITDEPTH_U10 | BITDEPTH_V10;
4473	break;
4474	}
4475	if ((vf->type & VIDTYPE_COMPRESS) == 0)
4476	vf->bitdepth =
4477	BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
4478	if (pic->bit_depth == AVS2_BITS_8)
4479	vf->bitdepth |= BITDEPTH_SAVING_MODE;
4480
4481	set_frame_info(dec, vf);
4482	/* if((vf->width!=pic->width)|
4483	(vf->height!=pic->height)) */
4484	/* pr_info("aaa: %d/%d, %d/%d\n",
4485	vf->width,vf->height, pic->width,
4486	pic->height); */
4487	vf->width = pic->pic_w /
4488	get_double_write_ratio(dec,
4489	pic->double_write_mode);
4490	vf->height = pic->pic_h /
4491	get_double_write_ratio(dec,
4492	pic->double_write_mode);
4493	if (force_w_h != 0) {
4494	vf->width = (force_w_h >> 16) & 0xffff;
4495	vf->height = force_w_h & 0xffff;
4496	}
4497	vf->compWidth = pic->pic_w;
4498	vf->compHeight = pic->pic_h;
4499	if (force_fps & 0x100) {
4500	u32 rate = force_fps & 0xff;
4501	if (rate)
4502	vf->duration = 96000/rate;
4503	else
4504	vf->duration = 0;
4505	}
4506	#ifdef AVS2_10B_MMU
4507	if (vf->type & VIDTYPE_SCATTER) {
4508	vf->mem_handle = decoder_mmu_box_get_mem_handle(
4509	dec->mmu_box,
4510	pic->index);
4511	vf->mem_head_handle = decoder_bmmu_box_get_mem_handle(
4512	dec->bmmu_box,
4513	HEADER_BUFFER_IDX(pic->index));
4514	} else {
4515	vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4516	dec->bmmu_box,
4517	VF_BUFFER_IDX(pic->index));
4518	vf->mem_head_handle = decoder_bmmu_box_get_mem_handle(
4519	dec->bmmu_box,
4520	HEADER_BUFFER_IDX(pic->index));
4521	}
4522	#else
4523	vf->mem_handle = decoder_bmmu_box_get_mem_handle(
4524	dec->bmmu_box,
4525	VF_BUFFER_IDX(pic->index));
4526	#endif
4527
4528	if (!dummy) {
4529	lock_buffer(dec, flags);
4530	pic->vf_ref = 1;
4531	unlock_buffer(dec, flags);
4532	}
4533	dec->vf_pre_count++;
4534	}
4535
4536
4537	static int avs2_prepare_display_buf(struct AVS2Decoder_s *dec)
4538	{
4539	#ifndef NO_DISPLAY
4540	struct vframe_s *vf = NULL;
4541	/*unsigned short slice_type;*/
4542	struct avs2_frame_s *pic;
4543	while (1) {
4544	pic = get_disp_pic(dec);
4545	if (pic == NULL)
4546	break;
4547
4548	if (force_disp_pic_index & 0x100) {
4549	/*recycle directly*/
4550	continue;
4551	}
4552
4553	if (pic->error_mark) {
4554	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
4555	"!!!error pic, skip\n",
4556	0);
4557	continue;
4558	}
4559
4560	if (dec->start_decoding_flag != 0) {
4561	if (dec->skip_PB_before_I &&
4562	pic->slice_type != I_IMG) {
4563	avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL,
4564	"!!!slice type %d (not I) skip\n",
4565	0, pic->slice_type);
4566	continue;
4567	}
4568	dec->skip_PB_before_I = 0;
4569	}
4570
4571	if (kfifo_get(&dec->newframe_q, &vf) == 0) {
4572	pr_info("fatal error, no available buffer slot.");
4573	return -1;
4574	}
4575
4576	if (vf) {
4577	set_vframe(dec, vf, pic, 0);
4578	decoder_do_frame_check(hw_to_vdec(dec), vf);
4579	kfifo_put(&dec->display_q, (const struct vframe_s *)vf);
4580	ATRACE_COUNTER(MODULE_NAME, vf->pts);
4581
4582	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
4583	/*count info*/
4584	gvs->frame_dur = dec->frame_dur;
4585	vdec_count_info(gvs, 0, stream_offset);
4586	#endif
4587	hw_to_vdec(dec)->vdec_fps_detec(hw_to_vdec(dec)->id);
4588	if (without_display_mode == 0) {
4589	vf_notify_receiver(dec->provider_name,
4590	VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
4591	} else
4592	vavs2_vf_put(vavs2_vf_get(dec), dec);
4593	}
4594	}
4595	/*!NO_DISPLAY*/
4596	#endif
4597	return 0;
4598	}
4599
4600	static void get_rpm_param(union param_u *params)
4601	{
4602	int i;
4603	unsigned int data32;
4604	if (debug & AVS2_DBG_BUFMGR)
4605	pr_info("enter %s\r\n", __func__);
4606	for (i = 0; i < (RPM_END - RPM_BEGIN); i++) {
4607	do {
4608	data32 = READ_VREG(RPM_CMD_REG);
4609	/*pr_info("%x\n", data32);*/
4610	} while ((data32 & 0x10000) == 0);
4611	params->l.data[i] = data32&0xffff;
4612	/*pr_info("%x\n", data32);*/
4613	WRITE_VREG(RPM_CMD_REG, 0);
4614	}
4615	if (debug & AVS2_DBG_BUFMGR)
4616	pr_info("leave %s\r\n", __func__);
4617	}
4618	static void debug_buffer_mgr_more(struct AVS2Decoder_s *dec)
4619	{
4620	int i;
4621	if (!(debug & AVS2_DBG_BUFMGR_MORE))
4622	return;
4623	pr_info("avs2_param: (%d)\n", dec->avs2_dec.img.number);
4624	for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
4625	pr_info("%04x ", dec->avs2_dec.param.l.data[i]);
4626	if (((i + 1) & 0xf) == 0)
4627	pr_info("\n");
4628	}
4629	}
4630
4631	#ifdef AVS2_10B_MMU
4632	static void avs2_recycle_mmu_buf_tail(struct AVS2Decoder_s *dec)
4633	{
4634	if (dec->cur_fb_idx_mmu != INVALID_IDX) {
4635	if (dec->used_4k_num == -1) {
4636	dec->used_4k_num =
4637	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
4638	if (dec->m_ins_flag)
4639	hevc_mmu_dma_check(hw_to_vdec(dec));
4640	decoder_mmu_box_free_idx_tail(dec->mmu_box,
4641	dec->cur_fb_idx_mmu, dec->used_4k_num);
4642	}
4643	dec->cur_fb_idx_mmu = INVALID_IDX;
4644	dec->used_4k_num = -1;
4645	}
4646	}
4647
4648	static void avs2_recycle_mmu_buf(struct AVS2Decoder_s *dec)
4649	{
4650	if (dec->cur_fb_idx_mmu != INVALID_IDX) {
4651	decoder_mmu_box_free_idx(dec->mmu_box,
4652	dec->cur_fb_idx_mmu);
4653
4654	dec->cur_fb_idx_mmu = INVALID_IDX;
4655	dec->used_4k_num = -1;
4656	}
4657	}
4658	#endif
4659
4660	static void dec_again_process(struct AVS2Decoder_s *dec)
4661	{
4662	amhevc_stop();
4663	dec->dec_result = DEC_RESULT_AGAIN;
4664	if (dec->process_state ==
4665	PROC_STATE_DECODING) {
4666	dec->process_state =
4667	PROC_STATE_DECODE_AGAIN;
4668	} else if (dec->process_state ==
4669	PROC_STATE_HEAD_DONE) {
4670	dec->process_state =
4671	PROC_STATE_HEAD_AGAIN;
4672	}
4673	dec->next_again_flag = 1;
4674	reset_process_time(dec);
4675	vdec_schedule_work(&dec->work);
4676	}
4677
4678	static uint32_t log2i(uint32_t val)
4679	{
4680	uint32_t ret = -1;
4681	while (val != 0) {
4682	val >>= 1;
4683	ret++;
4684	}
4685	return ret;
4686	}
4687
4688	static void check_pic_error(struct AVS2Decoder_s *dec,
4689	struct avs2_frame_s *pic)
4690	{
4691	if (pic->decoded_lcu == 0) {
4692	pic->decoded_lcu =
4693	(READ_VREG(HEVC_PARSER_LCU_START)
4694	& 0xffffff) + 1;
4695	}
4696	if (pic->decoded_lcu != dec->avs2_dec.lcu_total) {
4697	avs2_print(dec, AVS2_DBG_BUFMGR,
4698	"%s error pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4699	__func__, pic->index, pic->imgtr_fwRefDistance,
4700	pic->decoded_lcu, dec->avs2_dec.lcu_total);
4701	pic->error_mark = 1;
4702	} else {
4703	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4704	"%s pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4705	__func__, pic->index, pic->imgtr_fwRefDistance,
4706	pic->decoded_lcu, dec->avs2_dec.lcu_total);
4707
4708	}
4709	}
4710	static void update_decoded_pic(struct AVS2Decoder_s *dec)
4711	{
4712	struct avs2_frame_s *pic = dec->avs2_dec.hc.cur_pic;
4713	if (pic) {
4714	dec->avs2_dec.hc.cur_pic->decoded_lcu =
4715	(READ_VREG(HEVC_PARSER_LCU_START)
4716	& 0xffffff) + 1;
4717	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4718	"%s pic(index %d imgtr_fwRefDistance %d) decoded lcu %d (total %d)\n",
4719	__func__, pic->index, pic->imgtr_fwRefDistance,
4720	pic->decoded_lcu, dec->avs2_dec.lcu_total);
4721	}
4722	}
4723	/* +[SE] [BUG][BUG-171463][chuanqi.wang]: get frame rate by video sequeue*/
4724	static int get_frame_rate(union param_u *params, struct AVS2Decoder_s *dec)
4725	{
4726	int tmp = 0;
4727
4728	switch (params->p.frame_rate_code) {
4729	case 1:
4730	case 2:
4731	tmp = 24;
4732	break;
4733	case 3:
4734	tmp = 25;
4735	break;
4736	case 4:
4737	case 5:
4738	tmp = 30;
4739	break;
4740	case 6:
4741	tmp = 50;
4742	break;
4743	case 7:
4744	case 8:
4745	tmp = 60;
4746	break;
4747	case 9:
4748	tmp = 100;
4749	break;
4750	case 10:
4751	tmp = 120;
4752	break;
4753	default:
4754	tmp = 25;
4755	break;
4756	}
4757
4758	if (!params->p.progressive_sequence)
4759	tmp = tmp / 2;
4760	dec->frame_dur = div_u64(96000ULL, tmp);
4761	dec->get_frame_dur = true;
4762	/*avs2_print(dec, 0, "avs2 frame_dur:%d,progressive:%d\n", dec->frame_dur, params->p.progressive_sequence);*/
4763	return 0;
4764	}
4765
4766
4767	#define HEVC_MV_INFO 0x310d
4768	#define HEVC_QP_INFO 0x3137
4769	#define HEVC_SKIP_INFO 0x3136
4770
4771	/* only when we decoded one field or one frame,
4772	we can call this function to get qos info*/
4773	static void get_picture_qos_info(struct AVS2Decoder_s *dec)
4774	{
4775	struct avs2_frame_s *picture = dec->avs2_dec.hc.cur_pic;
4776	if (!picture) {
4777	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
4778	"%s decode picture is none exist\n");
4779
4780	return;
4781	}
4782
4783	/*
4784	#define DEBUG_QOS
4785	*/
4786
4787	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4788	unsigned char a[3];
4789	unsigned char i, j, t;
4790	unsigned long data;
4791
4792	data = READ_VREG(HEVC_MV_INFO);
4793	if (picture->slice_type == I_IMG)
4794	data = 0;
4795	a[0] = data & 0xff;
4796	a[1] = (data >> 8) & 0xff;
4797	a[2] = (data >> 16) & 0xff;
4798
4799	for (i = 0; i < 3; i++)
4800	for (j = i+1; j < 3; j++) {
4801	if (a[j] < a[i]) {
4802	t = a[j];
4803	a[j] = a[i];
4804	a[i] = t;
4805	} else if (a[j] == a[i]) {
4806	a[i]++;
4807	t = a[j];
4808	a[j] = a[i];
4809	a[i] = t;
4810	}
4811	}
4812	picture->max_mv = a[2];
4813	picture->avg_mv = a[1];
4814	picture->min_mv = a[0];
4815	#ifdef DEBUG_QOS
4816	avs2_print(dec, 0, "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4817	data, a[0], a[1], a[2]);
4818	#endif
4819
4820	data = READ_VREG(HEVC_QP_INFO);
4821	a[0] = data & 0x1f;
4822	a[1] = (data >> 8) & 0x3f;
4823	a[2] = (data >> 16) & 0x7f;
4824
4825	for (i = 0; i < 3; i++)
4826	for (j = i+1; j < 3; j++) {
4827	if (a[j] < a[i]) {
4828	t = a[j];
4829	a[j] = a[i];
4830	a[i] = t;
4831	} else if (a[j] == a[i]) {
4832	a[i]++;
4833	t = a[j];
4834	a[j] = a[i];
4835	a[i] = t;
4836	}
4837	}
4838	picture->max_qp = a[2];
4839	picture->avg_qp = a[1];
4840	picture->min_qp = a[0];
4841	#ifdef DEBUG_QOS
4842	avs2_print(dec, 0, "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4843	data, a[0], a[1], a[2]);
4844	#endif
4845
4846	data = READ_VREG(HEVC_SKIP_INFO);
4847	a[0] = data & 0x1f;
4848	a[1] = (data >> 8) & 0x3f;
4849	a[2] = (data >> 16) & 0x7f;
4850
4851	for (i = 0; i < 3; i++)
4852	for (j = i+1; j < 3; j++) {
4853	if (a[j] < a[i]) {
4854	t = a[j];
4855	a[j] = a[i];
4856	a[i] = t;
4857	} else if (a[j] == a[i]) {
4858	a[i]++;
4859	t = a[j];
4860	a[j] = a[i];
4861	a[i] = t;
4862	}
4863	}
4864	picture->max_skip = a[2];
4865	picture->avg_skip = a[1];
4866	picture->min_skip = a[0];
4867
4868	#ifdef DEBUG_QOS
4869	avs2_print(dec, 0,
4870	"skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4871	data, a[0], a[1], a[2]);
4872	#endif
4873	} else {
4874	uint32_t blk88_y_count;
4875	uint32_t blk88_c_count;
4876	uint32_t blk22_mv_count;
4877	uint32_t rdata32;
4878	int32_t mv_hi;
4879	int32_t mv_lo;
4880	uint32_t rdata32_l;
4881	uint32_t mvx_L0_hi;
4882	uint32_t mvy_L0_hi;
4883	uint32_t mvx_L1_hi;
4884	uint32_t mvy_L1_hi;
4885	int64_t value;
4886	uint64_t temp_value;
4887	#ifdef DEBUG_QOS
4888	int pic_number = 0;
4889	#endif
4890
4891	picture->max_mv = 0;
4892	picture->avg_mv = 0;
4893	picture->min_mv = 0;
4894
4895	picture->max_skip = 0;
4896	picture->avg_skip = 0;
4897	picture->min_skip = 0;
4898
4899	picture->max_qp = 0;
4900	picture->avg_qp = 0;
4901	picture->min_qp = 0;
4902
4903
4904
4905	#ifdef DEBUG_QOS
4906	avs2_print(dec, 0, "slice_type:%d, poc:%d\n",
4907	picture->slice_type,
4908	pic_number);
4909	#endif
4910	/* set rd_idx to 0 */
4911	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
4912
4913	blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
4914	if (blk88_y_count == 0) {
4915	#ifdef DEBUG_QOS
4916	avs2_print(dec, 0,
4917	"[Picture %d Quality] NO Data yet.\n",
4918	pic_number);
4919	#endif
4920	/* reset all counts */
4921	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
4922	return;
4923	}
4924	/* qp_y_sum */
4925	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4926	#ifdef DEBUG_QOS
4927	avs2_print(dec, 0,
4928	"[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4929	pic_number, rdata32/blk88_y_count,
4930	rdata32, blk88_y_count);
4931	#endif
4932	picture->avg_qp = rdata32/blk88_y_count;
4933	/* intra_y_count */
4934	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4935	#ifdef DEBUG_QOS
4936	avs2_print(dec, 0,
4937	"[Picture %d Quality] Y intra rate : %d%c (%d)\n",
4938	pic_number, rdata32*100/blk88_y_count,
4939	'%', rdata32);
4940	#endif
4941	/* skipped_y_count */
4942	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4943	#ifdef DEBUG_QOS
4944	avs2_print(dec, 0,
4945	"[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4946	pic_number, rdata32*100/blk88_y_count,
4947	'%', rdata32);
4948	#endif
4949	picture->avg_skip = rdata32*100/blk88_y_count;
4950	/* coeff_non_zero_y_count */
4951	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4952	#ifdef DEBUG_QOS
4953	avs2_print(dec, 0,
4954	"[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4955	pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4956	'%', rdata32);
4957	#endif
4958	/* blk66_c_count */
4959	blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
4960	if (blk88_c_count == 0) {
4961	#ifdef DEBUG_QOS
4962	avs2_print(dec, 0,
4963	"[Picture %d Quality] NO Data yet.\n",
4964	pic_number);
4965	#endif
4966	/* reset all counts */
4967	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
4968	return;
4969	}
4970	/* qp_c_sum */
4971	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4972	#ifdef DEBUG_QOS
4973	avs2_print(dec, 0,
4974	"[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4975	pic_number, rdata32/blk88_c_count,
4976	rdata32, blk88_c_count);
4977	#endif
4978	/* intra_c_count */
4979	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4980	#ifdef DEBUG_QOS
4981	avs2_print(dec, 0,
4982	"[Picture %d Quality] C intra rate : %d%c (%d)\n",
4983	pic_number, rdata32*100/blk88_c_count,
4984	'%', rdata32);
4985	#endif
4986	/* skipped_cu_c_count */
4987	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4988	#ifdef DEBUG_QOS
4989	avs2_print(dec, 0,
4990	"[Picture %d Quality] C skipped rate : %d%c (%d)\n",
4991	pic_number, rdata32*100/blk88_c_count,
4992	'%', rdata32);
4993	#endif
4994	/* coeff_non_zero_c_count */
4995	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
4996	#ifdef DEBUG_QOS
4997	avs2_print(dec, 0,
4998	"[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4999	pic_number, (100 - rdata32*100/(blk88_c_count*1)),
5000	'%', rdata32);
5001	#endif
5002
5003	/* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
5004	1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
5005	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5006	#ifdef DEBUG_QOS
5007	avs2_print(dec, 0, "[Picture %d Quality] Y QP min : %d\n",
5008	pic_number, (rdata32>>0)&0xff);
5009	#endif
5010	picture->min_qp = (rdata32>>0)&0xff;
5011
5012	#ifdef DEBUG_QOS
5013	avs2_print(dec, 0, "[Picture %d Quality] Y QP max : %d\n",
5014	pic_number, (rdata32>>8)&0xff);
5015	#endif
5016	picture->max_qp = (rdata32>>8)&0xff;
5017
5018	#ifdef DEBUG_QOS
5019	avs2_print(dec, 0, "[Picture %d Quality] C QP min : %d\n",
5020	pic_number, (rdata32>>16)&0xff);
5021	avs2_print(dec, 0, "[Picture %d Quality] C QP max : %d\n",
5022	pic_number, (rdata32>>24)&0xff);
5023	#endif
5024
5025	/* blk22_mv_count */
5026	blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
5027	if (blk22_mv_count == 0) {
5028	#ifdef DEBUG_QOS
5029	avs2_print(dec, 0,
5030	"[Picture %d Quality] NO MV Data yet.\n",
5031	pic_number);
5032	#endif
5033	/* reset all counts */
5034	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5035	return;
5036	}
5037	/* mvy_L1_count[39:32], mvx_L1_count[39:32],
5038	mvy_L0_count[39:32], mvx_L0_count[39:32] */
5039	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5040	/* should all be 0x00 or 0xff */
5041	#ifdef DEBUG_QOS
5042	avs2_print(dec, 0,
5043	"[Picture %d Quality] MV AVG High Bits: 0x%X\n",
5044	pic_number, rdata32);
5045	#endif
5046	mvx_L0_hi = ((rdata32>>0)&0xff);
5047	mvy_L0_hi = ((rdata32>>8)&0xff);
5048	mvx_L1_hi = ((rdata32>>16)&0xff);
5049	mvy_L1_hi = ((rdata32>>24)&0xff);
5050
5051	/* mvx_L0_count[31:0] */
5052	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5053	temp_value = mvx_L0_hi;
5054	temp_value = (temp_value << 32) | rdata32_l;
5055
5056	if (mvx_L0_hi & 0x80)
5057	value = 0xFFFFFFF000000000 | temp_value;
5058	else
5059	value = temp_value;
5060	value = div_s64(value, blk22_mv_count);
5061	#ifdef DEBUG_QOS
5062	avs2_print(dec, 0,
5063	"[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
5064	pic_number, (int)value,
5065	value, blk22_mv_count);
5066	#endif
5067	picture->avg_mv = value;
5068
5069	/* mvy_L0_count[31:0] */
5070	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5071	temp_value = mvy_L0_hi;
5072	temp_value = (temp_value << 32) | rdata32_l;
5073
5074	if (mvy_L0_hi & 0x80)
5075	value = 0xFFFFFFF000000000 | temp_value;
5076	else
5077	value = temp_value;
5078	#ifdef DEBUG_QOS
5079	avs2_print(dec, 0,
5080	"[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
5081	pic_number, rdata32_l/blk22_mv_count,
5082	value, blk22_mv_count);
5083	#endif
5084
5085	/* mvx_L1_count[31:0] */
5086	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5087	temp_value = mvx_L1_hi;
5088	temp_value = (temp_value << 32) | rdata32_l;
5089	if (mvx_L1_hi & 0x80)
5090	value = 0xFFFFFFF000000000 | temp_value;
5091	else
5092	value = temp_value;
5093	#ifdef DEBUG_QOS
5094	avs2_print(dec, 0,
5095	"[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
5096	pic_number, rdata32_l/blk22_mv_count,
5097	value, blk22_mv_count);
5098	#endif
5099
5100	/* mvy_L1_count[31:0] */
5101	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
5102	temp_value = mvy_L1_hi;
5103	temp_value = (temp_value << 32) | rdata32_l;
5104	if (mvy_L1_hi & 0x80)
5105	value = 0xFFFFFFF000000000 | temp_value;
5106	else
5107	value = temp_value;
5108	#ifdef DEBUG_QOS
5109	avs2_print(dec, 0,
5110	"[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
5111	pic_number, rdata32_l/blk22_mv_count,
5112	value, blk22_mv_count);
5113	#endif
5114
5115	/* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
5116	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5117	mv_hi = (rdata32>>16)&0xffff;
5118	if (mv_hi & 0x8000)
5119	mv_hi = 0x8000 - mv_hi;
5120	#ifdef DEBUG_QOS
5121	avs2_print(dec, 0, "[Picture %d Quality] MVX_L0 MAX : %d\n",
5122	pic_number, mv_hi);
5123	#endif
5124	picture->max_mv = mv_hi;
5125
5126	mv_lo = (rdata32>>0)&0xffff;
5127	if (mv_lo & 0x8000)
5128	mv_lo = 0x8000 - mv_lo;
5129	#ifdef DEBUG_QOS
5130	avs2_print(dec, 0, "[Picture %d Quality] MVX_L0 MIN : %d\n",
5131	pic_number, mv_lo);
5132	#endif
5133	picture->min_mv = mv_lo;
5134
5135	/* {mvy_L0_max, mvy_L0_min} */
5136	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5137	mv_hi = (rdata32>>16)&0xffff;
5138	if (mv_hi & 0x8000)
5139	mv_hi = 0x8000 - mv_hi;
5140	#ifdef DEBUG_QOS
5141	avs2_print(dec, 0, "[Picture %d Quality] MVY_L0 MAX : %d\n",
5142	pic_number, mv_hi);
5143	#endif
5144
5145	mv_lo = (rdata32>>0)&0xffff;
5146	if (mv_lo & 0x8000)
5147	mv_lo = 0x8000 - mv_lo;
5148	#ifdef DEBUG_QOS
5149	avs2_print(dec, 0, "[Picture %d Quality] MVY_L0 MIN : %d\n",
5150	pic_number, mv_lo);
5151	#endif
5152
5153	/* {mvx_L1_max, mvx_L1_min} */
5154	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5155	mv_hi = (rdata32>>16)&0xffff;
5156	if (mv_hi & 0x8000)
5157	mv_hi = 0x8000 - mv_hi;
5158	#ifdef DEBUG_QOS
5159	avs2_print(dec, 0, "[Picture %d Quality] MVX_L1 MAX : %d\n",
5160	pic_number, mv_hi);
5161	#endif
5162
5163	mv_lo = (rdata32>>0)&0xffff;
5164	if (mv_lo & 0x8000)
5165	mv_lo = 0x8000 - mv_lo;
5166	#ifdef DEBUG_QOS
5167	avs2_print(dec, 0, "[Picture %d Quality] MVX_L1 MIN : %d\n",
5168	pic_number, mv_lo);
5169	#endif
5170
5171	/* {mvy_L1_max, mvy_L1_min} */
5172	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
5173	mv_hi = (rdata32>>16)&0xffff;
5174	if (mv_hi & 0x8000)
5175	mv_hi = 0x8000 - mv_hi;
5176	#ifdef DEBUG_QOS
5177	avs2_print(dec, 0, "[Picture %d Quality] MVY_L1 MAX : %d\n",
5178	pic_number, mv_hi);
5179	#endif
5180	mv_lo = (rdata32>>0)&0xffff;
5181	if (mv_lo & 0x8000)
5182	mv_lo = 0x8000 - mv_lo;
5183	#ifdef DEBUG_QOS
5184	avs2_print(dec, 0, "[Picture %d Quality] MVY_L1 MIN : %d\n",
5185	pic_number, mv_lo);
5186	#endif
5187
5188	rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
5189	#ifdef DEBUG_QOS
5190	avs2_print(dec, 0,
5191	"[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
5192	pic_number, rdata32);
5193	#endif
5194	/* reset all counts */
5195	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
5196	}
5197	}
5198
5199	static irqreturn_t vavs2_isr_thread_fn(int irq, void *data)
5200	{
5201	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data;
5202	unsigned int dec_status = dec->dec_status;
5203	int i, ret;
5204	int32_t start_code = 0;
5205
5206	/*if (dec->wait_buf)
5207	pr_info("set wait_buf to 0\r\n");
5208	*/
5209
5210	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
5211	"%s decode_status 0x%x process_state %d lcu 0x%x\n",
5212	__func__, dec_status, dec->process_state,
5213	READ_VREG(HEVC_PARSER_LCU_START));
5214
5215	#ifndef G12A_BRINGUP_DEBUG
5216	if (dec->eos) {
5217	PRINT_LINE();
5218	goto irq_handled_exit;
5219	}
5220	#endif
5221	dec->wait_buf = 0;
5222	if (dec_status == AVS2_DECODE_BUFEMPTY) {
5223	PRINT_LINE();
5224	if (dec->m_ins_flag) {
5225	reset_process_time(dec);
5226	if (!vdec_frame_based(hw_to_vdec(dec)))
5227	dec_again_process(dec);
5228	else {
5229	dec->dec_result = DEC_RESULT_DONE;
5230	reset_process_time(dec);
5231	amhevc_stop();
5232	vdec_schedule_work(&dec->work);
5233	}
5234	}
5235	goto irq_handled_exit;
5236	} else if (dec_status == HEVC_DECPIC_DATA_DONE) {
5237	PRINT_LINE();
5238	dec->start_decoding_flag |= 0x3;
5239	if (dec->m_ins_flag) {
5240	update_decoded_pic(dec);
5241	get_picture_qos_info(dec);
5242	reset_process_time(dec);
5243	dec->dec_result = DEC_RESULT_DONE;
5244	amhevc_stop();
5245	#if 0 /*def AVS2_10B_MMU*/
5246	if (dec->m_ins_flag) {
5247	/*avs2_recycle_mmu_buf_tail(dec);*/
5248	dec->used_4k_num =
5249	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
5250	}
5251	#endif
5252
5253	#if 0
5254	/*keep hardware state*/
5255	WRITE_VREG(HEVC_MPRED_INT_STATUS, (1<<31));
5256	WRITE_VREG(HEVC_PARSER_RESULT_3, 0xffffffff);
5257	dec->mpred_abv_start_addr =
5258	READ_VREG(HEVC_MPRED_ABV_START_ADDR);
5259	/**/
5260	#endif
5261	vdec_schedule_work(&dec->work);
5262	}
5263	goto irq_handled_exit;
5264	}
5265	PRINT_LINE();
5266	#if 0
5267	if (dec_status == AVS2_EOS) {
5268	if (dec->m_ins_flag)
5269	reset_process_time(dec);
5270
5271	avs2_print(dec, AVS2_DBG_BUFMGR,
5272	"AVS2_EOS, flush buffer\r\n");
5273
5274	avs2_post_process(&dec->avs2_dec);
5275	avs2_prepare_display_buf(dec);
5276
5277	avs2_print(dec, AVS2_DBG_BUFMGR,
5278	"send AVS2_10B_DISCARD_NAL\r\n");
5279	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL);
5280	if (dec->m_ins_flag) {
5281	update_decoded_pic(dec);
5282	dec->dec_result = DEC_RESULT_DONE;
5283	amhevc_stop();
5284	vdec_schedule_work(&dec->work);
5285	}
5286	goto irq_handled_exit;
5287	} else
5288	#endif
5289	if (dec_status == AVS2_DECODE_OVER_SIZE) {
5290	avs2_print(dec, 0,
5291	"avs2 decode oversize !!\n");
5292	debug |= (AVS2_DBG_DIS_LOC_ERROR_PROC |
5293	AVS2_DBG_DIS_SYS_ERROR_PROC);
5294	dec->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
5295	if (dec->m_ins_flag)
5296	reset_process_time(dec);
5297	goto irq_handled_exit;
5298	}
5299	PRINT_LINE();
5300
5301	if (dec->m_ins_flag)
5302	reset_process_time(dec);
5303
5304	if (dec_status == AVS2_HEAD_SEQ_READY)
5305	start_code = SEQUENCE_HEADER_CODE;
5306	else if (dec_status == AVS2_HEAD_PIC_I_READY)
5307	start_code = I_PICTURE_START_CODE;
5308	else if (dec_status == AVS2_HEAD_PIC_PB_READY)
5309	start_code = PB_PICTURE_START_CODE;
5310	else if (dec_status == AVS2_STARTCODE_SEARCH_DONE)
5311	/*SEQUENCE_END_CODE, VIDEO_EDIT_CODE*/
5312	start_code = READ_VREG(CUR_NAL_UNIT_TYPE);
5313
5314	if (dec->process_state ==
5315	PROC_STATE_HEAD_AGAIN
5316	) {
5317	if ((start_code == I_PICTURE_START_CODE)
5318	|| (start_code == PB_PICTURE_START_CODE)) {
5319	avs2_print(dec, 0,
5320	"PROC_STATE_HEAD_AGAIN error, start_code 0x%x!!!\r\n",
5321	start_code);
5322	goto irq_handled_exit;
5323	} else {
5324	avs2_print(dec, AVS2_DBG_BUFMGR,
5325	"PROC_STATE_HEAD_AGAIN, start_code 0x%x\r\n",
5326	start_code);
5327	dec->process_state = PROC_STATE_HEAD_DONE;
5328	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5329	goto irq_handled_exit;
5330	}
5331	} else if (dec->process_state ==
5332	PROC_STATE_DECODE_AGAIN) {
5333	if ((start_code == I_PICTURE_START_CODE)
5334	|| (start_code == PB_PICTURE_START_CODE)) {
5335	avs2_print(dec, AVS2_DBG_BUFMGR,
5336	"PROC_STATE_DECODE_AGAIN=> decode_slice, start_code 0x%x\r\n",
5337	start_code);
5338	goto decode_slice;
5339	} else {
5340	avs2_print(dec, 0,
5341	"PROC_STATE_DECODE_AGAIN, start_code 0x%x!!!\r\n",
5342	start_code);
5343	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5344	goto irq_handled_exit;
5345	}
5346	}
5347
5348	if ((start_code == I_PICTURE_START_CODE)
5349	|| (start_code == PB_PICTURE_START_CODE)
5350	|| (start_code == SEQUENCE_END_CODE)
5351	|| (start_code == VIDEO_EDIT_CODE)) {
5352	PRINT_LINE();
5353
5354	if (dec->avs2_dec.hc.cur_pic != NULL) {
5355	int32_t ii;
5356	#ifdef AVS2_10B_MMU
5357	avs2_recycle_mmu_buf_tail(dec);
5358	#endif
5359	check_pic_error(dec, dec->avs2_dec.hc.cur_pic);
5360	avs2_post_process(&dec->avs2_dec);
5361
5362	if (debug & AVS2_DBG_PRINT_PIC_LIST)
5363	dump_pic_list(dec);
5364
5365	avs2_prepare_display_buf(dec);
5366	dec->avs2_dec.hc.cur_pic = NULL;
5367	for (ii = 0; ii < dec->avs2_dec.ref_maxbuffer;
5368	ii++) {
5369	if (dec->avs2_dec.fref[ii]->
5370	bg_flag == 0 &&
5371	dec->avs2_dec.fref[ii]->
5372	is_output == -1 &&
5373	dec->avs2_dec.fref[ii]->
5374	mmu_alloc_flag &&
5375	dec->avs2_dec.fref[ii]->
5376	vf_ref == 0) {
5377	struct avs2_frame_s *pic =
5378	dec->avs2_dec.fref[ii];
5379	if (dec->avs2_dec.fref[ii]->
5380	refered_by_others == 0) {
5381	#ifdef AVS2_10B_MMU
5382	dec->avs2_dec.fref[ii]->
5383	mmu_alloc_flag = 0;
5384	/*release_buffer_4k(
5385	dec->avs2_dec.fref[ii]->index);*/
5386	decoder_mmu_box_free_idx(dec->mmu_box,
5387	dec->avs2_dec.fref[ii]->index);
5388	#ifdef DYNAMIC_ALLOC_HEAD
5389	decoder_bmmu_box_free_idx(
5390	dec->bmmu_box,
5391	HEADER_BUFFER_IDX(pic->index));
5392	pic->header_adr = 0;
5393	#endif
5394	#endif
5395	#ifndef MV_USE_FIXED_BUF
5396	decoder_bmmu_box_free_idx(
5397	dec->bmmu_box,
5398	MV_BUFFER_IDX(pic->index));
5399	pic->mpred_mv_wr_start_addr = 0;
5400	#endif
5401	}
5402	decoder_bmmu_box_free_idx(
5403	dec->bmmu_box,
5404	VF_BUFFER_IDX(pic->index));
5405	dec->cma_alloc_addr = 0;
5406	}
5407	}
5408	}
5409	}
5410
5411	if ((dec_status == AVS2_HEAD_PIC_I_READY)
5412	|| (dec_status == AVS2_HEAD_PIC_PB_READY)) {
5413	PRINT_LINE();
5414
5415	if (debug & AVS2_DBG_SEND_PARAM_WITH_REG) {
5416	get_rpm_param(
5417	&dec->avs2_dec.param);
5418	} else {
5419
5420	for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
5421	int ii;
5422	for (ii = 0; ii < 4; ii++)
5423	dec->avs2_dec.param.l.data[i + ii] =
5424	dec->rpm_ptr[i + 3 - ii];
5425	}
5426	}
5427	#ifdef SANITY_CHECK
5428	if (dec->avs2_dec.param.p.num_of_ref_cur >
5429	dec->avs2_dec.ref_maxbuffer) {
5430	pr_info("Warning: Wrong num_of_ref_cur %d, force to %d\n",
5431	dec->avs2_dec.param.p.num_of_ref_cur,
5432	dec->avs2_dec.ref_maxbuffer);
5433	dec->avs2_dec.param.p.num_of_ref_cur =
5434	dec->avs2_dec.ref_maxbuffer;
5435	}
5436	#endif
5437	PRINT_LINE();
5438
5439	debug_buffer_mgr_more(dec);
5440	get_frame_rate(&dec->avs2_dec.param, dec);
5441
5442	if (dec->avs2_dec.param.p.video_signal_type
5443	& (1<<30)) {
5444	union param_u *pPara;
5445
5446	avs2_print(dec, 0,
5447	"avs2 HDR meta data present\n");
5448	pPara = &dec->avs2_dec.param;
5449
5450	/*clean this flag*/
5451	pPara->p.video_signal_type
5452	&= ~(1<<30);
5453
5454	dec->vf_dp.present_flag = 1;
5455
5456	dec->vf_dp.white_point[0]
5457	= pPara->p.white_point_x;
5458	avs2_print(dec, AVS2_DBG_HDR_INFO,
5459	"white_point[0]:0x%x\n",
5460	dec->vf_dp.white_point[0]);
5461
5462	dec->vf_dp.white_point[1]
5463	= pPara->p.white_point_y;
5464	avs2_print(dec, AVS2_DBG_HDR_INFO,
5465	"white_point[1]:0x%x\n",
5466	dec->vf_dp.white_point[1]);
5467
5468	for (i = 0; i < 3; i++) {
5469	dec->vf_dp.primaries[i][0]
5470	= pPara->p.display_primaries_x[i];
5471	avs2_print(dec, AVS2_DBG_HDR_INFO,
5472	"primaries[%d][0]:0x%x\n",
5473	i,
5474	dec->vf_dp.primaries[i][0]);
5475	}
5476
5477	for (i = 0; i < 3; i++) {
5478	dec->vf_dp.primaries[i][1]
5479	= pPara->p.display_primaries_y[i];
5480	avs2_print(dec, AVS2_DBG_HDR_INFO,
5481	"primaries[%d][1]:0x%x\n",
5482	i,
5483	dec->vf_dp.primaries[i][1]);
5484	}
5485
5486	dec->vf_dp.luminance[0]
5487	= pPara->p.max_display_mastering_luminance;
5488	avs2_print(dec, AVS2_DBG_HDR_INFO,
5489	"luminance[0]:0x%x\n",
5490	dec->vf_dp.luminance[0]);
5491
5492	dec->vf_dp.luminance[1]
5493	= pPara->p.min_display_mastering_luminance;
5494	avs2_print(dec, AVS2_DBG_HDR_INFO,
5495	"luminance[1]:0x%x\n",
5496	dec->vf_dp.luminance[1]);
5497
5498
5499	dec->vf_dp.content_light_level.present_flag
5500	= 1;
5501	dec->vf_dp.content_light_level.max_content
5502	= pPara->p.max_content_light_level;
5503	avs2_print(dec, AVS2_DBG_HDR_INFO,
5504	"max_content:0x%x\n",
5505	dec->vf_dp.content_light_level.max_content);
5506
5507	dec->vf_dp.content_light_level.max_pic_average
5508	= pPara->p.max_picture_average_light_level;
5509
5510	avs2_print(dec, AVS2_DBG_HDR_INFO,
5511	"max_pic_average:0x%x\n",
5512	dec->vf_dp.content_light_level.max_pic_average);
5513	}
5514
5515
5516	if (dec->video_ori_signal_type !=
5517	((dec->avs2_dec.param.p.video_signal_type << 16)
5518	| dec->avs2_dec.param.p.color_description)) {
5519	u32 v = dec->avs2_dec.param.p.video_signal_type;
5520	u32 c = dec->avs2_dec.param.p.color_description;
5521	u32 convert_c = c;
5522
5523	if (v & 0x2000) {
5524	avs2_print(dec, 0,
5525	"video_signal_type present:\n");
5526	avs2_print(dec, 0,
5527	" %s %s\n",
5528	video_format_names[(v >> 10) & 7],
5529	((v >> 9) & 1) ?
5530	"full_range" : "limited");
5531	if (v & 0x100) {
5532	u32 transfer;
5533	u32 maxtrix;
5534
5535	avs2_print(dec, 0,
5536	"color_description present:\n");
5537	avs2_print(dec, 0,
5538	"color_primarie = %d\n",
5539	v & 0xff);
5540	avs2_print(dec, 0,
5541	"transfer_characteristic = %d\n",
5542	(c >> 8) & 0xff);
5543	avs2_print(dec, 0,
5544	" matrix_coefficient = %d\n",
5545	c & 0xff);
5546
5547	transfer = (c >> 8) & 0xFF;
5548	if (transfer >= 15)
5549	avs2_print(dec, 0,
5550	"unsupport transfer_characteristic\n");
5551	else if (transfer == 14)
5552	transfer = 18; /* HLG */
5553	else if (transfer == 13)
5554	transfer = 32;
5555	else if (transfer == 12)
5556	transfer = 16;
5557	else if (transfer == 11)
5558	transfer = 15;
5559
5560	maxtrix = c & 0xFF;
5561	if (maxtrix >= 10)
5562	avs2_print(dec, 0,
5563	"unsupport matrix_coefficient\n");
5564	else if (maxtrix == 9)
5565	maxtrix = 10;
5566	else if (maxtrix == 8)
5567	maxtrix = 9;
5568
5569	convert_c = (transfer << 8) | (maxtrix);
5570
5571	avs2_print(dec, 0,
5572	" convered c:0x%x\n",
5573	convert_c);
5574	}
5575	}
5576
5577	if (enable_force_video_signal_type)
5578	dec->video_signal_type
5579	= force_video_signal_type;
5580	else {
5581	dec->video_signal_type
5582	= (v << 16) | convert_c;
5583
5584	dec->video_ori_signal_type
5585	= (v << 16) | c;
5586	}
5587
5588	video_signal_type = dec->video_signal_type;
5589	}
5590	}
5591	#if 0
5592	if ((debug_again & 0x4) &&
5593	dec->process_state ==
5594	PROC_STATE_INIT) {
5595	if (start_code == PB_PICTURE_START_CODE) {
5596	dec->process_state = PROC_STATE_TEST1;
5597	dec_again_process(dec);
5598	goto irq_handled_exit;
5599	}
5600	}
5601	#endif
5602	PRINT_LINE();
5603	avs2_prepare_header(&dec->avs2_dec, start_code);
5604
5605	if (start_code == SEQUENCE_HEADER_CODE ||
5606	start_code == VIDEO_EDIT_CODE ||
5607	start_code == SEQUENCE_END_CODE) {
5608	if (dec->m_ins_flag &&
5609	vdec_frame_based(hw_to_vdec(dec)))
5610	dec->start_decoding_flag |= 0x1;
5611	dec->process_state = PROC_STATE_HEAD_DONE;
5612	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5613	} else if (start_code == I_PICTURE_START_CODE ||
5614	start_code == PB_PICTURE_START_CODE) {
5615	ret = 0;
5616	if (dec->pic_list_init_flag == 0) {
5617	int32_t lcu_size_log2 =
5618	log2i(dec->avs2_dec.param.p.lcu_size);
5619
5620	avs2_init_global_buffers(&dec->avs2_dec);
5621	/*avs2_dec->m_bg->index is
5622	set to dec->used_buf_num - 1*/
5623	init_pic_list(dec, lcu_size_log2);
5624	init_pic_list_hw(dec);
5625	}
5626	ret = avs2_process_header(&dec->avs2_dec);
5627	if (!dec->m_ins_flag)
5628	dec->slice_idx++;
5629
5630	PRINT_LINE();
5631	#ifdef I_ONLY_SUPPORT
5632	if ((start_code == PB_PICTURE_START_CODE) &&
5633	(dec->i_only & 0x2))
5634	ret = -2;
5635	#endif
5636	#ifdef AVS2_10B_MMU
5637	if (ret >= 0) {
5638	ret = avs2_alloc_mmu(dec,
5639	dec->avs2_dec.hc.cur_pic->index,
5640	dec->avs2_dec.img.width,
5641	dec->avs2_dec.img.height,
5642	dec->avs2_dec.input.sample_bit_depth,
5643	dec->frame_mmu_map_addr);
5644	if (ret >= 0) {
5645	dec->cur_fb_idx_mmu =
5646	dec->avs2_dec.hc.cur_pic->index;
5647	dec->avs2_dec.hc.cur_pic->mmu_alloc_flag = 1;
5648	} else
5649	pr_err("can't alloc need mmu1,idx %d ret =%d\n",
5650	dec->avs2_dec.hc.cur_pic->index,
5651	ret);
5652	}
5653	#endif
5654
5655	#ifndef MV_USE_FIXED_BUF
5656	if (ret >= 0 &&
5657	dec->avs2_dec.hc.cur_pic->
5658	mpred_mv_wr_start_addr == 0) {
5659	unsigned long buf_addr;
5660	unsigned mv_buf_size = 0x120000;
5661	int i = dec->avs2_dec.hc.cur_pic->index;
5662	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
5663	mv_buf_size = 0x120000 * 4;
5664	if (decoder_bmmu_box_alloc_buf_phy
5665	(dec->bmmu_box,
5666	MV_BUFFER_IDX(i),
5667	mv_buf_size,
5668	DRIVER_NAME,
5669	&buf_addr) < 0)
5670	ret = -1;
5671	else
5672	dec->avs2_dec.hc.cur_pic->
5673	mpred_mv_wr_start_addr
5674	= buf_addr;
5675	}
5676	#endif
5677	if (ret < 0) {
5678	avs2_print(dec, AVS2_DBG_BUFMGR,
5679	"avs2_bufmgr_process=> %d, AVS2_10B_DISCARD_NAL\r\n",
5680	ret);
5681	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL);
5682	#ifdef AVS2_10B_MMU
5683	avs2_recycle_mmu_buf(dec);
5684	#endif
5685	if (dec->m_ins_flag) {
5686	dec->dec_result = DEC_RESULT_DONE;
5687	amhevc_stop();
5688	vdec_schedule_work(&dec->work);
5689	}
5690
5691	goto irq_handled_exit;
5692	} else {
5693	PRINT_LINE();
5694	dec->avs2_dec.hc.cur_pic->stream_offset =
5695	READ_VREG(HEVC_SHIFT_BYTE_COUNT);
5696	/*
5697	struct PIC_BUFFER_CONFIG_s *cur_pic
5698	= &cm->cur_frame->buf;
5699	cur_pic->decode_idx = dec->frame_count;
5700	*/
5701	if (!dec->m_ins_flag) {
5702	dec->frame_count++;
5703	decode_frame_count[dec->index]
5704	= dec->frame_count;
5705	}
5706	/*MULTI_INSTANCE_SUPPORT*/
5707	if (dec->chunk) {
5708	dec->avs2_dec.hc.cur_pic->pts =
5709	dec->chunk->pts;
5710	dec->avs2_dec.hc.cur_pic->pts64 =
5711	dec->chunk->pts64;
5712	}
5713	/**/
5714	dec->avs2_dec.hc.cur_pic->bit_depth
5715	= dec->avs2_dec.input.sample_bit_depth;
5716	dec->avs2_dec.hc.cur_pic->double_write_mode
5717	= get_double_write_mode(dec);
5718	decode_slice:
5719	PRINT_LINE();
5720
5721	config_mc_buffer(dec);
5722	config_mcrcc_axi_hw(dec);
5723	config_mpred_hw(dec);
5724	config_dblk_hw(dec);
5725	config_sao_hw(dec);
5726	config_alf_hw(dec);
5727	config_other_hw(dec);
5728
5729	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
5730	"=>fref0 imgtr_fwRefDistance %d, fref1 imgtr_fwRefDistance %d, dis2/dis3/dis4 %d %d %d img->tr %d\n",
5731	dec->avs2_dec.fref[0]->imgtr_fwRefDistance,
5732	dec->avs2_dec.fref[1]->imgtr_fwRefDistance,
5733	dec->avs2_dec.fref[2]->imgtr_fwRefDistance,
5734	dec->avs2_dec.fref[3]->imgtr_fwRefDistance,
5735	dec->avs2_dec.fref[4]->imgtr_fwRefDistance,
5736	dec->avs2_dec.img.tr);
5737
5738	if ((debug_again & 0x2) &&
5739	dec->process_state ==
5740	PROC_STATE_INIT) {
5741	dec->process_state = PROC_STATE_DECODING;
5742	dec_again_process(dec);
5743	goto irq_handled_exit;
5744	}
5745
5746	dec->process_state = PROC_STATE_DECODING;
5747
5748	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
5749
5750	}
5751
5752	if (dec->m_ins_flag)
5753	start_process_time(dec);
5754	}
5755	irq_handled_exit:
5756	PRINT_LINE();
5757	dec->process_busy = 0;
5758	return IRQ_HANDLED;
5759	}
5760
5761	static irqreturn_t vavs2_isr(int irq, void *data)
5762	{
5763	int i;
5764	unsigned int dec_status;
5765	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data;
5766	uint debug_tag;
5767
5768	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
5769
5770	dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
5771
5772	if (!dec)
5773	return IRQ_HANDLED;
5774	if (dec->init_flag == 0)
5775	return IRQ_HANDLED;
5776	if (dec->process_busy)/*on process.*/
5777	return IRQ_HANDLED;
5778	dec->dec_status = dec_status;
5779	dec->process_busy = 1;
5780	if (debug & AVS2_DBG_IRQ_EVENT)
5781	avs2_print(dec, 0,
5782	"avs2 isr dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
5783	dec_status, READ_VREG(HEVC_PARSER_LCU_START),
5784	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
5785	READ_VREG(HEVC_STREAM_START_ADDR),
5786	READ_VREG(HEVC_STREAM_END_ADDR),
5787	READ_VREG(HEVC_STREAM_LEVEL),
5788	READ_VREG(HEVC_STREAM_WR_PTR),
5789	READ_VREG(HEVC_STREAM_RD_PTR)
5790	);
5791
5792	debug_tag = READ_HREG(DEBUG_REG1);
5793	if (debug_tag & 0x10000) {
5794	dma_sync_single_for_cpu(
5795	amports_get_dma_device(),
5796	dec->lmem_phy_addr,
5797	LMEM_BUF_SIZE,
5798	DMA_FROM_DEVICE);
5799
5800	pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
5801	for (i = 0; i < 0x400; i += 4) {
5802	int ii;
5803	if ((i & 0xf) == 0)
5804	pr_info("%03x: ", i);
5805	for (ii = 0; ii < 4; ii++) {
5806	pr_info("%04x ",
5807	dec->lmem_ptr[i + 3 - ii]);
5808	}
5809	if (((i + ii) & 0xf) == 0)
5810	pr_info("\n");
5811	}
5812
5813	if (((udebug_pause_pos & 0xffff)
5814	== (debug_tag & 0xffff)) &&
5815	(udebug_pause_decode_idx == 0 ||
5816	udebug_pause_decode_idx == dec->decode_idx) &&
5817	(udebug_pause_val == 0 ||
5818	udebug_pause_val == READ_HREG(DEBUG_REG2))) {
5819	udebug_pause_pos &= 0xffff;
5820	dec->ucode_pause_pos = udebug_pause_pos;
5821	} else if (debug_tag & 0x20000)
5822	dec->ucode_pause_pos = 0xffffffff;
5823	if (dec->ucode_pause_pos)
5824	reset_process_time(dec);
5825	else
5826	WRITE_HREG(DEBUG_REG1, 0);
5827	} else if (debug_tag != 0) {
5828	pr_info(
5829	"dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
5830	READ_HREG(DEBUG_REG2),
5831	READ_VREG(HEVC_PARSER_LCU_START));
5832	if (((udebug_pause_pos & 0xffff)
5833	== (debug_tag & 0xffff)) &&
5834	(udebug_pause_decode_idx == 0 ||
5835	udebug_pause_decode_idx == dec->decode_idx) &&
5836	(udebug_pause_val == 0 ||
5837	udebug_pause_val == READ_HREG(DEBUG_REG2))) {
5838	udebug_pause_pos &= 0xffff;
5839	dec->ucode_pause_pos = udebug_pause_pos;
5840	}
5841	if (dec->ucode_pause_pos)
5842	reset_process_time(dec);
5843	else
5844	WRITE_HREG(DEBUG_REG1, 0);
5845	dec->process_busy = 0;
5846	return IRQ_HANDLED;
5847	}
5848
5849	if (!dec->m_ins_flag) {
5850	if (dec->error_flag == 1) {
5851	dec->error_flag = 2;
5852	dec->process_busy = 0;
5853	return IRQ_HANDLED;
5854	} else if (dec->error_flag == 3) {
5855	dec->process_busy = 0;
5856	return IRQ_HANDLED;
5857	}
5858
5859	if ((dec->pic_list_init_flag) &&
5860	get_free_buf_count(dec) <= 0) {
5861	/*
5862	if (dec->wait_buf == 0)
5863	pr_info("set wait_buf to 1\r\n");
5864	*/
5865	dec->wait_buf = 1;
5866	dec->process_busy = 0;
5867	if (debug & AVS2_DBG_IRQ_EVENT)
5868	avs2_print(dec, 0, "wait_buf\n");
5869	return IRQ_HANDLED;
5870	} else if (force_disp_pic_index) {
5871	dec->process_busy = 0;
5872	return IRQ_HANDLED;
5873	}
5874	}
5875	return IRQ_WAKE_THREAD;
5876	}
5877
5878	static void vavs2_put_timer_func(unsigned long arg)
5879	{
5880	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)arg;
5881	struct timer_list *timer = &dec->timer;
5882	uint8_t empty_flag;
5883	unsigned int buf_level;
5884
5885	enum receviver_start_e state = RECEIVER_INACTIVE;
5886	if (dec->m_ins_flag) {
5887	if (hw_to_vdec(dec)->next_status
5888	== VDEC_STATUS_DISCONNECTED) {
5889	dec->dec_result = DEC_RESULT_FORCE_EXIT;
5890	vdec_schedule_work(&dec->work);
5891	avs2_print(dec, AVS2_DBG_BUFMGR,
5892	"vdec requested to be disconnected\n");
5893	return;
5894	}
5895	}
5896	if (dec->init_flag == 0) {
5897	if (dec->stat & STAT_TIMER_ARM) {
5898	timer->expires = jiffies + PUT_INTERVAL;
5899	add_timer(&dec->timer);
5900	}
5901	return;
5902	}
5903	if (dec->m_ins_flag == 0) {
5904	if (vf_get_receiver(dec->provider_name)) {
5905	state =
5906	vf_notify_receiver(dec->provider_name,
5907	VFRAME_EVENT_PROVIDER_QUREY_STATE,
5908	NULL);
5909	if ((state == RECEIVER_STATE_NULL)
5910	|| (state == RECEIVER_STATE_NONE))
5911	state = RECEIVER_INACTIVE;
5912	} else
5913	state = RECEIVER_INACTIVE;
5914
5915	empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
5916	/* error watchdog */
5917	if (empty_flag == 0) {
5918	/* decoder has input */
5919	if ((debug & AVS2_DBG_DIS_LOC_ERROR_PROC) == 0) {
5920
5921	buf_level = READ_VREG(HEVC_STREAM_LEVEL);
5922	/* receiver has no buffer to recycle */
5923	if ((state == RECEIVER_INACTIVE) &&
5924	(kfifo_is_empty(&dec->display_q) &&
5925	buf_level > 0x200)
5926	) {
5927	WRITE_VREG
5928	(HEVC_ASSIST_MBOX0_IRQ_REG,
5929	0x1);
5930	}
5931	}
5932
5933	if ((debug & AVS2_DBG_DIS_SYS_ERROR_PROC) == 0) {
5934	/* receiver has no buffer to recycle */
5935	/*if ((state == RECEIVER_INACTIVE) &&
5936	(kfifo_is_empty(&dec->display_q))) {
5937	pr_info("avs2 something error,need reset\n");
5938	}*/
5939	}
5940	}
5941	} else {
5942	if (
5943	(decode_timeout_val > 0) &&
5944	(dec->start_process_time > 0) &&
5945	((1000 * (jiffies - dec->start_process_time) / HZ)
5946	> decode_timeout_val)
5947	) {
5948	int current_lcu_idx =
5949	READ_VREG(HEVC_PARSER_LCU_START)
5950	& 0xffffff;
5951	if (dec->last_lcu_idx == current_lcu_idx) {
5952	if (dec->decode_timeout_count > 0)
5953	dec->decode_timeout_count--;
5954	if (dec->decode_timeout_count == 0) {
5955	if (input_frame_based(
5956	hw_to_vdec(dec)) ||
5957	(READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
5958	timeout_process(dec);
5959	else {
5960	avs2_print(dec, 0,
5961	"timeout & empty, again\n");
5962	dec_again_process(dec);
5963	}
5964	}
5965	} else {
5966	start_process_time(dec);
5967	dec->last_lcu_idx = current_lcu_idx;
5968	}
5969	}
5970	}
5971
5972	if ((dec->ucode_pause_pos != 0) &&
5973	(dec->ucode_pause_pos != 0xffffffff) &&
5974	udebug_pause_pos != dec->ucode_pause_pos) {
5975	dec->ucode_pause_pos = 0;
5976	WRITE_HREG(DEBUG_REG1, 0);
5977	}
5978	if (debug & AVS2_DBG_DUMP_DATA) {
5979	debug &= ~AVS2_DBG_DUMP_DATA;
5980	avs2_print(dec, 0,
5981	"%s: chunk size 0x%x off 0x%x sum 0x%x\n",
5982	__func__,
5983	dec->chunk->size,
5984	dec->chunk->offset,
5985	get_data_check_sum(dec, dec->chunk->size)
5986	);
5987	dump_data(dec, dec->chunk->size);
5988	}
5989	if (debug & AVS2_DBG_DUMP_PIC_LIST) {
5990	dump_pic_list(dec);
5991	debug &= ~AVS2_DBG_DUMP_PIC_LIST;
5992	}
5993	if (debug & AVS2_DBG_TRIG_SLICE_SEGMENT_PROC) {
5994	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
5995	debug &= ~AVS2_DBG_TRIG_SLICE_SEGMENT_PROC;
5996	}
5997	if (debug & AVS2_DBG_DUMP_RPM_BUF) {
5998	int i;
5999	pr_info("RPM:\n");
6000	for (i = 0; i < RPM_BUF_SIZE; i += 4) {
6001	int ii;
6002	if ((i & 0xf) == 0)
6003	pr_info("%03x: ", i);
6004	for (ii = 0; ii < 4; ii++) {
6005	pr_info("%04x ",
6006	dec->lmem_ptr[i + 3 - ii]);
6007	}
6008	if (((i + ii) & 0xf) == 0)
6009	pr_info("\n");
6010	}
6011	debug &= ~AVS2_DBG_DUMP_RPM_BUF;
6012	}
6013	if (debug & AVS2_DBG_DUMP_LMEM_BUF) {
6014	int i;
6015	pr_info("LMEM:\n");
6016	for (i = 0; i < LMEM_BUF_SIZE; i += 4) {
6017	int ii;
6018	if ((i & 0xf) == 0)
6019	pr_info("%03x: ", i);
6020	for (ii = 0; ii < 4; ii++) {
6021	pr_info("%04x ",
6022	dec->lmem_ptr[i + 3 - ii]);
6023	}
6024	if (((i + ii) & 0xf) == 0)
6025	pr_info("\n");
6026	}
6027	debug &= ~AVS2_DBG_DUMP_LMEM_BUF;
6028	}
6029	/*if (debug & AVS2_DBG_HW_RESET) {
6030	}*/
6031
6032	if (radr != 0) {
6033	if (rval != 0) {
6034	WRITE_VREG(radr, rval);
6035	pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6036	} else
6037	pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6038	rval = 0;
6039	radr = 0;
6040	}
6041	if (pop_shorts != 0) {
6042	int i;
6043	u32 sum = 0;
6044	pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
6045	for (i = 0; i < pop_shorts; i++) {
6046	u32 data =
6047	(READ_HREG(HEVC_SHIFTED_DATA) >> 16);
6048	WRITE_HREG(HEVC_SHIFT_COMMAND,
6049	(1<<7)|16);
6050	if ((i & 0xf) == 0)
6051	pr_info("%04x:", i);
6052	pr_info("%04x ", data);
6053	if (((i + 1) & 0xf) == 0)
6054	pr_info("\r\n");
6055	sum += data;
6056	}
6057	pr_info("\r\nsum = %x\r\n", sum);
6058	pop_shorts = 0;
6059	}
6060	if (dbg_cmd != 0) {
6061	if (dbg_cmd == 1) {
6062	u32 disp_laddr;
6063	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
6064	get_double_write_mode(dec) == 0) {
6065	disp_laddr =
6066	READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
6067	} else {
6068	struct canvas_s cur_canvas;
6069	canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
6070	& 0xff), &cur_canvas);
6071	disp_laddr = cur_canvas.addr;
6072	}
6073	pr_info("current displayed buffer address %x\r\n",
6074	disp_laddr);
6075	}
6076	dbg_cmd = 0;
6077	}
6078	/*don't changed at start.*/
6079	if (dec->get_frame_dur && dec->show_frame_num > 60 &&
6080	dec->frame_dur > 0 && dec->saved_resolution !=
6081	frame_width * frame_height *
6082	(96000 / dec->frame_dur)) {
6083	int fps = 96000 / dec->frame_dur;
6084	if (hevc_source_changed(VFORMAT_AVS2,
6085	frame_width, frame_height, fps) > 0)
6086	dec->saved_resolution = frame_width *
6087	frame_height * fps;
6088	}
6089
6090	timer->expires = jiffies + PUT_INTERVAL;
6091	add_timer(timer);
6092	}
6093
6094
6095	int vavs2_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6096	{
6097	struct AVS2Decoder_s *dec =
6098	(struct AVS2Decoder_s *)vdec->private;
6099
6100	if (!dec)
6101	return -1;
6102
6103	vstatus->frame_width = dec->frame_width;
6104	vstatus->frame_height = dec->frame_height;
6105
6106	if (dec->frame_dur != 0)
6107	vstatus->frame_rate = 96000 / dec->frame_dur;
6108	else
6109	vstatus->frame_rate = -1;
6110	vstatus->error_count = 0;
6111	vstatus->status = dec->stat | dec->fatal_error;
6112	vstatus->frame_dur = dec->frame_dur;
6113	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
6114	vstatus->bit_rate = gvs->bit_rate;
6115	vstatus->frame_data = gvs->frame_data;
6116	vstatus->total_data = gvs->total_data;
6117	vstatus->frame_count = gvs->frame_count;
6118	vstatus->error_frame_count = gvs->error_frame_count;
6119	vstatus->drop_frame_count = gvs->drop_frame_count;
6120	vstatus->total_data = gvs->total_data;
6121	vstatus->samp_cnt = gvs->samp_cnt;
6122	vstatus->offset = gvs->offset;
6123	snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6124	"%s", DRIVER_NAME);
6125	#endif
6126	return 0;
6127	}
6128
6129	int vavs2_set_isreset(struct vdec_s *vdec, int isreset)
6130	{
6131	is_reset = isreset;
6132	return 0;
6133	}
6134
6135	static void vavs2_prot_init(struct AVS2Decoder_s *dec)
6136	{
6137	unsigned int data32;
6138
6139	avs2_config_work_space_hw(dec);
6140	if (dec->pic_list_init_flag)
6141	init_pic_list_hw(dec);
6142
6143	avs2_init_decoder_hw(dec);
6144
6145	#if 1
6146	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
6147	"%s\n", __func__);
6148	data32 = READ_VREG(HEVC_STREAM_CONTROL);
6149	data32 = data32 |
6150	(1 << 0)/*stream_fetch_enable*/
6151	;
6152	WRITE_VREG(HEVC_STREAM_CONTROL, data32);
6153	#if 0
6154	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
6155	if (data32 != 0x00000100) {
6156	pr_info("avs2 prot init error %d\n", __LINE__);
6157	return;
6158	}
6159	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
6160	if (data32 != 0x00000300) {
6161	pr_info("avs2 prot init error %d\n", __LINE__);
6162	return;
6163	}
6164	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
6165	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
6166	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
6167	if (data32 != 0x12345678) {
6168	pr_info("avs2 prot init error %d\n", __LINE__);
6169	return;
6170	}
6171	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
6172	if (data32 != 0x9abcdef0) {
6173	pr_info("avs2 prot init error %d\n", __LINE__);
6174	return;
6175	}
6176	#endif
6177	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
6178	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000000);
6179	#endif
6180
6181
6182
6183	WRITE_VREG(HEVC_WAIT_FLAG, 1);
6184
6185	/* WRITE_VREG(HEVC_MPSR, 1); */
6186
6187	/* clear mailbox interrupt */
6188	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
6189
6190	/* enable mailbox interrupt */
6191	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
6192
6193	/* disable PSCALE for hardware sharing */
6194	WRITE_VREG(HEVC_PSCALE_CTRL, 0);
6195
6196	WRITE_VREG(DEBUG_REG1, 0x0);
6197	/*check vps/sps/pps/i-slice in ucode*/
6198	WRITE_VREG(NAL_SEARCH_CTL, 0x8);
6199
6200	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
6201
6202	}
6203
6204	#ifdef I_ONLY_SUPPORT
6205	static int vavs2_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6206	{
6207	struct AVS2Decoder_s *dec =
6208	(struct AVS2Decoder_s *)vdec->private;
6209	if (i_only_flag & 0x100)
6210	return 0;
6211	if (trickmode == TRICKMODE_I)
6212	dec->i_only = 0x3;
6213	else if (trickmode == TRICKMODE_NONE)
6214	dec->i_only = 0x0;
6215	return 0;
6216	}
6217	#endif
6218
6219	static int vavs2_local_init(struct AVS2Decoder_s *dec)
6220	{
6221	int i;
6222	int ret;
6223	int width, height;
6224
6225	dec->gvs = vzalloc(sizeof(struct vdec_info));
6226	if (NULL == dec->gvs) {
6227	avs2_print(dec, 0,
6228	"the struct of vdec status malloc failed.\n");
6229	return -1;
6230	}
6231	#ifdef DEBUG_PTS
6232	dec->pts_missed = 0;
6233	dec->pts_hit = 0;
6234	#endif
6235	dec->new_frame_displayed = 0;
6236	dec->last_put_idx = -1;
6237	dec->saved_resolution = 0;
6238	dec->get_frame_dur = false;
6239	on_no_keyframe_skiped = 0;
6240	width = dec->vavs2_amstream_dec_info.width;
6241	height = dec->vavs2_amstream_dec_info.height;
6242	dec->frame_dur =
6243	(dec->vavs2_amstream_dec_info.rate ==
6244	0) ? 3600 : dec->vavs2_amstream_dec_info.rate;
6245	if (width && height)
6246	dec->frame_ar = height * 0x100 / width;
6247	/*
6248	TODO:FOR VERSION
6249	*/
6250	avs2_print(dec, AVS2_DBG_BUFMGR,
6251	"avs2: ver (%d,%d) decinfo: %dx%d rate=%d\n", avs2_version,
6252	0, width, height, dec->frame_dur);
6253
6254	if (dec->frame_dur == 0)
6255	dec->frame_dur = 96000 / 24;
6256	#ifdef I_ONLY_SUPPORT
6257	if (i_only_flag & 0x100)
6258	dec->i_only = i_only_flag & 0xff;
6259	else if ((unsigned long) dec->vavs2_amstream_dec_info.param
6260	& 0x08)
6261	dec->i_only = 0x7;
6262	else
6263	dec->i_only = 0x0;
6264	#endif
6265	INIT_KFIFO(dec->display_q);
6266	INIT_KFIFO(dec->newframe_q);
6267
6268
6269	for (i = 0; i < VF_POOL_SIZE; i++) {
6270	const struct vframe_s *vf = &dec->vfpool[i];
6271	dec->vfpool[i].index = -1;
6272	kfifo_put(&dec->newframe_q, vf);
6273	}
6274
6275
6276	ret = avs2_local_init(dec);
6277
6278	return ret;
6279	}
6280
6281
6282	static s32 vavs2_init(struct vdec_s *vdec)
6283	{
6284	int ret = -1, size = -1;
6285	int fw_size = 0x1000 * 16;
6286	struct firmware_s *fw = NULL;
6287	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)vdec->private;
6288	init_timer(&dec->timer);
6289
6290	dec->stat |= STAT_TIMER_INIT;
6291	if (vavs2_local_init(dec) < 0)
6292	return -EBUSY;
6293
6294	fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6295	if (IS_ERR_OR_NULL(fw))
6296	return -ENOMEM;
6297
6298	size = get_firmware_data(VIDEO_DEC_AVS2_MMU, fw->data);
6299	if (size < 0) {
6300	pr_err("get firmware fail.\n");
6301	vfree(fw);
6302	return -1;
6303	}
6304
6305	fw->len = fw_size;
6306
6307	if (dec->m_ins_flag) {
6308	dec->timer.data = (ulong) dec;
6309	dec->timer.function = vavs2_put_timer_func;
6310	dec->timer.expires = jiffies + PUT_INTERVAL;
6311
6312	/*add_timer(&dec->timer);
6313
6314	dec->stat |= STAT_TIMER_ARM;
6315	dec->stat |= STAT_ISR_REG;*/
6316
6317	INIT_WORK(&dec->work, avs2_work);
6318	dec->fw = fw;
6319
6320	return 0;
6321	}
6322	amhevc_enable();
6323	ret = amhevc_loadmc_ex(VFORMAT_AVS2, NULL, fw->data);
6324	if (ret < 0) {
6325	amhevc_disable();
6326	vfree(fw);
6327	pr_err("AVS2: the %s fw loading failed, err: %x\n",
6328	tee_enabled() ? "TEE" : "local", ret);
6329	return -EBUSY;
6330	}
6331
6332	vfree(fw);
6333
6334	dec->stat |= STAT_MC_LOAD;
6335
6336	/* enable AMRISC side protocol */
6337	vavs2_prot_init(dec);
6338
6339	if (vdec_request_threaded_irq(VDEC_IRQ_0,
6340	vavs2_isr,
6341	vavs2_isr_thread_fn,
6342	IRQF_ONESHOT,/*run thread on this irq disabled*/
6343	"vavs2-irq", (void *)dec)) {
6344	pr_info("vavs2 irq register error.\n");
6345	amhevc_disable();
6346	return -ENOENT;
6347	}
6348
6349	dec->stat |= STAT_ISR_REG;
6350
6351	dec->provider_name = PROVIDER_NAME;
6352	vf_provider_init(&vavs2_vf_prov, PROVIDER_NAME,
6353	&vavs2_vf_provider, dec);
6354	vf_reg_provider(&vavs2_vf_prov);
6355	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
6356	if (dec->frame_dur != 0) {
6357	if (!is_reset)
6358	vf_notify_receiver(dec->provider_name,
6359	VFRAME_EVENT_PROVIDER_FR_HINT,
6360	(void *)
6361	((unsigned long)dec->frame_dur));
6362	}
6363	dec->stat |= STAT_VF_HOOK;
6364
6365	dec->timer.data = (ulong)dec;
6366	dec->timer.function = vavs2_put_timer_func;
6367	dec->timer.expires = jiffies + PUT_INTERVAL;
6368
6369
6370	add_timer(&dec->timer);
6371
6372	dec->stat |= STAT_TIMER_ARM;
6373
6374	/* dec->stat |= STAT_KTHREAD; */
6375	dec->process_busy = 0;
6376	avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
6377	"%d, vavs2_init, RP=0x%x\n",
6378	__LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
6379	return 0;
6380	}
6381
6382	static int vmavs2_stop(struct AVS2Decoder_s *dec)
6383	{
6384	dec->init_flag = 0;
6385	dec->first_sc_checked = 0;
6386	if (dec->stat & STAT_TIMER_ARM) {
6387	del_timer_sync(&dec->timer);
6388	dec->stat &= ~STAT_TIMER_ARM;
6389	}
6390
6391	if (dec->stat & STAT_VF_HOOK) {
6392	if (!is_reset)
6393	vf_notify_receiver(dec->provider_name,
6394	VFRAME_EVENT_PROVIDER_FR_END_HINT,
6395	NULL);
6396
6397	vf_unreg_provider(&vavs2_vf_prov);
6398	dec->stat &= ~STAT_VF_HOOK;
6399	}
6400	avs2_local_uninit(dec);
6401	reset_process_time(dec);
6402	cancel_work_sync(&dec->work);
6403	uninit_mmu_buffers(dec);
6404	if (dec->fw) {
6405	vfree(dec->fw);
6406	dec->fw = NULL;
6407	}
6408
6409	return 0;
6410	}
6411
6412
6413	static int vavs2_stop(struct AVS2Decoder_s *dec)
6414	{
6415
6416	dec->init_flag = 0;
6417	dec->first_sc_checked = 0;
6418	if (dec->stat & STAT_VDEC_RUN) {
6419	amhevc_stop();
6420	dec->stat &= ~STAT_VDEC_RUN;
6421	}
6422
6423	if (dec->stat & STAT_ISR_REG) {
6424	if (!dec->m_ins_flag)
6425	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
6426	vdec_free_irq(VDEC_IRQ_0, (void *)dec);
6427	dec->stat &= ~STAT_ISR_REG;
6428	}
6429
6430	if (dec->stat & STAT_TIMER_ARM) {
6431	del_timer_sync(&dec->timer);
6432	dec->stat &= ~STAT_TIMER_ARM;
6433	}
6434
6435	if (dec->stat & STAT_VF_HOOK) {
6436	if (!is_reset)
6437	vf_notify_receiver(dec->provider_name,
6438	VFRAME_EVENT_PROVIDER_FR_END_HINT,
6439	NULL);
6440
6441	vf_unreg_provider(&vavs2_vf_prov);
6442	dec->stat &= ~STAT_VF_HOOK;
6443	}
6444	avs2_local_uninit(dec);
6445
6446	if (dec->m_ins_flag)
6447	cancel_work_sync(&dec->work);
6448	else
6449	amhevc_disable();
6450	uninit_mmu_buffers(dec);
6451
6452	return 0;
6453	}
6454
6455	static int amvdec_avs2_mmu_init(struct AVS2Decoder_s *dec)
6456	{
6457	int tvp_flag = vdec_secure(hw_to_vdec(dec)) ?
6458	CODEC_MM_FLAGS_TVP : 0;
6459	int buf_size = 48;
6460
6461	#ifdef AVS2_10B_MMU
6462	dec->need_cache_size = buf_size * SZ_1M;
6463	dec->sc_start_time = get_jiffies_64();
6464	dec->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
6465	dec->index, FRAME_BUFFERS,
6466	dec->need_cache_size,
6467	tvp_flag
6468	);
6469	if (!dec->mmu_box) {
6470	pr_err("avs2 alloc mmu box failed!!\n");
6471	return -1;
6472	}
6473	#endif
6474	dec->bmmu_box = decoder_bmmu_box_alloc_box(
6475	DRIVER_NAME,
6476	dec->index,
6477	MAX_BMMU_BUFFER_NUM,
6478	4 + PAGE_SHIFT,
6479	CODEC_MM_FLAGS_CMA_CLEAR |
6480	CODEC_MM_FLAGS_FOR_VDECODER |
6481	tvp_flag);
6482	if (!dec->bmmu_box) {
6483	pr_err("avs2 alloc bmmu box failed!!\n");
6484	return -1;
6485	}
6486	return 0;
6487	}
6488
6489	static int amvdec_avs2_probe(struct platform_device *pdev)
6490	{
6491	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
6492	struct BUF_s BUF[MAX_BUF_NUM];
6493	struct AVS2Decoder_s *dec = &gAVS2Decoder;
6494	int ret;
6495	pr_info("%s\n", __func__);
6496	mutex_lock(&vavs2_mutex);
6497
6498	memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
6499	memset(dec, 0, sizeof(struct AVS2Decoder_s));
6500	memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
6501
6502	dec->init_flag = 0;
6503	dec->first_sc_checked = 0;
6504	dec->eos = 0;
6505	dec->start_process_time = 0;
6506	dec->timeout_num = 0;
6507	dec->fatal_error = 0;
6508	dec->show_frame_num = 0;
6509	if (pdata == NULL) {
6510	avs2_print(dec, 0,
6511	"\namvdec_avs2 memory resource undefined.\n");
6512	mutex_unlock(&vavs2_mutex);
6513	return -EFAULT;
6514	}
6515	dec->m_ins_flag = 0;
6516	dec->platform_dev = pdev;
6517	platform_set_drvdata(pdev, pdata);
6518
6519	if (amvdec_avs2_mmu_init(dec) < 0) {
6520	mutex_unlock(&vavs2_mutex);
6521	pr_err("avs2 alloc bmmu box failed!!\n");
6522	return -1;
6523	}
6524
6525	ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID,
6526	work_buf_size, DRIVER_NAME, &pdata->mem_start);
6527	if (ret < 0) {
6528	uninit_mmu_buffers(dec);
6529	mutex_unlock(&vavs2_mutex);
6530	return ret;
6531	}
6532	dec->buf_size = work_buf_size;
6533
6534	dec->buf_start = pdata->mem_start;
6535
6536
6537	if (debug) {
6538	avs2_print(dec, 0,
6539	"===AVS2 decoder mem resource 0x%lx size 0x%x\n",
6540	pdata->mem_start, dec->buf_size);
6541	}
6542
6543	if (pdata->sys_info) {
6544	dec->vavs2_amstream_dec_info = *pdata->sys_info;
6545	dec->frame_width = dec->vavs2_amstream_dec_info.width;
6546	dec->frame_height = dec->vavs2_amstream_dec_info.height;
6547	} else {
6548	dec->vavs2_amstream_dec_info.width = 0;
6549	dec->vavs2_amstream_dec_info.height = 0;
6550	dec->vavs2_amstream_dec_info.rate = 30;
6551	}
6552	dec->cma_dev = pdata->cma_dev;
6553
6554	pdata->private = dec;
6555	pdata->dec_status = vavs2_dec_status;
6556	/*pdata->set_isreset = vavs2_set_isreset;*/
6557	is_reset = 0;
6558	if (vavs2_init(pdata) < 0) {
6559	pr_info("\namvdec_avs2 init failed.\n");
6560	avs2_local_uninit(dec);
6561	uninit_mmu_buffers(dec);
6562	pdata->dec_status = NULL;
6563	mutex_unlock(&vavs2_mutex);
6564	return -ENODEV;
6565	}
6566	/*set the max clk for smooth playing...*/
6567	hevc_source_changed(VFORMAT_AVS2,
6568	4096, 2048, 60);
6569	mutex_unlock(&vavs2_mutex);
6570
6571	return 0;
6572	}
6573
6574	static int amvdec_avs2_remove(struct platform_device *pdev)
6575	{
6576	struct AVS2Decoder_s *dec = &gAVS2Decoder;
6577	if (debug)
6578	pr_info("amvdec_avs2_remove\n");
6579
6580	mutex_lock(&vavs2_mutex);
6581
6582	vavs2_stop(dec);
6583
6584
6585	hevc_source_changed(VFORMAT_AVS2, 0, 0, 0);
6586
6587
6588	#ifdef DEBUG_PTS
6589	pr_info("pts missed %ld, pts hit %ld, duration %d\n",
6590	dec->pts_missed, dec->pts_hit, dec->frame_dur);
6591	#endif
6592
6593	mutex_unlock(&vavs2_mutex);
6594
6595	return 0;
6596	}
6597
6598	/****************************************/
6599	#ifdef CONFIG_PM
6600	static int avs2_suspend(struct device *dev)
6601	{
6602	amhevc_suspend(to_platform_device(dev), dev->power.power_state);
6603	return 0;
6604	}
6605
6606	static int avs2_resume(struct device *dev)
6607	{
6608	amhevc_resume(to_platform_device(dev));
6609	return 0;
6610	}
6611
6612	static const struct dev_pm_ops avs2_pm_ops = {
6613	SET_SYSTEM_SLEEP_PM_OPS(avs2_suspend, avs2_resume)
6614	};
6615	#endif
6616
6617	static struct platform_driver amvdec_avs2_driver = {
6618	.probe = amvdec_avs2_probe,
6619	.remove = amvdec_avs2_remove,
6620	.driver = {
6621	.name = DRIVER_NAME,
6622	#ifdef CONFIG_PM
6623	.pm = &avs2_pm_ops,
6624	#endif
6625	}
6626	};
6627
6628	static struct codec_profile_t amvdec_avs2_profile = {
6629	.name = "avs2",
6630	.profile = ""
6631	};
6632
6633	static struct codec_profile_t amvdec_avs2_profile_mult;
6634
6635	static unsigned char get_data_check_sum
6636	(struct AVS2Decoder_s *dec, int size)
6637	{
6638	int jj;
6639	int sum = 0;
6640	u8 *data = NULL;
6641
6642	if (!dec->chunk->block->is_mapped)
6643	data = codec_mm_vmap(dec->chunk->block->start +
6644	dec->chunk->offset, size);
6645	else
6646	data = ((u8 *)dec->chunk->block->start_virt) +
6647	dec->chunk->offset;
6648
6649	for (jj = 0; jj < size; jj++)
6650	sum += data[jj];
6651
6652	if (!dec->chunk->block->is_mapped)
6653	codec_mm_unmap_phyaddr(data);
6654	return sum;
6655	}
6656
6657	static void dump_data(struct AVS2Decoder_s *dec, int size)
6658	{
6659	int jj;
6660	u8 *data = NULL;
6661	int padding_size = dec->chunk->offset &
6662	(VDEC_FIFO_ALIGN - 1);
6663
6664	if (!dec->chunk->block->is_mapped)
6665	data = codec_mm_vmap(dec->chunk->block->start +
6666	dec->chunk->offset, size);
6667	else
6668	data = ((u8 *)dec->chunk->block->start_virt) +
6669	dec->chunk->offset;
6670
6671	avs2_print(dec, 0, "padding: ");
6672	for (jj = padding_size; jj > 0; jj--)
6673	avs2_print_cont(dec,
6674	0,
6675	"%02x ", *(data - jj));
6676	avs2_print_cont(dec, 0, "data adr %p\n",
6677	data);
6678
6679	for (jj = 0; jj < size; jj++) {
6680	if ((jj & 0xf) == 0)
6681	avs2_print(dec,
6682	0,
6683	"%06x:", jj);
6684	avs2_print_cont(dec,
6685	0,
6686	"%02x ", data[jj]);
6687	if (((jj + 1) & 0xf) == 0)
6688	avs2_print(dec,
6689	0,
6690	"\n");
6691	}
6692	avs2_print(dec,
6693	0,
6694	"\n");
6695
6696	if (!dec->chunk->block->is_mapped)
6697	codec_mm_unmap_phyaddr(data);
6698	}
6699
6700	static void avs2_work(struct work_struct *work)
6701	{
6702	struct AVS2Decoder_s *dec = container_of(work,
6703	struct AVS2Decoder_s, work);
6704	struct vdec_s *vdec = hw_to_vdec(dec);
6705	/* finished decoding one frame or error,
6706	* notify vdec core to switch context
6707	*/
6708	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6709	"%s dec_result %d %x %x %x\n",
6710	__func__,
6711	dec->dec_result,
6712	READ_VREG(HEVC_STREAM_LEVEL),
6713	READ_VREG(HEVC_STREAM_WR_PTR),
6714	READ_VREG(HEVC_STREAM_RD_PTR));
6715
6716	if (((dec->dec_result == DEC_RESULT_GET_DATA) ||
6717	(dec->dec_result == DEC_RESULT_GET_DATA_RETRY))
6718	&& (hw_to_vdec(dec)->next_status !=
6719	VDEC_STATUS_DISCONNECTED)) {
6720	if (!vdec_has_more_input(vdec)) {
6721	dec->dec_result = DEC_RESULT_EOS;
6722	vdec_schedule_work(&dec->work);
6723	return;
6724	}
6725
6726	if (dec->dec_result == DEC_RESULT_GET_DATA) {
6727	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6728	"%s DEC_RESULT_GET_DATA %x %x %x\n",
6729	__func__,
6730	READ_VREG(HEVC_STREAM_LEVEL),
6731	READ_VREG(HEVC_STREAM_WR_PTR),
6732	READ_VREG(HEVC_STREAM_RD_PTR));
6733	vdec_vframe_dirty(vdec, dec->chunk);
6734	vdec_clean_input(vdec);
6735	}
6736
6737	if (get_free_buf_count(dec) >=
6738	run_ready_min_buf_num) {
6739	int r;
6740	int decode_size;
6741	r = vdec_prepare_input(vdec, &dec->chunk);
6742	if (r < 0) {
6743	dec->dec_result = DEC_RESULT_GET_DATA_RETRY;
6744
6745	avs2_print(dec,
6746	PRINT_FLAG_VDEC_DETAIL,
6747	"amvdec_vh265: Insufficient data\n");
6748
6749	vdec_schedule_work(&dec->work);
6750	return;
6751	}
6752	dec->dec_result = DEC_RESULT_NONE;
6753	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6754	"%s: chunk size 0x%x sum 0x%x\n",
6755	__func__, r,
6756	(debug & PRINT_FLAG_VDEC_STATUS) ?
6757	get_data_check_sum(dec, r) : 0
6758	);
6759	if (debug & PRINT_FLAG_VDEC_DATA)
6760	dump_data(dec, dec->chunk->size);
6761
6762	decode_size = dec->chunk->size +
6763	(dec->chunk->offset & (VDEC_FIFO_ALIGN - 1));
6764
6765	WRITE_VREG(HEVC_DECODE_SIZE,
6766	READ_VREG(HEVC_DECODE_SIZE) + decode_size);
6767
6768	vdec_enable_input(vdec);
6769
6770	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE);
6771
6772	start_process_time(dec);
6773
6774	} else{
6775	dec->dec_result = DEC_RESULT_GET_DATA_RETRY;
6776
6777	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6778	"amvdec_vh265: Insufficient data\n");
6779
6780	vdec_schedule_work(&dec->work);
6781	}
6782	return;
6783	} else if (dec->dec_result == DEC_RESULT_DONE) {
6784	/* if (!dec->ctx_valid)
6785	dec->ctx_valid = 1; */
6786	dec->slice_idx++;
6787	dec->frame_count++;
6788	dec->process_state = PROC_STATE_INIT;
6789	decode_frame_count[dec->index] = dec->frame_count;
6790
6791	#ifdef AVS2_10B_MMU
6792	dec->used_4k_num =
6793	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
6794	#endif
6795	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6796	"%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
6797	__func__,
6798	dec->frame_count,
6799	dec->dec_result,
6800	READ_VREG(HEVC_STREAM_LEVEL),
6801	READ_VREG(HEVC_STREAM_WR_PTR),
6802	READ_VREG(HEVC_STREAM_RD_PTR),
6803	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
6804	READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
6805	dec->start_shift_bytes
6806	);
6807	vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk);
6808	} else if (dec->dec_result == DEC_RESULT_AGAIN) {
6809	/*
6810	stream base: stream buf empty or timeout
6811	frame base: vdec_prepare_input fail
6812	*/
6813	if (!vdec_has_more_input(vdec)) {
6814	dec->dec_result = DEC_RESULT_EOS;
6815	vdec_schedule_work(&dec->work);
6816	return;
6817	}
6818	} else if (dec->dec_result == DEC_RESULT_EOS) {
6819	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6820	"%s: end of stream\n",
6821	__func__);
6822	dec->eos = 1;
6823	check_pic_error(dec, dec->avs2_dec.hc.cur_pic);
6824	avs2_post_process(&dec->avs2_dec);
6825	avs2_prepare_display_buf(dec);
6826	vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk);
6827	} else if (dec->dec_result == DEC_RESULT_FORCE_EXIT) {
6828	avs2_print(dec, PRINT_FLAG_VDEC_STATUS,
6829	"%s: force exit\n",
6830	__func__);
6831	if (dec->stat & STAT_VDEC_RUN) {
6832	amhevc_stop();
6833	dec->stat &= ~STAT_VDEC_RUN;
6834	}
6835
6836	if (dec->stat & STAT_ISR_REG) {
6837	if (!dec->m_ins_flag)
6838	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
6839	vdec_free_irq(VDEC_IRQ_0, (void *)dec);
6840	dec->stat &= ~STAT_ISR_REG;
6841	}
6842	}
6843
6844	if (dec->stat & STAT_TIMER_ARM) {
6845	del_timer_sync(&dec->timer);
6846	dec->stat &= ~STAT_TIMER_ARM;
6847	}
6848	/* mark itself has all HW resource released and input released */
6849	if (vdec->parallel_dec ==1)
6850	vdec_core_finish_run(vdec, CORE_MASK_HEVC);
6851	else
6852	vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
6853
6854	if (dec->vdec_cb)
6855	dec->vdec_cb(hw_to_vdec(dec), dec->vdec_cb_arg);
6856	}
6857
6858	static int avs2_hw_ctx_restore(struct AVS2Decoder_s *dec)
6859	{
6860	/* new to do ... */
6861	vavs2_prot_init(dec);
6862	return 0;
6863	}
6864
6865	static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
6866	{
6867	struct AVS2Decoder_s *dec =
6868	(struct AVS2Decoder_s *)vdec->private;
6869	int tvp = vdec_secure(hw_to_vdec(dec)) ?
6870	CODEC_MM_FLAGS_TVP : 0;
6871	unsigned long ret = 0;
6872	avs2_print(dec,
6873	PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
6874	if (debug & AVS2_DBG_PIC_LEAK_WAIT)
6875	return ret;
6876
6877	if (dec->eos)
6878	return ret;
6879	if (!dec->first_sc_checked) {
6880	int size = decoder_mmu_box_sc_check(dec->mmu_box, tvp);
6881	dec->first_sc_checked = 1;
6882	avs2_print(dec, 0, "vavs2 cached=%d need_size=%d speed= %d ms\n",
6883	size, (dec->need_cache_size >> PAGE_SHIFT),
6884	(int)(get_jiffies_64() - dec->sc_start_time) * 1000/HZ);
6885	}
6886
6887	if (dec->next_again_flag &&
6888	(!vdec_frame_based(vdec))) {
6889	u32 parser_wr_ptr =
6890	READ_PARSER_REG(PARSER_VIDEO_WP);
6891	if (parser_wr_ptr >= dec->pre_parser_wr_ptr &&
6892	(parser_wr_ptr - dec->pre_parser_wr_ptr) <
6893	again_threshold) {
6894	int r = vdec_sync_input(vdec);
6895	avs2_print(dec,
6896	PRINT_FLAG_VDEC_DETAIL, "%s buf lelvel:%x\n", __func__, r);
6897	return 0;
6898	}
6899	}
6900	/*
6901	if (vdec_stream_based(vdec) && (dec->pic_list_init_flag == 0)
6902	&& pre_decode_buf_level != 0) {
6903	u32 rp, wp, level;
6904
6905	rp = READ_PARSER_REG(PARSER_VIDEO_RP);
6906	wp = READ_PARSER_REG(PARSER_VIDEO_WP);
6907	if (wp < rp)
6908	level = vdec->input.size + wp - rp;
6909	else
6910	level = wp - rp;
6911
6912	if (level < pre_decode_buf_level)
6913	return 0;
6914	}
6915	*/
6916
6917	if ((dec->pic_list_init_flag == 0) ||
6918	get_free_buf_count(dec) >=
6919	run_ready_min_buf_num)
6920	ret = 1;
6921	#ifdef CONSTRAIN_MAX_BUF_NUM
6922	if (dec->pic_list_init_flag) {
6923	if (run_ready_max_vf_only_num > 0 &&
6924	get_vf_ref_only_buf_count(dec) >=
6925	run_ready_max_vf_only_num
6926	)
6927	ret = 0;
6928	if (run_ready_display_q_num > 0 &&
6929	kfifo_len(&dec->display_q) >=
6930	run_ready_display_q_num)
6931	ret = 0;
6932
6933	if (run_ready_max_buf_num == 0xff &&
6934	get_used_buf_count(dec) >=
6935	dec->avs2_dec.ref_maxbuffer)
6936	ret = 0;
6937	else if (run_ready_max_buf_num &&
6938	get_used_buf_count(dec) >=
6939	run_ready_max_buf_num)
6940	ret = 0;
6941	}
6942	#endif
6943	if (ret)
6944	not_run_ready[dec->index] = 0;
6945	else
6946	not_run_ready[dec->index]++;
6947
6948	if (vdec->parallel_dec == 1)
6949	return ret ? CORE_MASK_HEVC : 0;
6950	else
6951	return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
6952	}
6953
6954	static void run(struct vdec_s *vdec, unsigned long mask,
6955	void (*callback)(struct vdec_s *, void *), void *arg)
6956	{
6957	struct AVS2Decoder_s *dec =
6958	(struct AVS2Decoder_s *)vdec->private;
6959	int r;
6960
6961	run_count[dec->index]++;
6962	dec->vdec_cb_arg = arg;
6963	dec->vdec_cb = callback;
6964	/* dec->chunk = vdec_prepare_input(vdec); */
6965	hevc_reset_core(vdec);
6966	dec->pre_parser_wr_ptr =
6967	READ_PARSER_REG(PARSER_VIDEO_WP);
6968	dec->next_again_flag = 0;
6969
6970	r = vdec_prepare_input(vdec, &dec->chunk);
6971	if (r < 0) {
6972	input_empty[dec->index]++;
6973
6974	dec->dec_result = DEC_RESULT_AGAIN;
6975
6976	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
6977	"ammvdec_vh265: Insufficient data\n");
6978
6979	vdec_schedule_work(&dec->work);
6980	return;
6981	}
6982	input_empty[dec->index] = 0;
6983	dec->dec_result = DEC_RESULT_NONE;
6984	dec->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
6985
6986	if (debug & PRINT_FLAG_VDEC_STATUS) {
6987	int ii;
6988	avs2_print(dec, 0,
6989	"%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
6990	__func__,
6991	dec->frame_count, r,
6992	dec->chunk ? dec->chunk->size : 0,
6993	dec->chunk ? dec->chunk->offset : 0,
6994	dec->chunk ? ((vdec_frame_based(vdec) &&
6995	(debug & PRINT_FLAG_VDEC_STATUS)) ?
6996	get_data_check_sum(dec, r) : 0) : 0,
6997	READ_VREG(HEVC_STREAM_START_ADDR),
6998	READ_VREG(HEVC_STREAM_END_ADDR),
6999	READ_VREG(HEVC_STREAM_LEVEL),
7000	READ_VREG(HEVC_STREAM_WR_PTR),
7001	READ_VREG(HEVC_STREAM_RD_PTR),
7002	dec->start_shift_bytes);
7003	if (vdec_frame_based(vdec) && dec->chunk) {
7004	u8 *data = NULL;
7005	if (!dec->chunk->block->is_mapped)
7006	data = codec_mm_vmap(dec->chunk->block->start +
7007	dec->chunk->offset, 8);
7008	else
7009	data = ((u8 *)dec->chunk->block->start_virt) +
7010	dec->chunk->offset;
7011
7012	avs2_print_cont(dec, 0, "data adr %p:",
7013	data);
7014	for (ii = 0; ii < 8; ii++)
7015	avs2_print_cont(dec, 0, "%02x ",
7016	data[ii]);
7017	if (!dec->chunk->block->is_mapped)
7018	codec_mm_unmap_phyaddr(data);
7019	}
7020	avs2_print_cont(dec, 0, "\r\n");
7021	}
7022	if (vdec->mc_loaded) {
7023	/*firmware have load before,
7024	and not changes to another.
7025	ignore reload.
7026	*/
7027	} else if (amhevc_loadmc_ex(VFORMAT_AVS2, NULL, dec->fw->data) < 0) {
7028	vdec->mc_loaded = 0;
7029	amhevc_disable();
7030	avs2_print(dec, 0,
7031	"%s: Error amvdec_loadmc fail\n", __func__);
7032	dec->dec_result = DEC_RESULT_FORCE_EXIT;
7033	vdec_schedule_work(&dec->work);
7034	return;
7035	} else {
7036	vdec->mc_loaded = 1;
7037	vdec->mc_type = VFORMAT_AVS2;
7038	}
7039
7040
7041	if (avs2_hw_ctx_restore(dec) < 0) {
7042	vdec_schedule_work(&dec->work);
7043	return;
7044	}
7045
7046	vdec_enable_input(vdec);
7047
7048	WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_SEARCH_NEW_PIC);
7049
7050	if (vdec_frame_based(vdec) && dec->chunk) {
7051	if (debug & PRINT_FLAG_VDEC_DATA)
7052	dump_data(dec, dec->chunk->size);
7053
7054	WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
7055	r = dec->chunk->size +
7056	(dec->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7057	}
7058
7059	WRITE_VREG(HEVC_DECODE_SIZE, r);
7060	WRITE_VREG(HEVC_DECODE_COUNT, dec->slice_idx);
7061	dec->init_flag = 1;
7062
7063	avs2_print(dec, PRINT_FLAG_VDEC_DETAIL,
7064	"%s: start hevc (%x %x %x)\n",
7065	__func__,
7066	READ_VREG(HEVC_DEC_STATUS_REG),
7067	READ_VREG(HEVC_MPC_E),
7068	READ_VREG(HEVC_MPSR));
7069
7070	start_process_time(dec);
7071	mod_timer(&dec->timer, jiffies);
7072	dec->stat |= STAT_TIMER_ARM;
7073	dec->stat |= STAT_ISR_REG;
7074	amhevc_start();
7075	dec->stat |= STAT_VDEC_RUN;
7076	}
7077
7078	static void reset(struct vdec_s *vdec)
7079	{
7080
7081	struct AVS2Decoder_s *dec =
7082	(struct AVS2Decoder_s *)vdec->private;
7083
7084	avs2_print(dec,
7085	PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
7086
7087	}
7088
7089	static irqreturn_t avs2_irq_cb(struct vdec_s *vdec, int irq)
7090	{
7091	struct AVS2Decoder_s *dec =
7092	(struct AVS2Decoder_s *)vdec->private;
7093	return vavs2_isr(0, dec);
7094	}
7095
7096	static irqreturn_t avs2_threaded_irq_cb(struct vdec_s *vdec, int irq)
7097	{
7098	struct AVS2Decoder_s *dec =
7099	(struct AVS2Decoder_s *)vdec->private;
7100	return vavs2_isr_thread_fn(0, dec);
7101	}
7102
7103	static void avs2_dump_state(struct vdec_s *vdec)
7104	{
7105	struct AVS2Decoder_s *dec =
7106	(struct AVS2Decoder_s *)vdec->private;
7107	int i;
7108	avs2_print(dec, 0, "====== %s\n", __func__);
7109
7110	avs2_print(dec, 0,
7111	"width/height (%d/%d), used_buf_num %d\n",
7112	dec->avs2_dec.img.width,
7113	dec->avs2_dec.img.height,
7114	dec->used_buf_num
7115	);
7116
7117	avs2_print(dec, 0,
7118	"is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
7119	input_frame_based(vdec),
7120	dec->eos,
7121	dec->dec_result,
7122	decode_frame_count[dec->index],
7123	display_frame_count[dec->index],
7124	run_count[dec->index],
7125	not_run_ready[dec->index],
7126	input_empty[dec->index]
7127	);
7128
7129	if (vf_get_receiver(vdec->vf_provider_name)) {
7130	enum receviver_start_e state =
7131	vf_notify_receiver(vdec->vf_provider_name,
7132	VFRAME_EVENT_PROVIDER_QUREY_STATE,
7133	NULL);
7134	avs2_print(dec, 0,
7135	"\nreceiver(%s) state %d\n",
7136	vdec->vf_provider_name,
7137	state);
7138	}
7139
7140	avs2_print(dec, 0,
7141	"%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
7142	__func__,
7143	kfifo_len(&dec->newframe_q),
7144	VF_POOL_SIZE,
7145	kfifo_len(&dec->display_q),
7146	VF_POOL_SIZE,
7147	dec->vf_pre_count,
7148	dec->vf_get_count,
7149	dec->vf_put_count,
7150	get_free_buf_count(dec),
7151	run_ready_min_buf_num
7152	);
7153
7154	dump_pic_list(dec);
7155
7156	for (i = 0; i < MAX_BUF_NUM; i++) {
7157	avs2_print(dec, 0,
7158	"mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
7159	i,
7160	dec->m_mv_BUF[i].start_adr,
7161	dec->m_mv_BUF[i].size,
7162	dec->m_mv_BUF[i].used_flag);
7163	}
7164
7165	avs2_print(dec, 0,
7166	"HEVC_DEC_STATUS_REG=0x%x\n",
7167	READ_VREG(HEVC_DEC_STATUS_REG));
7168	avs2_print(dec, 0,
7169	"HEVC_MPC_E=0x%x\n",
7170	READ_VREG(HEVC_MPC_E));
7171	avs2_print(dec, 0,
7172	"DECODE_MODE=0x%x\n",
7173	READ_VREG(DECODE_MODE));
7174	avs2_print(dec, 0,
7175	"NAL_SEARCH_CTL=0x%x\n",
7176	READ_VREG(NAL_SEARCH_CTL));
7177	avs2_print(dec, 0,
7178	"HEVC_PARSER_LCU_START=0x%x\n",
7179	READ_VREG(HEVC_PARSER_LCU_START));
7180	avs2_print(dec, 0,
7181	"HEVC_DECODE_SIZE=0x%x\n",
7182	READ_VREG(HEVC_DECODE_SIZE));
7183	avs2_print(dec, 0,
7184	"HEVC_SHIFT_BYTE_COUNT=0x%x\n",
7185	READ_VREG(HEVC_SHIFT_BYTE_COUNT));
7186	avs2_print(dec, 0,
7187	"HEVC_STREAM_START_ADDR=0x%x\n",
7188	READ_VREG(HEVC_STREAM_START_ADDR));
7189	avs2_print(dec, 0,
7190	"HEVC_STREAM_END_ADDR=0x%x\n",
7191	READ_VREG(HEVC_STREAM_END_ADDR));
7192	avs2_print(dec, 0,
7193	"HEVC_STREAM_LEVEL=0x%x\n",
7194	READ_VREG(HEVC_STREAM_LEVEL));
7195	avs2_print(dec, 0,
7196	"HEVC_STREAM_WR_PTR=0x%x\n",
7197	READ_VREG(HEVC_STREAM_WR_PTR));
7198	avs2_print(dec, 0,
7199	"HEVC_STREAM_RD_PTR=0x%x\n",
7200	READ_VREG(HEVC_STREAM_RD_PTR));
7201	avs2_print(dec, 0,
7202	"PARSER_VIDEO_RP=0x%x\n",
7203	READ_PARSER_REG(PARSER_VIDEO_RP));
7204	avs2_print(dec, 0,
7205	"PARSER_VIDEO_WP=0x%x\n",
7206	READ_PARSER_REG(PARSER_VIDEO_WP));
7207
7208	if (input_frame_based(vdec) &&
7209	(debug & PRINT_FLAG_VDEC_DATA)
7210	) {
7211	int jj;
7212	if (dec->chunk && dec->chunk->block &&
7213	dec->chunk->size > 0) {
7214	u8 *data = NULL;
7215	if (!dec->chunk->block->is_mapped)
7216	data = codec_mm_vmap(dec->chunk->block->start +
7217	dec->chunk->offset, dec->chunk->size);
7218	else
7219	data = ((u8 *)dec->chunk->block->start_virt) +
7220	dec->chunk->offset;
7221	avs2_print(dec, 0,
7222	"frame data size 0x%x\n",
7223	dec->chunk->size);
7224	for (jj = 0; jj < dec->chunk->size; jj++) {
7225	if ((jj & 0xf) == 0)
7226	avs2_print(dec, 0,
7227	"%06x:", jj);
7228	avs2_print_cont(dec, 0,
7229	"%02x ", data[jj]);
7230	if (((jj + 1) & 0xf) == 0)
7231	avs2_print_cont(dec, 0,
7232	"\n");
7233	}
7234
7235	if (!dec->chunk->block->is_mapped)
7236	codec_mm_unmap_phyaddr(data);
7237	}
7238	}
7239
7240	}
7241
7242	static int ammvdec_avs2_probe(struct platform_device *pdev)
7243	{
7244	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
7245	int ret;
7246	int config_val;
7247	struct vframe_content_light_level_s content_light_level;
7248	struct vframe_master_display_colour_s vf_dp;
7249
7250	struct BUF_s BUF[MAX_BUF_NUM];
7251	struct AVS2Decoder_s *dec = NULL;
7252	pr_info("%s\n", __func__);
7253	if (pdata == NULL) {
7254	pr_info("\nammvdec_avs2 memory resource undefined.\n");
7255	return -EFAULT;
7256	}
7257	/*dec = (struct AVS2Decoder_s *)devm_kzalloc(&pdev->dev,
7258	sizeof(struct AVS2Decoder_s), GFP_KERNEL);*/
7259	memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
7260	dec = vmalloc(sizeof(struct AVS2Decoder_s));
7261	memset(dec, 0, sizeof(struct AVS2Decoder_s));
7262	if (dec == NULL) {
7263	pr_info("\nammvdec_avs2 device data allocation failed\n");
7264	return -ENOMEM;
7265	}
7266	if (pdata->parallel_dec == 1) {
7267	int i;
7268	for (i = 0; i < AVS2_MAX_BUFFER_NUM; i++) {
7269	dec->avs2_dec.frm_pool[i].y_canvas_index = -1;
7270	dec->avs2_dec.frm_pool[i].uv_canvas_index = -1;
7271	}
7272	}
7273	pdata->private = dec;
7274	pdata->dec_status = vavs2_dec_status;
7275	#ifdef I_ONLY_SUPPORT
7276	pdata->set_trickmode = vavs2_set_trickmode;
7277	#endif
7278	pdata->run_ready = run_ready;
7279	pdata->run = run;
7280	pdata->reset = reset;
7281	pdata->irq_handler = avs2_irq_cb;
7282	pdata->threaded_irq_handler = avs2_threaded_irq_cb;
7283	pdata->dump_state = avs2_dump_state;
7284
7285	memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
7286	memset(dec, 0, sizeof(struct AVS2Decoder_s));
7287	memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
7288
7289	dec->index = pdev->id;
7290	dec->m_ins_flag = 1;
7291
7292	if (pdata->use_vfm_path) {
7293	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
7294	VFM_DEC_PROVIDER_NAME);
7295	dec->frameinfo_enable = 1;
7296	} else
7297	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
7298	MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
7299
7300	vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
7301	&vavs2_vf_provider, dec);
7302
7303	dec->provider_name = pdata->vf_provider_name;
7304	platform_set_drvdata(pdev, pdata);
7305
7306	dec->platform_dev = pdev;
7307	dec->video_signal_type = 0;
7308	dec->video_ori_signal_type = 0;
7309	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
7310	dec->stat |= VP9_TRIGGER_FRAME_ENABLE;
7311	#if 1
7312	if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
7313	pdata->config && pdata->config_len) {
7314	/*use ptr config for doubel_write_mode, etc*/
7315	avs2_print(dec, 0, "pdata->config=%s\n", pdata->config);
7316	if (get_config_int(pdata->config, "avs2_double_write_mode",
7317	&config_val) == 0)
7318	dec->double_write_mode = config_val;
7319	else
7320	dec->double_write_mode = double_write_mode;
7321	if (get_config_int(pdata->config, "HDRStaticInfo",
7322	&vf_dp.present_flag) == 0
7323	&& vf_dp.present_flag == 1) {
7324	get_config_int(pdata->config, "mG.x",
7325	&vf_dp.primaries[0][0]);
7326	get_config_int(pdata->config, "mG.y",
7327	&vf_dp.primaries[0][1]);
7328	get_config_int(pdata->config, "mB.x",
7329	&vf_dp.primaries[1][0]);
7330	get_config_int(pdata->config, "mB.y",
7331	&vf_dp.primaries[1][1]);
7332	get_config_int(pdata->config, "mR.x",
7333	&vf_dp.primaries[2][0]);
7334	get_config_int(pdata->config, "mR.y",
7335	&vf_dp.primaries[2][1]);
7336	get_config_int(pdata->config, "mW.x",
7337	&vf_dp.white_point[0]);
7338	get_config_int(pdata->config, "mW.y",
7339	&vf_dp.white_point[1]);
7340	get_config_int(pdata->config, "mMaxDL",
7341	&vf_dp.luminance[0]);
7342	get_config_int(pdata->config, "mMinDL",
7343	&vf_dp.luminance[1]);
7344	vf_dp.content_light_level.present_flag = 1;
7345	get_config_int(pdata->config, "mMaxCLL",
7346	&content_light_level.max_content);
7347	get_config_int(pdata->config, "mMaxFALL",
7348	&content_light_level.max_pic_average);
7349	vf_dp.content_light_level = content_light_level;
7350	dec->video_signal_type = (1 << 29)
7351	| (5 << 26) /* unspecified */
7352	| (0 << 25) /* limit */
7353	| (1 << 24) /* color available */
7354	| (9 << 16) /* 2020 */
7355	| (16 << 8) /* 2084 */
7356	| (9 << 0); /* 2020 */
7357	}
7358	dec->vf_dp = vf_dp;
7359	} else
7360	#endif
7361	{
7362	/*dec->vavs2_amstream_dec_info.width = 0;
7363	dec->vavs2_amstream_dec_info.height = 0;
7364	dec->vavs2_amstream_dec_info.rate = 30;*/
7365	dec->double_write_mode = double_write_mode;
7366	}
7367	video_signal_type = dec->video_signal_type;
7368
7369	#if 0
7370	dec->buf_start = pdata->mem_start;
7371	dec->buf_size = pdata->mem_end - pdata->mem_start + 1;
7372	#else
7373	if (amvdec_avs2_mmu_init(dec) < 0) {
7374	pr_err("avs2 alloc bmmu box failed!!\n");
7375	/* devm_kfree(&pdev->dev, (void *)dec); */
7376	vfree((void *)dec);
7377	return -1;
7378	}
7379	dec->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
7380	ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID,
7381	dec->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
7382	&dec->cma_alloc_addr);
7383	if (ret < 0) {
7384	uninit_mmu_buffers(dec);
7385	/* devm_kfree(&pdev->dev, (void *)dec); */
7386	vfree((void *)dec);
7387	return ret;
7388	}
7389	dec->buf_start = dec->cma_alloc_addr;
7390	dec->buf_size = work_buf_size;
7391	#endif
7392	dec->init_flag = 0;
7393	dec->first_sc_checked = 0;
7394	dec->fatal_error = 0;
7395	dec->show_frame_num = 0;
7396	if (pdata == NULL) {
7397	pr_info("\namvdec_avs2 memory resource undefined.\n");
7398	uninit_mmu_buffers(dec);
7399	/* devm_kfree(&pdev->dev, (void *)dec); */
7400	vfree((void *)dec);
7401	return -EFAULT;
7402	}
7403
7404	if (debug) {
7405	pr_info("===AVS2 decoder mem resource 0x%lx size 0x%x\n",
7406	dec->buf_start,
7407	dec->buf_size);
7408	}
7409
7410	if (pdata->sys_info) {
7411	dec->vavs2_amstream_dec_info = *pdata->sys_info;
7412	dec->frame_width = dec->vavs2_amstream_dec_info.width;
7413	dec->frame_height = dec->vavs2_amstream_dec_info.height;
7414	} else {
7415	dec->vavs2_amstream_dec_info.width = 0;
7416	dec->vavs2_amstream_dec_info.height = 0;
7417	dec->vavs2_amstream_dec_info.rate = 30;
7418	}
7419
7420	dec->cma_dev = pdata->cma_dev;
7421	if (vavs2_init(pdata) < 0) {
7422	pr_info("\namvdec_avs2 init failed.\n");
7423	avs2_local_uninit(dec);
7424	uninit_mmu_buffers(dec);
7425	/* devm_kfree(&pdev->dev, (void *)dec); */
7426	vfree((void *)dec);
7427	pdata->dec_status = NULL;
7428	return -ENODEV;
7429	}
7430	vdec_set_prepare_level(pdata, start_decode_buf_level);
7431	hevc_source_changed(VFORMAT_AVS2,
7432	4096, 2048, 60);
7433	if (pdata->parallel_dec == 1)
7434	vdec_core_request(pdata, CORE_MASK_HEVC);
7435	else {
7436	vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
7437	| CORE_MASK_COMBINE);
7438	}
7439
7440	return 0;
7441	}
7442
7443	static int ammvdec_avs2_remove(struct platform_device *pdev)
7444	{
7445	struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)
7446	(((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
7447	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
7448	int i;
7449
7450	if (debug)
7451	pr_info("amvdec_avs2_remove\n");
7452
7453	vmavs2_stop(dec);
7454
7455	if (pdata->parallel_dec == 1)
7456	vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC);
7457	else
7458	vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC);
7459
7460	vdec_set_status(hw_to_vdec(dec), VDEC_STATUS_DISCONNECTED);
7461	if (pdata->parallel_dec == 1) {
7462	for (i = 0; i < AVS2_MAX_BUFFER_NUM; i++) {
7463	pdata->free_canvas_ex(dec->avs2_dec.frm_pool[i].y_canvas_index, pdata->id);
7464	pdata->free_canvas_ex(dec->avs2_dec.frm_pool[i].uv_canvas_index, pdata->id);
7465	}
7466	}
7467
7468
7469	#ifdef DEBUG_PTS
7470	pr_info("pts missed %ld, pts hit %ld, duration %d\n",
7471	dec->pts_missed, dec->pts_hit, dec->frame_dur);
7472	#endif
7473	/* devm_kfree(&pdev->dev, (void *)dec); */
7474	vfree((void *)dec);
7475	return 0;
7476	}
7477
7478	static struct platform_driver ammvdec_avs2_driver = {
7479	.probe = ammvdec_avs2_probe,
7480	.remove = ammvdec_avs2_remove,
7481	.driver = {
7482	.name = MULTI_DRIVER_NAME,
7483	#ifdef CONFIG_PM
7484	.pm = &avs2_pm_ops,
7485	#endif
7486	}
7487	};
7488	#endif
7489	static struct mconfig avs2_configs[] = {
7490	MC_PU32("bit_depth_luma", &bit_depth_luma),
7491	MC_PU32("bit_depth_chroma", &bit_depth_chroma),
7492	MC_PU32("frame_width", &frame_width),
7493	MC_PU32("frame_height", &frame_height),
7494	MC_PU32("debug", &debug),
7495	MC_PU32("radr", &radr),
7496	MC_PU32("rval", &rval),
7497	MC_PU32("pop_shorts", &pop_shorts),
7498	MC_PU32("dbg_cmd", &dbg_cmd),
7499	MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
7500	MC_PU32("endian", &endian),
7501	MC_PU32("step", &step),
7502	MC_PU32("udebug_flag", &udebug_flag),
7503	MC_PU32("decode_pic_begin", &decode_pic_begin),
7504	MC_PU32("slice_parse_begin", &slice_parse_begin),
7505	MC_PU32("i_only_flag", &i_only_flag),
7506	MC_PU32("error_handle_policy", &error_handle_policy),
7507	MC_PU32("buf_alloc_width", &buf_alloc_width),
7508	MC_PU32("buf_alloc_height", &buf_alloc_height),
7509	MC_PU32("buf_alloc_depth", &buf_alloc_depth),
7510	MC_PU32("buf_alloc_size", &buf_alloc_size),
7511	MC_PU32("buffer_mode", &buffer_mode),
7512	MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
7513	MC_PU32("max_buf_num", &max_buf_num),
7514	MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
7515	MC_PU32("mem_map_mode", &mem_map_mode),
7516	MC_PU32("double_write_mode", &double_write_mode),
7517	MC_PU32("enable_mem_saving", &enable_mem_saving),
7518	MC_PU32("force_w_h", &force_w_h),
7519	MC_PU32("force_fps", &force_fps),
7520	MC_PU32("max_decoding_time", &max_decoding_time),
7521	MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
7522	MC_PU32("start_decode_buf_level", &start_decode_buf_level),
7523	MC_PU32("decode_timeout_val", &decode_timeout_val),
7524	};
7525	static struct mconfig_node avs2_node;
7526
7527	static int __init amvdec_avs2_driver_init_module(void)
7528	{
7529
7530	#ifdef AVS2_10B_MMU
7531
7532	struct BuffInfo_s *p_buf_info;
7533
7534	if (vdec_is_support_4k()) {
7535	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7536	p_buf_info = &amvavs2_workbuff_spec[2];
7537	else
7538	p_buf_info = &amvavs2_workbuff_spec[1];
7539	} else
7540	p_buf_info = &amvavs2_workbuff_spec[0];
7541
7542	init_buff_spec(NULL, p_buf_info);
7543	work_buf_size =
7544	(p_buf_info->end_adr - p_buf_info->start_adr
7545	+ 0xffff) & (~0xffff);
7546
7547	#endif
7548	pr_debug("amvdec_avs2 module init\n");
7549
7550	#ifdef ERROR_HANDLE_DEBUG
7551	dbg_nal_skip_flag = 0;
7552	dbg_nal_skip_count = 0;
7553	#endif
7554	udebug_flag = 0;
7555	decode_pic_begin = 0;
7556	slice_parse_begin = 0;
7557	step = 0;
7558	buf_alloc_size = 0;
7559	if (platform_driver_register(&ammvdec_avs2_driver))
7560	pr_err("failed to register ammvdec_avs2 driver\n");
7561
7562	if (platform_driver_register(&amvdec_avs2_driver)) {
7563	pr_err("failed to register amvdec_avs2 driver\n");
7564	return -ENODEV;
7565	}
7566
7567	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
7568	amvdec_avs2_profile.profile =
7569	"8k, 10bit, dwrite, compressed";
7570	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7571	if (vdec_is_support_4k())
7572	amvdec_avs2_profile.profile =
7573	"4k, 10bit, dwrite, compressed";
7574	else
7575	amvdec_avs2_profile.profile =
7576	"10bit, dwrite, compressed";
7577	} else {
7578	amvdec_avs2_profile.name = "avs2_unsupport";
7579	}
7580
7581	vcodec_profile_register(&amvdec_avs2_profile);
7582	amvdec_avs2_profile_mult = amvdec_avs2_profile;
7583	amvdec_avs2_profile_mult.name = "mavs2";
7584	vcodec_profile_register(&amvdec_avs2_profile_mult);
7585
7586	INIT_REG_NODE_CONFIGS("media.decoder", &avs2_node,
7587	"avs2", avs2_configs, CONFIG_FOR_RW);
7588
7589	return 0;
7590	}
7591
7592	static void __exit amvdec_avs2_driver_remove_module(void)
7593	{
7594	pr_debug("amvdec_avs2 module remove.\n");
7595	platform_driver_unregister(&ammvdec_avs2_driver);
7596	platform_driver_unregister(&amvdec_avs2_driver);
7597	}
7598
7599	/****************************************/
7600
7601	module_param(bit_depth_luma, uint, 0664);
7602	MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_avs2 bit_depth_luma\n");
7603
7604	module_param(bit_depth_chroma, uint, 0664);
7605	MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_avs2 bit_depth_chroma\n");
7606
7607	module_param(frame_width, uint, 0664);
7608	MODULE_PARM_DESC(frame_width, "\n amvdec_avs2 frame_width\n");
7609
7610	module_param(frame_height, uint, 0664);
7611	MODULE_PARM_DESC(frame_height, "\n amvdec_avs2 frame_height\n");
7612
7613	module_param(debug, uint, 0664);
7614	MODULE_PARM_DESC(debug, "\n amvdec_avs2 debug\n");
7615
7616	module_param(debug_again, uint, 0664);
7617	MODULE_PARM_DESC(debug_again, "\n amvdec_avs2 debug_again\n");
7618
7619	module_param(radr, uint, 0664);
7620	MODULE_PARM_DESC(radr, "\nradr\n");
7621
7622	module_param(rval, uint, 0664);
7623	MODULE_PARM_DESC(rval, "\nrval\n");
7624
7625	module_param(pop_shorts, uint, 0664);
7626	MODULE_PARM_DESC(pop_shorts, "\nrval\n");
7627
7628	module_param(dbg_cmd, uint, 0664);
7629	MODULE_PARM_DESC(dbg_cmd, "\ndbg_cmd\n");
7630
7631	module_param(dbg_skip_decode_index, uint, 0664);
7632	MODULE_PARM_DESC(dbg_skip_decode_index, "\ndbg_skip_decode_index\n");
7633
7634	module_param(endian, uint, 0664);
7635	MODULE_PARM_DESC(endian, "\nrval\n");
7636
7637	module_param(step, uint, 0664);
7638	MODULE_PARM_DESC(step, "\n amvdec_avs2 step\n");
7639
7640	module_param(decode_pic_begin, uint, 0664);
7641	MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_avs2 decode_pic_begin\n");
7642
7643	module_param(slice_parse_begin, uint, 0664);
7644	MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_avs2 slice_parse_begin\n");
7645
7646	module_param(i_only_flag, uint, 0664);
7647	MODULE_PARM_DESC(i_only_flag, "\n amvdec_avs2 i_only_flag\n");
7648
7649	module_param(error_handle_policy, uint, 0664);
7650	MODULE_PARM_DESC(error_handle_policy, "\n amvdec_avs2 error_handle_policy\n");
7651
7652	module_param(re_search_seq_threshold, uint, 0664);
7653	MODULE_PARM_DESC(re_search_seq_threshold, "\n amvdec_avs2 re_search_seq_threshold\n");
7654
7655	module_param(buf_alloc_width, uint, 0664);
7656	MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
7657
7658	module_param(buf_alloc_height, uint, 0664);
7659	MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
7660
7661	module_param(buf_alloc_depth, uint, 0664);
7662	MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
7663
7664	module_param(buf_alloc_size, uint, 0664);
7665	MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
7666
7667	module_param(buffer_mode, uint, 0664);
7668	MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
7669
7670	module_param(buffer_mode_dbg, uint, 0664);
7671	MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
7672	/*USE_BUF_BLOCK*/
7673	module_param(max_buf_num, uint, 0664);
7674	MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
7675
7676	module_param(dynamic_buf_num_margin, uint, 0664);
7677	MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
7678
7679	#ifdef CONSTRAIN_MAX_BUF_NUM
7680	module_param(run_ready_max_vf_only_num, uint, 0664);
7681	MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
7682
7683	module_param(run_ready_display_q_num, uint, 0664);
7684	MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
7685
7686	module_param(run_ready_max_buf_num, uint, 0664);
7687	MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
7688	#endif
7689
7690	module_param(mv_buf_margin, uint, 0664);
7691	MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
7692
7693	module_param(run_ready_min_buf_num, uint, 0664);
7694	MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
7695
7696	/**/
7697
7698	module_param(mem_map_mode, uint, 0664);
7699	MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
7700
7701	module_param(double_write_mode, uint, 0664);
7702	MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
7703
7704	module_param(enable_mem_saving, uint, 0664);
7705	MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
7706
7707	module_param(force_w_h, uint, 0664);
7708	MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
7709
7710	module_param(force_fps, uint, 0664);
7711	MODULE_PARM_DESC(force_fps, "\n force_fps\n");
7712
7713	module_param(max_decoding_time, uint, 0664);
7714	MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
7715
7716	module_param(on_no_keyframe_skiped, uint, 0664);
7717	MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
7718
7719
7720	module_param(start_decode_buf_level, int, 0664);
7721	MODULE_PARM_DESC(start_decode_buf_level,
7722	"\n avs2 start_decode_buf_level\n");
7723
7724	module_param(decode_timeout_val, uint, 0664);
7725	MODULE_PARM_DESC(decode_timeout_val,
7726	"\n avs2 decode_timeout_val\n");
7727
7728	module_param_array(decode_frame_count, uint,
7729	&max_decode_instance_num, 0664);
7730
7731	module_param_array(display_frame_count, uint,
7732	&max_decode_instance_num, 0664);
7733
7734	module_param_array(max_process_time, uint,
7735	&max_decode_instance_num, 0664);
7736
7737	module_param_array(run_count, uint,
7738	&max_decode_instance_num, 0664);
7739
7740	module_param_array(input_empty, uint,
7741	&max_decode_instance_num, 0664);
7742
7743	module_param_array(not_run_ready, uint,
7744	&max_decode_instance_num, 0664);
7745
7746	module_param(video_signal_type, uint, 0664);
7747	MODULE_PARM_DESC(video_signal_type, "\n amvdec_avs2 video_signal_type\n");
7748
7749	module_param(force_video_signal_type, uint, 0664);
7750	MODULE_PARM_DESC(force_video_signal_type, "\n amvdec_avs2 force_video_signal_type\n");
7751
7752	module_param(enable_force_video_signal_type, uint, 0664);
7753	MODULE_PARM_DESC(enable_force_video_signal_type, "\n amvdec_avs2 enable_force_video_signal_type\n");
7754
7755
7756	module_param(udebug_flag, uint, 0664);
7757	MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
7758
7759	module_param(udebug_pause_pos, uint, 0664);
7760	MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
7761
7762	module_param(udebug_pause_val, uint, 0664);
7763	MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
7764
7765	module_param(udebug_pause_decode_idx, uint, 0664);
7766	MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
7767
7768	module_param(pre_decode_buf_level, int, 0664);
7769	MODULE_PARM_DESC(pre_decode_buf_level,
7770	"\n amvdec_avs2 pre_decode_buf_level\n");
7771
7772	module_param(again_threshold, uint, 0664);
7773	MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
7774
7775
7776	module_param(force_disp_pic_index, int, 0664);
7777	MODULE_PARM_DESC(force_disp_pic_index,
7778	"\n amvdec_h265 force_disp_pic_index\n");
7779
7780	module_param(without_display_mode, uint, 0664);
7781	MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
7782
7783	module_init(amvdec_avs2_driver_init_module);
7784	module_exit(amvdec_avs2_driver_remove_module);
7785
7786	MODULE_DESCRIPTION("AMLOGIC avs2 Video Decoder Driver");
7787	MODULE_LICENSE("GPL");
7788	MODULE_AUTHOR("Tim Yao <tim.yao@amlogic.com>");
7789