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path: root/drivers/frame_provider/decoder/h264/vh264.c (plain)
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1/*
2 * drivers/amlogic/media/frame_provider/decoder/h264/vh264.c
3 *
4 * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#define DEBUG
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/timer.h>
24#include <linux/kfifo.h>
25#include <linux/platform_device.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/tsync.h>
34#include <linux/workqueue.h>
35#include <linux/dma-mapping.h>
36#include <linux/atomic.h>
37#include <linux/module.h>
38#include <linux/slab.h>
39#include "../../../stream_input/amports/amports_priv.h"
40#include <linux/amlogic/media/canvas/canvas.h>
41
42#include "../utils/vdec.h"
43#include <linux/amlogic/media/utils/vdec_reg.h>
44#include "../utils/amvdec.h"
45#include "vh264.h"
46#include "../../../stream_input/parser/streambuf.h"
47#include <linux/delay.h>
48#include <linux/amlogic/media/video_sink/video.h>
49#include <linux/amlogic/tee.h>
50#include <linux/amlogic/media/ge2d/ge2d.h>
51#include "../utils/decoder_mmu_box.h"
52#include "../utils/decoder_bmmu_box.h"
53#include <linux/amlogic/media/codec_mm/codec_mm.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/firmware.h"
56#include <linux/amlogic/tee.h>
57
58#define DRIVER_NAME "amvdec_h264"
59#define MODULE_NAME "amvdec_h264"
60#define MEM_NAME "codec_264"
61#define HANDLE_H264_IRQ
62
63#if 0
64/* currently, only iptv supports this function*/
65#define SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
66#endif
67
68/* #define DEBUG_PTS */
69#if 0 /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV */
70#define DROP_B_FRAME_FOR_1080P_50_60FPS
71#endif
72#define RATE_MEASURE_NUM 8
73#define RATE_CORRECTION_THRESHOLD 5
74#define RATE_24_FPS 4004 /* 23.97 */
75#define RATE_25_FPS 3840 /* 25 */
76#define DUR2PTS(x) ((x)*90/96)
77#define PTS2DUR(x) ((x)*96/90)
78#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
79#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
80#define VDEC_CLOCK_ADJUST_FRAME 50
81
82static inline bool close_to(int a, int b, int m)
83{
84 return (abs(a - b) < m) ? true : false;
85}
86
87static DEFINE_MUTEX(vh264_mutex);
88#define DEF_BUF_START_ADDR 0x1000000
89#define V_BUF_ADDR_OFFSET_NEW (0x1ee000)
90#define V_BUF_ADDR_OFFSET (0x13e000)
91
92#define PIC_SINGLE_FRAME 0
93#define PIC_TOP_BOT_TOP 1
94#define PIC_BOT_TOP_BOT 2
95#define PIC_DOUBLE_FRAME 3
96#define PIC_TRIPLE_FRAME 4
97#define PIC_TOP_BOT 5
98#define PIC_BOT_TOP 6
99#define PIC_INVALID 7
100
101#define EXTEND_SAR 0xff
102
103#define VF_POOL_SIZE 64
104#define VF_BUF_NUM 24
105#define WORKSPACE_BUF_NUM 2
106#define PUT_INTERVAL (HZ/100)
107#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
108
109#define SWITCHING_STATE_OFF 0
110#define SWITCHING_STATE_ON_CMD3 1
111#define SWITCHING_STATE_ON_CMD1 2
112#define SWITCHING_STATE_ON_CMD1_PENDING 3
113
114
115#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
116#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
117#define DEC_CONTROL_FLAG_DISABLE_FAST_POC 0x0004
118
119#define INCPTR(p) ptr_atomic_wrap_inc(&p)
120
121#define SLICE_TYPE_I 2
122#define SLICE_TYPE_P 5
123#define SLICE_TYPE_B 6
124
125struct buffer_spec_s {
126 unsigned int y_addr;
127 unsigned int u_addr;
128 unsigned int v_addr;
129
130 int y_canvas_index;
131 int u_canvas_index;
132 int v_canvas_index;
133
134 unsigned int y_canvas_width;
135 unsigned int u_canvas_width;
136 unsigned int v_canvas_width;
137
138 unsigned int y_canvas_height;
139 unsigned int u_canvas_height;
140 unsigned int v_canvas_height;
141
142 unsigned long phy_addr;
143 int alloc_count;
144};
145
146#define spec2canvas(x) \
147 (((x)->v_canvas_index << 16) | \
148 ((x)->u_canvas_index << 8) | \
149 ((x)->y_canvas_index << 0))
150
151static struct vframe_s *vh264_vf_peek(void *);
152static struct vframe_s *vh264_vf_get(void *);
153static void vh264_vf_put(struct vframe_s *, void *);
154static int vh264_vf_states(struct vframe_states *states, void *);
155static int vh264_event_cb(int type, void *data, void *private_data);
156
157static void vh264_prot_init(void);
158static int vh264_local_init(void);
159static void vh264_put_timer_func(unsigned long arg);
160static void stream_switching_done(void);
161
162static const char vh264_dec_id[] = "vh264-dev";
163
164#define PROVIDER_NAME "decoder.h264"
165
166static const struct vframe_operations_s vh264_vf_provider_ops = {
167 .peek = vh264_vf_peek,
168 .get = vh264_vf_get,
169 .put = vh264_vf_put,
170 .event_cb = vh264_event_cb,
171 .vf_states = vh264_vf_states,
172};
173
174static struct vframe_provider_s vh264_vf_prov;
175/*TODO irq*/
176#if 1
177static u32 frame_width, frame_height, frame_dur, frame_prog, frame_packing_type,
178 last_duration;
179static u32 saved_resolution;
180static u32 last_mb_width, last_mb_height;
181#else
182static u32 frame_buffer_size;
183static u32 frame_width, frame_height, frame_dur, frame_prog, last_duration;
184static u32 last_mb_width, last_mb_height;
185static u32 frame_packing_type;
186#endif
187static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
188static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
189static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE);
190static DECLARE_KFIFO(delay_display_q, struct vframe_s *, VF_POOL_SIZE);
191
192static struct vframe_s vfpool[VF_POOL_SIZE];
193static s32 vfbuf_use[VF_BUF_NUM];
194static struct buffer_spec_s buffer_spec[VF_BUF_NUM];
195static struct buffer_spec_s fense_buffer_spec[2];
196/* disp buf + keep buf+ fense buf + workspace */
197
198#define MAX_BLK_BUFFERS (VF_BUF_NUM + 2 + WORKSPACE_BUF_NUM)
199#define VF_BUFFER_IDX(n) (WORKSPACE_BUF_NUM + n)
200#define FENSE_BUFFER_IDX(n) (WORKSPACE_BUF_NUM + VF_BUF_NUM + n)
201
202#define USER_DATA_RUND_SIZE (USER_DATA_SIZE + 4096)
203static struct vframe_s fense_vf[2];
204
205static struct timer_list recycle_timer;
206static u32 stat;
207static s32 buf_offset;
208static u32 pts_outside;
209static u32 sync_outside;
210static u32 dec_control;
211static u32 vh264_ratio;
212static u32 vh264_rotation;
213static u32 use_idr_framerate;
214static u32 high_bandwidth;
215
216static u32 seq_info;
217static u32 timing_info_present_flag;
218static u32 fixed_frame_rate_flag;
219static u32 fixed_frame_rate_check_count;
220static u32 aspect_ratio_info;
221static u32 num_units_in_tick;
222static u32 time_scale;
223static u32 h264_ar;
224static u32 decoder_debug_flag;
225static u32 dpb_size_adj = 6;
226static u32 fr_hint_status;
227
228#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
229static u32 last_interlaced;
230#endif
231static bool is_4k;
232static unsigned char h264_first_pts_ready;
233static bool h264_first_valid_pts_ready;
234static u32 h264pts1, h264pts2;
235static u32 h264_pts_count, duration_from_pts_done, duration_on_correcting;
236static u32 vh264_error_count;
237static u32 vh264_no_disp_count;
238static u32 fatal_error_flag;
239static u32 fatal_error_reset;
240static u32 max_refer_buf = 1;
241static u32 decoder_force_reset;
242static unsigned int no_idr_error_count;
243static unsigned int no_idr_error_max = 60;
244#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
245/* 0~128*/
246static u32 bad_block_scale;
247#endif
248
249static unsigned int enable_switch_fense = 1;
250#define EN_SWITCH_FENCE() (enable_switch_fense && !is_4k)
251#if 0
252static u32 vh264_no_disp_wd_count;
253#endif
254static u32 vh264_running;
255static s32 vh264_stream_switching_state;
256static s32 vh264_eos;
257static struct vframe_s *p_last_vf;
258static s32 iponly_early_mode;
259static void *mm_blk_handle;
260static int tvp_flag;
261static bool is_reset;
262
263/*TODO irq*/
264#if 1
265static u32 last_pts, last_pts_remainder;
266#else
267static u32 last_pts;
268#endif
269static bool check_pts_discontinue;
270static u32 wait_buffer_counter;
271static u32 video_signal_from_vui;
272
273static uint error_recovery_mode;
274static uint error_recovery_mode_in = 3;
275static uint error_recovery_mode_use = 3;
276
277static uint mb_total = 0, mb_width = 0, mb_height;
278static uint saved_idc_level;
279#define UCODE_IP_ONLY 2
280#define UCODE_IP_ONLY_PARAM 1
281static uint ucode_type;
282
283#ifdef DEBUG_PTS
284static unsigned long pts_missed, pts_hit;
285#endif
286static uint debugfirmware;
287
288static atomic_t vh264_active = ATOMIC_INIT(0);
289static int vh264_reset;
290static struct work_struct error_wd_work;
291static struct work_struct stream_switching_work;
292static struct work_struct set_parameter_work;
293static struct work_struct notify_work;
294
295static struct work_struct userdata_push_work;
296
297
298
299static struct dec_sysinfo vh264_amstream_dec_info;
300static dma_addr_t mc_dma_handle;
301static void *mc_cpu_addr;
302static u32 first_offset;
303static u32 first_pts;
304static u64 first_pts64;
305static bool first_pts_cached;
306static void *sei_data_buffer;
307static dma_addr_t sei_data_buffer_phys;
308static int clk_adj_frame_count;
309
310#define MC_OFFSET_HEADER 0x0000
311#define MC_OFFSET_DATA 0x1000
312#define MC_OFFSET_MMCO 0x2000
313#define MC_OFFSET_LIST 0x3000
314#define MC_OFFSET_SLICE 0x4000
315
316#define MC_TOTAL_SIZE (20*SZ_1K)
317#define MC_SWAP_SIZE (4*SZ_1K)
318
319#define MODE_ERROR 0
320#define MODE_FULL 1
321
322static DEFINE_SPINLOCK(lock);
323static DEFINE_SPINLOCK(prepare_lock);
324static DEFINE_SPINLOCK(recycle_lock);
325
326static bool block_display_q;
327static int vh264_stop(int mode);
328static s32 vh264_init(void);
329
330#define DFS_HIGH_THEASHOLD 3
331
332static bool pts_discontinue;
333
334static struct ge2d_context_s *ge2d_videoh264_context;
335
336static struct vdec_info *gvs;
337
338static int ge2d_videoh264task_init(void)
339{
340 if (ge2d_videoh264_context == NULL)
341 ge2d_videoh264_context = create_ge2d_work_queue();
342
343 if (ge2d_videoh264_context == NULL) {
344 pr_info("create_ge2d_work_queue video task failed\n");
345 return -1;
346 }
347 return 0;
348}
349
350static int ge2d_videoh264task_release(void)
351{
352 if (ge2d_videoh264_context) {
353 destroy_ge2d_work_queue(ge2d_videoh264_context);
354 ge2d_videoh264_context = NULL;
355 }
356 return 0;
357}
358
359static int ge2d_canvas_dup(struct canvas_s *srcy, struct canvas_s *srcu,
360 struct canvas_s *des, int format, u32 srcindex,
361 u32 desindex)
362{
363
364 struct config_para_ex_s ge2d_config;
365 /* pr_info("[%s]h264 ADDR srcy[0x%lx] srcu[0x%lx] des[0x%lx]\n",
366 * __func__, srcy->addr, srcu->addr, des->addr);
367 */
368 memset(&ge2d_config, 0, sizeof(struct config_para_ex_s));
369
370 ge2d_config.alu_const_color = 0;
371 ge2d_config.bitmask_en = 0;
372 ge2d_config.src1_gb_alpha = 0;
373
374 ge2d_config.src_planes[0].addr = srcy->addr;
375 ge2d_config.src_planes[0].w = srcy->width;
376 ge2d_config.src_planes[0].h = srcy->height;
377
378 ge2d_config.src_planes[1].addr = srcu->addr;
379 ge2d_config.src_planes[1].w = srcu->width;
380 ge2d_config.src_planes[1].h = srcu->height;
381
382 ge2d_config.dst_planes[0].addr = des->addr;
383 ge2d_config.dst_planes[0].w = des->width;
384 ge2d_config.dst_planes[0].h = des->height;
385
386 ge2d_config.src_para.canvas_index = srcindex;
387 ge2d_config.src_para.mem_type = CANVAS_TYPE_INVALID;
388 ge2d_config.src_para.format = format;
389 ge2d_config.src_para.fill_color_en = 0;
390 ge2d_config.src_para.fill_mode = 0;
391 ge2d_config.src_para.color = 0;
392 ge2d_config.src_para.top = 0;
393 ge2d_config.src_para.left = 0;
394 ge2d_config.src_para.width = srcy->width;
395 ge2d_config.src_para.height = srcy->height;
396
397 ge2d_config.dst_para.canvas_index = desindex;
398 ge2d_config.dst_para.mem_type = CANVAS_TYPE_INVALID;
399 ge2d_config.dst_para.format = format;
400 ge2d_config.dst_para.fill_color_en = 0;
401 ge2d_config.dst_para.fill_mode = 0;
402 ge2d_config.dst_para.color = 0;
403 ge2d_config.dst_para.top = 0;
404 ge2d_config.dst_para.left = 0;
405 ge2d_config.dst_para.width = srcy->width;
406 ge2d_config.dst_para.height = srcy->height;
407
408 if (ge2d_context_config_ex(ge2d_videoh264_context, &ge2d_config) < 0) {
409 pr_info("ge2d_context_config_ex failed\n");
410 return -1;
411 }
412
413 stretchblt_noalpha(ge2d_videoh264_context, 0, 0, srcy->width,
414 srcy->height, 0, 0, srcy->width, srcy->height);
415
416 return 0;
417}
418
419static inline int fifo_level(void)
420{
421 return VF_POOL_SIZE - kfifo_len(&newframe_q);
422}
423
424
425void spec_set_canvas(struct buffer_spec_s *spec,
426 unsigned int width, unsigned int height)
427{
428 canvas_config(spec->y_canvas_index,
429 spec->y_addr,
430 width, height,
431 CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32);
432
433 canvas_config(spec->u_canvas_index,
434 spec->u_addr,
435 width, height / 2,
436 CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32);
437 return;
438}
439
440static void vh264_notify_work(struct work_struct *work)
441{
442 pr_info("frame duration changed %d\n", frame_dur);
443 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
444 (void *)((unsigned long)frame_dur));
445
446 return;
447}
448
449static void prepare_display_q(void)
450{
451 unsigned long flags;
452 int count;
453
454 spin_lock_irqsave(&prepare_lock, flags);
455
456 if (block_display_q) {
457 spin_unlock_irqrestore(&prepare_lock, flags);
458 return;
459 }
460
461 spin_unlock_irqrestore(&prepare_lock, flags);
462
463 count = (int)VF_POOL_SIZE -
464 kfifo_len(&delay_display_q) -
465 kfifo_len(&display_q) -
466 kfifo_len(&recycle_q) -
467 kfifo_len(&newframe_q);
468
469 if ((vh264_stream_switching_state != SWITCHING_STATE_OFF)
470 || !EN_SWITCH_FENCE())
471 count = 0;
472 else
473 count = (count < 2) ? 0 : 2;
474
475 while (kfifo_len(&delay_display_q) > count) {
476 struct vframe_s *vf;
477
478 if (kfifo_get(&delay_display_q, &vf)) {
479 kfifo_put(&display_q,
480 (const struct vframe_s *)vf);
481 vf_notify_receiver(PROVIDER_NAME,
482 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
483 }
484 }
485}
486
487static struct vframe_s *vh264_vf_peek(void *op_arg)
488{
489 struct vframe_s *vf;
490
491 if (kfifo_peek(&display_q, &vf))
492 return vf;
493
494 return NULL;
495}
496
497static struct vframe_s *vh264_vf_get(void *op_arg)
498{
499 struct vframe_s *vf;
500
501 if (kfifo_get(&display_q, &vf))
502 return vf;
503
504 return NULL;
505}
506
507static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
508{
509 unsigned long flags;
510
511 spin_lock_irqsave(&recycle_lock, flags);
512
513 if ((vf != &fense_vf[0]) && (vf != &fense_vf[1]))
514 kfifo_put(&recycle_q, (const struct vframe_s *)vf);
515
516 spin_unlock_irqrestore(&recycle_lock, flags);
517}
518
519static int vh264_event_cb(int type, void *data, void *private_data)
520{
521 if (type & VFRAME_EVENT_RECEIVER_RESET) {
522 unsigned long flags;
523
524 amvdec_stop();
525#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
526 vf_light_unreg_provider(&vh264_vf_prov);
527#endif
528 spin_lock_irqsave(&lock, flags);
529 vh264_local_init();
530 vh264_prot_init();
531 spin_unlock_irqrestore(&lock, flags);
532#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
533 vf_reg_provider(&vh264_vf_prov);
534#endif
535 amvdec_start();
536 }
537 return 0;
538}
539
540static int vh264_vf_states(struct vframe_states *states, void *op_arg)
541{
542 unsigned long flags;
543
544 spin_lock_irqsave(&lock, flags);
545
546 states->vf_pool_size = VF_POOL_SIZE;
547 states->buf_free_num = kfifo_len(&newframe_q);
548 states->buf_avail_num = kfifo_len(&display_q) +
549 kfifo_len(&delay_display_q);
550 states->buf_recycle_num = kfifo_len(&recycle_q);
551
552 spin_unlock_irqrestore(&lock, flags);
553
554 return 0;
555}
556
557#if 0
558static tvin_trans_fmt_t convert_3d_format(u32 type)
559{
560 const tvin_trans_fmt_t conv_tab[] = {
561 0, /* checkerboard */
562 0, /* column alternation */
563 TVIN_TFMT_3D_LA, /* row alternation */
564 TVIN_TFMT_3D_LRH_OLER, /* side by side */
565 TVIN_TFMT_3D_FA /* top bottom */
566 };
567
568 return (type <= 4) ? conv_tab[type] : 0;
569}
570#endif
571
572
573#ifdef DEBUG_CC_USER_DATA
574static int vbi_to_ascii(int c)
575{
576 if (c < 0)
577 return '?';
578
579 c &= 0x7F;
580
581 if (c < 0x20 || c >= 0x7F)
582 return '.';
583
584 return c;
585}
586
587static void dump_cc_ascii(const uint8_t *buf, int poc)
588{
589 int cc_flag;
590 int cc_count;
591 int i;
592 int szAscii[32];
593 int index = 0;
594
595 cc_flag = buf[1] & 0x40;
596 if (!cc_flag) {
597 pr_info("### cc_flag is invalid\n");
598 return;
599 }
600 cc_count = buf[1] & 0x1f;
601
602 for (i = 0; i < cc_count; ++i) {
603 unsigned int b0;
604 unsigned int cc_valid;
605 unsigned int cc_type;
606 unsigned char cc_data1;
607 unsigned char cc_data2;
608
609 b0 = buf[3 + i * 3];
610 cc_valid = b0 & 4;
611 cc_type = b0 & 3;
612 cc_data1 = buf[4 + i * 3];
613 cc_data2 = buf[5 + i * 3];
614
615
616 if (cc_type == 0) {
617 /* NTSC pair, Line 21 */
618 szAscii[index++] = vbi_to_ascii(cc_data1);
619 szAscii[index++] = vbi_to_ascii(cc_data2);
620 if ((!cc_valid) || (i >= 3))
621 break;
622 }
623 }
624 switch (index) {
625 case 8:
626 pr_info("push poc:%d : %c %c %c %c %c %c %c %c\n",
627 poc,
628 szAscii[0], szAscii[1], szAscii[2], szAscii[3],
629 szAscii[4], szAscii[5], szAscii[6], szAscii[7]);
630 break;
631 case 7:
632 pr_info("push poc:%d : %c %c %c %c %c %c %c\n",
633 poc,
634 szAscii[0], szAscii[1], szAscii[2], szAscii[3],
635 szAscii[4], szAscii[5], szAscii[6]);
636 break;
637 case 6:
638 pr_info("push poc:%d : %c %c %c %c %c %c\n", poc,
639 szAscii[0], szAscii[1], szAscii[2], szAscii[3],
640 szAscii[4], szAscii[5]);
641 break;
642 case 5:
643 pr_info("push poc:%d : %c %c %c %c %c\n", poc,
644 szAscii[0], szAscii[1], szAscii[2], szAscii[3],
645 szAscii[4]);
646 break;
647 case 4:
648 pr_info("push poc:%d : %c %c %c %c\n", poc,
649 szAscii[0], szAscii[1], szAscii[2], szAscii[3]);
650 break;
651 case 3:
652 pr_info("push poc:%d : %c %c %c\n", poc,
653 szAscii[0], szAscii[1], szAscii[2]);
654 break;
655 case 2:
656 pr_info("push poc:%d : %c %c\n", poc,
657 szAscii[0], szAscii[1]);
658 break;
659 case 1:
660 pr_info("push poc:%d : %c\n", poc, szAscii[0]);
661 break;
662 default:
663 pr_info("push poc:%d and no CC data: index = %d\n",
664 poc, index);
665 break;
666 }
667}
668
669/*
670#define DUMP_USER_DATA_HEX
671*/
672
673#ifdef DUMP_USER_DATA_HEX
674static void print_data(unsigned char *pdata, int len)
675{
676 int nLeft;
677
678 nLeft = len;
679
680 while (nLeft >= 8) {
681 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
682 pdata[0], pdata[1], pdata[2], pdata[3],
683 pdata[4], pdata[5], pdata[6], pdata[7]);
684 nLeft -= 8;
685 pdata += 8;
686 }
687}
688#endif
689
690static void aml_swap_data(uint8_t *user_data, int ud_size)
691{
692 int swap_blocks, i, j, k, m;
693 unsigned char c_temp;
694
695 /* swap byte order */
696 swap_blocks = ud_size / 8;
697 for (i = 0; i < swap_blocks; i++) {
698 j = i * 8;
699 k = j + 7;
700 for (m = 0; m < 4; m++) {
701 c_temp = user_data[j];
702 user_data[j++] = user_data[k];
703 user_data[k--] = c_temp;
704 }
705 }
706}
707
708static void dump_data(unsigned int user_data_wp,
709 unsigned int user_data_length,
710 int poc)
711{
712 unsigned char *pdata;
713 int user_data_len;
714 int wp_start;
715 int nLeft;
716 unsigned char szBuf[256];
717 int nOffset;
718
719 dma_sync_single_for_cpu(amports_get_dma_device(),
720 sei_data_buffer_phys, USER_DATA_SIZE,
721 DMA_FROM_DEVICE);
722
723 if (user_data_length & 0x07)
724 user_data_len = (user_data_length + 8) & 0xFFFFFFF8;
725 else
726 user_data_len = user_data_length;
727
728 if (user_data_wp >= user_data_len) {
729 wp_start = user_data_wp - user_data_len;
730
731 pdata = (unsigned char *)sei_data_buffer;
732 pdata += wp_start;
733 nLeft = user_data_len;
734
735 memset(szBuf, 0, 256);
736 memcpy(szBuf, pdata, user_data_len);
737 } else {
738 wp_start = user_data_wp +
739 USER_DATA_SIZE - user_data_len;
740
741 pdata = (unsigned char *)sei_data_buffer;
742 pdata += wp_start;
743 nLeft = USER_DATA_SIZE - wp_start;
744
745 memset(szBuf, 0, 256);
746 memcpy(szBuf, pdata, nLeft);
747 nOffset = nLeft;
748
749 pdata = (unsigned char *)sei_data_buffer;
750 nLeft = user_data_wp;
751 memcpy(szBuf+nOffset, pdata, nLeft);
752 }
753
754 aml_swap_data(szBuf, user_data_len);
755#ifdef DUMP_USER_DATA_HEX
756 print_data(szBuf, user_data_len);
757#endif
758 dump_cc_ascii(szBuf+7, poc);
759}
760#endif
761
762
763static void userdata_push_do_work(struct work_struct *work)
764{
765 unsigned int sei_itu35_flags;
766 unsigned int sei_itu35_wp;
767 unsigned int sei_itu35_data_length;
768 struct userdata_poc_info_t user_data_poc;
769
770 sei_itu35_flags = READ_VREG(AV_SCRATCH_J);
771 sei_itu35_wp = (sei_itu35_flags >> 16) & 0xffff;
772 sei_itu35_data_length = sei_itu35_flags & 0x7fff;
773
774#if 0
775 pr_info("pocinfo 0x%x, top poc %d, wp 0x%x, length %d\n",
776 READ_VREG(AV_SCRATCH_L),
777 READ_VREG(AV_SCRATCH_M),
778 sei_itu35_wp, sei_itu35_data_length);
779#endif
780 user_data_poc.poc_info = READ_VREG(AV_SCRATCH_L);
781 user_data_poc.poc_number = READ_VREG(AV_SCRATCH_M);
782#ifdef DEBUG_CC_USER_DATA
783 dump_data(sei_itu35_wp, sei_itu35_data_length,
784 user_data_poc.poc_number);
785#endif
786 WRITE_VREG(AV_SCRATCH_J, 0);
787 wakeup_userdata_poll(user_data_poc, sei_itu35_wp,
788 (unsigned long)sei_data_buffer,
789 USER_DATA_SIZE, sei_itu35_data_length);
790}
791
792
793static void set_frame_info(struct vframe_s *vf)
794{
795 vf->width = frame_width;
796 vf->height = frame_height;
797 vf->duration = frame_dur;
798 vf->ratio_control =
799 (min(h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
800 DISP_RATIO_ASPECT_RATIO_BIT;
801 vf->orientation = vh264_rotation;
802 vf->flag = 0;
803
804#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER_3D_PROCESS
805 vf->trans_fmt = 0;
806 if ((vf->trans_fmt == TVIN_TFMT_3D_LRF) ||
807 (vf->trans_fmt == TVIN_TFMT_3D_LA)) {
808 vf->left_eye.start_x = 0;
809 vf->left_eye.start_y = 0;
810 vf->left_eye.width = frame_width / 2;
811 vf->left_eye.height = frame_height;
812
813 vf->right_eye.start_x = 0;
814 vf->right_eye.start_y = 0;
815 vf->right_eye.width = frame_width / 2;
816 vf->right_eye.height = frame_height;
817 } else if ((vf->trans_fmt == TVIN_TFMT_3D_LRH_OLER) ||
818 (vf->trans_fmt == TVIN_TFMT_3D_TB)) {
819 vf->left_eye.start_x = 0;
820 vf->left_eye.start_y = 0;
821 vf->left_eye.width = frame_width / 2;
822 vf->left_eye.height = frame_height;
823
824 vf->right_eye.start_x = 0;
825 vf->right_eye.start_y = 0;
826 vf->right_eye.width = frame_width / 2;
827 vf->right_eye.height = frame_height;
828 }
829#endif
830
831}
832
833#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
834static void vh264_ppmgr_reset(void)
835{
836 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL);
837
838 vh264_local_init();
839
840 pr_info("vh264dec: vf_ppmgr_reset\n");
841}
842#endif
843
844static int get_max_dpb_size(int level_idc, int mb_width, int mb_height)
845{
846 int size, r;
847
848 switch (level_idc) {
849 case 10:
850 r = 1485;
851 break;
852 case 11:
853 r = 3375;
854 break;
855 case 12:
856 case 13:
857 case 20:
858 r = 8910;
859 break;
860 case 21:
861 r = 17820;
862 break;
863 case 22:
864 case 30:
865 r = 30375;
866 break;
867 case 31:
868 r = 67500;
869 break;
870 case 32:
871 r = 76800;
872 break;
873 case 40:
874 case 41:
875 case 42:
876 r = 122880;
877 break;
878 case 50:
879 r = 414000;
880 break;
881 case 51:
882 case 52:
883 r = 691200;
884 break;
885 default:
886 return 0;
887 }
888 size = (mb_width * mb_height +
889 (mb_width * mb_height / 2)) * 256 * 10;
890 r = (r * 1024 + size-1) / size;
891 r = min(r, 16);
892 /*pr_info("max_dpb %d size:%d\n", r, size);*/
893 return r;
894}
895static void vh264_set_params(struct work_struct *work)
896{
897 int aspect_ratio_info_present_flag, aspect_ratio_idc;
898 int max_dpb_size, actual_dpb_size, max_reference_size;
899 int i, mb_mv_byte, ret;
900 unsigned long addr;
901 unsigned int post_canvas, buf_size;
902 unsigned int frame_mbs_only_flag;
903 unsigned int chroma_format_idc, chroma444, video_signal;
904 unsigned int crop_infor, crop_bottom, crop_right, level_idc;
905 if (!atomic_read(&vh264_active))
906 return;
907 mutex_lock(&vh264_mutex);
908 if (vh264_stream_switching_state == SWITCHING_STATE_ON_CMD1)
909 vh264_stream_switching_state = SWITCHING_STATE_ON_CMD1_PENDING;
910 post_canvas = get_post_canvas();
911 clk_adj_frame_count = 0;
912 /* set to max decoder clock rate at the beginning */
913 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
914 timing_info_present_flag = 0;
915 mb_width = READ_VREG(AV_SCRATCH_1);
916 seq_info = READ_VREG(AV_SCRATCH_2);
917 aspect_ratio_info = READ_VREG(AV_SCRATCH_3);
918 num_units_in_tick = READ_VREG(AV_SCRATCH_4);
919 time_scale = READ_VREG(AV_SCRATCH_5);
920 level_idc = READ_VREG(AV_SCRATCH_A);
921 if (level_idc > 0)
922 saved_idc_level = level_idc;
923 else if (saved_idc_level > 0)
924 level_idc = saved_idc_level;
925 video_signal = READ_VREG(AV_SCRATCH_H);
926 video_signal_from_vui =
927 ((video_signal & 0xffff) << 8) |
928 ((video_signal & 0xff0000) >> 16) |
929 ((video_signal & 0x3f000000));
930/*
931 * pr_info("video_signal_type_present_flag 0x%x\n",
932 * (video_signal_from_vui >> 29) & 1);
933 * pr_info("video_format 0x%x\n",
934 * (video_signal_from_vui >> 26) & 7);
935 * pr_info("video_full_range_flag 0x%x\n",
936 * (video_signal_from_vui >> 25) & 1);
937 * pr_info("color_description_present_flag 0x%x\n",
938 * (video_signal_from_vui >> 24) & 1);
939 * pr_info("color_primaries 0x%x\n",
940 * (video_signal_from_vui >> 16) & 0xff);
941 * pr_info("transfer_characteristic 0x%x\n",
942 * (video_signal_from_vui >> 8) & 0xff);
943 * pr_info("matrix_coefficient 0x%x\n",
944 * video_signal_from_vui & 0xff);
945 */
946
947 mb_total = (mb_width >> 8) & 0xffff;
948 max_reference_size = (mb_width >> 24) & 0x7f;
949 mb_mv_byte = (mb_width & 0x80000000) ? 24 : 96;
950 if (ucode_type == UCODE_IP_ONLY_PARAM)
951 mb_mv_byte = 96;
952 mb_width = mb_width & 0xff;
953 if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) {
954 if (!mb_width && mb_total)
955 mb_width = 256;
956 }
957 mb_height = mb_total / mb_width;
958 last_duration = 0;
959 /* AV_SCRATCH_2
960 * bit 15: frame_mbs_only_flag
961 * bit 13-14: chroma_format_idc
962 */
963 frame_mbs_only_flag = (seq_info >> 15) & 0x01;
964 chroma_format_idc = (seq_info >> 13) & 0x03;
965 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
966
967 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
968 * @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
969 * (2 - frame_mbs_only_flag)
970 */
971 crop_infor = READ_VREG(AV_SCRATCH_6);
972 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
973 crop_right = ((crop_infor >> 16) & 0xff) >> (2 - frame_mbs_only_flag);
974
975 /* if width or height from outside is not equal to mb, then use mb */
976 /* add: for seeking stream with other resolution */
977 if ((last_mb_width && (last_mb_width != mb_width))
978 || (mb_width != ((frame_width + 15) >> 4)))
979 frame_width = 0;
980 if ((last_mb_height && (last_mb_height != mb_height))
981 || (mb_height != ((frame_height + 15) >> 4)))
982 frame_height = 0;
983 last_mb_width = mb_width;
984 last_mb_height = mb_height;
985
986 if ((frame_width == 0) || (frame_height == 0) || crop_infor) {
987 frame_width = mb_width << 4;
988 frame_height = mb_height << 4;
989 if (frame_mbs_only_flag) {
990 frame_height =
991 frame_height - (2 >> chroma444) *
992 min(crop_bottom,
993 (unsigned int)((8 << chroma444) - 1));
994 frame_width =
995 frame_width - (2 >> chroma444) * min(crop_right,
996 (unsigned
997 int)((8 << chroma444) - 1));
998 } else {
999 frame_height =
1000 frame_height - (4 >> chroma444) *
1001 min(crop_bottom,
1002 (unsigned int)((8 << chroma444)
1003 - 1));
1004 frame_width =
1005 frame_width - (4 >> chroma444) * min(crop_right,
1006 (unsigned
1007 int)((8 <<
1008 chroma444)
1009 - 1));
1010 }
1011#if 0
1012 pr_info
1013 ("frame_mbs_only_flag %d, crop_bottom %d, frame_height %d, ",
1014 frame_mbs_only_flag, crop_bottom, frame_height);
1015 pr_info
1016 ("mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
1017 mb_height, crop_right, frame_width, mb_width);
1018#endif
1019 if (frame_height == 1088)
1020 frame_height = 1080;
1021 }
1022
1023 mb_width = (mb_width + 3) & 0xfffffffc;
1024 mb_height = (mb_height + 3) & 0xfffffffc;
1025 mb_total = mb_width * mb_height;
1026
1027 /*max_reference_size <= max_dpb_size <= actual_dpb_size*/
1028 is_4k = (mb_total > 8160) ? true:false;
1029
1030
1031 max_dpb_size = get_max_dpb_size(level_idc, mb_width, mb_height);
1032 if (max_dpb_size < max_reference_size)
1033 max_dpb_size = max_reference_size;
1034 if (max_dpb_size > 15
1035 && get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB
1036 && (codec_mm_get_total_size() < 80 * SZ_1M)) {
1037 actual_dpb_size
1038 = max_reference_size + dpb_size_adj;
1039 if (actual_dpb_size > VF_BUF_NUM)
1040 actual_dpb_size = VF_BUF_NUM;
1041 } else {
1042 actual_dpb_size = max_dpb_size + dpb_size_adj;
1043 actual_dpb_size = min(actual_dpb_size, VF_BUF_NUM);
1044 }
1045 max_reference_size++;
1046 pr_info("actual_dpb_size %d max_dpb_size %d max_ref %d\n",
1047 actual_dpb_size, max_dpb_size,
1048 max_reference_size);
1049 buf_size = mb_total * mb_mv_byte * max_reference_size;
1050
1051 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 1,
1052 buf_size, DRIVER_NAME, &addr);
1053
1054 if (ret < 0) {
1055 fatal_error_flag =
1056 DECODER_FATAL_ERROR_NO_MEM;
1057 vh264_running = 0;
1058 mutex_unlock(&vh264_mutex);
1059 return;
1060 }
1061
1062 WRITE_VREG(AV_SCRATCH_1, addr);
1063 WRITE_VREG(AV_SCRATCH_3, post_canvas);
1064 WRITE_VREG(AV_SCRATCH_4, addr + buf_size);
1065
1066 if (!(READ_VREG(AV_SCRATCH_F) & 0x1)) {
1067 for (i = 0; i < actual_dpb_size; i++) {
1068#ifdef DOUBLE_WRITE
1069 int page_count =
1070 PAGE_ALIGN((mb_total << 8) + (mb_total
1071 << 7) + (mb_total << 6) +
1072 (mb_total << 5)) / PAGE_SIZE;
1073#else
1074 int page_count =
1075 PAGE_ALIGN((mb_total << 8) +
1076 (mb_total << 7)) / PAGE_SIZE;
1077#endif
1078
1079 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle,
1080 VF_BUFFER_IDX(i),
1081 page_count << PAGE_SHIFT,
1082 DRIVER_NAME, &buffer_spec[i].phy_addr);
1083
1084 if (ret < 0) {
1085 buffer_spec[i].alloc_count = 0;
1086 fatal_error_flag =
1087 DECODER_FATAL_ERROR_NO_MEM;
1088 vh264_running = 0;
1089 mutex_unlock(&vh264_mutex);
1090 return;
1091 }
1092
1093 addr = buffer_spec[i].phy_addr;
1094 buffer_spec[i].alloc_count = page_count;
1095
1096 if (i <= 21) {
1097 buffer_spec[i].y_addr = addr;
1098 addr += mb_total << 8;
1099 buffer_spec[i].u_addr = addr;
1100 buffer_spec[i].v_addr = addr;
1101 addr += mb_total << 7;
1102 vfbuf_use[i] = 0;
1103
1104 buffer_spec[i].y_canvas_index = 128 + i * 2;
1105 buffer_spec[i].u_canvas_index = 128 + i * 2 + 1;
1106 buffer_spec[i].v_canvas_index = 128 + i * 2 + 1;
1107
1108 buffer_spec[i].y_canvas_width = mb_width << 4;
1109 buffer_spec[i].y_canvas_height = mb_height << 4;
1110 buffer_spec[i].u_canvas_width = mb_width << 4;
1111 buffer_spec[i].u_canvas_height = mb_height << 4;
1112 buffer_spec[i].v_canvas_width = mb_width << 4;
1113 buffer_spec[i].v_canvas_height = mb_height << 4;
1114
1115 canvas_config(128 + i * 2,
1116 buffer_spec[i].y_addr,
1117 mb_width << 4, mb_height << 4,
1118 CANVAS_ADDR_NOWRAP,
1119 CANVAS_BLKMODE_32X32);
1120 canvas_config(128 + i * 2 + 1,
1121 buffer_spec[i].u_addr,
1122 mb_width << 4, mb_height << 3,
1123 CANVAS_ADDR_NOWRAP,
1124 CANVAS_BLKMODE_32X32);
1125 WRITE_VREG(ANC0_CANVAS_ADDR + i,
1126 spec2canvas(&buffer_spec[i]));
1127 } else {
1128 buffer_spec[i].y_canvas_index =
1129 2 * (i - 21) + 4;
1130 buffer_spec[i].y_addr = addr;
1131 addr += mb_total << 8;
1132 buffer_spec[i].u_canvas_index =
1133 2 * (i - 21) + 5;
1134 buffer_spec[i].v_canvas_index =
1135 2 * (i - 21) + 5;
1136 buffer_spec[i].u_addr = addr;
1137 addr += mb_total << 7;
1138 vfbuf_use[i] = 0;
1139
1140 buffer_spec[i].y_canvas_width = mb_width << 4;
1141 buffer_spec[i].y_canvas_height = mb_height << 4;
1142 buffer_spec[i].u_canvas_width = mb_width << 4;
1143 buffer_spec[i].u_canvas_height = mb_height << 4;
1144 buffer_spec[i].v_canvas_width = mb_width << 4;
1145 buffer_spec[i].v_canvas_height = mb_height << 4;
1146
1147 spec_set_canvas(&buffer_spec[i]
1148 , mb_width << 4, mb_height << 4);
1149 WRITE_VREG(ANC0_CANVAS_ADDR + i
1150 , spec2canvas(&buffer_spec[i]));
1151 }
1152 }
1153 } else {
1154 fatal_error_flag =
1155 DECODER_FATAL_ERROR_NO_MEM;
1156 vh264_running = 0;
1157 mutex_unlock(&vh264_mutex);
1158 pr_err("never be here!!\n");
1159 return;
1160 }
1161
1162 timing_info_present_flag = seq_info & 0x2;
1163 fixed_frame_rate_flag = 0;
1164 aspect_ratio_info_present_flag = seq_info & 0x1;
1165 aspect_ratio_idc = (seq_info >> 16) & 0xff;
1166
1167 if (timing_info_present_flag) {
1168 fixed_frame_rate_flag = seq_info & 0x40;
1169
1170 if (((num_units_in_tick * 120) >= time_scale
1171 && ((!sync_outside) || (!frame_dur))) &&
1172 num_units_in_tick
1173 && time_scale) {
1174 if (use_idr_framerate || !frame_dur
1175 || !duration_from_pts_done || vh264_running) {
1176 u32 frame_dur_es =
1177 div_u64(96000ULL * 2 *
1178 num_units_in_tick,
1179 time_scale);
1180
1181 /* hack to avoid use ES frame duration
1182 * when it's half of the rate from
1183 * system info
1184 */
1185 /* sometimes the encoder is given a wrong
1186 * frame rate but the system side information
1187 *is more reliable
1188 */
1189 if ((frame_dur * 2) != frame_dur_es) {
1190 frame_dur = frame_dur_es;
1191 if (fr_hint_status == VDEC_NEED_HINT) {
1192 schedule_work(&notify_work);
1193 fr_hint_status = VDEC_HINTED;
1194 }
1195 }
1196 }
1197 }
1198 } else
1199 pr_info("H.264: timing_info not present\n");
1200
1201 if (aspect_ratio_info_present_flag) {
1202 if (aspect_ratio_idc == EXTEND_SAR) {
1203 h264_ar =
1204 div_u64(256ULL * (aspect_ratio_info >> 16) *
1205 frame_height,
1206 (aspect_ratio_info & 0xffff) *
1207 frame_width);
1208 } else {
1209 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
1210 * aspect_ratio_idc);
1211 */
1212
1213 switch (aspect_ratio_idc) {
1214 case 1:
1215 h264_ar = 0x100 * frame_height / frame_width;
1216 break;
1217 case 2:
1218 h264_ar = 0x100 * frame_height * 11 /
1219 (frame_width * 12);
1220 break;
1221 case 3:
1222 h264_ar = 0x100 * frame_height * 11 /
1223 (frame_width * 10);
1224 break;
1225 case 4:
1226 h264_ar = 0x100 * frame_height * 11 /
1227 (frame_width * 16);
1228 break;
1229 case 5:
1230 h264_ar = 0x100 * frame_height * 33 /
1231 (frame_width * 40);
1232 break;
1233 case 6:
1234 h264_ar = 0x100 * frame_height * 11 /
1235 (frame_width * 24);
1236 break;
1237 case 7:
1238 h264_ar = 0x100 * frame_height * 11 /
1239 (frame_width * 20);
1240 break;
1241 case 8:
1242 h264_ar = 0x100 * frame_height * 11 /
1243 (frame_width * 32);
1244 break;
1245 case 9:
1246 h264_ar = 0x100 * frame_height * 33 /
1247 (frame_width * 80);
1248 break;
1249 case 10:
1250 h264_ar = 0x100 * frame_height * 11 /
1251 (frame_width * 18);
1252 break;
1253 case 11:
1254 h264_ar = 0x100 * frame_height * 11 /
1255 (frame_width * 15);
1256 break;
1257 case 12:
1258 h264_ar = 0x100 * frame_height * 33 /
1259 (frame_width * 64);
1260 break;
1261 case 13:
1262 h264_ar = 0x100 * frame_height * 99 /
1263 (frame_width * 160);
1264 break;
1265 case 14:
1266 h264_ar = 0x100 * frame_height * 3 /
1267 (frame_width * 4);
1268 break;
1269 case 15:
1270 h264_ar = 0x100 * frame_height * 2 /
1271 (frame_width * 3);
1272 break;
1273 case 16:
1274 h264_ar = 0x100 * frame_height * 1 /
1275 (frame_width * 2);
1276 break;
1277 default:
1278 if (vh264_ratio >> 16) {
1279 h264_ar = (frame_height *
1280 (vh264_ratio & 0xffff) *
1281 0x100 +
1282 ((vh264_ratio >> 16) *
1283 frame_width / 2)) /
1284 ((vh264_ratio >> 16) *
1285 frame_width);
1286 } else {
1287 h264_ar = frame_height * 0x100 /
1288 frame_width;
1289 }
1290 break;
1291 }
1292 }
1293 } else {
1294 pr_info("v264dec: aspect_ratio not available from source\n");
1295 if (vh264_ratio >> 16) {
1296 /* high 16 bit is width, low 16 bit is height */
1297 h264_ar =
1298 ((vh264_ratio & 0xffff) * frame_height * 0x100 +
1299 (vh264_ratio >> 16) * frame_width / 2) /
1300 ((vh264_ratio >> 16) * frame_width);
1301 } else
1302 h264_ar = frame_height * 0x100 / frame_width;
1303 }
1304
1305 WRITE_VREG(AV_SCRATCH_0,
1306 (max_reference_size << 24) | (actual_dpb_size << 16) |
1307 (max_dpb_size << 8));
1308 if (vh264_stream_switching_state != SWITCHING_STATE_OFF) {
1309 vh264_stream_switching_state = SWITCHING_STATE_OFF;
1310 pr_info("Leaving switching mode.\n");
1311 }
1312 mutex_unlock(&vh264_mutex);
1313}
1314
1315static unsigned int pts_inc_by_duration(
1316 unsigned int *new_pts, unsigned int *new_pts_rem)
1317{
1318 unsigned int r, rem;
1319
1320 r = last_pts + DUR2PTS(frame_dur);
1321 rem = last_pts_remainder + DUR2PTS_REM(frame_dur);
1322
1323 if (rem >= 96) {
1324 r++;
1325 rem -= 96;
1326 }
1327
1328 if (new_pts)
1329 *new_pts = r;
1330 if (new_pts_rem)
1331 *new_pts_rem = rem;
1332
1333 return r;
1334}
1335static inline bool vh264_isr_parser(struct vframe_s *vf,
1336 unsigned int pts_valid, unsigned int buffer_index,
1337 unsigned int pts)
1338{
1339 unsigned int pts_duration = 0;
1340
1341 if (h264_first_pts_ready == 0) {
1342 if (pts_valid == 0) {
1343 vfbuf_use[buffer_index]++;
1344 vf->index = buffer_index;
1345 kfifo_put(&recycle_q,
1346 (const struct vframe_s *)vf);
1347 return false;
1348 }
1349
1350 h264pts1 = pts;
1351 h264_pts_count = 0;
1352 h264_first_pts_ready = 1;
1353 } else {
1354 if (pts < h264pts1) {
1355 if (h264_pts_count > 24) {
1356 pr_info("invalid h264pts1, reset\n");
1357 h264pts1 = pts;
1358 h264_pts_count = 0;
1359 }
1360 }
1361 if (pts_valid && (pts > h264pts1) && (h264_pts_count > 24)
1362 && (duration_from_pts_done == 0)) {
1363 unsigned int
1364 old_duration = frame_dur;
1365 h264pts2 = pts;
1366
1367 pts_duration = (h264pts2 - h264pts1) * 16 /
1368 (h264_pts_count * 15);
1369
1370 if ((pts_duration != frame_dur)
1371 && (!pts_outside)) {
1372 if (use_idr_framerate) {
1373 bool pts_c_24 = close_to(pts_duration,
1374 RATE_24_FPS,
1375 RATE_CORRECTION_THRESHOLD);
1376 bool frm_c_25 = close_to(frame_dur,
1377 RATE_25_FPS,
1378 RATE_CORRECTION_THRESHOLD);
1379 bool pts_c_25 = close_to(pts_duration,
1380 RATE_25_FPS,
1381 RATE_CORRECTION_THRESHOLD);
1382 bool frm_c_24 = close_to(frame_dur,
1383 RATE_24_FPS,
1384 RATE_CORRECTION_THRESHOLD);
1385 if ((pts_c_24 && frm_c_25)
1386 || (pts_c_25 && frm_c_24)) {
1387 pr_info
1388 ("H.264:Correct frame dur ");
1389 pr_info
1390 (" from %d to duration based ",
1391 frame_dur);
1392 pr_info
1393 ("on PTS %d ---\n",
1394 pts_duration);
1395 frame_dur = pts_duration;
1396 duration_from_pts_done = 1;
1397 } else if (((frame_dur < 96000 / 240)
1398 && (pts_duration > 96000 / 240))
1399 || (!duration_on_correcting &&
1400 !frm_c_25 && !frm_c_24)) {
1401 /* fft: if the frame rate is
1402 * not regular, use the
1403 * calculate rate insteadof.
1404 */
1405 pr_info
1406 ("H.264:Correct frame dur ");
1407 pr_info
1408 (" from %d to duration based ",
1409 frame_dur);
1410 pr_info
1411 ("on PTS %d ---\n",
1412 pts_duration);
1413 frame_dur = pts_duration;
1414 duration_on_correcting = 1;
1415 }
1416 } else {
1417 if (close_to(pts_duration,
1418 frame_dur, 2000)) {
1419 frame_dur = pts_duration;
1420 pr_info
1421 ("used calculate frame rate,");
1422 pr_info("on duration =%d\n",
1423 frame_dur);
1424 } else {
1425 pr_info
1426 ("don't use calculate frame ");
1427 pr_info
1428 ("rate pts_duration =%d\n",
1429 pts_duration);
1430 }
1431 }
1432 }
1433
1434 if (duration_from_pts_done == 0) {
1435 if (close_to
1436 (pts_duration,
1437 old_duration,
1438 RATE_CORRECTION_THRESHOLD)) {
1439 pr_info
1440 ("finished correct frame dur");
1441 pr_info
1442 (" new=%d,old_duration=%d,cnt=%d\n",
1443 pts_duration,
1444 old_duration,
1445 h264_pts_count);
1446 duration_from_pts_done = 1;
1447 } else { /*not the same,redo it. */
1448 if (!close_to(pts_duration,
1449 old_duration, 1000) &&
1450 !close_to(pts_duration,
1451 frame_dur, 1000) &&
1452 close_to(pts_duration,
1453 last_duration, 200)) {
1454 /* yangle: frame_dur must
1455 * wrong,recover it.
1456 */
1457 frame_dur = pts_duration;
1458 }
1459
1460 pr_info
1461 ("restart correct frame duration ");
1462 pr_info
1463 ("new=%d,old_duration=%d,cnt=%d\n",
1464 pts_duration,
1465 old_duration,
1466 h264_pts_count);
1467 h264pts1 = h264pts2;
1468 h264_pts_count = 0;
1469 duration_from_pts_done = 0;
1470 }
1471 }
1472 last_duration = pts_duration;
1473 }
1474 }
1475 return true;
1476}
1477#ifdef HANDLE_H264_IRQ
1478static irqreturn_t vh264_isr(int irq, void *dev_id)
1479#else
1480static void vh264_isr(void)
1481#endif
1482{
1483 unsigned int buffer_index;
1484 struct vframe_s *vf;
1485 unsigned int cpu_cmd;
1486 unsigned int pts, pts_lookup_save, pts_valid_save, pts_valid = 0;
1487 unsigned int pts_us64_valid = 0;
1488 u64 pts_us64;
1489 bool force_interlaced_frame = false;
1490 unsigned int sei_itu35_flags;
1491 static const unsigned int idr_num =
1492 FIX_FRAME_RATE_CHECK_IDRFRAME_NUM;
1493 static const unsigned int flg_1080_itl =
1494 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE;
1495 static const unsigned int flg_576_itl =
1496 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
1497
1498 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1499
1500 if (0 == (stat & STAT_VDEC_RUN)) {
1501 pr_info("decoder is not running\n");
1502#ifdef HANDLE_H264_IRQ
1503 return IRQ_HANDLED;
1504#else
1505 return;
1506#endif
1507 }
1508
1509 cpu_cmd = READ_VREG(AV_SCRATCH_0);
1510
1511#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
1512 if ((frame_dur < 2004) &&
1513 (frame_width >= 1400) &&
1514 (frame_height >= 1000) && (last_interlaced == 0))
1515 SET_VREG_MASK(AV_SCRATCH_F, 0x8);
1516#endif
1517 if ((decoder_force_reset == 1)
1518 || ((error_recovery_mode != 1)
1519 && (no_idr_error_count >= no_idr_error_max)
1520 && (ucode_type != UCODE_IP_ONLY_PARAM))) {
1521 vh264_running = 0;
1522 pr_info("force reset decoder %d!!!\n", no_idr_error_count);
1523 schedule_work(&error_wd_work);
1524 decoder_force_reset = 0;
1525 no_idr_error_count = 0;
1526 } else if ((cpu_cmd & 0xff) == 1) {
1527 if (unlikely
1528 (vh264_running
1529 && (kfifo_len(&newframe_q) != VF_POOL_SIZE))) {
1530 /* a cmd 1 sent during decoding w/o getting a cmd 3. */
1531 /* should not happen but the original code has such
1532 * case, do the same process
1533 */
1534 if ((READ_VREG(AV_SCRATCH_1) & 0xff)
1535 == 1) {/*invalid mb_width*/
1536 vh264_running = 0;
1537 fatal_error_flag = DECODER_FATAL_ERROR_UNKNOWN;
1538 /* this is fatal error, need restart */
1539 pr_info("cmd 1 fatal error happened\n");
1540 schedule_work(&error_wd_work);
1541 } else {
1542 vh264_stream_switching_state = SWITCHING_STATE_ON_CMD1;
1543 pr_info("Enter switching mode cmd1.\n");
1544 schedule_work(&stream_switching_work);
1545 }
1546 return IRQ_HANDLED;
1547 }
1548 pr_info("Enter set parameter cmd1.\n");
1549 schedule_work(&set_parameter_work);
1550 return IRQ_HANDLED;
1551 } else if ((cpu_cmd & 0xff) == 2) {
1552 int frame_mb_only, pic_struct_present, pic_struct, prog_frame,
1553 poc_sel, idr_flag, eos, error;
1554 int i, status, num_frame, b_offset;
1555 int current_error_count, slice_type;
1556
1557 vh264_running = 1;
1558 vh264_no_disp_count = 0;
1559 num_frame = (cpu_cmd >> 8) & 0xff;
1560 frame_mb_only = seq_info & 0x8000;
1561 pic_struct_present = seq_info & 0x10;
1562
1563 current_error_count = READ_VREG(AV_SCRATCH_D);
1564 if (vh264_error_count != current_error_count) {
1565 /* pr_info("decoder error happened, count %d\n",
1566 * current_error_count);
1567 */
1568 vh264_error_count = current_error_count;
1569 }
1570
1571 for (i = 0; (i < num_frame) && (!vh264_eos); i++) {
1572 status = READ_VREG(AV_SCRATCH_1 + i);
1573 buffer_index = status & 0x1f;
1574 error = status & 0x200;
1575 slice_type = (READ_VREG(AV_SCRATCH_H) >> (i * 4)) & 0xf;
1576
1577 if ((error_recovery_mode_use & 2) && error)
1578 check_pts_discontinue = true;
1579 if (ucode_type == UCODE_IP_ONLY_PARAM
1580 && iponly_early_mode)
1581 continue;
1582 if ((p_last_vf != NULL)
1583 && (p_last_vf->index == buffer_index))
1584 continue;
1585
1586 if (buffer_index >= VF_BUF_NUM)
1587 continue;
1588
1589 pic_struct = (status >> 5) & 0x7;
1590 prog_frame = status & 0x100;
1591 poc_sel = status & 0x200;
1592 idr_flag = status & 0x400;
1593 frame_packing_type = (status >> 12) & 0x7;
1594 eos = (status >> 15) & 1;
1595
1596 if (eos)
1597 vh264_eos = 1;
1598
1599 b_offset = (status >> 16) & 0xffff;
1600
1601 if (error)
1602 no_idr_error_count++;
1603 if (idr_flag ||
1604 (!error && (slice_type != SLICE_TYPE_I)))
1605 no_idr_error_count = 0;
1606
1607 if (decoder_debug_flag) {
1608 pr_info
1609 ("slice_type %x idr %x error %x count %d",
1610 slice_type, idr_flag, error,
1611 no_idr_error_count);
1612 pr_info(" prog %x pic_struct %x offset %x\n",
1613 prog_frame, pic_struct, b_offset);
1614 }
1615#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
1616 last_interlaced = prog_frame ? 0 : 1;
1617#endif
1618 if (kfifo_get(&newframe_q, &vf) == 0) {
1619 pr_info
1620 ("fatal error, no available buffer slot.");
1621 return IRQ_HANDLED;
1622 }
1623
1624 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME)
1625 clk_adj_frame_count++;
1626
1627 set_frame_info(vf);
1628
1629 switch (i) {
1630 case 0:
1631 b_offset |=
1632 (READ_VREG(AV_SCRATCH_A) & 0xffff)
1633 << 16;
1634 break;
1635 case 1:
1636 b_offset |=
1637 READ_VREG(AV_SCRATCH_A) & 0xffff0000;
1638 break;
1639 case 2:
1640 b_offset |=
1641 (READ_VREG(AV_SCRATCH_B) & 0xffff)
1642 << 16;
1643 break;
1644 case 3:
1645 b_offset |=
1646 READ_VREG(AV_SCRATCH_B) & 0xffff0000;
1647 break;
1648 case 4:
1649 b_offset |=
1650 (READ_VREG(AV_SCRATCH_C) & 0xffff)
1651 << 16;
1652 break;
1653 case 5:
1654 b_offset |=
1655 READ_VREG(AV_SCRATCH_C) & 0xffff0000;
1656 break;
1657 default:
1658 break;
1659 }
1660
1661 if (error)
1662 gvs->drop_frame_count++;
1663
1664 /* add 64bit pts us ; */
1665 if (unlikely
1666 ((b_offset == first_offset)
1667 && (first_pts_cached))) {
1668 pts = first_pts;
1669 pts_us64 = first_pts64;
1670 first_pts_cached = false;
1671 pts_valid = 1;
1672 pts_us64_valid = 1;
1673#ifdef DEBUG_PTS
1674 pts_hit++;
1675#endif
1676 } else if (pts_lookup_offset_us64
1677 (PTS_TYPE_VIDEO, b_offset, &pts, 0,
1678 &pts_us64) == 0) {
1679 pts_valid = 1;
1680 pts_us64_valid = 1;
1681#ifdef DEBUG_PTS
1682 pts_hit++;
1683#endif
1684 } else {
1685 pts_valid = 0;
1686 pts_us64_valid = 0;
1687#ifdef DEBUG_PTS
1688 pts_missed++;
1689#endif
1690 }
1691
1692 /* on second IDR frame,check the diff between pts
1693 * compute from duration and pts from lookup ,
1694 * if large than frame_dur,we think it is uncorrect.
1695 */
1696 pts_lookup_save = pts;
1697 pts_valid_save = pts_valid;
1698 if (fixed_frame_rate_flag
1699 && (fixed_frame_rate_check_count <=
1700 idr_num)) {
1701 if (idr_flag && pts_valid) {
1702 fixed_frame_rate_check_count++;
1703 /* pr_info("diff:%d\n",
1704 * last_pts - pts_lookup_save);
1705 */
1706 if ((fixed_frame_rate_check_count ==
1707 idr_num) &&
1708 (abs(pts - (last_pts +
1709 DUR2PTS(frame_dur))) >
1710 DUR2PTS(frame_dur))) {
1711 fixed_frame_rate_flag = 0;
1712 pr_info("pts sync mode play\n");
1713 }
1714
1715 if (fixed_frame_rate_flag
1716 && (fixed_frame_rate_check_count
1717 > idr_num)) {
1718 pr_info
1719 ("fix_frame_rate mode play\n");
1720 }
1721 }
1722 }
1723
1724 if (READ_VREG(AV_SCRATCH_F) & 2) {
1725 /* for I only mode, ignore the PTS information
1726 * and only uses frame duration for each I
1727 * frame decoded
1728 */
1729 if (p_last_vf)
1730 pts_valid = 0;
1731 /* also skip frame duration calculation
1732 * based on PTS
1733 */
1734 duration_from_pts_done = 1;
1735 /* and add a default duration for 1/30 second
1736 * if there is no valid frame
1737 * duration available
1738 */
1739 if (frame_dur == 0)
1740 frame_dur = 96000 / 30;
1741 }
1742
1743 if (sync_outside == 0) {
1744 if (!vh264_isr_parser(vf,
1745 pts_valid, buffer_index, pts))
1746 continue;
1747
1748 h264_pts_count++;
1749 } else {
1750 if (!idr_flag)
1751 pts_valid = 0;
1752 }
1753
1754 if (pts_valid && !pts_discontinue) {
1755 pts_discontinue =
1756 (abs(last_pts - pts) >=
1757 tsync_vpts_discontinuity_margin());
1758 }
1759 /* if use_idr_framerate or fixed frame rate, only
1760 * use PTS for IDR frames except for pts discontinue
1761 */
1762 if (timing_info_present_flag &&
1763 frame_dur &&
1764 (use_idr_framerate ||
1765 (fixed_frame_rate_flag != 0))
1766 && pts_valid && h264_first_valid_pts_ready
1767 && (!pts_discontinue)) {
1768 pts_valid =
1769 (slice_type == SLICE_TYPE_I) ? 1 : 0;
1770 }
1771
1772 if (!h264_first_valid_pts_ready && pts_valid) {
1773 h264_first_valid_pts_ready = true;
1774 last_pts = pts - DUR2PTS(frame_dur);
1775 last_pts_remainder = 0;
1776 }
1777 /* calculate PTS of next frame and smooth
1778 * PTS for fixed rate source
1779 */
1780 if (pts_valid) {
1781 if ((fixed_frame_rate_flag) &&
1782 (!pts_discontinue) &&
1783 (abs(pts_inc_by_duration(NULL, NULL)
1784 - pts)
1785 < DUR2PTS(frame_dur))) {
1786 pts = pts_inc_by_duration(&pts,
1787 &last_pts_remainder);
1788 } else
1789 last_pts_remainder = 0;
1790
1791 } else {
1792 if (fixed_frame_rate_flag && !pts_discontinue &&
1793 (fixed_frame_rate_check_count > idr_num) &&
1794 pts_valid_save && (sync_outside == 0) &&
1795 (abs(pts_inc_by_duration(NULL, NULL) - pts)
1796 > DUR2PTS(frame_dur))) {
1797 duration_from_pts_done = 0;
1798 pr_info("recalc frame_dur\n");
1799 } else
1800 pts = pts_inc_by_duration(&pts,
1801 &last_pts_remainder);
1802 pts_valid = 1;
1803 }
1804
1805 if ((dec_control &
1806 flg_1080_itl)
1807 && (frame_width == 1920)
1808 && (frame_height >= 1080)
1809 && (vf->duration == 3203))
1810 force_interlaced_frame = true;
1811 else if ((dec_control &
1812 flg_576_itl)
1813 && (frame_width == 720)
1814 && (frame_height == 576)
1815 && (vf->duration == 3840))
1816 force_interlaced_frame = true;
1817
1818 /* for frames with PTS, check if there is PTS
1819 * discontinue based on previous frames
1820 * (including error frames),
1821 * force no VPTS discontinue reporting if we saw
1822 *errors earlier but only once.
1823 */
1824
1825 /*count info*/
1826 gvs->frame_dur = frame_dur;
1827 vdec_count_info(gvs, error, b_offset);
1828
1829 if ((pts_valid) && (check_pts_discontinue)
1830 && (!error)) {
1831 if (pts_discontinue) {
1832 vf->flag = 0;
1833 check_pts_discontinue = false;
1834 } else if ((pts - last_pts) < 90000) {
1835 vf->flag = VFRAME_FLAG_NO_DISCONTINUE;
1836 check_pts_discontinue = false;
1837 }
1838 }
1839
1840 last_pts = pts;
1841
1842 if (fixed_frame_rate_flag
1843 && (fixed_frame_rate_check_count <=
1844 idr_num)
1845 && (sync_outside == 0)
1846 && pts_valid_save)
1847 pts = pts_lookup_save;
1848
1849 if (pic_struct_present) {
1850 if ((pic_struct == PIC_TOP_BOT)
1851 || (pic_struct == PIC_BOT_TOP))
1852 prog_frame = 0;
1853 }
1854
1855 if ((!force_interlaced_frame)
1856 && (prog_frame
1857 || (pic_struct_present
1858 && pic_struct
1859 <= PIC_TRIPLE_FRAME))) {
1860 if (pic_struct_present) {
1861 if (pic_struct == PIC_TOP_BOT_TOP
1862 || pic_struct
1863 == PIC_BOT_TOP_BOT) {
1864 vf->duration +=
1865 vf->duration >> 1;
1866 } else if (pic_struct ==
1867 PIC_DOUBLE_FRAME)
1868 vf->duration += vf->duration;
1869 else if (pic_struct ==
1870 PIC_TRIPLE_FRAME) {
1871 vf->duration +=
1872 vf->duration << 1;
1873 }
1874 }
1875
1876 last_pts =
1877 last_pts + DUR2PTS(vf->duration -
1878 frame_dur);
1879
1880 vf->index = buffer_index;
1881 vf->type =
1882 VIDTYPE_PROGRESSIVE |
1883 VIDTYPE_VIU_FIELD |
1884 VIDTYPE_VIU_NV21;
1885 vf->duration_pulldown = 0;
1886 vf->signal_type = video_signal_from_vui;
1887 vf->index = buffer_index;
1888 vf->pts = (pts_valid) ? pts : 0;
1889 if (pts_us64_valid == 1)
1890 vf->pts_us64 = pts_us64;
1891 else
1892 vf->pts_us64 = div64_u64(((u64)vf->pts)*100, 9);
1893 vf->canvas0Addr = vf->canvas1Addr =
1894 spec2canvas(&buffer_spec[buffer_index]);
1895 vf->type_original = vf->type;
1896 vfbuf_use[buffer_index]++;
1897 vf->mem_handle =
1898 decoder_bmmu_box_get_mem_handle(
1899 mm_blk_handle,
1900 VF_BUFFER_IDX(buffer_index));
1901 if ((error_recovery_mode_use & 2) && error) {
1902 kfifo_put(&recycle_q,
1903 (const struct vframe_s *)vf);
1904 } else {
1905 p_last_vf = vf;
1906 pts_discontinue = false;
1907 kfifo_put(&delay_display_q,
1908 (const struct vframe_s *)vf);
1909 }
1910 } else {
1911 if (pic_struct_present
1912 && pic_struct == PIC_TOP_BOT)
1913 vf->type = VIDTYPE_INTERLACE_TOP;
1914 else if (pic_struct_present
1915 && pic_struct == PIC_BOT_TOP)
1916 vf->type = VIDTYPE_INTERLACE_BOTTOM;
1917 else {
1918 vf->type =
1919 poc_sel ?
1920 VIDTYPE_INTERLACE_BOTTOM :
1921 VIDTYPE_INTERLACE_TOP;
1922 }
1923 vf->type |= VIDTYPE_VIU_NV21;
1924 vf->type |= VIDTYPE_INTERLACE_FIRST;
1925
1926 high_bandwidth |=
1927 ((codec_mm_get_total_size() < 80 * SZ_1M)
1928 & ((READ_VREG(AV_SCRATCH_N) & 0xf) == 3)
1929 & ((frame_width * frame_height) >= 1920*1080));
1930 if (high_bandwidth)
1931 vf->flag |= VFRAME_FLAG_HIGH_BANDWIDTH;
1932
1933 vf->duration >>= 1;
1934 vf->duration_pulldown = 0;
1935 vf->signal_type = video_signal_from_vui;
1936 vf->index = buffer_index;
1937 vf->pts = (pts_valid) ? pts : 0;
1938 if (pts_us64_valid == 1)
1939 vf->pts_us64 = pts_us64;
1940 else
1941 vf->pts_us64 = div64_u64(((u64)vf->pts)*100, 9);
1942 vf->canvas0Addr = vf->canvas1Addr =
1943 spec2canvas(&buffer_spec[buffer_index]);
1944 vf->type_original = vf->type;
1945 vfbuf_use[buffer_index]++;
1946 vf->ready_jiffies64 = jiffies_64;
1947 vf->mem_handle =
1948 decoder_bmmu_box_get_mem_handle(
1949 mm_blk_handle,
1950 VF_BUFFER_IDX(buffer_index));
1951 if ((error_recovery_mode_use & 2) && error) {
1952 kfifo_put(&recycle_q,
1953 (const struct vframe_s *)vf);
1954 continue;
1955 } else {
1956 pts_discontinue = false;
1957 kfifo_put(&delay_display_q,
1958 (const struct vframe_s *)vf);
1959 }
1960
1961 if (READ_VREG(AV_SCRATCH_F) & 2)
1962 continue;
1963
1964 if (kfifo_get(&newframe_q, &vf) == 0) {
1965 pr_info
1966 ("fatal error, no avail buffer slot.");
1967 return IRQ_HANDLED;
1968 }
1969
1970 set_frame_info(vf);
1971
1972 if (pic_struct_present
1973 && pic_struct == PIC_TOP_BOT)
1974 vf->type = VIDTYPE_INTERLACE_BOTTOM;
1975 else if (pic_struct_present
1976 && pic_struct == PIC_BOT_TOP)
1977 vf->type = VIDTYPE_INTERLACE_TOP;
1978 else {
1979 vf->type =
1980 poc_sel ?
1981 VIDTYPE_INTERLACE_TOP :
1982 VIDTYPE_INTERLACE_BOTTOM;
1983 }
1984
1985 vf->type |= VIDTYPE_VIU_NV21;
1986 vf->duration >>= 1;
1987 vf->duration_pulldown = 0;
1988 vf->signal_type = video_signal_from_vui;
1989 vf->index = buffer_index;
1990 vf->pts = 0;
1991 vf->pts_us64 = 0;
1992 vf->canvas0Addr = vf->canvas1Addr =
1993 spec2canvas(&buffer_spec[buffer_index]);
1994 vf->type_original = vf->type;
1995 vfbuf_use[buffer_index]++;
1996 if (high_bandwidth)
1997 vf->flag |= VFRAME_FLAG_HIGH_BANDWIDTH;
1998
1999 p_last_vf = vf;
2000 vf->ready_jiffies64 = jiffies_64;
2001 vf->mem_handle =
2002 decoder_bmmu_box_get_mem_handle(
2003 mm_blk_handle,
2004 VF_BUFFER_IDX(buffer_index));
2005 kfifo_put(&delay_display_q,
2006 (const struct vframe_s *)vf);
2007 }
2008 }
2009
2010 WRITE_VREG(AV_SCRATCH_0, 0);
2011 } else if ((cpu_cmd & 0xff) == 3) {
2012 vh264_running = 1;
2013 vh264_stream_switching_state = SWITCHING_STATE_ON_CMD3;
2014
2015 pr_info("Enter switching mode cmd3.\n");
2016 schedule_work(&stream_switching_work);
2017
2018 } else if ((cpu_cmd & 0xff) == 4) {
2019 vh264_running = 1;
2020 /* reserved for slice group */
2021 WRITE_VREG(AV_SCRATCH_0, 0);
2022 } else if ((cpu_cmd & 0xff) == 5) {
2023 vh264_running = 1;
2024 /* reserved for slice group */
2025 WRITE_VREG(AV_SCRATCH_0, 0);
2026 } else if ((cpu_cmd & 0xff) == 6) {
2027 vh264_running = 0;
2028 fatal_error_flag = DECODER_FATAL_ERROR_UNKNOWN;
2029 /* this is fatal error, need restart */
2030 pr_info("fatal error happend\n");
2031 amvdec_stop();
2032 if (!fatal_error_reset)
2033 schedule_work(&error_wd_work);
2034 } else if ((cpu_cmd & 0xff) == 7) {
2035 vh264_running = 0;
2036 frame_width = (READ_VREG(AV_SCRATCH_1) + 1) * 16;
2037 pr_info("Over decoder supported size, width = %d\n",
2038 frame_width);
2039 fatal_error_flag = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
2040 } else if ((cpu_cmd & 0xff) == 8) {
2041 vh264_running = 0;
2042 frame_height = (READ_VREG(AV_SCRATCH_1) + 1) * 16;
2043 pr_info("Over decoder supported size, height = %d\n",
2044 frame_height);
2045 fatal_error_flag = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
2046 } else if ((cpu_cmd & 0xff) == 9) {
2047 first_offset = READ_VREG(AV_SCRATCH_1);
2048 if (pts_lookup_offset_us64
2049 (PTS_TYPE_VIDEO, first_offset, &first_pts, 0,
2050 &first_pts64) == 0)
2051 first_pts_cached = true;
2052 WRITE_VREG(AV_SCRATCH_0, 0);
2053 } else if ((cpu_cmd & 0xff) == 0xa) {
2054 int b_offset;
2055
2056 b_offset = READ_VREG(AV_SCRATCH_2);
2057 buffer_index = READ_VREG(AV_SCRATCH_1);
2058 /*pr_info("iponly output %d b_offset %x\n",
2059 * buffer_index,b_offset);
2060 */
2061 if (kfifo_get(&newframe_q, &vf) == 0) {
2062 WRITE_VREG(AV_SCRATCH_0, 0);
2063 pr_info
2064 ("fatal error, no available buffer slot.");
2065 return IRQ_HANDLED;
2066 }
2067 if (pts_lookup_offset_us64 (PTS_TYPE_VIDEO, b_offset,
2068 &pts, 0, &pts_us64) != 0)
2069 vf->pts_us64 = vf->pts = 0;
2070 else {
2071 vf->pts_us64 = pts_us64;
2072 vf->pts = pts;
2073 }
2074 set_frame_info(vf);
2075 vf->type = VIDTYPE_PROGRESSIVE |
2076 VIDTYPE_VIU_FIELD |
2077 VIDTYPE_VIU_NV21;
2078 vf->duration_pulldown = 0;
2079 vf->signal_type = video_signal_from_vui;
2080 vf->index = buffer_index;
2081 vf->canvas0Addr = vf->canvas1Addr =
2082 spec2canvas(&buffer_spec[buffer_index]);
2083 vf->type_original = vf->type;
2084 vf->mem_handle = decoder_bmmu_box_get_mem_handle(
2085 mm_blk_handle,
2086 VF_BUFFER_IDX(buffer_index));
2087 vfbuf_use[buffer_index]++;
2088 p_last_vf = vf;
2089 pts_discontinue = false;
2090 iponly_early_mode = 1;
2091 kfifo_put(&delay_display_q,
2092 (const struct vframe_s *)vf);
2093 WRITE_VREG(AV_SCRATCH_0, 0);
2094 }
2095
2096 sei_itu35_flags = READ_VREG(AV_SCRATCH_J);
2097 if (sei_itu35_flags & (1 << 15)) { /* data ready */
2098 schedule_work(&userdata_push_work);
2099 }
2100#ifdef HANDLE_H264_IRQ
2101 return IRQ_HANDLED;
2102#else
2103 return;
2104#endif
2105}
2106
2107static void vh264_put_timer_func(unsigned long arg)
2108{
2109 struct timer_list *timer = (struct timer_list *)arg;
2110 unsigned int wait_buffer_status;
2111 unsigned int wait_i_pass_frames;
2112 unsigned int reg_val;
2113
2114 enum receviver_start_e state = RECEIVER_INACTIVE;
2115
2116 if (vh264_reset) {
2117 pr_info("operation forbidden in timer !\n");
2118 goto exit;
2119 }
2120
2121 prepare_display_q();
2122
2123 if (vf_get_receiver(PROVIDER_NAME)) {
2124 state =
2125 vf_notify_receiver(PROVIDER_NAME,
2126 VFRAME_EVENT_PROVIDER_QUREY_STATE,
2127 NULL);
2128 if ((state == RECEIVER_STATE_NULL)
2129 || (state == RECEIVER_STATE_NONE)) {
2130 /* receiver has no event_cb or receiver's
2131 * event_cb does not process this event
2132 */
2133 state = RECEIVER_INACTIVE;
2134 }
2135 } else
2136 state = RECEIVER_INACTIVE;
2137#ifndef HANDLE_H264_IRQ
2138 vh264_isr();
2139#endif
2140
2141 if (vh264_stream_switching_state != SWITCHING_STATE_OFF)
2142 wait_buffer_counter = 0;
2143 else {
2144 reg_val = READ_VREG(AV_SCRATCH_9);
2145 wait_buffer_status = reg_val & (1 << 31);
2146 wait_i_pass_frames = reg_val & 0xff;
2147 if (wait_buffer_status) {
2148 if (kfifo_is_empty(&display_q) &&
2149 kfifo_is_empty(&delay_display_q) &&
2150 kfifo_is_empty(&recycle_q) &&
2151 (state == RECEIVER_INACTIVE)) {
2152 pr_info("$$$$decoder is waiting for buffer\n");
2153 if (++wait_buffer_counter > 4) {
2154 amvdec_stop();
2155 schedule_work(&error_wd_work);
2156 }
2157 } else
2158 wait_buffer_counter = 0;
2159 } else if (wait_i_pass_frames > 1000) {
2160 pr_info("i passed frames > 1000\n");
2161 amvdec_stop();
2162 schedule_work(&error_wd_work);
2163 }
2164 }
2165
2166#if 0
2167 if (!wait_buffer_status) {
2168 if (vh264_no_disp_count++ > NO_DISP_WD_COUNT) {
2169 pr_info("$$$decoder did not send frame out\n");
2170 amvdec_stop();
2171#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2172 vh264_ppmgr_reset();
2173#else
2174 vf_light_unreg_provider(PROVIDER_NAME);
2175 vh264_local_init();
2176 vf_reg_provider(vh264_vf_prov);
2177#endif
2178 vh264_prot_init();
2179 amvdec_start();
2180
2181 vh264_no_disp_count = 0;
2182 vh264_no_disp_wd_count++;
2183 }
2184 }
2185#endif
2186
2187 while (!kfifo_is_empty(&recycle_q) &&
2188 ((READ_VREG(AV_SCRATCH_7) == 0)
2189 || (READ_VREG(AV_SCRATCH_8) == 0))
2190 && (vh264_stream_switching_state == SWITCHING_STATE_OFF)) {
2191 struct vframe_s *vf;
2192
2193 if (kfifo_get(&recycle_q, &vf)) {
2194 if ((vf->index >= 0) && (vf->index < VF_BUF_NUM)) {
2195 if (--vfbuf_use[vf->index] == 0) {
2196 if (READ_VREG(AV_SCRATCH_7) == 0) {
2197 WRITE_VREG(AV_SCRATCH_7,
2198 vf->index + 1);
2199 } else {
2200 WRITE_VREG(AV_SCRATCH_8,
2201 vf->index + 1);
2202 }
2203 }
2204
2205 vf->index = VF_BUF_NUM;
2206 kfifo_put(&newframe_q,
2207 (const struct vframe_s *)vf);
2208 }
2209 }
2210 }
2211
2212 if (vh264_stream_switching_state != SWITCHING_STATE_OFF) {
2213 while (!kfifo_is_empty(&recycle_q)) {
2214 struct vframe_s *vf;
2215
2216 if (kfifo_get(&recycle_q, &vf)) {
2217 if ((vf->index >= 0 &&
2218 (vf->index < VF_BUF_NUM))) {
2219 vf->index = VF_BUF_NUM;
2220 kfifo_put(&newframe_q,
2221 (const struct vframe_s *)vf);
2222 }
2223 }
2224 }
2225
2226 WRITE_VREG(AV_SCRATCH_7, 0);
2227 WRITE_VREG(AV_SCRATCH_8, 0);
2228
2229 if (kfifo_len(&newframe_q) == VF_POOL_SIZE)
2230 stream_switching_done();
2231 }
2232
2233 if (ucode_type != UCODE_IP_ONLY_PARAM &&
2234 (clk_adj_frame_count > VDEC_CLOCK_ADJUST_FRAME) &&
2235 frame_dur > 0 && saved_resolution !=
2236 frame_width * frame_height * (96000 / frame_dur)) {
2237 int fps = 96000 / frame_dur;
2238
2239 if (frame_dur < 10) /*dur is too small ,think it errors fps*/
2240 fps = 60;
2241 saved_resolution = frame_width * frame_height * fps;
2242 vdec_source_changed(VFORMAT_H264,
2243 frame_width, frame_height, fps);
2244 }
2245exit:
2246 timer->expires = jiffies + PUT_INTERVAL;
2247
2248 add_timer(timer);
2249}
2250
2251int vh264_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
2252{
2253 vstatus->frame_width = frame_width;
2254 vstatus->frame_height = frame_height;
2255 if (frame_dur != 0)
2256 vstatus->frame_rate = 96000 / frame_dur;
2257 else
2258 vstatus->frame_rate = -1;
2259 vstatus->error_count = READ_VREG(AV_SCRATCH_D);
2260 vstatus->status = stat;
2261 if (fatal_error_reset)
2262 vstatus->status |= fatal_error_flag;
2263 vstatus->bit_rate = gvs->bit_rate;
2264 vstatus->frame_dur = frame_dur;
2265 vstatus->frame_data = gvs->frame_data;
2266 vstatus->total_data = gvs->total_data;
2267 vstatus->frame_count = gvs->frame_count;
2268 vstatus->error_frame_count = gvs->error_frame_count;
2269 vstatus->drop_frame_count = gvs->drop_frame_count;
2270 vstatus->total_data = gvs->total_data;
2271 vstatus->samp_cnt = gvs->samp_cnt;
2272 vstatus->offset = gvs->offset;
2273 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
2274 "%s", DRIVER_NAME);
2275
2276 return 0;
2277}
2278
2279static int vh264_vdec_info_init(void)
2280{
2281 gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL);
2282 if (NULL == gvs) {
2283 pr_info("the struct of vdec status malloc failed.\n");
2284 return -ENOMEM;
2285 }
2286 return 0;
2287}
2288
2289int vh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
2290{
2291 if (trickmode == TRICKMODE_I) {
2292 WRITE_VREG(AV_SCRATCH_F,
2293 (READ_VREG(AV_SCRATCH_F) & 0xfffffffc) | 2);
2294 trickmode_i = 1;
2295 } else if (trickmode == TRICKMODE_NONE) {
2296 WRITE_VREG(AV_SCRATCH_F, READ_VREG(AV_SCRATCH_F) & 0xfffffffc);
2297 trickmode_i = 0;
2298 }
2299
2300 return 0;
2301}
2302
2303int vh264_set_isreset(struct vdec_s *vdec, int isreset)
2304{
2305 is_reset = isreset;
2306 return 0;
2307}
2308
2309static void vh264_prot_init(void)
2310{
2311
2312 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
2313 ;
2314 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
2315 ; /* reg address is 0x350 */
2316
2317#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
2318 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
2319 WRITE_VREG(DOS_SW_RESET0, 0);
2320
2321 READ_VREG(DOS_SW_RESET0);
2322 READ_VREG(DOS_SW_RESET0);
2323 READ_VREG(DOS_SW_RESET0);
2324
2325 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4));
2326 WRITE_VREG(DOS_SW_RESET0, 0);
2327
2328 WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8));
2329 WRITE_VREG(DOS_SW_RESET0, 0);
2330
2331 READ_VREG(DOS_SW_RESET0);
2332 READ_VREG(DOS_SW_RESET0);
2333 READ_VREG(DOS_SW_RESET0);
2334
2335#else
2336 WRITE_RESET_REG(RESET0_REGISTER,
2337 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
2338 READ_RESET_REG(RESET0_REGISTER);
2339 WRITE_RESET_REG(RESET0_REGISTER,
2340 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
2341
2342 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
2343#endif
2344
2345 WRITE_VREG(POWER_CTL_VLD,
2346 READ_VREG(POWER_CTL_VLD) |
2347 (0 << 10) | (1 << 9) | (1 << 6));
2348
2349 /* disable PSCALE for hardware sharing */
2350 WRITE_VREG(PSCALE_CTRL, 0);
2351
2352 WRITE_VREG(AV_SCRATCH_0, 0);
2353 WRITE_VREG(AV_SCRATCH_1, buf_offset);
2354 if (!tee_enabled())
2355 WRITE_VREG(AV_SCRATCH_G, mc_dma_handle);
2356 WRITE_VREG(AV_SCRATCH_7, 0);
2357 WRITE_VREG(AV_SCRATCH_8, 0);
2358 WRITE_VREG(AV_SCRATCH_9, 0);
2359 WRITE_VREG(AV_SCRATCH_N, 0);
2360
2361#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
2362 if (bad_block_scale > 128)
2363 bad_block_scale = 128;
2364 WRITE_VREG(AV_SCRATCH_A, bad_block_scale);
2365#endif
2366
2367 error_recovery_mode_use =
2368 (error_recovery_mode !=
2369 0) ? error_recovery_mode : error_recovery_mode_in;
2370 WRITE_VREG(AV_SCRATCH_F,
2371 (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
2372 (READ_VREG(AV_SCRATCH_F) & 0xffffff43) |
2373 ((error_recovery_mode_use & 0x1) << 4));
2374 if (dec_control & DEC_CONTROL_FLAG_DISABLE_FAST_POC)
2375 SET_VREG_MASK(AV_SCRATCH_F, 1 << 7);
2376 /* clear mailbox interrupt */
2377 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
2378
2379 /* enable mailbox interrupt */
2380 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
2381
2382 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
2383 if (ucode_type == UCODE_IP_ONLY_PARAM)
2384 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
2385 else
2386 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
2387
2388 WRITE_VREG(AV_SCRATCH_I, (u32)(sei_data_buffer_phys - buf_offset));
2389 WRITE_VREG(AV_SCRATCH_J, 0);
2390 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
2391 if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) && !is_meson_mtvd_cpu()) {
2392 /* pr_info("vh264 meson8 prot init\n"); */
2393 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
2394 }
2395 /* #endif */
2396}
2397
2398static int vh264_local_init(void)
2399{
2400 int i, ret;
2401 u32 size;
2402 unsigned long buf_start;
2403 vh264_ratio = vh264_amstream_dec_info.ratio;
2404 /* vh264_ratio = 0x100; */
2405
2406 vh264_rotation = (((unsigned long) vh264_amstream_dec_info.param)
2407 >> 16) & 0xffff;
2408
2409 frame_prog = 0;
2410 frame_width = vh264_amstream_dec_info.width;
2411 frame_height = vh264_amstream_dec_info.height;
2412 frame_dur = vh264_amstream_dec_info.rate;
2413 pts_outside = ((unsigned long) vh264_amstream_dec_info.param) & 0x01;
2414 sync_outside = ((unsigned long) vh264_amstream_dec_info.param & 0x02)
2415 >> 1;
2416 use_idr_framerate = ((unsigned long) vh264_amstream_dec_info.param
2417 & 0x04) >> 2;
2418 max_refer_buf = !(((unsigned long) vh264_amstream_dec_info.param
2419 & 0x10) >> 4);
2420 if (!vh264_reset) {
2421 if (mm_blk_handle) {
2422 decoder_bmmu_box_free(mm_blk_handle);
2423 mm_blk_handle = NULL;
2424 }
2425
2426 mm_blk_handle = decoder_bmmu_box_alloc_box(
2427 DRIVER_NAME,
2428 0,
2429 MAX_BLK_BUFFERS,
2430 4 + PAGE_SHIFT,
2431 CODEC_MM_FLAGS_CMA_CLEAR |
2432 CODEC_MM_FLAGS_FOR_VDECODER |
2433 tvp_flag);
2434 }
2435 pr_info
2436 ("H264 sysinfo: %dx%d duration=%d, pts_outside=%d \n",
2437 frame_width, frame_height, frame_dur, pts_outside);
2438 pr_debug("sync_outside=%d, use_idr_framerate=%d\n",
2439 sync_outside, use_idr_framerate);
2440
2441 if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB)
2442 size = V_BUF_ADDR_OFFSET_NEW;
2443 else
2444 size = V_BUF_ADDR_OFFSET;
2445
2446 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 0,
2447 size, DRIVER_NAME, &buf_start);
2448 if (ret < 0)
2449 return ret;
2450
2451 buf_offset = buf_start - DEF_BUF_START_ADDR;
2452
2453 if ((unsigned long) vh264_amstream_dec_info.param & 0x08)
2454 ucode_type = UCODE_IP_ONLY_PARAM;
2455 else
2456 ucode_type = 0;
2457
2458 if ((unsigned long) vh264_amstream_dec_info.param & 0x20)
2459 error_recovery_mode_in = 1;
2460 else
2461 error_recovery_mode_in = 3;
2462
2463 if (!vh264_running) {
2464 last_mb_width = 0;
2465 last_mb_height = 0;
2466 }
2467
2468 for (i = 0; i < VF_BUF_NUM; i++)
2469 vfbuf_use[i] = 0;
2470
2471 INIT_KFIFO(display_q);
2472 INIT_KFIFO(delay_display_q);
2473 INIT_KFIFO(recycle_q);
2474 INIT_KFIFO(newframe_q);
2475
2476 for (i = 0; i < VF_POOL_SIZE; i++) {
2477 const struct vframe_s *vf = &vfpool[i];
2478
2479 vfpool[i].index = VF_BUF_NUM;
2480 vfpool[i].bufWidth = 1920;
2481 kfifo_put(&newframe_q, vf);
2482 }
2483
2484#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS
2485 last_interlaced = 1;
2486#endif
2487 h264_first_pts_ready = 0;
2488 h264_first_valid_pts_ready = false;
2489 h264pts1 = 0;
2490 h264pts2 = 0;
2491 h264_pts_count = 0;
2492 duration_from_pts_done = 0;
2493 vh264_error_count = READ_VREG(AV_SCRATCH_D);
2494
2495 p_last_vf = NULL;
2496 check_pts_discontinue = false;
2497 last_pts = 0;
2498 wait_buffer_counter = 0;
2499 vh264_no_disp_count = 0;
2500 fatal_error_flag = 0;
2501 high_bandwidth = 0;
2502 vh264_stream_switching_state = SWITCHING_STATE_OFF;
2503#ifdef DEBUG_PTS
2504 pts_missed = 0;
2505 pts_hit = 0;
2506#endif
2507 pts_discontinue = false;
2508 no_idr_error_count = 0;
2509
2510 reset_userdata_fifo(1);
2511
2512 if (enable_switch_fense) {
2513 for (i = 0; i < ARRAY_SIZE(fense_buffer_spec); i++) {
2514 struct buffer_spec_s *s = &fense_buffer_spec[i];
2515 s->alloc_count = 3 * SZ_1M / PAGE_SIZE;
2516 ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle,
2517 FENSE_BUFFER_IDX(i),
2518 3 * SZ_1M, DRIVER_NAME, &s->phy_addr);
2519
2520 if (ret < 0) {
2521 fatal_error_flag =
2522 DECODER_FATAL_ERROR_NO_MEM;
2523 vh264_running = 0;
2524 return ret;
2525 }
2526 s->y_canvas_index = 2 * i;
2527 s->u_canvas_index = 2 * i + 1;
2528 s->v_canvas_index = 2 * i + 1;
2529 }
2530 }
2531 return 0;
2532}
2533
2534static s32 vh264_init(void)
2535{
2536 int ret = 0;
2537 int trickmode_fffb = 0;
2538 int firmwareloaded = 0;
2539
2540 /* pr_info("\nvh264_init\n"); */
2541 init_timer(&recycle_timer);
2542
2543 stat |= STAT_TIMER_INIT;
2544
2545 vh264_running = 0;/* init here to reset last_mb_width&last_mb_height */
2546 vh264_eos = 0;
2547 duration_on_correcting = 0;
2548 first_pts = 0;
2549 first_pts64 = 0;
2550 first_offset = 0;
2551 first_pts_cached = false;
2552 fixed_frame_rate_check_count = 0;
2553 fr_hint_status = VDEC_NO_NEED_HINT;
2554 saved_resolution = 0;
2555 iponly_early_mode = 0;
2556 saved_idc_level = 0;
2557
2558 /*init vdec status*/
2559 ret = vh264_vdec_info_init();
2560 if (0 != ret)
2561 return -ret;
2562
2563 ret = vh264_local_init();
2564 if (ret < 0)
2565 return ret;
2566 query_video_status(0, &trickmode_fffb);
2567
2568 amvdec_enable();
2569 if (!firmwareloaded && tee_enabled()) {
2570 if (tee_load_video_fw((u32)VIDEO_DEC_H264) != 0) {
2571 amvdec_disable();
2572 return -1;
2573 }
2574 } else {
2575 /* -- ucode loading (amrisc and swap code) */
2576 mc_cpu_addr =
2577 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
2578 &mc_dma_handle, GFP_KERNEL);
2579 if (!mc_cpu_addr) {
2580 amvdec_disable();
2581 del_timer_sync(&recycle_timer);
2582 pr_err("vh264_init: Can not allocate mc memory.\n");
2583 return -ENOMEM;
2584 }
2585
2586 pr_debug("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
2587 (void *)mc_dma_handle, mc_cpu_addr);
2588 if (debugfirmware) {
2589 int r0, r1, r2, r3, r4, r5;
2590 char firmwarename[32];
2591
2592 pr_debug("start load debug %d firmware ...\n", debugfirmware);
2593
2594 snprintf(firmwarename, 32, "%s%d", "vh264_mc", debugfirmware);
2595 r0 = amvdec_loadmc_ex(VFORMAT_H264, firmwarename, NULL);
2596
2597#define DEBUGGET_FW(t, name, buf, size, ret)\
2598 do {\
2599 snprintf(firmwarename, 32, "%s%d", name,\
2600 debugfirmware);\
2601 ret = get_decoder_firmware_data(t,\
2602 firmwarename, buf, size);\
2603 } while (0)
2604 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_HEADER, vh264_header_mc,
2605 *MC_SWAP_SIZE);
2606 */
2607 DEBUGGET_FW(VFORMAT_H264, "vh264_header_mc",
2608 (u8 *) mc_cpu_addr + MC_OFFSET_HEADER,
2609 MC_SWAP_SIZE, r1);
2610
2611 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_DATA, vh264_data_mc,
2612 *MC_SWAP_SIZE);
2613 */
2614 DEBUGGET_FW(VFORMAT_H264, "vh264_data_mc",
2615 (u8 *) mc_cpu_addr + MC_OFFSET_DATA, MC_SWAP_SIZE, r2);
2616 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_MMCO, vh264_mmco_mc,
2617 *MC_SWAP_SIZE);
2618 */
2619 DEBUGGET_FW(VFORMAT_H264, "vh264_mmco_mc",
2620 (u8 *) mc_cpu_addr + MC_OFFSET_MMCO, MC_SWAP_SIZE, r3);
2621 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_LIST, vh264_list_mc,
2622 *MC_SWAP_SIZE);
2623 */
2624 DEBUGGET_FW(VFORMAT_H264, "vh264_list_mc",
2625 (u8 *) mc_cpu_addr + MC_OFFSET_LIST, MC_SWAP_SIZE, r4);
2626 /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_SLICE, vh264_slice_mc,
2627 *MC_SWAP_SIZE);
2628 */
2629 DEBUGGET_FW(VFORMAT_H264, "vh264_slice_mc",
2630 (u8 *) mc_cpu_addr + MC_OFFSET_SLICE, MC_SWAP_SIZE, r5);
2631
2632 if (r0 < 0 || r1 < 0 || r2 < 0 || r3 < 0 || r4 < 0 || r5 < 0) {
2633 pr_err("264 load debugfirmware err %d,%d,%d,%d,%d,%d\n",
2634 r0, r1, r2, r3, r4, r5);
2635 amvdec_disable();
2636 if (mc_cpu_addr) {
2637 dma_free_coherent(amports_get_dma_device(),
2638 MC_TOTAL_SIZE, mc_cpu_addr,
2639 mc_dma_handle);
2640 mc_cpu_addr = NULL;
2641 }
2642 return -EBUSY;
2643 }
2644 firmwareloaded = 1;
2645 } else {
2646 int ret = -1, size = -1;
2647 char *buf = vmalloc(0x1000 * 16);
2648
2649 if (IS_ERR_OR_NULL(buf))
2650 return -ENOMEM;
2651
2652 size = get_firmware_data(VIDEO_DEC_H264, buf);
2653 if (size < 0) {
2654 pr_err("get firmware fail.");
2655 vfree(buf);
2656 return -1;
2657 }
2658
2659 ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);
2660 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_HEADER,
2661 buf + 0x4000, MC_SWAP_SIZE);
2662 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_DATA,
2663 buf + 0x2000, MC_SWAP_SIZE);
2664 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_MMCO,
2665 buf + 0x6000, MC_SWAP_SIZE);
2666 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_LIST,
2667 buf + 0x3000, MC_SWAP_SIZE);
2668 memcpy((u8 *) mc_cpu_addr + MC_OFFSET_SLICE,
2669 buf + 0x5000, MC_SWAP_SIZE);
2670
2671 vfree(buf);
2672
2673 if (ret < 0) {
2674 pr_err("h264 load orignal firmware error %d.\n", ret);
2675 amvdec_disable();
2676 if (mc_cpu_addr) {
2677 dma_free_coherent(amports_get_dma_device(),
2678 MC_TOTAL_SIZE, mc_cpu_addr,
2679 mc_dma_handle);
2680 mc_cpu_addr = NULL;
2681 }
2682 return -EBUSY;
2683 }
2684 }
2685 }
2686
2687 stat |= STAT_MC_LOAD;
2688
2689 /* enable AMRISC side protocol */
2690 vh264_prot_init();
2691
2692#ifdef HANDLE_H264_IRQ
2693 /*TODO irq */
2694
2695 if (vdec_request_irq(VDEC_IRQ_1, vh264_isr,
2696 "vh264-irq", (void *)vh264_dec_id)) {
2697 pr_err("vh264 irq register error.\n");
2698 amvdec_disable();
2699 return -ENOENT;
2700 }
2701#endif
2702
2703 stat |= STAT_ISR_REG;
2704
2705#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2706 vf_provider_init(&vh264_vf_prov, PROVIDER_NAME, &vh264_vf_provider_ops,
2707 NULL);
2708 vf_reg_provider(&vh264_vf_prov);
2709 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
2710#else
2711 vf_provider_init(&vh264_vf_prov, PROVIDER_NAME, &vh264_vf_provider_ops,
2712 NULL);
2713 vf_reg_provider(&vh264_vf_prov);
2714#endif
2715
2716 if (frame_dur != 0) {
2717 if (!is_reset)
2718 vf_notify_receiver(PROVIDER_NAME,
2719 VFRAME_EVENT_PROVIDER_FR_HINT,
2720 (void *)((unsigned long)frame_dur));
2721 fr_hint_status = VDEC_HINTED;
2722 } else
2723 fr_hint_status = VDEC_NEED_HINT;
2724
2725 stat |= STAT_VF_HOOK;
2726
2727 recycle_timer.data = (ulong) &recycle_timer;
2728 recycle_timer.function = vh264_put_timer_func;
2729 recycle_timer.expires = jiffies + PUT_INTERVAL;
2730
2731 add_timer(&recycle_timer);
2732
2733 stat |= STAT_TIMER_ARM;
2734
2735 vh264_stream_switching_state = SWITCHING_STATE_OFF;
2736
2737 stat |= STAT_VDEC_RUN;
2738 wmb(); /* Ensure fetchbuf contents visible */
2739
2740 /* -- start decoder */
2741 amvdec_start();
2742
2743 init_userdata_fifo();
2744
2745 return 0;
2746}
2747
2748static int vh264_stop(int mode)
2749{
2750
2751
2752 if (stat & STAT_VDEC_RUN) {
2753 amvdec_stop();
2754 stat &= ~STAT_VDEC_RUN;
2755 }
2756
2757 if (stat & STAT_ISR_REG) {
2758 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
2759 /*TODO irq */
2760
2761 vdec_free_irq(VDEC_IRQ_1, (void *)vh264_dec_id);
2762
2763 stat &= ~STAT_ISR_REG;
2764 }
2765
2766 if (stat & STAT_TIMER_ARM) {
2767 del_timer_sync(&recycle_timer);
2768 stat &= ~STAT_TIMER_ARM;
2769 }
2770
2771 if (stat & STAT_VF_HOOK) {
2772 if (mode == MODE_FULL) {
2773 if (fr_hint_status == VDEC_HINTED && !is_reset)
2774 vf_notify_receiver(PROVIDER_NAME,
2775 VFRAME_EVENT_PROVIDER_FR_END_HINT,
2776 NULL);
2777 fr_hint_status = VDEC_NO_NEED_HINT;
2778 }
2779
2780 vf_unreg_provider(&vh264_vf_prov);
2781 stat &= ~STAT_VF_HOOK;
2782 }
2783
2784 if (stat & STAT_MC_LOAD) {
2785 if (mc_cpu_addr != NULL) {
2786 dma_free_coherent(amports_get_dma_device(),
2787 MC_TOTAL_SIZE, mc_cpu_addr,
2788 mc_dma_handle);
2789 mc_cpu_addr = NULL;
2790 }
2791 }
2792 if (sei_data_buffer != NULL) {
2793 dma_free_coherent(
2794 amports_get_dma_device(),
2795 USER_DATA_RUND_SIZE,
2796 sei_data_buffer,
2797 sei_data_buffer_phys);
2798 sei_data_buffer = NULL;
2799 sei_data_buffer_phys = 0;
2800 }
2801 amvdec_disable();
2802 if (mm_blk_handle) {
2803 decoder_bmmu_box_free(mm_blk_handle);
2804 mm_blk_handle = NULL;
2805 }
2806 memset(&fense_buffer_spec, 0, sizeof(fense_buffer_spec));
2807 memset(&buffer_spec, 0, sizeof(buffer_spec));
2808 return 0;
2809}
2810
2811static void error_do_work(struct work_struct *work)
2812{
2813 mutex_lock(&vh264_mutex);
2814
2815 /*
2816 * we need to lock vh264_stop/vh264_init.
2817 * because we will call amvdec_h264_remove on this step;
2818 * then we may call more than once on
2819 * free_irq/deltimer/..and some other.
2820 */
2821 if (atomic_read(&vh264_active)) {
2822 amvdec_stop();
2823 do {
2824 msleep(20);
2825 } while (vh264_stream_switching_state != SWITCHING_STATE_OFF);
2826 vh264_reset = 1;
2827#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
2828 vh264_ppmgr_reset();
2829#else
2830 vf_light_unreg_provider(&vh264_vf_prov);
2831
2832 vh264_local_init();
2833
2834 vf_reg_provider(&vh264_vf_prov);
2835#endif
2836 msleep(30);
2837 vh264_prot_init();
2838
2839 amvdec_start();
2840 vh264_reset = 0;
2841 }
2842
2843 mutex_unlock(&vh264_mutex);
2844}
2845
2846static void stream_switching_done(void)
2847{
2848 int state = vh264_stream_switching_state;
2849
2850 WRITE_VREG(AV_SCRATCH_7, 0);
2851 WRITE_VREG(AV_SCRATCH_8, 0);
2852 WRITE_VREG(AV_SCRATCH_9, 0);
2853
2854 if (state == SWITCHING_STATE_ON_CMD1) {
2855 pr_info("Enter set parameter cmd1 switching_state %x.\n",
2856 vh264_stream_switching_state);
2857 schedule_work(&set_parameter_work);
2858 return;
2859 } else if (state == SWITCHING_STATE_ON_CMD1_PENDING)
2860 return;
2861
2862 vh264_stream_switching_state = SWITCHING_STATE_OFF;
2863
2864 wmb(); /* Ensure fetchbuf contents visible */
2865
2866 if (state == SWITCHING_STATE_ON_CMD3)
2867 WRITE_VREG(AV_SCRATCH_0, 0);
2868
2869 pr_info("Leaving switching mode.\n");
2870}
2871
2872/* construt a new frame as a copy of last frame so frame receiver can
2873 * release all buffer resources to decoder.
2874 */
2875static void stream_switching_do(struct work_struct *work)
2876{
2877 int mb_total_num, mb_width_num, mb_height_num, i = 0;
2878 struct vframe_s *vf = NULL;
2879 u32 y_index, u_index, src_index, des_index, y_desindex, u_desindex;
2880 struct canvas_s csy, csu, cyd;
2881 unsigned long flags;
2882 bool delay = true;
2883
2884 if (!atomic_read(&vh264_active))
2885 return;
2886
2887 if (vh264_stream_switching_state == SWITCHING_STATE_OFF)
2888 return;
2889
2890 spin_lock_irqsave(&prepare_lock, flags);
2891
2892 block_display_q = true;
2893
2894 spin_unlock_irqrestore(&prepare_lock, flags);
2895
2896 mb_total_num = mb_total;
2897 mb_width_num = mb_width;
2898 mb_height_num = mb_height;
2899
2900 while (is_4k || kfifo_len(&delay_display_q) > 2) {
2901 if (kfifo_get(&delay_display_q, &vf)) {
2902 kfifo_put(&display_q,
2903 (const struct vframe_s *)vf);
2904 vf_notify_receiver(PROVIDER_NAME,
2905 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2906 } else
2907 break;
2908 }
2909
2910 if (!kfifo_get(&delay_display_q, &vf)) {
2911 vf = p_last_vf;
2912 delay = false;
2913 }
2914
2915 while (vf) {
2916 int buffer_index;
2917
2918 buffer_index = vf->index & 0xff;
2919
2920 /* construct a clone of the frame from last frame */
2921
2922#if 0
2923
2924 pr_info("src yaddr[0x%x] index[%d] width[%d] heigth[%d]\n",
2925 buffer_spec[buffer_index].y_addr,
2926 buffer_spec[buffer_index].y_canvas_index,
2927 buffer_spec[buffer_index].y_canvas_width,
2928 buffer_spec[buffer_index].y_canvas_height);
2929
2930 pr_info("src uaddr[0x%x] index[%d] width[%d] heigth[%d]\n",
2931 buffer_spec[buffer_index].u_addr,
2932 buffer_spec[buffer_index].u_canvas_index,
2933 buffer_spec[buffer_index].u_canvas_width,
2934 buffer_spec[buffer_index].u_canvas_height);
2935#endif
2936 if (EN_SWITCH_FENCE()) {
2937 y_index = buffer_spec[buffer_index].y_canvas_index;
2938 u_index = buffer_spec[buffer_index].u_canvas_index;
2939
2940 canvas_read(y_index, &csy);
2941 canvas_read(u_index, &csu);
2942
2943 canvas_config(fense_buffer_spec[i].y_canvas_index,
2944 fense_buffer_spec[i].phy_addr,
2945 mb_width_num << 4, mb_height_num << 4,
2946 CANVAS_ADDR_NOWRAP,
2947 CANVAS_BLKMODE_LINEAR);
2948 canvas_config(fense_buffer_spec[i].u_canvas_index,
2949 fense_buffer_spec[i].phy_addr +
2950 (mb_total_num << 8),
2951 mb_width_num << 4, mb_height_num << 3,
2952 CANVAS_ADDR_NOWRAP,
2953 CANVAS_BLKMODE_LINEAR);
2954
2955 y_desindex = fense_buffer_spec[i].y_canvas_index;
2956 u_desindex = fense_buffer_spec[i].u_canvas_index;
2957
2958 canvas_read(y_desindex, &cyd);
2959
2960 src_index = ((y_index & 0xff) |
2961 ((u_index << 8) & 0x0000ff00));
2962 des_index = ((y_desindex & 0xff) |
2963 ((u_desindex << 8) & 0x0000ff00));
2964
2965 ge2d_canvas_dup(&csy, &csu, &cyd,
2966 GE2D_FORMAT_M24_NV21,
2967 src_index,
2968 des_index);
2969 }
2970 vf->mem_handle = decoder_bmmu_box_get_mem_handle(
2971 mm_blk_handle,
2972 FENSE_BUFFER_IDX(i));
2973 fense_vf[i] = *vf;
2974 fense_vf[i].index = -1;
2975
2976 if (EN_SWITCH_FENCE())
2977 fense_vf[i].canvas0Addr =
2978 spec2canvas(&fense_buffer_spec[i]);
2979 else
2980 fense_vf[i].flag |= VFRAME_FLAG_SWITCHING_FENSE;
2981
2982 /* send clone to receiver */
2983 kfifo_put(&display_q,
2984 (const struct vframe_s *)&fense_vf[i]);
2985
2986 /* early recycle frames for last session */
2987 if (delay)
2988 vh264_vf_put(vf, NULL);
2989
2990 vf_notify_receiver(PROVIDER_NAME,
2991 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2992
2993 i++;
2994
2995 if (!kfifo_get(&delay_display_q, &vf))
2996 break;
2997 }
2998
2999 block_display_q = false;
3000
3001 pr_info("Switching fense frame post\n");
3002}
3003
3004static int amvdec_h264_probe(struct platform_device *pdev)
3005{
3006 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
3007
3008 mutex_lock(&vh264_mutex);
3009
3010 if (pdata == NULL) {
3011 pr_info("\namvdec_h264 memory resource undefined.\n");
3012 mutex_unlock(&vh264_mutex);
3013 return -EFAULT;
3014 }
3015 tvp_flag = vdec_secure(pdata) ? CODEC_MM_FLAGS_TVP : 0;
3016 if (pdata->sys_info)
3017 vh264_amstream_dec_info = *pdata->sys_info;
3018 if (sei_data_buffer == NULL) {
3019 sei_data_buffer =
3020 dma_alloc_coherent(amports_get_dma_device(),
3021 USER_DATA_RUND_SIZE,
3022 &sei_data_buffer_phys, GFP_KERNEL);
3023 if (!sei_data_buffer) {
3024 pr_info("%s: Can not allocate sei_data_buffer\n",
3025 __func__);
3026 mutex_unlock(&vh264_mutex);
3027 return -ENOMEM;
3028 }
3029 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
3030 * sei_data_buffer, sei_data_buffer_phys,
3031 * (u32)sei_data_buffer_remap);
3032 */
3033 }
3034 pdata->dec_status = vh264_dec_status;
3035 pdata->set_trickmode = vh264_set_trickmode;
3036 pdata->set_isreset = vh264_set_isreset;
3037 is_reset = 0;
3038
3039 if (vh264_init() < 0) {
3040 pr_info("\namvdec_h264 init failed.\n");
3041 kfree(gvs);
3042 gvs = NULL;
3043 mutex_unlock(&vh264_mutex);
3044 return -ENODEV;
3045 }
3046
3047 INIT_WORK(&error_wd_work, error_do_work);
3048 INIT_WORK(&stream_switching_work, stream_switching_do);
3049 INIT_WORK(&set_parameter_work, vh264_set_params);
3050 INIT_WORK(&notify_work, vh264_notify_work);
3051
3052 INIT_WORK(&userdata_push_work, userdata_push_do_work);
3053
3054
3055
3056 atomic_set(&vh264_active, 1);
3057
3058 mutex_unlock(&vh264_mutex);
3059
3060 return 0;
3061}
3062
3063static int amvdec_h264_remove(struct platform_device *pdev)
3064{
3065 atomic_set(&vh264_active, 0);
3066 cancel_work_sync(&set_parameter_work);
3067 cancel_work_sync(&error_wd_work);
3068 cancel_work_sync(&stream_switching_work);
3069 cancel_work_sync(&notify_work);
3070 cancel_work_sync(&userdata_push_work);
3071
3072 mutex_lock(&vh264_mutex);
3073 vh264_stop(MODE_FULL);
3074 vdec_source_changed(VFORMAT_H264, 0, 0, 0);
3075 atomic_set(&vh264_active, 0);
3076#ifdef DEBUG_PTS
3077 pr_info
3078 ("pts missed %ld, pts hit %ld, pts_outside %d, duration %d, ",
3079 pts_missed, pts_hit, pts_outside, frame_dur);
3080 pr_info("sync_outside %d, use_idr_framerate %d\n",
3081 sync_outside, use_idr_framerate);
3082#endif
3083 kfree(gvs);
3084 gvs = NULL;
3085 mutex_unlock(&vh264_mutex);
3086 return 0;
3087}
3088
3089/****************************************/
3090
3091static struct platform_driver amvdec_h264_driver = {
3092 .probe = amvdec_h264_probe,
3093 .remove = amvdec_h264_remove,
3094#ifdef CONFIG_PM
3095 .suspend = amvdec_suspend,
3096 .resume = amvdec_resume,
3097#endif
3098 .driver = {
3099 .name = DRIVER_NAME,
3100 }
3101};
3102
3103static struct codec_profile_t amvdec_h264_profile = {
3104 .name = "h264",
3105 .profile = ""
3106};
3107
3108
3109static struct mconfig h264_configs[] = {
3110 MC_PU32("stat", &stat),
3111 MC_PU32("error_recovery_mode", &error_recovery_mode),
3112 MC_PU32("sync_outside", &sync_outside),
3113 MC_PU32("dec_control", &dec_control),
3114 MC_PU32("fatal_error_reset", &fatal_error_reset),
3115 MC_PU32("max_refer_buf", &max_refer_buf),
3116 MC_PU32("ucode_type", &ucode_type),
3117 MC_PU32("debugfirmware", &debugfirmware),
3118 MC_PU32("fixed_frame_rate_flag", &fixed_frame_rate_flag),
3119 MC_PU32("decoder_debug_flag", &decoder_debug_flag),
3120 MC_PU32("dpb_size_adj", &dpb_size_adj),
3121 MC_PU32("decoder_force_reset", &decoder_force_reset),
3122 MC_PU32("no_idr_error_max", &no_idr_error_max),
3123 MC_PU32("enable_switch_fense", &enable_switch_fense),
3124};
3125static struct mconfig_node h264_node;
3126
3127
3128static int __init amvdec_h264_driver_init_module(void)
3129{
3130 pr_debug("amvdec_h264 module init\n");
3131
3132 ge2d_videoh264task_init();
3133
3134 if (platform_driver_register(&amvdec_h264_driver)) {
3135 pr_err("failed to register amvdec_h264 driver\n");
3136 return -ENODEV;
3137 }
3138 if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB
3139 && (codec_mm_get_total_size() > 80 * SZ_1M)) {
3140 amvdec_h264_profile.profile = "4k";
3141 }
3142 vcodec_profile_register(&amvdec_h264_profile);
3143 INIT_REG_NODE_CONFIGS("media.decoder", &h264_node,
3144 "h264", h264_configs, CONFIG_FOR_RW);
3145 return 0;
3146}
3147
3148static void __exit amvdec_h264_driver_remove_module(void)
3149{
3150 pr_debug("amvdec_h264 module remove.\n");
3151
3152 platform_driver_unregister(&amvdec_h264_driver);
3153
3154 ge2d_videoh264task_release();
3155}
3156
3157/****************************************/
3158
3159module_param(stat, uint, 0664);
3160MODULE_PARM_DESC(stat, "\n amvdec_h264 stat\n");
3161module_param(error_recovery_mode, uint, 0664);
3162MODULE_PARM_DESC(error_recovery_mode, "\n amvdec_h264 error_recovery_mode\n");
3163module_param(sync_outside, uint, 0664);
3164MODULE_PARM_DESC(sync_outside, "\n amvdec_h264 sync_outside\n");
3165module_param(dec_control, uint, 0664);
3166MODULE_PARM_DESC(dec_control, "\n amvdec_h264 decoder control\n");
3167module_param(fatal_error_reset, uint, 0664);
3168MODULE_PARM_DESC(fatal_error_reset,
3169 "\n amvdec_h264 decoder reset when fatal error happens\n");
3170module_param(max_refer_buf, uint, 0664);
3171MODULE_PARM_DESC(max_refer_buf,
3172 "\n amvdec_h264 dec buffering or not for reference frame\n");
3173module_param(ucode_type, uint, 0664);
3174MODULE_PARM_DESC(ucode_type,
3175 "\n amvdec_h264 dec buffering or not for reference frame\n");
3176module_param(debugfirmware, uint, 0664);
3177MODULE_PARM_DESC(debugfirmware, "\n amvdec_h264 debug load firmware\n");
3178module_param(fixed_frame_rate_flag, uint, 0664);
3179MODULE_PARM_DESC(fixed_frame_rate_flag,
3180 "\n amvdec_h264 fixed_frame_rate_flag\n");
3181module_param(decoder_debug_flag, uint, 0664);
3182MODULE_PARM_DESC(decoder_debug_flag,
3183 "\n amvdec_h264 decoder_debug_flag\n");
3184
3185module_param(dpb_size_adj, uint, 0664);
3186MODULE_PARM_DESC(dpb_size_adj,
3187 "\n amvdec_h264 dpb_size_adj\n");
3188
3189
3190module_param(decoder_force_reset, uint, 0664);
3191MODULE_PARM_DESC(decoder_force_reset,
3192 "\n amvdec_h264 decoder force reset\n");
3193module_param(no_idr_error_max, uint, 0664);
3194MODULE_PARM_DESC(no_idr_error_max,
3195 "\n print no_idr_error_max\n");
3196module_param(enable_switch_fense, uint, 0664);
3197MODULE_PARM_DESC(enable_switch_fense,
3198 "\n enable switch fense\n");
3199
3200#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY
3201module_param(bad_block_scale, uint, 0664);
3202MODULE_PARM_DESC(bad_block_scale,
3203 "\n print bad_block_scale\n");
3204#endif
3205
3206module_init(amvdec_h264_driver_init_module);
3207module_exit(amvdec_h264_driver_remove_module);
3208
3209MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
3210MODULE_LICENSE("GPL");
3211MODULE_AUTHOR("Chen Zhang <chen.zhang@amlogic.com>");
3212
generated by cgit at 2024-05-19 20:29:04 (GMT)