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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: c2a0f3890f845d6128de86d07a1f2d6aeb635b6c
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64#include <media/v4l2-mem2mem.h>
65
66#undef pr_info
67#define pr_info printk
68#define VDEC_DW
69#define DEBUG_UCODE
70#define MEM_NAME "codec_m264"
71#define MULTI_INSTANCE_FRAMEWORK
72/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
73#include "h264_dpb.h"
74/* #define SEND_PARAM_WITH_REG */
75
76#define DRIVER_NAME "ammvdec_h264"
77#define MODULE_NAME "ammvdec_h264"
78#define DRIVER_HEADER_NAME "ammvdec_h264_header"
79
80#define CHECK_INTERVAL (HZ/100)
81
82#define SEI_DATA_SIZE (8*1024)
83#define SEI_ITU_DATA_SIZE (4*1024)
84
85#define RATE_MEASURE_NUM 8
86#define RATE_CORRECTION_THRESHOLD 5
87#define RATE_2397_FPS 4004 /* 23.97 */
88#define RATE_25_FPS 3840 /* 25 */
89#define RATE_2997_FPS 3203 /* 29.97 */
90#define DUR2PTS(x) ((x)*90/96)
91#define PTS2DUR(x) ((x)*96/90)
92#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
93#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
94
95#define FIX_FRAME_RATE_OFF 0
96#define FIX_FRAME_RATE_ON 1
97#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
98
99#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
100#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
101#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
102#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
103
104#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
105
106#define RATE_MEASURE_NUM 8
107#define RATE_CORRECTION_THRESHOLD 5
108#define RATE_24_FPS 4004 /* 23.97 */
109#define RATE_25_FPS 3840 /* 25 */
110#define DUR2PTS(x) ((x)*90/96)
111#define PTS2DUR(x) ((x)*96/90)
112#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
113#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
114
115#define H264_DEV_NUM 9
116
117#define CONSTRAIN_MAX_BUF_NUM
118
119#define H264_MMU
120#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
121#define INVALID_IDX -1 /* Invalid buffer index.*/
122
123static int mmu_enable;
124/*mmu do not support mbaff*/
125static int force_enable_mmu = 0;
126unsigned int h264_debug_flag; /* 0xa0000000; */
127unsigned int h264_debug_mask = 0xff;
128 /*
129 *h264_debug_cmd:
130 * 0x1xx, force decoder id of xx to be disconnected
131 */
132unsigned int h264_debug_cmd;
133
134static unsigned int dec_control =
135 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
136 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
137
138static unsigned int force_rate_streambase;
139static unsigned int force_rate_framebase;
140static unsigned int force_disp_bufspec_num;
141static unsigned int fixed_frame_rate_mode;
142static unsigned int error_recovery_mode_in;
143static int start_decode_buf_level = 0x4000;
144static int pre_decode_buf_level = 0x1000;
145static int stream_mode_start_num = 4;
146
147#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
148/*to make reorder size difference of bl and el not too big*/
149static unsigned int reorder_dpb_size_margin_dv = 16;
150#endif
151static unsigned int reorder_dpb_size_margin = 6;
152static unsigned int reference_buf_margin = 4;
153
154#ifdef CONSTRAIN_MAX_BUF_NUM
155static u32 run_ready_max_vf_only_num;
156static u32 run_ready_display_q_num;
157 /*0: not check
158 0xff: mDPB.size
159 */
160static u32 run_ready_max_buf_num = 0xff;
161#endif
162
163static u32 run_ready_min_buf_num = 2;
164
165#define VDEC_ASSIST_CANVAS_BLK32 0x5
166
167
168static unsigned int max_alloc_buf_count;
169static unsigned int decode_timeout_val = 100;
170static unsigned int errordata_timeout_val = 50;
171static unsigned int get_data_timeout_val = 2000;
172#if 1
173/* H264_DATA_REQUEST does not work, disable it,
174decode has error for data in none continuous address
175*/
176static unsigned int frame_max_data_packet;
177#else
178static unsigned int frame_max_data_packet = 8;
179#endif
180static unsigned int radr;
181static unsigned int rval;
182static u32 endian = 0xff0;
183
184/*
185 udebug_flag:
186 bit 0, enable ucode print
187 bit 1, enable ucode detail print
188 bit 3, disable ucode watchdog
189 bit [31:16] not 0, pos to dump lmem
190 bit 2, pop bits to lmem
191 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
192*/
193static u32 udebug_flag;
194/*
195 when udebug_flag[1:0] is not 0
196 udebug_pause_pos not 0,
197 pause position
198*/
199static u32 udebug_pause_pos;
200/*
201 when udebug_flag[1:0] is not 0
202 and udebug_pause_pos is not 0,
203 pause only when DEBUG_REG2 is equal to this val
204*/
205static u32 udebug_pause_val;
206
207static u32 udebug_pause_decode_idx;
208
209static unsigned int disp_vframe_valve_level;
210
211static unsigned int max_decode_instance_num = H264_DEV_NUM;
212static unsigned int decode_frame_count[H264_DEV_NUM];
213static unsigned int display_frame_count[H264_DEV_NUM];
214static unsigned int max_process_time[H264_DEV_NUM];
215static unsigned int max_get_frame_interval[H264_DEV_NUM];
216static unsigned int run_count[H264_DEV_NUM];
217static unsigned int input_empty[H264_DEV_NUM];
218static unsigned int not_run_ready[H264_DEV_NUM];
219static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
220{1, 1, 1, 1, 1, 1, 1, 1, 1};
221
222#define VDEC_CLOCK_ADJUST_FRAME 30
223static unsigned int clk_adj_frame_count;
224
225/*
226 *bit[3:0]: 0, run ; 1, pause; 3, step
227 *bit[4]: 1, schedule run
228 */
229static unsigned int step[H264_DEV_NUM];
230
231#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
232static u32 prefix_aux_buf_size = (16 * 1024);
233static u32 suffix_aux_buf_size;
234
235#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
236static u32 dv_toggle_prov_name;
237
238static u32 dolby_meta_with_el;
239#endif
240
241/*
242 bit[8]
243 0: use sys_info[bit 3]
244 not 0:use i_only_flag[7:0]
245 bit[7:0]:
246 bit 0, 1: only display I picture;
247 bit 1, 1: only decode I picture;
248*/
249static unsigned int i_only_flag;
250
251/*
252 error_proc_policy:
253 bit[0] send_error_frame_flag;
254 (valid when bit[31] is 1, otherwise use sysinfo)
255 bit[1] do not decode if config_decode_buf() fail
256 bit[2] force release buf if in deadlock
257 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
258 bit[4] check inactive of receiver
259 bit[5] reset buffmgr if in deadlock
260 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
261 bit[7] reset buffmgr if dpb error
262
263 bit[8] check total mbx/mby of decoded frame
264 bit[9] check ERROR_STATUS_REG
265 bit[10] check reference list
266 bit[11] mark error if dpb error
267 bit[12] i_only when error happen
268 bit[13] 0: mark error according to last pic, 1: ignore mark error
269 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
270*/
271static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
272
273
274/*
275 error_skip_count:
276 bit[11:0] error skip frame count
277 bit[15:12] error skip i picture count
278*/
279static unsigned int error_skip_count = (0x2 << 12) | 0x40;
280
281static unsigned int force_sliding_margin;
282/*
283 bit[1:0]:
284 0, start playing from any frame
285 1, start playing from I frame
286 bit[15:8]: the count of skip frames after first I
287 2, start playing from second I frame (decode from the first I)
288 bit[15:8]: the max count of skip frames after first I
289 3, start playing from IDR
290*/
291static unsigned int first_i_policy = 1;
292
293/*
294 fast_output_enable:
295 bit [0], output frame if there is IDR in list
296 bit [1], output frame if the current poc is 1 big than the previous poc
297 bit [2], if even poc only, output frame ifthe cuurent poc
298 is 2 big than the previous poc
299 bit [3], ip only
300*/
301static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
302
303static unsigned int enable_itu_t35 = 1;
304
305static unsigned int frmbase_cont_bitlevel = 0x40;
306
307static unsigned int frmbase_cont_bitlevel2 = 0x1;
308
309
310#define MH264_USERDATA_ENABLE
311
312/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
313/* hevc->double_write_mode:
314 0, no double write
315 1, 1:1 ratio
316 2, (1/4):(1/4) ratio
317 3, (1/4):(1/4) ratio, with both compressed frame included
318 4, (1/2):(1/2) ratio
319 0x10, double write only
320 0x10000: vdec dw horizotal 1/2
321 0x20000: vdec dw horizotal/vertical 1/2
322*/
323static u32 double_write_mode;
324static u32 without_display_mode;
325#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
326
327static void vmh264_dump_state(struct vdec_s *vdec);
328
329#define is_in_parsing_state(status) \
330 ((status == H264_ACTION_SEARCH_HEAD) || \
331 ((status & 0xf0) == 0x80))
332
333#define is_interlace(frame) \
334 (frame->frame &&\
335 frame->top_field &&\
336 frame->bottom_field &&\
337 (!frame->frame->coded_frame))
338static inline bool close_to(int a, int b, int m)
339{
340 return (abs(a - b) < m) ? true : false;
341}
342
343#if 0
344#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
345#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
346#else
347#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
348#define h264_free_hw_stru(dev, hw) vfree(hw)
349#endif
350
351/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
352#define NV21
353/* #endif */
354
355/* 12M for L41 */
356#define MAX_DPB_BUFF_SIZE (12*1024*1024)
357#define DEFAULT_MEM_SIZE (32*1024*1024)
358#define AVIL_DPB_BUFF_SIZE 0x01ec2000
359
360#define DEF_BUF_START_ADDR 0x01000000
361#define mem_sps_base 0x011c3c00
362#define mem_pps_base 0x011cbc00
363/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
364u32 V_BUF_ADDR_OFFSET = 0x200000;
365#define DCAC_READ_MARGIN (64 * 1024)
366
367
368#define EXTEND_SAR 0xff
369#define BUFSPEC_POOL_SIZE 64
370#define VF_POOL_SIZE 64
371#define VF_POOL_NUM 2
372#define MAX_VF_BUF_NUM 27
373#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
374#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
375#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
376#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
377#define EXTIF_BUF_SIZE (0x10000 * 2)
378
379#define HEADER_BUFFER_IDX(n) (n)
380#define VF_BUFFER_IDX(n) (n)
381
382
383#define PUT_INTERVAL (HZ/100)
384#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
385
386#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
387#define SWITCHING_STATE_OFF 0
388#define SWITCHING_STATE_ON_CMD3 1
389#define SWITCHING_STATE_ON_CMD1 2
390
391
392
393#define INCPTR(p) ptr_atomic_wrap_inc(&p)
394
395#define SLICE_TYPE_I 2
396#define SLICE_TYPE_P 5
397#define SLICE_TYPE_B 6
398
399struct buffer_spec_s {
400 /*
401 used:
402 -1, none allocated
403 0, allocated, free
404 1, used by dpb
405 2, in disp queue;
406 3, in disp queue, isolated,
407 do not use for dpb when vf_put;
408 4, to release
409 5, in disp queue, isolated (but not to release)
410 do not use for dpb when vf_put;
411 */
412 unsigned int used;
413 unsigned int info0;
414 unsigned int info1;
415 unsigned int info2;
416 unsigned int y_addr;
417 unsigned int u_addr;
418 unsigned int v_addr;
419
420 int y_canvas_index;
421 int u_canvas_index;
422 int v_canvas_index;
423
424#ifdef VDEC_DW
425 unsigned int vdec_dw_y_addr;
426 unsigned int vdec_dw_u_addr;
427 unsigned int vdec_dw_v_addr;
428
429 int vdec_dw_y_canvas_index;
430 int vdec_dw_u_canvas_index;
431 int vdec_dw_v_canvas_index;
432#ifdef NV21
433 struct canvas_config_s vdec_dw_canvas_config[2];
434#else
435 struct canvas_config_s vdec_dw_canvas_config[3];
436#endif
437#endif
438
439#ifdef NV21
440 struct canvas_config_s canvas_config[2];
441#else
442 struct canvas_config_s canvas_config[3];
443#endif
444 unsigned long cma_alloc_addr;
445 unsigned int buf_adr;
446#ifdef H264_MMU
447 unsigned long alloc_header_addr;
448#endif
449 char *aux_data_buf;
450 int aux_data_size;
451#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
452 unsigned char dv_enhance_exist;
453#endif
454 int canvas_pos;
455 int vf_ref;
456 /*unsigned int comp_body_size;*/
457 unsigned int dw_y_adr;
458 unsigned int dw_u_v_adr;
459};
460
461#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
462#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
463#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
464
465
466#define vdec_dw_spec2canvas(x) \
467 (((x)->vdec_dw_v_canvas_index << 16) | \
468 ((x)->vdec_dw_u_canvas_index << 8) | \
469 ((x)->vdec_dw_y_canvas_index << 0))
470
471
472#define spec2canvas(x) \
473 (((x)->v_canvas_index << 16) | \
474 ((x)->u_canvas_index << 8) | \
475 ((x)->y_canvas_index << 0))
476
477#define FRAME_INDEX(vf_index) (vf_index & 0xff)
478#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
479#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
480
481static struct vframe_s *vh264_vf_peek(void *);
482static struct vframe_s *vh264_vf_get(void *);
483static void vh264_vf_put(struct vframe_s *, void *);
484static int vh264_vf_states(struct vframe_states *states, void *);
485static int vh264_event_cb(int type, void *data, void *private_data);
486static void vh264_work(struct work_struct *work);
487static void vh264_timeout_work(struct work_struct *work);
488static void vh264_notify_work(struct work_struct *work);
489#ifdef MH264_USERDATA_ENABLE
490static void user_data_ready_notify_work(struct work_struct *work);
491static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
492#endif
493
494static const char vh264_dec_id[] = "vh264-dev";
495
496#define PROVIDER_NAME "vdec.h264"
497
498static const struct vframe_operations_s vf_provider_ops = {
499 .peek = vh264_vf_peek,
500 .get = vh264_vf_get,
501 .put = vh264_vf_put,
502 .event_cb = vh264_event_cb,
503 .vf_states = vh264_vf_states,
504};
505
506#define DEC_RESULT_NONE 0
507#define DEC_RESULT_DONE 1
508#define DEC_RESULT_AGAIN 2
509#define DEC_RESULT_CONFIG_PARAM 3
510#define DEC_RESULT_GET_DATA 4
511#define DEC_RESULT_GET_DATA_RETRY 5
512#define DEC_RESULT_ERROR 6
513#define DEC_RESULT_EOS 7
514#define DEC_RESULT_FORCE_EXIT 8
515
516/*
517 *static const char *dec_result_str[] = {
518 * "DEC_RESULT_NONE ",
519 * "DEC_RESULT_DONE ",
520 * "DEC_RESULT_AGAIN ",
521 * "DEC_RESULT_CONFIG_PARAM",
522 * "DEC_RESULT_GET_DATA ",
523 * "DEC_RESULT_GET_DA_RETRY",
524 * "DEC_RESULT_ERROR ",
525 *};
526 */
527
528#define UCODE_IP_ONLY 2
529#define UCODE_IP_ONLY_PARAM 1
530
531#define MC_OFFSET_HEADER 0x0000
532#define MC_OFFSET_DATA 0x1000
533#define MC_OFFSET_MMCO 0x2000
534#define MC_OFFSET_LIST 0x3000
535#define MC_OFFSET_SLICE 0x4000
536#define MC_OFFSET_MAIN 0x5000
537
538#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
539#define MC_SWAP_SIZE (4*SZ_1K)
540#define MODE_ERROR 0
541#define MODE_FULL 1
542
543#define DFS_HIGH_THEASHOLD 3
544
545#define INIT_FLAG_REG AV_SCRATCH_2
546#define HEAD_PADING_REG AV_SCRATCH_3
547#define UCODE_WATCHDOG_REG AV_SCRATCH_7
548#define LMEM_DUMP_ADR AV_SCRATCH_L
549#define DEBUG_REG1 AV_SCRATCH_M
550#define DEBUG_REG2 AV_SCRATCH_N
551#define FRAME_COUNTER_REG AV_SCRATCH_I
552#define RPM_CMD_REG AV_SCRATCH_A
553#define H264_DECODE_SIZE AV_SCRATCH_E
554#define H264_DECODE_MODE AV_SCRATCH_4
555#define H264_DECODE_SEQINFO AV_SCRATCH_5
556#define H264_AUX_ADR AV_SCRATCH_C
557#define H264_AUX_DATA_SIZE AV_SCRATCH_H
558
559#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
560#define DPB_STATUS_REG AV_SCRATCH_J
561#define ERROR_STATUS_REG AV_SCRATCH_9
562 /*
563 NAL_SEARCH_CTL: bit 0, enable itu_t35
564 NAL_SEARCH_CTL: bit 1, enable mmu
565 */
566#define NAL_SEARCH_CTL AV_SCRATCH_9
567#define MBY_MBX MB_MOTION_MODE /*0xc07*/
568
569#define DECODE_MODE_SINGLE 0x0
570#define DECODE_MODE_MULTI_FRAMEBASE 0x1
571#define DECODE_MODE_MULTI_STREAMBASE 0x2
572#define DECODE_MODE_MULTI_DVBAL 0x3
573#define DECODE_MODE_MULTI_DVENL 0x4
574static DEFINE_MUTEX(vmh264_mutex);
575
576
577
578#ifdef MH264_USERDATA_ENABLE
579
580struct mh264_userdata_record_t {
581 struct userdata_meta_info_t meta_info;
582 u32 rec_start;
583 u32 rec_len;
584};
585
586struct mh264_ud_record_wait_node_t {
587 struct list_head list;
588 struct mh264_userdata_record_t ud_record;
589};
590#define USERDATA_FIFO_NUM 256
591#define MAX_FREE_USERDATA_NODES 5
592
593struct mh264_userdata_info_t {
594 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
595 u8 *data_buf;
596 u8 *data_buf_end;
597 u32 buf_len;
598 u32 read_index;
599 u32 write_index;
600 u32 last_wp;
601};
602
603
604#endif
605
606struct vdec_h264_hw_s {
607 spinlock_t lock;
608 spinlock_t bufspec_lock;
609 int id;
610 struct platform_device *platform_dev;
611 unsigned long cma_alloc_addr;
612 /* struct page *collocate_cma_alloc_pages; */
613 unsigned long collocate_cma_alloc_addr;
614
615 u32 prefix_aux_size;
616 u32 suffix_aux_size;
617 void *aux_addr;
618 dma_addr_t aux_phy_addr;
619
620 /* buffer for store all sei data */
621 void *sei_data_buf;
622 u32 sei_data_len;
623
624 /* buffer for storing one itu35 recored */
625 void *sei_itu_data_buf;
626 u32 sei_itu_data_len;
627
628 /* recycle buffer for user data storing all itu35 records */
629 void *sei_user_data_buffer;
630 u32 sei_user_data_wp;
631#ifdef MH264_USERDATA_ENABLE
632 struct work_struct user_data_ready_work;
633#endif
634 struct StorablePicture *last_dec_picture;
635
636 ulong lmem_addr;
637 dma_addr_t lmem_addr_remap;
638
639 void *bmmu_box;
640#ifdef H264_MMU
641 void *mmu_box;
642 void *frame_mmu_map_addr;
643 dma_addr_t frame_mmu_map_phy_addr;
644 u32 hevc_cur_buf_idx;
645 u32 losless_comp_body_size;
646 u32 losless_comp_body_size_sao;
647 u32 losless_comp_header_size;
648 u32 mc_buffer_size_u_v;
649 u32 mc_buffer_size_u_v_h;
650 u32 is_idr_frame;
651 u32 is_new_pic;
652 u32 frame_done;
653 u32 frame_busy;
654 unsigned long extif_addr;
655 int double_write_mode;
656 int mmu_enable;
657#endif
658
659 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
660 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
661
662 int cur_pool;
663 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
664 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
665 struct vframe_s switching_fense_vf;
666 struct h264_dpb_stru dpb;
667 u8 init_flag;
668 u8 first_sc_checked;
669 u8 has_i_frame;
670 u8 config_bufmgr_done;
671 u32 max_reference_size;
672 u32 decode_pic_count;
673 u32 reflist_error_count;
674 int start_search_pos;
675 u32 reg_iqidct_control;
676 u32 reg_vcop_ctrl_reg;
677 u32 reg_rv_ai_mb_count;
678 u32 vld_dec_control;
679 struct vframe_s vframe_dummy;
680
681 unsigned char buffer_empty_flag;
682
683 u32 frame_width;
684 u32 frame_height;
685 u32 frame_dur;
686 u32 frame_prog;
687 u32 frame_packing_type;
688
689 struct vframe_chunk_s *chunk;
690
691 u32 stat;
692 unsigned long buf_start;
693 u32 buf_offset;
694 u32 buf_size;
695 /* u32 ucode_map_start; */
696 u32 pts_outside;
697 u32 sync_outside;
698 u32 vh264_ratio;
699 u32 vh264_rotation;
700 u32 use_idr_framerate;
701
702 u32 seq_info;
703 u32 seq_info2;
704 u32 video_signal_from_vui; /*to do .. */
705 u32 timing_info_present_flag;
706 u32 fixed_frame_rate_flag;
707 u32 bitstream_restriction_flag;
708 u32 num_reorder_frames;
709 u32 max_dec_frame_buffering;
710 u32 iframe_count;
711 u32 aspect_ratio_info;
712 u32 num_units_in_tick;
713 u32 time_scale;
714 u32 h264_ar;
715 bool h264_first_valid_pts_ready;
716 u32 h264pts1;
717 u32 h264pts2;
718 u32 pts_duration;
719 u32 h264_pts_count;
720 u32 duration_from_pts_done;
721 u32 pts_unstable;
722 u32 unstable_pts;
723 u32 last_checkout_pts;
724 u32 max_refer_buf;
725
726 s32 vh264_stream_switching_state;
727 struct vframe_s *p_last_vf;
728 u32 last_pts;
729 u32 last_pts_remainder;
730 u32 last_duration;
731 u32 last_mb_width, last_mb_height;
732 bool check_pts_discontinue;
733 bool pts_discontinue;
734 u32 wait_buffer_counter;
735 u32 first_offset;
736 u32 first_pts;
737 u64 first_pts64;
738 bool first_pts_cached;
739 u64 last_pts64;
740#if 0
741 void *sei_data_buffer;
742 dma_addr_t sei_data_buffer_phys;
743#endif
744
745 uint error_recovery_mode;
746 uint mb_total;
747 uint mb_width;
748 uint mb_height;
749
750 uint i_only;
751 int skip_frame_count;
752 bool no_poc_reorder_flag;
753 bool send_error_frame_flag;
754 dma_addr_t mc_dma_handle;
755 void *mc_cpu_addr;
756 int vh264_reset;
757
758 atomic_t vh264_active;
759
760 struct dec_sysinfo vh264_amstream_dec_info;
761
762 int dec_result;
763 struct work_struct work;
764 struct work_struct notify_work;
765 struct work_struct timeout_work;
766 void (*vdec_cb)(struct vdec_s *, void *);
767 void *vdec_cb_arg;
768
769 struct timer_list check_timer;
770
771 /**/
772 unsigned int last_frame_time;
773 u32 vf_pre_count;
774 u32 vf_get_count;
775 u32 vf_put_count;
776
777 /* timeout handle */
778 unsigned long int start_process_time;
779 unsigned int last_mby_mbx;
780 unsigned int last_vld_level;
781 unsigned int decode_timeout_count;
782 unsigned int timeout_num;
783 unsigned int search_dataempty_num;
784 unsigned int decode_timeout_num;
785 unsigned int decode_dataempty_num;
786 unsigned int buffer_empty_recover_num;
787
788 unsigned get_data_count;
789 unsigned get_data_start_time;
790 /**/
791
792 /*log*/
793 unsigned int packet_write_success_count;
794 unsigned int packet_write_EAGAIN_count;
795 unsigned int packet_write_ENOMEM_count;
796 unsigned int packet_write_EFAULT_count;
797 unsigned int total_read_size_pre;
798 unsigned int total_read_size;
799 unsigned int frame_count_pre;
800#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
801 u8 switch_dvlayer_flag;
802 u8 got_valid_nal;
803#endif
804 u8 eos;
805 u8 data_flag;
806 u32 no_error_count;
807 u32 no_error_i_count;
808 /*
809 NODISP_FLAG
810 */
811 u8 dec_flag;
812
813 u32 ucode_pause_pos;
814
815 u8 reset_bufmgr_flag;
816 u32 reset_bufmgr_count;
817 u32 cfg_param1;
818 u32 cfg_param2;
819 u32 cfg_param3;
820 u32 cfg_param4;
821 int valve_count;
822 u8 next_again_flag;
823 u32 pre_parser_wr_ptr;
824 struct firmware_s *fw;
825 struct firmware_s *fw_mmu;
826#ifdef MH264_USERDATA_ENABLE
827 /*user data*/
828 struct mutex userdata_mutex;
829 struct mh264_userdata_info_t userdata_info;
830 struct mh264_userdata_record_t ud_record;
831 int wait_for_udr_send;
832#endif
833 u32 no_mem_count;
834 u32 canvas_mode;
835 bool is_used_v4l;
836 void *v4l2_ctx;
837 bool v4l_params_parsed;
838 wait_queue_head_t wait_q;
839 u32 reg_g_status;
840 struct mutex chunks_mutex;
841 int need_cache_size;
842 u64 sc_start_time;
843 u8 frmbase_cont_flag;
844 struct vframe_qos_s vframe_qos;
845 int frameinfo_enable;
846 bool first_head_check_flag;
847 unsigned int height_aspect_ratio;
848 unsigned int width_aspect_ratio;
849 bool new_iframe_flag;
850 bool ref_err_flush_dpb_flag;
851 unsigned int first_i_policy;
852 u32 reorder_dpb_size_margin;
853};
854
855static u32 again_threshold;
856
857static void timeout_process(struct vdec_h264_hw_s *hw);
858static void dump_bufspec(struct vdec_h264_hw_s *hw,
859 const char *caller);
860static void h264_reconfig(struct vdec_h264_hw_s *hw);
861static void h264_reset_bufmgr(struct vdec_s *vdec);
862static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset);
863static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
864static int vh264_stop(struct vdec_h264_hw_s *hw);
865static s32 vh264_init(struct vdec_h264_hw_s *hw);
866static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
867 u32 index);
868static void release_aux_data(struct vdec_h264_hw_s *hw,
869 int buf_spec_num);
870#ifdef ERROR_HANDLE_TEST
871static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
872#endif
873
874#define H265_PUT_SAO_4K_SET 0x03
875#define H265_ABORT_SAO_4K_SET 0x04
876#define H265_ABORT_SAO_4K_SET_DONE 0x05
877
878#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
879#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
880#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
881#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
882#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
883
884
885#define HEVC_CM_HEADER_START_ADDR 0x3628
886#define HEVC_CM_BODY_START_ADDR 0x3626
887#define HEVC_CM_BODY_LENGTH 0x3627
888#define HEVC_CM_HEADER_LENGTH 0x3629
889#define HEVC_CM_HEADER_OFFSET 0x362b
890#define HEVC_SAO_CTRL9 0x362d
891#define HEVCD_MPP_DECOMP_CTL3 0x34c4
892#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
893#define HEVC_DBLK_CFGB 0x350b
894#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
895
896#define H265_DW_NO_SCALE
897#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
898#define H265_LOSLESS_COMPRESS_MODE
899#define MAX_FRAME_4K_NUM 0x1200
900#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
901
902/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
903static u32 mem_map_mode = H265_MEM_MAP_MODE;
904
905#define MAX_SIZE_8K (8192 * 4608)
906#define MAX_SIZE_4K (4096 * 2304)
907
908static int is_oversize(int w, int h)
909{
910 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
911 MAX_SIZE_8K : MAX_SIZE_4K;
912
913 if (w < 0 || h < 0)
914 return true;
915
916 if (h != 0 && (w > max / h))
917 return true;
918
919 return false;
920}
921
922static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
923 int frame_type,
924 u32 vpts,
925 u32 vpts_valid);
926static int compute_losless_comp_body_size(int width,
927 int height, int bit_depth_10);
928static int compute_losless_comp_header_size(int width, int height);
929
930static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
931 int pic_width, int pic_height, u16 bit_depth,
932 unsigned int *mmu_index_adr) {
933 int cur_buf_idx;
934 int bit_depth_10 = (bit_depth != 0x00);
935 int picture_size;
936 u32 cur_mmu_4k_number;
937
938 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
939 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
940 picture_size = compute_losless_comp_body_size(pic_width,
941 pic_height, bit_depth_10);
942 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
943 dpb_print(DECODE_ID(hw),
944 PRINT_FLAG_MMU_DETAIL,
945 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
946 cur_buf_idx, picture_size, cur_mmu_4k_number);
947
948 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
949 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
950 cur_mmu_4k_number);
951 return -1;
952 }
953
954 return decoder_mmu_box_alloc_idx(
955 hw->mmu_box,
956 cur_buf_idx,
957 cur_mmu_4k_number,
958 mmu_index_adr);
959}
960
961static int compute_losless_comp_body_size(int width,
962 int height, int bit_depth_10)
963{
964 int width_x64;
965 int height_x32;
966 int bsize;
967
968 width_x64 = width + 63;
969 width_x64 >>= 6;
970
971 height_x32 = height + 31;
972 height_x32 >>= 5;
973
974#ifdef H264_MMU
975 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
976#else
977 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
978#endif
979 return bsize;
980}
981
982static int compute_losless_comp_header_size(int width, int height)
983{
984 int width_x64;
985 int width_x128;
986 int height_x64;
987 int hsize;
988
989 width_x64 = width + 63;
990 width_x64 >>= 6;
991
992 width_x128 = width + 127;
993 width_x128 >>= 7;
994
995 height_x64 = height + 63;
996 height_x64 >>= 6;
997
998#ifdef H264_MMU
999 hsize = 128*width_x64*height_x64;
1000#else
1001 hsize = 32*width_x128*height_x64;
1002#endif
1003 return hsize;
1004}
1005
1006static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1007{
1008 int ratio = 1;
1009 int dw_mode = hw->double_write_mode;
1010 if ((dw_mode == 2) ||
1011 (dw_mode == 3))
1012 ratio = 4;
1013 else if (dw_mode == 4)
1014 ratio = 2;
1015 return ratio;
1016}
1017
1018
1019static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1020{
1021 int pic_width, pic_height;
1022 int lcu_size = 16;
1023 int dw_buf_size;
1024 u32 dw_buffer_size_u_v;
1025 u32 dw_buffer_size_u_v_h;
1026 int dw_mode = hw->double_write_mode;
1027
1028 pic_width = hw->frame_width;
1029 pic_height = hw->frame_height;
1030
1031 if (dw_mode) {
1032 int pic_width_dw = pic_width /
1033 get_double_write_ratio(hw);
1034 int pic_height_dw = pic_height /
1035 get_double_write_ratio(hw);
1036
1037 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1038 pic_width_dw / lcu_size + 1 :
1039 pic_width_dw / lcu_size;
1040 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1041 pic_height_dw / lcu_size + 1 :
1042 pic_height_dw / lcu_size;
1043 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1044
1045
1046 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1047 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1048 /*64k alignment*/
1049 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1050 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1051 } else {
1052 *pdw_buffer_size_u_v_h = 0;
1053 dw_buf_size = 0;
1054 }
1055
1056 return dw_buf_size;
1057}
1058
1059
1060static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1061{
1062 int i, size;
1063 u32 canvas_addr;
1064 unsigned long maddr;
1065 int num_buff = hw->dpb.mDPB.size;
1066 int dw_size = 0;
1067 u32 dw_buffer_size_u_v_h;
1068 u32 blkmode = hw->canvas_mode;
1069 int dw_mode = hw->double_write_mode;
1070
1071 canvas_addr = ANC0_CANVAS_ADDR;
1072 for (i = 0; i < num_buff; i++)
1073 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1074
1075 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1076 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1077
1078
1079 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1080 size += dw_size;
1081 if (size > 0)
1082 size += 0x10000;
1083
1084 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1085 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1086 dw_buffer_size_u_v_h, dw_size, size);
1087
1088 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1089 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1090 hw->losless_comp_body_size,
1091 hw->losless_comp_header_size,
1092 hw->losless_comp_body_size_sao);
1093
1094 for (i = 0; i < num_buff; i++) {
1095 if (!restore) {
1096 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1097 HEADER_BUFFER_IDX(i), size,
1098 DRIVER_HEADER_NAME, &maddr) < 0) {
1099 dpb_print(DECODE_ID(hw), 0,
1100 "%s malloc compress header failed %d\n",
1101 DRIVER_HEADER_NAME, i);
1102 return;
1103 }
1104 } else
1105 maddr = hw->buffer_spec[i].alloc_header_addr;
1106 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1107 hw->buffer_spec[i].alloc_header_addr = maddr;
1108 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1109 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1110 __func__, i, (u32)maddr, size);
1111
1112 if (dw_mode) {
1113 u32 addr;
1114 int canvas_w;
1115 int canvas_h;
1116
1117 canvas_w = hw->frame_width /
1118 get_double_write_ratio(hw);
1119 canvas_h = hw->frame_height /
1120 get_double_write_ratio(hw);
1121
1122 if (hw->canvas_mode == 0)
1123 canvas_w = ALIGN(canvas_w, 32);
1124 else
1125 canvas_w = ALIGN(canvas_w, 64);
1126 canvas_h = ALIGN(canvas_h, 32);
1127
1128 hw->buffer_spec[i].dw_y_adr =
1129 maddr + hw->losless_comp_header_size;
1130
1131 hw->buffer_spec[i].dw_y_adr =
1132 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1133 << 16;
1134 hw->buffer_spec[i].dw_u_v_adr =
1135 hw->buffer_spec[i].dw_y_adr
1136 + (dw_buffer_size_u_v_h << 16) * 2;
1137
1138
1139 hw->buffer_spec[i].buf_adr
1140 = hw->buffer_spec[i].dw_y_adr;
1141 addr = hw->buffer_spec[i].buf_adr;
1142
1143
1144 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1145 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1146 hw->buffer_spec[i].dw_y_adr,
1147 hw->buffer_spec[i].dw_u_v_adr,
1148 hw->buffer_spec[i].y_addr,
1149 hw->buffer_spec[i].u_addr,
1150 hw->buffer_spec[i].v_addr,
1151 canvas_w,
1152 canvas_h);
1153
1154 hw->buffer_spec[i].canvas_config[0].phy_addr =
1155 hw->buffer_spec[i].dw_y_adr;
1156 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1157 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1158 hw->buffer_spec[i].canvas_config[0].block_mode =
1159 blkmode;
1160 hw->buffer_spec[i].canvas_config[0].endian = 7;
1161
1162 hw->buffer_spec[i].canvas_config[1].phy_addr =
1163 hw->buffer_spec[i].dw_u_v_adr;
1164 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1165 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1166 hw->buffer_spec[i].canvas_config[1].block_mode =
1167 blkmode;
1168 hw->buffer_spec[i].canvas_config[1].endian = 7;
1169 }
1170 }
1171 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1172
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1174 for (i = 0; i < 32; i++)
1175 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1176 return;
1177}
1178static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1179{
1180 u32 i;
1181 u32 ref_canv;
1182 struct Slice *pSlice = &(hw->dpb.mSlice);
1183 /*REFLIST[0]*/
1184 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1185 struct StorablePicture *ref = pSlice->listX[0][i];
1186 if (ref == NULL)
1187 return;
1188 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1189 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1191 (ref->buf_spec_num & 0x3f) << 8);
1192 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1193 }
1194 /*REFLIST[1]*/
1195 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1196 struct StorablePicture *ref = pSlice->listX[1][i];
1197 if (ref == NULL)
1198 return;
1199 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1200 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1202 (ref->buf_spec_num & 0x3f) << 8);
1203 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1204 }
1205 return;
1206}
1207
1208static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1209{
1210 u32 rdata32;
1211 u32 rdata32_2;
1212 u32 slice_type;
1213 struct StorablePicture *ref;
1214 struct Slice *pSlice;
1215 slice_type = hw->dpb.mSlice.slice_type;
1216 pSlice = &(hw->dpb.mSlice);
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1218 if (slice_type == I_SLICE) {
1219 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1220 return;
1221 }
1222 if (slice_type == B_SLICE) {
1223 ref = pSlice->listX[0][0];
1224 if (ref == NULL)
1225 return;
1226 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1227 ((ref->buf_spec_num & 0x3f) << 8));
1228 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1229 rdata32 = rdata32 & 0xffff;
1230 rdata32 = rdata32 | (rdata32 << 16);
1231 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1232
1233 ref = pSlice->listX[1][0];
1234 if (ref == NULL)
1235 return;
1236 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1237 ((ref->buf_spec_num & 0x3f) << 8));
1238 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1239 rdata32_2 = rdata32_2 & 0xffff;
1240 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1241 if (rdata32 == rdata32_2) {
1242 ref = pSlice->listX[1][1];
1243 if (ref == NULL)
1244 return;
1245 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1246 ((ref->buf_spec_num & 0x3f) << 8));
1247 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1248 rdata32_2 = rdata32_2 & 0xffff;
1249 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1250 }
1251 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1252 } else { /*P-PIC*/
1253 ref = pSlice->listX[0][0];
1254 if (ref == NULL)
1255 return;
1256 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1257 ((ref->buf_spec_num & 0x3f) << 8));
1258 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1259 rdata32 = rdata32 & 0xffff;
1260 rdata32 = rdata32 | (rdata32 << 16);
1261 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1262
1263 ref = pSlice->listX[0][1];
1264 if (ref == NULL)
1265 return;
1266 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1267 ((ref->buf_spec_num & 0x3f) << 8));
1268 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1269 rdata32 = rdata32 & 0xffff;
1270 rdata32 = rdata32 | (rdata32 << 16);
1271 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1272 }
1273 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1274 return;
1275}
1276
1277
1278static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1279 u32 width, u32 height) {
1280 u32 data32;
1281 u32 lcu_x_num, lcu_y_num;
1282 u32 lcu_total;
1283 u32 mc_buffer_size_u_v;
1284 u32 mc_buffer_size_u_v_h;
1285 int dw_mode = hw->double_write_mode;
1286
1287 lcu_x_num = (width + 15) >> 4;
1288 lcu_y_num = (height + 15) >> 4;
1289 lcu_total = lcu_x_num * lcu_y_num;
1290
1291 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1292 hw->mc_buffer_size_u_v_h =
1293 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1294
1295 hw->losless_comp_body_size = 0;
1296
1297 hw->losless_comp_body_size_sao =
1298 compute_losless_comp_body_size(width, height, 0);
1299 hw->losless_comp_header_size =
1300 compute_losless_comp_header_size(width, height);
1301
1302 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1303 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1304
1305 /* setup lcu_size = 16*/
1306 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1307 /*pic_width/pic_height*/
1308 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1309 (height & 0xffff) << 16 | (width & 0xffff));
1310 /* bitdepth_luma = 8*/
1311 /* bitdepth_chroma = 8*/
1312 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1313
1314#ifdef H265_LOSLESS_COMPRESS_MODE
1315 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1317#else
1318 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1319#endif
1320 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1321 data32 &= (~0x30);
1322 data32 |= (hw->canvas_mode << 4);
1323 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1324
1325 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1326 (0x80 << 20) | (0x80 << 10) | (0xff));
1327
1328 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1329
1330 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1331 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1332 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1333 /* ipp_enable*/
1334 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1335
1336 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1337 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1338 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1339 if (dw_mode)
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1341 else
1342 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1343 }
1344
1345 data32 = READ_VREG(HEVC_SAO_CTRL0);
1346 data32 &= (~0xf);
1347 data32 |= 0x4;
1348 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1349 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1350 (width & 0xffff));
1351 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1352
1353 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1354 data32 = (lcu_x_num | lcu_y_num << 16);
1355 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1357 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1358 data32 = (mc_buffer_size_u_v_h << 16);
1359 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1360
1361 data32 = READ_VREG(HEVC_SAO_CTRL1);
1362 data32 &= (~0x3000);
1363 data32 &= (~0xff0);
1364 data32 |= endian; /* Big-Endian per 64-bit */
1365
1366 if (hw->mmu_enable && dw_mode)
1367 data32 |= ((hw->canvas_mode << 12));
1368 else
1369 data32 |= ((hw->canvas_mode << 12)|2);
1370
1371 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1372
1373#ifdef H265_DW_NO_SCALE
1374 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1375 if (hw->mmu_enable && dw_mode) {
1376 data32 = READ_VREG(HEVC_SAO_CTRL5);
1377 data32 &= (~(0xff << 16));
1378 if (dw_mode == 2 ||
1379 dw_mode == 3)
1380 data32 |= (0xff<<16);
1381 else if (dw_mode == 4)
1382 data32 |= (0x33<<16);
1383 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1384 }
1385
1386
1387#endif
1388
1389
1390#ifdef H265_LOSLESS_COMPRESS_MODE
1391 data32 = READ_VREG(HEVC_SAO_CTRL5);
1392 data32 |= (1<<9); /*8-bit smem-mode*/
1393 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1394
1395 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1396 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1397 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1398#endif
1399
1400#ifdef H265_LOSLESS_COMPRESS_MODE
1401 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1402 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1403#endif
1404
1405 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1406
1407 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1408
1409 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1410 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1411 return;
1412}
1413
1414static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1415 u32 is_new_pic, u32 is_idr)
1416{
1417 hw->is_new_pic = is_new_pic;
1418 hw->is_idr_frame = is_idr;
1419 return;
1420}
1421
1422static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1423 struct StorablePicture *pic) {
1424 u32 mc_y_adr;
1425 u32 mc_u_v_adr;
1426 u32 dw_y_adr;
1427 u32 dw_u_v_adr;
1428 u32 canvas_addr;
1429 int ret;
1430 int dw_mode = hw->double_write_mode;
1431 if (hw->is_new_pic != 1)
1432 return;
1433
1434 if (hw->is_idr_frame) {
1435 /* William TBD */
1436 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1437 }
1438
1439 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1440 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1441 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1442 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1443 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1444 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1445 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1446 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1447 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1448
1449
1450 if (dw_mode) {
1451 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1452 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1453 } else {
1454 dw_y_adr = 0;
1455 dw_u_v_adr = 0;
1456 }
1457#ifdef H265_LOSLESS_COMPRESS_MODE
1458 if (dw_mode)
1459 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1460 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1461#ifdef H264_MMU
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1463#else
1464 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1465 (mc_y_adr + hw->losless_comp_body_size));
1466#endif
1467#else
1468 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1469#endif
1470
1471#ifndef H265_LOSLESS_COMPRESS_MODE
1472 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1473#else
1474 if (dw_mode)
1475 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1476#endif
1477
1478#ifndef LOSLESS_COMPRESS_MODE
1479 if (dw_mode) {
1480 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1481 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1482 }
1483#else
1484 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1485 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1486#endif
1487
1488 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1489 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1490 hw->frame_mmu_map_addr);
1491 if (ret != 0) {
1492 dpb_print(DECODE_ID(hw),
1493 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1494 pic->buf_spec_num,
1495 ret);
1496 return;
1497 }
1498
1499 /*Reset SAO + Enable SAO slice_start*/
1500 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1501 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1504 WRITE_VREG(HEVC_SAO_INT_STATUS,
1505 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1506 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1507 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1508
1509 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1510 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1511 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1512 } else
1513 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1514 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1515 hw->frame_busy = 1;
1516 return;
1517}
1518
1519
1520static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1521 u32 buf_spec_num) {
1522 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1523 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1524 dpb_print(DECODE_ID(hw),
1525 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1526 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1527 return;
1528}
1529
1530
1531static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1532{
1533 ulong timeout = jiffies + HZ;
1534 dpb_print(DECODE_ID(hw),
1535 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1536 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1537 if (time_after(jiffies, timeout)) {
1538 dpb_print(DECODE_ID(hw),
1539 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1540 break;
1541 }
1542 }
1543 timeout = jiffies + HZ;
1544 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1545 if (time_after(jiffies, timeout)) {
1546 dpb_print(DECODE_ID(hw),
1547 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1548 break;
1549 }
1550 }
1551 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1552 hw->frame_done = 1;
1553 return;
1554}
1555
1556static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1557{
1558 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1559 if (p_H264_Dpb->mVideo.dec_picture) {
1560 release_picture(p_H264_Dpb,
1561 p_H264_Dpb->mVideo.dec_picture);
1562 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1563 p_H264_Dpb->mVideo.dec_picture = NULL;
1564 if (hw->mmu_enable)
1565 hevc_set_frame_done(hw);
1566 }
1567}
1568
1569static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1570{
1571 ulong timeout = jiffies + HZ;
1572 dpb_print(DECODE_ID(hw),
1573 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1574 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1575 if (time_after(jiffies, timeout)) {
1576 dpb_print(DECODE_ID(hw),
1577 PRINT_FLAG_MMU_DETAIL,
1578 "hevc_sao_wait_done...wait timeout!\n");
1579 break;
1580 }
1581 }
1582 timeout = jiffies + HZ;
1583 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1584 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1585 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1586 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1587 H265_ABORT_SAO_4K_SET_DONE) {
1588 if (time_after(jiffies, timeout)) {
1589 dpb_print(DECODE_ID(hw),
1590 PRINT_FLAG_MMU_DETAIL,
1591 "wait h265_abort_sao_4k_set_done timeout!\n");
1592 break;
1593 }
1594 }
1595 }
1596 amhevc_stop();
1597 hw->frame_busy = 0;
1598 hw->frame_done = 0;
1599 dpb_print(DECODE_ID(hw),
1600 PRINT_FLAG_MMU_DETAIL,
1601 "sao wait done ,hevc stop!\n");
1602 }
1603 return;
1604}
1605static void buf_spec_init(struct vdec_h264_hw_s *hw)
1606{
1607 int i;
1608 unsigned long flags;
1609 spin_lock_irqsave(&hw->bufspec_lock, flags);
1610
1611 for (i = 0; i < VF_POOL_SIZE; i++) {
1612 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1613 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1614 if ((vf->index != -1) &&
1615 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1616 (hw->buffer_spec[ref_idx].used != -1)) {
1617 vf->index = -1;
1618 }
1619 }
1620
1621 hw->cur_pool++;
1622 if (hw->cur_pool >= VF_POOL_NUM)
1623 hw->cur_pool = 0;
1624
1625 for (i = 0; i < VF_POOL_SIZE; i++) {
1626 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1627 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1628 if ((vf->index != -1) &&
1629 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1630 (hw->buffer_spec[ref_idx].used != -1)) {
1631 vf->index = -1;
1632 }
1633 }
1634
1635 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1636 hw->buffer_spec[i].used = -1;
1637 hw->buffer_spec[i].canvas_pos = -1;
1638 }
1639
1640 if (dpb_is_debug(DECODE_ID(hw),
1641 PRINT_FLAG_DUMP_BUFSPEC))
1642 dump_bufspec(hw, __func__);
1643 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1644}
1645
1646/*is active in buf management */
1647static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1648 int buf_spec_num)
1649{
1650 unsigned char ret = 0;
1651 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1652 hw->buffer_spec[buf_spec_num].used == 2 ||
1653 hw->buffer_spec[buf_spec_num].used == 3 ||
1654 hw->buffer_spec[buf_spec_num].used == 5)
1655 ret = 1;
1656 return ret;
1657}
1658
1659static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1660 int buf_spec_num)
1661{
1662 unsigned char ret = 0;
1663 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1664 hw->buffer_spec[buf_spec_num].used == 3 ||
1665 hw->buffer_spec[buf_spec_num].used == 5)
1666 ret = 1;
1667 return ret;
1668}
1669
1670static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1671{
1672 if (hw->mmu_enable) {
1673 if (hw->buffer_spec[i].alloc_header_addr)
1674 return 0;
1675 else
1676 return -1;
1677 } else {
1678
1679 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1680 int addr;
1681#ifdef VDEC_DW
1682 int orig_buf_size;
1683 orig_buf_size = buf_size;
1684 if (IS_VDEC_DW(hw) == 1)
1685 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1686 else if (IS_VDEC_DW(hw) == 2)
1687 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1688#endif
1689 if (hw->buffer_spec[i].cma_alloc_addr)
1690 return 0;
1691
1692 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1693 PAGE_ALIGN(buf_size), DRIVER_NAME,
1694 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1695 hw->buffer_spec[i].cma_alloc_addr = 0;
1696 if (hw->no_mem_count++ > 3) {
1697 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1698 hw->reset_bufmgr_flag = 1;
1699 }
1700 dpb_print(DECODE_ID(hw), 0,
1701 "%s, fail to alloc buf for bufspec%d, try later\n",
1702 __func__, i
1703 );
1704 return -1;
1705 } else {
1706 hw->no_mem_count = 0;
1707 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1708 }
1709
1710 hw->buffer_spec[i].buf_adr =
1711 hw->buffer_spec[i].cma_alloc_addr;
1712 addr = hw->buffer_spec[i].buf_adr;
1713
1714
1715 hw->buffer_spec[i].y_addr = addr;
1716 addr += hw->mb_total << 8;
1717 hw->buffer_spec[i].u_addr = addr;
1718 hw->buffer_spec[i].v_addr = addr;
1719 addr += hw->mb_total << 7;
1720
1721 hw->buffer_spec[i].canvas_config[0].phy_addr =
1722 hw->buffer_spec[i].y_addr;
1723 hw->buffer_spec[i].canvas_config[0].width =
1724 hw->mb_width << 4;
1725 hw->buffer_spec[i].canvas_config[0].height =
1726 hw->mb_height << 4;
1727 hw->buffer_spec[i].canvas_config[0].block_mode =
1728 hw->canvas_mode;
1729
1730 hw->buffer_spec[i].canvas_config[1].phy_addr =
1731 hw->buffer_spec[i].u_addr;
1732 hw->buffer_spec[i].canvas_config[1].width =
1733 hw->mb_width << 4;
1734 hw->buffer_spec[i].canvas_config[1].height =
1735 hw->mb_height << 3;
1736 hw->buffer_spec[i].canvas_config[1].block_mode =
1737 hw->canvas_mode;
1738 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1739 "%s, alloc buf for bufspec%d\n",
1740 __func__, i
1741 );
1742#ifdef VDEC_DW
1743
1744 if (!IS_VDEC_DW(hw))
1745 return 0;
1746 else if (IS_VDEC_DW(hw) == 1) {
1747 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1748 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1749 addr += hw->mb_total << 7;
1750 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1751 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1752 addr += hw->mb_total << 6;
1753
1754 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1755 hw->buffer_spec[i].vdec_dw_y_addr;
1756 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1757 hw->mb_width << 3;
1758 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1759 hw->mb_height << 4;
1760 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1761 CANVAS_BLKMODE_32X32;
1762
1763 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1764 hw->buffer_spec[i].vdec_dw_u_addr;
1765 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1766 hw->mb_width << 3;
1767 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1768 hw->mb_height << 3;
1769 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1770 CANVAS_BLKMODE_32X32;
1771 }else {
1772 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1773 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1774 addr += hw->mb_total << 6;
1775 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1776 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1777 addr += hw->mb_total << 5;
1778
1779 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1780 hw->buffer_spec[i].vdec_dw_y_addr;
1781 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1782 hw->mb_width << 3;
1783 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1784 hw->mb_height << 3;
1785 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1786 CANVAS_BLKMODE_32X32;
1787
1788 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1789 hw->buffer_spec[i].vdec_dw_u_addr;
1790 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1791 hw->mb_width << 3;
1792 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1793 hw->mb_height << 2;
1794 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1795 CANVAS_BLKMODE_32X32;
1796 }
1797 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1798 "%s, vdec_dw: alloc buf for bufspec%d\n",
1799 __func__, i
1800 );
1801#endif
1802 }
1803 return 0;
1804}
1805
1806static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1807{
1808 int ret = 0;
1809 struct aml_vcodec_ctx *ctx = NULL;
1810 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1811 struct canvas_config_s *y_canvas_cfg = NULL;
1812 struct canvas_config_s *c_canvas_cfg = NULL;
1813 struct vdec_v4l2_buffer *fb = NULL;
1814 unsigned int y_addr = 0, c_addr = 0;
1815
1816 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1817 pr_err("the v4l context has err.\n");
1818 return -1;
1819 }
1820
1821 if (bs->cma_alloc_addr)
1822 return 0;
1823
1824 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1825 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1826 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1827 ctx->id, __func__,
1828 (hw->mb_total << 8) + (hw->mb_total << 7));
1829
1830 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1831 if (ret < 0) {
1832 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1833 "[%d] get fb fail.\n", ctx->id);
1834 return ret;
1835 }
1836
1837 bs->cma_alloc_addr = (unsigned long)fb;
1838 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1839 "[%d] %s(), cma alloc addr: 0x%x\n",
1840 ctx->id, __func__, bs->cma_alloc_addr);
1841
1842 if (fb->num_planes == 1) {
1843 y_addr = fb->m.mem[0].addr;
1844 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1845 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1846 } else if (fb->num_planes == 2) {
1847 y_addr = fb->m.mem[0].addr;
1848 c_addr = fb->m.mem[1].addr;
1849 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1850 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1851 }
1852
1853 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1854 "[%d] %s(), y_addr: %x, size: %u\n",
1855 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1856 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1857 "[%d] %s(), c_addr: %x, size: %u\n",
1858 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1859
1860 bs->y_addr = y_addr;
1861 bs->u_addr = c_addr;
1862 bs->v_addr = c_addr;
1863
1864 y_canvas_cfg = &bs->canvas_config[0];
1865 c_canvas_cfg = &bs->canvas_config[1];
1866
1867 y_canvas_cfg->phy_addr = y_addr;
1868 y_canvas_cfg->width = hw->mb_width << 4;
1869 y_canvas_cfg->height = hw->mb_height << 4;
1870 y_canvas_cfg->block_mode = hw->canvas_mode;
1871 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1872 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1873 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1874 y_canvas_cfg->width,y_canvas_cfg->height);
1875
1876 c_canvas_cfg->phy_addr = c_addr;
1877 c_canvas_cfg->width = hw->mb_width << 4;
1878 c_canvas_cfg->height = hw->mb_height << 3;
1879 c_canvas_cfg->block_mode = hw->canvas_mode;
1880 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1881 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1882 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1883 c_canvas_cfg->width, c_canvas_cfg->height);
1884
1885 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1886 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1887
1888 return ret;
1889}
1890
1891static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1892{
1893 int blkmode = hw->canvas_mode;
1894 int endian = 0;
1895
1896 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1897 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1898 endian = 7;
1899 else
1900 endian = 0;
1901 }
1902
1903 if (hw->is_used_v4l)
1904 endian = 7;
1905
1906 canvas_config_ex(hw->buffer_spec[i].
1907 y_canvas_index,
1908 hw->buffer_spec[i].y_addr,
1909 hw->mb_width << 4,
1910 hw->mb_height << 4,
1911 CANVAS_ADDR_NOWRAP,
1912 blkmode,
1913 endian);
1914
1915 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1916 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1917 (1 << 11) | /* canvas_blk32_wr */
1918 (blkmode << 10) | /* canvas_blk32*/
1919 (1 << 8) | /* canvas_index_wr*/
1920 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1921 );
1922 }
1923
1924 canvas_config_ex(hw->buffer_spec[i].
1925 u_canvas_index,
1926 hw->buffer_spec[i].u_addr,
1927 hw->mb_width << 4,
1928 hw->mb_height << 3,
1929 CANVAS_ADDR_NOWRAP,
1930 blkmode,
1931 endian);
1932
1933 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1934 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1935 (1 << 11) |
1936 (blkmode << 10) |
1937 (1 << 8) |
1938 (hw->buffer_spec[i].u_canvas_index << 0));
1939 }
1940
1941 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1942 spec2canvas(&hw->buffer_spec[i]));
1943
1944
1945#ifdef VDEC_DW
1946 if (!IS_VDEC_DW(hw))
1947 return;
1948 else if (IS_VDEC_DW(hw) == 1) {
1949 canvas_config_ex(hw->buffer_spec[i].
1950 vdec_dw_y_canvas_index,
1951 hw->buffer_spec[i].vdec_dw_y_addr,
1952 hw->mb_width << 3,
1953 hw->mb_height << 4,
1954 CANVAS_ADDR_NOWRAP,
1955 blkmode,
1956 endian);
1957 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1958 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1959 (1 << 11) |
1960 (blkmode << 10) |
1961 (1 << 8) |
1962 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1963 }
1964 canvas_config_ex(hw->buffer_spec[i].
1965 vdec_dw_u_canvas_index,
1966 hw->buffer_spec[i].vdec_dw_u_addr,
1967 hw->mb_width << 3,
1968 hw->mb_height << 3,
1969 CANVAS_ADDR_NOWRAP,
1970 blkmode,
1971 endian);
1972 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1973 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1974 (1 << 11) |
1975 (blkmode << 10) |
1976 (1 << 8) |
1977 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1978 }
1979 } else {
1980 canvas_config_ex(hw->buffer_spec[i].
1981 vdec_dw_y_canvas_index,
1982 hw->buffer_spec[i].vdec_dw_y_addr,
1983 hw->mb_width << 3,
1984 hw->mb_height << 3,
1985 CANVAS_ADDR_NOWRAP,
1986 blkmode,
1987 endian);
1988 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1989 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1990 (1 << 11) |
1991 (blkmode << 10) |
1992 (1 << 8) |
1993 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1994 }
1995
1996 canvas_config_ex(hw->buffer_spec[i].
1997 vdec_dw_u_canvas_index,
1998 hw->buffer_spec[i].vdec_dw_u_addr,
1999 hw->mb_width << 3,
2000 hw->mb_height << 2,
2001 CANVAS_ADDR_NOWRAP,
2002 blkmode,
2003 endian);
2004 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2005 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2006 (1 << 11) |
2007 (blkmode << 10) |
2008 (1 << 8) |
2009 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
2010 }
2011 }
2012#endif
2013}
2014
2015static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
2016{
2017 u32 blkmode = hw->canvas_mode;
2018 int canvas_w;
2019 int canvas_h;
2020
2021 canvas_w = hw->frame_width /
2022 get_double_write_ratio(hw);
2023 canvas_h = hw->frame_height /
2024 get_double_write_ratio(hw);
2025
2026 if (hw->canvas_mode == 0)
2027 canvas_w = ALIGN(canvas_w, 32);
2028 else
2029 canvas_w = ALIGN(canvas_w, 64);
2030 canvas_h = ALIGN(canvas_h, 32);
2031
2032 canvas_config_ex(hw->buffer_spec[i].
2033 y_canvas_index,
2034 hw->buffer_spec[i].dw_y_adr,
2035 canvas_w,
2036 canvas_h,
2037 CANVAS_ADDR_NOWRAP,
2038 blkmode,
2039 7);
2040
2041 canvas_config_ex(hw->buffer_spec[i].
2042 u_canvas_index,
2043 hw->buffer_spec[i].dw_u_v_adr,
2044 canvas_w,
2045 canvas_h,
2046 CANVAS_ADDR_NOWRAP,
2047 blkmode,
2048 7);
2049}
2050
2051static int v4l_get_free_buf_idx(struct vdec_s *vdec)
2052{
2053 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2054 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2055 struct v4l_buff_pool *pool = &v4l->cap_pool;
2056 struct buffer_spec_s *pic = NULL;
2057 int i, idx = INVALID_IDX;
2058 ulong flags;
2059
2060 spin_lock_irqsave(&hw->bufspec_lock, flags);
2061 for (i = 0; i < pool->in; ++i) {
2062 u32 state = (pool->seq[i] >> 16);
2063 u32 index = (pool->seq[i] & 0xffff);
2064
2065 switch (state) {
2066 case V4L_CAP_BUFF_IN_DEC:
2067 pic = &hw->buffer_spec[i];
2068 if ((pic->vf_ref == 0) &&
2069 (pic->used == 0) &&
2070 pic->cma_alloc_addr) {
2071 idx = i;
2072 }
2073 break;
2074 case V4L_CAP_BUFF_IN_M2M:
2075 pic = &hw->buffer_spec[index];
2076 if (!alloc_one_buf_spec_from_queue(hw, index)) {
2077 config_decode_canvas(hw, index);
2078 idx = index;
2079 }
2080 break;
2081 default:
2082 pr_err("v4l buffer state err %d.\n", state);
2083 break;
2084 }
2085
2086 if (idx != INVALID_IDX) {
2087 pic->used = 1;
2088 break;
2089 }
2090 }
2091 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2092
2093 if (idx < 0) {
2094 dpb_print(DECODE_ID(hw), 0, "%s fail\n", __func__);
2095 vmh264_dump_state(vdec);
2096 }
2097
2098 return idx;
2099}
2100
2101int get_free_buf_idx(struct vdec_s *vdec)
2102{
2103 int i;
2104 unsigned long addr, flags;
2105 int index = -1;
2106 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2107 int buf_total = BUFSPEC_POOL_SIZE;
2108
2109 if (hw->is_used_v4l)
2110 return v4l_get_free_buf_idx(vdec);
2111
2112 spin_lock_irqsave(&hw->bufspec_lock, flags);
2113 /*hw->start_search_pos = 0;*/
2114 for (i = hw->start_search_pos; i < buf_total; i++) {
2115 if (hw->mmu_enable)
2116 addr = hw->buffer_spec[i].alloc_header_addr;
2117 else
2118 addr = hw->buffer_spec[i].cma_alloc_addr;
2119
2120 if (hw->buffer_spec[i].vf_ref == 0 &&
2121 hw->buffer_spec[i].used == 0 && addr) {
2122 hw->buffer_spec[i].used = 1;
2123 hw->start_search_pos = i+1;
2124 index = i;
2125 break;
2126 }
2127 }
2128 if (index < 0) {
2129 for (i = 0; i < hw->start_search_pos; i++) {
2130 if (hw->mmu_enable)
2131 addr = hw->buffer_spec[i].alloc_header_addr;
2132 else
2133 addr = hw->buffer_spec[i].cma_alloc_addr;
2134
2135 if (hw->buffer_spec[i].vf_ref == 0 &&
2136 hw->buffer_spec[i].used == 0 && addr) {
2137 hw->buffer_spec[i].used = 1;
2138 hw->start_search_pos = i+1;
2139 index = i;
2140 break;
2141 }
2142 }
2143 }
2144 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2145 if (hw->start_search_pos >= buf_total)
2146 hw->start_search_pos = 0;
2147 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2148 "%s, buf_spec_num %d\n", __func__, index);
2149
2150 if (index < 0) {
2151 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2152 "%s fail\n", __func__);
2153 vmh264_dump_state(vdec);
2154 }
2155
2156 if (dpb_is_debug(DECODE_ID(hw),
2157 PRINT_FLAG_DUMP_BUFSPEC))
2158 dump_bufspec(hw, __func__);
2159 return index;
2160}
2161
2162int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2163{
2164 /*u32 cur_buf_idx;*/
2165 unsigned long flags;
2166 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2167 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2168 "%s buf_spec_num %d used %d\n",
2169 __func__, buf_spec_num,
2170 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2171 if (buf_spec_num >= 0 &&
2172 buf_spec_num < BUFSPEC_POOL_SIZE
2173 ) {
2174 spin_lock_irqsave(&hw->bufspec_lock, flags);
2175 hw->buffer_spec[buf_spec_num].used = 0;
2176 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2177 if (hw->mmu_enable) {
2178 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2179 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2180 cur_buf_idx = cur_buf_idx&0xff;*/
2181 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2182 }
2183 release_aux_data(hw, buf_spec_num);
2184 }
2185 if (dpb_is_debug(DECODE_ID(hw),
2186 PRINT_FLAG_DUMP_BUFSPEC))
2187 dump_bufspec(hw, __func__);
2188 return 0;
2189}
2190
2191static void config_buf_specs(struct vdec_s *vdec)
2192{
2193 int i, j;
2194 unsigned long flags;
2195 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2196 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2197
2198 spin_lock_irqsave(&hw->bufspec_lock, flags);
2199 for (i = 0, j = 0;
2200 j < hw->dpb.mDPB.size
2201 && i < BUFSPEC_POOL_SIZE;
2202 i++) {
2203 int canvas;
2204 if (hw->buffer_spec[i].used != -1)
2205 continue;
2206 if (vdec->parallel_dec == 1) {
2207 if (hw->buffer_spec[i].y_canvas_index == -1)
2208 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2209 if (hw->buffer_spec[i].u_canvas_index == -1) {
2210 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2211 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2212 }
2213#ifdef VDEC_DW
2214 if (IS_VDEC_DW(hw)) {
2215 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2216 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2217 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2218 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2219 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2220 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2221 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2222 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2223 }
2224 }
2225#endif
2226 } else {
2227 canvas = vdec->get_canvas(j * mode, 2);
2228 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2229 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2230 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2231 dpb_print(DECODE_ID(hw),
2232 PRINT_FLAG_DPB_DETAIL,
2233 "config canvas (%d) %x for bufspec %d\r\n",
2234 j, canvas, i);
2235#ifdef VDEC_DW
2236 if (IS_VDEC_DW(hw)) {
2237 canvas = vdec->get_canvas(j * mode + 1, 2);
2238 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2239 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2240 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2241 dpb_print(DECODE_ID(hw),
2242 PRINT_FLAG_DPB_DETAIL,
2243 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2244 j, canvas, i);
2245 }
2246#endif
2247 }
2248
2249 hw->buffer_spec[i].used = 0;
2250 hw->buffer_spec[i].canvas_pos = j;
2251
2252
2253 j++;
2254 }
2255 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2256}
2257
2258static void config_buf_specs_ex(struct vdec_s *vdec)
2259{
2260 int i, j;
2261 unsigned long flags;
2262 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2263 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2264
2265 spin_lock_irqsave(&hw->bufspec_lock, flags);
2266 for (i = 0, j = 0;
2267 j < hw->dpb.mDPB.size
2268 && i < BUFSPEC_POOL_SIZE;
2269 i++) {
2270 int canvas = 0;
2271 if (hw->buffer_spec[i].used != -1)
2272 continue;
2273 if (vdec->parallel_dec == 1) {
2274 if (hw->buffer_spec[i].y_canvas_index == -1)
2275 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2276 if (hw->buffer_spec[i].u_canvas_index == -1) {
2277 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2278 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2279 }
2280#ifdef VDEC_DW
2281 if (IS_VDEC_DW(hw)) {
2282 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2283 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2284 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2285 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2286 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2287 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2288 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2289 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2290 }
2291 }
2292#endif
2293 } else {
2294 canvas = vdec->get_canvas(j* mode, 2);
2295 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2296 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2297 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2298
2299 dpb_print(DECODE_ID(hw),
2300 PRINT_FLAG_DPB_DETAIL,
2301 "config canvas (%d) %x for bufspec %d\r\n",
2302 j, canvas, i);
2303#ifdef VDEC_DW
2304 if (IS_VDEC_DW(hw)) {
2305 canvas = vdec->get_canvas(j*mode + 1, 2);
2306 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2307 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2308 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2309 dpb_print(DECODE_ID(hw),
2310 PRINT_FLAG_DPB_DETAIL,
2311 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2312 j, canvas, i);
2313 }
2314#endif
2315 }
2316
2317 hw->buffer_spec[i].used = 0;
2318 hw->buffer_spec[i].alloc_header_addr = 0;
2319 hw->buffer_spec[i].canvas_pos = j;
2320
2321 j++;
2322 }
2323 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2324}
2325
2326
2327static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2328 unsigned char release_all)
2329{
2330 int i;
2331 unsigned long flags;
2332 unsigned char dealloc_flag = 0;
2333 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2334 if (hw->buffer_spec[i].used == 4 ||
2335 release_all) {
2336 dealloc_flag = 1;
2337 dpb_print(DECODE_ID(hw),
2338 PRINT_FLAG_DPB_DETAIL,
2339 "%s buf_spec_num %d\n",
2340 __func__, i
2341 );
2342 spin_lock_irqsave
2343 (&hw->bufspec_lock, flags);
2344 hw->buffer_spec[i].used = -1;
2345 spin_unlock_irqrestore
2346 (&hw->bufspec_lock, flags);
2347 release_aux_data(hw, i);
2348
2349 if (!hw->mmu_enable) {
2350 if (hw->buffer_spec[i].cma_alloc_addr) {
2351 if (!hw->is_used_v4l) {
2352 decoder_bmmu_box_free_idx(
2353 hw->bmmu_box,
2354 i);
2355 }
2356 spin_lock_irqsave
2357 (&hw->bufspec_lock, flags);
2358 hw->buffer_spec[i].cma_alloc_addr = 0;
2359 hw->buffer_spec[i].buf_adr = 0;
2360 spin_unlock_irqrestore
2361 (&hw->bufspec_lock, flags);
2362 }
2363 } else {
2364 if (hw->buffer_spec[i].alloc_header_addr) {
2365 decoder_mmu_box_free_idx(
2366 hw->mmu_box,
2367 i);
2368 spin_lock_irqsave
2369 (&hw->bufspec_lock, flags);
2370 hw->buffer_spec[i].
2371 alloc_header_addr = 0;
2372 hw->buffer_spec[i].buf_adr = 0;
2373 spin_unlock_irqrestore
2374 (&hw->bufspec_lock, flags);
2375 }
2376 }
2377 }
2378 }
2379 if (dealloc_flag &&
2380 dpb_is_debug(DECODE_ID(hw),
2381 PRINT_FLAG_DUMP_BUFSPEC))
2382 dump_bufspec(hw, __func__);
2383 return;
2384}
2385
2386unsigned char have_free_buf_spec(struct vdec_s *vdec)
2387{
2388 int i;
2389 unsigned long addr;
2390 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2391 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2392 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2393 int index = -1;
2394 int ret = 0;
2395 int allocated_count = 0;
2396
2397 if (hw->is_used_v4l) {
2398 for (i = 0; i < hw->dpb.mDPB.size; i++) {
2399 if (hw->buffer_spec[i].used == 0 &&
2400 hw->buffer_spec[i].vf_ref == 0 &&
2401 hw->buffer_spec[i].cma_alloc_addr) {
2402 return 1;
2403 }
2404 }
2405
2406 if (v4l2_m2m_num_dst_bufs_ready(v4l->m2m_ctx)
2407 >= run_ready_min_buf_num)
2408 return 1;
2409
2410 return 0;
2411 }
2412
2413 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2414 if (hw->mmu_enable)
2415 addr = hw->buffer_spec[i].alloc_header_addr;
2416 else
2417 addr = hw->buffer_spec[i].cma_alloc_addr;
2418 if (hw->buffer_spec[i].used == 0 &&
2419 hw->buffer_spec[i].vf_ref == 0) {
2420
2421 if (addr)
2422 return 1;
2423 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2424 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2425 index = i;
2426 }
2427 }
2428 if (addr)
2429 allocated_count++;
2430 }
2431 if (index >= 0) {
2432 mutex_lock(&vmh264_mutex);
2433 dealloc_buf_specs(hw, 0);
2434 if (max_alloc_buf_count == 0 ||
2435 allocated_count < max_alloc_buf_count) {
2436 if (alloc_one_buf_spec(hw, index) >= 0)
2437 ret = 1;
2438 }
2439 mutex_unlock(&vmh264_mutex);
2440 }
2441
2442 return ret;
2443}
2444
2445static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2446 int canvas_pos)
2447{
2448 int i;
2449 int j = 0;
2450 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2451 if (hw->buffer_spec[i].canvas_pos >= 0) {
2452 if (j == canvas_pos)
2453 return i;
2454 j++;
2455 }
2456 }
2457 return -1;
2458}
2459static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2460 struct vframe_s *vf, int index)
2461{
2462 if (index < 0) {
2463 vf->mem_handle = NULL;
2464 vf->mem_head_handle = NULL;
2465 } else if (vf->type & VIDTYPE_SCATTER) {
2466 vf->mem_handle =
2467 decoder_mmu_box_get_mem_handle(
2468 hw->mmu_box, index);
2469 vf->mem_head_handle =
2470 decoder_bmmu_box_get_mem_handle(
2471 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2472 } else {
2473 vf->mem_handle =
2474 decoder_bmmu_box_get_mem_handle(
2475 hw->bmmu_box, VF_BUFFER_IDX(index));
2476 /* vf->mem_head_handle =
2477 decoder_bmmu_box_get_mem_handle(
2478 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2479 }
2480 return;
2481}
2482static int check_force_interlace(struct vdec_h264_hw_s *hw,
2483 struct FrameStore *frame)
2484{
2485 int bForceInterlace = 0;
2486 /* no di in secure mode, disable force di */
2487 if (vdec_secure(hw_to_vdec(hw)))
2488 return 0;
2489 if (frame->frame) {
2490 if (frame->frame->coded_frame
2491 && !frame->frame->frame_mbs_only_flag) {
2492 if (frame->frame->structure == FRAME)
2493 return 1;
2494 }
2495 }
2496
2497 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2498 && hw->bitstream_restriction_flag
2499 && (hw->frame_width == 1920)
2500 && (hw->frame_height >= 1080)
2501 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2502 bForceInterlace = 1;
2503 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2504 && (hw->frame_width == 720)
2505 && (hw->frame_height == 576)
2506 && (hw->frame_dur == 3840)) {
2507 bForceInterlace = 1;
2508 }
2509
2510 return bForceInterlace;
2511}
2512
2513static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2514{
2515 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2516 if (frame->slice_type == I_SLICE)
2517 vframe_qos->type = 1;
2518 else if (frame->slice_type == P_SLICE)
2519 vframe_qos->type = 2;
2520 else if (frame->slice_type == B_SLICE)
2521 vframe_qos->type = 3;
2522
2523 vframe_qos->size = frame->frame_size;
2524 vframe_qos->pts = frame->pts64;
2525
2526 vframe_qos->max_mv = frame->max_mv;
2527 vframe_qos->avg_mv = frame->avg_mv;
2528 vframe_qos->min_mv = frame->min_mv;
2529/*
2530 pr_info("mv: max:%d, avg:%d, min:%d\n",
2531 vframe_qos->max_mv,
2532 vframe_qos->avg_mv,
2533 vframe_qos->min_mv);
2534*/
2535
2536 vframe_qos->max_qp = frame->max_qp;
2537 vframe_qos->avg_qp = frame->avg_qp;
2538 vframe_qos->min_qp = frame->min_qp;
2539/*
2540 pr_info("qp: max:%d, avg:%d, min:%d\n",
2541 vframe_qos->max_qp,
2542 vframe_qos->avg_qp,
2543 vframe_qos->min_qp);
2544*/
2545
2546 vframe_qos->max_skip = frame->max_skip;
2547 vframe_qos->avg_skip = frame->avg_skip;
2548 vframe_qos->min_skip = frame->min_skip;
2549/*
2550 pr_info("skip: max:%d, avg:%d, min:%d\n",
2551 vframe_qos->max_skip,
2552 vframe_qos->avg_skip,
2553 vframe_qos->min_skip);
2554*/
2555 vframe_qos->num++;
2556 if (hw->frameinfo_enable)
2557 vdec_fill_frame_info(vframe_qos, 1);
2558}
2559
2560static int is_iframe(struct FrameStore *frame) {
2561
2562 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2563 return 1;
2564 }
2565 return 0;
2566}
2567
2568
2569
2570int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2571{
2572 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2573 struct vframe_s *vf = NULL;
2574 int buffer_index = frame->buf_spec_num;
2575 int vf_count = 1;
2576 int i;
2577 int bForceInterlace = 0;
2578
2579 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2580 dpb_print(DECODE_ID(hw), 0,
2581 "%s, buffer_index 0x%x is beyond range\n",
2582 __func__, buffer_index);
2583 return -1;
2584 }
2585 if (force_disp_bufspec_num & 0x100) {
2586 /*recycle directly*/
2587 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2588 hw->buffer_spec[frame->buf_spec_num].used != 5)
2589 set_frame_output_flag(&hw->dpb, frame->index);
2590
2591 /*make pre_output not set*/
2592 return -1;
2593 }
2594 if (error_proc_policy & 0x1000) {
2595 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2596 int error_skip_frame_count = error_skip_count & 0xfff;
2597 if (((hw->no_error_count < error_skip_frame_count)
2598 && (error_skip_i_count == 0 ||
2599 hw->no_error_i_count < error_skip_i_count))
2600 && (!(frame->data_flag & I_FLAG)))
2601 frame->data_flag |= ERROR_FLAG;
2602 }
2603 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2604 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2605 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2606 frame->poc, hw->data_flag & ERROR_FLAG,
2607 error_proc_policy);
2608 if (frame->frame == NULL &&
2609 ((frame->is_used == 1 && frame->top_field)
2610 || (frame->is_used == 2 && frame->bottom_field))) {
2611 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2612 "%s Error frame_num %d used %d\n",
2613 __func__, frame->frame_num, frame->is_used);
2614 frame->data_flag |= ERROR_FLAG;
2615 }
2616 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2617 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2618 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2619 0, &frame->pts64) == 0)) {
2620 hw->last_pts64 = frame->pts64;
2621 hw->last_pts = frame->pts;
2622 } else {
2623 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2624 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2625 }
2626 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2627 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2628 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2629 frame->offset_delimiter, frame->pts,hw->last_pts,
2630 frame->pts64, hw->last_pts64, hw->frame_dur);
2631 hw->last_pts64 = frame->pts64;
2632 hw->last_pts = frame->pts;
2633 }
2634 if ((frame->data_flag & NODISP_FLAG) ||
2635 (frame->data_flag & NULL_FLAG) ||
2636 ((!hw->send_error_frame_flag) &&
2637 (frame->data_flag & ERROR_FLAG)) ||
2638 ((hw->i_only & 0x1) &&
2639 (!(frame->data_flag & I_FLAG)))
2640 ) {
2641 set_frame_output_flag(&hw->dpb, frame->index);
2642 return 0; /*do not return -1,
2643 otherwise flush_dpb() will not flush all dbp frames*/
2644 }
2645
2646 display_frame_count[DECODE_ID(hw)]++;
2647
2648 if (dpb_is_debug(DECODE_ID(hw),
2649 PRINT_FLAG_DPB_DETAIL)) {
2650 dpb_print(DECODE_ID(hw), 0,
2651 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2652 __func__, frame->index, frame->poc,
2653 frame->buf_spec_num);
2654 print_pic_info(DECODE_ID(hw), "predis_frm",
2655 frame->frame, -1);
2656 print_pic_info(DECODE_ID(hw), "predis_top",
2657 frame->top_field, -1);
2658 print_pic_info(DECODE_ID(hw), "predis_bot",
2659 frame->bottom_field, -1);
2660 }
2661
2662 if (!is_interlace(frame))
2663 vf_count = 1;
2664 else
2665 vf_count = 2;
2666 bForceInterlace = check_force_interlace(hw, frame);
2667 if (bForceInterlace)
2668 vf_count = 2;
2669 hw->buffer_spec[buffer_index].vf_ref = 0;
2670 fill_frame_info(hw, frame);
2671 for (i = 0; i < vf_count; i++) {
2672 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2673 vf == NULL) {
2674 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2675 "%s fatal error, no available buffer slot.\n",
2676 __func__);
2677 return -1;
2678 }
2679 vf->duration_pulldown = 0;
2680 if (!(is_iframe(frame)) && hw->unstable_pts) {
2681 vf->pts = 0;
2682 vf->pts_us64 = 0;
2683 vf->timestamp = 0;
2684 vf->index = VF_INDEX(frame->index, buffer_index);
2685 } else {
2686 vf->pts = frame->pts;
2687 vf->pts_us64 = frame->pts64;
2688 vf->timestamp = frame->timestamp;
2689 vf->index = VF_INDEX(frame->index, buffer_index);
2690 }
2691
2692 if (hw->is_used_v4l) {
2693 vf->v4l_mem_handle
2694 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2695 }
2696
2697 if (hw->mmu_enable) {
2698 if (hw->double_write_mode & 0x10) {
2699 /* double write only */
2700 vf->compBodyAddr = 0;
2701 vf->compHeadAddr = 0;
2702 } else {
2703 /*head adr*/
2704 vf->compHeadAddr =
2705 hw->buffer_spec[buffer_index].alloc_header_addr;
2706 /*body adr*/
2707 vf->compBodyAddr = 0;
2708 vf->canvas0Addr = vf->canvas1Addr = 0;
2709 }
2710
2711 vf->type = VIDTYPE_SCATTER;
2712
2713 if (hw->double_write_mode) {
2714 vf->type |= VIDTYPE_PROGRESSIVE
2715 | VIDTYPE_VIU_FIELD;
2716 vf->type |= VIDTYPE_VIU_NV21;
2717 if (hw->double_write_mode == 3)
2718 vf->type |= VIDTYPE_COMPRESS;
2719
2720 vf->canvas0Addr = vf->canvas1Addr = -1;
2721 vf->plane_num = 2;
2722 vf->canvas0_config[0] =
2723 hw->buffer_spec[buffer_index].
2724 canvas_config[0];
2725 vf->canvas0_config[1] =
2726 hw->buffer_spec[buffer_index].
2727 canvas_config[1];
2728
2729 vf->canvas1_config[0] =
2730 hw->buffer_spec[buffer_index].
2731 canvas_config[0];
2732 vf->canvas1_config[1] =
2733 hw->buffer_spec[buffer_index].
2734 canvas_config[1];
2735
2736 } else {
2737 vf->type |=
2738 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2739 vf->canvas0Addr = vf->canvas1Addr = 0;
2740 }
2741
2742 vf->bitdepth =
2743 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2744
2745 vf->compWidth = hw->frame_width;
2746 vf->compHeight = hw->frame_height;
2747 } else {
2748 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2749 VIDTYPE_VIU_NV21;
2750
2751 vf->canvas0Addr = vf->canvas1Addr =
2752 spec2canvas(&hw->buffer_spec[buffer_index]);
2753#ifdef VDEC_DW
2754 if (IS_VDEC_DW(hw))
2755 vf->canvas0Addr = vf->canvas1Addr =
2756 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2757#endif
2758
2759 }
2760 set_frame_info(hw, vf, buffer_index);
2761
2762 if (hw->mmu_enable && hw->double_write_mode) {
2763 vf->width = hw->frame_width /
2764 get_double_write_ratio(hw);
2765 vf->height = hw->frame_height /
2766 get_double_write_ratio(hw);
2767 }
2768
2769 vf->flag = 0;
2770 if (frame->data_flag & I_FLAG)
2771 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2772 if (frame->data_flag & ERROR_FLAG)
2773 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2774 update_vf_memhandle(hw, vf, buffer_index);
2775 hw->buffer_spec[buffer_index].used = 2;
2776 hw->buffer_spec[buffer_index].vf_ref++;
2777
2778 if (bForceInterlace || is_interlace(frame)) {
2779 vf->type =
2780 VIDTYPE_INTERLACE_FIRST |
2781 VIDTYPE_VIU_NV21;
2782
2783 if (bForceInterlace) {
2784 vf->type |= (i == 0 ?
2785 VIDTYPE_INTERLACE_TOP :
2786 VIDTYPE_INTERLACE_BOTTOM);
2787 if (i == 1) {
2788 vf->pts = 0;
2789 vf->pts_us64 = 0;
2790 }
2791 } else if (frame->top_field->poc <=
2792 frame->bottom_field->poc) /*top first*/
2793 vf->type |= (i == 0 ?
2794 VIDTYPE_INTERLACE_TOP :
2795 VIDTYPE_INTERLACE_BOTTOM);
2796 else
2797 vf->type |= (i == 0 ?
2798 VIDTYPE_INTERLACE_BOTTOM :
2799 VIDTYPE_INTERLACE_TOP);
2800 vf->duration = vf->duration/2;
2801 }
2802
2803 if (i == 0)
2804 decoder_do_frame_check(hw_to_vdec(hw), vf);
2805
2806 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2807 vf->sar_width = hw->width_aspect_ratio;
2808 vf->sar_height = hw->height_aspect_ratio;
2809
2810 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2811 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2812 hw->vf_pre_count++;
2813 vdec->vdec_fps_detec(vdec->id);
2814 if (without_display_mode == 0) {
2815 vf_notify_receiver(vdec->vf_provider_name,
2816 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2817 } else
2818 vh264_vf_put(vh264_vf_get(vdec), vdec);
2819 }
2820 if (dpb_is_debug(DECODE_ID(hw),
2821 PRINT_FLAG_DUMP_BUFSPEC))
2822 dump_bufspec(hw, __func__);
2823
2824 return 0;
2825}
2826
2827int notify_v4l_eos(struct vdec_s *vdec)
2828{
2829 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2830 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2831 struct vframe_s *vf = &hw->vframe_dummy;
2832 struct vdec_v4l2_buffer *fb = NULL;
2833 int index = INVALID_IDX;
2834 ulong expires;
2835
2836 if (hw->is_used_v4l && hw->eos) {
2837 expires = jiffies + msecs_to_jiffies(2000);
2838 while (INVALID_IDX == (index = v4l_get_free_buf_idx(vdec))) {
2839 if (time_after(jiffies, expires))
2840 break;
2841 }
2842
2843 if (index == INVALID_IDX) {
2844 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2845 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2846 return -1;
2847 }
2848 }
2849
2850 vf->type |= VIDTYPE_V4L_EOS;
2851 vf->timestamp = ULONG_MAX;
2852 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2853 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2854 hw->buffer_spec[index].cma_alloc_addr;
2855
2856 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2857
2858 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2859 vf_notify_receiver(vdec->vf_provider_name,
2860 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2861
2862 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2863 }
2864
2865 return 0;
2866}
2867
2868/******************
2869 * Hardware config
2870 */
2871char *slice_type_name[] = {
2872 "P_SLICE ",
2873 "B_SLICE ",
2874 "I_SLICE ",
2875 "SP_SLICE",
2876 "SI_SLICE",
2877};
2878
2879char *picture_structure_name[] = {
2880 "FRAME",
2881 "TOP_FIELD",
2882 "BOTTOM_FIELD"
2883};
2884
2885void print_pic_info(int decindex, const char *info,
2886 struct StorablePicture *pic,
2887 int slice_type)
2888{
2889 if (pic)
2890 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2891 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2892 info,
2893 picture_structure_name[pic->structure],
2894 pic->coded_frame ? "Frame" : "Field",
2895 (slice_type < 0 ||
2896 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2897 pic->mb_aff_frame_flag,
2898 pic->poc,
2899 pic->pic_num,
2900 pic->buf_spec_num,
2901 pic->data_flag);
2902}
2903
2904static void reset_process_time(struct vdec_h264_hw_s *hw)
2905{
2906 if (hw->start_process_time) {
2907 unsigned process_time =
2908 1000 * (jiffies - hw->start_process_time) / HZ;
2909 hw->start_process_time = 0;
2910 if (process_time > max_process_time[DECODE_ID(hw)])
2911 max_process_time[DECODE_ID(hw)] = process_time;
2912 }
2913}
2914
2915static void start_process_time(struct vdec_h264_hw_s *hw)
2916{
2917 hw->decode_timeout_count = 10;
2918 hw->start_process_time = jiffies;
2919}
2920
2921static void config_aux_buf(struct vdec_h264_hw_s *hw)
2922{
2923 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2924 WRITE_VREG(H264_AUX_DATA_SIZE,
2925 ((hw->prefix_aux_size >> 4) << 16) |
2926 (hw->suffix_aux_size >> 4)
2927 );
2928}
2929
2930/*
2931* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2932*/
2933static void set_aux_data(struct vdec_h264_hw_s *hw,
2934 struct StorablePicture *pic, unsigned char suffix_flag,
2935 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2936{
2937 int i;
2938 unsigned short *aux_adr;
2939 unsigned size_reg_val =
2940 READ_VREG(H264_AUX_DATA_SIZE);
2941 unsigned aux_count = 0;
2942 int aux_size = 0;
2943 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2944 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2945 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2946 return;
2947
2948 if (suffix_flag) {
2949 aux_adr = (unsigned short *)
2950 (hw_buf->aux_addr +
2951 hw_buf->prefix_aux_size);
2952 aux_count =
2953 ((size_reg_val & 0xffff) << 4)
2954 >> 1;
2955 aux_size =
2956 hw_buf->suffix_aux_size;
2957 } else {
2958 aux_adr =
2959 (unsigned short *)hw_buf->aux_addr;
2960 aux_count =
2961 ((size_reg_val >> 16) << 4)
2962 >> 1;
2963 aux_size =
2964 hw_buf->prefix_aux_size;
2965 }
2966 if (dpb_is_debug(DECODE_ID(hw),
2967 PRINT_FLAG_DPB_DETAIL)) {
2968 dpb_print(DECODE_ID(hw), 0,
2969 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2970 __func__, AUX_DATA_SIZE(pic),
2971 aux_count, suffix_flag, dv_meta_flag);
2972 }
2973 if (aux_size > 0 && aux_count > 0) {
2974 int heads_size = 0;
2975 int new_size;
2976 char *new_buf;
2977 for (i = 0; i < aux_count; i++) {
2978 unsigned char tag = aux_adr[i] >> 8;
2979 if (tag != 0 && tag != 0xff) {
2980 if (dv_meta_flag == 0)
2981 heads_size += 8;
2982 else if (dv_meta_flag == 1 && tag == 0x1)
2983 heads_size += 8;
2984 else if (dv_meta_flag == 2 && tag != 0x1)
2985 heads_size += 8;
2986 }
2987 }
2988 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2989 new_buf = krealloc(AUX_DATA_BUF(pic),
2990 new_size,
2991 GFP_KERNEL);
2992 if (new_buf) {
2993 unsigned char valid_tag = 0;
2994 unsigned char *h =
2995 new_buf +
2996 AUX_DATA_SIZE(pic);
2997 unsigned char *p = h + 8;
2998 int len = 0;
2999 int padding_len = 0;
3000 AUX_DATA_BUF(pic) = new_buf;
3001 for (i = 0; i < aux_count; i += 4) {
3002 int ii;
3003 unsigned char tag = aux_adr[i + 3] >> 8;
3004 if (tag != 0 && tag != 0xff) {
3005 if (dv_meta_flag == 0)
3006 valid_tag = 1;
3007 else if (dv_meta_flag == 1
3008 && tag == 0x1)
3009 valid_tag = 1;
3010 else if (dv_meta_flag == 2
3011 && tag != 0x1)
3012 valid_tag = 1;
3013 else
3014 valid_tag = 0;
3015 if (valid_tag && len > 0) {
3016 AUX_DATA_SIZE(pic) +=
3017 (len + 8);
3018 h[0] =
3019 (len >> 24) & 0xff;
3020 h[1] =
3021 (len >> 16) & 0xff;
3022 h[2] =
3023 (len >> 8) & 0xff;
3024 h[3] =
3025 (len >> 0) & 0xff;
3026 h[6] =
3027 (padding_len >> 8)
3028 & 0xff;
3029 h[7] =
3030 (padding_len) & 0xff;
3031 h += (len + 8);
3032 p += 8;
3033 len = 0;
3034 padding_len = 0;
3035 }
3036 if (valid_tag) {
3037 h[4] = tag;
3038 h[5] = 0;
3039 h[6] = 0;
3040 h[7] = 0;
3041 }
3042 }
3043 if (valid_tag) {
3044 for (ii = 0; ii < 4; ii++) {
3045 unsigned short aa =
3046 aux_adr[i + 3
3047 - ii];
3048 *p = aa & 0xff;
3049 p++;
3050 len++;
3051 /*if ((aa >> 8) == 0xff)
3052 padding_len++;*/
3053 }
3054 }
3055 }
3056 if (len > 0) {
3057 AUX_DATA_SIZE(pic) += (len + 8);
3058 h[0] = (len >> 24) & 0xff;
3059 h[1] = (len >> 16) & 0xff;
3060 h[2] = (len >> 8) & 0xff;
3061 h[3] = (len >> 0) & 0xff;
3062 h[6] = (padding_len >> 8) & 0xff;
3063 h[7] = (padding_len) & 0xff;
3064 }
3065 if (dpb_is_debug(DECODE_ID(hw),
3066 PRINT_FLAG_DPB_DETAIL)) {
3067 dpb_print(DECODE_ID(hw), 0,
3068 "aux: (size %d) suffix_flag %d\n",
3069 AUX_DATA_SIZE(pic), suffix_flag);
3070 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
3071 dpb_print_cont(DECODE_ID(hw), 0,
3072 "%02x ", AUX_DATA_BUF(pic)[i]);
3073 if (((i + 1) & 0xf) == 0)
3074 dpb_print_cont(
3075 DECODE_ID(hw),
3076 0, "\n");
3077 }
3078 dpb_print_cont(DECODE_ID(hw),
3079 0, "\n");
3080 }
3081
3082 }
3083 }
3084
3085}
3086
3087static void release_aux_data(struct vdec_h264_hw_s *hw,
3088 int buf_spec_num)
3089{
3090 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3091 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3092 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3093}
3094
3095static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3096{
3097 int i;
3098 unsigned short *aux_adr =
3099 (unsigned short *)
3100 hw->aux_addr;
3101 unsigned aux_size =
3102 (READ_VREG(H264_AUX_DATA_SIZE)
3103 >> 16) << 4;
3104
3105 if (hw->prefix_aux_size > 0) {
3106 dpb_print(DECODE_ID(hw),
3107 0,
3108 "prefix aux: (size %d)\n",
3109 aux_size);
3110 for (i = 0; i <
3111 (aux_size >> 1); i++) {
3112 dpb_print_cont(DECODE_ID(hw),
3113 0,
3114 "%04x ",
3115 *(aux_adr + i));
3116 if (((i + 1) & 0xf)
3117 == 0)
3118 dpb_print_cont(
3119 DECODE_ID(hw),
3120 0, "\n");
3121 }
3122 }
3123 if (hw->suffix_aux_size > 0) {
3124 aux_adr = (unsigned short *)
3125 (hw->aux_addr +
3126 hw->prefix_aux_size);
3127 aux_size =
3128 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3129 << 4;
3130 dpb_print(DECODE_ID(hw),
3131 0,
3132 "suffix aux: (size %d)\n",
3133 aux_size);
3134 for (i = 0; i <
3135 (aux_size >> 1); i++) {
3136 dpb_print_cont(DECODE_ID(hw),
3137 0,
3138 "%04x ", *(aux_adr + i));
3139 if (((i + 1) & 0xf) == 0)
3140 dpb_print_cont(DECODE_ID(hw),
3141 0, "\n");
3142 }
3143 }
3144}
3145
3146static void config_decode_mode(struct vdec_h264_hw_s *hw)
3147{
3148#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3149 struct vdec_s *vdec = hw_to_vdec(hw);
3150#endif
3151 if (input_frame_based(hw_to_vdec(hw)))
3152 WRITE_VREG(H264_DECODE_MODE,
3153 DECODE_MODE_MULTI_FRAMEBASE);
3154#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3155 else if (vdec->slave)
3156 WRITE_VREG(H264_DECODE_MODE,
3157 (hw->got_valid_nal << 8) |
3158 DECODE_MODE_MULTI_DVBAL);
3159 else if (vdec->master)
3160 WRITE_VREG(H264_DECODE_MODE,
3161 (hw->got_valid_nal << 8) |
3162 DECODE_MODE_MULTI_DVENL);
3163#endif
3164 else
3165 WRITE_VREG(H264_DECODE_MODE,
3166 DECODE_MODE_MULTI_STREAMBASE);
3167 WRITE_VREG(H264_DECODE_SEQINFO,
3168 hw->seq_info2);
3169 WRITE_VREG(HEAD_PADING_REG, 0);
3170
3171 if (hw->init_flag == 0)
3172 WRITE_VREG(INIT_FLAG_REG, 0);
3173 else
3174 WRITE_VREG(INIT_FLAG_REG, 1);
3175}
3176int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3177{
3178 /* static int count = 0; */
3179 int ret = 0;
3180 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3181 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3182 unsigned int colocate_adr_offset;
3183 unsigned int val;
3184 struct StorablePicture *last_pic = hw->last_dec_picture;
3185
3186#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3187 int colocate_buf_index;
3188#endif
3189#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3190#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3191#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3192#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3193
3194#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3195/* bit 31:30 -- L1[0] picture coding structure,
3196 * 00 - top field, 01 - bottom field,
3197 * 10 - frame, 11 - mbaff frame
3198 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3199 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3200 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3201 */
3202#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3203
3204/* bit 15 -- flush co_mb_data to DDR -- W-Only
3205 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3206 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3207 * bit 9 -- soft_reset -- W-Only
3208 * bit 8 -- upgent
3209 * bit 7:2 -- h264_co_mb_mem_wr_addr
3210 * bit 1:0 -- h264_co_mb_info_wr_ptr
3211 */
3212#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3213
3214 unsigned long canvas_adr;
3215 unsigned int ref_reg_val;
3216 unsigned int one_ref_cfg = 0;
3217 int h264_buffer_info_data_write_count;
3218 int i, j;
3219 unsigned int colocate_wr_adr;
3220 unsigned int colocate_rd_adr;
3221 unsigned char use_direct_8x8;
3222 int canvas_pos;
3223 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3224 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3225 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3226 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3227 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3228
3229 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3230 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3231 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3232 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3233 canvas_pos);
3234 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3235
3236#ifdef VDEC_DW
3237 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3238 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3239 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3240#endif
3241 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3242 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3243
3244 if (!hw->mmu_enable) {
3245 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3246 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3247 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3248#ifdef VDEC_DW
3249 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3250 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3251 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3252#endif
3253 } else
3254 hevc_sao_set_pic_buffer(hw, pic);
3255
3256 if (pic->mb_aff_frame_flag)
3257 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3258 else if (pic->structure == TOP_FIELD)
3259 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3260 else if (pic->structure == BOTTOM_FIELD)
3261 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3262 else
3263 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3264
3265 if (pic->bottom_poc < pic->top_poc)
3266 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3267
3268 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3269 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3270 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3271
3272 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3273 int long_term_flag;
3274 i = get_buf_spec_by_canvas_pos(hw, j);
3275 if (i < 0)
3276 break;
3277 long_term_flag =
3278 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3279 if (long_term_flag > 0) {
3280 if (long_term_flag & 0x1)
3281 hw->buffer_spec[i].info0 |= (1 << 4);
3282 else
3283 hw->buffer_spec[i].info0 &= ~(1 << 4);
3284
3285 if (long_term_flag & 0x2)
3286 hw->buffer_spec[i].info0 |= (1 << 5);
3287 else
3288 hw->buffer_spec[i].info0 &= ~(1 << 5);
3289 }
3290
3291 if (i == pic->buf_spec_num)
3292 WRITE_VREG(H264_BUFFER_INFO_DATA,
3293 hw->buffer_spec[i].info0 | 0xf);
3294 else
3295 WRITE_VREG(H264_BUFFER_INFO_DATA,
3296 hw->buffer_spec[i].info0);
3297 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3298 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3299 }
3300
3301 /* config reference buffer */
3302 if (hw->mmu_enable) {
3303 hevc_mcr_config_mc_ref(hw);
3304 hevc_mcr_config_mcrcc(hw);
3305 }
3306
3307 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3308 "list0 size %d\n", pSlice->listXsize[0]);
3309 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3310 ref_reg_val = 0;
3311 j = 0;
3312 h264_buffer_info_data_write_count = 0;
3313
3314 //disable this read cache when frame width <= 64 (4MBs)
3315 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3316 if (hw->frame_width <= 64)
3317 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3318 else
3319 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3320
3321 if (last_pic)
3322 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3323 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3324 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3325 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3326 last_pic && (last_pic->data_flag & ERROR_FLAG)
3327 && (!(last_pic->slice_type == B_SLICE))
3328 && (!(pSlice->slice_type == I_SLICE))) {
3329 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3330 "no i/idr error mark\n");
3331 hw->data_flag |= ERROR_FLAG;
3332 pic->data_flag |= ERROR_FLAG;
3333 }
3334
3335 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3336 /*ref list 0 */
3337 struct StorablePicture *ref = pSlice->listX[0][i];
3338 unsigned int cfg;
3339 /* bit[6:5] - frame/field info,
3340 * 01 - top, 10 - bottom, 11 - frame
3341 */
3342 #ifdef ERROR_CHECK
3343 if (ref == NULL) {
3344 hw->data_flag |= ERROR_FLAG;
3345 pic->data_flag |= ERROR_FLAG;
3346 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3347 return -1;
3348 }
3349 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3350 hw->data_flag |= ERROR_FLAG;
3351 pic->data_flag |= ERROR_FLAG;
3352 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3353 }
3354 if (ref->data_flag & NULL_FLAG)
3355 hw->data_flag |= NULL_FLAG;
3356#endif
3357 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3358
3359 if (ref->structure == TOP_FIELD)
3360 cfg = 0x1;
3361 else if (ref->structure == BOTTOM_FIELD)
3362 cfg = 0x2;
3363 else /* FRAME */
3364 cfg = 0x3;
3365
3366 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3367 ref_reg_val <<= 8;
3368 ref_reg_val |= one_ref_cfg;
3369 j++;
3370
3371 if (j == 4) {
3372 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3373 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3374 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3375 h264_buffer_info_data_write_count++;
3376 j = 0;
3377 }
3378 print_pic_info(DECODE_ID(hw), "list0",
3379 pSlice->listX[0][i], -1);
3380 }
3381 if (j != 0) {
3382 while (j != 4) {
3383 ref_reg_val <<= 8;
3384 ref_reg_val |= one_ref_cfg;
3385 j++;
3386 }
3387 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3388 "H264_BUFFER_INFO_DATA: %x\n",
3389 ref_reg_val);
3390 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3391 h264_buffer_info_data_write_count++;
3392 }
3393 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3394 (one_ref_cfg << 8) | one_ref_cfg;
3395 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3396 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3397
3398 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3399 "list1 size %d\n", pSlice->listXsize[1]);
3400 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3401 ref_reg_val = 0;
3402 j = 0;
3403
3404 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3405 /* ref list 0 */
3406 struct StorablePicture *ref = pSlice->listX[1][i];
3407 unsigned int cfg;
3408 /* bit[6:5] - frame/field info,
3409 * 01 - top, 10 - bottom, 11 - frame
3410 */
3411
3412 #ifdef ERROR_CHECK
3413 if (ref == NULL) {
3414 hw->data_flag |= ERROR_FLAG;
3415 pic->data_flag |= ERROR_FLAG;
3416 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3417 return -2;
3418 }
3419 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3420 pic->data_flag |= ERROR_FLAG;
3421 hw->data_flag |= ERROR_FLAG;
3422 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3423 }
3424 if (ref->data_flag & NULL_FLAG)
3425 hw->data_flag |= NULL_FLAG;
3426#endif
3427 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3428 if (ref->structure == TOP_FIELD)
3429 cfg = 0x1;
3430 else if (ref->structure == BOTTOM_FIELD)
3431 cfg = 0x2;
3432 else /* FRAME */
3433 cfg = 0x3;
3434 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3435 ref_reg_val <<= 8;
3436 ref_reg_val |= one_ref_cfg;
3437 j++;
3438
3439 if (j == 4) {
3440 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3441 "H264_BUFFER_INFO_DATA: %x\n",
3442 ref_reg_val);
3443 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3444 j = 0;
3445 }
3446 print_pic_info(DECODE_ID(hw), "list1",
3447 pSlice->listX[1][i], -1);
3448 }
3449 if (j != 0) {
3450 while (j != 4) {
3451 ref_reg_val <<= 8;
3452 ref_reg_val |= one_ref_cfg;
3453 j++;
3454 }
3455 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3456 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3457 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3458 }
3459
3460 /* configure co-locate buffer */
3461 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3462 ;
3463 if ((pSlice->mode_8x8_flags & 0x4) &&
3464 (pSlice->mode_8x8_flags & 0x2))
3465 use_direct_8x8 = 1;
3466 else
3467 use_direct_8x8 = 0;
3468
3469#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3470 colocate_adr_offset =
3471 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3472 ? 1 : 2) * 96;
3473 if (use_direct_8x8)
3474 colocate_adr_offset >>= 2;
3475
3476 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3477 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3478 colocate_adr_offset, pSlice->first_mb_in_slice,
3479 colocate_adr_offset * pSlice->first_mb_in_slice);
3480
3481 colocate_adr_offset *= pSlice->first_mb_in_slice;
3482
3483 if ((pic->colocated_buf_index >= 0) &&
3484 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3485 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3486 ((p_H264_Dpb->colocated_buf_size *
3487 pic->colocated_buf_index)
3488 >> (use_direct_8x8 ? 2 : 0));
3489 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3490 p_H264_Dpb->colocated_mv_addr_end) {
3491 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3492 "Error, colocate buf is not enough, index is %d\n",
3493 pic->colocated_buf_index);
3494 ret = -3;
3495 }
3496 val = colocate_wr_adr + colocate_adr_offset;
3497 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3498 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3499 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3500 val, pSlice->first_mb_in_slice, pic->structure,
3501 colocate_adr_offset, pSlice->mode_8x8_flags,
3502 p_H264_Dpb->colocated_buf_size);
3503 } else {
3504 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3505 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3506 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3507 }
3508#else
3509 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3510 colocate_adr_offset =
3511 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3512 if (use_direct_8x8)
3513 colocate_adr_offset >>= 2;
3514
3515 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3516 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3517 colocate_adr_offset, pSlice->first_mb_in_slice,
3518 colocate_adr_offset * pSlice->first_mb_in_slice);
3519
3520 colocate_adr_offset *= pSlice->first_mb_in_slice;
3521
3522 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3523 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3524 (use_direct_8x8 ? 2 : 0));
3525
3526 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3527 p_H264_Dpb->colocated_mv_addr_end) {
3528 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3529 "Error, colocate buf is not enough, col buf index is %d\n",
3530 colocate_buf_index);
3531 ret = -4;
3532 }
3533 val = colocate_wr_adr + colocate_adr_offset;
3534 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3535 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3536 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3537 val, pSlice->first_mb_in_slice, pic->structure,
3538 colocate_adr_offset, pSlice->mode_8x8_flags,
3539 p_H264_Dpb->colocated_buf_size);
3540#endif
3541 if (pSlice->listXsize[1] > 0) {
3542 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3543 /* H264_CO_MB_RD_ADDR[bit 31:30],
3544 * original picture structure of L1[0],
3545 * 00 - top field, 01 - bottom field,
3546 * 10 - frame, 11 - mbaff frame
3547 */
3548 int l10_structure;
3549 int cur_colocate_ref_type;
3550 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3551 * 0 - top, 1 - bot
3552 */
3553 unsigned int val;
3554#ifdef ERROR_CHECK
3555 if (colocate_pic == NULL) {
3556 hw->data_flag |= ERROR_FLAG;
3557 pic->data_flag |= ERROR_FLAG;
3558 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3559 return -5;
3560 }
3561 if (colocate_pic->data_flag & ERROR_FLAG) {
3562 pic->data_flag |= ERROR_FLAG;
3563 hw->data_flag |= ERROR_FLAG;
3564 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3565 }
3566 if (colocate_pic->data_flag & NULL_FLAG)
3567 hw->data_flag |= NULL_FLAG;
3568#endif
3569
3570 if (colocate_pic->mb_aff_frame_flag)
3571 l10_structure = 3;
3572 else {
3573 if (colocate_pic->coded_frame)
3574 l10_structure = 2;
3575 else
3576 l10_structure = (colocate_pic->structure ==
3577 BOTTOM_FIELD) ? 1 : 0;
3578 }
3579#if 0
3580 /*case0016, p16,
3581 *cur_colocate_ref_type should be configured base on current pic
3582 */
3583 if (pic->structure == FRAME &&
3584 pic->mb_aff_frame_flag)
3585 cur_colocate_ref_type = 0;
3586 else if (pic->structure == BOTTOM_FIELD)
3587 cur_colocate_ref_type = 1;
3588 else
3589 cur_colocate_ref_type = 0;
3590#else
3591 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3592 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3593 pic->mb_aff_frame_flag,
3594 pic->structure,
3595 pic->coded_frame);
3596 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3597 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3598 colocate_pic->mb_aff_frame_flag,
3599 colocate_pic->structure,
3600 colocate_pic->coded_frame);
3601 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3602 cur_colocate_ref_type =
3603 (abs(pic->poc - colocate_pic->top_poc)
3604 < abs(pic->poc -
3605 colocate_pic->bottom_poc)) ? 0 : 1;
3606 } else
3607 cur_colocate_ref_type =
3608 (colocate_pic->structure
3609 == BOTTOM_FIELD) ? 1 : 0;
3610#endif
3611
3612#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3613 if ((colocate_pic->colocated_buf_index >= 0) &&
3614 (colocate_pic->colocated_buf_index <
3615 p_H264_Dpb->colocated_buf_count)) {
3616 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3617 ((p_H264_Dpb->colocated_buf_size *
3618 colocate_pic->colocated_buf_index)
3619 >> (use_direct_8x8 ? 2 : 0));
3620 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3621 p_H264_Dpb->colocated_mv_addr_end) {
3622 dpb_print(DECODE_ID(hw),
3623 PRINT_FLAG_ERROR,
3624 "Error, colocate buf is not enough, index is %d\n",
3625 colocate_pic->colocated_buf_index);
3626 ret = -6;
3627 }
3628 /* bit 31:30 -- L1[0] picture coding structure,
3629 * 00 - top field, 01 - bottom field,
3630 * 10 - frame, 11 - mbaff frame
3631 * bit 29 - L1[0] top/bot for B field pciture,
3632 * 0 - top, 1 - bot
3633 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3634 * -- only used for B Picture Direct mode
3635 * [2:0] will set to 3'b000
3636 */
3637 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3638 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3639 (l10_structure << 30) |
3640 (cur_colocate_ref_type << 29);
3641 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3642 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3643 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3644 colocate_pic->colocated_buf_index,
3645 val, colocate_rd_adr + colocate_adr_offset,
3646 colocate_pic->structure,
3647 colocate_pic->mb_aff_frame_flag);
3648 } else {
3649 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3650 "Error, reference pic has no colocated buf\n");
3651 ret = -7;
3652 }
3653#else
3654 colocate_buf_index =
3655 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3656 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3657 ((p_H264_Dpb->colocated_buf_size *
3658 colocate_buf_index)
3659 >> (use_direct_8x8 ? 2 : 0));
3660 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3661 p_H264_Dpb->colocated_mv_addr_end) {
3662 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3663 "Error, colocate buf is not enough, col buf index is %d\n",
3664 colocate_buf_index);
3665 ret = -8;
3666 }
3667 /* bit 31:30 -- L1[0] picture coding structure,
3668 * 00 - top field, 01 - bottom field,
3669 * 10 - frame, 11 - mbaff frame
3670 * bit 29 - L1[0] top/bot for B field pciture,
3671 * 0 - top, 1 - bot
3672 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3673 * -- only used for B Picture Direct mode
3674 * [2:0] will set to 3'b000
3675 */
3676 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3677 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3678 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3679 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3680 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3681 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3682 val, colocate_pic->structure,
3683 colocate_pic->mb_aff_frame_flag);
3684#endif
3685 }
3686 return ret;
3687}
3688
3689static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3690{
3691 unsigned long flags;
3692 struct vdec_s *vdec = op_arg;
3693 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3694
3695 spin_lock_irqsave(&hw->lock, flags);
3696
3697 states->vf_pool_size = VF_POOL_SIZE;
3698 states->buf_free_num = kfifo_len(&hw->newframe_q);
3699 states->buf_avail_num = kfifo_len(&hw->display_q);
3700
3701 spin_unlock_irqrestore(&hw->lock, flags);
3702
3703 return 0;
3704}
3705
3706static struct vframe_s *vh264_vf_peek(void *op_arg)
3707{
3708 struct vframe_s *vf[2] = {0, 0};
3709 struct vdec_s *vdec = op_arg;
3710 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3711
3712 if (!hw)
3713 return NULL;
3714
3715 if (force_disp_bufspec_num & 0x100) {
3716 if (force_disp_bufspec_num & 0x200)
3717 return NULL;
3718 return &hw->vframe_dummy;
3719 }
3720
3721 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3722 if (vf[1]) {
3723 vf[0]->next_vf_pts_valid = true;
3724 vf[0]->next_vf_pts = vf[1]->pts;
3725 } else
3726 vf[0]->next_vf_pts_valid = false;
3727 return vf[0];
3728 }
3729
3730 return NULL;
3731}
3732
3733static struct vframe_s *vh264_vf_get(void *op_arg)
3734{
3735 struct vframe_s *vf;
3736 struct vdec_s *vdec = op_arg;
3737 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3738
3739 if (!hw)
3740 return NULL;
3741
3742 if (force_disp_bufspec_num & 0x100) {
3743 int buffer_index = force_disp_bufspec_num & 0xff;
3744 if (force_disp_bufspec_num & 0x200)
3745 return NULL;
3746
3747 vf = &hw->vframe_dummy;
3748 vf->duration_pulldown = 0;
3749 vf->pts = 0;
3750 vf->pts_us64 = 0;
3751 set_frame_info(hw, vf, buffer_index);
3752 vf->flag = 0;
3753 if (hw->mmu_enable) {
3754 if (hw->double_write_mode & 0x10) {
3755 /* double write only */
3756 vf->compBodyAddr = 0;
3757 vf->compHeadAddr = 0;
3758 } else {
3759 /*head adr*/
3760 vf->compHeadAddr =
3761 hw->buffer_spec[buffer_index].alloc_header_addr;
3762 /*body adr*/
3763 vf->compBodyAddr = 0;
3764 vf->canvas0Addr = vf->canvas1Addr = 0;
3765 }
3766
3767 vf->type = VIDTYPE_SCATTER;
3768
3769 if (hw->double_write_mode) {
3770 vf->type |= VIDTYPE_PROGRESSIVE
3771 | VIDTYPE_VIU_FIELD;
3772 vf->type |= VIDTYPE_VIU_NV21;
3773 if (hw->double_write_mode == 3)
3774 vf->type |= VIDTYPE_COMPRESS;
3775
3776 vf->canvas0Addr = vf->canvas1Addr = -1;
3777 vf->plane_num = 2;
3778 vf->canvas0_config[0] =
3779 hw->buffer_spec[buffer_index].
3780 canvas_config[0];
3781 vf->canvas0_config[1] =
3782 hw->buffer_spec[buffer_index].
3783 canvas_config[1];
3784
3785 vf->canvas1_config[0] =
3786 hw->buffer_spec[buffer_index].
3787 canvas_config[0];
3788 vf->canvas1_config[1] =
3789 hw->buffer_spec[buffer_index].
3790 canvas_config[1];
3791 } else {
3792 vf->type |=
3793 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3794 vf->canvas0Addr = vf->canvas1Addr = 0;
3795 }
3796 vf->bitdepth =
3797 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3798
3799 vf->compWidth = hw->frame_width;
3800 vf->compHeight = hw->frame_height;
3801
3802 if (hw->double_write_mode) {
3803 vf->width = hw->frame_width /
3804 get_double_write_ratio(hw);
3805 vf->height = hw->frame_height /
3806 get_double_write_ratio(hw);
3807 }
3808 } else {
3809 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3810 VIDTYPE_VIU_NV21;
3811 vf->canvas0Addr = vf->canvas1Addr =
3812 spec2canvas(&hw->buffer_spec[buffer_index]);
3813 }
3814
3815 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3816 hw->bmmu_box, buffer_index);*/
3817 update_vf_memhandle(hw, vf, buffer_index);
3818 force_disp_bufspec_num |= 0x200;
3819 return vf;
3820 }
3821
3822 if (kfifo_get(&hw->display_q, &vf)) {
3823 int time = jiffies;
3824 unsigned int frame_interval =
3825 1000*(time - hw->last_frame_time)/HZ;
3826 struct vframe_s *next_vf;
3827 if (dpb_is_debug(DECODE_ID(hw),
3828 PRINT_FLAG_VDEC_DETAIL)) {
3829 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3830 int frame_index = FRAME_INDEX(vf->index);
3831 if (frame_index < 0 ||
3832 frame_index >= DPB_SIZE_MAX) {
3833 dpb_print(DECODE_ID(hw), 0,
3834 "%s vf index 0x%x error\r\n",
3835 __func__, vf->index);
3836 } else {
3837 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3838 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3839 __func__, BUFSPEC_INDEX(vf->index), vf,
3840 p_H264_Dpb->mFrameStore[frame_index].poc,
3841 vf->duration, vf->pts, frame_interval);
3842 }
3843 }
3844 if (hw->last_frame_time > 0) {
3845 if (frame_interval >
3846 max_get_frame_interval[DECODE_ID(hw)])
3847 max_get_frame_interval[DECODE_ID(hw)]
3848 = frame_interval;
3849 }
3850 hw->last_frame_time = time;
3851 vf->index_disp = hw->vf_get_count;
3852 hw->vf_get_count++;
3853 if (kfifo_peek(&hw->display_q, &next_vf)) {
3854 vf->next_vf_pts_valid = true;
3855 vf->next_vf_pts = next_vf->pts;
3856 } else
3857 vf->next_vf_pts_valid = false;
3858 return vf;
3859 }
3860
3861 return NULL;
3862}
3863
3864static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3865{
3866 struct vdec_s *vdec = op_arg;
3867 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3868 unsigned long flags;
3869 int buf_spec_num;
3870 int frame_index;
3871
3872 if (vf == (&hw->vframe_dummy))
3873 return;
3874 if (vf->index == -1) {
3875 dpb_print(DECODE_ID(hw), 0,
3876 "Warning: %s vf %p invalid index\r\n",
3877 __func__, vf);
3878 return;
3879 }
3880 frame_index = FRAME_INDEX(vf->index);
3881 buf_spec_num = BUFSPEC_INDEX(vf->index);
3882 if (frame_index < 0 ||
3883 frame_index >= DPB_SIZE_MAX ||
3884 buf_spec_num < 0 ||
3885 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3886 dpb_print(DECODE_ID(hw), 0,
3887 "%s vf index 0x%x error\r\n",
3888 __func__, vf->index);
3889 return;
3890 }
3891 /*get_buf_spec_idx_by_canvas_config(hw,
3892 &vf->canvas0_config[0]);*/
3893 spin_lock_irqsave(&hw->bufspec_lock, flags);
3894 if (hw->buffer_spec[buf_spec_num].used == 2) {
3895 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3896 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3897 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3898 __func__, vf, frame_index,
3899 p_H264_Dpb->mFrameStore[frame_index].poc,
3900 buf_spec_num,
3901 hw->buffer_spec[buf_spec_num].used,
3902 hw->buffer_spec[buf_spec_num].vf_ref);
3903 hw->buffer_spec[buf_spec_num].vf_ref--;
3904 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3905 set_frame_output_flag(&hw->dpb, frame_index);
3906 } else {
3907 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3908 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3909 __func__, vf, buf_spec_num,
3910 hw->buffer_spec[buf_spec_num].used,
3911 hw->buffer_spec[buf_spec_num].vf_ref);
3912 hw->buffer_spec[buf_spec_num].vf_ref--;
3913 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3914 if (hw->buffer_spec[buf_spec_num].used == 3)
3915 hw->buffer_spec[buf_spec_num].used = 4;
3916 else if (hw->buffer_spec[buf_spec_num].used == 5)
3917 hw->buffer_spec[buf_spec_num].used = 0;
3918 }
3919 if (dpb_is_debug(DECODE_ID(hw),
3920 PRINT_FLAG_DUMP_BUFSPEC))
3921 dump_bufspec(hw, __func__);
3922
3923 }
3924 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3925
3926 hw->vf_put_count++;
3927 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3928
3929#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3930 if (hw->buffer_empty_flag)
3931 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3932}
3933
3934static int vh264_event_cb(int type, void *data, void *op_arg)
3935{
3936 unsigned long flags;
3937 struct vdec_s *vdec = op_arg;
3938 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3939
3940 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3941 struct provider_aux_req_s *req =
3942 (struct provider_aux_req_s *)data;
3943 int buf_spec_num;
3944
3945 if (!req->vf) {
3946 req->aux_size = hw->vf_put_count;
3947 return 0;
3948 }
3949 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3950 spin_lock_irqsave(&hw->lock, flags);
3951 req->aux_buf = NULL;
3952 req->aux_size = 0;
3953 if (buf_spec_num >= 0 &&
3954 buf_spec_num < BUFSPEC_POOL_SIZE &&
3955 is_buf_spec_in_disp_q(hw, buf_spec_num)
3956 ) {
3957 req->aux_buf =
3958 hw->buffer_spec[buf_spec_num].aux_data_buf;
3959 req->aux_size =
3960 hw->buffer_spec[buf_spec_num].aux_data_size;
3961#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3962 req->dv_enhance_exist =
3963 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3964#else
3965 req->dv_enhance_exist = 0;
3966#endif
3967 }
3968 spin_unlock_irqrestore(&hw->lock, flags);
3969
3970 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3971 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3972 __func__, type, buf_spec_num, req->aux_size);
3973 }
3974
3975 return 0;
3976}
3977
3978static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3979 u32 index)
3980{
3981 struct canvas_config_s *p_canvas_config;
3982 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3983 force_rate_framebase : force_rate_streambase;
3984 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3985 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3986 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3987
3988 /* signal_type */
3989 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3990 vf->signal_type = hw->video_signal_from_vui;
3991 if (hw->is_used_v4l) {
3992 struct aml_vdec_hdr_infos hdr;
3993 struct aml_vcodec_ctx *ctx =
3994 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3995
3996 memset(&hdr, 0, sizeof(hdr));
3997 hdr.signal_type = hw->video_signal_from_vui;
3998 vdec_v4l_set_hdr_infos(ctx, &hdr);
3999 }
4000 } else
4001 vf->signal_type = 0;
4002
4003 vf->width = hw->frame_width;
4004 vf->height = hw->frame_height;
4005 if (force_rate) {
4006 if (force_rate == -1)
4007 vf->duration = 0;
4008 else
4009 vf->duration = 96000/force_rate;
4010 } else
4011 vf->duration = hw->frame_dur;
4012 vf->ratio_control =
4013 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
4014 DISP_RATIO_ASPECT_RATIO_BIT;
4015 vf->orientation = hw->vh264_rotation;
4016
4017 if (hw->mmu_enable)
4018 return;
4019
4020 vf->canvas0Addr = vf->canvas1Addr = -1;
4021#ifdef NV21
4022 vf->plane_num = 2;
4023#else
4024 vf->plane_num = 3;
4025#endif
4026
4027 if (IS_VDEC_DW(hw)) {
4028 vf->width = (hw->frame_width /2);
4029 if (IS_VDEC_DW(hw) == 2)
4030 vf->height = (hw->frame_height /2);
4031 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
4032 } else
4033 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
4034
4035 vf->canvas0_config[0] = p_canvas_config[0];
4036 vf->canvas0_config[1] = p_canvas_config[1];
4037#ifndef NV21
4038 vf->canvas0_config[2] = p_canvas_config[2];
4039#endif
4040 vf->canvas1_config[0] = p_canvas_config[0];
4041 vf->canvas1_config[1] = p_canvas_config[1];
4042#ifndef NV21
4043 vf->canvas1_config[2] = p_canvas_config[2];
4044#endif
4045}
4046
4047static void get_picture_qos_info(struct StorablePicture *picture)
4048{
4049 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4050 unsigned char a[3];
4051 unsigned char i, j, t;
4052 unsigned long data;
4053
4054 get_random_bytes(&data, sizeof(unsigned long));
4055 if (picture->slice_type == I_SLICE)
4056 data = 0;
4057 a[0] = data & 0xff;
4058 a[1] = (data >> 8) & 0xff;
4059 a[2] = (data >> 16) & 0xff;
4060
4061 for (i = 0; i < 3; i++)
4062 for (j = i+1; j < 3; j++) {
4063 if (a[j] < a[i]) {
4064 t = a[j];
4065 a[j] = a[i];
4066 a[i] = t;
4067 } else if (a[j] == a[i]) {
4068 a[i]++;
4069 t = a[j];
4070 a[j] = a[i];
4071 a[i] = t;
4072 }
4073 }
4074 picture->max_mv = a[2];
4075 picture->avg_mv = a[1];
4076 picture->min_mv = a[0];
4077 /*
4078 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4079 data, a[0], a[1], a[2]);
4080 */
4081
4082 get_random_bytes(&data, sizeof(unsigned long));
4083 a[0] = data & 0x1f;
4084 a[1] = (data >> 8) & 0x3f;
4085 a[2] = (data >> 16) & 0x7f;
4086
4087 for (i = 0; i < 3; i++)
4088 for (j = i+1; j < 3; j++) {
4089 if (a[j] < a[i]) {
4090 t = a[j];
4091 a[j] = a[i];
4092 a[i] = t;
4093 } else if (a[j] == a[i]) {
4094 a[i]++;
4095 t = a[j];
4096 a[j] = a[i];
4097 a[i] = t;
4098 }
4099 }
4100 picture->max_qp = a[2];
4101 picture->avg_qp = a[1];
4102 picture->min_qp = a[0];
4103 /*
4104 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4105 data, a[0], a[1], a[2]);
4106 */
4107
4108 get_random_bytes(&data, sizeof(unsigned long));
4109 a[0] = data & 0x1f;
4110 a[1] = (data >> 8) & 0x3f;
4111 a[2] = (data >> 16) & 0x7f;
4112
4113 for (i = 0; i < 3; i++)
4114 for (j = i+1; j < 3; j++) {
4115 if (a[j] < a[i]) {
4116 t = a[j];
4117 a[j] = a[i];
4118 a[i] = t;
4119 } else if (a[j] == a[i]) {
4120 a[i]++;
4121 t = a[j];
4122 a[j] = a[i];
4123 a[i] = t;
4124 }
4125 }
4126 picture->max_skip = a[2];
4127 picture->avg_skip = a[1];
4128 picture->min_skip = a[0];
4129
4130
4131 /*
4132 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4133 data,a[0], a[1], a[2]);
4134 */
4135 } else {
4136 uint32_t blk88_y_count;
4137 uint32_t blk88_c_count;
4138 uint32_t blk22_mv_count;
4139 uint32_t rdata32;
4140 int32_t mv_hi;
4141 int32_t mv_lo;
4142 uint32_t rdata32_l;
4143 uint32_t mvx_L0_hi;
4144 uint32_t mvy_L0_hi;
4145 uint32_t mvx_L1_hi;
4146 uint32_t mvy_L1_hi;
4147 int64_t value;
4148 uint64_t temp_value;
4149/*
4150#define DEBUG_QOS
4151*/
4152#ifdef DEBUG_QOS
4153 int pic_number = picture->poc;
4154#endif
4155
4156 picture->max_mv = 0;
4157 picture->avg_mv = 0;
4158 picture->min_mv = 0;
4159
4160 picture->max_skip = 0;
4161 picture->avg_skip = 0;
4162 picture->min_skip = 0;
4163
4164 picture->max_qp = 0;
4165 picture->avg_qp = 0;
4166 picture->min_qp = 0;
4167
4168
4169
4170
4171
4172 /* set rd_idx to 0 */
4173 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4174 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4175 if (blk88_y_count == 0) {
4176#ifdef DEBUG_QOS
4177 pr_info(" [Picture %d Quality] NO Data yet.\n",
4178 pic_number);
4179#endif
4180 /* reset all counts */
4181 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4182 return;
4183 }
4184 /* qp_y_sum */
4185 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4186#ifdef DEBUG_QOS
4187 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4188 pic_number, rdata32/blk88_y_count,
4189 rdata32, blk88_y_count);
4190#endif
4191 picture->avg_qp = rdata32/blk88_y_count;
4192 /* intra_y_count */
4193 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4194#ifdef DEBUG_QOS
4195 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4196 pic_number, rdata32*100/blk88_y_count,
4197 '%', rdata32);
4198#endif
4199 /* skipped_y_count */
4200 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4201#ifdef DEBUG_QOS
4202 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4203 pic_number, rdata32*100/blk88_y_count,
4204 '%', rdata32);
4205#endif
4206 picture->avg_skip = rdata32*100/blk88_y_count;
4207 /* coeff_non_zero_y_count */
4208 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4209#ifdef DEBUG_QOS
4210 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4211 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4212 '%', rdata32);
4213#endif
4214 /* blk66_c_count */
4215 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4216 if (blk88_c_count == 0) {
4217#ifdef DEBUG_QOS
4218 pr_info(" [Picture %d Quality] NO Data yet.\n",
4219 pic_number);
4220#endif
4221 /* reset all counts */
4222 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4223 return;
4224 }
4225 /* qp_c_sum */
4226 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4227#ifdef DEBUG_QOS
4228 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4229 pic_number, rdata32/blk88_c_count,
4230 rdata32, blk88_c_count);
4231#endif
4232 /* intra_c_count */
4233 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4234#ifdef DEBUG_QOS
4235 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4236 pic_number, rdata32*100/blk88_c_count,
4237 '%', rdata32);
4238#endif
4239 /* skipped_cu_c_count */
4240 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4241#ifdef DEBUG_QOS
4242 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4243 pic_number, rdata32*100/blk88_c_count,
4244 '%', rdata32);
4245#endif
4246 /* coeff_non_zero_c_count */
4247 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4248#ifdef DEBUG_QOS
4249 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4250 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4251 '%', rdata32);
4252#endif
4253
4254 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4255 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4256 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4257#ifdef DEBUG_QOS
4258 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4259 pic_number, (rdata32>>0)&0xff);
4260#endif
4261 picture->min_qp = (rdata32>>0)&0xff;
4262
4263#ifdef DEBUG_QOS
4264 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4265 pic_number, (rdata32>>8)&0xff);
4266#endif
4267 picture->max_qp = (rdata32>>8)&0xff;
4268
4269#ifdef DEBUG_QOS
4270 pr_info(" [Picture %d Quality] C QP min : %d\n",
4271 pic_number, (rdata32>>16)&0xff);
4272 pr_info(" [Picture %d Quality] C QP max : %d\n",
4273 pic_number, (rdata32>>24)&0xff);
4274#endif
4275
4276 /* blk22_mv_count */
4277 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4278 if (blk22_mv_count == 0) {
4279#ifdef DEBUG_QOS
4280 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4281 pic_number);
4282#endif
4283 /* reset all counts */
4284 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4285 return;
4286 }
4287 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4288 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4289 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4290 /* should all be 0x00 or 0xff */
4291#ifdef DEBUG_QOS
4292 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4293 pic_number, rdata32);
4294#endif
4295 mvx_L0_hi = ((rdata32>>0)&0xff);
4296 mvy_L0_hi = ((rdata32>>8)&0xff);
4297 mvx_L1_hi = ((rdata32>>16)&0xff);
4298 mvy_L1_hi = ((rdata32>>24)&0xff);
4299
4300 /* mvx_L0_count[31:0] */
4301 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4302 temp_value = mvx_L0_hi;
4303 temp_value = (temp_value << 32) | rdata32_l;
4304
4305 if (mvx_L0_hi & 0x80)
4306 value = 0xFFFFFFF000000000 | temp_value;
4307 else
4308 value = temp_value;
4309 value = div_s64(value, blk22_mv_count);
4310#ifdef DEBUG_QOS
4311 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4312 pic_number, (int)(value),
4313 value, blk22_mv_count);
4314#endif
4315 picture->avg_mv = value;
4316
4317 /* mvy_L0_count[31:0] */
4318 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4319 temp_value = mvy_L0_hi;
4320 temp_value = (temp_value << 32) | rdata32_l;
4321
4322 if (mvy_L0_hi & 0x80)
4323 value = 0xFFFFFFF000000000 | temp_value;
4324 else
4325 value = temp_value;
4326#ifdef DEBUG_QOS
4327 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4328 pic_number, rdata32_l/blk22_mv_count,
4329 value, blk22_mv_count);
4330#endif
4331
4332 /* mvx_L1_count[31:0] */
4333 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4334 temp_value = mvx_L1_hi;
4335 temp_value = (temp_value << 32) | rdata32_l;
4336 if (mvx_L1_hi & 0x80)
4337 value = 0xFFFFFFF000000000 | temp_value;
4338 else
4339 value = temp_value;
4340#ifdef DEBUG_QOS
4341 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4342 pic_number, rdata32_l/blk22_mv_count,
4343 value, blk22_mv_count);
4344#endif
4345
4346 /* mvy_L1_count[31:0] */
4347 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4348 temp_value = mvy_L1_hi;
4349 temp_value = (temp_value << 32) | rdata32_l;
4350 if (mvy_L1_hi & 0x80)
4351 value = 0xFFFFFFF000000000 | temp_value;
4352 else
4353 value = temp_value;
4354#ifdef DEBUG_QOS
4355 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4356 pic_number, rdata32_l/blk22_mv_count,
4357 value, blk22_mv_count);
4358#endif
4359
4360 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4361 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4362 mv_hi = (rdata32>>16)&0xffff;
4363 if (mv_hi & 0x8000)
4364 mv_hi = 0x8000 - mv_hi;
4365#ifdef DEBUG_QOS
4366 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4367 pic_number, mv_hi);
4368#endif
4369 picture->max_mv = mv_hi;
4370
4371 mv_lo = (rdata32>>0)&0xffff;
4372 if (mv_lo & 0x8000)
4373 mv_lo = 0x8000 - mv_lo;
4374#ifdef DEBUG_QOS
4375 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4376 pic_number, mv_lo);
4377#endif
4378 picture->min_mv = mv_lo;
4379
4380 /* {mvy_L0_max, mvy_L0_min} */
4381 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4382 mv_hi = (rdata32>>16)&0xffff;
4383 if (mv_hi & 0x8000)
4384 mv_hi = 0x8000 - mv_hi;
4385#ifdef DEBUG_QOS
4386 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4387 pic_number, mv_hi);
4388#endif
4389
4390 mv_lo = (rdata32>>0)&0xffff;
4391 if (mv_lo & 0x8000)
4392 mv_lo = 0x8000 - mv_lo;
4393#ifdef DEBUG_QOS
4394 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4395 pic_number, mv_lo);
4396#endif
4397
4398 /* {mvx_L1_max, mvx_L1_min} */
4399 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4400 mv_hi = (rdata32>>16)&0xffff;
4401 if (mv_hi & 0x8000)
4402 mv_hi = 0x8000 - mv_hi;
4403#ifdef DEBUG_QOS
4404 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4405 pic_number, mv_hi);
4406#endif
4407
4408 mv_lo = (rdata32>>0)&0xffff;
4409 if (mv_lo & 0x8000)
4410 mv_lo = 0x8000 - mv_lo;
4411#ifdef DEBUG_QOS
4412 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4413 pic_number, mv_lo);
4414#endif
4415
4416 /* {mvy_L1_max, mvy_L1_min} */
4417 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4418 mv_hi = (rdata32>>16)&0xffff;
4419 if (mv_hi & 0x8000)
4420 mv_hi = 0x8000 - mv_hi;
4421#ifdef DEBUG_QOS
4422 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4423 pic_number, mv_hi);
4424#endif
4425 mv_lo = (rdata32>>0)&0xffff;
4426 if (mv_lo & 0x8000)
4427 mv_lo = 0x8000 - mv_lo;
4428#ifdef DEBUG_QOS
4429 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4430 pic_number, mv_lo);
4431#endif
4432
4433 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4434#ifdef DEBUG_QOS
4435 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4436 pic_number, rdata32);
4437#endif
4438 /* reset all counts */
4439 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4440 }
4441}
4442
4443static int get_max_dec_frame_buf_size(int level_idc,
4444 int max_reference_frame_num, int mb_width,
4445 int mb_height)
4446{
4447 int pic_size = mb_width * mb_height * 384;
4448
4449 int size = 0;
4450
4451 switch (level_idc) {
4452 case 9:
4453 size = 152064;
4454 break;
4455 case 10:
4456 size = 152064;
4457 break;
4458 case 11:
4459 size = 345600;
4460 break;
4461 case 12:
4462 size = 912384;
4463 break;
4464 case 13:
4465 size = 912384;
4466 break;
4467 case 20:
4468 size = 912384;
4469 break;
4470 case 21:
4471 size = 1824768;
4472 break;
4473 case 22:
4474 size = 3110400;
4475 break;
4476 case 30:
4477 size = 3110400;
4478 break;
4479 case 31:
4480 size = 6912000;
4481 break;
4482 case 32:
4483 size = 7864320;
4484 break;
4485 case 40:
4486 size = 12582912;
4487 break;
4488 case 41:
4489 size = 12582912;
4490 break;
4491 case 42:
4492 size = 13369344;
4493 break;
4494 case 50:
4495 size = 42393600;
4496 break;
4497 case 51:
4498 case 52:
4499 default:
4500 size = 70778880;
4501 break;
4502 }
4503
4504 size /= pic_size;
4505 size = size + 1; /* need one more buffer */
4506
4507 if (max_reference_frame_num > size)
4508 size = max_reference_frame_num;
4509 size = imin(size, 16);
4510
4511 return size;
4512}
4513
4514static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4515{
4516 int i, j;
4517
4518 if (hw->double_write_mode) {
4519 mutex_lock(&vmh264_mutex);
4520 if (hw->decode_pic_count == 0) {
4521 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4522 i = get_buf_spec_by_canvas_pos(hw, j);
4523 if (i >= 0)
4524 config_decode_canvas_ex(hw, i);
4525 }
4526 }
4527 mutex_unlock(&vmh264_mutex);
4528 }
4529}
4530
4531static int vh264_set_params(struct vdec_h264_hw_s *hw,
4532 u32 param1, u32 param2, u32 param3, u32 param4)
4533{
4534 int i, j;
4535 int mb_width, mb_total;
4536 int max_reference_size, level_idc;
4537 int mb_height = 0;
4538 unsigned long flags;
4539 /*int mb_mv_byte;*/
4540 struct vdec_s *vdec = hw_to_vdec(hw);
4541 u32 seq_info2;
4542 int ret = 0;
4543 int active_buffer_spec_num;
4544 unsigned int buf_size;
4545 unsigned int frame_mbs_only_flag;
4546 unsigned int chroma_format_idc, chroma444;
4547 unsigned int crop_infor, crop_bottom, crop_right;
4548 unsigned int used_reorder_dpb_size_margin
4549 = hw->reorder_dpb_size_margin;
4550 u8 *colocate_vaddr = NULL;
4551
4552#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4553 if (vdec->master || vdec->slave)
4554 used_reorder_dpb_size_margin =
4555 reorder_dpb_size_margin_dv;
4556#endif
4557 seq_info2 = param1;
4558 hw->seq_info = param2;
4559
4560 mb_width = seq_info2 & 0xff;
4561 mb_total = (seq_info2 >> 8) & 0xffff;
4562 if (!mb_width && mb_total) /*for 4k2k*/
4563 mb_width = 256;
4564 if (mb_width)
4565 mb_height = mb_total/mb_width;
4566 if (mb_width <= 0 || mb_height <= 0 ||
4567 is_oversize(mb_width << 4, mb_height << 4)) {
4568 dpb_print(DECODE_ID(hw), 0,
4569 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4570 seq_info2,
4571 mb_width,
4572 mb_height);
4573 return -1;
4574 }
4575
4576 if (seq_info2 != 0 &&
4577 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4578 hw->seq_info2 != 0
4579 ) /*picture size changed*/
4580 h264_reconfig(hw);
4581
4582 if (hw->config_bufmgr_done == 0) {
4583 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4584 u32 reg_val;
4585 hw->cfg_param1 = param1;
4586 hw->cfg_param2 = param2;
4587 hw->cfg_param3 = param3;
4588 hw->cfg_param4 = param4;
4589
4590 hw->seq_info2 = seq_info2 & (~0x80000000);
4591 dpb_print(DECODE_ID(hw), 0,
4592 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4593 seq_info2, hw->seq_info);
4594
4595 dpb_init_global(&hw->dpb,
4596 DECODE_ID(hw), 0, 0);
4597
4598 p_H264_Dpb->fast_output_enable = fast_output_enable;
4599 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4600
4601#if 1
4602 /*crop*/
4603 /* AV_SCRATCH_2
4604 bit 15: frame_mbs_only_flag
4605 bit 13-14: chroma_format_idc */
4606 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4607 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4608 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4609
4610 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4611 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4612 (2 - frame_mbs_only_flag) */
4613 crop_infor = param3;
4614 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4615 crop_right = ((crop_infor >> 16) & 0xff)
4616 >> (2 - frame_mbs_only_flag);
4617
4618 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4619 hw->frame_width = mb_width << 4;
4620 hw->frame_height = mb_height << 4;
4621 if (frame_mbs_only_flag) {
4622 hw->frame_height =
4623 hw->frame_height - (2 >> chroma444) *
4624 min(crop_bottom,
4625 (unsigned int)((8 << chroma444) - 1));
4626 hw->frame_width =
4627 hw->frame_width -
4628 (2 >> chroma444) * min(crop_right,
4629 (unsigned
4630 int)((8 << chroma444) - 1));
4631 } else {
4632 hw->frame_height =
4633 hw->frame_height - (4 >> chroma444) *
4634 min(crop_bottom,
4635 (unsigned int)((8 << chroma444)
4636 - 1));
4637 hw->frame_width =
4638 hw->frame_width -
4639 (4 >> chroma444) * min(crop_right,
4640 (unsigned int)((8 << chroma444) - 1));
4641 }
4642 dpb_print(DECODE_ID(hw), 0,
4643 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4644 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4645 dpb_print(DECODE_ID(hw), 0,
4646 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4647 mb_height, crop_right,
4648 hw->frame_width, mb_width);
4649
4650 if (hw->frame_height == 1088)
4651 hw->frame_height = 1080;
4652#endif
4653 if (!hw->mmu_enable) {
4654 mb_width = (mb_width+3) & 0xfffffffc;
4655 mb_height = (mb_height+3) & 0xfffffffc;
4656 }
4657 mb_total = mb_width * mb_height;
4658 hw->mb_width = mb_width;
4659 hw->mb_height = mb_height;
4660 hw->mb_total = mb_total;
4661 if (hw->mmu_enable)
4662 hevc_mcr_sao_global_hw_init(hw,
4663 (hw->mb_width << 4), (hw->mb_height << 4));
4664
4665 reg_val = param4;
4666 level_idc = reg_val & 0xff;
4667 max_reference_size = (reg_val >> 8) & 0xff;
4668 hw->dpb.origin_max_reference = max_reference_size;
4669 dpb_print(DECODE_ID(hw), 0,
4670 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4671 mb_height, mb_width, mb_total,
4672 level_idc, max_reference_size);
4673
4674
4675 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4676 hw->dpb.reorder_pic_num =
4677 get_max_dec_frame_buf_size(level_idc,
4678 max_reference_size, mb_width, mb_height);
4679
4680 dpb_print(DECODE_ID(hw), 0,
4681 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4682 hw->bitstream_restriction_flag,
4683 hw->max_dec_frame_buffering,
4684 hw->dpb.reorder_pic_num);
4685
4686 if ((hw->bitstream_restriction_flag) &&
4687 (hw->max_dec_frame_buffering <
4688 hw->dpb.reorder_pic_num)) {
4689 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4690 dpb_print(DECODE_ID(hw), 0,
4691 "set reorder_pic_num to %d\n",
4692 hw->dpb.reorder_pic_num);
4693 }
4694
4695 active_buffer_spec_num =
4696 hw->dpb.reorder_pic_num
4697 + used_reorder_dpb_size_margin;
4698 hw->max_reference_size =
4699 max_reference_size + reference_buf_margin;
4700
4701 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4702 active_buffer_spec_num = MAX_VF_BUF_NUM;
4703 hw->dpb.reorder_pic_num = active_buffer_spec_num
4704 - used_reorder_dpb_size_margin;
4705 }
4706 hw->dpb.mDPB.size = active_buffer_spec_num;
4707 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4708 hw->max_reference_size = MAX_VF_BUF_NUM;
4709 hw->dpb.max_reference_size = hw->max_reference_size;
4710
4711 if (hw->no_poc_reorder_flag)
4712 hw->dpb.reorder_pic_num = 1;
4713 dpb_print(DECODE_ID(hw), 0,
4714 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4715 __func__, active_buffer_spec_num,
4716 hw->dpb.reorder_pic_num,
4717 hw->max_reference_size);
4718
4719 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4720
4721 mutex_lock(&vmh264_mutex);
4722 if (!hw->mmu_enable) {
4723 config_buf_specs(vdec);
4724 i = get_buf_spec_by_canvas_pos(hw, 0);
4725
4726 if (hw->is_used_v4l) {
4727 if (i != -1) {
4728 pr_info("v4l: delay alloc the buffer.\n");
4729 }
4730 } else {
4731 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4732 config_decode_canvas(hw, i);
4733 else
4734 ret = -1;
4735 }
4736 } else {
4737 if (hw->double_write_mode) {
4738 config_buf_specs_ex(vdec);
4739 } else {
4740 spin_lock_irqsave(&hw->bufspec_lock, flags);
4741 for (i = 0, j = 0;
4742 j < active_buffer_spec_num
4743 && i < BUFSPEC_POOL_SIZE;
4744 i++) {
4745 if (hw->buffer_spec[i].used != -1)
4746 continue;
4747 hw->buffer_spec[i].used = 0;
4748 hw->buffer_spec[i].
4749 alloc_header_addr = 0;
4750 hw->buffer_spec[i].canvas_pos = j;
4751 j++;
4752 }
4753 spin_unlock_irqrestore(&hw->bufspec_lock,
4754 flags);
4755 }
4756 hevc_mcr_config_canv2axitbl(hw, 0);
4757 }
4758 mutex_unlock(&vmh264_mutex);
4759 if (dpb_is_debug(DECODE_ID(hw),
4760 PRINT_FLAG_DUMP_BUFSPEC))
4761 dump_bufspec(hw, __func__);
4762
4763#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4764 buf_size = PAGE_ALIGN(
4765 p_H264_Dpb->colocated_buf_size *
4766 active_buffer_spec_num);
4767#else
4768 buf_size = PAGE_ALIGN(
4769 p_H264_Dpb->colocated_buf_size *
4770 hw->max_reference_size);
4771#endif
4772
4773 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4774 buf_size, DRIVER_NAME,
4775 &hw->collocate_cma_alloc_addr) < 0)
4776 return -1;
4777 if (!vdec_secure(vdec)) {
4778 /* clear for some mosaic problem after reset bufmgr */
4779 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4780 if (colocate_vaddr != NULL) {
4781 memset(colocate_vaddr, 0, buf_size);
4782 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4783 codec_mm_unmap_phyaddr(colocate_vaddr);
4784 }
4785 }
4786
4787 hw->dpb.colocated_mv_addr_start =
4788 hw->collocate_cma_alloc_addr;
4789#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4790 hw->dpb.colocated_mv_addr_end =
4791 hw->dpb.colocated_mv_addr_start +
4792 (p_H264_Dpb->colocated_buf_size *
4793 active_buffer_spec_num);
4794#else
4795 hw->dpb.colocated_mv_addr_end =
4796 hw->dpb.colocated_mv_addr_start +
4797 (p_H264_Dpb->colocated_buf_size *
4798 hw->max_reference_size);
4799#endif
4800 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4801 "callocate cma, %lx, %x\n",
4802 hw->collocate_cma_alloc_addr,
4803 hw->dpb.colocated_mv_addr_start);
4804
4805 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4806 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4807 hw->dpb.colocated_mv_addr_start,
4808 hw->dpb.colocated_mv_addr_end);
4809 if (!hw->mmu_enable) {
4810 mutex_lock(&vmh264_mutex);
4811 if (ret >= 0 && hw->decode_pic_count == 0) {
4812 int buf_cnt;
4813 /* h264_reconfig: alloc later*/
4814 buf_cnt = hw->dpb.mDPB.size;
4815
4816 for (j = 1; j < buf_cnt; j++) {
4817 i = get_buf_spec_by_canvas_pos(hw, j);
4818
4819 if (hw->is_used_v4l) {
4820 pr_info("v4l: delay alloc the buffer.\n");
4821 break;
4822 } else if (alloc_one_buf_spec(hw, i) < 0)
4823 break;
4824
4825 config_decode_canvas(hw, i);
4826 }
4827 }
4828 mutex_unlock(&vmh264_mutex);
4829 } else {
4830 vh264_config_canvs_for_mmu(hw);
4831 }
4832
4833 hw->config_bufmgr_done = 1;
4834
4835 /*end of config_bufmgr_done */
4836 }
4837
4838 return ret;
4839}
4840
4841static void vui_config(struct vdec_h264_hw_s *hw)
4842{
4843 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4844 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4845 /*time*/
4846 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4847 hw->time_scale = p_H264_Dpb->time_scale;
4848 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4849
4850 hw->bitstream_restriction_flag =
4851 p_H264_Dpb->bitstream_restriction_flag;
4852 hw->num_reorder_frames =
4853 p_H264_Dpb->num_reorder_frames;
4854 hw->max_dec_frame_buffering =
4855 p_H264_Dpb->max_dec_frame_buffering;
4856
4857 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4858 "vui_config: pdb %d, %d, %d\n",
4859 p_H264_Dpb->bitstream_restriction_flag,
4860 p_H264_Dpb->num_reorder_frames,
4861 p_H264_Dpb->max_dec_frame_buffering);
4862
4863 hw->fixed_frame_rate_flag = 0;
4864 if (hw->timing_info_present_flag) {
4865 hw->fixed_frame_rate_flag =
4866 p_H264_Dpb->fixed_frame_rate_flag;
4867
4868 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4869 ((!hw->sync_outside) ||
4870 (!hw->frame_dur)))
4871 && hw->num_units_in_tick && hw->time_scale) {
4872 if (hw->use_idr_framerate ||
4873 hw->fixed_frame_rate_flag ||
4874 !hw->frame_dur ||
4875 !hw->duration_from_pts_done
4876 /*|| vh264_running*/) {
4877 u32 frame_dur_es =
4878 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4879 hw->time_scale);
4880 if (hw->frame_dur != frame_dur_es) {
4881 hw->h264_first_valid_pts_ready = false;
4882 hw->h264pts1 = 0;
4883 hw->h264pts2 = 0;
4884 hw->h264_pts_count = 0;
4885 hw->duration_from_pts_done = 0;
4886 fixed_frame_rate_mode =
4887 FIX_FRAME_RATE_OFF;
4888 hw->pts_duration = 0;
4889 hw->frame_dur = frame_dur_es;
4890 vdec_schedule_work(&hw->notify_work);
4891 dpb_print(DECODE_ID(hw),
4892 PRINT_FLAG_DEC_DETAIL,
4893 "frame_dur %d from timing_info\n",
4894 hw->frame_dur);
4895 }
4896
4897 /*hack to avoid use ES frame duration when
4898 *it's half of the rate from system info
4899 * sometimes the encoder is given a wrong
4900 * frame rate but the system side information
4901 * is more reliable
4902 *if ((frame_dur * 2) != frame_dur_es) {
4903 * frame_dur = frame_dur_es;
4904 *}
4905 */
4906 }
4907 }
4908 } else {
4909 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4910 "H.264: timing_info not present\n");
4911 }
4912
4913 /*aspect ratio*/
4914 aspect_ratio_info_present_flag =
4915 p_H264_Dpb->vui_status & 0x1;
4916 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4917
4918 if (aspect_ratio_info_present_flag) {
4919 if (aspect_ratio_idc == EXTEND_SAR) {
4920 hw->h264_ar = 0x3ff;
4921 hw->height_aspect_ratio =
4922 p_H264_Dpb->aspect_ratio_sar_height;
4923 hw->width_aspect_ratio =
4924 p_H264_Dpb->aspect_ratio_sar_width;
4925 } else {
4926 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4927 aspect_ratio_idc); */
4928
4929 switch (aspect_ratio_idc) {
4930 case 1:
4931 hw->h264_ar = 0x3ff;
4932 hw->height_aspect_ratio = 1;
4933 hw->width_aspect_ratio = 1;
4934 break;
4935 case 2:
4936 hw->h264_ar = 0x3ff;
4937 hw->height_aspect_ratio = 11;
4938 hw->width_aspect_ratio = 12;
4939 break;
4940 case 3:
4941 hw->h264_ar = 0x3ff;
4942 hw->height_aspect_ratio = 11;
4943 hw->width_aspect_ratio = 10;
4944 break;
4945 case 4:
4946 hw->h264_ar = 0x3ff;
4947 hw->height_aspect_ratio = 11;
4948 hw->width_aspect_ratio = 16;
4949 break;
4950 case 5:
4951 hw->h264_ar = 0x3ff;
4952 hw->height_aspect_ratio = 33;
4953 hw->width_aspect_ratio = 40;
4954 break;
4955 case 6:
4956 hw->h264_ar = 0x3ff;
4957 hw->height_aspect_ratio = 11;
4958 hw->width_aspect_ratio = 24;
4959 break;
4960 case 7:
4961 hw->h264_ar = 0x3ff;
4962 hw->height_aspect_ratio = 11;
4963 hw->width_aspect_ratio = 20;
4964 break;
4965 case 8:
4966 hw->h264_ar = 0x3ff;
4967 hw->height_aspect_ratio = 11;
4968 hw->width_aspect_ratio = 32;
4969 break;
4970 case 9:
4971 hw->h264_ar = 0x3ff;
4972 hw->height_aspect_ratio = 33;
4973 hw->width_aspect_ratio = 80;
4974 break;
4975 case 10:
4976 hw->h264_ar = 0x3ff;
4977 hw->height_aspect_ratio = 11;
4978 hw->width_aspect_ratio = 18;
4979 break;
4980 case 11:
4981 hw->h264_ar = 0x3ff;
4982 hw->height_aspect_ratio = 11;
4983 hw->width_aspect_ratio = 15;
4984 break;
4985 case 12:
4986 hw->h264_ar = 0x3ff;
4987 hw->height_aspect_ratio = 33;
4988 hw->width_aspect_ratio = 64;
4989 break;
4990 case 13:
4991 hw->h264_ar = 0x3ff;
4992 hw->height_aspect_ratio = 99;
4993 hw->width_aspect_ratio = 160;
4994 break;
4995 case 14:
4996 hw->h264_ar = 0x3ff;
4997 hw->height_aspect_ratio = 3;
4998 hw->width_aspect_ratio = 4;
4999 break;
5000 case 15:
5001 hw->h264_ar = 0x3ff;
5002 hw->height_aspect_ratio = 2;
5003 hw->width_aspect_ratio = 3;
5004 break;
5005 case 16:
5006 hw->h264_ar = 0x3ff;
5007 hw->height_aspect_ratio = 1;
5008 hw->width_aspect_ratio = 2;
5009 break;
5010 default:
5011 if (hw->vh264_ratio >> 16) {
5012 hw->h264_ar = (hw->frame_height *
5013 (hw->vh264_ratio & 0xffff) *
5014 0x100 +
5015 ((hw->vh264_ratio >> 16) *
5016 hw->frame_width / 2)) /
5017 ((hw->vh264_ratio >> 16) *
5018 hw->frame_width);
5019 hw->height_aspect_ratio = 1;
5020 hw->width_aspect_ratio = 1;
5021 } else {
5022 hw->h264_ar = 0x3ff;
5023 hw->height_aspect_ratio = 1;
5024 hw->width_aspect_ratio = 1;
5025 }
5026 break;
5027 }
5028 }
5029 } else {
5030 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5031 "v264dec: aspect_ratio not available from source\n");
5032 if (hw->vh264_ratio >> 16) {
5033 /* high 16 bit is width, low 16 bit is height */
5034 hw->h264_ar =
5035 ((hw->vh264_ratio & 0xffff) *
5036 hw->frame_height * 0x100 +
5037 (hw->vh264_ratio >> 16) *
5038 hw->frame_width / 2) /
5039 ((hw->vh264_ratio >> 16) *
5040 hw->frame_width);
5041 hw->height_aspect_ratio = 1;
5042 hw->width_aspect_ratio = 1;
5043 } else {
5044 hw->h264_ar = 0x3ff;
5045 hw->height_aspect_ratio = 1;
5046 hw->width_aspect_ratio = 1;
5047 }
5048 }
5049
5050 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
5051 if (((hw->frame_dur == RATE_2397_FPS)
5052 && (dec_control
5053 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
5054 || ((RATE_2997_FPS ==
5055 hw->frame_dur) &&
5056 (dec_control &
5057 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
5058 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5059 "force fix frame rate\n");
5060 hw->fixed_frame_rate_flag = 0x40;
5061 }
5062 }
5063
5064 /*video_signal_from_vui: to do .. */
5065}
5066
5067static void bufmgr_recover(struct vdec_h264_hw_s *hw)
5068{
5069 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5070
5071 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5072 if (error_proc_policy & 0x20) {
5073 if (!hw->is_used_v4l)
5074 hw->reset_bufmgr_flag = 1;
5075 }
5076}
5077
5078void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
5079{
5080 struct vdec_h264_hw_s *hw =
5081 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
5082
5083 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5084
5085 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5086 hw->reset_bufmgr_flag = 1;
5087}
5088
5089#ifdef CONSTRAIN_MAX_BUF_NUM
5090static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5091{
5092 int i;
5093 int count = 0;
5094 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5095 if (is_buf_spec_in_disp_q(hw, i) &&
5096 hw->buffer_spec[i].vf_ref > 0)
5097 count++;
5098 }
5099 return count;
5100}
5101
5102static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5103{
5104 int i;
5105 int count = 0;
5106 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5107 if (is_buf_spec_in_use(hw, i))
5108 count++;
5109 }
5110 return count;
5111}
5112#endif
5113
5114
5115static bool is_buffer_available(struct vdec_s *vdec)
5116{
5117 bool buffer_available = 1;
5118 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5119 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5120 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5121 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5122 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5123 ((p_H264_Dpb->mDPB.init_done) &&
5124 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5125 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5126 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5127 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5128 __func__,
5129 kfifo_len(&hw->newframe_q),
5130 have_free_buf_spec(vdec),
5131 p_H264_Dpb->mDPB.init_done,
5132 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5133 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5134 );
5135 buffer_available = 0;
5136 if (dpb_is_debug(DECODE_ID(hw),
5137 DEBUG_DISABLE_RUNREADY_RMBUF))
5138 return buffer_available;
5139
5140 if ((error_proc_policy & 0x4) &&
5141 (error_proc_policy & 0x8)) {
5142 if ((kfifo_len(&hw->display_q) <= 0) &&
5143 (p_H264_Dpb->mDPB.used_size ==
5144 p_H264_Dpb->mDPB.size) &&
5145 (p_Dpb->ref_frames_in_buffer >
5146 (imax(
5147 1, p_Dpb->num_ref_frames)
5148 - p_Dpb->ltref_frames_in_buffer +
5149 force_sliding_margin)))
5150 bufmgr_recover(hw);
5151 else
5152 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5153 } else if ((error_proc_policy & 0x4) &&
5154 (kfifo_len(&hw->display_q) <= 0) &&
5155 ((p_H264_Dpb->mDPB.used_size ==
5156 p_H264_Dpb->mDPB.size) ||
5157 (!have_free_buf_spec(vdec)))) {
5158 enum receviver_start_e state = RECEIVER_INACTIVE;
5159 if ((error_proc_policy & 0x10) &&
5160 vf_get_receiver(vdec->vf_provider_name)) {
5161 state =
5162 vf_notify_receiver(vdec->vf_provider_name,
5163 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5164 NULL);
5165 if ((state == RECEIVER_STATE_NULL)
5166 || (state == RECEIVER_STATE_NONE))
5167 state = RECEIVER_INACTIVE;
5168 }
5169 if (state == RECEIVER_INACTIVE)
5170 bufmgr_recover(hw);
5171 else
5172 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5173 } else if ((error_proc_policy & 0x8) &&
5174 (p_Dpb->ref_frames_in_buffer >
5175 (imax(
5176 1, p_Dpb->num_ref_frames)
5177 - p_Dpb->ltref_frames_in_buffer +
5178 force_sliding_margin)))
5179 bufmgr_recover(hw);
5180 else
5181 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5182
5183 if (hw->reset_bufmgr_flag == 1)
5184 buffer_available = 1;
5185 else if (hw->is_used_v4l)
5186 buffer_available = have_free_buf_spec(vdec);
5187 }
5188
5189 return buffer_available;
5190}
5191
5192#define AUX_TAG_SEI 0x2
5193
5194#define SEI_BUFFERING_PERIOD 0
5195#define SEI_PicTiming 1
5196#define SEI_USER_DATA 4
5197#define SEI_RECOVERY_POINT 6
5198
5199/*
5200 *************************************************************************
5201 * Function:Reads bits from the bitstream buffer
5202 * Input:
5203 byte buffer[]
5204 containing sei message data bits
5205 int totbitoffset
5206 bit offset from start of partition
5207 int bytecount
5208 total bytes in bitstream
5209 int numbits
5210 number of bits to read
5211 * Output:
5212 int *info
5213 * Return:
5214 -1: failed
5215 > 0: the count of bit read
5216 * Attention:
5217 *************************************************************************
5218 */
5219
5220static int get_bits(unsigned char buffer[],
5221 int totbitoffset,
5222 int *info,
5223 int bytecount,
5224 int numbits)
5225{
5226 register int inf;
5227 long byteoffset;
5228 int bitoffset;
5229
5230 int bitcounter = numbits;
5231
5232 byteoffset = totbitoffset / 8;
5233 bitoffset = 7 - (totbitoffset % 8);
5234
5235 inf = 0;
5236 while (numbits) {
5237 inf <<= 1;
5238 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5239 numbits--;
5240 bitoffset--;
5241 if (bitoffset < 0) {
5242 byteoffset++;
5243 bitoffset += 8;
5244 if (byteoffset > bytecount)
5245 return -1;
5246 }
5247 }
5248
5249 *info = inf;
5250
5251
5252 return bitcounter;
5253}
5254
5255static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5256 u8 *sei_data_buf,
5257 u8 *sei_data_buf_end)
5258{
5259 int payload_type;
5260 int payload_size;
5261 u8 *p_sei;
5262 int temp = 0;
5263 int bit_offset;
5264 int read_size;
5265 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5266
5267 p_sei = sei_data_buf;
5268 read_size = 0;
5269 payload_type = 0;
5270 do {
5271 if (p_sei >= sei_data_buf_end)
5272 return read_size;
5273
5274 payload_type += *p_sei;
5275 read_size++;
5276 } while (*p_sei++ == 255);
5277
5278
5279 payload_size = 0;
5280 do {
5281 if (p_sei >= sei_data_buf_end)
5282 return read_size;
5283
5284 payload_size += *p_sei;
5285 read_size++;
5286 } while (*p_sei++ == 255);
5287
5288
5289 if (p_sei + payload_size > sei_data_buf_end) {
5290 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5291 "%s: payload_type = %d, payload_size = %d is over\n",
5292 __func__, payload_type, payload_size);
5293 return read_size;
5294 }
5295 bit_offset = 0;
5296
5297 if (payload_size <= 0) {
5298 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5299 "%s warning: this is a null sei message for payload_type = %d\n",
5300 __func__, payload_type);
5301 return read_size;
5302 }
5303 switch (payload_type) {
5304 case SEI_BUFFERING_PERIOD:
5305 break;
5306 case SEI_PicTiming:
5307 if (p_H264_Dpb->vui_status & 0xc) {
5308 int cpb_removal_delay;
5309 int dpb_output_delay;
5310 u32 delay_len;
5311
5312 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5313 cpb_removal_delay
5314 = (delay_len & 0x1F) + 1;
5315 dpb_output_delay
5316 = ((delay_len >> 5) & 0x1F) + 1;
5317
5318 get_bits(p_sei, bit_offset,
5319 &temp, payload_size,
5320 dpb_output_delay+cpb_removal_delay);
5321 bit_offset += dpb_output_delay+cpb_removal_delay;
5322 }
5323 if (p_H264_Dpb->vui_status & 0x10) {
5324 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5325 bit_offset += 4;
5326 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5327 }
5328 break;
5329 case SEI_USER_DATA:
5330 if (enable_itu_t35) {
5331 int i;
5332 int j;
5333 int data_len;
5334 u8 *user_data_buf;
5335
5336 user_data_buf
5337 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5338 /* user data length should be align with 8 bytes,
5339 if not, then padding with zero*/
5340 for (i = 0; i < payload_size; i += 8) {
5341 for (j = 0; j < 8; j++) {
5342 int index;
5343
5344 index = i+7-j;
5345 if (index >= payload_size)
5346 user_data_buf[i+j] = 0;
5347 else
5348 user_data_buf[i+j]
5349 = p_sei[i+7-j];
5350 }
5351 }
5352
5353 data_len = payload_size;
5354 if (payload_size % 8)
5355 data_len = ((payload_size + 8) >> 3) << 3;
5356
5357 hw->sei_itu_data_len += data_len;
5358 /*
5359 dpb_print(DECODE_ID(hw), 0,
5360 "%s: user data, and len = %d:\n",
5361 __func__, hw->sei_itu_data_len);
5362 */
5363 }
5364 break;
5365 case SEI_RECOVERY_POINT:
5366 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5367 break;
5368 }
5369
5370 return read_size + payload_size;
5371}
5372
5373static void parse_sei_data(struct vdec_h264_hw_s *hw,
5374 u8 *sei_data_buf,
5375 int len)
5376{
5377 char *p_sei;
5378 char *p_sei_end;
5379 int parsed_size;
5380 int read_size;
5381
5382
5383 p_sei = sei_data_buf;
5384 p_sei_end = p_sei + len;
5385 parsed_size = 0;
5386 while (parsed_size < len) {
5387 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5388 p_sei += read_size;
5389 parsed_size += read_size;
5390 if (*p_sei == 0x80) {
5391 p_sei++;
5392 parsed_size++;
5393 }
5394 }
5395}
5396
5397static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5398{
5399 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5400 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5401 unsigned mby_mbx = READ_VREG(MBY_MBX);
5402 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5403 unsigned decode_mb_count =
5404 ((mby_mbx & 0xff) * hw->mb_width +
5405 (((mby_mbx >> 8) & 0xff) + 1));
5406 if (mby_mbx == 0)
5407 return;
5408 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5409 mb_total /= 2;
5410 if (error_proc_policy & 0x100) {
5411 if (decode_mb_count < mb_total)
5412 p->data_flag |= ERROR_FLAG;
5413 }
5414
5415 if ((error_proc_policy & 0x200) &&
5416 READ_VREG(ERROR_STATUS_REG) != 0) {
5417 p->data_flag |= ERROR_FLAG;
5418 }
5419
5420 if (p->data_flag & ERROR_FLAG) {
5421 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5422 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5423 __func__,
5424 hw->seq_info2,
5425 mby_mbx,
5426 mb_total,
5427 decode_mb_count,
5428 READ_VREG(ERROR_STATUS_REG)
5429 );
5430
5431 }
5432}
5433
5434static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5435{
5436 int i;
5437 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5438 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5439 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5440 u32 debug_tag;
5441 int ret;
5442
5443 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5444#if 1
5445 unsigned short *p = (unsigned short *)hw->lmem_addr;
5446 dma_sync_single_for_cpu(
5447 amports_get_dma_device(),
5448 hw->lmem_addr_remap,
5449 PAGE_SIZE,
5450 DMA_FROM_DEVICE);
5451 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5452 int ii;
5453 for (ii = 0; ii < 4; ii++) {
5454 p_H264_Dpb->dpb_param.l.data[i+ii] =
5455 p[i+3-ii];
5456 if (dpb_is_debug(DECODE_ID(hw),
5457 RRINT_FLAG_RPM)) {
5458 if (((i + ii) & 0xf) == 0)
5459 dpb_print(DECODE_ID(hw),
5460 0, "%04x:",
5461 i);
5462 dpb_print_cont(DECODE_ID(hw),
5463 0, "%04x ",
5464 p[i+3-ii]);
5465 if (((i + ii + 1) & 0xf) == 0)
5466 dpb_print_cont(
5467 DECODE_ID(hw),
5468 0, "\r\n");
5469 }
5470 }
5471 }
5472
5473 p_H264_Dpb->bitstream_restriction_flag =
5474 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5475 p_H264_Dpb->num_reorder_frames =
5476 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5477 p_H264_Dpb->max_dec_frame_buffering =
5478 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5479
5480 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5481 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5482 p_H264_Dpb->bitstream_restriction_flag,
5483 p_H264_Dpb->num_reorder_frames,
5484 p_H264_Dpb->max_dec_frame_buffering);
5485 hw->bitstream_restriction_flag =
5486 p_H264_Dpb->bitstream_restriction_flag;
5487 hw->num_reorder_frames =
5488 p_H264_Dpb->num_reorder_frames;
5489 hw->max_dec_frame_buffering =
5490 p_H264_Dpb->max_dec_frame_buffering;
5491#endif
5492
5493 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5494 reset_process_time(hw);
5495 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5496 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5497 vdec_schedule_work(&hw->work);
5498 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5499 u16 data_hight;
5500 u16 data_low;
5501 u32 video_signal;
5502
5503 int slice_header_process_status = 0;
5504 int I_flag;
5505 /*unsigned char is_idr;*/
5506 unsigned short *p = (unsigned short *)hw->lmem_addr;
5507 reset_process_time(hw);
5508
5509 if (hw->is_used_v4l) {
5510 struct aml_vcodec_ctx *ctx =
5511 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5512
5513 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5514 //amvdec_stop();
5515 hw->dec_result = DEC_RESULT_DONE;
5516 vdec_schedule_work(&hw->work);
5517 return IRQ_HANDLED;
5518 }
5519 }
5520
5521 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5522 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5523 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5524 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5525 if (input_frame_based(vdec) &&
5526 frmbase_cont_bitlevel2 != 0 &&
5527 READ_VREG(VIFF_BIT_CNT) <
5528 frmbase_cont_bitlevel2 &&
5529 hw->get_data_count >= 0x70000000) {
5530 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5531 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5532 __func__,
5533 READ_VREG(VIFF_BIT_CNT));
5534
5535 goto empty_proc;
5536 }
5537
5538 dma_sync_single_for_cpu(
5539 amports_get_dma_device(),
5540 hw->lmem_addr_remap,
5541 PAGE_SIZE,
5542 DMA_FROM_DEVICE);
5543#if 0
5544 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5545 if (!is_buffer_available(vdec)) {
5546 hw->buffer_empty_flag = 1;
5547 dpb_print(DECODE_ID(hw),
5548 PRINT_FLAG_UCODE_EVT,
5549 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5550 __func__,
5551 kfifo_len(&hw->newframe_q),
5552 have_free_buf_spec(vdec),
5553 p_H264_Dpb->mDPB.init_done,
5554 p_H264_Dpb->mDPB.used_size,
5555 p_H264_Dpb->mDPB.size,
5556 is_there_unused_frame_from_dpb(
5557 &p_H264_Dpb->mDPB));
5558 return IRQ_HANDLED;
5559 }
5560 }
5561
5562 hw->buffer_empty_flag = 0;
5563#endif
5564#ifdef SEND_PARAM_WITH_REG
5565 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5566 unsigned int data32;
5567
5568 do {
5569 data32 = READ_VREG(RPM_CMD_REG);
5570 /* printk("%x\n", data32); */
5571 } while ((data32&0x10000) == 0);
5572 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5573 WRITE_VREG(RPM_CMD_REG, 0);
5574 /* printk("%x:%x\n", i,data32); */
5575 }
5576#else
5577 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5578 int ii;
5579
5580 for (ii = 0; ii < 4; ii++) {
5581 p_H264_Dpb->dpb_param.l.data[i+ii] =
5582 p[i+3-ii];
5583 if (dpb_is_debug(DECODE_ID(hw),
5584 RRINT_FLAG_RPM)) {
5585 if (((i + ii) & 0xf) == 0)
5586 dpb_print(DECODE_ID(hw),
5587 0, "%04x:",
5588 i);
5589 dpb_print_cont(DECODE_ID(hw),
5590 0, "%04x ",
5591 p[i+3-ii]);
5592 if (((i + ii + 1) & 0xf) == 0)
5593 dpb_print_cont(
5594 DECODE_ID(hw),
5595 0, "\r\n");
5596 }
5597 }
5598 }
5599#endif
5600 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5601 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5602
5603 video_signal = (data_hight << 16) | data_low;
5604 hw->video_signal_from_vui =
5605 ((video_signal & 0xffff) << 8) |
5606 ((video_signal & 0xff0000) >> 16) |
5607 ((video_signal & 0x3f000000));
5608
5609
5610 /*dpb_print(DECODE_ID(hw),
5611 0,
5612 "video_signal_from_vui:0x%x, "
5613 "data_low:0x%x, data_hight:0x%x\n",
5614 hw->video_signal_from_vui,
5615 data_low,
5616 data_hight);*/
5617
5618 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5619
5620 if (hw->config_bufmgr_done == 0) {
5621 hw->dec_result = DEC_RESULT_DONE;
5622 vdec_schedule_work(&hw->work);
5623 dpb_print(DECODE_ID(hw),
5624 PRINT_FLAG_UCODE_EVT,
5625 "config_bufmgr not done, discard frame\n");
5626 return IRQ_HANDLED;
5627 } else if ((hw->first_i_policy & 0x3) != 0) {
5628 unsigned char is_i_slice =
5629 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5630 == I_Slice)
5631 ? 1 : 0;
5632 unsigned char is_idr =
5633 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5634 == 5);
5635 if ((hw->first_i_policy & 0x3) == 0x3)
5636 is_i_slice = is_idr;
5637 if (!is_i_slice) {
5638 if (hw->has_i_frame == 0) {
5639 amvdec_stop();
5640 vdec->mc_loaded = 0;
5641 hw->dec_result = DEC_RESULT_DONE;
5642 vdec_schedule_work(&hw->work);
5643 dpb_print(DECODE_ID(hw),
5644 PRINT_FLAG_UCODE_EVT,
5645 "has_i_frame is 0, discard none I(DR) frame\n");
5646 return IRQ_HANDLED;
5647 }
5648 } else {
5649 if (hw->skip_frame_count < 0 || is_idr) {
5650 /* second I */
5651 hw->dec_flag &= (~NODISP_FLAG);
5652 hw->skip_frame_count = 0;
5653 }
5654 if (hw->has_i_frame == 0 &&
5655 (!is_idr)) {
5656 int skip_count =
5657 (hw->first_i_policy >> 8) & 0xff;
5658 /* first I (not IDR) */
5659 if ((hw->first_i_policy & 0x3) == 2)
5660 hw->skip_frame_count =
5661 -1 - skip_count;
5662 else
5663 hw->skip_frame_count =
5664 skip_count;
5665 if (hw->skip_frame_count != 0)
5666 hw->dec_flag |= NODISP_FLAG;
5667 }
5668 }
5669 }
5670 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5671 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5672 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5673 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5674 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5675 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5676 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5677 ? I_FLAG : 0;
5678
5679 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5680 flush_dpb(p_H264_Dpb);
5681
5682 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5683 (p_H264_Dpb->mSlice.structure == FRAME)) {
5684 hw->data_flag = NULL_FLAG;
5685 goto pic_done_proc;
5686 }
5687
5688 slice_header_process_status =
5689 h264_slice_header_process(p_H264_Dpb);
5690 if (hw->mmu_enable)
5691 hevc_sao_set_slice_type(hw,
5692 slice_header_process_status,
5693 hw->dpb.mSlice.idr_flag);
5694 vui_config(hw);
5695
5696 if (p_H264_Dpb->mVideo.dec_picture) {
5697 int cfg_ret = 0;
5698 bool field_pic_flag = false;
5699
5700 if (slice_header_process_status == 1) {
5701 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5702 field_pic_flag =
5703 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5704 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5705 true : false;
5706 }
5707
5708 if (!field_pic_flag && (((p_H264_Dpb->mSPS.profile_idc == BASELINE) &&
5709 (p_H264_Dpb->reorder_pic_num < 2)) ||
5710 (((unsigned long)(hw->vh264_amstream_dec_info
5711 .param)) & 0x8))) {
5712 p_H264_Dpb->fast_output_enable =
5713 H264_OUTPUT_MODE_FAST;
5714 }
5715 else
5716 p_H264_Dpb->fast_output_enable
5717 = fast_output_enable;
5718 hw->data_flag = I_flag;
5719 if ((p_H264_Dpb->
5720 dpb_param.dpb.NAL_info_mmco & 0x1f)
5721 == 5)
5722 hw->data_flag |= IDR_FLAG;
5723 dpb_print(DECODE_ID(hw),
5724 PRINT_FLAG_VDEC_STATUS,
5725 "==================> frame count %d to skip %d\n",
5726 hw->decode_pic_count+1,
5727 hw->skip_frame_count);
5728 } else if (error_proc_policy & 0x100){
5729 struct StorablePicture *p =
5730 p_H264_Dpb->mVideo.dec_picture;
5731 unsigned mby_mbx = READ_VREG(MBY_MBX);
5732 unsigned decode_mb_count =
5733 ((mby_mbx & 0xff) * hw->mb_width +
5734 (((mby_mbx >> 8) & 0xff) + 1));
5735 if (decode_mb_count <
5736 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5737 (1 + p->mb_aff_frame_flag))) {
5738 dpb_print(DECODE_ID(hw),
5739 PRINT_FLAG_VDEC_STATUS,
5740 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5741 p_H264_Dpb->dpb_param.l.
5742 data[FIRST_MB_IN_SLICE],
5743 READ_VREG(MBY_MBX),
5744 decode_mb_count);
5745 p->data_flag |= ERROR_FLAG;
5746 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5747 p->data_flag |= ERROR_FLAG;
5748 goto pic_done_proc;
5749 }
5750 }
5751
5752 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5753 hw->new_iframe_flag = 1;
5754 }
5755 if (hw->new_iframe_flag) {
5756 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5757 hw->new_iframe_flag = 0;
5758 hw->ref_err_flush_dpb_flag = 1;
5759 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5760 hw->new_iframe_flag = 0;
5761 hw->ref_err_flush_dpb_flag = 0;
5762 }
5763 }
5764
5765 if (error_proc_policy & 0x400) {
5766 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5767 if (ret != 0) {
5768 hw->reflist_error_count ++;
5769 dpb_print(DECODE_ID(hw), 0,
5770 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5771 ret,
5772 hw->decode_pic_count+1,
5773 hw->skip_frame_count,
5774 hw->reflist_error_count);
5775
5776 if (hw->ref_err_flush_dpb_flag) {
5777 flush_dpb(p_H264_Dpb);
5778 p_H264_Dpb->colocated_buf_map = 0;
5779 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5780 p_H264_Dpb->colocated_buf_map |= 1 <<
5781 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5782 }
5783 }
5784
5785 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5786 if (((error_proc_policy & 0x80)
5787 && ((hw->dec_flag &
5788 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5789 hw->reset_bufmgr_flag = 1;
5790 hw->reflist_error_count =0;
5791 amvdec_stop();
5792 vdec->mc_loaded = 0;
5793 hw->dec_result = DEC_RESULT_DONE;
5794 vdec_schedule_work(&hw->work);
5795 return IRQ_HANDLED;
5796 }
5797 } else
5798 hw->reflist_error_count = 0;
5799 }
5800 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5801 && p_H264_Dpb->dpb_error_flag != 0) {
5802 dpb_print(DECODE_ID(hw), 0,
5803 "dpb error %d\n",
5804 p_H264_Dpb->dpb_error_flag);
5805 hw->data_flag |= ERROR_FLAG;
5806 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5807 if ((error_proc_policy & 0x80) &&
5808 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5809 hw->reset_bufmgr_flag = 1;
5810 amvdec_stop();
5811 vdec->mc_loaded = 0;
5812 hw->dec_result = DEC_RESULT_DONE;
5813 vdec_schedule_work(&hw->work);
5814 return IRQ_HANDLED;
5815 }
5816 }
5817
5818 cfg_ret = config_decode_buf(hw,
5819 p_H264_Dpb->mVideo.dec_picture);
5820 if (cfg_ret < 0) {
5821 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5822 "config_decode_buf fail (%d)\n",
5823 cfg_ret);
5824 if (error_proc_policy & 0x2) {
5825 release_cur_decoding_buf(hw);
5826 /*hw->data_flag |= ERROR_FLAG;*/
5827 hw->reset_bufmgr_flag = 1;
5828 hw->dec_result = DEC_RESULT_DONE;
5829 vdec_schedule_work(&hw->work);
5830 return IRQ_HANDLED;
5831 } else
5832 hw->data_flag |= ERROR_FLAG;
5833 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5834 }
5835 }
5836
5837 if (slice_header_process_status == 1)
5838 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5839 else
5840 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5841 hw->last_mby_mbx = 0;
5842 hw->last_vld_level = 0;
5843 start_process_time(hw);
5844 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5845 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5846pic_done_proc:
5847 reset_process_time(hw);
5848
5849 if (input_frame_based(vdec) &&
5850 (!(hw->i_only & 0x2)) &&
5851 frmbase_cont_bitlevel != 0 &&
5852 READ_VREG(VIFF_BIT_CNT) >
5853 frmbase_cont_bitlevel) {
5854 /*handle the case: multi pictures in one packet*/
5855 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5856 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5857 __func__,
5858 hw->decode_pic_count,
5859 READ_VREG(VIFF_BIT_CNT));
5860 hw->frmbase_cont_flag = 1;
5861 } else
5862 hw->frmbase_cont_flag = 0;
5863
5864 if (p_H264_Dpb->mVideo.dec_picture) {
5865 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5866#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5867 DEL_EXIST(hw,
5868 p_H264_Dpb->mVideo.dec_picture) = 0;
5869 if (vdec->master) {
5870 struct vdec_h264_hw_s *hw_ba =
5871 (struct vdec_h264_hw_s *)
5872 vdec->master->private;
5873 if (hw_ba->last_dec_picture)
5874 DEL_EXIST(hw_ba,
5875 hw_ba->last_dec_picture)
5876 = 1;
5877 }
5878#endif
5879 mutex_lock(&hw->chunks_mutex);
5880 if (hw->chunk) {
5881 p_H264_Dpb->mVideo.dec_picture->pts =
5882 hw->chunk->pts;
5883 p_H264_Dpb->mVideo.dec_picture->pts64 =
5884 hw->chunk->pts64;
5885 p_H264_Dpb->mVideo.dec_picture->timestamp =
5886 hw->chunk->timestamp;
5887#ifdef MH264_USERDATA_ENABLE
5888 vmh264_udc_fill_vpts(hw,
5889 p_H264_Dpb->mSlice.slice_type,
5890 hw->chunk->pts, 1);
5891#endif
5892
5893#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5894 } else if (vdec->master) {
5895 /*dv enhance layer,
5896 do not checkout pts*/
5897 struct StorablePicture *pic =
5898 p_H264_Dpb->mVideo.dec_picture;
5899 pic->pts = 0;
5900 pic->pts64 = 0;
5901#endif
5902 } else {
5903 struct StorablePicture *pic =
5904 p_H264_Dpb->mVideo.dec_picture;
5905 u32 offset = pic->offset_delimiter;
5906 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5907 offset, &pic->pts, 0, &pic->pts64)) {
5908 pic->pts = 0;
5909 pic->pts64 = 0;
5910#ifdef MH264_USERDATA_ENABLE
5911 vmh264_udc_fill_vpts(hw,
5912 p_H264_Dpb->mSlice.slice_type,
5913 pic->pts, 0);
5914#endif
5915 } else {
5916#ifdef MH264_USERDATA_ENABLE
5917 vmh264_udc_fill_vpts(hw,
5918 p_H264_Dpb->mSlice.slice_type,
5919 pic->pts, 1);
5920#endif
5921 }
5922
5923 }
5924 mutex_unlock(&hw->chunks_mutex);
5925
5926 check_decoded_pic_error(hw);
5927#ifdef ERROR_HANDLE_TEST
5928 if ((hw->data_flag & ERROR_FLAG)
5929 && (error_proc_policy & 0x80)) {
5930 release_cur_decoding_buf(hw);
5931 h264_clear_dpb(hw);
5932 hw->dec_flag = 0;
5933 hw->data_flag = 0;
5934 hw->skip_frame_count = 0;
5935 hw->has_i_frame = 0;
5936 hw->no_error_count = 0xfff;
5937 hw->no_error_i_count = 0xf;
5938 } else
5939#endif
5940 ret = store_picture_in_dpb(p_H264_Dpb,
5941 p_H264_Dpb->mVideo.dec_picture,
5942 hw->data_flag | hw->dec_flag |
5943 p_H264_Dpb->mVideo.dec_picture->data_flag);
5944
5945
5946
5947 if (ret == -1) {
5948 release_cur_decoding_buf(hw);
5949 bufmgr_force_recover(p_H264_Dpb);
5950 } else {
5951 if (hw->data_flag & ERROR_FLAG) {
5952 hw->no_error_count = 0;
5953 hw->no_error_i_count = 0;
5954 } else {
5955 hw->no_error_count++;
5956 if (hw->data_flag & I_FLAG)
5957 hw->no_error_i_count++;
5958 }
5959 if (hw->mmu_enable)
5960 hevc_set_unused_4k_buff_idx(hw,
5961 p_H264_Dpb->mVideo.
5962 dec_picture->buf_spec_num);
5963 bufmgr_post(p_H264_Dpb);
5964 hw->last_dec_picture =
5965 p_H264_Dpb->mVideo.dec_picture;
5966 p_H264_Dpb->mVideo.dec_picture = NULL;
5967 /* dump_dpb(&p_H264_Dpb->mDPB); */
5968 hw->has_i_frame = 1;
5969 if (hw->mmu_enable)
5970 hevc_set_frame_done(hw);
5971 hw->decode_pic_count++;
5972 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5973 if (hw->skip_frame_count > 0) {
5974 /*skip n frame after first I */
5975 hw->skip_frame_count--;
5976 if (hw->skip_frame_count == 0)
5977 hw->dec_flag &= (~NODISP_FLAG);
5978 } else if (hw->skip_frame_count < -1) {
5979 /*skip n frame after first I until second I */
5980 hw->skip_frame_count++;
5981 if (hw->skip_frame_count == -1)
5982 hw->dec_flag &= (~NODISP_FLAG);
5983 }
5984 }
5985 }
5986 if (hw->frmbase_cont_flag) {
5987 /*do not DEC_RESULT_GET_DATA*/
5988 hw->get_data_count = 0x7fffffff;
5989 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5990 decode_frame_count[DECODE_ID(hw)]++;
5991 start_process_time(hw);
5992 return IRQ_HANDLED;
5993 }
5994 amvdec_stop();
5995 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5996 "%s %s decode slice count %d\n",
5997 __func__,
5998 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5999 "H264_PIC_DATA_DONE" :
6000 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
6001 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
6002 hw->decode_pic_count);
6003 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
6004 hw->dec_result = DEC_RESULT_DONE;
6005#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6006 if (vdec->slave &&
6007 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
6008 struct vdec_h264_hw_s *hw_el =
6009 (struct vdec_h264_hw_s *)(vdec->slave->private);
6010 hw_el->got_valid_nal = 0;
6011 hw->switch_dvlayer_flag = 1;
6012 } else if (vdec->master &&
6013 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
6014 struct vdec_h264_hw_s *hw_bl =
6015 (struct vdec_h264_hw_s *)(vdec->master->private);
6016 hw_bl->got_valid_nal = 0;
6017 hw->switch_dvlayer_flag = 1;
6018 } else {
6019 hw->switch_dvlayer_flag = 0;
6020 hw->got_valid_nal = 1;
6021 }
6022#endif
6023
6024 hw->dec_result = DEC_RESULT_DONE;
6025 vdec_schedule_work(&hw->work);
6026
6027#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6028 } else if (
6029 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
6030 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
6031 goto pic_done_proc;
6032#endif
6033 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
6034 reset_process_time(hw);
6035 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
6036 dma_sync_single_for_cpu(
6037 amports_get_dma_device(),
6038 hw->aux_phy_addr,
6039 hw->prefix_aux_size + hw->suffix_aux_size,
6040 DMA_FROM_DEVICE);
6041 if (dpb_is_debug(DECODE_ID(hw),
6042 PRINT_FLAG_DPB_DETAIL))
6043 dump_aux_buf(hw);
6044#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6045 if (vdec->dolby_meta_with_el || vdec->slave) {
6046 if (hw->last_dec_picture)
6047 set_aux_data(hw, hw->last_dec_picture,
6048 0, 0, NULL);
6049 } else {
6050 if (vdec->master) {
6051 struct vdec_h264_hw_s *hw_bl =
6052 (struct vdec_h264_hw_s *)
6053 (vdec->master->private);
6054 if (hw_bl->last_dec_picture != NULL) {
6055 set_aux_data(hw_bl,
6056 hw_bl->last_dec_picture,
6057 0, 1, hw);
6058 }
6059 set_aux_data(hw,
6060 hw->last_dec_picture,
6061 0, 2, NULL);
6062 }
6063 }
6064#else
6065 if (hw->last_dec_picture)
6066 set_aux_data(hw,
6067 hw->last_dec_picture, 0, 0, NULL);
6068#endif
6069 }
6070#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6071 hw->switch_dvlayer_flag = 0;
6072 hw->got_valid_nal = 1;
6073#endif
6074 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6075 "%s H264_AUX_DATA_READY\n", __func__);
6076 hw->dec_result = DEC_RESULT_DONE;
6077 vdec_schedule_work(&hw->work);
6078 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
6079 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
6080 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
6081 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
6082empty_proc:
6083 reset_process_time(hw);
6084 if (!hw->frmbase_cont_flag)
6085 release_cur_decoding_buf(hw);
6086
6087 if (input_frame_based(vdec) ||
6088 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6089 if (h264_debug_flag &
6090 DISABLE_ERROR_HANDLE) {
6091 dpb_print(DECODE_ID(hw),
6092 PRINT_FLAG_ERROR,
6093 "%s decoding error, level 0x%x\n",
6094 __func__,
6095 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6096 goto send_again;
6097 }
6098 amvdec_stop();
6099 vdec->mc_loaded = 0;
6100 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6101 "%s %s\n", __func__,
6102 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6103 "H264_SEARCH_BUFEMPTY" :
6104 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6105 "H264_DECODE_BUFEMPTY" :
6106 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6107 "H264_DECODE_TIMEOUT" :
6108 "OTHER");
6109 hw->dec_result = DEC_RESULT_DONE;
6110
6111 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6112 hw->search_dataempty_num++;
6113 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6114 hw->decode_timeout_num++;
6115 if (error_proc_policy & 0x4000) {
6116 hw->data_flag |= ERROR_FLAG;
6117 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6118 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6119 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6120 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6121 dpb_print(DECODE_ID(hw),
6122 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6123 p_H264_Dpb->last_dpb_status, __func__);
6124 hw->reset_bufmgr_flag = 1;
6125 }
6126 }
6127 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6128 hw->decode_dataempty_num++;
6129 if (!hw->frmbase_cont_flag)
6130 hw->data_flag |= ERROR_FLAG;
6131
6132 vdec_schedule_work(&hw->work);
6133 } else {
6134 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6135 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6136 "%s DEC_RESULT_AGAIN\n", __func__);
6137send_again:
6138 hw->dec_result = DEC_RESULT_AGAIN;
6139 vdec_schedule_work(&hw->work);
6140 }
6141 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6142 reset_process_time(hw);
6143 if (input_frame_based(vdec)) {
6144 dpb_print(DECODE_ID(hw),
6145 PRINT_FLAG_VDEC_STATUS,
6146 "%s H264_DATA_REQUEST (%d)\n",
6147 __func__, hw->get_data_count);
6148 hw->dec_result = DEC_RESULT_GET_DATA;
6149 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6150 hw->get_data_start_time = jiffies;
6151 hw->get_data_count++;
6152 if (hw->get_data_count >= frame_max_data_packet)
6153 goto empty_proc;
6154 vdec_schedule_work(&hw->work);
6155 } else
6156 goto empty_proc;
6157 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6158 dpb_print(DECODE_ID(hw), 0,
6159 "vmh264 decode oversize !!\n");
6160 release_cur_decoding_buf(hw);
6161 hw->data_flag |= ERROR_FLAG;
6162 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6163 reset_process_time(hw);
6164 hw->dec_result = DEC_RESULT_DONE;
6165 vdec_schedule_work(&hw->work);
6166 return IRQ_HANDLED;
6167 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6168 int aux_data_len;
6169 aux_data_len =
6170 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6171
6172 if (aux_data_len > SEI_DATA_SIZE) {
6173 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6174 "sei data size more than 4K: %d, discarded it\n",
6175 hw->sei_itu_data_len);
6176 hw->sei_itu_data_len = 0;
6177 }
6178
6179 if (aux_data_len != 0) {
6180 u8 *trans_data_buf;
6181 u8 *sei_data_buf;
6182 u8 swap_byte;
6183
6184 dma_sync_single_for_cpu(
6185 amports_get_dma_device(),
6186 hw->aux_phy_addr,
6187 hw->prefix_aux_size + hw->suffix_aux_size,
6188 DMA_FROM_DEVICE);
6189#if 0
6190 dump_aux_buf(hw);
6191#endif
6192 trans_data_buf = (u8 *)hw->aux_addr;
6193
6194 if (trans_data_buf[7] == AUX_TAG_SEI) {
6195 int left_len;
6196
6197 sei_data_buf = (u8 *)hw->sei_data_buf
6198 + hw->sei_data_len;
6199 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6200 if (aux_data_len/2 <= left_len) {
6201 for (i = 0; i < aux_data_len/2; i++)
6202 sei_data_buf[i]
6203 = trans_data_buf[i*2];
6204
6205 aux_data_len = aux_data_len / 2;
6206 for (i = 0; i < aux_data_len; i = i+4) {
6207 swap_byte = sei_data_buf[i];
6208 sei_data_buf[i]
6209 = sei_data_buf[i+3];
6210 sei_data_buf[i+3] = swap_byte;
6211
6212 swap_byte = sei_data_buf[i+1];
6213 sei_data_buf[i+1]
6214 = sei_data_buf[i+2];
6215 sei_data_buf[i+2] = swap_byte;
6216 }
6217
6218 for (i = aux_data_len-1; i >= 0; i--)
6219 if (sei_data_buf[i] != 0)
6220 break;
6221
6222 hw->sei_data_len += i+1;
6223 } else
6224 dpb_print(DECODE_ID(hw),
6225 PRINT_FLAG_ERROR,
6226 "sei data size %d and more than left space: %d, discarded it\n",
6227 hw->sei_itu_data_len,
6228 left_len);
6229 }
6230 }
6231 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6232
6233 return IRQ_HANDLED;
6234 }
6235
6236
6237 /* ucode debug */
6238 debug_tag = READ_VREG(DEBUG_REG1);
6239 if (debug_tag & 0x10000) {
6240 unsigned short *p = (unsigned short *)hw->lmem_addr;
6241
6242 dma_sync_single_for_cpu(
6243 amports_get_dma_device(),
6244 hw->lmem_addr_remap,
6245 PAGE_SIZE,
6246 DMA_FROM_DEVICE);
6247
6248 dpb_print(DECODE_ID(hw), 0,
6249 "LMEM<tag %x>:\n", debug_tag);
6250 for (i = 0; i < 0x400; i += 4) {
6251 int ii;
6252 if ((i & 0xf) == 0)
6253 dpb_print_cont(DECODE_ID(hw), 0,
6254 "%03x: ", i);
6255 for (ii = 0; ii < 4; ii++)
6256 dpb_print_cont(DECODE_ID(hw), 0,
6257 "%04x ", p[i+3-ii]);
6258 if (((i+ii) & 0xf) == 0)
6259 dpb_print_cont(DECODE_ID(hw), 0,
6260 "\n");
6261 }
6262 if (((udebug_pause_pos & 0xffff)
6263 == (debug_tag & 0xffff)) &&
6264 (udebug_pause_decode_idx == 0 ||
6265 udebug_pause_decode_idx ==
6266 hw->decode_pic_count) &&
6267 (udebug_pause_val == 0 ||
6268 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6269 udebug_pause_pos &= 0xffff;
6270 hw->ucode_pause_pos = udebug_pause_pos;
6271 }
6272 else if (debug_tag & 0x20000)
6273 hw->ucode_pause_pos = 0xffffffff;
6274 if (hw->ucode_pause_pos)
6275 reset_process_time(hw);
6276 else
6277 WRITE_VREG(DEBUG_REG1, 0);
6278 } else if (debug_tag != 0) {
6279 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6280 "dbg%x: %x\n", debug_tag,
6281 READ_VREG(DEBUG_REG2));
6282 if (((udebug_pause_pos & 0xffff)
6283 == (debug_tag & 0xffff)) &&
6284 (udebug_pause_decode_idx == 0 ||
6285 udebug_pause_decode_idx ==
6286 hw->decode_pic_count) &&
6287 (udebug_pause_val == 0 ||
6288 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6289 udebug_pause_pos &= 0xffff;
6290 hw->ucode_pause_pos = udebug_pause_pos;
6291 }
6292 if (hw->ucode_pause_pos)
6293 reset_process_time(hw);
6294 else
6295 WRITE_VREG(DEBUG_REG1, 0);
6296 }
6297 /**/
6298 return IRQ_HANDLED;
6299}
6300
6301static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6302{
6303 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6304 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6305
6306
6307 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6308
6309 if (!hw)
6310 return IRQ_HANDLED;
6311
6312 if (hw->eos)
6313 return IRQ_HANDLED;
6314
6315 p_H264_Dpb->vdec = vdec;
6316 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6317
6318 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6319 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6320 __func__,
6321 p_H264_Dpb->dec_dpb_status,
6322 READ_VREG(ERROR_STATUS_REG),
6323 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6324 READ_VREG(VLD_MEM_VIFIFO_WP),
6325 READ_VREG(VLD_MEM_VIFIFO_RP),
6326 READ_VREG(VIFF_BIT_CNT),
6327 READ_VREG(MBY_MBX));
6328
6329 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6330 if (hw->mmu_enable)
6331 hevc_sao_wait_done(hw);
6332 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6333 return IRQ_HANDLED;
6334 }
6335 return IRQ_WAKE_THREAD;
6336
6337}
6338
6339static void timeout_process(struct vdec_h264_hw_s *hw)
6340{
6341 struct vdec_s *vdec = hw_to_vdec(hw);
6342 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6343
6344 /*
6345 * In this very timeout point,the vh264_work arrives,
6346 * let it to handle the scenario.
6347 */
6348 if (work_pending(&hw->work))
6349 return;
6350
6351 hw->timeout_num++;
6352 amvdec_stop();
6353 vdec->mc_loaded = 0;
6354 if (hw->mmu_enable) {
6355 hevc_set_frame_done(hw);
6356 hevc_sao_wait_done(hw);
6357 }
6358 if (!hw->i_only && (error_proc_policy & 0x2))
6359 flush_dpb(p_H264_Dpb);
6360 dpb_print(DECODE_ID(hw),
6361 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6362 release_cur_decoding_buf(hw);
6363 hw->dec_result = DEC_RESULT_DONE;
6364 hw->data_flag |= ERROR_FLAG;
6365
6366 if (work_pending(&hw->work))
6367 return;
6368 vdec_schedule_work(&hw->timeout_work);
6369}
6370
6371static void dump_bufspec(struct vdec_h264_hw_s *hw,
6372 const char *caller)
6373{
6374 int i;
6375 dpb_print(DECODE_ID(hw), 0,
6376 "%s in %s:\n", __func__, caller);
6377 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6378 if (hw->buffer_spec[i].used == -1)
6379 continue;
6380 dpb_print(DECODE_ID(hw), 0,
6381 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6382 i, hw->buffer_spec[i].used,
6383 hw->buffer_spec[i].buf_adr,
6384 hw->buffer_spec[i].canvas_pos,
6385 hw->buffer_spec[i].vf_ref
6386 );
6387#ifdef CONFIG_AM_VDEC_DV
6388 dpb_print_cont(DECODE_ID(hw), 0,
6389 "dv_el_exist %d",
6390 hw->buffer_spec[i].dv_enhance_exist
6391 );
6392#endif
6393 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6394 }
6395
6396}
6397
6398static void vmh264_dump_state(struct vdec_s *vdec)
6399{
6400 struct vdec_h264_hw_s *hw =
6401 (struct vdec_h264_hw_s *)(vdec->private);
6402 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6403 dpb_print(DECODE_ID(hw), 0,
6404 "====== %s\n", __func__);
6405 dpb_print(DECODE_ID(hw), 0,
6406 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6407 hw->frame_width,
6408 hw->frame_height,
6409 hw->dpb.reorder_pic_num,
6410 hw->dpb.mDPB.size,
6411 hw->max_reference_size,
6412 hw->i_only,
6413 hw->send_error_frame_flag
6414 );
6415
6416 dpb_print(DECODE_ID(hw), 0,
6417 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6418 input_frame_based(vdec),
6419 hw->eos,
6420 hw->stat,
6421 hw->dec_result,
6422 decode_frame_count[DECODE_ID(hw)],
6423 display_frame_count[DECODE_ID(hw)],
6424 run_count[DECODE_ID(hw)],
6425 not_run_ready[DECODE_ID(hw)],
6426 input_empty[DECODE_ID(hw)],
6427 hw->reset_bufmgr_count
6428 );
6429
6430 if (vf_get_receiver(vdec->vf_provider_name)) {
6431 enum receviver_start_e state =
6432 vf_notify_receiver(vdec->vf_provider_name,
6433 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6434 NULL);
6435 dpb_print(DECODE_ID(hw), 0,
6436 "\nreceiver(%s) state %d\n",
6437 vdec->vf_provider_name,
6438 state);
6439 }
6440
6441 dpb_print(DECODE_ID(hw), 0,
6442 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x \n",
6443 __func__,
6444 kfifo_len(&hw->newframe_q),
6445 VF_POOL_SIZE,
6446 kfifo_len(&hw->display_q),
6447 VF_POOL_SIZE,
6448 hw->vf_pre_count,
6449 hw->vf_get_count,
6450 hw->vf_put_count,
6451 have_free_buf_spec(vdec),
6452 p_H264_Dpb->mDPB.init_done,
6453 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6454 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6455 p_H264_Dpb->fast_output_enable
6456 );
6457
6458 dump_dpb(&p_H264_Dpb->mDPB, 1);
6459 dump_pic(p_H264_Dpb);
6460 dump_bufspec(hw, __func__);
6461
6462 dpb_print(DECODE_ID(hw), 0,
6463 "DPB_STATUS_REG=0x%x\n",
6464 READ_VREG(DPB_STATUS_REG));
6465 dpb_print(DECODE_ID(hw), 0,
6466 "MPC_E=0x%x\n",
6467 READ_VREG(MPC_E));
6468 dpb_print(DECODE_ID(hw), 0,
6469 "H264_DECODE_MODE=0x%x\n",
6470 READ_VREG(H264_DECODE_MODE));
6471 dpb_print(DECODE_ID(hw), 0,
6472 "MBY_MBX=0x%x\n",
6473 READ_VREG(MBY_MBX));
6474 dpb_print(DECODE_ID(hw), 0,
6475 "H264_DECODE_SIZE=0x%x\n",
6476 READ_VREG(H264_DECODE_SIZE));
6477 dpb_print(DECODE_ID(hw), 0,
6478 "VIFF_BIT_CNT=0x%x\n",
6479 READ_VREG(VIFF_BIT_CNT));
6480 dpb_print(DECODE_ID(hw), 0,
6481 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6482 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6483 dpb_print(DECODE_ID(hw), 0,
6484 "VLD_MEM_VIFIFO_WP=0x%x\n",
6485 READ_VREG(VLD_MEM_VIFIFO_WP));
6486 dpb_print(DECODE_ID(hw), 0,
6487 "VLD_MEM_VIFIFO_RP=0x%x\n",
6488 READ_VREG(VLD_MEM_VIFIFO_RP));
6489 dpb_print(DECODE_ID(hw), 0,
6490 "PARSER_VIDEO_RP=0x%x\n",
6491 READ_PARSER_REG(PARSER_VIDEO_RP));
6492 dpb_print(DECODE_ID(hw), 0,
6493 "PARSER_VIDEO_WP=0x%x\n",
6494 READ_PARSER_REG(PARSER_VIDEO_WP));
6495
6496 if (input_frame_based(vdec) &&
6497 dpb_is_debug(DECODE_ID(hw),
6498 PRINT_FRAMEBASE_DATA)
6499 ) {
6500 int jj;
6501 if (hw->chunk && hw->chunk->block &&
6502 hw->chunk->size > 0) {
6503 u8 *data = NULL;
6504
6505 if (!hw->chunk->block->is_mapped)
6506 data = codec_mm_vmap(hw->chunk->block->start +
6507 hw->chunk->offset, hw->chunk->size);
6508 else
6509 data = ((u8 *)hw->chunk->block->start_virt)
6510 + hw->chunk->offset;
6511
6512 dpb_print(DECODE_ID(hw), 0,
6513 "frame data size 0x%x\n",
6514 hw->chunk->size);
6515 for (jj = 0; jj < hw->chunk->size; jj++) {
6516 if ((jj & 0xf) == 0)
6517 dpb_print(DECODE_ID(hw),
6518 PRINT_FRAMEBASE_DATA,
6519 "%06x:", jj);
6520 dpb_print_cont(DECODE_ID(hw),
6521 PRINT_FRAMEBASE_DATA,
6522 "%02x ", data[jj]);
6523 if (((jj + 1) & 0xf) == 0)
6524 dpb_print_cont(DECODE_ID(hw),
6525 PRINT_FRAMEBASE_DATA,
6526 "\n");
6527 }
6528
6529 if (!hw->chunk->block->is_mapped)
6530 codec_mm_unmap_phyaddr(data);
6531 }
6532 }
6533}
6534
6535
6536static void check_timer_func(unsigned long arg)
6537{
6538 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6539 struct vdec_s *vdec = hw_to_vdec(hw);
6540 int error_skip_frame_count = error_skip_count & 0xfff;
6541 unsigned int timeout_val = decode_timeout_val;
6542 if (timeout_val != 0 &&
6543 hw->no_error_count < error_skip_frame_count)
6544 timeout_val = errordata_timeout_val;
6545 if ((h264_debug_cmd & 0x100) != 0 &&
6546 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6547 hw->dec_result = DEC_RESULT_DONE;
6548 vdec_schedule_work(&hw->work);
6549 pr_info("vdec %d is forced to be disconnected\n",
6550 h264_debug_cmd & 0xff);
6551 h264_debug_cmd = 0;
6552 return;
6553 }
6554 if ((h264_debug_cmd & 0x200) != 0 &&
6555 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6556 pr_debug("vdec %d is forced to reset bufmgr\n",
6557 h264_debug_cmd & 0xff);
6558 hw->reset_bufmgr_flag = 1;
6559 h264_debug_cmd = 0;
6560 return;
6561 }
6562
6563 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6564 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6565 vdec_schedule_work(&hw->work);
6566 pr_debug("vdec requested to be disconnected\n");
6567 return;
6568 }
6569
6570 if (radr != 0) {
6571 if (rval != 0) {
6572 WRITE_VREG(radr, rval);
6573 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6574 } else
6575 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6576 rval = 0;
6577 radr = 0;
6578 }
6579
6580 if ((input_frame_based(vdec) ||
6581 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6582 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6583 (timeout_val > 0) &&
6584 (hw->start_process_time > 0) &&
6585 ((1000 * (jiffies - hw->start_process_time) / HZ)
6586 > timeout_val)
6587 ) {
6588 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6589 u32 mby_mbx = READ_VREG(MBY_MBX);
6590 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6591 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6592 if (hw->last_mby_mbx == mby_mbx) {
6593 if (hw->decode_timeout_count > 0)
6594 hw->decode_timeout_count--;
6595 if (hw->decode_timeout_count == 0)
6596 {
6597 reset_process_time(hw);
6598 timeout_process(hw);
6599 }
6600 } else
6601 start_process_time(hw);
6602 } else if (is_in_parsing_state(dpb_status)) {
6603 if (hw->last_vld_level ==
6604 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6605 if (hw->decode_timeout_count > 0)
6606 hw->decode_timeout_count--;
6607 if (hw->decode_timeout_count == 0)
6608 {
6609 reset_process_time(hw);
6610 timeout_process(hw);
6611 }
6612 }
6613 }
6614 hw->last_vld_level =
6615 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6616 hw->last_mby_mbx = mby_mbx;
6617 }
6618
6619 if ((hw->ucode_pause_pos != 0) &&
6620 (hw->ucode_pause_pos != 0xffffffff) &&
6621 udebug_pause_pos != hw->ucode_pause_pos) {
6622 hw->ucode_pause_pos = 0;
6623 WRITE_VREG(DEBUG_REG1, 0);
6624 }
6625
6626 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6627}
6628
6629static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6630{
6631 u32 ar;
6632 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6633
6634 if (!hw)
6635 return -1;
6636
6637 vstatus->frame_width = hw->frame_width;
6638 vstatus->frame_height = hw->frame_height;
6639 if (hw->frame_dur != 0)
6640 vstatus->frame_rate = 96000 / hw->frame_dur;
6641 else
6642 vstatus->frame_rate = -1;
6643 vstatus->error_count = 0;
6644 vstatus->status = hw->stat;
6645 if (hw->h264_ar == 0x3ff)
6646 hw->h264_ar = (0x100 *
6647 hw->frame_height * hw->height_aspect_ratio) /
6648 (hw->frame_width * hw->width_aspect_ratio);
6649 ar = min_t(u32,
6650 hw->h264_ar,
6651 DISP_RATIO_ASPECT_RATIO_MAX);
6652 vstatus->ratio_control =
6653 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6654
6655 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6656 "%s-%02d", DRIVER_NAME, hw->id);
6657
6658 return 0;
6659}
6660
6661static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6662{
6663 int i, j;
6664 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6665
6666 /* if (hw->init_flag == 0) { */
6667 if (h264_debug_flag & 0x40000000) {
6668 /* if (1) */
6669 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6670 "%s, reset register\n", __func__);
6671
6672 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6673 ;
6674 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6675 ; /* reg address is 0x350 */
6676
6677#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6678 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6679 WRITE_VREG(DOS_SW_RESET0, 0);
6680
6681 READ_VREG(DOS_SW_RESET0);
6682 READ_VREG(DOS_SW_RESET0);
6683 READ_VREG(DOS_SW_RESET0);
6684
6685 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6686 WRITE_VREG(DOS_SW_RESET0, 0);
6687
6688 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6689 WRITE_VREG(DOS_SW_RESET0, 0);
6690
6691 READ_VREG(DOS_SW_RESET0);
6692 READ_VREG(DOS_SW_RESET0);
6693 READ_VREG(DOS_SW_RESET0);
6694
6695#else
6696 WRITE_RESET_REG(RESET0_REGISTER,
6697 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6698 READ_RESET_REG(RESET0_REGISTER);
6699 WRITE_RESET_REG(RESET0_REGISTER,
6700 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6701
6702 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6703#endif
6704 WRITE_VREG(POWER_CTL_VLD,
6705 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6706 (1 << 9) | (1 << 6));
6707 } else {
6708 /* WRITE_VREG(POWER_CTL_VLD,
6709 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6710 */
6711 WRITE_VREG(POWER_CTL_VLD,
6712 READ_VREG(POWER_CTL_VLD) |
6713 (0 << 10) | (1 << 9) | (1 << 6));
6714 }
6715 /* disable PSCALE for hardware sharing */
6716 WRITE_VREG(PSCALE_CTRL, 0);
6717
6718 /* clear mailbox interrupt */
6719 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6720
6721 /* enable mailbox interrupt */
6722 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6723
6724#ifdef NV21
6725 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6726#endif
6727
6728 /* cbcr_merge_swap_en */
6729 if (hw->is_used_v4l
6730 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6731 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6732 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6733
6734 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6735 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6736
6737 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6738 if (hw->mmu_enable) {
6739 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6740 /* sw reset to extif hardware */
6741 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6742 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6743 } else {
6744 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6745 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6746 }
6747
6748
6749#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6750 /* pr_info("vh264 meson8 prot init\n"); */
6751 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6752#endif
6753
6754#ifdef VDEC_DW
6755 if (IS_VDEC_DW(hw)) {
6756 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6757
6758 if (IS_VDEC_DW(hw) == 2)
6759 data |= (1 << 9);
6760 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6761 }
6762#endif
6763 if (hw->dpb.mDPB.size > 0) {
6764 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6765 (hw->dpb.mDPB.size << 16) |
6766 (hw->dpb.mDPB.size << 8));
6767
6768 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6769 i = get_buf_spec_by_canvas_pos(hw, j);
6770 if (i < 0)
6771 break;
6772
6773 if (!hw->mmu_enable &&
6774 hw->buffer_spec[i].cma_alloc_addr)
6775 config_decode_canvas(hw, i);
6776 if (hw->mmu_enable && hw->double_write_mode)
6777 config_decode_canvas_ex(hw, i);
6778 }
6779 } else {
6780 WRITE_VREG(AV_SCRATCH_0, 0);
6781 WRITE_VREG(AV_SCRATCH_9, 0);
6782 }
6783
6784 if (hw->init_flag == 0)
6785 WRITE_VREG(DPB_STATUS_REG, 0);
6786 else
6787 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6788
6789 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6790 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6791 if (!tee_enabled())
6792 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6793
6794 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6795 * error_recovery_mode : error_recovery_mode_in;
6796 */
6797 /* WRITE_VREG(AV_SCRATCH_F,
6798 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6799 */
6800 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6801 ((error_recovery_mode_in & 0x1) << 4));
6802 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6803 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6804 else*/
6805 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6806
6807 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6808#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6809 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6810#endif
6811
6812 WRITE_VREG(DEBUG_REG1, 0);
6813 WRITE_VREG(DEBUG_REG2, 0);
6814
6815 if (hw->reg_iqidct_control)
6816 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6817 if (hw->reg_vcop_ctrl_reg)
6818 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6819 if (hw->vld_dec_control)
6820 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6821 return 0;
6822}
6823
6824static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6825{
6826 struct vdec_h264_hw_s *hw =
6827 (struct vdec_h264_hw_s *)vdec->private;
6828 if (i_only_flag & 0x100)
6829 return 0;
6830 if (trickmode == TRICKMODE_I)
6831 hw->i_only = 0x3;
6832 else if (trickmode == TRICKMODE_NONE)
6833 hw->i_only = 0x0;
6834 return 0;
6835}
6836
6837static unsigned char amvdec_enable_flag;
6838static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset)
6839{
6840 int i;
6841 hw->init_flag = 0;
6842 hw->first_sc_checked= 0;
6843 hw->eos = 0;
6844 hw->valve_count = 0;
6845 hw->config_bufmgr_done = 0;
6846 hw->start_process_time = 0;
6847 hw->has_i_frame = 0;
6848 hw->no_error_count = 0xfff;
6849 hw->no_error_i_count = 0xf;
6850
6851 hw->dec_flag = 0;
6852 hw->data_flag = 0;
6853 hw->skip_frame_count = 0;
6854 hw->reg_iqidct_control = 0;
6855 hw->reg_vcop_ctrl_reg = 0;
6856 hw->reg_rv_ai_mb_count = 0;
6857 hw->vld_dec_control = 0;
6858 hw->decode_timeout_count = 0;
6859 hw->no_mem_count = 0;
6860 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6861 /* vh264_ratio = 0x100; */
6862
6863 hw->vh264_rotation = (((unsigned long)
6864 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6865
6866 hw->frame_prog = 0;
6867 hw->frame_width = hw->vh264_amstream_dec_info.width;
6868 hw->frame_height = hw->vh264_amstream_dec_info.height;
6869 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6870 hw->pts_outside = ((unsigned long)
6871 hw->vh264_amstream_dec_info.param) & 0x01;
6872 hw->sync_outside = ((unsigned long)
6873 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6874 hw->use_idr_framerate = ((unsigned long)
6875 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6876 hw->max_refer_buf = !(((unsigned long)
6877 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6878 if (hw->frame_dur < 96000/960) {
6879 /*more than 960fps,it should not be a correct value,
6880 *give default 30fps
6881 */
6882 hw->frame_dur = 96000/30;
6883 }
6884
6885 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6886
6887 hw->first_i_policy = first_i_policy;
6888
6889 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6890 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6891 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6892 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6893
6894 if (i_only_flag & 0x100)
6895 hw->i_only = i_only_flag & 0xff;
6896 if (hw->i_only)
6897 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6898
6899 if ((unsigned long) hw->vh264_amstream_dec_info.param
6900 & 0x08)
6901 hw->no_poc_reorder_flag = 1;
6902
6903 error_recovery_mode_in = 1; /*ucode control?*/
6904 if (error_proc_policy & 0x80000000)
6905 hw->send_error_frame_flag = error_proc_policy & 0x1;
6906 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6907 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6908
6909 if (!is_reset) {
6910 INIT_KFIFO(hw->display_q);
6911 INIT_KFIFO(hw->newframe_q);
6912
6913 for (i = 0; i < VF_POOL_SIZE; i++) {
6914 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6915 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6916 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6917 kfifo_put(&hw->newframe_q, vf);
6918 }
6919 }
6920
6921 hw->duration_from_pts_done = 0;
6922
6923 hw->p_last_vf = NULL;
6924 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6925 hw->hevc_cur_buf_idx = 0xffff;
6926
6927 init_waitqueue_head(&hw->wait_q);
6928
6929 return;
6930}
6931
6932static s32 vh264_init(struct vdec_h264_hw_s *hw)
6933{
6934 int size = -1;
6935 int fw_size = 0x1000 * 16;
6936 int fw_mmu_size = 0x1000 * 16;
6937 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6938
6939 /* int trickmode_fffb = 0; */
6940
6941 /* pr_info("\nvh264_init\n"); */
6942 /* init_timer(&hw->recycle_timer); */
6943
6944 /* timer init */
6945 init_timer(&hw->check_timer);
6946
6947 hw->check_timer.data = (unsigned long)hw;
6948 hw->check_timer.function = check_timer_func;
6949 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6950
6951 /* add_timer(&hw->check_timer); */
6952 hw->stat |= STAT_TIMER_ARM;
6953 hw->stat |= STAT_ISR_REG;
6954
6955 mutex_init(&hw->chunks_mutex);
6956 vh264_local_init(hw, false);
6957 INIT_WORK(&hw->work, vh264_work);
6958 INIT_WORK(&hw->notify_work, vh264_notify_work);
6959 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6960#ifdef MH264_USERDATA_ENABLE
6961 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6962#endif
6963
6964 if (!amvdec_enable_flag) {
6965 amvdec_enable_flag = true;
6966 amvdec_enable();
6967 if (hw->mmu_enable)
6968 amhevc_enable();
6969 }
6970 if (hw->mmu_enable) {
6971
6972 hw->frame_mmu_map_addr =
6973 dma_alloc_coherent(amports_get_dma_device(),
6974 FRAME_MMU_MAP_SIZE,
6975 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6976 if (hw->frame_mmu_map_addr == NULL) {
6977 pr_err("%s: failed to alloc count_buffer\n", __func__);
6978 return -ENOMEM;
6979 }
6980 }
6981
6982 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6983 if (IS_ERR_OR_NULL(fw))
6984 return -ENOMEM;
6985
6986 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6987 if (size < 0) {
6988 pr_err("get firmware fail.\n");
6989 vfree(fw);
6990 return -1;
6991 }
6992
6993 fw->len = size;
6994 hw->fw = fw;
6995
6996 if (hw->mmu_enable) {
6997 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6998 if (IS_ERR_OR_NULL(fw_mmu))
6999 return -ENOMEM;
7000
7001 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
7002 if (size < 0) {
7003 pr_err("get mmu fw fail.\n");
7004 vfree(fw_mmu);
7005 return -1;
7006 }
7007
7008 fw_mmu->len = size;
7009 hw->fw_mmu = fw_mmu;
7010 }
7011
7012 if (!tee_enabled()) {
7013 /* -- ucode loading (amrisc and swap code) */
7014 hw->mc_cpu_addr =
7015 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
7016 &hw->mc_dma_handle, GFP_KERNEL);
7017 if (!hw->mc_cpu_addr) {
7018 amvdec_enable_flag = false;
7019 amvdec_disable();
7020 if (hw->mmu_enable)
7021 amhevc_disable();
7022 pr_info("vh264_init: Can not allocate mc memory.\n");
7023 return -ENOMEM;
7024 }
7025
7026 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
7027 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
7028 */
7029
7030 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
7031
7032 /*header*/
7033 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
7034 fw->data + 0x4000, MC_SWAP_SIZE);
7035 /*data*/
7036 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
7037 fw->data + 0x2000, MC_SWAP_SIZE);
7038 /*mmco*/
7039 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
7040 fw->data + 0x6000, MC_SWAP_SIZE);
7041 /*list*/
7042 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
7043 fw->data + 0x3000, MC_SWAP_SIZE);
7044 /*slice*/
7045 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
7046 fw->data + 0x5000, MC_SWAP_SIZE);
7047 /*main*/
7048 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
7049 fw->data, 0x2000);
7050 /*data*/
7051 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
7052 fw->data + 0x2000, 0x1000);
7053 /*slice*/
7054 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
7055 fw->data + 0x5000, 0x1000);
7056 }
7057
7058#if 1 /* #ifdef BUFFER_MGR_IN_C */
7059 hw->lmem_addr = __get_free_page(GFP_KERNEL);
7060 if (!hw->lmem_addr) {
7061 pr_info("%s: failed to alloc lmem_addr\n", __func__);
7062 return -ENOMEM;
7063 } else {
7064 hw->lmem_addr_remap = dma_map_single(
7065 amports_get_dma_device(),
7066 (void *)hw->lmem_addr,
7067 PAGE_SIZE, DMA_FROM_DEVICE);
7068 if (dma_mapping_error(amports_get_dma_device(),
7069 hw->lmem_addr_remap)) {
7070 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
7071 "%s: failed to map lmem_addr\n", __func__);
7072 free_page(hw->lmem_addr);
7073 hw->lmem_addr = 0;
7074 hw->lmem_addr_remap = 0;
7075 return -ENOMEM;
7076 }
7077
7078 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
7079 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
7080 }
7081
7082 if (prefix_aux_buf_size > 0 ||
7083 suffix_aux_buf_size > 0) {
7084 u32 aux_buf_size;
7085 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7086 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7087 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7088 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7089 if (hw->aux_addr == NULL) {
7090 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7091 return -1;
7092 }
7093
7094 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7095 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7096 if (dma_mapping_error(amports_get_dma_device(),
7097 hw->aux_phy_addr)) {
7098 pr_err("%s: failed to map rpm buffer\n", __func__);
7099 kfree(hw->aux_addr);
7100 hw->aux_addr = NULL;
7101 return -1;
7102 }
7103 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7104 if (hw->sei_data_buf == NULL) {
7105 pr_err("%s: failed to alloc sei itu data buffer\n",
7106 __func__);
7107 return -1;
7108 }
7109 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7110 if (hw->sei_itu_data_buf == NULL) {
7111 pr_err("%s: failed to alloc sei itu data buffer\n",
7112 __func__);
7113 kfree(hw->aux_addr);
7114 hw->aux_addr = NULL;
7115 kfree(hw->sei_data_buf);
7116 hw->sei_data_buf = NULL;
7117
7118 return -1;
7119 }
7120
7121 if (NULL == hw->sei_user_data_buffer) {
7122 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7123 GFP_KERNEL);
7124 if (!hw->sei_user_data_buffer) {
7125 pr_info("%s: Can not allocate sei_data_buffer\n",
7126 __func__);
7127 kfree(hw->aux_addr);
7128 hw->aux_addr = NULL;
7129 kfree(hw->sei_data_buf);
7130 hw->sei_data_buf = NULL;
7131 kfree(hw->sei_itu_data_buf);
7132 hw->sei_itu_data_buf = NULL;
7133
7134 return -1;
7135 }
7136 hw->sei_user_data_wp = 0;
7137 }
7138 }
7139/* BUFFER_MGR_IN_C */
7140#endif
7141 hw->stat |= STAT_MC_LOAD;
7142
7143 /* add memory barrier */
7144 wmb();
7145
7146 return 0;
7147}
7148
7149static int vh264_stop(struct vdec_h264_hw_s *hw)
7150{
7151 if (hw->stat & STAT_VDEC_RUN) {
7152 amvdec_stop();
7153 hw->stat &= ~STAT_VDEC_RUN;
7154 }
7155#ifdef VDEC_DW
7156 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7157#endif
7158#ifdef MH264_USERDATA_ENABLE
7159 cancel_work_sync(&hw->user_data_ready_work);
7160#endif
7161 cancel_work_sync(&hw->notify_work);
7162 cancel_work_sync(&hw->timeout_work);
7163 cancel_work_sync(&hw->work);
7164
7165
7166 if (hw->stat & STAT_MC_LOAD) {
7167 if (hw->mc_cpu_addr != NULL) {
7168 dma_free_coherent(amports_get_dma_device(),
7169 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7170 hw->mc_dma_handle);
7171 hw->mc_cpu_addr = NULL;
7172 }
7173 if (hw->frame_mmu_map_addr != NULL) {
7174 dma_free_coherent(amports_get_dma_device(),
7175 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7176 hw->frame_mmu_map_phy_addr);
7177 hw->frame_mmu_map_addr = NULL;
7178 }
7179
7180 }
7181 if (hw->stat & STAT_ISR_REG) {
7182 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7183 hw->stat &= ~STAT_ISR_REG;
7184 }
7185 if (hw->lmem_addr_remap) {
7186 dma_unmap_single(amports_get_dma_device(),
7187 hw->lmem_addr_remap,
7188 PAGE_SIZE, DMA_FROM_DEVICE);
7189 hw->lmem_addr_remap = 0;
7190 }
7191 if (hw->lmem_addr) {
7192 free_page(hw->lmem_addr);
7193 hw->lmem_addr = 0;
7194 }
7195 if (hw->aux_addr) {
7196 dma_unmap_single(amports_get_dma_device(),
7197 hw->aux_phy_addr,
7198 hw->prefix_aux_size + hw->suffix_aux_size,
7199 DMA_FROM_DEVICE);
7200 kfree(hw->aux_addr);
7201 hw->aux_addr = NULL;
7202 }
7203 if (hw->sei_data_buf != NULL) {
7204 kfree(hw->sei_data_buf);
7205 hw->sei_data_buf = NULL;
7206 }
7207 if (hw->sei_itu_data_buf != NULL) {
7208 kfree(hw->sei_itu_data_buf);
7209 hw->sei_itu_data_buf = NULL;
7210 }
7211 if (hw->sei_user_data_buffer != NULL) {
7212 kfree(hw->sei_user_data_buffer);
7213 hw->sei_user_data_buffer = NULL;
7214 }
7215 /* amvdec_disable(); */
7216
7217 vfree(hw->fw);
7218 hw->fw = NULL;
7219
7220 if (hw->mmu_enable) {
7221 vfree(hw->fw_mmu);
7222 hw->fw_mmu = NULL;
7223 }
7224
7225 dpb_print(DECODE_ID(hw), 0,
7226 "%s\n",
7227 __func__);
7228 return 0;
7229}
7230
7231static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7232{
7233 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7234 int count = 0;
7235 do {
7236 usleep_range(100, 500);
7237 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7238 break;
7239 if (count > 2000) {
7240 dpb_print(DECODE_ID(hw),
7241 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7242 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7243 break;
7244 } else
7245 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7246 count++;
7247 } while (1);
7248}
7249
7250static void vh264_notify_work(struct work_struct *work)
7251{
7252 struct vdec_h264_hw_s *hw = container_of(work,
7253 struct vdec_h264_hw_s, notify_work);
7254 struct vdec_s *vdec = hw_to_vdec(hw);
7255 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7256 vf_notify_receiver(vdec->vf_provider_name,
7257 VFRAME_EVENT_PROVIDER_FR_HINT,
7258 (void *)((unsigned long)hw->frame_dur));
7259 vdec->fr_hint_state = VDEC_HINTED;
7260 }
7261
7262 return;
7263}
7264
7265#ifdef MH264_USERDATA_ENABLE
7266static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7267{
7268 hw->wait_for_udr_send = 0;
7269 hw->sei_itu_data_len = 0;
7270 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7271}
7272
7273static void vmh264_crate_userdata_manager(
7274 struct vdec_h264_hw_s *hw,
7275 u8 *userdata_buf,
7276 int buf_len)
7277{
7278 if (hw) {
7279
7280
7281 mutex_init(&hw->userdata_mutex);
7282
7283 memset(&hw->userdata_info, 0,
7284 sizeof(struct mh264_userdata_info_t));
7285 hw->userdata_info.data_buf = userdata_buf;
7286 hw->userdata_info.buf_len = buf_len;
7287 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7288
7289 vmh264_reset_udr_mgr(hw);
7290
7291 }
7292}
7293
7294static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7295{
7296 if (hw)
7297 memset(&hw->userdata_info,
7298 0,
7299 sizeof(struct mh264_userdata_info_t));
7300}
7301
7302/*
7303#define DUMP_USERDATA_RECORD
7304*/
7305#ifdef DUMP_USERDATA_RECORD
7306
7307#define MAX_USER_DATA_SIZE 3145728
7308static void *user_data_buf;
7309static unsigned char *pbuf_start;
7310static int total_len;
7311static int bskip;
7312static int n_userdata_id;
7313
7314static void print_data(unsigned char *pdata,
7315 int len,
7316 unsigned int poc_number,
7317 unsigned int flag,
7318 unsigned int duration,
7319 unsigned int vpts,
7320 unsigned int vpts_valid,
7321 int rec_id)
7322{
7323 int nLeft;
7324
7325 nLeft = len;
7326#if 0
7327 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7328 rec_id, len, flag,
7329 duration, vpts, vpts_valid, poc_number);
7330#endif
7331 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7332 rec_id, len, flag, vpts);
7333
7334 if (len == 96) {
7335 int i;
7336 nLeft = 72;
7337 while (nLeft >= 16) {
7338 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7339 pdata[0], pdata[1], pdata[2], pdata[3],
7340 pdata[4], pdata[5], pdata[6], pdata[7],
7341 pdata[8], pdata[9], pdata[10], pdata[11],
7342 pdata[12], pdata[13], pdata[14], pdata[15]);
7343 nLeft -= 16;
7344 pdata += 16;
7345 }
7346
7347
7348 while (nLeft > 0) {
7349 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7350 pdata[0], pdata[1], pdata[2], pdata[3],
7351 pdata[4], pdata[5], pdata[6], pdata[7]);
7352 nLeft -= 8;
7353 pdata += 8;
7354 }
7355
7356 i = 0;
7357 nLeft = 96-72;
7358 while (i < nLeft) {
7359 if (pdata[0] != 0) {
7360 pr_info("some data error\n");
7361 break;
7362 }
7363 pdata++;
7364 i++;
7365 }
7366 } else {
7367 while (nLeft >= 16) {
7368 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7369 pdata[0], pdata[1], pdata[2], pdata[3],
7370 pdata[4], pdata[5], pdata[6], pdata[7],
7371 pdata[8], pdata[9], pdata[10], pdata[11],
7372 pdata[12], pdata[13], pdata[14], pdata[15]);
7373 nLeft -= 16;
7374 pdata += 16;
7375 }
7376
7377
7378 while (nLeft > 0) {
7379 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7380 pdata[0], pdata[1], pdata[2], pdata[3],
7381 pdata[4], pdata[5], pdata[6], pdata[7]);
7382 nLeft -= 8;
7383 pdata += 8;
7384 }
7385
7386 }
7387}
7388
7389static void push_to_buf(struct vdec_h264_hw_s *hw,
7390 u8 *pdata,
7391 int len,
7392 struct userdata_meta_info_t *pmeta);
7393
7394static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7395 struct mh264_userdata_record_t *record)
7396{
7397 if (record && hw) {
7398 u8 *pdata;
7399
7400 pdata = hw->userdata_info.data_buf + record->rec_start;
7401/*
7402 print_data(pdata,
7403 record->rec_len,
7404 record->meta_info.flags,
7405 record->meta_info.duration,
7406 record->meta_info.vpts,
7407 record->meta_info.vpts_valid,
7408 n_record_id);
7409*/
7410 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7411 n_userdata_id++;
7412 }
7413}
7414
7415
7416static void push_to_buf(struct vdec_h264_hw_s *hw,
7417 u8 *pdata, int len,
7418 struct userdata_meta_info_t *pmeta)
7419{
7420 u32 *pLen;
7421 int info_cnt;
7422 u8 *pbuf_end;
7423
7424 if (!user_data_buf)
7425 return;
7426
7427 if (bskip) {
7428 pr_info("over size, skip\n");
7429 return;
7430 }
7431 info_cnt = 0;
7432 pLen = (u32 *)pbuf_start;
7433
7434 *pLen = len;
7435 pbuf_start += sizeof(u32);
7436 info_cnt++;
7437 pLen++;
7438
7439 *pLen = pmeta->poc_number;
7440 pbuf_start += sizeof(u32);
7441 info_cnt++;
7442 pLen++;
7443
7444 *pLen = pmeta->duration;
7445 pbuf_start += sizeof(u32);
7446 info_cnt++;
7447 pLen++;
7448
7449 *pLen = pmeta->flags;
7450 pbuf_start += sizeof(u32);
7451 info_cnt++;
7452 pLen++;
7453
7454 *pLen = pmeta->vpts;
7455 pbuf_start += sizeof(u32);
7456 info_cnt++;
7457 pLen++;
7458
7459 *pLen = pmeta->vpts_valid;
7460 pbuf_start += sizeof(u32);
7461 info_cnt++;
7462 pLen++;
7463
7464
7465 *pLen = n_userdata_id;
7466 pbuf_start += sizeof(u32);
7467 info_cnt++;
7468 pLen++;
7469
7470
7471
7472 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7473 if (pdata + len > pbuf_end) {
7474 int first_section_len;
7475
7476 first_section_len = pbuf_end - pdata;
7477 memcpy(pbuf_start, pdata, first_section_len);
7478 pdata = (u8 *)hw->sei_user_data_buffer;
7479 pbuf_start += first_section_len;
7480 memcpy(pbuf_start, pdata, len - first_section_len);
7481 pbuf_start += len - first_section_len;
7482 } else {
7483 memcpy(pbuf_start, pdata, len);
7484 pbuf_start += len;
7485 }
7486
7487 total_len += len + info_cnt * sizeof(u32);
7488 if (total_len >= MAX_USER_DATA_SIZE-4096)
7489 bskip = 1;
7490}
7491
7492static void show_user_data_buf(void)
7493{
7494 u8 *pbuf;
7495 int len;
7496 unsigned int flag;
7497 unsigned int duration;
7498 unsigned int vpts;
7499 unsigned int vpts_valid;
7500 unsigned int poc_number;
7501 int rec_id;
7502
7503 pr_info("show user data buf\n");
7504 pbuf = user_data_buf;
7505
7506 while (pbuf < pbuf_start) {
7507 u32 *pLen;
7508
7509 pLen = (u32 *)pbuf;
7510
7511 len = *pLen;
7512 pLen++;
7513 pbuf += sizeof(u32);
7514
7515 poc_number = *pLen;
7516 pLen++;
7517 pbuf += sizeof(u32);
7518
7519 duration = *pLen;
7520 pLen++;
7521 pbuf += sizeof(u32);
7522
7523 flag = *pLen;
7524 pLen++;
7525 pbuf += sizeof(u32);
7526
7527 vpts = *pLen;
7528 pLen++;
7529 pbuf += sizeof(u32);
7530
7531 vpts_valid = *pLen;
7532 pLen++;
7533 pbuf += sizeof(u32);
7534
7535 rec_id = *pLen;
7536 pLen++;
7537 pbuf += sizeof(u32);
7538
7539 print_data(pbuf, len, poc_number, flag,
7540 duration, vpts,
7541 vpts_valid, rec_id);
7542 pbuf += len;
7543 msleep(30);
7544 }
7545}
7546
7547static int vmh264_init_userdata_dump(void)
7548{
7549 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7550 if (user_data_buf)
7551 return 1;
7552 else
7553 return 0;
7554}
7555
7556static void vmh264_dump_userdata(void)
7557{
7558 if (user_data_buf) {
7559 show_user_data_buf();
7560 kfree(user_data_buf);
7561 user_data_buf = NULL;
7562 }
7563}
7564
7565static void vmh264_reset_user_data_buf(void)
7566{
7567 total_len = 0;
7568 pbuf_start = user_data_buf;
7569 bskip = 0;
7570 n_userdata_id = 0;
7571}
7572#endif
7573
7574
7575static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7576 int frame_type,
7577 u32 vpts,
7578 u32 vpts_valid)
7579{
7580 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7581
7582 unsigned char *pdata;
7583 u8 *pmax_sei_data_buffer;
7584 u8 *sei_data_buf;
7585 int i;
7586 int wp;
7587 int data_length;
7588 struct mh264_userdata_record_t *p_userdata_rec;
7589
7590
7591#ifdef MH264_USERDATA_ENABLE
7592 struct userdata_meta_info_t meta_info;
7593 memset(&meta_info, 0, sizeof(meta_info));
7594#endif
7595
7596 if (hw->sei_itu_data_len <= 0)
7597 return;
7598
7599 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7600 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7601 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7602 for (i = 0; i < hw->sei_itu_data_len; i++) {
7603 *pdata++ = sei_data_buf[i];
7604 if (pdata >= pmax_sei_data_buffer)
7605 pdata = (u8 *)hw->sei_user_data_buffer;
7606 }
7607
7608 hw->sei_user_data_wp = (hw->sei_user_data_wp
7609 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7610 hw->sei_itu_data_len = 0;
7611
7612#ifdef MH264_USERDATA_ENABLE
7613 meta_info.duration = hw->frame_dur;
7614 meta_info.flags |= (VFORMAT_H264 << 3);
7615
7616 meta_info.vpts = vpts;
7617 meta_info.vpts_valid = vpts_valid;
7618 meta_info.poc_number =
7619 p_H264_Dpb->mVideo.dec_picture->poc;
7620
7621
7622 wp = hw->sei_user_data_wp;
7623
7624 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7625 data_length = wp - hw->userdata_info.last_wp;
7626 else
7627 data_length = wp + hw->userdata_info.buf_len
7628 - hw->userdata_info.last_wp;
7629
7630 if (data_length & 0x7)
7631 data_length = (((data_length + 8) >> 3) << 3);
7632
7633 p_userdata_rec = &hw->ud_record;
7634 p_userdata_rec->meta_info = meta_info;
7635 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7636 p_userdata_rec->rec_len = data_length;
7637 hw->userdata_info.last_wp = wp;
7638
7639 p_userdata_rec->meta_info.flags |=
7640 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7641
7642 hw->wait_for_udr_send = 1;
7643 vdec_schedule_work(&hw->user_data_ready_work);
7644#endif
7645}
7646
7647
7648static void user_data_ready_notify_work(struct work_struct *work)
7649{
7650 struct vdec_h264_hw_s *hw = container_of(work,
7651 struct vdec_h264_hw_s, user_data_ready_work);
7652
7653
7654 mutex_lock(&hw->userdata_mutex);
7655
7656 hw->userdata_info.records[hw->userdata_info.write_index]
7657 = hw->ud_record;
7658 hw->userdata_info.write_index++;
7659 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7660 hw->userdata_info.write_index = 0;
7661
7662 mutex_unlock(&hw->userdata_mutex);
7663
7664#ifdef DUMP_USERDATA_RECORD
7665 dump_userdata_record(hw, &hw->ud_record);
7666#endif
7667 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7668
7669 hw->wait_for_udr_send = 0;
7670}
7671
7672static int vmh264_user_data_read(struct vdec_s *vdec,
7673 struct userdata_param_t *puserdata_para)
7674{
7675 struct vdec_h264_hw_s *hw = NULL;
7676 int rec_ri, rec_wi;
7677 int rec_len;
7678 u8 *rec_data_start;
7679 u8 *pdest_buf;
7680 struct mh264_userdata_record_t *p_userdata_rec;
7681 u32 data_size;
7682 u32 res;
7683 int copy_ok = 1;
7684
7685 hw = (struct vdec_h264_hw_s *)vdec->private;
7686
7687 pdest_buf = puserdata_para->pbuf_addr;
7688
7689 mutex_lock(&hw->userdata_mutex);
7690
7691/*
7692 pr_info("ri = %d, wi = %d\n",
7693 lg_p_mpeg12_userdata_info->read_index,
7694 lg_p_mpeg12_userdata_info->write_index);
7695*/
7696 rec_ri = hw->userdata_info.read_index;
7697 rec_wi = hw->userdata_info.write_index;
7698
7699 if (rec_ri == rec_wi) {
7700 mutex_unlock(&hw->userdata_mutex);
7701 return 0;
7702 }
7703
7704 p_userdata_rec = hw->userdata_info.records + rec_ri;
7705
7706 rec_len = p_userdata_rec->rec_len;
7707 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7708/*
7709 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7710 p_userdata_rec->rec_len,
7711 p_userdata_rec->rec_start,
7712 puserdata_para->buf_len);
7713*/
7714 if (rec_len <= puserdata_para->buf_len) {
7715 /* dvb user data buffer is enought to
7716 copy the whole recored. */
7717 data_size = rec_len;
7718 if (rec_data_start + data_size
7719 > hw->userdata_info.data_buf_end) {
7720 int first_section_len;
7721
7722 first_section_len = hw->userdata_info.buf_len -
7723 p_userdata_rec->rec_start;
7724 res = (u32)copy_to_user((void *)pdest_buf,
7725 (void *)rec_data_start,
7726 first_section_len);
7727 if (res) {
7728 pr_info("p1 read not end res=%d, request=%d\n",
7729 res, first_section_len);
7730 copy_ok = 0;
7731
7732 p_userdata_rec->rec_len -=
7733 first_section_len - res;
7734 p_userdata_rec->rec_start +=
7735 first_section_len - res;
7736 puserdata_para->data_size =
7737 first_section_len - res;
7738 } else {
7739 res = (u32)copy_to_user(
7740 (void *)(pdest_buf+first_section_len),
7741 (void *)hw->userdata_info.data_buf,
7742 data_size - first_section_len);
7743 if (res) {
7744 pr_info("p2 read not end res=%d, request=%d\n",
7745 res, data_size);
7746 copy_ok = 0;
7747 }
7748 p_userdata_rec->rec_len -=
7749 data_size - res;
7750 p_userdata_rec->rec_start =
7751 data_size - first_section_len - res;
7752 puserdata_para->data_size =
7753 data_size - res;
7754 }
7755 } else {
7756 res = (u32)copy_to_user((void *)pdest_buf,
7757 (void *)rec_data_start,
7758 data_size);
7759 if (res) {
7760 pr_info("p3 read not end res=%d, request=%d\n",
7761 res, data_size);
7762 copy_ok = 0;
7763 }
7764 p_userdata_rec->rec_len -= data_size - res;
7765 p_userdata_rec->rec_start += data_size - res;
7766 puserdata_para->data_size = data_size - res;
7767 }
7768
7769 if (copy_ok) {
7770 hw->userdata_info.read_index++;
7771 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7772 hw->userdata_info.read_index = 0;
7773 }
7774 } else {
7775 /* dvb user data buffer is not enought
7776 to copy the whole recored. */
7777 data_size = puserdata_para->buf_len;
7778 if (rec_data_start + data_size
7779 > hw->userdata_info.data_buf_end) {
7780 int first_section_len;
7781
7782 first_section_len = hw->userdata_info.buf_len -
7783 p_userdata_rec->rec_start;
7784 res = (u32)copy_to_user((void *)pdest_buf,
7785 (void *)rec_data_start,
7786 first_section_len);
7787 if (res) {
7788 pr_info("p4 read not end res=%d, request=%d\n",
7789 res, first_section_len);
7790 copy_ok = 0;
7791 p_userdata_rec->rec_len -=
7792 first_section_len - res;
7793 p_userdata_rec->rec_start +=
7794 first_section_len - res;
7795 puserdata_para->data_size =
7796 first_section_len - res;
7797 } else {
7798 /* first secton copy is ok*/
7799 res = (u32)copy_to_user(
7800 (void *)(pdest_buf+first_section_len),
7801 (void *)hw->userdata_info.data_buf,
7802 data_size - first_section_len);
7803 if (res) {
7804 pr_info("p5 read not end res=%d, request=%d\n",
7805 res,
7806 data_size - first_section_len);
7807 copy_ok = 0;
7808 }
7809
7810 p_userdata_rec->rec_len -=
7811 data_size - res;
7812 p_userdata_rec->rec_start =
7813 data_size - first_section_len - res;
7814 puserdata_para->data_size =
7815 data_size - res;
7816 }
7817 } else {
7818 res = (u32)copy_to_user((void *)pdest_buf,
7819 (void *)rec_data_start,
7820 data_size);
7821 if (res) {
7822 pr_info("p6 read not end res=%d, request=%d\n",
7823 res, data_size);
7824 copy_ok = 0;
7825 }
7826
7827 p_userdata_rec->rec_len -= data_size - res;
7828 p_userdata_rec->rec_start += data_size - res;
7829 puserdata_para->data_size = data_size - res;
7830 }
7831
7832 if (copy_ok) {
7833 hw->userdata_info.read_index++;
7834 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7835 hw->userdata_info.read_index = 0;
7836 }
7837
7838 }
7839 puserdata_para->meta_info = p_userdata_rec->meta_info;
7840
7841 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7842 puserdata_para->meta_info.records_in_que =
7843 hw->userdata_info.write_index -
7844 hw->userdata_info.read_index;
7845 else
7846 puserdata_para->meta_info.records_in_que =
7847 hw->userdata_info.write_index +
7848 USERDATA_FIFO_NUM -
7849 hw->userdata_info.read_index;
7850
7851 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7852
7853 mutex_unlock(&hw->userdata_mutex);
7854
7855 return 1;
7856}
7857
7858static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7859{
7860 struct vdec_h264_hw_s *hw = NULL;
7861
7862 hw = (struct vdec_h264_hw_s *)vdec->private;
7863
7864 if (hw) {
7865 mutex_lock(&hw->userdata_mutex);
7866 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7867 bInit,
7868 hw->userdata_info.read_index,
7869 hw->userdata_info.write_index);
7870 hw->userdata_info.read_index = 0;
7871 hw->userdata_info.write_index = 0;
7872
7873 if (bInit)
7874 hw->userdata_info.last_wp = 0;
7875 mutex_unlock(&hw->userdata_mutex);
7876 }
7877}
7878
7879static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7880{
7881 amstream_wakeup_userdata_poll(vdec);
7882}
7883
7884#endif
7885
7886
7887static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7888 struct vdec_s *vdec, int from)
7889{
7890 /* finished decoding one frame or error,
7891 * notify vdec core to switch context
7892 */
7893 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7894 "%s dec_result %d %x %x %x\n",
7895 __func__,
7896 hw->dec_result,
7897 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7898 READ_VREG(VLD_MEM_VIFIFO_WP),
7899 READ_VREG(VLD_MEM_VIFIFO_RP));
7900 if (!hw->mmu_enable) {
7901 mutex_lock(&vmh264_mutex);
7902 dealloc_buf_specs(hw, 0);
7903 mutex_unlock(&vmh264_mutex);
7904 }
7905 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7906 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7907 u32 param1 = READ_VREG(AV_SCRATCH_1);
7908 u32 param2 = READ_VREG(AV_SCRATCH_2);
7909 u32 param3 = READ_VREG(AV_SCRATCH_6);
7910 u32 param4 = READ_VREG(AV_SCRATCH_B);
7911
7912 if (vh264_set_params(hw, param1,
7913 param2, param3, param4) < 0)
7914 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7915
7916 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7917 (hw->dpb.mDPB.size<<16) |
7918 (hw->dpb.mDPB.size<<8));
7919
7920 if (hw->is_used_v4l) {
7921 struct aml_vcodec_ctx *ctx =
7922 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7923
7924 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7925 struct aml_vdec_ps_infos ps;
7926
7927 ps.visible_width = hw->frame_width;
7928 ps.visible_height = hw->frame_height;
7929 ps.coded_width = ALIGN(hw->frame_width, 64);
7930 ps.coded_height = ALIGN(hw->frame_height, 64);
7931 ps.dpb_size = hw->dpb.mDPB.size;
7932 hw->v4l_params_parsed = true;
7933 vdec_v4l_set_ps_infos(ctx, &ps);
7934 }
7935 }
7936
7937 start_process_time(hw);
7938 return;
7939 } else
7940 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7941 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7942 && (hw_to_vdec(hw)->next_status !=
7943 VDEC_STATUS_DISCONNECTED)) {
7944 if (!vdec_has_more_input(vdec)) {
7945 hw->dec_result = DEC_RESULT_EOS;
7946 vdec_schedule_work(&hw->work);
7947 return;
7948 }
7949
7950 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7951 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7952 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7953 __func__,
7954 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7955 READ_VREG(VLD_MEM_VIFIFO_WP),
7956 READ_VREG(VLD_MEM_VIFIFO_RP));
7957 mutex_lock(&hw->chunks_mutex);
7958 vdec_vframe_dirty(vdec, hw->chunk);
7959 hw->chunk = NULL;
7960 mutex_unlock(&hw->chunks_mutex);
7961 vdec_clean_input(vdec);
7962 }
7963 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7964 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7965 > get_data_timeout_val)) {
7966 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7967 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7968 __func__);
7969 goto result_done;
7970 }
7971 if (is_buffer_available(vdec)) {
7972 int r;
7973 int decode_size;
7974 r = vdec_prepare_input(vdec, &hw->chunk);
7975 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7976 VDEC_STATUS_DISCONNECTED)) {
7977 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7978
7979 dpb_print(DECODE_ID(hw),
7980 PRINT_FLAG_VDEC_DETAIL,
7981 "vdec_prepare_input: Insufficient data\n");
7982 vdec_schedule_work(&hw->work);
7983 return;
7984 }
7985 hw->dec_result = DEC_RESULT_NONE;
7986 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7987 "%s: chunk size 0x%x\n",
7988 __func__, hw->chunk->size);
7989
7990 if (dpb_is_debug(DECODE_ID(hw),
7991 PRINT_FRAMEBASE_DATA)) {
7992 int jj;
7993 u8 *data = NULL;
7994
7995 if (!hw->chunk->block->is_mapped)
7996 data = codec_mm_vmap(
7997 hw->chunk->block->start +
7998 hw->chunk->offset, r);
7999 else
8000 data = ((u8 *)
8001 hw->chunk->block->start_virt)
8002 + hw->chunk->offset;
8003
8004 for (jj = 0; jj < r; jj++) {
8005 if ((jj & 0xf) == 0)
8006 dpb_print(DECODE_ID(hw),
8007 PRINT_FRAMEBASE_DATA,
8008 "%06x:", jj);
8009 dpb_print_cont(DECODE_ID(hw),
8010 PRINT_FRAMEBASE_DATA,
8011 "%02x ", data[jj]);
8012 if (((jj + 1) & 0xf) == 0)
8013 dpb_print_cont(DECODE_ID(hw),
8014 PRINT_FRAMEBASE_DATA,
8015 "\n");
8016 }
8017
8018 if (!hw->chunk->block->is_mapped)
8019 codec_mm_unmap_phyaddr(data);
8020 }
8021 WRITE_VREG(POWER_CTL_VLD,
8022 READ_VREG(POWER_CTL_VLD) |
8023 (0 << 10) | (1 << 9) | (1 << 6));
8024 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8025 decode_size = hw->chunk->size +
8026 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8027 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8028 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8029 vdec_enable_input(vdec);
8030
8031 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8032 start_process_time(hw);
8033 } else{
8034 if (hw_to_vdec(hw)->next_status
8035 != VDEC_STATUS_DISCONNECTED) {
8036 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8037 vdec_schedule_work(&hw->work);
8038 }
8039 }
8040 return;
8041 } else if (hw->dec_result == DEC_RESULT_DONE) {
8042 /* if (!hw->ctx_valid)
8043 hw->ctx_valid = 1; */
8044result_done:
8045 if (hw->mmu_enable
8046 && hw->frame_busy && hw->frame_done) {
8047 long used_4k_num;
8048 hevc_sao_wait_done(hw);
8049 if (hw->hevc_cur_buf_idx != 0xffff) {
8050 used_4k_num =
8051 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
8052 if (used_4k_num >= 0)
8053 dpb_print(DECODE_ID(hw),
8054 PRINT_FLAG_MMU_DETAIL,
8055 "release unused buf , used_4k_num %ld index %d\n",
8056 used_4k_num, hw->hevc_cur_buf_idx);
8057 hevc_mmu_dma_check(hw_to_vdec(hw));
8058 decoder_mmu_box_free_idx_tail(
8059 hw->mmu_box,
8060 hw->hevc_cur_buf_idx,
8061 used_4k_num);
8062 hw->hevc_cur_buf_idx = 0xffff;
8063 }
8064 }
8065 decode_frame_count[DECODE_ID(hw)]++;
8066 amvdec_stop();
8067 if (!vdec_is_support_4k()) {
8068 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
8069 clk_adj_frame_count++;
8070 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
8071 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8072 }
8073 }
8074 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8075 "%s dec_result %d %x %x %x\n",
8076 __func__,
8077 hw->dec_result,
8078 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8079 READ_VREG(VLD_MEM_VIFIFO_WP),
8080 READ_VREG(VLD_MEM_VIFIFO_RP));
8081 mutex_lock(&hw->chunks_mutex);
8082 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8083 hw->chunk = NULL;
8084 mutex_unlock(&hw->chunks_mutex);
8085 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8086 /*
8087 stream base: stream buf empty or timeout
8088 frame base: vdec_prepare_input fail
8089 */
8090 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8091 VDEC_STATUS_DISCONNECTED)) {
8092 hw->dec_result = DEC_RESULT_EOS;
8093 vdec_schedule_work(&hw->work);
8094 return;
8095 }
8096 hw->next_again_flag = 1;
8097 } else if (hw->dec_result == DEC_RESULT_EOS) {
8098 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8099 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8100 "%s: end of stream\n",
8101 __func__);
8102 amvdec_stop();
8103 if (hw->mmu_enable)
8104 amhevc_stop();
8105 hw->eos = 1;
8106 flush_dpb(p_H264_Dpb);
8107 if (hw->is_used_v4l)
8108 notify_v4l_eos(hw_to_vdec(hw));
8109 mutex_lock(&hw->chunks_mutex);
8110 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8111 hw->chunk = NULL;
8112 mutex_unlock(&hw->chunks_mutex);
8113 vdec_clean_input(vdec);
8114 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8115 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8116 "%s: force exit\n",
8117 __func__);
8118 amvdec_stop();
8119 if (hw->mmu_enable)
8120 amhevc_stop();
8121 if (hw->stat & STAT_ISR_REG) {
8122 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8123 hw->stat &= ~STAT_ISR_REG;
8124 }
8125 }
8126 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8127 del_timer_sync(&hw->check_timer);
8128 hw->stat &= ~STAT_TIMER_ARM;
8129
8130 wait_vmh264_search_done(hw);
8131 /* mark itself has all HW resource released and input released */
8132
8133#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8134 if (hw->switch_dvlayer_flag) {
8135 if (vdec->slave)
8136 vdec_set_next_sched(vdec, vdec->slave);
8137 else if (vdec->master)
8138 vdec_set_next_sched(vdec, vdec->master);
8139 } else if (vdec->slave || vdec->master)
8140 vdec_set_next_sched(vdec, vdec);
8141#endif
8142
8143 if (from == 1) {
8144 /* This is a timeout work */
8145 if (work_pending(&hw->work)) {
8146 /*
8147 * The vh264_work arrives at the last second,
8148 * give it a chance to handle the scenario.
8149 */
8150 return;
8151 }
8152 }
8153
8154 /* mark itself has all HW resource released and input released */
8155 if (vdec->parallel_dec == 1) {
8156 if (hw->mmu_enable == 0)
8157 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8158 else
8159 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8160 } else
8161 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8162
8163 wake_up_interruptible(&hw->wait_q);
8164
8165 if (hw->is_used_v4l) {
8166 struct aml_vcodec_ctx *ctx =
8167 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8168
8169 if (ctx->param_sets_from_ucode &&
8170 !hw->v4l_params_parsed)
8171 vdec_v4l_write_frame_sync(ctx);
8172 }
8173
8174 if (hw->vdec_cb)
8175 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8176}
8177
8178
8179static void vh264_work(struct work_struct *work)
8180{
8181 struct vdec_h264_hw_s *hw = container_of(work,
8182 struct vdec_h264_hw_s, work);
8183 struct vdec_s *vdec = hw_to_vdec(hw);
8184
8185 vh264_work_implement(hw, vdec, 0);
8186}
8187
8188
8189static void vh264_timeout_work(struct work_struct *work)
8190{
8191 struct vdec_h264_hw_s *hw = container_of(work,
8192 struct vdec_h264_hw_s, timeout_work);
8193 struct vdec_s *vdec = hw_to_vdec(hw);
8194
8195 if (work_pending(&hw->work))
8196 return;
8197
8198 vh264_work_implement(hw, vdec, 1);
8199}
8200
8201static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8202{
8203 bool ret = 0;
8204 struct vdec_h264_hw_s *hw =
8205 (struct vdec_h264_hw_s *)vdec->private;
8206 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8207 CODEC_MM_FLAGS_TVP : 0;
8208
8209 if (!hw->first_sc_checked && hw->mmu_enable) {
8210 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8211 hw->first_sc_checked =1;
8212 dpb_print(DECODE_ID(hw), 0,
8213 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8214 size, (hw->need_cache_size >> PAGE_SHIFT),
8215 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8216 }
8217
8218 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8219 && pre_decode_buf_level != 0) {
8220 u32 rp, wp, level;
8221
8222 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8223 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8224 if (wp < rp)
8225 level = vdec->input.size + wp - rp;
8226 else
8227 level = wp - rp;
8228
8229 if (level < pre_decode_buf_level)
8230 return 0;
8231 }
8232
8233#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8234 if (vdec->master)
8235 return 0;
8236#endif
8237 if (hw->eos)
8238 return 0;
8239
8240 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8241 return 0;
8242
8243 if (disp_vframe_valve_level &&
8244 kfifo_len(&hw->display_q) >=
8245 disp_vframe_valve_level) {
8246 hw->valve_count--;
8247 if (hw->valve_count <= 0)
8248 hw->valve_count = 2;
8249 else
8250 return 0;
8251 }
8252 if (hw->next_again_flag &&
8253 (!vdec_frame_based(vdec))) {
8254 u32 parser_wr_ptr =
8255 READ_PARSER_REG(PARSER_VIDEO_WP);
8256 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8257 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8258 again_threshold) {
8259 int r = vdec_sync_input(vdec);
8260 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8261 "%s buf lelvel:%x\n", __func__, r);
8262 return 0;
8263 }
8264 }
8265
8266 if (h264_debug_flag & 0x20000000) {
8267 /* pr_info("%s, a\n", __func__); */
8268 ret = 1;
8269 } else
8270 ret = is_buffer_available(vdec);
8271
8272#ifdef CONSTRAIN_MAX_BUF_NUM
8273 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8274 if (run_ready_max_vf_only_num > 0 &&
8275 get_vf_ref_only_buf_count(hw) >=
8276 run_ready_max_vf_only_num
8277 )
8278 ret = 0;
8279 if (run_ready_display_q_num > 0 &&
8280 kfifo_len(&hw->display_q) >=
8281 run_ready_display_q_num)
8282 ret = 0;
8283 /*avoid more buffers consumed when
8284 switching resolution*/
8285 if (run_ready_max_buf_num == 0xff &&
8286 get_used_buf_count(hw) >
8287 hw->dpb.mDPB.size)
8288 ret = 0;
8289 else if (run_ready_max_buf_num &&
8290 get_used_buf_count(hw) >=
8291 run_ready_max_buf_num)
8292 ret = 0;
8293 }
8294#endif
8295 if (hw->is_used_v4l) {
8296 struct aml_vcodec_ctx *ctx =
8297 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8298
8299 if (ctx->param_sets_from_ucode &&
8300 !ctx->v4l_codec_ready &&
8301 hw->v4l_params_parsed) {
8302 ret = 0; /*the params has parsed.*/
8303 } else if (!ctx->v4l_codec_dpb_ready) {
8304 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8305 run_ready_min_buf_num)
8306 ret = 0;
8307 }
8308 }
8309
8310 if (ret)
8311 not_run_ready[DECODE_ID(hw)] = 0;
8312 else
8313 not_run_ready[DECODE_ID(hw)]++;
8314 if (vdec->parallel_dec == 1) {
8315 if (hw->mmu_enable == 0)
8316 return ret ? (CORE_MASK_VDEC_1) : 0;
8317 else
8318 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8319 } else
8320 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8321}
8322
8323static unsigned char get_data_check_sum
8324 (struct vdec_h264_hw_s *hw, int size)
8325{
8326 int jj;
8327 int sum = 0;
8328 u8 *data = NULL;
8329
8330 if (!hw->chunk->block->is_mapped)
8331 data = codec_mm_vmap(hw->chunk->block->start +
8332 hw->chunk->offset, size);
8333 else
8334 data = ((u8 *)hw->chunk->block->start_virt)
8335 + hw->chunk->offset;
8336
8337 for (jj = 0; jj < size; jj++)
8338 sum += data[jj];
8339
8340 if (!hw->chunk->block->is_mapped)
8341 codec_mm_unmap_phyaddr(data);
8342 return sum;
8343}
8344
8345static void run(struct vdec_s *vdec, unsigned long mask,
8346 void (*callback)(struct vdec_s *, void *), void *arg)
8347{
8348 struct vdec_h264_hw_s *hw =
8349 (struct vdec_h264_hw_s *)vdec->private;
8350 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8351 int size, ret = -1;
8352
8353 run_count[DECODE_ID(hw)]++;
8354 vdec_reset_core(vdec);
8355 if (hw->mmu_enable)
8356 hevc_reset_core(vdec);
8357 hw->vdec_cb_arg = arg;
8358 hw->vdec_cb = callback;
8359
8360 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8361 hw->reset_bufmgr_flag = 1;
8362 dpb_print(DECODE_ID(hw), 0,
8363 "kfifo len:%d invaild, need bufmgr reset\n",
8364 kfifo_len(&hw->display_q));
8365 }
8366
8367 hw->pre_parser_wr_ptr =
8368 READ_PARSER_REG(PARSER_VIDEO_WP);
8369 hw->next_again_flag = 0;
8370
8371 if (hw->reset_bufmgr_flag ||
8372 ((error_proc_policy & 0x40) &&
8373 p_H264_Dpb->buf_alloc_fail)) {
8374 h264_reset_bufmgr(vdec);
8375 hw->reset_bufmgr_flag = 0;
8376 }
8377
8378 if (h264_debug_cmd & 0xf000) {
8379 if (((h264_debug_cmd >> 12) & 0xf)
8380 == (DECODE_ID(hw) + 1)) {
8381 h264_reconfig(hw);
8382 h264_debug_cmd &= (~0xf000);
8383 }
8384 }
8385 /* hw->chunk = vdec_prepare_input(vdec); */
8386#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8387 if (vdec->slave || vdec->master)
8388 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8389#endif
8390 size = vdec_prepare_input(vdec, &hw->chunk);
8391 if ((size < 0) ||
8392 (input_frame_based(vdec) && hw->chunk == NULL)) {
8393 input_empty[DECODE_ID(hw)]++;
8394 hw->dec_result = DEC_RESULT_AGAIN;
8395
8396 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8397 "vdec_prepare_input: Insufficient data\n");
8398
8399 vdec_schedule_work(&hw->work);
8400 return;
8401 }
8402 input_empty[DECODE_ID(hw)] = 0;
8403
8404 hw->dec_result = DEC_RESULT_NONE;
8405 hw->get_data_count = 0;
8406#if 0
8407 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8408 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8409 READ_VREG(VLD_MEM_VIFIFO_RP),
8410 READ_VREG(VLD_MEM_VIFIFO_WP));
8411#endif
8412
8413 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8414 u8 *data = NULL;
8415
8416 if (!hw->chunk->block->is_mapped)
8417 data = codec_mm_vmap(hw->chunk->block->start +
8418 hw->chunk->offset, size);
8419 else
8420 data = ((u8 *)hw->chunk->block->start_virt)
8421 + hw->chunk->offset;
8422
8423 if (dpb_is_debug(DECODE_ID(hw),
8424 PRINT_FLAG_VDEC_STATUS)
8425 ) {
8426 dpb_print(DECODE_ID(hw), 0,
8427 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8428 __func__, size, get_data_check_sum(hw, size),
8429 data[0], data[1], data[2], data[3],
8430 data[4], data[5], data[size - 4],
8431 data[size - 3], data[size - 2],
8432 data[size - 1]);
8433 }
8434 if (dpb_is_debug(DECODE_ID(hw),
8435 PRINT_FRAMEBASE_DATA)
8436 ) {
8437 int jj;
8438
8439 for (jj = 0; jj < size; jj++) {
8440 if ((jj & 0xf) == 0)
8441 dpb_print(DECODE_ID(hw),
8442 PRINT_FRAMEBASE_DATA,
8443 "%06x:", jj);
8444 dpb_print_cont(DECODE_ID(hw),
8445 PRINT_FRAMEBASE_DATA,
8446 "%02x ", data[jj]);
8447 if (((jj + 1) & 0xf) == 0)
8448 dpb_print_cont(DECODE_ID(hw),
8449 PRINT_FRAMEBASE_DATA,
8450 "\n");
8451 }
8452 }
8453
8454 if (!hw->chunk->block->is_mapped)
8455 codec_mm_unmap_phyaddr(data);
8456 } else
8457 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8458 "%s: %x %x %x %x %x size 0x%x\n",
8459 __func__,
8460 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8461 READ_VREG(VLD_MEM_VIFIFO_WP),
8462 READ_VREG(VLD_MEM_VIFIFO_RP),
8463 READ_PARSER_REG(PARSER_VIDEO_RP),
8464 READ_PARSER_REG(PARSER_VIDEO_WP),
8465 size);
8466
8467 start_process_time(hw);
8468 if (vdec->mc_loaded) {
8469 /*firmware have load before,
8470 and not changes to another.
8471 ignore reload.
8472 */
8473 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8474 } else {
8475
8476 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8477 if (ret < 0) {
8478 amvdec_enable_flag = false;
8479 amvdec_disable();
8480
8481 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8482 "MH264 the %s fw loading failed, err: %x\n",
8483 tee_enabled() ? "TEE" : "local", ret);
8484 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8485 vdec_schedule_work(&hw->work);
8486 return;
8487 }
8488 vdec->mc_type = VFORMAT_H264;
8489 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8490 if (hw->mmu_enable) {
8491 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8492 hw->fw_mmu->data);
8493 if (ret < 0) {
8494 amvdec_enable_flag = false;
8495 amhevc_disable();
8496
8497 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8498 "MH264_MMU the %s fw loading failed, err: %x\n",
8499 tee_enabled() ? "TEE" : "local", ret);
8500 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8501 vdec_schedule_work(&hw->work);
8502 return;
8503 }
8504 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8505 }
8506 vdec->mc_loaded = 1;
8507 }
8508 vmh264_reset_udr_mgr(hw);
8509
8510 if (vh264_hw_ctx_restore(hw) < 0) {
8511 vdec_schedule_work(&hw->work);
8512 return;
8513 }
8514 if (input_frame_based(vdec)) {
8515 int decode_size = 0;
8516
8517 decode_size = hw->chunk->size +
8518 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8519 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8520 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8521 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8522 } else {
8523 if (size <= 0)
8524 size = 0x7fffffff; /*error happen*/
8525 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8526 WRITE_VREG(H264_DECODE_SIZE, size);
8527 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8528 }
8529 config_aux_buf(hw);
8530 config_decode_mode(hw);
8531 vdec_enable_input(vdec);
8532 WRITE_VREG(NAL_SEARCH_CTL, 0);
8533 hw->sei_data_len = 0;
8534 if (enable_itu_t35)
8535 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8536 if (!hw->init_flag) {
8537 if (hw->mmu_enable)
8538 WRITE_VREG(NAL_SEARCH_CTL,
8539 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8540 else
8541 WRITE_VREG(NAL_SEARCH_CTL,
8542 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8543 }
8544 if (udebug_flag)
8545 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8546 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8547
8548 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8549
8550 if (hw->mmu_enable)
8551 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8552 else
8553 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8554 }
8555 amvdec_start();
8556 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8557 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8558 amhevc_start();
8559 if (hw->config_bufmgr_done) {
8560 hevc_mcr_sao_global_hw_init(hw,
8561 (hw->mb_width << 4), (hw->mb_height << 4));
8562 hevc_mcr_config_canv2axitbl(hw, 1);
8563 }
8564 }
8565
8566 /* if (hw->init_flag) { */
8567 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8568 /* } */
8569
8570 hw->init_flag = 1;
8571}
8572
8573static void clear_refer_bufs(struct vdec_h264_hw_s *hw)
8574{
8575 int i;
8576
8577 mutex_lock(&vmh264_mutex);
8578 dealloc_buf_specs(hw, 1);
8579 mutex_unlock(&vmh264_mutex);
8580
8581 INIT_KFIFO(hw->display_q);
8582 INIT_KFIFO(hw->newframe_q);
8583
8584 for (i = 0; i < VF_POOL_SIZE; i++) {
8585 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8586 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8587 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8588 kfifo_put(&hw->newframe_q, vf);
8589 }
8590}
8591
8592static void reset(struct vdec_s *vdec)
8593{
8594 struct vdec_h264_hw_s *hw =
8595 (struct vdec_h264_hw_s *)vdec->private;
8596
8597 pr_info("vmh264 reset\n");
8598
8599 cancel_work_sync(&hw->work);
8600 cancel_work_sync(&hw->notify_work);
8601 if (hw->stat & STAT_VDEC_RUN) {
8602 amhevc_stop();
8603 hw->stat &= ~STAT_VDEC_RUN;
8604 }
8605
8606 if (hw->stat & STAT_TIMER_ARM) {
8607 del_timer_sync(&hw->check_timer);
8608 hw->stat &= ~STAT_TIMER_ARM;
8609 }
8610 hw->eos = 0;
8611 hw->decode_pic_count = 0;
8612 hw->dec_result = DEC_RESULT_NONE;
8613
8614 clear_refer_bufs(hw);
8615 reset_process_time(hw);
8616 h264_reset_bufmgr(vdec);
8617
8618 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8619}
8620
8621static void h264_reconfig(struct vdec_h264_hw_s *hw)
8622{
8623 int i;
8624 unsigned long flags;
8625 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8626 struct vdec_s *vdec = hw_to_vdec(hw);
8627 dpb_print(DECODE_ID(hw), 0,
8628 "%s\n", __func__);
8629 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8630 all buffers are in display queue (used == 2),
8631 or free (used == 0)
8632 */
8633 if (dpb_is_debug(DECODE_ID(hw),
8634 PRINT_FLAG_DUMP_BUFSPEC))
8635 dump_bufspec(hw, "pre h264_reconfig");
8636
8637 flush_dpb(p_H264_Dpb);
8638 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8639
8640 if (hw->collocate_cma_alloc_addr) {
8641 decoder_bmmu_box_free_idx(
8642 hw->bmmu_box,
8643 BMMU_REF_IDX);
8644 hw->collocate_cma_alloc_addr = 0;
8645 hw->dpb.colocated_mv_addr_start = 0;
8646 hw->dpb.colocated_mv_addr_end = 0;
8647 }
8648 spin_lock_irqsave(&hw->bufspec_lock, flags);
8649 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8650 if (vdec->parallel_dec == 1) {
8651 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8652 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8653 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8654 hw->buffer_spec[i].y_canvas_index = -1;
8655 hw->buffer_spec[i].u_canvas_index = -1;
8656 hw->buffer_spec[i].v_canvas_index = -1;
8657#ifdef VDEC_DW
8658 if (IS_VDEC_DW(hw)) {
8659 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8660 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8661 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8662 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8663 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8664 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8665#endif
8666 }
8667 }
8668 /*make sure buffers not put back to bufmgr when
8669 vf_put is called*/
8670 if (hw->buffer_spec[i].used == 2)
8671 hw->buffer_spec[i].used = 3;
8672
8673 /* ready to release "free buffers"
8674 */
8675 if (hw->buffer_spec[i].used == 0)
8676 hw->buffer_spec[i].used = 4;
8677
8678 hw->buffer_spec[i].canvas_pos = -1;
8679 }
8680 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8681 hw->has_i_frame = 0;
8682 hw->config_bufmgr_done = 0;
8683
8684 if (hw->is_used_v4l) {
8685 mutex_lock(&vmh264_mutex);
8686 dealloc_buf_specs(hw, 1);
8687 mutex_unlock(&vmh264_mutex);
8688 }
8689
8690 if (dpb_is_debug(DECODE_ID(hw),
8691 PRINT_FLAG_DUMP_BUFSPEC))
8692 dump_bufspec(hw, "after h264_reconfig");
8693}
8694
8695#ifdef ERROR_HANDLE_TEST
8696static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8697{
8698 int i;
8699 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8700 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8701 "%s\n", __func__);
8702 remove_dpb_pictures(p_H264_Dpb);
8703 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8704 /*make sure buffers not put back to bufmgr when
8705 vf_put is called*/
8706 if (hw->buffer_spec[i].used == 2)
8707 hw->buffer_spec[i].used = 5;
8708 }
8709
8710}
8711#endif
8712
8713static void h264_reset_bufmgr(struct vdec_s *vdec)
8714{
8715 ulong timeout;
8716 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8717#if 0
8718 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8719 int actual_dpb_size, max_reference_size;
8720 int reorder_pic_num;
8721 unsigned int colocated_buf_size;
8722 unsigned int colocated_mv_addr_start;
8723 unsigned int colocated_mv_addr_end;
8724 dpb_print(DECODE_ID(hw), 0,
8725 "%s\n", __func__);
8726
8727 for (i = 0; i < VF_POOL_SIZE; i++)
8728 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8729
8730 actual_dpb_size = p_H264_Dpb->mDPB.size;
8731 max_reference_size = p_H264_Dpb->max_reference_size;
8732 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8733
8734 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8735 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8736 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8737
8738 hw->cur_pool++;
8739 if (hw->cur_pool >= VF_POOL_NUM)
8740 hw->cur_pool = 0;
8741
8742 INIT_KFIFO(hw->display_q);
8743 INIT_KFIFO(hw->newframe_q);
8744
8745 for (i = 0; i < VF_POOL_SIZE; i++) {
8746 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8747 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8748 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8749 kfifo_put(&hw->newframe_q, vf);
8750 }
8751
8752 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8753 hw->buffer_spec[i].used = 0;
8754
8755 dpb_init_global(&hw->dpb,
8756 DECODE_ID(hw), 0, 0);
8757 p_H264_Dpb->mDPB.size = actual_dpb_size;
8758 p_H264_Dpb->max_reference_size = max_reference_size;
8759 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8760
8761 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8762 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8763 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8764
8765 p_H264_Dpb->fast_output_enable = fast_output_enable;
8766 hw->has_i_frame = 0;
8767#else
8768 dpb_print(DECODE_ID(hw), 0,
8769 "%s frame count %d to skip %d\n\n",
8770 __func__, hw->decode_pic_count+1,
8771 hw->skip_frame_count);
8772
8773 timeout = jiffies + HZ;
8774 while (kfifo_len(&hw->display_q) > 0) {
8775 if (time_after(jiffies, timeout))
8776 break;
8777 schedule();
8778 }
8779
8780 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8781
8782 buf_spec_init(hw);
8783
8784 vh264_local_init(hw, true);
8785 /*hw->decode_pic_count = 0;
8786 hw->seq_info2 = 0;*/
8787
8788 if (vh264_set_params(hw,
8789 hw->cfg_param1,
8790 hw->cfg_param2,
8791 hw->cfg_param3,
8792 hw->cfg_param4) < 0)
8793 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8794
8795 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8796 if (first_i_policy & 0x01)
8797 hw->first_i_policy = (3 << 8) | first_i_policy;
8798
8799 hw->init_flag = 1;
8800 hw->reset_bufmgr_count++;
8801#endif
8802}
8803
8804int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8805{
8806 int ret = -1;
8807 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8808 CODEC_MM_FLAGS_TVP : 0;
8809 int buf_size = 64;
8810
8811 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8812 tvp_flag, hw->mmu_enable);
8813 hw->need_cache_size = buf_size * SZ_1M;
8814 hw->sc_start_time = get_jiffies_64();
8815 if (hw->mmu_enable && !hw->mmu_box) {
8816 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8817 hw->id,
8818 MMU_MAX_BUFFERS,
8819 hw->need_cache_size,
8820 tvp_flag);
8821 if (!hw->mmu_box) {
8822 pr_err("h264 4k alloc mmu box failed!!\n");
8823 return -1;
8824 }
8825 ret = 0;
8826 }
8827 if (!hw->bmmu_box) {
8828 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8829 DRIVER_NAME,
8830 hw->id,
8831 BMMU_MAX_BUFFERS,
8832 4 + PAGE_SHIFT,
8833 CODEC_MM_FLAGS_CMA_CLEAR |
8834 CODEC_MM_FLAGS_FOR_VDECODER |
8835 tvp_flag);
8836 if (hw->bmmu_box)
8837 ret = 0;
8838 }
8839 return ret;
8840}
8841int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8842{
8843 if (hw->mmu_box) {
8844 decoder_mmu_box_free(hw->mmu_box);
8845 hw->mmu_box = NULL;
8846 }
8847 if (hw->bmmu_box) {
8848 decoder_bmmu_box_free(hw->bmmu_box);
8849 hw->bmmu_box = NULL;
8850 }
8851 return 0;
8852}
8853
8854static int ammvdec_h264_probe(struct platform_device *pdev)
8855{
8856 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8857 struct vdec_h264_hw_s *hw = NULL;
8858 char *tmpbuf;
8859 int config_val;
8860
8861 if (pdata == NULL) {
8862 pr_info("\nammvdec_h264 memory resource undefined.\n");
8863 return -EFAULT;
8864 }
8865
8866 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8867 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8868 if (hw == NULL) {
8869 pr_info("\nammvdec_h264 device data allocation failed\n");
8870 return -ENOMEM;
8871 }
8872 hw->id = pdev->id;
8873 hw->platform_dev = pdev;
8874
8875 /* the ctx from v4l2 driver. */
8876 hw->v4l2_ctx = pdata->private;
8877
8878 platform_set_drvdata(pdev, pdata);
8879
8880 hw->mmu_enable = 0;
8881 hw->first_head_check_flag = 0;
8882 hw->new_iframe_flag = 0;
8883 hw->ref_err_flush_dpb_flag = 0;
8884
8885 if (pdata->sys_info)
8886 hw->vh264_amstream_dec_info = *pdata->sys_info;
8887
8888 if (force_enable_mmu && pdata->sys_info &&
8889 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8890 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8891 (pdata->sys_info->height * pdata->sys_info->width
8892 > 1920 * 1088))
8893 hw->mmu_enable = 1;
8894
8895 if (hw->mmu_enable &&
8896 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8897 hw->mmu_enable = 0;
8898 pr_info("ionvideo needs disable mmu, path= %d \n",
8899 pdata->frame_base_video_path);
8900 }
8901
8902 if (ammvdec_h264_mmu_init(hw)) {
8903 h264_free_hw_stru(&pdev->dev, (void *)hw);
8904 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8905 return -ENOMEM;
8906 }
8907
8908 if (pdata->config_len) {
8909 /*use ptr config for doubel_write_mode, etc*/
8910 if (get_config_int(pdata->config,
8911 "mh264_double_write_mode", &config_val) == 0)
8912 hw->double_write_mode = config_val;
8913 else
8914 hw->double_write_mode = double_write_mode;
8915
8916 if (get_config_int(pdata->config,
8917 "parm_v4l_codec_enable",
8918 &config_val) == 0)
8919 hw->is_used_v4l = config_val;
8920
8921 if (get_config_int(pdata->config,
8922 "parm_v4l_buffer_margin",
8923 &config_val) == 0)
8924 hw->reorder_dpb_size_margin = config_val;
8925
8926 if (get_config_int(pdata->config,
8927 "parm_v4l_canvas_mem_mode",
8928 &config_val) == 0)
8929 hw->canvas_mode = config_val;
8930 } else
8931 hw->double_write_mode = double_write_mode;
8932
8933 if (!hw->is_used_v4l) {
8934 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8935 hw->canvas_mode = mem_map_mode;
8936
8937 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8938 hw->canvas_mode = pdata->canvas_mode;
8939 }
8940
8941 if (hw->mmu_enable)
8942 hw->double_write_mode &= 0xffff;
8943
8944 if (pdata->parallel_dec == 1) {
8945 int i;
8946 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8947 hw->buffer_spec[i].y_canvas_index = -1;
8948 hw->buffer_spec[i].u_canvas_index = -1;
8949 hw->buffer_spec[i].v_canvas_index = -1;
8950#ifdef VDEC_DW
8951 if (IS_VDEC_DW(hw)) {
8952 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8953 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8954 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8955 }
8956#endif
8957 }
8958 }
8959
8960 dpb_print(DECODE_ID(hw), 0,
8961 "%s mmu_enable %d double_write_mode 0x%x\n",
8962 __func__, hw->mmu_enable, hw->double_write_mode);
8963
8964 pdata->private = hw;
8965 pdata->dec_status = dec_status;
8966 pdata->set_trickmode = vmh264_set_trickmode;
8967 pdata->run_ready = run_ready;
8968 pdata->run = run;
8969 pdata->reset = reset;
8970 pdata->irq_handler = vh264_isr;
8971 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8972 pdata->dump_state = vmh264_dump_state;
8973
8974#ifdef MH264_USERDATA_ENABLE
8975 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8976 pdata->user_data_read = vmh264_user_data_read;
8977 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8978#else
8979 pdata->wakeup_userdata_poll = NULL;
8980 pdata->user_data_read = NULL;
8981 pdata->reset_userdata_fifo = NULL;
8982#endif
8983 if (pdata->use_vfm_path) {
8984 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8985 VFM_DEC_PROVIDER_NAME);
8986 hw->frameinfo_enable = 1;
8987 }
8988#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8989 else if (vdec_dual(pdata)) {
8990 if (dv_toggle_prov_name) /*debug purpose*/
8991 snprintf(pdata->vf_provider_name,
8992 VDEC_PROVIDER_NAME_SIZE,
8993 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8994 VFM_DEC_DVEL_PROVIDER_NAME);
8995 else
8996 snprintf(pdata->vf_provider_name,
8997 VDEC_PROVIDER_NAME_SIZE,
8998 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8999 VFM_DEC_DVBL_PROVIDER_NAME);
9000 }
9001#endif
9002 else
9003 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9004 PROVIDER_NAME ".%02x", pdev->id & 0xff);
9005
9006 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
9007 &vf_provider_ops, pdata);
9008
9009 platform_set_drvdata(pdev, pdata);
9010
9011 buf_spec_init(hw);
9012
9013 hw->platform_dev = pdev;
9014
9015#ifdef DUMP_USERDATA_RECORD
9016 vmh264_init_userdata_dump();
9017 vmh264_reset_user_data_buf();
9018#endif
9019 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
9020 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
9021 h264_free_hw_stru(&pdev->dev, (void *)hw);
9022 pdata->dec_status = NULL;
9023 return -ENOMEM;
9024 }
9025
9026 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
9027 DCAC_READ_MARGIN;
9028 if (hw->mmu_enable) {
9029 u32 extif_size = EXTIF_BUF_SIZE;
9030 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
9031 extif_size <<= 1;
9032 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
9033 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
9034 h264_free_hw_stru(&pdev->dev, (void *)hw);
9035 pdata->dec_status = NULL;
9036 return -ENOMEM;
9037 }
9038 }
9039 if (!vdec_secure(pdata)) {
9040#if 1
9041 /*init internal buf*/
9042 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
9043 if (tmpbuf) {
9044 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9045 codec_mm_dma_flush(tmpbuf,
9046 V_BUF_ADDR_OFFSET,
9047 DMA_TO_DEVICE);
9048 } else {
9049 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
9050 V_BUF_ADDR_OFFSET);
9051 if (tmpbuf) {
9052 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9053 codec_mm_dma_flush(tmpbuf,
9054 V_BUF_ADDR_OFFSET,
9055 DMA_TO_DEVICE);
9056 codec_mm_unmap_phyaddr(tmpbuf);
9057 }
9058 }
9059#else
9060 /*init sps/pps internal buf 64k*/
9061 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
9062 + (mem_sps_base - DEF_BUF_START_ADDR));
9063 memset(tmpbuf, 0, 0x10000);
9064 dma_sync_single_for_device(amports_get_dma_device(),
9065 hw->cma_alloc_addr +
9066 (mem_sps_base - DEF_BUF_START_ADDR),
9067 0x10000, DMA_TO_DEVICE);
9068#endif
9069 }
9070 /**/
9071
9072#if 0
9073 if (NULL == hw->sei_data_buffer) {
9074 hw->sei_data_buffer =
9075 dma_alloc_coherent(amports_get_dma_device(),
9076 USER_DATA_SIZE,
9077 &hw->sei_data_buffer_phys, GFP_KERNEL);
9078 if (!hw->sei_data_buffer) {
9079 pr_info("%s: Can not allocate sei_data_buffer\n",
9080 __func__);
9081 ammvdec_h264_mmu_release(hw);
9082 h264_free_hw_stru(&pdev->dev, (void *)hw);
9083 return -ENOMEM;
9084 }
9085 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9086 sei_data_buffer, sei_data_buffer_phys,
9087 (u32)sei_data_buffer_remap); */
9088 }
9089#endif
9090 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9091 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9092
9093 if (vdec_is_support_4k() ||
9094 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9095 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9096 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9097 {
9098 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9099 }else
9100 {
9101 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9102 }
9103
9104 if (vh264_init(hw) < 0) {
9105 pr_info("\nammvdec_h264 init failed.\n");
9106 ammvdec_h264_mmu_release(hw);
9107 h264_free_hw_stru(&pdev->dev, (void *)hw);
9108 pdata->dec_status = NULL;
9109 return -ENODEV;
9110 }
9111#ifdef MH264_USERDATA_ENABLE
9112 vmh264_crate_userdata_manager(hw,
9113 hw->sei_user_data_buffer,
9114 USER_DATA_SIZE);
9115#endif
9116
9117 vdec_set_prepare_level(pdata, start_decode_buf_level);
9118 if (pdata->parallel_dec == 1) {
9119 if (hw->mmu_enable == 0)
9120 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9121 else {
9122 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9123 | CORE_MASK_COMBINE);
9124 }
9125 } else
9126 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9127 | CORE_MASK_COMBINE);
9128
9129 atomic_set(&hw->vh264_active, 1);
9130
9131 return 0;
9132}
9133
9134static int ammvdec_h264_remove(struct platform_device *pdev)
9135{
9136 struct vdec_h264_hw_s *hw =
9137 (struct vdec_h264_hw_s *)
9138 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9139 int i;
9140
9141 struct vdec_s *vdec = hw_to_vdec(hw);
9142
9143 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9144 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9145 dpb_print(DECODE_ID(hw), 0,
9146 "%s force exit %d\n", __func__, __LINE__);
9147 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9148 vdec_schedule_work(&hw->work);
9149 wait_event_interruptible_timeout(hw->wait_q,
9150 (vdec->status == VDEC_STATUS_CONNECTED),
9151 msecs_to_jiffies(1000)); /* wait for work done */
9152 }
9153
9154 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9155 release_aux_data(hw, i);
9156
9157 atomic_set(&hw->vh264_active, 0);
9158
9159 if (hw->stat & STAT_TIMER_ARM) {
9160 del_timer_sync(&hw->check_timer);
9161 hw->stat &= ~STAT_TIMER_ARM;
9162 }
9163
9164 vh264_stop(hw);
9165#ifdef MH264_USERDATA_ENABLE
9166#ifdef DUMP_USERDATA_RECORD
9167 vmh264_dump_userdata();
9168#endif
9169 vmh264_destroy_userdata_manager(hw);
9170#endif
9171 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9172
9173 atomic_set(&hw->vh264_active, 0);
9174 if (vdec->parallel_dec == 1) {
9175 if (hw->mmu_enable == 0)
9176 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9177 else
9178 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9179 CORE_MASK_COMBINE);
9180 } else
9181 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9182
9183 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9184 if (vdec->parallel_dec == 1) {
9185 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9186 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9187 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9188 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9189 if (IS_VDEC_DW(hw)) {
9190 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9191 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9192 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9193 }
9194 }
9195 }
9196
9197 ammvdec_h264_mmu_release(hw);
9198 h264_free_hw_stru(&pdev->dev, (void *)hw);
9199 clk_adj_frame_count = 0;
9200
9201 return 0;
9202}
9203
9204/****************************************/
9205#ifdef CONFIG_PM
9206static int mh264_suspend(struct device *dev)
9207{
9208 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9209 return 0;
9210}
9211
9212static int mh264_resume(struct device *dev)
9213{
9214 amvdec_resume(to_platform_device(dev));
9215 return 0;
9216}
9217
9218static const struct dev_pm_ops mh264_pm_ops = {
9219 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9220};
9221#endif
9222
9223static struct platform_driver ammvdec_h264_driver = {
9224 .probe = ammvdec_h264_probe,
9225 .remove = ammvdec_h264_remove,
9226 .driver = {
9227 .name = DRIVER_NAME,
9228#ifdef CONFIG_PM
9229 .pm = &mh264_pm_ops,
9230#endif
9231 }
9232};
9233
9234static struct codec_profile_t ammvdec_h264_profile = {
9235 .name = "mh264",
9236 .profile = ""
9237};
9238
9239static struct mconfig hm264_configs[] = {
9240 MC_PU32("h264_debug_flag", &h264_debug_flag),
9241 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9242 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9243 MC_PU32("decode_timeout_val", &decode_timeout_val),
9244 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9245 MC_PU32("reference_buf_margin", &reference_buf_margin),
9246 MC_PU32("radr", &radr),
9247 MC_PU32("rval", &rval),
9248 MC_PU32("h264_debug_mask", &h264_debug_mask),
9249 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9250 MC_PI32("force_rate_streambase", &force_rate_streambase),
9251 MC_PI32("dec_control", &dec_control),
9252 MC_PI32("force_rate_framebase", &force_rate_framebase),
9253 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9254 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9255 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9256#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9257 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9258 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9259 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9260#endif
9261 MC_PU32("i_only_flag", &i_only_flag),
9262 MC_PU32("force_rate_streambase", &force_rate_streambase),
9263};
9264static struct mconfig_node hm264_node;
9265
9266
9267static int __init ammvdec_h264_driver_init_module(void)
9268{
9269 pr_info("ammvdec_h264 module init\n");
9270 if (platform_driver_register(&ammvdec_h264_driver)) {
9271 pr_info("failed to register ammvdec_h264 driver\n");
9272 return -ENODEV;
9273 }
9274
9275 if (vdec_is_support_4k()) {
9276 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9277 ammvdec_h264_profile.profile =
9278 "4k, dwrite, compressed";
9279 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9280 ammvdec_h264_profile.profile = "4k";
9281 }
9282 }
9283
9284 vcodec_profile_register(&ammvdec_h264_profile);
9285 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9286 "mh264", hm264_configs, CONFIG_FOR_RW);
9287 return 0;
9288}
9289
9290static void __exit ammvdec_h264_driver_remove_module(void)
9291{
9292 pr_info("ammvdec_h264 module remove.\n");
9293
9294 platform_driver_unregister(&ammvdec_h264_driver);
9295}
9296
9297/****************************************/
9298module_param(h264_debug_flag, uint, 0664);
9299MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9300
9301module_param(start_decode_buf_level, int, 0664);
9302MODULE_PARM_DESC(start_decode_buf_level,
9303 "\n ammvdec_h264 start_decode_buf_level\n");
9304
9305module_param(pre_decode_buf_level, int, 0664);
9306MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9307
9308module_param(fixed_frame_rate_mode, uint, 0664);
9309MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9310
9311module_param(decode_timeout_val, uint, 0664);
9312MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9313
9314module_param(errordata_timeout_val, uint, 0664);
9315MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9316
9317module_param(get_data_timeout_val, uint, 0664);
9318MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9319
9320module_param(frame_max_data_packet, uint, 0664);
9321MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9322
9323module_param(reorder_dpb_size_margin, uint, 0664);
9324MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9325
9326#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9327module_param(reorder_dpb_size_margin_dv, uint, 0664);
9328MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9329 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9330#endif
9331
9332module_param(reference_buf_margin, uint, 0664);
9333MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9334
9335#ifdef CONSTRAIN_MAX_BUF_NUM
9336module_param(run_ready_max_vf_only_num, uint, 0664);
9337MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9338
9339module_param(run_ready_display_q_num, uint, 0664);
9340MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9341
9342module_param(run_ready_max_buf_num, uint, 0664);
9343MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9344#endif
9345
9346module_param(radr, uint, 0664);
9347MODULE_PARM_DESC(radr, "\nradr\n");
9348
9349module_param(rval, uint, 0664);
9350MODULE_PARM_DESC(rval, "\nrval\n");
9351
9352module_param(h264_debug_mask, uint, 0664);
9353MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9354
9355module_param(h264_debug_cmd, uint, 0664);
9356MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9357
9358module_param(force_rate_streambase, int, 0664);
9359MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9360
9361module_param(dec_control, int, 0664);
9362MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9363
9364module_param(force_rate_framebase, int, 0664);
9365MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9366
9367module_param(force_disp_bufspec_num, int, 0664);
9368MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9369
9370module_param(V_BUF_ADDR_OFFSET, int, 0664);
9371MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9372
9373module_param(prefix_aux_buf_size, uint, 0664);
9374MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9375
9376module_param(suffix_aux_buf_size, uint, 0664);
9377MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9378
9379#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9380module_param(dv_toggle_prov_name, uint, 0664);
9381MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9382
9383module_param(dolby_meta_with_el, uint, 0664);
9384MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9385
9386#endif
9387
9388module_param(fast_output_enable, uint, 0664);
9389MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9390
9391module_param(error_proc_policy, uint, 0664);
9392MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9393
9394module_param(error_skip_count, uint, 0664);
9395MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9396
9397module_param(force_sliding_margin, uint, 0664);
9398MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9399
9400module_param(i_only_flag, uint, 0664);
9401MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9402
9403module_param(first_i_policy, uint, 0664);
9404MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9405
9406module_param(frmbase_cont_bitlevel, uint, 0664);
9407MODULE_PARM_DESC(frmbase_cont_bitlevel,
9408 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9409
9410module_param(frmbase_cont_bitlevel2, uint, 0664);
9411MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9412 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9413
9414module_param(udebug_flag, uint, 0664);
9415MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9416
9417module_param(udebug_pause_pos, uint, 0664);
9418MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9419
9420module_param(udebug_pause_val, uint, 0664);
9421MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9422
9423module_param(udebug_pause_decode_idx, uint, 0664);
9424MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9425
9426module_param(max_alloc_buf_count, uint, 0664);
9427MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9428
9429module_param(enable_itu_t35, uint, 0664);
9430MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9431
9432module_param(endian, uint, 0664);
9433MODULE_PARM_DESC(endian, "\nrval\n");
9434
9435module_param(mmu_enable, uint, 0664);
9436MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9437
9438module_param(force_enable_mmu, uint, 0664);
9439MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9440
9441module_param(again_threshold, uint, 0664);
9442MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9443
9444module_param(stream_mode_start_num, uint, 0664);
9445MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9446
9447/*
9448module_param(trigger_task, uint, 0664);
9449MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9450*/
9451module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9452
9453module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9454
9455module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9456
9457module_param_array(run_count, uint,
9458 &max_decode_instance_num, 0664);
9459
9460module_param_array(not_run_ready, uint,
9461 &max_decode_instance_num, 0664);
9462
9463module_param_array(input_empty, uint,
9464 &max_decode_instance_num, 0664);
9465
9466module_param_array(max_get_frame_interval, uint,
9467 &max_decode_instance_num, 0664);
9468
9469module_param_array(step, uint, &max_decode_instance_num, 0664);
9470
9471module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9472
9473module_param(disp_vframe_valve_level, uint, 0664);
9474MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9475
9476module_param(double_write_mode, uint, 0664);
9477MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9478
9479module_param(mem_map_mode, uint, 0664);
9480MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9481
9482module_param(without_display_mode, uint, 0664);
9483MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9484
9485
9486module_init(ammvdec_h264_driver_init_module);
9487module_exit(ammvdec_h264_driver_remove_module);
9488
9489MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9490MODULE_LICENSE("GPL");
9491
generated by cgit at 2024-05-17 10:48:31 (GMT)