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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
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1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120
121static int mmu_enable;
122/*mmu do not support mbaff*/
123static int force_enable_mmu = 0;
124unsigned int h264_debug_flag; /* 0xa0000000; */
125unsigned int h264_debug_mask = 0xff;
126 /*
127 *h264_debug_cmd:
128 * 0x1xx, force decoder id of xx to be disconnected
129 */
130unsigned int h264_debug_cmd;
131
132static unsigned int dec_control =
133 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
134 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
135
136static unsigned int force_rate_streambase;
137static unsigned int force_rate_framebase;
138static unsigned int force_disp_bufspec_num;
139static unsigned int fixed_frame_rate_mode;
140static unsigned int error_recovery_mode_in;
141static int start_decode_buf_level = 0x4000;
142static int pre_decode_buf_level = 0x1000;
143static int stream_mode_start_num = 4;
144
145#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
146/*to make reorder size difference of bl and el not too big*/
147static unsigned int reorder_dpb_size_margin_dv = 16;
148#endif
149static unsigned int reorder_dpb_size_margin = 6;
150static unsigned int reference_buf_margin = 4;
151
152#ifdef CONSTRAIN_MAX_BUF_NUM
153static u32 run_ready_max_vf_only_num;
154static u32 run_ready_display_q_num;
155 /*0: not check
156 0xff: mDPB.size
157 */
158static u32 run_ready_max_buf_num = 0xff;
159#endif
160
161#define VDEC_ASSIST_CANVAS_BLK32 0x5
162
163
164static unsigned int max_alloc_buf_count;
165static unsigned int decode_timeout_val = 100;
166static unsigned int errordata_timeout_val = 50;
167static unsigned int get_data_timeout_val = 2000;
168#if 1
169/* H264_DATA_REQUEST does not work, disable it,
170decode has error for data in none continuous address
171*/
172static unsigned int frame_max_data_packet;
173#else
174static unsigned int frame_max_data_packet = 8;
175#endif
176static unsigned int radr;
177static unsigned int rval;
178static u32 endian = 0xff0;
179
180/*
181 udebug_flag:
182 bit 0, enable ucode print
183 bit 1, enable ucode detail print
184 bit 3, disable ucode watchdog
185 bit [31:16] not 0, pos to dump lmem
186 bit 2, pop bits to lmem
187 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
188*/
189static u32 udebug_flag;
190/*
191 when udebug_flag[1:0] is not 0
192 udebug_pause_pos not 0,
193 pause position
194*/
195static u32 udebug_pause_pos;
196/*
197 when udebug_flag[1:0] is not 0
198 and udebug_pause_pos is not 0,
199 pause only when DEBUG_REG2 is equal to this val
200*/
201static u32 udebug_pause_val;
202
203static u32 udebug_pause_decode_idx;
204
205static unsigned int disp_vframe_valve_level;
206
207static unsigned int max_decode_instance_num = H264_DEV_NUM;
208static unsigned int decode_frame_count[H264_DEV_NUM];
209static unsigned int display_frame_count[H264_DEV_NUM];
210static unsigned int max_process_time[H264_DEV_NUM];
211static unsigned int max_get_frame_interval[H264_DEV_NUM];
212static unsigned int run_count[H264_DEV_NUM];
213static unsigned int input_empty[H264_DEV_NUM];
214static unsigned int not_run_ready[H264_DEV_NUM];
215static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
216{1, 1, 1, 1, 1, 1, 1, 1, 1};
217
218#define VDEC_CLOCK_ADJUST_FRAME 30
219static unsigned int clk_adj_frame_count;
220
221/*
222 *bit[3:0]: 0, run ; 1, pause; 3, step
223 *bit[4]: 1, schedule run
224 */
225static unsigned int step[H264_DEV_NUM];
226
227#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
228static u32 prefix_aux_buf_size = (16 * 1024);
229static u32 suffix_aux_buf_size;
230
231#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
232static u32 dv_toggle_prov_name;
233
234static u32 dolby_meta_with_el;
235#endif
236
237/*
238 bit[8]
239 0: use sys_info[bit 3]
240 not 0:use i_only_flag[7:0]
241 bit[7:0]:
242 bit 0, 1: only display I picture;
243 bit 1, 1: only decode I picture;
244*/
245static unsigned int i_only_flag;
246
247/*
248 error_proc_policy:
249 bit[0] send_error_frame_flag;
250 (valid when bit[31] is 1, otherwise use sysinfo)
251 bit[1] do not decode if config_decode_buf() fail
252 bit[2] force release buf if in deadlock
253 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
254 bit[4] check inactive of receiver
255 bit[5] reset buffmgr if in deadlock
256 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
257 bit[7] reset buffmgr if dpb error
258
259 bit[8] check total mbx/mby of decoded frame
260 bit[9] check ERROR_STATUS_REG
261 bit[10] check reference list
262 bit[11] mark error if dpb error
263 bit[12] i_only when error happen
264 bit[13] 0: mark error according to last pic, 1: ignore mark error
265 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
266*/
267static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
268
269
270/*
271 error_skip_count:
272 bit[11:0] error skip frame count
273 bit[15:12] error skip i picture count
274*/
275static unsigned int error_skip_count = (0x2 << 12) | 0x40;
276
277static unsigned int force_sliding_margin;
278/*
279 bit[1:0]:
280 0, start playing from any frame
281 1, start playing from I frame
282 bit[15:8]: the count of skip frames after first I
283 2, start playing from second I frame (decode from the first I)
284 bit[15:8]: the max count of skip frames after first I
285 3, start playing from IDR
286*/
287static unsigned int first_i_policy = 1;
288
289/*
290 fast_output_enable:
291 bit [0], output frame if there is IDR in list
292 bit [1], output frame if the current poc is 1 big than the previous poc
293 bit [2], if even poc only, output frame ifthe cuurent poc
294 is 2 big than the previous poc
295 bit [3], ip only
296*/
297static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
298
299static unsigned int enable_itu_t35 = 1;
300
301static unsigned int frmbase_cont_bitlevel = 0x40;
302
303static unsigned int frmbase_cont_bitlevel2 = 0x1;
304
305
306#define MH264_USERDATA_ENABLE
307
308/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
309/* hevc->double_write_mode:
310 0, no double write
311 1, 1:1 ratio
312 2, (1/4):(1/4) ratio
313 3, (1/4):(1/4) ratio, with both compressed frame included
314 4, (1/2):(1/2) ratio
315 0x10, double write only
316 0x10000: vdec dw horizotal 1/2
317 0x20000: vdec dw horizotal/vertical 1/2
318*/
319static u32 double_write_mode;
320static u32 without_display_mode;
321#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
322
323static void vmh264_dump_state(struct vdec_s *vdec);
324
325#define is_in_parsing_state(status) \
326 ((status == H264_ACTION_SEARCH_HEAD) || \
327 ((status & 0xf0) == 0x80))
328
329#define is_interlace(frame) \
330 (frame->frame &&\
331 frame->top_field &&\
332 frame->bottom_field &&\
333 (!frame->frame->coded_frame))
334static inline bool close_to(int a, int b, int m)
335{
336 return (abs(a - b) < m) ? true : false;
337}
338
339#if 0
340#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
341#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
342#else
343#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
344#define h264_free_hw_stru(dev, hw) vfree(hw)
345#endif
346
347/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
348#define NV21
349/* #endif */
350
351/* 12M for L41 */
352#define MAX_DPB_BUFF_SIZE (12*1024*1024)
353#define DEFAULT_MEM_SIZE (32*1024*1024)
354#define AVIL_DPB_BUFF_SIZE 0x01ec2000
355
356#define DEF_BUF_START_ADDR 0x01000000
357#define mem_sps_base 0x011c3c00
358#define mem_pps_base 0x011cbc00
359/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
360u32 V_BUF_ADDR_OFFSET = 0x200000;
361#define DCAC_READ_MARGIN (64 * 1024)
362
363
364#define EXTEND_SAR 0xff
365#define BUFSPEC_POOL_SIZE 64
366#define VF_POOL_SIZE 64
367#define VF_POOL_NUM 2
368#define MAX_VF_BUF_NUM 27
369#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
370#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
371#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
372#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
373#define EXTIF_BUF_SIZE (0x10000 * 2)
374
375#define HEADER_BUFFER_IDX(n) (n)
376#define VF_BUFFER_IDX(n) (n)
377
378
379#define PUT_INTERVAL (HZ/100)
380#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
381
382#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
383#define SWITCHING_STATE_OFF 0
384#define SWITCHING_STATE_ON_CMD3 1
385#define SWITCHING_STATE_ON_CMD1 2
386
387
388
389#define INCPTR(p) ptr_atomic_wrap_inc(&p)
390
391#define SLICE_TYPE_I 2
392#define SLICE_TYPE_P 5
393#define SLICE_TYPE_B 6
394
395struct buffer_spec_s {
396 /*
397 used:
398 -1, none allocated
399 0, allocated, free
400 1, used by dpb
401 2, in disp queue;
402 3, in disp queue, isolated,
403 do not use for dpb when vf_put;
404 4, to release
405 5, in disp queue, isolated (but not to release)
406 do not use for dpb when vf_put;
407 */
408 unsigned int used;
409 unsigned int info0;
410 unsigned int info1;
411 unsigned int info2;
412 unsigned int y_addr;
413 unsigned int u_addr;
414 unsigned int v_addr;
415
416 int y_canvas_index;
417 int u_canvas_index;
418 int v_canvas_index;
419
420#ifdef VDEC_DW
421 unsigned int vdec_dw_y_addr;
422 unsigned int vdec_dw_u_addr;
423 unsigned int vdec_dw_v_addr;
424
425 int vdec_dw_y_canvas_index;
426 int vdec_dw_u_canvas_index;
427 int vdec_dw_v_canvas_index;
428#ifdef NV21
429 struct canvas_config_s vdec_dw_canvas_config[2];
430#else
431 struct canvas_config_s vdec_dw_canvas_config[3];
432#endif
433#endif
434
435#ifdef NV21
436 struct canvas_config_s canvas_config[2];
437#else
438 struct canvas_config_s canvas_config[3];
439#endif
440 unsigned long cma_alloc_addr;
441 unsigned int buf_adr;
442#ifdef H264_MMU
443 unsigned long alloc_header_addr;
444#endif
445 char *aux_data_buf;
446 int aux_data_size;
447#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
448 unsigned char dv_enhance_exist;
449#endif
450 int canvas_pos;
451 int vf_ref;
452 /*unsigned int comp_body_size;*/
453 unsigned int dw_y_adr;
454 unsigned int dw_u_v_adr;
455};
456
457#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
458#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
459#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
460
461
462#define vdec_dw_spec2canvas(x) \
463 (((x)->vdec_dw_v_canvas_index << 16) | \
464 ((x)->vdec_dw_u_canvas_index << 8) | \
465 ((x)->vdec_dw_y_canvas_index << 0))
466
467
468#define spec2canvas(x) \
469 (((x)->v_canvas_index << 16) | \
470 ((x)->u_canvas_index << 8) | \
471 ((x)->y_canvas_index << 0))
472
473#define FRAME_INDEX(vf_index) (vf_index & 0xff)
474#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
475#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
476
477static struct vframe_s *vh264_vf_peek(void *);
478static struct vframe_s *vh264_vf_get(void *);
479static void vh264_vf_put(struct vframe_s *, void *);
480static int vh264_vf_states(struct vframe_states *states, void *);
481static int vh264_event_cb(int type, void *data, void *private_data);
482static void vh264_work(struct work_struct *work);
483static void vh264_timeout_work(struct work_struct *work);
484static void vh264_notify_work(struct work_struct *work);
485#ifdef MH264_USERDATA_ENABLE
486static void user_data_ready_notify_work(struct work_struct *work);
487static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
488#endif
489
490static const char vh264_dec_id[] = "vh264-dev";
491
492#define PROVIDER_NAME "vdec.h264"
493
494static const struct vframe_operations_s vf_provider_ops = {
495 .peek = vh264_vf_peek,
496 .get = vh264_vf_get,
497 .put = vh264_vf_put,
498 .event_cb = vh264_event_cb,
499 .vf_states = vh264_vf_states,
500};
501
502#define DEC_RESULT_NONE 0
503#define DEC_RESULT_DONE 1
504#define DEC_RESULT_AGAIN 2
505#define DEC_RESULT_CONFIG_PARAM 3
506#define DEC_RESULT_GET_DATA 4
507#define DEC_RESULT_GET_DATA_RETRY 5
508#define DEC_RESULT_ERROR 6
509#define DEC_RESULT_EOS 7
510#define DEC_RESULT_FORCE_EXIT 8
511
512/*
513 *static const char *dec_result_str[] = {
514 * "DEC_RESULT_NONE ",
515 * "DEC_RESULT_DONE ",
516 * "DEC_RESULT_AGAIN ",
517 * "DEC_RESULT_CONFIG_PARAM",
518 * "DEC_RESULT_GET_DATA ",
519 * "DEC_RESULT_GET_DA_RETRY",
520 * "DEC_RESULT_ERROR ",
521 *};
522 */
523
524#define UCODE_IP_ONLY 2
525#define UCODE_IP_ONLY_PARAM 1
526
527#define MC_OFFSET_HEADER 0x0000
528#define MC_OFFSET_DATA 0x1000
529#define MC_OFFSET_MMCO 0x2000
530#define MC_OFFSET_LIST 0x3000
531#define MC_OFFSET_SLICE 0x4000
532#define MC_OFFSET_MAIN 0x5000
533
534#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
535#define MC_SWAP_SIZE (4*SZ_1K)
536#define MODE_ERROR 0
537#define MODE_FULL 1
538
539#define DFS_HIGH_THEASHOLD 3
540
541#define INIT_FLAG_REG AV_SCRATCH_2
542#define HEAD_PADING_REG AV_SCRATCH_3
543#define UCODE_WATCHDOG_REG AV_SCRATCH_7
544#define LMEM_DUMP_ADR AV_SCRATCH_L
545#define DEBUG_REG1 AV_SCRATCH_M
546#define DEBUG_REG2 AV_SCRATCH_N
547#define FRAME_COUNTER_REG AV_SCRATCH_I
548#define RPM_CMD_REG AV_SCRATCH_A
549#define H264_DECODE_SIZE AV_SCRATCH_E
550#define H264_DECODE_MODE AV_SCRATCH_4
551#define H264_DECODE_SEQINFO AV_SCRATCH_5
552#define H264_AUX_ADR AV_SCRATCH_C
553#define H264_AUX_DATA_SIZE AV_SCRATCH_H
554
555#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
556#define DPB_STATUS_REG AV_SCRATCH_J
557#define ERROR_STATUS_REG AV_SCRATCH_9
558 /*
559 NAL_SEARCH_CTL: bit 0, enable itu_t35
560 NAL_SEARCH_CTL: bit 1, enable mmu
561 */
562#define NAL_SEARCH_CTL AV_SCRATCH_9
563#define MBY_MBX MB_MOTION_MODE /*0xc07*/
564
565#define DECODE_MODE_SINGLE 0x0
566#define DECODE_MODE_MULTI_FRAMEBASE 0x1
567#define DECODE_MODE_MULTI_STREAMBASE 0x2
568#define DECODE_MODE_MULTI_DVBAL 0x3
569#define DECODE_MODE_MULTI_DVENL 0x4
570static DEFINE_MUTEX(vmh264_mutex);
571
572
573
574#ifdef MH264_USERDATA_ENABLE
575
576struct mh264_userdata_record_t {
577 struct userdata_meta_info_t meta_info;
578 u32 rec_start;
579 u32 rec_len;
580};
581
582struct mh264_ud_record_wait_node_t {
583 struct list_head list;
584 struct mh264_userdata_record_t ud_record;
585};
586#define USERDATA_FIFO_NUM 256
587#define MAX_FREE_USERDATA_NODES 5
588
589struct mh264_userdata_info_t {
590 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
591 u8 *data_buf;
592 u8 *data_buf_end;
593 u32 buf_len;
594 u32 read_index;
595 u32 write_index;
596 u32 last_wp;
597};
598
599
600#endif
601
602struct vdec_h264_hw_s {
603 spinlock_t lock;
604 spinlock_t bufspec_lock;
605 int id;
606 struct platform_device *platform_dev;
607 unsigned long cma_alloc_addr;
608 /* struct page *collocate_cma_alloc_pages; */
609 unsigned long collocate_cma_alloc_addr;
610
611 u32 prefix_aux_size;
612 u32 suffix_aux_size;
613 void *aux_addr;
614 dma_addr_t aux_phy_addr;
615
616 /* buffer for store all sei data */
617 void *sei_data_buf;
618 u32 sei_data_len;
619
620 /* buffer for storing one itu35 recored */
621 void *sei_itu_data_buf;
622 u32 sei_itu_data_len;
623
624 /* recycle buffer for user data storing all itu35 records */
625 void *sei_user_data_buffer;
626 u32 sei_user_data_wp;
627#ifdef MH264_USERDATA_ENABLE
628 struct work_struct user_data_ready_work;
629#endif
630 struct StorablePicture *last_dec_picture;
631
632 ulong lmem_addr;
633 dma_addr_t lmem_addr_remap;
634
635 void *bmmu_box;
636#ifdef H264_MMU
637 void *mmu_box;
638 void *frame_mmu_map_addr;
639 dma_addr_t frame_mmu_map_phy_addr;
640 u32 hevc_cur_buf_idx;
641 u32 losless_comp_body_size;
642 u32 losless_comp_body_size_sao;
643 u32 losless_comp_header_size;
644 u32 mc_buffer_size_u_v;
645 u32 mc_buffer_size_u_v_h;
646 u32 is_idr_frame;
647 u32 is_new_pic;
648 u32 frame_done;
649 u32 frame_busy;
650 unsigned long extif_addr;
651 int double_write_mode;
652 int mmu_enable;
653#endif
654
655 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
656 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
657
658 int cur_pool;
659 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
660 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
661 struct vframe_s switching_fense_vf;
662 struct h264_dpb_stru dpb;
663 u8 init_flag;
664 u8 first_sc_checked;
665 u8 has_i_frame;
666 u8 config_bufmgr_done;
667 u32 max_reference_size;
668 u32 decode_pic_count;
669 u32 reflist_error_count;
670 int start_search_pos;
671 u32 reg_iqidct_control;
672 u32 reg_vcop_ctrl_reg;
673 u32 reg_rv_ai_mb_count;
674 u32 vld_dec_control;
675 struct vframe_s vframe_dummy;
676
677 unsigned char buffer_empty_flag;
678
679 u32 frame_width;
680 u32 frame_height;
681 u32 frame_dur;
682 u32 frame_prog;
683 u32 frame_packing_type;
684
685 struct vframe_chunk_s *chunk;
686
687 u32 stat;
688 unsigned long buf_start;
689 u32 buf_offset;
690 u32 buf_size;
691 /* u32 ucode_map_start; */
692 u32 pts_outside;
693 u32 sync_outside;
694 u32 vh264_ratio;
695 u32 vh264_rotation;
696 u32 use_idr_framerate;
697
698 u32 seq_info;
699 u32 seq_info2;
700 u32 video_signal_from_vui; /*to do .. */
701 u32 timing_info_present_flag;
702 u32 fixed_frame_rate_flag;
703 u32 bitstream_restriction_flag;
704 u32 num_reorder_frames;
705 u32 max_dec_frame_buffering;
706 u32 iframe_count;
707 u32 aspect_ratio_info;
708 u32 num_units_in_tick;
709 u32 time_scale;
710 u32 h264_ar;
711 bool h264_first_valid_pts_ready;
712 u32 h264pts1;
713 u32 h264pts2;
714 u32 pts_duration;
715 u32 h264_pts_count;
716 u32 duration_from_pts_done;
717 u32 pts_unstable;
718 u32 unstable_pts;
719 u32 last_checkout_pts;
720 u32 max_refer_buf;
721
722 s32 vh264_stream_switching_state;
723 struct vframe_s *p_last_vf;
724 u32 last_pts;
725 u32 last_pts_remainder;
726 u32 last_duration;
727 u32 last_mb_width, last_mb_height;
728 bool check_pts_discontinue;
729 bool pts_discontinue;
730 u32 wait_buffer_counter;
731 u32 first_offset;
732 u32 first_pts;
733 u64 first_pts64;
734 bool first_pts_cached;
735 u64 last_pts64;
736#if 0
737 void *sei_data_buffer;
738 dma_addr_t sei_data_buffer_phys;
739#endif
740
741 uint error_recovery_mode;
742 uint mb_total;
743 uint mb_width;
744 uint mb_height;
745
746 uint i_only;
747 int skip_frame_count;
748 bool no_poc_reorder_flag;
749 bool send_error_frame_flag;
750 dma_addr_t mc_dma_handle;
751 void *mc_cpu_addr;
752 int vh264_reset;
753
754 atomic_t vh264_active;
755
756 struct dec_sysinfo vh264_amstream_dec_info;
757
758 int dec_result;
759 struct work_struct work;
760 struct work_struct notify_work;
761 struct work_struct timeout_work;
762 void (*vdec_cb)(struct vdec_s *, void *);
763 void *vdec_cb_arg;
764
765 struct timer_list check_timer;
766
767 /**/
768 unsigned int last_frame_time;
769 u32 vf_pre_count;
770 u32 vf_get_count;
771 u32 vf_put_count;
772
773 /* timeout handle */
774 unsigned long int start_process_time;
775 unsigned int last_mby_mbx;
776 unsigned int last_vld_level;
777 unsigned int decode_timeout_count;
778 unsigned int timeout_num;
779 unsigned int search_dataempty_num;
780 unsigned int decode_timeout_num;
781 unsigned int decode_dataempty_num;
782 unsigned int buffer_empty_recover_num;
783
784 unsigned get_data_count;
785 unsigned get_data_start_time;
786 /**/
787
788 /*log*/
789 unsigned int packet_write_success_count;
790 unsigned int packet_write_EAGAIN_count;
791 unsigned int packet_write_ENOMEM_count;
792 unsigned int packet_write_EFAULT_count;
793 unsigned int total_read_size_pre;
794 unsigned int total_read_size;
795 unsigned int frame_count_pre;
796#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
797 u8 switch_dvlayer_flag;
798 u8 got_valid_nal;
799#endif
800 u8 eos;
801 u8 data_flag;
802 u32 no_error_count;
803 u32 no_error_i_count;
804 /*
805 NODISP_FLAG
806 */
807 u8 dec_flag;
808
809 u32 ucode_pause_pos;
810
811 u8 reset_bufmgr_flag;
812 u32 reset_bufmgr_count;
813 u32 cfg_param1;
814 u32 cfg_param2;
815 u32 cfg_param3;
816 u32 cfg_param4;
817 int valve_count;
818 u8 next_again_flag;
819 u32 pre_parser_wr_ptr;
820 struct firmware_s *fw;
821 struct firmware_s *fw_mmu;
822#ifdef MH264_USERDATA_ENABLE
823 /*user data*/
824 struct mutex userdata_mutex;
825 struct mh264_userdata_info_t userdata_info;
826 struct mh264_userdata_record_t ud_record;
827 int wait_for_udr_send;
828#endif
829 u32 no_mem_count;
830 u32 canvas_mode;
831 bool is_used_v4l;
832 void *v4l2_ctx;
833 bool v4l_params_parsed;
834 wait_queue_head_t wait_q;
835 u32 reg_g_status;
836 struct mutex chunks_mutex;
837 int need_cache_size;
838 u64 sc_start_time;
839 u8 frmbase_cont_flag;
840 struct vframe_qos_s vframe_qos;
841 int frameinfo_enable;
842 bool first_head_check_flag;
843 unsigned int height_aspect_ratio;
844 unsigned int width_aspect_ratio;
845 bool new_iframe_flag;
846 bool ref_err_flush_dpb_flag;
847 unsigned int first_i_policy;
848};
849
850static u32 again_threshold;
851
852static void timeout_process(struct vdec_h264_hw_s *hw);
853static void dump_bufspec(struct vdec_h264_hw_s *hw,
854 const char *caller);
855static void h264_reconfig(struct vdec_h264_hw_s *hw);
856static void h264_reset_bufmgr(struct vdec_s *vdec);
857static void vh264_local_init(struct vdec_h264_hw_s *hw);
858static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
859static int vh264_stop(struct vdec_h264_hw_s *hw);
860static s32 vh264_init(struct vdec_h264_hw_s *hw);
861static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
862 u32 index);
863static void release_aux_data(struct vdec_h264_hw_s *hw,
864 int buf_spec_num);
865#ifdef ERROR_HANDLE_TEST
866static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
867#endif
868
869#define H265_PUT_SAO_4K_SET 0x03
870#define H265_ABORT_SAO_4K_SET 0x04
871#define H265_ABORT_SAO_4K_SET_DONE 0x05
872
873#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
874#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
875#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
876#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
877#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
878
879
880#define HEVC_CM_HEADER_START_ADDR 0x3628
881#define HEVC_CM_BODY_START_ADDR 0x3626
882#define HEVC_CM_BODY_LENGTH 0x3627
883#define HEVC_CM_HEADER_LENGTH 0x3629
884#define HEVC_CM_HEADER_OFFSET 0x362b
885#define HEVC_SAO_CTRL9 0x362d
886#define HEVCD_MPP_DECOMP_CTL3 0x34c4
887#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
888#define HEVC_DBLK_CFGB 0x350b
889#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
890
891#define H265_DW_NO_SCALE
892#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
893#define H265_LOSLESS_COMPRESS_MODE
894#define MAX_FRAME_4K_NUM 0x1200
895#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
896
897/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
898static u32 mem_map_mode = H265_MEM_MAP_MODE;
899
900#define MAX_SIZE_8K (8192 * 4608)
901#define MAX_SIZE_4K (4096 * 2304)
902
903static int is_oversize(int w, int h)
904{
905 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
906 MAX_SIZE_8K : MAX_SIZE_4K;
907
908 if (w < 0 || h < 0)
909 return true;
910
911 if (h != 0 && (w > max / h))
912 return true;
913
914 return false;
915}
916
917static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
918 int frame_type,
919 u32 vpts,
920 u32 vpts_valid);
921static int compute_losless_comp_body_size(int width,
922 int height, int bit_depth_10);
923static int compute_losless_comp_header_size(int width, int height);
924
925static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
926 int pic_width, int pic_height, u16 bit_depth,
927 unsigned int *mmu_index_adr) {
928 int cur_buf_idx;
929 int bit_depth_10 = (bit_depth != 0x00);
930 int picture_size;
931 u32 cur_mmu_4k_number;
932
933 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
934 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
935 picture_size = compute_losless_comp_body_size(pic_width,
936 pic_height, bit_depth_10);
937 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
938 dpb_print(DECODE_ID(hw),
939 PRINT_FLAG_MMU_DETAIL,
940 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
941 cur_buf_idx, picture_size, cur_mmu_4k_number);
942
943 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
944 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
945 cur_mmu_4k_number);
946 return -1;
947 }
948
949 return decoder_mmu_box_alloc_idx(
950 hw->mmu_box,
951 cur_buf_idx,
952 cur_mmu_4k_number,
953 mmu_index_adr);
954
955}
956
957static int compute_losless_comp_body_size(int width,
958 int height, int bit_depth_10)
959{
960 int width_x64;
961 int height_x32;
962 int bsize;
963
964 width_x64 = width + 63;
965 width_x64 >>= 6;
966
967 height_x32 = height + 31;
968 height_x32 >>= 5;
969
970#ifdef H264_MMU
971 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
972#else
973 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
974#endif
975 return bsize;
976}
977
978static int compute_losless_comp_header_size(int width, int height)
979{
980 int width_x64;
981 int width_x128;
982 int height_x64;
983 int hsize;
984
985 width_x64 = width + 63;
986 width_x64 >>= 6;
987
988 width_x128 = width + 127;
989 width_x128 >>= 7;
990
991 height_x64 = height + 63;
992 height_x64 >>= 6;
993
994#ifdef H264_MMU
995 hsize = 128*width_x64*height_x64;
996#else
997 hsize = 32*width_x128*height_x64;
998#endif
999 return hsize;
1000}
1001
1002static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1003{
1004 int ratio = 1;
1005 int dw_mode = hw->double_write_mode;
1006 if ((dw_mode == 2) ||
1007 (dw_mode == 3))
1008 ratio = 4;
1009 else if (dw_mode == 4)
1010 ratio = 2;
1011 return ratio;
1012}
1013
1014
1015static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1016{
1017 int pic_width, pic_height;
1018 int lcu_size = 16;
1019 int dw_buf_size;
1020 u32 dw_buffer_size_u_v;
1021 u32 dw_buffer_size_u_v_h;
1022 int dw_mode = hw->double_write_mode;
1023
1024 pic_width = hw->frame_width;
1025 pic_height = hw->frame_height;
1026
1027 if (dw_mode) {
1028 int pic_width_dw = pic_width /
1029 get_double_write_ratio(hw);
1030 int pic_height_dw = pic_height /
1031 get_double_write_ratio(hw);
1032
1033 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1034 pic_width_dw / lcu_size + 1 :
1035 pic_width_dw / lcu_size;
1036 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1037 pic_height_dw / lcu_size + 1 :
1038 pic_height_dw / lcu_size;
1039 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1040
1041
1042 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1043 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1044 /*64k alignment*/
1045 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1046 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1047 } else {
1048 *pdw_buffer_size_u_v_h = 0;
1049 dw_buf_size = 0;
1050 }
1051
1052 return dw_buf_size;
1053}
1054
1055
1056static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1057{
1058 int i, size;
1059 u32 canvas_addr;
1060 unsigned long maddr;
1061 int num_buff = hw->dpb.mDPB.size;
1062 int dw_size = 0;
1063 u32 dw_buffer_size_u_v_h;
1064 u32 blkmode = mem_map_mode;
1065 int dw_mode = hw->double_write_mode;
1066
1067 canvas_addr = ANC0_CANVAS_ADDR;
1068 for (i = 0; i < num_buff; i++)
1069 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1070
1071 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1072 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1073
1074
1075 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1076 size += dw_size;
1077 if (size > 0)
1078 size += 0x10000;
1079
1080 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1081 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1082 dw_buffer_size_u_v_h, dw_size, size);
1083
1084 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1085 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1086 hw->losless_comp_body_size,
1087 hw->losless_comp_header_size,
1088 hw->losless_comp_body_size_sao);
1089
1090 for (i = 0; i < num_buff; i++) {
1091 if (!restore) {
1092 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1093 HEADER_BUFFER_IDX(i), size,
1094 DRIVER_HEADER_NAME, &maddr) < 0) {
1095 dpb_print(DECODE_ID(hw), 0,
1096 "%s malloc compress header failed %d\n",
1097 DRIVER_HEADER_NAME, i);
1098 return;
1099 }
1100 } else
1101 maddr = hw->buffer_spec[i].alloc_header_addr;
1102 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1103 hw->buffer_spec[i].alloc_header_addr = maddr;
1104 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1105 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1106 __func__, i, (u32)maddr, size);
1107
1108 if (dw_mode) {
1109 u32 addr;
1110 int canvas_w;
1111 int canvas_h;
1112
1113 canvas_w = hw->frame_width /
1114 get_double_write_ratio(hw);
1115 canvas_h = hw->frame_height /
1116 get_double_write_ratio(hw);
1117
1118 if (mem_map_mode == 0)
1119 canvas_w = ALIGN(canvas_w, 32);
1120 else
1121 canvas_w = ALIGN(canvas_w, 64);
1122 canvas_h = ALIGN(canvas_h, 32);
1123
1124 hw->buffer_spec[i].dw_y_adr =
1125 maddr + hw->losless_comp_header_size;
1126
1127 hw->buffer_spec[i].dw_y_adr =
1128 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1129 << 16;
1130 hw->buffer_spec[i].dw_u_v_adr =
1131 hw->buffer_spec[i].dw_y_adr
1132 + (dw_buffer_size_u_v_h << 16) * 2;
1133
1134
1135 hw->buffer_spec[i].buf_adr
1136 = hw->buffer_spec[i].dw_y_adr;
1137 addr = hw->buffer_spec[i].buf_adr;
1138
1139
1140 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1141 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1142 hw->buffer_spec[i].dw_y_adr,
1143 hw->buffer_spec[i].dw_u_v_adr,
1144 hw->buffer_spec[i].y_addr,
1145 hw->buffer_spec[i].u_addr,
1146 hw->buffer_spec[i].v_addr,
1147 canvas_w,
1148 canvas_h);
1149
1150 hw->buffer_spec[i].canvas_config[0].phy_addr =
1151 hw->buffer_spec[i].dw_y_adr;
1152 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1153 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1154 hw->buffer_spec[i].canvas_config[0].block_mode =
1155 blkmode;
1156 hw->buffer_spec[i].canvas_config[0].endian = 7;
1157
1158 hw->buffer_spec[i].canvas_config[1].phy_addr =
1159 hw->buffer_spec[i].dw_u_v_adr;
1160 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1161 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1162 hw->buffer_spec[i].canvas_config[1].block_mode =
1163 blkmode;
1164 hw->buffer_spec[i].canvas_config[1].endian = 7;
1165 }
1166 }
1167 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1168
1169 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1170 for (i = 0; i < 32; i++)
1171 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1172 return;
1173}
1174static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1175{
1176 u32 i;
1177 u32 ref_canv;
1178 struct Slice *pSlice = &(hw->dpb.mSlice);
1179 /*REFLIST[0]*/
1180 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1181 struct StorablePicture *ref = pSlice->listX[0][i];
1182 if (ref == NULL)
1183 return;
1184 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1185 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1186 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1187 (ref->buf_spec_num & 0x3f) << 8);
1188 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1189 }
1190 /*REFLIST[1]*/
1191 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1192 struct StorablePicture *ref = pSlice->listX[1][i];
1193 if (ref == NULL)
1194 return;
1195 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1196 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1197 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1198 (ref->buf_spec_num & 0x3f) << 8);
1199 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1200 }
1201 return;
1202}
1203
1204static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1205{
1206 u32 rdata32;
1207 u32 rdata32_2;
1208 u32 slice_type;
1209 struct StorablePicture *ref;
1210 struct Slice *pSlice;
1211 slice_type = hw->dpb.mSlice.slice_type;
1212 pSlice = &(hw->dpb.mSlice);
1213 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1214 if (slice_type == I_SLICE) {
1215 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1216 return;
1217 }
1218 if (slice_type == B_SLICE) {
1219 ref = pSlice->listX[0][0];
1220 if (ref == NULL)
1221 return;
1222 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1223 ((ref->buf_spec_num & 0x3f) << 8));
1224 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1225 rdata32 = rdata32 & 0xffff;
1226 rdata32 = rdata32 | (rdata32 << 16);
1227 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1228
1229 ref = pSlice->listX[1][0];
1230 if (ref == NULL)
1231 return;
1232 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1233 ((ref->buf_spec_num & 0x3f) << 8));
1234 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1235 rdata32_2 = rdata32_2 & 0xffff;
1236 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1237 if (rdata32 == rdata32_2) {
1238 ref = pSlice->listX[1][1];
1239 if (ref == NULL)
1240 return;
1241 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1242 ((ref->buf_spec_num & 0x3f) << 8));
1243 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1244 rdata32_2 = rdata32_2 & 0xffff;
1245 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1246 }
1247 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1248 } else { /*P-PIC*/
1249 ref = pSlice->listX[0][0];
1250 if (ref == NULL)
1251 return;
1252 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1253 ((ref->buf_spec_num & 0x3f) << 8));
1254 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1255 rdata32 = rdata32 & 0xffff;
1256 rdata32 = rdata32 | (rdata32 << 16);
1257 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1258
1259 ref = pSlice->listX[0][1];
1260 if (ref == NULL)
1261 return;
1262 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1263 ((ref->buf_spec_num & 0x3f) << 8));
1264 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1265 rdata32 = rdata32 & 0xffff;
1266 rdata32 = rdata32 | (rdata32 << 16);
1267 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1268 }
1269 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1270 return;
1271}
1272
1273
1274static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1275 u32 width, u32 height) {
1276 u32 data32;
1277 u32 lcu_x_num, lcu_y_num;
1278 u32 lcu_total;
1279 u32 mc_buffer_size_u_v;
1280 u32 mc_buffer_size_u_v_h;
1281 int dw_mode = hw->double_write_mode;
1282
1283 lcu_x_num = (width + 15) >> 4;
1284 lcu_y_num = (height + 15) >> 4;
1285 lcu_total = lcu_x_num * lcu_y_num;
1286
1287 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1288 hw->mc_buffer_size_u_v_h =
1289 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1290
1291 hw->losless_comp_body_size = 0;
1292
1293 hw->losless_comp_body_size_sao =
1294 compute_losless_comp_body_size(width, height, 0);
1295 hw->losless_comp_header_size =
1296 compute_losless_comp_header_size(width, height);
1297
1298 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1299 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1300
1301 /* setup lcu_size = 16*/
1302 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1303 /*pic_width/pic_height*/
1304 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1305 (height & 0xffff) << 16 | (width & 0xffff));
1306 /* bitdepth_luma = 8*/
1307 /* bitdepth_chroma = 8*/
1308 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1309
1310#ifdef H265_LOSLESS_COMPRESS_MODE
1311 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1312 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1313#else
1314 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1315#endif
1316 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1317 data32 &= (~0x30);
1318 data32 |= (mem_map_mode << 4);
1319 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1320
1321 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1322 (0x80 << 20) | (0x80 << 10) | (0xff));
1323
1324 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1325
1326 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1327 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1328 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1329 /* ipp_enable*/
1330 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1331
1332 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1333 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1334 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1335 if (dw_mode)
1336 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1337 else
1338 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1339 }
1340
1341 data32 = READ_VREG(HEVC_SAO_CTRL0);
1342 data32 &= (~0xf);
1343 data32 |= 0x4;
1344 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1345 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1346 (width & 0xffff));
1347 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1348
1349 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1350 data32 = (lcu_x_num | lcu_y_num << 16);
1351 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1352 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1353 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1354 data32 = (mc_buffer_size_u_v_h << 16);
1355 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1356
1357 data32 = READ_VREG(HEVC_SAO_CTRL1);
1358 data32 &= (~0x3000);
1359 data32 &= (~0xff0);
1360 data32 |= endian; /* Big-Endian per 64-bit */
1361
1362 if (hw->mmu_enable && dw_mode)
1363 data32 |= ((mem_map_mode << 12));
1364 else
1365 data32 |= ((mem_map_mode << 12)|2);
1366
1367 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1368
1369#ifdef H265_DW_NO_SCALE
1370 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1371 if (hw->mmu_enable && dw_mode) {
1372 data32 = READ_VREG(HEVC_SAO_CTRL5);
1373 data32 &= (~(0xff << 16));
1374 if (dw_mode == 2 ||
1375 dw_mode == 3)
1376 data32 |= (0xff<<16);
1377 else if (dw_mode == 4)
1378 data32 |= (0x33<<16);
1379 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1380 }
1381
1382
1383#endif
1384
1385
1386#ifdef H265_LOSLESS_COMPRESS_MODE
1387 data32 = READ_VREG(HEVC_SAO_CTRL5);
1388 data32 |= (1<<9); /*8-bit smem-mode*/
1389 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1390
1391 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1392 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1393 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1394#endif
1395
1396#ifdef H265_LOSLESS_COMPRESS_MODE
1397 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1398 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1399#endif
1400
1401 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1402
1403 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1404
1405 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1406 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1407 return;
1408}
1409
1410static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1411 u32 is_new_pic, u32 is_idr)
1412{
1413 hw->is_new_pic = is_new_pic;
1414 hw->is_idr_frame = is_idr;
1415 return;
1416}
1417
1418static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1419 struct StorablePicture *pic) {
1420 u32 mc_y_adr;
1421 u32 mc_u_v_adr;
1422 u32 dw_y_adr;
1423 u32 dw_u_v_adr;
1424 u32 canvas_addr;
1425 int ret;
1426 int dw_mode = hw->double_write_mode;
1427 if (hw->is_new_pic != 1)
1428 return;
1429
1430 if (hw->is_idr_frame) {
1431 /* William TBD */
1432 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1433 }
1434
1435 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1436 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1437 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1438 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1439 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1440 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1441 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1442 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1443 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1444
1445
1446 if (dw_mode) {
1447 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1448 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1449 } else {
1450 dw_y_adr = 0;
1451 dw_u_v_adr = 0;
1452 }
1453#ifdef H265_LOSLESS_COMPRESS_MODE
1454 if (dw_mode)
1455 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1456 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1457#ifdef H264_MMU
1458 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1459#else
1460 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1461 (mc_y_adr + hw->losless_comp_body_size));
1462#endif
1463#else
1464 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1465#endif
1466
1467#ifndef H265_LOSLESS_COMPRESS_MODE
1468 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1469#else
1470 if (dw_mode)
1471 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1472#endif
1473
1474#ifndef LOSLESS_COMPRESS_MODE
1475 if (dw_mode) {
1476 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1477 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1478 }
1479#else
1480 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1481 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1482#endif
1483
1484 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1485 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1486 hw->frame_mmu_map_addr);
1487 if (ret != 0) {
1488 dpb_print(DECODE_ID(hw),
1489 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1490 pic->buf_spec_num,
1491 ret);
1492 return;
1493 }
1494
1495 /*Reset SAO + Enable SAO slice_start*/
1496 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1497 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1498 WRITE_VREG(HEVC_SAO_INT_STATUS,
1499 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1500 WRITE_VREG(HEVC_SAO_INT_STATUS,
1501 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1502 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1503 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1504
1505 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1506 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1507 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1508 } else
1509 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1510 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1511 hw->frame_busy = 1;
1512 return;
1513}
1514
1515
1516static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1517 u32 buf_spec_num) {
1518 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1519 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1520 dpb_print(DECODE_ID(hw),
1521 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1522 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1523 return;
1524}
1525
1526
1527static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1528{
1529 ulong timeout = jiffies + HZ;
1530 dpb_print(DECODE_ID(hw),
1531 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1532 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1533 if (time_after(jiffies, timeout)) {
1534 dpb_print(DECODE_ID(hw),
1535 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1536 break;
1537 }
1538 }
1539 timeout = jiffies + HZ;
1540 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1541 if (time_after(jiffies, timeout)) {
1542 dpb_print(DECODE_ID(hw),
1543 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1544 break;
1545 }
1546 }
1547 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1548 hw->frame_done = 1;
1549 return;
1550}
1551
1552static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1553{
1554 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1555 if (p_H264_Dpb->mVideo.dec_picture) {
1556 release_picture(p_H264_Dpb,
1557 p_H264_Dpb->mVideo.dec_picture);
1558 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1559 p_H264_Dpb->mVideo.dec_picture = NULL;
1560 if (hw->mmu_enable)
1561 hevc_set_frame_done(hw);
1562 }
1563}
1564
1565static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1566{
1567 ulong timeout = jiffies + HZ;
1568 dpb_print(DECODE_ID(hw),
1569 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1570 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1571 if (time_after(jiffies, timeout)) {
1572 dpb_print(DECODE_ID(hw),
1573 PRINT_FLAG_MMU_DETAIL,
1574 "hevc_sao_wait_done...wait timeout!\n");
1575 break;
1576 }
1577 }
1578 timeout = jiffies + HZ;
1579 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1580 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1581 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1582 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1583 H265_ABORT_SAO_4K_SET_DONE) {
1584 if (time_after(jiffies, timeout)) {
1585 dpb_print(DECODE_ID(hw),
1586 PRINT_FLAG_MMU_DETAIL,
1587 "wait h265_abort_sao_4k_set_done timeout!\n");
1588 break;
1589 }
1590 }
1591 }
1592 amhevc_stop();
1593 hw->frame_busy = 0;
1594 hw->frame_done = 0;
1595 dpb_print(DECODE_ID(hw),
1596 PRINT_FLAG_MMU_DETAIL,
1597 "sao wait done ,hevc stop!\n");
1598 }
1599 return;
1600}
1601static void buf_spec_init(struct vdec_h264_hw_s *hw)
1602{
1603 int i;
1604 unsigned long flags;
1605 spin_lock_irqsave(&hw->bufspec_lock, flags);
1606 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1607 hw->buffer_spec[i].used = -1;
1608 hw->buffer_spec[i].canvas_pos = -1;
1609 }
1610 if (dpb_is_debug(DECODE_ID(hw),
1611 PRINT_FLAG_DUMP_BUFSPEC))
1612 dump_bufspec(hw, __func__);
1613 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1614}
1615
1616/*is active in buf management */
1617static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1618 int buf_spec_num)
1619{
1620 unsigned char ret = 0;
1621 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1622 hw->buffer_spec[buf_spec_num].used == 2 ||
1623 hw->buffer_spec[buf_spec_num].used == 3 ||
1624 hw->buffer_spec[buf_spec_num].used == 5)
1625 ret = 1;
1626 return ret;
1627}
1628
1629static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1630 int buf_spec_num)
1631{
1632 unsigned char ret = 0;
1633 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1634 hw->buffer_spec[buf_spec_num].used == 3 ||
1635 hw->buffer_spec[buf_spec_num].used == 5)
1636 ret = 1;
1637 return ret;
1638}
1639
1640static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1641{
1642 if (hw->mmu_enable) {
1643 if (hw->buffer_spec[i].alloc_header_addr)
1644 return 0;
1645 else
1646 return -1;
1647 } else {
1648
1649 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1650 int addr;
1651#ifdef VDEC_DW
1652 int orig_buf_size;
1653 orig_buf_size = buf_size;
1654 if (IS_VDEC_DW(hw) == 1)
1655 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1656 else if (IS_VDEC_DW(hw) == 2)
1657 buf_size += (hw->mb_total << 6) + (hw->mb_total << 6);
1658#endif
1659 if (hw->buffer_spec[i].cma_alloc_addr)
1660 return 0;
1661
1662 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1663 PAGE_ALIGN(buf_size), DRIVER_NAME,
1664 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1665 hw->buffer_spec[i].cma_alloc_addr = 0;
1666 if (hw->no_mem_count++ > 3) {
1667 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1668 hw->reset_bufmgr_flag = 1;
1669 }
1670 dpb_print(DECODE_ID(hw), 0,
1671 "%s, fail to alloc buf for bufspec%d, try later\n",
1672 __func__, i
1673 );
1674 return -1;
1675 } else {
1676 hw->no_mem_count = 0;
1677 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1678 }
1679
1680 hw->buffer_spec[i].buf_adr =
1681 hw->buffer_spec[i].cma_alloc_addr;
1682 addr = hw->buffer_spec[i].buf_adr;
1683
1684
1685 hw->buffer_spec[i].y_addr = addr;
1686 addr += hw->mb_total << 8;
1687 hw->buffer_spec[i].u_addr = addr;
1688 hw->buffer_spec[i].v_addr = addr;
1689 addr += hw->mb_total << 7;
1690
1691 hw->buffer_spec[i].canvas_config[0].phy_addr =
1692 hw->buffer_spec[i].y_addr;
1693 hw->buffer_spec[i].canvas_config[0].width =
1694 hw->mb_width << 4;
1695 hw->buffer_spec[i].canvas_config[0].height =
1696 hw->mb_height << 4;
1697 hw->buffer_spec[i].canvas_config[0].block_mode =
1698 hw->canvas_mode;
1699
1700 hw->buffer_spec[i].canvas_config[1].phy_addr =
1701 hw->buffer_spec[i].u_addr;
1702 hw->buffer_spec[i].canvas_config[1].width =
1703 hw->mb_width << 4;
1704 hw->buffer_spec[i].canvas_config[1].height =
1705 hw->mb_height << 3;
1706 hw->buffer_spec[i].canvas_config[1].block_mode =
1707 hw->canvas_mode;
1708 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1709 "%s, alloc buf for bufspec%d\n",
1710 __func__, i
1711 );
1712#ifdef VDEC_DW
1713
1714 if (!IS_VDEC_DW(hw))
1715 return 0;
1716 else if (IS_VDEC_DW(hw) == 1) {
1717 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1718 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1719 addr += hw->mb_total << 7;
1720 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1721 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1722 addr += hw->mb_total << 6;
1723
1724 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1725 hw->buffer_spec[i].vdec_dw_y_addr;
1726 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1727 hw->mb_width << 3;
1728 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1729 hw->mb_height << 4;
1730 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1731 CANVAS_BLKMODE_32X32;
1732
1733 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1734 hw->buffer_spec[i].vdec_dw_u_addr;
1735 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1736 hw->mb_width << 3;
1737 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1738 hw->mb_height << 3;
1739 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1740 CANVAS_BLKMODE_32X32;
1741 }else {
1742 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1743 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1744 addr += hw->mb_total << 6;
1745 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1746 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1747 addr += hw->mb_total << 5;
1748
1749 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1750 hw->buffer_spec[i].vdec_dw_y_addr;
1751 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1752 hw->mb_width << 3;
1753 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1754 hw->mb_height << 3;
1755 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1756 CANVAS_BLKMODE_32X32;
1757
1758 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1759 hw->buffer_spec[i].vdec_dw_u_addr;
1760 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1761 hw->mb_width << 3;
1762 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1763 hw->mb_height << 2;
1764 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1765 CANVAS_BLKMODE_32X32;
1766 }
1767 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1768 "%s, vdec_dw: alloc buf for bufspec%d\n",
1769 __func__, i
1770 );
1771#endif
1772 }
1773 return 0;
1774}
1775
1776static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1777{
1778 int ret = 0;
1779 struct aml_vcodec_ctx *ctx = NULL;
1780 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1781 struct canvas_config_s *y_canvas_cfg = NULL;
1782 struct canvas_config_s *c_canvas_cfg = NULL;
1783 struct vdec_v4l2_buffer *fb = NULL;
1784 unsigned int y_addr = 0, c_addr = 0;
1785
1786 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1787 pr_err("the v4l context has err.\n");
1788 return -1;
1789 }
1790
1791 if (bs->cma_alloc_addr)
1792 return 0;
1793
1794 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1795 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1796 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1797 ctx->id, __func__,
1798 (hw->mb_total << 8) + (hw->mb_total << 7));
1799
1800 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1801 if (ret) {
1802 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1803 "[%d] get fb fail.\n", ctx->id);
1804 return ret;
1805 }
1806
1807 bs->cma_alloc_addr = (unsigned long)fb;
1808 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1809 "[%d] %s(), cma alloc addr: 0x%x\n",
1810 ctx->id, __func__, bs->cma_alloc_addr);
1811
1812 if (fb->num_planes == 1) {
1813 y_addr = fb->m.mem[0].addr;
1814 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1815 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1816 } else if (fb->num_planes == 2) {
1817 y_addr = fb->m.mem[0].addr;
1818 c_addr = fb->m.mem[1].addr;
1819 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1820 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1821 }
1822
1823 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1824 "[%d] %s(), y_addr: %x, size: %u\n",
1825 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1826 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1827 "[%d] %s(), c_addr: %x, size: %u\n",
1828 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1829
1830 bs->y_addr = y_addr;
1831 bs->u_addr = c_addr;
1832 bs->v_addr = c_addr;
1833
1834 y_canvas_cfg = &bs->canvas_config[0];
1835 c_canvas_cfg = &bs->canvas_config[1];
1836
1837 y_canvas_cfg->phy_addr = y_addr;
1838 y_canvas_cfg->width = hw->mb_width << 4;
1839 y_canvas_cfg->height = hw->mb_height << 4;
1840 y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1841 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1842 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1843 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1844 y_canvas_cfg->width,y_canvas_cfg->height);
1845
1846 c_canvas_cfg->phy_addr = c_addr;
1847 c_canvas_cfg->width = hw->mb_width << 4;
1848 c_canvas_cfg->height = hw->mb_height << 3;
1849 c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1850 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1851 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1852 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1853 c_canvas_cfg->width, c_canvas_cfg->height);
1854
1855 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1856 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1857
1858 return ret;
1859}
1860
1861static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1862{
1863 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
1864 int blkmode = CANVAS_BLKMODE_32X32;
1865 int endian = 0;
1866
1867 if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
1868 blkmode = CANVAS_BLKMODE_LINEAR;
1869 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1870 endian = 7;
1871 else
1872 endian = 0;
1873 }
1874
1875 if (hw->is_used_v4l) {
1876 blkmode = CANVAS_BLKMODE_LINEAR;
1877 if (v4l2_ctx->ada_ctx->vfm_path
1878 != FRAME_BASE_PATH_V4L_VIDEO)
1879 endian = 7;
1880 }
1881
1882 canvas_config_ex(hw->buffer_spec[i].
1883 y_canvas_index,
1884 hw->buffer_spec[i].y_addr,
1885 hw->mb_width << 4,
1886 hw->mb_height << 4,
1887 CANVAS_ADDR_NOWRAP,
1888 blkmode,
1889 endian);
1890
1891 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1892 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1893 (1 << 11) | /* canvas_blk32_wr */
1894 (blkmode << 10) | /* canvas_blk32*/
1895 (1 << 8) | /* canvas_index_wr*/
1896 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1897 );
1898 }
1899
1900 canvas_config_ex(hw->buffer_spec[i].
1901 u_canvas_index,
1902 hw->buffer_spec[i].u_addr,
1903 hw->mb_width << 4,
1904 hw->mb_height << 3,
1905 CANVAS_ADDR_NOWRAP,
1906 blkmode,
1907 endian);
1908
1909 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1910 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1911 (1 << 11) |
1912 (blkmode << 10) |
1913 (1 << 8) |
1914 (hw->buffer_spec[i].u_canvas_index << 0));
1915 }
1916
1917 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1918 spec2canvas(&hw->buffer_spec[i]));
1919
1920
1921#ifdef VDEC_DW
1922 if (!IS_VDEC_DW(hw))
1923 return;
1924 else if (IS_VDEC_DW(hw) == 1) {
1925 canvas_config_ex(hw->buffer_spec[i].
1926 vdec_dw_y_canvas_index,
1927 hw->buffer_spec[i].vdec_dw_y_addr,
1928 hw->mb_width << 3,
1929 hw->mb_height << 4,
1930 CANVAS_ADDR_NOWRAP,
1931 blkmode,
1932 endian);
1933 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1934 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1935 (1 << 11) |
1936 (blkmode << 10) |
1937 (1 << 8) |
1938 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1939 }
1940 canvas_config_ex(hw->buffer_spec[i].
1941 vdec_dw_u_canvas_index,
1942 hw->buffer_spec[i].vdec_dw_u_addr,
1943 hw->mb_width << 3,
1944 hw->mb_height << 3,
1945 CANVAS_ADDR_NOWRAP,
1946 blkmode,
1947 endian);
1948 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1949 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1950 (1 << 11) |
1951 (blkmode << 10) |
1952 (1 << 8) |
1953 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1954 }
1955 } else {
1956 canvas_config_ex(hw->buffer_spec[i].
1957 vdec_dw_y_canvas_index,
1958 hw->buffer_spec[i].vdec_dw_y_addr,
1959 hw->mb_width << 3,
1960 hw->mb_height << 3,
1961 CANVAS_ADDR_NOWRAP,
1962 blkmode,
1963 endian);
1964 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1965 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1966 (1 << 11) |
1967 (blkmode << 10) |
1968 (1 << 8) |
1969 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1970 }
1971
1972 canvas_config_ex(hw->buffer_spec[i].
1973 vdec_dw_u_canvas_index,
1974 hw->buffer_spec[i].vdec_dw_u_addr,
1975 hw->mb_width << 3,
1976 hw->mb_height << 2,
1977 CANVAS_ADDR_NOWRAP,
1978 blkmode,
1979 endian);
1980 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1981 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1982 (1 << 11) |
1983 (blkmode << 10) |
1984 (1 << 8) |
1985 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1986 }
1987 }
1988#endif
1989}
1990
1991static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1992{
1993 u32 blkmode = mem_map_mode;
1994 int canvas_w;
1995 int canvas_h;
1996
1997 canvas_w = hw->frame_width /
1998 get_double_write_ratio(hw);
1999 canvas_h = hw->frame_height /
2000 get_double_write_ratio(hw);
2001
2002 if (mem_map_mode == 0)
2003 canvas_w = ALIGN(canvas_w, 32);
2004 else
2005 canvas_w = ALIGN(canvas_w, 64);
2006 canvas_h = ALIGN(canvas_h, 32);
2007
2008 canvas_config_ex(hw->buffer_spec[i].
2009 y_canvas_index,
2010 hw->buffer_spec[i].dw_y_adr,
2011 canvas_w,
2012 canvas_h,
2013 CANVAS_ADDR_NOWRAP,
2014 blkmode,
2015 7);
2016
2017 canvas_config_ex(hw->buffer_spec[i].
2018 u_canvas_index,
2019 hw->buffer_spec[i].dw_u_v_adr,
2020 canvas_w,
2021 canvas_h,
2022 CANVAS_ADDR_NOWRAP,
2023 blkmode,
2024 7);
2025}
2026
2027
2028int get_free_buf_idx(struct vdec_s *vdec)
2029{
2030 int i;
2031 unsigned long addr, flags;
2032 int index = -1;
2033 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2034 int buf_total = BUFSPEC_POOL_SIZE;
2035
2036 if (hw->is_used_v4l)
2037 buf_total = hw->dpb.mDPB.size;
2038
2039 spin_lock_irqsave(&hw->bufspec_lock, flags);
2040 /*hw->start_search_pos = 0;*/
2041 for (i = hw->start_search_pos; i < buf_total; i++) {
2042 if (hw->mmu_enable)
2043 addr = hw->buffer_spec[i].alloc_header_addr;
2044 else {
2045 addr = hw->buffer_spec[i].cma_alloc_addr;
2046 if (hw->is_used_v4l && !addr) {
2047 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2048 config_decode_canvas(hw, i);
2049 addr = hw->buffer_spec[i].cma_alloc_addr;
2050 }
2051 }
2052 }
2053 if (hw->buffer_spec[i].used == 0 && addr) {
2054 hw->buffer_spec[i].used = 1;
2055 hw->start_search_pos = i+1;
2056 index = i;
2057 break;
2058 }
2059 }
2060 if (index < 0) {
2061 for (i = 0; i < hw->start_search_pos; i++) {
2062 if (hw->mmu_enable)
2063 addr = hw->buffer_spec[i].alloc_header_addr;
2064 else {
2065 addr = hw->buffer_spec[i].cma_alloc_addr;
2066 if (hw->is_used_v4l && !addr) {
2067 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2068 config_decode_canvas(hw, i);
2069 addr = hw->buffer_spec[i].cma_alloc_addr;
2070 }
2071 }
2072 }
2073 if (hw->buffer_spec[i].used == 0 && addr) {
2074 hw->buffer_spec[i].used = 1;
2075 hw->start_search_pos = i+1;
2076 index = i;
2077 break;
2078 }
2079 }
2080 }
2081 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2082 if (hw->start_search_pos >= buf_total)
2083 hw->start_search_pos = 0;
2084 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2085 "%s, buf_spec_num %d\n", __func__, index);
2086
2087 if (index < 0) {
2088 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2089 "%s fail\n", __func__);
2090 vmh264_dump_state(vdec);
2091 }
2092
2093 if (dpb_is_debug(DECODE_ID(hw),
2094 PRINT_FLAG_DUMP_BUFSPEC))
2095 dump_bufspec(hw, __func__);
2096 return index;
2097}
2098
2099int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2100{
2101 /*u32 cur_buf_idx;*/
2102 unsigned long flags;
2103 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2104 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2105 "%s buf_spec_num %d used %d\n",
2106 __func__, buf_spec_num,
2107 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2108 if (buf_spec_num >= 0 &&
2109 buf_spec_num < BUFSPEC_POOL_SIZE
2110 ) {
2111 spin_lock_irqsave(&hw->bufspec_lock, flags);
2112 hw->buffer_spec[buf_spec_num].used = 0;
2113 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2114 if (hw->mmu_enable) {
2115 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2116 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2117 cur_buf_idx = cur_buf_idx&0xff;*/
2118 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2119 }
2120 release_aux_data(hw, buf_spec_num);
2121 }
2122 if (dpb_is_debug(DECODE_ID(hw),
2123 PRINT_FLAG_DUMP_BUFSPEC))
2124 dump_bufspec(hw, __func__);
2125 return 0;
2126}
2127
2128static void config_buf_specs(struct vdec_s *vdec)
2129{
2130 int i, j;
2131 unsigned long flags;
2132 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2133 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2134
2135 spin_lock_irqsave(&hw->bufspec_lock, flags);
2136 for (i = 0, j = 0;
2137 j < hw->dpb.mDPB.size
2138 && i < BUFSPEC_POOL_SIZE;
2139 i++) {
2140 int canvas;
2141 if (hw->buffer_spec[i].used != -1)
2142 continue;
2143 if (vdec->parallel_dec == 1) {
2144 if (hw->buffer_spec[i].y_canvas_index == -1)
2145 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2146 if (hw->buffer_spec[i].u_canvas_index == -1) {
2147 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2148 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2149 }
2150#ifdef VDEC_DW
2151 if (IS_VDEC_DW(hw)) {
2152 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2153 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2154 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2155 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2156 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2157 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2158 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2159 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2160 }
2161 }
2162#endif
2163 } else {
2164 canvas = vdec->get_canvas(j * mode, 2);
2165 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2166 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2167 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2168 dpb_print(DECODE_ID(hw),
2169 PRINT_FLAG_DPB_DETAIL,
2170 "config canvas (%d) %x for bufspec %d\r\n",
2171 j, canvas, i);
2172#ifdef VDEC_DW
2173 if (IS_VDEC_DW(hw)) {
2174 canvas = vdec->get_canvas(j * mode + 1, 2);
2175 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2176 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2177 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2178 dpb_print(DECODE_ID(hw),
2179 PRINT_FLAG_DPB_DETAIL,
2180 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2181 j, canvas, i);
2182 }
2183#endif
2184 }
2185
2186 hw->buffer_spec[i].used = 0;
2187 hw->buffer_spec[i].canvas_pos = j;
2188
2189
2190 j++;
2191 }
2192 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2193}
2194
2195static void config_buf_specs_ex(struct vdec_s *vdec)
2196{
2197 int i, j;
2198 unsigned long flags;
2199 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2200 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2201
2202 spin_lock_irqsave(&hw->bufspec_lock, flags);
2203 for (i = 0, j = 0;
2204 j < hw->dpb.mDPB.size
2205 && i < BUFSPEC_POOL_SIZE;
2206 i++) {
2207 int canvas = 0;
2208 if (hw->buffer_spec[i].used != -1)
2209 continue;
2210 if (vdec->parallel_dec == 1) {
2211 if (hw->buffer_spec[i].y_canvas_index == -1)
2212 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2213 if (hw->buffer_spec[i].u_canvas_index == -1) {
2214 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2215 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2216 }
2217#ifdef VDEC_DW
2218 if (IS_VDEC_DW(hw)) {
2219 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2220 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2221 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2222 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2223 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2224 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2225 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2226 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2227 }
2228 }
2229#endif
2230 } else {
2231 canvas = vdec->get_canvas(j* mode, 2);
2232 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2233 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2234 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2235
2236 dpb_print(DECODE_ID(hw),
2237 PRINT_FLAG_DPB_DETAIL,
2238 "config canvas (%d) %x for bufspec %d\r\n",
2239 j, canvas, i);
2240#ifdef VDEC_DW
2241 if (IS_VDEC_DW(hw)) {
2242 canvas = vdec->get_canvas(j*mode + 1, 2);
2243 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2244 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2245 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2246 dpb_print(DECODE_ID(hw),
2247 PRINT_FLAG_DPB_DETAIL,
2248 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2249 j, canvas, i);
2250 }
2251#endif
2252 }
2253
2254 hw->buffer_spec[i].used = 0;
2255 hw->buffer_spec[i].alloc_header_addr = 0;
2256 hw->buffer_spec[i].canvas_pos = j;
2257
2258 j++;
2259 }
2260 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2261}
2262
2263
2264static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2265 unsigned char release_all)
2266{
2267 int i;
2268 unsigned long flags;
2269 unsigned char dealloc_flag = 0;
2270 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2271 if (hw->buffer_spec[i].used == 4 ||
2272 release_all) {
2273 dealloc_flag = 1;
2274 dpb_print(DECODE_ID(hw),
2275 PRINT_FLAG_DPB_DETAIL,
2276 "%s buf_spec_num %d\n",
2277 __func__, i
2278 );
2279 spin_lock_irqsave
2280 (&hw->bufspec_lock, flags);
2281 hw->buffer_spec[i].used = -1;
2282 spin_unlock_irqrestore
2283 (&hw->bufspec_lock, flags);
2284 release_aux_data(hw, i);
2285
2286 if (!hw->mmu_enable) {
2287 if (hw->buffer_spec[i].cma_alloc_addr) {
2288 if (!hw->is_used_v4l) {
2289 decoder_bmmu_box_free_idx(
2290 hw->bmmu_box,
2291 i);
2292 }
2293 spin_lock_irqsave
2294 (&hw->bufspec_lock, flags);
2295 hw->buffer_spec[i].cma_alloc_addr = 0;
2296 hw->buffer_spec[i].buf_adr = 0;
2297 spin_unlock_irqrestore
2298 (&hw->bufspec_lock, flags);
2299 }
2300 } else {
2301 if (hw->buffer_spec[i].alloc_header_addr) {
2302 decoder_mmu_box_free_idx(
2303 hw->mmu_box,
2304 i);
2305 spin_lock_irqsave
2306 (&hw->bufspec_lock, flags);
2307 hw->buffer_spec[i].
2308 alloc_header_addr = 0;
2309 hw->buffer_spec[i].buf_adr = 0;
2310 spin_unlock_irqrestore
2311 (&hw->bufspec_lock, flags);
2312 }
2313 }
2314 }
2315 }
2316 if (dealloc_flag &&
2317 dpb_is_debug(DECODE_ID(hw),
2318 PRINT_FLAG_DUMP_BUFSPEC))
2319 dump_bufspec(hw, __func__);
2320 return;
2321}
2322
2323unsigned char have_free_buf_spec(struct vdec_s *vdec)
2324{
2325 int i;
2326 unsigned long addr;
2327 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2328 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2329 int index = -1;
2330 int ret = 0;
2331 int allocated_count = 0;
2332 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2333 if (hw->mmu_enable)
2334 addr = hw->buffer_spec[i].alloc_header_addr;
2335 else
2336 addr = hw->buffer_spec[i].cma_alloc_addr;
2337 if (hw->buffer_spec[i].used == 0) {
2338
2339 if (addr)
2340 return 1;
2341 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2342 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2343 index = i;
2344 }
2345 }
2346 if (addr)
2347 allocated_count++;
2348 }
2349 if (index >= 0) {
2350 mutex_lock(&vmh264_mutex);
2351 dealloc_buf_specs(hw, 0);
2352 if (max_alloc_buf_count == 0 ||
2353 allocated_count < max_alloc_buf_count) {
2354 if (hw->is_used_v4l)
2355 ret = 1;
2356 else if (alloc_one_buf_spec(hw, index) >= 0)
2357 ret = 1;
2358 }
2359 mutex_unlock(&vmh264_mutex);
2360 }
2361 return ret;
2362}
2363
2364static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2365 int canvas_pos)
2366{
2367 int i;
2368 int j = 0;
2369 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2370 if (hw->buffer_spec[i].canvas_pos >= 0) {
2371 if (j == canvas_pos)
2372 return i;
2373 j++;
2374 }
2375 }
2376 return -1;
2377}
2378static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2379 struct vframe_s *vf, int index)
2380{
2381 if (index < 0) {
2382 vf->mem_handle = NULL;
2383 vf->mem_head_handle = NULL;
2384 } else if (vf->type & VIDTYPE_SCATTER) {
2385 vf->mem_handle =
2386 decoder_mmu_box_get_mem_handle(
2387 hw->mmu_box, index);
2388 vf->mem_head_handle =
2389 decoder_bmmu_box_get_mem_handle(
2390 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2391 } else {
2392 vf->mem_handle =
2393 decoder_bmmu_box_get_mem_handle(
2394 hw->bmmu_box, VF_BUFFER_IDX(index));
2395 /* vf->mem_head_handle =
2396 decoder_bmmu_box_get_mem_handle(
2397 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2398 }
2399 return;
2400}
2401static int check_force_interlace(struct vdec_h264_hw_s *hw,
2402 struct FrameStore *frame)
2403{
2404 int bForceInterlace = 0;
2405 /* no di in secure mode, disable force di */
2406 if (vdec_secure(hw_to_vdec(hw)))
2407 return 0;
2408 if (frame->frame) {
2409 if (frame->frame->coded_frame
2410 && !frame->frame->frame_mbs_only_flag) {
2411 if (frame->frame->structure == FRAME)
2412 return 1;
2413 }
2414 }
2415
2416 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2417 && hw->bitstream_restriction_flag
2418 && (hw->frame_width == 1920)
2419 && (hw->frame_height >= 1080)
2420 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2421 bForceInterlace = 1;
2422 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2423 && (hw->frame_width == 720)
2424 && (hw->frame_height == 576)
2425 && (hw->frame_dur == 3840)) {
2426 bForceInterlace = 1;
2427 }
2428
2429 return bForceInterlace;
2430}
2431
2432static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2433{
2434 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2435 if (frame->slice_type == I_SLICE)
2436 vframe_qos->type = 1;
2437 else if (frame->slice_type == P_SLICE)
2438 vframe_qos->type = 2;
2439 else if (frame->slice_type == B_SLICE)
2440 vframe_qos->type = 3;
2441
2442 vframe_qos->size = frame->frame_size;
2443 vframe_qos->pts = frame->pts64;
2444
2445 vframe_qos->max_mv = frame->max_mv;
2446 vframe_qos->avg_mv = frame->avg_mv;
2447 vframe_qos->min_mv = frame->min_mv;
2448/*
2449 pr_info("mv: max:%d, avg:%d, min:%d\n",
2450 vframe_qos->max_mv,
2451 vframe_qos->avg_mv,
2452 vframe_qos->min_mv);
2453*/
2454
2455 vframe_qos->max_qp = frame->max_qp;
2456 vframe_qos->avg_qp = frame->avg_qp;
2457 vframe_qos->min_qp = frame->min_qp;
2458/*
2459 pr_info("qp: max:%d, avg:%d, min:%d\n",
2460 vframe_qos->max_qp,
2461 vframe_qos->avg_qp,
2462 vframe_qos->min_qp);
2463*/
2464
2465 vframe_qos->max_skip = frame->max_skip;
2466 vframe_qos->avg_skip = frame->avg_skip;
2467 vframe_qos->min_skip = frame->min_skip;
2468/*
2469 pr_info("skip: max:%d, avg:%d, min:%d\n",
2470 vframe_qos->max_skip,
2471 vframe_qos->avg_skip,
2472 vframe_qos->min_skip);
2473*/
2474 vframe_qos->num++;
2475 if (hw->frameinfo_enable)
2476 vdec_fill_frame_info(vframe_qos, 1);
2477}
2478
2479static int is_iframe(struct FrameStore *frame) {
2480
2481 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2482 return 1;
2483 }
2484 return 0;
2485}
2486
2487
2488
2489int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2490{
2491 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2492 struct vframe_s *vf = NULL;
2493 int buffer_index = frame->buf_spec_num;
2494 int vf_count = 1;
2495 int i;
2496 int bForceInterlace = 0;
2497
2498 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2499 dpb_print(DECODE_ID(hw), 0,
2500 "%s, buffer_index 0x%x is beyond range\n",
2501 __func__, buffer_index);
2502 return -1;
2503 }
2504 if (force_disp_bufspec_num & 0x100) {
2505 /*recycle directly*/
2506 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2507 hw->buffer_spec[frame->buf_spec_num].used != 5)
2508 set_frame_output_flag(&hw->dpb, frame->index);
2509
2510 /*make pre_output not set*/
2511 return -1;
2512 }
2513 if (error_proc_policy & 0x1000) {
2514 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2515 int error_skip_frame_count = error_skip_count & 0xfff;
2516 if (((hw->no_error_count < error_skip_frame_count)
2517 && (error_skip_i_count == 0 ||
2518 hw->no_error_i_count < error_skip_i_count))
2519 && (!(frame->data_flag & I_FLAG)))
2520 frame->data_flag |= ERROR_FLAG;
2521 }
2522 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2523 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2524 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2525 frame->poc, hw->data_flag & ERROR_FLAG,
2526 error_proc_policy);
2527 if (frame->frame == NULL &&
2528 ((frame->is_used == 1 && frame->top_field)
2529 || (frame->is_used == 2 && frame->bottom_field))) {
2530 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2531 "%s Error frame_num %d used %d\n",
2532 __func__, frame->frame_num, frame->is_used);
2533 frame->data_flag |= ERROR_FLAG;
2534 }
2535 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2536 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2537 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2538 0, &frame->pts64) == 0)) {
2539 hw->last_pts64 = frame->pts64;
2540 hw->last_pts = frame->pts;
2541 } else {
2542 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2543 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2544 }
2545 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2546 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2547 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2548 frame->offset_delimiter, frame->pts,hw->last_pts,
2549 frame->pts64, hw->last_pts64, hw->frame_dur);
2550 hw->last_pts64 = frame->pts64;
2551 hw->last_pts = frame->pts;
2552 }
2553 if ((frame->data_flag & NODISP_FLAG) ||
2554 (frame->data_flag & NULL_FLAG) ||
2555 ((!hw->send_error_frame_flag) &&
2556 (frame->data_flag & ERROR_FLAG)) ||
2557 ((hw->i_only & 0x1) &&
2558 (!(frame->data_flag & I_FLAG)))
2559 ) {
2560 set_frame_output_flag(&hw->dpb, frame->index);
2561 return 0; /*do not return -1,
2562 otherwise flush_dpb() will not flush all dbp frames*/
2563 }
2564
2565 display_frame_count[DECODE_ID(hw)]++;
2566
2567 if (dpb_is_debug(DECODE_ID(hw),
2568 PRINT_FLAG_DPB_DETAIL)) {
2569 dpb_print(DECODE_ID(hw), 0,
2570 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2571 __func__, frame->index, frame->poc,
2572 frame->buf_spec_num);
2573 print_pic_info(DECODE_ID(hw), "predis_frm",
2574 frame->frame, -1);
2575 print_pic_info(DECODE_ID(hw), "predis_top",
2576 frame->top_field, -1);
2577 print_pic_info(DECODE_ID(hw), "predis_bot",
2578 frame->bottom_field, -1);
2579 }
2580
2581 if (!is_interlace(frame))
2582 vf_count = 1;
2583 else
2584 vf_count = 2;
2585 bForceInterlace = check_force_interlace(hw, frame);
2586 if (bForceInterlace)
2587 vf_count = 2;
2588 hw->buffer_spec[buffer_index].vf_ref = 0;
2589 fill_frame_info(hw, frame);
2590 for (i = 0; i < vf_count; i++) {
2591 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2592 vf == NULL) {
2593 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2594 "%s fatal error, no available buffer slot.\n",
2595 __func__);
2596 return -1;
2597 }
2598 vf->duration_pulldown = 0;
2599 if (!(is_iframe(frame)) && hw->unstable_pts) {
2600 vf->pts = 0;
2601 vf->pts_us64 = 0;
2602 vf->timestamp = 0;
2603 vf->index = VF_INDEX(frame->index, buffer_index);
2604 } else {
2605 vf->pts = frame->pts;
2606 vf->pts_us64 = frame->pts64;
2607 vf->timestamp = frame->timestamp;
2608 vf->index = VF_INDEX(frame->index, buffer_index);
2609 }
2610
2611 if (hw->is_used_v4l) {
2612 vf->v4l_mem_handle
2613 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2614 if (hw->mmu_enable) {
2615 if (vdec_v4l_binding_fd_and_vf(vf->v4l_mem_handle, vf) < 0) {
2616 dpb_print(DECODE_ID(hw),
2617 PRINT_FLAG_V4L_DETAIL,
2618 "v4l: binding vf fail.\n");
2619 return -1;
2620 }
2621 }
2622 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
2623 "[%d] %s(), v4l mem handle: 0x%x\n",
2624 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
2625 __func__, vf->v4l_mem_handle);
2626 }
2627
2628 if (hw->mmu_enable) {
2629 if (hw->double_write_mode & 0x10) {
2630 /* double write only */
2631 vf->compBodyAddr = 0;
2632 vf->compHeadAddr = 0;
2633 } else {
2634 /*head adr*/
2635 vf->compHeadAddr =
2636 hw->buffer_spec[buffer_index].alloc_header_addr;
2637 /*body adr*/
2638 vf->compBodyAddr = 0;
2639 vf->canvas0Addr = vf->canvas1Addr = 0;
2640 }
2641
2642 vf->type = VIDTYPE_SCATTER;
2643
2644 if (hw->double_write_mode) {
2645 vf->type |= VIDTYPE_PROGRESSIVE
2646 | VIDTYPE_VIU_FIELD;
2647 vf->type |= VIDTYPE_VIU_NV21;
2648 if (hw->double_write_mode == 3)
2649 vf->type |= VIDTYPE_COMPRESS;
2650
2651 vf->canvas0Addr = vf->canvas1Addr = -1;
2652 vf->plane_num = 2;
2653 vf->canvas0_config[0] =
2654 hw->buffer_spec[buffer_index].
2655 canvas_config[0];
2656 vf->canvas0_config[1] =
2657 hw->buffer_spec[buffer_index].
2658 canvas_config[1];
2659
2660 vf->canvas1_config[0] =
2661 hw->buffer_spec[buffer_index].
2662 canvas_config[0];
2663 vf->canvas1_config[1] =
2664 hw->buffer_spec[buffer_index].
2665 canvas_config[1];
2666
2667 } else {
2668 vf->type |=
2669 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2670 vf->canvas0Addr = vf->canvas1Addr = 0;
2671 }
2672
2673 vf->bitdepth =
2674 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2675
2676 vf->compWidth = hw->frame_width;
2677 vf->compHeight = hw->frame_height;
2678 } else {
2679 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2680 VIDTYPE_VIU_NV21;
2681
2682 vf->canvas0Addr = vf->canvas1Addr =
2683 spec2canvas(&hw->buffer_spec[buffer_index]);
2684#ifdef VDEC_DW
2685 if (IS_VDEC_DW(hw))
2686 vf->canvas0Addr = vf->canvas1Addr =
2687 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2688#endif
2689
2690 }
2691 set_frame_info(hw, vf, buffer_index);
2692
2693 if (hw->mmu_enable && hw->double_write_mode) {
2694 vf->width = hw->frame_width /
2695 get_double_write_ratio(hw);
2696 vf->height = hw->frame_height /
2697 get_double_write_ratio(hw);
2698 }
2699
2700 vf->flag = 0;
2701 if (frame->data_flag & I_FLAG)
2702 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2703 if (frame->data_flag & ERROR_FLAG)
2704 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2705 update_vf_memhandle(hw, vf, buffer_index);
2706 hw->buffer_spec[buffer_index].used = 2;
2707 hw->buffer_spec[buffer_index].vf_ref++;
2708
2709 if (bForceInterlace || is_interlace(frame)) {
2710 vf->type =
2711 VIDTYPE_INTERLACE_FIRST |
2712 VIDTYPE_VIU_NV21;
2713
2714 if (bForceInterlace) {
2715 vf->type |= (i == 0 ?
2716 VIDTYPE_INTERLACE_TOP :
2717 VIDTYPE_INTERLACE_BOTTOM);
2718 if (i == 1) {
2719 vf->pts = 0;
2720 vf->pts_us64 = 0;
2721 }
2722 } else if (frame->top_field->poc <=
2723 frame->bottom_field->poc) /*top first*/
2724 vf->type |= (i == 0 ?
2725 VIDTYPE_INTERLACE_TOP :
2726 VIDTYPE_INTERLACE_BOTTOM);
2727 else
2728 vf->type |= (i == 0 ?
2729 VIDTYPE_INTERLACE_BOTTOM :
2730 VIDTYPE_INTERLACE_TOP);
2731 vf->duration = vf->duration/2;
2732 }
2733
2734 if (i == 0)
2735 decoder_do_frame_check(hw_to_vdec(hw), vf);
2736
2737 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2738 vf->sar_width = hw->width_aspect_ratio;
2739 vf->sar_height = hw->height_aspect_ratio;
2740
2741 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2742 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2743 hw->vf_pre_count++;
2744 vdec->vdec_fps_detec(vdec->id);
2745 if (without_display_mode == 0) {
2746 vf_notify_receiver(vdec->vf_provider_name,
2747 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2748 } else
2749 vh264_vf_put(vh264_vf_get(vdec), vdec);
2750 }
2751 if (dpb_is_debug(DECODE_ID(hw),
2752 PRINT_FLAG_DUMP_BUFSPEC))
2753 dump_bufspec(hw, __func__);
2754
2755 return 0;
2756}
2757
2758int notify_v4l_eos(struct vdec_s *vdec)
2759{
2760 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2761 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2762 struct vframe_s *vf = NULL;
2763 struct vdec_v4l2_buffer *fb = NULL;
2764
2765 if (hw->is_used_v4l && hw->eos) {
2766 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
2767 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2768 "%s fatal error, no available buffer slot.\n",
2769 __func__);
2770 return -1;
2771 }
2772
2773 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
2774 pr_err("[%d] get fb fail.\n", ctx->id);
2775 return -1;
2776 }
2777
2778 vf->type |= VIDTYPE_V4L_EOS;
2779 vf->timestamp = ULONG_MAX;
2780 vf->v4l_mem_handle = (unsigned long)fb;
2781 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2782
2783 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2784
2785 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2786 vf_notify_receiver(vdec->vf_provider_name,
2787 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2788
2789 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2790 }
2791
2792 return 0;
2793}
2794
2795/******************
2796 * Hardware config
2797 */
2798char *slice_type_name[] = {
2799 "P_SLICE ",
2800 "B_SLICE ",
2801 "I_SLICE ",
2802 "SP_SLICE",
2803 "SI_SLICE",
2804};
2805
2806char *picture_structure_name[] = {
2807 "FRAME",
2808 "TOP_FIELD",
2809 "BOTTOM_FIELD"
2810};
2811
2812void print_pic_info(int decindex, const char *info,
2813 struct StorablePicture *pic,
2814 int slice_type)
2815{
2816 if (pic)
2817 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2818 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2819 info,
2820 picture_structure_name[pic->structure],
2821 pic->coded_frame ? "Frame" : "Field",
2822 (slice_type < 0 ||
2823 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2824 pic->mb_aff_frame_flag,
2825 pic->poc,
2826 pic->pic_num,
2827 pic->buf_spec_num,
2828 pic->data_flag);
2829}
2830
2831static void reset_process_time(struct vdec_h264_hw_s *hw)
2832{
2833 if (hw->start_process_time) {
2834 unsigned process_time =
2835 1000 * (jiffies - hw->start_process_time) / HZ;
2836 hw->start_process_time = 0;
2837 if (process_time > max_process_time[DECODE_ID(hw)])
2838 max_process_time[DECODE_ID(hw)] = process_time;
2839 }
2840}
2841
2842static void start_process_time(struct vdec_h264_hw_s *hw)
2843{
2844 hw->decode_timeout_count = 10;
2845 hw->start_process_time = jiffies;
2846}
2847
2848static void config_aux_buf(struct vdec_h264_hw_s *hw)
2849{
2850 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2851 WRITE_VREG(H264_AUX_DATA_SIZE,
2852 ((hw->prefix_aux_size >> 4) << 16) |
2853 (hw->suffix_aux_size >> 4)
2854 );
2855}
2856
2857/*
2858* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2859*/
2860static void set_aux_data(struct vdec_h264_hw_s *hw,
2861 struct StorablePicture *pic, unsigned char suffix_flag,
2862 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2863{
2864 int i;
2865 unsigned short *aux_adr;
2866 unsigned size_reg_val =
2867 READ_VREG(H264_AUX_DATA_SIZE);
2868 unsigned aux_count = 0;
2869 int aux_size = 0;
2870 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2871 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2872 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2873 return;
2874
2875 if (suffix_flag) {
2876 aux_adr = (unsigned short *)
2877 (hw_buf->aux_addr +
2878 hw_buf->prefix_aux_size);
2879 aux_count =
2880 ((size_reg_val & 0xffff) << 4)
2881 >> 1;
2882 aux_size =
2883 hw_buf->suffix_aux_size;
2884 } else {
2885 aux_adr =
2886 (unsigned short *)hw_buf->aux_addr;
2887 aux_count =
2888 ((size_reg_val >> 16) << 4)
2889 >> 1;
2890 aux_size =
2891 hw_buf->prefix_aux_size;
2892 }
2893 if (dpb_is_debug(DECODE_ID(hw),
2894 PRINT_FLAG_DPB_DETAIL)) {
2895 dpb_print(DECODE_ID(hw), 0,
2896 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2897 __func__, AUX_DATA_SIZE(pic),
2898 aux_count, suffix_flag, dv_meta_flag);
2899 }
2900 if (aux_size > 0 && aux_count > 0) {
2901 int heads_size = 0;
2902 int new_size;
2903 char *new_buf;
2904 for (i = 0; i < aux_count; i++) {
2905 unsigned char tag = aux_adr[i] >> 8;
2906 if (tag != 0 && tag != 0xff) {
2907 if (dv_meta_flag == 0)
2908 heads_size += 8;
2909 else if (dv_meta_flag == 1 && tag == 0x1)
2910 heads_size += 8;
2911 else if (dv_meta_flag == 2 && tag != 0x1)
2912 heads_size += 8;
2913 }
2914 }
2915 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2916 new_buf = krealloc(AUX_DATA_BUF(pic),
2917 new_size,
2918 GFP_KERNEL);
2919 if (new_buf) {
2920 unsigned char valid_tag = 0;
2921 unsigned char *h =
2922 new_buf +
2923 AUX_DATA_SIZE(pic);
2924 unsigned char *p = h + 8;
2925 int len = 0;
2926 int padding_len = 0;
2927 AUX_DATA_BUF(pic) = new_buf;
2928 for (i = 0; i < aux_count; i += 4) {
2929 int ii;
2930 unsigned char tag = aux_adr[i + 3] >> 8;
2931 if (tag != 0 && tag != 0xff) {
2932 if (dv_meta_flag == 0)
2933 valid_tag = 1;
2934 else if (dv_meta_flag == 1
2935 && tag == 0x1)
2936 valid_tag = 1;
2937 else if (dv_meta_flag == 2
2938 && tag != 0x1)
2939 valid_tag = 1;
2940 else
2941 valid_tag = 0;
2942 if (valid_tag && len > 0) {
2943 AUX_DATA_SIZE(pic) +=
2944 (len + 8);
2945 h[0] =
2946 (len >> 24) & 0xff;
2947 h[1] =
2948 (len >> 16) & 0xff;
2949 h[2] =
2950 (len >> 8) & 0xff;
2951 h[3] =
2952 (len >> 0) & 0xff;
2953 h[6] =
2954 (padding_len >> 8)
2955 & 0xff;
2956 h[7] =
2957 (padding_len) & 0xff;
2958 h += (len + 8);
2959 p += 8;
2960 len = 0;
2961 padding_len = 0;
2962 }
2963 if (valid_tag) {
2964 h[4] = tag;
2965 h[5] = 0;
2966 h[6] = 0;
2967 h[7] = 0;
2968 }
2969 }
2970 if (valid_tag) {
2971 for (ii = 0; ii < 4; ii++) {
2972 unsigned short aa =
2973 aux_adr[i + 3
2974 - ii];
2975 *p = aa & 0xff;
2976 p++;
2977 len++;
2978 /*if ((aa >> 8) == 0xff)
2979 padding_len++;*/
2980 }
2981 }
2982 }
2983 if (len > 0) {
2984 AUX_DATA_SIZE(pic) += (len + 8);
2985 h[0] = (len >> 24) & 0xff;
2986 h[1] = (len >> 16) & 0xff;
2987 h[2] = (len >> 8) & 0xff;
2988 h[3] = (len >> 0) & 0xff;
2989 h[6] = (padding_len >> 8) & 0xff;
2990 h[7] = (padding_len) & 0xff;
2991 }
2992 if (dpb_is_debug(DECODE_ID(hw),
2993 PRINT_FLAG_DPB_DETAIL)) {
2994 dpb_print(DECODE_ID(hw), 0,
2995 "aux: (size %d) suffix_flag %d\n",
2996 AUX_DATA_SIZE(pic), suffix_flag);
2997 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2998 dpb_print_cont(DECODE_ID(hw), 0,
2999 "%02x ", AUX_DATA_BUF(pic)[i]);
3000 if (((i + 1) & 0xf) == 0)
3001 dpb_print_cont(
3002 DECODE_ID(hw),
3003 0, "\n");
3004 }
3005 dpb_print_cont(DECODE_ID(hw),
3006 0, "\n");
3007 }
3008
3009 }
3010 }
3011
3012}
3013
3014static void release_aux_data(struct vdec_h264_hw_s *hw,
3015 int buf_spec_num)
3016{
3017 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3018 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3019 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3020}
3021
3022static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3023{
3024 int i;
3025 unsigned short *aux_adr =
3026 (unsigned short *)
3027 hw->aux_addr;
3028 unsigned aux_size =
3029 (READ_VREG(H264_AUX_DATA_SIZE)
3030 >> 16) << 4;
3031
3032 if (hw->prefix_aux_size > 0) {
3033 dpb_print(DECODE_ID(hw),
3034 0,
3035 "prefix aux: (size %d)\n",
3036 aux_size);
3037 for (i = 0; i <
3038 (aux_size >> 1); i++) {
3039 dpb_print_cont(DECODE_ID(hw),
3040 0,
3041 "%04x ",
3042 *(aux_adr + i));
3043 if (((i + 1) & 0xf)
3044 == 0)
3045 dpb_print_cont(
3046 DECODE_ID(hw),
3047 0, "\n");
3048 }
3049 }
3050 if (hw->suffix_aux_size > 0) {
3051 aux_adr = (unsigned short *)
3052 (hw->aux_addr +
3053 hw->prefix_aux_size);
3054 aux_size =
3055 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3056 << 4;
3057 dpb_print(DECODE_ID(hw),
3058 0,
3059 "suffix aux: (size %d)\n",
3060 aux_size);
3061 for (i = 0; i <
3062 (aux_size >> 1); i++) {
3063 dpb_print_cont(DECODE_ID(hw),
3064 0,
3065 "%04x ", *(aux_adr + i));
3066 if (((i + 1) & 0xf) == 0)
3067 dpb_print_cont(DECODE_ID(hw),
3068 0, "\n");
3069 }
3070 }
3071}
3072
3073static void config_decode_mode(struct vdec_h264_hw_s *hw)
3074{
3075#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3076 struct vdec_s *vdec = hw_to_vdec(hw);
3077#endif
3078 if (input_frame_based(hw_to_vdec(hw)))
3079 WRITE_VREG(H264_DECODE_MODE,
3080 DECODE_MODE_MULTI_FRAMEBASE);
3081#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3082 else if (vdec->slave)
3083 WRITE_VREG(H264_DECODE_MODE,
3084 (hw->got_valid_nal << 8) |
3085 DECODE_MODE_MULTI_DVBAL);
3086 else if (vdec->master)
3087 WRITE_VREG(H264_DECODE_MODE,
3088 (hw->got_valid_nal << 8) |
3089 DECODE_MODE_MULTI_DVENL);
3090#endif
3091 else
3092 WRITE_VREG(H264_DECODE_MODE,
3093 DECODE_MODE_MULTI_STREAMBASE);
3094 WRITE_VREG(H264_DECODE_SEQINFO,
3095 hw->seq_info2);
3096 WRITE_VREG(HEAD_PADING_REG, 0);
3097
3098 if (hw->init_flag == 0)
3099 WRITE_VREG(INIT_FLAG_REG, 0);
3100 else
3101 WRITE_VREG(INIT_FLAG_REG, 1);
3102}
3103int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3104{
3105 /* static int count = 0; */
3106 int ret = 0;
3107 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3108 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3109 unsigned int colocate_adr_offset;
3110 unsigned int val;
3111 struct StorablePicture *last_pic = hw->last_dec_picture;
3112
3113#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3114 int colocate_buf_index;
3115#endif
3116#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3117#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3118#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3119#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3120
3121#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3122/* bit 31:30 -- L1[0] picture coding structure,
3123 * 00 - top field, 01 - bottom field,
3124 * 10 - frame, 11 - mbaff frame
3125 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3126 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3127 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3128 */
3129#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3130
3131/* bit 15 -- flush co_mb_data to DDR -- W-Only
3132 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3133 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3134 * bit 9 -- soft_reset -- W-Only
3135 * bit 8 -- upgent
3136 * bit 7:2 -- h264_co_mb_mem_wr_addr
3137 * bit 1:0 -- h264_co_mb_info_wr_ptr
3138 */
3139#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3140
3141 unsigned long canvas_adr;
3142 unsigned int ref_reg_val;
3143 unsigned int one_ref_cfg = 0;
3144 int h264_buffer_info_data_write_count;
3145 int i, j;
3146 unsigned int colocate_wr_adr;
3147 unsigned int colocate_rd_adr;
3148 unsigned char use_direct_8x8;
3149 int canvas_pos;
3150 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3151 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3152 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3153 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3154 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3155
3156 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3157 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3158 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3159 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3160 canvas_pos);
3161 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3162
3163#ifdef VDEC_DW
3164 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3165 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3166 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3167#endif
3168 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3169 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3170
3171 if (!hw->mmu_enable) {
3172 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3173 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3174 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3175#ifdef VDEC_DW
3176 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3177 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3178 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3179#endif
3180 } else
3181 hevc_sao_set_pic_buffer(hw, pic);
3182
3183 if (pic->mb_aff_frame_flag)
3184 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3185 else if (pic->structure == TOP_FIELD)
3186 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3187 else if (pic->structure == BOTTOM_FIELD)
3188 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3189 else
3190 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3191
3192 if (pic->bottom_poc < pic->top_poc)
3193 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3194
3195 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3196 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3197 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3198
3199 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3200 int long_term_flag;
3201 i = get_buf_spec_by_canvas_pos(hw, j);
3202 if (i < 0)
3203 break;
3204 long_term_flag =
3205 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3206 if (long_term_flag > 0) {
3207 if (long_term_flag & 0x1)
3208 hw->buffer_spec[i].info0 |= (1 << 4);
3209 else
3210 hw->buffer_spec[i].info0 &= ~(1 << 4);
3211
3212 if (long_term_flag & 0x2)
3213 hw->buffer_spec[i].info0 |= (1 << 5);
3214 else
3215 hw->buffer_spec[i].info0 &= ~(1 << 5);
3216 }
3217
3218 if (i == pic->buf_spec_num)
3219 WRITE_VREG(H264_BUFFER_INFO_DATA,
3220 hw->buffer_spec[i].info0 | 0xf);
3221 else
3222 WRITE_VREG(H264_BUFFER_INFO_DATA,
3223 hw->buffer_spec[i].info0);
3224 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3225 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3226 }
3227
3228 /* config reference buffer */
3229 if (hw->mmu_enable) {
3230 hevc_mcr_config_mc_ref(hw);
3231 hevc_mcr_config_mcrcc(hw);
3232 }
3233
3234 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3235 "list0 size %d\n", pSlice->listXsize[0]);
3236 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3237 ref_reg_val = 0;
3238 j = 0;
3239 h264_buffer_info_data_write_count = 0;
3240
3241 //disable this read cache when frame width <= 64 (4MBs)
3242 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3243 if (hw->frame_width <= 64)
3244 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3245 else
3246 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3247
3248 if (last_pic)
3249 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3250 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3251 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3252 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3253 last_pic && (last_pic->data_flag & ERROR_FLAG)
3254 && (!(last_pic->slice_type == B_SLICE))
3255 && (!(pSlice->slice_type == I_SLICE))) {
3256 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3257 "no i/idr error mark\n");
3258 hw->data_flag |= ERROR_FLAG;
3259 pic->data_flag |= ERROR_FLAG;
3260 }
3261
3262 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3263 /*ref list 0 */
3264 struct StorablePicture *ref = pSlice->listX[0][i];
3265 unsigned int cfg;
3266 /* bit[6:5] - frame/field info,
3267 * 01 - top, 10 - bottom, 11 - frame
3268 */
3269 #ifdef ERROR_CHECK
3270 if (ref == NULL) {
3271 hw->data_flag |= ERROR_FLAG;
3272 pic->data_flag |= ERROR_FLAG;
3273 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3274 return -1;
3275 }
3276 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3277 hw->data_flag |= ERROR_FLAG;
3278 pic->data_flag |= ERROR_FLAG;
3279 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3280 }
3281 if (ref->data_flag & NULL_FLAG)
3282 hw->data_flag |= NULL_FLAG;
3283#endif
3284 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3285
3286 if (ref->structure == TOP_FIELD)
3287 cfg = 0x1;
3288 else if (ref->structure == BOTTOM_FIELD)
3289 cfg = 0x2;
3290 else /* FRAME */
3291 cfg = 0x3;
3292
3293 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3294 ref_reg_val <<= 8;
3295 ref_reg_val |= one_ref_cfg;
3296 j++;
3297
3298 if (j == 4) {
3299 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3300 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3301 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3302 h264_buffer_info_data_write_count++;
3303 j = 0;
3304 }
3305 print_pic_info(DECODE_ID(hw), "list0",
3306 pSlice->listX[0][i], -1);
3307 }
3308 if (j != 0) {
3309 while (j != 4) {
3310 ref_reg_val <<= 8;
3311 ref_reg_val |= one_ref_cfg;
3312 j++;
3313 }
3314 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3315 "H264_BUFFER_INFO_DATA: %x\n",
3316 ref_reg_val);
3317 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3318 h264_buffer_info_data_write_count++;
3319 }
3320 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3321 (one_ref_cfg << 8) | one_ref_cfg;
3322 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3323 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3324
3325 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3326 "list1 size %d\n", pSlice->listXsize[1]);
3327 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3328 ref_reg_val = 0;
3329 j = 0;
3330
3331 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3332 /* ref list 0 */
3333 struct StorablePicture *ref = pSlice->listX[1][i];
3334 unsigned int cfg;
3335 /* bit[6:5] - frame/field info,
3336 * 01 - top, 10 - bottom, 11 - frame
3337 */
3338
3339 #ifdef ERROR_CHECK
3340 if (ref == NULL) {
3341 hw->data_flag |= ERROR_FLAG;
3342 pic->data_flag |= ERROR_FLAG;
3343 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3344 return -2;
3345 }
3346 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3347 pic->data_flag |= ERROR_FLAG;
3348 hw->data_flag |= ERROR_FLAG;
3349 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3350 }
3351 if (ref->data_flag & NULL_FLAG)
3352 hw->data_flag |= NULL_FLAG;
3353#endif
3354 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3355 if (ref->structure == TOP_FIELD)
3356 cfg = 0x1;
3357 else if (ref->structure == BOTTOM_FIELD)
3358 cfg = 0x2;
3359 else /* FRAME */
3360 cfg = 0x3;
3361 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3362 ref_reg_val <<= 8;
3363 ref_reg_val |= one_ref_cfg;
3364 j++;
3365
3366 if (j == 4) {
3367 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3368 "H264_BUFFER_INFO_DATA: %x\n",
3369 ref_reg_val);
3370 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3371 j = 0;
3372 }
3373 print_pic_info(DECODE_ID(hw), "list1",
3374 pSlice->listX[1][i], -1);
3375 }
3376 if (j != 0) {
3377 while (j != 4) {
3378 ref_reg_val <<= 8;
3379 ref_reg_val |= one_ref_cfg;
3380 j++;
3381 }
3382 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3383 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3384 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3385 }
3386
3387 /* configure co-locate buffer */
3388 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3389 ;
3390 if ((pSlice->mode_8x8_flags & 0x4) &&
3391 (pSlice->mode_8x8_flags & 0x2))
3392 use_direct_8x8 = 1;
3393 else
3394 use_direct_8x8 = 0;
3395
3396#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3397 colocate_adr_offset =
3398 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3399 ? 1 : 2) * 96;
3400 if (use_direct_8x8)
3401 colocate_adr_offset >>= 2;
3402
3403 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3404 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3405 colocate_adr_offset, pSlice->first_mb_in_slice,
3406 colocate_adr_offset * pSlice->first_mb_in_slice);
3407
3408 colocate_adr_offset *= pSlice->first_mb_in_slice;
3409
3410 if ((pic->colocated_buf_index >= 0) &&
3411 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3412 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3413 ((p_H264_Dpb->colocated_buf_size *
3414 pic->colocated_buf_index)
3415 >> (use_direct_8x8 ? 2 : 0));
3416 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3417 p_H264_Dpb->colocated_mv_addr_end) {
3418 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3419 "Error, colocate buf is not enough, index is %d\n",
3420 pic->colocated_buf_index);
3421 ret = -3;
3422 }
3423 val = colocate_wr_adr + colocate_adr_offset;
3424 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3425 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3426 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3427 val, pSlice->first_mb_in_slice, pic->structure,
3428 colocate_adr_offset, pSlice->mode_8x8_flags,
3429 p_H264_Dpb->colocated_buf_size);
3430 } else {
3431 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3432 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3433 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3434 }
3435#else
3436 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3437 colocate_adr_offset =
3438 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3439 if (use_direct_8x8)
3440 colocate_adr_offset >>= 2;
3441
3442 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3443 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3444 colocate_adr_offset, pSlice->first_mb_in_slice,
3445 colocate_adr_offset * pSlice->first_mb_in_slice);
3446
3447 colocate_adr_offset *= pSlice->first_mb_in_slice;
3448
3449 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3450 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3451 (use_direct_8x8 ? 2 : 0));
3452
3453 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3454 p_H264_Dpb->colocated_mv_addr_end) {
3455 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3456 "Error, colocate buf is not enough, col buf index is %d\n",
3457 colocate_buf_index);
3458 ret = -4;
3459 }
3460 val = colocate_wr_adr + colocate_adr_offset;
3461 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3462 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3463 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3464 val, pSlice->first_mb_in_slice, pic->structure,
3465 colocate_adr_offset, pSlice->mode_8x8_flags,
3466 p_H264_Dpb->colocated_buf_size);
3467#endif
3468 if (pSlice->listXsize[1] > 0) {
3469 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3470 /* H264_CO_MB_RD_ADDR[bit 31:30],
3471 * original picture structure of L1[0],
3472 * 00 - top field, 01 - bottom field,
3473 * 10 - frame, 11 - mbaff frame
3474 */
3475 int l10_structure;
3476 int cur_colocate_ref_type;
3477 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3478 * 0 - top, 1 - bot
3479 */
3480 unsigned int val;
3481#ifdef ERROR_CHECK
3482 if (colocate_pic == NULL) {
3483 hw->data_flag |= ERROR_FLAG;
3484 pic->data_flag |= ERROR_FLAG;
3485 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3486 return -5;
3487 }
3488 if (colocate_pic->data_flag & ERROR_FLAG) {
3489 pic->data_flag |= ERROR_FLAG;
3490 hw->data_flag |= ERROR_FLAG;
3491 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3492 }
3493 if (colocate_pic->data_flag & NULL_FLAG)
3494 hw->data_flag |= NULL_FLAG;
3495#endif
3496
3497 if (colocate_pic->mb_aff_frame_flag)
3498 l10_structure = 3;
3499 else {
3500 if (colocate_pic->coded_frame)
3501 l10_structure = 2;
3502 else
3503 l10_structure = (colocate_pic->structure ==
3504 BOTTOM_FIELD) ? 1 : 0;
3505 }
3506#if 0
3507 /*case0016, p16,
3508 *cur_colocate_ref_type should be configured base on current pic
3509 */
3510 if (pic->structure == FRAME &&
3511 pic->mb_aff_frame_flag)
3512 cur_colocate_ref_type = 0;
3513 else if (pic->structure == BOTTOM_FIELD)
3514 cur_colocate_ref_type = 1;
3515 else
3516 cur_colocate_ref_type = 0;
3517#else
3518 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3519 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3520 pic->mb_aff_frame_flag,
3521 pic->structure,
3522 pic->coded_frame);
3523 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3524 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3525 colocate_pic->mb_aff_frame_flag,
3526 colocate_pic->structure,
3527 colocate_pic->coded_frame);
3528 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3529 cur_colocate_ref_type =
3530 (abs(pic->poc - colocate_pic->top_poc)
3531 < abs(pic->poc -
3532 colocate_pic->bottom_poc)) ? 0 : 1;
3533 } else
3534 cur_colocate_ref_type =
3535 (colocate_pic->structure
3536 == BOTTOM_FIELD) ? 1 : 0;
3537#endif
3538
3539#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3540 if ((colocate_pic->colocated_buf_index >= 0) &&
3541 (colocate_pic->colocated_buf_index <
3542 p_H264_Dpb->colocated_buf_count)) {
3543 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3544 ((p_H264_Dpb->colocated_buf_size *
3545 colocate_pic->colocated_buf_index)
3546 >> (use_direct_8x8 ? 2 : 0));
3547 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3548 p_H264_Dpb->colocated_mv_addr_end) {
3549 dpb_print(DECODE_ID(hw),
3550 PRINT_FLAG_ERROR,
3551 "Error, colocate buf is not enough, index is %d\n",
3552 colocate_pic->colocated_buf_index);
3553 ret = -6;
3554 }
3555 /* bit 31:30 -- L1[0] picture coding structure,
3556 * 00 - top field, 01 - bottom field,
3557 * 10 - frame, 11 - mbaff frame
3558 * bit 29 - L1[0] top/bot for B field pciture,
3559 * 0 - top, 1 - bot
3560 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3561 * -- only used for B Picture Direct mode
3562 * [2:0] will set to 3'b000
3563 */
3564 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3565 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3566 (l10_structure << 30) |
3567 (cur_colocate_ref_type << 29);
3568 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3569 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3570 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3571 colocate_pic->colocated_buf_index,
3572 val, colocate_rd_adr + colocate_adr_offset,
3573 colocate_pic->structure,
3574 colocate_pic->mb_aff_frame_flag);
3575 } else {
3576 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3577 "Error, reference pic has no colocated buf\n");
3578 ret = -7;
3579 }
3580#else
3581 colocate_buf_index =
3582 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3583 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3584 ((p_H264_Dpb->colocated_buf_size *
3585 colocate_buf_index)
3586 >> (use_direct_8x8 ? 2 : 0));
3587 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3588 p_H264_Dpb->colocated_mv_addr_end) {
3589 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3590 "Error, colocate buf is not enough, col buf index is %d\n",
3591 colocate_buf_index);
3592 ret = -8;
3593 }
3594 /* bit 31:30 -- L1[0] picture coding structure,
3595 * 00 - top field, 01 - bottom field,
3596 * 10 - frame, 11 - mbaff frame
3597 * bit 29 - L1[0] top/bot for B field pciture,
3598 * 0 - top, 1 - bot
3599 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3600 * -- only used for B Picture Direct mode
3601 * [2:0] will set to 3'b000
3602 */
3603 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3604 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3605 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3606 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3607 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3608 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3609 val, colocate_pic->structure,
3610 colocate_pic->mb_aff_frame_flag);
3611#endif
3612 }
3613 return ret;
3614}
3615
3616static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3617{
3618 unsigned long flags;
3619 struct vdec_s *vdec = op_arg;
3620 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3621
3622 spin_lock_irqsave(&hw->lock, flags);
3623
3624 states->vf_pool_size = VF_POOL_SIZE;
3625 states->buf_free_num = kfifo_len(&hw->newframe_q);
3626 states->buf_avail_num = kfifo_len(&hw->display_q);
3627
3628 spin_unlock_irqrestore(&hw->lock, flags);
3629
3630 return 0;
3631}
3632
3633static struct vframe_s *vh264_vf_peek(void *op_arg)
3634{
3635 struct vframe_s *vf[2] = {0, 0};
3636 struct vdec_s *vdec = op_arg;
3637 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3638
3639 if (!hw)
3640 return NULL;
3641
3642 if (force_disp_bufspec_num & 0x100) {
3643 if (force_disp_bufspec_num & 0x200)
3644 return NULL;
3645 return &hw->vframe_dummy;
3646 }
3647
3648 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3649 if (vf[1]) {
3650 vf[0]->next_vf_pts_valid = true;
3651 vf[0]->next_vf_pts = vf[1]->pts;
3652 } else
3653 vf[0]->next_vf_pts_valid = false;
3654 return vf[0];
3655 }
3656
3657 return NULL;
3658}
3659
3660static struct vframe_s *vh264_vf_get(void *op_arg)
3661{
3662 struct vframe_s *vf;
3663 struct vdec_s *vdec = op_arg;
3664 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3665
3666 if (!hw)
3667 return NULL;
3668
3669 if (force_disp_bufspec_num & 0x100) {
3670 int buffer_index = force_disp_bufspec_num & 0xff;
3671 if (force_disp_bufspec_num & 0x200)
3672 return NULL;
3673
3674 vf = &hw->vframe_dummy;
3675 vf->duration_pulldown = 0;
3676 vf->pts = 0;
3677 vf->pts_us64 = 0;
3678 set_frame_info(hw, vf, buffer_index);
3679 vf->flag = 0;
3680 if (hw->mmu_enable) {
3681 if (hw->double_write_mode & 0x10) {
3682 /* double write only */
3683 vf->compBodyAddr = 0;
3684 vf->compHeadAddr = 0;
3685 } else {
3686 /*head adr*/
3687 vf->compHeadAddr =
3688 hw->buffer_spec[buffer_index].alloc_header_addr;
3689 /*body adr*/
3690 vf->compBodyAddr = 0;
3691 vf->canvas0Addr = vf->canvas1Addr = 0;
3692 }
3693
3694 vf->type = VIDTYPE_SCATTER;
3695
3696 if (hw->double_write_mode) {
3697 vf->type |= VIDTYPE_PROGRESSIVE
3698 | VIDTYPE_VIU_FIELD;
3699 vf->type |= VIDTYPE_VIU_NV21;
3700 if (hw->double_write_mode == 3)
3701 vf->type |= VIDTYPE_COMPRESS;
3702
3703 vf->canvas0Addr = vf->canvas1Addr = -1;
3704 vf->plane_num = 2;
3705 vf->canvas0_config[0] =
3706 hw->buffer_spec[buffer_index].
3707 canvas_config[0];
3708 vf->canvas0_config[1] =
3709 hw->buffer_spec[buffer_index].
3710 canvas_config[1];
3711
3712 vf->canvas1_config[0] =
3713 hw->buffer_spec[buffer_index].
3714 canvas_config[0];
3715 vf->canvas1_config[1] =
3716 hw->buffer_spec[buffer_index].
3717 canvas_config[1];
3718 } else {
3719 vf->type |=
3720 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3721 vf->canvas0Addr = vf->canvas1Addr = 0;
3722 }
3723 vf->bitdepth =
3724 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3725
3726 vf->compWidth = hw->frame_width;
3727 vf->compHeight = hw->frame_height;
3728
3729 if (hw->double_write_mode) {
3730 vf->width = hw->frame_width /
3731 get_double_write_ratio(hw);
3732 vf->height = hw->frame_height /
3733 get_double_write_ratio(hw);
3734 }
3735 } else {
3736 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3737 VIDTYPE_VIU_NV21;
3738 vf->canvas0Addr = vf->canvas1Addr =
3739 spec2canvas(&hw->buffer_spec[buffer_index]);
3740 }
3741
3742 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3743 hw->bmmu_box, buffer_index);*/
3744 update_vf_memhandle(hw, vf, buffer_index);
3745 force_disp_bufspec_num |= 0x200;
3746 return vf;
3747 }
3748
3749 if (kfifo_get(&hw->display_q, &vf)) {
3750 int time = jiffies;
3751 unsigned int frame_interval =
3752 1000*(time - hw->last_frame_time)/HZ;
3753 struct vframe_s *next_vf;
3754 if (dpb_is_debug(DECODE_ID(hw),
3755 PRINT_FLAG_VDEC_DETAIL)) {
3756 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3757 int frame_index = FRAME_INDEX(vf->index);
3758 if (frame_index < 0 ||
3759 frame_index >= DPB_SIZE_MAX) {
3760 dpb_print(DECODE_ID(hw), 0,
3761 "%s vf index 0x%x error\r\n",
3762 __func__, vf->index);
3763 } else {
3764 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3765 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3766 __func__, BUFSPEC_INDEX(vf->index), vf,
3767 p_H264_Dpb->mFrameStore[frame_index].poc,
3768 vf->duration, vf->pts, frame_interval);
3769 }
3770 }
3771 if (hw->last_frame_time > 0) {
3772 if (frame_interval >
3773 max_get_frame_interval[DECODE_ID(hw)])
3774 max_get_frame_interval[DECODE_ID(hw)]
3775 = frame_interval;
3776 }
3777 hw->last_frame_time = time;
3778 hw->vf_get_count++;
3779 if (kfifo_peek(&hw->display_q, &next_vf)) {
3780 vf->next_vf_pts_valid = true;
3781 vf->next_vf_pts = next_vf->pts;
3782 } else
3783 vf->next_vf_pts_valid = false;
3784 return vf;
3785 }
3786
3787 return NULL;
3788}
3789
3790static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3791{
3792 struct vdec_s *vdec = op_arg;
3793 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3794 int buf_spec_num;
3795 int frame_index;
3796
3797 if (vf == (&hw->vframe_dummy))
3798 return;
3799 if (vf->index == -1) {
3800 dpb_print(DECODE_ID(hw), 0,
3801 "Warning: %s vf %p invalid index\r\n",
3802 __func__, vf);
3803 return;
3804 }
3805 frame_index = FRAME_INDEX(vf->index);
3806 buf_spec_num = BUFSPEC_INDEX(vf->index);
3807 if (frame_index < 0 ||
3808 frame_index >= DPB_SIZE_MAX ||
3809 buf_spec_num < 0 ||
3810 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3811 dpb_print(DECODE_ID(hw), 0,
3812 "%s vf index 0x%x error\r\n",
3813 __func__, vf->index);
3814 return;
3815 }
3816 /*get_buf_spec_idx_by_canvas_config(hw,
3817 &vf->canvas0_config[0]);*/
3818 if (hw->buffer_spec[buf_spec_num].used == 2) {
3819 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3820 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3821 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3822 __func__, vf, frame_index,
3823 p_H264_Dpb->mFrameStore[frame_index].poc,
3824 buf_spec_num,
3825 hw->buffer_spec[buf_spec_num].used,
3826 hw->buffer_spec[buf_spec_num].vf_ref);
3827 hw->buffer_spec[buf_spec_num].vf_ref--;
3828 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3829 set_frame_output_flag(&hw->dpb, frame_index);
3830 } else {
3831 unsigned long flags;
3832 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3833 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3834 __func__, vf, buf_spec_num,
3835 hw->buffer_spec[buf_spec_num].used,
3836 hw->buffer_spec[buf_spec_num].vf_ref);
3837 spin_lock_irqsave(&hw->bufspec_lock, flags);
3838 hw->buffer_spec[buf_spec_num].vf_ref--;
3839 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3840 if (hw->buffer_spec[buf_spec_num].used == 3)
3841 hw->buffer_spec[buf_spec_num].used = 4;
3842 else if (hw->buffer_spec[buf_spec_num].used == 5)
3843 hw->buffer_spec[buf_spec_num].used = 0;
3844 }
3845 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3846 if (dpb_is_debug(DECODE_ID(hw),
3847 PRINT_FLAG_DUMP_BUFSPEC))
3848 dump_bufspec(hw, __func__);
3849
3850 }
3851
3852 hw->vf_put_count++;
3853 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3854
3855#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3856 if (hw->buffer_empty_flag)
3857 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3858}
3859
3860static int vh264_event_cb(int type, void *data, void *op_arg)
3861{
3862 unsigned long flags;
3863 struct vdec_s *vdec = op_arg;
3864 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3865
3866 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3867 struct provider_aux_req_s *req =
3868 (struct provider_aux_req_s *)data;
3869 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3870 spin_lock_irqsave(&hw->lock, flags);
3871 req->aux_buf = NULL;
3872 req->aux_size = 0;
3873 if (buf_spec_num >= 0 &&
3874 buf_spec_num < BUFSPEC_POOL_SIZE &&
3875 is_buf_spec_in_disp_q(hw, buf_spec_num)
3876 ) {
3877 req->aux_buf =
3878 hw->buffer_spec[buf_spec_num].aux_data_buf;
3879 req->aux_size =
3880 hw->buffer_spec[buf_spec_num].aux_data_size;
3881#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3882 req->dv_enhance_exist =
3883 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3884#else
3885 req->dv_enhance_exist = 0;
3886#endif
3887 }
3888 spin_unlock_irqrestore(&hw->lock, flags);
3889
3890 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3891 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3892 __func__, type, buf_spec_num, req->aux_size);
3893 }
3894
3895 return 0;
3896}
3897
3898static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3899 u32 index)
3900{
3901 struct canvas_config_s *p_canvas_config;
3902 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3903 force_rate_framebase : force_rate_streambase;
3904 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3905 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3906 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3907
3908 vf->width = hw->frame_width;
3909 vf->height = hw->frame_height;
3910 if (force_rate) {
3911 if (force_rate == -1)
3912 vf->duration = 0;
3913 else
3914 vf->duration = 96000/force_rate;
3915 } else
3916 vf->duration = hw->frame_dur;
3917 vf->ratio_control =
3918 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3919 DISP_RATIO_ASPECT_RATIO_BIT;
3920 vf->orientation = hw->vh264_rotation;
3921 if (hw->mmu_enable)
3922 return;
3923 vf->canvas0Addr = vf->canvas1Addr = -1;
3924#ifdef NV21
3925 vf->plane_num = 2;
3926#else
3927 vf->plane_num = 3;
3928#endif
3929
3930 if (IS_VDEC_DW(hw)) {
3931 vf->width = (hw->frame_width /2);
3932 if (IS_VDEC_DW(hw) == 2)
3933 vf->height = (hw->frame_height /2);
3934 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3935 } else
3936 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3937
3938 vf->canvas0_config[0] = p_canvas_config[0];
3939 vf->canvas0_config[1] = p_canvas_config[1];
3940#ifndef NV21
3941 vf->canvas0_config[2] = p_canvas_config[2];
3942#endif
3943 vf->canvas1_config[0] = p_canvas_config[0];
3944 vf->canvas1_config[1] = p_canvas_config[1];
3945#ifndef NV21
3946 vf->canvas1_config[2] = p_canvas_config[2];
3947#endif
3948 /* signal_type */
3949 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK)
3950 vf->signal_type = hw->video_signal_from_vui;
3951 else
3952 vf->signal_type = 0;
3953
3954}
3955
3956static void get_picture_qos_info(struct StorablePicture *picture)
3957{
3958 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3959 unsigned char a[3];
3960 unsigned char i, j, t;
3961 unsigned long data;
3962
3963 get_random_bytes(&data, sizeof(unsigned long));
3964 if (picture->slice_type == I_SLICE)
3965 data = 0;
3966 a[0] = data & 0xff;
3967 a[1] = (data >> 8) & 0xff;
3968 a[2] = (data >> 16) & 0xff;
3969
3970 for (i = 0; i < 3; i++)
3971 for (j = i+1; j < 3; j++) {
3972 if (a[j] < a[i]) {
3973 t = a[j];
3974 a[j] = a[i];
3975 a[i] = t;
3976 } else if (a[j] == a[i]) {
3977 a[i]++;
3978 t = a[j];
3979 a[j] = a[i];
3980 a[i] = t;
3981 }
3982 }
3983 picture->max_mv = a[2];
3984 picture->avg_mv = a[1];
3985 picture->min_mv = a[0];
3986 /*
3987 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3988 data, a[0], a[1], a[2]);
3989 */
3990
3991 get_random_bytes(&data, sizeof(unsigned long));
3992 a[0] = data & 0x1f;
3993 a[1] = (data >> 8) & 0x3f;
3994 a[2] = (data >> 16) & 0x7f;
3995
3996 for (i = 0; i < 3; i++)
3997 for (j = i+1; j < 3; j++) {
3998 if (a[j] < a[i]) {
3999 t = a[j];
4000 a[j] = a[i];
4001 a[i] = t;
4002 } else if (a[j] == a[i]) {
4003 a[i]++;
4004 t = a[j];
4005 a[j] = a[i];
4006 a[i] = t;
4007 }
4008 }
4009 picture->max_qp = a[2];
4010 picture->avg_qp = a[1];
4011 picture->min_qp = a[0];
4012 /*
4013 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4014 data, a[0], a[1], a[2]);
4015 */
4016
4017 get_random_bytes(&data, sizeof(unsigned long));
4018 a[0] = data & 0x1f;
4019 a[1] = (data >> 8) & 0x3f;
4020 a[2] = (data >> 16) & 0x7f;
4021
4022 for (i = 0; i < 3; i++)
4023 for (j = i+1; j < 3; j++) {
4024 if (a[j] < a[i]) {
4025 t = a[j];
4026 a[j] = a[i];
4027 a[i] = t;
4028 } else if (a[j] == a[i]) {
4029 a[i]++;
4030 t = a[j];
4031 a[j] = a[i];
4032 a[i] = t;
4033 }
4034 }
4035 picture->max_skip = a[2];
4036 picture->avg_skip = a[1];
4037 picture->min_skip = a[0];
4038
4039
4040 /*
4041 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4042 data,a[0], a[1], a[2]);
4043 */
4044 } else {
4045 uint32_t blk88_y_count;
4046 uint32_t blk88_c_count;
4047 uint32_t blk22_mv_count;
4048 uint32_t rdata32;
4049 int32_t mv_hi;
4050 int32_t mv_lo;
4051 uint32_t rdata32_l;
4052 uint32_t mvx_L0_hi;
4053 uint32_t mvy_L0_hi;
4054 uint32_t mvx_L1_hi;
4055 uint32_t mvy_L1_hi;
4056 int64_t value;
4057 uint64_t temp_value;
4058/*
4059#define DEBUG_QOS
4060*/
4061#ifdef DEBUG_QOS
4062 int pic_number = picture->poc;
4063#endif
4064
4065 picture->max_mv = 0;
4066 picture->avg_mv = 0;
4067 picture->min_mv = 0;
4068
4069 picture->max_skip = 0;
4070 picture->avg_skip = 0;
4071 picture->min_skip = 0;
4072
4073 picture->max_qp = 0;
4074 picture->avg_qp = 0;
4075 picture->min_qp = 0;
4076
4077
4078
4079
4080
4081 /* set rd_idx to 0 */
4082 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4083 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4084 if (blk88_y_count == 0) {
4085#ifdef DEBUG_QOS
4086 pr_info(" [Picture %d Quality] NO Data yet.\n",
4087 pic_number);
4088#endif
4089 /* reset all counts */
4090 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4091 return;
4092 }
4093 /* qp_y_sum */
4094 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4095#ifdef DEBUG_QOS
4096 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4097 pic_number, rdata32/blk88_y_count,
4098 rdata32, blk88_y_count);
4099#endif
4100 picture->avg_qp = rdata32/blk88_y_count;
4101 /* intra_y_count */
4102 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4103#ifdef DEBUG_QOS
4104 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4105 pic_number, rdata32*100/blk88_y_count,
4106 '%', rdata32);
4107#endif
4108 /* skipped_y_count */
4109 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4110#ifdef DEBUG_QOS
4111 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4112 pic_number, rdata32*100/blk88_y_count,
4113 '%', rdata32);
4114#endif
4115 picture->avg_skip = rdata32*100/blk88_y_count;
4116 /* coeff_non_zero_y_count */
4117 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4118#ifdef DEBUG_QOS
4119 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4120 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4121 '%', rdata32);
4122#endif
4123 /* blk66_c_count */
4124 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4125 if (blk88_c_count == 0) {
4126#ifdef DEBUG_QOS
4127 pr_info(" [Picture %d Quality] NO Data yet.\n",
4128 pic_number);
4129#endif
4130 /* reset all counts */
4131 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4132 return;
4133 }
4134 /* qp_c_sum */
4135 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4136#ifdef DEBUG_QOS
4137 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4138 pic_number, rdata32/blk88_c_count,
4139 rdata32, blk88_c_count);
4140#endif
4141 /* intra_c_count */
4142 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4143#ifdef DEBUG_QOS
4144 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4145 pic_number, rdata32*100/blk88_c_count,
4146 '%', rdata32);
4147#endif
4148 /* skipped_cu_c_count */
4149 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4150#ifdef DEBUG_QOS
4151 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4152 pic_number, rdata32*100/blk88_c_count,
4153 '%', rdata32);
4154#endif
4155 /* coeff_non_zero_c_count */
4156 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4157#ifdef DEBUG_QOS
4158 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4159 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4160 '%', rdata32);
4161#endif
4162
4163 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4164 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4165 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4166#ifdef DEBUG_QOS
4167 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4168 pic_number, (rdata32>>0)&0xff);
4169#endif
4170 picture->min_qp = (rdata32>>0)&0xff;
4171
4172#ifdef DEBUG_QOS
4173 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4174 pic_number, (rdata32>>8)&0xff);
4175#endif
4176 picture->max_qp = (rdata32>>8)&0xff;
4177
4178#ifdef DEBUG_QOS
4179 pr_info(" [Picture %d Quality] C QP min : %d\n",
4180 pic_number, (rdata32>>16)&0xff);
4181 pr_info(" [Picture %d Quality] C QP max : %d\n",
4182 pic_number, (rdata32>>24)&0xff);
4183#endif
4184
4185 /* blk22_mv_count */
4186 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4187 if (blk22_mv_count == 0) {
4188#ifdef DEBUG_QOS
4189 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4190 pic_number);
4191#endif
4192 /* reset all counts */
4193 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4194 return;
4195 }
4196 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4197 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4198 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4199 /* should all be 0x00 or 0xff */
4200#ifdef DEBUG_QOS
4201 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4202 pic_number, rdata32);
4203#endif
4204 mvx_L0_hi = ((rdata32>>0)&0xff);
4205 mvy_L0_hi = ((rdata32>>8)&0xff);
4206 mvx_L1_hi = ((rdata32>>16)&0xff);
4207 mvy_L1_hi = ((rdata32>>24)&0xff);
4208
4209 /* mvx_L0_count[31:0] */
4210 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4211 temp_value = mvx_L0_hi;
4212 temp_value = (temp_value << 32) | rdata32_l;
4213
4214 if (mvx_L0_hi & 0x80)
4215 value = 0xFFFFFFF000000000 | temp_value;
4216 else
4217 value = temp_value;
4218 value = div_s64(value, blk22_mv_count);
4219#ifdef DEBUG_QOS
4220 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4221 pic_number, (int)(value),
4222 value, blk22_mv_count);
4223#endif
4224 picture->avg_mv = value;
4225
4226 /* mvy_L0_count[31:0] */
4227 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4228 temp_value = mvy_L0_hi;
4229 temp_value = (temp_value << 32) | rdata32_l;
4230
4231 if (mvy_L0_hi & 0x80)
4232 value = 0xFFFFFFF000000000 | temp_value;
4233 else
4234 value = temp_value;
4235#ifdef DEBUG_QOS
4236 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4237 pic_number, rdata32_l/blk22_mv_count,
4238 value, blk22_mv_count);
4239#endif
4240
4241 /* mvx_L1_count[31:0] */
4242 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4243 temp_value = mvx_L1_hi;
4244 temp_value = (temp_value << 32) | rdata32_l;
4245 if (mvx_L1_hi & 0x80)
4246 value = 0xFFFFFFF000000000 | temp_value;
4247 else
4248 value = temp_value;
4249#ifdef DEBUG_QOS
4250 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4251 pic_number, rdata32_l/blk22_mv_count,
4252 value, blk22_mv_count);
4253#endif
4254
4255 /* mvy_L1_count[31:0] */
4256 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4257 temp_value = mvy_L1_hi;
4258 temp_value = (temp_value << 32) | rdata32_l;
4259 if (mvy_L1_hi & 0x80)
4260 value = 0xFFFFFFF000000000 | temp_value;
4261 else
4262 value = temp_value;
4263#ifdef DEBUG_QOS
4264 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4265 pic_number, rdata32_l/blk22_mv_count,
4266 value, blk22_mv_count);
4267#endif
4268
4269 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4270 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4271 mv_hi = (rdata32>>16)&0xffff;
4272 if (mv_hi & 0x8000)
4273 mv_hi = 0x8000 - mv_hi;
4274#ifdef DEBUG_QOS
4275 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4276 pic_number, mv_hi);
4277#endif
4278 picture->max_mv = mv_hi;
4279
4280 mv_lo = (rdata32>>0)&0xffff;
4281 if (mv_lo & 0x8000)
4282 mv_lo = 0x8000 - mv_lo;
4283#ifdef DEBUG_QOS
4284 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4285 pic_number, mv_lo);
4286#endif
4287 picture->min_mv = mv_lo;
4288
4289 /* {mvy_L0_max, mvy_L0_min} */
4290 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4291 mv_hi = (rdata32>>16)&0xffff;
4292 if (mv_hi & 0x8000)
4293 mv_hi = 0x8000 - mv_hi;
4294#ifdef DEBUG_QOS
4295 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4296 pic_number, mv_hi);
4297#endif
4298
4299 mv_lo = (rdata32>>0)&0xffff;
4300 if (mv_lo & 0x8000)
4301 mv_lo = 0x8000 - mv_lo;
4302#ifdef DEBUG_QOS
4303 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4304 pic_number, mv_lo);
4305#endif
4306
4307 /* {mvx_L1_max, mvx_L1_min} */
4308 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4309 mv_hi = (rdata32>>16)&0xffff;
4310 if (mv_hi & 0x8000)
4311 mv_hi = 0x8000 - mv_hi;
4312#ifdef DEBUG_QOS
4313 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4314 pic_number, mv_hi);
4315#endif
4316
4317 mv_lo = (rdata32>>0)&0xffff;
4318 if (mv_lo & 0x8000)
4319 mv_lo = 0x8000 - mv_lo;
4320#ifdef DEBUG_QOS
4321 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4322 pic_number, mv_lo);
4323#endif
4324
4325 /* {mvy_L1_max, mvy_L1_min} */
4326 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4327 mv_hi = (rdata32>>16)&0xffff;
4328 if (mv_hi & 0x8000)
4329 mv_hi = 0x8000 - mv_hi;
4330#ifdef DEBUG_QOS
4331 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4332 pic_number, mv_hi);
4333#endif
4334 mv_lo = (rdata32>>0)&0xffff;
4335 if (mv_lo & 0x8000)
4336 mv_lo = 0x8000 - mv_lo;
4337#ifdef DEBUG_QOS
4338 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4339 pic_number, mv_lo);
4340#endif
4341
4342 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4343#ifdef DEBUG_QOS
4344 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4345 pic_number, rdata32);
4346#endif
4347 /* reset all counts */
4348 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4349 }
4350}
4351
4352static int get_max_dec_frame_buf_size(int level_idc,
4353 int max_reference_frame_num, int mb_width,
4354 int mb_height)
4355{
4356 int pic_size = mb_width * mb_height * 384;
4357
4358 int size = 0;
4359
4360 switch (level_idc) {
4361 case 9:
4362 size = 152064;
4363 break;
4364 case 10:
4365 size = 152064;
4366 break;
4367 case 11:
4368 size = 345600;
4369 break;
4370 case 12:
4371 size = 912384;
4372 break;
4373 case 13:
4374 size = 912384;
4375 break;
4376 case 20:
4377 size = 912384;
4378 break;
4379 case 21:
4380 size = 1824768;
4381 break;
4382 case 22:
4383 size = 3110400;
4384 break;
4385 case 30:
4386 size = 3110400;
4387 break;
4388 case 31:
4389 size = 6912000;
4390 break;
4391 case 32:
4392 size = 7864320;
4393 break;
4394 case 40:
4395 size = 12582912;
4396 break;
4397 case 41:
4398 size = 12582912;
4399 break;
4400 case 42:
4401 size = 13369344;
4402 break;
4403 case 50:
4404 size = 42393600;
4405 break;
4406 case 51:
4407 case 52:
4408 default:
4409 size = 70778880;
4410 break;
4411 }
4412
4413 size /= pic_size;
4414 size = size + 1; /* need one more buffer */
4415
4416 if (max_reference_frame_num > size)
4417 size = max_reference_frame_num;
4418 size = imin(size, 16);
4419
4420 return size;
4421}
4422
4423static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4424{
4425 int i, j;
4426
4427 if (hw->double_write_mode) {
4428 mutex_lock(&vmh264_mutex);
4429 if (hw->decode_pic_count == 0) {
4430 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4431 i = get_buf_spec_by_canvas_pos(hw, j);
4432 if (i >= 0)
4433 config_decode_canvas_ex(hw, i);
4434 }
4435 }
4436 mutex_unlock(&vmh264_mutex);
4437 }
4438}
4439
4440static int vh264_set_params(struct vdec_h264_hw_s *hw,
4441 u32 param1, u32 param2, u32 param3, u32 param4)
4442{
4443 int i, j;
4444 int mb_width, mb_total;
4445 int max_reference_size, level_idc;
4446 int mb_height = 0;
4447 unsigned long flags;
4448 /*int mb_mv_byte;*/
4449 struct vdec_s *vdec = hw_to_vdec(hw);
4450 u32 seq_info2;
4451 int ret = 0;
4452 int active_buffer_spec_num;
4453 unsigned int buf_size;
4454 unsigned int frame_mbs_only_flag;
4455 unsigned int chroma_format_idc, chroma444;
4456 unsigned int crop_infor, crop_bottom, crop_right;
4457 unsigned int used_reorder_dpb_size_margin
4458 = reorder_dpb_size_margin;
4459 u8 *colocate_vaddr = NULL;
4460
4461#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4462 if (vdec->master || vdec->slave)
4463 used_reorder_dpb_size_margin =
4464 reorder_dpb_size_margin_dv;
4465#endif
4466 seq_info2 = param1;
4467 hw->seq_info = param2;
4468
4469 mb_width = seq_info2 & 0xff;
4470 mb_total = (seq_info2 >> 8) & 0xffff;
4471 if (!mb_width && mb_total) /*for 4k2k*/
4472 mb_width = 256;
4473 if (mb_width)
4474 mb_height = mb_total/mb_width;
4475 if (mb_width <= 0 || mb_height <= 0 ||
4476 is_oversize(mb_width << 4, mb_height << 4)) {
4477 dpb_print(DECODE_ID(hw), 0,
4478 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4479 seq_info2,
4480 mb_width,
4481 mb_height);
4482 return -1;
4483 }
4484
4485 if (seq_info2 != 0 &&
4486 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4487 hw->seq_info2 != 0
4488 ) /*picture size changed*/
4489 h264_reconfig(hw);
4490
4491 if (hw->config_bufmgr_done == 0) {
4492 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4493 u32 reg_val;
4494 hw->cfg_param1 = param1;
4495 hw->cfg_param2 = param2;
4496 hw->cfg_param3 = param3;
4497 hw->cfg_param4 = param4;
4498
4499 hw->seq_info2 = seq_info2 & (~0x80000000);
4500 dpb_print(DECODE_ID(hw), 0,
4501 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4502 seq_info2, hw->seq_info);
4503
4504 dpb_init_global(&hw->dpb,
4505 DECODE_ID(hw), 0, 0);
4506
4507 p_H264_Dpb->fast_output_enable = fast_output_enable;
4508 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4509
4510#if 1
4511 /*crop*/
4512 /* AV_SCRATCH_2
4513 bit 15: frame_mbs_only_flag
4514 bit 13-14: chroma_format_idc */
4515 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4516 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4517 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4518
4519 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4520 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4521 (2 - frame_mbs_only_flag) */
4522 crop_infor = param3;
4523 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4524 crop_right = ((crop_infor >> 16) & 0xff)
4525 >> (2 - frame_mbs_only_flag);
4526
4527 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4528 hw->frame_width = mb_width << 4;
4529 hw->frame_height = mb_height << 4;
4530 if (frame_mbs_only_flag) {
4531 hw->frame_height =
4532 hw->frame_height - (2 >> chroma444) *
4533 min(crop_bottom,
4534 (unsigned int)((8 << chroma444) - 1));
4535 hw->frame_width =
4536 hw->frame_width -
4537 (2 >> chroma444) * min(crop_right,
4538 (unsigned
4539 int)((8 << chroma444) - 1));
4540 } else {
4541 hw->frame_height =
4542 hw->frame_height - (4 >> chroma444) *
4543 min(crop_bottom,
4544 (unsigned int)((8 << chroma444)
4545 - 1));
4546 hw->frame_width =
4547 hw->frame_width -
4548 (4 >> chroma444) * min(crop_right,
4549 (unsigned int)((8 << chroma444) - 1));
4550 }
4551 dpb_print(DECODE_ID(hw), 0,
4552 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4553 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4554 dpb_print(DECODE_ID(hw), 0,
4555 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4556 mb_height, crop_right,
4557 hw->frame_width, mb_width);
4558
4559 if (hw->frame_height == 1088)
4560 hw->frame_height = 1080;
4561#endif
4562 if (!hw->mmu_enable) {
4563 mb_width = (mb_width+3) & 0xfffffffc;
4564 mb_height = (mb_height+3) & 0xfffffffc;
4565 }
4566 mb_total = mb_width * mb_height;
4567 hw->mb_width = mb_width;
4568 hw->mb_height = mb_height;
4569 hw->mb_total = mb_total;
4570 if (hw->mmu_enable)
4571 hevc_mcr_sao_global_hw_init(hw,
4572 (hw->mb_width << 4), (hw->mb_height << 4));
4573
4574 reg_val = param4;
4575 level_idc = reg_val & 0xff;
4576 max_reference_size = (reg_val >> 8) & 0xff;
4577 hw->dpb.origin_max_reference = max_reference_size;
4578 dpb_print(DECODE_ID(hw), 0,
4579 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4580 mb_height, mb_width, mb_total,
4581 level_idc, max_reference_size);
4582
4583
4584 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4585 hw->dpb.reorder_pic_num =
4586 get_max_dec_frame_buf_size(level_idc,
4587 max_reference_size, mb_width, mb_height);
4588
4589 dpb_print(DECODE_ID(hw), 0,
4590 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4591 hw->bitstream_restriction_flag,
4592 hw->max_dec_frame_buffering,
4593 hw->dpb.reorder_pic_num);
4594
4595 if ((hw->bitstream_restriction_flag) &&
4596 (hw->max_dec_frame_buffering <
4597 hw->dpb.reorder_pic_num)) {
4598 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4599 dpb_print(DECODE_ID(hw), 0,
4600 "set reorder_pic_num to %d\n",
4601 hw->dpb.reorder_pic_num);
4602 }
4603
4604 active_buffer_spec_num =
4605 hw->dpb.reorder_pic_num
4606 + used_reorder_dpb_size_margin;
4607 hw->max_reference_size =
4608 max_reference_size + reference_buf_margin;
4609
4610 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4611 active_buffer_spec_num = MAX_VF_BUF_NUM;
4612 hw->dpb.reorder_pic_num = active_buffer_spec_num
4613 - used_reorder_dpb_size_margin;
4614 }
4615 hw->dpb.mDPB.size = active_buffer_spec_num;
4616 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4617 hw->max_reference_size = MAX_VF_BUF_NUM;
4618 hw->dpb.max_reference_size = hw->max_reference_size;
4619
4620 if (hw->no_poc_reorder_flag)
4621 hw->dpb.reorder_pic_num = 1;
4622 dpb_print(DECODE_ID(hw), 0,
4623 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4624 __func__, active_buffer_spec_num,
4625 hw->dpb.reorder_pic_num,
4626 hw->max_reference_size);
4627
4628 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4629
4630 mutex_lock(&vmh264_mutex);
4631 if (!hw->mmu_enable) {
4632 config_buf_specs(vdec);
4633 i = get_buf_spec_by_canvas_pos(hw, 0);
4634
4635 if (hw->is_used_v4l) {
4636 if (i != -1) {
4637 pr_info("alloc the buf of v4l when it is about to decoding.\n");
4638 }
4639 } else {
4640 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4641 config_decode_canvas(hw, i);
4642 else
4643 ret = -1;
4644 }
4645 } else {
4646 if (hw->double_write_mode) {
4647 config_buf_specs_ex(vdec);
4648 } else {
4649 spin_lock_irqsave(&hw->bufspec_lock, flags);
4650 for (i = 0, j = 0;
4651 j < active_buffer_spec_num
4652 && i < BUFSPEC_POOL_SIZE;
4653 i++) {
4654 if (hw->buffer_spec[i].used != -1)
4655 continue;
4656 hw->buffer_spec[i].used = 0;
4657 hw->buffer_spec[i].
4658 alloc_header_addr = 0;
4659 hw->buffer_spec[i].canvas_pos = j;
4660 j++;
4661 }
4662 spin_unlock_irqrestore(&hw->bufspec_lock,
4663 flags);
4664 }
4665 hevc_mcr_config_canv2axitbl(hw, 0);
4666 }
4667 mutex_unlock(&vmh264_mutex);
4668 if (dpb_is_debug(DECODE_ID(hw),
4669 PRINT_FLAG_DUMP_BUFSPEC))
4670 dump_bufspec(hw, __func__);
4671
4672#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4673 buf_size = PAGE_ALIGN(
4674 p_H264_Dpb->colocated_buf_size *
4675 active_buffer_spec_num);
4676#else
4677 buf_size = PAGE_ALIGN(
4678 p_H264_Dpb->colocated_buf_size *
4679 hw->max_reference_size);
4680#endif
4681
4682 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4683 buf_size, DRIVER_NAME,
4684 &hw->collocate_cma_alloc_addr) < 0)
4685 return -1;
4686 if (!vdec_secure(vdec)) {
4687 /* clear for some mosaic problem after reset bufmgr */
4688 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4689 if (colocate_vaddr != NULL) {
4690 memset(colocate_vaddr, 0, buf_size);
4691 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4692 codec_mm_unmap_phyaddr(colocate_vaddr);
4693 }
4694 }
4695
4696 hw->dpb.colocated_mv_addr_start =
4697 hw->collocate_cma_alloc_addr;
4698#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4699 hw->dpb.colocated_mv_addr_end =
4700 hw->dpb.colocated_mv_addr_start +
4701 (p_H264_Dpb->colocated_buf_size *
4702 active_buffer_spec_num);
4703#else
4704 hw->dpb.colocated_mv_addr_end =
4705 hw->dpb.colocated_mv_addr_start +
4706 (p_H264_Dpb->colocated_buf_size *
4707 hw->max_reference_size);
4708#endif
4709 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4710 "callocate cma, %lx, %x\n",
4711 hw->collocate_cma_alloc_addr,
4712 hw->dpb.colocated_mv_addr_start);
4713
4714 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4715 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4716 hw->dpb.colocated_mv_addr_start,
4717 hw->dpb.colocated_mv_addr_end);
4718 if (!hw->mmu_enable) {
4719 mutex_lock(&vmh264_mutex);
4720 if (ret >= 0 && hw->decode_pic_count == 0) {
4721 int buf_cnt;
4722 /* h264_reconfig: alloc later*/
4723 buf_cnt = hw->dpb.mDPB.size;
4724
4725 for (j = 1; j < buf_cnt; j++) {
4726 i = get_buf_spec_by_canvas_pos(hw, j);
4727
4728 if (hw->is_used_v4l) {
4729 pr_info("alloc the buf of v4l when it is about to decoding.\n");
4730 break;
4731 } else if (alloc_one_buf_spec(hw, i) < 0)
4732 break;
4733
4734 config_decode_canvas(hw, i);
4735 }
4736 }
4737 mutex_unlock(&vmh264_mutex);
4738 } else {
4739 vh264_config_canvs_for_mmu(hw);
4740 }
4741
4742 hw->config_bufmgr_done = 1;
4743
4744 /*end of config_bufmgr_done */
4745 }
4746
4747 return ret;
4748}
4749
4750static void vui_config(struct vdec_h264_hw_s *hw)
4751{
4752 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4753 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4754 /*time*/
4755 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4756 hw->time_scale = p_H264_Dpb->time_scale;
4757 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4758
4759 hw->bitstream_restriction_flag =
4760 p_H264_Dpb->bitstream_restriction_flag;
4761 hw->num_reorder_frames =
4762 p_H264_Dpb->num_reorder_frames;
4763 hw->max_dec_frame_buffering =
4764 p_H264_Dpb->max_dec_frame_buffering;
4765
4766 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4767 "vui_config: pdb %d, %d, %d\n",
4768 p_H264_Dpb->bitstream_restriction_flag,
4769 p_H264_Dpb->num_reorder_frames,
4770 p_H264_Dpb->max_dec_frame_buffering);
4771
4772 hw->fixed_frame_rate_flag = 0;
4773 if (hw->timing_info_present_flag) {
4774 hw->fixed_frame_rate_flag =
4775 p_H264_Dpb->fixed_frame_rate_flag;
4776
4777 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4778 ((!hw->sync_outside) ||
4779 (!hw->frame_dur)))
4780 && hw->num_units_in_tick && hw->time_scale) {
4781 if (hw->use_idr_framerate ||
4782 hw->fixed_frame_rate_flag ||
4783 !hw->frame_dur ||
4784 !hw->duration_from_pts_done
4785 /*|| vh264_running*/) {
4786 u32 frame_dur_es =
4787 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4788 hw->time_scale);
4789 if (hw->frame_dur != frame_dur_es) {
4790 hw->h264_first_valid_pts_ready = false;
4791 hw->h264pts1 = 0;
4792 hw->h264pts2 = 0;
4793 hw->h264_pts_count = 0;
4794 hw->duration_from_pts_done = 0;
4795 fixed_frame_rate_mode =
4796 FIX_FRAME_RATE_OFF;
4797 hw->pts_duration = 0;
4798 hw->frame_dur = frame_dur_es;
4799 vdec_schedule_work(&hw->notify_work);
4800 dpb_print(DECODE_ID(hw),
4801 PRINT_FLAG_DEC_DETAIL,
4802 "frame_dur %d from timing_info\n",
4803 hw->frame_dur);
4804 }
4805
4806 /*hack to avoid use ES frame duration when
4807 *it's half of the rate from system info
4808 * sometimes the encoder is given a wrong
4809 * frame rate but the system side information
4810 * is more reliable
4811 *if ((frame_dur * 2) != frame_dur_es) {
4812 * frame_dur = frame_dur_es;
4813 *}
4814 */
4815 }
4816 }
4817 } else {
4818 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4819 "H.264: timing_info not present\n");
4820 }
4821
4822 /*aspect ratio*/
4823 aspect_ratio_info_present_flag =
4824 p_H264_Dpb->vui_status & 0x1;
4825 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4826
4827 if (aspect_ratio_info_present_flag) {
4828 if (aspect_ratio_idc == EXTEND_SAR) {
4829 hw->h264_ar = 0x3ff;
4830 hw->height_aspect_ratio =
4831 p_H264_Dpb->aspect_ratio_sar_height;
4832 hw->width_aspect_ratio =
4833 p_H264_Dpb->aspect_ratio_sar_width;
4834 } else {
4835 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4836 aspect_ratio_idc); */
4837
4838 switch (aspect_ratio_idc) {
4839 case 1:
4840 hw->h264_ar = 0x3ff;
4841 hw->height_aspect_ratio = 1;
4842 hw->width_aspect_ratio = 1;
4843 break;
4844 case 2:
4845 hw->h264_ar = 0x3ff;
4846 hw->height_aspect_ratio = 11;
4847 hw->width_aspect_ratio = 12;
4848 break;
4849 case 3:
4850 hw->h264_ar = 0x3ff;
4851 hw->height_aspect_ratio = 11;
4852 hw->width_aspect_ratio = 10;
4853 break;
4854 case 4:
4855 hw->h264_ar = 0x3ff;
4856 hw->height_aspect_ratio = 11;
4857 hw->width_aspect_ratio = 16;
4858 break;
4859 case 5:
4860 hw->h264_ar = 0x3ff;
4861 hw->height_aspect_ratio = 33;
4862 hw->width_aspect_ratio = 40;
4863 break;
4864 case 6:
4865 hw->h264_ar = 0x3ff;
4866 hw->height_aspect_ratio = 11;
4867 hw->width_aspect_ratio = 24;
4868 break;
4869 case 7:
4870 hw->h264_ar = 0x3ff;
4871 hw->height_aspect_ratio = 11;
4872 hw->width_aspect_ratio = 20;
4873 break;
4874 case 8:
4875 hw->h264_ar = 0x3ff;
4876 hw->height_aspect_ratio = 11;
4877 hw->width_aspect_ratio = 32;
4878 break;
4879 case 9:
4880 hw->h264_ar = 0x3ff;
4881 hw->height_aspect_ratio = 33;
4882 hw->width_aspect_ratio = 80;
4883 break;
4884 case 10:
4885 hw->h264_ar = 0x3ff;
4886 hw->height_aspect_ratio = 11;
4887 hw->width_aspect_ratio = 18;
4888 break;
4889 case 11:
4890 hw->h264_ar = 0x3ff;
4891 hw->height_aspect_ratio = 11;
4892 hw->width_aspect_ratio = 15;
4893 break;
4894 case 12:
4895 hw->h264_ar = 0x3ff;
4896 hw->height_aspect_ratio = 33;
4897 hw->width_aspect_ratio = 64;
4898 break;
4899 case 13:
4900 hw->h264_ar = 0x3ff;
4901 hw->height_aspect_ratio = 99;
4902 hw->width_aspect_ratio = 160;
4903 break;
4904 case 14:
4905 hw->h264_ar = 0x3ff;
4906 hw->height_aspect_ratio = 3;
4907 hw->width_aspect_ratio = 4;
4908 break;
4909 case 15:
4910 hw->h264_ar = 0x3ff;
4911 hw->height_aspect_ratio = 2;
4912 hw->width_aspect_ratio = 3;
4913 break;
4914 case 16:
4915 hw->h264_ar = 0x3ff;
4916 hw->height_aspect_ratio = 1;
4917 hw->width_aspect_ratio = 2;
4918 break;
4919 default:
4920 if (hw->vh264_ratio >> 16) {
4921 hw->h264_ar = (hw->frame_height *
4922 (hw->vh264_ratio & 0xffff) *
4923 0x100 +
4924 ((hw->vh264_ratio >> 16) *
4925 hw->frame_width / 2)) /
4926 ((hw->vh264_ratio >> 16) *
4927 hw->frame_width);
4928 hw->height_aspect_ratio = 1;
4929 hw->width_aspect_ratio = 1;
4930 } else {
4931 hw->h264_ar = 0x3ff;
4932 hw->height_aspect_ratio = 1;
4933 hw->width_aspect_ratio = 1;
4934 }
4935 break;
4936 }
4937 }
4938 } else {
4939 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4940 "v264dec: aspect_ratio not available from source\n");
4941 if (hw->vh264_ratio >> 16) {
4942 /* high 16 bit is width, low 16 bit is height */
4943 hw->h264_ar =
4944 ((hw->vh264_ratio & 0xffff) *
4945 hw->frame_height * 0x100 +
4946 (hw->vh264_ratio >> 16) *
4947 hw->frame_width / 2) /
4948 ((hw->vh264_ratio >> 16) *
4949 hw->frame_width);
4950 hw->height_aspect_ratio = 1;
4951 hw->width_aspect_ratio = 1;
4952 } else {
4953 hw->h264_ar = 0x3ff;
4954 hw->height_aspect_ratio = 1;
4955 hw->width_aspect_ratio = 1;
4956 }
4957 }
4958
4959 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4960 if (((hw->frame_dur == RATE_2397_FPS)
4961 && (dec_control
4962 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4963 || ((RATE_2997_FPS ==
4964 hw->frame_dur) &&
4965 (dec_control &
4966 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4967 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4968 "force fix frame rate\n");
4969 hw->fixed_frame_rate_flag = 0x40;
4970 }
4971 }
4972
4973 /*video_signal_from_vui: to do .. */
4974}
4975
4976static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4977{
4978 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4979
4980 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4981 if (error_proc_policy & 0x20) {
4982 if (!hw->is_used_v4l)
4983 hw->reset_bufmgr_flag = 1;
4984 }
4985}
4986
4987void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4988{
4989 struct vdec_h264_hw_s *hw =
4990 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4991
4992 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4993
4994 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4995 hw->reset_bufmgr_flag = 1;
4996}
4997
4998#ifdef CONSTRAIN_MAX_BUF_NUM
4999static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5000{
5001 int i;
5002 int count = 0;
5003 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5004 if (is_buf_spec_in_disp_q(hw, i) &&
5005 hw->buffer_spec[i].vf_ref > 0)
5006 count++;
5007 }
5008 return count;
5009}
5010
5011static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5012{
5013 int i;
5014 int count = 0;
5015 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5016 if (is_buf_spec_in_use(hw, i))
5017 count++;
5018 }
5019 return count;
5020}
5021#endif
5022
5023
5024static bool is_buffer_available(struct vdec_s *vdec)
5025{
5026 bool buffer_available = 1;
5027 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5028 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5029 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5030 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5031 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5032 ((p_H264_Dpb->mDPB.init_done) &&
5033 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5034 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5035 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5036 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5037 __func__,
5038 kfifo_len(&hw->newframe_q),
5039 have_free_buf_spec(vdec),
5040 p_H264_Dpb->mDPB.init_done,
5041 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5042 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5043 );
5044 buffer_available = 0;
5045 if (dpb_is_debug(DECODE_ID(hw),
5046 DEBUG_DISABLE_RUNREADY_RMBUF))
5047 return buffer_available;
5048
5049 if ((error_proc_policy & 0x4) &&
5050 (error_proc_policy & 0x8)) {
5051 if ((kfifo_len(&hw->display_q) <= 0) &&
5052 (p_H264_Dpb->mDPB.used_size ==
5053 p_H264_Dpb->mDPB.size) &&
5054 (p_Dpb->ref_frames_in_buffer >
5055 (imax(
5056 1, p_Dpb->num_ref_frames)
5057 - p_Dpb->ltref_frames_in_buffer +
5058 force_sliding_margin)))
5059 bufmgr_recover(hw);
5060 else
5061 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5062 } else if ((error_proc_policy & 0x4) &&
5063 (kfifo_len(&hw->display_q) <= 0) &&
5064 ((p_H264_Dpb->mDPB.used_size ==
5065 p_H264_Dpb->mDPB.size) ||
5066 (!have_free_buf_spec(vdec)))) {
5067 enum receviver_start_e state = RECEIVER_INACTIVE;
5068 if ((error_proc_policy & 0x10) &&
5069 vf_get_receiver(vdec->vf_provider_name)) {
5070 state =
5071 vf_notify_receiver(vdec->vf_provider_name,
5072 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5073 NULL);
5074 if ((state == RECEIVER_STATE_NULL)
5075 || (state == RECEIVER_STATE_NONE))
5076 state = RECEIVER_INACTIVE;
5077 }
5078 if (state == RECEIVER_INACTIVE)
5079 bufmgr_recover(hw);
5080 else
5081 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5082 } else if ((error_proc_policy & 0x8) &&
5083 (p_Dpb->ref_frames_in_buffer >
5084 (imax(
5085 1, p_Dpb->num_ref_frames)
5086 - p_Dpb->ltref_frames_in_buffer +
5087 force_sliding_margin)))
5088 bufmgr_recover(hw);
5089 else
5090 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5091
5092 if (hw->reset_bufmgr_flag == 1)
5093 buffer_available = 1;
5094 }
5095
5096 return buffer_available;
5097}
5098
5099#define AUX_TAG_SEI 0x2
5100
5101#define SEI_BUFFERING_PERIOD 0
5102#define SEI_PicTiming 1
5103#define SEI_USER_DATA 4
5104#define SEI_RECOVERY_POINT 6
5105
5106/*
5107 *************************************************************************
5108 * Function:Reads bits from the bitstream buffer
5109 * Input:
5110 byte buffer[]
5111 containing sei message data bits
5112 int totbitoffset
5113 bit offset from start of partition
5114 int bytecount
5115 total bytes in bitstream
5116 int numbits
5117 number of bits to read
5118 * Output:
5119 int *info
5120 * Return:
5121 -1: failed
5122 > 0: the count of bit read
5123 * Attention:
5124 *************************************************************************
5125 */
5126
5127static int get_bits(unsigned char buffer[],
5128 int totbitoffset,
5129 int *info,
5130 int bytecount,
5131 int numbits)
5132{
5133 register int inf;
5134 long byteoffset;
5135 int bitoffset;
5136
5137 int bitcounter = numbits;
5138
5139 byteoffset = totbitoffset / 8;
5140 bitoffset = 7 - (totbitoffset % 8);
5141
5142 inf = 0;
5143 while (numbits) {
5144 inf <<= 1;
5145 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5146 numbits--;
5147 bitoffset--;
5148 if (bitoffset < 0) {
5149 byteoffset++;
5150 bitoffset += 8;
5151 if (byteoffset > bytecount)
5152 return -1;
5153 }
5154 }
5155
5156 *info = inf;
5157
5158
5159 return bitcounter;
5160}
5161
5162static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5163 u8 *sei_data_buf,
5164 u8 *sei_data_buf_end)
5165{
5166 int payload_type;
5167 int payload_size;
5168 u8 *p_sei;
5169 int temp = 0;
5170 int bit_offset;
5171 int read_size;
5172 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5173
5174 p_sei = sei_data_buf;
5175 read_size = 0;
5176 payload_type = 0;
5177 do {
5178 if (p_sei >= sei_data_buf_end)
5179 return read_size;
5180
5181 payload_type += *p_sei;
5182 read_size++;
5183 } while (*p_sei++ == 255);
5184
5185
5186 payload_size = 0;
5187 do {
5188 if (p_sei >= sei_data_buf_end)
5189 return read_size;
5190
5191 payload_size += *p_sei;
5192 read_size++;
5193 } while (*p_sei++ == 255);
5194
5195
5196 if (p_sei + payload_size > sei_data_buf_end) {
5197 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5198 "%s: payload_type = %d, payload_size = %d is over\n",
5199 __func__, payload_type, payload_size);
5200 return read_size;
5201 }
5202 bit_offset = 0;
5203
5204 if (payload_size <= 0) {
5205 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5206 "%s warning: this is a null sei message for payload_type = %d\n",
5207 __func__, payload_type);
5208 return read_size;
5209 }
5210 switch (payload_type) {
5211 case SEI_BUFFERING_PERIOD:
5212 break;
5213 case SEI_PicTiming:
5214 if (p_H264_Dpb->vui_status & 0xc) {
5215 int cpb_removal_delay;
5216 int dpb_output_delay;
5217 u32 delay_len;
5218
5219 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5220 cpb_removal_delay
5221 = (delay_len & 0x1F) + 1;
5222 dpb_output_delay
5223 = ((delay_len >> 5) & 0x1F) + 1;
5224
5225 get_bits(p_sei, bit_offset,
5226 &temp, payload_size,
5227 dpb_output_delay+cpb_removal_delay);
5228 bit_offset += dpb_output_delay+cpb_removal_delay;
5229 }
5230 if (p_H264_Dpb->vui_status & 0x10) {
5231 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5232 bit_offset += 4;
5233 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5234 }
5235 break;
5236 case SEI_USER_DATA:
5237 if (enable_itu_t35) {
5238 int i;
5239 int j;
5240 int data_len;
5241 u8 *user_data_buf;
5242
5243 user_data_buf
5244 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5245 /* user data length should be align with 8 bytes,
5246 if not, then padding with zero*/
5247 for (i = 0; i < payload_size; i += 8) {
5248 for (j = 0; j < 8; j++) {
5249 int index;
5250
5251 index = i+7-j;
5252 if (index >= payload_size)
5253 user_data_buf[i+j] = 0;
5254 else
5255 user_data_buf[i+j]
5256 = p_sei[i+7-j];
5257 }
5258 }
5259
5260 data_len = payload_size;
5261 if (payload_size % 8)
5262 data_len = ((payload_size + 8) >> 3) << 3;
5263
5264 hw->sei_itu_data_len += data_len;
5265 /*
5266 dpb_print(DECODE_ID(hw), 0,
5267 "%s: user data, and len = %d:\n",
5268 __func__, hw->sei_itu_data_len);
5269 */
5270 }
5271 break;
5272 case SEI_RECOVERY_POINT:
5273 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5274 break;
5275 }
5276
5277 return read_size + payload_size;
5278}
5279
5280static void parse_sei_data(struct vdec_h264_hw_s *hw,
5281 u8 *sei_data_buf,
5282 int len)
5283{
5284 char *p_sei;
5285 char *p_sei_end;
5286 int parsed_size;
5287 int read_size;
5288
5289
5290 p_sei = sei_data_buf;
5291 p_sei_end = p_sei + len;
5292 parsed_size = 0;
5293 while (parsed_size < len) {
5294 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5295 p_sei += read_size;
5296 parsed_size += read_size;
5297 if (*p_sei == 0x80) {
5298 p_sei++;
5299 parsed_size++;
5300 }
5301 }
5302}
5303
5304static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5305{
5306 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5307 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5308 unsigned mby_mbx = READ_VREG(MBY_MBX);
5309 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5310 unsigned decode_mb_count =
5311 ((mby_mbx & 0xff) * hw->mb_width +
5312 (((mby_mbx >> 8) & 0xff) + 1));
5313 if (mby_mbx == 0)
5314 return;
5315 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5316 mb_total /= 2;
5317 if (error_proc_policy & 0x100) {
5318 if (decode_mb_count < mb_total)
5319 p->data_flag |= ERROR_FLAG;
5320 }
5321
5322 if ((error_proc_policy & 0x200) &&
5323 READ_VREG(ERROR_STATUS_REG) != 0) {
5324 p->data_flag |= ERROR_FLAG;
5325 }
5326
5327 if (p->data_flag & ERROR_FLAG) {
5328 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5329 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5330 __func__,
5331 hw->seq_info2,
5332 mby_mbx,
5333 mb_total,
5334 decode_mb_count,
5335 READ_VREG(ERROR_STATUS_REG)
5336 );
5337
5338 }
5339}
5340
5341static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5342{
5343 int i;
5344 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5345 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5346 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5347 u32 debug_tag;
5348 int ret;
5349
5350 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5351#if 1
5352 unsigned short *p = (unsigned short *)hw->lmem_addr;
5353 dma_sync_single_for_cpu(
5354 amports_get_dma_device(),
5355 hw->lmem_addr_remap,
5356 PAGE_SIZE,
5357 DMA_FROM_DEVICE);
5358 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5359 int ii;
5360 for (ii = 0; ii < 4; ii++) {
5361 p_H264_Dpb->dpb_param.l.data[i+ii] =
5362 p[i+3-ii];
5363 if (dpb_is_debug(DECODE_ID(hw),
5364 RRINT_FLAG_RPM)) {
5365 if (((i + ii) & 0xf) == 0)
5366 dpb_print(DECODE_ID(hw),
5367 0, "%04x:",
5368 i);
5369 dpb_print_cont(DECODE_ID(hw),
5370 0, "%04x ",
5371 p[i+3-ii]);
5372 if (((i + ii + 1) & 0xf) == 0)
5373 dpb_print_cont(
5374 DECODE_ID(hw),
5375 0, "\r\n");
5376 }
5377 }
5378 }
5379
5380 p_H264_Dpb->bitstream_restriction_flag =
5381 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5382 p_H264_Dpb->num_reorder_frames =
5383 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5384 p_H264_Dpb->max_dec_frame_buffering =
5385 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5386
5387 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5388 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5389 p_H264_Dpb->bitstream_restriction_flag,
5390 p_H264_Dpb->num_reorder_frames,
5391 p_H264_Dpb->max_dec_frame_buffering);
5392 hw->bitstream_restriction_flag =
5393 p_H264_Dpb->bitstream_restriction_flag;
5394 hw->num_reorder_frames =
5395 p_H264_Dpb->num_reorder_frames;
5396 hw->max_dec_frame_buffering =
5397 p_H264_Dpb->max_dec_frame_buffering;
5398#endif
5399
5400 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5401 reset_process_time(hw);
5402 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5403 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5404 vdec_schedule_work(&hw->work);
5405 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5406 u16 data_hight;
5407 u16 data_low;
5408 u32 video_signal;
5409
5410 int slice_header_process_status = 0;
5411 int I_flag;
5412 /*unsigned char is_idr;*/
5413 unsigned short *p = (unsigned short *)hw->lmem_addr;
5414 reset_process_time(hw);
5415
5416 if (hw->is_used_v4l) {
5417 struct aml_vcodec_ctx *ctx =
5418 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5419
5420 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5421 //amvdec_stop();
5422 hw->dec_result = DEC_RESULT_DONE;
5423 vdec_schedule_work(&hw->work);
5424 return IRQ_HANDLED;
5425 }
5426 }
5427
5428 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5429 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5430 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5431 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5432 if (input_frame_based(vdec) &&
5433 frmbase_cont_bitlevel2 != 0 &&
5434 READ_VREG(VIFF_BIT_CNT) <
5435 frmbase_cont_bitlevel2 &&
5436 hw->get_data_count >= 0x70000000) {
5437 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5438 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5439 __func__,
5440 READ_VREG(VIFF_BIT_CNT));
5441
5442 goto empty_proc;
5443 }
5444
5445 dma_sync_single_for_cpu(
5446 amports_get_dma_device(),
5447 hw->lmem_addr_remap,
5448 PAGE_SIZE,
5449 DMA_FROM_DEVICE);
5450#if 0
5451 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5452 if (!is_buffer_available(vdec)) {
5453 hw->buffer_empty_flag = 1;
5454 dpb_print(DECODE_ID(hw),
5455 PRINT_FLAG_UCODE_EVT,
5456 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5457 __func__,
5458 kfifo_len(&hw->newframe_q),
5459 have_free_buf_spec(vdec),
5460 p_H264_Dpb->mDPB.init_done,
5461 p_H264_Dpb->mDPB.used_size,
5462 p_H264_Dpb->mDPB.size,
5463 is_there_unused_frame_from_dpb(
5464 &p_H264_Dpb->mDPB));
5465 return IRQ_HANDLED;
5466 }
5467 }
5468
5469 hw->buffer_empty_flag = 0;
5470#endif
5471#ifdef SEND_PARAM_WITH_REG
5472 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5473 unsigned int data32;
5474
5475 do {
5476 data32 = READ_VREG(RPM_CMD_REG);
5477 /* printk("%x\n", data32); */
5478 } while ((data32&0x10000) == 0);
5479 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5480 WRITE_VREG(RPM_CMD_REG, 0);
5481 /* printk("%x:%x\n", i,data32); */
5482 }
5483#else
5484 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5485 int ii;
5486
5487 for (ii = 0; ii < 4; ii++) {
5488 p_H264_Dpb->dpb_param.l.data[i+ii] =
5489 p[i+3-ii];
5490 if (dpb_is_debug(DECODE_ID(hw),
5491 RRINT_FLAG_RPM)) {
5492 if (((i + ii) & 0xf) == 0)
5493 dpb_print(DECODE_ID(hw),
5494 0, "%04x:",
5495 i);
5496 dpb_print_cont(DECODE_ID(hw),
5497 0, "%04x ",
5498 p[i+3-ii]);
5499 if (((i + ii + 1) & 0xf) == 0)
5500 dpb_print_cont(
5501 DECODE_ID(hw),
5502 0, "\r\n");
5503 }
5504 }
5505 }
5506#endif
5507 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5508 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5509
5510 video_signal = (data_hight << 16) | data_low;
5511 hw->video_signal_from_vui =
5512 ((video_signal & 0xffff) << 8) |
5513 ((video_signal & 0xff0000) >> 16) |
5514 ((video_signal & 0x3f000000));
5515
5516
5517 /*dpb_print(DECODE_ID(hw),
5518 0,
5519 "video_signal_from_vui:0x%x, "
5520 "data_low:0x%x, data_hight:0x%x\n",
5521 hw->video_signal_from_vui,
5522 data_low,
5523 data_hight);*/
5524
5525 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5526
5527 if (hw->config_bufmgr_done == 0) {
5528 hw->dec_result = DEC_RESULT_DONE;
5529 vdec_schedule_work(&hw->work);
5530 dpb_print(DECODE_ID(hw),
5531 PRINT_FLAG_UCODE_EVT,
5532 "config_bufmgr not done, discard frame\n");
5533 return IRQ_HANDLED;
5534 } else if ((hw->first_i_policy & 0x3) != 0) {
5535 unsigned char is_i_slice =
5536 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5537 == I_Slice)
5538 ? 1 : 0;
5539 unsigned char is_idr =
5540 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5541 == 5);
5542 if ((hw->first_i_policy & 0x3) == 0x3)
5543 is_i_slice = is_idr;
5544 if (!is_i_slice) {
5545 if (hw->has_i_frame == 0) {
5546 amvdec_stop();
5547 vdec->mc_loaded = 0;
5548 hw->dec_result = DEC_RESULT_DONE;
5549 vdec_schedule_work(&hw->work);
5550 dpb_print(DECODE_ID(hw),
5551 PRINT_FLAG_UCODE_EVT,
5552 "has_i_frame is 0, discard none I(DR) frame\n");
5553 return IRQ_HANDLED;
5554 }
5555 } else {
5556 if (hw->skip_frame_count < 0 || is_idr) {
5557 /* second I */
5558 hw->dec_flag &= (~NODISP_FLAG);
5559 hw->skip_frame_count = 0;
5560 }
5561 if (hw->has_i_frame == 0 &&
5562 (!is_idr)) {
5563 int skip_count =
5564 (hw->first_i_policy >> 8) & 0xff;
5565 /* first I (not IDR) */
5566 if ((hw->first_i_policy & 0x3) == 2)
5567 hw->skip_frame_count =
5568 -1 - skip_count;
5569 else
5570 hw->skip_frame_count =
5571 skip_count;
5572 if (hw->skip_frame_count != 0)
5573 hw->dec_flag |= NODISP_FLAG;
5574 }
5575 }
5576 }
5577 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5578 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5579 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5580 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5581 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5582 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5583 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5584 ? I_FLAG : 0;
5585 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5586 (p_H264_Dpb->mSlice.structure == FRAME)) {
5587 hw->data_flag = NULL_FLAG;
5588 goto pic_done_proc;
5589 }
5590
5591 slice_header_process_status =
5592 h264_slice_header_process(p_H264_Dpb);
5593 if (hw->mmu_enable)
5594 hevc_sao_set_slice_type(hw,
5595 slice_header_process_status,
5596 hw->dpb.mSlice.idr_flag);
5597 vui_config(hw);
5598
5599 if (p_H264_Dpb->mVideo.dec_picture) {
5600 int cfg_ret = 0;
5601 bool field_pic_flag = false;
5602
5603 if (slice_header_process_status == 1) {
5604 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5605 field_pic_flag =
5606 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5607 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5608 true : false;
5609 }
5610
5611 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5612 (((unsigned long)(hw->vh264_amstream_dec_info
5613 .param)) & 0x8))) {
5614 p_H264_Dpb->fast_output_enable =
5615 H264_OUTPUT_MODE_FAST;
5616 }
5617 else
5618 p_H264_Dpb->fast_output_enable
5619 = fast_output_enable;
5620 hw->data_flag = I_flag;
5621 if ((p_H264_Dpb->
5622 dpb_param.dpb.NAL_info_mmco & 0x1f)
5623 == 5)
5624 hw->data_flag |= IDR_FLAG;
5625 dpb_print(DECODE_ID(hw),
5626 PRINT_FLAG_VDEC_STATUS,
5627 "==================> frame count %d to skip %d\n",
5628 hw->decode_pic_count+1,
5629 hw->skip_frame_count);
5630 } else if (error_proc_policy & 0x100){
5631 struct StorablePicture *p =
5632 p_H264_Dpb->mVideo.dec_picture;
5633 unsigned mby_mbx = READ_VREG(MBY_MBX);
5634 unsigned decode_mb_count =
5635 ((mby_mbx & 0xff) * hw->mb_width +
5636 (((mby_mbx >> 8) & 0xff) + 1));
5637 if (decode_mb_count <
5638 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5639 (1 + p->mb_aff_frame_flag))) {
5640 dpb_print(DECODE_ID(hw),
5641 PRINT_FLAG_VDEC_STATUS,
5642 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5643 p_H264_Dpb->dpb_param.l.
5644 data[FIRST_MB_IN_SLICE],
5645 READ_VREG(MBY_MBX),
5646 decode_mb_count);
5647 p->data_flag |= ERROR_FLAG;
5648 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5649 p->data_flag |= ERROR_FLAG;
5650 goto pic_done_proc;
5651 }
5652 }
5653
5654 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5655 hw->new_iframe_flag = 1;
5656 }
5657 if (hw->new_iframe_flag) {
5658 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5659 hw->new_iframe_flag = 0;
5660 hw->ref_err_flush_dpb_flag = 1;
5661 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5662 hw->new_iframe_flag = 0;
5663 hw->ref_err_flush_dpb_flag = 0;
5664 }
5665 }
5666
5667 if (error_proc_policy & 0x400) {
5668 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5669 if (ret != 0) {
5670 hw->reflist_error_count ++;
5671 dpb_print(DECODE_ID(hw), 0,
5672 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5673 ret,
5674 hw->decode_pic_count+1,
5675 hw->skip_frame_count,
5676 hw->reflist_error_count);
5677
5678 if (hw->ref_err_flush_dpb_flag) {
5679 flush_dpb(p_H264_Dpb);
5680 p_H264_Dpb->colocated_buf_map = 0;
5681 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5682 p_H264_Dpb->colocated_buf_map |= 1 <<
5683 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5684 }
5685 }
5686
5687 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5688 if (((error_proc_policy & 0x80)
5689 && ((hw->dec_flag &
5690 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5691 hw->reset_bufmgr_flag = 1;
5692 hw->reflist_error_count =0;
5693 amvdec_stop();
5694 vdec->mc_loaded = 0;
5695 hw->dec_result = DEC_RESULT_DONE;
5696 vdec_schedule_work(&hw->work);
5697 return IRQ_HANDLED;
5698 }
5699 } else
5700 hw->reflist_error_count = 0;
5701 }
5702 if ((error_proc_policy & 0x800)
5703 && p_H264_Dpb->dpb_error_flag != 0) {
5704 dpb_print(DECODE_ID(hw), 0,
5705 "dpb error %d\n",
5706 p_H264_Dpb->dpb_error_flag);
5707 hw->data_flag |= ERROR_FLAG;
5708 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5709 if ((error_proc_policy & 0x80) &&
5710 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5711 hw->reset_bufmgr_flag = 1;
5712 amvdec_stop();
5713 vdec->mc_loaded = 0;
5714 hw->dec_result = DEC_RESULT_DONE;
5715 vdec_schedule_work(&hw->work);
5716 return IRQ_HANDLED;
5717 }
5718 }
5719
5720 cfg_ret = config_decode_buf(hw,
5721 p_H264_Dpb->mVideo.dec_picture);
5722 if (cfg_ret < 0) {
5723 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5724 "config_decode_buf fail (%d)\n",
5725 cfg_ret);
5726 if (error_proc_policy & 0x2) {
5727 release_cur_decoding_buf(hw);
5728 /*hw->data_flag |= ERROR_FLAG;*/
5729 hw->reset_bufmgr_flag = 1;
5730 hw->dec_result = DEC_RESULT_DONE;
5731 vdec_schedule_work(&hw->work);
5732 return IRQ_HANDLED;
5733 } else
5734 hw->data_flag |= ERROR_FLAG;
5735 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5736 }
5737 }
5738
5739 if (slice_header_process_status == 1)
5740 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5741 else
5742 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5743 hw->last_mby_mbx = 0;
5744 hw->last_vld_level = 0;
5745 start_process_time(hw);
5746 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5747 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5748pic_done_proc:
5749 reset_process_time(hw);
5750
5751 if (input_frame_based(vdec) &&
5752 frmbase_cont_bitlevel != 0 &&
5753 READ_VREG(VIFF_BIT_CNT) >
5754 frmbase_cont_bitlevel) {
5755 /*handle the case: multi pictures in one packet*/
5756 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5757 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5758 __func__,
5759 hw->decode_pic_count,
5760 READ_VREG(VIFF_BIT_CNT));
5761 hw->frmbase_cont_flag = 1;
5762 } else
5763 hw->frmbase_cont_flag = 0;
5764
5765 if (p_H264_Dpb->mVideo.dec_picture) {
5766 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5767#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5768 DEL_EXIST(hw,
5769 p_H264_Dpb->mVideo.dec_picture) = 0;
5770 if (vdec->master) {
5771 struct vdec_h264_hw_s *hw_ba =
5772 (struct vdec_h264_hw_s *)
5773 vdec->master->private;
5774 if (hw_ba->last_dec_picture)
5775 DEL_EXIST(hw_ba,
5776 hw_ba->last_dec_picture)
5777 = 1;
5778 }
5779#endif
5780 mutex_lock(&hw->chunks_mutex);
5781 if (hw->chunk) {
5782 p_H264_Dpb->mVideo.dec_picture->pts =
5783 hw->chunk->pts;
5784 p_H264_Dpb->mVideo.dec_picture->pts64 =
5785 hw->chunk->pts64;
5786 p_H264_Dpb->mVideo.dec_picture->timestamp =
5787 hw->chunk->timestamp;
5788#ifdef MH264_USERDATA_ENABLE
5789 vmh264_udc_fill_vpts(hw,
5790 p_H264_Dpb->mSlice.slice_type,
5791 hw->chunk->pts, 1);
5792#endif
5793
5794#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5795 } else if (vdec->master) {
5796 /*dv enhance layer,
5797 do not checkout pts*/
5798 struct StorablePicture *pic =
5799 p_H264_Dpb->mVideo.dec_picture;
5800 pic->pts = 0;
5801 pic->pts64 = 0;
5802#endif
5803 } else {
5804 struct StorablePicture *pic =
5805 p_H264_Dpb->mVideo.dec_picture;
5806 u32 offset = pic->offset_delimiter;
5807 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5808 offset, &pic->pts, 0, &pic->pts64)) {
5809 pic->pts = 0;
5810 pic->pts64 = 0;
5811#ifdef MH264_USERDATA_ENABLE
5812 vmh264_udc_fill_vpts(hw,
5813 p_H264_Dpb->mSlice.slice_type,
5814 pic->pts, 0);
5815#endif
5816 } else {
5817#ifdef MH264_USERDATA_ENABLE
5818 vmh264_udc_fill_vpts(hw,
5819 p_H264_Dpb->mSlice.slice_type,
5820 pic->pts, 1);
5821#endif
5822 }
5823
5824 }
5825 mutex_unlock(&hw->chunks_mutex);
5826 check_decoded_pic_error(hw);
5827#ifdef ERROR_HANDLE_TEST
5828 if ((hw->data_flag & ERROR_FLAG)
5829 && (error_proc_policy & 0x80)) {
5830 release_cur_decoding_buf(hw);
5831 h264_clear_dpb(hw);
5832 hw->dec_flag = 0;
5833 hw->data_flag = 0;
5834 hw->skip_frame_count = 0;
5835 hw->has_i_frame = 0;
5836 hw->no_error_count = 0xfff;
5837 hw->no_error_i_count = 0xf;
5838 } else
5839#endif
5840 ret = store_picture_in_dpb(p_H264_Dpb,
5841 p_H264_Dpb->mVideo.dec_picture,
5842 hw->data_flag | hw->dec_flag |
5843 p_H264_Dpb->mVideo.dec_picture->data_flag);
5844
5845
5846
5847 if (ret == -1) {
5848 release_cur_decoding_buf(hw);
5849 bufmgr_force_recover(p_H264_Dpb);
5850 } else {
5851 if (hw->data_flag & ERROR_FLAG) {
5852 hw->no_error_count = 0;
5853 hw->no_error_i_count = 0;
5854 } else {
5855 hw->no_error_count++;
5856 if (hw->data_flag & I_FLAG)
5857 hw->no_error_i_count++;
5858 }
5859 if (hw->mmu_enable)
5860 hevc_set_unused_4k_buff_idx(hw,
5861 p_H264_Dpb->mVideo.
5862 dec_picture->buf_spec_num);
5863 bufmgr_post(p_H264_Dpb);
5864 hw->last_dec_picture =
5865 p_H264_Dpb->mVideo.dec_picture;
5866 p_H264_Dpb->mVideo.dec_picture = NULL;
5867 /* dump_dpb(&p_H264_Dpb->mDPB); */
5868 hw->has_i_frame = 1;
5869 if (hw->mmu_enable)
5870 hevc_set_frame_done(hw);
5871 hw->decode_pic_count++;
5872 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5873 if (hw->skip_frame_count > 0) {
5874 /*skip n frame after first I */
5875 hw->skip_frame_count--;
5876 if (hw->skip_frame_count == 0)
5877 hw->dec_flag &= (~NODISP_FLAG);
5878 } else if (hw->skip_frame_count < -1) {
5879 /*skip n frame after first I until second I */
5880 hw->skip_frame_count++;
5881 if (hw->skip_frame_count == -1)
5882 hw->dec_flag &= (~NODISP_FLAG);
5883 }
5884 }
5885 }
5886 if (hw->frmbase_cont_flag) {
5887 /*do not DEC_RESULT_GET_DATA*/
5888 hw->get_data_count = 0x7fffffff;
5889 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5890 decode_frame_count[DECODE_ID(hw)]++;
5891 start_process_time(hw);
5892 return IRQ_HANDLED;
5893 }
5894 amvdec_stop();
5895 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5896 "%s %s decode slice count %d\n",
5897 __func__,
5898 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5899 "H264_PIC_DATA_DONE" :
5900 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5901 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5902 hw->decode_pic_count);
5903 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5904 hw->dec_result = DEC_RESULT_DONE;
5905#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5906 if (vdec->slave &&
5907 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5908 struct vdec_h264_hw_s *hw_el =
5909 (struct vdec_h264_hw_s *)(vdec->slave->private);
5910 hw_el->got_valid_nal = 0;
5911 hw->switch_dvlayer_flag = 1;
5912 } else if (vdec->master &&
5913 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5914 struct vdec_h264_hw_s *hw_bl =
5915 (struct vdec_h264_hw_s *)(vdec->master->private);
5916 hw_bl->got_valid_nal = 0;
5917 hw->switch_dvlayer_flag = 1;
5918 } else {
5919 hw->switch_dvlayer_flag = 0;
5920 hw->got_valid_nal = 1;
5921 }
5922#endif
5923
5924 hw->dec_result = DEC_RESULT_DONE;
5925 vdec_schedule_work(&hw->work);
5926
5927#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5928 } else if (
5929 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5930 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5931 goto pic_done_proc;
5932#endif
5933 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5934 reset_process_time(hw);
5935 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5936 dma_sync_single_for_cpu(
5937 amports_get_dma_device(),
5938 hw->aux_phy_addr,
5939 hw->prefix_aux_size + hw->suffix_aux_size,
5940 DMA_FROM_DEVICE);
5941 if (dpb_is_debug(DECODE_ID(hw),
5942 PRINT_FLAG_DPB_DETAIL))
5943 dump_aux_buf(hw);
5944#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5945 if (vdec->dolby_meta_with_el || vdec->slave) {
5946 if (hw->last_dec_picture)
5947 set_aux_data(hw, hw->last_dec_picture,
5948 0, 0, NULL);
5949 } else {
5950 if (vdec->master) {
5951 struct vdec_h264_hw_s *hw_bl =
5952 (struct vdec_h264_hw_s *)
5953 (vdec->master->private);
5954 if (hw_bl->last_dec_picture != NULL) {
5955 set_aux_data(hw_bl,
5956 hw_bl->last_dec_picture,
5957 0, 1, hw);
5958 }
5959 set_aux_data(hw,
5960 hw->last_dec_picture,
5961 0, 2, NULL);
5962 }
5963 }
5964#else
5965 if (hw->last_dec_picture)
5966 set_aux_data(hw,
5967 hw->last_dec_picture, 0, 0, NULL);
5968#endif
5969 }
5970#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5971 hw->switch_dvlayer_flag = 0;
5972 hw->got_valid_nal = 1;
5973#endif
5974 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5975 "%s H264_AUX_DATA_READY\n", __func__);
5976 hw->dec_result = DEC_RESULT_DONE;
5977 vdec_schedule_work(&hw->work);
5978 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5979 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5980 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5981 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5982empty_proc:
5983 reset_process_time(hw);
5984 if (!hw->frmbase_cont_flag)
5985 release_cur_decoding_buf(hw);
5986
5987 if (input_frame_based(vdec) ||
5988 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
5989 if (h264_debug_flag &
5990 DISABLE_ERROR_HANDLE) {
5991 dpb_print(DECODE_ID(hw),
5992 PRINT_FLAG_ERROR,
5993 "%s decoding error, level 0x%x\n",
5994 __func__,
5995 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
5996 goto send_again;
5997 }
5998 amvdec_stop();
5999 vdec->mc_loaded = 0;
6000 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6001 "%s %s\n", __func__,
6002 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6003 "H264_SEARCH_BUFEMPTY" :
6004 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6005 "H264_DECODE_BUFEMPTY" :
6006 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6007 "H264_DECODE_TIMEOUT" :
6008 "OTHER");
6009 hw->dec_result = DEC_RESULT_DONE;
6010
6011 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6012 hw->search_dataempty_num++;
6013 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6014 hw->decode_timeout_num++;
6015 if (error_proc_policy & 0x4000) {
6016 hw->data_flag |= ERROR_FLAG;
6017 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6018 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6019 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6020 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6021 dpb_print(DECODE_ID(hw),
6022 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6023 p_H264_Dpb->last_dpb_status, __func__);
6024 hw->reset_bufmgr_flag = 1;
6025 }
6026 }
6027 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6028 hw->decode_dataempty_num++;
6029 if (!hw->frmbase_cont_flag)
6030 hw->data_flag |= ERROR_FLAG;
6031
6032 vdec_schedule_work(&hw->work);
6033 } else {
6034 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6035 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6036 "%s DEC_RESULT_AGAIN\n", __func__);
6037send_again:
6038 hw->dec_result = DEC_RESULT_AGAIN;
6039 vdec_schedule_work(&hw->work);
6040 }
6041 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6042 reset_process_time(hw);
6043 if (input_frame_based(vdec)) {
6044 dpb_print(DECODE_ID(hw),
6045 PRINT_FLAG_VDEC_STATUS,
6046 "%s H264_DATA_REQUEST (%d)\n",
6047 __func__, hw->get_data_count);
6048 hw->dec_result = DEC_RESULT_GET_DATA;
6049 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6050 hw->get_data_start_time = jiffies;
6051 hw->get_data_count++;
6052 if (hw->get_data_count >= frame_max_data_packet)
6053 goto empty_proc;
6054 vdec_schedule_work(&hw->work);
6055 } else
6056 goto empty_proc;
6057 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6058 dpb_print(DECODE_ID(hw), 0,
6059 "vmh264 decode oversize !!\n");
6060 release_cur_decoding_buf(hw);
6061 hw->data_flag |= ERROR_FLAG;
6062 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6063 reset_process_time(hw);
6064 hw->dec_result = DEC_RESULT_DONE;
6065 vdec_schedule_work(&hw->work);
6066 return IRQ_HANDLED;
6067 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6068 int aux_data_len;
6069 aux_data_len =
6070 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6071
6072 if (aux_data_len > SEI_DATA_SIZE) {
6073 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6074 "sei data size more than 4K: %d, discarded it\n",
6075 hw->sei_itu_data_len);
6076 hw->sei_itu_data_len = 0;
6077 }
6078
6079 if (aux_data_len != 0) {
6080 u8 *trans_data_buf;
6081 u8 *sei_data_buf;
6082 u8 swap_byte;
6083
6084 dma_sync_single_for_cpu(
6085 amports_get_dma_device(),
6086 hw->aux_phy_addr,
6087 hw->prefix_aux_size + hw->suffix_aux_size,
6088 DMA_FROM_DEVICE);
6089#if 0
6090 dump_aux_buf(hw);
6091#endif
6092 trans_data_buf = (u8 *)hw->aux_addr;
6093
6094 if (trans_data_buf[7] == AUX_TAG_SEI) {
6095 int left_len;
6096
6097 sei_data_buf = (u8 *)hw->sei_data_buf
6098 + hw->sei_data_len;
6099 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6100 if (aux_data_len/2 <= left_len) {
6101 for (i = 0; i < aux_data_len/2; i++)
6102 sei_data_buf[i]
6103 = trans_data_buf[i*2];
6104
6105 aux_data_len = aux_data_len / 2;
6106 for (i = 0; i < aux_data_len; i = i+4) {
6107 swap_byte = sei_data_buf[i];
6108 sei_data_buf[i]
6109 = sei_data_buf[i+3];
6110 sei_data_buf[i+3] = swap_byte;
6111
6112 swap_byte = sei_data_buf[i+1];
6113 sei_data_buf[i+1]
6114 = sei_data_buf[i+2];
6115 sei_data_buf[i+2] = swap_byte;
6116 }
6117
6118 for (i = aux_data_len-1; i >= 0; i--)
6119 if (sei_data_buf[i] != 0)
6120 break;
6121
6122 hw->sei_data_len += i+1;
6123 } else
6124 dpb_print(DECODE_ID(hw),
6125 PRINT_FLAG_ERROR,
6126 "sei data size %d and more than left space: %d, discarded it\n",
6127 hw->sei_itu_data_len,
6128 left_len);
6129 }
6130 }
6131 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6132
6133 return IRQ_HANDLED;
6134 }
6135
6136
6137 /* ucode debug */
6138 debug_tag = READ_VREG(DEBUG_REG1);
6139 if (debug_tag & 0x10000) {
6140 unsigned short *p = (unsigned short *)hw->lmem_addr;
6141
6142 dma_sync_single_for_cpu(
6143 amports_get_dma_device(),
6144 hw->lmem_addr_remap,
6145 PAGE_SIZE,
6146 DMA_FROM_DEVICE);
6147
6148 dpb_print(DECODE_ID(hw), 0,
6149 "LMEM<tag %x>:\n", debug_tag);
6150 for (i = 0; i < 0x400; i += 4) {
6151 int ii;
6152 if ((i & 0xf) == 0)
6153 dpb_print_cont(DECODE_ID(hw), 0,
6154 "%03x: ", i);
6155 for (ii = 0; ii < 4; ii++)
6156 dpb_print_cont(DECODE_ID(hw), 0,
6157 "%04x ", p[i+3-ii]);
6158 if (((i+ii) & 0xf) == 0)
6159 dpb_print_cont(DECODE_ID(hw), 0,
6160 "\n");
6161 }
6162 if (((udebug_pause_pos & 0xffff)
6163 == (debug_tag & 0xffff)) &&
6164 (udebug_pause_decode_idx == 0 ||
6165 udebug_pause_decode_idx ==
6166 hw->decode_pic_count) &&
6167 (udebug_pause_val == 0 ||
6168 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6169 udebug_pause_pos &= 0xffff;
6170 hw->ucode_pause_pos = udebug_pause_pos;
6171 }
6172 else if (debug_tag & 0x20000)
6173 hw->ucode_pause_pos = 0xffffffff;
6174 if (hw->ucode_pause_pos)
6175 reset_process_time(hw);
6176 else
6177 WRITE_VREG(DEBUG_REG1, 0);
6178 } else if (debug_tag != 0) {
6179 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6180 "dbg%x: %x\n", debug_tag,
6181 READ_VREG(DEBUG_REG2));
6182 if (((udebug_pause_pos & 0xffff)
6183 == (debug_tag & 0xffff)) &&
6184 (udebug_pause_decode_idx == 0 ||
6185 udebug_pause_decode_idx ==
6186 hw->decode_pic_count) &&
6187 (udebug_pause_val == 0 ||
6188 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6189 udebug_pause_pos &= 0xffff;
6190 hw->ucode_pause_pos = udebug_pause_pos;
6191 }
6192 if (hw->ucode_pause_pos)
6193 reset_process_time(hw);
6194 else
6195 WRITE_VREG(DEBUG_REG1, 0);
6196 }
6197 /**/
6198 return IRQ_HANDLED;
6199}
6200
6201static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6202{
6203 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6204 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6205
6206
6207 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6208
6209 if (!hw)
6210 return IRQ_HANDLED;
6211
6212 if (hw->eos)
6213 return IRQ_HANDLED;
6214
6215 p_H264_Dpb->vdec = vdec;
6216 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6217
6218 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6219 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6220 __func__,
6221 p_H264_Dpb->dec_dpb_status,
6222 READ_VREG(ERROR_STATUS_REG),
6223 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6224 READ_VREG(VLD_MEM_VIFIFO_WP),
6225 READ_VREG(VLD_MEM_VIFIFO_RP),
6226 READ_VREG(VIFF_BIT_CNT),
6227 READ_VREG(MBY_MBX));
6228
6229 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6230 if (hw->mmu_enable)
6231 hevc_sao_wait_done(hw);
6232 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6233 return IRQ_HANDLED;
6234 }
6235 return IRQ_WAKE_THREAD;
6236
6237}
6238
6239static void timeout_process(struct vdec_h264_hw_s *hw)
6240{
6241 struct vdec_s *vdec = hw_to_vdec(hw);
6242 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6243
6244 /*
6245 * In this very timeout point,the vh264_work arrives,
6246 * let it to handle the scenario.
6247 */
6248 if (work_pending(&hw->work))
6249 return;
6250
6251 hw->timeout_num++;
6252 amvdec_stop();
6253 vdec->mc_loaded = 0;
6254 if (hw->mmu_enable) {
6255 hevc_set_frame_done(hw);
6256 hevc_sao_wait_done(hw);
6257 }
6258 if (!hw->i_only && (error_proc_policy & 0x2))
6259 flush_dpb(p_H264_Dpb);
6260 dpb_print(DECODE_ID(hw),
6261 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6262 release_cur_decoding_buf(hw);
6263 hw->dec_result = DEC_RESULT_DONE;
6264 hw->data_flag |= ERROR_FLAG;
6265
6266 if (work_pending(&hw->work))
6267 return;
6268 vdec_schedule_work(&hw->timeout_work);
6269}
6270
6271static void dump_bufspec(struct vdec_h264_hw_s *hw,
6272 const char *caller)
6273{
6274 int i;
6275 dpb_print(DECODE_ID(hw), 0,
6276 "%s in %s:\n", __func__, caller);
6277 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6278 if (hw->buffer_spec[i].used == -1)
6279 continue;
6280 dpb_print(DECODE_ID(hw), 0,
6281 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6282 i, hw->buffer_spec[i].used,
6283 hw->buffer_spec[i].buf_adr,
6284 hw->buffer_spec[i].canvas_pos,
6285 hw->buffer_spec[i].vf_ref
6286 );
6287#ifdef CONFIG_AM_VDEC_DV
6288 dpb_print_cont(DECODE_ID(hw), 0,
6289 "dv_el_exist %d",
6290 hw->buffer_spec[i].dv_enhance_exist
6291 );
6292#endif
6293 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6294 }
6295
6296}
6297
6298static void vmh264_dump_state(struct vdec_s *vdec)
6299{
6300 struct vdec_h264_hw_s *hw =
6301 (struct vdec_h264_hw_s *)(vdec->private);
6302 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6303 dpb_print(DECODE_ID(hw), 0,
6304 "====== %s\n", __func__);
6305 dpb_print(DECODE_ID(hw), 0,
6306 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6307 hw->frame_width,
6308 hw->frame_height,
6309 hw->dpb.reorder_pic_num,
6310 hw->dpb.mDPB.size,
6311 hw->max_reference_size,
6312 hw->i_only,
6313 hw->send_error_frame_flag
6314 );
6315
6316 dpb_print(DECODE_ID(hw), 0,
6317 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6318 input_frame_based(vdec),
6319 hw->eos,
6320 hw->stat,
6321 hw->dec_result,
6322 decode_frame_count[DECODE_ID(hw)],
6323 display_frame_count[DECODE_ID(hw)],
6324 run_count[DECODE_ID(hw)],
6325 not_run_ready[DECODE_ID(hw)],
6326 input_empty[DECODE_ID(hw)],
6327 hw->reset_bufmgr_count
6328 );
6329
6330 if (vf_get_receiver(vdec->vf_provider_name)) {
6331 enum receviver_start_e state =
6332 vf_notify_receiver(vdec->vf_provider_name,
6333 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6334 NULL);
6335 dpb_print(DECODE_ID(hw), 0,
6336 "\nreceiver(%s) state %d\n",
6337 vdec->vf_provider_name,
6338 state);
6339 }
6340
6341 dpb_print(DECODE_ID(hw), 0,
6342 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x\n",
6343 __func__,
6344 kfifo_len(&hw->newframe_q),
6345 VF_POOL_SIZE,
6346 kfifo_len(&hw->display_q),
6347 VF_POOL_SIZE,
6348 hw->vf_pre_count,
6349 hw->vf_get_count,
6350 hw->vf_put_count,
6351 have_free_buf_spec(vdec),
6352 p_H264_Dpb->mDPB.init_done,
6353 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6354 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6355 p_H264_Dpb->fast_output_enable
6356 );
6357
6358 dump_dpb(&p_H264_Dpb->mDPB, 1);
6359 dump_pic(p_H264_Dpb);
6360 dump_bufspec(hw, __func__);
6361
6362 dpb_print(DECODE_ID(hw), 0,
6363 "DPB_STATUS_REG=0x%x\n",
6364 READ_VREG(DPB_STATUS_REG));
6365 dpb_print(DECODE_ID(hw), 0,
6366 "MPC_E=0x%x\n",
6367 READ_VREG(MPC_E));
6368 dpb_print(DECODE_ID(hw), 0,
6369 "H264_DECODE_MODE=0x%x\n",
6370 READ_VREG(H264_DECODE_MODE));
6371 dpb_print(DECODE_ID(hw), 0,
6372 "MBY_MBX=0x%x\n",
6373 READ_VREG(MBY_MBX));
6374 dpb_print(DECODE_ID(hw), 0,
6375 "H264_DECODE_SIZE=0x%x\n",
6376 READ_VREG(H264_DECODE_SIZE));
6377 dpb_print(DECODE_ID(hw), 0,
6378 "VIFF_BIT_CNT=0x%x\n",
6379 READ_VREG(VIFF_BIT_CNT));
6380 dpb_print(DECODE_ID(hw), 0,
6381 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6382 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6383 dpb_print(DECODE_ID(hw), 0,
6384 "VLD_MEM_VIFIFO_WP=0x%x\n",
6385 READ_VREG(VLD_MEM_VIFIFO_WP));
6386 dpb_print(DECODE_ID(hw), 0,
6387 "VLD_MEM_VIFIFO_RP=0x%x\n",
6388 READ_VREG(VLD_MEM_VIFIFO_RP));
6389 dpb_print(DECODE_ID(hw), 0,
6390 "PARSER_VIDEO_RP=0x%x\n",
6391 READ_PARSER_REG(PARSER_VIDEO_RP));
6392 dpb_print(DECODE_ID(hw), 0,
6393 "PARSER_VIDEO_WP=0x%x\n",
6394 READ_PARSER_REG(PARSER_VIDEO_WP));
6395
6396 if (input_frame_based(vdec) &&
6397 dpb_is_debug(DECODE_ID(hw),
6398 PRINT_FRAMEBASE_DATA)
6399 ) {
6400 int jj;
6401 if (hw->chunk && hw->chunk->block &&
6402 hw->chunk->size > 0) {
6403 u8 *data = NULL;
6404
6405 if (!hw->chunk->block->is_mapped)
6406 data = codec_mm_vmap(hw->chunk->block->start +
6407 hw->chunk->offset, hw->chunk->size);
6408 else
6409 data = ((u8 *)hw->chunk->block->start_virt)
6410 + hw->chunk->offset;
6411
6412 dpb_print(DECODE_ID(hw), 0,
6413 "frame data size 0x%x\n",
6414 hw->chunk->size);
6415 for (jj = 0; jj < hw->chunk->size; jj++) {
6416 if ((jj & 0xf) == 0)
6417 dpb_print(DECODE_ID(hw),
6418 PRINT_FRAMEBASE_DATA,
6419 "%06x:", jj);
6420 dpb_print_cont(DECODE_ID(hw),
6421 PRINT_FRAMEBASE_DATA,
6422 "%02x ", data[jj]);
6423 if (((jj + 1) & 0xf) == 0)
6424 dpb_print_cont(DECODE_ID(hw),
6425 PRINT_FRAMEBASE_DATA,
6426 "\n");
6427 }
6428
6429 if (!hw->chunk->block->is_mapped)
6430 codec_mm_unmap_phyaddr(data);
6431 }
6432 }
6433}
6434
6435
6436static void check_timer_func(unsigned long arg)
6437{
6438 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6439 struct vdec_s *vdec = hw_to_vdec(hw);
6440 int error_skip_frame_count = error_skip_count & 0xfff;
6441 unsigned int timeout_val = decode_timeout_val;
6442 if (timeout_val != 0 &&
6443 hw->no_error_count < error_skip_frame_count)
6444 timeout_val = errordata_timeout_val;
6445 if ((h264_debug_cmd & 0x100) != 0 &&
6446 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6447 hw->dec_result = DEC_RESULT_DONE;
6448 vdec_schedule_work(&hw->work);
6449 pr_info("vdec %d is forced to be disconnected\n",
6450 h264_debug_cmd & 0xff);
6451 h264_debug_cmd = 0;
6452 return;
6453 }
6454 if ((h264_debug_cmd & 0x200) != 0 &&
6455 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6456 pr_debug("vdec %d is forced to reset bufmgr\n",
6457 h264_debug_cmd & 0xff);
6458 hw->reset_bufmgr_flag = 1;
6459 h264_debug_cmd = 0;
6460 return;
6461 }
6462
6463 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6464 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6465 vdec_schedule_work(&hw->work);
6466 pr_debug("vdec requested to be disconnected\n");
6467 return;
6468 }
6469
6470 if (radr != 0) {
6471 if (rval != 0) {
6472 WRITE_VREG(radr, rval);
6473 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6474 } else
6475 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6476 rval = 0;
6477 radr = 0;
6478 }
6479
6480 if ((input_frame_based(vdec) ||
6481 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6482 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6483 (timeout_val > 0) &&
6484 (hw->start_process_time > 0) &&
6485 ((1000 * (jiffies - hw->start_process_time) / HZ)
6486 > timeout_val)
6487 ) {
6488 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6489 u32 mby_mbx = READ_VREG(MBY_MBX);
6490 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6491 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6492 if (hw->last_mby_mbx == mby_mbx) {
6493 if (hw->decode_timeout_count > 0)
6494 hw->decode_timeout_count--;
6495 if (hw->decode_timeout_count == 0)
6496 {
6497 reset_process_time(hw);
6498 timeout_process(hw);
6499 }
6500 } else
6501 start_process_time(hw);
6502 } else if (is_in_parsing_state(dpb_status)) {
6503 if (hw->last_vld_level ==
6504 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6505 if (hw->decode_timeout_count > 0)
6506 hw->decode_timeout_count--;
6507 if (hw->decode_timeout_count == 0)
6508 {
6509 reset_process_time(hw);
6510 timeout_process(hw);
6511 }
6512 }
6513 }
6514 hw->last_vld_level =
6515 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6516 hw->last_mby_mbx = mby_mbx;
6517 }
6518
6519 if ((hw->ucode_pause_pos != 0) &&
6520 (hw->ucode_pause_pos != 0xffffffff) &&
6521 udebug_pause_pos != hw->ucode_pause_pos) {
6522 hw->ucode_pause_pos = 0;
6523 WRITE_VREG(DEBUG_REG1, 0);
6524 }
6525
6526 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6527}
6528
6529static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6530{
6531 u32 ar;
6532 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6533
6534 if (!hw)
6535 return -1;
6536
6537 vstatus->frame_width = hw->frame_width;
6538 vstatus->frame_height = hw->frame_height;
6539 if (hw->frame_dur != 0)
6540 vstatus->frame_rate = 96000 / hw->frame_dur;
6541 else
6542 vstatus->frame_rate = -1;
6543 vstatus->error_count = 0;
6544 vstatus->status = hw->stat;
6545 if (hw->h264_ar == 0x3ff)
6546 hw->h264_ar = (0x100 *
6547 hw->frame_height * hw->height_aspect_ratio) /
6548 (hw->frame_width * hw->width_aspect_ratio);
6549 ar = min_t(u32,
6550 hw->h264_ar,
6551 DISP_RATIO_ASPECT_RATIO_MAX);
6552 vstatus->ratio_control =
6553 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6554
6555 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6556 "%s-%02d", DRIVER_NAME, hw->id);
6557
6558 return 0;
6559}
6560
6561static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6562{
6563 int i, j;
6564 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6565
6566 /* if (hw->init_flag == 0) { */
6567 if (h264_debug_flag & 0x40000000) {
6568 /* if (1) */
6569 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6570 "%s, reset register\n", __func__);
6571
6572 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6573 ;
6574 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6575 ; /* reg address is 0x350 */
6576
6577#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6578 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6579 WRITE_VREG(DOS_SW_RESET0, 0);
6580
6581 READ_VREG(DOS_SW_RESET0);
6582 READ_VREG(DOS_SW_RESET0);
6583 READ_VREG(DOS_SW_RESET0);
6584
6585 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6586 WRITE_VREG(DOS_SW_RESET0, 0);
6587
6588 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6589 WRITE_VREG(DOS_SW_RESET0, 0);
6590
6591 READ_VREG(DOS_SW_RESET0);
6592 READ_VREG(DOS_SW_RESET0);
6593 READ_VREG(DOS_SW_RESET0);
6594
6595#else
6596 WRITE_RESET_REG(RESET0_REGISTER,
6597 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6598 READ_RESET_REG(RESET0_REGISTER);
6599 WRITE_RESET_REG(RESET0_REGISTER,
6600 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6601
6602 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6603#endif
6604 WRITE_VREG(POWER_CTL_VLD,
6605 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6606 (1 << 9) | (1 << 6));
6607 } else {
6608 /* WRITE_VREG(POWER_CTL_VLD,
6609 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6610 */
6611 WRITE_VREG(POWER_CTL_VLD,
6612 READ_VREG(POWER_CTL_VLD) |
6613 (0 << 10) | (1 << 9) | (1 << 6));
6614 }
6615 /* disable PSCALE for hardware sharing */
6616 WRITE_VREG(PSCALE_CTRL, 0);
6617
6618 /* clear mailbox interrupt */
6619 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6620
6621 /* enable mailbox interrupt */
6622 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6623
6624#ifdef NV21
6625 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6626#endif
6627
6628 /* cbcr_merge_swap_en */
6629 if (hw->is_used_v4l
6630 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6631 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6632 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6633
6634 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6635 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6636
6637 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6638 if (hw->mmu_enable) {
6639 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6640 /* sw reset to extif hardware */
6641 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6642 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6643 } else {
6644 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6645 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6646 }
6647
6648
6649#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6650 /* pr_info("vh264 meson8 prot init\n"); */
6651 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6652#endif
6653
6654#ifdef VDEC_DW
6655 if (IS_VDEC_DW(hw)) {
6656 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6657
6658 if (IS_VDEC_DW(hw) == 2)
6659 data |= (1 << 9);
6660 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6661 }
6662#endif
6663 if (hw->dpb.mDPB.size > 0) {
6664 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6665 (hw->dpb.mDPB.size << 16) |
6666 (hw->dpb.mDPB.size << 8));
6667
6668 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6669 i = get_buf_spec_by_canvas_pos(hw, j);
6670 if (i < 0)
6671 break;
6672
6673 if (!hw->mmu_enable &&
6674 hw->buffer_spec[i].cma_alloc_addr)
6675 config_decode_canvas(hw, i);
6676 if (hw->mmu_enable && hw->double_write_mode)
6677 config_decode_canvas_ex(hw, i);
6678 }
6679 } else {
6680 WRITE_VREG(AV_SCRATCH_0, 0);
6681 WRITE_VREG(AV_SCRATCH_9, 0);
6682 }
6683
6684 if (hw->init_flag == 0)
6685 WRITE_VREG(DPB_STATUS_REG, 0);
6686 else
6687 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6688
6689 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6690 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6691 if (!tee_enabled())
6692 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6693
6694 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6695 * error_recovery_mode : error_recovery_mode_in;
6696 */
6697 /* WRITE_VREG(AV_SCRATCH_F,
6698 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6699 */
6700 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6701 ((error_recovery_mode_in & 0x1) << 4));
6702 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6703 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6704 else*/
6705 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6706
6707 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6708#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6709 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6710#endif
6711
6712 WRITE_VREG(DEBUG_REG1, 0);
6713 WRITE_VREG(DEBUG_REG2, 0);
6714
6715 if (hw->reg_iqidct_control)
6716 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6717 if (hw->reg_vcop_ctrl_reg)
6718 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6719 if (hw->vld_dec_control)
6720 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6721 return 0;
6722}
6723
6724static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6725{
6726 struct vdec_h264_hw_s *hw =
6727 (struct vdec_h264_hw_s *)vdec->private;
6728 if (i_only_flag & 0x100)
6729 return 0;
6730 if (trickmode == TRICKMODE_I)
6731 hw->i_only = 0x3;
6732 else if (trickmode == TRICKMODE_NONE)
6733 hw->i_only = 0x0;
6734 return 0;
6735}
6736
6737static unsigned char amvdec_enable_flag;
6738static void vh264_local_init(struct vdec_h264_hw_s *hw)
6739{
6740 int i;
6741 hw->init_flag = 0;
6742 hw->first_sc_checked= 0;
6743 hw->eos = 0;
6744 hw->valve_count = 0;
6745 hw->config_bufmgr_done = 0;
6746 hw->start_process_time = 0;
6747 hw->has_i_frame = 0;
6748 hw->no_error_count = 0xfff;
6749 hw->no_error_i_count = 0xf;
6750
6751 hw->dec_flag = 0;
6752 hw->data_flag = 0;
6753 hw->skip_frame_count = 0;
6754 hw->reg_iqidct_control = 0;
6755 hw->reg_vcop_ctrl_reg = 0;
6756 hw->reg_rv_ai_mb_count = 0;
6757 hw->vld_dec_control = 0;
6758 hw->decode_timeout_count = 0;
6759 hw->no_mem_count = 0;
6760 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6761 /* vh264_ratio = 0x100; */
6762
6763 hw->vh264_rotation = (((unsigned long)
6764 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6765
6766 hw->frame_prog = 0;
6767 hw->frame_width = hw->vh264_amstream_dec_info.width;
6768 hw->frame_height = hw->vh264_amstream_dec_info.height;
6769 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6770 hw->pts_outside = ((unsigned long)
6771 hw->vh264_amstream_dec_info.param) & 0x01;
6772 hw->sync_outside = ((unsigned long)
6773 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6774 hw->use_idr_framerate = ((unsigned long)
6775 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6776 hw->max_refer_buf = !(((unsigned long)
6777 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6778 if (hw->frame_dur < 96000/960) {
6779 /*more than 960fps,it should not be a correct value,
6780 *give default 30fps
6781 */
6782 hw->frame_dur = 96000/30;
6783 }
6784
6785 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6786
6787 hw->first_i_policy = first_i_policy;
6788
6789 if (hw->is_used_v4l)
6790 mem_map_mode = CANVAS_BLKMODE_LINEAR;
6791
6792 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6793 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6794 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6795 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6796
6797 if (i_only_flag & 0x100)
6798 hw->i_only = i_only_flag & 0xff;
6799 if (hw->i_only)
6800 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6801
6802 if ((unsigned long) hw->vh264_amstream_dec_info.param
6803 & 0x08)
6804 hw->no_poc_reorder_flag = 1;
6805
6806 error_recovery_mode_in = 1; /*ucode control?*/
6807 if (error_proc_policy & 0x80000000)
6808 hw->send_error_frame_flag = error_proc_policy & 0x1;
6809 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6810 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6811
6812 INIT_KFIFO(hw->display_q);
6813 INIT_KFIFO(hw->newframe_q);
6814
6815 for (i = 0; i < VF_POOL_SIZE; i++) {
6816 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6817 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6818 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6819 kfifo_put(&hw->newframe_q, vf);
6820 }
6821
6822 hw->duration_from_pts_done = 0;
6823
6824 hw->p_last_vf = NULL;
6825 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6826 hw->hevc_cur_buf_idx = 0xffff;
6827
6828 init_waitqueue_head(&hw->wait_q);
6829
6830 return;
6831}
6832
6833static s32 vh264_init(struct vdec_h264_hw_s *hw)
6834{
6835 int size = -1;
6836 int fw_size = 0x1000 * 16;
6837 int fw_mmu_size = 0x1000 * 16;
6838 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6839
6840 /* int trickmode_fffb = 0; */
6841
6842 /* pr_info("\nvh264_init\n"); */
6843 /* init_timer(&hw->recycle_timer); */
6844
6845 /* timer init */
6846 init_timer(&hw->check_timer);
6847
6848 hw->check_timer.data = (unsigned long)hw;
6849 hw->check_timer.function = check_timer_func;
6850 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6851
6852 /* add_timer(&hw->check_timer); */
6853 hw->stat |= STAT_TIMER_ARM;
6854 hw->stat |= STAT_ISR_REG;
6855
6856 mutex_init(&hw->chunks_mutex);
6857 vh264_local_init(hw);
6858 INIT_WORK(&hw->work, vh264_work);
6859 INIT_WORK(&hw->notify_work, vh264_notify_work);
6860 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6861#ifdef MH264_USERDATA_ENABLE
6862 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6863#endif
6864
6865 if (!amvdec_enable_flag) {
6866 amvdec_enable_flag = true;
6867 amvdec_enable();
6868 if (hw->mmu_enable)
6869 amhevc_enable();
6870 }
6871 if (hw->mmu_enable) {
6872
6873 hw->frame_mmu_map_addr =
6874 dma_alloc_coherent(amports_get_dma_device(),
6875 FRAME_MMU_MAP_SIZE,
6876 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6877 if (hw->frame_mmu_map_addr == NULL) {
6878 pr_err("%s: failed to alloc count_buffer\n", __func__);
6879 return -ENOMEM;
6880 }
6881 }
6882
6883 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6884 if (IS_ERR_OR_NULL(fw))
6885 return -ENOMEM;
6886
6887 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6888 if (size < 0) {
6889 pr_err("get firmware fail.\n");
6890 vfree(fw);
6891 return -1;
6892 }
6893
6894 fw->len = size;
6895 hw->fw = fw;
6896
6897 if (hw->mmu_enable) {
6898 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6899 if (IS_ERR_OR_NULL(fw_mmu))
6900 return -ENOMEM;
6901
6902 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6903 if (size < 0) {
6904 pr_err("get mmu fw fail.\n");
6905 vfree(fw_mmu);
6906 return -1;
6907 }
6908
6909 fw_mmu->len = size;
6910 hw->fw_mmu = fw_mmu;
6911 }
6912
6913 if (!tee_enabled()) {
6914 /* -- ucode loading (amrisc and swap code) */
6915 hw->mc_cpu_addr =
6916 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6917 &hw->mc_dma_handle, GFP_KERNEL);
6918 if (!hw->mc_cpu_addr) {
6919 amvdec_enable_flag = false;
6920 amvdec_disable();
6921 if (hw->mmu_enable)
6922 amhevc_disable();
6923 pr_info("vh264_init: Can not allocate mc memory.\n");
6924 return -ENOMEM;
6925 }
6926
6927 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6928 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6929 */
6930
6931 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6932
6933 /*header*/
6934 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6935 fw->data + 0x4000, MC_SWAP_SIZE);
6936 /*data*/
6937 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6938 fw->data + 0x2000, MC_SWAP_SIZE);
6939 /*mmco*/
6940 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6941 fw->data + 0x6000, MC_SWAP_SIZE);
6942 /*list*/
6943 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6944 fw->data + 0x3000, MC_SWAP_SIZE);
6945 /*slice*/
6946 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6947 fw->data + 0x5000, MC_SWAP_SIZE);
6948 /*main*/
6949 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6950 fw->data, 0x2000);
6951 /*data*/
6952 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6953 fw->data + 0x2000, 0x1000);
6954 /*slice*/
6955 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6956 fw->data + 0x5000, 0x1000);
6957 }
6958
6959#if 1 /* #ifdef BUFFER_MGR_IN_C */
6960 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6961 if (!hw->lmem_addr) {
6962 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6963 return -ENOMEM;
6964 } else {
6965 hw->lmem_addr_remap = dma_map_single(
6966 amports_get_dma_device(),
6967 (void *)hw->lmem_addr,
6968 PAGE_SIZE, DMA_FROM_DEVICE);
6969 if (dma_mapping_error(amports_get_dma_device(),
6970 hw->lmem_addr_remap)) {
6971 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6972 "%s: failed to map lmem_addr\n", __func__);
6973 free_page(hw->lmem_addr);
6974 hw->lmem_addr = 0;
6975 hw->lmem_addr_remap = 0;
6976 return -ENOMEM;
6977 }
6978
6979 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6980 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6981 }
6982
6983 if (prefix_aux_buf_size > 0 ||
6984 suffix_aux_buf_size > 0) {
6985 u32 aux_buf_size;
6986 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6987 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
6988 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
6989 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
6990 if (hw->aux_addr == NULL) {
6991 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6992 return -1;
6993 }
6994
6995 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
6996 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
6997 if (dma_mapping_error(amports_get_dma_device(),
6998 hw->aux_phy_addr)) {
6999 pr_err("%s: failed to map rpm buffer\n", __func__);
7000 kfree(hw->aux_addr);
7001 hw->aux_addr = NULL;
7002 return -1;
7003 }
7004 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7005 if (hw->sei_data_buf == NULL) {
7006 pr_err("%s: failed to alloc sei itu data buffer\n",
7007 __func__);
7008 return -1;
7009 }
7010 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7011 if (hw->sei_itu_data_buf == NULL) {
7012 pr_err("%s: failed to alloc sei itu data buffer\n",
7013 __func__);
7014 kfree(hw->aux_addr);
7015 hw->aux_addr = NULL;
7016 kfree(hw->sei_data_buf);
7017 hw->sei_data_buf = NULL;
7018
7019 return -1;
7020 }
7021
7022 if (NULL == hw->sei_user_data_buffer) {
7023 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7024 GFP_KERNEL);
7025 if (!hw->sei_user_data_buffer) {
7026 pr_info("%s: Can not allocate sei_data_buffer\n",
7027 __func__);
7028 kfree(hw->aux_addr);
7029 hw->aux_addr = NULL;
7030 kfree(hw->sei_data_buf);
7031 hw->sei_data_buf = NULL;
7032 kfree(hw->sei_itu_data_buf);
7033 hw->sei_itu_data_buf = NULL;
7034
7035 return -1;
7036 }
7037 hw->sei_user_data_wp = 0;
7038 }
7039 }
7040/* BUFFER_MGR_IN_C */
7041#endif
7042 hw->stat |= STAT_MC_LOAD;
7043
7044 /* add memory barrier */
7045 wmb();
7046
7047 return 0;
7048}
7049
7050static int vh264_stop(struct vdec_h264_hw_s *hw)
7051{
7052 if (hw->stat & STAT_VDEC_RUN) {
7053 amvdec_stop();
7054 hw->stat &= ~STAT_VDEC_RUN;
7055 }
7056#ifdef VDEC_DW
7057 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7058#endif
7059#ifdef MH264_USERDATA_ENABLE
7060 cancel_work_sync(&hw->user_data_ready_work);
7061#endif
7062 cancel_work_sync(&hw->notify_work);
7063 cancel_work_sync(&hw->timeout_work);
7064 cancel_work_sync(&hw->work);
7065
7066
7067 if (hw->stat & STAT_MC_LOAD) {
7068 if (hw->mc_cpu_addr != NULL) {
7069 dma_free_coherent(amports_get_dma_device(),
7070 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7071 hw->mc_dma_handle);
7072 hw->mc_cpu_addr = NULL;
7073 }
7074 if (hw->frame_mmu_map_addr != NULL) {
7075 dma_free_coherent(amports_get_dma_device(),
7076 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7077 hw->frame_mmu_map_phy_addr);
7078 hw->frame_mmu_map_addr = NULL;
7079 }
7080
7081 }
7082 if (hw->stat & STAT_ISR_REG) {
7083 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7084 hw->stat &= ~STAT_ISR_REG;
7085 }
7086 if (hw->lmem_addr_remap) {
7087 dma_unmap_single(amports_get_dma_device(),
7088 hw->lmem_addr_remap,
7089 PAGE_SIZE, DMA_FROM_DEVICE);
7090 hw->lmem_addr_remap = 0;
7091 }
7092 if (hw->lmem_addr) {
7093 free_page(hw->lmem_addr);
7094 hw->lmem_addr = 0;
7095 }
7096 if (hw->aux_addr) {
7097 dma_unmap_single(amports_get_dma_device(),
7098 hw->aux_phy_addr,
7099 hw->prefix_aux_size + hw->suffix_aux_size,
7100 DMA_FROM_DEVICE);
7101 kfree(hw->aux_addr);
7102 hw->aux_addr = NULL;
7103 }
7104 if (hw->sei_data_buf != NULL) {
7105 kfree(hw->sei_data_buf);
7106 hw->sei_data_buf = NULL;
7107 }
7108 if (hw->sei_itu_data_buf != NULL) {
7109 kfree(hw->sei_itu_data_buf);
7110 hw->sei_itu_data_buf = NULL;
7111 }
7112 if (hw->sei_user_data_buffer != NULL) {
7113 kfree(hw->sei_user_data_buffer);
7114 hw->sei_user_data_buffer = NULL;
7115 }
7116 /* amvdec_disable(); */
7117
7118 vfree(hw->fw);
7119 hw->fw = NULL;
7120
7121 if (hw->mmu_enable) {
7122 vfree(hw->fw_mmu);
7123 hw->fw_mmu = NULL;
7124 }
7125
7126 dpb_print(DECODE_ID(hw), 0,
7127 "%s\n",
7128 __func__);
7129 return 0;
7130}
7131
7132static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7133{
7134 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7135 int count = 0;
7136 do {
7137 usleep_range(100, 500);
7138 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7139 break;
7140 if (count > 2000) {
7141 dpb_print(DECODE_ID(hw),
7142 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7143 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7144 break;
7145 } else
7146 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7147 count++;
7148 } while (1);
7149}
7150
7151static void vh264_notify_work(struct work_struct *work)
7152{
7153 struct vdec_h264_hw_s *hw = container_of(work,
7154 struct vdec_h264_hw_s, notify_work);
7155 struct vdec_s *vdec = hw_to_vdec(hw);
7156 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7157 vf_notify_receiver(vdec->vf_provider_name,
7158 VFRAME_EVENT_PROVIDER_FR_HINT,
7159 (void *)((unsigned long)hw->frame_dur));
7160 vdec->fr_hint_state = VDEC_HINTED;
7161 }
7162
7163 return;
7164}
7165
7166#ifdef MH264_USERDATA_ENABLE
7167static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7168{
7169 hw->wait_for_udr_send = 0;
7170 hw->sei_itu_data_len = 0;
7171 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7172}
7173
7174static void vmh264_crate_userdata_manager(
7175 struct vdec_h264_hw_s *hw,
7176 u8 *userdata_buf,
7177 int buf_len)
7178{
7179 if (hw) {
7180
7181
7182 mutex_init(&hw->userdata_mutex);
7183
7184 memset(&hw->userdata_info, 0,
7185 sizeof(struct mh264_userdata_info_t));
7186 hw->userdata_info.data_buf = userdata_buf;
7187 hw->userdata_info.buf_len = buf_len;
7188 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7189
7190 vmh264_reset_udr_mgr(hw);
7191
7192 }
7193}
7194
7195static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7196{
7197 if (hw)
7198 memset(&hw->userdata_info,
7199 0,
7200 sizeof(struct mh264_userdata_info_t));
7201}
7202
7203/*
7204#define DUMP_USERDATA_RECORD
7205*/
7206#ifdef DUMP_USERDATA_RECORD
7207
7208#define MAX_USER_DATA_SIZE 3145728
7209static void *user_data_buf;
7210static unsigned char *pbuf_start;
7211static int total_len;
7212static int bskip;
7213static int n_userdata_id;
7214
7215static void print_data(unsigned char *pdata,
7216 int len,
7217 unsigned int poc_number,
7218 unsigned int flag,
7219 unsigned int duration,
7220 unsigned int vpts,
7221 unsigned int vpts_valid,
7222 int rec_id)
7223{
7224 int nLeft;
7225
7226 nLeft = len;
7227#if 0
7228 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7229 rec_id, len, flag,
7230 duration, vpts, vpts_valid, poc_number);
7231#endif
7232 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7233 rec_id, len, flag, vpts);
7234
7235 if (len == 96) {
7236 int i;
7237 nLeft = 72;
7238 while (nLeft >= 16) {
7239 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7240 pdata[0], pdata[1], pdata[2], pdata[3],
7241 pdata[4], pdata[5], pdata[6], pdata[7],
7242 pdata[8], pdata[9], pdata[10], pdata[11],
7243 pdata[12], pdata[13], pdata[14], pdata[15]);
7244 nLeft -= 16;
7245 pdata += 16;
7246 }
7247
7248
7249 while (nLeft > 0) {
7250 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7251 pdata[0], pdata[1], pdata[2], pdata[3],
7252 pdata[4], pdata[5], pdata[6], pdata[7]);
7253 nLeft -= 8;
7254 pdata += 8;
7255 }
7256
7257 i = 0;
7258 nLeft = 96-72;
7259 while (i < nLeft) {
7260 if (pdata[0] != 0) {
7261 pr_info("some data error\n");
7262 break;
7263 }
7264 pdata++;
7265 i++;
7266 }
7267 } else {
7268 while (nLeft >= 16) {
7269 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7270 pdata[0], pdata[1], pdata[2], pdata[3],
7271 pdata[4], pdata[5], pdata[6], pdata[7],
7272 pdata[8], pdata[9], pdata[10], pdata[11],
7273 pdata[12], pdata[13], pdata[14], pdata[15]);
7274 nLeft -= 16;
7275 pdata += 16;
7276 }
7277
7278
7279 while (nLeft > 0) {
7280 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7281 pdata[0], pdata[1], pdata[2], pdata[3],
7282 pdata[4], pdata[5], pdata[6], pdata[7]);
7283 nLeft -= 8;
7284 pdata += 8;
7285 }
7286
7287 }
7288}
7289
7290static void push_to_buf(struct vdec_h264_hw_s *hw,
7291 u8 *pdata,
7292 int len,
7293 struct userdata_meta_info_t *pmeta);
7294
7295static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7296 struct mh264_userdata_record_t *record)
7297{
7298 if (record && hw) {
7299 u8 *pdata;
7300
7301 pdata = hw->userdata_info.data_buf + record->rec_start;
7302/*
7303 print_data(pdata,
7304 record->rec_len,
7305 record->meta_info.flags,
7306 record->meta_info.duration,
7307 record->meta_info.vpts,
7308 record->meta_info.vpts_valid,
7309 n_record_id);
7310*/
7311 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7312 n_userdata_id++;
7313 }
7314}
7315
7316
7317static void push_to_buf(struct vdec_h264_hw_s *hw,
7318 u8 *pdata, int len,
7319 struct userdata_meta_info_t *pmeta)
7320{
7321 u32 *pLen;
7322 int info_cnt;
7323 u8 *pbuf_end;
7324
7325 if (!user_data_buf)
7326 return;
7327
7328 if (bskip) {
7329 pr_info("over size, skip\n");
7330 return;
7331 }
7332 info_cnt = 0;
7333 pLen = (u32 *)pbuf_start;
7334
7335 *pLen = len;
7336 pbuf_start += sizeof(u32);
7337 info_cnt++;
7338 pLen++;
7339
7340 *pLen = pmeta->poc_number;
7341 pbuf_start += sizeof(u32);
7342 info_cnt++;
7343 pLen++;
7344
7345 *pLen = pmeta->duration;
7346 pbuf_start += sizeof(u32);
7347 info_cnt++;
7348 pLen++;
7349
7350 *pLen = pmeta->flags;
7351 pbuf_start += sizeof(u32);
7352 info_cnt++;
7353 pLen++;
7354
7355 *pLen = pmeta->vpts;
7356 pbuf_start += sizeof(u32);
7357 info_cnt++;
7358 pLen++;
7359
7360 *pLen = pmeta->vpts_valid;
7361 pbuf_start += sizeof(u32);
7362 info_cnt++;
7363 pLen++;
7364
7365
7366 *pLen = n_userdata_id;
7367 pbuf_start += sizeof(u32);
7368 info_cnt++;
7369 pLen++;
7370
7371
7372
7373 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7374 if (pdata + len > pbuf_end) {
7375 int first_section_len;
7376
7377 first_section_len = pbuf_end - pdata;
7378 memcpy(pbuf_start, pdata, first_section_len);
7379 pdata = (u8 *)hw->sei_user_data_buffer;
7380 pbuf_start += first_section_len;
7381 memcpy(pbuf_start, pdata, len - first_section_len);
7382 pbuf_start += len - first_section_len;
7383 } else {
7384 memcpy(pbuf_start, pdata, len);
7385 pbuf_start += len;
7386 }
7387
7388 total_len += len + info_cnt * sizeof(u32);
7389 if (total_len >= MAX_USER_DATA_SIZE-4096)
7390 bskip = 1;
7391}
7392
7393static void show_user_data_buf(void)
7394{
7395 u8 *pbuf;
7396 int len;
7397 unsigned int flag;
7398 unsigned int duration;
7399 unsigned int vpts;
7400 unsigned int vpts_valid;
7401 unsigned int poc_number;
7402 int rec_id;
7403
7404 pr_info("show user data buf\n");
7405 pbuf = user_data_buf;
7406
7407 while (pbuf < pbuf_start) {
7408 u32 *pLen;
7409
7410 pLen = (u32 *)pbuf;
7411
7412 len = *pLen;
7413 pLen++;
7414 pbuf += sizeof(u32);
7415
7416 poc_number = *pLen;
7417 pLen++;
7418 pbuf += sizeof(u32);
7419
7420 duration = *pLen;
7421 pLen++;
7422 pbuf += sizeof(u32);
7423
7424 flag = *pLen;
7425 pLen++;
7426 pbuf += sizeof(u32);
7427
7428 vpts = *pLen;
7429 pLen++;
7430 pbuf += sizeof(u32);
7431
7432 vpts_valid = *pLen;
7433 pLen++;
7434 pbuf += sizeof(u32);
7435
7436 rec_id = *pLen;
7437 pLen++;
7438 pbuf += sizeof(u32);
7439
7440 print_data(pbuf, len, poc_number, flag,
7441 duration, vpts,
7442 vpts_valid, rec_id);
7443 pbuf += len;
7444 msleep(30);
7445 }
7446}
7447
7448static int vmh264_init_userdata_dump(void)
7449{
7450 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7451 if (user_data_buf)
7452 return 1;
7453 else
7454 return 0;
7455}
7456
7457static void vmh264_dump_userdata(void)
7458{
7459 if (user_data_buf) {
7460 show_user_data_buf();
7461 kfree(user_data_buf);
7462 user_data_buf = NULL;
7463 }
7464}
7465
7466static void vmh264_reset_user_data_buf(void)
7467{
7468 total_len = 0;
7469 pbuf_start = user_data_buf;
7470 bskip = 0;
7471 n_userdata_id = 0;
7472}
7473#endif
7474
7475
7476static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7477 int frame_type,
7478 u32 vpts,
7479 u32 vpts_valid)
7480{
7481 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7482
7483 unsigned char *pdata;
7484 u8 *pmax_sei_data_buffer;
7485 u8 *sei_data_buf;
7486 int i;
7487 int wp;
7488 int data_length;
7489 struct mh264_userdata_record_t *p_userdata_rec;
7490
7491
7492#ifdef MH264_USERDATA_ENABLE
7493 struct userdata_meta_info_t meta_info;
7494 memset(&meta_info, 0, sizeof(meta_info));
7495#endif
7496
7497 if (hw->sei_itu_data_len <= 0)
7498 return;
7499
7500 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7501 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7502 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7503 for (i = 0; i < hw->sei_itu_data_len; i++) {
7504 *pdata++ = sei_data_buf[i];
7505 if (pdata >= pmax_sei_data_buffer)
7506 pdata = (u8 *)hw->sei_user_data_buffer;
7507 }
7508
7509 hw->sei_user_data_wp = (hw->sei_user_data_wp
7510 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7511 hw->sei_itu_data_len = 0;
7512
7513#ifdef MH264_USERDATA_ENABLE
7514 meta_info.duration = hw->frame_dur;
7515 meta_info.flags |= (VFORMAT_H264 << 3);
7516
7517 meta_info.vpts = vpts;
7518 meta_info.vpts_valid = vpts_valid;
7519 meta_info.poc_number =
7520 p_H264_Dpb->mVideo.dec_picture->poc;
7521
7522
7523 wp = hw->sei_user_data_wp;
7524
7525 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7526 data_length = wp - hw->userdata_info.last_wp;
7527 else
7528 data_length = wp + hw->userdata_info.buf_len
7529 - hw->userdata_info.last_wp;
7530
7531 if (data_length & 0x7)
7532 data_length = (((data_length + 8) >> 3) << 3);
7533
7534 p_userdata_rec = &hw->ud_record;
7535 p_userdata_rec->meta_info = meta_info;
7536 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7537 p_userdata_rec->rec_len = data_length;
7538 hw->userdata_info.last_wp = wp;
7539
7540 p_userdata_rec->meta_info.flags |=
7541 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7542
7543 hw->wait_for_udr_send = 1;
7544 vdec_schedule_work(&hw->user_data_ready_work);
7545#endif
7546}
7547
7548
7549static void user_data_ready_notify_work(struct work_struct *work)
7550{
7551 struct vdec_h264_hw_s *hw = container_of(work,
7552 struct vdec_h264_hw_s, user_data_ready_work);
7553
7554
7555 mutex_lock(&hw->userdata_mutex);
7556
7557 hw->userdata_info.records[hw->userdata_info.write_index]
7558 = hw->ud_record;
7559 hw->userdata_info.write_index++;
7560 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7561 hw->userdata_info.write_index = 0;
7562
7563 mutex_unlock(&hw->userdata_mutex);
7564
7565#ifdef DUMP_USERDATA_RECORD
7566 dump_userdata_record(hw, &hw->ud_record);
7567#endif
7568 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7569
7570 hw->wait_for_udr_send = 0;
7571}
7572
7573static int vmh264_user_data_read(struct vdec_s *vdec,
7574 struct userdata_param_t *puserdata_para)
7575{
7576 struct vdec_h264_hw_s *hw = NULL;
7577 int rec_ri, rec_wi;
7578 int rec_len;
7579 u8 *rec_data_start;
7580 u8 *pdest_buf;
7581 struct mh264_userdata_record_t *p_userdata_rec;
7582 u32 data_size;
7583 u32 res;
7584 int copy_ok = 1;
7585
7586 hw = (struct vdec_h264_hw_s *)vdec->private;
7587
7588 pdest_buf = puserdata_para->pbuf_addr;
7589
7590 mutex_lock(&hw->userdata_mutex);
7591
7592/*
7593 pr_info("ri = %d, wi = %d\n",
7594 lg_p_mpeg12_userdata_info->read_index,
7595 lg_p_mpeg12_userdata_info->write_index);
7596*/
7597 rec_ri = hw->userdata_info.read_index;
7598 rec_wi = hw->userdata_info.write_index;
7599
7600 if (rec_ri == rec_wi) {
7601 mutex_unlock(&hw->userdata_mutex);
7602 return 0;
7603 }
7604
7605 p_userdata_rec = hw->userdata_info.records + rec_ri;
7606
7607 rec_len = p_userdata_rec->rec_len;
7608 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7609/*
7610 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7611 p_userdata_rec->rec_len,
7612 p_userdata_rec->rec_start,
7613 puserdata_para->buf_len);
7614*/
7615 if (rec_len <= puserdata_para->buf_len) {
7616 /* dvb user data buffer is enought to
7617 copy the whole recored. */
7618 data_size = rec_len;
7619 if (rec_data_start + data_size
7620 > hw->userdata_info.data_buf_end) {
7621 int first_section_len;
7622
7623 first_section_len = hw->userdata_info.buf_len -
7624 p_userdata_rec->rec_start;
7625 res = (u32)copy_to_user((void *)pdest_buf,
7626 (void *)rec_data_start,
7627 first_section_len);
7628 if (res) {
7629 pr_info("p1 read not end res=%d, request=%d\n",
7630 res, first_section_len);
7631 copy_ok = 0;
7632
7633 p_userdata_rec->rec_len -=
7634 first_section_len - res;
7635 p_userdata_rec->rec_start +=
7636 first_section_len - res;
7637 puserdata_para->data_size =
7638 first_section_len - res;
7639 } else {
7640 res = (u32)copy_to_user(
7641 (void *)(pdest_buf+first_section_len),
7642 (void *)hw->userdata_info.data_buf,
7643 data_size - first_section_len);
7644 if (res) {
7645 pr_info("p2 read not end res=%d, request=%d\n",
7646 res, data_size);
7647 copy_ok = 0;
7648 }
7649 p_userdata_rec->rec_len -=
7650 data_size - res;
7651 p_userdata_rec->rec_start =
7652 data_size - first_section_len - res;
7653 puserdata_para->data_size =
7654 data_size - res;
7655 }
7656 } else {
7657 res = (u32)copy_to_user((void *)pdest_buf,
7658 (void *)rec_data_start,
7659 data_size);
7660 if (res) {
7661 pr_info("p3 read not end res=%d, request=%d\n",
7662 res, data_size);
7663 copy_ok = 0;
7664 }
7665 p_userdata_rec->rec_len -= data_size - res;
7666 p_userdata_rec->rec_start += data_size - res;
7667 puserdata_para->data_size = data_size - res;
7668 }
7669
7670 if (copy_ok) {
7671 hw->userdata_info.read_index++;
7672 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7673 hw->userdata_info.read_index = 0;
7674 }
7675 } else {
7676 /* dvb user data buffer is not enought
7677 to copy the whole recored. */
7678 data_size = puserdata_para->buf_len;
7679 if (rec_data_start + data_size
7680 > hw->userdata_info.data_buf_end) {
7681 int first_section_len;
7682
7683 first_section_len = hw->userdata_info.buf_len -
7684 p_userdata_rec->rec_start;
7685 res = (u32)copy_to_user((void *)pdest_buf,
7686 (void *)rec_data_start,
7687 first_section_len);
7688 if (res) {
7689 pr_info("p4 read not end res=%d, request=%d\n",
7690 res, first_section_len);
7691 copy_ok = 0;
7692 p_userdata_rec->rec_len -=
7693 first_section_len - res;
7694 p_userdata_rec->rec_start +=
7695 first_section_len - res;
7696 puserdata_para->data_size =
7697 first_section_len - res;
7698 } else {
7699 /* first secton copy is ok*/
7700 res = (u32)copy_to_user(
7701 (void *)(pdest_buf+first_section_len),
7702 (void *)hw->userdata_info.data_buf,
7703 data_size - first_section_len);
7704 if (res) {
7705 pr_info("p5 read not end res=%d, request=%d\n",
7706 res,
7707 data_size - first_section_len);
7708 copy_ok = 0;
7709 }
7710
7711 p_userdata_rec->rec_len -=
7712 data_size - res;
7713 p_userdata_rec->rec_start =
7714 data_size - first_section_len - res;
7715 puserdata_para->data_size =
7716 data_size - res;
7717 }
7718 } else {
7719 res = (u32)copy_to_user((void *)pdest_buf,
7720 (void *)rec_data_start,
7721 data_size);
7722 if (res) {
7723 pr_info("p6 read not end res=%d, request=%d\n",
7724 res, data_size);
7725 copy_ok = 0;
7726 }
7727
7728 p_userdata_rec->rec_len -= data_size - res;
7729 p_userdata_rec->rec_start += data_size - res;
7730 puserdata_para->data_size = data_size - res;
7731 }
7732
7733 if (copy_ok) {
7734 hw->userdata_info.read_index++;
7735 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7736 hw->userdata_info.read_index = 0;
7737 }
7738
7739 }
7740 puserdata_para->meta_info = p_userdata_rec->meta_info;
7741
7742 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7743 puserdata_para->meta_info.records_in_que =
7744 hw->userdata_info.write_index -
7745 hw->userdata_info.read_index;
7746 else
7747 puserdata_para->meta_info.records_in_que =
7748 hw->userdata_info.write_index +
7749 USERDATA_FIFO_NUM -
7750 hw->userdata_info.read_index;
7751
7752 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7753
7754 mutex_unlock(&hw->userdata_mutex);
7755
7756 return 1;
7757}
7758
7759static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7760{
7761 struct vdec_h264_hw_s *hw = NULL;
7762
7763 hw = (struct vdec_h264_hw_s *)vdec->private;
7764
7765 if (hw) {
7766 mutex_lock(&hw->userdata_mutex);
7767 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7768 bInit,
7769 hw->userdata_info.read_index,
7770 hw->userdata_info.write_index);
7771 hw->userdata_info.read_index = 0;
7772 hw->userdata_info.write_index = 0;
7773
7774 if (bInit)
7775 hw->userdata_info.last_wp = 0;
7776 mutex_unlock(&hw->userdata_mutex);
7777 }
7778}
7779
7780static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7781{
7782 amstream_wakeup_userdata_poll(vdec);
7783}
7784
7785#endif
7786
7787
7788static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7789 struct vdec_s *vdec, int from)
7790{
7791 /* finished decoding one frame or error,
7792 * notify vdec core to switch context
7793 */
7794 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7795 "%s dec_result %d %x %x %x\n",
7796 __func__,
7797 hw->dec_result,
7798 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7799 READ_VREG(VLD_MEM_VIFIFO_WP),
7800 READ_VREG(VLD_MEM_VIFIFO_RP));
7801 if (!hw->mmu_enable) {
7802 mutex_lock(&vmh264_mutex);
7803 dealloc_buf_specs(hw, 0);
7804 mutex_unlock(&vmh264_mutex);
7805 }
7806 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7807 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7808 u32 param1 = READ_VREG(AV_SCRATCH_1);
7809 u32 param2 = READ_VREG(AV_SCRATCH_2);
7810 u32 param3 = READ_VREG(AV_SCRATCH_6);
7811 u32 param4 = READ_VREG(AV_SCRATCH_B);
7812
7813 if (vh264_set_params(hw, param1,
7814 param2, param3, param4) < 0)
7815 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7816
7817 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7818 (hw->dpb.mDPB.size<<16) |
7819 (hw->dpb.mDPB.size<<8));
7820
7821 if (hw->is_used_v4l) {
7822 struct aml_vcodec_ctx *ctx =
7823 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7824
7825 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7826 struct aml_vdec_pic_infos info;
7827
7828 info.visible_width = hw->frame_width;
7829 info.visible_height = hw->frame_height;
7830 info.coded_width = ALIGN(hw->frame_width, 64);
7831 info.coded_height = ALIGN(hw->frame_height, 64);
7832 info.dpb_size = hw->dpb.mDPB.size;
7833 hw->v4l_params_parsed = true;
7834 vdec_v4l_set_pic_infos(ctx, &info);
7835 }
7836 }
7837
7838 start_process_time(hw);
7839 return;
7840 } else
7841 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7842 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7843 && (hw_to_vdec(hw)->next_status !=
7844 VDEC_STATUS_DISCONNECTED)) {
7845 if (!vdec_has_more_input(vdec)) {
7846 hw->dec_result = DEC_RESULT_EOS;
7847 vdec_schedule_work(&hw->work);
7848 return;
7849 }
7850
7851 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7852 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7853 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7854 __func__,
7855 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7856 READ_VREG(VLD_MEM_VIFIFO_WP),
7857 READ_VREG(VLD_MEM_VIFIFO_RP));
7858 mutex_lock(&hw->chunks_mutex);
7859 vdec_vframe_dirty(vdec, hw->chunk);
7860 hw->chunk = NULL;
7861 mutex_unlock(&hw->chunks_mutex);
7862 vdec_clean_input(vdec);
7863 }
7864 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7865 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7866 > get_data_timeout_val)) {
7867 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7868 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7869 __func__);
7870 goto result_done;
7871 }
7872 if (is_buffer_available(vdec)) {
7873 int r;
7874 int decode_size;
7875 r = vdec_prepare_input(vdec, &hw->chunk);
7876 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7877 VDEC_STATUS_DISCONNECTED)) {
7878 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7879
7880 dpb_print(DECODE_ID(hw),
7881 PRINT_FLAG_VDEC_DETAIL,
7882 "vdec_prepare_input: Insufficient data\n");
7883 vdec_schedule_work(&hw->work);
7884 return;
7885 }
7886 hw->dec_result = DEC_RESULT_NONE;
7887 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7888 "%s: chunk size 0x%x\n",
7889 __func__, hw->chunk->size);
7890
7891 if (dpb_is_debug(DECODE_ID(hw),
7892 PRINT_FRAMEBASE_DATA)) {
7893 int jj;
7894 u8 *data = NULL;
7895
7896 if (!hw->chunk->block->is_mapped)
7897 data = codec_mm_vmap(
7898 hw->chunk->block->start +
7899 hw->chunk->offset, r);
7900 else
7901 data = ((u8 *)
7902 hw->chunk->block->start_virt)
7903 + hw->chunk->offset;
7904
7905 for (jj = 0; jj < r; jj++) {
7906 if ((jj & 0xf) == 0)
7907 dpb_print(DECODE_ID(hw),
7908 PRINT_FRAMEBASE_DATA,
7909 "%06x:", jj);
7910 dpb_print_cont(DECODE_ID(hw),
7911 PRINT_FRAMEBASE_DATA,
7912 "%02x ", data[jj]);
7913 if (((jj + 1) & 0xf) == 0)
7914 dpb_print_cont(DECODE_ID(hw),
7915 PRINT_FRAMEBASE_DATA,
7916 "\n");
7917 }
7918
7919 if (!hw->chunk->block->is_mapped)
7920 codec_mm_unmap_phyaddr(data);
7921 }
7922 WRITE_VREG(POWER_CTL_VLD,
7923 READ_VREG(POWER_CTL_VLD) |
7924 (0 << 10) | (1 << 9) | (1 << 6));
7925 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7926 decode_size = hw->chunk->size +
7927 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7928 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7929 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7930 vdec_enable_input(vdec);
7931
7932 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7933 start_process_time(hw);
7934 } else{
7935 if (hw_to_vdec(hw)->next_status
7936 != VDEC_STATUS_DISCONNECTED) {
7937 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7938 vdec_schedule_work(&hw->work);
7939 }
7940 }
7941 return;
7942 } else if (hw->dec_result == DEC_RESULT_DONE) {
7943 /* if (!hw->ctx_valid)
7944 hw->ctx_valid = 1; */
7945result_done:
7946 if (hw->mmu_enable
7947 && hw->frame_busy && hw->frame_done) {
7948 long used_4k_num;
7949 hevc_sao_wait_done(hw);
7950 if (hw->hevc_cur_buf_idx != 0xffff) {
7951 used_4k_num =
7952 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7953 if (used_4k_num >= 0)
7954 dpb_print(DECODE_ID(hw),
7955 PRINT_FLAG_MMU_DETAIL,
7956 "release unused buf , used_4k_num %ld index %d\n",
7957 used_4k_num, hw->hevc_cur_buf_idx);
7958 hevc_mmu_dma_check(hw_to_vdec(hw));
7959 decoder_mmu_box_free_idx_tail(
7960 hw->mmu_box,
7961 hw->hevc_cur_buf_idx,
7962 used_4k_num);
7963 hw->hevc_cur_buf_idx = 0xffff;
7964 }
7965 }
7966 decode_frame_count[DECODE_ID(hw)]++;
7967 amvdec_stop();
7968 if (!vdec_is_support_4k()) {
7969 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7970 clk_adj_frame_count++;
7971 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7972 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7973 }
7974 }
7975 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7976 "%s dec_result %d %x %x %x\n",
7977 __func__,
7978 hw->dec_result,
7979 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7980 READ_VREG(VLD_MEM_VIFIFO_WP),
7981 READ_VREG(VLD_MEM_VIFIFO_RP));
7982 mutex_lock(&hw->chunks_mutex);
7983 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7984 hw->chunk = NULL;
7985 mutex_unlock(&hw->chunks_mutex);
7986 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7987 /*
7988 stream base: stream buf empty or timeout
7989 frame base: vdec_prepare_input fail
7990 */
7991 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
7992 VDEC_STATUS_DISCONNECTED)) {
7993 hw->dec_result = DEC_RESULT_EOS;
7994 vdec_schedule_work(&hw->work);
7995 return;
7996 }
7997 hw->next_again_flag = 1;
7998 } else if (hw->dec_result == DEC_RESULT_EOS) {
7999 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8000 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8001 "%s: end of stream\n",
8002 __func__);
8003 amvdec_stop();
8004 if (hw->mmu_enable)
8005 amhevc_stop();
8006 hw->eos = 1;
8007 flush_dpb(p_H264_Dpb);
8008 if (hw->is_used_v4l)
8009 notify_v4l_eos(hw_to_vdec(hw));
8010 mutex_lock(&hw->chunks_mutex);
8011 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8012 hw->chunk = NULL;
8013 mutex_unlock(&hw->chunks_mutex);
8014 vdec_clean_input(vdec);
8015 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8016 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8017 "%s: force exit\n",
8018 __func__);
8019 amvdec_stop();
8020 if (hw->mmu_enable)
8021 amhevc_stop();
8022 if (hw->stat & STAT_ISR_REG) {
8023 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8024 hw->stat &= ~STAT_ISR_REG;
8025 }
8026 }
8027 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8028 del_timer_sync(&hw->check_timer);
8029 hw->stat &= ~STAT_TIMER_ARM;
8030
8031 wait_vmh264_search_done(hw);
8032 /* mark itself has all HW resource released and input released */
8033
8034#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8035 if (hw->switch_dvlayer_flag) {
8036 if (vdec->slave)
8037 vdec_set_next_sched(vdec, vdec->slave);
8038 else if (vdec->master)
8039 vdec_set_next_sched(vdec, vdec->master);
8040 } else if (vdec->slave || vdec->master)
8041 vdec_set_next_sched(vdec, vdec);
8042#endif
8043
8044 if (from == 1) {
8045 /* This is a timeout work */
8046 if (work_pending(&hw->work)) {
8047 /*
8048 * The vh264_work arrives at the last second,
8049 * give it a chance to handle the scenario.
8050 */
8051 return;
8052 }
8053 }
8054
8055 /* mark itself has all HW resource released and input released */
8056 if (vdec->parallel_dec == 1) {
8057 if (hw->mmu_enable == 0)
8058 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8059 else
8060 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8061 } else
8062 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8063
8064 wake_up_interruptible(&hw->wait_q);
8065
8066 if (hw->is_used_v4l) {
8067 struct aml_vcodec_ctx *ctx =
8068 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8069
8070 if (ctx->param_sets_from_ucode &&
8071 !hw->v4l_params_parsed)
8072 vdec_v4l_write_frame_sync(ctx);
8073 }
8074
8075 if (hw->vdec_cb)
8076 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8077}
8078
8079
8080static void vh264_work(struct work_struct *work)
8081{
8082 struct vdec_h264_hw_s *hw = container_of(work,
8083 struct vdec_h264_hw_s, work);
8084 struct vdec_s *vdec = hw_to_vdec(hw);
8085
8086 vh264_work_implement(hw, vdec, 0);
8087}
8088
8089
8090static void vh264_timeout_work(struct work_struct *work)
8091{
8092 struct vdec_h264_hw_s *hw = container_of(work,
8093 struct vdec_h264_hw_s, timeout_work);
8094 struct vdec_s *vdec = hw_to_vdec(hw);
8095
8096 if (work_pending(&hw->work))
8097 return;
8098
8099 vh264_work_implement(hw, vdec, 1);
8100}
8101
8102static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8103{
8104 bool ret = 0;
8105 struct vdec_h264_hw_s *hw =
8106 (struct vdec_h264_hw_s *)vdec->private;
8107 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8108 CODEC_MM_FLAGS_TVP : 0;
8109
8110 if (!hw->first_sc_checked && hw->mmu_enable) {
8111 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8112 hw->first_sc_checked =1;
8113 dpb_print(DECODE_ID(hw), 0,
8114 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8115 size, (hw->need_cache_size >> PAGE_SHIFT),
8116 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8117 }
8118
8119 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8120 && pre_decode_buf_level != 0) {
8121 u32 rp, wp, level;
8122
8123 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8124 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8125 if (wp < rp)
8126 level = vdec->input.size + wp - rp;
8127 else
8128 level = wp - rp;
8129
8130 if (level < pre_decode_buf_level)
8131 return 0;
8132 }
8133
8134#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8135 if (vdec->master)
8136 return 0;
8137#endif
8138 if (hw->eos)
8139 return 0;
8140
8141 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8142 return 0;
8143
8144 if (disp_vframe_valve_level &&
8145 kfifo_len(&hw->display_q) >=
8146 disp_vframe_valve_level) {
8147 hw->valve_count--;
8148 if (hw->valve_count <= 0)
8149 hw->valve_count = 2;
8150 else
8151 return 0;
8152 }
8153 if (hw->next_again_flag &&
8154 (!vdec_frame_based(vdec))) {
8155 u32 parser_wr_ptr =
8156 READ_PARSER_REG(PARSER_VIDEO_WP);
8157 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8158 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8159 again_threshold) {
8160 int r = vdec_sync_input(vdec);
8161 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8162 "%s buf lelvel:%x\n", __func__, r);
8163 return 0;
8164 }
8165 }
8166
8167 if (h264_debug_flag & 0x20000000) {
8168 /* pr_info("%s, a\n", __func__); */
8169 ret = 1;
8170 } else
8171 ret = is_buffer_available(vdec);
8172
8173#ifdef CONSTRAIN_MAX_BUF_NUM
8174 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8175 if (run_ready_max_vf_only_num > 0 &&
8176 get_vf_ref_only_buf_count(hw) >=
8177 run_ready_max_vf_only_num
8178 )
8179 ret = 0;
8180 if (run_ready_display_q_num > 0 &&
8181 kfifo_len(&hw->display_q) >=
8182 run_ready_display_q_num)
8183 ret = 0;
8184 /*avoid more buffers consumed when
8185 switching resolution*/
8186 if (run_ready_max_buf_num == 0xff &&
8187 get_used_buf_count(hw) >
8188 hw->dpb.mDPB.size)
8189 ret = 0;
8190 else if (run_ready_max_buf_num &&
8191 get_used_buf_count(hw) >=
8192 run_ready_max_buf_num)
8193 ret = 0;
8194
8195 if (hw->is_used_v4l) {
8196 struct aml_vcodec_ctx *ctx =
8197 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8198
8199 if (ctx->param_sets_from_ucode &&
8200 !ctx->v4l_codec_ready &&
8201 hw->v4l_params_parsed)
8202 ret = 0; /*the params has parsed.*/
8203 }
8204 }
8205#endif
8206 if (ret)
8207 not_run_ready[DECODE_ID(hw)] = 0;
8208 else
8209 not_run_ready[DECODE_ID(hw)]++;
8210 if (vdec->parallel_dec == 1) {
8211 if (hw->mmu_enable == 0)
8212 return ret ? (CORE_MASK_VDEC_1) : 0;
8213 else
8214 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8215 } else
8216 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8217}
8218
8219static unsigned char get_data_check_sum
8220 (struct vdec_h264_hw_s *hw, int size)
8221{
8222 int jj;
8223 int sum = 0;
8224 u8 *data = NULL;
8225
8226 if (!hw->chunk->block->is_mapped)
8227 data = codec_mm_vmap(hw->chunk->block->start +
8228 hw->chunk->offset, size);
8229 else
8230 data = ((u8 *)hw->chunk->block->start_virt)
8231 + hw->chunk->offset;
8232
8233 for (jj = 0; jj < size; jj++)
8234 sum += data[jj];
8235
8236 if (!hw->chunk->block->is_mapped)
8237 codec_mm_unmap_phyaddr(data);
8238 return sum;
8239}
8240
8241static void run(struct vdec_s *vdec, unsigned long mask,
8242 void (*callback)(struct vdec_s *, void *), void *arg)
8243{
8244 struct vdec_h264_hw_s *hw =
8245 (struct vdec_h264_hw_s *)vdec->private;
8246 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8247 int size, ret = -1;
8248
8249 run_count[DECODE_ID(hw)]++;
8250 vdec_reset_core(vdec);
8251 if (hw->mmu_enable)
8252 hevc_reset_core(vdec);
8253 hw->vdec_cb_arg = arg;
8254 hw->vdec_cb = callback;
8255
8256 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8257 hw->reset_bufmgr_flag = 1;
8258 dpb_print(DECODE_ID(hw), 0,
8259 "kfifo len:%d invaild, need bufmgr reset\n",
8260 kfifo_len(&hw->display_q));
8261 }
8262
8263 hw->pre_parser_wr_ptr =
8264 READ_PARSER_REG(PARSER_VIDEO_WP);
8265 hw->next_again_flag = 0;
8266
8267 if (hw->reset_bufmgr_flag ||
8268 ((error_proc_policy & 0x40) &&
8269 p_H264_Dpb->buf_alloc_fail)) {
8270 h264_reset_bufmgr(vdec);
8271 hw->reset_bufmgr_flag = 0;
8272 }
8273
8274 if (h264_debug_cmd & 0xf000) {
8275 if (((h264_debug_cmd >> 12) & 0xf)
8276 == (DECODE_ID(hw) + 1)) {
8277 h264_reconfig(hw);
8278 h264_debug_cmd &= (~0xf000);
8279 }
8280 }
8281 /* hw->chunk = vdec_prepare_input(vdec); */
8282#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8283 if (vdec->slave || vdec->master)
8284 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8285#endif
8286 size = vdec_prepare_input(vdec, &hw->chunk);
8287 if ((size < 0) ||
8288 (input_frame_based(vdec) && hw->chunk == NULL)) {
8289 input_empty[DECODE_ID(hw)]++;
8290 hw->dec_result = DEC_RESULT_AGAIN;
8291
8292 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8293 "vdec_prepare_input: Insufficient data\n");
8294
8295 vdec_schedule_work(&hw->work);
8296 return;
8297 }
8298 input_empty[DECODE_ID(hw)] = 0;
8299
8300 hw->dec_result = DEC_RESULT_NONE;
8301 hw->get_data_count = 0;
8302#if 0
8303 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8304 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8305 READ_VREG(VLD_MEM_VIFIFO_RP),
8306 READ_VREG(VLD_MEM_VIFIFO_WP));
8307#endif
8308
8309 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8310 u8 *data = NULL;
8311
8312 if (!hw->chunk->block->is_mapped)
8313 data = codec_mm_vmap(hw->chunk->block->start +
8314 hw->chunk->offset, size);
8315 else
8316 data = ((u8 *)hw->chunk->block->start_virt)
8317 + hw->chunk->offset;
8318
8319 if (dpb_is_debug(DECODE_ID(hw),
8320 PRINT_FLAG_VDEC_STATUS)
8321 ) {
8322 dpb_print(DECODE_ID(hw), 0,
8323 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8324 __func__, size, get_data_check_sum(hw, size),
8325 data[0], data[1], data[2], data[3],
8326 data[4], data[5], data[size - 4],
8327 data[size - 3], data[size - 2],
8328 data[size - 1]);
8329 }
8330 if (dpb_is_debug(DECODE_ID(hw),
8331 PRINT_FRAMEBASE_DATA)
8332 ) {
8333 int jj;
8334
8335 for (jj = 0; jj < size; jj++) {
8336 if ((jj & 0xf) == 0)
8337 dpb_print(DECODE_ID(hw),
8338 PRINT_FRAMEBASE_DATA,
8339 "%06x:", jj);
8340 dpb_print_cont(DECODE_ID(hw),
8341 PRINT_FRAMEBASE_DATA,
8342 "%02x ", data[jj]);
8343 if (((jj + 1) & 0xf) == 0)
8344 dpb_print_cont(DECODE_ID(hw),
8345 PRINT_FRAMEBASE_DATA,
8346 "\n");
8347 }
8348 }
8349
8350 if (!hw->chunk->block->is_mapped)
8351 codec_mm_unmap_phyaddr(data);
8352 } else
8353 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8354 "%s: %x %x %x %x %x size 0x%x\n",
8355 __func__,
8356 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8357 READ_VREG(VLD_MEM_VIFIFO_WP),
8358 READ_VREG(VLD_MEM_VIFIFO_RP),
8359 READ_PARSER_REG(PARSER_VIDEO_RP),
8360 READ_PARSER_REG(PARSER_VIDEO_WP),
8361 size);
8362
8363 start_process_time(hw);
8364 if (vdec->mc_loaded) {
8365 /*firmware have load before,
8366 and not changes to another.
8367 ignore reload.
8368 */
8369 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8370 } else {
8371
8372 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8373 if (ret < 0) {
8374 amvdec_enable_flag = false;
8375 amvdec_disable();
8376
8377 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8378 "MH264 the %s fw loading failed, err: %x\n",
8379 tee_enabled() ? "TEE" : "local", ret);
8380 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8381 vdec_schedule_work(&hw->work);
8382 return;
8383 }
8384 vdec->mc_type = VFORMAT_H264;
8385 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8386 if (hw->mmu_enable) {
8387 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8388 hw->fw_mmu->data);
8389 if (ret < 0) {
8390 amvdec_enable_flag = false;
8391 amhevc_disable();
8392
8393 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8394 "MH264_MMU the %s fw loading failed, err: %x\n",
8395 tee_enabled() ? "TEE" : "local", ret);
8396 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8397 vdec_schedule_work(&hw->work);
8398 return;
8399 }
8400 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8401 }
8402 vdec->mc_loaded = 1;
8403 }
8404 vmh264_reset_udr_mgr(hw);
8405
8406 if (vh264_hw_ctx_restore(hw) < 0) {
8407 vdec_schedule_work(&hw->work);
8408 return;
8409 }
8410 if (input_frame_based(vdec)) {
8411 int decode_size = 0;
8412
8413 decode_size = hw->chunk->size +
8414 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8415 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8416 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8417 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8418 } else {
8419 if (size <= 0)
8420 size = 0x7fffffff; /*error happen*/
8421 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8422 WRITE_VREG(H264_DECODE_SIZE, size);
8423 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8424 }
8425 config_aux_buf(hw);
8426 config_decode_mode(hw);
8427 vdec_enable_input(vdec);
8428 WRITE_VREG(NAL_SEARCH_CTL, 0);
8429 hw->sei_data_len = 0;
8430 if (enable_itu_t35)
8431 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8432 if (!hw->init_flag) {
8433 if (hw->mmu_enable)
8434 WRITE_VREG(NAL_SEARCH_CTL,
8435 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8436 else
8437 WRITE_VREG(NAL_SEARCH_CTL,
8438 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8439 }
8440 if (udebug_flag)
8441 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8442 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8443
8444 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8445
8446 if (hw->mmu_enable)
8447 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8448 else
8449 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8450 }
8451 amvdec_start();
8452 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8453 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8454 amhevc_start();
8455 if (hw->config_bufmgr_done) {
8456 hevc_mcr_sao_global_hw_init(hw,
8457 (hw->mb_width << 4), (hw->mb_height << 4));
8458 hevc_mcr_config_canv2axitbl(hw, 1);
8459 }
8460 }
8461
8462 /* if (hw->init_flag) { */
8463 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8464 /* } */
8465
8466 hw->init_flag = 1;
8467}
8468
8469static void reset(struct vdec_s *vdec)
8470{
8471 struct vdec_h264_hw_s *hw =
8472 (struct vdec_h264_hw_s *)vdec->private;
8473
8474 pr_info("vmh264 reset\n");
8475
8476 cancel_work_sync(&hw->work);
8477 cancel_work_sync(&hw->notify_work);
8478 if (hw->stat & STAT_VDEC_RUN) {
8479 amhevc_stop();
8480 hw->stat &= ~STAT_VDEC_RUN;
8481 }
8482
8483 if (hw->stat & STAT_TIMER_ARM) {
8484 del_timer_sync(&hw->check_timer);
8485 hw->stat &= ~STAT_TIMER_ARM;
8486 }
8487 hw->eos = 0;
8488 hw->decode_pic_count = 0;
8489 hw->dec_result = DEC_RESULT_NONE;
8490 reset_process_time(hw);
8491 h264_reset_bufmgr(vdec);
8492
8493 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8494}
8495
8496static void h264_reconfig(struct vdec_h264_hw_s *hw)
8497{
8498 int i;
8499 unsigned long flags;
8500 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8501 struct vdec_s *vdec = hw_to_vdec(hw);
8502 dpb_print(DECODE_ID(hw), 0,
8503 "%s\n", __func__);
8504 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8505 all buffers are in display queue (used == 2),
8506 or free (used == 0)
8507 */
8508 if (dpb_is_debug(DECODE_ID(hw),
8509 PRINT_FLAG_DUMP_BUFSPEC))
8510 dump_bufspec(hw, "pre h264_reconfig");
8511
8512 flush_dpb(p_H264_Dpb);
8513 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8514
8515 if (hw->collocate_cma_alloc_addr) {
8516 decoder_bmmu_box_free_idx(
8517 hw->bmmu_box,
8518 BMMU_REF_IDX);
8519 hw->collocate_cma_alloc_addr = 0;
8520 hw->dpb.colocated_mv_addr_start = 0;
8521 hw->dpb.colocated_mv_addr_end = 0;
8522 }
8523 spin_lock_irqsave(&hw->bufspec_lock, flags);
8524 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8525 if (vdec->parallel_dec == 1) {
8526 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8527 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8528 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8529 hw->buffer_spec[i].y_canvas_index = -1;
8530 hw->buffer_spec[i].u_canvas_index = -1;
8531 hw->buffer_spec[i].v_canvas_index = -1;
8532#ifdef VDEC_DW
8533 if (IS_VDEC_DW(hw)) {
8534 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8535 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8536 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8537 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8538 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8539 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8540#endif
8541 }
8542 }
8543 /*make sure buffers not put back to bufmgr when
8544 vf_put is called*/
8545 if (hw->buffer_spec[i].used == 2)
8546 hw->buffer_spec[i].used = 3;
8547
8548 /* ready to release "free buffers"
8549 */
8550 if (hw->buffer_spec[i].used == 0)
8551 hw->buffer_spec[i].used = 4;
8552
8553 hw->buffer_spec[i].canvas_pos = -1;
8554 }
8555 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8556 hw->has_i_frame = 0;
8557 hw->config_bufmgr_done = 0;
8558
8559 if (hw->is_used_v4l) {
8560 mutex_lock(&vmh264_mutex);
8561 dealloc_buf_specs(hw, 1);
8562 mutex_unlock(&vmh264_mutex);
8563 }
8564
8565 if (dpb_is_debug(DECODE_ID(hw),
8566 PRINT_FLAG_DUMP_BUFSPEC))
8567 dump_bufspec(hw, "after h264_reconfig");
8568
8569}
8570
8571#ifdef ERROR_HANDLE_TEST
8572static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8573{
8574 int i;
8575 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8576 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8577 "%s\n", __func__);
8578 remove_dpb_pictures(p_H264_Dpb);
8579 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8580 /*make sure buffers not put back to bufmgr when
8581 vf_put is called*/
8582 if (hw->buffer_spec[i].used == 2)
8583 hw->buffer_spec[i].used = 5;
8584 }
8585
8586}
8587#endif
8588
8589static void h264_reset_bufmgr(struct vdec_s *vdec)
8590{
8591 int i;
8592 ulong timeout;
8593 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8594#if 0
8595 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8596 int actual_dpb_size, max_reference_size;
8597 int reorder_pic_num;
8598 unsigned int colocated_buf_size;
8599 unsigned int colocated_mv_addr_start;
8600 unsigned int colocated_mv_addr_end;
8601 dpb_print(DECODE_ID(hw), 0,
8602 "%s\n", __func__);
8603
8604 for (i = 0; i < VF_POOL_SIZE; i++)
8605 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8606
8607 actual_dpb_size = p_H264_Dpb->mDPB.size;
8608 max_reference_size = p_H264_Dpb->max_reference_size;
8609 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8610
8611 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8612 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8613 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8614
8615 hw->cur_pool++;
8616 if (hw->cur_pool >= VF_POOL_NUM)
8617 hw->cur_pool = 0;
8618
8619 INIT_KFIFO(hw->display_q);
8620 INIT_KFIFO(hw->newframe_q);
8621
8622 for (i = 0; i < VF_POOL_SIZE; i++) {
8623 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8624 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8625 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8626 kfifo_put(&hw->newframe_q, vf);
8627 }
8628
8629 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8630 hw->buffer_spec[i].used = 0;
8631
8632 dpb_init_global(&hw->dpb,
8633 DECODE_ID(hw), 0, 0);
8634 p_H264_Dpb->mDPB.size = actual_dpb_size;
8635 p_H264_Dpb->max_reference_size = max_reference_size;
8636 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8637
8638 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8639 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8640 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8641
8642 p_H264_Dpb->fast_output_enable = fast_output_enable;
8643 hw->has_i_frame = 0;
8644#else
8645 dpb_print(DECODE_ID(hw), 0,
8646 "%s frame count %d to skip %d\n\n",
8647 __func__, hw->decode_pic_count+1,
8648 hw->skip_frame_count);
8649
8650 timeout = jiffies + HZ;
8651 while (kfifo_len(&hw->display_q) > 0) {
8652 if (time_after(jiffies, timeout))
8653 break;
8654 schedule();
8655 }
8656
8657 for (i = 0; i < VF_POOL_SIZE; i++)
8658 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8659
8660 hw->cur_pool++;
8661 if (hw->cur_pool >= VF_POOL_NUM)
8662 hw->cur_pool = 0;
8663
8664 for (i = 0; i < VF_POOL_SIZE; i++)
8665 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8666
8667
8668 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8669
8670 buf_spec_init(hw);
8671
8672 vh264_local_init(hw);
8673 /*hw->decode_pic_count = 0;
8674 hw->seq_info2 = 0;*/
8675
8676 if (hw->is_used_v4l) {
8677 mutex_lock(&vmh264_mutex);
8678 /* detach relationship with v4l buffs.*/
8679 dealloc_buf_specs(hw, 1);
8680 mutex_unlock(&vmh264_mutex);
8681 }
8682
8683 if (vh264_set_params(hw,
8684 hw->cfg_param1,
8685 hw->cfg_param2,
8686 hw->cfg_param3,
8687 hw->cfg_param4) < 0)
8688 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8689
8690 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8691 if (first_i_policy & 0x01)
8692 hw->first_i_policy = (3 << 8) | first_i_policy;
8693
8694 hw->init_flag = 1;
8695 hw->reset_bufmgr_count++;
8696#endif
8697}
8698
8699int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8700{
8701 int ret = -1;
8702 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8703 CODEC_MM_FLAGS_TVP : 0;
8704 int buf_size = 64;
8705
8706 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8707 tvp_flag, hw->mmu_enable);
8708 hw->need_cache_size = buf_size * SZ_1M;
8709 hw->sc_start_time = get_jiffies_64();
8710 if (hw->mmu_enable && !hw->mmu_box) {
8711 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8712 hw->id,
8713 MMU_MAX_BUFFERS,
8714 hw->need_cache_size,
8715 tvp_flag);
8716 if (!hw->mmu_box) {
8717 pr_err("h264 4k alloc mmu box failed!!\n");
8718 return -1;
8719 }
8720 ret = 0;
8721 }
8722 if (!hw->bmmu_box) {
8723 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8724 DRIVER_NAME,
8725 hw->id,
8726 BMMU_MAX_BUFFERS,
8727 4 + PAGE_SHIFT,
8728 CODEC_MM_FLAGS_CMA_CLEAR |
8729 CODEC_MM_FLAGS_FOR_VDECODER |
8730 tvp_flag);
8731 if (hw->bmmu_box)
8732 ret = 0;
8733 }
8734 return ret;
8735}
8736int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8737{
8738 if (hw->mmu_box) {
8739 decoder_mmu_box_free(hw->mmu_box);
8740 hw->mmu_box = NULL;
8741 }
8742 if (hw->bmmu_box) {
8743 decoder_bmmu_box_free(hw->bmmu_box);
8744 hw->bmmu_box = NULL;
8745 }
8746 return 0;
8747}
8748
8749static int ammvdec_h264_probe(struct platform_device *pdev)
8750{
8751 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8752 struct vdec_h264_hw_s *hw = NULL;
8753 char *tmpbuf;
8754 int config_val;
8755
8756 if (pdata == NULL) {
8757 pr_info("\nammvdec_h264 memory resource undefined.\n");
8758 return -EFAULT;
8759 }
8760
8761 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8762 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8763 if (hw == NULL) {
8764 pr_info("\nammvdec_h264 device data allocation failed\n");
8765 return -ENOMEM;
8766 }
8767 hw->id = pdev->id;
8768 hw->platform_dev = pdev;
8769
8770 /* the ctx from v4l2 driver. */
8771 hw->v4l2_ctx = pdata->private;
8772
8773 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8774 hw->canvas_mode = pdata->canvas_mode;
8775 else
8776 hw->canvas_mode = mem_map_mode;
8777
8778 platform_set_drvdata(pdev, pdata);
8779
8780 hw->mmu_enable = 0;
8781 hw->first_head_check_flag = 0;
8782 hw->new_iframe_flag = 0;
8783 hw->ref_err_flush_dpb_flag = 0;
8784
8785 if (pdata->sys_info)
8786 hw->vh264_amstream_dec_info = *pdata->sys_info;
8787
8788 hw->is_used_v4l = (((unsigned long)
8789 hw->vh264_amstream_dec_info.param & 0x80) >> 7);
8790 if (hw->is_used_v4l) {
8791 hw->mmu_enable = (((unsigned long)
8792 hw->vh264_amstream_dec_info.param & 0x100) >> 8);
8793 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
8794 "%s v4: enable mmu %d.\n",
8795 __func__, hw->mmu_enable);
8796 }
8797
8798 if (force_enable_mmu && pdata->sys_info &&
8799 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8800 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8801 (pdata->sys_info->height * pdata->sys_info->width
8802 > 1920 * 1088))
8803 hw->mmu_enable = 1;
8804
8805 if (hw->mmu_enable &&
8806 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8807 hw->mmu_enable = 0;
8808 pr_info("ionvideo needs disable mmu, path= %d \n",
8809 pdata->frame_base_video_path);
8810 }
8811
8812 if (ammvdec_h264_mmu_init(hw)) {
8813 h264_free_hw_stru(&pdev->dev, (void *)hw);
8814 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8815 return -ENOMEM;
8816 }
8817
8818 if (pdata->config_len) {
8819 /*use ptr config for doubel_write_mode, etc*/
8820 if (get_config_int(pdata->config,
8821 "mh264_double_write_mode", &config_val) == 0)
8822 hw->double_write_mode = config_val;
8823 else
8824 hw->double_write_mode = double_write_mode;
8825 } else
8826 hw->double_write_mode = double_write_mode;
8827
8828 if (hw->mmu_enable)
8829 hw->double_write_mode &= 0xffff;
8830
8831 if (pdata->parallel_dec == 1) {
8832 int i;
8833 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8834 hw->buffer_spec[i].y_canvas_index = -1;
8835 hw->buffer_spec[i].u_canvas_index = -1;
8836 hw->buffer_spec[i].v_canvas_index = -1;
8837#ifdef VDEC_DW
8838 if (IS_VDEC_DW(hw)) {
8839 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8840 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8841 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8842 }
8843#endif
8844 }
8845 }
8846
8847 dpb_print(DECODE_ID(hw), 0,
8848 "%s mmu_enable %d double_write_mode 0x%x\n",
8849 __func__, hw->mmu_enable, hw->double_write_mode);
8850
8851 pdata->private = hw;
8852 pdata->dec_status = dec_status;
8853 pdata->set_trickmode = vmh264_set_trickmode;
8854 pdata->run_ready = run_ready;
8855 pdata->run = run;
8856 pdata->reset = reset;
8857 pdata->irq_handler = vh264_isr;
8858 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8859 pdata->dump_state = vmh264_dump_state;
8860
8861#ifdef MH264_USERDATA_ENABLE
8862 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8863 pdata->user_data_read = vmh264_user_data_read;
8864 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8865#else
8866 pdata->wakeup_userdata_poll = NULL;
8867 pdata->user_data_read = NULL;
8868 pdata->reset_userdata_fifo = NULL;
8869#endif
8870 if (pdata->use_vfm_path) {
8871 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8872 VFM_DEC_PROVIDER_NAME);
8873 hw->frameinfo_enable = 1;
8874 }
8875#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8876 else if (vdec_dual(pdata)) {
8877 if (dv_toggle_prov_name) /*debug purpose*/
8878 snprintf(pdata->vf_provider_name,
8879 VDEC_PROVIDER_NAME_SIZE,
8880 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8881 VFM_DEC_DVEL_PROVIDER_NAME);
8882 else
8883 snprintf(pdata->vf_provider_name,
8884 VDEC_PROVIDER_NAME_SIZE,
8885 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8886 VFM_DEC_DVBL_PROVIDER_NAME);
8887 }
8888#endif
8889 else
8890 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8891 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8892
8893 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8894 &vf_provider_ops, pdata);
8895
8896 platform_set_drvdata(pdev, pdata);
8897
8898 buf_spec_init(hw);
8899
8900 hw->platform_dev = pdev;
8901
8902#ifdef DUMP_USERDATA_RECORD
8903 vmh264_init_userdata_dump();
8904 vmh264_reset_user_data_buf();
8905#endif
8906 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8907 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8908 h264_free_hw_stru(&pdev->dev, (void *)hw);
8909 pdata->dec_status = NULL;
8910 return -ENOMEM;
8911 }
8912
8913 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8914 DCAC_READ_MARGIN;
8915 if (hw->mmu_enable) {
8916 u32 extif_size = EXTIF_BUF_SIZE;
8917 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8918 extif_size <<= 1;
8919 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8920 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8921 h264_free_hw_stru(&pdev->dev, (void *)hw);
8922 pdata->dec_status = NULL;
8923 return -ENOMEM;
8924 }
8925 }
8926 if (!vdec_secure(pdata)) {
8927#if 1
8928 /*init internal buf*/
8929 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8930 if (tmpbuf) {
8931 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8932 codec_mm_dma_flush(tmpbuf,
8933 V_BUF_ADDR_OFFSET,
8934 DMA_TO_DEVICE);
8935 } else {
8936 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8937 V_BUF_ADDR_OFFSET);
8938 if (tmpbuf) {
8939 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8940 codec_mm_dma_flush(tmpbuf,
8941 V_BUF_ADDR_OFFSET,
8942 DMA_TO_DEVICE);
8943 codec_mm_unmap_phyaddr(tmpbuf);
8944 }
8945 }
8946#else
8947 /*init sps/pps internal buf 64k*/
8948 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8949 + (mem_sps_base - DEF_BUF_START_ADDR));
8950 memset(tmpbuf, 0, 0x10000);
8951 dma_sync_single_for_device(amports_get_dma_device(),
8952 hw->cma_alloc_addr +
8953 (mem_sps_base - DEF_BUF_START_ADDR),
8954 0x10000, DMA_TO_DEVICE);
8955#endif
8956 }
8957 /**/
8958
8959#if 0
8960 if (NULL == hw->sei_data_buffer) {
8961 hw->sei_data_buffer =
8962 dma_alloc_coherent(amports_get_dma_device(),
8963 USER_DATA_SIZE,
8964 &hw->sei_data_buffer_phys, GFP_KERNEL);
8965 if (!hw->sei_data_buffer) {
8966 pr_info("%s: Can not allocate sei_data_buffer\n",
8967 __func__);
8968 ammvdec_h264_mmu_release(hw);
8969 h264_free_hw_stru(&pdev->dev, (void *)hw);
8970 return -ENOMEM;
8971 }
8972 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
8973 sei_data_buffer, sei_data_buffer_phys,
8974 (u32)sei_data_buffer_remap); */
8975 }
8976#endif
8977 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
8978 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
8979
8980 if (vdec_is_support_4k() ||
8981 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
8982 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8983 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
8984 {
8985 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
8986 }else
8987 {
8988 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
8989 }
8990
8991 if (vh264_init(hw) < 0) {
8992 pr_info("\nammvdec_h264 init failed.\n");
8993 ammvdec_h264_mmu_release(hw);
8994 h264_free_hw_stru(&pdev->dev, (void *)hw);
8995 pdata->dec_status = NULL;
8996 return -ENODEV;
8997 }
8998#ifdef MH264_USERDATA_ENABLE
8999 vmh264_crate_userdata_manager(hw,
9000 hw->sei_user_data_buffer,
9001 USER_DATA_SIZE);
9002#endif
9003
9004 vdec_set_prepare_level(pdata, start_decode_buf_level);
9005 if (pdata->parallel_dec == 1) {
9006 if (hw->mmu_enable == 0)
9007 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9008 else {
9009 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9010 | CORE_MASK_COMBINE);
9011 }
9012 } else
9013 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9014 | CORE_MASK_COMBINE);
9015
9016 atomic_set(&hw->vh264_active, 1);
9017
9018 return 0;
9019}
9020
9021static int ammvdec_h264_remove(struct platform_device *pdev)
9022{
9023 struct vdec_h264_hw_s *hw =
9024 (struct vdec_h264_hw_s *)
9025 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9026 int i;
9027
9028 struct vdec_s *vdec = hw_to_vdec(hw);
9029
9030 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9031 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9032 dpb_print(DECODE_ID(hw), 0,
9033 "%s force exit %d\n", __func__, __LINE__);
9034 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9035 vdec_schedule_work(&hw->work);
9036 wait_event_interruptible_timeout(hw->wait_q,
9037 (vdec->status == VDEC_STATUS_CONNECTED),
9038 msecs_to_jiffies(1000)); /* wait for work done */
9039 }
9040
9041 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9042 release_aux_data(hw, i);
9043
9044 atomic_set(&hw->vh264_active, 0);
9045
9046 if (hw->stat & STAT_TIMER_ARM) {
9047 del_timer_sync(&hw->check_timer);
9048 hw->stat &= ~STAT_TIMER_ARM;
9049 }
9050
9051 vh264_stop(hw);
9052#ifdef MH264_USERDATA_ENABLE
9053#ifdef DUMP_USERDATA_RECORD
9054 vmh264_dump_userdata();
9055#endif
9056 vmh264_destroy_userdata_manager(hw);
9057#endif
9058 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9059
9060 atomic_set(&hw->vh264_active, 0);
9061 if (vdec->parallel_dec == 1) {
9062 if (hw->mmu_enable == 0)
9063 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9064 else
9065 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9066 CORE_MASK_COMBINE);
9067 } else
9068 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9069
9070 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9071 if (vdec->parallel_dec == 1) {
9072 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9073 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9074 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9075 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9076 if (IS_VDEC_DW(hw)) {
9077 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9078 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9079 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9080 }
9081 }
9082 }
9083
9084 ammvdec_h264_mmu_release(hw);
9085 h264_free_hw_stru(&pdev->dev, (void *)hw);
9086 clk_adj_frame_count = 0;
9087
9088 return 0;
9089}
9090
9091/****************************************/
9092#ifdef CONFIG_PM
9093static int mh264_suspend(struct device *dev)
9094{
9095 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9096 return 0;
9097}
9098
9099static int mh264_resume(struct device *dev)
9100{
9101 amvdec_resume(to_platform_device(dev));
9102 return 0;
9103}
9104
9105static const struct dev_pm_ops mh264_pm_ops = {
9106 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9107};
9108#endif
9109
9110static struct platform_driver ammvdec_h264_driver = {
9111 .probe = ammvdec_h264_probe,
9112 .remove = ammvdec_h264_remove,
9113 .driver = {
9114 .name = DRIVER_NAME,
9115#ifdef CONFIG_PM
9116 .pm = &mh264_pm_ops,
9117#endif
9118 }
9119};
9120
9121static struct codec_profile_t ammvdec_h264_profile = {
9122 .name = "mh264",
9123 .profile = ""
9124};
9125
9126static struct mconfig hm264_configs[] = {
9127 MC_PU32("h264_debug_flag", &h264_debug_flag),
9128 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9129 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9130 MC_PU32("decode_timeout_val", &decode_timeout_val),
9131 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9132 MC_PU32("reference_buf_margin", &reference_buf_margin),
9133 MC_PU32("radr", &radr),
9134 MC_PU32("rval", &rval),
9135 MC_PU32("h264_debug_mask", &h264_debug_mask),
9136 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9137 MC_PI32("force_rate_streambase", &force_rate_streambase),
9138 MC_PI32("dec_control", &dec_control),
9139 MC_PI32("force_rate_framebase", &force_rate_framebase),
9140 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9141 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9142 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9143#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9144 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9145 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9146 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9147#endif
9148 MC_PU32("i_only_flag", &i_only_flag),
9149 MC_PU32("force_rate_streambase", &force_rate_streambase),
9150};
9151static struct mconfig_node hm264_node;
9152
9153
9154static int __init ammvdec_h264_driver_init_module(void)
9155{
9156 pr_info("ammvdec_h264 module init\n");
9157 if (platform_driver_register(&ammvdec_h264_driver)) {
9158 pr_info("failed to register ammvdec_h264 driver\n");
9159 return -ENODEV;
9160 }
9161
9162 if (vdec_is_support_4k()) {
9163 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9164 ammvdec_h264_profile.profile =
9165 "4k, dwrite, compressed";
9166 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9167 ammvdec_h264_profile.profile = "4k";
9168 }
9169 }
9170
9171 vcodec_profile_register(&ammvdec_h264_profile);
9172 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9173 "mh264", hm264_configs, CONFIG_FOR_RW);
9174 return 0;
9175}
9176
9177static void __exit ammvdec_h264_driver_remove_module(void)
9178{
9179 pr_info("ammvdec_h264 module remove.\n");
9180
9181 platform_driver_unregister(&ammvdec_h264_driver);
9182}
9183
9184/****************************************/
9185module_param(h264_debug_flag, uint, 0664);
9186MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9187
9188module_param(start_decode_buf_level, int, 0664);
9189MODULE_PARM_DESC(start_decode_buf_level,
9190 "\n ammvdec_h264 start_decode_buf_level\n");
9191
9192module_param(pre_decode_buf_level, int, 0664);
9193MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9194
9195module_param(fixed_frame_rate_mode, uint, 0664);
9196MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9197
9198module_param(decode_timeout_val, uint, 0664);
9199MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9200
9201module_param(errordata_timeout_val, uint, 0664);
9202MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9203
9204module_param(get_data_timeout_val, uint, 0664);
9205MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9206
9207module_param(frame_max_data_packet, uint, 0664);
9208MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9209
9210module_param(reorder_dpb_size_margin, uint, 0664);
9211MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9212
9213#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9214module_param(reorder_dpb_size_margin_dv, uint, 0664);
9215MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9216 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9217#endif
9218
9219module_param(reference_buf_margin, uint, 0664);
9220MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9221
9222#ifdef CONSTRAIN_MAX_BUF_NUM
9223module_param(run_ready_max_vf_only_num, uint, 0664);
9224MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9225
9226module_param(run_ready_display_q_num, uint, 0664);
9227MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9228
9229module_param(run_ready_max_buf_num, uint, 0664);
9230MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9231#endif
9232
9233module_param(radr, uint, 0664);
9234MODULE_PARM_DESC(radr, "\nradr\n");
9235
9236module_param(rval, uint, 0664);
9237MODULE_PARM_DESC(rval, "\nrval\n");
9238
9239module_param(h264_debug_mask, uint, 0664);
9240MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9241
9242module_param(h264_debug_cmd, uint, 0664);
9243MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9244
9245module_param(force_rate_streambase, int, 0664);
9246MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9247
9248module_param(dec_control, int, 0664);
9249MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9250
9251module_param(force_rate_framebase, int, 0664);
9252MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9253
9254module_param(force_disp_bufspec_num, int, 0664);
9255MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9256
9257module_param(V_BUF_ADDR_OFFSET, int, 0664);
9258MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9259
9260module_param(prefix_aux_buf_size, uint, 0664);
9261MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9262
9263module_param(suffix_aux_buf_size, uint, 0664);
9264MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9265
9266#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9267module_param(dv_toggle_prov_name, uint, 0664);
9268MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9269
9270module_param(dolby_meta_with_el, uint, 0664);
9271MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9272
9273#endif
9274
9275module_param(fast_output_enable, uint, 0664);
9276MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9277
9278module_param(error_proc_policy, uint, 0664);
9279MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9280
9281module_param(error_skip_count, uint, 0664);
9282MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9283
9284module_param(force_sliding_margin, uint, 0664);
9285MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9286
9287module_param(i_only_flag, uint, 0664);
9288MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9289
9290module_param(first_i_policy, uint, 0664);
9291MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9292
9293module_param(frmbase_cont_bitlevel, uint, 0664);
9294MODULE_PARM_DESC(frmbase_cont_bitlevel,
9295 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9296
9297module_param(frmbase_cont_bitlevel2, uint, 0664);
9298MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9299 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9300
9301module_param(udebug_flag, uint, 0664);
9302MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9303
9304module_param(udebug_pause_pos, uint, 0664);
9305MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9306
9307module_param(udebug_pause_val, uint, 0664);
9308MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9309
9310module_param(udebug_pause_decode_idx, uint, 0664);
9311MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9312
9313module_param(max_alloc_buf_count, uint, 0664);
9314MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9315
9316module_param(enable_itu_t35, uint, 0664);
9317MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9318
9319module_param(endian, uint, 0664);
9320MODULE_PARM_DESC(endian, "\nrval\n");
9321
9322module_param(mmu_enable, uint, 0664);
9323MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9324
9325module_param(force_enable_mmu, uint, 0664);
9326MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9327
9328module_param(again_threshold, uint, 0664);
9329MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9330
9331module_param(stream_mode_start_num, uint, 0664);
9332MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9333
9334/*
9335module_param(trigger_task, uint, 0664);
9336MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9337*/
9338module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9339
9340module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9341
9342module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9343
9344module_param_array(run_count, uint,
9345 &max_decode_instance_num, 0664);
9346
9347module_param_array(not_run_ready, uint,
9348 &max_decode_instance_num, 0664);
9349
9350module_param_array(input_empty, uint,
9351 &max_decode_instance_num, 0664);
9352
9353module_param_array(max_get_frame_interval, uint,
9354 &max_decode_instance_num, 0664);
9355
9356module_param_array(step, uint, &max_decode_instance_num, 0664);
9357
9358module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9359
9360module_param(disp_vframe_valve_level, uint, 0664);
9361MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9362
9363module_param(double_write_mode, uint, 0664);
9364MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9365
9366module_param(mem_map_mode, uint, 0664);
9367MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9368
9369module_param(without_display_mode, uint, 0664);
9370MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9371
9372
9373module_init(ammvdec_h264_driver_init_module);
9374module_exit(ammvdec_h264_driver_remove_module);
9375
9376MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9377MODULE_LICENSE("GPL");
9378
generated by cgit at 2024-05-17 07:44:14 (GMT)