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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: c2e0e91ede9cc481a485f2337003e91a216345e5
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64#include <media/v4l2-mem2mem.h>
65
66#undef pr_info
67#define pr_info printk
68#define VDEC_DW
69#define DEBUG_UCODE
70#define MEM_NAME "codec_m264"
71#define MULTI_INSTANCE_FRAMEWORK
72/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
73#include "h264_dpb.h"
74/* #define SEND_PARAM_WITH_REG */
75
76#define DRIVER_NAME "ammvdec_h264"
77#define MODULE_NAME "ammvdec_h264"
78#define DRIVER_HEADER_NAME "ammvdec_h264_header"
79
80#define CHECK_INTERVAL (HZ/100)
81
82#define SEI_DATA_SIZE (8*1024)
83#define SEI_ITU_DATA_SIZE (4*1024)
84
85#define RATE_MEASURE_NUM 8
86#define RATE_CORRECTION_THRESHOLD 5
87#define RATE_2397_FPS 4004 /* 23.97 */
88#define RATE_25_FPS 3840 /* 25 */
89#define RATE_2997_FPS 3203 /* 29.97 */
90#define DUR2PTS(x) ((x)*90/96)
91#define PTS2DUR(x) ((x)*96/90)
92#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
93#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
94
95#define FIX_FRAME_RATE_OFF 0
96#define FIX_FRAME_RATE_ON 1
97#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
98
99#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
100#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
101#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
102#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
103
104#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
105
106#define RATE_MEASURE_NUM 8
107#define RATE_CORRECTION_THRESHOLD 5
108#define RATE_24_FPS 4004 /* 23.97 */
109#define RATE_25_FPS 3840 /* 25 */
110#define DUR2PTS(x) ((x)*90/96)
111#define PTS2DUR(x) ((x)*96/90)
112#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
113#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
114
115#define H264_DEV_NUM 9
116
117#define CONSTRAIN_MAX_BUF_NUM
118
119#define H264_MMU
120#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
121#define INVALID_IDX -1 /* Invalid buffer index.*/
122
123static int mmu_enable;
124/*mmu do not support mbaff*/
125static int force_enable_mmu = 0;
126unsigned int h264_debug_flag; /* 0xa0000000; */
127unsigned int h264_debug_mask = 0xff;
128 /*
129 *h264_debug_cmd:
130 * 0x1xx, force decoder id of xx to be disconnected
131 */
132unsigned int h264_debug_cmd;
133
134static unsigned int dec_control =
135 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
136 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
137
138static unsigned int force_rate_streambase;
139static unsigned int force_rate_framebase;
140static unsigned int force_disp_bufspec_num;
141static unsigned int fixed_frame_rate_mode;
142static unsigned int error_recovery_mode_in;
143static int start_decode_buf_level = 0x4000;
144static int pre_decode_buf_level = 0x1000;
145static int stream_mode_start_num = 4;
146
147#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
148/*to make reorder size difference of bl and el not too big*/
149static unsigned int reorder_dpb_size_margin_dv = 16;
150#endif
151static unsigned int reorder_dpb_size_margin = 6;
152static unsigned int reference_buf_margin = 4;
153
154#ifdef CONSTRAIN_MAX_BUF_NUM
155static u32 run_ready_max_vf_only_num;
156static u32 run_ready_display_q_num;
157 /*0: not check
158 0xff: mDPB.size
159 */
160static u32 run_ready_max_buf_num = 0xff;
161#endif
162
163static u32 run_ready_min_buf_num = 2;
164
165#define VDEC_ASSIST_CANVAS_BLK32 0x5
166
167
168static unsigned int max_alloc_buf_count;
169static unsigned int decode_timeout_val = 100;
170static unsigned int errordata_timeout_val = 50;
171static unsigned int get_data_timeout_val = 2000;
172#if 1
173/* H264_DATA_REQUEST does not work, disable it,
174decode has error for data in none continuous address
175*/
176static unsigned int frame_max_data_packet;
177#else
178static unsigned int frame_max_data_packet = 8;
179#endif
180static unsigned int radr;
181static unsigned int rval;
182static u32 endian = 0xff0;
183
184/*
185 udebug_flag:
186 bit 0, enable ucode print
187 bit 1, enable ucode detail print
188 bit 3, disable ucode watchdog
189 bit [31:16] not 0, pos to dump lmem
190 bit 2, pop bits to lmem
191 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
192*/
193static u32 udebug_flag;
194/*
195 when udebug_flag[1:0] is not 0
196 udebug_pause_pos not 0,
197 pause position
198*/
199static u32 udebug_pause_pos;
200/*
201 when udebug_flag[1:0] is not 0
202 and udebug_pause_pos is not 0,
203 pause only when DEBUG_REG2 is equal to this val
204*/
205static u32 udebug_pause_val;
206
207static u32 udebug_pause_decode_idx;
208
209static unsigned int disp_vframe_valve_level;
210
211static unsigned int max_decode_instance_num = H264_DEV_NUM;
212static unsigned int decode_frame_count[H264_DEV_NUM];
213static unsigned int display_frame_count[H264_DEV_NUM];
214static unsigned int max_process_time[H264_DEV_NUM];
215static unsigned int max_get_frame_interval[H264_DEV_NUM];
216static unsigned int run_count[H264_DEV_NUM];
217static unsigned int input_empty[H264_DEV_NUM];
218static unsigned int not_run_ready[H264_DEV_NUM];
219static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
220{1, 1, 1, 1, 1, 1, 1, 1, 1};
221
222#define VDEC_CLOCK_ADJUST_FRAME 30
223static unsigned int clk_adj_frame_count;
224
225/*
226 *bit[3:0]: 0, run ; 1, pause; 3, step
227 *bit[4]: 1, schedule run
228 */
229static unsigned int step[H264_DEV_NUM];
230
231#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
232static u32 prefix_aux_buf_size = (16 * 1024);
233static u32 suffix_aux_buf_size;
234
235#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
236static u32 dv_toggle_prov_name;
237
238static u32 dolby_meta_with_el;
239#endif
240
241/*
242 bit[8]
243 0: use sys_info[bit 3]
244 not 0:use i_only_flag[7:0]
245 bit[7:0]:
246 bit 0, 1: only display I picture;
247 bit 1, 1: only decode I picture;
248*/
249static unsigned int i_only_flag;
250
251/*
252 error_proc_policy:
253 bit[0] send_error_frame_flag;
254 (valid when bit[31] is 1, otherwise use sysinfo)
255 bit[1] do not decode if config_decode_buf() fail
256 bit[2] force release buf if in deadlock
257 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
258 bit[4] check inactive of receiver
259 bit[5] reset buffmgr if in deadlock
260 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
261 bit[7] reset buffmgr if dpb error
262
263 bit[8] check total mbx/mby of decoded frame
264 bit[9] check ERROR_STATUS_REG
265 bit[10] check reference list
266 bit[11] mark error if dpb error
267 bit[12] i_only when error happen
268 bit[13] 0: mark error according to last pic, 1: ignore mark error
269 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
270*/
271static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
272
273
274/*
275 error_skip_count:
276 bit[11:0] error skip frame count
277 bit[15:12] error skip i picture count
278*/
279static unsigned int error_skip_count = (0x2 << 12) | 0x40;
280
281static unsigned int force_sliding_margin;
282/*
283 bit[1:0]:
284 0, start playing from any frame
285 1, start playing from I frame
286 bit[15:8]: the count of skip frames after first I
287 2, start playing from second I frame (decode from the first I)
288 bit[15:8]: the max count of skip frames after first I
289 3, start playing from IDR
290*/
291static unsigned int first_i_policy = 1;
292
293/*
294 fast_output_enable:
295 bit [0], output frame if there is IDR in list
296 bit [1], output frame if the current poc is 1 big than the previous poc
297 bit [2], if even poc only, output frame ifthe cuurent poc
298 is 2 big than the previous poc
299 bit [3], ip only
300*/
301static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
302
303static unsigned int enable_itu_t35 = 1;
304
305static unsigned int frmbase_cont_bitlevel = 0x40;
306
307static unsigned int frmbase_cont_bitlevel2 = 0x1;
308
309
310#define MH264_USERDATA_ENABLE
311
312/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
313/* hevc->double_write_mode:
314 0, no double write
315 1, 1:1 ratio
316 2, (1/4):(1/4) ratio
317 3, (1/4):(1/4) ratio, with both compressed frame included
318 4, (1/2):(1/2) ratio
319 0x10, double write only
320 0x10000: vdec dw horizotal 1/2
321 0x20000: vdec dw horizotal/vertical 1/2
322*/
323static u32 double_write_mode;
324static u32 without_display_mode;
325#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
326
327static void vmh264_dump_state(struct vdec_s *vdec);
328
329#define is_in_parsing_state(status) \
330 ((status == H264_ACTION_SEARCH_HEAD) || \
331 ((status & 0xf0) == 0x80))
332
333#define is_interlace(frame) \
334 (frame->frame &&\
335 frame->top_field &&\
336 frame->bottom_field &&\
337 (!frame->frame->coded_frame))
338static inline bool close_to(int a, int b, int m)
339{
340 return (abs(a - b) < m) ? true : false;
341}
342
343#if 0
344#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
345#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
346#else
347#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
348#define h264_free_hw_stru(dev, hw) vfree(hw)
349#endif
350
351/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
352#define NV21
353/* #endif */
354
355/* 12M for L41 */
356#define MAX_DPB_BUFF_SIZE (12*1024*1024)
357#define DEFAULT_MEM_SIZE (32*1024*1024)
358#define AVIL_DPB_BUFF_SIZE 0x01ec2000
359
360#define DEF_BUF_START_ADDR 0x01000000
361#define mem_sps_base 0x011c3c00
362#define mem_pps_base 0x011cbc00
363/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
364u32 V_BUF_ADDR_OFFSET = 0x200000;
365#define DCAC_READ_MARGIN (64 * 1024)
366
367
368#define EXTEND_SAR 0xff
369#define BUFSPEC_POOL_SIZE 64
370#define VF_POOL_SIZE 64
371#define VF_POOL_NUM 2
372#define MAX_VF_BUF_NUM 27
373#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
374#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
375#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
376#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
377#define EXTIF_BUF_SIZE (0x10000 * 2)
378
379#define HEADER_BUFFER_IDX(n) (n)
380#define VF_BUFFER_IDX(n) (n)
381
382
383#define PUT_INTERVAL (HZ/100)
384#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
385
386#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
387#define SWITCHING_STATE_OFF 0
388#define SWITCHING_STATE_ON_CMD3 1
389#define SWITCHING_STATE_ON_CMD1 2
390
391
392
393#define INCPTR(p) ptr_atomic_wrap_inc(&p)
394
395#define SLICE_TYPE_I 2
396#define SLICE_TYPE_P 5
397#define SLICE_TYPE_B 6
398
399struct buffer_spec_s {
400 /*
401 used:
402 -1, none allocated
403 0, allocated, free
404 1, used by dpb
405 2, in disp queue;
406 3, in disp queue, isolated,
407 do not use for dpb when vf_put;
408 4, to release
409 5, in disp queue, isolated (but not to release)
410 do not use for dpb when vf_put;
411 */
412 unsigned int used;
413 unsigned int info0;
414 unsigned int info1;
415 unsigned int info2;
416 unsigned int y_addr;
417 unsigned int u_addr;
418 unsigned int v_addr;
419
420 int y_canvas_index;
421 int u_canvas_index;
422 int v_canvas_index;
423
424#ifdef VDEC_DW
425 unsigned int vdec_dw_y_addr;
426 unsigned int vdec_dw_u_addr;
427 unsigned int vdec_dw_v_addr;
428
429 int vdec_dw_y_canvas_index;
430 int vdec_dw_u_canvas_index;
431 int vdec_dw_v_canvas_index;
432#ifdef NV21
433 struct canvas_config_s vdec_dw_canvas_config[2];
434#else
435 struct canvas_config_s vdec_dw_canvas_config[3];
436#endif
437#endif
438
439#ifdef NV21
440 struct canvas_config_s canvas_config[2];
441#else
442 struct canvas_config_s canvas_config[3];
443#endif
444 unsigned long cma_alloc_addr;
445 unsigned int buf_adr;
446#ifdef H264_MMU
447 unsigned long alloc_header_addr;
448#endif
449 char *aux_data_buf;
450 int aux_data_size;
451#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
452 unsigned char dv_enhance_exist;
453#endif
454 int canvas_pos;
455 int vf_ref;
456 /*unsigned int comp_body_size;*/
457 unsigned int dw_y_adr;
458 unsigned int dw_u_v_adr;
459};
460
461#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
462#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
463#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
464
465
466#define vdec_dw_spec2canvas(x) \
467 (((x)->vdec_dw_v_canvas_index << 16) | \
468 ((x)->vdec_dw_u_canvas_index << 8) | \
469 ((x)->vdec_dw_y_canvas_index << 0))
470
471
472#define spec2canvas(x) \
473 (((x)->v_canvas_index << 16) | \
474 ((x)->u_canvas_index << 8) | \
475 ((x)->y_canvas_index << 0))
476
477#define FRAME_INDEX(vf_index) (vf_index & 0xff)
478#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
479#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
480
481static struct vframe_s *vh264_vf_peek(void *);
482static struct vframe_s *vh264_vf_get(void *);
483static void vh264_vf_put(struct vframe_s *, void *);
484static int vh264_vf_states(struct vframe_states *states, void *);
485static int vh264_event_cb(int type, void *data, void *private_data);
486static void vh264_work(struct work_struct *work);
487static void vh264_timeout_work(struct work_struct *work);
488static void vh264_notify_work(struct work_struct *work);
489#ifdef MH264_USERDATA_ENABLE
490static void user_data_ready_notify_work(struct work_struct *work);
491static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
492#endif
493
494static const char vh264_dec_id[] = "vh264-dev";
495
496#define PROVIDER_NAME "vdec.h264"
497
498static const struct vframe_operations_s vf_provider_ops = {
499 .peek = vh264_vf_peek,
500 .get = vh264_vf_get,
501 .put = vh264_vf_put,
502 .event_cb = vh264_event_cb,
503 .vf_states = vh264_vf_states,
504};
505
506#define DEC_RESULT_NONE 0
507#define DEC_RESULT_DONE 1
508#define DEC_RESULT_AGAIN 2
509#define DEC_RESULT_CONFIG_PARAM 3
510#define DEC_RESULT_GET_DATA 4
511#define DEC_RESULT_GET_DATA_RETRY 5
512#define DEC_RESULT_ERROR 6
513#define DEC_RESULT_EOS 7
514#define DEC_RESULT_FORCE_EXIT 8
515
516/*
517 *static const char *dec_result_str[] = {
518 * "DEC_RESULT_NONE ",
519 * "DEC_RESULT_DONE ",
520 * "DEC_RESULT_AGAIN ",
521 * "DEC_RESULT_CONFIG_PARAM",
522 * "DEC_RESULT_GET_DATA ",
523 * "DEC_RESULT_GET_DA_RETRY",
524 * "DEC_RESULT_ERROR ",
525 *};
526 */
527
528#define UCODE_IP_ONLY 2
529#define UCODE_IP_ONLY_PARAM 1
530
531#define MC_OFFSET_HEADER 0x0000
532#define MC_OFFSET_DATA 0x1000
533#define MC_OFFSET_MMCO 0x2000
534#define MC_OFFSET_LIST 0x3000
535#define MC_OFFSET_SLICE 0x4000
536#define MC_OFFSET_MAIN 0x5000
537
538#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
539#define MC_SWAP_SIZE (4*SZ_1K)
540#define MODE_ERROR 0
541#define MODE_FULL 1
542
543#define DFS_HIGH_THEASHOLD 3
544
545#define INIT_FLAG_REG AV_SCRATCH_2
546#define HEAD_PADING_REG AV_SCRATCH_3
547#define UCODE_WATCHDOG_REG AV_SCRATCH_7
548#define LMEM_DUMP_ADR AV_SCRATCH_L
549#define DEBUG_REG1 AV_SCRATCH_M
550#define DEBUG_REG2 AV_SCRATCH_N
551#define FRAME_COUNTER_REG AV_SCRATCH_I
552#define RPM_CMD_REG AV_SCRATCH_A
553#define H264_DECODE_SIZE AV_SCRATCH_E
554#define H264_DECODE_MODE AV_SCRATCH_4
555#define H264_DECODE_SEQINFO AV_SCRATCH_5
556#define H264_AUX_ADR AV_SCRATCH_C
557#define H264_AUX_DATA_SIZE AV_SCRATCH_H
558
559#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
560#define DPB_STATUS_REG AV_SCRATCH_J
561#define ERROR_STATUS_REG AV_SCRATCH_9
562 /*
563 NAL_SEARCH_CTL: bit 0, enable itu_t35
564 NAL_SEARCH_CTL: bit 1, enable mmu
565 */
566#define NAL_SEARCH_CTL AV_SCRATCH_9
567#define MBY_MBX MB_MOTION_MODE /*0xc07*/
568
569#define DECODE_MODE_SINGLE 0x0
570#define DECODE_MODE_MULTI_FRAMEBASE 0x1
571#define DECODE_MODE_MULTI_STREAMBASE 0x2
572#define DECODE_MODE_MULTI_DVBAL 0x3
573#define DECODE_MODE_MULTI_DVENL 0x4
574static DEFINE_MUTEX(vmh264_mutex);
575
576
577
578#ifdef MH264_USERDATA_ENABLE
579
580struct mh264_userdata_record_t {
581 struct userdata_meta_info_t meta_info;
582 u32 rec_start;
583 u32 rec_len;
584};
585
586struct mh264_ud_record_wait_node_t {
587 struct list_head list;
588 struct mh264_userdata_record_t ud_record;
589};
590#define USERDATA_FIFO_NUM 256
591#define MAX_FREE_USERDATA_NODES 5
592
593struct mh264_userdata_info_t {
594 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
595 u8 *data_buf;
596 u8 *data_buf_end;
597 u32 buf_len;
598 u32 read_index;
599 u32 write_index;
600 u32 last_wp;
601};
602
603
604#endif
605
606struct vdec_h264_hw_s {
607 spinlock_t lock;
608 spinlock_t bufspec_lock;
609 int id;
610 struct platform_device *platform_dev;
611 unsigned long cma_alloc_addr;
612 /* struct page *collocate_cma_alloc_pages; */
613 unsigned long collocate_cma_alloc_addr;
614
615 u32 prefix_aux_size;
616 u32 suffix_aux_size;
617 void *aux_addr;
618 dma_addr_t aux_phy_addr;
619
620 /* buffer for store all sei data */
621 void *sei_data_buf;
622 u32 sei_data_len;
623
624 /* buffer for storing one itu35 recored */
625 void *sei_itu_data_buf;
626 u32 sei_itu_data_len;
627
628 /* recycle buffer for user data storing all itu35 records */
629 void *sei_user_data_buffer;
630 u32 sei_user_data_wp;
631#ifdef MH264_USERDATA_ENABLE
632 struct work_struct user_data_ready_work;
633#endif
634 struct StorablePicture *last_dec_picture;
635
636 ulong lmem_addr;
637 dma_addr_t lmem_addr_remap;
638
639 void *bmmu_box;
640#ifdef H264_MMU
641 void *mmu_box;
642 void *frame_mmu_map_addr;
643 dma_addr_t frame_mmu_map_phy_addr;
644 u32 hevc_cur_buf_idx;
645 u32 losless_comp_body_size;
646 u32 losless_comp_body_size_sao;
647 u32 losless_comp_header_size;
648 u32 mc_buffer_size_u_v;
649 u32 mc_buffer_size_u_v_h;
650 u32 is_idr_frame;
651 u32 is_new_pic;
652 u32 frame_done;
653 u32 frame_busy;
654 unsigned long extif_addr;
655 int double_write_mode;
656 int mmu_enable;
657#endif
658
659 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
660 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
661
662 int cur_pool;
663 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
664 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
665 struct vframe_s switching_fense_vf;
666 struct h264_dpb_stru dpb;
667 u8 init_flag;
668 u8 first_sc_checked;
669 u8 has_i_frame;
670 u8 config_bufmgr_done;
671 u32 max_reference_size;
672 u32 decode_pic_count;
673 u32 reflist_error_count;
674 int start_search_pos;
675 u32 reg_iqidct_control;
676 u32 reg_vcop_ctrl_reg;
677 u32 reg_rv_ai_mb_count;
678 u32 vld_dec_control;
679 struct vframe_s vframe_dummy;
680
681 unsigned char buffer_empty_flag;
682
683 u32 frame_width;
684 u32 frame_height;
685 u32 frame_dur;
686 u32 frame_prog;
687 u32 frame_packing_type;
688
689 struct vframe_chunk_s *chunk;
690
691 u32 stat;
692 unsigned long buf_start;
693 u32 buf_offset;
694 u32 buf_size;
695 /* u32 ucode_map_start; */
696 u32 pts_outside;
697 u32 sync_outside;
698 u32 vh264_ratio;
699 u32 vh264_rotation;
700 u32 use_idr_framerate;
701
702 u32 seq_info;
703 u32 seq_info2;
704 u32 video_signal_from_vui; /*to do .. */
705 u32 timing_info_present_flag;
706 u32 fixed_frame_rate_flag;
707 u32 bitstream_restriction_flag;
708 u32 num_reorder_frames;
709 u32 max_dec_frame_buffering;
710 u32 iframe_count;
711 u32 aspect_ratio_info;
712 u32 num_units_in_tick;
713 u32 time_scale;
714 u32 h264_ar;
715 bool h264_first_valid_pts_ready;
716 u32 h264pts1;
717 u32 h264pts2;
718 u32 pts_duration;
719 u32 h264_pts_count;
720 u32 duration_from_pts_done;
721 u32 pts_unstable;
722 u32 unstable_pts;
723 u32 last_checkout_pts;
724 u32 max_refer_buf;
725
726 s32 vh264_stream_switching_state;
727 struct vframe_s *p_last_vf;
728 u32 last_pts;
729 u32 last_pts_remainder;
730 u32 last_duration;
731 u32 last_mb_width, last_mb_height;
732 bool check_pts_discontinue;
733 bool pts_discontinue;
734 u32 wait_buffer_counter;
735 u32 first_offset;
736 u32 first_pts;
737 u64 first_pts64;
738 bool first_pts_cached;
739 u64 last_pts64;
740#if 0
741 void *sei_data_buffer;
742 dma_addr_t sei_data_buffer_phys;
743#endif
744
745 uint error_recovery_mode;
746 uint mb_total;
747 uint mb_width;
748 uint mb_height;
749
750 uint i_only;
751 int skip_frame_count;
752 bool no_poc_reorder_flag;
753 bool send_error_frame_flag;
754 dma_addr_t mc_dma_handle;
755 void *mc_cpu_addr;
756 int vh264_reset;
757
758 atomic_t vh264_active;
759
760 struct dec_sysinfo vh264_amstream_dec_info;
761
762 int dec_result;
763 struct work_struct work;
764 struct work_struct notify_work;
765 struct work_struct timeout_work;
766 void (*vdec_cb)(struct vdec_s *, void *);
767 void *vdec_cb_arg;
768
769 struct timer_list check_timer;
770
771 /**/
772 unsigned int last_frame_time;
773 u32 vf_pre_count;
774 u32 vf_get_count;
775 u32 vf_put_count;
776
777 /* timeout handle */
778 unsigned long int start_process_time;
779 unsigned int last_mby_mbx;
780 unsigned int last_vld_level;
781 unsigned int decode_timeout_count;
782 unsigned int timeout_num;
783 unsigned int search_dataempty_num;
784 unsigned int decode_timeout_num;
785 unsigned int decode_dataempty_num;
786 unsigned int buffer_empty_recover_num;
787
788 unsigned get_data_count;
789 unsigned get_data_start_time;
790 /**/
791
792 /*log*/
793 unsigned int packet_write_success_count;
794 unsigned int packet_write_EAGAIN_count;
795 unsigned int packet_write_ENOMEM_count;
796 unsigned int packet_write_EFAULT_count;
797 unsigned int total_read_size_pre;
798 unsigned int total_read_size;
799 unsigned int frame_count_pre;
800#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
801 u8 switch_dvlayer_flag;
802 u8 got_valid_nal;
803#endif
804 u8 eos;
805 u8 data_flag;
806 u32 no_error_count;
807 u32 no_error_i_count;
808 /*
809 NODISP_FLAG
810 */
811 u8 dec_flag;
812
813 u32 ucode_pause_pos;
814
815 u8 reset_bufmgr_flag;
816 u32 reset_bufmgr_count;
817 u32 cfg_param1;
818 u32 cfg_param2;
819 u32 cfg_param3;
820 u32 cfg_param4;
821 int valve_count;
822 u8 next_again_flag;
823 u32 pre_parser_wr_ptr;
824 struct firmware_s *fw;
825 struct firmware_s *fw_mmu;
826#ifdef MH264_USERDATA_ENABLE
827 /*user data*/
828 struct mutex userdata_mutex;
829 struct mh264_userdata_info_t userdata_info;
830 struct mh264_userdata_record_t ud_record;
831 int wait_for_udr_send;
832#endif
833 u32 no_mem_count;
834 u32 canvas_mode;
835 bool is_used_v4l;
836 void *v4l2_ctx;
837 bool v4l_params_parsed;
838 wait_queue_head_t wait_q;
839 u32 reg_g_status;
840 struct mutex chunks_mutex;
841 int need_cache_size;
842 u64 sc_start_time;
843 u8 frmbase_cont_flag;
844 struct vframe_qos_s vframe_qos;
845 int frameinfo_enable;
846 bool first_head_check_flag;
847 unsigned int height_aspect_ratio;
848 unsigned int width_aspect_ratio;
849 bool new_iframe_flag;
850 bool ref_err_flush_dpb_flag;
851 unsigned int first_i_policy;
852 u32 reorder_dpb_size_margin;
853};
854
855static u32 again_threshold;
856
857static void timeout_process(struct vdec_h264_hw_s *hw);
858static void dump_bufspec(struct vdec_h264_hw_s *hw,
859 const char *caller);
860static void h264_reconfig(struct vdec_h264_hw_s *hw);
861static void h264_reset_bufmgr(struct vdec_s *vdec);
862static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset);
863static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
864static int vh264_stop(struct vdec_h264_hw_s *hw);
865static s32 vh264_init(struct vdec_h264_hw_s *hw);
866static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
867 u32 index);
868static void release_aux_data(struct vdec_h264_hw_s *hw,
869 int buf_spec_num);
870#ifdef ERROR_HANDLE_TEST
871static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
872#endif
873
874#define H265_PUT_SAO_4K_SET 0x03
875#define H265_ABORT_SAO_4K_SET 0x04
876#define H265_ABORT_SAO_4K_SET_DONE 0x05
877
878#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
879#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
880#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
881#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
882#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
883
884
885#define HEVC_CM_HEADER_START_ADDR 0x3628
886#define HEVC_CM_BODY_START_ADDR 0x3626
887#define HEVC_CM_BODY_LENGTH 0x3627
888#define HEVC_CM_HEADER_LENGTH 0x3629
889#define HEVC_CM_HEADER_OFFSET 0x362b
890#define HEVC_SAO_CTRL9 0x362d
891#define HEVCD_MPP_DECOMP_CTL3 0x34c4
892#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
893#define HEVC_DBLK_CFGB 0x350b
894#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
895
896#define H265_DW_NO_SCALE
897#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
898#define H265_LOSLESS_COMPRESS_MODE
899#define MAX_FRAME_4K_NUM 0x1200
900#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
901
902/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
903static u32 mem_map_mode = H265_MEM_MAP_MODE;
904
905#define MAX_SIZE_8K (8192 * 4608)
906#define MAX_SIZE_4K (4096 * 2304)
907
908static int is_oversize(int w, int h)
909{
910 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
911 MAX_SIZE_8K : MAX_SIZE_4K;
912
913 if (w < 0 || h < 0)
914 return true;
915
916 if (h != 0 && (w > max / h))
917 return true;
918
919 return false;
920}
921
922static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
923 int frame_type,
924 u32 vpts,
925 u32 vpts_valid);
926static int compute_losless_comp_body_size(int width,
927 int height, int bit_depth_10);
928static int compute_losless_comp_header_size(int width, int height);
929
930static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
931 int pic_width, int pic_height, u16 bit_depth,
932 unsigned int *mmu_index_adr) {
933 int cur_buf_idx;
934 int bit_depth_10 = (bit_depth != 0x00);
935 int picture_size;
936 u32 cur_mmu_4k_number;
937
938 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
939 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
940 picture_size = compute_losless_comp_body_size(pic_width,
941 pic_height, bit_depth_10);
942 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
943 dpb_print(DECODE_ID(hw),
944 PRINT_FLAG_MMU_DETAIL,
945 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
946 cur_buf_idx, picture_size, cur_mmu_4k_number);
947
948 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
949 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
950 cur_mmu_4k_number);
951 return -1;
952 }
953
954 return decoder_mmu_box_alloc_idx(
955 hw->mmu_box,
956 cur_buf_idx,
957 cur_mmu_4k_number,
958 mmu_index_adr);
959}
960
961static int compute_losless_comp_body_size(int width,
962 int height, int bit_depth_10)
963{
964 int width_x64;
965 int height_x32;
966 int bsize;
967
968 width_x64 = width + 63;
969 width_x64 >>= 6;
970
971 height_x32 = height + 31;
972 height_x32 >>= 5;
973
974#ifdef H264_MMU
975 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
976#else
977 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
978#endif
979 return bsize;
980}
981
982static int compute_losless_comp_header_size(int width, int height)
983{
984 int width_x64;
985 int width_x128;
986 int height_x64;
987 int hsize;
988
989 width_x64 = width + 63;
990 width_x64 >>= 6;
991
992 width_x128 = width + 127;
993 width_x128 >>= 7;
994
995 height_x64 = height + 63;
996 height_x64 >>= 6;
997
998#ifdef H264_MMU
999 hsize = 128*width_x64*height_x64;
1000#else
1001 hsize = 32*width_x128*height_x64;
1002#endif
1003 return hsize;
1004}
1005
1006static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1007{
1008 int ratio = 1;
1009 int dw_mode = hw->double_write_mode;
1010 if ((dw_mode == 2) ||
1011 (dw_mode == 3))
1012 ratio = 4;
1013 else if (dw_mode == 4)
1014 ratio = 2;
1015 return ratio;
1016}
1017
1018
1019static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1020{
1021 int pic_width, pic_height;
1022 int lcu_size = 16;
1023 int dw_buf_size;
1024 u32 dw_buffer_size_u_v;
1025 u32 dw_buffer_size_u_v_h;
1026 int dw_mode = hw->double_write_mode;
1027
1028 pic_width = hw->frame_width;
1029 pic_height = hw->frame_height;
1030
1031 if (dw_mode) {
1032 int pic_width_dw = pic_width /
1033 get_double_write_ratio(hw);
1034 int pic_height_dw = pic_height /
1035 get_double_write_ratio(hw);
1036
1037 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1038 pic_width_dw / lcu_size + 1 :
1039 pic_width_dw / lcu_size;
1040 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1041 pic_height_dw / lcu_size + 1 :
1042 pic_height_dw / lcu_size;
1043 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1044
1045
1046 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1047 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1048 /*64k alignment*/
1049 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1050 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1051 } else {
1052 *pdw_buffer_size_u_v_h = 0;
1053 dw_buf_size = 0;
1054 }
1055
1056 return dw_buf_size;
1057}
1058
1059
1060static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1061{
1062 int i, size;
1063 u32 canvas_addr;
1064 unsigned long maddr;
1065 int num_buff = hw->dpb.mDPB.size;
1066 int dw_size = 0;
1067 u32 dw_buffer_size_u_v_h;
1068 u32 blkmode = hw->canvas_mode;
1069 int dw_mode = hw->double_write_mode;
1070
1071 canvas_addr = ANC0_CANVAS_ADDR;
1072 for (i = 0; i < num_buff; i++)
1073 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1074
1075 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1076 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1077
1078
1079 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1080 size += dw_size;
1081 if (size > 0)
1082 size += 0x10000;
1083
1084 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1085 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1086 dw_buffer_size_u_v_h, dw_size, size);
1087
1088 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1089 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1090 hw->losless_comp_body_size,
1091 hw->losless_comp_header_size,
1092 hw->losless_comp_body_size_sao);
1093
1094 for (i = 0; i < num_buff; i++) {
1095 if (!restore) {
1096 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1097 HEADER_BUFFER_IDX(i), size,
1098 DRIVER_HEADER_NAME, &maddr) < 0) {
1099 dpb_print(DECODE_ID(hw), 0,
1100 "%s malloc compress header failed %d\n",
1101 DRIVER_HEADER_NAME, i);
1102 return;
1103 }
1104 } else
1105 maddr = hw->buffer_spec[i].alloc_header_addr;
1106 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1107 hw->buffer_spec[i].alloc_header_addr = maddr;
1108 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1109 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1110 __func__, i, (u32)maddr, size);
1111
1112 if (dw_mode) {
1113 u32 addr;
1114 int canvas_w;
1115 int canvas_h;
1116
1117 canvas_w = hw->frame_width /
1118 get_double_write_ratio(hw);
1119 canvas_h = hw->frame_height /
1120 get_double_write_ratio(hw);
1121
1122 if (hw->canvas_mode == 0)
1123 canvas_w = ALIGN(canvas_w, 32);
1124 else
1125 canvas_w = ALIGN(canvas_w, 64);
1126 canvas_h = ALIGN(canvas_h, 32);
1127
1128 hw->buffer_spec[i].dw_y_adr =
1129 maddr + hw->losless_comp_header_size;
1130
1131 hw->buffer_spec[i].dw_y_adr =
1132 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1133 << 16;
1134 hw->buffer_spec[i].dw_u_v_adr =
1135 hw->buffer_spec[i].dw_y_adr
1136 + (dw_buffer_size_u_v_h << 16) * 2;
1137
1138
1139 hw->buffer_spec[i].buf_adr
1140 = hw->buffer_spec[i].dw_y_adr;
1141 addr = hw->buffer_spec[i].buf_adr;
1142
1143
1144 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1145 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1146 hw->buffer_spec[i].dw_y_adr,
1147 hw->buffer_spec[i].dw_u_v_adr,
1148 hw->buffer_spec[i].y_addr,
1149 hw->buffer_spec[i].u_addr,
1150 hw->buffer_spec[i].v_addr,
1151 canvas_w,
1152 canvas_h);
1153
1154 hw->buffer_spec[i].canvas_config[0].phy_addr =
1155 hw->buffer_spec[i].dw_y_adr;
1156 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1157 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1158 hw->buffer_spec[i].canvas_config[0].block_mode =
1159 blkmode;
1160 hw->buffer_spec[i].canvas_config[0].endian = 7;
1161
1162 hw->buffer_spec[i].canvas_config[1].phy_addr =
1163 hw->buffer_spec[i].dw_u_v_adr;
1164 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1165 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1166 hw->buffer_spec[i].canvas_config[1].block_mode =
1167 blkmode;
1168 hw->buffer_spec[i].canvas_config[1].endian = 7;
1169 }
1170 }
1171 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1172
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1174 for (i = 0; i < 32; i++)
1175 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1176 return;
1177}
1178static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1179{
1180 u32 i;
1181 u32 ref_canv;
1182 struct Slice *pSlice = &(hw->dpb.mSlice);
1183 /*REFLIST[0]*/
1184 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1185 struct StorablePicture *ref = pSlice->listX[0][i];
1186 if (ref == NULL)
1187 return;
1188 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1189 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1191 (ref->buf_spec_num & 0x3f) << 8);
1192 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1193 }
1194 /*REFLIST[1]*/
1195 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1196 struct StorablePicture *ref = pSlice->listX[1][i];
1197 if (ref == NULL)
1198 return;
1199 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1200 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1202 (ref->buf_spec_num & 0x3f) << 8);
1203 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1204 }
1205 return;
1206}
1207
1208static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1209{
1210 u32 rdata32;
1211 u32 rdata32_2;
1212 u32 slice_type;
1213 struct StorablePicture *ref;
1214 struct Slice *pSlice;
1215 slice_type = hw->dpb.mSlice.slice_type;
1216 pSlice = &(hw->dpb.mSlice);
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1218 if (slice_type == I_SLICE) {
1219 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1220 return;
1221 }
1222 if (slice_type == B_SLICE) {
1223 ref = pSlice->listX[0][0];
1224 if (ref == NULL)
1225 return;
1226 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1227 ((ref->buf_spec_num & 0x3f) << 8));
1228 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1229 rdata32 = rdata32 & 0xffff;
1230 rdata32 = rdata32 | (rdata32 << 16);
1231 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1232
1233 ref = pSlice->listX[1][0];
1234 if (ref == NULL)
1235 return;
1236 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1237 ((ref->buf_spec_num & 0x3f) << 8));
1238 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1239 rdata32_2 = rdata32_2 & 0xffff;
1240 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1241 if (rdata32 == rdata32_2) {
1242 ref = pSlice->listX[1][1];
1243 if (ref == NULL)
1244 return;
1245 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1246 ((ref->buf_spec_num & 0x3f) << 8));
1247 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1248 rdata32_2 = rdata32_2 & 0xffff;
1249 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1250 }
1251 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1252 } else { /*P-PIC*/
1253 ref = pSlice->listX[0][0];
1254 if (ref == NULL)
1255 return;
1256 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1257 ((ref->buf_spec_num & 0x3f) << 8));
1258 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1259 rdata32 = rdata32 & 0xffff;
1260 rdata32 = rdata32 | (rdata32 << 16);
1261 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1262
1263 ref = pSlice->listX[0][1];
1264 if (ref == NULL)
1265 return;
1266 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1267 ((ref->buf_spec_num & 0x3f) << 8));
1268 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1269 rdata32 = rdata32 & 0xffff;
1270 rdata32 = rdata32 | (rdata32 << 16);
1271 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1272 }
1273 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1274 return;
1275}
1276
1277
1278static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1279 u32 width, u32 height) {
1280 u32 data32;
1281 u32 lcu_x_num, lcu_y_num;
1282 u32 lcu_total;
1283 u32 mc_buffer_size_u_v;
1284 u32 mc_buffer_size_u_v_h;
1285 int dw_mode = hw->double_write_mode;
1286
1287 lcu_x_num = (width + 15) >> 4;
1288 lcu_y_num = (height + 15) >> 4;
1289 lcu_total = lcu_x_num * lcu_y_num;
1290
1291 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1292 hw->mc_buffer_size_u_v_h =
1293 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1294
1295 hw->losless_comp_body_size = 0;
1296
1297 hw->losless_comp_body_size_sao =
1298 compute_losless_comp_body_size(width, height, 0);
1299 hw->losless_comp_header_size =
1300 compute_losless_comp_header_size(width, height);
1301
1302 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1303 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1304
1305 /* setup lcu_size = 16*/
1306 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1307 /*pic_width/pic_height*/
1308 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1309 (height & 0xffff) << 16 | (width & 0xffff));
1310 /* bitdepth_luma = 8*/
1311 /* bitdepth_chroma = 8*/
1312 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1313
1314#ifdef H265_LOSLESS_COMPRESS_MODE
1315 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1317#else
1318 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1319#endif
1320 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1321 data32 &= (~0x30);
1322 data32 |= (hw->canvas_mode << 4);
1323 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1324
1325 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1326 (0x80 << 20) | (0x80 << 10) | (0xff));
1327
1328 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1329
1330 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1331 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1332 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1333 /* ipp_enable*/
1334 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1335
1336 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1337 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1338 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1339 if (dw_mode)
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1341 else
1342 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1343 }
1344
1345 data32 = READ_VREG(HEVC_SAO_CTRL0);
1346 data32 &= (~0xf);
1347 data32 |= 0x4;
1348 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1349 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1350 (width & 0xffff));
1351 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1352
1353 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1354 data32 = (lcu_x_num | lcu_y_num << 16);
1355 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1357 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1358 data32 = (mc_buffer_size_u_v_h << 16);
1359 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1360
1361 data32 = READ_VREG(HEVC_SAO_CTRL1);
1362 data32 &= (~0x3000);
1363 data32 &= (~0xff0);
1364 data32 |= endian; /* Big-Endian per 64-bit */
1365
1366 if (hw->mmu_enable && dw_mode)
1367 data32 |= ((hw->canvas_mode << 12));
1368 else
1369 data32 |= ((hw->canvas_mode << 12)|2);
1370
1371 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1372
1373#ifdef H265_DW_NO_SCALE
1374 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1375 if (hw->mmu_enable && dw_mode) {
1376 data32 = READ_VREG(HEVC_SAO_CTRL5);
1377 data32 &= (~(0xff << 16));
1378 if (dw_mode == 2 ||
1379 dw_mode == 3)
1380 data32 |= (0xff<<16);
1381 else if (dw_mode == 4)
1382 data32 |= (0x33<<16);
1383 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1384 }
1385
1386
1387#endif
1388
1389
1390#ifdef H265_LOSLESS_COMPRESS_MODE
1391 data32 = READ_VREG(HEVC_SAO_CTRL5);
1392 data32 |= (1<<9); /*8-bit smem-mode*/
1393 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1394
1395 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1396 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1397 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1398#endif
1399
1400#ifdef H265_LOSLESS_COMPRESS_MODE
1401 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1402 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1403#endif
1404
1405 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1406
1407 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1408
1409 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1410 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1411 return;
1412}
1413
1414static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1415 u32 is_new_pic, u32 is_idr)
1416{
1417 hw->is_new_pic = is_new_pic;
1418 hw->is_idr_frame = is_idr;
1419 return;
1420}
1421
1422static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1423 struct StorablePicture *pic) {
1424 u32 mc_y_adr;
1425 u32 mc_u_v_adr;
1426 u32 dw_y_adr;
1427 u32 dw_u_v_adr;
1428 u32 canvas_addr;
1429 int ret;
1430 int dw_mode = hw->double_write_mode;
1431 if (hw->is_new_pic != 1)
1432 return;
1433
1434 if (hw->is_idr_frame) {
1435 /* William TBD */
1436 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1437 }
1438
1439 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1440 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1441 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1442 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1443 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1444 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1445 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1446 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1447 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1448
1449
1450 if (dw_mode) {
1451 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1452 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1453 } else {
1454 dw_y_adr = 0;
1455 dw_u_v_adr = 0;
1456 }
1457#ifdef H265_LOSLESS_COMPRESS_MODE
1458 if (dw_mode)
1459 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1460 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1461#ifdef H264_MMU
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1463#else
1464 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1465 (mc_y_adr + hw->losless_comp_body_size));
1466#endif
1467#else
1468 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1469#endif
1470
1471#ifndef H265_LOSLESS_COMPRESS_MODE
1472 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1473#else
1474 if (dw_mode)
1475 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1476#endif
1477
1478#ifndef LOSLESS_COMPRESS_MODE
1479 if (dw_mode) {
1480 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1481 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1482 }
1483#else
1484 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1485 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1486#endif
1487
1488 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1489 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1490 hw->frame_mmu_map_addr);
1491 if (ret != 0) {
1492 dpb_print(DECODE_ID(hw),
1493 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1494 pic->buf_spec_num,
1495 ret);
1496 return;
1497 }
1498
1499 /*Reset SAO + Enable SAO slice_start*/
1500 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1501 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1504 WRITE_VREG(HEVC_SAO_INT_STATUS,
1505 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1506 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1507 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1508
1509 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1510 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1511 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1512 } else
1513 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1514 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1515 hw->frame_busy = 1;
1516 return;
1517}
1518
1519
1520static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1521 u32 buf_spec_num) {
1522 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1523 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1524 dpb_print(DECODE_ID(hw),
1525 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1526 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1527 return;
1528}
1529
1530
1531static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1532{
1533 ulong timeout = jiffies + HZ;
1534 dpb_print(DECODE_ID(hw),
1535 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1536 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1537 if (time_after(jiffies, timeout)) {
1538 dpb_print(DECODE_ID(hw),
1539 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1540 break;
1541 }
1542 }
1543 timeout = jiffies + HZ;
1544 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1545 if (time_after(jiffies, timeout)) {
1546 dpb_print(DECODE_ID(hw),
1547 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1548 break;
1549 }
1550 }
1551 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1552 hw->frame_done = 1;
1553 return;
1554}
1555
1556static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1557{
1558 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1559 if (p_H264_Dpb->mVideo.dec_picture) {
1560 release_picture(p_H264_Dpb,
1561 p_H264_Dpb->mVideo.dec_picture);
1562 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1563 p_H264_Dpb->mVideo.dec_picture = NULL;
1564 if (hw->mmu_enable)
1565 hevc_set_frame_done(hw);
1566 }
1567}
1568
1569static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1570{
1571 ulong timeout = jiffies + HZ;
1572 dpb_print(DECODE_ID(hw),
1573 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1574 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1575 if (time_after(jiffies, timeout)) {
1576 dpb_print(DECODE_ID(hw),
1577 PRINT_FLAG_MMU_DETAIL,
1578 "hevc_sao_wait_done...wait timeout!\n");
1579 break;
1580 }
1581 }
1582 timeout = jiffies + HZ;
1583 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1584 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1585 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1586 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1587 H265_ABORT_SAO_4K_SET_DONE) {
1588 if (time_after(jiffies, timeout)) {
1589 dpb_print(DECODE_ID(hw),
1590 PRINT_FLAG_MMU_DETAIL,
1591 "wait h265_abort_sao_4k_set_done timeout!\n");
1592 break;
1593 }
1594 }
1595 }
1596 amhevc_stop();
1597 hw->frame_busy = 0;
1598 hw->frame_done = 0;
1599 dpb_print(DECODE_ID(hw),
1600 PRINT_FLAG_MMU_DETAIL,
1601 "sao wait done ,hevc stop!\n");
1602 }
1603 return;
1604}
1605static void buf_spec_init(struct vdec_h264_hw_s *hw)
1606{
1607 int i;
1608 unsigned long flags;
1609 spin_lock_irqsave(&hw->bufspec_lock, flags);
1610
1611 for (i = 0; i < VF_POOL_SIZE; i++) {
1612 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1613 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1614 if ((vf->index != -1) &&
1615 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1616 (hw->buffer_spec[ref_idx].used != -1)) {
1617 vf->index = -1;
1618 }
1619 }
1620
1621 hw->cur_pool++;
1622 if (hw->cur_pool >= VF_POOL_NUM)
1623 hw->cur_pool = 0;
1624
1625 for (i = 0; i < VF_POOL_SIZE; i++) {
1626 struct vframe_s *vf = &hw->vfpool[hw->cur_pool][i];
1627 u32 ref_idx = BUFSPEC_INDEX(vf->index);
1628 if ((vf->index != -1) &&
1629 (hw->buffer_spec[ref_idx].vf_ref == 0) &&
1630 (hw->buffer_spec[ref_idx].used != -1)) {
1631 vf->index = -1;
1632 }
1633 }
1634
1635 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1636 hw->buffer_spec[i].used = -1;
1637 hw->buffer_spec[i].canvas_pos = -1;
1638 }
1639
1640 if (dpb_is_debug(DECODE_ID(hw),
1641 PRINT_FLAG_DUMP_BUFSPEC))
1642 dump_bufspec(hw, __func__);
1643 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1644}
1645
1646/*is active in buf management */
1647static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1648 int buf_spec_num)
1649{
1650 unsigned char ret = 0;
1651 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1652 hw->buffer_spec[buf_spec_num].used == 2 ||
1653 hw->buffer_spec[buf_spec_num].used == 3 ||
1654 hw->buffer_spec[buf_spec_num].used == 5)
1655 ret = 1;
1656 return ret;
1657}
1658
1659static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1660 int buf_spec_num)
1661{
1662 unsigned char ret = 0;
1663 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1664 hw->buffer_spec[buf_spec_num].used == 3 ||
1665 hw->buffer_spec[buf_spec_num].used == 5)
1666 ret = 1;
1667 return ret;
1668}
1669
1670static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1671{
1672 if (hw->mmu_enable) {
1673 if (hw->buffer_spec[i].alloc_header_addr)
1674 return 0;
1675 else
1676 return -1;
1677 } else {
1678
1679 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1680 int addr;
1681#ifdef VDEC_DW
1682 int orig_buf_size;
1683 orig_buf_size = buf_size;
1684 if (IS_VDEC_DW(hw) == 1)
1685 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1686 else if (IS_VDEC_DW(hw) == 2)
1687 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1688#endif
1689 if (hw->buffer_spec[i].cma_alloc_addr)
1690 return 0;
1691
1692 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1693 PAGE_ALIGN(buf_size), DRIVER_NAME,
1694 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1695 hw->buffer_spec[i].cma_alloc_addr = 0;
1696 if (hw->no_mem_count++ > 3) {
1697 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1698 hw->reset_bufmgr_flag = 1;
1699 }
1700 dpb_print(DECODE_ID(hw), 0,
1701 "%s, fail to alloc buf for bufspec%d, try later\n",
1702 __func__, i
1703 );
1704 return -1;
1705 } else {
1706 hw->no_mem_count = 0;
1707 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1708 }
1709
1710 hw->buffer_spec[i].buf_adr =
1711 hw->buffer_spec[i].cma_alloc_addr;
1712 addr = hw->buffer_spec[i].buf_adr;
1713
1714
1715 hw->buffer_spec[i].y_addr = addr;
1716 addr += hw->mb_total << 8;
1717 hw->buffer_spec[i].u_addr = addr;
1718 hw->buffer_spec[i].v_addr = addr;
1719 addr += hw->mb_total << 7;
1720
1721 hw->buffer_spec[i].canvas_config[0].phy_addr =
1722 hw->buffer_spec[i].y_addr;
1723 hw->buffer_spec[i].canvas_config[0].width =
1724 hw->mb_width << 4;
1725 hw->buffer_spec[i].canvas_config[0].height =
1726 hw->mb_height << 4;
1727 hw->buffer_spec[i].canvas_config[0].block_mode =
1728 hw->canvas_mode;
1729
1730 hw->buffer_spec[i].canvas_config[1].phy_addr =
1731 hw->buffer_spec[i].u_addr;
1732 hw->buffer_spec[i].canvas_config[1].width =
1733 hw->mb_width << 4;
1734 hw->buffer_spec[i].canvas_config[1].height =
1735 hw->mb_height << 3;
1736 hw->buffer_spec[i].canvas_config[1].block_mode =
1737 hw->canvas_mode;
1738 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1739 "%s, alloc buf for bufspec%d\n",
1740 __func__, i
1741 );
1742#ifdef VDEC_DW
1743
1744 if (!IS_VDEC_DW(hw))
1745 return 0;
1746 else if (IS_VDEC_DW(hw) == 1) {
1747 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1748 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1749 addr += hw->mb_total << 7;
1750 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1751 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1752 addr += hw->mb_total << 6;
1753
1754 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1755 hw->buffer_spec[i].vdec_dw_y_addr;
1756 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1757 hw->mb_width << 3;
1758 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1759 hw->mb_height << 4;
1760 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1761 CANVAS_BLKMODE_32X32;
1762
1763 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1764 hw->buffer_spec[i].vdec_dw_u_addr;
1765 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1766 hw->mb_width << 3;
1767 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1768 hw->mb_height << 3;
1769 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1770 CANVAS_BLKMODE_32X32;
1771 }else {
1772 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1773 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1774 addr += hw->mb_total << 6;
1775 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1776 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1777 addr += hw->mb_total << 5;
1778
1779 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1780 hw->buffer_spec[i].vdec_dw_y_addr;
1781 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1782 hw->mb_width << 3;
1783 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1784 hw->mb_height << 3;
1785 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1786 CANVAS_BLKMODE_32X32;
1787
1788 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1789 hw->buffer_spec[i].vdec_dw_u_addr;
1790 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1791 hw->mb_width << 3;
1792 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1793 hw->mb_height << 2;
1794 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1795 CANVAS_BLKMODE_32X32;
1796 }
1797 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1798 "%s, vdec_dw: alloc buf for bufspec%d\n",
1799 __func__, i
1800 );
1801#endif
1802 }
1803 return 0;
1804}
1805
1806static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1807{
1808 int ret = 0;
1809 struct aml_vcodec_ctx *ctx = NULL;
1810 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1811 struct canvas_config_s *y_canvas_cfg = NULL;
1812 struct canvas_config_s *c_canvas_cfg = NULL;
1813 struct vdec_v4l2_buffer *fb = NULL;
1814 unsigned int y_addr = 0, c_addr = 0;
1815
1816 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1817 pr_err("the v4l context has err.\n");
1818 return -1;
1819 }
1820
1821 if (bs->cma_alloc_addr)
1822 return 0;
1823
1824 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1825 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1826 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1827 ctx->id, __func__,
1828 (hw->mb_total << 8) + (hw->mb_total << 7));
1829
1830 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1831 if (ret < 0) {
1832 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1833 "[%d] get fb fail.\n", ctx->id);
1834 return ret;
1835 }
1836
1837 bs->cma_alloc_addr = (unsigned long)fb;
1838 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1839 "[%d] %s(), cma alloc addr: 0x%x\n",
1840 ctx->id, __func__, bs->cma_alloc_addr);
1841
1842 if (fb->num_planes == 1) {
1843 y_addr = fb->m.mem[0].addr;
1844 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1845 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1846 } else if (fb->num_planes == 2) {
1847 y_addr = fb->m.mem[0].addr;
1848 c_addr = fb->m.mem[1].addr;
1849 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1850 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1851 }
1852
1853 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1854 "[%d] %s(), y_addr: %x, size: %u\n",
1855 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1856 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1857 "[%d] %s(), c_addr: %x, size: %u\n",
1858 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1859
1860 bs->y_addr = y_addr;
1861 bs->u_addr = c_addr;
1862 bs->v_addr = c_addr;
1863
1864 y_canvas_cfg = &bs->canvas_config[0];
1865 c_canvas_cfg = &bs->canvas_config[1];
1866
1867 y_canvas_cfg->phy_addr = y_addr;
1868 y_canvas_cfg->width = hw->mb_width << 4;
1869 y_canvas_cfg->height = hw->mb_height << 4;
1870 y_canvas_cfg->block_mode = hw->canvas_mode;
1871 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1872 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1873 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1874 y_canvas_cfg->width,y_canvas_cfg->height);
1875
1876 c_canvas_cfg->phy_addr = c_addr;
1877 c_canvas_cfg->width = hw->mb_width << 4;
1878 c_canvas_cfg->height = hw->mb_height << 3;
1879 c_canvas_cfg->block_mode = hw->canvas_mode;
1880 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1881 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1882 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1883 c_canvas_cfg->width, c_canvas_cfg->height);
1884
1885 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1886 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1887
1888 return ret;
1889}
1890
1891static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1892{
1893 int blkmode = hw->canvas_mode;
1894 int endian = 0;
1895
1896 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1897 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1898 endian = 7;
1899 else
1900 endian = 0;
1901 }
1902
1903 if (hw->is_used_v4l)
1904 endian = 7;
1905
1906 canvas_config_ex(hw->buffer_spec[i].
1907 y_canvas_index,
1908 hw->buffer_spec[i].y_addr,
1909 hw->mb_width << 4,
1910 hw->mb_height << 4,
1911 CANVAS_ADDR_NOWRAP,
1912 blkmode,
1913 endian);
1914
1915 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1916 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1917 (1 << 11) | /* canvas_blk32_wr */
1918 (blkmode << 10) | /* canvas_blk32*/
1919 (1 << 8) | /* canvas_index_wr*/
1920 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1921 );
1922 }
1923
1924 canvas_config_ex(hw->buffer_spec[i].
1925 u_canvas_index,
1926 hw->buffer_spec[i].u_addr,
1927 hw->mb_width << 4,
1928 hw->mb_height << 3,
1929 CANVAS_ADDR_NOWRAP,
1930 blkmode,
1931 endian);
1932
1933 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1934 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1935 (1 << 11) |
1936 (blkmode << 10) |
1937 (1 << 8) |
1938 (hw->buffer_spec[i].u_canvas_index << 0));
1939 }
1940
1941 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1942 spec2canvas(&hw->buffer_spec[i]));
1943
1944
1945#ifdef VDEC_DW
1946 if (!IS_VDEC_DW(hw))
1947 return;
1948 else if (IS_VDEC_DW(hw) == 1) {
1949 canvas_config_ex(hw->buffer_spec[i].
1950 vdec_dw_y_canvas_index,
1951 hw->buffer_spec[i].vdec_dw_y_addr,
1952 hw->mb_width << 3,
1953 hw->mb_height << 4,
1954 CANVAS_ADDR_NOWRAP,
1955 blkmode,
1956 endian);
1957 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1958 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1959 (1 << 11) |
1960 (blkmode << 10) |
1961 (1 << 8) |
1962 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1963 }
1964 canvas_config_ex(hw->buffer_spec[i].
1965 vdec_dw_u_canvas_index,
1966 hw->buffer_spec[i].vdec_dw_u_addr,
1967 hw->mb_width << 3,
1968 hw->mb_height << 3,
1969 CANVAS_ADDR_NOWRAP,
1970 blkmode,
1971 endian);
1972 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1973 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1974 (1 << 11) |
1975 (blkmode << 10) |
1976 (1 << 8) |
1977 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1978 }
1979 } else {
1980 canvas_config_ex(hw->buffer_spec[i].
1981 vdec_dw_y_canvas_index,
1982 hw->buffer_spec[i].vdec_dw_y_addr,
1983 hw->mb_width << 3,
1984 hw->mb_height << 3,
1985 CANVAS_ADDR_NOWRAP,
1986 blkmode,
1987 endian);
1988 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1989 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1990 (1 << 11) |
1991 (blkmode << 10) |
1992 (1 << 8) |
1993 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1994 }
1995
1996 canvas_config_ex(hw->buffer_spec[i].
1997 vdec_dw_u_canvas_index,
1998 hw->buffer_spec[i].vdec_dw_u_addr,
1999 hw->mb_width << 3,
2000 hw->mb_height << 2,
2001 CANVAS_ADDR_NOWRAP,
2002 blkmode,
2003 endian);
2004 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
2005 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
2006 (1 << 11) |
2007 (blkmode << 10) |
2008 (1 << 8) |
2009 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
2010 }
2011 }
2012#endif
2013}
2014
2015static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
2016{
2017 u32 blkmode = hw->canvas_mode;
2018 int canvas_w;
2019 int canvas_h;
2020
2021 canvas_w = hw->frame_width /
2022 get_double_write_ratio(hw);
2023 canvas_h = hw->frame_height /
2024 get_double_write_ratio(hw);
2025
2026 if (hw->canvas_mode == 0)
2027 canvas_w = ALIGN(canvas_w, 32);
2028 else
2029 canvas_w = ALIGN(canvas_w, 64);
2030 canvas_h = ALIGN(canvas_h, 32);
2031
2032 canvas_config_ex(hw->buffer_spec[i].
2033 y_canvas_index,
2034 hw->buffer_spec[i].dw_y_adr,
2035 canvas_w,
2036 canvas_h,
2037 CANVAS_ADDR_NOWRAP,
2038 blkmode,
2039 7);
2040
2041 canvas_config_ex(hw->buffer_spec[i].
2042 u_canvas_index,
2043 hw->buffer_spec[i].dw_u_v_adr,
2044 canvas_w,
2045 canvas_h,
2046 CANVAS_ADDR_NOWRAP,
2047 blkmode,
2048 7);
2049}
2050
2051static int v4l_get_free_buf_idx(struct vdec_s *vdec)
2052{
2053 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2054 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2055 struct v4l_buff_pool *pool = &v4l->cap_pool;
2056 struct buffer_spec_s *pic = NULL;
2057 int i, idx = INVALID_IDX;
2058 ulong flags;
2059
2060 spin_lock_irqsave(&hw->bufspec_lock, flags);
2061 for (i = 0; i < pool->in; ++i) {
2062 u32 state = (pool->seq[i] >> 16);
2063 u32 index = (pool->seq[i] & 0xffff);
2064
2065 switch (state) {
2066 case V4L_CAP_BUFF_IN_DEC:
2067 pic = &hw->buffer_spec[i];
2068 if ((pic->vf_ref == 0) &&
2069 (pic->used == 0) &&
2070 pic->cma_alloc_addr) {
2071 idx = i;
2072 }
2073 break;
2074 case V4L_CAP_BUFF_IN_M2M:
2075 pic = &hw->buffer_spec[index];
2076 if (!alloc_one_buf_spec_from_queue(hw, index)) {
2077 config_decode_canvas(hw, index);
2078 idx = index;
2079 }
2080 break;
2081 default:
2082 pr_err("v4l buffer state err %d.\n", state);
2083 break;
2084 }
2085
2086 if (idx != INVALID_IDX) {
2087 pic->used = 1;
2088 break;
2089 }
2090 }
2091 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2092
2093 if (idx < 0) {
2094 dpb_print(DECODE_ID(hw), 0, "%s fail\n", __func__);
2095 vmh264_dump_state(vdec);
2096 }
2097
2098 return idx;
2099}
2100
2101int get_free_buf_idx(struct vdec_s *vdec)
2102{
2103 int i;
2104 unsigned long addr, flags;
2105 int index = -1;
2106 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2107 int buf_total = BUFSPEC_POOL_SIZE;
2108
2109 if (hw->is_used_v4l)
2110 return v4l_get_free_buf_idx(vdec);
2111
2112 spin_lock_irqsave(&hw->bufspec_lock, flags);
2113 /*hw->start_search_pos = 0;*/
2114 for (i = hw->start_search_pos; i < buf_total; i++) {
2115 if (hw->mmu_enable)
2116 addr = hw->buffer_spec[i].alloc_header_addr;
2117 else
2118 addr = hw->buffer_spec[i].cma_alloc_addr;
2119
2120 if (hw->buffer_spec[i].vf_ref == 0 &&
2121 hw->buffer_spec[i].used == 0 && addr) {
2122 hw->buffer_spec[i].used = 1;
2123 hw->start_search_pos = i+1;
2124 index = i;
2125 break;
2126 }
2127 }
2128 if (index < 0) {
2129 for (i = 0; i < hw->start_search_pos; i++) {
2130 if (hw->mmu_enable)
2131 addr = hw->buffer_spec[i].alloc_header_addr;
2132 else
2133 addr = hw->buffer_spec[i].cma_alloc_addr;
2134
2135 if (hw->buffer_spec[i].vf_ref == 0 &&
2136 hw->buffer_spec[i].used == 0 && addr) {
2137 hw->buffer_spec[i].used = 1;
2138 hw->start_search_pos = i+1;
2139 index = i;
2140 break;
2141 }
2142 }
2143 }
2144 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2145 if (hw->start_search_pos >= buf_total)
2146 hw->start_search_pos = 0;
2147 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2148 "%s, buf_spec_num %d\n", __func__, index);
2149
2150 if (index < 0) {
2151 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2152 "%s fail\n", __func__);
2153 vmh264_dump_state(vdec);
2154 }
2155
2156 if (dpb_is_debug(DECODE_ID(hw),
2157 PRINT_FLAG_DUMP_BUFSPEC))
2158 dump_bufspec(hw, __func__);
2159 return index;
2160}
2161
2162int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2163{
2164 /*u32 cur_buf_idx;*/
2165 unsigned long flags;
2166 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2167 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2168 "%s buf_spec_num %d used %d\n",
2169 __func__, buf_spec_num,
2170 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2171 if (buf_spec_num >= 0 &&
2172 buf_spec_num < BUFSPEC_POOL_SIZE
2173 ) {
2174 spin_lock_irqsave(&hw->bufspec_lock, flags);
2175 hw->buffer_spec[buf_spec_num].used = 0;
2176 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2177 if (hw->mmu_enable) {
2178 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2179 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2180 cur_buf_idx = cur_buf_idx&0xff;*/
2181 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2182 }
2183 release_aux_data(hw, buf_spec_num);
2184 }
2185 if (dpb_is_debug(DECODE_ID(hw),
2186 PRINT_FLAG_DUMP_BUFSPEC))
2187 dump_bufspec(hw, __func__);
2188 return 0;
2189}
2190
2191static void config_buf_specs(struct vdec_s *vdec)
2192{
2193 int i, j;
2194 unsigned long flags;
2195 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2196 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2197
2198 spin_lock_irqsave(&hw->bufspec_lock, flags);
2199 for (i = 0, j = 0;
2200 j < hw->dpb.mDPB.size
2201 && i < BUFSPEC_POOL_SIZE;
2202 i++) {
2203 int canvas;
2204 if (hw->buffer_spec[i].used != -1)
2205 continue;
2206 if (vdec->parallel_dec == 1) {
2207 if (hw->buffer_spec[i].y_canvas_index == -1)
2208 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2209 if (hw->buffer_spec[i].u_canvas_index == -1) {
2210 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2211 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2212 }
2213#ifdef VDEC_DW
2214 if (IS_VDEC_DW(hw)) {
2215 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2216 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2217 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2218 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2219 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2220 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2221 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2222 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2223 }
2224 }
2225#endif
2226 } else {
2227 canvas = vdec->get_canvas(j * mode, 2);
2228 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2229 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2230 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2231 dpb_print(DECODE_ID(hw),
2232 PRINT_FLAG_DPB_DETAIL,
2233 "config canvas (%d) %x for bufspec %d\r\n",
2234 j, canvas, i);
2235#ifdef VDEC_DW
2236 if (IS_VDEC_DW(hw)) {
2237 canvas = vdec->get_canvas(j * mode + 1, 2);
2238 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2239 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2240 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2241 dpb_print(DECODE_ID(hw),
2242 PRINT_FLAG_DPB_DETAIL,
2243 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2244 j, canvas, i);
2245 }
2246#endif
2247 }
2248
2249 hw->buffer_spec[i].used = 0;
2250 hw->buffer_spec[i].canvas_pos = j;
2251
2252
2253 j++;
2254 }
2255 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2256}
2257
2258static void config_buf_specs_ex(struct vdec_s *vdec)
2259{
2260 int i, j;
2261 unsigned long flags;
2262 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2263 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2264
2265 spin_lock_irqsave(&hw->bufspec_lock, flags);
2266 for (i = 0, j = 0;
2267 j < hw->dpb.mDPB.size
2268 && i < BUFSPEC_POOL_SIZE;
2269 i++) {
2270 int canvas = 0;
2271 if (hw->buffer_spec[i].used != -1)
2272 continue;
2273 if (vdec->parallel_dec == 1) {
2274 if (hw->buffer_spec[i].y_canvas_index == -1)
2275 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2276 if (hw->buffer_spec[i].u_canvas_index == -1) {
2277 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2278 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2279 }
2280#ifdef VDEC_DW
2281 if (IS_VDEC_DW(hw)) {
2282 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2283 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2284 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2285 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2286 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2287 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2288 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2289 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2290 }
2291 }
2292#endif
2293 } else {
2294 canvas = vdec->get_canvas(j* mode, 2);
2295 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2296 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2297 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2298
2299 dpb_print(DECODE_ID(hw),
2300 PRINT_FLAG_DPB_DETAIL,
2301 "config canvas (%d) %x for bufspec %d\r\n",
2302 j, canvas, i);
2303#ifdef VDEC_DW
2304 if (IS_VDEC_DW(hw)) {
2305 canvas = vdec->get_canvas(j*mode + 1, 2);
2306 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2307 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2308 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2309 dpb_print(DECODE_ID(hw),
2310 PRINT_FLAG_DPB_DETAIL,
2311 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2312 j, canvas, i);
2313 }
2314#endif
2315 }
2316
2317 hw->buffer_spec[i].used = 0;
2318 hw->buffer_spec[i].alloc_header_addr = 0;
2319 hw->buffer_spec[i].canvas_pos = j;
2320
2321 j++;
2322 }
2323 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2324}
2325
2326
2327static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2328 unsigned char release_all)
2329{
2330 int i;
2331 unsigned long flags;
2332 unsigned char dealloc_flag = 0;
2333 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2334 if (hw->buffer_spec[i].used == 4 ||
2335 release_all) {
2336 dealloc_flag = 1;
2337 dpb_print(DECODE_ID(hw),
2338 PRINT_FLAG_DPB_DETAIL,
2339 "%s buf_spec_num %d\n",
2340 __func__, i
2341 );
2342 spin_lock_irqsave
2343 (&hw->bufspec_lock, flags);
2344 hw->buffer_spec[i].used = -1;
2345 spin_unlock_irqrestore
2346 (&hw->bufspec_lock, flags);
2347 release_aux_data(hw, i);
2348
2349 if (!hw->mmu_enable) {
2350 if (hw->buffer_spec[i].cma_alloc_addr) {
2351 if (!hw->is_used_v4l) {
2352 decoder_bmmu_box_free_idx(
2353 hw->bmmu_box,
2354 i);
2355 }
2356 spin_lock_irqsave
2357 (&hw->bufspec_lock, flags);
2358 hw->buffer_spec[i].cma_alloc_addr = 0;
2359 hw->buffer_spec[i].buf_adr = 0;
2360 spin_unlock_irqrestore
2361 (&hw->bufspec_lock, flags);
2362 }
2363 } else {
2364 if (hw->buffer_spec[i].alloc_header_addr) {
2365 decoder_mmu_box_free_idx(
2366 hw->mmu_box,
2367 i);
2368 spin_lock_irqsave
2369 (&hw->bufspec_lock, flags);
2370 hw->buffer_spec[i].
2371 alloc_header_addr = 0;
2372 hw->buffer_spec[i].buf_adr = 0;
2373 spin_unlock_irqrestore
2374 (&hw->bufspec_lock, flags);
2375 }
2376 }
2377 }
2378 }
2379 if (dealloc_flag &&
2380 dpb_is_debug(DECODE_ID(hw),
2381 PRINT_FLAG_DUMP_BUFSPEC))
2382 dump_bufspec(hw, __func__);
2383 return;
2384}
2385
2386unsigned char have_free_buf_spec(struct vdec_s *vdec)
2387{
2388 int i;
2389 unsigned long addr;
2390 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2391 struct aml_vcodec_ctx * v4l = hw->v4l2_ctx;
2392 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2393 int index = -1;
2394 int ret = 0;
2395 int allocated_count = 0;
2396
2397 if (hw->is_used_v4l) {
2398 for (i = 0; i < hw->dpb.mDPB.size; i++) {
2399 if (hw->buffer_spec[i].used == 0 &&
2400 hw->buffer_spec[i].vf_ref == 0 &&
2401 hw->buffer_spec[i].cma_alloc_addr) {
2402 return 1;
2403 }
2404 }
2405
2406 if (v4l2_m2m_num_dst_bufs_ready(v4l->m2m_ctx)
2407 >= run_ready_min_buf_num)
2408 return 1;
2409
2410 return 0;
2411 }
2412
2413 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2414 if (hw->mmu_enable)
2415 addr = hw->buffer_spec[i].alloc_header_addr;
2416 else
2417 addr = hw->buffer_spec[i].cma_alloc_addr;
2418 if (hw->buffer_spec[i].used == 0 &&
2419 hw->buffer_spec[i].vf_ref == 0) {
2420
2421 if (addr)
2422 return 1;
2423 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2424 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2425 index = i;
2426 }
2427 }
2428 if (addr)
2429 allocated_count++;
2430 }
2431 if (index >= 0) {
2432 mutex_lock(&vmh264_mutex);
2433 dealloc_buf_specs(hw, 0);
2434 if (max_alloc_buf_count == 0 ||
2435 allocated_count < max_alloc_buf_count) {
2436 if (alloc_one_buf_spec(hw, index) >= 0)
2437 ret = 1;
2438 }
2439 mutex_unlock(&vmh264_mutex);
2440 }
2441
2442 return ret;
2443}
2444
2445static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2446 int canvas_pos)
2447{
2448 int i;
2449 int j = 0;
2450 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2451 if (hw->buffer_spec[i].canvas_pos >= 0) {
2452 if (j == canvas_pos)
2453 return i;
2454 j++;
2455 }
2456 }
2457 return -1;
2458}
2459static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2460 struct vframe_s *vf, int index)
2461{
2462 if (index < 0) {
2463 vf->mem_handle = NULL;
2464 vf->mem_head_handle = NULL;
2465 } else if (vf->type & VIDTYPE_SCATTER) {
2466 vf->mem_handle =
2467 decoder_mmu_box_get_mem_handle(
2468 hw->mmu_box, index);
2469 vf->mem_head_handle =
2470 decoder_bmmu_box_get_mem_handle(
2471 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2472 } else {
2473 vf->mem_handle =
2474 decoder_bmmu_box_get_mem_handle(
2475 hw->bmmu_box, VF_BUFFER_IDX(index));
2476 /* vf->mem_head_handle =
2477 decoder_bmmu_box_get_mem_handle(
2478 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2479 }
2480 return;
2481}
2482static int check_force_interlace(struct vdec_h264_hw_s *hw,
2483 struct FrameStore *frame)
2484{
2485 int bForceInterlace = 0;
2486 /* no di in secure mode, disable force di */
2487 if (vdec_secure(hw_to_vdec(hw)))
2488 return 0;
2489 if (frame->frame) {
2490 if (frame->frame->coded_frame
2491 && !frame->frame->frame_mbs_only_flag) {
2492 if (frame->frame->structure == FRAME)
2493 return 1;
2494 }
2495 }
2496
2497 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2498 && hw->bitstream_restriction_flag
2499 && (hw->frame_width == 1920)
2500 && (hw->frame_height >= 1080)
2501 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2502 bForceInterlace = 1;
2503 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2504 && (hw->frame_width == 720)
2505 && (hw->frame_height == 576)
2506 && (hw->frame_dur == 3840)) {
2507 bForceInterlace = 1;
2508 }
2509
2510 return bForceInterlace;
2511}
2512
2513static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2514{
2515 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2516 if (frame->slice_type == I_SLICE)
2517 vframe_qos->type = 1;
2518 else if (frame->slice_type == P_SLICE)
2519 vframe_qos->type = 2;
2520 else if (frame->slice_type == B_SLICE)
2521 vframe_qos->type = 3;
2522
2523 vframe_qos->size = frame->frame_size;
2524 vframe_qos->pts = frame->pts64;
2525
2526 vframe_qos->max_mv = frame->max_mv;
2527 vframe_qos->avg_mv = frame->avg_mv;
2528 vframe_qos->min_mv = frame->min_mv;
2529/*
2530 pr_info("mv: max:%d, avg:%d, min:%d\n",
2531 vframe_qos->max_mv,
2532 vframe_qos->avg_mv,
2533 vframe_qos->min_mv);
2534*/
2535
2536 vframe_qos->max_qp = frame->max_qp;
2537 vframe_qos->avg_qp = frame->avg_qp;
2538 vframe_qos->min_qp = frame->min_qp;
2539/*
2540 pr_info("qp: max:%d, avg:%d, min:%d\n",
2541 vframe_qos->max_qp,
2542 vframe_qos->avg_qp,
2543 vframe_qos->min_qp);
2544*/
2545
2546 vframe_qos->max_skip = frame->max_skip;
2547 vframe_qos->avg_skip = frame->avg_skip;
2548 vframe_qos->min_skip = frame->min_skip;
2549/*
2550 pr_info("skip: max:%d, avg:%d, min:%d\n",
2551 vframe_qos->max_skip,
2552 vframe_qos->avg_skip,
2553 vframe_qos->min_skip);
2554*/
2555 vframe_qos->num++;
2556 if (hw->frameinfo_enable)
2557 vdec_fill_frame_info(vframe_qos, 1);
2558}
2559
2560static int is_iframe(struct FrameStore *frame) {
2561
2562 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2563 return 1;
2564 }
2565 return 0;
2566}
2567
2568
2569
2570int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2571{
2572 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2573 struct vframe_s *vf = NULL;
2574 int buffer_index = frame->buf_spec_num;
2575 int vf_count = 1;
2576 int i;
2577 int bForceInterlace = 0;
2578
2579 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2580 dpb_print(DECODE_ID(hw), 0,
2581 "%s, buffer_index 0x%x is beyond range\n",
2582 __func__, buffer_index);
2583 return -1;
2584 }
2585 if (force_disp_bufspec_num & 0x100) {
2586 /*recycle directly*/
2587 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2588 hw->buffer_spec[frame->buf_spec_num].used != 5)
2589 set_frame_output_flag(&hw->dpb, frame->index);
2590
2591 /*make pre_output not set*/
2592 return -1;
2593 }
2594 if (error_proc_policy & 0x1000) {
2595 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2596 int error_skip_frame_count = error_skip_count & 0xfff;
2597 if (((hw->no_error_count < error_skip_frame_count)
2598 && (error_skip_i_count == 0 ||
2599 hw->no_error_i_count < error_skip_i_count))
2600 && (!(frame->data_flag & I_FLAG)))
2601 frame->data_flag |= ERROR_FLAG;
2602 }
2603 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2604 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2605 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2606 frame->poc, hw->data_flag & ERROR_FLAG,
2607 error_proc_policy);
2608 if (frame->frame == NULL &&
2609 ((frame->is_used == 1 && frame->top_field)
2610 || (frame->is_used == 2 && frame->bottom_field))) {
2611 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2612 "%s Error frame_num %d used %d\n",
2613 __func__, frame->frame_num, frame->is_used);
2614 frame->data_flag |= ERROR_FLAG;
2615 }
2616 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2617 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2618 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2619 0, &frame->pts64) == 0)) {
2620 hw->last_pts64 = frame->pts64;
2621 hw->last_pts = frame->pts;
2622 } else {
2623 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2624 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2625 }
2626 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2627 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2628 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2629 frame->offset_delimiter, frame->pts,hw->last_pts,
2630 frame->pts64, hw->last_pts64, hw->frame_dur);
2631 hw->last_pts64 = frame->pts64;
2632 hw->last_pts = frame->pts;
2633 }
2634 if ((frame->data_flag & NODISP_FLAG) ||
2635 (frame->data_flag & NULL_FLAG) ||
2636 ((!hw->send_error_frame_flag) &&
2637 (frame->data_flag & ERROR_FLAG)) ||
2638 ((hw->i_only & 0x1) &&
2639 (!(frame->data_flag & I_FLAG)))
2640 ) {
2641 set_frame_output_flag(&hw->dpb, frame->index);
2642 return 0; /*do not return -1,
2643 otherwise flush_dpb() will not flush all dbp frames*/
2644 }
2645
2646 display_frame_count[DECODE_ID(hw)]++;
2647
2648 if (dpb_is_debug(DECODE_ID(hw),
2649 PRINT_FLAG_DPB_DETAIL)) {
2650 dpb_print(DECODE_ID(hw), 0,
2651 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2652 __func__, frame->index, frame->poc,
2653 frame->buf_spec_num);
2654 print_pic_info(DECODE_ID(hw), "predis_frm",
2655 frame->frame, -1);
2656 print_pic_info(DECODE_ID(hw), "predis_top",
2657 frame->top_field, -1);
2658 print_pic_info(DECODE_ID(hw), "predis_bot",
2659 frame->bottom_field, -1);
2660 }
2661
2662 if (!is_interlace(frame))
2663 vf_count = 1;
2664 else
2665 vf_count = 2;
2666 bForceInterlace = check_force_interlace(hw, frame);
2667 if (bForceInterlace)
2668 vf_count = 2;
2669 hw->buffer_spec[buffer_index].vf_ref = 0;
2670 fill_frame_info(hw, frame);
2671 for (i = 0; i < vf_count; i++) {
2672 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2673 vf == NULL) {
2674 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2675 "%s fatal error, no available buffer slot.\n",
2676 __func__);
2677 return -1;
2678 }
2679 vf->duration_pulldown = 0;
2680 if (!(is_iframe(frame)) && hw->unstable_pts) {
2681 vf->pts = 0;
2682 vf->pts_us64 = 0;
2683 vf->timestamp = 0;
2684 vf->index = VF_INDEX(frame->index, buffer_index);
2685 } else {
2686 vf->pts = frame->pts;
2687 vf->pts_us64 = frame->pts64;
2688 vf->timestamp = frame->timestamp;
2689 vf->index = VF_INDEX(frame->index, buffer_index);
2690 }
2691
2692 if (hw->is_used_v4l) {
2693 vf->v4l_mem_handle
2694 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2695 }
2696
2697 if (hw->mmu_enable) {
2698 if (hw->double_write_mode & 0x10) {
2699 /* double write only */
2700 vf->compBodyAddr = 0;
2701 vf->compHeadAddr = 0;
2702 } else {
2703 /*head adr*/
2704 vf->compHeadAddr =
2705 hw->buffer_spec[buffer_index].alloc_header_addr;
2706 /*body adr*/
2707 vf->compBodyAddr = 0;
2708 vf->canvas0Addr = vf->canvas1Addr = 0;
2709 }
2710
2711 vf->type = VIDTYPE_SCATTER;
2712
2713 if (hw->double_write_mode) {
2714 vf->type |= VIDTYPE_PROGRESSIVE
2715 | VIDTYPE_VIU_FIELD;
2716 vf->type |= VIDTYPE_VIU_NV21;
2717 if (hw->double_write_mode == 3)
2718 vf->type |= VIDTYPE_COMPRESS;
2719
2720 vf->canvas0Addr = vf->canvas1Addr = -1;
2721 vf->plane_num = 2;
2722 vf->canvas0_config[0] =
2723 hw->buffer_spec[buffer_index].
2724 canvas_config[0];
2725 vf->canvas0_config[1] =
2726 hw->buffer_spec[buffer_index].
2727 canvas_config[1];
2728
2729 vf->canvas1_config[0] =
2730 hw->buffer_spec[buffer_index].
2731 canvas_config[0];
2732 vf->canvas1_config[1] =
2733 hw->buffer_spec[buffer_index].
2734 canvas_config[1];
2735
2736 } else {
2737 vf->type |=
2738 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2739 vf->canvas0Addr = vf->canvas1Addr = 0;
2740 }
2741
2742 vf->bitdepth =
2743 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2744
2745 vf->compWidth = hw->frame_width;
2746 vf->compHeight = hw->frame_height;
2747 } else {
2748 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2749 VIDTYPE_VIU_NV21;
2750
2751 vf->canvas0Addr = vf->canvas1Addr =
2752 spec2canvas(&hw->buffer_spec[buffer_index]);
2753#ifdef VDEC_DW
2754 if (IS_VDEC_DW(hw))
2755 vf->canvas0Addr = vf->canvas1Addr =
2756 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2757#endif
2758
2759 }
2760 set_frame_info(hw, vf, buffer_index);
2761
2762 if (hw->mmu_enable && hw->double_write_mode) {
2763 vf->width = hw->frame_width /
2764 get_double_write_ratio(hw);
2765 vf->height = hw->frame_height /
2766 get_double_write_ratio(hw);
2767 }
2768
2769 vf->flag = 0;
2770 if (frame->data_flag & I_FLAG)
2771 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2772 if (frame->data_flag & ERROR_FLAG)
2773 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2774 update_vf_memhandle(hw, vf, buffer_index);
2775 hw->buffer_spec[buffer_index].used = 2;
2776 hw->buffer_spec[buffer_index].vf_ref++;
2777
2778 if (bForceInterlace || is_interlace(frame)) {
2779 vf->type =
2780 VIDTYPE_INTERLACE_FIRST |
2781 VIDTYPE_VIU_NV21;
2782
2783 if (bForceInterlace) {
2784 vf->type |= (i == 0 ?
2785 VIDTYPE_INTERLACE_TOP :
2786 VIDTYPE_INTERLACE_BOTTOM);
2787 if (i == 1) {
2788 vf->pts = 0;
2789 vf->pts_us64 = 0;
2790 }
2791 } else if (frame->top_field->poc <=
2792 frame->bottom_field->poc) /*top first*/
2793 vf->type |= (i == 0 ?
2794 VIDTYPE_INTERLACE_TOP :
2795 VIDTYPE_INTERLACE_BOTTOM);
2796 else
2797 vf->type |= (i == 0 ?
2798 VIDTYPE_INTERLACE_BOTTOM :
2799 VIDTYPE_INTERLACE_TOP);
2800 vf->duration = vf->duration/2;
2801 }
2802
2803 if (i == 0)
2804 decoder_do_frame_check(hw_to_vdec(hw), vf);
2805
2806 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2807 vf->sar_width = hw->width_aspect_ratio;
2808 vf->sar_height = hw->height_aspect_ratio;
2809
2810 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2811 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2812 hw->vf_pre_count++;
2813 vdec->vdec_fps_detec(vdec->id);
2814 if (without_display_mode == 0) {
2815 vf_notify_receiver(vdec->vf_provider_name,
2816 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2817 } else
2818 vh264_vf_put(vh264_vf_get(vdec), vdec);
2819 }
2820 if (dpb_is_debug(DECODE_ID(hw),
2821 PRINT_FLAG_DUMP_BUFSPEC))
2822 dump_bufspec(hw, __func__);
2823
2824 return 0;
2825}
2826
2827int notify_v4l_eos(struct vdec_s *vdec)
2828{
2829 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2830 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2831 struct vframe_s *vf = &hw->vframe_dummy;
2832 struct vdec_v4l2_buffer *fb = NULL;
2833 int index = INVALID_IDX;
2834 ulong expires;
2835
2836 if (hw->is_used_v4l && hw->eos) {
2837 expires = jiffies + msecs_to_jiffies(2000);
2838 while (INVALID_IDX == (index = v4l_get_free_buf_idx(vdec))) {
2839 if (time_after(jiffies, expires) ||
2840 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
2841 break;
2842 }
2843
2844 if (index == INVALID_IDX) {
2845 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2846 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2847 return -1;
2848 }
2849 }
2850
2851 vf->type |= VIDTYPE_V4L_EOS;
2852 vf->timestamp = ULONG_MAX;
2853 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2854 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2855 hw->buffer_spec[index].cma_alloc_addr;
2856
2857 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2858
2859 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2860 vf_notify_receiver(vdec->vf_provider_name,
2861 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2862
2863 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2864 }
2865
2866 return 0;
2867}
2868
2869/******************
2870 * Hardware config
2871 */
2872char *slice_type_name[] = {
2873 "P_SLICE ",
2874 "B_SLICE ",
2875 "I_SLICE ",
2876 "SP_SLICE",
2877 "SI_SLICE",
2878};
2879
2880char *picture_structure_name[] = {
2881 "FRAME",
2882 "TOP_FIELD",
2883 "BOTTOM_FIELD"
2884};
2885
2886void print_pic_info(int decindex, const char *info,
2887 struct StorablePicture *pic,
2888 int slice_type)
2889{
2890 if (pic)
2891 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2892 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2893 info,
2894 picture_structure_name[pic->structure],
2895 pic->coded_frame ? "Frame" : "Field",
2896 (slice_type < 0 ||
2897 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2898 pic->mb_aff_frame_flag,
2899 pic->poc,
2900 pic->pic_num,
2901 pic->buf_spec_num,
2902 pic->data_flag);
2903}
2904
2905static void reset_process_time(struct vdec_h264_hw_s *hw)
2906{
2907 if (hw->start_process_time) {
2908 unsigned process_time =
2909 1000 * (jiffies - hw->start_process_time) / HZ;
2910 hw->start_process_time = 0;
2911 if (process_time > max_process_time[DECODE_ID(hw)])
2912 max_process_time[DECODE_ID(hw)] = process_time;
2913 }
2914}
2915
2916static void start_process_time(struct vdec_h264_hw_s *hw)
2917{
2918 hw->decode_timeout_count = 10;
2919 hw->start_process_time = jiffies;
2920}
2921
2922static void config_aux_buf(struct vdec_h264_hw_s *hw)
2923{
2924 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2925 WRITE_VREG(H264_AUX_DATA_SIZE,
2926 ((hw->prefix_aux_size >> 4) << 16) |
2927 (hw->suffix_aux_size >> 4)
2928 );
2929}
2930
2931/*
2932* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2933*/
2934static void set_aux_data(struct vdec_h264_hw_s *hw,
2935 struct StorablePicture *pic, unsigned char suffix_flag,
2936 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2937{
2938 int i;
2939 unsigned short *aux_adr;
2940 unsigned size_reg_val =
2941 READ_VREG(H264_AUX_DATA_SIZE);
2942 unsigned aux_count = 0;
2943 int aux_size = 0;
2944 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2945 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2946 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2947 return;
2948
2949 if (suffix_flag) {
2950 aux_adr = (unsigned short *)
2951 (hw_buf->aux_addr +
2952 hw_buf->prefix_aux_size);
2953 aux_count =
2954 ((size_reg_val & 0xffff) << 4)
2955 >> 1;
2956 aux_size =
2957 hw_buf->suffix_aux_size;
2958 } else {
2959 aux_adr =
2960 (unsigned short *)hw_buf->aux_addr;
2961 aux_count =
2962 ((size_reg_val >> 16) << 4)
2963 >> 1;
2964 aux_size =
2965 hw_buf->prefix_aux_size;
2966 }
2967 if (dpb_is_debug(DECODE_ID(hw),
2968 PRINT_FLAG_DPB_DETAIL)) {
2969 dpb_print(DECODE_ID(hw), 0,
2970 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2971 __func__, AUX_DATA_SIZE(pic),
2972 aux_count, suffix_flag, dv_meta_flag);
2973 }
2974 if (aux_size > 0 && aux_count > 0) {
2975 int heads_size = 0;
2976 int new_size;
2977 char *new_buf;
2978 for (i = 0; i < aux_count; i++) {
2979 unsigned char tag = aux_adr[i] >> 8;
2980 if (tag != 0 && tag != 0xff) {
2981 if (dv_meta_flag == 0)
2982 heads_size += 8;
2983 else if (dv_meta_flag == 1 && tag == 0x1)
2984 heads_size += 8;
2985 else if (dv_meta_flag == 2 && tag != 0x1)
2986 heads_size += 8;
2987 }
2988 }
2989 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2990 new_buf = krealloc(AUX_DATA_BUF(pic),
2991 new_size,
2992 GFP_KERNEL);
2993 if (new_buf) {
2994 unsigned char valid_tag = 0;
2995 unsigned char *h =
2996 new_buf +
2997 AUX_DATA_SIZE(pic);
2998 unsigned char *p = h + 8;
2999 int len = 0;
3000 int padding_len = 0;
3001 AUX_DATA_BUF(pic) = new_buf;
3002 for (i = 0; i < aux_count; i += 4) {
3003 int ii;
3004 unsigned char tag = aux_adr[i + 3] >> 8;
3005 if (tag != 0 && tag != 0xff) {
3006 if (dv_meta_flag == 0)
3007 valid_tag = 1;
3008 else if (dv_meta_flag == 1
3009 && tag == 0x1)
3010 valid_tag = 1;
3011 else if (dv_meta_flag == 2
3012 && tag != 0x1)
3013 valid_tag = 1;
3014 else
3015 valid_tag = 0;
3016 if (valid_tag && len > 0) {
3017 AUX_DATA_SIZE(pic) +=
3018 (len + 8);
3019 h[0] =
3020 (len >> 24) & 0xff;
3021 h[1] =
3022 (len >> 16) & 0xff;
3023 h[2] =
3024 (len >> 8) & 0xff;
3025 h[3] =
3026 (len >> 0) & 0xff;
3027 h[6] =
3028 (padding_len >> 8)
3029 & 0xff;
3030 h[7] =
3031 (padding_len) & 0xff;
3032 h += (len + 8);
3033 p += 8;
3034 len = 0;
3035 padding_len = 0;
3036 }
3037 if (valid_tag) {
3038 h[4] = tag;
3039 h[5] = 0;
3040 h[6] = 0;
3041 h[7] = 0;
3042 }
3043 }
3044 if (valid_tag) {
3045 for (ii = 0; ii < 4; ii++) {
3046 unsigned short aa =
3047 aux_adr[i + 3
3048 - ii];
3049 *p = aa & 0xff;
3050 p++;
3051 len++;
3052 /*if ((aa >> 8) == 0xff)
3053 padding_len++;*/
3054 }
3055 }
3056 }
3057 if (len > 0) {
3058 AUX_DATA_SIZE(pic) += (len + 8);
3059 h[0] = (len >> 24) & 0xff;
3060 h[1] = (len >> 16) & 0xff;
3061 h[2] = (len >> 8) & 0xff;
3062 h[3] = (len >> 0) & 0xff;
3063 h[6] = (padding_len >> 8) & 0xff;
3064 h[7] = (padding_len) & 0xff;
3065 }
3066 if (dpb_is_debug(DECODE_ID(hw),
3067 PRINT_FLAG_DPB_DETAIL)) {
3068 dpb_print(DECODE_ID(hw), 0,
3069 "aux: (size %d) suffix_flag %d\n",
3070 AUX_DATA_SIZE(pic), suffix_flag);
3071 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
3072 dpb_print_cont(DECODE_ID(hw), 0,
3073 "%02x ", AUX_DATA_BUF(pic)[i]);
3074 if (((i + 1) & 0xf) == 0)
3075 dpb_print_cont(
3076 DECODE_ID(hw),
3077 0, "\n");
3078 }
3079 dpb_print_cont(DECODE_ID(hw),
3080 0, "\n");
3081 }
3082
3083 }
3084 }
3085
3086}
3087
3088static void release_aux_data(struct vdec_h264_hw_s *hw,
3089 int buf_spec_num)
3090{
3091 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3092 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3093 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3094}
3095
3096static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3097{
3098 int i;
3099 unsigned short *aux_adr =
3100 (unsigned short *)
3101 hw->aux_addr;
3102 unsigned aux_size =
3103 (READ_VREG(H264_AUX_DATA_SIZE)
3104 >> 16) << 4;
3105
3106 if (hw->prefix_aux_size > 0) {
3107 dpb_print(DECODE_ID(hw),
3108 0,
3109 "prefix aux: (size %d)\n",
3110 aux_size);
3111 for (i = 0; i <
3112 (aux_size >> 1); i++) {
3113 dpb_print_cont(DECODE_ID(hw),
3114 0,
3115 "%04x ",
3116 *(aux_adr + i));
3117 if (((i + 1) & 0xf)
3118 == 0)
3119 dpb_print_cont(
3120 DECODE_ID(hw),
3121 0, "\n");
3122 }
3123 }
3124 if (hw->suffix_aux_size > 0) {
3125 aux_adr = (unsigned short *)
3126 (hw->aux_addr +
3127 hw->prefix_aux_size);
3128 aux_size =
3129 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3130 << 4;
3131 dpb_print(DECODE_ID(hw),
3132 0,
3133 "suffix aux: (size %d)\n",
3134 aux_size);
3135 for (i = 0; i <
3136 (aux_size >> 1); i++) {
3137 dpb_print_cont(DECODE_ID(hw),
3138 0,
3139 "%04x ", *(aux_adr + i));
3140 if (((i + 1) & 0xf) == 0)
3141 dpb_print_cont(DECODE_ID(hw),
3142 0, "\n");
3143 }
3144 }
3145}
3146
3147static void config_decode_mode(struct vdec_h264_hw_s *hw)
3148{
3149#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3150 struct vdec_s *vdec = hw_to_vdec(hw);
3151#endif
3152 if (input_frame_based(hw_to_vdec(hw)))
3153 WRITE_VREG(H264_DECODE_MODE,
3154 DECODE_MODE_MULTI_FRAMEBASE);
3155#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3156 else if (vdec->slave)
3157 WRITE_VREG(H264_DECODE_MODE,
3158 (hw->got_valid_nal << 8) |
3159 DECODE_MODE_MULTI_DVBAL);
3160 else if (vdec->master)
3161 WRITE_VREG(H264_DECODE_MODE,
3162 (hw->got_valid_nal << 8) |
3163 DECODE_MODE_MULTI_DVENL);
3164#endif
3165 else
3166 WRITE_VREG(H264_DECODE_MODE,
3167 DECODE_MODE_MULTI_STREAMBASE);
3168 WRITE_VREG(H264_DECODE_SEQINFO,
3169 hw->seq_info2);
3170 WRITE_VREG(HEAD_PADING_REG, 0);
3171
3172 if (hw->init_flag == 0)
3173 WRITE_VREG(INIT_FLAG_REG, 0);
3174 else
3175 WRITE_VREG(INIT_FLAG_REG, 1);
3176}
3177int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3178{
3179 /* static int count = 0; */
3180 int ret = 0;
3181 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3182 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3183 unsigned int colocate_adr_offset;
3184 unsigned int val;
3185 struct StorablePicture *last_pic = hw->last_dec_picture;
3186
3187#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3188 int colocate_buf_index;
3189#endif
3190#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3191#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3192#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3193#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3194
3195#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3196/* bit 31:30 -- L1[0] picture coding structure,
3197 * 00 - top field, 01 - bottom field,
3198 * 10 - frame, 11 - mbaff frame
3199 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3200 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3201 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3202 */
3203#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3204
3205/* bit 15 -- flush co_mb_data to DDR -- W-Only
3206 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3207 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3208 * bit 9 -- soft_reset -- W-Only
3209 * bit 8 -- upgent
3210 * bit 7:2 -- h264_co_mb_mem_wr_addr
3211 * bit 1:0 -- h264_co_mb_info_wr_ptr
3212 */
3213#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3214
3215 unsigned long canvas_adr;
3216 unsigned int ref_reg_val;
3217 unsigned int one_ref_cfg = 0;
3218 int h264_buffer_info_data_write_count;
3219 int i, j;
3220 unsigned int colocate_wr_adr;
3221 unsigned int colocate_rd_adr;
3222 unsigned char use_direct_8x8;
3223 int canvas_pos;
3224 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3225 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3226 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3227 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3228 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3229
3230 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3231 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3232 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3233 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3234 canvas_pos);
3235 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3236
3237#ifdef VDEC_DW
3238 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3239 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3240 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3241#endif
3242 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3243 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3244
3245 if (!hw->mmu_enable) {
3246 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3247 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3248 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3249#ifdef VDEC_DW
3250 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3251 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3252 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3253#endif
3254 } else
3255 hevc_sao_set_pic_buffer(hw, pic);
3256
3257 if (pic->mb_aff_frame_flag)
3258 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3259 else if (pic->structure == TOP_FIELD)
3260 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3261 else if (pic->structure == BOTTOM_FIELD)
3262 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3263 else
3264 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3265
3266 if (pic->bottom_poc < pic->top_poc)
3267 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3268
3269 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3270 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3271 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3272
3273 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3274 int long_term_flag;
3275 i = get_buf_spec_by_canvas_pos(hw, j);
3276 if (i < 0)
3277 break;
3278 long_term_flag =
3279 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3280 if (long_term_flag > 0) {
3281 if (long_term_flag & 0x1)
3282 hw->buffer_spec[i].info0 |= (1 << 4);
3283 else
3284 hw->buffer_spec[i].info0 &= ~(1 << 4);
3285
3286 if (long_term_flag & 0x2)
3287 hw->buffer_spec[i].info0 |= (1 << 5);
3288 else
3289 hw->buffer_spec[i].info0 &= ~(1 << 5);
3290 }
3291
3292 if (i == pic->buf_spec_num)
3293 WRITE_VREG(H264_BUFFER_INFO_DATA,
3294 hw->buffer_spec[i].info0 | 0xf);
3295 else
3296 WRITE_VREG(H264_BUFFER_INFO_DATA,
3297 hw->buffer_spec[i].info0);
3298 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3299 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3300 }
3301
3302 /* config reference buffer */
3303 if (hw->mmu_enable) {
3304 hevc_mcr_config_mc_ref(hw);
3305 hevc_mcr_config_mcrcc(hw);
3306 }
3307
3308 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3309 "list0 size %d\n", pSlice->listXsize[0]);
3310 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3311 ref_reg_val = 0;
3312 j = 0;
3313 h264_buffer_info_data_write_count = 0;
3314
3315 //disable this read cache when frame width <= 64 (4MBs)
3316 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3317 if (hw->frame_width <= 64)
3318 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3319 else
3320 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3321
3322 if (last_pic)
3323 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3324 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3325 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3326 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3327 last_pic && (last_pic->data_flag & ERROR_FLAG)
3328 && (!(last_pic->slice_type == B_SLICE))
3329 && (!(pSlice->slice_type == I_SLICE))) {
3330 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3331 "no i/idr error mark\n");
3332 hw->data_flag |= ERROR_FLAG;
3333 pic->data_flag |= ERROR_FLAG;
3334 }
3335
3336 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3337 /*ref list 0 */
3338 struct StorablePicture *ref = pSlice->listX[0][i];
3339 unsigned int cfg;
3340 /* bit[6:5] - frame/field info,
3341 * 01 - top, 10 - bottom, 11 - frame
3342 */
3343 #ifdef ERROR_CHECK
3344 if (ref == NULL) {
3345 hw->data_flag |= ERROR_FLAG;
3346 pic->data_flag |= ERROR_FLAG;
3347 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3348 return -1;
3349 }
3350 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3351 hw->data_flag |= ERROR_FLAG;
3352 pic->data_flag |= ERROR_FLAG;
3353 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3354 }
3355 if (ref->data_flag & NULL_FLAG)
3356 hw->data_flag |= NULL_FLAG;
3357#endif
3358 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3359
3360 if (ref->structure == TOP_FIELD)
3361 cfg = 0x1;
3362 else if (ref->structure == BOTTOM_FIELD)
3363 cfg = 0x2;
3364 else /* FRAME */
3365 cfg = 0x3;
3366
3367 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3368 ref_reg_val <<= 8;
3369 ref_reg_val |= one_ref_cfg;
3370 j++;
3371
3372 if (j == 4) {
3373 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3374 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3375 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3376 h264_buffer_info_data_write_count++;
3377 j = 0;
3378 }
3379 print_pic_info(DECODE_ID(hw), "list0",
3380 pSlice->listX[0][i], -1);
3381 }
3382 if (j != 0) {
3383 while (j != 4) {
3384 ref_reg_val <<= 8;
3385 ref_reg_val |= one_ref_cfg;
3386 j++;
3387 }
3388 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3389 "H264_BUFFER_INFO_DATA: %x\n",
3390 ref_reg_val);
3391 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3392 h264_buffer_info_data_write_count++;
3393 }
3394 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3395 (one_ref_cfg << 8) | one_ref_cfg;
3396 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3397 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3398
3399 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3400 "list1 size %d\n", pSlice->listXsize[1]);
3401 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3402 ref_reg_val = 0;
3403 j = 0;
3404
3405 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3406 /* ref list 0 */
3407 struct StorablePicture *ref = pSlice->listX[1][i];
3408 unsigned int cfg;
3409 /* bit[6:5] - frame/field info,
3410 * 01 - top, 10 - bottom, 11 - frame
3411 */
3412
3413 #ifdef ERROR_CHECK
3414 if (ref == NULL) {
3415 hw->data_flag |= ERROR_FLAG;
3416 pic->data_flag |= ERROR_FLAG;
3417 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3418 return -2;
3419 }
3420 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3421 pic->data_flag |= ERROR_FLAG;
3422 hw->data_flag |= ERROR_FLAG;
3423 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3424 }
3425 if (ref->data_flag & NULL_FLAG)
3426 hw->data_flag |= NULL_FLAG;
3427#endif
3428 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3429 if (ref->structure == TOP_FIELD)
3430 cfg = 0x1;
3431 else if (ref->structure == BOTTOM_FIELD)
3432 cfg = 0x2;
3433 else /* FRAME */
3434 cfg = 0x3;
3435 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3436 ref_reg_val <<= 8;
3437 ref_reg_val |= one_ref_cfg;
3438 j++;
3439
3440 if (j == 4) {
3441 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3442 "H264_BUFFER_INFO_DATA: %x\n",
3443 ref_reg_val);
3444 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3445 j = 0;
3446 }
3447 print_pic_info(DECODE_ID(hw), "list1",
3448 pSlice->listX[1][i], -1);
3449 }
3450 if (j != 0) {
3451 while (j != 4) {
3452 ref_reg_val <<= 8;
3453 ref_reg_val |= one_ref_cfg;
3454 j++;
3455 }
3456 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3457 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3458 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3459 }
3460
3461 /* configure co-locate buffer */
3462 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3463 ;
3464 if ((pSlice->mode_8x8_flags & 0x4) &&
3465 (pSlice->mode_8x8_flags & 0x2))
3466 use_direct_8x8 = 1;
3467 else
3468 use_direct_8x8 = 0;
3469
3470#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3471 colocate_adr_offset =
3472 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3473 ? 1 : 2) * 96;
3474 if (use_direct_8x8)
3475 colocate_adr_offset >>= 2;
3476
3477 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3478 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3479 colocate_adr_offset, pSlice->first_mb_in_slice,
3480 colocate_adr_offset * pSlice->first_mb_in_slice);
3481
3482 colocate_adr_offset *= pSlice->first_mb_in_slice;
3483
3484 if ((pic->colocated_buf_index >= 0) &&
3485 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3486 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3487 ((p_H264_Dpb->colocated_buf_size *
3488 pic->colocated_buf_index)
3489 >> (use_direct_8x8 ? 2 : 0));
3490 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3491 p_H264_Dpb->colocated_mv_addr_end) {
3492 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3493 "Error, colocate buf is not enough, index is %d\n",
3494 pic->colocated_buf_index);
3495 ret = -3;
3496 }
3497 val = colocate_wr_adr + colocate_adr_offset;
3498 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3499 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3500 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3501 val, pSlice->first_mb_in_slice, pic->structure,
3502 colocate_adr_offset, pSlice->mode_8x8_flags,
3503 p_H264_Dpb->colocated_buf_size);
3504 } else {
3505 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3506 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3507 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3508 }
3509#else
3510 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3511 colocate_adr_offset =
3512 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3513 if (use_direct_8x8)
3514 colocate_adr_offset >>= 2;
3515
3516 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3517 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3518 colocate_adr_offset, pSlice->first_mb_in_slice,
3519 colocate_adr_offset * pSlice->first_mb_in_slice);
3520
3521 colocate_adr_offset *= pSlice->first_mb_in_slice;
3522
3523 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3524 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3525 (use_direct_8x8 ? 2 : 0));
3526
3527 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3528 p_H264_Dpb->colocated_mv_addr_end) {
3529 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3530 "Error, colocate buf is not enough, col buf index is %d\n",
3531 colocate_buf_index);
3532 ret = -4;
3533 }
3534 val = colocate_wr_adr + colocate_adr_offset;
3535 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3536 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3537 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3538 val, pSlice->first_mb_in_slice, pic->structure,
3539 colocate_adr_offset, pSlice->mode_8x8_flags,
3540 p_H264_Dpb->colocated_buf_size);
3541#endif
3542 if (pSlice->listXsize[1] > 0) {
3543 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3544 /* H264_CO_MB_RD_ADDR[bit 31:30],
3545 * original picture structure of L1[0],
3546 * 00 - top field, 01 - bottom field,
3547 * 10 - frame, 11 - mbaff frame
3548 */
3549 int l10_structure;
3550 int cur_colocate_ref_type;
3551 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3552 * 0 - top, 1 - bot
3553 */
3554 unsigned int val;
3555#ifdef ERROR_CHECK
3556 if (colocate_pic == NULL) {
3557 hw->data_flag |= ERROR_FLAG;
3558 pic->data_flag |= ERROR_FLAG;
3559 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3560 return -5;
3561 }
3562 if (colocate_pic->data_flag & ERROR_FLAG) {
3563 pic->data_flag |= ERROR_FLAG;
3564 hw->data_flag |= ERROR_FLAG;
3565 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3566 }
3567 if (colocate_pic->data_flag & NULL_FLAG)
3568 hw->data_flag |= NULL_FLAG;
3569#endif
3570
3571 if (colocate_pic->mb_aff_frame_flag)
3572 l10_structure = 3;
3573 else {
3574 if (colocate_pic->coded_frame)
3575 l10_structure = 2;
3576 else
3577 l10_structure = (colocate_pic->structure ==
3578 BOTTOM_FIELD) ? 1 : 0;
3579 }
3580#if 0
3581 /*case0016, p16,
3582 *cur_colocate_ref_type should be configured base on current pic
3583 */
3584 if (pic->structure == FRAME &&
3585 pic->mb_aff_frame_flag)
3586 cur_colocate_ref_type = 0;
3587 else if (pic->structure == BOTTOM_FIELD)
3588 cur_colocate_ref_type = 1;
3589 else
3590 cur_colocate_ref_type = 0;
3591#else
3592 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3593 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3594 pic->mb_aff_frame_flag,
3595 pic->structure,
3596 pic->coded_frame);
3597 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3598 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3599 colocate_pic->mb_aff_frame_flag,
3600 colocate_pic->structure,
3601 colocate_pic->coded_frame);
3602 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3603 cur_colocate_ref_type =
3604 (abs(pic->poc - colocate_pic->top_poc)
3605 < abs(pic->poc -
3606 colocate_pic->bottom_poc)) ? 0 : 1;
3607 } else
3608 cur_colocate_ref_type =
3609 (colocate_pic->structure
3610 == BOTTOM_FIELD) ? 1 : 0;
3611#endif
3612
3613#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3614 if ((colocate_pic->colocated_buf_index >= 0) &&
3615 (colocate_pic->colocated_buf_index <
3616 p_H264_Dpb->colocated_buf_count)) {
3617 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3618 ((p_H264_Dpb->colocated_buf_size *
3619 colocate_pic->colocated_buf_index)
3620 >> (use_direct_8x8 ? 2 : 0));
3621 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3622 p_H264_Dpb->colocated_mv_addr_end) {
3623 dpb_print(DECODE_ID(hw),
3624 PRINT_FLAG_ERROR,
3625 "Error, colocate buf is not enough, index is %d\n",
3626 colocate_pic->colocated_buf_index);
3627 ret = -6;
3628 }
3629 /* bit 31:30 -- L1[0] picture coding structure,
3630 * 00 - top field, 01 - bottom field,
3631 * 10 - frame, 11 - mbaff frame
3632 * bit 29 - L1[0] top/bot for B field pciture,
3633 * 0 - top, 1 - bot
3634 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3635 * -- only used for B Picture Direct mode
3636 * [2:0] will set to 3'b000
3637 */
3638 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3639 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3640 (l10_structure << 30) |
3641 (cur_colocate_ref_type << 29);
3642 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3643 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3644 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3645 colocate_pic->colocated_buf_index,
3646 val, colocate_rd_adr + colocate_adr_offset,
3647 colocate_pic->structure,
3648 colocate_pic->mb_aff_frame_flag);
3649 } else {
3650 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3651 "Error, reference pic has no colocated buf\n");
3652 ret = -7;
3653 }
3654#else
3655 colocate_buf_index =
3656 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3657 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3658 ((p_H264_Dpb->colocated_buf_size *
3659 colocate_buf_index)
3660 >> (use_direct_8x8 ? 2 : 0));
3661 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3662 p_H264_Dpb->colocated_mv_addr_end) {
3663 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3664 "Error, colocate buf is not enough, col buf index is %d\n",
3665 colocate_buf_index);
3666 ret = -8;
3667 }
3668 /* bit 31:30 -- L1[0] picture coding structure,
3669 * 00 - top field, 01 - bottom field,
3670 * 10 - frame, 11 - mbaff frame
3671 * bit 29 - L1[0] top/bot for B field pciture,
3672 * 0 - top, 1 - bot
3673 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3674 * -- only used for B Picture Direct mode
3675 * [2:0] will set to 3'b000
3676 */
3677 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3678 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3679 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3680 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3681 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3682 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3683 val, colocate_pic->structure,
3684 colocate_pic->mb_aff_frame_flag);
3685#endif
3686 }
3687 return ret;
3688}
3689
3690static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3691{
3692 unsigned long flags;
3693 struct vdec_s *vdec = op_arg;
3694 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3695
3696 spin_lock_irqsave(&hw->lock, flags);
3697
3698 states->vf_pool_size = VF_POOL_SIZE;
3699 states->buf_free_num = kfifo_len(&hw->newframe_q);
3700 states->buf_avail_num = kfifo_len(&hw->display_q);
3701
3702 spin_unlock_irqrestore(&hw->lock, flags);
3703
3704 return 0;
3705}
3706
3707static struct vframe_s *vh264_vf_peek(void *op_arg)
3708{
3709 struct vframe_s *vf[2] = {0, 0};
3710 struct vdec_s *vdec = op_arg;
3711 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3712
3713 if (!hw)
3714 return NULL;
3715
3716 if (force_disp_bufspec_num & 0x100) {
3717 if (force_disp_bufspec_num & 0x200)
3718 return NULL;
3719 return &hw->vframe_dummy;
3720 }
3721
3722 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3723 if (vf[1]) {
3724 vf[0]->next_vf_pts_valid = true;
3725 vf[0]->next_vf_pts = vf[1]->pts;
3726 } else
3727 vf[0]->next_vf_pts_valid = false;
3728 return vf[0];
3729 }
3730
3731 return NULL;
3732}
3733
3734static struct vframe_s *vh264_vf_get(void *op_arg)
3735{
3736 struct vframe_s *vf;
3737 struct vdec_s *vdec = op_arg;
3738 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3739
3740 if (!hw)
3741 return NULL;
3742
3743 if (force_disp_bufspec_num & 0x100) {
3744 int buffer_index = force_disp_bufspec_num & 0xff;
3745 if (force_disp_bufspec_num & 0x200)
3746 return NULL;
3747
3748 vf = &hw->vframe_dummy;
3749 vf->duration_pulldown = 0;
3750 vf->pts = 0;
3751 vf->pts_us64 = 0;
3752 set_frame_info(hw, vf, buffer_index);
3753 vf->flag = 0;
3754 if (hw->mmu_enable) {
3755 if (hw->double_write_mode & 0x10) {
3756 /* double write only */
3757 vf->compBodyAddr = 0;
3758 vf->compHeadAddr = 0;
3759 } else {
3760 /*head adr*/
3761 vf->compHeadAddr =
3762 hw->buffer_spec[buffer_index].alloc_header_addr;
3763 /*body adr*/
3764 vf->compBodyAddr = 0;
3765 vf->canvas0Addr = vf->canvas1Addr = 0;
3766 }
3767
3768 vf->type = VIDTYPE_SCATTER;
3769
3770 if (hw->double_write_mode) {
3771 vf->type |= VIDTYPE_PROGRESSIVE
3772 | VIDTYPE_VIU_FIELD;
3773 vf->type |= VIDTYPE_VIU_NV21;
3774 if (hw->double_write_mode == 3)
3775 vf->type |= VIDTYPE_COMPRESS;
3776
3777 vf->canvas0Addr = vf->canvas1Addr = -1;
3778 vf->plane_num = 2;
3779 vf->canvas0_config[0] =
3780 hw->buffer_spec[buffer_index].
3781 canvas_config[0];
3782 vf->canvas0_config[1] =
3783 hw->buffer_spec[buffer_index].
3784 canvas_config[1];
3785
3786 vf->canvas1_config[0] =
3787 hw->buffer_spec[buffer_index].
3788 canvas_config[0];
3789 vf->canvas1_config[1] =
3790 hw->buffer_spec[buffer_index].
3791 canvas_config[1];
3792 } else {
3793 vf->type |=
3794 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3795 vf->canvas0Addr = vf->canvas1Addr = 0;
3796 }
3797 vf->bitdepth =
3798 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3799
3800 vf->compWidth = hw->frame_width;
3801 vf->compHeight = hw->frame_height;
3802
3803 if (hw->double_write_mode) {
3804 vf->width = hw->frame_width /
3805 get_double_write_ratio(hw);
3806 vf->height = hw->frame_height /
3807 get_double_write_ratio(hw);
3808 }
3809 } else {
3810 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3811 VIDTYPE_VIU_NV21;
3812 vf->canvas0Addr = vf->canvas1Addr =
3813 spec2canvas(&hw->buffer_spec[buffer_index]);
3814 }
3815
3816 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3817 hw->bmmu_box, buffer_index);*/
3818 update_vf_memhandle(hw, vf, buffer_index);
3819 force_disp_bufspec_num |= 0x200;
3820 return vf;
3821 }
3822
3823 if (kfifo_get(&hw->display_q, &vf)) {
3824 int time = jiffies;
3825 unsigned int frame_interval =
3826 1000*(time - hw->last_frame_time)/HZ;
3827 struct vframe_s *next_vf;
3828 if (dpb_is_debug(DECODE_ID(hw),
3829 PRINT_FLAG_VDEC_DETAIL)) {
3830 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3831 int frame_index = FRAME_INDEX(vf->index);
3832 if (frame_index < 0 ||
3833 frame_index >= DPB_SIZE_MAX) {
3834 dpb_print(DECODE_ID(hw), 0,
3835 "%s vf index 0x%x error\r\n",
3836 __func__, vf->index);
3837 } else {
3838 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3839 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3840 __func__, BUFSPEC_INDEX(vf->index), vf,
3841 p_H264_Dpb->mFrameStore[frame_index].poc,
3842 vf->duration, vf->pts, frame_interval);
3843 }
3844 }
3845 if (hw->last_frame_time > 0) {
3846 if (frame_interval >
3847 max_get_frame_interval[DECODE_ID(hw)])
3848 max_get_frame_interval[DECODE_ID(hw)]
3849 = frame_interval;
3850 }
3851 hw->last_frame_time = time;
3852 vf->index_disp = hw->vf_get_count;
3853 hw->vf_get_count++;
3854 if (kfifo_peek(&hw->display_q, &next_vf)) {
3855 vf->next_vf_pts_valid = true;
3856 vf->next_vf_pts = next_vf->pts;
3857 } else
3858 vf->next_vf_pts_valid = false;
3859 return vf;
3860 }
3861
3862 return NULL;
3863}
3864
3865static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3866{
3867 struct vdec_s *vdec = op_arg;
3868 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3869 unsigned long flags;
3870 int buf_spec_num;
3871 int frame_index;
3872
3873 if (vf == (&hw->vframe_dummy))
3874 return;
3875 if (vf->index == -1) {
3876 dpb_print(DECODE_ID(hw), 0,
3877 "Warning: %s vf %p invalid index\r\n",
3878 __func__, vf);
3879 return;
3880 }
3881 frame_index = FRAME_INDEX(vf->index);
3882 buf_spec_num = BUFSPEC_INDEX(vf->index);
3883 if (frame_index < 0 ||
3884 frame_index >= DPB_SIZE_MAX ||
3885 buf_spec_num < 0 ||
3886 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3887 dpb_print(DECODE_ID(hw), 0,
3888 "%s vf index 0x%x error\r\n",
3889 __func__, vf->index);
3890 return;
3891 }
3892 /*get_buf_spec_idx_by_canvas_config(hw,
3893 &vf->canvas0_config[0]);*/
3894 spin_lock_irqsave(&hw->bufspec_lock, flags);
3895 if (hw->buffer_spec[buf_spec_num].used == 2) {
3896 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3897 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3898 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3899 __func__, vf, frame_index,
3900 p_H264_Dpb->mFrameStore[frame_index].poc,
3901 buf_spec_num,
3902 hw->buffer_spec[buf_spec_num].used,
3903 hw->buffer_spec[buf_spec_num].vf_ref);
3904 hw->buffer_spec[buf_spec_num].vf_ref--;
3905 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3906 set_frame_output_flag(&hw->dpb, frame_index);
3907 } else {
3908 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3909 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3910 __func__, vf, buf_spec_num,
3911 hw->buffer_spec[buf_spec_num].used,
3912 hw->buffer_spec[buf_spec_num].vf_ref);
3913 hw->buffer_spec[buf_spec_num].vf_ref--;
3914 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3915 if (hw->buffer_spec[buf_spec_num].used == 3)
3916 hw->buffer_spec[buf_spec_num].used = 4;
3917 else if (hw->buffer_spec[buf_spec_num].used == 5)
3918 hw->buffer_spec[buf_spec_num].used = 0;
3919 }
3920 if (dpb_is_debug(DECODE_ID(hw),
3921 PRINT_FLAG_DUMP_BUFSPEC))
3922 dump_bufspec(hw, __func__);
3923
3924 }
3925 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3926
3927 hw->vf_put_count++;
3928 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3929
3930#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3931 if (hw->buffer_empty_flag)
3932 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3933}
3934
3935static int vh264_event_cb(int type, void *data, void *op_arg)
3936{
3937 unsigned long flags;
3938 struct vdec_s *vdec = op_arg;
3939 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3940
3941 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3942 struct provider_aux_req_s *req =
3943 (struct provider_aux_req_s *)data;
3944 int buf_spec_num;
3945
3946 if (!req->vf) {
3947 req->aux_size = hw->vf_put_count;
3948 return 0;
3949 }
3950 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3951 spin_lock_irqsave(&hw->lock, flags);
3952 req->aux_buf = NULL;
3953 req->aux_size = 0;
3954 if (buf_spec_num >= 0 &&
3955 buf_spec_num < BUFSPEC_POOL_SIZE &&
3956 is_buf_spec_in_disp_q(hw, buf_spec_num)
3957 ) {
3958 req->aux_buf =
3959 hw->buffer_spec[buf_spec_num].aux_data_buf;
3960 req->aux_size =
3961 hw->buffer_spec[buf_spec_num].aux_data_size;
3962#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3963 req->dv_enhance_exist =
3964 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3965#else
3966 req->dv_enhance_exist = 0;
3967#endif
3968 }
3969 spin_unlock_irqrestore(&hw->lock, flags);
3970
3971 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3972 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3973 __func__, type, buf_spec_num, req->aux_size);
3974 }
3975
3976 return 0;
3977}
3978
3979static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3980 u32 index)
3981{
3982 struct canvas_config_s *p_canvas_config;
3983 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3984 force_rate_framebase : force_rate_streambase;
3985 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3986 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3987 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3988
3989 /* signal_type */
3990 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3991 vf->signal_type = hw->video_signal_from_vui;
3992 if (hw->is_used_v4l) {
3993 struct aml_vdec_hdr_infos hdr;
3994 struct aml_vcodec_ctx *ctx =
3995 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3996
3997 memset(&hdr, 0, sizeof(hdr));
3998 hdr.signal_type = hw->video_signal_from_vui;
3999 vdec_v4l_set_hdr_infos(ctx, &hdr);
4000 }
4001 } else
4002 vf->signal_type = 0;
4003
4004 vf->width = hw->frame_width;
4005 vf->height = hw->frame_height;
4006 if (force_rate) {
4007 if (force_rate == -1)
4008 vf->duration = 0;
4009 else
4010 vf->duration = 96000/force_rate;
4011 } else
4012 vf->duration = hw->frame_dur;
4013 vf->ratio_control =
4014 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
4015 DISP_RATIO_ASPECT_RATIO_BIT;
4016 vf->orientation = hw->vh264_rotation;
4017
4018 if (hw->mmu_enable)
4019 return;
4020
4021 vf->canvas0Addr = vf->canvas1Addr = -1;
4022#ifdef NV21
4023 vf->plane_num = 2;
4024#else
4025 vf->plane_num = 3;
4026#endif
4027
4028 if (IS_VDEC_DW(hw)) {
4029 vf->width = (hw->frame_width /2);
4030 if (IS_VDEC_DW(hw) == 2)
4031 vf->height = (hw->frame_height /2);
4032 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
4033 } else
4034 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
4035
4036 vf->canvas0_config[0] = p_canvas_config[0];
4037 vf->canvas0_config[1] = p_canvas_config[1];
4038#ifndef NV21
4039 vf->canvas0_config[2] = p_canvas_config[2];
4040#endif
4041 vf->canvas1_config[0] = p_canvas_config[0];
4042 vf->canvas1_config[1] = p_canvas_config[1];
4043#ifndef NV21
4044 vf->canvas1_config[2] = p_canvas_config[2];
4045#endif
4046}
4047
4048static void get_picture_qos_info(struct StorablePicture *picture)
4049{
4050 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
4051 unsigned char a[3];
4052 unsigned char i, j, t;
4053 unsigned long data;
4054
4055 get_random_bytes(&data, sizeof(unsigned long));
4056 if (picture->slice_type == I_SLICE)
4057 data = 0;
4058 a[0] = data & 0xff;
4059 a[1] = (data >> 8) & 0xff;
4060 a[2] = (data >> 16) & 0xff;
4061
4062 for (i = 0; i < 3; i++)
4063 for (j = i+1; j < 3; j++) {
4064 if (a[j] < a[i]) {
4065 t = a[j];
4066 a[j] = a[i];
4067 a[i] = t;
4068 } else if (a[j] == a[i]) {
4069 a[i]++;
4070 t = a[j];
4071 a[j] = a[i];
4072 a[i] = t;
4073 }
4074 }
4075 picture->max_mv = a[2];
4076 picture->avg_mv = a[1];
4077 picture->min_mv = a[0];
4078 /*
4079 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
4080 data, a[0], a[1], a[2]);
4081 */
4082
4083 get_random_bytes(&data, sizeof(unsigned long));
4084 a[0] = data & 0x1f;
4085 a[1] = (data >> 8) & 0x3f;
4086 a[2] = (data >> 16) & 0x7f;
4087
4088 for (i = 0; i < 3; i++)
4089 for (j = i+1; j < 3; j++) {
4090 if (a[j] < a[i]) {
4091 t = a[j];
4092 a[j] = a[i];
4093 a[i] = t;
4094 } else if (a[j] == a[i]) {
4095 a[i]++;
4096 t = a[j];
4097 a[j] = a[i];
4098 a[i] = t;
4099 }
4100 }
4101 picture->max_qp = a[2];
4102 picture->avg_qp = a[1];
4103 picture->min_qp = a[0];
4104 /*
4105 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4106 data, a[0], a[1], a[2]);
4107 */
4108
4109 get_random_bytes(&data, sizeof(unsigned long));
4110 a[0] = data & 0x1f;
4111 a[1] = (data >> 8) & 0x3f;
4112 a[2] = (data >> 16) & 0x7f;
4113
4114 for (i = 0; i < 3; i++)
4115 for (j = i+1; j < 3; j++) {
4116 if (a[j] < a[i]) {
4117 t = a[j];
4118 a[j] = a[i];
4119 a[i] = t;
4120 } else if (a[j] == a[i]) {
4121 a[i]++;
4122 t = a[j];
4123 a[j] = a[i];
4124 a[i] = t;
4125 }
4126 }
4127 picture->max_skip = a[2];
4128 picture->avg_skip = a[1];
4129 picture->min_skip = a[0];
4130
4131
4132 /*
4133 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4134 data,a[0], a[1], a[2]);
4135 */
4136 } else {
4137 uint32_t blk88_y_count;
4138 uint32_t blk88_c_count;
4139 uint32_t blk22_mv_count;
4140 uint32_t rdata32;
4141 int32_t mv_hi;
4142 int32_t mv_lo;
4143 uint32_t rdata32_l;
4144 uint32_t mvx_L0_hi;
4145 uint32_t mvy_L0_hi;
4146 uint32_t mvx_L1_hi;
4147 uint32_t mvy_L1_hi;
4148 int64_t value;
4149 uint64_t temp_value;
4150/*
4151#define DEBUG_QOS
4152*/
4153#ifdef DEBUG_QOS
4154 int pic_number = picture->poc;
4155#endif
4156
4157 picture->max_mv = 0;
4158 picture->avg_mv = 0;
4159 picture->min_mv = 0;
4160
4161 picture->max_skip = 0;
4162 picture->avg_skip = 0;
4163 picture->min_skip = 0;
4164
4165 picture->max_qp = 0;
4166 picture->avg_qp = 0;
4167 picture->min_qp = 0;
4168
4169
4170
4171
4172
4173 /* set rd_idx to 0 */
4174 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4175 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4176 if (blk88_y_count == 0) {
4177#ifdef DEBUG_QOS
4178 pr_info(" [Picture %d Quality] NO Data yet.\n",
4179 pic_number);
4180#endif
4181 /* reset all counts */
4182 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4183 return;
4184 }
4185 /* qp_y_sum */
4186 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4187#ifdef DEBUG_QOS
4188 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4189 pic_number, rdata32/blk88_y_count,
4190 rdata32, blk88_y_count);
4191#endif
4192 picture->avg_qp = rdata32/blk88_y_count;
4193 /* intra_y_count */
4194 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4195#ifdef DEBUG_QOS
4196 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4197 pic_number, rdata32*100/blk88_y_count,
4198 '%', rdata32);
4199#endif
4200 /* skipped_y_count */
4201 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4202#ifdef DEBUG_QOS
4203 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4204 pic_number, rdata32*100/blk88_y_count,
4205 '%', rdata32);
4206#endif
4207 picture->avg_skip = rdata32*100/blk88_y_count;
4208 /* coeff_non_zero_y_count */
4209 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4210#ifdef DEBUG_QOS
4211 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4212 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4213 '%', rdata32);
4214#endif
4215 /* blk66_c_count */
4216 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4217 if (blk88_c_count == 0) {
4218#ifdef DEBUG_QOS
4219 pr_info(" [Picture %d Quality] NO Data yet.\n",
4220 pic_number);
4221#endif
4222 /* reset all counts */
4223 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4224 return;
4225 }
4226 /* qp_c_sum */
4227 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4228#ifdef DEBUG_QOS
4229 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4230 pic_number, rdata32/blk88_c_count,
4231 rdata32, blk88_c_count);
4232#endif
4233 /* intra_c_count */
4234 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4235#ifdef DEBUG_QOS
4236 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4237 pic_number, rdata32*100/blk88_c_count,
4238 '%', rdata32);
4239#endif
4240 /* skipped_cu_c_count */
4241 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4242#ifdef DEBUG_QOS
4243 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4244 pic_number, rdata32*100/blk88_c_count,
4245 '%', rdata32);
4246#endif
4247 /* coeff_non_zero_c_count */
4248 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4249#ifdef DEBUG_QOS
4250 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4251 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4252 '%', rdata32);
4253#endif
4254
4255 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4256 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4257 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4258#ifdef DEBUG_QOS
4259 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4260 pic_number, (rdata32>>0)&0xff);
4261#endif
4262 picture->min_qp = (rdata32>>0)&0xff;
4263
4264#ifdef DEBUG_QOS
4265 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4266 pic_number, (rdata32>>8)&0xff);
4267#endif
4268 picture->max_qp = (rdata32>>8)&0xff;
4269
4270#ifdef DEBUG_QOS
4271 pr_info(" [Picture %d Quality] C QP min : %d\n",
4272 pic_number, (rdata32>>16)&0xff);
4273 pr_info(" [Picture %d Quality] C QP max : %d\n",
4274 pic_number, (rdata32>>24)&0xff);
4275#endif
4276
4277 /* blk22_mv_count */
4278 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4279 if (blk22_mv_count == 0) {
4280#ifdef DEBUG_QOS
4281 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4282 pic_number);
4283#endif
4284 /* reset all counts */
4285 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4286 return;
4287 }
4288 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4289 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4290 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4291 /* should all be 0x00 or 0xff */
4292#ifdef DEBUG_QOS
4293 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4294 pic_number, rdata32);
4295#endif
4296 mvx_L0_hi = ((rdata32>>0)&0xff);
4297 mvy_L0_hi = ((rdata32>>8)&0xff);
4298 mvx_L1_hi = ((rdata32>>16)&0xff);
4299 mvy_L1_hi = ((rdata32>>24)&0xff);
4300
4301 /* mvx_L0_count[31:0] */
4302 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4303 temp_value = mvx_L0_hi;
4304 temp_value = (temp_value << 32) | rdata32_l;
4305
4306 if (mvx_L0_hi & 0x80)
4307 value = 0xFFFFFFF000000000 | temp_value;
4308 else
4309 value = temp_value;
4310 value = div_s64(value, blk22_mv_count);
4311#ifdef DEBUG_QOS
4312 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4313 pic_number, (int)(value),
4314 value, blk22_mv_count);
4315#endif
4316 picture->avg_mv = value;
4317
4318 /* mvy_L0_count[31:0] */
4319 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4320 temp_value = mvy_L0_hi;
4321 temp_value = (temp_value << 32) | rdata32_l;
4322
4323 if (mvy_L0_hi & 0x80)
4324 value = 0xFFFFFFF000000000 | temp_value;
4325 else
4326 value = temp_value;
4327#ifdef DEBUG_QOS
4328 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4329 pic_number, rdata32_l/blk22_mv_count,
4330 value, blk22_mv_count);
4331#endif
4332
4333 /* mvx_L1_count[31:0] */
4334 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4335 temp_value = mvx_L1_hi;
4336 temp_value = (temp_value << 32) | rdata32_l;
4337 if (mvx_L1_hi & 0x80)
4338 value = 0xFFFFFFF000000000 | temp_value;
4339 else
4340 value = temp_value;
4341#ifdef DEBUG_QOS
4342 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4343 pic_number, rdata32_l/blk22_mv_count,
4344 value, blk22_mv_count);
4345#endif
4346
4347 /* mvy_L1_count[31:0] */
4348 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4349 temp_value = mvy_L1_hi;
4350 temp_value = (temp_value << 32) | rdata32_l;
4351 if (mvy_L1_hi & 0x80)
4352 value = 0xFFFFFFF000000000 | temp_value;
4353 else
4354 value = temp_value;
4355#ifdef DEBUG_QOS
4356 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4357 pic_number, rdata32_l/blk22_mv_count,
4358 value, blk22_mv_count);
4359#endif
4360
4361 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4362 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4363 mv_hi = (rdata32>>16)&0xffff;
4364 if (mv_hi & 0x8000)
4365 mv_hi = 0x8000 - mv_hi;
4366#ifdef DEBUG_QOS
4367 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4368 pic_number, mv_hi);
4369#endif
4370 picture->max_mv = mv_hi;
4371
4372 mv_lo = (rdata32>>0)&0xffff;
4373 if (mv_lo & 0x8000)
4374 mv_lo = 0x8000 - mv_lo;
4375#ifdef DEBUG_QOS
4376 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4377 pic_number, mv_lo);
4378#endif
4379 picture->min_mv = mv_lo;
4380
4381 /* {mvy_L0_max, mvy_L0_min} */
4382 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4383 mv_hi = (rdata32>>16)&0xffff;
4384 if (mv_hi & 0x8000)
4385 mv_hi = 0x8000 - mv_hi;
4386#ifdef DEBUG_QOS
4387 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4388 pic_number, mv_hi);
4389#endif
4390
4391 mv_lo = (rdata32>>0)&0xffff;
4392 if (mv_lo & 0x8000)
4393 mv_lo = 0x8000 - mv_lo;
4394#ifdef DEBUG_QOS
4395 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4396 pic_number, mv_lo);
4397#endif
4398
4399 /* {mvx_L1_max, mvx_L1_min} */
4400 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4401 mv_hi = (rdata32>>16)&0xffff;
4402 if (mv_hi & 0x8000)
4403 mv_hi = 0x8000 - mv_hi;
4404#ifdef DEBUG_QOS
4405 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4406 pic_number, mv_hi);
4407#endif
4408
4409 mv_lo = (rdata32>>0)&0xffff;
4410 if (mv_lo & 0x8000)
4411 mv_lo = 0x8000 - mv_lo;
4412#ifdef DEBUG_QOS
4413 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4414 pic_number, mv_lo);
4415#endif
4416
4417 /* {mvy_L1_max, mvy_L1_min} */
4418 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4419 mv_hi = (rdata32>>16)&0xffff;
4420 if (mv_hi & 0x8000)
4421 mv_hi = 0x8000 - mv_hi;
4422#ifdef DEBUG_QOS
4423 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4424 pic_number, mv_hi);
4425#endif
4426 mv_lo = (rdata32>>0)&0xffff;
4427 if (mv_lo & 0x8000)
4428 mv_lo = 0x8000 - mv_lo;
4429#ifdef DEBUG_QOS
4430 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4431 pic_number, mv_lo);
4432#endif
4433
4434 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4435#ifdef DEBUG_QOS
4436 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4437 pic_number, rdata32);
4438#endif
4439 /* reset all counts */
4440 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4441 }
4442}
4443
4444static int get_max_dec_frame_buf_size(int level_idc,
4445 int max_reference_frame_num, int mb_width,
4446 int mb_height)
4447{
4448 int pic_size = mb_width * mb_height * 384;
4449
4450 int size = 0;
4451
4452 switch (level_idc) {
4453 case 9:
4454 size = 152064;
4455 break;
4456 case 10:
4457 size = 152064;
4458 break;
4459 case 11:
4460 size = 345600;
4461 break;
4462 case 12:
4463 size = 912384;
4464 break;
4465 case 13:
4466 size = 912384;
4467 break;
4468 case 20:
4469 size = 912384;
4470 break;
4471 case 21:
4472 size = 1824768;
4473 break;
4474 case 22:
4475 size = 3110400;
4476 break;
4477 case 30:
4478 size = 3110400;
4479 break;
4480 case 31:
4481 size = 6912000;
4482 break;
4483 case 32:
4484 size = 7864320;
4485 break;
4486 case 40:
4487 size = 12582912;
4488 break;
4489 case 41:
4490 size = 12582912;
4491 break;
4492 case 42:
4493 size = 13369344;
4494 break;
4495 case 50:
4496 size = 42393600;
4497 break;
4498 case 51:
4499 case 52:
4500 default:
4501 size = 70778880;
4502 break;
4503 }
4504
4505 size /= pic_size;
4506 size = size + 1; /* need one more buffer */
4507
4508 if (max_reference_frame_num > size)
4509 size = max_reference_frame_num;
4510 size = imin(size, 16);
4511
4512 return size;
4513}
4514
4515static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4516{
4517 int i, j;
4518
4519 if (hw->double_write_mode) {
4520 mutex_lock(&vmh264_mutex);
4521 if (hw->decode_pic_count == 0) {
4522 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4523 i = get_buf_spec_by_canvas_pos(hw, j);
4524 if (i >= 0)
4525 config_decode_canvas_ex(hw, i);
4526 }
4527 }
4528 mutex_unlock(&vmh264_mutex);
4529 }
4530}
4531
4532static int vh264_set_params(struct vdec_h264_hw_s *hw,
4533 u32 param1, u32 param2, u32 param3, u32 param4)
4534{
4535 int i, j;
4536 int mb_width, mb_total;
4537 int max_reference_size, level_idc;
4538 int mb_height = 0;
4539 unsigned long flags;
4540 /*int mb_mv_byte;*/
4541 struct vdec_s *vdec = hw_to_vdec(hw);
4542 u32 seq_info2;
4543 int ret = 0;
4544 int active_buffer_spec_num;
4545 unsigned int buf_size;
4546 unsigned int frame_mbs_only_flag;
4547 unsigned int chroma_format_idc, chroma444;
4548 unsigned int crop_infor, crop_bottom, crop_right;
4549 unsigned int used_reorder_dpb_size_margin
4550 = hw->reorder_dpb_size_margin;
4551 u8 *colocate_vaddr = NULL;
4552
4553#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4554 if (vdec->master || vdec->slave)
4555 used_reorder_dpb_size_margin =
4556 reorder_dpb_size_margin_dv;
4557#endif
4558 seq_info2 = param1;
4559 hw->seq_info = param2;
4560
4561 mb_width = seq_info2 & 0xff;
4562 mb_total = (seq_info2 >> 8) & 0xffff;
4563 if (!mb_width && mb_total) /*for 4k2k*/
4564 mb_width = 256;
4565 if (mb_width)
4566 mb_height = mb_total/mb_width;
4567 if (mb_width <= 0 || mb_height <= 0 ||
4568 is_oversize(mb_width << 4, mb_height << 4)) {
4569 dpb_print(DECODE_ID(hw), 0,
4570 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4571 seq_info2,
4572 mb_width,
4573 mb_height);
4574 return -1;
4575 }
4576
4577 if (seq_info2 != 0 &&
4578 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4579 hw->seq_info2 != 0
4580 ) /*picture size changed*/
4581 h264_reconfig(hw);
4582
4583 if (hw->config_bufmgr_done == 0) {
4584 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4585 u32 reg_val;
4586 hw->cfg_param1 = param1;
4587 hw->cfg_param2 = param2;
4588 hw->cfg_param3 = param3;
4589 hw->cfg_param4 = param4;
4590
4591 hw->seq_info2 = seq_info2 & (~0x80000000);
4592 dpb_print(DECODE_ID(hw), 0,
4593 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4594 seq_info2, hw->seq_info);
4595
4596 dpb_init_global(&hw->dpb,
4597 DECODE_ID(hw), 0, 0);
4598
4599 p_H264_Dpb->fast_output_enable = fast_output_enable;
4600 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4601
4602#if 1
4603 /*crop*/
4604 /* AV_SCRATCH_2
4605 bit 15: frame_mbs_only_flag
4606 bit 13-14: chroma_format_idc */
4607 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4608 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4609 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4610
4611 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4612 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4613 (2 - frame_mbs_only_flag) */
4614 crop_infor = param3;
4615 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4616 crop_right = ((crop_infor >> 16) & 0xff)
4617 >> (2 - frame_mbs_only_flag);
4618
4619 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4620 hw->frame_width = mb_width << 4;
4621 hw->frame_height = mb_height << 4;
4622 if (frame_mbs_only_flag) {
4623 hw->frame_height =
4624 hw->frame_height - (2 >> chroma444) *
4625 min(crop_bottom,
4626 (unsigned int)((8 << chroma444) - 1));
4627 hw->frame_width =
4628 hw->frame_width -
4629 (2 >> chroma444) * min(crop_right,
4630 (unsigned
4631 int)((8 << chroma444) - 1));
4632 } else {
4633 hw->frame_height =
4634 hw->frame_height - (4 >> chroma444) *
4635 min(crop_bottom,
4636 (unsigned int)((8 << chroma444)
4637 - 1));
4638 hw->frame_width =
4639 hw->frame_width -
4640 (4 >> chroma444) * min(crop_right,
4641 (unsigned int)((8 << chroma444) - 1));
4642 }
4643 dpb_print(DECODE_ID(hw), 0,
4644 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4645 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4646 dpb_print(DECODE_ID(hw), 0,
4647 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4648 mb_height, crop_right,
4649 hw->frame_width, mb_width);
4650
4651 if (hw->frame_height == 1088)
4652 hw->frame_height = 1080;
4653#endif
4654 if (!hw->mmu_enable) {
4655 mb_width = (mb_width+3) & 0xfffffffc;
4656 mb_height = (mb_height+3) & 0xfffffffc;
4657 }
4658 mb_total = mb_width * mb_height;
4659 hw->mb_width = mb_width;
4660 hw->mb_height = mb_height;
4661 hw->mb_total = mb_total;
4662 if (hw->mmu_enable)
4663 hevc_mcr_sao_global_hw_init(hw,
4664 (hw->mb_width << 4), (hw->mb_height << 4));
4665
4666 reg_val = param4;
4667 level_idc = reg_val & 0xff;
4668 max_reference_size = (reg_val >> 8) & 0xff;
4669 hw->dpb.origin_max_reference = max_reference_size;
4670 dpb_print(DECODE_ID(hw), 0,
4671 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4672 mb_height, mb_width, mb_total,
4673 level_idc, max_reference_size);
4674
4675
4676 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4677 hw->dpb.reorder_pic_num =
4678 get_max_dec_frame_buf_size(level_idc,
4679 max_reference_size, mb_width, mb_height);
4680
4681 dpb_print(DECODE_ID(hw), 0,
4682 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4683 hw->bitstream_restriction_flag,
4684 hw->max_dec_frame_buffering,
4685 hw->dpb.reorder_pic_num);
4686
4687 if ((hw->bitstream_restriction_flag) &&
4688 (hw->max_dec_frame_buffering <
4689 hw->dpb.reorder_pic_num)) {
4690 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4691 dpb_print(DECODE_ID(hw), 0,
4692 "set reorder_pic_num to %d\n",
4693 hw->dpb.reorder_pic_num);
4694 }
4695
4696 active_buffer_spec_num =
4697 hw->dpb.reorder_pic_num
4698 + used_reorder_dpb_size_margin;
4699 hw->max_reference_size =
4700 max_reference_size + reference_buf_margin;
4701
4702 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4703 active_buffer_spec_num = MAX_VF_BUF_NUM;
4704 hw->dpb.reorder_pic_num = active_buffer_spec_num
4705 - used_reorder_dpb_size_margin;
4706 }
4707 hw->dpb.mDPB.size = active_buffer_spec_num;
4708 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4709 hw->max_reference_size = MAX_VF_BUF_NUM;
4710 hw->dpb.max_reference_size = hw->max_reference_size;
4711
4712 if (hw->no_poc_reorder_flag)
4713 hw->dpb.reorder_pic_num = 1;
4714 dpb_print(DECODE_ID(hw), 0,
4715 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4716 __func__, active_buffer_spec_num,
4717 hw->dpb.reorder_pic_num,
4718 hw->max_reference_size);
4719
4720 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4721
4722 mutex_lock(&vmh264_mutex);
4723 if (!hw->mmu_enable) {
4724 config_buf_specs(vdec);
4725 i = get_buf_spec_by_canvas_pos(hw, 0);
4726
4727 if (hw->is_used_v4l) {
4728 if (i != -1) {
4729 pr_info("v4l: delay alloc the buffer.\n");
4730 }
4731 } else {
4732 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4733 config_decode_canvas(hw, i);
4734 else
4735 ret = -1;
4736 }
4737 } else {
4738 if (hw->double_write_mode) {
4739 config_buf_specs_ex(vdec);
4740 } else {
4741 spin_lock_irqsave(&hw->bufspec_lock, flags);
4742 for (i = 0, j = 0;
4743 j < active_buffer_spec_num
4744 && i < BUFSPEC_POOL_SIZE;
4745 i++) {
4746 if (hw->buffer_spec[i].used != -1)
4747 continue;
4748 hw->buffer_spec[i].used = 0;
4749 hw->buffer_spec[i].
4750 alloc_header_addr = 0;
4751 hw->buffer_spec[i].canvas_pos = j;
4752 j++;
4753 }
4754 spin_unlock_irqrestore(&hw->bufspec_lock,
4755 flags);
4756 }
4757 hevc_mcr_config_canv2axitbl(hw, 0);
4758 }
4759 mutex_unlock(&vmh264_mutex);
4760 if (dpb_is_debug(DECODE_ID(hw),
4761 PRINT_FLAG_DUMP_BUFSPEC))
4762 dump_bufspec(hw, __func__);
4763
4764#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4765 buf_size = PAGE_ALIGN(
4766 p_H264_Dpb->colocated_buf_size *
4767 active_buffer_spec_num);
4768#else
4769 buf_size = PAGE_ALIGN(
4770 p_H264_Dpb->colocated_buf_size *
4771 hw->max_reference_size);
4772#endif
4773
4774 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4775 buf_size, DRIVER_NAME,
4776 &hw->collocate_cma_alloc_addr) < 0)
4777 return -1;
4778 if (!vdec_secure(vdec)) {
4779 /* clear for some mosaic problem after reset bufmgr */
4780 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4781 if (colocate_vaddr != NULL) {
4782 memset(colocate_vaddr, 0, buf_size);
4783 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4784 codec_mm_unmap_phyaddr(colocate_vaddr);
4785 }
4786 }
4787
4788 hw->dpb.colocated_mv_addr_start =
4789 hw->collocate_cma_alloc_addr;
4790#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4791 hw->dpb.colocated_mv_addr_end =
4792 hw->dpb.colocated_mv_addr_start +
4793 (p_H264_Dpb->colocated_buf_size *
4794 active_buffer_spec_num);
4795#else
4796 hw->dpb.colocated_mv_addr_end =
4797 hw->dpb.colocated_mv_addr_start +
4798 (p_H264_Dpb->colocated_buf_size *
4799 hw->max_reference_size);
4800#endif
4801 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4802 "callocate cma, %lx, %x\n",
4803 hw->collocate_cma_alloc_addr,
4804 hw->dpb.colocated_mv_addr_start);
4805
4806 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4807 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4808 hw->dpb.colocated_mv_addr_start,
4809 hw->dpb.colocated_mv_addr_end);
4810 if (!hw->mmu_enable) {
4811 mutex_lock(&vmh264_mutex);
4812 if (ret >= 0 && hw->decode_pic_count == 0) {
4813 int buf_cnt;
4814 /* h264_reconfig: alloc later*/
4815 buf_cnt = hw->dpb.mDPB.size;
4816
4817 for (j = 1; j < buf_cnt; j++) {
4818 i = get_buf_spec_by_canvas_pos(hw, j);
4819
4820 if (hw->is_used_v4l) {
4821 pr_info("v4l: delay alloc the buffer.\n");
4822 break;
4823 } else if (alloc_one_buf_spec(hw, i) < 0)
4824 break;
4825
4826 config_decode_canvas(hw, i);
4827 }
4828 }
4829 mutex_unlock(&vmh264_mutex);
4830 } else {
4831 vh264_config_canvs_for_mmu(hw);
4832 }
4833
4834 hw->config_bufmgr_done = 1;
4835
4836 /*end of config_bufmgr_done */
4837 }
4838
4839 return ret;
4840}
4841
4842static void vui_config(struct vdec_h264_hw_s *hw)
4843{
4844 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4845 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4846 /*time*/
4847 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4848 hw->time_scale = p_H264_Dpb->time_scale;
4849 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4850
4851 hw->bitstream_restriction_flag =
4852 p_H264_Dpb->bitstream_restriction_flag;
4853 hw->num_reorder_frames =
4854 p_H264_Dpb->num_reorder_frames;
4855 hw->max_dec_frame_buffering =
4856 p_H264_Dpb->max_dec_frame_buffering;
4857
4858 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4859 "vui_config: pdb %d, %d, %d\n",
4860 p_H264_Dpb->bitstream_restriction_flag,
4861 p_H264_Dpb->num_reorder_frames,
4862 p_H264_Dpb->max_dec_frame_buffering);
4863
4864 hw->fixed_frame_rate_flag = 0;
4865 if (hw->timing_info_present_flag) {
4866 hw->fixed_frame_rate_flag =
4867 p_H264_Dpb->fixed_frame_rate_flag;
4868
4869 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4870 ((!hw->sync_outside) ||
4871 (!hw->frame_dur)))
4872 && hw->num_units_in_tick && hw->time_scale) {
4873 if (hw->use_idr_framerate ||
4874 hw->fixed_frame_rate_flag ||
4875 !hw->frame_dur ||
4876 !hw->duration_from_pts_done
4877 /*|| vh264_running*/) {
4878 u32 frame_dur_es =
4879 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4880 hw->time_scale);
4881 if (hw->frame_dur != frame_dur_es) {
4882 hw->h264_first_valid_pts_ready = false;
4883 hw->h264pts1 = 0;
4884 hw->h264pts2 = 0;
4885 hw->h264_pts_count = 0;
4886 hw->duration_from_pts_done = 0;
4887 fixed_frame_rate_mode =
4888 FIX_FRAME_RATE_OFF;
4889 hw->pts_duration = 0;
4890 hw->frame_dur = frame_dur_es;
4891 vdec_schedule_work(&hw->notify_work);
4892 dpb_print(DECODE_ID(hw),
4893 PRINT_FLAG_DEC_DETAIL,
4894 "frame_dur %d from timing_info\n",
4895 hw->frame_dur);
4896 }
4897
4898 /*hack to avoid use ES frame duration when
4899 *it's half of the rate from system info
4900 * sometimes the encoder is given a wrong
4901 * frame rate but the system side information
4902 * is more reliable
4903 *if ((frame_dur * 2) != frame_dur_es) {
4904 * frame_dur = frame_dur_es;
4905 *}
4906 */
4907 }
4908 }
4909 } else {
4910 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4911 "H.264: timing_info not present\n");
4912 }
4913
4914 /*aspect ratio*/
4915 aspect_ratio_info_present_flag =
4916 p_H264_Dpb->vui_status & 0x1;
4917 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4918
4919 if (aspect_ratio_info_present_flag) {
4920 if (aspect_ratio_idc == EXTEND_SAR) {
4921 hw->h264_ar = 0x3ff;
4922 hw->height_aspect_ratio =
4923 p_H264_Dpb->aspect_ratio_sar_height;
4924 hw->width_aspect_ratio =
4925 p_H264_Dpb->aspect_ratio_sar_width;
4926 } else {
4927 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4928 aspect_ratio_idc); */
4929
4930 switch (aspect_ratio_idc) {
4931 case 1:
4932 hw->h264_ar = 0x3ff;
4933 hw->height_aspect_ratio = 1;
4934 hw->width_aspect_ratio = 1;
4935 break;
4936 case 2:
4937 hw->h264_ar = 0x3ff;
4938 hw->height_aspect_ratio = 11;
4939 hw->width_aspect_ratio = 12;
4940 break;
4941 case 3:
4942 hw->h264_ar = 0x3ff;
4943 hw->height_aspect_ratio = 11;
4944 hw->width_aspect_ratio = 10;
4945 break;
4946 case 4:
4947 hw->h264_ar = 0x3ff;
4948 hw->height_aspect_ratio = 11;
4949 hw->width_aspect_ratio = 16;
4950 break;
4951 case 5:
4952 hw->h264_ar = 0x3ff;
4953 hw->height_aspect_ratio = 33;
4954 hw->width_aspect_ratio = 40;
4955 break;
4956 case 6:
4957 hw->h264_ar = 0x3ff;
4958 hw->height_aspect_ratio = 11;
4959 hw->width_aspect_ratio = 24;
4960 break;
4961 case 7:
4962 hw->h264_ar = 0x3ff;
4963 hw->height_aspect_ratio = 11;
4964 hw->width_aspect_ratio = 20;
4965 break;
4966 case 8:
4967 hw->h264_ar = 0x3ff;
4968 hw->height_aspect_ratio = 11;
4969 hw->width_aspect_ratio = 32;
4970 break;
4971 case 9:
4972 hw->h264_ar = 0x3ff;
4973 hw->height_aspect_ratio = 33;
4974 hw->width_aspect_ratio = 80;
4975 break;
4976 case 10:
4977 hw->h264_ar = 0x3ff;
4978 hw->height_aspect_ratio = 11;
4979 hw->width_aspect_ratio = 18;
4980 break;
4981 case 11:
4982 hw->h264_ar = 0x3ff;
4983 hw->height_aspect_ratio = 11;
4984 hw->width_aspect_ratio = 15;
4985 break;
4986 case 12:
4987 hw->h264_ar = 0x3ff;
4988 hw->height_aspect_ratio = 33;
4989 hw->width_aspect_ratio = 64;
4990 break;
4991 case 13:
4992 hw->h264_ar = 0x3ff;
4993 hw->height_aspect_ratio = 99;
4994 hw->width_aspect_ratio = 160;
4995 break;
4996 case 14:
4997 hw->h264_ar = 0x3ff;
4998 hw->height_aspect_ratio = 3;
4999 hw->width_aspect_ratio = 4;
5000 break;
5001 case 15:
5002 hw->h264_ar = 0x3ff;
5003 hw->height_aspect_ratio = 2;
5004 hw->width_aspect_ratio = 3;
5005 break;
5006 case 16:
5007 hw->h264_ar = 0x3ff;
5008 hw->height_aspect_ratio = 1;
5009 hw->width_aspect_ratio = 2;
5010 break;
5011 default:
5012 if (hw->vh264_ratio >> 16) {
5013 hw->h264_ar = (hw->frame_height *
5014 (hw->vh264_ratio & 0xffff) *
5015 0x100 +
5016 ((hw->vh264_ratio >> 16) *
5017 hw->frame_width / 2)) /
5018 ((hw->vh264_ratio >> 16) *
5019 hw->frame_width);
5020 hw->height_aspect_ratio = 1;
5021 hw->width_aspect_ratio = 1;
5022 } else {
5023 hw->h264_ar = 0x3ff;
5024 hw->height_aspect_ratio = 1;
5025 hw->width_aspect_ratio = 1;
5026 }
5027 break;
5028 }
5029 }
5030 } else {
5031 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5032 "v264dec: aspect_ratio not available from source\n");
5033 if (hw->vh264_ratio >> 16) {
5034 /* high 16 bit is width, low 16 bit is height */
5035 hw->h264_ar =
5036 ((hw->vh264_ratio & 0xffff) *
5037 hw->frame_height * 0x100 +
5038 (hw->vh264_ratio >> 16) *
5039 hw->frame_width / 2) /
5040 ((hw->vh264_ratio >> 16) *
5041 hw->frame_width);
5042 hw->height_aspect_ratio = 1;
5043 hw->width_aspect_ratio = 1;
5044 } else {
5045 hw->h264_ar = 0x3ff;
5046 hw->height_aspect_ratio = 1;
5047 hw->width_aspect_ratio = 1;
5048 }
5049 }
5050
5051 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
5052 if (((hw->frame_dur == RATE_2397_FPS)
5053 && (dec_control
5054 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
5055 || ((RATE_2997_FPS ==
5056 hw->frame_dur) &&
5057 (dec_control &
5058 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
5059 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
5060 "force fix frame rate\n");
5061 hw->fixed_frame_rate_flag = 0x40;
5062 }
5063 }
5064
5065 /*video_signal_from_vui: to do .. */
5066}
5067
5068static void bufmgr_recover(struct vdec_h264_hw_s *hw)
5069{
5070 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5071
5072 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5073 if (error_proc_policy & 0x20) {
5074 if (!hw->is_used_v4l)
5075 hw->reset_bufmgr_flag = 1;
5076 }
5077}
5078
5079void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
5080{
5081 struct vdec_h264_hw_s *hw =
5082 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
5083
5084 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5085
5086 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5087 hw->reset_bufmgr_flag = 1;
5088}
5089
5090#ifdef CONSTRAIN_MAX_BUF_NUM
5091static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5092{
5093 int i;
5094 int count = 0;
5095 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5096 if (is_buf_spec_in_disp_q(hw, i) &&
5097 hw->buffer_spec[i].vf_ref > 0)
5098 count++;
5099 }
5100 return count;
5101}
5102
5103static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5104{
5105 int i;
5106 int count = 0;
5107 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5108 if (is_buf_spec_in_use(hw, i))
5109 count++;
5110 }
5111 return count;
5112}
5113#endif
5114
5115
5116static bool is_buffer_available(struct vdec_s *vdec)
5117{
5118 bool buffer_available = 1;
5119 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5120 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5121 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5122 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5123 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5124 ((p_H264_Dpb->mDPB.init_done) &&
5125 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5126 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5127 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5128 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5129 __func__,
5130 kfifo_len(&hw->newframe_q),
5131 have_free_buf_spec(vdec),
5132 p_H264_Dpb->mDPB.init_done,
5133 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5134 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5135 );
5136 buffer_available = 0;
5137 if (dpb_is_debug(DECODE_ID(hw),
5138 DEBUG_DISABLE_RUNREADY_RMBUF))
5139 return buffer_available;
5140
5141 if ((error_proc_policy & 0x4) &&
5142 (error_proc_policy & 0x8)) {
5143 if ((kfifo_len(&hw->display_q) <= 0) &&
5144 (p_H264_Dpb->mDPB.used_size ==
5145 p_H264_Dpb->mDPB.size) &&
5146 (p_Dpb->ref_frames_in_buffer >
5147 (imax(
5148 1, p_Dpb->num_ref_frames)
5149 - p_Dpb->ltref_frames_in_buffer +
5150 force_sliding_margin)))
5151 bufmgr_recover(hw);
5152 else
5153 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5154 } else if ((error_proc_policy & 0x4) &&
5155 (kfifo_len(&hw->display_q) <= 0) &&
5156 ((p_H264_Dpb->mDPB.used_size ==
5157 p_H264_Dpb->mDPB.size) ||
5158 (!have_free_buf_spec(vdec)))) {
5159 enum receviver_start_e state = RECEIVER_INACTIVE;
5160 if ((error_proc_policy & 0x10) &&
5161 vf_get_receiver(vdec->vf_provider_name)) {
5162 state =
5163 vf_notify_receiver(vdec->vf_provider_name,
5164 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5165 NULL);
5166 if ((state == RECEIVER_STATE_NULL)
5167 || (state == RECEIVER_STATE_NONE))
5168 state = RECEIVER_INACTIVE;
5169 }
5170 if (state == RECEIVER_INACTIVE)
5171 bufmgr_recover(hw);
5172 else
5173 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5174 } else if ((error_proc_policy & 0x8) &&
5175 (p_Dpb->ref_frames_in_buffer >
5176 (imax(
5177 1, p_Dpb->num_ref_frames)
5178 - p_Dpb->ltref_frames_in_buffer +
5179 force_sliding_margin)))
5180 bufmgr_recover(hw);
5181 else
5182 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5183
5184 if (hw->reset_bufmgr_flag == 1)
5185 buffer_available = 1;
5186 else if (hw->is_used_v4l)
5187 buffer_available = have_free_buf_spec(vdec);
5188 }
5189
5190 return buffer_available;
5191}
5192
5193#define AUX_TAG_SEI 0x2
5194
5195#define SEI_BUFFERING_PERIOD 0
5196#define SEI_PicTiming 1
5197#define SEI_USER_DATA 4
5198#define SEI_RECOVERY_POINT 6
5199
5200/*
5201 *************************************************************************
5202 * Function:Reads bits from the bitstream buffer
5203 * Input:
5204 byte buffer[]
5205 containing sei message data bits
5206 int totbitoffset
5207 bit offset from start of partition
5208 int bytecount
5209 total bytes in bitstream
5210 int numbits
5211 number of bits to read
5212 * Output:
5213 int *info
5214 * Return:
5215 -1: failed
5216 > 0: the count of bit read
5217 * Attention:
5218 *************************************************************************
5219 */
5220
5221static int get_bits(unsigned char buffer[],
5222 int totbitoffset,
5223 int *info,
5224 int bytecount,
5225 int numbits)
5226{
5227 register int inf;
5228 long byteoffset;
5229 int bitoffset;
5230
5231 int bitcounter = numbits;
5232
5233 byteoffset = totbitoffset / 8;
5234 bitoffset = 7 - (totbitoffset % 8);
5235
5236 inf = 0;
5237 while (numbits) {
5238 inf <<= 1;
5239 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5240 numbits--;
5241 bitoffset--;
5242 if (bitoffset < 0) {
5243 byteoffset++;
5244 bitoffset += 8;
5245 if (byteoffset > bytecount)
5246 return -1;
5247 }
5248 }
5249
5250 *info = inf;
5251
5252
5253 return bitcounter;
5254}
5255
5256static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5257 u8 *sei_data_buf,
5258 u8 *sei_data_buf_end)
5259{
5260 int payload_type;
5261 int payload_size;
5262 u8 *p_sei;
5263 int temp = 0;
5264 int bit_offset;
5265 int read_size;
5266 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5267
5268 p_sei = sei_data_buf;
5269 read_size = 0;
5270 payload_type = 0;
5271 do {
5272 if (p_sei >= sei_data_buf_end)
5273 return read_size;
5274
5275 payload_type += *p_sei;
5276 read_size++;
5277 } while (*p_sei++ == 255);
5278
5279
5280 payload_size = 0;
5281 do {
5282 if (p_sei >= sei_data_buf_end)
5283 return read_size;
5284
5285 payload_size += *p_sei;
5286 read_size++;
5287 } while (*p_sei++ == 255);
5288
5289
5290 if (p_sei + payload_size > sei_data_buf_end) {
5291 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5292 "%s: payload_type = %d, payload_size = %d is over\n",
5293 __func__, payload_type, payload_size);
5294 return read_size;
5295 }
5296 bit_offset = 0;
5297
5298 if (payload_size <= 0) {
5299 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5300 "%s warning: this is a null sei message for payload_type = %d\n",
5301 __func__, payload_type);
5302 return read_size;
5303 }
5304 switch (payload_type) {
5305 case SEI_BUFFERING_PERIOD:
5306 break;
5307 case SEI_PicTiming:
5308 if (p_H264_Dpb->vui_status & 0xc) {
5309 int cpb_removal_delay;
5310 int dpb_output_delay;
5311 u32 delay_len;
5312
5313 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5314 cpb_removal_delay
5315 = (delay_len & 0x1F) + 1;
5316 dpb_output_delay
5317 = ((delay_len >> 5) & 0x1F) + 1;
5318
5319 get_bits(p_sei, bit_offset,
5320 &temp, payload_size,
5321 dpb_output_delay+cpb_removal_delay);
5322 bit_offset += dpb_output_delay+cpb_removal_delay;
5323 }
5324 if (p_H264_Dpb->vui_status & 0x10) {
5325 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5326 bit_offset += 4;
5327 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5328 }
5329 break;
5330 case SEI_USER_DATA:
5331 if (enable_itu_t35) {
5332 int i;
5333 int j;
5334 int data_len;
5335 u8 *user_data_buf;
5336
5337 user_data_buf
5338 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5339 /* user data length should be align with 8 bytes,
5340 if not, then padding with zero*/
5341 for (i = 0; i < payload_size; i += 8) {
5342 for (j = 0; j < 8; j++) {
5343 int index;
5344
5345 index = i+7-j;
5346 if (index >= payload_size)
5347 user_data_buf[i+j] = 0;
5348 else
5349 user_data_buf[i+j]
5350 = p_sei[i+7-j];
5351 }
5352 }
5353
5354 data_len = payload_size;
5355 if (payload_size % 8)
5356 data_len = ((payload_size + 8) >> 3) << 3;
5357
5358 hw->sei_itu_data_len += data_len;
5359 /*
5360 dpb_print(DECODE_ID(hw), 0,
5361 "%s: user data, and len = %d:\n",
5362 __func__, hw->sei_itu_data_len);
5363 */
5364 }
5365 break;
5366 case SEI_RECOVERY_POINT:
5367 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5368 break;
5369 }
5370
5371 return read_size + payload_size;
5372}
5373
5374static void parse_sei_data(struct vdec_h264_hw_s *hw,
5375 u8 *sei_data_buf,
5376 int len)
5377{
5378 char *p_sei;
5379 char *p_sei_end;
5380 int parsed_size;
5381 int read_size;
5382
5383
5384 p_sei = sei_data_buf;
5385 p_sei_end = p_sei + len;
5386 parsed_size = 0;
5387 while (parsed_size < len) {
5388 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5389 p_sei += read_size;
5390 parsed_size += read_size;
5391 if (*p_sei == 0x80) {
5392 p_sei++;
5393 parsed_size++;
5394 }
5395 }
5396}
5397
5398static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5399{
5400 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5401 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5402 unsigned mby_mbx = READ_VREG(MBY_MBX);
5403 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5404 unsigned decode_mb_count =
5405 ((mby_mbx & 0xff) * hw->mb_width +
5406 (((mby_mbx >> 8) & 0xff) + 1));
5407 if (mby_mbx == 0)
5408 return;
5409 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5410 mb_total /= 2;
5411 if (error_proc_policy & 0x100) {
5412 if (decode_mb_count < mb_total)
5413 p->data_flag |= ERROR_FLAG;
5414 }
5415
5416 if ((error_proc_policy & 0x200) &&
5417 READ_VREG(ERROR_STATUS_REG) != 0) {
5418 p->data_flag |= ERROR_FLAG;
5419 }
5420
5421 if (p->data_flag & ERROR_FLAG) {
5422 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5423 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5424 __func__,
5425 hw->seq_info2,
5426 mby_mbx,
5427 mb_total,
5428 decode_mb_count,
5429 READ_VREG(ERROR_STATUS_REG)
5430 );
5431
5432 }
5433}
5434
5435static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5436{
5437 int i;
5438 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5439 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5440 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5441 u32 debug_tag;
5442 int ret;
5443
5444 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5445#if 1
5446 unsigned short *p = (unsigned short *)hw->lmem_addr;
5447 dma_sync_single_for_cpu(
5448 amports_get_dma_device(),
5449 hw->lmem_addr_remap,
5450 PAGE_SIZE,
5451 DMA_FROM_DEVICE);
5452 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5453 int ii;
5454 for (ii = 0; ii < 4; ii++) {
5455 p_H264_Dpb->dpb_param.l.data[i+ii] =
5456 p[i+3-ii];
5457 if (dpb_is_debug(DECODE_ID(hw),
5458 RRINT_FLAG_RPM)) {
5459 if (((i + ii) & 0xf) == 0)
5460 dpb_print(DECODE_ID(hw),
5461 0, "%04x:",
5462 i);
5463 dpb_print_cont(DECODE_ID(hw),
5464 0, "%04x ",
5465 p[i+3-ii]);
5466 if (((i + ii + 1) & 0xf) == 0)
5467 dpb_print_cont(
5468 DECODE_ID(hw),
5469 0, "\r\n");
5470 }
5471 }
5472 }
5473
5474 p_H264_Dpb->bitstream_restriction_flag =
5475 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5476 p_H264_Dpb->num_reorder_frames =
5477 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5478 p_H264_Dpb->max_dec_frame_buffering =
5479 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5480
5481 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5482 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5483 p_H264_Dpb->bitstream_restriction_flag,
5484 p_H264_Dpb->num_reorder_frames,
5485 p_H264_Dpb->max_dec_frame_buffering);
5486 hw->bitstream_restriction_flag =
5487 p_H264_Dpb->bitstream_restriction_flag;
5488 hw->num_reorder_frames =
5489 p_H264_Dpb->num_reorder_frames;
5490 hw->max_dec_frame_buffering =
5491 p_H264_Dpb->max_dec_frame_buffering;
5492#endif
5493
5494 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5495 reset_process_time(hw);
5496 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5497 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5498 vdec_schedule_work(&hw->work);
5499 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5500 u16 data_hight;
5501 u16 data_low;
5502 u32 video_signal;
5503
5504 int slice_header_process_status = 0;
5505 int I_flag;
5506 /*unsigned char is_idr;*/
5507 unsigned short *p = (unsigned short *)hw->lmem_addr;
5508 reset_process_time(hw);
5509
5510 if (hw->is_used_v4l) {
5511 struct aml_vcodec_ctx *ctx =
5512 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5513
5514 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5515 //amvdec_stop();
5516 hw->dec_result = DEC_RESULT_DONE;
5517 vdec_schedule_work(&hw->work);
5518 return IRQ_HANDLED;
5519 }
5520 }
5521
5522 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5523 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5524 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5525 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5526 if (input_frame_based(vdec) &&
5527 frmbase_cont_bitlevel2 != 0 &&
5528 READ_VREG(VIFF_BIT_CNT) <
5529 frmbase_cont_bitlevel2 &&
5530 hw->get_data_count >= 0x70000000) {
5531 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5532 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5533 __func__,
5534 READ_VREG(VIFF_BIT_CNT));
5535
5536 goto empty_proc;
5537 }
5538
5539 dma_sync_single_for_cpu(
5540 amports_get_dma_device(),
5541 hw->lmem_addr_remap,
5542 PAGE_SIZE,
5543 DMA_FROM_DEVICE);
5544#if 0
5545 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5546 if (!is_buffer_available(vdec)) {
5547 hw->buffer_empty_flag = 1;
5548 dpb_print(DECODE_ID(hw),
5549 PRINT_FLAG_UCODE_EVT,
5550 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5551 __func__,
5552 kfifo_len(&hw->newframe_q),
5553 have_free_buf_spec(vdec),
5554 p_H264_Dpb->mDPB.init_done,
5555 p_H264_Dpb->mDPB.used_size,
5556 p_H264_Dpb->mDPB.size,
5557 is_there_unused_frame_from_dpb(
5558 &p_H264_Dpb->mDPB));
5559 return IRQ_HANDLED;
5560 }
5561 }
5562
5563 hw->buffer_empty_flag = 0;
5564#endif
5565#ifdef SEND_PARAM_WITH_REG
5566 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5567 unsigned int data32;
5568
5569 do {
5570 data32 = READ_VREG(RPM_CMD_REG);
5571 /* printk("%x\n", data32); */
5572 } while ((data32&0x10000) == 0);
5573 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5574 WRITE_VREG(RPM_CMD_REG, 0);
5575 /* printk("%x:%x\n", i,data32); */
5576 }
5577#else
5578 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5579 int ii;
5580
5581 for (ii = 0; ii < 4; ii++) {
5582 p_H264_Dpb->dpb_param.l.data[i+ii] =
5583 p[i+3-ii];
5584 if (dpb_is_debug(DECODE_ID(hw),
5585 RRINT_FLAG_RPM)) {
5586 if (((i + ii) & 0xf) == 0)
5587 dpb_print(DECODE_ID(hw),
5588 0, "%04x:",
5589 i);
5590 dpb_print_cont(DECODE_ID(hw),
5591 0, "%04x ",
5592 p[i+3-ii]);
5593 if (((i + ii + 1) & 0xf) == 0)
5594 dpb_print_cont(
5595 DECODE_ID(hw),
5596 0, "\r\n");
5597 }
5598 }
5599 }
5600#endif
5601 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5602 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5603
5604 video_signal = (data_hight << 16) | data_low;
5605 hw->video_signal_from_vui =
5606 ((video_signal & 0xffff) << 8) |
5607 ((video_signal & 0xff0000) >> 16) |
5608 ((video_signal & 0x3f000000));
5609
5610
5611 /*dpb_print(DECODE_ID(hw),
5612 0,
5613 "video_signal_from_vui:0x%x, "
5614 "data_low:0x%x, data_hight:0x%x\n",
5615 hw->video_signal_from_vui,
5616 data_low,
5617 data_hight);*/
5618
5619 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5620
5621 if (hw->config_bufmgr_done == 0) {
5622 hw->dec_result = DEC_RESULT_DONE;
5623 vdec_schedule_work(&hw->work);
5624 dpb_print(DECODE_ID(hw),
5625 PRINT_FLAG_UCODE_EVT,
5626 "config_bufmgr not done, discard frame\n");
5627 return IRQ_HANDLED;
5628 } else if ((hw->first_i_policy & 0x3) != 0) {
5629 unsigned char is_i_slice =
5630 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5631 == I_Slice)
5632 ? 1 : 0;
5633 unsigned char is_idr =
5634 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5635 == 5);
5636 if ((hw->first_i_policy & 0x3) == 0x3)
5637 is_i_slice = is_idr;
5638 if (!is_i_slice) {
5639 if (hw->has_i_frame == 0) {
5640 amvdec_stop();
5641 vdec->mc_loaded = 0;
5642 hw->dec_result = DEC_RESULT_DONE;
5643 vdec_schedule_work(&hw->work);
5644 dpb_print(DECODE_ID(hw),
5645 PRINT_FLAG_UCODE_EVT,
5646 "has_i_frame is 0, discard none I(DR) frame\n");
5647 return IRQ_HANDLED;
5648 }
5649 } else {
5650 if (hw->skip_frame_count < 0 || is_idr) {
5651 /* second I */
5652 hw->dec_flag &= (~NODISP_FLAG);
5653 hw->skip_frame_count = 0;
5654 }
5655 if (hw->has_i_frame == 0 &&
5656 (!is_idr)) {
5657 int skip_count =
5658 (hw->first_i_policy >> 8) & 0xff;
5659 /* first I (not IDR) */
5660 if ((hw->first_i_policy & 0x3) == 2)
5661 hw->skip_frame_count =
5662 -1 - skip_count;
5663 else
5664 hw->skip_frame_count =
5665 skip_count;
5666 if (hw->skip_frame_count != 0)
5667 hw->dec_flag |= NODISP_FLAG;
5668 }
5669 }
5670 }
5671 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5672 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5673 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5674 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5675 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5676 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5677 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5678 ? I_FLAG : 0;
5679
5680 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5681 flush_dpb(p_H264_Dpb);
5682
5683 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5684 (p_H264_Dpb->mSlice.structure == FRAME)) {
5685 hw->data_flag = NULL_FLAG;
5686 goto pic_done_proc;
5687 }
5688
5689 slice_header_process_status =
5690 h264_slice_header_process(p_H264_Dpb);
5691 if (hw->mmu_enable)
5692 hevc_sao_set_slice_type(hw,
5693 slice_header_process_status,
5694 hw->dpb.mSlice.idr_flag);
5695 vui_config(hw);
5696
5697 if (p_H264_Dpb->mVideo.dec_picture) {
5698 int cfg_ret = 0;
5699 bool field_pic_flag = false;
5700
5701 if (slice_header_process_status == 1) {
5702 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5703 field_pic_flag =
5704 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5705 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5706 true : false;
5707 }
5708
5709 if (!field_pic_flag && (((p_H264_Dpb->mSPS.profile_idc == BASELINE) &&
5710 (p_H264_Dpb->reorder_pic_num < 2)) ||
5711 (((unsigned long)(hw->vh264_amstream_dec_info
5712 .param)) & 0x8))) {
5713 p_H264_Dpb->fast_output_enable =
5714 H264_OUTPUT_MODE_FAST;
5715 }
5716 else
5717 p_H264_Dpb->fast_output_enable
5718 = fast_output_enable;
5719 hw->data_flag = I_flag;
5720 if ((p_H264_Dpb->
5721 dpb_param.dpb.NAL_info_mmco & 0x1f)
5722 == 5)
5723 hw->data_flag |= IDR_FLAG;
5724 dpb_print(DECODE_ID(hw),
5725 PRINT_FLAG_VDEC_STATUS,
5726 "==================> frame count %d to skip %d\n",
5727 hw->decode_pic_count+1,
5728 hw->skip_frame_count);
5729 } else if (error_proc_policy & 0x100){
5730 struct StorablePicture *p =
5731 p_H264_Dpb->mVideo.dec_picture;
5732 unsigned mby_mbx = READ_VREG(MBY_MBX);
5733 unsigned decode_mb_count =
5734 ((mby_mbx & 0xff) * hw->mb_width +
5735 (((mby_mbx >> 8) & 0xff) + 1));
5736 if (decode_mb_count <
5737 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5738 (1 + p->mb_aff_frame_flag))) {
5739 dpb_print(DECODE_ID(hw),
5740 PRINT_FLAG_VDEC_STATUS,
5741 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5742 p_H264_Dpb->dpb_param.l.
5743 data[FIRST_MB_IN_SLICE],
5744 READ_VREG(MBY_MBX),
5745 decode_mb_count);
5746 p->data_flag |= ERROR_FLAG;
5747 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5748 p->data_flag |= ERROR_FLAG;
5749 goto pic_done_proc;
5750 }
5751 }
5752
5753 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5754 hw->new_iframe_flag = 1;
5755 }
5756 if (hw->new_iframe_flag) {
5757 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5758 hw->new_iframe_flag = 0;
5759 hw->ref_err_flush_dpb_flag = 1;
5760 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5761 hw->new_iframe_flag = 0;
5762 hw->ref_err_flush_dpb_flag = 0;
5763 }
5764 }
5765
5766 if (error_proc_policy & 0x400) {
5767 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5768 if (ret != 0) {
5769 hw->reflist_error_count ++;
5770 dpb_print(DECODE_ID(hw), 0,
5771 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5772 ret,
5773 hw->decode_pic_count+1,
5774 hw->skip_frame_count,
5775 hw->reflist_error_count);
5776
5777 if (hw->ref_err_flush_dpb_flag) {
5778 flush_dpb(p_H264_Dpb);
5779 p_H264_Dpb->colocated_buf_map = 0;
5780 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5781 p_H264_Dpb->colocated_buf_map |= 1 <<
5782 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5783 }
5784 }
5785
5786 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5787 if (((error_proc_policy & 0x80)
5788 && ((hw->dec_flag &
5789 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5790 hw->reset_bufmgr_flag = 1;
5791 hw->reflist_error_count =0;
5792 amvdec_stop();
5793 vdec->mc_loaded = 0;
5794 hw->dec_result = DEC_RESULT_DONE;
5795 vdec_schedule_work(&hw->work);
5796 return IRQ_HANDLED;
5797 }
5798 } else
5799 hw->reflist_error_count = 0;
5800 }
5801 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5802 && p_H264_Dpb->dpb_error_flag != 0) {
5803 dpb_print(DECODE_ID(hw), 0,
5804 "dpb error %d\n",
5805 p_H264_Dpb->dpb_error_flag);
5806 hw->data_flag |= ERROR_FLAG;
5807 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5808 if ((error_proc_policy & 0x80) &&
5809 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5810 hw->reset_bufmgr_flag = 1;
5811 amvdec_stop();
5812 vdec->mc_loaded = 0;
5813 hw->dec_result = DEC_RESULT_DONE;
5814 vdec_schedule_work(&hw->work);
5815 return IRQ_HANDLED;
5816 }
5817 }
5818
5819 cfg_ret = config_decode_buf(hw,
5820 p_H264_Dpb->mVideo.dec_picture);
5821 if (cfg_ret < 0) {
5822 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5823 "config_decode_buf fail (%d)\n",
5824 cfg_ret);
5825 if (error_proc_policy & 0x2) {
5826 release_cur_decoding_buf(hw);
5827 /*hw->data_flag |= ERROR_FLAG;*/
5828 hw->reset_bufmgr_flag = 1;
5829 hw->dec_result = DEC_RESULT_DONE;
5830 vdec_schedule_work(&hw->work);
5831 return IRQ_HANDLED;
5832 } else
5833 hw->data_flag |= ERROR_FLAG;
5834 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5835 }
5836 }
5837
5838 if (slice_header_process_status == 1)
5839 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5840 else
5841 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5842 hw->last_mby_mbx = 0;
5843 hw->last_vld_level = 0;
5844 start_process_time(hw);
5845 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5846 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5847pic_done_proc:
5848 reset_process_time(hw);
5849
5850 if (input_frame_based(vdec) &&
5851 (!(hw->i_only & 0x2)) &&
5852 frmbase_cont_bitlevel != 0 &&
5853 READ_VREG(VIFF_BIT_CNT) >
5854 frmbase_cont_bitlevel) {
5855 /*handle the case: multi pictures in one packet*/
5856 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5857 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5858 __func__,
5859 hw->decode_pic_count,
5860 READ_VREG(VIFF_BIT_CNT));
5861 hw->frmbase_cont_flag = 1;
5862 } else
5863 hw->frmbase_cont_flag = 0;
5864
5865 if (p_H264_Dpb->mVideo.dec_picture) {
5866 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5867#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5868 DEL_EXIST(hw,
5869 p_H264_Dpb->mVideo.dec_picture) = 0;
5870 if (vdec->master) {
5871 struct vdec_h264_hw_s *hw_ba =
5872 (struct vdec_h264_hw_s *)
5873 vdec->master->private;
5874 if (hw_ba->last_dec_picture)
5875 DEL_EXIST(hw_ba,
5876 hw_ba->last_dec_picture)
5877 = 1;
5878 }
5879#endif
5880 mutex_lock(&hw->chunks_mutex);
5881 if (hw->chunk) {
5882 p_H264_Dpb->mVideo.dec_picture->pts =
5883 hw->chunk->pts;
5884 p_H264_Dpb->mVideo.dec_picture->pts64 =
5885 hw->chunk->pts64;
5886 p_H264_Dpb->mVideo.dec_picture->timestamp =
5887 hw->chunk->timestamp;
5888#ifdef MH264_USERDATA_ENABLE
5889 vmh264_udc_fill_vpts(hw,
5890 p_H264_Dpb->mSlice.slice_type,
5891 hw->chunk->pts, 1);
5892#endif
5893
5894#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5895 } else if (vdec->master) {
5896 /*dv enhance layer,
5897 do not checkout pts*/
5898 struct StorablePicture *pic =
5899 p_H264_Dpb->mVideo.dec_picture;
5900 pic->pts = 0;
5901 pic->pts64 = 0;
5902#endif
5903 } else {
5904 struct StorablePicture *pic =
5905 p_H264_Dpb->mVideo.dec_picture;
5906 u32 offset = pic->offset_delimiter;
5907 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5908 offset, &pic->pts, 0, &pic->pts64)) {
5909 pic->pts = 0;
5910 pic->pts64 = 0;
5911#ifdef MH264_USERDATA_ENABLE
5912 vmh264_udc_fill_vpts(hw,
5913 p_H264_Dpb->mSlice.slice_type,
5914 pic->pts, 0);
5915#endif
5916 } else {
5917#ifdef MH264_USERDATA_ENABLE
5918 vmh264_udc_fill_vpts(hw,
5919 p_H264_Dpb->mSlice.slice_type,
5920 pic->pts, 1);
5921#endif
5922 }
5923
5924 }
5925 mutex_unlock(&hw->chunks_mutex);
5926
5927 check_decoded_pic_error(hw);
5928#ifdef ERROR_HANDLE_TEST
5929 if ((hw->data_flag & ERROR_FLAG)
5930 && (error_proc_policy & 0x80)) {
5931 release_cur_decoding_buf(hw);
5932 h264_clear_dpb(hw);
5933 hw->dec_flag = 0;
5934 hw->data_flag = 0;
5935 hw->skip_frame_count = 0;
5936 hw->has_i_frame = 0;
5937 hw->no_error_count = 0xfff;
5938 hw->no_error_i_count = 0xf;
5939 } else
5940#endif
5941 ret = store_picture_in_dpb(p_H264_Dpb,
5942 p_H264_Dpb->mVideo.dec_picture,
5943 hw->data_flag | hw->dec_flag |
5944 p_H264_Dpb->mVideo.dec_picture->data_flag);
5945
5946
5947
5948 if (ret == -1) {
5949 release_cur_decoding_buf(hw);
5950 bufmgr_force_recover(p_H264_Dpb);
5951 } else {
5952 if (hw->data_flag & ERROR_FLAG) {
5953 hw->no_error_count = 0;
5954 hw->no_error_i_count = 0;
5955 } else {
5956 hw->no_error_count++;
5957 if (hw->data_flag & I_FLAG)
5958 hw->no_error_i_count++;
5959 }
5960 if (hw->mmu_enable)
5961 hevc_set_unused_4k_buff_idx(hw,
5962 p_H264_Dpb->mVideo.
5963 dec_picture->buf_spec_num);
5964 bufmgr_post(p_H264_Dpb);
5965 hw->last_dec_picture =
5966 p_H264_Dpb->mVideo.dec_picture;
5967 p_H264_Dpb->mVideo.dec_picture = NULL;
5968 /* dump_dpb(&p_H264_Dpb->mDPB); */
5969 hw->has_i_frame = 1;
5970 if (hw->mmu_enable)
5971 hevc_set_frame_done(hw);
5972 hw->decode_pic_count++;
5973 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5974 if (hw->skip_frame_count > 0) {
5975 /*skip n frame after first I */
5976 hw->skip_frame_count--;
5977 if (hw->skip_frame_count == 0)
5978 hw->dec_flag &= (~NODISP_FLAG);
5979 } else if (hw->skip_frame_count < -1) {
5980 /*skip n frame after first I until second I */
5981 hw->skip_frame_count++;
5982 if (hw->skip_frame_count == -1)
5983 hw->dec_flag &= (~NODISP_FLAG);
5984 }
5985 }
5986 }
5987 if (hw->frmbase_cont_flag) {
5988 /*do not DEC_RESULT_GET_DATA*/
5989 hw->get_data_count = 0x7fffffff;
5990 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5991 decode_frame_count[DECODE_ID(hw)]++;
5992 start_process_time(hw);
5993 return IRQ_HANDLED;
5994 }
5995 amvdec_stop();
5996 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5997 "%s %s decode slice count %d\n",
5998 __func__,
5999 (dec_dpb_status == H264_PIC_DATA_DONE) ?
6000 "H264_PIC_DATA_DONE" :
6001 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
6002 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
6003 hw->decode_pic_count);
6004 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
6005 hw->dec_result = DEC_RESULT_DONE;
6006#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6007 if (vdec->slave &&
6008 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
6009 struct vdec_h264_hw_s *hw_el =
6010 (struct vdec_h264_hw_s *)(vdec->slave->private);
6011 hw_el->got_valid_nal = 0;
6012 hw->switch_dvlayer_flag = 1;
6013 } else if (vdec->master &&
6014 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
6015 struct vdec_h264_hw_s *hw_bl =
6016 (struct vdec_h264_hw_s *)(vdec->master->private);
6017 hw_bl->got_valid_nal = 0;
6018 hw->switch_dvlayer_flag = 1;
6019 } else {
6020 hw->switch_dvlayer_flag = 0;
6021 hw->got_valid_nal = 1;
6022 }
6023#endif
6024
6025 hw->dec_result = DEC_RESULT_DONE;
6026 vdec_schedule_work(&hw->work);
6027
6028#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6029 } else if (
6030 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
6031 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
6032 goto pic_done_proc;
6033#endif
6034 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
6035 reset_process_time(hw);
6036 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
6037 dma_sync_single_for_cpu(
6038 amports_get_dma_device(),
6039 hw->aux_phy_addr,
6040 hw->prefix_aux_size + hw->suffix_aux_size,
6041 DMA_FROM_DEVICE);
6042 if (dpb_is_debug(DECODE_ID(hw),
6043 PRINT_FLAG_DPB_DETAIL))
6044 dump_aux_buf(hw);
6045#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6046 if (vdec->dolby_meta_with_el || vdec->slave) {
6047 if (hw->last_dec_picture)
6048 set_aux_data(hw, hw->last_dec_picture,
6049 0, 0, NULL);
6050 } else {
6051 if (vdec->master) {
6052 struct vdec_h264_hw_s *hw_bl =
6053 (struct vdec_h264_hw_s *)
6054 (vdec->master->private);
6055 if (hw_bl->last_dec_picture != NULL) {
6056 set_aux_data(hw_bl,
6057 hw_bl->last_dec_picture,
6058 0, 1, hw);
6059 }
6060 set_aux_data(hw,
6061 hw->last_dec_picture,
6062 0, 2, NULL);
6063 }
6064 }
6065#else
6066 if (hw->last_dec_picture)
6067 set_aux_data(hw,
6068 hw->last_dec_picture, 0, 0, NULL);
6069#endif
6070 }
6071#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6072 hw->switch_dvlayer_flag = 0;
6073 hw->got_valid_nal = 1;
6074#endif
6075 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6076 "%s H264_AUX_DATA_READY\n", __func__);
6077 hw->dec_result = DEC_RESULT_DONE;
6078 vdec_schedule_work(&hw->work);
6079 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
6080 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
6081 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
6082 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
6083empty_proc:
6084 reset_process_time(hw);
6085 if (!hw->frmbase_cont_flag)
6086 release_cur_decoding_buf(hw);
6087
6088 if (input_frame_based(vdec) ||
6089 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6090 if (h264_debug_flag &
6091 DISABLE_ERROR_HANDLE) {
6092 dpb_print(DECODE_ID(hw),
6093 PRINT_FLAG_ERROR,
6094 "%s decoding error, level 0x%x\n",
6095 __func__,
6096 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6097 goto send_again;
6098 }
6099 amvdec_stop();
6100 vdec->mc_loaded = 0;
6101 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6102 "%s %s\n", __func__,
6103 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6104 "H264_SEARCH_BUFEMPTY" :
6105 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6106 "H264_DECODE_BUFEMPTY" :
6107 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6108 "H264_DECODE_TIMEOUT" :
6109 "OTHER");
6110 hw->dec_result = DEC_RESULT_DONE;
6111
6112 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6113 hw->search_dataempty_num++;
6114 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6115 hw->decode_timeout_num++;
6116 if (error_proc_policy & 0x4000) {
6117 hw->data_flag |= ERROR_FLAG;
6118 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6119 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6120 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6121 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6122 dpb_print(DECODE_ID(hw),
6123 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6124 p_H264_Dpb->last_dpb_status, __func__);
6125 hw->reset_bufmgr_flag = 1;
6126 }
6127 }
6128 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6129 hw->decode_dataempty_num++;
6130 if (!hw->frmbase_cont_flag)
6131 hw->data_flag |= ERROR_FLAG;
6132
6133 vdec_schedule_work(&hw->work);
6134 } else {
6135 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6136 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6137 "%s DEC_RESULT_AGAIN\n", __func__);
6138send_again:
6139 hw->dec_result = DEC_RESULT_AGAIN;
6140 vdec_schedule_work(&hw->work);
6141 }
6142 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6143 reset_process_time(hw);
6144 if (input_frame_based(vdec)) {
6145 dpb_print(DECODE_ID(hw),
6146 PRINT_FLAG_VDEC_STATUS,
6147 "%s H264_DATA_REQUEST (%d)\n",
6148 __func__, hw->get_data_count);
6149 hw->dec_result = DEC_RESULT_GET_DATA;
6150 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6151 hw->get_data_start_time = jiffies;
6152 hw->get_data_count++;
6153 if (hw->get_data_count >= frame_max_data_packet)
6154 goto empty_proc;
6155 vdec_schedule_work(&hw->work);
6156 } else
6157 goto empty_proc;
6158 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6159 dpb_print(DECODE_ID(hw), 0,
6160 "vmh264 decode oversize !!\n");
6161 release_cur_decoding_buf(hw);
6162 hw->data_flag |= ERROR_FLAG;
6163 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6164 reset_process_time(hw);
6165 hw->dec_result = DEC_RESULT_DONE;
6166 vdec_schedule_work(&hw->work);
6167 return IRQ_HANDLED;
6168 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6169 int aux_data_len;
6170 aux_data_len =
6171 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6172
6173 if (aux_data_len > SEI_DATA_SIZE) {
6174 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6175 "sei data size more than 4K: %d, discarded it\n",
6176 hw->sei_itu_data_len);
6177 hw->sei_itu_data_len = 0;
6178 }
6179
6180 if (aux_data_len != 0) {
6181 u8 *trans_data_buf;
6182 u8 *sei_data_buf;
6183 u8 swap_byte;
6184
6185 dma_sync_single_for_cpu(
6186 amports_get_dma_device(),
6187 hw->aux_phy_addr,
6188 hw->prefix_aux_size + hw->suffix_aux_size,
6189 DMA_FROM_DEVICE);
6190#if 0
6191 dump_aux_buf(hw);
6192#endif
6193 trans_data_buf = (u8 *)hw->aux_addr;
6194
6195 if (trans_data_buf[7] == AUX_TAG_SEI) {
6196 int left_len;
6197
6198 sei_data_buf = (u8 *)hw->sei_data_buf
6199 + hw->sei_data_len;
6200 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6201 if (aux_data_len/2 <= left_len) {
6202 for (i = 0; i < aux_data_len/2; i++)
6203 sei_data_buf[i]
6204 = trans_data_buf[i*2];
6205
6206 aux_data_len = aux_data_len / 2;
6207 for (i = 0; i < aux_data_len; i = i+4) {
6208 swap_byte = sei_data_buf[i];
6209 sei_data_buf[i]
6210 = sei_data_buf[i+3];
6211 sei_data_buf[i+3] = swap_byte;
6212
6213 swap_byte = sei_data_buf[i+1];
6214 sei_data_buf[i+1]
6215 = sei_data_buf[i+2];
6216 sei_data_buf[i+2] = swap_byte;
6217 }
6218
6219 for (i = aux_data_len-1; i >= 0; i--)
6220 if (sei_data_buf[i] != 0)
6221 break;
6222
6223 hw->sei_data_len += i+1;
6224 } else
6225 dpb_print(DECODE_ID(hw),
6226 PRINT_FLAG_ERROR,
6227 "sei data size %d and more than left space: %d, discarded it\n",
6228 hw->sei_itu_data_len,
6229 left_len);
6230 }
6231 }
6232 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6233
6234 return IRQ_HANDLED;
6235 }
6236
6237
6238 /* ucode debug */
6239 debug_tag = READ_VREG(DEBUG_REG1);
6240 if (debug_tag & 0x10000) {
6241 unsigned short *p = (unsigned short *)hw->lmem_addr;
6242
6243 dma_sync_single_for_cpu(
6244 amports_get_dma_device(),
6245 hw->lmem_addr_remap,
6246 PAGE_SIZE,
6247 DMA_FROM_DEVICE);
6248
6249 dpb_print(DECODE_ID(hw), 0,
6250 "LMEM<tag %x>:\n", debug_tag);
6251 for (i = 0; i < 0x400; i += 4) {
6252 int ii;
6253 if ((i & 0xf) == 0)
6254 dpb_print_cont(DECODE_ID(hw), 0,
6255 "%03x: ", i);
6256 for (ii = 0; ii < 4; ii++)
6257 dpb_print_cont(DECODE_ID(hw), 0,
6258 "%04x ", p[i+3-ii]);
6259 if (((i+ii) & 0xf) == 0)
6260 dpb_print_cont(DECODE_ID(hw), 0,
6261 "\n");
6262 }
6263 if (((udebug_pause_pos & 0xffff)
6264 == (debug_tag & 0xffff)) &&
6265 (udebug_pause_decode_idx == 0 ||
6266 udebug_pause_decode_idx ==
6267 hw->decode_pic_count) &&
6268 (udebug_pause_val == 0 ||
6269 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6270 udebug_pause_pos &= 0xffff;
6271 hw->ucode_pause_pos = udebug_pause_pos;
6272 }
6273 else if (debug_tag & 0x20000)
6274 hw->ucode_pause_pos = 0xffffffff;
6275 if (hw->ucode_pause_pos)
6276 reset_process_time(hw);
6277 else
6278 WRITE_VREG(DEBUG_REG1, 0);
6279 } else if (debug_tag != 0) {
6280 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6281 "dbg%x: %x\n", debug_tag,
6282 READ_VREG(DEBUG_REG2));
6283 if (((udebug_pause_pos & 0xffff)
6284 == (debug_tag & 0xffff)) &&
6285 (udebug_pause_decode_idx == 0 ||
6286 udebug_pause_decode_idx ==
6287 hw->decode_pic_count) &&
6288 (udebug_pause_val == 0 ||
6289 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6290 udebug_pause_pos &= 0xffff;
6291 hw->ucode_pause_pos = udebug_pause_pos;
6292 }
6293 if (hw->ucode_pause_pos)
6294 reset_process_time(hw);
6295 else
6296 WRITE_VREG(DEBUG_REG1, 0);
6297 }
6298 /**/
6299 return IRQ_HANDLED;
6300}
6301
6302static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6303{
6304 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6305 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6306
6307
6308 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6309
6310 if (!hw)
6311 return IRQ_HANDLED;
6312
6313 if (hw->eos)
6314 return IRQ_HANDLED;
6315
6316 p_H264_Dpb->vdec = vdec;
6317 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6318
6319 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6320 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6321 __func__,
6322 p_H264_Dpb->dec_dpb_status,
6323 READ_VREG(ERROR_STATUS_REG),
6324 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6325 READ_VREG(VLD_MEM_VIFIFO_WP),
6326 READ_VREG(VLD_MEM_VIFIFO_RP),
6327 READ_VREG(VIFF_BIT_CNT),
6328 READ_VREG(MBY_MBX));
6329
6330 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6331 if (hw->mmu_enable)
6332 hevc_sao_wait_done(hw);
6333 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6334 return IRQ_HANDLED;
6335 }
6336 return IRQ_WAKE_THREAD;
6337
6338}
6339
6340static void timeout_process(struct vdec_h264_hw_s *hw)
6341{
6342 struct vdec_s *vdec = hw_to_vdec(hw);
6343 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6344
6345 /*
6346 * In this very timeout point,the vh264_work arrives,
6347 * let it to handle the scenario.
6348 */
6349 if (work_pending(&hw->work))
6350 return;
6351
6352 hw->timeout_num++;
6353 amvdec_stop();
6354 vdec->mc_loaded = 0;
6355 if (hw->mmu_enable) {
6356 hevc_set_frame_done(hw);
6357 hevc_sao_wait_done(hw);
6358 }
6359 if (!hw->i_only && (error_proc_policy & 0x2))
6360 flush_dpb(p_H264_Dpb);
6361 dpb_print(DECODE_ID(hw),
6362 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6363 release_cur_decoding_buf(hw);
6364 hw->dec_result = DEC_RESULT_DONE;
6365 hw->data_flag |= ERROR_FLAG;
6366
6367 if (work_pending(&hw->work))
6368 return;
6369 vdec_schedule_work(&hw->timeout_work);
6370}
6371
6372static void dump_bufspec(struct vdec_h264_hw_s *hw,
6373 const char *caller)
6374{
6375 int i;
6376 dpb_print(DECODE_ID(hw), 0,
6377 "%s in %s:\n", __func__, caller);
6378 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6379 if (hw->buffer_spec[i].used == -1)
6380 continue;
6381 dpb_print(DECODE_ID(hw), 0,
6382 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6383 i, hw->buffer_spec[i].used,
6384 hw->buffer_spec[i].buf_adr,
6385 hw->buffer_spec[i].canvas_pos,
6386 hw->buffer_spec[i].vf_ref
6387 );
6388#ifdef CONFIG_AM_VDEC_DV
6389 dpb_print_cont(DECODE_ID(hw), 0,
6390 "dv_el_exist %d",
6391 hw->buffer_spec[i].dv_enhance_exist
6392 );
6393#endif
6394 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6395 }
6396
6397}
6398
6399static void vmh264_dump_state(struct vdec_s *vdec)
6400{
6401 struct vdec_h264_hw_s *hw =
6402 (struct vdec_h264_hw_s *)(vdec->private);
6403 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6404 dpb_print(DECODE_ID(hw), 0,
6405 "====== %s\n", __func__);
6406 dpb_print(DECODE_ID(hw), 0,
6407 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6408 hw->frame_width,
6409 hw->frame_height,
6410 hw->dpb.reorder_pic_num,
6411 hw->dpb.mDPB.size,
6412 hw->max_reference_size,
6413 hw->i_only,
6414 hw->send_error_frame_flag
6415 );
6416
6417 dpb_print(DECODE_ID(hw), 0,
6418 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6419 input_frame_based(vdec),
6420 hw->eos,
6421 hw->stat,
6422 hw->dec_result,
6423 decode_frame_count[DECODE_ID(hw)],
6424 display_frame_count[DECODE_ID(hw)],
6425 run_count[DECODE_ID(hw)],
6426 not_run_ready[DECODE_ID(hw)],
6427 input_empty[DECODE_ID(hw)],
6428 hw->reset_bufmgr_count
6429 );
6430
6431 if (vf_get_receiver(vdec->vf_provider_name)) {
6432 enum receviver_start_e state =
6433 vf_notify_receiver(vdec->vf_provider_name,
6434 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6435 NULL);
6436 dpb_print(DECODE_ID(hw), 0,
6437 "\nreceiver(%s) state %d\n",
6438 vdec->vf_provider_name,
6439 state);
6440 }
6441
6442 dpb_print(DECODE_ID(hw), 0,
6443 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x \n",
6444 __func__,
6445 kfifo_len(&hw->newframe_q),
6446 VF_POOL_SIZE,
6447 kfifo_len(&hw->display_q),
6448 VF_POOL_SIZE,
6449 hw->vf_pre_count,
6450 hw->vf_get_count,
6451 hw->vf_put_count,
6452 have_free_buf_spec(vdec),
6453 p_H264_Dpb->mDPB.init_done,
6454 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6455 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6456 p_H264_Dpb->fast_output_enable
6457 );
6458
6459 dump_dpb(&p_H264_Dpb->mDPB, 1);
6460 dump_pic(p_H264_Dpb);
6461 dump_bufspec(hw, __func__);
6462
6463 dpb_print(DECODE_ID(hw), 0,
6464 "DPB_STATUS_REG=0x%x\n",
6465 READ_VREG(DPB_STATUS_REG));
6466 dpb_print(DECODE_ID(hw), 0,
6467 "MPC_E=0x%x\n",
6468 READ_VREG(MPC_E));
6469 dpb_print(DECODE_ID(hw), 0,
6470 "H264_DECODE_MODE=0x%x\n",
6471 READ_VREG(H264_DECODE_MODE));
6472 dpb_print(DECODE_ID(hw), 0,
6473 "MBY_MBX=0x%x\n",
6474 READ_VREG(MBY_MBX));
6475 dpb_print(DECODE_ID(hw), 0,
6476 "H264_DECODE_SIZE=0x%x\n",
6477 READ_VREG(H264_DECODE_SIZE));
6478 dpb_print(DECODE_ID(hw), 0,
6479 "VIFF_BIT_CNT=0x%x\n",
6480 READ_VREG(VIFF_BIT_CNT));
6481 dpb_print(DECODE_ID(hw), 0,
6482 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6483 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6484 dpb_print(DECODE_ID(hw), 0,
6485 "VLD_MEM_VIFIFO_WP=0x%x\n",
6486 READ_VREG(VLD_MEM_VIFIFO_WP));
6487 dpb_print(DECODE_ID(hw), 0,
6488 "VLD_MEM_VIFIFO_RP=0x%x\n",
6489 READ_VREG(VLD_MEM_VIFIFO_RP));
6490 dpb_print(DECODE_ID(hw), 0,
6491 "PARSER_VIDEO_RP=0x%x\n",
6492 READ_PARSER_REG(PARSER_VIDEO_RP));
6493 dpb_print(DECODE_ID(hw), 0,
6494 "PARSER_VIDEO_WP=0x%x\n",
6495 READ_PARSER_REG(PARSER_VIDEO_WP));
6496
6497 if (input_frame_based(vdec) &&
6498 dpb_is_debug(DECODE_ID(hw),
6499 PRINT_FRAMEBASE_DATA)
6500 ) {
6501 int jj;
6502 if (hw->chunk && hw->chunk->block &&
6503 hw->chunk->size > 0) {
6504 u8 *data = NULL;
6505
6506 if (!hw->chunk->block->is_mapped)
6507 data = codec_mm_vmap(hw->chunk->block->start +
6508 hw->chunk->offset, hw->chunk->size);
6509 else
6510 data = ((u8 *)hw->chunk->block->start_virt)
6511 + hw->chunk->offset;
6512
6513 dpb_print(DECODE_ID(hw), 0,
6514 "frame data size 0x%x\n",
6515 hw->chunk->size);
6516 for (jj = 0; jj < hw->chunk->size; jj++) {
6517 if ((jj & 0xf) == 0)
6518 dpb_print(DECODE_ID(hw),
6519 PRINT_FRAMEBASE_DATA,
6520 "%06x:", jj);
6521 dpb_print_cont(DECODE_ID(hw),
6522 PRINT_FRAMEBASE_DATA,
6523 "%02x ", data[jj]);
6524 if (((jj + 1) & 0xf) == 0)
6525 dpb_print_cont(DECODE_ID(hw),
6526 PRINT_FRAMEBASE_DATA,
6527 "\n");
6528 }
6529
6530 if (!hw->chunk->block->is_mapped)
6531 codec_mm_unmap_phyaddr(data);
6532 }
6533 }
6534}
6535
6536
6537static void check_timer_func(unsigned long arg)
6538{
6539 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6540 struct vdec_s *vdec = hw_to_vdec(hw);
6541 int error_skip_frame_count = error_skip_count & 0xfff;
6542 unsigned int timeout_val = decode_timeout_val;
6543 if (timeout_val != 0 &&
6544 hw->no_error_count < error_skip_frame_count)
6545 timeout_val = errordata_timeout_val;
6546 if ((h264_debug_cmd & 0x100) != 0 &&
6547 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6548 hw->dec_result = DEC_RESULT_DONE;
6549 vdec_schedule_work(&hw->work);
6550 pr_info("vdec %d is forced to be disconnected\n",
6551 h264_debug_cmd & 0xff);
6552 h264_debug_cmd = 0;
6553 return;
6554 }
6555 if ((h264_debug_cmd & 0x200) != 0 &&
6556 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6557 pr_debug("vdec %d is forced to reset bufmgr\n",
6558 h264_debug_cmd & 0xff);
6559 hw->reset_bufmgr_flag = 1;
6560 h264_debug_cmd = 0;
6561 return;
6562 }
6563
6564 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6565 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6566 vdec_schedule_work(&hw->work);
6567 pr_debug("vdec requested to be disconnected\n");
6568 return;
6569 }
6570
6571 if (radr != 0) {
6572 if (rval != 0) {
6573 WRITE_VREG(radr, rval);
6574 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6575 } else
6576 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6577 rval = 0;
6578 radr = 0;
6579 }
6580
6581 if ((input_frame_based(vdec) ||
6582 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6583 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6584 (timeout_val > 0) &&
6585 (hw->start_process_time > 0) &&
6586 ((1000 * (jiffies - hw->start_process_time) / HZ)
6587 > timeout_val)
6588 ) {
6589 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6590 u32 mby_mbx = READ_VREG(MBY_MBX);
6591 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6592 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6593 if (hw->last_mby_mbx == mby_mbx) {
6594 if (hw->decode_timeout_count > 0)
6595 hw->decode_timeout_count--;
6596 if (hw->decode_timeout_count == 0)
6597 {
6598 reset_process_time(hw);
6599 timeout_process(hw);
6600 }
6601 } else
6602 start_process_time(hw);
6603 } else if (is_in_parsing_state(dpb_status)) {
6604 if (hw->last_vld_level ==
6605 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6606 if (hw->decode_timeout_count > 0)
6607 hw->decode_timeout_count--;
6608 if (hw->decode_timeout_count == 0)
6609 {
6610 reset_process_time(hw);
6611 timeout_process(hw);
6612 }
6613 }
6614 }
6615 hw->last_vld_level =
6616 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6617 hw->last_mby_mbx = mby_mbx;
6618 }
6619
6620 if ((hw->ucode_pause_pos != 0) &&
6621 (hw->ucode_pause_pos != 0xffffffff) &&
6622 udebug_pause_pos != hw->ucode_pause_pos) {
6623 hw->ucode_pause_pos = 0;
6624 WRITE_VREG(DEBUG_REG1, 0);
6625 }
6626
6627 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6628}
6629
6630static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6631{
6632 u32 ar;
6633 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6634
6635 if (!hw)
6636 return -1;
6637
6638 vstatus->frame_width = hw->frame_width;
6639 vstatus->frame_height = hw->frame_height;
6640 if (hw->frame_dur != 0)
6641 vstatus->frame_rate = 96000 / hw->frame_dur;
6642 else
6643 vstatus->frame_rate = -1;
6644 vstatus->error_count = 0;
6645 vstatus->status = hw->stat;
6646 if (hw->h264_ar == 0x3ff)
6647 hw->h264_ar = (0x100 *
6648 hw->frame_height * hw->height_aspect_ratio) /
6649 (hw->frame_width * hw->width_aspect_ratio);
6650 ar = min_t(u32,
6651 hw->h264_ar,
6652 DISP_RATIO_ASPECT_RATIO_MAX);
6653 vstatus->ratio_control =
6654 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6655
6656 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6657 "%s-%02d", DRIVER_NAME, hw->id);
6658
6659 return 0;
6660}
6661
6662static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6663{
6664 int i, j;
6665 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6666
6667 /* if (hw->init_flag == 0) { */
6668 if (h264_debug_flag & 0x40000000) {
6669 /* if (1) */
6670 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6671 "%s, reset register\n", __func__);
6672
6673 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6674 ;
6675 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6676 ; /* reg address is 0x350 */
6677
6678#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6679 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6680 WRITE_VREG(DOS_SW_RESET0, 0);
6681
6682 READ_VREG(DOS_SW_RESET0);
6683 READ_VREG(DOS_SW_RESET0);
6684 READ_VREG(DOS_SW_RESET0);
6685
6686 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6687 WRITE_VREG(DOS_SW_RESET0, 0);
6688
6689 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6690 WRITE_VREG(DOS_SW_RESET0, 0);
6691
6692 READ_VREG(DOS_SW_RESET0);
6693 READ_VREG(DOS_SW_RESET0);
6694 READ_VREG(DOS_SW_RESET0);
6695
6696#else
6697 WRITE_RESET_REG(RESET0_REGISTER,
6698 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6699 READ_RESET_REG(RESET0_REGISTER);
6700 WRITE_RESET_REG(RESET0_REGISTER,
6701 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6702
6703 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6704#endif
6705 WRITE_VREG(POWER_CTL_VLD,
6706 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6707 (1 << 9) | (1 << 6));
6708 } else {
6709 /* WRITE_VREG(POWER_CTL_VLD,
6710 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6711 */
6712 WRITE_VREG(POWER_CTL_VLD,
6713 READ_VREG(POWER_CTL_VLD) |
6714 (0 << 10) | (1 << 9) | (1 << 6));
6715 }
6716 /* disable PSCALE for hardware sharing */
6717 WRITE_VREG(PSCALE_CTRL, 0);
6718
6719 /* clear mailbox interrupt */
6720 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6721
6722 /* enable mailbox interrupt */
6723 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6724
6725#ifdef NV21
6726 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6727#endif
6728
6729 /* cbcr_merge_swap_en */
6730 if (hw->is_used_v4l
6731 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6732 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6733 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6734
6735 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6736 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6737
6738 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6739 if (hw->mmu_enable) {
6740 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6741 /* sw reset to extif hardware */
6742 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6743 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6744 } else {
6745 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6746 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6747 }
6748
6749
6750#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6751 /* pr_info("vh264 meson8 prot init\n"); */
6752 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6753#endif
6754
6755#ifdef VDEC_DW
6756 if (IS_VDEC_DW(hw)) {
6757 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6758
6759 if (IS_VDEC_DW(hw) == 2)
6760 data |= (1 << 9);
6761 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6762 }
6763#endif
6764 if (hw->dpb.mDPB.size > 0) {
6765 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6766 (hw->dpb.mDPB.size << 16) |
6767 (hw->dpb.mDPB.size << 8));
6768
6769 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6770 i = get_buf_spec_by_canvas_pos(hw, j);
6771 if (i < 0)
6772 break;
6773
6774 if (!hw->mmu_enable &&
6775 hw->buffer_spec[i].cma_alloc_addr)
6776 config_decode_canvas(hw, i);
6777 if (hw->mmu_enable && hw->double_write_mode)
6778 config_decode_canvas_ex(hw, i);
6779 }
6780 } else {
6781 WRITE_VREG(AV_SCRATCH_0, 0);
6782 WRITE_VREG(AV_SCRATCH_9, 0);
6783 }
6784
6785 if (hw->init_flag == 0)
6786 WRITE_VREG(DPB_STATUS_REG, 0);
6787 else
6788 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6789
6790 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6791 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6792 if (!tee_enabled())
6793 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6794
6795 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6796 * error_recovery_mode : error_recovery_mode_in;
6797 */
6798 /* WRITE_VREG(AV_SCRATCH_F,
6799 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6800 */
6801 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6802 ((error_recovery_mode_in & 0x1) << 4));
6803 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6804 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6805 else*/
6806 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6807
6808 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6809#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6810 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6811#endif
6812
6813 WRITE_VREG(DEBUG_REG1, 0);
6814 WRITE_VREG(DEBUG_REG2, 0);
6815
6816 if (hw->reg_iqidct_control)
6817 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6818 if (hw->reg_vcop_ctrl_reg)
6819 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6820 if (hw->vld_dec_control)
6821 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6822 return 0;
6823}
6824
6825static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6826{
6827 struct vdec_h264_hw_s *hw =
6828 (struct vdec_h264_hw_s *)vdec->private;
6829 if (i_only_flag & 0x100)
6830 return 0;
6831 if (trickmode == TRICKMODE_I)
6832 hw->i_only = 0x3;
6833 else if (trickmode == TRICKMODE_NONE)
6834 hw->i_only = 0x0;
6835 return 0;
6836}
6837
6838static unsigned char amvdec_enable_flag;
6839static void vh264_local_init(struct vdec_h264_hw_s *hw, bool is_reset)
6840{
6841 int i;
6842 hw->init_flag = 0;
6843 hw->first_sc_checked= 0;
6844 hw->eos = 0;
6845 hw->valve_count = 0;
6846 hw->config_bufmgr_done = 0;
6847 hw->start_process_time = 0;
6848 hw->has_i_frame = 0;
6849 hw->no_error_count = 0xfff;
6850 hw->no_error_i_count = 0xf;
6851
6852 hw->dec_flag = 0;
6853 hw->data_flag = 0;
6854 hw->skip_frame_count = 0;
6855 hw->reg_iqidct_control = 0;
6856 hw->reg_vcop_ctrl_reg = 0;
6857 hw->reg_rv_ai_mb_count = 0;
6858 hw->vld_dec_control = 0;
6859 hw->decode_timeout_count = 0;
6860 hw->no_mem_count = 0;
6861 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6862 /* vh264_ratio = 0x100; */
6863
6864 hw->vh264_rotation = (((unsigned long)
6865 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6866
6867 hw->frame_prog = 0;
6868 hw->frame_width = hw->vh264_amstream_dec_info.width;
6869 hw->frame_height = hw->vh264_amstream_dec_info.height;
6870 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6871 hw->pts_outside = ((unsigned long)
6872 hw->vh264_amstream_dec_info.param) & 0x01;
6873 hw->sync_outside = ((unsigned long)
6874 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6875 hw->use_idr_framerate = ((unsigned long)
6876 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6877 hw->max_refer_buf = !(((unsigned long)
6878 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6879 if (hw->frame_dur < 96000/960) {
6880 /*more than 960fps,it should not be a correct value,
6881 *give default 30fps
6882 */
6883 hw->frame_dur = 96000/30;
6884 }
6885
6886 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6887
6888 hw->first_i_policy = first_i_policy;
6889
6890 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6891 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6892 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6893 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6894
6895 if (i_only_flag & 0x100)
6896 hw->i_only = i_only_flag & 0xff;
6897 if (hw->i_only)
6898 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6899
6900 if ((unsigned long) hw->vh264_amstream_dec_info.param
6901 & 0x08)
6902 hw->no_poc_reorder_flag = 1;
6903
6904 error_recovery_mode_in = 1; /*ucode control?*/
6905 if (error_proc_policy & 0x80000000)
6906 hw->send_error_frame_flag = error_proc_policy & 0x1;
6907 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6908 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6909
6910 if (!is_reset) {
6911 INIT_KFIFO(hw->display_q);
6912 INIT_KFIFO(hw->newframe_q);
6913
6914 for (i = 0; i < VF_POOL_SIZE; i++) {
6915 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6916 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6917 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6918 kfifo_put(&hw->newframe_q, vf);
6919 }
6920 }
6921
6922 hw->duration_from_pts_done = 0;
6923
6924 hw->p_last_vf = NULL;
6925 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6926 hw->hevc_cur_buf_idx = 0xffff;
6927
6928 init_waitqueue_head(&hw->wait_q);
6929
6930 return;
6931}
6932
6933static s32 vh264_init(struct vdec_h264_hw_s *hw)
6934{
6935 int size = -1;
6936 int fw_size = 0x1000 * 16;
6937 int fw_mmu_size = 0x1000 * 16;
6938 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6939
6940 /* int trickmode_fffb = 0; */
6941
6942 /* pr_info("\nvh264_init\n"); */
6943 /* init_timer(&hw->recycle_timer); */
6944
6945 /* timer init */
6946 init_timer(&hw->check_timer);
6947
6948 hw->check_timer.data = (unsigned long)hw;
6949 hw->check_timer.function = check_timer_func;
6950 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6951
6952 /* add_timer(&hw->check_timer); */
6953 hw->stat |= STAT_TIMER_ARM;
6954 hw->stat |= STAT_ISR_REG;
6955
6956 mutex_init(&hw->chunks_mutex);
6957 vh264_local_init(hw, false);
6958 INIT_WORK(&hw->work, vh264_work);
6959 INIT_WORK(&hw->notify_work, vh264_notify_work);
6960 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6961#ifdef MH264_USERDATA_ENABLE
6962 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6963#endif
6964
6965 if (!amvdec_enable_flag) {
6966 amvdec_enable_flag = true;
6967 amvdec_enable();
6968 if (hw->mmu_enable)
6969 amhevc_enable();
6970 }
6971 if (hw->mmu_enable) {
6972
6973 hw->frame_mmu_map_addr =
6974 dma_alloc_coherent(amports_get_dma_device(),
6975 FRAME_MMU_MAP_SIZE,
6976 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6977 if (hw->frame_mmu_map_addr == NULL) {
6978 pr_err("%s: failed to alloc count_buffer\n", __func__);
6979 return -ENOMEM;
6980 }
6981 }
6982
6983 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6984 if (IS_ERR_OR_NULL(fw))
6985 return -ENOMEM;
6986
6987 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6988 if (size < 0) {
6989 pr_err("get firmware fail.\n");
6990 vfree(fw);
6991 return -1;
6992 }
6993
6994 fw->len = size;
6995 hw->fw = fw;
6996
6997 if (hw->mmu_enable) {
6998 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6999 if (IS_ERR_OR_NULL(fw_mmu))
7000 return -ENOMEM;
7001
7002 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
7003 if (size < 0) {
7004 pr_err("get mmu fw fail.\n");
7005 vfree(fw_mmu);
7006 return -1;
7007 }
7008
7009 fw_mmu->len = size;
7010 hw->fw_mmu = fw_mmu;
7011 }
7012
7013 if (!tee_enabled()) {
7014 /* -- ucode loading (amrisc and swap code) */
7015 hw->mc_cpu_addr =
7016 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
7017 &hw->mc_dma_handle, GFP_KERNEL);
7018 if (!hw->mc_cpu_addr) {
7019 amvdec_enable_flag = false;
7020 amvdec_disable();
7021 if (hw->mmu_enable)
7022 amhevc_disable();
7023 pr_info("vh264_init: Can not allocate mc memory.\n");
7024 return -ENOMEM;
7025 }
7026
7027 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
7028 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
7029 */
7030
7031 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
7032
7033 /*header*/
7034 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
7035 fw->data + 0x4000, MC_SWAP_SIZE);
7036 /*data*/
7037 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
7038 fw->data + 0x2000, MC_SWAP_SIZE);
7039 /*mmco*/
7040 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
7041 fw->data + 0x6000, MC_SWAP_SIZE);
7042 /*list*/
7043 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
7044 fw->data + 0x3000, MC_SWAP_SIZE);
7045 /*slice*/
7046 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
7047 fw->data + 0x5000, MC_SWAP_SIZE);
7048 /*main*/
7049 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
7050 fw->data, 0x2000);
7051 /*data*/
7052 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
7053 fw->data + 0x2000, 0x1000);
7054 /*slice*/
7055 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
7056 fw->data + 0x5000, 0x1000);
7057 }
7058
7059#if 1 /* #ifdef BUFFER_MGR_IN_C */
7060 hw->lmem_addr = __get_free_page(GFP_KERNEL);
7061 if (!hw->lmem_addr) {
7062 pr_info("%s: failed to alloc lmem_addr\n", __func__);
7063 return -ENOMEM;
7064 } else {
7065 hw->lmem_addr_remap = dma_map_single(
7066 amports_get_dma_device(),
7067 (void *)hw->lmem_addr,
7068 PAGE_SIZE, DMA_FROM_DEVICE);
7069 if (dma_mapping_error(amports_get_dma_device(),
7070 hw->lmem_addr_remap)) {
7071 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
7072 "%s: failed to map lmem_addr\n", __func__);
7073 free_page(hw->lmem_addr);
7074 hw->lmem_addr = 0;
7075 hw->lmem_addr_remap = 0;
7076 return -ENOMEM;
7077 }
7078
7079 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
7080 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
7081 }
7082
7083 if (prefix_aux_buf_size > 0 ||
7084 suffix_aux_buf_size > 0) {
7085 u32 aux_buf_size;
7086 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7087 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7088 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7089 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7090 if (hw->aux_addr == NULL) {
7091 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7092 return -1;
7093 }
7094
7095 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7096 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7097 if (dma_mapping_error(amports_get_dma_device(),
7098 hw->aux_phy_addr)) {
7099 pr_err("%s: failed to map rpm buffer\n", __func__);
7100 kfree(hw->aux_addr);
7101 hw->aux_addr = NULL;
7102 return -1;
7103 }
7104 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7105 if (hw->sei_data_buf == NULL) {
7106 pr_err("%s: failed to alloc sei itu data buffer\n",
7107 __func__);
7108 return -1;
7109 }
7110 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7111 if (hw->sei_itu_data_buf == NULL) {
7112 pr_err("%s: failed to alloc sei itu data buffer\n",
7113 __func__);
7114 kfree(hw->aux_addr);
7115 hw->aux_addr = NULL;
7116 kfree(hw->sei_data_buf);
7117 hw->sei_data_buf = NULL;
7118
7119 return -1;
7120 }
7121
7122 if (NULL == hw->sei_user_data_buffer) {
7123 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7124 GFP_KERNEL);
7125 if (!hw->sei_user_data_buffer) {
7126 pr_info("%s: Can not allocate sei_data_buffer\n",
7127 __func__);
7128 kfree(hw->aux_addr);
7129 hw->aux_addr = NULL;
7130 kfree(hw->sei_data_buf);
7131 hw->sei_data_buf = NULL;
7132 kfree(hw->sei_itu_data_buf);
7133 hw->sei_itu_data_buf = NULL;
7134
7135 return -1;
7136 }
7137 hw->sei_user_data_wp = 0;
7138 }
7139 }
7140/* BUFFER_MGR_IN_C */
7141#endif
7142 hw->stat |= STAT_MC_LOAD;
7143
7144 /* add memory barrier */
7145 wmb();
7146
7147 return 0;
7148}
7149
7150static int vh264_stop(struct vdec_h264_hw_s *hw)
7151{
7152 if (hw->stat & STAT_VDEC_RUN) {
7153 amvdec_stop();
7154 hw->stat &= ~STAT_VDEC_RUN;
7155 }
7156#ifdef VDEC_DW
7157 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7158#endif
7159#ifdef MH264_USERDATA_ENABLE
7160 cancel_work_sync(&hw->user_data_ready_work);
7161#endif
7162 cancel_work_sync(&hw->notify_work);
7163 cancel_work_sync(&hw->timeout_work);
7164 cancel_work_sync(&hw->work);
7165
7166
7167 if (hw->stat & STAT_MC_LOAD) {
7168 if (hw->mc_cpu_addr != NULL) {
7169 dma_free_coherent(amports_get_dma_device(),
7170 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7171 hw->mc_dma_handle);
7172 hw->mc_cpu_addr = NULL;
7173 }
7174 if (hw->frame_mmu_map_addr != NULL) {
7175 dma_free_coherent(amports_get_dma_device(),
7176 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7177 hw->frame_mmu_map_phy_addr);
7178 hw->frame_mmu_map_addr = NULL;
7179 }
7180
7181 }
7182 if (hw->stat & STAT_ISR_REG) {
7183 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7184 hw->stat &= ~STAT_ISR_REG;
7185 }
7186 if (hw->lmem_addr_remap) {
7187 dma_unmap_single(amports_get_dma_device(),
7188 hw->lmem_addr_remap,
7189 PAGE_SIZE, DMA_FROM_DEVICE);
7190 hw->lmem_addr_remap = 0;
7191 }
7192 if (hw->lmem_addr) {
7193 free_page(hw->lmem_addr);
7194 hw->lmem_addr = 0;
7195 }
7196 if (hw->aux_addr) {
7197 dma_unmap_single(amports_get_dma_device(),
7198 hw->aux_phy_addr,
7199 hw->prefix_aux_size + hw->suffix_aux_size,
7200 DMA_FROM_DEVICE);
7201 kfree(hw->aux_addr);
7202 hw->aux_addr = NULL;
7203 }
7204 if (hw->sei_data_buf != NULL) {
7205 kfree(hw->sei_data_buf);
7206 hw->sei_data_buf = NULL;
7207 }
7208 if (hw->sei_itu_data_buf != NULL) {
7209 kfree(hw->sei_itu_data_buf);
7210 hw->sei_itu_data_buf = NULL;
7211 }
7212 if (hw->sei_user_data_buffer != NULL) {
7213 kfree(hw->sei_user_data_buffer);
7214 hw->sei_user_data_buffer = NULL;
7215 }
7216 /* amvdec_disable(); */
7217
7218 vfree(hw->fw);
7219 hw->fw = NULL;
7220
7221 if (hw->mmu_enable) {
7222 vfree(hw->fw_mmu);
7223 hw->fw_mmu = NULL;
7224 }
7225
7226 dpb_print(DECODE_ID(hw), 0,
7227 "%s\n",
7228 __func__);
7229 return 0;
7230}
7231
7232static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7233{
7234 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7235 int count = 0;
7236 do {
7237 usleep_range(100, 500);
7238 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7239 break;
7240 if (count > 2000) {
7241 dpb_print(DECODE_ID(hw),
7242 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7243 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7244 break;
7245 } else
7246 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7247 count++;
7248 } while (1);
7249}
7250
7251static void vh264_notify_work(struct work_struct *work)
7252{
7253 struct vdec_h264_hw_s *hw = container_of(work,
7254 struct vdec_h264_hw_s, notify_work);
7255 struct vdec_s *vdec = hw_to_vdec(hw);
7256 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7257 vf_notify_receiver(vdec->vf_provider_name,
7258 VFRAME_EVENT_PROVIDER_FR_HINT,
7259 (void *)((unsigned long)hw->frame_dur));
7260 vdec->fr_hint_state = VDEC_HINTED;
7261 }
7262
7263 return;
7264}
7265
7266#ifdef MH264_USERDATA_ENABLE
7267static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7268{
7269 hw->wait_for_udr_send = 0;
7270 hw->sei_itu_data_len = 0;
7271 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7272}
7273
7274static void vmh264_crate_userdata_manager(
7275 struct vdec_h264_hw_s *hw,
7276 u8 *userdata_buf,
7277 int buf_len)
7278{
7279 if (hw) {
7280
7281
7282 mutex_init(&hw->userdata_mutex);
7283
7284 memset(&hw->userdata_info, 0,
7285 sizeof(struct mh264_userdata_info_t));
7286 hw->userdata_info.data_buf = userdata_buf;
7287 hw->userdata_info.buf_len = buf_len;
7288 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7289
7290 vmh264_reset_udr_mgr(hw);
7291
7292 }
7293}
7294
7295static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7296{
7297 if (hw)
7298 memset(&hw->userdata_info,
7299 0,
7300 sizeof(struct mh264_userdata_info_t));
7301}
7302
7303/*
7304#define DUMP_USERDATA_RECORD
7305*/
7306#ifdef DUMP_USERDATA_RECORD
7307
7308#define MAX_USER_DATA_SIZE 3145728
7309static void *user_data_buf;
7310static unsigned char *pbuf_start;
7311static int total_len;
7312static int bskip;
7313static int n_userdata_id;
7314
7315static void print_data(unsigned char *pdata,
7316 int len,
7317 unsigned int poc_number,
7318 unsigned int flag,
7319 unsigned int duration,
7320 unsigned int vpts,
7321 unsigned int vpts_valid,
7322 int rec_id)
7323{
7324 int nLeft;
7325
7326 nLeft = len;
7327#if 0
7328 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7329 rec_id, len, flag,
7330 duration, vpts, vpts_valid, poc_number);
7331#endif
7332 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7333 rec_id, len, flag, vpts);
7334
7335 if (len == 96) {
7336 int i;
7337 nLeft = 72;
7338 while (nLeft >= 16) {
7339 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7340 pdata[0], pdata[1], pdata[2], pdata[3],
7341 pdata[4], pdata[5], pdata[6], pdata[7],
7342 pdata[8], pdata[9], pdata[10], pdata[11],
7343 pdata[12], pdata[13], pdata[14], pdata[15]);
7344 nLeft -= 16;
7345 pdata += 16;
7346 }
7347
7348
7349 while (nLeft > 0) {
7350 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7351 pdata[0], pdata[1], pdata[2], pdata[3],
7352 pdata[4], pdata[5], pdata[6], pdata[7]);
7353 nLeft -= 8;
7354 pdata += 8;
7355 }
7356
7357 i = 0;
7358 nLeft = 96-72;
7359 while (i < nLeft) {
7360 if (pdata[0] != 0) {
7361 pr_info("some data error\n");
7362 break;
7363 }
7364 pdata++;
7365 i++;
7366 }
7367 } else {
7368 while (nLeft >= 16) {
7369 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7370 pdata[0], pdata[1], pdata[2], pdata[3],
7371 pdata[4], pdata[5], pdata[6], pdata[7],
7372 pdata[8], pdata[9], pdata[10], pdata[11],
7373 pdata[12], pdata[13], pdata[14], pdata[15]);
7374 nLeft -= 16;
7375 pdata += 16;
7376 }
7377
7378
7379 while (nLeft > 0) {
7380 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7381 pdata[0], pdata[1], pdata[2], pdata[3],
7382 pdata[4], pdata[5], pdata[6], pdata[7]);
7383 nLeft -= 8;
7384 pdata += 8;
7385 }
7386
7387 }
7388}
7389
7390static void push_to_buf(struct vdec_h264_hw_s *hw,
7391 u8 *pdata,
7392 int len,
7393 struct userdata_meta_info_t *pmeta);
7394
7395static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7396 struct mh264_userdata_record_t *record)
7397{
7398 if (record && hw) {
7399 u8 *pdata;
7400
7401 pdata = hw->userdata_info.data_buf + record->rec_start;
7402/*
7403 print_data(pdata,
7404 record->rec_len,
7405 record->meta_info.flags,
7406 record->meta_info.duration,
7407 record->meta_info.vpts,
7408 record->meta_info.vpts_valid,
7409 n_record_id);
7410*/
7411 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7412 n_userdata_id++;
7413 }
7414}
7415
7416
7417static void push_to_buf(struct vdec_h264_hw_s *hw,
7418 u8 *pdata, int len,
7419 struct userdata_meta_info_t *pmeta)
7420{
7421 u32 *pLen;
7422 int info_cnt;
7423 u8 *pbuf_end;
7424
7425 if (!user_data_buf)
7426 return;
7427
7428 if (bskip) {
7429 pr_info("over size, skip\n");
7430 return;
7431 }
7432 info_cnt = 0;
7433 pLen = (u32 *)pbuf_start;
7434
7435 *pLen = len;
7436 pbuf_start += sizeof(u32);
7437 info_cnt++;
7438 pLen++;
7439
7440 *pLen = pmeta->poc_number;
7441 pbuf_start += sizeof(u32);
7442 info_cnt++;
7443 pLen++;
7444
7445 *pLen = pmeta->duration;
7446 pbuf_start += sizeof(u32);
7447 info_cnt++;
7448 pLen++;
7449
7450 *pLen = pmeta->flags;
7451 pbuf_start += sizeof(u32);
7452 info_cnt++;
7453 pLen++;
7454
7455 *pLen = pmeta->vpts;
7456 pbuf_start += sizeof(u32);
7457 info_cnt++;
7458 pLen++;
7459
7460 *pLen = pmeta->vpts_valid;
7461 pbuf_start += sizeof(u32);
7462 info_cnt++;
7463 pLen++;
7464
7465
7466 *pLen = n_userdata_id;
7467 pbuf_start += sizeof(u32);
7468 info_cnt++;
7469 pLen++;
7470
7471
7472
7473 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7474 if (pdata + len > pbuf_end) {
7475 int first_section_len;
7476
7477 first_section_len = pbuf_end - pdata;
7478 memcpy(pbuf_start, pdata, first_section_len);
7479 pdata = (u8 *)hw->sei_user_data_buffer;
7480 pbuf_start += first_section_len;
7481 memcpy(pbuf_start, pdata, len - first_section_len);
7482 pbuf_start += len - first_section_len;
7483 } else {
7484 memcpy(pbuf_start, pdata, len);
7485 pbuf_start += len;
7486 }
7487
7488 total_len += len + info_cnt * sizeof(u32);
7489 if (total_len >= MAX_USER_DATA_SIZE-4096)
7490 bskip = 1;
7491}
7492
7493static void show_user_data_buf(void)
7494{
7495 u8 *pbuf;
7496 int len;
7497 unsigned int flag;
7498 unsigned int duration;
7499 unsigned int vpts;
7500 unsigned int vpts_valid;
7501 unsigned int poc_number;
7502 int rec_id;
7503
7504 pr_info("show user data buf\n");
7505 pbuf = user_data_buf;
7506
7507 while (pbuf < pbuf_start) {
7508 u32 *pLen;
7509
7510 pLen = (u32 *)pbuf;
7511
7512 len = *pLen;
7513 pLen++;
7514 pbuf += sizeof(u32);
7515
7516 poc_number = *pLen;
7517 pLen++;
7518 pbuf += sizeof(u32);
7519
7520 duration = *pLen;
7521 pLen++;
7522 pbuf += sizeof(u32);
7523
7524 flag = *pLen;
7525 pLen++;
7526 pbuf += sizeof(u32);
7527
7528 vpts = *pLen;
7529 pLen++;
7530 pbuf += sizeof(u32);
7531
7532 vpts_valid = *pLen;
7533 pLen++;
7534 pbuf += sizeof(u32);
7535
7536 rec_id = *pLen;
7537 pLen++;
7538 pbuf += sizeof(u32);
7539
7540 print_data(pbuf, len, poc_number, flag,
7541 duration, vpts,
7542 vpts_valid, rec_id);
7543 pbuf += len;
7544 msleep(30);
7545 }
7546}
7547
7548static int vmh264_init_userdata_dump(void)
7549{
7550 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7551 if (user_data_buf)
7552 return 1;
7553 else
7554 return 0;
7555}
7556
7557static void vmh264_dump_userdata(void)
7558{
7559 if (user_data_buf) {
7560 show_user_data_buf();
7561 kfree(user_data_buf);
7562 user_data_buf = NULL;
7563 }
7564}
7565
7566static void vmh264_reset_user_data_buf(void)
7567{
7568 total_len = 0;
7569 pbuf_start = user_data_buf;
7570 bskip = 0;
7571 n_userdata_id = 0;
7572}
7573#endif
7574
7575
7576static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7577 int frame_type,
7578 u32 vpts,
7579 u32 vpts_valid)
7580{
7581 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7582
7583 unsigned char *pdata;
7584 u8 *pmax_sei_data_buffer;
7585 u8 *sei_data_buf;
7586 int i;
7587 int wp;
7588 int data_length;
7589 struct mh264_userdata_record_t *p_userdata_rec;
7590
7591
7592#ifdef MH264_USERDATA_ENABLE
7593 struct userdata_meta_info_t meta_info;
7594 memset(&meta_info, 0, sizeof(meta_info));
7595#endif
7596
7597 if (hw->sei_itu_data_len <= 0)
7598 return;
7599
7600 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7601 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7602 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7603 for (i = 0; i < hw->sei_itu_data_len; i++) {
7604 *pdata++ = sei_data_buf[i];
7605 if (pdata >= pmax_sei_data_buffer)
7606 pdata = (u8 *)hw->sei_user_data_buffer;
7607 }
7608
7609 hw->sei_user_data_wp = (hw->sei_user_data_wp
7610 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7611 hw->sei_itu_data_len = 0;
7612
7613#ifdef MH264_USERDATA_ENABLE
7614 meta_info.duration = hw->frame_dur;
7615 meta_info.flags |= (VFORMAT_H264 << 3);
7616
7617 meta_info.vpts = vpts;
7618 meta_info.vpts_valid = vpts_valid;
7619 meta_info.poc_number =
7620 p_H264_Dpb->mVideo.dec_picture->poc;
7621
7622
7623 wp = hw->sei_user_data_wp;
7624
7625 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7626 data_length = wp - hw->userdata_info.last_wp;
7627 else
7628 data_length = wp + hw->userdata_info.buf_len
7629 - hw->userdata_info.last_wp;
7630
7631 if (data_length & 0x7)
7632 data_length = (((data_length + 8) >> 3) << 3);
7633
7634 p_userdata_rec = &hw->ud_record;
7635 p_userdata_rec->meta_info = meta_info;
7636 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7637 p_userdata_rec->rec_len = data_length;
7638 hw->userdata_info.last_wp = wp;
7639
7640 p_userdata_rec->meta_info.flags |=
7641 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7642
7643 hw->wait_for_udr_send = 1;
7644 vdec_schedule_work(&hw->user_data_ready_work);
7645#endif
7646}
7647
7648
7649static void user_data_ready_notify_work(struct work_struct *work)
7650{
7651 struct vdec_h264_hw_s *hw = container_of(work,
7652 struct vdec_h264_hw_s, user_data_ready_work);
7653
7654
7655 mutex_lock(&hw->userdata_mutex);
7656
7657 hw->userdata_info.records[hw->userdata_info.write_index]
7658 = hw->ud_record;
7659 hw->userdata_info.write_index++;
7660 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7661 hw->userdata_info.write_index = 0;
7662
7663 mutex_unlock(&hw->userdata_mutex);
7664
7665#ifdef DUMP_USERDATA_RECORD
7666 dump_userdata_record(hw, &hw->ud_record);
7667#endif
7668 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7669
7670 hw->wait_for_udr_send = 0;
7671}
7672
7673static int vmh264_user_data_read(struct vdec_s *vdec,
7674 struct userdata_param_t *puserdata_para)
7675{
7676 struct vdec_h264_hw_s *hw = NULL;
7677 int rec_ri, rec_wi;
7678 int rec_len;
7679 u8 *rec_data_start;
7680 u8 *pdest_buf;
7681 struct mh264_userdata_record_t *p_userdata_rec;
7682 u32 data_size;
7683 u32 res;
7684 int copy_ok = 1;
7685
7686 hw = (struct vdec_h264_hw_s *)vdec->private;
7687
7688 pdest_buf = puserdata_para->pbuf_addr;
7689
7690 mutex_lock(&hw->userdata_mutex);
7691
7692/*
7693 pr_info("ri = %d, wi = %d\n",
7694 lg_p_mpeg12_userdata_info->read_index,
7695 lg_p_mpeg12_userdata_info->write_index);
7696*/
7697 rec_ri = hw->userdata_info.read_index;
7698 rec_wi = hw->userdata_info.write_index;
7699
7700 if (rec_ri == rec_wi) {
7701 mutex_unlock(&hw->userdata_mutex);
7702 return 0;
7703 }
7704
7705 p_userdata_rec = hw->userdata_info.records + rec_ri;
7706
7707 rec_len = p_userdata_rec->rec_len;
7708 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7709/*
7710 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7711 p_userdata_rec->rec_len,
7712 p_userdata_rec->rec_start,
7713 puserdata_para->buf_len);
7714*/
7715 if (rec_len <= puserdata_para->buf_len) {
7716 /* dvb user data buffer is enought to
7717 copy the whole recored. */
7718 data_size = rec_len;
7719 if (rec_data_start + data_size
7720 > hw->userdata_info.data_buf_end) {
7721 int first_section_len;
7722
7723 first_section_len = hw->userdata_info.buf_len -
7724 p_userdata_rec->rec_start;
7725 res = (u32)copy_to_user((void *)pdest_buf,
7726 (void *)rec_data_start,
7727 first_section_len);
7728 if (res) {
7729 pr_info("p1 read not end res=%d, request=%d\n",
7730 res, first_section_len);
7731 copy_ok = 0;
7732
7733 p_userdata_rec->rec_len -=
7734 first_section_len - res;
7735 p_userdata_rec->rec_start +=
7736 first_section_len - res;
7737 puserdata_para->data_size =
7738 first_section_len - res;
7739 } else {
7740 res = (u32)copy_to_user(
7741 (void *)(pdest_buf+first_section_len),
7742 (void *)hw->userdata_info.data_buf,
7743 data_size - first_section_len);
7744 if (res) {
7745 pr_info("p2 read not end res=%d, request=%d\n",
7746 res, data_size);
7747 copy_ok = 0;
7748 }
7749 p_userdata_rec->rec_len -=
7750 data_size - res;
7751 p_userdata_rec->rec_start =
7752 data_size - first_section_len - res;
7753 puserdata_para->data_size =
7754 data_size - res;
7755 }
7756 } else {
7757 res = (u32)copy_to_user((void *)pdest_buf,
7758 (void *)rec_data_start,
7759 data_size);
7760 if (res) {
7761 pr_info("p3 read not end res=%d, request=%d\n",
7762 res, data_size);
7763 copy_ok = 0;
7764 }
7765 p_userdata_rec->rec_len -= data_size - res;
7766 p_userdata_rec->rec_start += data_size - res;
7767 puserdata_para->data_size = data_size - res;
7768 }
7769
7770 if (copy_ok) {
7771 hw->userdata_info.read_index++;
7772 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7773 hw->userdata_info.read_index = 0;
7774 }
7775 } else {
7776 /* dvb user data buffer is not enought
7777 to copy the whole recored. */
7778 data_size = puserdata_para->buf_len;
7779 if (rec_data_start + data_size
7780 > hw->userdata_info.data_buf_end) {
7781 int first_section_len;
7782
7783 first_section_len = hw->userdata_info.buf_len -
7784 p_userdata_rec->rec_start;
7785 res = (u32)copy_to_user((void *)pdest_buf,
7786 (void *)rec_data_start,
7787 first_section_len);
7788 if (res) {
7789 pr_info("p4 read not end res=%d, request=%d\n",
7790 res, first_section_len);
7791 copy_ok = 0;
7792 p_userdata_rec->rec_len -=
7793 first_section_len - res;
7794 p_userdata_rec->rec_start +=
7795 first_section_len - res;
7796 puserdata_para->data_size =
7797 first_section_len - res;
7798 } else {
7799 /* first secton copy is ok*/
7800 res = (u32)copy_to_user(
7801 (void *)(pdest_buf+first_section_len),
7802 (void *)hw->userdata_info.data_buf,
7803 data_size - first_section_len);
7804 if (res) {
7805 pr_info("p5 read not end res=%d, request=%d\n",
7806 res,
7807 data_size - first_section_len);
7808 copy_ok = 0;
7809 }
7810
7811 p_userdata_rec->rec_len -=
7812 data_size - res;
7813 p_userdata_rec->rec_start =
7814 data_size - first_section_len - res;
7815 puserdata_para->data_size =
7816 data_size - res;
7817 }
7818 } else {
7819 res = (u32)copy_to_user((void *)pdest_buf,
7820 (void *)rec_data_start,
7821 data_size);
7822 if (res) {
7823 pr_info("p6 read not end res=%d, request=%d\n",
7824 res, data_size);
7825 copy_ok = 0;
7826 }
7827
7828 p_userdata_rec->rec_len -= data_size - res;
7829 p_userdata_rec->rec_start += data_size - res;
7830 puserdata_para->data_size = data_size - res;
7831 }
7832
7833 if (copy_ok) {
7834 hw->userdata_info.read_index++;
7835 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7836 hw->userdata_info.read_index = 0;
7837 }
7838
7839 }
7840 puserdata_para->meta_info = p_userdata_rec->meta_info;
7841
7842 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7843 puserdata_para->meta_info.records_in_que =
7844 hw->userdata_info.write_index -
7845 hw->userdata_info.read_index;
7846 else
7847 puserdata_para->meta_info.records_in_que =
7848 hw->userdata_info.write_index +
7849 USERDATA_FIFO_NUM -
7850 hw->userdata_info.read_index;
7851
7852 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7853
7854 mutex_unlock(&hw->userdata_mutex);
7855
7856 return 1;
7857}
7858
7859static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7860{
7861 struct vdec_h264_hw_s *hw = NULL;
7862
7863 hw = (struct vdec_h264_hw_s *)vdec->private;
7864
7865 if (hw) {
7866 mutex_lock(&hw->userdata_mutex);
7867 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7868 bInit,
7869 hw->userdata_info.read_index,
7870 hw->userdata_info.write_index);
7871 hw->userdata_info.read_index = 0;
7872 hw->userdata_info.write_index = 0;
7873
7874 if (bInit)
7875 hw->userdata_info.last_wp = 0;
7876 mutex_unlock(&hw->userdata_mutex);
7877 }
7878}
7879
7880static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7881{
7882 amstream_wakeup_userdata_poll(vdec);
7883}
7884
7885#endif
7886
7887
7888static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7889 struct vdec_s *vdec, int from)
7890{
7891 /* finished decoding one frame or error,
7892 * notify vdec core to switch context
7893 */
7894 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7895 "%s dec_result %d %x %x %x\n",
7896 __func__,
7897 hw->dec_result,
7898 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7899 READ_VREG(VLD_MEM_VIFIFO_WP),
7900 READ_VREG(VLD_MEM_VIFIFO_RP));
7901 if (!hw->mmu_enable) {
7902 mutex_lock(&vmh264_mutex);
7903 dealloc_buf_specs(hw, 0);
7904 mutex_unlock(&vmh264_mutex);
7905 }
7906 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7907 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7908 u32 param1 = READ_VREG(AV_SCRATCH_1);
7909 u32 param2 = READ_VREG(AV_SCRATCH_2);
7910 u32 param3 = READ_VREG(AV_SCRATCH_6);
7911 u32 param4 = READ_VREG(AV_SCRATCH_B);
7912
7913 if (vh264_set_params(hw, param1,
7914 param2, param3, param4) < 0)
7915 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7916
7917 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7918 (hw->dpb.mDPB.size<<16) |
7919 (hw->dpb.mDPB.size<<8));
7920
7921 if (hw->is_used_v4l) {
7922 struct aml_vcodec_ctx *ctx =
7923 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7924
7925 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7926 struct aml_vdec_ps_infos ps;
7927
7928 ps.visible_width = hw->frame_width;
7929 ps.visible_height = hw->frame_height;
7930 ps.coded_width = ALIGN(hw->frame_width, 64);
7931 ps.coded_height = ALIGN(hw->frame_height, 64);
7932 ps.dpb_size = hw->dpb.mDPB.size;
7933 hw->v4l_params_parsed = true;
7934 vdec_v4l_set_ps_infos(ctx, &ps);
7935 }
7936 }
7937
7938 start_process_time(hw);
7939 return;
7940 } else
7941 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7942 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7943 && (hw_to_vdec(hw)->next_status !=
7944 VDEC_STATUS_DISCONNECTED)) {
7945 if (!vdec_has_more_input(vdec)) {
7946 hw->dec_result = DEC_RESULT_EOS;
7947 vdec_schedule_work(&hw->work);
7948 return;
7949 }
7950
7951 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7952 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7953 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7954 __func__,
7955 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7956 READ_VREG(VLD_MEM_VIFIFO_WP),
7957 READ_VREG(VLD_MEM_VIFIFO_RP));
7958 mutex_lock(&hw->chunks_mutex);
7959 vdec_vframe_dirty(vdec, hw->chunk);
7960 hw->chunk = NULL;
7961 mutex_unlock(&hw->chunks_mutex);
7962 vdec_clean_input(vdec);
7963 }
7964 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7965 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7966 > get_data_timeout_val)) {
7967 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7968 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7969 __func__);
7970 goto result_done;
7971 }
7972 if (is_buffer_available(vdec)) {
7973 int r;
7974 int decode_size;
7975 r = vdec_prepare_input(vdec, &hw->chunk);
7976 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7977 VDEC_STATUS_DISCONNECTED)) {
7978 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7979
7980 dpb_print(DECODE_ID(hw),
7981 PRINT_FLAG_VDEC_DETAIL,
7982 "vdec_prepare_input: Insufficient data\n");
7983 vdec_schedule_work(&hw->work);
7984 return;
7985 }
7986 hw->dec_result = DEC_RESULT_NONE;
7987 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7988 "%s: chunk size 0x%x\n",
7989 __func__, hw->chunk->size);
7990
7991 if (dpb_is_debug(DECODE_ID(hw),
7992 PRINT_FRAMEBASE_DATA)) {
7993 int jj;
7994 u8 *data = NULL;
7995
7996 if (!hw->chunk->block->is_mapped)
7997 data = codec_mm_vmap(
7998 hw->chunk->block->start +
7999 hw->chunk->offset, r);
8000 else
8001 data = ((u8 *)
8002 hw->chunk->block->start_virt)
8003 + hw->chunk->offset;
8004
8005 for (jj = 0; jj < r; jj++) {
8006 if ((jj & 0xf) == 0)
8007 dpb_print(DECODE_ID(hw),
8008 PRINT_FRAMEBASE_DATA,
8009 "%06x:", jj);
8010 dpb_print_cont(DECODE_ID(hw),
8011 PRINT_FRAMEBASE_DATA,
8012 "%02x ", data[jj]);
8013 if (((jj + 1) & 0xf) == 0)
8014 dpb_print_cont(DECODE_ID(hw),
8015 PRINT_FRAMEBASE_DATA,
8016 "\n");
8017 }
8018
8019 if (!hw->chunk->block->is_mapped)
8020 codec_mm_unmap_phyaddr(data);
8021 }
8022 WRITE_VREG(POWER_CTL_VLD,
8023 READ_VREG(POWER_CTL_VLD) |
8024 (0 << 10) | (1 << 9) | (1 << 6));
8025 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8026 decode_size = hw->chunk->size +
8027 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8028 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8029 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8030 vdec_enable_input(vdec);
8031
8032 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8033 start_process_time(hw);
8034 } else{
8035 if (hw_to_vdec(hw)->next_status
8036 != VDEC_STATUS_DISCONNECTED) {
8037 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
8038 vdec_schedule_work(&hw->work);
8039 }
8040 }
8041 return;
8042 } else if (hw->dec_result == DEC_RESULT_DONE) {
8043 /* if (!hw->ctx_valid)
8044 hw->ctx_valid = 1; */
8045result_done:
8046 if (hw->mmu_enable
8047 && hw->frame_busy && hw->frame_done) {
8048 long used_4k_num;
8049 hevc_sao_wait_done(hw);
8050 if (hw->hevc_cur_buf_idx != 0xffff) {
8051 used_4k_num =
8052 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
8053 if (used_4k_num >= 0)
8054 dpb_print(DECODE_ID(hw),
8055 PRINT_FLAG_MMU_DETAIL,
8056 "release unused buf , used_4k_num %ld index %d\n",
8057 used_4k_num, hw->hevc_cur_buf_idx);
8058 hevc_mmu_dma_check(hw_to_vdec(hw));
8059 decoder_mmu_box_free_idx_tail(
8060 hw->mmu_box,
8061 hw->hevc_cur_buf_idx,
8062 used_4k_num);
8063 hw->hevc_cur_buf_idx = 0xffff;
8064 }
8065 }
8066 decode_frame_count[DECODE_ID(hw)]++;
8067 amvdec_stop();
8068 if (!vdec_is_support_4k()) {
8069 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
8070 clk_adj_frame_count++;
8071 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
8072 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8073 }
8074 }
8075 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8076 "%s dec_result %d %x %x %x\n",
8077 __func__,
8078 hw->dec_result,
8079 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8080 READ_VREG(VLD_MEM_VIFIFO_WP),
8081 READ_VREG(VLD_MEM_VIFIFO_RP));
8082 mutex_lock(&hw->chunks_mutex);
8083 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8084 hw->chunk = NULL;
8085 mutex_unlock(&hw->chunks_mutex);
8086 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8087 /*
8088 stream base: stream buf empty or timeout
8089 frame base: vdec_prepare_input fail
8090 */
8091 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8092 VDEC_STATUS_DISCONNECTED)) {
8093 hw->dec_result = DEC_RESULT_EOS;
8094 vdec_schedule_work(&hw->work);
8095 return;
8096 }
8097 hw->next_again_flag = 1;
8098 } else if (hw->dec_result == DEC_RESULT_EOS) {
8099 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8100 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8101 "%s: end of stream\n",
8102 __func__);
8103 amvdec_stop();
8104 if (hw->mmu_enable)
8105 amhevc_stop();
8106 hw->eos = 1;
8107 flush_dpb(p_H264_Dpb);
8108 if (hw->is_used_v4l)
8109 notify_v4l_eos(hw_to_vdec(hw));
8110 mutex_lock(&hw->chunks_mutex);
8111 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8112 hw->chunk = NULL;
8113 mutex_unlock(&hw->chunks_mutex);
8114 vdec_clean_input(vdec);
8115 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8116 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8117 "%s: force exit\n",
8118 __func__);
8119 amvdec_stop();
8120 if (hw->mmu_enable)
8121 amhevc_stop();
8122 if (hw->stat & STAT_ISR_REG) {
8123 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8124 hw->stat &= ~STAT_ISR_REG;
8125 }
8126 }
8127 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8128 del_timer_sync(&hw->check_timer);
8129 hw->stat &= ~STAT_TIMER_ARM;
8130
8131 wait_vmh264_search_done(hw);
8132 /* mark itself has all HW resource released and input released */
8133
8134#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8135 if (hw->switch_dvlayer_flag) {
8136 if (vdec->slave)
8137 vdec_set_next_sched(vdec, vdec->slave);
8138 else if (vdec->master)
8139 vdec_set_next_sched(vdec, vdec->master);
8140 } else if (vdec->slave || vdec->master)
8141 vdec_set_next_sched(vdec, vdec);
8142#endif
8143
8144 if (from == 1) {
8145 /* This is a timeout work */
8146 if (work_pending(&hw->work)) {
8147 /*
8148 * The vh264_work arrives at the last second,
8149 * give it a chance to handle the scenario.
8150 */
8151 return;
8152 }
8153 }
8154
8155 /* mark itself has all HW resource released and input released */
8156 if (vdec->parallel_dec == 1) {
8157 if (hw->mmu_enable == 0)
8158 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8159 else
8160 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8161 } else
8162 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8163
8164 wake_up_interruptible(&hw->wait_q);
8165
8166 if (hw->is_used_v4l) {
8167 struct aml_vcodec_ctx *ctx =
8168 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8169
8170 if (ctx->param_sets_from_ucode &&
8171 !hw->v4l_params_parsed)
8172 vdec_v4l_write_frame_sync(ctx);
8173 }
8174
8175 if (hw->vdec_cb)
8176 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8177}
8178
8179
8180static void vh264_work(struct work_struct *work)
8181{
8182 struct vdec_h264_hw_s *hw = container_of(work,
8183 struct vdec_h264_hw_s, work);
8184 struct vdec_s *vdec = hw_to_vdec(hw);
8185
8186 vh264_work_implement(hw, vdec, 0);
8187}
8188
8189
8190static void vh264_timeout_work(struct work_struct *work)
8191{
8192 struct vdec_h264_hw_s *hw = container_of(work,
8193 struct vdec_h264_hw_s, timeout_work);
8194 struct vdec_s *vdec = hw_to_vdec(hw);
8195
8196 if (work_pending(&hw->work))
8197 return;
8198
8199 vh264_work_implement(hw, vdec, 1);
8200}
8201
8202static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8203{
8204 bool ret = 0;
8205 struct vdec_h264_hw_s *hw =
8206 (struct vdec_h264_hw_s *)vdec->private;
8207 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8208 CODEC_MM_FLAGS_TVP : 0;
8209
8210 if (!hw->first_sc_checked && hw->mmu_enable) {
8211 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8212 hw->first_sc_checked =1;
8213 dpb_print(DECODE_ID(hw), 0,
8214 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8215 size, (hw->need_cache_size >> PAGE_SHIFT),
8216 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8217 }
8218
8219 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8220 && pre_decode_buf_level != 0) {
8221 u32 rp, wp, level;
8222
8223 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8224 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8225 if (wp < rp)
8226 level = vdec->input.size + wp - rp;
8227 else
8228 level = wp - rp;
8229
8230 if (level < pre_decode_buf_level)
8231 return 0;
8232 }
8233
8234#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8235 if (vdec->master)
8236 return 0;
8237#endif
8238 if (hw->eos)
8239 return 0;
8240
8241 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8242 return 0;
8243
8244 if (disp_vframe_valve_level &&
8245 kfifo_len(&hw->display_q) >=
8246 disp_vframe_valve_level) {
8247 hw->valve_count--;
8248 if (hw->valve_count <= 0)
8249 hw->valve_count = 2;
8250 else
8251 return 0;
8252 }
8253 if (hw->next_again_flag &&
8254 (!vdec_frame_based(vdec))) {
8255 u32 parser_wr_ptr =
8256 READ_PARSER_REG(PARSER_VIDEO_WP);
8257 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8258 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8259 again_threshold) {
8260 int r = vdec_sync_input(vdec);
8261 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8262 "%s buf lelvel:%x\n", __func__, r);
8263 return 0;
8264 }
8265 }
8266
8267 if (h264_debug_flag & 0x20000000) {
8268 /* pr_info("%s, a\n", __func__); */
8269 ret = 1;
8270 } else
8271 ret = is_buffer_available(vdec);
8272
8273#ifdef CONSTRAIN_MAX_BUF_NUM
8274 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8275 if (run_ready_max_vf_only_num > 0 &&
8276 get_vf_ref_only_buf_count(hw) >=
8277 run_ready_max_vf_only_num
8278 )
8279 ret = 0;
8280 if (run_ready_display_q_num > 0 &&
8281 kfifo_len(&hw->display_q) >=
8282 run_ready_display_q_num)
8283 ret = 0;
8284 /*avoid more buffers consumed when
8285 switching resolution*/
8286 if (run_ready_max_buf_num == 0xff &&
8287 get_used_buf_count(hw) >
8288 hw->dpb.mDPB.size)
8289 ret = 0;
8290 else if (run_ready_max_buf_num &&
8291 get_used_buf_count(hw) >=
8292 run_ready_max_buf_num)
8293 ret = 0;
8294 }
8295#endif
8296 if (hw->is_used_v4l) {
8297 struct aml_vcodec_ctx *ctx =
8298 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8299
8300 if (ctx->param_sets_from_ucode &&
8301 !ctx->v4l_codec_ready &&
8302 hw->v4l_params_parsed) {
8303 ret = 0; /*the params has parsed.*/
8304 } else if (!ctx->v4l_codec_dpb_ready) {
8305 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8306 run_ready_min_buf_num)
8307 ret = 0;
8308 }
8309 }
8310
8311 if (ret)
8312 not_run_ready[DECODE_ID(hw)] = 0;
8313 else
8314 not_run_ready[DECODE_ID(hw)]++;
8315 if (vdec->parallel_dec == 1) {
8316 if (hw->mmu_enable == 0)
8317 return ret ? (CORE_MASK_VDEC_1) : 0;
8318 else
8319 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8320 } else
8321 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8322}
8323
8324static unsigned char get_data_check_sum
8325 (struct vdec_h264_hw_s *hw, int size)
8326{
8327 int jj;
8328 int sum = 0;
8329 u8 *data = NULL;
8330
8331 if (!hw->chunk->block->is_mapped)
8332 data = codec_mm_vmap(hw->chunk->block->start +
8333 hw->chunk->offset, size);
8334 else
8335 data = ((u8 *)hw->chunk->block->start_virt)
8336 + hw->chunk->offset;
8337
8338 for (jj = 0; jj < size; jj++)
8339 sum += data[jj];
8340
8341 if (!hw->chunk->block->is_mapped)
8342 codec_mm_unmap_phyaddr(data);
8343 return sum;
8344}
8345
8346static void run(struct vdec_s *vdec, unsigned long mask,
8347 void (*callback)(struct vdec_s *, void *), void *arg)
8348{
8349 struct vdec_h264_hw_s *hw =
8350 (struct vdec_h264_hw_s *)vdec->private;
8351 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8352 int size, ret = -1;
8353
8354 run_count[DECODE_ID(hw)]++;
8355 vdec_reset_core(vdec);
8356 if (hw->mmu_enable)
8357 hevc_reset_core(vdec);
8358 hw->vdec_cb_arg = arg;
8359 hw->vdec_cb = callback;
8360
8361 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8362 hw->reset_bufmgr_flag = 1;
8363 dpb_print(DECODE_ID(hw), 0,
8364 "kfifo len:%d invaild, need bufmgr reset\n",
8365 kfifo_len(&hw->display_q));
8366 }
8367
8368 hw->pre_parser_wr_ptr =
8369 READ_PARSER_REG(PARSER_VIDEO_WP);
8370 hw->next_again_flag = 0;
8371
8372 if (hw->reset_bufmgr_flag ||
8373 ((error_proc_policy & 0x40) &&
8374 p_H264_Dpb->buf_alloc_fail)) {
8375 h264_reset_bufmgr(vdec);
8376 hw->reset_bufmgr_flag = 0;
8377 }
8378
8379 if (h264_debug_cmd & 0xf000) {
8380 if (((h264_debug_cmd >> 12) & 0xf)
8381 == (DECODE_ID(hw) + 1)) {
8382 h264_reconfig(hw);
8383 h264_debug_cmd &= (~0xf000);
8384 }
8385 }
8386 /* hw->chunk = vdec_prepare_input(vdec); */
8387#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8388 if (vdec->slave || vdec->master)
8389 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8390#endif
8391 size = vdec_prepare_input(vdec, &hw->chunk);
8392 if ((size < 0) ||
8393 (input_frame_based(vdec) && hw->chunk == NULL)) {
8394 input_empty[DECODE_ID(hw)]++;
8395 hw->dec_result = DEC_RESULT_AGAIN;
8396
8397 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8398 "vdec_prepare_input: Insufficient data\n");
8399
8400 vdec_schedule_work(&hw->work);
8401 return;
8402 }
8403 input_empty[DECODE_ID(hw)] = 0;
8404
8405 hw->dec_result = DEC_RESULT_NONE;
8406 hw->get_data_count = 0;
8407#if 0
8408 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8409 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8410 READ_VREG(VLD_MEM_VIFIFO_RP),
8411 READ_VREG(VLD_MEM_VIFIFO_WP));
8412#endif
8413
8414 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8415 u8 *data = NULL;
8416
8417 if (!hw->chunk->block->is_mapped)
8418 data = codec_mm_vmap(hw->chunk->block->start +
8419 hw->chunk->offset, size);
8420 else
8421 data = ((u8 *)hw->chunk->block->start_virt)
8422 + hw->chunk->offset;
8423
8424 if (dpb_is_debug(DECODE_ID(hw),
8425 PRINT_FLAG_VDEC_STATUS)
8426 ) {
8427 dpb_print(DECODE_ID(hw), 0,
8428 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8429 __func__, size, get_data_check_sum(hw, size),
8430 data[0], data[1], data[2], data[3],
8431 data[4], data[5], data[size - 4],
8432 data[size - 3], data[size - 2],
8433 data[size - 1]);
8434 }
8435 if (dpb_is_debug(DECODE_ID(hw),
8436 PRINT_FRAMEBASE_DATA)
8437 ) {
8438 int jj;
8439
8440 for (jj = 0; jj < size; jj++) {
8441 if ((jj & 0xf) == 0)
8442 dpb_print(DECODE_ID(hw),
8443 PRINT_FRAMEBASE_DATA,
8444 "%06x:", jj);
8445 dpb_print_cont(DECODE_ID(hw),
8446 PRINT_FRAMEBASE_DATA,
8447 "%02x ", data[jj]);
8448 if (((jj + 1) & 0xf) == 0)
8449 dpb_print_cont(DECODE_ID(hw),
8450 PRINT_FRAMEBASE_DATA,
8451 "\n");
8452 }
8453 }
8454
8455 if (!hw->chunk->block->is_mapped)
8456 codec_mm_unmap_phyaddr(data);
8457 } else
8458 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8459 "%s: %x %x %x %x %x size 0x%x\n",
8460 __func__,
8461 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8462 READ_VREG(VLD_MEM_VIFIFO_WP),
8463 READ_VREG(VLD_MEM_VIFIFO_RP),
8464 READ_PARSER_REG(PARSER_VIDEO_RP),
8465 READ_PARSER_REG(PARSER_VIDEO_WP),
8466 size);
8467
8468 start_process_time(hw);
8469 if (vdec->mc_loaded) {
8470 /*firmware have load before,
8471 and not changes to another.
8472 ignore reload.
8473 */
8474 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8475 } else {
8476
8477 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8478 if (ret < 0) {
8479 amvdec_enable_flag = false;
8480 amvdec_disable();
8481
8482 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8483 "MH264 the %s fw loading failed, err: %x\n",
8484 tee_enabled() ? "TEE" : "local", ret);
8485 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8486 vdec_schedule_work(&hw->work);
8487 return;
8488 }
8489 vdec->mc_type = VFORMAT_H264;
8490 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8491 if (hw->mmu_enable) {
8492 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8493 hw->fw_mmu->data);
8494 if (ret < 0) {
8495 amvdec_enable_flag = false;
8496 amhevc_disable();
8497
8498 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8499 "MH264_MMU the %s fw loading failed, err: %x\n",
8500 tee_enabled() ? "TEE" : "local", ret);
8501 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8502 vdec_schedule_work(&hw->work);
8503 return;
8504 }
8505 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8506 }
8507 vdec->mc_loaded = 1;
8508 }
8509 vmh264_reset_udr_mgr(hw);
8510
8511 if (vh264_hw_ctx_restore(hw) < 0) {
8512 vdec_schedule_work(&hw->work);
8513 return;
8514 }
8515 if (input_frame_based(vdec)) {
8516 int decode_size = 0;
8517
8518 decode_size = hw->chunk->size +
8519 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8520 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8521 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8522 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8523 } else {
8524 if (size <= 0)
8525 size = 0x7fffffff; /*error happen*/
8526 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8527 WRITE_VREG(H264_DECODE_SIZE, size);
8528 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8529 }
8530 config_aux_buf(hw);
8531 config_decode_mode(hw);
8532 vdec_enable_input(vdec);
8533 WRITE_VREG(NAL_SEARCH_CTL, 0);
8534 hw->sei_data_len = 0;
8535 if (enable_itu_t35)
8536 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8537 if (!hw->init_flag) {
8538 if (hw->mmu_enable)
8539 WRITE_VREG(NAL_SEARCH_CTL,
8540 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8541 else
8542 WRITE_VREG(NAL_SEARCH_CTL,
8543 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8544 }
8545 if (udebug_flag)
8546 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8547 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8548
8549 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8550
8551 if (hw->mmu_enable)
8552 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8553 else
8554 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8555 }
8556 amvdec_start();
8557 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8558 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8559 amhevc_start();
8560 if (hw->config_bufmgr_done) {
8561 hevc_mcr_sao_global_hw_init(hw,
8562 (hw->mb_width << 4), (hw->mb_height << 4));
8563 hevc_mcr_config_canv2axitbl(hw, 1);
8564 }
8565 }
8566
8567 /* if (hw->init_flag) { */
8568 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8569 /* } */
8570
8571 hw->init_flag = 1;
8572}
8573
8574static void clear_refer_bufs(struct vdec_h264_hw_s *hw)
8575{
8576 int i;
8577
8578 mutex_lock(&vmh264_mutex);
8579 dealloc_buf_specs(hw, 1);
8580 mutex_unlock(&vmh264_mutex);
8581
8582 INIT_KFIFO(hw->display_q);
8583 INIT_KFIFO(hw->newframe_q);
8584
8585 for (i = 0; i < VF_POOL_SIZE; i++) {
8586 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8587 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8588 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8589 kfifo_put(&hw->newframe_q, vf);
8590 }
8591}
8592
8593static void reset(struct vdec_s *vdec)
8594{
8595 struct vdec_h264_hw_s *hw =
8596 (struct vdec_h264_hw_s *)vdec->private;
8597
8598 pr_info("vmh264 reset\n");
8599
8600 cancel_work_sync(&hw->work);
8601 cancel_work_sync(&hw->notify_work);
8602 if (hw->stat & STAT_VDEC_RUN) {
8603 amhevc_stop();
8604 hw->stat &= ~STAT_VDEC_RUN;
8605 }
8606
8607 if (hw->stat & STAT_TIMER_ARM) {
8608 del_timer_sync(&hw->check_timer);
8609 hw->stat &= ~STAT_TIMER_ARM;
8610 }
8611 hw->eos = 0;
8612 hw->decode_pic_count = 0;
8613 hw->dec_result = DEC_RESULT_NONE;
8614
8615 clear_refer_bufs(hw);
8616 reset_process_time(hw);
8617 h264_reset_bufmgr(vdec);
8618
8619 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8620}
8621
8622static void h264_reconfig(struct vdec_h264_hw_s *hw)
8623{
8624 int i;
8625 unsigned long flags;
8626 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8627 struct vdec_s *vdec = hw_to_vdec(hw);
8628 dpb_print(DECODE_ID(hw), 0,
8629 "%s\n", __func__);
8630 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8631 all buffers are in display queue (used == 2),
8632 or free (used == 0)
8633 */
8634 if (dpb_is_debug(DECODE_ID(hw),
8635 PRINT_FLAG_DUMP_BUFSPEC))
8636 dump_bufspec(hw, "pre h264_reconfig");
8637
8638 flush_dpb(p_H264_Dpb);
8639 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8640
8641 if (hw->collocate_cma_alloc_addr) {
8642 decoder_bmmu_box_free_idx(
8643 hw->bmmu_box,
8644 BMMU_REF_IDX);
8645 hw->collocate_cma_alloc_addr = 0;
8646 hw->dpb.colocated_mv_addr_start = 0;
8647 hw->dpb.colocated_mv_addr_end = 0;
8648 }
8649 spin_lock_irqsave(&hw->bufspec_lock, flags);
8650 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8651 if (vdec->parallel_dec == 1) {
8652 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8653 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8654 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8655 hw->buffer_spec[i].y_canvas_index = -1;
8656 hw->buffer_spec[i].u_canvas_index = -1;
8657 hw->buffer_spec[i].v_canvas_index = -1;
8658#ifdef VDEC_DW
8659 if (IS_VDEC_DW(hw)) {
8660 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8661 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8662 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8663 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8664 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8665 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8666#endif
8667 }
8668 }
8669 /*make sure buffers not put back to bufmgr when
8670 vf_put is called*/
8671 if (hw->buffer_spec[i].used == 2)
8672 hw->buffer_spec[i].used = 3;
8673
8674 /* ready to release "free buffers"
8675 */
8676 if (hw->buffer_spec[i].used == 0)
8677 hw->buffer_spec[i].used = 4;
8678
8679 hw->buffer_spec[i].canvas_pos = -1;
8680 }
8681 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8682 hw->has_i_frame = 0;
8683 hw->config_bufmgr_done = 0;
8684
8685 if (hw->is_used_v4l) {
8686 mutex_lock(&vmh264_mutex);
8687 dealloc_buf_specs(hw, 1);
8688 mutex_unlock(&vmh264_mutex);
8689 }
8690
8691 if (dpb_is_debug(DECODE_ID(hw),
8692 PRINT_FLAG_DUMP_BUFSPEC))
8693 dump_bufspec(hw, "after h264_reconfig");
8694}
8695
8696#ifdef ERROR_HANDLE_TEST
8697static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8698{
8699 int i;
8700 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8701 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8702 "%s\n", __func__);
8703 remove_dpb_pictures(p_H264_Dpb);
8704 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8705 /*make sure buffers not put back to bufmgr when
8706 vf_put is called*/
8707 if (hw->buffer_spec[i].used == 2)
8708 hw->buffer_spec[i].used = 5;
8709 }
8710
8711}
8712#endif
8713
8714static void h264_reset_bufmgr(struct vdec_s *vdec)
8715{
8716 ulong timeout;
8717 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8718#if 0
8719 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8720 int actual_dpb_size, max_reference_size;
8721 int reorder_pic_num;
8722 unsigned int colocated_buf_size;
8723 unsigned int colocated_mv_addr_start;
8724 unsigned int colocated_mv_addr_end;
8725 dpb_print(DECODE_ID(hw), 0,
8726 "%s\n", __func__);
8727
8728 for (i = 0; i < VF_POOL_SIZE; i++)
8729 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8730
8731 actual_dpb_size = p_H264_Dpb->mDPB.size;
8732 max_reference_size = p_H264_Dpb->max_reference_size;
8733 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8734
8735 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8736 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8737 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8738
8739 hw->cur_pool++;
8740 if (hw->cur_pool >= VF_POOL_NUM)
8741 hw->cur_pool = 0;
8742
8743 INIT_KFIFO(hw->display_q);
8744 INIT_KFIFO(hw->newframe_q);
8745
8746 for (i = 0; i < VF_POOL_SIZE; i++) {
8747 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8748 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8749 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8750 kfifo_put(&hw->newframe_q, vf);
8751 }
8752
8753 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8754 hw->buffer_spec[i].used = 0;
8755
8756 dpb_init_global(&hw->dpb,
8757 DECODE_ID(hw), 0, 0);
8758 p_H264_Dpb->mDPB.size = actual_dpb_size;
8759 p_H264_Dpb->max_reference_size = max_reference_size;
8760 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8761
8762 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8763 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8764 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8765
8766 p_H264_Dpb->fast_output_enable = fast_output_enable;
8767 hw->has_i_frame = 0;
8768#else
8769 dpb_print(DECODE_ID(hw), 0,
8770 "%s frame count %d to skip %d\n\n",
8771 __func__, hw->decode_pic_count+1,
8772 hw->skip_frame_count);
8773
8774 timeout = jiffies + HZ;
8775 while (kfifo_len(&hw->display_q) > 0) {
8776 if (time_after(jiffies, timeout))
8777 break;
8778 schedule();
8779 }
8780
8781 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8782
8783 buf_spec_init(hw);
8784
8785 vh264_local_init(hw, true);
8786 /*hw->decode_pic_count = 0;
8787 hw->seq_info2 = 0;*/
8788
8789 if (vh264_set_params(hw,
8790 hw->cfg_param1,
8791 hw->cfg_param2,
8792 hw->cfg_param3,
8793 hw->cfg_param4) < 0)
8794 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8795
8796 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8797 if (first_i_policy & 0x01)
8798 hw->first_i_policy = (3 << 8) | first_i_policy;
8799
8800 hw->init_flag = 1;
8801 hw->reset_bufmgr_count++;
8802#endif
8803}
8804
8805int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8806{
8807 int ret = -1;
8808 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8809 CODEC_MM_FLAGS_TVP : 0;
8810 int buf_size = 64;
8811
8812 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8813 tvp_flag, hw->mmu_enable);
8814 hw->need_cache_size = buf_size * SZ_1M;
8815 hw->sc_start_time = get_jiffies_64();
8816 if (hw->mmu_enable && !hw->mmu_box) {
8817 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8818 hw->id,
8819 MMU_MAX_BUFFERS,
8820 hw->need_cache_size,
8821 tvp_flag);
8822 if (!hw->mmu_box) {
8823 pr_err("h264 4k alloc mmu box failed!!\n");
8824 return -1;
8825 }
8826 ret = 0;
8827 }
8828 if (!hw->bmmu_box) {
8829 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8830 DRIVER_NAME,
8831 hw->id,
8832 BMMU_MAX_BUFFERS,
8833 4 + PAGE_SHIFT,
8834 CODEC_MM_FLAGS_CMA_CLEAR |
8835 CODEC_MM_FLAGS_FOR_VDECODER |
8836 tvp_flag);
8837 if (hw->bmmu_box)
8838 ret = 0;
8839 }
8840 return ret;
8841}
8842int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8843{
8844 if (hw->mmu_box) {
8845 decoder_mmu_box_free(hw->mmu_box);
8846 hw->mmu_box = NULL;
8847 }
8848 if (hw->bmmu_box) {
8849 decoder_bmmu_box_free(hw->bmmu_box);
8850 hw->bmmu_box = NULL;
8851 }
8852 return 0;
8853}
8854
8855static int ammvdec_h264_probe(struct platform_device *pdev)
8856{
8857 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8858 struct vdec_h264_hw_s *hw = NULL;
8859 char *tmpbuf;
8860 int config_val;
8861
8862 if (pdata == NULL) {
8863 pr_info("\nammvdec_h264 memory resource undefined.\n");
8864 return -EFAULT;
8865 }
8866
8867 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8868 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8869 if (hw == NULL) {
8870 pr_info("\nammvdec_h264 device data allocation failed\n");
8871 return -ENOMEM;
8872 }
8873 hw->id = pdev->id;
8874 hw->platform_dev = pdev;
8875
8876 /* the ctx from v4l2 driver. */
8877 hw->v4l2_ctx = pdata->private;
8878
8879 platform_set_drvdata(pdev, pdata);
8880
8881 hw->mmu_enable = 0;
8882 hw->first_head_check_flag = 0;
8883 hw->new_iframe_flag = 0;
8884 hw->ref_err_flush_dpb_flag = 0;
8885
8886 if (pdata->sys_info)
8887 hw->vh264_amstream_dec_info = *pdata->sys_info;
8888
8889 if (force_enable_mmu && pdata->sys_info &&
8890 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8891 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8892 (pdata->sys_info->height * pdata->sys_info->width
8893 > 1920 * 1088))
8894 hw->mmu_enable = 1;
8895
8896 if (hw->mmu_enable &&
8897 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8898 hw->mmu_enable = 0;
8899 pr_info("ionvideo needs disable mmu, path= %d \n",
8900 pdata->frame_base_video_path);
8901 }
8902
8903 if (ammvdec_h264_mmu_init(hw)) {
8904 h264_free_hw_stru(&pdev->dev, (void *)hw);
8905 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8906 return -ENOMEM;
8907 }
8908
8909 if (pdata->config_len) {
8910 /*use ptr config for doubel_write_mode, etc*/
8911 if (get_config_int(pdata->config,
8912 "mh264_double_write_mode", &config_val) == 0)
8913 hw->double_write_mode = config_val;
8914 else
8915 hw->double_write_mode = double_write_mode;
8916
8917 if (get_config_int(pdata->config,
8918 "parm_v4l_codec_enable",
8919 &config_val) == 0)
8920 hw->is_used_v4l = config_val;
8921
8922 if (get_config_int(pdata->config,
8923 "parm_v4l_buffer_margin",
8924 &config_val) == 0)
8925 hw->reorder_dpb_size_margin = config_val;
8926
8927 if (get_config_int(pdata->config,
8928 "parm_v4l_canvas_mem_mode",
8929 &config_val) == 0)
8930 hw->canvas_mode = config_val;
8931 } else
8932 hw->double_write_mode = double_write_mode;
8933
8934 if (!hw->is_used_v4l) {
8935 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8936 hw->canvas_mode = mem_map_mode;
8937
8938 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8939 hw->canvas_mode = pdata->canvas_mode;
8940 }
8941
8942 if (hw->mmu_enable)
8943 hw->double_write_mode &= 0xffff;
8944
8945 if (pdata->parallel_dec == 1) {
8946 int i;
8947 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8948 hw->buffer_spec[i].y_canvas_index = -1;
8949 hw->buffer_spec[i].u_canvas_index = -1;
8950 hw->buffer_spec[i].v_canvas_index = -1;
8951#ifdef VDEC_DW
8952 if (IS_VDEC_DW(hw)) {
8953 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8954 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8955 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8956 }
8957#endif
8958 }
8959 }
8960
8961 dpb_print(DECODE_ID(hw), 0,
8962 "%s mmu_enable %d double_write_mode 0x%x\n",
8963 __func__, hw->mmu_enable, hw->double_write_mode);
8964
8965 pdata->private = hw;
8966 pdata->dec_status = dec_status;
8967 pdata->set_trickmode = vmh264_set_trickmode;
8968 pdata->run_ready = run_ready;
8969 pdata->run = run;
8970 pdata->reset = reset;
8971 pdata->irq_handler = vh264_isr;
8972 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8973 pdata->dump_state = vmh264_dump_state;
8974
8975#ifdef MH264_USERDATA_ENABLE
8976 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8977 pdata->user_data_read = vmh264_user_data_read;
8978 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8979#else
8980 pdata->wakeup_userdata_poll = NULL;
8981 pdata->user_data_read = NULL;
8982 pdata->reset_userdata_fifo = NULL;
8983#endif
8984 if (pdata->use_vfm_path) {
8985 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8986 VFM_DEC_PROVIDER_NAME);
8987 hw->frameinfo_enable = 1;
8988 }
8989#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8990 else if (vdec_dual(pdata)) {
8991 if (dv_toggle_prov_name) /*debug purpose*/
8992 snprintf(pdata->vf_provider_name,
8993 VDEC_PROVIDER_NAME_SIZE,
8994 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8995 VFM_DEC_DVEL_PROVIDER_NAME);
8996 else
8997 snprintf(pdata->vf_provider_name,
8998 VDEC_PROVIDER_NAME_SIZE,
8999 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
9000 VFM_DEC_DVBL_PROVIDER_NAME);
9001 }
9002#endif
9003 else
9004 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9005 PROVIDER_NAME ".%02x", pdev->id & 0xff);
9006
9007 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
9008 &vf_provider_ops, pdata);
9009
9010 platform_set_drvdata(pdev, pdata);
9011
9012 buf_spec_init(hw);
9013
9014 hw->platform_dev = pdev;
9015
9016#ifdef DUMP_USERDATA_RECORD
9017 vmh264_init_userdata_dump();
9018 vmh264_reset_user_data_buf();
9019#endif
9020 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
9021 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
9022 h264_free_hw_stru(&pdev->dev, (void *)hw);
9023 pdata->dec_status = NULL;
9024 return -ENOMEM;
9025 }
9026
9027 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
9028 DCAC_READ_MARGIN;
9029 if (hw->mmu_enable) {
9030 u32 extif_size = EXTIF_BUF_SIZE;
9031 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
9032 extif_size <<= 1;
9033 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
9034 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
9035 h264_free_hw_stru(&pdev->dev, (void *)hw);
9036 pdata->dec_status = NULL;
9037 return -ENOMEM;
9038 }
9039 }
9040 if (!vdec_secure(pdata)) {
9041#if 1
9042 /*init internal buf*/
9043 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
9044 if (tmpbuf) {
9045 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9046 codec_mm_dma_flush(tmpbuf,
9047 V_BUF_ADDR_OFFSET,
9048 DMA_TO_DEVICE);
9049 } else {
9050 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
9051 V_BUF_ADDR_OFFSET);
9052 if (tmpbuf) {
9053 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
9054 codec_mm_dma_flush(tmpbuf,
9055 V_BUF_ADDR_OFFSET,
9056 DMA_TO_DEVICE);
9057 codec_mm_unmap_phyaddr(tmpbuf);
9058 }
9059 }
9060#else
9061 /*init sps/pps internal buf 64k*/
9062 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
9063 + (mem_sps_base - DEF_BUF_START_ADDR));
9064 memset(tmpbuf, 0, 0x10000);
9065 dma_sync_single_for_device(amports_get_dma_device(),
9066 hw->cma_alloc_addr +
9067 (mem_sps_base - DEF_BUF_START_ADDR),
9068 0x10000, DMA_TO_DEVICE);
9069#endif
9070 }
9071 /**/
9072
9073#if 0
9074 if (NULL == hw->sei_data_buffer) {
9075 hw->sei_data_buffer =
9076 dma_alloc_coherent(amports_get_dma_device(),
9077 USER_DATA_SIZE,
9078 &hw->sei_data_buffer_phys, GFP_KERNEL);
9079 if (!hw->sei_data_buffer) {
9080 pr_info("%s: Can not allocate sei_data_buffer\n",
9081 __func__);
9082 ammvdec_h264_mmu_release(hw);
9083 h264_free_hw_stru(&pdev->dev, (void *)hw);
9084 return -ENOMEM;
9085 }
9086 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9087 sei_data_buffer, sei_data_buffer_phys,
9088 (u32)sei_data_buffer_remap); */
9089 }
9090#endif
9091 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9092 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9093
9094 if (vdec_is_support_4k() ||
9095 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9096 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9097 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9098 {
9099 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9100 }else
9101 {
9102 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9103 }
9104
9105 if (vh264_init(hw) < 0) {
9106 pr_info("\nammvdec_h264 init failed.\n");
9107 ammvdec_h264_mmu_release(hw);
9108 h264_free_hw_stru(&pdev->dev, (void *)hw);
9109 pdata->dec_status = NULL;
9110 return -ENODEV;
9111 }
9112#ifdef MH264_USERDATA_ENABLE
9113 vmh264_crate_userdata_manager(hw,
9114 hw->sei_user_data_buffer,
9115 USER_DATA_SIZE);
9116#endif
9117
9118 vdec_set_prepare_level(pdata, start_decode_buf_level);
9119 if (pdata->parallel_dec == 1) {
9120 if (hw->mmu_enable == 0)
9121 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9122 else {
9123 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9124 | CORE_MASK_COMBINE);
9125 }
9126 } else
9127 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9128 | CORE_MASK_COMBINE);
9129
9130 atomic_set(&hw->vh264_active, 1);
9131
9132 return 0;
9133}
9134
9135static int ammvdec_h264_remove(struct platform_device *pdev)
9136{
9137 struct vdec_h264_hw_s *hw =
9138 (struct vdec_h264_hw_s *)
9139 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9140 int i;
9141
9142 struct vdec_s *vdec = hw_to_vdec(hw);
9143
9144 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9145 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9146 dpb_print(DECODE_ID(hw), 0,
9147 "%s force exit %d\n", __func__, __LINE__);
9148 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9149 vdec_schedule_work(&hw->work);
9150 wait_event_interruptible_timeout(hw->wait_q,
9151 (vdec->status == VDEC_STATUS_CONNECTED),
9152 msecs_to_jiffies(1000)); /* wait for work done */
9153 }
9154
9155 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9156 release_aux_data(hw, i);
9157
9158 atomic_set(&hw->vh264_active, 0);
9159
9160 if (hw->stat & STAT_TIMER_ARM) {
9161 del_timer_sync(&hw->check_timer);
9162 hw->stat &= ~STAT_TIMER_ARM;
9163 }
9164
9165 vh264_stop(hw);
9166#ifdef MH264_USERDATA_ENABLE
9167#ifdef DUMP_USERDATA_RECORD
9168 vmh264_dump_userdata();
9169#endif
9170 vmh264_destroy_userdata_manager(hw);
9171#endif
9172 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9173
9174 atomic_set(&hw->vh264_active, 0);
9175 if (vdec->parallel_dec == 1) {
9176 if (hw->mmu_enable == 0)
9177 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9178 else
9179 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9180 CORE_MASK_COMBINE);
9181 } else
9182 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9183
9184 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9185 if (vdec->parallel_dec == 1) {
9186 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9187 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9188 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9189 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9190 if (IS_VDEC_DW(hw)) {
9191 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9192 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9193 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9194 }
9195 }
9196 }
9197
9198 ammvdec_h264_mmu_release(hw);
9199 h264_free_hw_stru(&pdev->dev, (void *)hw);
9200 clk_adj_frame_count = 0;
9201
9202 return 0;
9203}
9204
9205/****************************************/
9206#ifdef CONFIG_PM
9207static int mh264_suspend(struct device *dev)
9208{
9209 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9210 return 0;
9211}
9212
9213static int mh264_resume(struct device *dev)
9214{
9215 amvdec_resume(to_platform_device(dev));
9216 return 0;
9217}
9218
9219static const struct dev_pm_ops mh264_pm_ops = {
9220 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9221};
9222#endif
9223
9224static struct platform_driver ammvdec_h264_driver = {
9225 .probe = ammvdec_h264_probe,
9226 .remove = ammvdec_h264_remove,
9227 .driver = {
9228 .name = DRIVER_NAME,
9229#ifdef CONFIG_PM
9230 .pm = &mh264_pm_ops,
9231#endif
9232 }
9233};
9234
9235static struct codec_profile_t ammvdec_h264_profile = {
9236 .name = "mh264",
9237 .profile = ""
9238};
9239
9240static struct mconfig hm264_configs[] = {
9241 MC_PU32("h264_debug_flag", &h264_debug_flag),
9242 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9243 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9244 MC_PU32("decode_timeout_val", &decode_timeout_val),
9245 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9246 MC_PU32("reference_buf_margin", &reference_buf_margin),
9247 MC_PU32("radr", &radr),
9248 MC_PU32("rval", &rval),
9249 MC_PU32("h264_debug_mask", &h264_debug_mask),
9250 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9251 MC_PI32("force_rate_streambase", &force_rate_streambase),
9252 MC_PI32("dec_control", &dec_control),
9253 MC_PI32("force_rate_framebase", &force_rate_framebase),
9254 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9255 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9256 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9257#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9258 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9259 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9260 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9261#endif
9262 MC_PU32("i_only_flag", &i_only_flag),
9263 MC_PU32("force_rate_streambase", &force_rate_streambase),
9264};
9265static struct mconfig_node hm264_node;
9266
9267
9268static int __init ammvdec_h264_driver_init_module(void)
9269{
9270 pr_info("ammvdec_h264 module init\n");
9271 if (platform_driver_register(&ammvdec_h264_driver)) {
9272 pr_info("failed to register ammvdec_h264 driver\n");
9273 return -ENODEV;
9274 }
9275
9276 if (vdec_is_support_4k()) {
9277 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9278 ammvdec_h264_profile.profile =
9279 "4k, dwrite, compressed";
9280 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9281 ammvdec_h264_profile.profile = "4k";
9282 }
9283 }
9284
9285 vcodec_profile_register(&ammvdec_h264_profile);
9286 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9287 "mh264", hm264_configs, CONFIG_FOR_RW);
9288 return 0;
9289}
9290
9291static void __exit ammvdec_h264_driver_remove_module(void)
9292{
9293 pr_info("ammvdec_h264 module remove.\n");
9294
9295 platform_driver_unregister(&ammvdec_h264_driver);
9296}
9297
9298/****************************************/
9299module_param(h264_debug_flag, uint, 0664);
9300MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9301
9302module_param(start_decode_buf_level, int, 0664);
9303MODULE_PARM_DESC(start_decode_buf_level,
9304 "\n ammvdec_h264 start_decode_buf_level\n");
9305
9306module_param(pre_decode_buf_level, int, 0664);
9307MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9308
9309module_param(fixed_frame_rate_mode, uint, 0664);
9310MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9311
9312module_param(decode_timeout_val, uint, 0664);
9313MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9314
9315module_param(errordata_timeout_val, uint, 0664);
9316MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9317
9318module_param(get_data_timeout_val, uint, 0664);
9319MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9320
9321module_param(frame_max_data_packet, uint, 0664);
9322MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9323
9324module_param(reorder_dpb_size_margin, uint, 0664);
9325MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9326
9327#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9328module_param(reorder_dpb_size_margin_dv, uint, 0664);
9329MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9330 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9331#endif
9332
9333module_param(reference_buf_margin, uint, 0664);
9334MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9335
9336#ifdef CONSTRAIN_MAX_BUF_NUM
9337module_param(run_ready_max_vf_only_num, uint, 0664);
9338MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9339
9340module_param(run_ready_display_q_num, uint, 0664);
9341MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9342
9343module_param(run_ready_max_buf_num, uint, 0664);
9344MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9345#endif
9346
9347module_param(radr, uint, 0664);
9348MODULE_PARM_DESC(radr, "\nradr\n");
9349
9350module_param(rval, uint, 0664);
9351MODULE_PARM_DESC(rval, "\nrval\n");
9352
9353module_param(h264_debug_mask, uint, 0664);
9354MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9355
9356module_param(h264_debug_cmd, uint, 0664);
9357MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9358
9359module_param(force_rate_streambase, int, 0664);
9360MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9361
9362module_param(dec_control, int, 0664);
9363MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9364
9365module_param(force_rate_framebase, int, 0664);
9366MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9367
9368module_param(force_disp_bufspec_num, int, 0664);
9369MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9370
9371module_param(V_BUF_ADDR_OFFSET, int, 0664);
9372MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9373
9374module_param(prefix_aux_buf_size, uint, 0664);
9375MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9376
9377module_param(suffix_aux_buf_size, uint, 0664);
9378MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9379
9380#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9381module_param(dv_toggle_prov_name, uint, 0664);
9382MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9383
9384module_param(dolby_meta_with_el, uint, 0664);
9385MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9386
9387#endif
9388
9389module_param(fast_output_enable, uint, 0664);
9390MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9391
9392module_param(error_proc_policy, uint, 0664);
9393MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9394
9395module_param(error_skip_count, uint, 0664);
9396MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9397
9398module_param(force_sliding_margin, uint, 0664);
9399MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9400
9401module_param(i_only_flag, uint, 0664);
9402MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9403
9404module_param(first_i_policy, uint, 0664);
9405MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9406
9407module_param(frmbase_cont_bitlevel, uint, 0664);
9408MODULE_PARM_DESC(frmbase_cont_bitlevel,
9409 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9410
9411module_param(frmbase_cont_bitlevel2, uint, 0664);
9412MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9413 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9414
9415module_param(udebug_flag, uint, 0664);
9416MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9417
9418module_param(udebug_pause_pos, uint, 0664);
9419MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9420
9421module_param(udebug_pause_val, uint, 0664);
9422MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9423
9424module_param(udebug_pause_decode_idx, uint, 0664);
9425MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9426
9427module_param(max_alloc_buf_count, uint, 0664);
9428MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9429
9430module_param(enable_itu_t35, uint, 0664);
9431MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9432
9433module_param(endian, uint, 0664);
9434MODULE_PARM_DESC(endian, "\nrval\n");
9435
9436module_param(mmu_enable, uint, 0664);
9437MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9438
9439module_param(force_enable_mmu, uint, 0664);
9440MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9441
9442module_param(again_threshold, uint, 0664);
9443MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9444
9445module_param(stream_mode_start_num, uint, 0664);
9446MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9447
9448/*
9449module_param(trigger_task, uint, 0664);
9450MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9451*/
9452module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9453
9454module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9455
9456module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9457
9458module_param_array(run_count, uint,
9459 &max_decode_instance_num, 0664);
9460
9461module_param_array(not_run_ready, uint,
9462 &max_decode_instance_num, 0664);
9463
9464module_param_array(input_empty, uint,
9465 &max_decode_instance_num, 0664);
9466
9467module_param_array(max_get_frame_interval, uint,
9468 &max_decode_instance_num, 0664);
9469
9470module_param_array(step, uint, &max_decode_instance_num, 0664);
9471
9472module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9473
9474module_param(disp_vframe_valve_level, uint, 0664);
9475MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9476
9477module_param(double_write_mode, uint, 0664);
9478MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9479
9480module_param(mem_map_mode, uint, 0664);
9481MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9482
9483module_param(without_display_mode, uint, 0664);
9484MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9485
9486
9487module_init(ammvdec_h264_driver_init_module);
9488module_exit(ammvdec_h264_driver_remove_module);
9489
9490MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9491MODULE_LICENSE("GPL");
9492
generated by cgit at 2024-05-17 11:58:02 (GMT)