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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 4992872a13e2c40327c80444d4cd78223cb17c39
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../amvdec_ports/vdec_drv_base.h"
62#include "../../../amvdec_ports/aml_vcodec_adapt.h"
63#include "../../../common/chips/decoder_cpu_ver_info.h"
64#include <linux/crc32.h>
65
66
67
68#undef pr_info
69#define pr_info printk
70#define VDEC_DW
71#define DEBUG_UCODE
72#define MEM_NAME "codec_m264"
73#define MULTI_INSTANCE_FRAMEWORK
74/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
75#include "h264_dpb.h"
76/* #define SEND_PARAM_WITH_REG */
77
78#define DRIVER_NAME "ammvdec_h264"
79#define MODULE_NAME "ammvdec_h264"
80#define DRIVER_HEADER_NAME "ammvdec_h264_header"
81
82#define CHECK_INTERVAL (HZ/100)
83
84#define SEI_DATA_SIZE (8*1024)
85#define SEI_ITU_DATA_SIZE (4*1024)
86
87#define RATE_MEASURE_NUM 8
88#define RATE_CORRECTION_THRESHOLD 5
89#define RATE_2397_FPS 4004 /* 23.97 */
90#define RATE_25_FPS 3840 /* 25 */
91#define RATE_2997_FPS 3203 /* 29.97 */
92#define DUR2PTS(x) ((x)*90/96)
93#define PTS2DUR(x) ((x)*96/90)
94#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
95#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
96
97#define FIX_FRAME_RATE_OFF 0
98#define FIX_FRAME_RATE_ON 1
99#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
100
101#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
102#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
103#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
104#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
105
106#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
107
108#define RATE_MEASURE_NUM 8
109#define RATE_CORRECTION_THRESHOLD 5
110#define RATE_24_FPS 4004 /* 23.97 */
111#define RATE_25_FPS 3840 /* 25 */
112#define DUR2PTS(x) ((x)*90/96)
113#define PTS2DUR(x) ((x)*96/90)
114#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
115#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
116
117#define H264_DEV_NUM 9
118
119#define CONSTRAIN_MAX_BUF_NUM
120
121#define H264_MMU
122#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
123
124static int mmu_enable;
125/*mmu do not support mbaff*/
126static int force_enable_mmu = 0;
127unsigned int h264_debug_flag; /* 0xa0000000; */
128unsigned int h264_debug_mask = 0xff;
129 /*
130 *h264_debug_cmd:
131 * 0x1xx, force decoder id of xx to be disconnected
132 */
133unsigned int h264_debug_cmd;
134
135static unsigned int dec_control =
136 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
137 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
138
139static unsigned int force_rate_streambase;
140static unsigned int force_rate_framebase;
141static unsigned int force_disp_bufspec_num;
142static unsigned int fixed_frame_rate_mode;
143static unsigned int error_recovery_mode_in;
144static int start_decode_buf_level = 0x4000;
145static int pre_decode_buf_level = 0x1000;
146static int stream_mode_start_num = 4;
147
148#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
149/*to make reorder size difference of bl and el not too big*/
150static unsigned int reorder_dpb_size_margin_dv = 16;
151#endif
152static unsigned int reorder_dpb_size_margin = 6;
153static unsigned int reference_buf_margin = 4;
154
155#ifdef CONSTRAIN_MAX_BUF_NUM
156static u32 run_ready_max_vf_only_num;
157static u32 run_ready_display_q_num;
158 /*0: not check
159 0xff: mDPB.size
160 */
161static u32 run_ready_max_buf_num = 0xff;
162#endif
163
164#define VDEC_ASSIST_CANVAS_BLK32 0x5
165
166
167static unsigned int max_alloc_buf_count;
168static unsigned int decode_timeout_val = 100;
169static unsigned int errordata_timeout_val = 50;
170static unsigned int get_data_timeout_val = 2000;
171#if 1
172/* H264_DATA_REQUEST does not work, disable it,
173decode has error for data in none continuous address
174*/
175static unsigned int frame_max_data_packet;
176#else
177static unsigned int frame_max_data_packet = 8;
178#endif
179static unsigned int radr;
180static unsigned int rval;
181static u32 endian = 0xff0;
182
183/*
184 udebug_flag:
185 bit 0, enable ucode print
186 bit 1, enable ucode detail print
187 bit 3, disable ucode watchdog
188 bit [31:16] not 0, pos to dump lmem
189 bit 2, pop bits to lmem
190 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
191*/
192static u32 udebug_flag;
193/*
194 when udebug_flag[1:0] is not 0
195 udebug_pause_pos not 0,
196 pause position
197*/
198static u32 udebug_pause_pos;
199/*
200 when udebug_flag[1:0] is not 0
201 and udebug_pause_pos is not 0,
202 pause only when DEBUG_REG2 is equal to this val
203*/
204static u32 udebug_pause_val;
205
206static u32 udebug_pause_decode_idx;
207
208static unsigned int disp_vframe_valve_level;
209
210static unsigned int max_decode_instance_num = H264_DEV_NUM;
211static unsigned int decode_frame_count[H264_DEV_NUM];
212static unsigned int display_frame_count[H264_DEV_NUM];
213static unsigned int max_process_time[H264_DEV_NUM];
214static unsigned int max_get_frame_interval[H264_DEV_NUM];
215static unsigned int run_count[H264_DEV_NUM];
216static unsigned int input_empty[H264_DEV_NUM];
217static unsigned int not_run_ready[H264_DEV_NUM];
218static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
219{1, 1, 1, 1, 1, 1, 1, 1, 1};
220
221#define VDEC_CLOCK_ADJUST_FRAME 30
222static unsigned int clk_adj_frame_count;
223
224/*
225 *bit[3:0]: 0, run ; 1, pause; 3, step
226 *bit[4]: 1, schedule run
227 */
228static unsigned int step[H264_DEV_NUM];
229
230#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
231static u32 prefix_aux_buf_size = (16 * 1024);
232static u32 suffix_aux_buf_size;
233
234#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
235static u32 dv_toggle_prov_name;
236
237static u32 dolby_meta_with_el;
238#endif
239
240/*
241 bit[8]
242 0: use sys_info[bit 3]
243 not 0:use i_only_flag[7:0]
244 bit[7:0]:
245 bit 0, 1: only display I picture;
246 bit 1, 1: only decode I picture;
247*/
248static unsigned int i_only_flag;
249
250/*
251 error_proc_policy:
252 bit[0] send_error_frame_flag;
253 (valid when bit[31] is 1, otherwise use sysinfo)
254 bit[1] do not decode if config_decode_buf() fail
255 bit[2] force release buf if in deadlock
256 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
257 bit[4] check inactive of receiver
258 bit[5] reset buffmgr if in deadlock
259 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
260 bit[7] reset buffmgr if dpb error
261
262 bit[8] check total mbx/mby of decoded frame
263 bit[9] check ERROR_STATUS_REG
264 bit[10] check reference list
265 bit[11] mark error if dpb error
266 bit[12] i_only when error happen
267 bit[13] 0: mark error according to last pic, 1: ignore mark error
268 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
269*/
270static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
271
272
273/*
274 error_skip_count:
275 bit[11:0] error skip frame count
276 bit[15:12] error skip i picture count
277*/
278static unsigned int error_skip_count = (0x2 << 12) | 0x40;
279
280static unsigned int force_sliding_margin;
281/*
282 bit[1:0]:
283 0, start playing from any frame
284 1, start playing from I frame
285 bit[15:8]: the count of skip frames after first I
286 2, start playing from second I frame (decode from the first I)
287 bit[15:8]: the max count of skip frames after first I
288 3, start playing from IDR
289*/
290static unsigned int first_i_policy = 1;
291
292/*
293 fast_output_enable:
294 bit [0], output frame if there is IDR in list
295 bit [1], output frame if the current poc is 1 big than the previous poc
296 bit [2], if even poc only, output frame ifthe cuurent poc
297 is 2 big than the previous poc
298 bit [3], ip only
299*/
300static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
301
302static unsigned int enable_itu_t35 = 1;
303
304static unsigned int frmbase_cont_bitlevel = 0x40;
305
306static unsigned int frmbase_cont_bitlevel2 = 0x1;
307
308
309#define MH264_USERDATA_ENABLE
310
311/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
312/* hevc->double_write_mode:
313 0, no double write
314 1, 1:1 ratio
315 2, (1/4):(1/4) ratio
316 3, (1/4):(1/4) ratio, with both compressed frame included
317 4, (1/2):(1/2) ratio
318 0x10, double write only
319 0x10000: vdec dw horizotal 1/2
320 0x20000: vdec dw horizotal/vertical 1/2
321*/
322static u32 double_write_mode;
323static u32 without_display_mode;
324#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
325
326static void vmh264_dump_state(struct vdec_s *vdec);
327
328#define is_in_parsing_state(status) \
329 ((status == H264_ACTION_SEARCH_HEAD) || \
330 ((status & 0xf0) == 0x80))
331
332#define is_interlace(frame) \
333 (frame->frame &&\
334 frame->top_field &&\
335 frame->bottom_field &&\
336 (!frame->frame->coded_frame))
337static inline bool close_to(int a, int b, int m)
338{
339 return (abs(a - b) < m) ? true : false;
340}
341
342#if 0
343#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
344#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
345#else
346#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
347#define h264_free_hw_stru(dev, hw) vfree(hw)
348#endif
349
350/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
351#define NV21
352/* #endif */
353
354/* 12M for L41 */
355#define MAX_DPB_BUFF_SIZE (12*1024*1024)
356#define DEFAULT_MEM_SIZE (32*1024*1024)
357#define AVIL_DPB_BUFF_SIZE 0x01ec2000
358
359#define DEF_BUF_START_ADDR 0x01000000
360#define mem_sps_base 0x011c3c00
361#define mem_pps_base 0x011cbc00
362/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
363u32 V_BUF_ADDR_OFFSET = 0x200000;
364#define DCAC_READ_MARGIN (64 * 1024)
365
366
367#define EXTEND_SAR 0xff
368#define BUFSPEC_POOL_SIZE 64
369#define VF_POOL_SIZE 64
370#define VF_POOL_NUM 2
371#define MAX_VF_BUF_NUM 27
372#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
373#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
374#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
375#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
376#define EXTIF_BUF_SIZE (0x10000 * 2)
377
378#define HEADER_BUFFER_IDX(n) (n)
379#define VF_BUFFER_IDX(n) (n)
380
381
382#define PUT_INTERVAL (HZ/100)
383#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
384
385#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
386#define SWITCHING_STATE_OFF 0
387#define SWITCHING_STATE_ON_CMD3 1
388#define SWITCHING_STATE_ON_CMD1 2
389
390
391
392#define INCPTR(p) ptr_atomic_wrap_inc(&p)
393
394#define SLICE_TYPE_I 2
395#define SLICE_TYPE_P 5
396#define SLICE_TYPE_B 6
397
398struct buffer_spec_s {
399 /*
400 used:
401 -1, none allocated
402 0, allocated, free
403 1, used by dpb
404 2, in disp queue;
405 3, in disp queue, isolated,
406 do not use for dpb when vf_put;
407 4, to release
408 5, in disp queue, isolated (but not to release)
409 do not use for dpb when vf_put;
410 */
411 unsigned int used;
412 unsigned int info0;
413 unsigned int info1;
414 unsigned int info2;
415 unsigned int y_addr;
416 unsigned int u_addr;
417 unsigned int v_addr;
418
419 int y_canvas_index;
420 int u_canvas_index;
421 int v_canvas_index;
422
423#ifdef VDEC_DW
424 unsigned int vdec_dw_y_addr;
425 unsigned int vdec_dw_u_addr;
426 unsigned int vdec_dw_v_addr;
427
428 int vdec_dw_y_canvas_index;
429 int vdec_dw_u_canvas_index;
430 int vdec_dw_v_canvas_index;
431#ifdef NV21
432 struct canvas_config_s vdec_dw_canvas_config[2];
433#else
434 struct canvas_config_s vdec_dw_canvas_config[3];
435#endif
436#endif
437
438#ifdef NV21
439 struct canvas_config_s canvas_config[2];
440#else
441 struct canvas_config_s canvas_config[3];
442#endif
443 unsigned long cma_alloc_addr;
444 unsigned int buf_adr;
445#ifdef H264_MMU
446 unsigned long alloc_header_addr;
447#endif
448 char *aux_data_buf;
449 int aux_data_size;
450#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
451 unsigned char dv_enhance_exist;
452#endif
453 int canvas_pos;
454 int vf_ref;
455 /*unsigned int comp_body_size;*/
456 unsigned int dw_y_adr;
457 unsigned int dw_u_v_adr;
458};
459
460#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
461#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
462#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
463
464
465#define vdec_dw_spec2canvas(x) \
466 (((x)->vdec_dw_v_canvas_index << 16) | \
467 ((x)->vdec_dw_u_canvas_index << 8) | \
468 ((x)->vdec_dw_y_canvas_index << 0))
469
470
471#define spec2canvas(x) \
472 (((x)->v_canvas_index << 16) | \
473 ((x)->u_canvas_index << 8) | \
474 ((x)->y_canvas_index << 0))
475
476#define FRAME_INDEX(vf_index) (vf_index & 0xff)
477#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
478#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
479
480static struct vframe_s *vh264_vf_peek(void *);
481static struct vframe_s *vh264_vf_get(void *);
482static void vh264_vf_put(struct vframe_s *, void *);
483static int vh264_vf_states(struct vframe_states *states, void *);
484static int vh264_event_cb(int type, void *data, void *private_data);
485static void vh264_work(struct work_struct *work);
486static void vh264_timeout_work(struct work_struct *work);
487static void vh264_notify_work(struct work_struct *work);
488#ifdef MH264_USERDATA_ENABLE
489static void user_data_ready_notify_work(struct work_struct *work);
490static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
491#endif
492
493static const char vh264_dec_id[] = "vh264-dev";
494
495#define PROVIDER_NAME "vdec.h264"
496
497static const struct vframe_operations_s vf_provider_ops = {
498 .peek = vh264_vf_peek,
499 .get = vh264_vf_get,
500 .put = vh264_vf_put,
501 .event_cb = vh264_event_cb,
502 .vf_states = vh264_vf_states,
503};
504
505#define DEC_RESULT_NONE 0
506#define DEC_RESULT_DONE 1
507#define DEC_RESULT_AGAIN 2
508#define DEC_RESULT_CONFIG_PARAM 3
509#define DEC_RESULT_GET_DATA 4
510#define DEC_RESULT_GET_DATA_RETRY 5
511#define DEC_RESULT_ERROR 6
512#define DEC_RESULT_EOS 7
513#define DEC_RESULT_FORCE_EXIT 8
514
515/*
516 *static const char *dec_result_str[] = {
517 * "DEC_RESULT_NONE ",
518 * "DEC_RESULT_DONE ",
519 * "DEC_RESULT_AGAIN ",
520 * "DEC_RESULT_CONFIG_PARAM",
521 * "DEC_RESULT_GET_DATA ",
522 * "DEC_RESULT_GET_DA_RETRY",
523 * "DEC_RESULT_ERROR ",
524 *};
525 */
526
527#define UCODE_IP_ONLY 2
528#define UCODE_IP_ONLY_PARAM 1
529
530#define MC_OFFSET_HEADER 0x0000
531#define MC_OFFSET_DATA 0x1000
532#define MC_OFFSET_MMCO 0x2000
533#define MC_OFFSET_LIST 0x3000
534#define MC_OFFSET_SLICE 0x4000
535#define MC_OFFSET_MAIN 0x5000
536
537#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
538#define MC_SWAP_SIZE (4*SZ_1K)
539#define MODE_ERROR 0
540#define MODE_FULL 1
541
542#define DFS_HIGH_THEASHOLD 3
543
544#define INIT_FLAG_REG AV_SCRATCH_2
545#define HEAD_PADING_REG AV_SCRATCH_3
546#define UCODE_WATCHDOG_REG AV_SCRATCH_7
547#define LMEM_DUMP_ADR AV_SCRATCH_L
548#define DEBUG_REG1 AV_SCRATCH_M
549#define DEBUG_REG2 AV_SCRATCH_N
550#define FRAME_COUNTER_REG AV_SCRATCH_I
551#define RPM_CMD_REG AV_SCRATCH_A
552#define H264_DECODE_SIZE AV_SCRATCH_E
553#define H264_DECODE_MODE AV_SCRATCH_4
554#define H264_DECODE_SEQINFO AV_SCRATCH_5
555#define H264_AUX_ADR AV_SCRATCH_C
556#define H264_AUX_DATA_SIZE AV_SCRATCH_H
557
558#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
559#define DPB_STATUS_REG AV_SCRATCH_J
560#define ERROR_STATUS_REG AV_SCRATCH_9
561 /*
562 NAL_SEARCH_CTL: bit 0, enable itu_t35
563 NAL_SEARCH_CTL: bit 1, enable mmu
564 */
565#define NAL_SEARCH_CTL AV_SCRATCH_9
566#define MBY_MBX MB_MOTION_MODE /*0xc07*/
567
568#define DECODE_MODE_SINGLE 0x0
569#define DECODE_MODE_MULTI_FRAMEBASE 0x1
570#define DECODE_MODE_MULTI_STREAMBASE 0x2
571#define DECODE_MODE_MULTI_DVBAL 0x3
572#define DECODE_MODE_MULTI_DVENL 0x4
573static DEFINE_MUTEX(vmh264_mutex);
574
575
576
577#ifdef MH264_USERDATA_ENABLE
578
579struct mh264_userdata_record_t {
580 struct userdata_meta_info_t meta_info;
581 u32 rec_start;
582 u32 rec_len;
583};
584
585struct mh264_ud_record_wait_node_t {
586 struct list_head list;
587 struct mh264_userdata_record_t ud_record;
588};
589#define USERDATA_FIFO_NUM 256
590#define MAX_FREE_USERDATA_NODES 5
591
592struct mh264_userdata_info_t {
593 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
594 u8 *data_buf;
595 u8 *data_buf_end;
596 u32 buf_len;
597 u32 read_index;
598 u32 write_index;
599 u32 last_wp;
600};
601
602
603#endif
604
605struct vdec_h264_hw_s {
606 spinlock_t lock;
607 spinlock_t bufspec_lock;
608 int id;
609 struct platform_device *platform_dev;
610 unsigned long cma_alloc_addr;
611 /* struct page *collocate_cma_alloc_pages; */
612 unsigned long collocate_cma_alloc_addr;
613
614 u32 prefix_aux_size;
615 u32 suffix_aux_size;
616 void *aux_addr;
617 dma_addr_t aux_phy_addr;
618
619 /* buffer for store all sei data */
620 void *sei_data_buf;
621 u32 sei_data_len;
622
623 /* buffer for storing one itu35 recored */
624 void *sei_itu_data_buf;
625 u32 sei_itu_data_len;
626
627 /* recycle buffer for user data storing all itu35 records */
628 void *sei_user_data_buffer;
629 u32 sei_user_data_wp;
630#ifdef MH264_USERDATA_ENABLE
631 struct work_struct user_data_ready_work;
632#endif
633 struct StorablePicture *last_dec_picture;
634
635 ulong lmem_addr;
636 dma_addr_t lmem_addr_remap;
637
638 void *bmmu_box;
639#ifdef H264_MMU
640 void *mmu_box;
641 void *frame_mmu_map_addr;
642 dma_addr_t frame_mmu_map_phy_addr;
643 u32 hevc_cur_buf_idx;
644 u32 losless_comp_body_size;
645 u32 losless_comp_body_size_sao;
646 u32 losless_comp_header_size;
647 u32 mc_buffer_size_u_v;
648 u32 mc_buffer_size_u_v_h;
649 u32 is_idr_frame;
650 u32 is_new_pic;
651 u32 frame_done;
652 u32 frame_busy;
653 unsigned long extif_addr;
654 int double_write_mode;
655 int mmu_enable;
656#endif
657
658 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
659 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
660
661 int cur_pool;
662 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
663 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
664 struct vframe_s switching_fense_vf;
665 struct h264_dpb_stru dpb;
666 u8 init_flag;
667 u8 first_sc_checked;
668 u8 has_i_frame;
669 u8 config_bufmgr_done;
670 u32 max_reference_size;
671 u32 decode_pic_count;
672 u32 reflist_error_count;
673 int start_search_pos;
674 u32 reg_iqidct_control;
675 u32 reg_vcop_ctrl_reg;
676 u32 reg_rv_ai_mb_count;
677 u32 vld_dec_control;
678 struct vframe_s vframe_dummy;
679
680 unsigned char buffer_empty_flag;
681
682 u32 frame_width;
683 u32 frame_height;
684 u32 frame_dur;
685 u32 frame_prog;
686 u32 frame_packing_type;
687
688 struct vframe_chunk_s *chunk;
689
690 u32 stat;
691 unsigned long buf_start;
692 u32 buf_offset;
693 u32 buf_size;
694 /* u32 ucode_map_start; */
695 u32 pts_outside;
696 u32 sync_outside;
697 u32 vh264_ratio;
698 u32 vh264_rotation;
699 u32 use_idr_framerate;
700
701 u32 seq_info;
702 u32 seq_info2;
703 u32 video_signal_from_vui; /*to do .. */
704 u32 timing_info_present_flag;
705 u32 fixed_frame_rate_flag;
706 u32 bitstream_restriction_flag;
707 u32 num_reorder_frames;
708 u32 max_dec_frame_buffering;
709 u32 iframe_count;
710 u32 aspect_ratio_info;
711 u32 num_units_in_tick;
712 u32 time_scale;
713 u32 h264_ar;
714 bool h264_first_valid_pts_ready;
715 u32 h264pts1;
716 u32 h264pts2;
717 u32 pts_duration;
718 u32 h264_pts_count;
719 u32 duration_from_pts_done;
720 u32 pts_unstable;
721 u32 unstable_pts;
722 u32 last_checkout_pts;
723 u32 max_refer_buf;
724
725 s32 vh264_stream_switching_state;
726 struct vframe_s *p_last_vf;
727 u32 last_pts;
728 u32 last_pts_remainder;
729 u32 last_duration;
730 u32 last_mb_width, last_mb_height;
731 bool check_pts_discontinue;
732 bool pts_discontinue;
733 u32 wait_buffer_counter;
734 u32 first_offset;
735 u32 first_pts;
736 u64 first_pts64;
737 bool first_pts_cached;
738 u64 last_pts64;
739#if 0
740 void *sei_data_buffer;
741 dma_addr_t sei_data_buffer_phys;
742#endif
743
744 uint error_recovery_mode;
745 uint mb_total;
746 uint mb_width;
747 uint mb_height;
748
749 uint i_only;
750 int skip_frame_count;
751 bool no_poc_reorder_flag;
752 bool send_error_frame_flag;
753 dma_addr_t mc_dma_handle;
754 void *mc_cpu_addr;
755 int vh264_reset;
756
757 atomic_t vh264_active;
758
759 struct dec_sysinfo vh264_amstream_dec_info;
760
761 int dec_result;
762 struct work_struct work;
763 struct work_struct notify_work;
764 struct work_struct timeout_work;
765 void (*vdec_cb)(struct vdec_s *, void *);
766 void *vdec_cb_arg;
767
768 struct timer_list check_timer;
769
770 /**/
771 unsigned int last_frame_time;
772 u32 vf_pre_count;
773 u32 vf_get_count;
774 u32 vf_put_count;
775
776 /* timeout handle */
777 unsigned long int start_process_time;
778 unsigned int last_mby_mbx;
779 unsigned int last_vld_level;
780 unsigned int decode_timeout_count;
781 unsigned int timeout_num;
782 unsigned int search_dataempty_num;
783 unsigned int decode_timeout_num;
784 unsigned int decode_dataempty_num;
785 unsigned int buffer_empty_recover_num;
786
787 unsigned get_data_count;
788 unsigned get_data_start_time;
789 /**/
790
791 /*log*/
792 unsigned int packet_write_success_count;
793 unsigned int packet_write_EAGAIN_count;
794 unsigned int packet_write_ENOMEM_count;
795 unsigned int packet_write_EFAULT_count;
796 unsigned int total_read_size_pre;
797 unsigned int total_read_size;
798 unsigned int frame_count_pre;
799#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
800 u8 switch_dvlayer_flag;
801 u8 got_valid_nal;
802#endif
803 u8 eos;
804 u8 data_flag;
805 u32 no_error_count;
806 u32 no_error_i_count;
807 /*
808 NODISP_FLAG
809 */
810 u8 dec_flag;
811
812 u32 ucode_pause_pos;
813
814 u8 reset_bufmgr_flag;
815 u32 reset_bufmgr_count;
816 u32 cfg_param1;
817 u32 cfg_param2;
818 u32 cfg_param3;
819 u32 cfg_param4;
820 int valve_count;
821 u8 next_again_flag;
822 u32 pre_parser_wr_ptr;
823 struct firmware_s *fw;
824 struct firmware_s *fw_mmu;
825#ifdef MH264_USERDATA_ENABLE
826 /*user data*/
827 struct mutex userdata_mutex;
828 struct mh264_userdata_info_t userdata_info;
829 struct mh264_userdata_record_t ud_record;
830 int wait_for_udr_send;
831#endif
832 u32 no_mem_count;
833 u32 canvas_mode;
834 bool is_used_v4l;
835 void *v4l2_ctx;
836 wait_queue_head_t wait_q;
837 u32 reg_g_status;
838 struct mutex chunks_mutex;
839 int need_cache_size;
840 u64 sc_start_time;
841 u8 frmbase_cont_flag;
842 struct vframe_qos_s vframe_qos;
843 int frameinfo_enable;
844 bool first_head_check_flag;
845 unsigned int height_aspect_ratio;
846 unsigned int width_aspect_ratio;
847 bool new_iframe_flag;
848 bool ref_err_flush_dpb_flag;
849 unsigned int first_i_policy;
850 u32 tfn_cnt;
851 u64 tfn_ns;
852};
853
854static u32 again_threshold;
855
856static void timeout_process(struct vdec_h264_hw_s *hw);
857static void dump_bufspec(struct vdec_h264_hw_s *hw,
858 const char *caller);
859static void h264_reconfig(struct vdec_h264_hw_s *hw);
860static void h264_reset_bufmgr(struct vdec_s *vdec);
861static void vh264_local_init(struct vdec_h264_hw_s *hw);
862static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
863static int vh264_stop(struct vdec_h264_hw_s *hw);
864static s32 vh264_init(struct vdec_h264_hw_s *hw);
865static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
866 u32 index);
867static void release_aux_data(struct vdec_h264_hw_s *hw,
868 int buf_spec_num);
869#ifdef ERROR_HANDLE_TEST
870static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
871#endif
872
873#define H265_PUT_SAO_4K_SET 0x03
874#define H265_ABORT_SAO_4K_SET 0x04
875#define H265_ABORT_SAO_4K_SET_DONE 0x05
876
877#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
878#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
879#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
880#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
881#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
882
883
884#define HEVC_CM_HEADER_START_ADDR 0x3628
885#define HEVC_CM_BODY_START_ADDR 0x3626
886#define HEVC_CM_BODY_LENGTH 0x3627
887#define HEVC_CM_HEADER_LENGTH 0x3629
888#define HEVC_CM_HEADER_OFFSET 0x362b
889#define HEVC_SAO_CTRL9 0x362d
890#define HEVCD_MPP_DECOMP_CTL3 0x34c4
891#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
892#define HEVC_DBLK_CFGB 0x350b
893#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
894
895#define H265_DW_NO_SCALE
896#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
897#define H265_LOSLESS_COMPRESS_MODE
898#define MAX_FRAME_4K_NUM 0x1200
899#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
900
901/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
902static u32 mem_map_mode = H265_MEM_MAP_MODE;
903
904#define MAX_SIZE_8K (8192 * 4608)
905#define MAX_SIZE_4K (4096 * 2304)
906
907static int is_oversize(int w, int h)
908{
909 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
910 MAX_SIZE_8K : MAX_SIZE_4K;
911
912 if (w < 0 || h < 0)
913 return true;
914
915 if (h != 0 && (w > max / h))
916 return true;
917
918 return false;
919}
920
921static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
922 int frame_type,
923 u32 vpts,
924 u32 vpts_valid);
925static int compute_losless_comp_body_size(int width,
926 int height, int bit_depth_10);
927static int compute_losless_comp_header_size(int width, int height);
928
929static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
930 int pic_width, int pic_height, u16 bit_depth,
931 unsigned int *mmu_index_adr) {
932 int cur_buf_idx;
933 int bit_depth_10 = (bit_depth != 0x00);
934 int picture_size;
935 u32 cur_mmu_4k_number;
936
937 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
938 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
939 picture_size = compute_losless_comp_body_size(pic_width,
940 pic_height, bit_depth_10);
941 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
942 dpb_print(DECODE_ID(hw),
943 PRINT_FLAG_MMU_DETAIL,
944 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
945 cur_buf_idx, picture_size, cur_mmu_4k_number);
946
947 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
948 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
949 cur_mmu_4k_number);
950 return -1;
951 }
952
953 return decoder_mmu_box_alloc_idx(
954 hw->mmu_box,
955 cur_buf_idx,
956 cur_mmu_4k_number,
957 mmu_index_adr);
958
959}
960
961static int compute_losless_comp_body_size(int width,
962 int height, int bit_depth_10)
963{
964 int width_x64;
965 int height_x32;
966 int bsize;
967
968 width_x64 = width + 63;
969 width_x64 >>= 6;
970
971 height_x32 = height + 31;
972 height_x32 >>= 5;
973
974#ifdef H264_MMU
975 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
976#else
977 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
978#endif
979 return bsize;
980}
981
982static int compute_losless_comp_header_size(int width, int height)
983{
984 int width_x64;
985 int width_x128;
986 int height_x64;
987 int hsize;
988
989 width_x64 = width + 63;
990 width_x64 >>= 6;
991
992 width_x128 = width + 127;
993 width_x128 >>= 7;
994
995 height_x64 = height + 63;
996 height_x64 >>= 6;
997
998#ifdef H264_MMU
999 hsize = 128*width_x64*height_x64;
1000#else
1001 hsize = 32*width_x128*height_x64;
1002#endif
1003 return hsize;
1004}
1005
1006static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1007{
1008 int ratio = 1;
1009 int dw_mode = hw->double_write_mode;
1010 if ((dw_mode == 2) ||
1011 (dw_mode == 3))
1012 ratio = 4;
1013 else if (dw_mode == 4)
1014 ratio = 2;
1015 return ratio;
1016}
1017
1018
1019static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1020{
1021 int pic_width, pic_height;
1022 int lcu_size = 16;
1023 int dw_buf_size;
1024 u32 dw_buffer_size_u_v;
1025 u32 dw_buffer_size_u_v_h;
1026 int dw_mode = hw->double_write_mode;
1027
1028 pic_width = hw->frame_width;
1029 pic_height = hw->frame_height;
1030
1031 if (dw_mode) {
1032 int pic_width_dw = pic_width /
1033 get_double_write_ratio(hw);
1034 int pic_height_dw = pic_height /
1035 get_double_write_ratio(hw);
1036
1037 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1038 pic_width_dw / lcu_size + 1 :
1039 pic_width_dw / lcu_size;
1040 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1041 pic_height_dw / lcu_size + 1 :
1042 pic_height_dw / lcu_size;
1043 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1044
1045
1046 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1047 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1048 /*64k alignment*/
1049 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1050 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1051 } else {
1052 *pdw_buffer_size_u_v_h = 0;
1053 dw_buf_size = 0;
1054 }
1055
1056 return dw_buf_size;
1057}
1058
1059
1060static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1061{
1062 int i, size;
1063 u32 canvas_addr;
1064 unsigned long maddr;
1065 int num_buff = hw->dpb.mDPB.size;
1066 int dw_size = 0;
1067 u32 dw_buffer_size_u_v_h;
1068 u32 blkmode = mem_map_mode;
1069 int dw_mode = hw->double_write_mode;
1070
1071 canvas_addr = ANC0_CANVAS_ADDR;
1072 for (i = 0; i < num_buff; i++)
1073 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1074
1075 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1076 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1077
1078
1079 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1080 size += dw_size;
1081 if (size > 0)
1082 size += 0x10000;
1083
1084 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1085 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1086 dw_buffer_size_u_v_h, dw_size, size);
1087
1088 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1089 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1090 hw->losless_comp_body_size,
1091 hw->losless_comp_header_size,
1092 hw->losless_comp_body_size_sao);
1093
1094 for (i = 0; i < num_buff; i++) {
1095 if (!restore) {
1096 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1097 HEADER_BUFFER_IDX(i), size,
1098 DRIVER_HEADER_NAME, &maddr) < 0) {
1099 dpb_print(DECODE_ID(hw), 0,
1100 "%s malloc compress header failed %d\n",
1101 DRIVER_HEADER_NAME, i);
1102 return;
1103 }
1104 } else
1105 maddr = hw->buffer_spec[i].alloc_header_addr;
1106 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1107 hw->buffer_spec[i].alloc_header_addr = maddr;
1108 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1109 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1110 __func__, i, (u32)maddr, size);
1111
1112 if (dw_mode) {
1113 u32 addr;
1114 int canvas_w;
1115 int canvas_h;
1116
1117 canvas_w = hw->frame_width /
1118 get_double_write_ratio(hw);
1119 canvas_h = hw->frame_height /
1120 get_double_write_ratio(hw);
1121
1122 if (mem_map_mode == 0)
1123 canvas_w = ALIGN(canvas_w, 32);
1124 else
1125 canvas_w = ALIGN(canvas_w, 64);
1126 canvas_h = ALIGN(canvas_h, 32);
1127
1128 hw->buffer_spec[i].dw_y_adr =
1129 maddr + hw->losless_comp_header_size;
1130
1131 hw->buffer_spec[i].dw_y_adr =
1132 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1133 << 16;
1134 hw->buffer_spec[i].dw_u_v_adr =
1135 hw->buffer_spec[i].dw_y_adr
1136 + (dw_buffer_size_u_v_h << 16) * 2;
1137
1138
1139 hw->buffer_spec[i].buf_adr
1140 = hw->buffer_spec[i].dw_y_adr;
1141 addr = hw->buffer_spec[i].buf_adr;
1142
1143
1144 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1145 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1146 hw->buffer_spec[i].dw_y_adr,
1147 hw->buffer_spec[i].dw_u_v_adr,
1148 hw->buffer_spec[i].y_addr,
1149 hw->buffer_spec[i].u_addr,
1150 hw->buffer_spec[i].v_addr,
1151 canvas_w,
1152 canvas_h);
1153
1154 hw->buffer_spec[i].canvas_config[0].phy_addr =
1155 hw->buffer_spec[i].dw_y_adr;
1156 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1157 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1158 hw->buffer_spec[i].canvas_config[0].block_mode =
1159 blkmode;
1160 hw->buffer_spec[i].canvas_config[0].endian = 7;
1161
1162 hw->buffer_spec[i].canvas_config[1].phy_addr =
1163 hw->buffer_spec[i].dw_u_v_adr;
1164 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1165 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1166 hw->buffer_spec[i].canvas_config[1].block_mode =
1167 blkmode;
1168 hw->buffer_spec[i].canvas_config[1].endian = 7;
1169 }
1170 }
1171 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1172
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1174 for (i = 0; i < 32; i++)
1175 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1176 return;
1177}
1178static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1179{
1180 u32 i;
1181 u32 ref_canv;
1182 struct Slice *pSlice = &(hw->dpb.mSlice);
1183 /*REFLIST[0]*/
1184 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1185 struct StorablePicture *ref = pSlice->listX[0][i];
1186 if (ref == NULL)
1187 return;
1188 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1189 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1191 (ref->buf_spec_num & 0x3f) << 8);
1192 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1193 }
1194 /*REFLIST[1]*/
1195 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1196 struct StorablePicture *ref = pSlice->listX[1][i];
1197 if (ref == NULL)
1198 return;
1199 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1200 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1202 (ref->buf_spec_num & 0x3f) << 8);
1203 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1204 }
1205 return;
1206}
1207
1208static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1209{
1210 u32 rdata32;
1211 u32 rdata32_2;
1212 u32 slice_type;
1213 struct StorablePicture *ref;
1214 struct Slice *pSlice;
1215 slice_type = hw->dpb.mSlice.slice_type;
1216 pSlice = &(hw->dpb.mSlice);
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1218 if (slice_type == I_SLICE) {
1219 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1220 return;
1221 }
1222 if (slice_type == B_SLICE) {
1223 ref = pSlice->listX[0][0];
1224 if (ref == NULL)
1225 return;
1226 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1227 ((ref->buf_spec_num & 0x3f) << 8));
1228 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1229 rdata32 = rdata32 & 0xffff;
1230 rdata32 = rdata32 | (rdata32 << 16);
1231 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1232
1233 ref = pSlice->listX[1][0];
1234 if (ref == NULL)
1235 return;
1236 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1237 ((ref->buf_spec_num & 0x3f) << 8));
1238 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1239 rdata32_2 = rdata32_2 & 0xffff;
1240 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1241 if (rdata32 == rdata32_2) {
1242 ref = pSlice->listX[1][1];
1243 if (ref == NULL)
1244 return;
1245 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1246 ((ref->buf_spec_num & 0x3f) << 8));
1247 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1248 rdata32_2 = rdata32_2 & 0xffff;
1249 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1250 }
1251 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1252 } else { /*P-PIC*/
1253 ref = pSlice->listX[0][0];
1254 if (ref == NULL)
1255 return;
1256 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1257 ((ref->buf_spec_num & 0x3f) << 8));
1258 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1259 rdata32 = rdata32 & 0xffff;
1260 rdata32 = rdata32 | (rdata32 << 16);
1261 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1262
1263 ref = pSlice->listX[0][1];
1264 if (ref == NULL)
1265 return;
1266 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1267 ((ref->buf_spec_num & 0x3f) << 8));
1268 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1269 rdata32 = rdata32 & 0xffff;
1270 rdata32 = rdata32 | (rdata32 << 16);
1271 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1272 }
1273 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1274 return;
1275}
1276
1277
1278static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1279 u32 width, u32 height) {
1280 u32 data32;
1281 u32 lcu_x_num, lcu_y_num;
1282 u32 lcu_total;
1283 u32 mc_buffer_size_u_v;
1284 u32 mc_buffer_size_u_v_h;
1285 int dw_mode = hw->double_write_mode;
1286
1287 lcu_x_num = (width + 15) >> 4;
1288 lcu_y_num = (height + 15) >> 4;
1289 lcu_total = lcu_x_num * lcu_y_num;
1290
1291 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1292 hw->mc_buffer_size_u_v_h =
1293 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1294
1295 hw->losless_comp_body_size = 0;
1296
1297 hw->losless_comp_body_size_sao =
1298 compute_losless_comp_body_size(width, height, 0);
1299 hw->losless_comp_header_size =
1300 compute_losless_comp_header_size(width, height);
1301
1302 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1303 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1304
1305 /* setup lcu_size = 16*/
1306 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1307 /*pic_width/pic_height*/
1308 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1309 (height & 0xffff) << 16 | (width & 0xffff));
1310 /* bitdepth_luma = 8*/
1311 /* bitdepth_chroma = 8*/
1312 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1313
1314#ifdef H265_LOSLESS_COMPRESS_MODE
1315 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1317#else
1318 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1319#endif
1320 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1321 data32 &= (~0x30);
1322 data32 |= (mem_map_mode << 4);
1323 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1324
1325 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1326 (0x80 << 20) | (0x80 << 10) | (0xff));
1327
1328 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1329
1330 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1331 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1332 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1333 /* ipp_enable*/
1334 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1335
1336 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1337 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1338 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1339 if (dw_mode)
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1341 else
1342 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1343 }
1344
1345 data32 = READ_VREG(HEVC_SAO_CTRL0);
1346 data32 &= (~0xf);
1347 data32 |= 0x4;
1348 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1349 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1350 (width & 0xffff));
1351 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1352
1353 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1354 data32 = (lcu_x_num | lcu_y_num << 16);
1355 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1357 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1358 data32 = (mc_buffer_size_u_v_h << 16);
1359 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1360
1361 data32 = READ_VREG(HEVC_SAO_CTRL1);
1362 data32 &= (~0x3000);
1363 data32 &= (~0xff0);
1364 data32 |= endian; /* Big-Endian per 64-bit */
1365
1366 if (hw->mmu_enable && dw_mode)
1367 data32 |= ((mem_map_mode << 12));
1368 else
1369 data32 |= ((mem_map_mode << 12)|2);
1370
1371 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1372
1373#ifdef H265_DW_NO_SCALE
1374 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1375 if (hw->mmu_enable && dw_mode) {
1376 data32 = READ_VREG(HEVC_SAO_CTRL5);
1377 data32 &= (~(0xff << 16));
1378 if (dw_mode == 2 ||
1379 dw_mode == 3)
1380 data32 |= (0xff<<16);
1381 else if (dw_mode == 4)
1382 data32 |= (0x33<<16);
1383 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1384 }
1385
1386
1387#endif
1388
1389
1390#ifdef H265_LOSLESS_COMPRESS_MODE
1391 data32 = READ_VREG(HEVC_SAO_CTRL5);
1392 data32 |= (1<<9); /*8-bit smem-mode*/
1393 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1394
1395 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1396 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1397 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1398#endif
1399
1400#ifdef H265_LOSLESS_COMPRESS_MODE
1401 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1402 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1403#endif
1404
1405 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1406
1407 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1408
1409 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1410 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1411 return;
1412}
1413
1414static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1415 u32 is_new_pic, u32 is_idr)
1416{
1417 hw->is_new_pic = is_new_pic;
1418 hw->is_idr_frame = is_idr;
1419 return;
1420}
1421
1422static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1423 struct StorablePicture *pic) {
1424 u32 mc_y_adr;
1425 u32 mc_u_v_adr;
1426 u32 dw_y_adr;
1427 u32 dw_u_v_adr;
1428 u32 canvas_addr;
1429 int ret;
1430 int dw_mode = hw->double_write_mode;
1431 if (hw->is_new_pic != 1)
1432 return;
1433
1434 if (hw->is_idr_frame) {
1435 /* William TBD */
1436 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1437 }
1438
1439 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1440 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1441 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1442 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1443 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1444 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1445 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1446 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1447 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1448
1449
1450 if (dw_mode) {
1451 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1452 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1453 } else {
1454 dw_y_adr = 0;
1455 dw_u_v_adr = 0;
1456 }
1457#ifdef H265_LOSLESS_COMPRESS_MODE
1458 if (dw_mode)
1459 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1460 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1461#ifdef H264_MMU
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1463#else
1464 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1465 (mc_y_adr + hw->losless_comp_body_size));
1466#endif
1467#else
1468 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1469#endif
1470
1471#ifndef H265_LOSLESS_COMPRESS_MODE
1472 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1473#else
1474 if (dw_mode)
1475 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1476#endif
1477
1478#ifndef LOSLESS_COMPRESS_MODE
1479 if (dw_mode) {
1480 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1481 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1482 }
1483#else
1484 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1485 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1486#endif
1487
1488 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1489 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1490 hw->frame_mmu_map_addr);
1491 if (ret != 0) {
1492 dpb_print(DECODE_ID(hw),
1493 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1494 pic->buf_spec_num,
1495 ret);
1496 return;
1497 }
1498
1499 /*Reset SAO + Enable SAO slice_start*/
1500 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1501 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1504 WRITE_VREG(HEVC_SAO_INT_STATUS,
1505 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1506 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1507 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1508
1509 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1510 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1511 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1512 } else
1513 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1514 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1515 hw->frame_busy = 1;
1516 return;
1517}
1518
1519
1520static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1521 u32 buf_spec_num) {
1522 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1523 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1524 dpb_print(DECODE_ID(hw),
1525 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1526 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1527 return;
1528}
1529
1530
1531static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1532{
1533 ulong timeout = jiffies + HZ;
1534 dpb_print(DECODE_ID(hw),
1535 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1536 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1537 if (time_after(jiffies, timeout)) {
1538 dpb_print(DECODE_ID(hw),
1539 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1540 break;
1541 }
1542 }
1543 timeout = jiffies + HZ;
1544 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1545 if (time_after(jiffies, timeout)) {
1546 dpb_print(DECODE_ID(hw),
1547 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1548 break;
1549 }
1550 }
1551 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1552 hw->frame_done = 1;
1553 return;
1554}
1555
1556static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1557{
1558 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1559 if (p_H264_Dpb->mVideo.dec_picture) {
1560 release_picture(p_H264_Dpb,
1561 p_H264_Dpb->mVideo.dec_picture);
1562 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1563 p_H264_Dpb->mVideo.dec_picture = NULL;
1564 if (hw->mmu_enable)
1565 hevc_set_frame_done(hw);
1566 }
1567}
1568
1569static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1570{
1571 ulong timeout = jiffies + HZ;
1572 dpb_print(DECODE_ID(hw),
1573 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1574 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1575 if (time_after(jiffies, timeout)) {
1576 dpb_print(DECODE_ID(hw),
1577 PRINT_FLAG_MMU_DETAIL,
1578 "hevc_sao_wait_done...wait timeout!\n");
1579 break;
1580 }
1581 }
1582 timeout = jiffies + HZ;
1583 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1584 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1585 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1586 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1587 H265_ABORT_SAO_4K_SET_DONE) {
1588 if (time_after(jiffies, timeout)) {
1589 dpb_print(DECODE_ID(hw),
1590 PRINT_FLAG_MMU_DETAIL,
1591 "wait h265_abort_sao_4k_set_done timeout!\n");
1592 break;
1593 }
1594 }
1595 }
1596 amhevc_stop();
1597 hw->frame_busy = 0;
1598 hw->frame_done = 0;
1599 dpb_print(DECODE_ID(hw),
1600 PRINT_FLAG_MMU_DETAIL,
1601 "sao wait done ,hevc stop!\n");
1602 }
1603 return;
1604}
1605static void buf_spec_init(struct vdec_h264_hw_s *hw)
1606{
1607 int i;
1608 unsigned long flags;
1609 spin_lock_irqsave(&hw->bufspec_lock, flags);
1610 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1611 hw->buffer_spec[i].used = -1;
1612 hw->buffer_spec[i].canvas_pos = -1;
1613 }
1614 if (dpb_is_debug(DECODE_ID(hw),
1615 PRINT_FLAG_DUMP_BUFSPEC))
1616 dump_bufspec(hw, __func__);
1617 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1618}
1619
1620/*is active in buf management */
1621static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1622 int buf_spec_num)
1623{
1624 unsigned char ret = 0;
1625 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1626 hw->buffer_spec[buf_spec_num].used == 2 ||
1627 hw->buffer_spec[buf_spec_num].used == 3 ||
1628 hw->buffer_spec[buf_spec_num].used == 5)
1629 ret = 1;
1630 return ret;
1631}
1632
1633static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1634 int buf_spec_num)
1635{
1636 unsigned char ret = 0;
1637 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1638 hw->buffer_spec[buf_spec_num].used == 3 ||
1639 hw->buffer_spec[buf_spec_num].used == 5)
1640 ret = 1;
1641 return ret;
1642}
1643
1644static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1645{
1646 if (hw->mmu_enable) {
1647 if (hw->buffer_spec[i].alloc_header_addr)
1648 return 0;
1649 else
1650 return -1;
1651 } else {
1652
1653 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1654 int addr;
1655#ifdef VDEC_DW
1656 int orig_buf_size;
1657 orig_buf_size = buf_size;
1658 if (IS_VDEC_DW(hw) == 1)
1659 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1660 else if (IS_VDEC_DW(hw) == 2)
1661 buf_size += (hw->mb_total << 6) + (hw->mb_total << 6);
1662#endif
1663 if (hw->buffer_spec[i].cma_alloc_addr)
1664 return 0;
1665
1666 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1667 PAGE_ALIGN(buf_size), DRIVER_NAME,
1668 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1669 hw->buffer_spec[i].cma_alloc_addr = 0;
1670 if (hw->no_mem_count++ > 3) {
1671 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1672 hw->reset_bufmgr_flag = 1;
1673 }
1674 dpb_print(DECODE_ID(hw), 0,
1675 "%s, fail to alloc buf for bufspec%d, try later\n",
1676 __func__, i
1677 );
1678 return -1;
1679 } else {
1680 hw->no_mem_count = 0;
1681 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1682 }
1683
1684 hw->buffer_spec[i].buf_adr =
1685 hw->buffer_spec[i].cma_alloc_addr;
1686 addr = hw->buffer_spec[i].buf_adr;
1687
1688
1689 hw->buffer_spec[i].y_addr = addr;
1690 addr += hw->mb_total << 8;
1691 hw->buffer_spec[i].u_addr = addr;
1692 hw->buffer_spec[i].v_addr = addr;
1693 addr += hw->mb_total << 7;
1694
1695 hw->buffer_spec[i].canvas_config[0].phy_addr =
1696 hw->buffer_spec[i].y_addr;
1697 hw->buffer_spec[i].canvas_config[0].width =
1698 hw->mb_width << 4;
1699 hw->buffer_spec[i].canvas_config[0].height =
1700 hw->mb_height << 4;
1701 hw->buffer_spec[i].canvas_config[0].block_mode =
1702 hw->canvas_mode;
1703
1704 hw->buffer_spec[i].canvas_config[1].phy_addr =
1705 hw->buffer_spec[i].u_addr;
1706 hw->buffer_spec[i].canvas_config[1].width =
1707 hw->mb_width << 4;
1708 hw->buffer_spec[i].canvas_config[1].height =
1709 hw->mb_height << 3;
1710 hw->buffer_spec[i].canvas_config[1].block_mode =
1711 hw->canvas_mode;
1712 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1713 "%s, alloc buf for bufspec%d\n",
1714 __func__, i
1715 );
1716#ifdef VDEC_DW
1717
1718 if (!IS_VDEC_DW(hw))
1719 return 0;
1720 else if (IS_VDEC_DW(hw) == 1) {
1721 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1722 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1723 addr += hw->mb_total << 7;
1724 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1725 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1726 addr += hw->mb_total << 6;
1727
1728 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1729 hw->buffer_spec[i].vdec_dw_y_addr;
1730 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1731 hw->mb_width << 3;
1732 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1733 hw->mb_height << 4;
1734 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1735 CANVAS_BLKMODE_32X32;
1736
1737 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1738 hw->buffer_spec[i].vdec_dw_u_addr;
1739 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1740 hw->mb_width << 3;
1741 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1742 hw->mb_height << 3;
1743 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1744 CANVAS_BLKMODE_32X32;
1745 }else {
1746 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1747 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1748 addr += hw->mb_total << 6;
1749 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1750 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1751 addr += hw->mb_total << 5;
1752
1753 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1754 hw->buffer_spec[i].vdec_dw_y_addr;
1755 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1756 hw->mb_width << 3;
1757 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1758 hw->mb_height << 3;
1759 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1760 CANVAS_BLKMODE_32X32;
1761
1762 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1763 hw->buffer_spec[i].vdec_dw_u_addr;
1764 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1765 hw->mb_width << 3;
1766 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1767 hw->mb_height << 2;
1768 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1769 CANVAS_BLKMODE_32X32;
1770 }
1771 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1772 "%s, vdec_dw: alloc buf for bufspec%d\n",
1773 __func__, i
1774 );
1775#endif
1776 }
1777 return 0;
1778}
1779
1780static int v4l_get_fb(struct aml_vcodec_ctx *ctx, struct vdec_fb **out)
1781{
1782 int ret = 0;
1783
1784 ret = ctx->dec_if->get_param(ctx->drv_handle,
1785 GET_PARAM_FREE_FRAME_BUFFER, out);
1786
1787 return ret;
1788}
1789
1790static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1791{
1792 int ret = 0;
1793 struct aml_vcodec_ctx *ctx = NULL;
1794 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1795 struct canvas_config_s *y_canvas_cfg = NULL;
1796 struct canvas_config_s *c_canvas_cfg = NULL;
1797 struct vdec_fb *fb = NULL;
1798 unsigned int y_addr, c_addr;
1799
1800 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1801 pr_err("the v4l context has err.\n");
1802 return -1;
1803 }
1804
1805 if (bs->cma_alloc_addr)
1806 return 0;
1807
1808 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1809 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1810 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1811 ctx->id, __func__,
1812 (hw->mb_total << 8) + (hw->mb_total << 7));
1813
1814 ret = v4l_get_fb(hw->v4l2_ctx, &fb);
1815 if (ret) {
1816 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1817 "[%d] get fb fail.\n", ctx->id);
1818 return ret;
1819 }
1820
1821 bs->cma_alloc_addr = (unsigned long)fb;
1822 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1823 "[%d] %s(), cma alloc addr: 0x%x\n",
1824 ctx->id, __func__, bs->cma_alloc_addr);
1825
1826 y_addr = virt_to_phys(fb->base_y.va);
1827 c_addr = virt_to_phys(fb->base_c.va);
1828
1829 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1830 "[%d] %s(), y_addr: %x, va: %p\n",
1831 ctx->id, __func__, y_addr, fb->base_y.va);
1832 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1833 "[%d] %s(), c_addr: %x, va: %p\n",
1834 ctx->id, __func__, c_addr, fb->base_c.va);
1835
1836 bs->y_addr = y_addr;
1837 bs->u_addr = c_addr;
1838 bs->v_addr = c_addr;
1839
1840 y_canvas_cfg = &bs->canvas_config[0];
1841 c_canvas_cfg = &bs->canvas_config[1];
1842
1843 y_canvas_cfg->phy_addr = y_addr;
1844 y_canvas_cfg->width = hw->mb_width << 4;
1845 y_canvas_cfg->height = hw->mb_height << 4;
1846 y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1847 fb->base_y.bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1848 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1849 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1850 y_canvas_cfg->width,y_canvas_cfg->height);
1851
1852 c_canvas_cfg->phy_addr = c_addr;
1853 c_canvas_cfg->width = hw->mb_width << 4;
1854 c_canvas_cfg->height = hw->mb_height << 3;
1855 c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1856 fb->base_c.bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1857 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1858 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1859 c_canvas_cfg->width, c_canvas_cfg->height);
1860
1861 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1862 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1863
1864 return ret;
1865}
1866
1867static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1868{
1869 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
1870 int blkmode = CANVAS_BLKMODE_32X32;
1871 int endian = 0;
1872
1873 if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
1874 blkmode = CANVAS_BLKMODE_LINEAR;
1875 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1876 endian = 7;
1877 else
1878 endian = 0;
1879 }
1880
1881 if (hw->is_used_v4l) {
1882 blkmode = CANVAS_BLKMODE_LINEAR;
1883 if (v4l2_ctx->ada_ctx->vfm_path
1884 != FRAME_BASE_PATH_V4L_VIDEO)
1885 endian = 7;
1886 }
1887
1888 canvas_config_ex(hw->buffer_spec[i].
1889 y_canvas_index,
1890 hw->buffer_spec[i].y_addr,
1891 hw->mb_width << 4,
1892 hw->mb_height << 4,
1893 CANVAS_ADDR_NOWRAP,
1894 blkmode,
1895 endian);
1896
1897 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1898 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1899 (1 << 11) | /* canvas_blk32_wr */
1900 (blkmode << 10) | /* canvas_blk32*/
1901 (1 << 8) | /* canvas_index_wr*/
1902 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1903 );
1904 }
1905
1906 canvas_config_ex(hw->buffer_spec[i].
1907 u_canvas_index,
1908 hw->buffer_spec[i].u_addr,
1909 hw->mb_width << 4,
1910 hw->mb_height << 3,
1911 CANVAS_ADDR_NOWRAP,
1912 blkmode,
1913 endian);
1914
1915 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1916 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1917 (1 << 11) |
1918 (blkmode << 10) |
1919 (1 << 8) |
1920 (hw->buffer_spec[i].u_canvas_index << 0));
1921 }
1922
1923 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1924 spec2canvas(&hw->buffer_spec[i]));
1925
1926
1927#ifdef VDEC_DW
1928 if (!IS_VDEC_DW(hw))
1929 return;
1930 else if (IS_VDEC_DW(hw) == 1) {
1931 canvas_config_ex(hw->buffer_spec[i].
1932 vdec_dw_y_canvas_index,
1933 hw->buffer_spec[i].vdec_dw_y_addr,
1934 hw->mb_width << 3,
1935 hw->mb_height << 4,
1936 CANVAS_ADDR_NOWRAP,
1937 blkmode,
1938 endian);
1939 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1940 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1941 (1 << 11) |
1942 (blkmode << 10) |
1943 (1 << 8) |
1944 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1945 }
1946 canvas_config_ex(hw->buffer_spec[i].
1947 vdec_dw_u_canvas_index,
1948 hw->buffer_spec[i].vdec_dw_u_addr,
1949 hw->mb_width << 3,
1950 hw->mb_height << 3,
1951 CANVAS_ADDR_NOWRAP,
1952 blkmode,
1953 endian);
1954 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1955 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1956 (1 << 11) |
1957 (blkmode << 10) |
1958 (1 << 8) |
1959 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1960 }
1961 } else {
1962 canvas_config_ex(hw->buffer_spec[i].
1963 vdec_dw_y_canvas_index,
1964 hw->buffer_spec[i].vdec_dw_y_addr,
1965 hw->mb_width << 3,
1966 hw->mb_height << 3,
1967 CANVAS_ADDR_NOWRAP,
1968 blkmode,
1969 endian);
1970 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1971 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1972 (1 << 11) |
1973 (blkmode << 10) |
1974 (1 << 8) |
1975 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1976 }
1977
1978 canvas_config_ex(hw->buffer_spec[i].
1979 vdec_dw_u_canvas_index,
1980 hw->buffer_spec[i].vdec_dw_u_addr,
1981 hw->mb_width << 3,
1982 hw->mb_height << 2,
1983 CANVAS_ADDR_NOWRAP,
1984 blkmode,
1985 endian);
1986 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1987 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1988 (1 << 11) |
1989 (blkmode << 10) |
1990 (1 << 8) |
1991 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1992 }
1993 }
1994#endif
1995}
1996
1997static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1998{
1999 u32 blkmode = mem_map_mode;
2000 int canvas_w;
2001 int canvas_h;
2002
2003 canvas_w = hw->frame_width /
2004 get_double_write_ratio(hw);
2005 canvas_h = hw->frame_height /
2006 get_double_write_ratio(hw);
2007
2008 if (mem_map_mode == 0)
2009 canvas_w = ALIGN(canvas_w, 32);
2010 else
2011 canvas_w = ALIGN(canvas_w, 64);
2012 canvas_h = ALIGN(canvas_h, 32);
2013
2014 canvas_config_ex(hw->buffer_spec[i].
2015 y_canvas_index,
2016 hw->buffer_spec[i].dw_y_adr,
2017 canvas_w,
2018 canvas_h,
2019 CANVAS_ADDR_NOWRAP,
2020 blkmode,
2021 7);
2022
2023 canvas_config_ex(hw->buffer_spec[i].
2024 u_canvas_index,
2025 hw->buffer_spec[i].dw_u_v_adr,
2026 canvas_w,
2027 canvas_h,
2028 CANVAS_ADDR_NOWRAP,
2029 blkmode,
2030 7);
2031}
2032
2033
2034int get_free_buf_idx(struct vdec_s *vdec)
2035{
2036 int i;
2037 unsigned long addr, flags;
2038 int index = -1;
2039 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2040 int buf_total = BUFSPEC_POOL_SIZE;
2041 spin_lock_irqsave(&hw->bufspec_lock, flags);
2042 /*hw->start_search_pos = 0;*/
2043 for (i = hw->start_search_pos; i < buf_total; i++) {
2044 if (hw->mmu_enable)
2045 addr = hw->buffer_spec[i].alloc_header_addr;
2046 else
2047 addr = hw->buffer_spec[i].cma_alloc_addr;
2048 if (hw->buffer_spec[i].used == 0 && addr) {
2049 hw->buffer_spec[i].used = 1;
2050 hw->start_search_pos = i+1;
2051 index = i;
2052 break;
2053 }
2054 }
2055 if (index < 0) {
2056 for (i = 0; i < hw->start_search_pos; i++) {
2057 if (hw->mmu_enable)
2058 addr = hw->buffer_spec[i].alloc_header_addr;
2059 else
2060 addr = hw->buffer_spec[i].cma_alloc_addr;
2061 if (hw->buffer_spec[i].used == 0 && addr) {
2062 hw->buffer_spec[i].used = 1;
2063 hw->start_search_pos = i+1;
2064 index = i;
2065 break;
2066 }
2067 }
2068 }
2069 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2070 if (hw->start_search_pos >= buf_total)
2071 hw->start_search_pos = 0;
2072 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2073 "%s, buf_spec_num %d\n", __func__, index);
2074
2075 if (index < 0) {
2076 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2077 "%s fail\n", __func__);
2078 vmh264_dump_state(vdec);
2079 }
2080
2081 if (dpb_is_debug(DECODE_ID(hw),
2082 PRINT_FLAG_DUMP_BUFSPEC))
2083 dump_bufspec(hw, __func__);
2084 return index;
2085}
2086
2087int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2088{
2089 /*u32 cur_buf_idx;*/
2090 unsigned long flags;
2091 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2092 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2093 "%s buf_spec_num %d used %d\n",
2094 __func__, buf_spec_num,
2095 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2096 if (buf_spec_num >= 0 &&
2097 buf_spec_num < BUFSPEC_POOL_SIZE
2098 ) {
2099 spin_lock_irqsave(&hw->bufspec_lock, flags);
2100 hw->buffer_spec[buf_spec_num].used = 0;
2101 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2102 if (hw->mmu_enable) {
2103 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2104 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2105 cur_buf_idx = cur_buf_idx&0xff;*/
2106 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2107 }
2108 release_aux_data(hw, buf_spec_num);
2109 }
2110 if (dpb_is_debug(DECODE_ID(hw),
2111 PRINT_FLAG_DUMP_BUFSPEC))
2112 dump_bufspec(hw, __func__);
2113 return 0;
2114}
2115
2116static void config_buf_specs(struct vdec_s *vdec)
2117{
2118 int i, j;
2119 unsigned long flags;
2120 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2121 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2122
2123 spin_lock_irqsave(&hw->bufspec_lock, flags);
2124 for (i = 0, j = 0;
2125 j < hw->dpb.mDPB.size
2126 && i < BUFSPEC_POOL_SIZE;
2127 i++) {
2128 int canvas;
2129 if (hw->buffer_spec[i].used != -1)
2130 continue;
2131 if (vdec->parallel_dec == 1) {
2132 if (hw->buffer_spec[i].y_canvas_index == -1)
2133 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2134 if (hw->buffer_spec[i].u_canvas_index == -1) {
2135 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2136 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2137 }
2138#ifdef VDEC_DW
2139 if (IS_VDEC_DW(hw)) {
2140 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2141 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2142 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2143 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2144 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2145 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2146 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2147 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2148 }
2149 }
2150#endif
2151 } else {
2152 canvas = vdec->get_canvas(j * mode, 2);
2153 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2154 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2155 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2156 dpb_print(DECODE_ID(hw),
2157 PRINT_FLAG_DPB_DETAIL,
2158 "config canvas (%d) %x for bufspec %d\r\n",
2159 j, canvas, i);
2160#ifdef VDEC_DW
2161 if (IS_VDEC_DW(hw)) {
2162 canvas = vdec->get_canvas(j * mode + 1, 2);
2163 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2164 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2165 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2166 dpb_print(DECODE_ID(hw),
2167 PRINT_FLAG_DPB_DETAIL,
2168 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2169 j, canvas, i);
2170 }
2171#endif
2172 }
2173
2174 hw->buffer_spec[i].used = 0;
2175 hw->buffer_spec[i].canvas_pos = j;
2176
2177
2178 j++;
2179 }
2180 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2181}
2182
2183static void config_buf_specs_ex(struct vdec_s *vdec)
2184{
2185 int i, j;
2186 unsigned long flags;
2187 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2188 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2189
2190 spin_lock_irqsave(&hw->bufspec_lock, flags);
2191 for (i = 0, j = 0;
2192 j < hw->dpb.mDPB.size
2193 && i < BUFSPEC_POOL_SIZE;
2194 i++) {
2195 int canvas = 0;
2196 if (hw->buffer_spec[i].used != -1)
2197 continue;
2198 if (vdec->parallel_dec == 1) {
2199 if (hw->buffer_spec[i].y_canvas_index == -1)
2200 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2201 if (hw->buffer_spec[i].u_canvas_index == -1) {
2202 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2203 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2204 }
2205#ifdef VDEC_DW
2206 if (IS_VDEC_DW(hw)) {
2207 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2208 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2209 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2210 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2211 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2212 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2213 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2214 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2215 }
2216 }
2217#endif
2218 } else {
2219 canvas = vdec->get_canvas(j* mode, 2);
2220 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2221 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2222 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2223
2224 dpb_print(DECODE_ID(hw),
2225 PRINT_FLAG_DPB_DETAIL,
2226 "config canvas (%d) %x for bufspec %d\r\n",
2227 j, canvas, i);
2228#ifdef VDEC_DW
2229 if (IS_VDEC_DW(hw)) {
2230 canvas = vdec->get_canvas(j*mode + 1, 2);
2231 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2232 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2233 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2234 dpb_print(DECODE_ID(hw),
2235 PRINT_FLAG_DPB_DETAIL,
2236 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2237 j, canvas, i);
2238 }
2239#endif
2240 }
2241
2242 hw->buffer_spec[i].used = 0;
2243 hw->buffer_spec[i].alloc_header_addr = 0;
2244 hw->buffer_spec[i].canvas_pos = j;
2245
2246 j++;
2247 }
2248 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2249}
2250
2251
2252static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2253 unsigned char release_all)
2254{
2255 int i;
2256 unsigned long flags;
2257 unsigned char dealloc_flag = 0;
2258 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2259 if (hw->buffer_spec[i].used == 4 ||
2260 release_all) {
2261 dealloc_flag = 1;
2262 dpb_print(DECODE_ID(hw),
2263 PRINT_FLAG_DPB_DETAIL,
2264 "%s buf_spec_num %d\n",
2265 __func__, i
2266 );
2267 spin_lock_irqsave
2268 (&hw->bufspec_lock, flags);
2269 hw->buffer_spec[i].used = -1;
2270 spin_unlock_irqrestore
2271 (&hw->bufspec_lock, flags);
2272 release_aux_data(hw, i);
2273
2274 if (!hw->mmu_enable) {
2275 if (hw->buffer_spec[i].cma_alloc_addr) {
2276 if (!hw->is_used_v4l) {
2277 decoder_bmmu_box_free_idx(
2278 hw->bmmu_box,
2279 i);
2280 }
2281 spin_lock_irqsave
2282 (&hw->bufspec_lock, flags);
2283 hw->buffer_spec[i].cma_alloc_addr = 0;
2284 hw->buffer_spec[i].buf_adr = 0;
2285 spin_unlock_irqrestore
2286 (&hw->bufspec_lock, flags);
2287 }
2288 } else {
2289 if (hw->buffer_spec[i].alloc_header_addr) {
2290 decoder_mmu_box_free_idx(
2291 hw->mmu_box,
2292 i);
2293 spin_lock_irqsave
2294 (&hw->bufspec_lock, flags);
2295 hw->buffer_spec[i].
2296 alloc_header_addr = 0;
2297 hw->buffer_spec[i].buf_adr = 0;
2298 spin_unlock_irqrestore
2299 (&hw->bufspec_lock, flags);
2300 }
2301 }
2302 }
2303 }
2304 if (dealloc_flag &&
2305 dpb_is_debug(DECODE_ID(hw),
2306 PRINT_FLAG_DUMP_BUFSPEC))
2307 dump_bufspec(hw, __func__);
2308 return;
2309}
2310
2311unsigned char have_free_buf_spec(struct vdec_s *vdec)
2312{
2313 int i;
2314 unsigned long addr;
2315 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2316 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2317 int index = -1;
2318 int ret = 0;
2319 int allocated_count = 0;
2320 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2321 if (hw->mmu_enable)
2322 addr = hw->buffer_spec[i].alloc_header_addr;
2323 else
2324 addr = hw->buffer_spec[i].cma_alloc_addr;
2325 if (hw->buffer_spec[i].used == 0) {
2326
2327 if (addr)
2328 return 1;
2329 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2330 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2331 index = i;
2332 }
2333 }
2334 if (addr)
2335 allocated_count++;
2336 }
2337 if (index >= 0) {
2338 mutex_lock(&vmh264_mutex);
2339 dealloc_buf_specs(hw, 0);
2340 if (max_alloc_buf_count == 0 ||
2341 allocated_count < max_alloc_buf_count) {
2342 if (hw->is_used_v4l) {
2343 if (alloc_one_buf_spec_from_queue(hw, index) >= 0)
2344 ret = 1;
2345 } else if (alloc_one_buf_spec(hw, index) >= 0)
2346 ret = 1;
2347 }
2348 mutex_unlock(&vmh264_mutex);
2349 }
2350 return ret;
2351}
2352
2353static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2354 int canvas_pos)
2355{
2356 int i;
2357 int j = 0;
2358 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2359 if (hw->buffer_spec[i].canvas_pos >= 0) {
2360 if (j == canvas_pos)
2361 return i;
2362 j++;
2363 }
2364 }
2365 return -1;
2366}
2367static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2368 struct vframe_s *vf, int index)
2369{
2370 if (index < 0) {
2371 vf->mem_handle = NULL;
2372 vf->mem_head_handle = NULL;
2373 } else if (vf->type & VIDTYPE_SCATTER) {
2374 vf->mem_handle =
2375 decoder_mmu_box_get_mem_handle(
2376 hw->mmu_box, index);
2377 vf->mem_head_handle =
2378 decoder_bmmu_box_get_mem_handle(
2379 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2380 } else {
2381 vf->mem_handle =
2382 decoder_bmmu_box_get_mem_handle(
2383 hw->bmmu_box, VF_BUFFER_IDX(index));
2384 /* vf->mem_head_handle =
2385 decoder_bmmu_box_get_mem_handle(
2386 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2387 }
2388 return;
2389}
2390static int check_force_interlace(struct vdec_h264_hw_s *hw,
2391 struct FrameStore *frame)
2392{
2393 int bForceInterlace = 0;
2394 /* no di in secure mode, disable force di */
2395 if (vdec_secure(hw_to_vdec(hw)))
2396 return 0;
2397 if (frame->frame) {
2398 if (frame->frame->coded_frame
2399 && !frame->frame->frame_mbs_only_flag) {
2400 if (frame->frame->structure == FRAME)
2401 return 1;
2402 }
2403 }
2404
2405 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2406 && hw->bitstream_restriction_flag
2407 && (hw->frame_width == 1920)
2408 && (hw->frame_height >= 1080)
2409 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2410 bForceInterlace = 1;
2411 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2412 && (hw->frame_width == 720)
2413 && (hw->frame_height == 576)
2414 && (hw->frame_dur == 3840)) {
2415 bForceInterlace = 1;
2416 }
2417
2418 return bForceInterlace;
2419}
2420
2421static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2422{
2423 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2424 if (frame->slice_type == I_SLICE)
2425 vframe_qos->type = 1;
2426 else if (frame->slice_type == P_SLICE)
2427 vframe_qos->type = 2;
2428 else if (frame->slice_type == B_SLICE)
2429 vframe_qos->type = 3;
2430
2431 vframe_qos->size = frame->frame_size;
2432 vframe_qos->pts = frame->pts64;
2433
2434 vframe_qos->max_mv = frame->max_mv;
2435 vframe_qos->avg_mv = frame->avg_mv;
2436 vframe_qos->min_mv = frame->min_mv;
2437/*
2438 pr_info("mv: max:%d, avg:%d, min:%d\n",
2439 vframe_qos->max_mv,
2440 vframe_qos->avg_mv,
2441 vframe_qos->min_mv);
2442*/
2443
2444 vframe_qos->max_qp = frame->max_qp;
2445 vframe_qos->avg_qp = frame->avg_qp;
2446 vframe_qos->min_qp = frame->min_qp;
2447/*
2448 pr_info("qp: max:%d, avg:%d, min:%d\n",
2449 vframe_qos->max_qp,
2450 vframe_qos->avg_qp,
2451 vframe_qos->min_qp);
2452*/
2453
2454 vframe_qos->max_skip = frame->max_skip;
2455 vframe_qos->avg_skip = frame->avg_skip;
2456 vframe_qos->min_skip = frame->min_skip;
2457/*
2458 pr_info("skip: max:%d, avg:%d, min:%d\n",
2459 vframe_qos->max_skip,
2460 vframe_qos->avg_skip,
2461 vframe_qos->min_skip);
2462*/
2463 vframe_qos->num++;
2464 if (hw->frameinfo_enable)
2465 vdec_fill_frame_info(vframe_qos, 1);
2466}
2467
2468static int is_iframe(struct FrameStore *frame) {
2469
2470 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2471 return 1;
2472 }
2473 return 0;
2474}
2475
2476
2477
2478int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2479{
2480 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2481 struct vframe_s *vf = NULL;
2482 int buffer_index = frame->buf_spec_num;
2483 int vf_count = 1;
2484 int i;
2485 int bForceInterlace = 0;
2486
2487 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2488 dpb_print(DECODE_ID(hw), 0,
2489 "%s, buffer_index 0x%x is beyond range\n",
2490 __func__, buffer_index);
2491 return -1;
2492 }
2493 if (force_disp_bufspec_num & 0x100) {
2494 /*recycle directly*/
2495 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2496 hw->buffer_spec[frame->buf_spec_num].used != 5)
2497 set_frame_output_flag(&hw->dpb, frame->index);
2498
2499 /*make pre_output not set*/
2500 return -1;
2501 }
2502 if (error_proc_policy & 0x1000) {
2503 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2504 int error_skip_frame_count = error_skip_count & 0xfff;
2505 if (((hw->no_error_count < error_skip_frame_count)
2506 && (error_skip_i_count == 0 ||
2507 hw->no_error_i_count < error_skip_i_count))
2508 && (!(frame->data_flag & I_FLAG)))
2509 frame->data_flag |= ERROR_FLAG;
2510 }
2511 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2512 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2513 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2514 frame->poc, hw->data_flag & ERROR_FLAG,
2515 error_proc_policy);
2516 if (frame->frame == NULL &&
2517 ((frame->is_used == 1 && frame->top_field)
2518 || (frame->is_used == 2 && frame->bottom_field))) {
2519 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2520 "%s Error frame_num %d used %d\n",
2521 __func__, frame->frame_num, frame->is_used);
2522 frame->data_flag |= ERROR_FLAG;
2523 }
2524 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2525 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2526 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2527 0, &frame->pts64) == 0)) {
2528 hw->last_pts64 = frame->pts64;
2529 hw->last_pts = frame->pts;
2530 } else {
2531 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2532 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2533 }
2534 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2535 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2536 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2537 frame->offset_delimiter, frame->pts,hw->last_pts,
2538 frame->pts64, hw->last_pts64, hw->frame_dur);
2539 hw->last_pts64 = frame->pts64;
2540 hw->last_pts = frame->pts;
2541 }
2542 if ((frame->data_flag & NODISP_FLAG) ||
2543 (frame->data_flag & NULL_FLAG) ||
2544 ((!hw->send_error_frame_flag) &&
2545 (frame->data_flag & ERROR_FLAG)) ||
2546 ((hw->i_only & 0x1) &&
2547 (!(frame->data_flag & I_FLAG)))
2548 ) {
2549 set_frame_output_flag(&hw->dpb, frame->index);
2550 return 0; /*do not return -1,
2551 otherwise flush_dpb() will not flush all dbp frames*/
2552 }
2553
2554 display_frame_count[DECODE_ID(hw)]++;
2555
2556 if (dpb_is_debug(DECODE_ID(hw),
2557 PRINT_FLAG_DPB_DETAIL)) {
2558 dpb_print(DECODE_ID(hw), 0,
2559 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2560 __func__, frame->index, frame->poc,
2561 frame->buf_spec_num);
2562 print_pic_info(DECODE_ID(hw), "predis_frm",
2563 frame->frame, -1);
2564 print_pic_info(DECODE_ID(hw), "predis_top",
2565 frame->top_field, -1);
2566 print_pic_info(DECODE_ID(hw), "predis_bot",
2567 frame->bottom_field, -1);
2568 }
2569
2570 if (!is_interlace(frame))
2571 vf_count = 1;
2572 else
2573 vf_count = 2;
2574 bForceInterlace = check_force_interlace(hw, frame);
2575 if (bForceInterlace)
2576 vf_count = 2;
2577 hw->buffer_spec[buffer_index].vf_ref = 0;
2578 fill_frame_info(hw, frame);
2579 for (i = 0; i < vf_count; i++) {
2580 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2581 vf == NULL) {
2582 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2583 "%s fatal error, no available buffer slot.\n",
2584 __func__);
2585 return -1;
2586 }
2587 vf->duration_pulldown = 0;
2588 if (!(is_iframe(frame)) && hw->unstable_pts) {
2589 vf->pts = 0;
2590 vf->pts_us64 = 0;
2591 vf->timestamp = 0;
2592 vf->index = VF_INDEX(frame->index, buffer_index);
2593 } else {
2594 vf->pts = frame->pts;
2595 vf->pts_us64 = frame->pts64;
2596 vf->timestamp = frame->timestamp;
2597 vf->index = VF_INDEX(frame->index, buffer_index);
2598 }
2599
2600 if (hw->is_used_v4l) {
2601 vf->v4l_mem_handle
2602 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2603 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
2604 "[%d] %s(), v4l mem handle: 0x%x\n",
2605 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
2606 __func__, vf->v4l_mem_handle);
2607 }
2608
2609 if (hw->mmu_enable) {
2610 if (hw->double_write_mode & 0x10) {
2611 /* double write only */
2612 vf->compBodyAddr = 0;
2613 vf->compHeadAddr = 0;
2614 } else {
2615 /*head adr*/
2616 vf->compHeadAddr =
2617 hw->buffer_spec[buffer_index].alloc_header_addr;
2618 /*body adr*/
2619 vf->compBodyAddr = 0;
2620 vf->canvas0Addr = vf->canvas1Addr = 0;
2621 }
2622
2623 vf->type = VIDTYPE_SCATTER;
2624
2625 if (hw->double_write_mode) {
2626 vf->type |= VIDTYPE_PROGRESSIVE
2627 | VIDTYPE_VIU_FIELD;
2628 vf->type |= VIDTYPE_VIU_NV21;
2629 if (hw->double_write_mode == 3)
2630 vf->type |= VIDTYPE_COMPRESS;
2631
2632 vf->canvas0Addr = vf->canvas1Addr = -1;
2633 vf->plane_num = 2;
2634 vf->canvas0_config[0] =
2635 hw->buffer_spec[buffer_index].
2636 canvas_config[0];
2637 vf->canvas0_config[1] =
2638 hw->buffer_spec[buffer_index].
2639 canvas_config[1];
2640
2641 vf->canvas1_config[0] =
2642 hw->buffer_spec[buffer_index].
2643 canvas_config[0];
2644 vf->canvas1_config[1] =
2645 hw->buffer_spec[buffer_index].
2646 canvas_config[1];
2647
2648 } else {
2649 vf->type |=
2650 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2651 vf->canvas0Addr = vf->canvas1Addr = 0;
2652 }
2653
2654 vf->bitdepth =
2655 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2656
2657 vf->compWidth = hw->frame_width;
2658 vf->compHeight = hw->frame_height;
2659 } else {
2660 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2661 VIDTYPE_VIU_NV21;
2662
2663 vf->canvas0Addr = vf->canvas1Addr =
2664 spec2canvas(&hw->buffer_spec[buffer_index]);
2665#ifdef VDEC_DW
2666 if (IS_VDEC_DW(hw))
2667 vf->canvas0Addr = vf->canvas1Addr =
2668 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2669#endif
2670
2671 }
2672 set_frame_info(hw, vf, buffer_index);
2673
2674 if (hw->mmu_enable && hw->double_write_mode) {
2675 vf->width = hw->frame_width /
2676 get_double_write_ratio(hw);
2677 vf->height = hw->frame_height /
2678 get_double_write_ratio(hw);
2679 }
2680
2681 vf->flag = 0;
2682 if (frame->data_flag & I_FLAG)
2683 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2684 if (frame->data_flag & ERROR_FLAG)
2685 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2686 update_vf_memhandle(hw, vf, buffer_index);
2687 hw->buffer_spec[buffer_index].used = 2;
2688 hw->buffer_spec[buffer_index].vf_ref++;
2689
2690 if (bForceInterlace || is_interlace(frame)) {
2691 vf->type =
2692 VIDTYPE_INTERLACE_FIRST |
2693 VIDTYPE_VIU_NV21;
2694
2695 if (bForceInterlace) {
2696 vf->type |= (i == 0 ?
2697 VIDTYPE_INTERLACE_TOP :
2698 VIDTYPE_INTERLACE_BOTTOM);
2699 if (i == 1) {
2700 vf->pts = 0;
2701 vf->pts_us64 = 0;
2702 }
2703 } else if (frame->top_field->poc <=
2704 frame->bottom_field->poc) /*top first*/
2705 vf->type |= (i == 0 ?
2706 VIDTYPE_INTERLACE_TOP :
2707 VIDTYPE_INTERLACE_BOTTOM);
2708 else
2709 vf->type |= (i == 0 ?
2710 VIDTYPE_INTERLACE_BOTTOM :
2711 VIDTYPE_INTERLACE_TOP);
2712 vf->duration = vf->duration/2;
2713 }
2714
2715 if (i == 0)
2716 decoder_do_frame_check(hw_to_vdec(hw), vf);
2717
2718 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2719 vf->sar_width = hw->width_aspect_ratio;
2720 vf->sar_height = hw->height_aspect_ratio;
2721
2722 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2723 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2724 hw->vf_pre_count++;
2725 vdec->vdec_fps_detec(vdec->id);
2726 if (without_display_mode == 0) {
2727 vf_notify_receiver(vdec->vf_provider_name,
2728 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2729 } else
2730 vh264_vf_put(vh264_vf_get(vdec), vdec);
2731 }
2732 if (dpb_is_debug(DECODE_ID(hw),
2733 PRINT_FLAG_DUMP_BUFSPEC))
2734 dump_bufspec(hw, __func__);
2735
2736 return 0;
2737}
2738
2739int notify_v4l_eos(struct vdec_s *vdec)
2740{
2741 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2742 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2743 struct vframe_s *vf = NULL;
2744 struct vdec_fb *fb = NULL;
2745
2746 if (hw->is_used_v4l && hw->eos) {
2747 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
2748 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2749 "%s fatal error, no available buffer slot.\n",
2750 __func__);
2751 return -1;
2752 }
2753
2754 if (v4l_get_fb(hw->v4l2_ctx, &fb)) {
2755 pr_err("[%d] get fb fail.\n", ctx->id);
2756 return -1;
2757 }
2758
2759 vf->timestamp = ULONG_MAX;
2760 vf->v4l_mem_handle = (unsigned long)fb;
2761 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2762
2763 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2764
2765 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2766 vf_notify_receiver(vdec->vf_provider_name,
2767 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2768
2769 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2770 }
2771
2772 return 0;
2773}
2774
2775/******************
2776 * Hardware config
2777 */
2778char *slice_type_name[] = {
2779 "P_SLICE ",
2780 "B_SLICE ",
2781 "I_SLICE ",
2782 "SP_SLICE",
2783 "SI_SLICE",
2784};
2785
2786char *picture_structure_name[] = {
2787 "FRAME",
2788 "TOP_FIELD",
2789 "BOTTOM_FIELD"
2790};
2791
2792void print_pic_info(int decindex, const char *info,
2793 struct StorablePicture *pic,
2794 int slice_type)
2795{
2796 if (pic)
2797 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2798 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2799 info,
2800 picture_structure_name[pic->structure],
2801 pic->coded_frame ? "Frame" : "Field",
2802 (slice_type < 0 ||
2803 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2804 pic->mb_aff_frame_flag,
2805 pic->poc,
2806 pic->pic_num,
2807 pic->buf_spec_num,
2808 pic->data_flag);
2809}
2810
2811static void reset_process_time(struct vdec_h264_hw_s *hw)
2812{
2813 if (hw->start_process_time) {
2814 unsigned process_time =
2815 1000 * (jiffies - hw->start_process_time) / HZ;
2816 hw->start_process_time = 0;
2817 if (process_time > max_process_time[DECODE_ID(hw)])
2818 max_process_time[DECODE_ID(hw)] = process_time;
2819 }
2820}
2821
2822static void start_process_time(struct vdec_h264_hw_s *hw)
2823{
2824 hw->decode_timeout_count = 10;
2825 hw->start_process_time = jiffies;
2826}
2827
2828static void config_aux_buf(struct vdec_h264_hw_s *hw)
2829{
2830 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2831 WRITE_VREG(H264_AUX_DATA_SIZE,
2832 ((hw->prefix_aux_size >> 4) << 16) |
2833 (hw->suffix_aux_size >> 4)
2834 );
2835}
2836
2837/*
2838* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2839*/
2840static void set_aux_data(struct vdec_h264_hw_s *hw,
2841 struct StorablePicture *pic, unsigned char suffix_flag,
2842 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2843{
2844 int i;
2845 unsigned short *aux_adr;
2846 unsigned size_reg_val =
2847 READ_VREG(H264_AUX_DATA_SIZE);
2848 unsigned aux_count = 0;
2849 int aux_size = 0;
2850 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2851 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2852 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2853 return;
2854
2855 if (suffix_flag) {
2856 aux_adr = (unsigned short *)
2857 (hw_buf->aux_addr +
2858 hw_buf->prefix_aux_size);
2859 aux_count =
2860 ((size_reg_val & 0xffff) << 4)
2861 >> 1;
2862 aux_size =
2863 hw_buf->suffix_aux_size;
2864 } else {
2865 aux_adr =
2866 (unsigned short *)hw_buf->aux_addr;
2867 aux_count =
2868 ((size_reg_val >> 16) << 4)
2869 >> 1;
2870 aux_size =
2871 hw_buf->prefix_aux_size;
2872 }
2873 if (dpb_is_debug(DECODE_ID(hw),
2874 PRINT_FLAG_DPB_DETAIL)) {
2875 dpb_print(DECODE_ID(hw), 0,
2876 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2877 __func__, AUX_DATA_SIZE(pic),
2878 aux_count, suffix_flag, dv_meta_flag);
2879 }
2880 if (aux_size > 0 && aux_count > 0) {
2881 int heads_size = 0;
2882 int new_size;
2883 char *new_buf;
2884 for (i = 0; i < aux_count; i++) {
2885 unsigned char tag = aux_adr[i] >> 8;
2886 if (tag != 0 && tag != 0xff) {
2887 if (dv_meta_flag == 0)
2888 heads_size += 8;
2889 else if (dv_meta_flag == 1 && tag == 0x1)
2890 heads_size += 8;
2891 else if (dv_meta_flag == 2 && tag != 0x1)
2892 heads_size += 8;
2893 }
2894 }
2895 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2896 new_buf = krealloc(AUX_DATA_BUF(pic),
2897 new_size,
2898 GFP_KERNEL);
2899 if (new_buf) {
2900 unsigned char valid_tag = 0;
2901 unsigned char *h =
2902 new_buf +
2903 AUX_DATA_SIZE(pic);
2904 unsigned char *p = h + 8;
2905 int len = 0;
2906 int padding_len = 0;
2907 AUX_DATA_BUF(pic) = new_buf;
2908 for (i = 0; i < aux_count; i += 4) {
2909 int ii;
2910 unsigned char tag = aux_adr[i + 3] >> 8;
2911 if (tag != 0 && tag != 0xff) {
2912 if (dv_meta_flag == 0)
2913 valid_tag = 1;
2914 else if (dv_meta_flag == 1
2915 && tag == 0x1)
2916 valid_tag = 1;
2917 else if (dv_meta_flag == 2
2918 && tag != 0x1)
2919 valid_tag = 1;
2920 else
2921 valid_tag = 0;
2922 if (valid_tag && len > 0) {
2923 AUX_DATA_SIZE(pic) +=
2924 (len + 8);
2925 h[0] =
2926 (len >> 24) & 0xff;
2927 h[1] =
2928 (len >> 16) & 0xff;
2929 h[2] =
2930 (len >> 8) & 0xff;
2931 h[3] =
2932 (len >> 0) & 0xff;
2933 h[6] =
2934 (padding_len >> 8)
2935 & 0xff;
2936 h[7] =
2937 (padding_len) & 0xff;
2938 h += (len + 8);
2939 p += 8;
2940 len = 0;
2941 padding_len = 0;
2942 }
2943 if (valid_tag) {
2944 h[4] = tag;
2945 h[5] = 0;
2946 h[6] = 0;
2947 h[7] = 0;
2948 }
2949 }
2950 if (valid_tag) {
2951 for (ii = 0; ii < 4; ii++) {
2952 unsigned short aa =
2953 aux_adr[i + 3
2954 - ii];
2955 *p = aa & 0xff;
2956 p++;
2957 len++;
2958 /*if ((aa >> 8) == 0xff)
2959 padding_len++;*/
2960 }
2961 }
2962 }
2963 if (len > 0) {
2964 AUX_DATA_SIZE(pic) += (len + 8);
2965 h[0] = (len >> 24) & 0xff;
2966 h[1] = (len >> 16) & 0xff;
2967 h[2] = (len >> 8) & 0xff;
2968 h[3] = (len >> 0) & 0xff;
2969 h[6] = (padding_len >> 8) & 0xff;
2970 h[7] = (padding_len) & 0xff;
2971 }
2972 if (dpb_is_debug(DECODE_ID(hw),
2973 PRINT_FLAG_DPB_DETAIL)) {
2974 dpb_print(DECODE_ID(hw), 0,
2975 "aux: (size %d) suffix_flag %d\n",
2976 AUX_DATA_SIZE(pic), suffix_flag);
2977 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2978 dpb_print_cont(DECODE_ID(hw), 0,
2979 "%02x ", AUX_DATA_BUF(pic)[i]);
2980 if (((i + 1) & 0xf) == 0)
2981 dpb_print_cont(
2982 DECODE_ID(hw),
2983 0, "\n");
2984 }
2985 dpb_print_cont(DECODE_ID(hw),
2986 0, "\n");
2987 }
2988
2989 }
2990 }
2991
2992}
2993
2994static void release_aux_data(struct vdec_h264_hw_s *hw,
2995 int buf_spec_num)
2996{
2997 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
2998 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
2999 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3000}
3001
3002static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3003{
3004 int i;
3005 unsigned short *aux_adr =
3006 (unsigned short *)
3007 hw->aux_addr;
3008 unsigned aux_size =
3009 (READ_VREG(H264_AUX_DATA_SIZE)
3010 >> 16) << 4;
3011
3012 if (hw->prefix_aux_size > 0) {
3013 dpb_print(DECODE_ID(hw),
3014 0,
3015 "prefix aux: (size %d)\n",
3016 aux_size);
3017 for (i = 0; i <
3018 (aux_size >> 1); i++) {
3019 dpb_print_cont(DECODE_ID(hw),
3020 0,
3021 "%04x ",
3022 *(aux_adr + i));
3023 if (((i + 1) & 0xf)
3024 == 0)
3025 dpb_print_cont(
3026 DECODE_ID(hw),
3027 0, "\n");
3028 }
3029 }
3030 if (hw->suffix_aux_size > 0) {
3031 aux_adr = (unsigned short *)
3032 (hw->aux_addr +
3033 hw->prefix_aux_size);
3034 aux_size =
3035 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3036 << 4;
3037 dpb_print(DECODE_ID(hw),
3038 0,
3039 "suffix aux: (size %d)\n",
3040 aux_size);
3041 for (i = 0; i <
3042 (aux_size >> 1); i++) {
3043 dpb_print_cont(DECODE_ID(hw),
3044 0,
3045 "%04x ", *(aux_adr + i));
3046 if (((i + 1) & 0xf) == 0)
3047 dpb_print_cont(DECODE_ID(hw),
3048 0, "\n");
3049 }
3050 }
3051}
3052
3053static void config_decode_mode(struct vdec_h264_hw_s *hw)
3054{
3055#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3056 struct vdec_s *vdec = hw_to_vdec(hw);
3057#endif
3058 if (input_frame_based(hw_to_vdec(hw)))
3059 WRITE_VREG(H264_DECODE_MODE,
3060 DECODE_MODE_MULTI_FRAMEBASE);
3061#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3062 else if (vdec->slave)
3063 WRITE_VREG(H264_DECODE_MODE,
3064 (hw->got_valid_nal << 8) |
3065 DECODE_MODE_MULTI_DVBAL);
3066 else if (vdec->master)
3067 WRITE_VREG(H264_DECODE_MODE,
3068 (hw->got_valid_nal << 8) |
3069 DECODE_MODE_MULTI_DVENL);
3070#endif
3071 else
3072 WRITE_VREG(H264_DECODE_MODE,
3073 DECODE_MODE_MULTI_STREAMBASE);
3074 WRITE_VREG(H264_DECODE_SEQINFO,
3075 hw->seq_info2);
3076 WRITE_VREG(HEAD_PADING_REG, 0);
3077
3078 if (hw->init_flag == 0)
3079 WRITE_VREG(INIT_FLAG_REG, 0);
3080 else
3081 WRITE_VREG(INIT_FLAG_REG, 1);
3082}
3083int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3084{
3085 /* static int count = 0; */
3086 int ret = 0;
3087 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3088 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3089 unsigned int colocate_adr_offset;
3090 unsigned int val;
3091 struct StorablePicture *last_pic = hw->last_dec_picture;
3092
3093#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3094 int colocate_buf_index;
3095#endif
3096#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3097#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3098#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3099#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3100
3101#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3102/* bit 31:30 -- L1[0] picture coding structure,
3103 * 00 - top field, 01 - bottom field,
3104 * 10 - frame, 11 - mbaff frame
3105 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3106 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3107 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3108 */
3109#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3110
3111/* bit 15 -- flush co_mb_data to DDR -- W-Only
3112 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3113 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3114 * bit 9 -- soft_reset -- W-Only
3115 * bit 8 -- upgent
3116 * bit 7:2 -- h264_co_mb_mem_wr_addr
3117 * bit 1:0 -- h264_co_mb_info_wr_ptr
3118 */
3119#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3120
3121 unsigned long canvas_adr;
3122 unsigned int ref_reg_val;
3123 unsigned int one_ref_cfg = 0;
3124 int h264_buffer_info_data_write_count;
3125 int i, j;
3126 unsigned int colocate_wr_adr;
3127 unsigned int colocate_rd_adr;
3128 unsigned char use_direct_8x8;
3129 int canvas_pos;
3130 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3131 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3132 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3133 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3134 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3135
3136 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3137 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3138 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3139 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3140 canvas_pos);
3141 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3142
3143#ifdef VDEC_DW
3144 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3145 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3146 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3147#endif
3148 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3149 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3150
3151 if (!hw->mmu_enable) {
3152 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3153 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3154 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3155#ifdef VDEC_DW
3156 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3157 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3158 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3159#endif
3160 } else
3161 hevc_sao_set_pic_buffer(hw, pic);
3162
3163 if (pic->mb_aff_frame_flag)
3164 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3165 else if (pic->structure == TOP_FIELD)
3166 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3167 else if (pic->structure == BOTTOM_FIELD)
3168 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3169 else
3170 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3171
3172 if (pic->bottom_poc < pic->top_poc)
3173 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3174
3175 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3176 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3177 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3178
3179 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3180 int long_term_flag;
3181 i = get_buf_spec_by_canvas_pos(hw, j);
3182 if (i < 0)
3183 break;
3184 long_term_flag =
3185 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3186 if (long_term_flag > 0) {
3187 if (long_term_flag & 0x1)
3188 hw->buffer_spec[i].info0 |= (1 << 4);
3189 else
3190 hw->buffer_spec[i].info0 &= ~(1 << 4);
3191
3192 if (long_term_flag & 0x2)
3193 hw->buffer_spec[i].info0 |= (1 << 5);
3194 else
3195 hw->buffer_spec[i].info0 &= ~(1 << 5);
3196 }
3197
3198 if (i == pic->buf_spec_num)
3199 WRITE_VREG(H264_BUFFER_INFO_DATA,
3200 hw->buffer_spec[i].info0 | 0xf);
3201 else
3202 WRITE_VREG(H264_BUFFER_INFO_DATA,
3203 hw->buffer_spec[i].info0);
3204 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3205 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3206 }
3207
3208 /* config reference buffer */
3209 if (hw->mmu_enable) {
3210 hevc_mcr_config_mc_ref(hw);
3211 hevc_mcr_config_mcrcc(hw);
3212 }
3213
3214 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3215 "list0 size %d\n", pSlice->listXsize[0]);
3216 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3217 ref_reg_val = 0;
3218 j = 0;
3219 h264_buffer_info_data_write_count = 0;
3220
3221 //disable this read cache when frame width <= 64 (4MBs)
3222 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3223 if (hw->frame_width <= 64)
3224 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3225 else
3226 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3227
3228 if (last_pic)
3229 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3230 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3231 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3232 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3233 last_pic && (last_pic->data_flag & ERROR_FLAG)
3234 && (!(last_pic->slice_type == B_SLICE))
3235 && (!(pSlice->slice_type == I_SLICE))) {
3236 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3237 "no i/idr error mark\n");
3238 hw->data_flag |= ERROR_FLAG;
3239 pic->data_flag |= ERROR_FLAG;
3240 }
3241
3242 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3243 /*ref list 0 */
3244 struct StorablePicture *ref = pSlice->listX[0][i];
3245 unsigned int cfg;
3246 /* bit[6:5] - frame/field info,
3247 * 01 - top, 10 - bottom, 11 - frame
3248 */
3249 #ifdef ERROR_CHECK
3250 if (ref == NULL) {
3251 hw->data_flag |= ERROR_FLAG;
3252 pic->data_flag |= ERROR_FLAG;
3253 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3254 return -1;
3255 }
3256 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3257 hw->data_flag |= ERROR_FLAG;
3258 pic->data_flag |= ERROR_FLAG;
3259 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3260 }
3261 if (ref->data_flag & NULL_FLAG)
3262 hw->data_flag |= NULL_FLAG;
3263#endif
3264 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3265
3266 if (ref->structure == TOP_FIELD)
3267 cfg = 0x1;
3268 else if (ref->structure == BOTTOM_FIELD)
3269 cfg = 0x2;
3270 else /* FRAME */
3271 cfg = 0x3;
3272
3273 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3274 ref_reg_val <<= 8;
3275 ref_reg_val |= one_ref_cfg;
3276 j++;
3277
3278 if (j == 4) {
3279 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3280 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3281 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3282 h264_buffer_info_data_write_count++;
3283 j = 0;
3284 }
3285 print_pic_info(DECODE_ID(hw), "list0",
3286 pSlice->listX[0][i], -1);
3287 }
3288 if (j != 0) {
3289 while (j != 4) {
3290 ref_reg_val <<= 8;
3291 ref_reg_val |= one_ref_cfg;
3292 j++;
3293 }
3294 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3295 "H264_BUFFER_INFO_DATA: %x\n",
3296 ref_reg_val);
3297 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3298 h264_buffer_info_data_write_count++;
3299 }
3300 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3301 (one_ref_cfg << 8) | one_ref_cfg;
3302 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3303 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3304
3305 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3306 "list1 size %d\n", pSlice->listXsize[1]);
3307 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3308 ref_reg_val = 0;
3309 j = 0;
3310
3311 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3312 /* ref list 0 */
3313 struct StorablePicture *ref = pSlice->listX[1][i];
3314 unsigned int cfg;
3315 /* bit[6:5] - frame/field info,
3316 * 01 - top, 10 - bottom, 11 - frame
3317 */
3318
3319 #ifdef ERROR_CHECK
3320 if (ref == NULL) {
3321 hw->data_flag |= ERROR_FLAG;
3322 pic->data_flag |= ERROR_FLAG;
3323 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3324 return -2;
3325 }
3326 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3327 pic->data_flag |= ERROR_FLAG;
3328 hw->data_flag |= ERROR_FLAG;
3329 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3330 }
3331 if (ref->data_flag & NULL_FLAG)
3332 hw->data_flag |= NULL_FLAG;
3333#endif
3334 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3335 if (ref->structure == TOP_FIELD)
3336 cfg = 0x1;
3337 else if (ref->structure == BOTTOM_FIELD)
3338 cfg = 0x2;
3339 else /* FRAME */
3340 cfg = 0x3;
3341 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3342 ref_reg_val <<= 8;
3343 ref_reg_val |= one_ref_cfg;
3344 j++;
3345
3346 if (j == 4) {
3347 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3348 "H264_BUFFER_INFO_DATA: %x\n",
3349 ref_reg_val);
3350 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3351 j = 0;
3352 }
3353 print_pic_info(DECODE_ID(hw), "list1",
3354 pSlice->listX[1][i], -1);
3355 }
3356 if (j != 0) {
3357 while (j != 4) {
3358 ref_reg_val <<= 8;
3359 ref_reg_val |= one_ref_cfg;
3360 j++;
3361 }
3362 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3363 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3364 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3365 }
3366
3367 /* configure co-locate buffer */
3368 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3369 ;
3370 if ((pSlice->mode_8x8_flags & 0x4) &&
3371 (pSlice->mode_8x8_flags & 0x2))
3372 use_direct_8x8 = 1;
3373 else
3374 use_direct_8x8 = 0;
3375
3376#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3377 colocate_adr_offset =
3378 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3379 ? 1 : 2) * 96;
3380 if (use_direct_8x8)
3381 colocate_adr_offset >>= 2;
3382
3383 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3384 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3385 colocate_adr_offset, pSlice->first_mb_in_slice,
3386 colocate_adr_offset * pSlice->first_mb_in_slice);
3387
3388 colocate_adr_offset *= pSlice->first_mb_in_slice;
3389
3390 if ((pic->colocated_buf_index >= 0) &&
3391 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3392 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3393 ((p_H264_Dpb->colocated_buf_size *
3394 pic->colocated_buf_index)
3395 >> (use_direct_8x8 ? 2 : 0));
3396 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3397 p_H264_Dpb->colocated_mv_addr_end) {
3398 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3399 "Error, colocate buf is not enough, index is %d\n",
3400 pic->colocated_buf_index);
3401 ret = -3;
3402 }
3403 val = colocate_wr_adr + colocate_adr_offset;
3404 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3405 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3406 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3407 val, pSlice->first_mb_in_slice, pic->structure,
3408 colocate_adr_offset, pSlice->mode_8x8_flags,
3409 p_H264_Dpb->colocated_buf_size);
3410 } else {
3411 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3412 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3413 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3414 }
3415#else
3416 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3417 colocate_adr_offset =
3418 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3419 if (use_direct_8x8)
3420 colocate_adr_offset >>= 2;
3421
3422 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3423 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3424 colocate_adr_offset, pSlice->first_mb_in_slice,
3425 colocate_adr_offset * pSlice->first_mb_in_slice);
3426
3427 colocate_adr_offset *= pSlice->first_mb_in_slice;
3428
3429 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3430 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3431 (use_direct_8x8 ? 2 : 0));
3432
3433 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3434 p_H264_Dpb->colocated_mv_addr_end) {
3435 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3436 "Error, colocate buf is not enough, col buf index is %d\n",
3437 colocate_buf_index);
3438 ret = -4;
3439 }
3440 val = colocate_wr_adr + colocate_adr_offset;
3441 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3442 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3443 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3444 val, pSlice->first_mb_in_slice, pic->structure,
3445 colocate_adr_offset, pSlice->mode_8x8_flags,
3446 p_H264_Dpb->colocated_buf_size);
3447#endif
3448 if (pSlice->listXsize[1] > 0) {
3449 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3450 /* H264_CO_MB_RD_ADDR[bit 31:30],
3451 * original picture structure of L1[0],
3452 * 00 - top field, 01 - bottom field,
3453 * 10 - frame, 11 - mbaff frame
3454 */
3455 int l10_structure;
3456 int cur_colocate_ref_type;
3457 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3458 * 0 - top, 1 - bot
3459 */
3460 unsigned int val;
3461#ifdef ERROR_CHECK
3462 if (colocate_pic == NULL) {
3463 hw->data_flag |= ERROR_FLAG;
3464 pic->data_flag |= ERROR_FLAG;
3465 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3466 return -5;
3467 }
3468 if (colocate_pic->data_flag & ERROR_FLAG) {
3469 pic->data_flag |= ERROR_FLAG;
3470 hw->data_flag |= ERROR_FLAG;
3471 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3472 }
3473 if (colocate_pic->data_flag & NULL_FLAG)
3474 hw->data_flag |= NULL_FLAG;
3475#endif
3476
3477 if (colocate_pic->mb_aff_frame_flag)
3478 l10_structure = 3;
3479 else {
3480 if (colocate_pic->coded_frame)
3481 l10_structure = 2;
3482 else
3483 l10_structure = (colocate_pic->structure ==
3484 BOTTOM_FIELD) ? 1 : 0;
3485 }
3486#if 0
3487 /*case0016, p16,
3488 *cur_colocate_ref_type should be configured base on current pic
3489 */
3490 if (pic->structure == FRAME &&
3491 pic->mb_aff_frame_flag)
3492 cur_colocate_ref_type = 0;
3493 else if (pic->structure == BOTTOM_FIELD)
3494 cur_colocate_ref_type = 1;
3495 else
3496 cur_colocate_ref_type = 0;
3497#else
3498 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3499 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3500 pic->mb_aff_frame_flag,
3501 pic->structure,
3502 pic->coded_frame);
3503 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3504 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3505 colocate_pic->mb_aff_frame_flag,
3506 colocate_pic->structure,
3507 colocate_pic->coded_frame);
3508 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3509 cur_colocate_ref_type =
3510 (abs(pic->poc - colocate_pic->top_poc)
3511 < abs(pic->poc -
3512 colocate_pic->bottom_poc)) ? 0 : 1;
3513 } else
3514 cur_colocate_ref_type =
3515 (colocate_pic->structure
3516 == BOTTOM_FIELD) ? 1 : 0;
3517#endif
3518
3519#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3520 if ((colocate_pic->colocated_buf_index >= 0) &&
3521 (colocate_pic->colocated_buf_index <
3522 p_H264_Dpb->colocated_buf_count)) {
3523 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3524 ((p_H264_Dpb->colocated_buf_size *
3525 colocate_pic->colocated_buf_index)
3526 >> (use_direct_8x8 ? 2 : 0));
3527 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3528 p_H264_Dpb->colocated_mv_addr_end) {
3529 dpb_print(DECODE_ID(hw),
3530 PRINT_FLAG_ERROR,
3531 "Error, colocate buf is not enough, index is %d\n",
3532 colocate_pic->colocated_buf_index);
3533 ret = -6;
3534 }
3535 /* bit 31:30 -- L1[0] picture coding structure,
3536 * 00 - top field, 01 - bottom field,
3537 * 10 - frame, 11 - mbaff frame
3538 * bit 29 - L1[0] top/bot for B field pciture,
3539 * 0 - top, 1 - bot
3540 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3541 * -- only used for B Picture Direct mode
3542 * [2:0] will set to 3'b000
3543 */
3544 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3545 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3546 (l10_structure << 30) |
3547 (cur_colocate_ref_type << 29);
3548 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3549 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3550 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3551 colocate_pic->colocated_buf_index,
3552 val, colocate_rd_adr + colocate_adr_offset,
3553 colocate_pic->structure,
3554 colocate_pic->mb_aff_frame_flag);
3555 } else {
3556 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3557 "Error, reference pic has no colocated buf\n");
3558 ret = -7;
3559 }
3560#else
3561 colocate_buf_index =
3562 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3563 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3564 ((p_H264_Dpb->colocated_buf_size *
3565 colocate_buf_index)
3566 >> (use_direct_8x8 ? 2 : 0));
3567 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3568 p_H264_Dpb->colocated_mv_addr_end) {
3569 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3570 "Error, colocate buf is not enough, col buf index is %d\n",
3571 colocate_buf_index);
3572 ret = -8;
3573 }
3574 /* bit 31:30 -- L1[0] picture coding structure,
3575 * 00 - top field, 01 - bottom field,
3576 * 10 - frame, 11 - mbaff frame
3577 * bit 29 - L1[0] top/bot for B field pciture,
3578 * 0 - top, 1 - bot
3579 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3580 * -- only used for B Picture Direct mode
3581 * [2:0] will set to 3'b000
3582 */
3583 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3584 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3585 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3586 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3587 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3588 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3589 val, colocate_pic->structure,
3590 colocate_pic->mb_aff_frame_flag);
3591#endif
3592 }
3593 return ret;
3594}
3595
3596static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3597{
3598 unsigned long flags;
3599 struct vdec_s *vdec = op_arg;
3600 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3601
3602 spin_lock_irqsave(&hw->lock, flags);
3603
3604 states->vf_pool_size = VF_POOL_SIZE;
3605 states->buf_free_num = kfifo_len(&hw->newframe_q);
3606 states->buf_avail_num = kfifo_len(&hw->display_q);
3607
3608 spin_unlock_irqrestore(&hw->lock, flags);
3609
3610 return 0;
3611}
3612
3613static struct vframe_s *vh264_vf_peek(void *op_arg)
3614{
3615 struct vframe_s *vf[2] = {0, 0};
3616 struct vdec_s *vdec = op_arg;
3617 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3618
3619 if (!hw)
3620 return NULL;
3621
3622 if (force_disp_bufspec_num & 0x100) {
3623 if (force_disp_bufspec_num & 0x200)
3624 return NULL;
3625 return &hw->vframe_dummy;
3626 }
3627
3628 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3629 if (vf[1]) {
3630 vf[0]->next_vf_pts_valid = true;
3631 vf[0]->next_vf_pts = vf[1]->pts;
3632 } else
3633 vf[0]->next_vf_pts_valid = false;
3634 return vf[0];
3635 }
3636
3637 return NULL;
3638}
3639
3640static struct vframe_s *vh264_vf_get(void *op_arg)
3641{
3642 struct vframe_s *vf;
3643 struct vdec_s *vdec = op_arg;
3644 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3645
3646 if (!hw)
3647 return NULL;
3648
3649 if (force_disp_bufspec_num & 0x100) {
3650 int buffer_index = force_disp_bufspec_num & 0xff;
3651 if (force_disp_bufspec_num & 0x200)
3652 return NULL;
3653
3654 vf = &hw->vframe_dummy;
3655 vf->duration_pulldown = 0;
3656 vf->pts = 0;
3657 vf->pts_us64 = 0;
3658 set_frame_info(hw, vf, buffer_index);
3659 vf->flag = 0;
3660 if (hw->mmu_enable) {
3661 if (hw->double_write_mode & 0x10) {
3662 /* double write only */
3663 vf->compBodyAddr = 0;
3664 vf->compHeadAddr = 0;
3665 } else {
3666 /*head adr*/
3667 vf->compHeadAddr =
3668 hw->buffer_spec[buffer_index].alloc_header_addr;
3669 /*body adr*/
3670 vf->compBodyAddr = 0;
3671 vf->canvas0Addr = vf->canvas1Addr = 0;
3672 }
3673
3674 vf->type = VIDTYPE_SCATTER;
3675
3676 if (hw->double_write_mode) {
3677 vf->type |= VIDTYPE_PROGRESSIVE
3678 | VIDTYPE_VIU_FIELD;
3679 vf->type |= VIDTYPE_VIU_NV21;
3680 if (hw->double_write_mode == 3)
3681 vf->type |= VIDTYPE_COMPRESS;
3682
3683 vf->canvas0Addr = vf->canvas1Addr = -1;
3684 vf->plane_num = 2;
3685 vf->canvas0_config[0] =
3686 hw->buffer_spec[buffer_index].
3687 canvas_config[0];
3688 vf->canvas0_config[1] =
3689 hw->buffer_spec[buffer_index].
3690 canvas_config[1];
3691
3692 vf->canvas1_config[0] =
3693 hw->buffer_spec[buffer_index].
3694 canvas_config[0];
3695 vf->canvas1_config[1] =
3696 hw->buffer_spec[buffer_index].
3697 canvas_config[1];
3698 } else {
3699 vf->type |=
3700 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3701 vf->canvas0Addr = vf->canvas1Addr = 0;
3702 }
3703 vf->bitdepth =
3704 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3705
3706 vf->compWidth = hw->frame_width;
3707 vf->compHeight = hw->frame_height;
3708
3709 if (hw->double_write_mode) {
3710 vf->width = hw->frame_width /
3711 get_double_write_ratio(hw);
3712 vf->height = hw->frame_height /
3713 get_double_write_ratio(hw);
3714 }
3715 } else {
3716 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3717 VIDTYPE_VIU_NV21;
3718 vf->canvas0Addr = vf->canvas1Addr =
3719 spec2canvas(&hw->buffer_spec[buffer_index]);
3720 }
3721
3722 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3723 hw->bmmu_box, buffer_index);*/
3724 update_vf_memhandle(hw, vf, buffer_index);
3725 force_disp_bufspec_num |= 0x200;
3726 return vf;
3727 }
3728
3729 if (kfifo_get(&hw->display_q, &vf)) {
3730 int time = jiffies;
3731 unsigned int frame_interval =
3732 1000*(time - hw->last_frame_time)/HZ;
3733 struct vframe_s *next_vf;
3734 if (dpb_is_debug(DECODE_ID(hw),
3735 PRINT_FLAG_VDEC_DETAIL)) {
3736 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3737 int frame_index = FRAME_INDEX(vf->index);
3738 if (frame_index < 0 ||
3739 frame_index >= DPB_SIZE_MAX) {
3740 dpb_print(DECODE_ID(hw), 0,
3741 "%s vf index 0x%x error\r\n",
3742 __func__, vf->index);
3743 } else {
3744 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3745 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3746 __func__, BUFSPEC_INDEX(vf->index), vf,
3747 p_H264_Dpb->mFrameStore[frame_index].poc,
3748 vf->duration, vf->pts, frame_interval);
3749 }
3750 }
3751 if (hw->last_frame_time > 0) {
3752 if (frame_interval >
3753 max_get_frame_interval[DECODE_ID(hw)])
3754 max_get_frame_interval[DECODE_ID(hw)]
3755 = frame_interval;
3756 }
3757 hw->last_frame_time = time;
3758 hw->vf_get_count++;
3759 if (kfifo_peek(&hw->display_q, &next_vf)) {
3760 vf->next_vf_pts_valid = true;
3761 vf->next_vf_pts = next_vf->pts;
3762 } else
3763 vf->next_vf_pts_valid = false;
3764 return vf;
3765 }
3766
3767 return NULL;
3768}
3769
3770static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3771{
3772 struct vdec_s *vdec = op_arg;
3773 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3774 int buf_spec_num;
3775 int frame_index;
3776
3777 if (vf == (&hw->vframe_dummy))
3778 return;
3779 if (vf->index == -1) {
3780 dpb_print(DECODE_ID(hw), 0,
3781 "Warning: %s vf %p invalid index\r\n",
3782 __func__, vf);
3783 return;
3784 }
3785 frame_index = FRAME_INDEX(vf->index);
3786 buf_spec_num = BUFSPEC_INDEX(vf->index);
3787 if (frame_index < 0 ||
3788 frame_index >= DPB_SIZE_MAX ||
3789 buf_spec_num < 0 ||
3790 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3791 dpb_print(DECODE_ID(hw), 0,
3792 "%s vf index 0x%x error\r\n",
3793 __func__, vf->index);
3794 return;
3795 }
3796 /*get_buf_spec_idx_by_canvas_config(hw,
3797 &vf->canvas0_config[0]);*/
3798 if (hw->buffer_spec[buf_spec_num].used == 2) {
3799 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3800 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3801 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3802 __func__, vf, frame_index,
3803 p_H264_Dpb->mFrameStore[frame_index].poc,
3804 buf_spec_num,
3805 hw->buffer_spec[buf_spec_num].used,
3806 hw->buffer_spec[buf_spec_num].vf_ref);
3807 hw->buffer_spec[buf_spec_num].vf_ref--;
3808 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3809 set_frame_output_flag(&hw->dpb, frame_index);
3810 } else {
3811 unsigned long flags;
3812 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3813 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3814 __func__, vf, buf_spec_num,
3815 hw->buffer_spec[buf_spec_num].used,
3816 hw->buffer_spec[buf_spec_num].vf_ref);
3817 spin_lock_irqsave(&hw->bufspec_lock, flags);
3818 hw->buffer_spec[buf_spec_num].vf_ref--;
3819 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3820 if (hw->buffer_spec[buf_spec_num].used == 3)
3821 hw->buffer_spec[buf_spec_num].used = 4;
3822 else if (hw->buffer_spec[buf_spec_num].used == 5)
3823 hw->buffer_spec[buf_spec_num].used = 0;
3824 }
3825 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3826 if (dpb_is_debug(DECODE_ID(hw),
3827 PRINT_FLAG_DUMP_BUFSPEC))
3828 dump_bufspec(hw, __func__);
3829
3830 }
3831
3832 hw->vf_put_count++;
3833 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3834
3835#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3836 if (hw->buffer_empty_flag)
3837 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3838}
3839
3840static int vh264_event_cb(int type, void *data, void *op_arg)
3841{
3842 unsigned long flags;
3843 struct vdec_s *vdec = op_arg;
3844 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3845
3846 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3847 struct provider_aux_req_s *req =
3848 (struct provider_aux_req_s *)data;
3849 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3850 spin_lock_irqsave(&hw->lock, flags);
3851 req->aux_buf = NULL;
3852 req->aux_size = 0;
3853 if (buf_spec_num >= 0 &&
3854 buf_spec_num < BUFSPEC_POOL_SIZE &&
3855 is_buf_spec_in_disp_q(hw, buf_spec_num)
3856 ) {
3857 req->aux_buf =
3858 hw->buffer_spec[buf_spec_num].aux_data_buf;
3859 req->aux_size =
3860 hw->buffer_spec[buf_spec_num].aux_data_size;
3861#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3862 req->dv_enhance_exist =
3863 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3864#else
3865 req->dv_enhance_exist = 0;
3866#endif
3867 }
3868 spin_unlock_irqrestore(&hw->lock, flags);
3869
3870 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3871 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3872 __func__, type, buf_spec_num, req->aux_size);
3873 }
3874
3875 return 0;
3876}
3877
3878static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3879 u32 index)
3880{
3881 struct canvas_config_s *p_canvas_config;
3882 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3883 force_rate_framebase : force_rate_streambase;
3884 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3885 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3886 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3887
3888 vf->width = hw->frame_width;
3889 vf->height = hw->frame_height;
3890 if (force_rate) {
3891 if (force_rate == -1)
3892 vf->duration = 0;
3893 else
3894 vf->duration = 96000/force_rate;
3895 } else
3896 vf->duration = hw->frame_dur;
3897 vf->ratio_control =
3898 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3899 DISP_RATIO_ASPECT_RATIO_BIT;
3900 vf->orientation = hw->vh264_rotation;
3901 if (hw->mmu_enable)
3902 return;
3903 vf->canvas0Addr = vf->canvas1Addr = -1;
3904#ifdef NV21
3905 vf->plane_num = 2;
3906#else
3907 vf->plane_num = 3;
3908#endif
3909
3910 if (IS_VDEC_DW(hw)) {
3911 vf->width = (hw->frame_width /2);
3912 if (IS_VDEC_DW(hw) == 2)
3913 vf->height = (hw->frame_height /2);
3914 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3915 } else
3916 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3917
3918 vf->canvas0_config[0] = p_canvas_config[0];
3919 vf->canvas0_config[1] = p_canvas_config[1];
3920#ifndef NV21
3921 vf->canvas0_config[2] = p_canvas_config[2];
3922#endif
3923 vf->canvas1_config[0] = p_canvas_config[0];
3924 vf->canvas1_config[1] = p_canvas_config[1];
3925#ifndef NV21
3926 vf->canvas1_config[2] = p_canvas_config[2];
3927#endif
3928 /* signal_type */
3929 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK)
3930 vf->signal_type = hw->video_signal_from_vui;
3931 else
3932 vf->signal_type = 0;
3933
3934}
3935
3936static void get_picture_qos_info(struct StorablePicture *picture)
3937{
3938 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3939 unsigned char a[3];
3940 unsigned char i, j, t;
3941 unsigned long data;
3942
3943 get_random_bytes(&data, sizeof(unsigned long));
3944 if (picture->slice_type == I_SLICE)
3945 data = 0;
3946 a[0] = data & 0xff;
3947 a[1] = (data >> 8) & 0xff;
3948 a[2] = (data >> 16) & 0xff;
3949
3950 for (i = 0; i < 3; i++)
3951 for (j = i+1; j < 3; j++) {
3952 if (a[j] < a[i]) {
3953 t = a[j];
3954 a[j] = a[i];
3955 a[i] = t;
3956 } else if (a[j] == a[i]) {
3957 a[i]++;
3958 t = a[j];
3959 a[j] = a[i];
3960 a[i] = t;
3961 }
3962 }
3963 picture->max_mv = a[2];
3964 picture->avg_mv = a[1];
3965 picture->min_mv = a[0];
3966 /*
3967 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3968 data, a[0], a[1], a[2]);
3969 */
3970
3971 get_random_bytes(&data, sizeof(unsigned long));
3972 a[0] = data & 0x1f;
3973 a[1] = (data >> 8) & 0x3f;
3974 a[2] = (data >> 16) & 0x7f;
3975
3976 for (i = 0; i < 3; i++)
3977 for (j = i+1; j < 3; j++) {
3978 if (a[j] < a[i]) {
3979 t = a[j];
3980 a[j] = a[i];
3981 a[i] = t;
3982 } else if (a[j] == a[i]) {
3983 a[i]++;
3984 t = a[j];
3985 a[j] = a[i];
3986 a[i] = t;
3987 }
3988 }
3989 picture->max_qp = a[2];
3990 picture->avg_qp = a[1];
3991 picture->min_qp = a[0];
3992 /*
3993 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
3994 data, a[0], a[1], a[2]);
3995 */
3996
3997 get_random_bytes(&data, sizeof(unsigned long));
3998 a[0] = data & 0x1f;
3999 a[1] = (data >> 8) & 0x3f;
4000 a[2] = (data >> 16) & 0x7f;
4001
4002 for (i = 0; i < 3; i++)
4003 for (j = i+1; j < 3; j++) {
4004 if (a[j] < a[i]) {
4005 t = a[j];
4006 a[j] = a[i];
4007 a[i] = t;
4008 } else if (a[j] == a[i]) {
4009 a[i]++;
4010 t = a[j];
4011 a[j] = a[i];
4012 a[i] = t;
4013 }
4014 }
4015 picture->max_skip = a[2];
4016 picture->avg_skip = a[1];
4017 picture->min_skip = a[0];
4018
4019
4020 /*
4021 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4022 data,a[0], a[1], a[2]);
4023 */
4024 } else {
4025 uint32_t blk88_y_count;
4026 uint32_t blk88_c_count;
4027 uint32_t blk22_mv_count;
4028 uint32_t rdata32;
4029 int32_t mv_hi;
4030 int32_t mv_lo;
4031 uint32_t rdata32_l;
4032 uint32_t mvx_L0_hi;
4033 uint32_t mvy_L0_hi;
4034 uint32_t mvx_L1_hi;
4035 uint32_t mvy_L1_hi;
4036 int64_t value;
4037 uint64_t temp_value;
4038/*
4039#define DEBUG_QOS
4040*/
4041#ifdef DEBUG_QOS
4042 int pic_number = picture->poc;
4043#endif
4044
4045 picture->max_mv = 0;
4046 picture->avg_mv = 0;
4047 picture->min_mv = 0;
4048
4049 picture->max_skip = 0;
4050 picture->avg_skip = 0;
4051 picture->min_skip = 0;
4052
4053 picture->max_qp = 0;
4054 picture->avg_qp = 0;
4055 picture->min_qp = 0;
4056
4057
4058
4059
4060
4061 /* set rd_idx to 0 */
4062 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4063 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4064 if (blk88_y_count == 0) {
4065#ifdef DEBUG_QOS
4066 pr_info(" [Picture %d Quality] NO Data yet.\n",
4067 pic_number);
4068#endif
4069 /* reset all counts */
4070 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4071 return;
4072 }
4073 /* qp_y_sum */
4074 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4075#ifdef DEBUG_QOS
4076 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4077 pic_number, rdata32/blk88_y_count,
4078 rdata32, blk88_y_count);
4079#endif
4080 picture->avg_qp = rdata32/blk88_y_count;
4081 /* intra_y_count */
4082 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4083#ifdef DEBUG_QOS
4084 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4085 pic_number, rdata32*100/blk88_y_count,
4086 '%', rdata32);
4087#endif
4088 /* skipped_y_count */
4089 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4090#ifdef DEBUG_QOS
4091 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4092 pic_number, rdata32*100/blk88_y_count,
4093 '%', rdata32);
4094#endif
4095 picture->avg_skip = rdata32*100/blk88_y_count;
4096 /* coeff_non_zero_y_count */
4097 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4098#ifdef DEBUG_QOS
4099 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4100 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4101 '%', rdata32);
4102#endif
4103 /* blk66_c_count */
4104 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4105 if (blk88_c_count == 0) {
4106#ifdef DEBUG_QOS
4107 pr_info(" [Picture %d Quality] NO Data yet.\n",
4108 pic_number);
4109#endif
4110 /* reset all counts */
4111 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4112 return;
4113 }
4114 /* qp_c_sum */
4115 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4116#ifdef DEBUG_QOS
4117 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4118 pic_number, rdata32/blk88_c_count,
4119 rdata32, blk88_c_count);
4120#endif
4121 /* intra_c_count */
4122 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4123#ifdef DEBUG_QOS
4124 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4125 pic_number, rdata32*100/blk88_c_count,
4126 '%', rdata32);
4127#endif
4128 /* skipped_cu_c_count */
4129 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4130#ifdef DEBUG_QOS
4131 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4132 pic_number, rdata32*100/blk88_c_count,
4133 '%', rdata32);
4134#endif
4135 /* coeff_non_zero_c_count */
4136 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4137#ifdef DEBUG_QOS
4138 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4139 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4140 '%', rdata32);
4141#endif
4142
4143 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4144 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4145 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4146#ifdef DEBUG_QOS
4147 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4148 pic_number, (rdata32>>0)&0xff);
4149#endif
4150 picture->min_qp = (rdata32>>0)&0xff;
4151
4152#ifdef DEBUG_QOS
4153 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4154 pic_number, (rdata32>>8)&0xff);
4155#endif
4156 picture->max_qp = (rdata32>>8)&0xff;
4157
4158#ifdef DEBUG_QOS
4159 pr_info(" [Picture %d Quality] C QP min : %d\n",
4160 pic_number, (rdata32>>16)&0xff);
4161 pr_info(" [Picture %d Quality] C QP max : %d\n",
4162 pic_number, (rdata32>>24)&0xff);
4163#endif
4164
4165 /* blk22_mv_count */
4166 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4167 if (blk22_mv_count == 0) {
4168#ifdef DEBUG_QOS
4169 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4170 pic_number);
4171#endif
4172 /* reset all counts */
4173 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4174 return;
4175 }
4176 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4177 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4178 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4179 /* should all be 0x00 or 0xff */
4180#ifdef DEBUG_QOS
4181 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4182 pic_number, rdata32);
4183#endif
4184 mvx_L0_hi = ((rdata32>>0)&0xff);
4185 mvy_L0_hi = ((rdata32>>8)&0xff);
4186 mvx_L1_hi = ((rdata32>>16)&0xff);
4187 mvy_L1_hi = ((rdata32>>24)&0xff);
4188
4189 /* mvx_L0_count[31:0] */
4190 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4191 temp_value = mvx_L0_hi;
4192 temp_value = (temp_value << 32) | rdata32_l;
4193
4194 if (mvx_L0_hi & 0x80)
4195 value = 0xFFFFFFF000000000 | temp_value;
4196 else
4197 value = temp_value;
4198 value = div_s64(value, blk22_mv_count);
4199#ifdef DEBUG_QOS
4200 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4201 pic_number, (int)(value),
4202 value, blk22_mv_count);
4203#endif
4204 picture->avg_mv = value;
4205
4206 /* mvy_L0_count[31:0] */
4207 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4208 temp_value = mvy_L0_hi;
4209 temp_value = (temp_value << 32) | rdata32_l;
4210
4211 if (mvy_L0_hi & 0x80)
4212 value = 0xFFFFFFF000000000 | temp_value;
4213 else
4214 value = temp_value;
4215#ifdef DEBUG_QOS
4216 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4217 pic_number, rdata32_l/blk22_mv_count,
4218 value, blk22_mv_count);
4219#endif
4220
4221 /* mvx_L1_count[31:0] */
4222 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4223 temp_value = mvx_L1_hi;
4224 temp_value = (temp_value << 32) | rdata32_l;
4225 if (mvx_L1_hi & 0x80)
4226 value = 0xFFFFFFF000000000 | temp_value;
4227 else
4228 value = temp_value;
4229#ifdef DEBUG_QOS
4230 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4231 pic_number, rdata32_l/blk22_mv_count,
4232 value, blk22_mv_count);
4233#endif
4234
4235 /* mvy_L1_count[31:0] */
4236 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4237 temp_value = mvy_L1_hi;
4238 temp_value = (temp_value << 32) | rdata32_l;
4239 if (mvy_L1_hi & 0x80)
4240 value = 0xFFFFFFF000000000 | temp_value;
4241 else
4242 value = temp_value;
4243#ifdef DEBUG_QOS
4244 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4245 pic_number, rdata32_l/blk22_mv_count,
4246 value, blk22_mv_count);
4247#endif
4248
4249 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4250 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4251 mv_hi = (rdata32>>16)&0xffff;
4252 if (mv_hi & 0x8000)
4253 mv_hi = 0x8000 - mv_hi;
4254#ifdef DEBUG_QOS
4255 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4256 pic_number, mv_hi);
4257#endif
4258 picture->max_mv = mv_hi;
4259
4260 mv_lo = (rdata32>>0)&0xffff;
4261 if (mv_lo & 0x8000)
4262 mv_lo = 0x8000 - mv_lo;
4263#ifdef DEBUG_QOS
4264 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4265 pic_number, mv_lo);
4266#endif
4267 picture->min_mv = mv_lo;
4268
4269 /* {mvy_L0_max, mvy_L0_min} */
4270 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4271 mv_hi = (rdata32>>16)&0xffff;
4272 if (mv_hi & 0x8000)
4273 mv_hi = 0x8000 - mv_hi;
4274#ifdef DEBUG_QOS
4275 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4276 pic_number, mv_hi);
4277#endif
4278
4279 mv_lo = (rdata32>>0)&0xffff;
4280 if (mv_lo & 0x8000)
4281 mv_lo = 0x8000 - mv_lo;
4282#ifdef DEBUG_QOS
4283 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4284 pic_number, mv_lo);
4285#endif
4286
4287 /* {mvx_L1_max, mvx_L1_min} */
4288 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4289 mv_hi = (rdata32>>16)&0xffff;
4290 if (mv_hi & 0x8000)
4291 mv_hi = 0x8000 - mv_hi;
4292#ifdef DEBUG_QOS
4293 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4294 pic_number, mv_hi);
4295#endif
4296
4297 mv_lo = (rdata32>>0)&0xffff;
4298 if (mv_lo & 0x8000)
4299 mv_lo = 0x8000 - mv_lo;
4300#ifdef DEBUG_QOS
4301 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4302 pic_number, mv_lo);
4303#endif
4304
4305 /* {mvy_L1_max, mvy_L1_min} */
4306 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4307 mv_hi = (rdata32>>16)&0xffff;
4308 if (mv_hi & 0x8000)
4309 mv_hi = 0x8000 - mv_hi;
4310#ifdef DEBUG_QOS
4311 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4312 pic_number, mv_hi);
4313#endif
4314 mv_lo = (rdata32>>0)&0xffff;
4315 if (mv_lo & 0x8000)
4316 mv_lo = 0x8000 - mv_lo;
4317#ifdef DEBUG_QOS
4318 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4319 pic_number, mv_lo);
4320#endif
4321
4322 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4323#ifdef DEBUG_QOS
4324 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4325 pic_number, rdata32);
4326#endif
4327 /* reset all counts */
4328 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4329 }
4330}
4331
4332static int get_max_dec_frame_buf_size(int level_idc,
4333 int max_reference_frame_num, int mb_width,
4334 int mb_height)
4335{
4336 int pic_size = mb_width * mb_height * 384;
4337
4338 int size = 0;
4339
4340 switch (level_idc) {
4341 case 9:
4342 size = 152064;
4343 break;
4344 case 10:
4345 size = 152064;
4346 break;
4347 case 11:
4348 size = 345600;
4349 break;
4350 case 12:
4351 size = 912384;
4352 break;
4353 case 13:
4354 size = 912384;
4355 break;
4356 case 20:
4357 size = 912384;
4358 break;
4359 case 21:
4360 size = 1824768;
4361 break;
4362 case 22:
4363 size = 3110400;
4364 break;
4365 case 30:
4366 size = 3110400;
4367 break;
4368 case 31:
4369 size = 6912000;
4370 break;
4371 case 32:
4372 size = 7864320;
4373 break;
4374 case 40:
4375 size = 12582912;
4376 break;
4377 case 41:
4378 size = 12582912;
4379 break;
4380 case 42:
4381 size = 13369344;
4382 break;
4383 case 50:
4384 size = 42393600;
4385 break;
4386 case 51:
4387 case 52:
4388 default:
4389 size = 70778880;
4390 break;
4391 }
4392
4393 size /= pic_size;
4394 size = size + 1; /* need one more buffer */
4395
4396 if (max_reference_frame_num > size)
4397 size = max_reference_frame_num;
4398
4399 return size;
4400}
4401
4402static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4403{
4404 int i, j;
4405
4406 if (hw->double_write_mode) {
4407 mutex_lock(&vmh264_mutex);
4408 if (hw->decode_pic_count == 0) {
4409 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4410 i = get_buf_spec_by_canvas_pos(hw, j);
4411 if (i >= 0)
4412 config_decode_canvas_ex(hw, i);
4413 }
4414 }
4415 mutex_unlock(&vmh264_mutex);
4416 }
4417}
4418
4419static int vh264_set_params(struct vdec_h264_hw_s *hw,
4420 u32 param1, u32 param2, u32 param3, u32 param4)
4421{
4422 int i, j;
4423 int mb_width, mb_total;
4424 int max_reference_size, level_idc;
4425 int mb_height = 0;
4426 unsigned long flags;
4427 /*int mb_mv_byte;*/
4428 struct vdec_s *vdec = hw_to_vdec(hw);
4429 u32 seq_info2;
4430 int ret = 0;
4431 int active_buffer_spec_num;
4432 unsigned int buf_size;
4433 unsigned int frame_mbs_only_flag;
4434 unsigned int chroma_format_idc, chroma444;
4435 unsigned int crop_infor, crop_bottom, crop_right;
4436 unsigned int used_reorder_dpb_size_margin
4437 = reorder_dpb_size_margin;
4438 u8 *colocate_vaddr = NULL;
4439
4440#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4441 if (vdec->master || vdec->slave)
4442 used_reorder_dpb_size_margin =
4443 reorder_dpb_size_margin_dv;
4444#endif
4445 seq_info2 = param1;
4446 hw->seq_info = param2;
4447
4448 mb_width = seq_info2 & 0xff;
4449 mb_total = (seq_info2 >> 8) & 0xffff;
4450 if (!mb_width && mb_total) /*for 4k2k*/
4451 mb_width = 256;
4452 if (mb_width)
4453 mb_height = mb_total/mb_width;
4454 if (mb_width <= 0 || mb_height <= 0 ||
4455 is_oversize(mb_width << 4, mb_height << 4)) {
4456 dpb_print(DECODE_ID(hw), 0,
4457 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4458 seq_info2,
4459 mb_width,
4460 mb_height);
4461 return -1;
4462 }
4463
4464 if (seq_info2 != 0 &&
4465 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4466 hw->seq_info2 != 0
4467 ) /*picture size changed*/
4468 h264_reconfig(hw);
4469
4470 if (hw->config_bufmgr_done == 0) {
4471 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4472 u32 reg_val;
4473 hw->cfg_param1 = param1;
4474 hw->cfg_param2 = param2;
4475 hw->cfg_param3 = param3;
4476 hw->cfg_param4 = param4;
4477
4478 hw->seq_info2 = seq_info2 & (~0x80000000);
4479 dpb_print(DECODE_ID(hw), 0,
4480 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4481 seq_info2, hw->seq_info);
4482
4483 dpb_init_global(&hw->dpb,
4484 DECODE_ID(hw), 0, 0);
4485
4486 p_H264_Dpb->fast_output_enable = fast_output_enable;
4487 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4488
4489#if 1
4490 /*crop*/
4491 /* AV_SCRATCH_2
4492 bit 15: frame_mbs_only_flag
4493 bit 13-14: chroma_format_idc */
4494 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4495 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4496 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4497
4498 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4499 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4500 (2 - frame_mbs_only_flag) */
4501 crop_infor = param3;
4502 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4503 crop_right = ((crop_infor >> 16) & 0xff)
4504 >> (2 - frame_mbs_only_flag);
4505
4506 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4507 hw->frame_width = mb_width << 4;
4508 hw->frame_height = mb_height << 4;
4509 if (frame_mbs_only_flag) {
4510 hw->frame_height =
4511 hw->frame_height - (2 >> chroma444) *
4512 min(crop_bottom,
4513 (unsigned int)((8 << chroma444) - 1));
4514 hw->frame_width =
4515 hw->frame_width -
4516 (2 >> chroma444) * min(crop_right,
4517 (unsigned
4518 int)((8 << chroma444) - 1));
4519 } else {
4520 hw->frame_height =
4521 hw->frame_height - (4 >> chroma444) *
4522 min(crop_bottom,
4523 (unsigned int)((8 << chroma444)
4524 - 1));
4525 hw->frame_width =
4526 hw->frame_width -
4527 (4 >> chroma444) * min(crop_right,
4528 (unsigned int)((8 << chroma444) - 1));
4529 }
4530 dpb_print(DECODE_ID(hw), 0,
4531 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4532 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4533 dpb_print(DECODE_ID(hw), 0,
4534 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4535 mb_height, crop_right,
4536 hw->frame_width, mb_width);
4537
4538 if (hw->frame_height == 1088)
4539 hw->frame_height = 1080;
4540#endif
4541 if (!hw->mmu_enable) {
4542 mb_width = (mb_width+3) & 0xfffffffc;
4543 mb_height = (mb_height+3) & 0xfffffffc;
4544 }
4545 mb_total = mb_width * mb_height;
4546 hw->mb_width = mb_width;
4547 hw->mb_height = mb_height;
4548 hw->mb_total = mb_total;
4549 if (hw->mmu_enable)
4550 hevc_mcr_sao_global_hw_init(hw,
4551 (hw->mb_width << 4), (hw->mb_height << 4));
4552
4553 reg_val = param4;
4554 level_idc = reg_val & 0xff;
4555 max_reference_size = (reg_val >> 8) & 0xff;
4556 hw->dpb.origin_max_reference = max_reference_size;
4557 dpb_print(DECODE_ID(hw), 0,
4558 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4559 mb_height, mb_width, mb_total,
4560 level_idc, max_reference_size);
4561
4562
4563 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4564 hw->dpb.reorder_pic_num =
4565 get_max_dec_frame_buf_size(level_idc,
4566 max_reference_size, mb_width, mb_height);
4567
4568 dpb_print(DECODE_ID(hw), 0,
4569 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4570 hw->bitstream_restriction_flag,
4571 hw->max_dec_frame_buffering,
4572 hw->dpb.reorder_pic_num);
4573
4574 if ((hw->bitstream_restriction_flag) &&
4575 (hw->max_dec_frame_buffering <
4576 hw->dpb.reorder_pic_num)) {
4577 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4578 dpb_print(DECODE_ID(hw), 0,
4579 "set reorder_pic_num to %d\n",
4580 hw->dpb.reorder_pic_num);
4581 }
4582
4583 active_buffer_spec_num =
4584 hw->dpb.reorder_pic_num
4585 + used_reorder_dpb_size_margin;
4586 hw->max_reference_size =
4587 max_reference_size + reference_buf_margin;
4588
4589 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4590 active_buffer_spec_num = MAX_VF_BUF_NUM;
4591 hw->dpb.reorder_pic_num = active_buffer_spec_num
4592 - used_reorder_dpb_size_margin;
4593 }
4594 hw->dpb.mDPB.size = active_buffer_spec_num;
4595 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4596 hw->max_reference_size = MAX_VF_BUF_NUM;
4597 hw->dpb.max_reference_size = hw->max_reference_size;
4598
4599 if (hw->no_poc_reorder_flag)
4600 hw->dpb.reorder_pic_num = 1;
4601 dpb_print(DECODE_ID(hw), 0,
4602 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4603 __func__, active_buffer_spec_num,
4604 hw->dpb.reorder_pic_num,
4605 hw->max_reference_size);
4606
4607 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4608
4609 mutex_lock(&vmh264_mutex);
4610 if (!hw->mmu_enable) {
4611 config_buf_specs(vdec);
4612 i = get_buf_spec_by_canvas_pos(hw, 0);
4613
4614 if (hw->is_used_v4l) {
4615 if (i != -1) {
4616 ret = alloc_one_buf_spec_from_queue(hw, i);
4617 if (!ret)
4618 config_decode_canvas(hw, i);
4619 }
4620 } else {
4621 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4622 config_decode_canvas(hw, i);
4623 else
4624 ret = -1;
4625 }
4626 } else {
4627 if (hw->double_write_mode) {
4628 config_buf_specs_ex(vdec);
4629 } else {
4630 spin_lock_irqsave(&hw->bufspec_lock, flags);
4631 for (i = 0, j = 0;
4632 j < active_buffer_spec_num
4633 && i < BUFSPEC_POOL_SIZE;
4634 i++) {
4635 if (hw->buffer_spec[i].used != -1)
4636 continue;
4637 hw->buffer_spec[i].used = 0;
4638 hw->buffer_spec[i].
4639 alloc_header_addr = 0;
4640 hw->buffer_spec[i].canvas_pos = j;
4641 j++;
4642 }
4643 spin_unlock_irqrestore(&hw->bufspec_lock,
4644 flags);
4645 }
4646 hevc_mcr_config_canv2axitbl(hw, 0);
4647 }
4648 mutex_unlock(&vmh264_mutex);
4649 if (dpb_is_debug(DECODE_ID(hw),
4650 PRINT_FLAG_DUMP_BUFSPEC))
4651 dump_bufspec(hw, __func__);
4652
4653#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4654 buf_size = PAGE_ALIGN(
4655 p_H264_Dpb->colocated_buf_size *
4656 active_buffer_spec_num);
4657#else
4658 buf_size = PAGE_ALIGN(
4659 p_H264_Dpb->colocated_buf_size *
4660 hw->max_reference_size);
4661#endif
4662
4663 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4664 buf_size, DRIVER_NAME,
4665 &hw->collocate_cma_alloc_addr) < 0)
4666 return -1;
4667 if (!vdec_secure(vdec)) {
4668 /* clear for some mosaic problem after reset bufmgr */
4669 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4670 if (colocate_vaddr != NULL) {
4671 memset(colocate_vaddr, 0, buf_size);
4672 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4673 codec_mm_unmap_phyaddr(colocate_vaddr);
4674 }
4675 }
4676
4677 hw->dpb.colocated_mv_addr_start =
4678 hw->collocate_cma_alloc_addr;
4679#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4680 hw->dpb.colocated_mv_addr_end =
4681 hw->dpb.colocated_mv_addr_start +
4682 (p_H264_Dpb->colocated_buf_size *
4683 active_buffer_spec_num);
4684#else
4685 hw->dpb.colocated_mv_addr_end =
4686 hw->dpb.colocated_mv_addr_start +
4687 (p_H264_Dpb->colocated_buf_size *
4688 hw->max_reference_size);
4689#endif
4690 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4691 "callocate cma, %lx, %x\n",
4692 hw->collocate_cma_alloc_addr,
4693 hw->dpb.colocated_mv_addr_start);
4694
4695 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4696 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4697 hw->dpb.colocated_mv_addr_start,
4698 hw->dpb.colocated_mv_addr_end);
4699 if (!hw->mmu_enable) {
4700 mutex_lock(&vmh264_mutex);
4701 if (ret >= 0 && hw->decode_pic_count == 0) {
4702 int buf_cnt;
4703 /* h264_reconfig: alloc later*/
4704 buf_cnt = hw->dpb.mDPB.size;
4705
4706 for (j = 1; j < buf_cnt; j++) {
4707 i = get_buf_spec_by_canvas_pos(hw, j);
4708
4709 if (hw->is_used_v4l) {
4710 if (alloc_one_buf_spec_from_queue
4711 (hw, i) < 0) {
4712 if (j++ != buf_cnt)
4713 ret = -1;
4714 break;
4715 }
4716 } else if (alloc_one_buf_spec(hw, i) < 0)
4717 break;
4718
4719 config_decode_canvas(hw, i);
4720 }
4721 }
4722 mutex_unlock(&vmh264_mutex);
4723 } else {
4724 vh264_config_canvs_for_mmu(hw);
4725 }
4726
4727 hw->config_bufmgr_done = 1;
4728
4729 /*end of config_bufmgr_done */
4730 }
4731
4732 return ret;
4733}
4734
4735static void vui_config(struct vdec_h264_hw_s *hw)
4736{
4737 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4738 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4739 /*time*/
4740 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4741 hw->time_scale = p_H264_Dpb->time_scale;
4742 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4743
4744 hw->bitstream_restriction_flag =
4745 p_H264_Dpb->bitstream_restriction_flag;
4746 hw->num_reorder_frames =
4747 p_H264_Dpb->num_reorder_frames;
4748 hw->max_dec_frame_buffering =
4749 p_H264_Dpb->max_dec_frame_buffering;
4750
4751 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4752 "vui_config: pdb %d, %d, %d\n",
4753 p_H264_Dpb->bitstream_restriction_flag,
4754 p_H264_Dpb->num_reorder_frames,
4755 p_H264_Dpb->max_dec_frame_buffering);
4756
4757 hw->fixed_frame_rate_flag = 0;
4758 if (hw->timing_info_present_flag) {
4759 hw->fixed_frame_rate_flag =
4760 p_H264_Dpb->fixed_frame_rate_flag;
4761
4762 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4763 ((!hw->sync_outside) ||
4764 (!hw->frame_dur)))
4765 && hw->num_units_in_tick && hw->time_scale) {
4766 if (hw->use_idr_framerate ||
4767 hw->fixed_frame_rate_flag ||
4768 !hw->frame_dur ||
4769 !hw->duration_from_pts_done
4770 /*|| vh264_running*/) {
4771 u32 frame_dur_es =
4772 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4773 hw->time_scale);
4774 if (hw->frame_dur != frame_dur_es) {
4775 hw->h264_first_valid_pts_ready = false;
4776 hw->h264pts1 = 0;
4777 hw->h264pts2 = 0;
4778 hw->h264_pts_count = 0;
4779 hw->duration_from_pts_done = 0;
4780 fixed_frame_rate_mode =
4781 FIX_FRAME_RATE_OFF;
4782 hw->pts_duration = 0;
4783 hw->frame_dur = frame_dur_es;
4784 vdec_schedule_work(&hw->notify_work);
4785 dpb_print(DECODE_ID(hw),
4786 PRINT_FLAG_DEC_DETAIL,
4787 "frame_dur %d from timing_info\n",
4788 hw->frame_dur);
4789 }
4790
4791 /*hack to avoid use ES frame duration when
4792 *it's half of the rate from system info
4793 * sometimes the encoder is given a wrong
4794 * frame rate but the system side information
4795 * is more reliable
4796 *if ((frame_dur * 2) != frame_dur_es) {
4797 * frame_dur = frame_dur_es;
4798 *}
4799 */
4800 }
4801 }
4802 } else {
4803 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4804 "H.264: timing_info not present\n");
4805 }
4806
4807 /*aspect ratio*/
4808 aspect_ratio_info_present_flag =
4809 p_H264_Dpb->vui_status & 0x1;
4810 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4811
4812 if (aspect_ratio_info_present_flag) {
4813 if (aspect_ratio_idc == EXTEND_SAR) {
4814 hw->h264_ar = 0x3ff;
4815 hw->height_aspect_ratio =
4816 p_H264_Dpb->aspect_ratio_sar_height;
4817 hw->width_aspect_ratio =
4818 p_H264_Dpb->aspect_ratio_sar_width;
4819 } else {
4820 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4821 aspect_ratio_idc); */
4822
4823 switch (aspect_ratio_idc) {
4824 case 1:
4825 hw->h264_ar = 0x3ff;
4826 hw->height_aspect_ratio = 1;
4827 hw->width_aspect_ratio = 1;
4828 break;
4829 case 2:
4830 hw->h264_ar = 0x3ff;
4831 hw->height_aspect_ratio = 11;
4832 hw->width_aspect_ratio = 12;
4833 break;
4834 case 3:
4835 hw->h264_ar = 0x3ff;
4836 hw->height_aspect_ratio = 11;
4837 hw->width_aspect_ratio = 10;
4838 break;
4839 case 4:
4840 hw->h264_ar = 0x3ff;
4841 hw->height_aspect_ratio = 11;
4842 hw->width_aspect_ratio = 16;
4843 break;
4844 case 5:
4845 hw->h264_ar = 0x3ff;
4846 hw->height_aspect_ratio = 33;
4847 hw->width_aspect_ratio = 40;
4848 break;
4849 case 6:
4850 hw->h264_ar = 0x3ff;
4851 hw->height_aspect_ratio = 11;
4852 hw->width_aspect_ratio = 24;
4853 break;
4854 case 7:
4855 hw->h264_ar = 0x3ff;
4856 hw->height_aspect_ratio = 11;
4857 hw->width_aspect_ratio = 20;
4858 break;
4859 case 8:
4860 hw->h264_ar = 0x3ff;
4861 hw->height_aspect_ratio = 11;
4862 hw->width_aspect_ratio = 32;
4863 break;
4864 case 9:
4865 hw->h264_ar = 0x3ff;
4866 hw->height_aspect_ratio = 33;
4867 hw->width_aspect_ratio = 80;
4868 break;
4869 case 10:
4870 hw->h264_ar = 0x3ff;
4871 hw->height_aspect_ratio = 11;
4872 hw->width_aspect_ratio = 18;
4873 break;
4874 case 11:
4875 hw->h264_ar = 0x3ff;
4876 hw->height_aspect_ratio = 11;
4877 hw->width_aspect_ratio = 15;
4878 break;
4879 case 12:
4880 hw->h264_ar = 0x3ff;
4881 hw->height_aspect_ratio = 33;
4882 hw->width_aspect_ratio = 64;
4883 break;
4884 case 13:
4885 hw->h264_ar = 0x3ff;
4886 hw->height_aspect_ratio = 99;
4887 hw->width_aspect_ratio = 160;
4888 break;
4889 case 14:
4890 hw->h264_ar = 0x3ff;
4891 hw->height_aspect_ratio = 3;
4892 hw->width_aspect_ratio = 4;
4893 break;
4894 case 15:
4895 hw->h264_ar = 0x3ff;
4896 hw->height_aspect_ratio = 2;
4897 hw->width_aspect_ratio = 3;
4898 break;
4899 case 16:
4900 hw->h264_ar = 0x3ff;
4901 hw->height_aspect_ratio = 1;
4902 hw->width_aspect_ratio = 2;
4903 break;
4904 default:
4905 if (hw->vh264_ratio >> 16) {
4906 hw->h264_ar = (hw->frame_height *
4907 (hw->vh264_ratio & 0xffff) *
4908 0x100 +
4909 ((hw->vh264_ratio >> 16) *
4910 hw->frame_width / 2)) /
4911 ((hw->vh264_ratio >> 16) *
4912 hw->frame_width);
4913 hw->height_aspect_ratio = 1;
4914 hw->width_aspect_ratio = 1;
4915 } else {
4916 hw->h264_ar = 0x3ff;
4917 hw->height_aspect_ratio = 1;
4918 hw->width_aspect_ratio = 1;
4919 }
4920 break;
4921 }
4922 }
4923 } else {
4924 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4925 "v264dec: aspect_ratio not available from source\n");
4926 if (hw->vh264_ratio >> 16) {
4927 /* high 16 bit is width, low 16 bit is height */
4928 hw->h264_ar =
4929 ((hw->vh264_ratio & 0xffff) *
4930 hw->frame_height * 0x100 +
4931 (hw->vh264_ratio >> 16) *
4932 hw->frame_width / 2) /
4933 ((hw->vh264_ratio >> 16) *
4934 hw->frame_width);
4935 hw->height_aspect_ratio = 1;
4936 hw->width_aspect_ratio = 1;
4937 } else {
4938 hw->h264_ar = 0x3ff;
4939 hw->height_aspect_ratio = 1;
4940 hw->width_aspect_ratio = 1;
4941 }
4942 }
4943
4944 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4945 if (((hw->frame_dur == RATE_2397_FPS)
4946 && (dec_control
4947 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4948 || ((RATE_2997_FPS ==
4949 hw->frame_dur) &&
4950 (dec_control &
4951 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4952 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4953 "force fix frame rate\n");
4954 hw->fixed_frame_rate_flag = 0x40;
4955 }
4956 }
4957
4958 /*video_signal_from_vui: to do .. */
4959}
4960
4961static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4962{
4963 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4964
4965 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4966 if (error_proc_policy & 0x20) {
4967 if (!hw->is_used_v4l)
4968 hw->reset_bufmgr_flag = 1;
4969 }
4970}
4971
4972void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4973{
4974 struct vdec_h264_hw_s *hw =
4975 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4976
4977 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4978
4979 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4980 hw->reset_bufmgr_flag = 1;
4981}
4982
4983#ifdef CONSTRAIN_MAX_BUF_NUM
4984static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
4985{
4986 int i;
4987 int count = 0;
4988 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
4989 if (is_buf_spec_in_disp_q(hw, i) &&
4990 hw->buffer_spec[i].vf_ref > 0)
4991 count++;
4992 }
4993 return count;
4994}
4995
4996static int get_used_buf_count(struct vdec_h264_hw_s *hw)
4997{
4998 int i;
4999 int count = 0;
5000 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5001 if (is_buf_spec_in_use(hw, i))
5002 count++;
5003 }
5004 return count;
5005}
5006#endif
5007
5008
5009static bool is_buffer_available(struct vdec_s *vdec)
5010{
5011 bool buffer_available = 1;
5012 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5013 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5014 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5015 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5016 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5017 ((p_H264_Dpb->mDPB.init_done) &&
5018 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5019 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5020 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5021 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5022 __func__,
5023 kfifo_len(&hw->newframe_q),
5024 have_free_buf_spec(vdec),
5025 p_H264_Dpb->mDPB.init_done,
5026 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5027 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5028 );
5029 buffer_available = 0;
5030 if (dpb_is_debug(DECODE_ID(hw),
5031 DEBUG_DISABLE_RUNREADY_RMBUF))
5032 return buffer_available;
5033
5034 if ((error_proc_policy & 0x4) &&
5035 (error_proc_policy & 0x8)) {
5036 if ((kfifo_len(&hw->display_q) <= 0) &&
5037 (p_H264_Dpb->mDPB.used_size ==
5038 p_H264_Dpb->mDPB.size) &&
5039 (p_Dpb->ref_frames_in_buffer >
5040 (imax(
5041 1, p_Dpb->num_ref_frames)
5042 - p_Dpb->ltref_frames_in_buffer +
5043 force_sliding_margin)))
5044 bufmgr_recover(hw);
5045 else
5046 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5047 } else if ((error_proc_policy & 0x4) &&
5048 (kfifo_len(&hw->display_q) <= 0) &&
5049 ((p_H264_Dpb->mDPB.used_size ==
5050 p_H264_Dpb->mDPB.size) ||
5051 (!have_free_buf_spec(vdec)))) {
5052 enum receviver_start_e state = RECEIVER_INACTIVE;
5053 if ((error_proc_policy & 0x10) &&
5054 vf_get_receiver(vdec->vf_provider_name)) {
5055 state =
5056 vf_notify_receiver(vdec->vf_provider_name,
5057 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5058 NULL);
5059 if ((state == RECEIVER_STATE_NULL)
5060 || (state == RECEIVER_STATE_NONE))
5061 state = RECEIVER_INACTIVE;
5062 }
5063 if (state == RECEIVER_INACTIVE)
5064 bufmgr_recover(hw);
5065 else
5066 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5067 } else if ((error_proc_policy & 0x8) &&
5068 (p_Dpb->ref_frames_in_buffer >
5069 (imax(
5070 1, p_Dpb->num_ref_frames)
5071 - p_Dpb->ltref_frames_in_buffer +
5072 force_sliding_margin)))
5073 bufmgr_recover(hw);
5074 else
5075 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5076
5077 if (hw->reset_bufmgr_flag == 1)
5078 buffer_available = 1;
5079 }
5080
5081 return buffer_available;
5082}
5083
5084#define AUX_TAG_SEI 0x2
5085
5086#define SEI_BUFFERING_PERIOD 0
5087#define SEI_PicTiming 1
5088#define SEI_USER_DATA 4
5089#define SEI_RECOVERY_POINT 6
5090
5091/*
5092 *************************************************************************
5093 * Function:Reads bits from the bitstream buffer
5094 * Input:
5095 byte buffer[]
5096 containing sei message data bits
5097 int totbitoffset
5098 bit offset from start of partition
5099 int bytecount
5100 total bytes in bitstream
5101 int numbits
5102 number of bits to read
5103 * Output:
5104 int *info
5105 * Return:
5106 -1: failed
5107 > 0: the count of bit read
5108 * Attention:
5109 *************************************************************************
5110 */
5111
5112static int get_bits(unsigned char buffer[],
5113 int totbitoffset,
5114 int *info,
5115 int bytecount,
5116 int numbits)
5117{
5118 register int inf;
5119 long byteoffset;
5120 int bitoffset;
5121
5122 int bitcounter = numbits;
5123
5124 byteoffset = totbitoffset / 8;
5125 bitoffset = 7 - (totbitoffset % 8);
5126
5127 inf = 0;
5128 while (numbits) {
5129 inf <<= 1;
5130 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5131 numbits--;
5132 bitoffset--;
5133 if (bitoffset < 0) {
5134 byteoffset++;
5135 bitoffset += 8;
5136 if (byteoffset > bytecount)
5137 return -1;
5138 }
5139 }
5140
5141 *info = inf;
5142
5143
5144 return bitcounter;
5145}
5146
5147static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5148 u8 *sei_data_buf,
5149 u8 *sei_data_buf_end)
5150{
5151 int payload_type;
5152 int payload_size;
5153 u8 *p_sei;
5154 int temp = 0;
5155 int bit_offset;
5156 int read_size;
5157 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5158
5159 p_sei = sei_data_buf;
5160 read_size = 0;
5161 payload_type = 0;
5162 do {
5163 if (p_sei >= sei_data_buf_end)
5164 return read_size;
5165
5166 payload_type += *p_sei;
5167 read_size++;
5168 } while (*p_sei++ == 255);
5169
5170
5171 payload_size = 0;
5172 do {
5173 if (p_sei >= sei_data_buf_end)
5174 return read_size;
5175
5176 payload_size += *p_sei;
5177 read_size++;
5178 } while (*p_sei++ == 255);
5179
5180
5181 if (p_sei + payload_size > sei_data_buf_end) {
5182 dpb_print(DECODE_ID(hw), 0,
5183 "%s: payload_type = %d, payload_size = %d is over\n",
5184 __func__, payload_type, payload_size);
5185 return read_size;
5186 }
5187 bit_offset = 0;
5188
5189 if (payload_size <= 0) {
5190 dpb_print(DECODE_ID(hw), 0,
5191 "%s warning: this is a null sei message for payload_type = %d\n",
5192 __func__, payload_type);
5193 return read_size;
5194 }
5195 switch (payload_type) {
5196 case SEI_BUFFERING_PERIOD:
5197 break;
5198 case SEI_PicTiming:
5199 if (p_H264_Dpb->vui_status & 0xc) {
5200 int cpb_removal_delay;
5201 int dpb_output_delay;
5202 u32 delay_len;
5203
5204 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5205 cpb_removal_delay
5206 = (delay_len & 0x1F) + 1;
5207 dpb_output_delay
5208 = ((delay_len >> 5) & 0x1F) + 1;
5209
5210 get_bits(p_sei, bit_offset,
5211 &temp, payload_size,
5212 dpb_output_delay+cpb_removal_delay);
5213 bit_offset += dpb_output_delay+cpb_removal_delay;
5214 }
5215 if (p_H264_Dpb->vui_status & 0x10) {
5216 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5217 bit_offset += 4;
5218 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5219 }
5220 break;
5221 case SEI_USER_DATA:
5222 if (enable_itu_t35) {
5223 int i;
5224 int j;
5225 int data_len;
5226 u8 *user_data_buf;
5227
5228 user_data_buf
5229 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5230 /* user data length should be align with 8 bytes,
5231 if not, then padding with zero*/
5232 for (i = 0; i < payload_size; i += 8) {
5233 for (j = 0; j < 8; j++) {
5234 int index;
5235
5236 index = i+7-j;
5237 if (index >= payload_size)
5238 user_data_buf[i+j] = 0;
5239 else
5240 user_data_buf[i+j]
5241 = p_sei[i+7-j];
5242 }
5243 }
5244
5245 data_len = payload_size;
5246 if (payload_size % 8)
5247 data_len = ((payload_size + 8) >> 3) << 3;
5248
5249 hw->sei_itu_data_len += data_len;
5250 /*
5251 dpb_print(DECODE_ID(hw), 0,
5252 "%s: user data, and len = %d:\n",
5253 __func__, hw->sei_itu_data_len);
5254 */
5255 }
5256 break;
5257 case SEI_RECOVERY_POINT:
5258 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5259 break;
5260 }
5261
5262 return read_size + payload_size;
5263}
5264
5265static void parse_sei_data(struct vdec_h264_hw_s *hw,
5266 u8 *sei_data_buf,
5267 int len)
5268{
5269 char *p_sei;
5270 char *p_sei_end;
5271 int parsed_size;
5272 int read_size;
5273
5274
5275 p_sei = sei_data_buf;
5276 p_sei_end = p_sei + len;
5277 parsed_size = 0;
5278 while (parsed_size < len) {
5279 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5280 p_sei += read_size;
5281 parsed_size += read_size;
5282 if (*p_sei == 0x80) {
5283 p_sei++;
5284 parsed_size++;
5285 }
5286 }
5287}
5288
5289static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5290{
5291 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5292 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5293 unsigned mby_mbx = READ_VREG(MBY_MBX);
5294 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5295 unsigned decode_mb_count =
5296 ((mby_mbx & 0xff) * hw->mb_width +
5297 (((mby_mbx >> 8) & 0xff) + 1));
5298 if (mby_mbx == 0)
5299 return;
5300 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5301 mb_total /= 2;
5302 if (error_proc_policy & 0x100) {
5303 if (decode_mb_count < mb_total)
5304 p->data_flag |= ERROR_FLAG;
5305 }
5306
5307 if ((error_proc_policy & 0x200) &&
5308 READ_VREG(ERROR_STATUS_REG) != 0) {
5309 p->data_flag |= ERROR_FLAG;
5310 }
5311
5312 if (p->data_flag & ERROR_FLAG) {
5313 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5314 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5315 __func__,
5316 hw->seq_info2,
5317 mby_mbx,
5318 mb_total,
5319 decode_mb_count,
5320 READ_VREG(ERROR_STATUS_REG)
5321 );
5322
5323 }
5324}
5325
5326static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5327{
5328 int i;
5329 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5330 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5331 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5332 u32 debug_tag;
5333 int ret;
5334 if (++hw->tfn_cnt == 1) {
5335 hw->tfn_ns = local_clock();
5336 } else if (hw->tfn_cnt >= 10) {
5337 u64 tenth_ns = local_clock();
5338 /* Here borrow the varible debug_tag for use */
5339 debug_tag = tenth_ns - hw->tfn_ns;
5340 hw->tfn_cnt = 1;
5341 hw->tfn_cnt = tenth_ns;
5342 if (debug_tag <= 10000000) {
5343 pr_err("Within 10ms 10 vh264_isr_thread_fn. Abnormal!\n");
5344 timeout_process(hw);
5345 return IRQ_HANDLED;
5346 }
5347 }
5348
5349 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5350#if 1
5351 unsigned short *p = (unsigned short *)hw->lmem_addr;
5352 dma_sync_single_for_cpu(
5353 amports_get_dma_device(),
5354 hw->lmem_addr_remap,
5355 PAGE_SIZE,
5356 DMA_FROM_DEVICE);
5357 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5358 int ii;
5359 for (ii = 0; ii < 4; ii++) {
5360 p_H264_Dpb->dpb_param.l.data[i+ii] =
5361 p[i+3-ii];
5362 if (dpb_is_debug(DECODE_ID(hw),
5363 RRINT_FLAG_RPM)) {
5364 if (((i + ii) & 0xf) == 0)
5365 dpb_print(DECODE_ID(hw),
5366 0, "%04x:",
5367 i);
5368 dpb_print_cont(DECODE_ID(hw),
5369 0, "%04x ",
5370 p[i+3-ii]);
5371 if (((i + ii + 1) & 0xf) == 0)
5372 dpb_print_cont(
5373 DECODE_ID(hw),
5374 0, "\r\n");
5375 }
5376 }
5377 }
5378
5379 p_H264_Dpb->bitstream_restriction_flag =
5380 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5381 p_H264_Dpb->num_reorder_frames =
5382 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5383 p_H264_Dpb->max_dec_frame_buffering =
5384 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5385
5386 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5387 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5388 p_H264_Dpb->bitstream_restriction_flag,
5389 p_H264_Dpb->num_reorder_frames,
5390 p_H264_Dpb->max_dec_frame_buffering);
5391 hw->bitstream_restriction_flag =
5392 p_H264_Dpb->bitstream_restriction_flag;
5393 hw->num_reorder_frames =
5394 p_H264_Dpb->num_reorder_frames;
5395 hw->max_dec_frame_buffering =
5396 p_H264_Dpb->max_dec_frame_buffering;
5397#endif
5398
5399 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5400 reset_process_time(hw);
5401 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5402 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5403 vdec_schedule_work(&hw->work);
5404 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5405 u16 data_hight;
5406 u16 data_low;
5407 u32 video_signal;
5408
5409 int slice_header_process_status = 0;
5410 int I_flag;
5411 /*unsigned char is_idr;*/
5412 unsigned short *p = (unsigned short *)hw->lmem_addr;
5413 reset_process_time(hw);
5414
5415 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5416 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5417 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5418 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5419 if (input_frame_based(vdec) &&
5420 frmbase_cont_bitlevel2 != 0 &&
5421 READ_VREG(VIFF_BIT_CNT) <
5422 frmbase_cont_bitlevel2 &&
5423 hw->get_data_count >= 0x70000000) {
5424 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5425 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5426 __func__,
5427 READ_VREG(VIFF_BIT_CNT));
5428
5429 goto empty_proc;
5430 }
5431
5432 dma_sync_single_for_cpu(
5433 amports_get_dma_device(),
5434 hw->lmem_addr_remap,
5435 PAGE_SIZE,
5436 DMA_FROM_DEVICE);
5437#if 0
5438 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5439 if (!is_buffer_available(vdec)) {
5440 hw->buffer_empty_flag = 1;
5441 dpb_print(DECODE_ID(hw),
5442 PRINT_FLAG_UCODE_EVT,
5443 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5444 __func__,
5445 kfifo_len(&hw->newframe_q),
5446 have_free_buf_spec(vdec),
5447 p_H264_Dpb->mDPB.init_done,
5448 p_H264_Dpb->mDPB.used_size,
5449 p_H264_Dpb->mDPB.size,
5450 is_there_unused_frame_from_dpb(
5451 &p_H264_Dpb->mDPB));
5452 return IRQ_HANDLED;
5453 }
5454 }
5455
5456 hw->buffer_empty_flag = 0;
5457#endif
5458#ifdef SEND_PARAM_WITH_REG
5459 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5460 unsigned int data32;
5461
5462 do {
5463 data32 = READ_VREG(RPM_CMD_REG);
5464 /* printk("%x\n", data32); */
5465 } while ((data32&0x10000) == 0);
5466 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5467 WRITE_VREG(RPM_CMD_REG, 0);
5468 /* printk("%x:%x\n", i,data32); */
5469 }
5470#else
5471 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5472 int ii;
5473
5474 for (ii = 0; ii < 4; ii++) {
5475 p_H264_Dpb->dpb_param.l.data[i+ii] =
5476 p[i+3-ii];
5477 if (dpb_is_debug(DECODE_ID(hw),
5478 RRINT_FLAG_RPM)) {
5479 if (((i + ii) & 0xf) == 0)
5480 dpb_print(DECODE_ID(hw),
5481 0, "%04x:",
5482 i);
5483 dpb_print_cont(DECODE_ID(hw),
5484 0, "%04x ",
5485 p[i+3-ii]);
5486 if (((i + ii + 1) & 0xf) == 0)
5487 dpb_print_cont(
5488 DECODE_ID(hw),
5489 0, "\r\n");
5490 }
5491 }
5492 }
5493#endif
5494 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5495 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5496
5497 video_signal = (data_hight << 16) | data_low;
5498 hw->video_signal_from_vui =
5499 ((video_signal & 0xffff) << 8) |
5500 ((video_signal & 0xff0000) >> 16) |
5501 ((video_signal & 0x3f000000));
5502
5503
5504 /*dpb_print(DECODE_ID(hw),
5505 0,
5506 "video_signal_from_vui:0x%x, "
5507 "data_low:0x%x, data_hight:0x%x\n",
5508 hw->video_signal_from_vui,
5509 data_low,
5510 data_hight);*/
5511
5512 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5513
5514 if (hw->config_bufmgr_done == 0) {
5515 hw->dec_result = DEC_RESULT_DONE;
5516 vdec_schedule_work(&hw->work);
5517 dpb_print(DECODE_ID(hw),
5518 PRINT_FLAG_UCODE_EVT,
5519 "config_bufmgr not done, discard frame\n");
5520 return IRQ_HANDLED;
5521 } else if ((hw->first_i_policy & 0x3) != 0) {
5522 unsigned char is_i_slice =
5523 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5524 == I_Slice)
5525 ? 1 : 0;
5526 unsigned char is_idr =
5527 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5528 == 5);
5529 if ((hw->first_i_policy & 0x3) == 0x3)
5530 is_i_slice = is_idr;
5531 if (!is_i_slice) {
5532 if (hw->has_i_frame == 0) {
5533 amvdec_stop();
5534 vdec->mc_loaded = 0;
5535 hw->dec_result = DEC_RESULT_DONE;
5536 vdec_schedule_work(&hw->work);
5537 dpb_print(DECODE_ID(hw),
5538 PRINT_FLAG_UCODE_EVT,
5539 "has_i_frame is 0, discard none I(DR) frame\n");
5540 return IRQ_HANDLED;
5541 }
5542 } else {
5543 if (hw->skip_frame_count < 0 || is_idr) {
5544 /* second I */
5545 hw->dec_flag &= (~NODISP_FLAG);
5546 hw->skip_frame_count = 0;
5547 }
5548 if (hw->has_i_frame == 0 &&
5549 (!is_idr)) {
5550 int skip_count =
5551 (hw->first_i_policy >> 8) & 0xff;
5552 /* first I (not IDR) */
5553 if ((hw->first_i_policy & 0x3) == 2)
5554 hw->skip_frame_count =
5555 -1 - skip_count;
5556 else
5557 hw->skip_frame_count =
5558 skip_count;
5559 if (hw->skip_frame_count != 0)
5560 hw->dec_flag |= NODISP_FLAG;
5561 }
5562 }
5563 }
5564 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5565 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5566 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5567 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5568 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5569 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5570 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5571 ? I_FLAG : 0;
5572 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5573 (p_H264_Dpb->mSlice.structure == FRAME)) {
5574 hw->data_flag = NULL_FLAG;
5575 goto pic_done_proc;
5576 }
5577
5578 slice_header_process_status =
5579 h264_slice_header_process(p_H264_Dpb);
5580 if (hw->mmu_enable)
5581 hevc_sao_set_slice_type(hw,
5582 slice_header_process_status,
5583 hw->dpb.mSlice.idr_flag);
5584 vui_config(hw);
5585
5586 if (p_H264_Dpb->mVideo.dec_picture) {
5587 int cfg_ret = 0;
5588 bool field_pic_flag = false;
5589
5590 if (slice_header_process_status == 1) {
5591 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5592 field_pic_flag =
5593 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5594 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5595 true : false;
5596 }
5597
5598 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5599 (((unsigned long)(hw->vh264_amstream_dec_info
5600 .param)) & 0x8))) {
5601 p_H264_Dpb->fast_output_enable =
5602 H264_OUTPUT_MODE_FAST;
5603 }
5604 else
5605 p_H264_Dpb->fast_output_enable
5606 = fast_output_enable;
5607 hw->data_flag = I_flag;
5608 if ((p_H264_Dpb->
5609 dpb_param.dpb.NAL_info_mmco & 0x1f)
5610 == 5)
5611 hw->data_flag |= IDR_FLAG;
5612 dpb_print(DECODE_ID(hw),
5613 PRINT_FLAG_VDEC_STATUS,
5614 "==================> frame count %d to skip %d\n",
5615 hw->decode_pic_count+1,
5616 hw->skip_frame_count);
5617 } else if (error_proc_policy & 0x100){
5618 struct StorablePicture *p =
5619 p_H264_Dpb->mVideo.dec_picture;
5620 unsigned mby_mbx = READ_VREG(MBY_MBX);
5621 unsigned decode_mb_count =
5622 ((mby_mbx & 0xff) * hw->mb_width +
5623 (((mby_mbx >> 8) & 0xff) + 1));
5624 if (decode_mb_count <
5625 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5626 (1 + p->mb_aff_frame_flag))) {
5627 dpb_print(DECODE_ID(hw),
5628 PRINT_FLAG_VDEC_STATUS,
5629 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5630 p_H264_Dpb->dpb_param.l.
5631 data[FIRST_MB_IN_SLICE],
5632 READ_VREG(MBY_MBX),
5633 decode_mb_count);
5634 p->data_flag |= ERROR_FLAG;
5635 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5636 p->data_flag |= ERROR_FLAG;
5637 goto pic_done_proc;
5638 }
5639 }
5640
5641 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5642 hw->new_iframe_flag = 1;
5643 }
5644 if (hw->new_iframe_flag) {
5645 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5646 hw->new_iframe_flag = 0;
5647 hw->ref_err_flush_dpb_flag = 1;
5648 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5649 hw->new_iframe_flag = 0;
5650 hw->ref_err_flush_dpb_flag = 0;
5651 }
5652 }
5653
5654 if (error_proc_policy & 0x400) {
5655 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5656 if (ret != 0) {
5657 hw->reflist_error_count ++;
5658 dpb_print(DECODE_ID(hw), 0,
5659 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5660 ret,
5661 hw->decode_pic_count+1,
5662 hw->skip_frame_count,
5663 hw->reflist_error_count);
5664
5665 if (hw->ref_err_flush_dpb_flag) {
5666 flush_dpb(p_H264_Dpb);
5667 p_H264_Dpb->colocated_buf_map = 0;
5668 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5669 p_H264_Dpb->colocated_buf_map |= 1 <<
5670 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5671 }
5672 }
5673
5674 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5675 if (((error_proc_policy & 0x80)
5676 && ((hw->dec_flag &
5677 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5678 hw->reset_bufmgr_flag = 1;
5679 hw->reflist_error_count =0;
5680 amvdec_stop();
5681 vdec->mc_loaded = 0;
5682 hw->dec_result = DEC_RESULT_DONE;
5683 vdec_schedule_work(&hw->work);
5684 return IRQ_HANDLED;
5685 }
5686 } else
5687 hw->reflist_error_count = 0;
5688 }
5689 if ((error_proc_policy & 0x800)
5690 && p_H264_Dpb->dpb_error_flag != 0) {
5691 dpb_print(DECODE_ID(hw), 0,
5692 "dpb error %d\n",
5693 p_H264_Dpb->dpb_error_flag);
5694 hw->data_flag |= ERROR_FLAG;
5695 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5696 if ((error_proc_policy & 0x80) &&
5697 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5698 hw->reset_bufmgr_flag = 1;
5699 amvdec_stop();
5700 vdec->mc_loaded = 0;
5701 hw->dec_result = DEC_RESULT_DONE;
5702 vdec_schedule_work(&hw->work);
5703 return IRQ_HANDLED;
5704 }
5705 }
5706
5707 cfg_ret = config_decode_buf(hw,
5708 p_H264_Dpb->mVideo.dec_picture);
5709 if (cfg_ret < 0) {
5710 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5711 "config_decode_buf fail (%d)\n",
5712 cfg_ret);
5713 if (error_proc_policy & 0x2) {
5714 release_cur_decoding_buf(hw);
5715 /*hw->data_flag |= ERROR_FLAG;*/
5716 hw->reset_bufmgr_flag = 1;
5717 hw->dec_result = DEC_RESULT_DONE;
5718 vdec_schedule_work(&hw->work);
5719 return IRQ_HANDLED;
5720 } else
5721 hw->data_flag |= ERROR_FLAG;
5722 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5723 }
5724 }
5725
5726 if (slice_header_process_status == 1)
5727 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5728 else
5729 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5730 hw->last_mby_mbx = 0;
5731 hw->last_vld_level = 0;
5732 start_process_time(hw);
5733 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5734 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5735pic_done_proc:
5736 reset_process_time(hw);
5737
5738 if (input_frame_based(vdec) &&
5739 frmbase_cont_bitlevel != 0 &&
5740 READ_VREG(VIFF_BIT_CNT) >
5741 frmbase_cont_bitlevel) {
5742 /*handle the case: multi pictures in one packet*/
5743 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5744 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5745 __func__,
5746 hw->decode_pic_count,
5747 READ_VREG(VIFF_BIT_CNT));
5748 hw->frmbase_cont_flag = 1;
5749 } else
5750 hw->frmbase_cont_flag = 0;
5751
5752 if (p_H264_Dpb->mVideo.dec_picture) {
5753 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5754#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5755 DEL_EXIST(hw,
5756 p_H264_Dpb->mVideo.dec_picture) = 0;
5757 if (vdec->master) {
5758 struct vdec_h264_hw_s *hw_ba =
5759 (struct vdec_h264_hw_s *)
5760 vdec->master->private;
5761 if (hw_ba->last_dec_picture)
5762 DEL_EXIST(hw_ba,
5763 hw_ba->last_dec_picture)
5764 = 1;
5765 }
5766#endif
5767 mutex_lock(&hw->chunks_mutex);
5768 if (hw->chunk) {
5769 p_H264_Dpb->mVideo.dec_picture->pts =
5770 hw->chunk->pts;
5771 p_H264_Dpb->mVideo.dec_picture->pts64 =
5772 hw->chunk->pts64;
5773 p_H264_Dpb->mVideo.dec_picture->timestamp =
5774 hw->chunk->timestamp;
5775#ifdef MH264_USERDATA_ENABLE
5776 vmh264_udc_fill_vpts(hw,
5777 p_H264_Dpb->mSlice.slice_type,
5778 hw->chunk->pts, 1);
5779#endif
5780
5781#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5782 } else if (vdec->master) {
5783 /*dv enhance layer,
5784 do not checkout pts*/
5785 struct StorablePicture *pic =
5786 p_H264_Dpb->mVideo.dec_picture;
5787 pic->pts = 0;
5788 pic->pts64 = 0;
5789#endif
5790 } else {
5791 struct StorablePicture *pic =
5792 p_H264_Dpb->mVideo.dec_picture;
5793 u32 offset = pic->offset_delimiter;
5794 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5795 offset, &pic->pts, 0, &pic->pts64)) {
5796 pic->pts = 0;
5797 pic->pts64 = 0;
5798#ifdef MH264_USERDATA_ENABLE
5799 vmh264_udc_fill_vpts(hw,
5800 p_H264_Dpb->mSlice.slice_type,
5801 pic->pts, 0);
5802#endif
5803 } else {
5804#ifdef MH264_USERDATA_ENABLE
5805 vmh264_udc_fill_vpts(hw,
5806 p_H264_Dpb->mSlice.slice_type,
5807 pic->pts, 1);
5808#endif
5809 }
5810
5811 }
5812 mutex_unlock(&hw->chunks_mutex);
5813 check_decoded_pic_error(hw);
5814#ifdef ERROR_HANDLE_TEST
5815 if ((hw->data_flag & ERROR_FLAG)
5816 && (error_proc_policy & 0x80)) {
5817 release_cur_decoding_buf(hw);
5818 h264_clear_dpb(hw);
5819 hw->dec_flag = 0;
5820 hw->data_flag = 0;
5821 hw->skip_frame_count = 0;
5822 hw->has_i_frame = 0;
5823 hw->no_error_count = 0xfff;
5824 hw->no_error_i_count = 0xf;
5825 } else
5826#endif
5827 ret = store_picture_in_dpb(p_H264_Dpb,
5828 p_H264_Dpb->mVideo.dec_picture,
5829 hw->data_flag | hw->dec_flag |
5830 p_H264_Dpb->mVideo.dec_picture->data_flag);
5831
5832
5833
5834 if (ret == -1) {
5835 release_cur_decoding_buf(hw);
5836 bufmgr_force_recover(p_H264_Dpb);
5837 } else {
5838 if (hw->data_flag & ERROR_FLAG) {
5839 hw->no_error_count = 0;
5840 hw->no_error_i_count = 0;
5841 } else {
5842 hw->no_error_count++;
5843 if (hw->data_flag & I_FLAG)
5844 hw->no_error_i_count++;
5845 }
5846 if (hw->mmu_enable)
5847 hevc_set_unused_4k_buff_idx(hw,
5848 p_H264_Dpb->mVideo.
5849 dec_picture->buf_spec_num);
5850 bufmgr_post(p_H264_Dpb);
5851 hw->last_dec_picture =
5852 p_H264_Dpb->mVideo.dec_picture;
5853 p_H264_Dpb->mVideo.dec_picture = NULL;
5854 /* dump_dpb(&p_H264_Dpb->mDPB); */
5855 hw->has_i_frame = 1;
5856 if (hw->mmu_enable)
5857 hevc_set_frame_done(hw);
5858 hw->decode_pic_count++;
5859 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5860 if (hw->skip_frame_count > 0) {
5861 /*skip n frame after first I */
5862 hw->skip_frame_count--;
5863 if (hw->skip_frame_count == 0)
5864 hw->dec_flag &= (~NODISP_FLAG);
5865 } else if (hw->skip_frame_count < -1) {
5866 /*skip n frame after first I until second I */
5867 hw->skip_frame_count++;
5868 if (hw->skip_frame_count == -1)
5869 hw->dec_flag &= (~NODISP_FLAG);
5870 }
5871 }
5872 }
5873 if (hw->frmbase_cont_flag) {
5874 /*do not DEC_RESULT_GET_DATA*/
5875 hw->get_data_count = 0x7fffffff;
5876 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5877 decode_frame_count[DECODE_ID(hw)]++;
5878 start_process_time(hw);
5879 return IRQ_HANDLED;
5880 }
5881 amvdec_stop();
5882 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5883 "%s %s decode slice count %d\n",
5884 __func__,
5885 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5886 "H264_PIC_DATA_DONE" :
5887 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5888 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5889 hw->decode_pic_count);
5890 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5891 hw->dec_result = DEC_RESULT_DONE;
5892#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5893 if (vdec->slave &&
5894 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5895 struct vdec_h264_hw_s *hw_el =
5896 (struct vdec_h264_hw_s *)(vdec->slave->private);
5897 hw_el->got_valid_nal = 0;
5898 hw->switch_dvlayer_flag = 1;
5899 } else if (vdec->master &&
5900 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5901 struct vdec_h264_hw_s *hw_bl =
5902 (struct vdec_h264_hw_s *)(vdec->master->private);
5903 hw_bl->got_valid_nal = 0;
5904 hw->switch_dvlayer_flag = 1;
5905 } else {
5906 hw->switch_dvlayer_flag = 0;
5907 hw->got_valid_nal = 1;
5908 }
5909#endif
5910
5911 hw->dec_result = DEC_RESULT_DONE;
5912 vdec_schedule_work(&hw->work);
5913
5914#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5915 } else if (
5916 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5917 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5918 goto pic_done_proc;
5919#endif
5920 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5921 reset_process_time(hw);
5922 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5923 dma_sync_single_for_cpu(
5924 amports_get_dma_device(),
5925 hw->aux_phy_addr,
5926 hw->prefix_aux_size + hw->suffix_aux_size,
5927 DMA_FROM_DEVICE);
5928 if (dpb_is_debug(DECODE_ID(hw),
5929 PRINT_FLAG_DPB_DETAIL))
5930 dump_aux_buf(hw);
5931#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5932 if (vdec->dolby_meta_with_el || vdec->slave) {
5933 if (hw->last_dec_picture)
5934 set_aux_data(hw, hw->last_dec_picture,
5935 0, 0, NULL);
5936 } else {
5937 if (vdec->master) {
5938 struct vdec_h264_hw_s *hw_bl =
5939 (struct vdec_h264_hw_s *)
5940 (vdec->master->private);
5941 if (hw_bl->last_dec_picture != NULL) {
5942 set_aux_data(hw_bl,
5943 hw_bl->last_dec_picture,
5944 0, 1, hw);
5945 }
5946 set_aux_data(hw,
5947 hw->last_dec_picture,
5948 0, 2, NULL);
5949 }
5950 }
5951#else
5952 if (hw->last_dec_picture)
5953 set_aux_data(hw,
5954 hw->last_dec_picture, 0, 0, NULL);
5955#endif
5956 }
5957#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5958 hw->switch_dvlayer_flag = 0;
5959 hw->got_valid_nal = 1;
5960#endif
5961 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5962 "%s H264_AUX_DATA_READY\n", __func__);
5963 hw->dec_result = DEC_RESULT_DONE;
5964 vdec_schedule_work(&hw->work);
5965 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5966 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5967 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5968 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5969empty_proc:
5970 reset_process_time(hw);
5971 if (!hw->frmbase_cont_flag)
5972 release_cur_decoding_buf(hw);
5973
5974 if (input_frame_based(vdec) ||
5975 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
5976 if (h264_debug_flag &
5977 DISABLE_ERROR_HANDLE) {
5978 dpb_print(DECODE_ID(hw),
5979 PRINT_FLAG_ERROR,
5980 "%s decoding error, level 0x%x\n",
5981 __func__,
5982 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
5983 goto send_again;
5984 }
5985 amvdec_stop();
5986 vdec->mc_loaded = 0;
5987 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5988 "%s %s\n", __func__,
5989 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
5990 "H264_SEARCH_BUFEMPTY" :
5991 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
5992 "H264_DECODE_BUFEMPTY" :
5993 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
5994 "H264_DECODE_TIMEOUT" :
5995 "OTHER");
5996 hw->dec_result = DEC_RESULT_DONE;
5997
5998 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
5999 hw->search_dataempty_num++;
6000 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6001 hw->decode_timeout_num++;
6002 if (error_proc_policy & 0x4000) {
6003 hw->data_flag |= ERROR_FLAG;
6004 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6005 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6006 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6007 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6008 dpb_print(DECODE_ID(hw),
6009 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6010 p_H264_Dpb->last_dpb_status, __func__);
6011 hw->reset_bufmgr_flag = 1;
6012 }
6013 }
6014 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6015 hw->decode_dataempty_num++;
6016 if (!hw->frmbase_cont_flag)
6017 hw->data_flag |= ERROR_FLAG;
6018
6019 vdec_schedule_work(&hw->work);
6020 } else {
6021 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6022 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6023 "%s DEC_RESULT_AGAIN\n", __func__);
6024send_again:
6025 hw->dec_result = DEC_RESULT_AGAIN;
6026 vdec_schedule_work(&hw->work);
6027 }
6028 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6029 reset_process_time(hw);
6030 if (input_frame_based(vdec)) {
6031 dpb_print(DECODE_ID(hw),
6032 PRINT_FLAG_VDEC_STATUS,
6033 "%s H264_DATA_REQUEST (%d)\n",
6034 __func__, hw->get_data_count);
6035 hw->dec_result = DEC_RESULT_GET_DATA;
6036 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6037 hw->get_data_start_time = jiffies;
6038 hw->get_data_count++;
6039 if (hw->get_data_count >= frame_max_data_packet)
6040 goto empty_proc;
6041 vdec_schedule_work(&hw->work);
6042 } else
6043 goto empty_proc;
6044 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6045 dpb_print(DECODE_ID(hw), 0,
6046 "vmh264 decode oversize !!\n");
6047 release_cur_decoding_buf(hw);
6048 hw->data_flag |= ERROR_FLAG;
6049 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6050 reset_process_time(hw);
6051 hw->dec_result = DEC_RESULT_DONE;
6052 vdec_schedule_work(&hw->work);
6053 return IRQ_HANDLED;
6054 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6055 int aux_data_len;
6056 aux_data_len =
6057 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6058
6059 if (aux_data_len > SEI_DATA_SIZE) {
6060 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6061 "sei data size more than 4K: %d, discarded it\n",
6062 hw->sei_itu_data_len);
6063 hw->sei_itu_data_len = 0;
6064 }
6065
6066 if (aux_data_len != 0) {
6067 u8 *trans_data_buf;
6068 u8 *sei_data_buf;
6069 u8 swap_byte;
6070
6071 dma_sync_single_for_cpu(
6072 amports_get_dma_device(),
6073 hw->aux_phy_addr,
6074 hw->prefix_aux_size + hw->suffix_aux_size,
6075 DMA_FROM_DEVICE);
6076#if 0
6077 dump_aux_buf(hw);
6078#endif
6079 trans_data_buf = (u8 *)hw->aux_addr;
6080
6081 if (trans_data_buf[7] == AUX_TAG_SEI) {
6082 int left_len;
6083
6084 sei_data_buf = (u8 *)hw->sei_data_buf
6085 + hw->sei_data_len;
6086 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6087 if (aux_data_len/2 <= left_len) {
6088 for (i = 0; i < aux_data_len/2; i++)
6089 sei_data_buf[i]
6090 = trans_data_buf[i*2];
6091
6092 aux_data_len = aux_data_len / 2;
6093 for (i = 0; i < aux_data_len; i = i+4) {
6094 swap_byte = sei_data_buf[i];
6095 sei_data_buf[i]
6096 = sei_data_buf[i+3];
6097 sei_data_buf[i+3] = swap_byte;
6098
6099 swap_byte = sei_data_buf[i+1];
6100 sei_data_buf[i+1]
6101 = sei_data_buf[i+2];
6102 sei_data_buf[i+2] = swap_byte;
6103 }
6104
6105 for (i = aux_data_len-1; i >= 0; i--)
6106 if (sei_data_buf[i] != 0)
6107 break;
6108
6109 hw->sei_data_len += i+1;
6110 } else
6111 dpb_print(DECODE_ID(hw),
6112 PRINT_FLAG_ERROR,
6113 "sei data size %d and more than left space: %d, discarded it\n",
6114 hw->sei_itu_data_len,
6115 left_len);
6116 }
6117 }
6118 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6119
6120 return IRQ_HANDLED;
6121 }
6122
6123
6124 /* ucode debug */
6125 debug_tag = READ_VREG(DEBUG_REG1);
6126 if (debug_tag & 0x10000) {
6127 unsigned short *p = (unsigned short *)hw->lmem_addr;
6128
6129 dma_sync_single_for_cpu(
6130 amports_get_dma_device(),
6131 hw->lmem_addr_remap,
6132 PAGE_SIZE,
6133 DMA_FROM_DEVICE);
6134
6135 dpb_print(DECODE_ID(hw), 0,
6136 "LMEM<tag %x>:\n", debug_tag);
6137 for (i = 0; i < 0x400; i += 4) {
6138 int ii;
6139 if ((i & 0xf) == 0)
6140 dpb_print_cont(DECODE_ID(hw), 0,
6141 "%03x: ", i);
6142 for (ii = 0; ii < 4; ii++)
6143 dpb_print_cont(DECODE_ID(hw), 0,
6144 "%04x ", p[i+3-ii]);
6145 if (((i+ii) & 0xf) == 0)
6146 dpb_print_cont(DECODE_ID(hw), 0,
6147 "\n");
6148 }
6149 if (((udebug_pause_pos & 0xffff)
6150 == (debug_tag & 0xffff)) &&
6151 (udebug_pause_decode_idx == 0 ||
6152 udebug_pause_decode_idx ==
6153 hw->decode_pic_count) &&
6154 (udebug_pause_val == 0 ||
6155 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6156 udebug_pause_pos &= 0xffff;
6157 hw->ucode_pause_pos = udebug_pause_pos;
6158 }
6159 else if (debug_tag & 0x20000)
6160 hw->ucode_pause_pos = 0xffffffff;
6161 if (hw->ucode_pause_pos)
6162 reset_process_time(hw);
6163 else
6164 WRITE_VREG(DEBUG_REG1, 0);
6165 } else if (debug_tag != 0) {
6166 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6167 "dbg%x: %x\n", debug_tag,
6168 READ_VREG(DEBUG_REG2));
6169 if (((udebug_pause_pos & 0xffff)
6170 == (debug_tag & 0xffff)) &&
6171 (udebug_pause_decode_idx == 0 ||
6172 udebug_pause_decode_idx ==
6173 hw->decode_pic_count) &&
6174 (udebug_pause_val == 0 ||
6175 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6176 udebug_pause_pos &= 0xffff;
6177 hw->ucode_pause_pos = udebug_pause_pos;
6178 }
6179 if (hw->ucode_pause_pos)
6180 reset_process_time(hw);
6181 else
6182 WRITE_VREG(DEBUG_REG1, 0);
6183 }
6184 /**/
6185 return IRQ_HANDLED;
6186}
6187
6188static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6189{
6190 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6191 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6192
6193
6194 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6195
6196 if (!hw)
6197 return IRQ_HANDLED;
6198
6199 if (hw->eos)
6200 return IRQ_HANDLED;
6201
6202 p_H264_Dpb->vdec = vdec;
6203 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6204
6205 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6206 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6207 __func__,
6208 p_H264_Dpb->dec_dpb_status,
6209 READ_VREG(ERROR_STATUS_REG),
6210 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6211 READ_VREG(VLD_MEM_VIFIFO_WP),
6212 READ_VREG(VLD_MEM_VIFIFO_RP),
6213 READ_VREG(VIFF_BIT_CNT),
6214 READ_VREG(MBY_MBX));
6215
6216 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6217 if (hw->mmu_enable)
6218 hevc_sao_wait_done(hw);
6219 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6220 return IRQ_HANDLED;
6221 }
6222 return IRQ_WAKE_THREAD;
6223
6224}
6225
6226static void timeout_process(struct vdec_h264_hw_s *hw)
6227{
6228 struct vdec_s *vdec = hw_to_vdec(hw);
6229 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6230
6231 /*
6232 * In this very timeout point,the vh264_work arrives,
6233 * let it to handle the scenario.
6234 */
6235 if (work_pending(&hw->work))
6236 return;
6237
6238 hw->timeout_num++;
6239 amvdec_stop();
6240 vdec->mc_loaded = 0;
6241 if (hw->mmu_enable) {
6242 hevc_set_frame_done(hw);
6243 hevc_sao_wait_done(hw);
6244 }
6245 if (!hw->i_only && (error_proc_policy & 0x2))
6246 flush_dpb(p_H264_Dpb);
6247 dpb_print(DECODE_ID(hw),
6248 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6249 release_cur_decoding_buf(hw);
6250 hw->dec_result = DEC_RESULT_DONE;
6251 hw->data_flag |= ERROR_FLAG;
6252
6253 if (work_pending(&hw->work))
6254 return;
6255 vdec_schedule_work(&hw->timeout_work);
6256}
6257
6258static void dump_bufspec(struct vdec_h264_hw_s *hw,
6259 const char *caller)
6260{
6261 int i;
6262 dpb_print(DECODE_ID(hw), 0,
6263 "%s in %s:\n", __func__, caller);
6264 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6265 if (hw->buffer_spec[i].used == -1)
6266 continue;
6267 dpb_print(DECODE_ID(hw), 0,
6268 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6269 i, hw->buffer_spec[i].used,
6270 hw->buffer_spec[i].buf_adr,
6271 hw->buffer_spec[i].canvas_pos,
6272 hw->buffer_spec[i].vf_ref
6273 );
6274#ifdef CONFIG_AM_VDEC_DV
6275 dpb_print_cont(DECODE_ID(hw), 0,
6276 "dv_el_exist %d",
6277 hw->buffer_spec[i].dv_enhance_exist
6278 );
6279#endif
6280 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6281 }
6282
6283}
6284
6285static void vmh264_dump_state(struct vdec_s *vdec)
6286{
6287 struct vdec_h264_hw_s *hw =
6288 (struct vdec_h264_hw_s *)(vdec->private);
6289 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6290 dpb_print(DECODE_ID(hw), 0,
6291 "====== %s\n", __func__);
6292 dpb_print(DECODE_ID(hw), 0,
6293 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6294 hw->frame_width,
6295 hw->frame_height,
6296 hw->dpb.reorder_pic_num,
6297 hw->dpb.mDPB.size,
6298 hw->max_reference_size,
6299 hw->i_only,
6300 hw->send_error_frame_flag
6301 );
6302
6303 dpb_print(DECODE_ID(hw), 0,
6304 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6305 input_frame_based(vdec),
6306 hw->eos,
6307 hw->stat,
6308 hw->dec_result,
6309 decode_frame_count[DECODE_ID(hw)],
6310 display_frame_count[DECODE_ID(hw)],
6311 run_count[DECODE_ID(hw)],
6312 not_run_ready[DECODE_ID(hw)],
6313 input_empty[DECODE_ID(hw)],
6314 hw->reset_bufmgr_count
6315 );
6316
6317 if (vf_get_receiver(vdec->vf_provider_name)) {
6318 enum receviver_start_e state =
6319 vf_notify_receiver(vdec->vf_provider_name,
6320 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6321 NULL);
6322 dpb_print(DECODE_ID(hw), 0,
6323 "\nreceiver(%s) state %d\n",
6324 vdec->vf_provider_name,
6325 state);
6326 }
6327
6328 dpb_print(DECODE_ID(hw), 0,
6329 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x\n",
6330 __func__,
6331 kfifo_len(&hw->newframe_q),
6332 VF_POOL_SIZE,
6333 kfifo_len(&hw->display_q),
6334 VF_POOL_SIZE,
6335 hw->vf_pre_count,
6336 hw->vf_get_count,
6337 hw->vf_put_count,
6338 have_free_buf_spec(vdec),
6339 p_H264_Dpb->mDPB.init_done,
6340 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6341 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6342 p_H264_Dpb->fast_output_enable
6343 );
6344
6345 dump_dpb(&p_H264_Dpb->mDPB, 1);
6346 dump_pic(p_H264_Dpb);
6347 dump_bufspec(hw, __func__);
6348
6349 dpb_print(DECODE_ID(hw), 0,
6350 "DPB_STATUS_REG=0x%x\n",
6351 READ_VREG(DPB_STATUS_REG));
6352 dpb_print(DECODE_ID(hw), 0,
6353 "MPC_E=0x%x\n",
6354 READ_VREG(MPC_E));
6355 dpb_print(DECODE_ID(hw), 0,
6356 "H264_DECODE_MODE=0x%x\n",
6357 READ_VREG(H264_DECODE_MODE));
6358 dpb_print(DECODE_ID(hw), 0,
6359 "MBY_MBX=0x%x\n",
6360 READ_VREG(MBY_MBX));
6361 dpb_print(DECODE_ID(hw), 0,
6362 "H264_DECODE_SIZE=0x%x\n",
6363 READ_VREG(H264_DECODE_SIZE));
6364 dpb_print(DECODE_ID(hw), 0,
6365 "VIFF_BIT_CNT=0x%x\n",
6366 READ_VREG(VIFF_BIT_CNT));
6367 dpb_print(DECODE_ID(hw), 0,
6368 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6369 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6370 dpb_print(DECODE_ID(hw), 0,
6371 "VLD_MEM_VIFIFO_WP=0x%x\n",
6372 READ_VREG(VLD_MEM_VIFIFO_WP));
6373 dpb_print(DECODE_ID(hw), 0,
6374 "VLD_MEM_VIFIFO_RP=0x%x\n",
6375 READ_VREG(VLD_MEM_VIFIFO_RP));
6376 dpb_print(DECODE_ID(hw), 0,
6377 "PARSER_VIDEO_RP=0x%x\n",
6378 READ_PARSER_REG(PARSER_VIDEO_RP));
6379 dpb_print(DECODE_ID(hw), 0,
6380 "PARSER_VIDEO_WP=0x%x\n",
6381 READ_PARSER_REG(PARSER_VIDEO_WP));
6382
6383 if (input_frame_based(vdec) &&
6384 dpb_is_debug(DECODE_ID(hw),
6385 PRINT_FRAMEBASE_DATA)
6386 ) {
6387 int jj;
6388 if (hw->chunk && hw->chunk->block &&
6389 hw->chunk->size > 0) {
6390 u8 *data = NULL;
6391
6392 if (!hw->chunk->block->is_mapped)
6393 data = codec_mm_vmap(hw->chunk->block->start +
6394 hw->chunk->offset, hw->chunk->size);
6395 else
6396 data = ((u8 *)hw->chunk->block->start_virt)
6397 + hw->chunk->offset;
6398
6399 dpb_print(DECODE_ID(hw), 0,
6400 "frame data size 0x%x\n",
6401 hw->chunk->size);
6402 for (jj = 0; jj < hw->chunk->size; jj++) {
6403 if ((jj & 0xf) == 0)
6404 dpb_print(DECODE_ID(hw),
6405 PRINT_FRAMEBASE_DATA,
6406 "%06x:", jj);
6407 dpb_print_cont(DECODE_ID(hw),
6408 PRINT_FRAMEBASE_DATA,
6409 "%02x ", data[jj]);
6410 if (((jj + 1) & 0xf) == 0)
6411 dpb_print_cont(DECODE_ID(hw),
6412 PRINT_FRAMEBASE_DATA,
6413 "\n");
6414 }
6415
6416 if (!hw->chunk->block->is_mapped)
6417 codec_mm_unmap_phyaddr(data);
6418 }
6419 }
6420}
6421
6422
6423static void check_timer_func(unsigned long arg)
6424{
6425 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6426 struct vdec_s *vdec = hw_to_vdec(hw);
6427 int error_skip_frame_count = error_skip_count & 0xfff;
6428 unsigned int timeout_val = decode_timeout_val;
6429 if (timeout_val != 0 &&
6430 hw->no_error_count < error_skip_frame_count)
6431 timeout_val = errordata_timeout_val;
6432 if ((h264_debug_cmd & 0x100) != 0 &&
6433 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6434 hw->dec_result = DEC_RESULT_DONE;
6435 vdec_schedule_work(&hw->work);
6436 pr_info("vdec %d is forced to be disconnected\n",
6437 h264_debug_cmd & 0xff);
6438 h264_debug_cmd = 0;
6439 return;
6440 }
6441 if ((h264_debug_cmd & 0x200) != 0 &&
6442 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6443 pr_debug("vdec %d is forced to reset bufmgr\n",
6444 h264_debug_cmd & 0xff);
6445 hw->reset_bufmgr_flag = 1;
6446 h264_debug_cmd = 0;
6447 return;
6448 }
6449
6450 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6451 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6452 vdec_schedule_work(&hw->work);
6453 pr_debug("vdec requested to be disconnected\n");
6454 return;
6455 }
6456
6457 if (radr != 0) {
6458 if (rval != 0) {
6459 WRITE_VREG(radr, rval);
6460 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6461 } else
6462 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6463 rval = 0;
6464 radr = 0;
6465 }
6466
6467 if ((input_frame_based(vdec) ||
6468 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6469 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6470 (timeout_val > 0) &&
6471 (hw->start_process_time > 0) &&
6472 ((1000 * (jiffies - hw->start_process_time) / HZ)
6473 > timeout_val)
6474 ) {
6475 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6476 u32 mby_mbx = READ_VREG(MBY_MBX);
6477 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6478 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6479 if (hw->last_mby_mbx == mby_mbx) {
6480 if (hw->decode_timeout_count > 0)
6481 hw->decode_timeout_count--;
6482 if (hw->decode_timeout_count == 0)
6483 {
6484 reset_process_time(hw);
6485 timeout_process(hw);
6486 }
6487 } else
6488 start_process_time(hw);
6489 } else if (is_in_parsing_state(dpb_status)) {
6490 if (hw->last_vld_level ==
6491 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6492 if (hw->decode_timeout_count > 0)
6493 hw->decode_timeout_count--;
6494 if (hw->decode_timeout_count == 0)
6495 {
6496 reset_process_time(hw);
6497 timeout_process(hw);
6498 }
6499 }
6500 }
6501 hw->last_vld_level =
6502 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6503 hw->last_mby_mbx = mby_mbx;
6504 }
6505
6506 if ((hw->ucode_pause_pos != 0) &&
6507 (hw->ucode_pause_pos != 0xffffffff) &&
6508 udebug_pause_pos != hw->ucode_pause_pos) {
6509 hw->ucode_pause_pos = 0;
6510 WRITE_VREG(DEBUG_REG1, 0);
6511 }
6512
6513 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6514}
6515
6516static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6517{
6518 u32 ar;
6519 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6520
6521 if (!hw)
6522 return -1;
6523
6524 vstatus->frame_width = hw->frame_width;
6525 vstatus->frame_height = hw->frame_height;
6526 if (hw->frame_dur != 0)
6527 vstatus->frame_rate = 96000 / hw->frame_dur;
6528 else
6529 vstatus->frame_rate = -1;
6530 vstatus->error_count = 0;
6531 vstatus->status = hw->stat;
6532 if (hw->h264_ar == 0x3ff)
6533 hw->h264_ar = (0x100 *
6534 hw->frame_height * hw->height_aspect_ratio) /
6535 (hw->frame_width * hw->width_aspect_ratio);
6536 ar = min_t(u32,
6537 hw->h264_ar,
6538 DISP_RATIO_ASPECT_RATIO_MAX);
6539 vstatus->ratio_control =
6540 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6541
6542 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6543 "%s-%02d", DRIVER_NAME, hw->id);
6544
6545 return 0;
6546}
6547
6548static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6549{
6550 int i, j;
6551 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6552
6553 /* if (hw->init_flag == 0) { */
6554 if (h264_debug_flag & 0x40000000) {
6555 /* if (1) */
6556 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6557 "%s, reset register\n", __func__);
6558
6559 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6560 ;
6561 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6562 ; /* reg address is 0x350 */
6563
6564#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6565 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6566 WRITE_VREG(DOS_SW_RESET0, 0);
6567
6568 READ_VREG(DOS_SW_RESET0);
6569 READ_VREG(DOS_SW_RESET0);
6570 READ_VREG(DOS_SW_RESET0);
6571
6572 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6573 WRITE_VREG(DOS_SW_RESET0, 0);
6574
6575 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6576 WRITE_VREG(DOS_SW_RESET0, 0);
6577
6578 READ_VREG(DOS_SW_RESET0);
6579 READ_VREG(DOS_SW_RESET0);
6580 READ_VREG(DOS_SW_RESET0);
6581
6582#else
6583 WRITE_RESET_REG(RESET0_REGISTER,
6584 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6585 READ_RESET_REG(RESET0_REGISTER);
6586 WRITE_RESET_REG(RESET0_REGISTER,
6587 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6588
6589 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6590#endif
6591 WRITE_VREG(POWER_CTL_VLD,
6592 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6593 (1 << 9) | (1 << 6));
6594 } else {
6595 /* WRITE_VREG(POWER_CTL_VLD,
6596 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6597 */
6598 WRITE_VREG(POWER_CTL_VLD,
6599 READ_VREG(POWER_CTL_VLD) |
6600 (0 << 10) | (1 << 9) | (1 << 6));
6601 }
6602 /* disable PSCALE for hardware sharing */
6603 WRITE_VREG(PSCALE_CTRL, 0);
6604
6605 /* clear mailbox interrupt */
6606 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6607
6608 /* enable mailbox interrupt */
6609 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6610
6611#ifdef NV21
6612 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6613#endif
6614
6615 /* cbcr_merge_swap_en */
6616 if (hw->is_used_v4l && v4l2_ctx->ada_ctx->vfm_path
6617 != FRAME_BASE_PATH_V4L_VIDEO)
6618 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6619
6620 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6621 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6622
6623 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6624 if (hw->mmu_enable) {
6625 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6626 /* sw reset to extif hardware */
6627 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6628 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6629 } else {
6630 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6631 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6632 }
6633
6634
6635#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6636 /* pr_info("vh264 meson8 prot init\n"); */
6637 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6638#endif
6639
6640#ifdef VDEC_DW
6641 if (IS_VDEC_DW(hw)) {
6642 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6643
6644 if (IS_VDEC_DW(hw) == 2)
6645 data |= (1 << 9);
6646 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6647 }
6648#endif
6649 if (hw->dpb.mDPB.size > 0) {
6650 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6651 (hw->dpb.mDPB.size << 16) |
6652 (hw->dpb.mDPB.size << 8));
6653
6654 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6655 i = get_buf_spec_by_canvas_pos(hw, j);
6656 if (i < 0)
6657 break;
6658
6659 if (!hw->mmu_enable &&
6660 hw->buffer_spec[i].cma_alloc_addr)
6661 config_decode_canvas(hw, i);
6662 if (hw->mmu_enable && hw->double_write_mode)
6663 config_decode_canvas_ex(hw, i);
6664 }
6665 } else {
6666 WRITE_VREG(AV_SCRATCH_0, 0);
6667 WRITE_VREG(AV_SCRATCH_9, 0);
6668 }
6669
6670 if (hw->init_flag == 0)
6671 WRITE_VREG(DPB_STATUS_REG, 0);
6672 else
6673 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6674
6675 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6676 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6677 if (!tee_enabled())
6678 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6679
6680 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6681 * error_recovery_mode : error_recovery_mode_in;
6682 */
6683 /* WRITE_VREG(AV_SCRATCH_F,
6684 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6685 */
6686 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6687 ((error_recovery_mode_in & 0x1) << 4));
6688 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6689 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6690 else*/
6691 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6692
6693 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6694#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6695 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6696#endif
6697
6698 WRITE_VREG(DEBUG_REG1, 0);
6699 WRITE_VREG(DEBUG_REG2, 0);
6700
6701 if (hw->reg_iqidct_control)
6702 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6703 if (hw->reg_vcop_ctrl_reg)
6704 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6705 if (hw->vld_dec_control)
6706 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6707 return 0;
6708}
6709
6710static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6711{
6712 struct vdec_h264_hw_s *hw =
6713 (struct vdec_h264_hw_s *)vdec->private;
6714 if (i_only_flag & 0x100)
6715 return 0;
6716 if (trickmode == TRICKMODE_I)
6717 hw->i_only = 0x3;
6718 else if (trickmode == TRICKMODE_NONE)
6719 hw->i_only = 0x0;
6720 return 0;
6721}
6722
6723static unsigned char amvdec_enable_flag;
6724static void vh264_local_init(struct vdec_h264_hw_s *hw)
6725{
6726 int i;
6727 hw->init_flag = 0;
6728 hw->first_sc_checked= 0;
6729 hw->eos = 0;
6730 hw->valve_count = 0;
6731 hw->config_bufmgr_done = 0;
6732 hw->start_process_time = 0;
6733 hw->has_i_frame = 0;
6734 hw->no_error_count = 0xfff;
6735 hw->no_error_i_count = 0xf;
6736
6737 hw->dec_flag = 0;
6738 hw->data_flag = 0;
6739 hw->skip_frame_count = 0;
6740 hw->reg_iqidct_control = 0;
6741 hw->reg_vcop_ctrl_reg = 0;
6742 hw->reg_rv_ai_mb_count = 0;
6743 hw->vld_dec_control = 0;
6744 hw->decode_timeout_count = 0;
6745 hw->no_mem_count = 0;
6746 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6747 /* vh264_ratio = 0x100; */
6748
6749 hw->vh264_rotation = (((unsigned long)
6750 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6751
6752 hw->frame_prog = 0;
6753 hw->frame_width = hw->vh264_amstream_dec_info.width;
6754 hw->frame_height = hw->vh264_amstream_dec_info.height;
6755 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6756 hw->pts_outside = ((unsigned long)
6757 hw->vh264_amstream_dec_info.param) & 0x01;
6758 hw->sync_outside = ((unsigned long)
6759 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6760 hw->use_idr_framerate = ((unsigned long)
6761 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6762 hw->max_refer_buf = !(((unsigned long)
6763 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6764 if (hw->frame_dur < 96000/960) {
6765 /*more than 960fps,it should not be a correct value,
6766 *give default 30fps
6767 */
6768 hw->frame_dur = 96000/30;
6769 }
6770
6771 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6772
6773 hw->first_i_policy = first_i_policy;
6774
6775 hw->is_used_v4l = (((unsigned long)
6776 hw->vh264_amstream_dec_info.param & 0x80) >> 7);
6777
6778 if (hw->is_used_v4l)
6779 mem_map_mode = CANVAS_BLKMODE_LINEAR;
6780
6781 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6782 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6783 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6784 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6785
6786 if (i_only_flag & 0x100)
6787 hw->i_only = i_only_flag & 0xff;
6788 if (hw->i_only)
6789 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6790
6791 if ((unsigned long) hw->vh264_amstream_dec_info.param
6792 & 0x08)
6793 hw->no_poc_reorder_flag = 1;
6794
6795 error_recovery_mode_in = 1; /*ucode control?*/
6796 if (error_proc_policy & 0x80000000)
6797 hw->send_error_frame_flag = error_proc_policy & 0x1;
6798 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6799 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6800
6801 INIT_KFIFO(hw->display_q);
6802 INIT_KFIFO(hw->newframe_q);
6803
6804 for (i = 0; i < VF_POOL_SIZE; i++) {
6805 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6806 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6807 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6808 kfifo_put(&hw->newframe_q, vf);
6809 }
6810
6811 hw->duration_from_pts_done = 0;
6812
6813 hw->p_last_vf = NULL;
6814 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6815 hw->hevc_cur_buf_idx = 0xffff;
6816
6817 init_waitqueue_head(&hw->wait_q);
6818
6819 return;
6820}
6821
6822static s32 vh264_init(struct vdec_h264_hw_s *hw)
6823{
6824 int size = -1;
6825 int fw_size = 0x1000 * 16;
6826 int fw_mmu_size = 0x1000 * 16;
6827 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6828
6829 /* int trickmode_fffb = 0; */
6830
6831 /* pr_info("\nvh264_init\n"); */
6832 /* init_timer(&hw->recycle_timer); */
6833
6834 /* timer init */
6835 init_timer(&hw->check_timer);
6836
6837 hw->check_timer.data = (unsigned long)hw;
6838 hw->check_timer.function = check_timer_func;
6839 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6840
6841 /* add_timer(&hw->check_timer); */
6842 hw->stat |= STAT_TIMER_ARM;
6843 hw->stat |= STAT_ISR_REG;
6844
6845 mutex_init(&hw->chunks_mutex);
6846 vh264_local_init(hw);
6847 INIT_WORK(&hw->work, vh264_work);
6848 INIT_WORK(&hw->notify_work, vh264_notify_work);
6849 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6850#ifdef MH264_USERDATA_ENABLE
6851 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6852#endif
6853
6854 if (!amvdec_enable_flag) {
6855 amvdec_enable_flag = true;
6856 amvdec_enable();
6857 if (hw->mmu_enable)
6858 amhevc_enable();
6859 }
6860 if (hw->mmu_enable) {
6861
6862 hw->frame_mmu_map_addr =
6863 dma_alloc_coherent(amports_get_dma_device(),
6864 FRAME_MMU_MAP_SIZE,
6865 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6866 if (hw->frame_mmu_map_addr == NULL) {
6867 pr_err("%s: failed to alloc count_buffer\n", __func__);
6868 return -ENOMEM;
6869 }
6870 }
6871
6872 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6873 if (IS_ERR_OR_NULL(fw))
6874 return -ENOMEM;
6875
6876 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6877 if (size < 0) {
6878 pr_err("get firmware fail.\n");
6879 vfree(fw);
6880 return -1;
6881 }
6882
6883 fw->len = size;
6884 hw->fw = fw;
6885
6886 if (hw->mmu_enable) {
6887 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6888 if (IS_ERR_OR_NULL(fw_mmu))
6889 return -ENOMEM;
6890
6891 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6892 if (size < 0) {
6893 pr_err("get mmu fw fail.\n");
6894 vfree(fw_mmu);
6895 return -1;
6896 }
6897
6898 fw_mmu->len = size;
6899 hw->fw_mmu = fw_mmu;
6900 }
6901
6902 if (!tee_enabled()) {
6903 /* -- ucode loading (amrisc and swap code) */
6904 hw->mc_cpu_addr =
6905 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6906 &hw->mc_dma_handle, GFP_KERNEL);
6907 if (!hw->mc_cpu_addr) {
6908 amvdec_enable_flag = false;
6909 amvdec_disable();
6910 if (hw->mmu_enable)
6911 amhevc_disable();
6912 pr_info("vh264_init: Can not allocate mc memory.\n");
6913 return -ENOMEM;
6914 }
6915
6916 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6917 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6918 */
6919
6920 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6921
6922 /*header*/
6923 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6924 fw->data + 0x4000, MC_SWAP_SIZE);
6925 /*data*/
6926 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6927 fw->data + 0x2000, MC_SWAP_SIZE);
6928 /*mmco*/
6929 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6930 fw->data + 0x6000, MC_SWAP_SIZE);
6931 /*list*/
6932 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6933 fw->data + 0x3000, MC_SWAP_SIZE);
6934 /*slice*/
6935 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6936 fw->data + 0x5000, MC_SWAP_SIZE);
6937 /*main*/
6938 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6939 fw->data, 0x2000);
6940 /*data*/
6941 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6942 fw->data + 0x2000, 0x1000);
6943 /*slice*/
6944 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6945 fw->data + 0x5000, 0x1000);
6946 }
6947
6948#if 1 /* #ifdef BUFFER_MGR_IN_C */
6949 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6950 if (!hw->lmem_addr) {
6951 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6952 return -ENOMEM;
6953 } else {
6954 hw->lmem_addr_remap = dma_map_single(
6955 amports_get_dma_device(),
6956 (void *)hw->lmem_addr,
6957 PAGE_SIZE, DMA_FROM_DEVICE);
6958 if (dma_mapping_error(amports_get_dma_device(),
6959 hw->lmem_addr_remap)) {
6960 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6961 "%s: failed to map lmem_addr\n", __func__);
6962 free_page(hw->lmem_addr);
6963 hw->lmem_addr = 0;
6964 hw->lmem_addr_remap = 0;
6965 return -ENOMEM;
6966 }
6967
6968 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6969 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6970 }
6971
6972 if (prefix_aux_buf_size > 0 ||
6973 suffix_aux_buf_size > 0) {
6974 u32 aux_buf_size;
6975 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6976 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
6977 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
6978 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
6979 if (hw->aux_addr == NULL) {
6980 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6981 return -1;
6982 }
6983
6984 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
6985 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
6986 if (dma_mapping_error(amports_get_dma_device(),
6987 hw->aux_phy_addr)) {
6988 pr_err("%s: failed to map rpm buffer\n", __func__);
6989 kfree(hw->aux_addr);
6990 hw->aux_addr = NULL;
6991 return -1;
6992 }
6993 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
6994 if (hw->sei_data_buf == NULL) {
6995 pr_err("%s: failed to alloc sei itu data buffer\n",
6996 __func__);
6997 return -1;
6998 }
6999 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7000 if (hw->sei_itu_data_buf == NULL) {
7001 pr_err("%s: failed to alloc sei itu data buffer\n",
7002 __func__);
7003 kfree(hw->aux_addr);
7004 hw->aux_addr = NULL;
7005 kfree(hw->sei_data_buf);
7006 hw->sei_data_buf = NULL;
7007
7008 return -1;
7009 }
7010
7011 if (NULL == hw->sei_user_data_buffer) {
7012 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7013 GFP_KERNEL);
7014 if (!hw->sei_user_data_buffer) {
7015 pr_info("%s: Can not allocate sei_data_buffer\n",
7016 __func__);
7017 kfree(hw->aux_addr);
7018 hw->aux_addr = NULL;
7019 kfree(hw->sei_data_buf);
7020 hw->sei_data_buf = NULL;
7021 kfree(hw->sei_itu_data_buf);
7022 hw->sei_itu_data_buf = NULL;
7023
7024 return -1;
7025 }
7026 hw->sei_user_data_wp = 0;
7027 }
7028 }
7029/* BUFFER_MGR_IN_C */
7030#endif
7031 hw->stat |= STAT_MC_LOAD;
7032
7033 /* add memory barrier */
7034 wmb();
7035
7036 return 0;
7037}
7038
7039static int vh264_stop(struct vdec_h264_hw_s *hw)
7040{
7041 if (hw->stat & STAT_VDEC_RUN) {
7042 amvdec_stop();
7043 hw->stat &= ~STAT_VDEC_RUN;
7044 }
7045#ifdef VDEC_DW
7046 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7047#endif
7048#ifdef MH264_USERDATA_ENABLE
7049 cancel_work_sync(&hw->user_data_ready_work);
7050#endif
7051 cancel_work_sync(&hw->notify_work);
7052 cancel_work_sync(&hw->timeout_work);
7053 cancel_work_sync(&hw->work);
7054
7055
7056 if (hw->stat & STAT_MC_LOAD) {
7057 if (hw->mc_cpu_addr != NULL) {
7058 dma_free_coherent(amports_get_dma_device(),
7059 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7060 hw->mc_dma_handle);
7061 hw->mc_cpu_addr = NULL;
7062 }
7063 if (hw->frame_mmu_map_addr != NULL) {
7064 dma_free_coherent(amports_get_dma_device(),
7065 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7066 hw->frame_mmu_map_phy_addr);
7067 hw->frame_mmu_map_addr = NULL;
7068 }
7069
7070 }
7071 if (hw->stat & STAT_ISR_REG) {
7072 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7073 hw->stat &= ~STAT_ISR_REG;
7074 }
7075 if (hw->lmem_addr_remap) {
7076 dma_unmap_single(amports_get_dma_device(),
7077 hw->lmem_addr_remap,
7078 PAGE_SIZE, DMA_FROM_DEVICE);
7079 hw->lmem_addr_remap = 0;
7080 }
7081 if (hw->lmem_addr) {
7082 free_page(hw->lmem_addr);
7083 hw->lmem_addr = 0;
7084 }
7085 if (hw->aux_addr) {
7086 dma_unmap_single(amports_get_dma_device(),
7087 hw->aux_phy_addr,
7088 hw->prefix_aux_size + hw->suffix_aux_size,
7089 DMA_FROM_DEVICE);
7090 kfree(hw->aux_addr);
7091 hw->aux_addr = NULL;
7092 }
7093 if (hw->sei_data_buf != NULL) {
7094 kfree(hw->sei_data_buf);
7095 hw->sei_data_buf = NULL;
7096 }
7097 if (hw->sei_itu_data_buf != NULL) {
7098 kfree(hw->sei_itu_data_buf);
7099 hw->sei_itu_data_buf = NULL;
7100 }
7101 if (hw->sei_user_data_buffer != NULL) {
7102 kfree(hw->sei_user_data_buffer);
7103 hw->sei_user_data_buffer = NULL;
7104 }
7105 /* amvdec_disable(); */
7106
7107 vfree(hw->fw);
7108 hw->fw = NULL;
7109
7110 if (hw->mmu_enable) {
7111 vfree(hw->fw_mmu);
7112 hw->fw_mmu = NULL;
7113 }
7114
7115 dpb_print(DECODE_ID(hw), 0,
7116 "%s\n",
7117 __func__);
7118 return 0;
7119}
7120
7121static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7122{
7123 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7124 int count = 0;
7125 do {
7126 usleep_range(100, 500);
7127 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7128 break;
7129 if (count > 2000) {
7130 dpb_print(DECODE_ID(hw),
7131 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7132 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7133 break;
7134 } else
7135 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7136 count++;
7137 } while (1);
7138}
7139
7140static void vh264_notify_work(struct work_struct *work)
7141{
7142 struct vdec_h264_hw_s *hw = container_of(work,
7143 struct vdec_h264_hw_s, notify_work);
7144 struct vdec_s *vdec = hw_to_vdec(hw);
7145 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7146 vf_notify_receiver(vdec->vf_provider_name,
7147 VFRAME_EVENT_PROVIDER_FR_HINT,
7148 (void *)((unsigned long)hw->frame_dur));
7149 vdec->fr_hint_state = VDEC_HINTED;
7150 }
7151
7152 return;
7153}
7154
7155#ifdef MH264_USERDATA_ENABLE
7156static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7157{
7158 hw->wait_for_udr_send = 0;
7159 hw->sei_itu_data_len = 0;
7160 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7161}
7162
7163static void vmh264_crate_userdata_manager(
7164 struct vdec_h264_hw_s *hw,
7165 u8 *userdata_buf,
7166 int buf_len)
7167{
7168 if (hw) {
7169
7170
7171 mutex_init(&hw->userdata_mutex);
7172
7173 memset(&hw->userdata_info, 0,
7174 sizeof(struct mh264_userdata_info_t));
7175 hw->userdata_info.data_buf = userdata_buf;
7176 hw->userdata_info.buf_len = buf_len;
7177 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7178
7179 vmh264_reset_udr_mgr(hw);
7180
7181 }
7182}
7183
7184static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7185{
7186 if (hw)
7187 memset(&hw->userdata_info,
7188 0,
7189 sizeof(struct mh264_userdata_info_t));
7190}
7191
7192/*
7193#define DUMP_USERDATA_RECORD
7194*/
7195#ifdef DUMP_USERDATA_RECORD
7196
7197#define MAX_USER_DATA_SIZE 3145728
7198static void *user_data_buf;
7199static unsigned char *pbuf_start;
7200static int total_len;
7201static int bskip;
7202static int n_userdata_id;
7203
7204static void print_data(unsigned char *pdata,
7205 int len,
7206 unsigned int poc_number,
7207 unsigned int flag,
7208 unsigned int duration,
7209 unsigned int vpts,
7210 unsigned int vpts_valid,
7211 int rec_id)
7212{
7213 int nLeft;
7214
7215 nLeft = len;
7216#if 0
7217 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7218 rec_id, len, flag,
7219 duration, vpts, vpts_valid, poc_number);
7220#endif
7221 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7222 rec_id, len, flag, vpts);
7223
7224 if (len == 96) {
7225 int i;
7226 nLeft = 72;
7227 while (nLeft >= 16) {
7228 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7229 pdata[0], pdata[1], pdata[2], pdata[3],
7230 pdata[4], pdata[5], pdata[6], pdata[7],
7231 pdata[8], pdata[9], pdata[10], pdata[11],
7232 pdata[12], pdata[13], pdata[14], pdata[15]);
7233 nLeft -= 16;
7234 pdata += 16;
7235 }
7236
7237
7238 while (nLeft > 0) {
7239 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7240 pdata[0], pdata[1], pdata[2], pdata[3],
7241 pdata[4], pdata[5], pdata[6], pdata[7]);
7242 nLeft -= 8;
7243 pdata += 8;
7244 }
7245
7246 i = 0;
7247 nLeft = 96-72;
7248 while (i < nLeft) {
7249 if (pdata[0] != 0) {
7250 pr_info("some data error\n");
7251 break;
7252 }
7253 pdata++;
7254 i++;
7255 }
7256 } else {
7257 while (nLeft >= 16) {
7258 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7259 pdata[0], pdata[1], pdata[2], pdata[3],
7260 pdata[4], pdata[5], pdata[6], pdata[7],
7261 pdata[8], pdata[9], pdata[10], pdata[11],
7262 pdata[12], pdata[13], pdata[14], pdata[15]);
7263 nLeft -= 16;
7264 pdata += 16;
7265 }
7266
7267
7268 while (nLeft > 0) {
7269 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7270 pdata[0], pdata[1], pdata[2], pdata[3],
7271 pdata[4], pdata[5], pdata[6], pdata[7]);
7272 nLeft -= 8;
7273 pdata += 8;
7274 }
7275
7276 }
7277}
7278
7279static void push_to_buf(struct vdec_h264_hw_s *hw,
7280 u8 *pdata,
7281 int len,
7282 struct userdata_meta_info_t *pmeta);
7283
7284static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7285 struct mh264_userdata_record_t *record)
7286{
7287 if (record && hw) {
7288 u8 *pdata;
7289
7290 pdata = hw->userdata_info.data_buf + record->rec_start;
7291/*
7292 print_data(pdata,
7293 record->rec_len,
7294 record->meta_info.flags,
7295 record->meta_info.duration,
7296 record->meta_info.vpts,
7297 record->meta_info.vpts_valid,
7298 n_record_id);
7299*/
7300 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7301 n_userdata_id++;
7302 }
7303}
7304
7305
7306static void push_to_buf(struct vdec_h264_hw_s *hw,
7307 u8 *pdata, int len,
7308 struct userdata_meta_info_t *pmeta)
7309{
7310 u32 *pLen;
7311 int info_cnt;
7312 u8 *pbuf_end;
7313
7314 if (!user_data_buf)
7315 return;
7316
7317 if (bskip) {
7318 pr_info("over size, skip\n");
7319 return;
7320 }
7321 info_cnt = 0;
7322 pLen = (u32 *)pbuf_start;
7323
7324 *pLen = len;
7325 pbuf_start += sizeof(u32);
7326 info_cnt++;
7327 pLen++;
7328
7329 *pLen = pmeta->poc_number;
7330 pbuf_start += sizeof(u32);
7331 info_cnt++;
7332 pLen++;
7333
7334 *pLen = pmeta->duration;
7335 pbuf_start += sizeof(u32);
7336 info_cnt++;
7337 pLen++;
7338
7339 *pLen = pmeta->flags;
7340 pbuf_start += sizeof(u32);
7341 info_cnt++;
7342 pLen++;
7343
7344 *pLen = pmeta->vpts;
7345 pbuf_start += sizeof(u32);
7346 info_cnt++;
7347 pLen++;
7348
7349 *pLen = pmeta->vpts_valid;
7350 pbuf_start += sizeof(u32);
7351 info_cnt++;
7352 pLen++;
7353
7354
7355 *pLen = n_userdata_id;
7356 pbuf_start += sizeof(u32);
7357 info_cnt++;
7358 pLen++;
7359
7360
7361
7362 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7363 if (pdata + len > pbuf_end) {
7364 int first_section_len;
7365
7366 first_section_len = pbuf_end - pdata;
7367 memcpy(pbuf_start, pdata, first_section_len);
7368 pdata = (u8 *)hw->sei_user_data_buffer;
7369 pbuf_start += first_section_len;
7370 memcpy(pbuf_start, pdata, len - first_section_len);
7371 pbuf_start += len - first_section_len;
7372 } else {
7373 memcpy(pbuf_start, pdata, len);
7374 pbuf_start += len;
7375 }
7376
7377 total_len += len + info_cnt * sizeof(u32);
7378 if (total_len >= MAX_USER_DATA_SIZE-4096)
7379 bskip = 1;
7380}
7381
7382static void show_user_data_buf(void)
7383{
7384 u8 *pbuf;
7385 int len;
7386 unsigned int flag;
7387 unsigned int duration;
7388 unsigned int vpts;
7389 unsigned int vpts_valid;
7390 unsigned int poc_number;
7391 int rec_id;
7392
7393 pr_info("show user data buf\n");
7394 pbuf = user_data_buf;
7395
7396 while (pbuf < pbuf_start) {
7397 u32 *pLen;
7398
7399 pLen = (u32 *)pbuf;
7400
7401 len = *pLen;
7402 pLen++;
7403 pbuf += sizeof(u32);
7404
7405 poc_number = *pLen;
7406 pLen++;
7407 pbuf += sizeof(u32);
7408
7409 duration = *pLen;
7410 pLen++;
7411 pbuf += sizeof(u32);
7412
7413 flag = *pLen;
7414 pLen++;
7415 pbuf += sizeof(u32);
7416
7417 vpts = *pLen;
7418 pLen++;
7419 pbuf += sizeof(u32);
7420
7421 vpts_valid = *pLen;
7422 pLen++;
7423 pbuf += sizeof(u32);
7424
7425 rec_id = *pLen;
7426 pLen++;
7427 pbuf += sizeof(u32);
7428
7429 print_data(pbuf, len, poc_number, flag,
7430 duration, vpts,
7431 vpts_valid, rec_id);
7432 pbuf += len;
7433 msleep(30);
7434 }
7435}
7436
7437static int vmh264_init_userdata_dump(void)
7438{
7439 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7440 if (user_data_buf)
7441 return 1;
7442 else
7443 return 0;
7444}
7445
7446static void vmh264_dump_userdata(void)
7447{
7448 if (user_data_buf) {
7449 show_user_data_buf();
7450 kfree(user_data_buf);
7451 user_data_buf = NULL;
7452 }
7453}
7454
7455static void vmh264_reset_user_data_buf(void)
7456{
7457 total_len = 0;
7458 pbuf_start = user_data_buf;
7459 bskip = 0;
7460 n_userdata_id = 0;
7461}
7462#endif
7463
7464
7465static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7466 int frame_type,
7467 u32 vpts,
7468 u32 vpts_valid)
7469{
7470 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7471
7472 unsigned char *pdata;
7473 u8 *pmax_sei_data_buffer;
7474 u8 *sei_data_buf;
7475 int i;
7476 int wp;
7477 int data_length;
7478 struct mh264_userdata_record_t *p_userdata_rec;
7479
7480
7481#ifdef MH264_USERDATA_ENABLE
7482 struct userdata_meta_info_t meta_info;
7483 memset(&meta_info, 0, sizeof(meta_info));
7484#endif
7485
7486 if (hw->sei_itu_data_len <= 0)
7487 return;
7488
7489 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7490 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7491 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7492 for (i = 0; i < hw->sei_itu_data_len; i++) {
7493 *pdata++ = sei_data_buf[i];
7494 if (pdata >= pmax_sei_data_buffer)
7495 pdata = (u8 *)hw->sei_user_data_buffer;
7496 }
7497
7498 hw->sei_user_data_wp = (hw->sei_user_data_wp
7499 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7500 hw->sei_itu_data_len = 0;
7501
7502#ifdef MH264_USERDATA_ENABLE
7503 meta_info.duration = hw->frame_dur;
7504 meta_info.flags |= (VFORMAT_H264 << 3);
7505
7506 meta_info.vpts = vpts;
7507 meta_info.vpts_valid = vpts_valid;
7508 meta_info.poc_number =
7509 p_H264_Dpb->mVideo.dec_picture->poc;
7510
7511
7512 wp = hw->sei_user_data_wp;
7513
7514 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7515 data_length = wp - hw->userdata_info.last_wp;
7516 else
7517 data_length = wp + hw->userdata_info.buf_len
7518 - hw->userdata_info.last_wp;
7519
7520 if (data_length & 0x7)
7521 data_length = (((data_length + 8) >> 3) << 3);
7522
7523 p_userdata_rec = &hw->ud_record;
7524 p_userdata_rec->meta_info = meta_info;
7525 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7526 p_userdata_rec->rec_len = data_length;
7527 hw->userdata_info.last_wp = wp;
7528
7529 p_userdata_rec->meta_info.flags |=
7530 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7531
7532 hw->wait_for_udr_send = 1;
7533 vdec_schedule_work(&hw->user_data_ready_work);
7534#endif
7535}
7536
7537
7538static void user_data_ready_notify_work(struct work_struct *work)
7539{
7540 struct vdec_h264_hw_s *hw = container_of(work,
7541 struct vdec_h264_hw_s, user_data_ready_work);
7542
7543
7544 mutex_lock(&hw->userdata_mutex);
7545
7546 hw->userdata_info.records[hw->userdata_info.write_index]
7547 = hw->ud_record;
7548 hw->userdata_info.write_index++;
7549 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7550 hw->userdata_info.write_index = 0;
7551
7552 mutex_unlock(&hw->userdata_mutex);
7553
7554#ifdef DUMP_USERDATA_RECORD
7555 dump_userdata_record(hw, &hw->ud_record);
7556#endif
7557 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7558
7559 hw->wait_for_udr_send = 0;
7560}
7561
7562static int vmh264_user_data_read(struct vdec_s *vdec,
7563 struct userdata_param_t *puserdata_para)
7564{
7565 struct vdec_h264_hw_s *hw = NULL;
7566 int rec_ri, rec_wi;
7567 int rec_len;
7568 u8 *rec_data_start;
7569 u8 *pdest_buf;
7570 struct mh264_userdata_record_t *p_userdata_rec;
7571 u32 data_size;
7572 u32 res;
7573 int copy_ok = 1;
7574
7575 hw = (struct vdec_h264_hw_s *)vdec->private;
7576
7577 pdest_buf = puserdata_para->pbuf_addr;
7578
7579 mutex_lock(&hw->userdata_mutex);
7580
7581/*
7582 pr_info("ri = %d, wi = %d\n",
7583 lg_p_mpeg12_userdata_info->read_index,
7584 lg_p_mpeg12_userdata_info->write_index);
7585*/
7586 rec_ri = hw->userdata_info.read_index;
7587 rec_wi = hw->userdata_info.write_index;
7588
7589 if (rec_ri == rec_wi) {
7590 mutex_unlock(&hw->userdata_mutex);
7591 return 0;
7592 }
7593
7594 p_userdata_rec = hw->userdata_info.records + rec_ri;
7595
7596 rec_len = p_userdata_rec->rec_len;
7597 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7598/*
7599 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7600 p_userdata_rec->rec_len,
7601 p_userdata_rec->rec_start,
7602 puserdata_para->buf_len);
7603*/
7604 if (rec_len <= puserdata_para->buf_len) {
7605 /* dvb user data buffer is enought to
7606 copy the whole recored. */
7607 data_size = rec_len;
7608 if (rec_data_start + data_size
7609 > hw->userdata_info.data_buf_end) {
7610 int first_section_len;
7611
7612 first_section_len = hw->userdata_info.buf_len -
7613 p_userdata_rec->rec_start;
7614 res = (u32)copy_to_user((void *)pdest_buf,
7615 (void *)rec_data_start,
7616 first_section_len);
7617 if (res) {
7618 pr_info("p1 read not end res=%d, request=%d\n",
7619 res, first_section_len);
7620 copy_ok = 0;
7621
7622 p_userdata_rec->rec_len -=
7623 first_section_len - res;
7624 p_userdata_rec->rec_start +=
7625 first_section_len - res;
7626 puserdata_para->data_size =
7627 first_section_len - res;
7628 } else {
7629 res = (u32)copy_to_user(
7630 (void *)(pdest_buf+first_section_len),
7631 (void *)hw->userdata_info.data_buf,
7632 data_size - first_section_len);
7633 if (res) {
7634 pr_info("p2 read not end res=%d, request=%d\n",
7635 res, data_size);
7636 copy_ok = 0;
7637 }
7638 p_userdata_rec->rec_len -=
7639 data_size - res;
7640 p_userdata_rec->rec_start =
7641 data_size - first_section_len - res;
7642 puserdata_para->data_size =
7643 data_size - res;
7644 }
7645 } else {
7646 res = (u32)copy_to_user((void *)pdest_buf,
7647 (void *)rec_data_start,
7648 data_size);
7649 if (res) {
7650 pr_info("p3 read not end res=%d, request=%d\n",
7651 res, data_size);
7652 copy_ok = 0;
7653 }
7654 p_userdata_rec->rec_len -= data_size - res;
7655 p_userdata_rec->rec_start += data_size - res;
7656 puserdata_para->data_size = data_size - res;
7657 }
7658
7659 if (copy_ok) {
7660 hw->userdata_info.read_index++;
7661 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7662 hw->userdata_info.read_index = 0;
7663 }
7664 } else {
7665 /* dvb user data buffer is not enought
7666 to copy the whole recored. */
7667 data_size = puserdata_para->buf_len;
7668 if (rec_data_start + data_size
7669 > hw->userdata_info.data_buf_end) {
7670 int first_section_len;
7671
7672 first_section_len = hw->userdata_info.buf_len -
7673 p_userdata_rec->rec_start;
7674 res = (u32)copy_to_user((void *)pdest_buf,
7675 (void *)rec_data_start,
7676 first_section_len);
7677 if (res) {
7678 pr_info("p4 read not end res=%d, request=%d\n",
7679 res, first_section_len);
7680 copy_ok = 0;
7681 p_userdata_rec->rec_len -=
7682 first_section_len - res;
7683 p_userdata_rec->rec_start +=
7684 first_section_len - res;
7685 puserdata_para->data_size =
7686 first_section_len - res;
7687 } else {
7688 /* first secton copy is ok*/
7689 res = (u32)copy_to_user(
7690 (void *)(pdest_buf+first_section_len),
7691 (void *)hw->userdata_info.data_buf,
7692 data_size - first_section_len);
7693 if (res) {
7694 pr_info("p5 read not end res=%d, request=%d\n",
7695 res,
7696 data_size - first_section_len);
7697 copy_ok = 0;
7698 }
7699
7700 p_userdata_rec->rec_len -=
7701 data_size - res;
7702 p_userdata_rec->rec_start =
7703 data_size - first_section_len - res;
7704 puserdata_para->data_size =
7705 data_size - res;
7706 }
7707 } else {
7708 res = (u32)copy_to_user((void *)pdest_buf,
7709 (void *)rec_data_start,
7710 data_size);
7711 if (res) {
7712 pr_info("p6 read not end res=%d, request=%d\n",
7713 res, data_size);
7714 copy_ok = 0;
7715 }
7716
7717 p_userdata_rec->rec_len -= data_size - res;
7718 p_userdata_rec->rec_start += data_size - res;
7719 puserdata_para->data_size = data_size - res;
7720 }
7721
7722 if (copy_ok) {
7723 hw->userdata_info.read_index++;
7724 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7725 hw->userdata_info.read_index = 0;
7726 }
7727
7728 }
7729 puserdata_para->meta_info = p_userdata_rec->meta_info;
7730
7731 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7732 puserdata_para->meta_info.records_in_que =
7733 hw->userdata_info.write_index -
7734 hw->userdata_info.read_index;
7735 else
7736 puserdata_para->meta_info.records_in_que =
7737 hw->userdata_info.write_index +
7738 USERDATA_FIFO_NUM -
7739 hw->userdata_info.read_index;
7740
7741 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7742
7743 mutex_unlock(&hw->userdata_mutex);
7744
7745 return 1;
7746}
7747
7748static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7749{
7750 struct vdec_h264_hw_s *hw = NULL;
7751
7752 hw = (struct vdec_h264_hw_s *)vdec->private;
7753
7754 if (hw) {
7755 mutex_lock(&hw->userdata_mutex);
7756 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7757 bInit,
7758 hw->userdata_info.read_index,
7759 hw->userdata_info.write_index);
7760 hw->userdata_info.read_index = 0;
7761 hw->userdata_info.write_index = 0;
7762
7763 if (bInit)
7764 hw->userdata_info.last_wp = 0;
7765 mutex_unlock(&hw->userdata_mutex);
7766 }
7767}
7768
7769static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7770{
7771 amstream_wakeup_userdata_poll(vdec);
7772}
7773
7774#endif
7775
7776
7777static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7778 struct vdec_s *vdec, int from)
7779{
7780 /* finished decoding one frame or error,
7781 * notify vdec core to switch context
7782 */
7783 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7784 "%s dec_result %d %x %x %x\n",
7785 __func__,
7786 hw->dec_result,
7787 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7788 READ_VREG(VLD_MEM_VIFIFO_WP),
7789 READ_VREG(VLD_MEM_VIFIFO_RP));
7790 if (!hw->mmu_enable) {
7791 mutex_lock(&vmh264_mutex);
7792 dealloc_buf_specs(hw, 0);
7793 mutex_unlock(&vmh264_mutex);
7794 }
7795 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7796 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7797 u32 param1 = READ_VREG(AV_SCRATCH_1);
7798 u32 param2 = READ_VREG(AV_SCRATCH_2);
7799 u32 param3 = READ_VREG(AV_SCRATCH_6);
7800 u32 param4 = READ_VREG(AV_SCRATCH_B);
7801 if (vh264_set_params(hw, param1,
7802 param2, param3, param4) < 0)
7803 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7804 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7805 (hw->dpb.mDPB.size<<16) |
7806 (hw->dpb.mDPB.size<<8));
7807 start_process_time(hw);
7808 return;
7809 } else
7810 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7811 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7812 && (hw_to_vdec(hw)->next_status !=
7813 VDEC_STATUS_DISCONNECTED)) {
7814 if (!vdec_has_more_input(vdec)) {
7815 hw->dec_result = DEC_RESULT_EOS;
7816 vdec_schedule_work(&hw->work);
7817 return;
7818 }
7819
7820 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7821 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7822 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7823 __func__,
7824 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7825 READ_VREG(VLD_MEM_VIFIFO_WP),
7826 READ_VREG(VLD_MEM_VIFIFO_RP));
7827 mutex_lock(&hw->chunks_mutex);
7828 vdec_vframe_dirty(vdec, hw->chunk);
7829 hw->chunk = NULL;
7830 mutex_unlock(&hw->chunks_mutex);
7831 vdec_clean_input(vdec);
7832 }
7833 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7834 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7835 > get_data_timeout_val)) {
7836 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7837 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7838 __func__);
7839 goto result_done;
7840 }
7841 if (is_buffer_available(vdec)) {
7842 int r;
7843 int decode_size;
7844 r = vdec_prepare_input(vdec, &hw->chunk);
7845 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7846 VDEC_STATUS_DISCONNECTED)) {
7847 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7848
7849 dpb_print(DECODE_ID(hw),
7850 PRINT_FLAG_VDEC_DETAIL,
7851 "vdec_prepare_input: Insufficient data\n");
7852 vdec_schedule_work(&hw->work);
7853 return;
7854 }
7855 hw->dec_result = DEC_RESULT_NONE;
7856 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7857 "%s: chunk size 0x%x\n",
7858 __func__, hw->chunk->size);
7859
7860 if (dpb_is_debug(DECODE_ID(hw),
7861 PRINT_FRAMEBASE_DATA)) {
7862 int jj;
7863 u8 *data = NULL;
7864
7865 if (!hw->chunk->block->is_mapped)
7866 data = codec_mm_vmap(
7867 hw->chunk->block->start +
7868 hw->chunk->offset, r);
7869 else
7870 data = ((u8 *)
7871 hw->chunk->block->start_virt)
7872 + hw->chunk->offset;
7873
7874 for (jj = 0; jj < r; jj++) {
7875 if ((jj & 0xf) == 0)
7876 dpb_print(DECODE_ID(hw),
7877 PRINT_FRAMEBASE_DATA,
7878 "%06x:", jj);
7879 dpb_print_cont(DECODE_ID(hw),
7880 PRINT_FRAMEBASE_DATA,
7881 "%02x ", data[jj]);
7882 if (((jj + 1) & 0xf) == 0)
7883 dpb_print_cont(DECODE_ID(hw),
7884 PRINT_FRAMEBASE_DATA,
7885 "\n");
7886 }
7887
7888 if (!hw->chunk->block->is_mapped)
7889 codec_mm_unmap_phyaddr(data);
7890 }
7891 WRITE_VREG(POWER_CTL_VLD,
7892 READ_VREG(POWER_CTL_VLD) |
7893 (0 << 10) | (1 << 9) | (1 << 6));
7894 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7895 decode_size = hw->chunk->size +
7896 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7897 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7898 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7899 vdec_enable_input(vdec);
7900
7901 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7902 start_process_time(hw);
7903 } else{
7904 if (hw_to_vdec(hw)->next_status
7905 != VDEC_STATUS_DISCONNECTED) {
7906 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7907 vdec_schedule_work(&hw->work);
7908 }
7909 }
7910 return;
7911 } else if (hw->dec_result == DEC_RESULT_DONE) {
7912 /* if (!hw->ctx_valid)
7913 hw->ctx_valid = 1; */
7914result_done:
7915 if (hw->mmu_enable
7916 && hw->frame_busy && hw->frame_done) {
7917 long used_4k_num;
7918 hevc_sao_wait_done(hw);
7919 if (hw->hevc_cur_buf_idx != 0xffff) {
7920 used_4k_num =
7921 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7922 if (used_4k_num >= 0)
7923 dpb_print(DECODE_ID(hw),
7924 PRINT_FLAG_MMU_DETAIL,
7925 "release unused buf , used_4k_num %ld index %d\n",
7926 used_4k_num, hw->hevc_cur_buf_idx);
7927 hevc_mmu_dma_check(hw_to_vdec(hw));
7928 decoder_mmu_box_free_idx_tail(
7929 hw->mmu_box,
7930 hw->hevc_cur_buf_idx,
7931 used_4k_num);
7932 hw->hevc_cur_buf_idx = 0xffff;
7933 }
7934 }
7935 decode_frame_count[DECODE_ID(hw)]++;
7936 amvdec_stop();
7937 if (!vdec_is_support_4k()) {
7938 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7939 clk_adj_frame_count++;
7940 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7941 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7942 }
7943 }
7944 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7945 "%s dec_result %d %x %x %x\n",
7946 __func__,
7947 hw->dec_result,
7948 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7949 READ_VREG(VLD_MEM_VIFIFO_WP),
7950 READ_VREG(VLD_MEM_VIFIFO_RP));
7951 mutex_lock(&hw->chunks_mutex);
7952 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7953 hw->chunk = NULL;
7954 mutex_unlock(&hw->chunks_mutex);
7955 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7956 /*
7957 stream base: stream buf empty or timeout
7958 frame base: vdec_prepare_input fail
7959 */
7960 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
7961 VDEC_STATUS_DISCONNECTED)) {
7962 hw->dec_result = DEC_RESULT_EOS;
7963 vdec_schedule_work(&hw->work);
7964 return;
7965 }
7966 hw->next_again_flag = 1;
7967 } else if (hw->dec_result == DEC_RESULT_EOS) {
7968 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7969 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7970 "%s: end of stream\n",
7971 __func__);
7972 amvdec_stop();
7973 if (hw->mmu_enable)
7974 amhevc_stop();
7975 hw->eos = 1;
7976 flush_dpb(p_H264_Dpb);
7977 if (hw->is_used_v4l)
7978 notify_v4l_eos(hw_to_vdec(hw));
7979 mutex_lock(&hw->chunks_mutex);
7980 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7981 hw->chunk = NULL;
7982 mutex_unlock(&hw->chunks_mutex);
7983 vdec_clean_input(vdec);
7984 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
7985 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7986 "%s: force exit\n",
7987 __func__);
7988 amvdec_stop();
7989 if (hw->mmu_enable)
7990 amhevc_stop();
7991 if (hw->stat & STAT_ISR_REG) {
7992 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7993 hw->stat &= ~STAT_ISR_REG;
7994 }
7995 }
7996 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
7997 del_timer_sync(&hw->check_timer);
7998 hw->stat &= ~STAT_TIMER_ARM;
7999
8000 wait_vmh264_search_done(hw);
8001 /* mark itself has all HW resource released and input released */
8002
8003#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8004 if (hw->switch_dvlayer_flag) {
8005 if (vdec->slave)
8006 vdec_set_next_sched(vdec, vdec->slave);
8007 else if (vdec->master)
8008 vdec_set_next_sched(vdec, vdec->master);
8009 } else if (vdec->slave || vdec->master)
8010 vdec_set_next_sched(vdec, vdec);
8011#endif
8012
8013 if (from == 1) {
8014 /* This is a timeout work */
8015 if (work_pending(&hw->work)) {
8016 /*
8017 * The vh264_work arrives at the last second,
8018 * give it a chance to handle the scenario.
8019 */
8020 return;
8021 }
8022 }
8023
8024 /* mark itself has all HW resource released and input released */
8025 if (vdec->parallel_dec == 1) {
8026 if (hw->mmu_enable == 0)
8027 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8028 else
8029 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8030 } else
8031 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8032
8033 wake_up_interruptible(&hw->wait_q);
8034 if (hw->vdec_cb)
8035 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8036}
8037
8038
8039static void vh264_work(struct work_struct *work)
8040{
8041 struct vdec_h264_hw_s *hw = container_of(work,
8042 struct vdec_h264_hw_s, work);
8043 struct vdec_s *vdec = hw_to_vdec(hw);
8044
8045 vh264_work_implement(hw, vdec, 0);
8046}
8047
8048
8049static void vh264_timeout_work(struct work_struct *work)
8050{
8051 struct vdec_h264_hw_s *hw = container_of(work,
8052 struct vdec_h264_hw_s, timeout_work);
8053 struct vdec_s *vdec = hw_to_vdec(hw);
8054
8055 if (work_pending(&hw->work))
8056 return;
8057
8058 vh264_work_implement(hw, vdec, 1);
8059}
8060
8061static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8062{
8063 bool ret = 0;
8064 struct vdec_h264_hw_s *hw =
8065 (struct vdec_h264_hw_s *)vdec->private;
8066 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8067 CODEC_MM_FLAGS_TVP : 0;
8068
8069 if (!hw->first_sc_checked && hw->mmu_enable) {
8070 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8071 hw->first_sc_checked =1;
8072 dpb_print(DECODE_ID(hw), 0,
8073 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8074 size, (hw->need_cache_size >> PAGE_SHIFT),
8075 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8076 }
8077
8078 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8079 && pre_decode_buf_level != 0) {
8080 u32 rp, wp, level;
8081
8082 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8083 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8084 if (wp < rp)
8085 level = vdec->input.size + wp - rp;
8086 else
8087 level = wp - rp;
8088
8089 if (level < pre_decode_buf_level)
8090 return 0;
8091 }
8092
8093#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8094 if (vdec->master)
8095 return 0;
8096#endif
8097 if (hw->eos)
8098 return 0;
8099
8100 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8101 return 0;
8102
8103 if (disp_vframe_valve_level &&
8104 kfifo_len(&hw->display_q) >=
8105 disp_vframe_valve_level) {
8106 hw->valve_count--;
8107 if (hw->valve_count <= 0)
8108 hw->valve_count = 2;
8109 else
8110 return 0;
8111 }
8112 if (hw->next_again_flag &&
8113 (!vdec_frame_based(vdec))) {
8114 u32 parser_wr_ptr =
8115 READ_PARSER_REG(PARSER_VIDEO_WP);
8116 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8117 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8118 again_threshold) {
8119 int r = vdec_sync_input(vdec);
8120 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8121 "%s buf lelvel:%x\n", __func__, r);
8122 return 0;
8123 }
8124 }
8125
8126 if (h264_debug_flag & 0x20000000) {
8127 /* pr_info("%s, a\n", __func__); */
8128 ret = 1;
8129 } else
8130 ret = is_buffer_available(vdec);
8131
8132#ifdef CONSTRAIN_MAX_BUF_NUM
8133 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8134 if (run_ready_max_vf_only_num > 0 &&
8135 get_vf_ref_only_buf_count(hw) >=
8136 run_ready_max_vf_only_num
8137 )
8138 ret = 0;
8139 if (run_ready_display_q_num > 0 &&
8140 kfifo_len(&hw->display_q) >=
8141 run_ready_display_q_num)
8142 ret = 0;
8143 /*avoid more buffers consumed when
8144 switching resolution*/
8145 if (run_ready_max_buf_num == 0xff &&
8146 get_used_buf_count(hw) >
8147 hw->dpb.mDPB.size)
8148 ret = 0;
8149 else if (run_ready_max_buf_num &&
8150 get_used_buf_count(hw) >=
8151 run_ready_max_buf_num)
8152 ret = 0;
8153 }
8154#endif
8155 if (ret)
8156 not_run_ready[DECODE_ID(hw)] = 0;
8157 else
8158 not_run_ready[DECODE_ID(hw)]++;
8159 if (vdec->parallel_dec == 1) {
8160 if (hw->mmu_enable == 0)
8161 return ret ? (CORE_MASK_VDEC_1) : 0;
8162 else
8163 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8164 } else
8165 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8166}
8167
8168static unsigned char get_data_check_sum
8169 (struct vdec_h264_hw_s *hw, int size)
8170{
8171 int jj;
8172 int sum = 0;
8173 u8 *data = NULL;
8174
8175 if (!hw->chunk->block->is_mapped)
8176 data = codec_mm_vmap(hw->chunk->block->start +
8177 hw->chunk->offset, size);
8178 else
8179 data = ((u8 *)hw->chunk->block->start_virt)
8180 + hw->chunk->offset;
8181
8182 for (jj = 0; jj < size; jj++)
8183 sum += data[jj];
8184
8185 if (!hw->chunk->block->is_mapped)
8186 codec_mm_unmap_phyaddr(data);
8187 return sum;
8188}
8189
8190static void run(struct vdec_s *vdec, unsigned long mask,
8191 void (*callback)(struct vdec_s *, void *), void *arg)
8192{
8193 struct vdec_h264_hw_s *hw =
8194 (struct vdec_h264_hw_s *)vdec->private;
8195 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8196 int size, ret = -1;
8197
8198 run_count[DECODE_ID(hw)]++;
8199 vdec_reset_core(vdec);
8200 if (hw->mmu_enable)
8201 hevc_reset_core(vdec);
8202 hw->vdec_cb_arg = arg;
8203 hw->vdec_cb = callback;
8204
8205 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8206 hw->reset_bufmgr_flag = 1;
8207 dpb_print(DECODE_ID(hw), 0,
8208 "kfifo len:%d invaild, need bufmgr reset\n",
8209 kfifo_len(&hw->display_q));
8210 }
8211
8212 hw->pre_parser_wr_ptr =
8213 READ_PARSER_REG(PARSER_VIDEO_WP);
8214 hw->next_again_flag = 0;
8215
8216 if (hw->reset_bufmgr_flag ||
8217 ((error_proc_policy & 0x40) &&
8218 p_H264_Dpb->buf_alloc_fail)) {
8219 h264_reset_bufmgr(vdec);
8220 hw->reset_bufmgr_flag = 0;
8221 }
8222
8223 if (h264_debug_cmd & 0xf000) {
8224 if (((h264_debug_cmd >> 12) & 0xf)
8225 == (DECODE_ID(hw) + 1)) {
8226 h264_reconfig(hw);
8227 h264_debug_cmd &= (~0xf000);
8228 }
8229 }
8230 /* hw->chunk = vdec_prepare_input(vdec); */
8231#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8232 if (vdec->slave || vdec->master)
8233 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8234#endif
8235 size = vdec_prepare_input(vdec, &hw->chunk);
8236 if ((size < 0) ||
8237 (input_frame_based(vdec) && hw->chunk == NULL)) {
8238 input_empty[DECODE_ID(hw)]++;
8239 hw->dec_result = DEC_RESULT_AGAIN;
8240
8241 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8242 "vdec_prepare_input: Insufficient data\n");
8243
8244 vdec_schedule_work(&hw->work);
8245 return;
8246 }
8247 input_empty[DECODE_ID(hw)] = 0;
8248
8249 hw->dec_result = DEC_RESULT_NONE;
8250 hw->get_data_count = 0;
8251#if 0
8252 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8253 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8254 READ_VREG(VLD_MEM_VIFIFO_RP),
8255 READ_VREG(VLD_MEM_VIFIFO_WP));
8256#endif
8257
8258 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8259 u8 *data = NULL;
8260
8261 if (!hw->chunk->block->is_mapped)
8262 data = codec_mm_vmap(hw->chunk->block->start +
8263 hw->chunk->offset, size);
8264 else
8265 data = ((u8 *)hw->chunk->block->start_virt)
8266 + hw->chunk->offset;
8267
8268 if (dpb_is_debug(DECODE_ID(hw),
8269 PRINT_FLAG_VDEC_STATUS)
8270 ) {
8271 dpb_print(DECODE_ID(hw), 0,
8272 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8273 __func__, size, get_data_check_sum(hw, size),
8274 data[0], data[1], data[2], data[3],
8275 data[4], data[5], data[size - 4],
8276 data[size - 3], data[size - 2],
8277 data[size - 1]);
8278 }
8279 if (dpb_is_debug(DECODE_ID(hw),
8280 PRINT_FRAMEBASE_DATA)
8281 ) {
8282 int jj;
8283
8284 for (jj = 0; jj < size; jj++) {
8285 if ((jj & 0xf) == 0)
8286 dpb_print(DECODE_ID(hw),
8287 PRINT_FRAMEBASE_DATA,
8288 "%06x:", jj);
8289 dpb_print_cont(DECODE_ID(hw),
8290 PRINT_FRAMEBASE_DATA,
8291 "%02x ", data[jj]);
8292 if (((jj + 1) & 0xf) == 0)
8293 dpb_print_cont(DECODE_ID(hw),
8294 PRINT_FRAMEBASE_DATA,
8295 "\n");
8296 }
8297 }
8298
8299 if (!hw->chunk->block->is_mapped)
8300 codec_mm_unmap_phyaddr(data);
8301 } else
8302 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8303 "%s: %x %x %x %x %x size 0x%x\n",
8304 __func__,
8305 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8306 READ_VREG(VLD_MEM_VIFIFO_WP),
8307 READ_VREG(VLD_MEM_VIFIFO_RP),
8308 READ_PARSER_REG(PARSER_VIDEO_RP),
8309 READ_PARSER_REG(PARSER_VIDEO_WP),
8310 size);
8311
8312 start_process_time(hw);
8313 if (vdec->mc_loaded) {
8314 /*firmware have load before,
8315 and not changes to another.
8316 ignore reload.
8317 */
8318 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8319 } else {
8320
8321 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8322 if (ret < 0) {
8323 amvdec_enable_flag = false;
8324 amvdec_disable();
8325
8326 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8327 "MH264 the %s fw loading failed, err: %x\n",
8328 tee_enabled() ? "TEE" : "local", ret);
8329 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8330 vdec_schedule_work(&hw->work);
8331 return;
8332 }
8333 vdec->mc_type = VFORMAT_H264;
8334 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8335 if (hw->mmu_enable) {
8336 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8337 hw->fw_mmu->data);
8338 if (ret < 0) {
8339 amvdec_enable_flag = false;
8340 amhevc_disable();
8341
8342 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8343 "MH264_MMU the %s fw loading failed, err: %x\n",
8344 tee_enabled() ? "TEE" : "local", ret);
8345 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8346 vdec_schedule_work(&hw->work);
8347 return;
8348 }
8349 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8350 }
8351 vdec->mc_loaded = 1;
8352 }
8353 vmh264_reset_udr_mgr(hw);
8354
8355 if (vh264_hw_ctx_restore(hw) < 0) {
8356 vdec_schedule_work(&hw->work);
8357 return;
8358 }
8359 if (input_frame_based(vdec)) {
8360 int decode_size = 0;
8361
8362 decode_size = hw->chunk->size +
8363 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8364 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8365 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8366 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8367 } else {
8368 if (size <= 0)
8369 size = 0x7fffffff; /*error happen*/
8370 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8371 WRITE_VREG(H264_DECODE_SIZE, size);
8372 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8373 }
8374 config_aux_buf(hw);
8375 config_decode_mode(hw);
8376 vdec_enable_input(vdec);
8377 WRITE_VREG(NAL_SEARCH_CTL, 0);
8378 hw->sei_data_len = 0;
8379 if (enable_itu_t35)
8380 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8381 if (!hw->init_flag) {
8382 if (hw->mmu_enable)
8383 WRITE_VREG(NAL_SEARCH_CTL,
8384 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8385 else
8386 WRITE_VREG(NAL_SEARCH_CTL,
8387 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8388 }
8389 if (udebug_flag)
8390 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8391 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8392
8393 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8394
8395 if (hw->mmu_enable)
8396 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8397 else
8398 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8399 }
8400 amvdec_start();
8401 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8402 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8403 amhevc_start();
8404 if (hw->config_bufmgr_done) {
8405 hevc_mcr_sao_global_hw_init(hw,
8406 (hw->mb_width << 4), (hw->mb_height << 4));
8407 hevc_mcr_config_canv2axitbl(hw, 1);
8408 }
8409 }
8410
8411 /* if (hw->init_flag) { */
8412 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8413 /* } */
8414
8415 hw->init_flag = 1;
8416}
8417
8418static void reset(struct vdec_s *vdec)
8419{
8420 struct vdec_h264_hw_s *hw =
8421 (struct vdec_h264_hw_s *)vdec->private;
8422
8423 pr_info("vmh264 reset\n");
8424
8425 cancel_work_sync(&hw->work);
8426 cancel_work_sync(&hw->notify_work);
8427 if (hw->stat & STAT_VDEC_RUN) {
8428 amhevc_stop();
8429 hw->stat &= ~STAT_VDEC_RUN;
8430 }
8431
8432 if (hw->stat & STAT_TIMER_ARM) {
8433 del_timer_sync(&hw->check_timer);
8434 hw->stat &= ~STAT_TIMER_ARM;
8435 }
8436 hw->eos = 0;
8437 hw->decode_pic_count = 0;
8438 hw->dec_result = DEC_RESULT_NONE;
8439 reset_process_time(hw);
8440 h264_reset_bufmgr(vdec);
8441 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8442}
8443
8444static void h264_reconfig(struct vdec_h264_hw_s *hw)
8445{
8446 int i;
8447 unsigned long flags;
8448 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8449 dpb_print(DECODE_ID(hw), 0,
8450 "%s\n", __func__);
8451 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8452 all buffers are in display queue (used == 2),
8453 or free (used == 0)
8454 */
8455 if (dpb_is_debug(DECODE_ID(hw),
8456 PRINT_FLAG_DUMP_BUFSPEC))
8457 dump_bufspec(hw, "pre h264_reconfig");
8458
8459 flush_dpb(p_H264_Dpb);
8460 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8461
8462 if (hw->collocate_cma_alloc_addr) {
8463 decoder_bmmu_box_free_idx(
8464 hw->bmmu_box,
8465 BMMU_REF_IDX);
8466 hw->collocate_cma_alloc_addr = 0;
8467 hw->dpb.colocated_mv_addr_start = 0;
8468 hw->dpb.colocated_mv_addr_end = 0;
8469 }
8470 spin_lock_irqsave(&hw->bufspec_lock, flags);
8471 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8472 /*make sure buffers not put back to bufmgr when
8473 vf_put is called*/
8474 if (hw->buffer_spec[i].used == 2)
8475 hw->buffer_spec[i].used = 3;
8476
8477 /* ready to release "free buffers"
8478 */
8479 if (hw->buffer_spec[i].used == 0)
8480 hw->buffer_spec[i].used = 4;
8481
8482 hw->buffer_spec[i].canvas_pos = -1;
8483 }
8484 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8485 hw->has_i_frame = 0;
8486 hw->config_bufmgr_done = 0;
8487
8488 if (dpb_is_debug(DECODE_ID(hw),
8489 PRINT_FLAG_DUMP_BUFSPEC))
8490 dump_bufspec(hw, "after h264_reconfig");
8491
8492}
8493
8494#ifdef ERROR_HANDLE_TEST
8495static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8496{
8497 int i;
8498 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8499 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8500 "%s\n", __func__);
8501 remove_dpb_pictures(p_H264_Dpb);
8502 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8503 /*make sure buffers not put back to bufmgr when
8504 vf_put is called*/
8505 if (hw->buffer_spec[i].used == 2)
8506 hw->buffer_spec[i].used = 5;
8507 }
8508
8509}
8510#endif
8511
8512static void h264_reset_bufmgr(struct vdec_s *vdec)
8513{
8514 int i;
8515 ulong timeout;
8516 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8517#if 0
8518 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8519 int actual_dpb_size, max_reference_size;
8520 int reorder_pic_num;
8521 unsigned int colocated_buf_size;
8522 unsigned int colocated_mv_addr_start;
8523 unsigned int colocated_mv_addr_end;
8524 dpb_print(DECODE_ID(hw), 0,
8525 "%s\n", __func__);
8526
8527 for (i = 0; i < VF_POOL_SIZE; i++)
8528 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8529
8530 actual_dpb_size = p_H264_Dpb->mDPB.size;
8531 max_reference_size = p_H264_Dpb->max_reference_size;
8532 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8533
8534 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8535 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8536 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8537
8538 hw->cur_pool++;
8539 if (hw->cur_pool >= VF_POOL_NUM)
8540 hw->cur_pool = 0;
8541
8542 INIT_KFIFO(hw->display_q);
8543 INIT_KFIFO(hw->newframe_q);
8544
8545 for (i = 0; i < VF_POOL_SIZE; i++) {
8546 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8547 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8548 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8549 kfifo_put(&hw->newframe_q, vf);
8550 }
8551
8552 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8553 hw->buffer_spec[i].used = 0;
8554
8555 dpb_init_global(&hw->dpb,
8556 DECODE_ID(hw), 0, 0);
8557 p_H264_Dpb->mDPB.size = actual_dpb_size;
8558 p_H264_Dpb->max_reference_size = max_reference_size;
8559 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8560
8561 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8562 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8563 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8564
8565 p_H264_Dpb->fast_output_enable = fast_output_enable;
8566 hw->has_i_frame = 0;
8567#else
8568 dpb_print(DECODE_ID(hw), 0,
8569 "%s frame count %d to skip %d\n\n",
8570 __func__, hw->decode_pic_count+1,
8571 hw->skip_frame_count);
8572
8573 timeout = jiffies + HZ;
8574 while (kfifo_len(&hw->display_q) > 0) {
8575 if (time_after(jiffies, timeout))
8576 break;
8577 schedule();
8578 }
8579
8580 for (i = 0; i < VF_POOL_SIZE; i++)
8581 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8582
8583 hw->cur_pool++;
8584 if (hw->cur_pool >= VF_POOL_NUM)
8585 hw->cur_pool = 0;
8586
8587 for (i = 0; i < VF_POOL_SIZE; i++)
8588 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8589
8590
8591 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8592
8593 buf_spec_init(hw);
8594
8595 vh264_local_init(hw);
8596 /*hw->decode_pic_count = 0;
8597 hw->seq_info2 = 0;*/
8598 if (!hw->is_used_v4l) {
8599 if (vh264_set_params(hw,
8600 hw->cfg_param1,
8601 hw->cfg_param2,
8602 hw->cfg_param3,
8603 hw->cfg_param4) < 0)
8604 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8605 } else {
8606 /* V4L2 decoder reset keeps decoder in same status as
8607 * after probe when there is no SPS/PPS header processed
8608 * and no buffers allocated.
8609 */
8610 hw->seq_info = 0;
8611 hw->seq_info2 = 0;
8612 }
8613 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8614 if (first_i_policy & 0x01)
8615 hw->first_i_policy = (3 << 8) | first_i_policy;
8616 hw->init_flag = 1;
8617 hw->reset_bufmgr_count++;
8618#endif
8619
8620}
8621
8622int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8623{
8624 int ret = -1;
8625 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8626 CODEC_MM_FLAGS_TVP : 0;
8627 int buf_size = 64;
8628
8629 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8630 tvp_flag, hw->mmu_enable);
8631 hw->need_cache_size = buf_size * SZ_1M;
8632 hw->sc_start_time = get_jiffies_64();
8633 if (hw->mmu_enable && !hw->mmu_box) {
8634 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8635 hw->id,
8636 MMU_MAX_BUFFERS,
8637 hw->need_cache_size,
8638 tvp_flag);
8639 if (!hw->mmu_box) {
8640 pr_err("h264 4k alloc mmu box failed!!\n");
8641 return -1;
8642 }
8643 ret = 0;
8644 }
8645 if (!hw->bmmu_box) {
8646 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8647 DRIVER_NAME,
8648 hw->id,
8649 BMMU_MAX_BUFFERS,
8650 4 + PAGE_SHIFT,
8651 CODEC_MM_FLAGS_CMA_CLEAR |
8652 CODEC_MM_FLAGS_FOR_VDECODER |
8653 tvp_flag);
8654 if (hw->bmmu_box)
8655 ret = 0;
8656 }
8657 return ret;
8658}
8659int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8660{
8661 if (hw->mmu_box) {
8662 decoder_mmu_box_free(hw->mmu_box);
8663 hw->mmu_box = NULL;
8664 }
8665 if (hw->bmmu_box) {
8666 decoder_bmmu_box_free(hw->bmmu_box);
8667 hw->bmmu_box = NULL;
8668 }
8669 return 0;
8670}
8671
8672static int ammvdec_h264_probe(struct platform_device *pdev)
8673{
8674 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8675 struct vdec_h264_hw_s *hw = NULL;
8676 char *tmpbuf;
8677 int config_val;
8678
8679 if (pdata == NULL) {
8680 pr_info("\nammvdec_h264 memory resource undefined.\n");
8681 return -EFAULT;
8682 }
8683
8684 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8685 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8686 if (hw == NULL) {
8687 pr_info("\nammvdec_h264 device data allocation failed\n");
8688 return -ENOMEM;
8689 }
8690 hw->id = pdev->id;
8691 hw->platform_dev = pdev;
8692
8693 /* the ctx from v4l2 driver. */
8694 hw->v4l2_ctx = pdata->private;
8695
8696 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8697 hw->canvas_mode = pdata->canvas_mode;
8698 else
8699 hw->canvas_mode = mem_map_mode;
8700
8701 platform_set_drvdata(pdev, pdata);
8702
8703 hw->mmu_enable = 0;
8704 hw->first_head_check_flag = 0;
8705 hw->new_iframe_flag = 0;
8706 hw->ref_err_flush_dpb_flag = 0;
8707 if (force_enable_mmu && pdata->sys_info &&
8708 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8709 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8710 (pdata->sys_info->height * pdata->sys_info->width
8711 > 1920 * 1088))
8712 hw->mmu_enable = 1;
8713
8714 if (hw->mmu_enable &&
8715 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8716 hw->mmu_enable = 0;
8717 pr_info("ionvideo needs disable mmu, path= %d \n",
8718 pdata->frame_base_video_path);
8719 }
8720
8721 if (ammvdec_h264_mmu_init(hw)) {
8722 h264_free_hw_stru(&pdev->dev, (void *)hw);
8723 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8724 return -ENOMEM;
8725 }
8726
8727 if (pdata->config_len) {
8728 /*use ptr config for doubel_write_mode, etc*/
8729 if (get_config_int(pdata->config,
8730 "mh264_double_write_mode", &config_val) == 0)
8731 hw->double_write_mode = config_val;
8732 else
8733 hw->double_write_mode = double_write_mode;
8734 } else
8735 hw->double_write_mode = double_write_mode;
8736
8737 if (hw->mmu_enable)
8738 hw->double_write_mode &= 0xffff;
8739
8740 if (pdata->parallel_dec == 1) {
8741 int i;
8742 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8743 hw->buffer_spec[i].y_canvas_index = -1;
8744 hw->buffer_spec[i].u_canvas_index = -1;
8745 hw->buffer_spec[i].v_canvas_index = -1;
8746#ifdef VDEC_DW
8747 if (IS_VDEC_DW(hw)) {
8748 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8749 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8750 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8751 }
8752#endif
8753 }
8754 }
8755
8756 dpb_print(DECODE_ID(hw), 0,
8757 "%s mmu_enable %d double_write_mode 0x%x\n",
8758 __func__, hw->mmu_enable, hw->double_write_mode);
8759
8760 pdata->private = hw;
8761 pdata->dec_status = dec_status;
8762 pdata->set_trickmode = vmh264_set_trickmode;
8763 pdata->run_ready = run_ready;
8764 pdata->run = run;
8765 pdata->reset = reset;
8766 pdata->irq_handler = vh264_isr;
8767 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8768 pdata->dump_state = vmh264_dump_state;
8769
8770#ifdef MH264_USERDATA_ENABLE
8771 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8772 pdata->user_data_read = vmh264_user_data_read;
8773 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8774#else
8775 pdata->wakeup_userdata_poll = NULL;
8776 pdata->user_data_read = NULL;
8777 pdata->reset_userdata_fifo = NULL;
8778#endif
8779 if (pdata->use_vfm_path) {
8780 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8781 VFM_DEC_PROVIDER_NAME);
8782 hw->frameinfo_enable = 1;
8783 }
8784#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8785 else if (vdec_dual(pdata)) {
8786 if (dv_toggle_prov_name) /*debug purpose*/
8787 snprintf(pdata->vf_provider_name,
8788 VDEC_PROVIDER_NAME_SIZE,
8789 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8790 VFM_DEC_DVEL_PROVIDER_NAME);
8791 else
8792 snprintf(pdata->vf_provider_name,
8793 VDEC_PROVIDER_NAME_SIZE,
8794 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8795 VFM_DEC_DVBL_PROVIDER_NAME);
8796 }
8797#endif
8798 else
8799 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8800 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8801
8802 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8803 &vf_provider_ops, pdata);
8804
8805 platform_set_drvdata(pdev, pdata);
8806
8807 buf_spec_init(hw);
8808
8809 hw->platform_dev = pdev;
8810
8811#ifdef DUMP_USERDATA_RECORD
8812 vmh264_init_userdata_dump();
8813 vmh264_reset_user_data_buf();
8814#endif
8815 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8816 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8817 h264_free_hw_stru(&pdev->dev, (void *)hw);
8818 pdata->dec_status = NULL;
8819 return -ENOMEM;
8820 }
8821
8822 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8823 DCAC_READ_MARGIN;
8824 if (hw->mmu_enable) {
8825 u32 extif_size = EXTIF_BUF_SIZE;
8826 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8827 extif_size <<= 1;
8828 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8829 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8830 h264_free_hw_stru(&pdev->dev, (void *)hw);
8831 pdata->dec_status = NULL;
8832 return -ENOMEM;
8833 }
8834 }
8835 if (!vdec_secure(pdata)) {
8836#if 1
8837 /*init internal buf*/
8838 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8839 if (tmpbuf) {
8840 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8841 codec_mm_dma_flush(tmpbuf,
8842 V_BUF_ADDR_OFFSET,
8843 DMA_TO_DEVICE);
8844 } else {
8845 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8846 V_BUF_ADDR_OFFSET);
8847 if (tmpbuf) {
8848 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8849 codec_mm_dma_flush(tmpbuf,
8850 V_BUF_ADDR_OFFSET,
8851 DMA_TO_DEVICE);
8852 codec_mm_unmap_phyaddr(tmpbuf);
8853 }
8854 }
8855#else
8856 /*init sps/pps internal buf 64k*/
8857 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8858 + (mem_sps_base - DEF_BUF_START_ADDR));
8859 memset(tmpbuf, 0, 0x10000);
8860 dma_sync_single_for_device(amports_get_dma_device(),
8861 hw->cma_alloc_addr +
8862 (mem_sps_base - DEF_BUF_START_ADDR),
8863 0x10000, DMA_TO_DEVICE);
8864#endif
8865 }
8866 /**/
8867
8868 if (pdata->sys_info)
8869 hw->vh264_amstream_dec_info = *pdata->sys_info;
8870#if 0
8871 if (NULL == hw->sei_data_buffer) {
8872 hw->sei_data_buffer =
8873 dma_alloc_coherent(amports_get_dma_device(),
8874 USER_DATA_SIZE,
8875 &hw->sei_data_buffer_phys, GFP_KERNEL);
8876 if (!hw->sei_data_buffer) {
8877 pr_info("%s: Can not allocate sei_data_buffer\n",
8878 __func__);
8879 ammvdec_h264_mmu_release(hw);
8880 h264_free_hw_stru(&pdev->dev, (void *)hw);
8881 return -ENOMEM;
8882 }
8883 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
8884 sei_data_buffer, sei_data_buffer_phys,
8885 (u32)sei_data_buffer_remap); */
8886 }
8887#endif
8888 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
8889 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
8890
8891 if (vdec_is_support_4k() ||
8892 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
8893 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8894 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
8895 {
8896 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
8897 }else
8898 {
8899 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
8900 }
8901
8902 if (vh264_init(hw) < 0) {
8903 pr_info("\nammvdec_h264 init failed.\n");
8904 ammvdec_h264_mmu_release(hw);
8905 h264_free_hw_stru(&pdev->dev, (void *)hw);
8906 pdata->dec_status = NULL;
8907 return -ENODEV;
8908 }
8909#ifdef MH264_USERDATA_ENABLE
8910 vmh264_crate_userdata_manager(hw,
8911 hw->sei_user_data_buffer,
8912 USER_DATA_SIZE);
8913#endif
8914
8915 vdec_set_prepare_level(pdata, start_decode_buf_level);
8916 if (pdata->parallel_dec == 1) {
8917 if (hw->mmu_enable == 0)
8918 vdec_core_request(pdata, CORE_MASK_VDEC_1);
8919 else {
8920 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
8921 | CORE_MASK_COMBINE);
8922 }
8923 } else
8924 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
8925 | CORE_MASK_COMBINE);
8926
8927 atomic_set(&hw->vh264_active, 1);
8928
8929 return 0;
8930}
8931
8932static int ammvdec_h264_remove(struct platform_device *pdev)
8933{
8934 struct vdec_h264_hw_s *hw =
8935 (struct vdec_h264_hw_s *)
8936 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
8937 int i;
8938
8939 struct vdec_s *vdec = hw_to_vdec(hw);
8940
8941 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
8942 && (vdec->status == VDEC_STATUS_ACTIVE)) {
8943 dpb_print(DECODE_ID(hw), 0,
8944 "%s force exit %d\n", __func__, __LINE__);
8945 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8946 vdec_schedule_work(&hw->work);
8947 wait_event_interruptible_timeout(hw->wait_q,
8948 (vdec->status == VDEC_STATUS_CONNECTED),
8949 msecs_to_jiffies(1000)); /* wait for work done */
8950 }
8951
8952 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8953 release_aux_data(hw, i);
8954
8955 atomic_set(&hw->vh264_active, 0);
8956
8957 if (hw->stat & STAT_TIMER_ARM) {
8958 del_timer_sync(&hw->check_timer);
8959 hw->stat &= ~STAT_TIMER_ARM;
8960 }
8961
8962 vh264_stop(hw);
8963#ifdef MH264_USERDATA_ENABLE
8964#ifdef DUMP_USERDATA_RECORD
8965 vmh264_dump_userdata();
8966#endif
8967 vmh264_destroy_userdata_manager(hw);
8968#endif
8969 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
8970
8971 atomic_set(&hw->vh264_active, 0);
8972 if (vdec->parallel_dec == 1) {
8973 if (hw->mmu_enable == 0)
8974 vdec_core_release(vdec, CORE_MASK_VDEC_1);
8975 else
8976 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
8977 CORE_MASK_COMBINE);
8978 } else
8979 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8980
8981 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
8982 if (vdec->parallel_dec == 1) {
8983 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8984 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8985 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8986 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8987 if (IS_VDEC_DW(hw)) {
8988 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8989 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8990 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8991 }
8992 }
8993 }
8994
8995 ammvdec_h264_mmu_release(hw);
8996 h264_free_hw_stru(&pdev->dev, (void *)hw);
8997 clk_adj_frame_count = 0;
8998
8999 return 0;
9000}
9001
9002/****************************************/
9003#ifdef CONFIG_PM
9004static int mh264_suspend(struct device *dev)
9005{
9006 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9007 return 0;
9008}
9009
9010static int mh264_resume(struct device *dev)
9011{
9012 amvdec_resume(to_platform_device(dev));
9013 return 0;
9014}
9015
9016static const struct dev_pm_ops mh264_pm_ops = {
9017 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9018};
9019#endif
9020
9021static struct platform_driver ammvdec_h264_driver = {
9022 .probe = ammvdec_h264_probe,
9023 .remove = ammvdec_h264_remove,
9024 .driver = {
9025 .name = DRIVER_NAME,
9026#ifdef CONFIG_PM
9027 .pm = &mh264_pm_ops,
9028#endif
9029 }
9030};
9031
9032static struct codec_profile_t ammvdec_h264_profile = {
9033 .name = "mh264",
9034 .profile = ""
9035};
9036
9037static struct mconfig hm264_configs[] = {
9038 MC_PU32("h264_debug_flag", &h264_debug_flag),
9039 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9040 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9041 MC_PU32("decode_timeout_val", &decode_timeout_val),
9042 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9043 MC_PU32("reference_buf_margin", &reference_buf_margin),
9044 MC_PU32("radr", &radr),
9045 MC_PU32("rval", &rval),
9046 MC_PU32("h264_debug_mask", &h264_debug_mask),
9047 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9048 MC_PI32("force_rate_streambase", &force_rate_streambase),
9049 MC_PI32("dec_control", &dec_control),
9050 MC_PI32("force_rate_framebase", &force_rate_framebase),
9051 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9052 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9053 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9054#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9055 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9056 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9057 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9058#endif
9059 MC_PU32("i_only_flag", &i_only_flag),
9060 MC_PU32("force_rate_streambase", &force_rate_streambase),
9061};
9062static struct mconfig_node hm264_node;
9063
9064
9065static int __init ammvdec_h264_driver_init_module(void)
9066{
9067 pr_info("ammvdec_h264 module init\n");
9068 if (platform_driver_register(&ammvdec_h264_driver)) {
9069 pr_info("failed to register ammvdec_h264 driver\n");
9070 return -ENODEV;
9071 }
9072
9073 if (vdec_is_support_4k()) {
9074 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9075 ammvdec_h264_profile.profile =
9076 "4k, dwrite, compressed";
9077 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9078 ammvdec_h264_profile.profile = "4k";
9079 }
9080 }
9081
9082 vcodec_profile_register(&ammvdec_h264_profile);
9083 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9084 "mh264", hm264_configs, CONFIG_FOR_RW);
9085 return 0;
9086}
9087
9088static void __exit ammvdec_h264_driver_remove_module(void)
9089{
9090 pr_info("ammvdec_h264 module remove.\n");
9091
9092 platform_driver_unregister(&ammvdec_h264_driver);
9093}
9094
9095/****************************************/
9096module_param(h264_debug_flag, uint, 0664);
9097MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9098
9099module_param(start_decode_buf_level, int, 0664);
9100MODULE_PARM_DESC(start_decode_buf_level,
9101 "\n ammvdec_h264 start_decode_buf_level\n");
9102
9103module_param(pre_decode_buf_level, int, 0664);
9104MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9105
9106module_param(fixed_frame_rate_mode, uint, 0664);
9107MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9108
9109module_param(decode_timeout_val, uint, 0664);
9110MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9111
9112module_param(errordata_timeout_val, uint, 0664);
9113MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9114
9115module_param(get_data_timeout_val, uint, 0664);
9116MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9117
9118module_param(frame_max_data_packet, uint, 0664);
9119MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9120
9121module_param(reorder_dpb_size_margin, uint, 0664);
9122MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9123
9124#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9125module_param(reorder_dpb_size_margin_dv, uint, 0664);
9126MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9127 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9128#endif
9129
9130module_param(reference_buf_margin, uint, 0664);
9131MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9132
9133#ifdef CONSTRAIN_MAX_BUF_NUM
9134module_param(run_ready_max_vf_only_num, uint, 0664);
9135MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9136
9137module_param(run_ready_display_q_num, uint, 0664);
9138MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9139
9140module_param(run_ready_max_buf_num, uint, 0664);
9141MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9142#endif
9143
9144module_param(radr, uint, 0664);
9145MODULE_PARM_DESC(radr, "\nradr\n");
9146
9147module_param(rval, uint, 0664);
9148MODULE_PARM_DESC(rval, "\nrval\n");
9149
9150module_param(h264_debug_mask, uint, 0664);
9151MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9152
9153module_param(h264_debug_cmd, uint, 0664);
9154MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9155
9156module_param(force_rate_streambase, int, 0664);
9157MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9158
9159module_param(dec_control, int, 0664);
9160MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9161
9162module_param(force_rate_framebase, int, 0664);
9163MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9164
9165module_param(force_disp_bufspec_num, int, 0664);
9166MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9167
9168module_param(V_BUF_ADDR_OFFSET, int, 0664);
9169MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9170
9171module_param(prefix_aux_buf_size, uint, 0664);
9172MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9173
9174module_param(suffix_aux_buf_size, uint, 0664);
9175MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9176
9177#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9178module_param(dv_toggle_prov_name, uint, 0664);
9179MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9180
9181module_param(dolby_meta_with_el, uint, 0664);
9182MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9183
9184#endif
9185
9186module_param(fast_output_enable, uint, 0664);
9187MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9188
9189module_param(error_proc_policy, uint, 0664);
9190MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9191
9192module_param(error_skip_count, uint, 0664);
9193MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9194
9195module_param(force_sliding_margin, uint, 0664);
9196MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9197
9198module_param(i_only_flag, uint, 0664);
9199MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9200
9201module_param(first_i_policy, uint, 0664);
9202MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9203
9204module_param(frmbase_cont_bitlevel, uint, 0664);
9205MODULE_PARM_DESC(frmbase_cont_bitlevel,
9206 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9207
9208module_param(frmbase_cont_bitlevel2, uint, 0664);
9209MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9210 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9211
9212module_param(udebug_flag, uint, 0664);
9213MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9214
9215module_param(udebug_pause_pos, uint, 0664);
9216MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9217
9218module_param(udebug_pause_val, uint, 0664);
9219MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9220
9221module_param(udebug_pause_decode_idx, uint, 0664);
9222MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9223
9224module_param(max_alloc_buf_count, uint, 0664);
9225MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9226
9227module_param(enable_itu_t35, uint, 0664);
9228MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9229
9230module_param(endian, uint, 0664);
9231MODULE_PARM_DESC(endian, "\nrval\n");
9232
9233module_param(mmu_enable, uint, 0664);
9234MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9235
9236module_param(force_enable_mmu, uint, 0664);
9237MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9238
9239module_param(again_threshold, uint, 0664);
9240MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9241
9242module_param(stream_mode_start_num, uint, 0664);
9243MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9244
9245/*
9246module_param(trigger_task, uint, 0664);
9247MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9248*/
9249module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9250
9251module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9252
9253module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9254
9255module_param_array(run_count, uint,
9256 &max_decode_instance_num, 0664);
9257
9258module_param_array(not_run_ready, uint,
9259 &max_decode_instance_num, 0664);
9260
9261module_param_array(input_empty, uint,
9262 &max_decode_instance_num, 0664);
9263
9264module_param_array(max_get_frame_interval, uint,
9265 &max_decode_instance_num, 0664);
9266
9267module_param_array(step, uint, &max_decode_instance_num, 0664);
9268
9269module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9270
9271module_param(disp_vframe_valve_level, uint, 0664);
9272MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9273
9274module_param(double_write_mode, uint, 0664);
9275MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9276
9277module_param(mem_map_mode, uint, 0664);
9278MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9279
9280module_param(without_display_mode, uint, 0664);
9281MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9282
9283
9284module_init(ammvdec_h264_driver_init_module);
9285module_exit(ammvdec_h264_driver_remove_module);
9286
9287MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9288MODULE_LICENSE("GPL");
9289
generated by cgit at 2024-05-17 08:46:43 (GMT)