summaryrefslogtreecommitdiff
path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 2b3e5c3bd7532d1c8af3d36acaca967b5efca9ce
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64#include <media/v4l2-mem2mem.h>
65
66#undef pr_info
67#define pr_info printk
68#define VDEC_DW
69#define DEBUG_UCODE
70#define MEM_NAME "codec_m264"
71#define MULTI_INSTANCE_FRAMEWORK
72/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
73#include "h264_dpb.h"
74/* #define SEND_PARAM_WITH_REG */
75
76#define DRIVER_NAME "ammvdec_h264"
77#define MODULE_NAME "ammvdec_h264"
78#define DRIVER_HEADER_NAME "ammvdec_h264_header"
79
80#define CHECK_INTERVAL (HZ/100)
81
82#define SEI_DATA_SIZE (8*1024)
83#define SEI_ITU_DATA_SIZE (4*1024)
84
85#define RATE_MEASURE_NUM 8
86#define RATE_CORRECTION_THRESHOLD 5
87#define RATE_2397_FPS 4004 /* 23.97 */
88#define RATE_25_FPS 3840 /* 25 */
89#define RATE_2997_FPS 3203 /* 29.97 */
90#define DUR2PTS(x) ((x)*90/96)
91#define PTS2DUR(x) ((x)*96/90)
92#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
93#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
94
95#define FIX_FRAME_RATE_OFF 0
96#define FIX_FRAME_RATE_ON 1
97#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
98
99#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
100#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
101#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
102#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
103
104#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
105
106#define RATE_MEASURE_NUM 8
107#define RATE_CORRECTION_THRESHOLD 5
108#define RATE_24_FPS 4004 /* 23.97 */
109#define RATE_25_FPS 3840 /* 25 */
110#define DUR2PTS(x) ((x)*90/96)
111#define PTS2DUR(x) ((x)*96/90)
112#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
113#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
114
115#define H264_DEV_NUM 9
116
117#define CONSTRAIN_MAX_BUF_NUM
118
119#define H264_MMU
120#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
121#define INVALID_IDX -1 /* Invalid buffer index.*/
122
123static int mmu_enable;
124/*mmu do not support mbaff*/
125static int force_enable_mmu = 0;
126unsigned int h264_debug_flag; /* 0xa0000000; */
127unsigned int h264_debug_mask = 0xff;
128 /*
129 *h264_debug_cmd:
130 * 0x1xx, force decoder id of xx to be disconnected
131 */
132unsigned int h264_debug_cmd;
133
134static unsigned int dec_control =
135 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
136 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
137
138static unsigned int force_rate_streambase;
139static unsigned int force_rate_framebase;
140static unsigned int force_disp_bufspec_num;
141static unsigned int fixed_frame_rate_mode;
142static unsigned int error_recovery_mode_in;
143static int start_decode_buf_level = 0x4000;
144static int pre_decode_buf_level = 0x1000;
145static int stream_mode_start_num = 4;
146
147#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
148/*to make reorder size difference of bl and el not too big*/
149static unsigned int reorder_dpb_size_margin_dv = 16;
150#endif
151static unsigned int reorder_dpb_size_margin = 6;
152static unsigned int reference_buf_margin = 4;
153
154#ifdef CONSTRAIN_MAX_BUF_NUM
155static u32 run_ready_max_vf_only_num;
156static u32 run_ready_display_q_num;
157 /*0: not check
158 0xff: mDPB.size
159 */
160static u32 run_ready_max_buf_num = 0xff;
161#endif
162
163static u32 run_ready_min_buf_num = 2;
164
165#define VDEC_ASSIST_CANVAS_BLK32 0x5
166
167
168static unsigned int max_alloc_buf_count;
169static unsigned int decode_timeout_val = 100;
170static unsigned int errordata_timeout_val = 50;
171static unsigned int get_data_timeout_val = 2000;
172#if 1
173/* H264_DATA_REQUEST does not work, disable it,
174decode has error for data in none continuous address
175*/
176static unsigned int frame_max_data_packet;
177#else
178static unsigned int frame_max_data_packet = 8;
179#endif
180static unsigned int radr;
181static unsigned int rval;
182static u32 endian = 0xff0;
183
184/*
185 udebug_flag:
186 bit 0, enable ucode print
187 bit 1, enable ucode detail print
188 bit 3, disable ucode watchdog
189 bit [31:16] not 0, pos to dump lmem
190 bit 2, pop bits to lmem
191 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
192*/
193static u32 udebug_flag;
194/*
195 when udebug_flag[1:0] is not 0
196 udebug_pause_pos not 0,
197 pause position
198*/
199static u32 udebug_pause_pos;
200/*
201 when udebug_flag[1:0] is not 0
202 and udebug_pause_pos is not 0,
203 pause only when DEBUG_REG2 is equal to this val
204*/
205static u32 udebug_pause_val;
206
207static u32 udebug_pause_decode_idx;
208
209static unsigned int disp_vframe_valve_level;
210
211static unsigned int max_decode_instance_num = H264_DEV_NUM;
212static unsigned int decode_frame_count[H264_DEV_NUM];
213static unsigned int display_frame_count[H264_DEV_NUM];
214static unsigned int max_process_time[H264_DEV_NUM];
215static unsigned int max_get_frame_interval[H264_DEV_NUM];
216static unsigned int run_count[H264_DEV_NUM];
217static unsigned int input_empty[H264_DEV_NUM];
218static unsigned int not_run_ready[H264_DEV_NUM];
219static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
220{1, 1, 1, 1, 1, 1, 1, 1, 1};
221
222#define VDEC_CLOCK_ADJUST_FRAME 30
223static unsigned int clk_adj_frame_count;
224
225/*
226 *bit[3:0]: 0, run ; 1, pause; 3, step
227 *bit[4]: 1, schedule run
228 */
229static unsigned int step[H264_DEV_NUM];
230
231#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
232static u32 prefix_aux_buf_size = (16 * 1024);
233static u32 suffix_aux_buf_size;
234
235#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
236static u32 dv_toggle_prov_name;
237
238static u32 dolby_meta_with_el;
239#endif
240
241/*
242 bit[8]
243 0: use sys_info[bit 3]
244 not 0:use i_only_flag[7:0]
245 bit[7:0]:
246 bit 0, 1: only display I picture;
247 bit 1, 1: only decode I picture;
248*/
249static unsigned int i_only_flag;
250
251/*
252 error_proc_policy:
253 bit[0] send_error_frame_flag;
254 (valid when bit[31] is 1, otherwise use sysinfo)
255 bit[1] do not decode if config_decode_buf() fail
256 bit[2] force release buf if in deadlock
257 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
258 bit[4] check inactive of receiver
259 bit[5] reset buffmgr if in deadlock
260 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
261 bit[7] reset buffmgr if dpb error
262
263 bit[8] check total mbx/mby of decoded frame
264 bit[9] check ERROR_STATUS_REG
265 bit[10] check reference list
266 bit[11] mark error if dpb error
267 bit[12] i_only when error happen
268 bit[13] 0: mark error according to last pic, 1: ignore mark error
269 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
270*/
271static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
272
273
274/*
275 error_skip_count:
276 bit[11:0] error skip frame count
277 bit[15:12] error skip i picture count
278*/
279static unsigned int error_skip_count = (0x2 << 12) | 0x40;
280
281static unsigned int force_sliding_margin;
282/*
283 bit[1:0]:
284 0, start playing from any frame
285 1, start playing from I frame
286 bit[15:8]: the count of skip frames after first I
287 2, start playing from second I frame (decode from the first I)
288 bit[15:8]: the max count of skip frames after first I
289 3, start playing from IDR
290*/
291static unsigned int first_i_policy = 1;
292
293/*
294 fast_output_enable:
295 bit [0], output frame if there is IDR in list
296 bit [1], output frame if the current poc is 1 big than the previous poc
297 bit [2], if even poc only, output frame ifthe cuurent poc
298 is 2 big than the previous poc
299 bit [3], ip only
300*/
301static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
302
303static unsigned int enable_itu_t35 = 1;
304
305static unsigned int frmbase_cont_bitlevel = 0x40;
306
307static unsigned int frmbase_cont_bitlevel2 = 0x1;
308
309
310#define MH264_USERDATA_ENABLE
311
312/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
313/* hevc->double_write_mode:
314 0, no double write
315 1, 1:1 ratio
316 2, (1/4):(1/4) ratio
317 3, (1/4):(1/4) ratio, with both compressed frame included
318 4, (1/2):(1/2) ratio
319 0x10, double write only
320 0x10000: vdec dw horizotal 1/2
321 0x20000: vdec dw horizotal/vertical 1/2
322*/
323static u32 double_write_mode;
324static u32 without_display_mode;
325#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
326
327static void vmh264_dump_state(struct vdec_s *vdec);
328
329#define is_in_parsing_state(status) \
330 ((status == H264_ACTION_SEARCH_HEAD) || \
331 ((status & 0xf0) == 0x80))
332
333#define is_interlace(frame) \
334 (frame->frame &&\
335 frame->top_field &&\
336 frame->bottom_field &&\
337 (!frame->frame->coded_frame))
338static inline bool close_to(int a, int b, int m)
339{
340 return (abs(a - b) < m) ? true : false;
341}
342
343#if 0
344#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
345#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
346#else
347#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
348#define h264_free_hw_stru(dev, hw) vfree(hw)
349#endif
350
351/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
352#define NV21
353/* #endif */
354
355/* 12M for L41 */
356#define MAX_DPB_BUFF_SIZE (12*1024*1024)
357#define DEFAULT_MEM_SIZE (32*1024*1024)
358#define AVIL_DPB_BUFF_SIZE 0x01ec2000
359
360#define DEF_BUF_START_ADDR 0x01000000
361#define mem_sps_base 0x011c3c00
362#define mem_pps_base 0x011cbc00
363/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
364u32 V_BUF_ADDR_OFFSET = 0x200000;
365#define DCAC_READ_MARGIN (64 * 1024)
366
367
368#define EXTEND_SAR 0xff
369#define BUFSPEC_POOL_SIZE 64
370#define VF_POOL_SIZE 64
371#define VF_POOL_NUM 2
372#define MAX_VF_BUF_NUM 27
373#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
374#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
375#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
376#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
377#define EXTIF_BUF_SIZE (0x10000 * 2)
378
379#define HEADER_BUFFER_IDX(n) (n)
380#define VF_BUFFER_IDX(n) (n)
381
382
383#define PUT_INTERVAL (HZ/100)
384#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
385
386#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
387#define SWITCHING_STATE_OFF 0
388#define SWITCHING_STATE_ON_CMD3 1
389#define SWITCHING_STATE_ON_CMD1 2
390
391
392
393#define INCPTR(p) ptr_atomic_wrap_inc(&p)
394
395#define SLICE_TYPE_I 2
396#define SLICE_TYPE_P 5
397#define SLICE_TYPE_B 6
398
399struct buffer_spec_s {
400 /*
401 used:
402 -1, none allocated
403 0, allocated, free
404 1, used by dpb
405 2, in disp queue;
406 3, in disp queue, isolated,
407 do not use for dpb when vf_put;
408 4, to release
409 5, in disp queue, isolated (but not to release)
410 do not use for dpb when vf_put;
411 */
412 unsigned int used;
413 unsigned int info0;
414 unsigned int info1;
415 unsigned int info2;
416 unsigned int y_addr;
417 unsigned int u_addr;
418 unsigned int v_addr;
419
420 int y_canvas_index;
421 int u_canvas_index;
422 int v_canvas_index;
423
424#ifdef VDEC_DW
425 unsigned int vdec_dw_y_addr;
426 unsigned int vdec_dw_u_addr;
427 unsigned int vdec_dw_v_addr;
428
429 int vdec_dw_y_canvas_index;
430 int vdec_dw_u_canvas_index;
431 int vdec_dw_v_canvas_index;
432#ifdef NV21
433 struct canvas_config_s vdec_dw_canvas_config[2];
434#else
435 struct canvas_config_s vdec_dw_canvas_config[3];
436#endif
437#endif
438
439#ifdef NV21
440 struct canvas_config_s canvas_config[2];
441#else
442 struct canvas_config_s canvas_config[3];
443#endif
444 unsigned long cma_alloc_addr;
445 unsigned int buf_adr;
446#ifdef H264_MMU
447 unsigned long alloc_header_addr;
448#endif
449 char *aux_data_buf;
450 int aux_data_size;
451#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
452 unsigned char dv_enhance_exist;
453#endif
454 int canvas_pos;
455 int vf_ref;
456 /*unsigned int comp_body_size;*/
457 unsigned int dw_y_adr;
458 unsigned int dw_u_v_adr;
459};
460
461#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
462#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
463#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
464
465
466#define vdec_dw_spec2canvas(x) \
467 (((x)->vdec_dw_v_canvas_index << 16) | \
468 ((x)->vdec_dw_u_canvas_index << 8) | \
469 ((x)->vdec_dw_y_canvas_index << 0))
470
471
472#define spec2canvas(x) \
473 (((x)->v_canvas_index << 16) | \
474 ((x)->u_canvas_index << 8) | \
475 ((x)->y_canvas_index << 0))
476
477#define FRAME_INDEX(vf_index) (vf_index & 0xff)
478#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
479#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
480
481static struct vframe_s *vh264_vf_peek(void *);
482static struct vframe_s *vh264_vf_get(void *);
483static void vh264_vf_put(struct vframe_s *, void *);
484static int vh264_vf_states(struct vframe_states *states, void *);
485static int vh264_event_cb(int type, void *data, void *private_data);
486static void vh264_work(struct work_struct *work);
487static void vh264_timeout_work(struct work_struct *work);
488static void vh264_notify_work(struct work_struct *work);
489#ifdef MH264_USERDATA_ENABLE
490static void user_data_ready_notify_work(struct work_struct *work);
491static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
492#endif
493
494static const char vh264_dec_id[] = "vh264-dev";
495
496#define PROVIDER_NAME "vdec.h264"
497
498static const struct vframe_operations_s vf_provider_ops = {
499 .peek = vh264_vf_peek,
500 .get = vh264_vf_get,
501 .put = vh264_vf_put,
502 .event_cb = vh264_event_cb,
503 .vf_states = vh264_vf_states,
504};
505
506#define DEC_RESULT_NONE 0
507#define DEC_RESULT_DONE 1
508#define DEC_RESULT_AGAIN 2
509#define DEC_RESULT_CONFIG_PARAM 3
510#define DEC_RESULT_GET_DATA 4
511#define DEC_RESULT_GET_DATA_RETRY 5
512#define DEC_RESULT_ERROR 6
513#define DEC_RESULT_EOS 7
514#define DEC_RESULT_FORCE_EXIT 8
515
516/*
517 *static const char *dec_result_str[] = {
518 * "DEC_RESULT_NONE ",
519 * "DEC_RESULT_DONE ",
520 * "DEC_RESULT_AGAIN ",
521 * "DEC_RESULT_CONFIG_PARAM",
522 * "DEC_RESULT_GET_DATA ",
523 * "DEC_RESULT_GET_DA_RETRY",
524 * "DEC_RESULT_ERROR ",
525 *};
526 */
527
528#define UCODE_IP_ONLY 2
529#define UCODE_IP_ONLY_PARAM 1
530
531#define MC_OFFSET_HEADER 0x0000
532#define MC_OFFSET_DATA 0x1000
533#define MC_OFFSET_MMCO 0x2000
534#define MC_OFFSET_LIST 0x3000
535#define MC_OFFSET_SLICE 0x4000
536#define MC_OFFSET_MAIN 0x5000
537
538#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
539#define MC_SWAP_SIZE (4*SZ_1K)
540#define MODE_ERROR 0
541#define MODE_FULL 1
542
543#define DFS_HIGH_THEASHOLD 3
544
545#define INIT_FLAG_REG AV_SCRATCH_2
546#define HEAD_PADING_REG AV_SCRATCH_3
547#define UCODE_WATCHDOG_REG AV_SCRATCH_7
548#define LMEM_DUMP_ADR AV_SCRATCH_L
549#define DEBUG_REG1 AV_SCRATCH_M
550#define DEBUG_REG2 AV_SCRATCH_N
551#define FRAME_COUNTER_REG AV_SCRATCH_I
552#define RPM_CMD_REG AV_SCRATCH_A
553#define H264_DECODE_SIZE AV_SCRATCH_E
554#define H264_DECODE_MODE AV_SCRATCH_4
555#define H264_DECODE_SEQINFO AV_SCRATCH_5
556#define H264_AUX_ADR AV_SCRATCH_C
557#define H264_AUX_DATA_SIZE AV_SCRATCH_H
558
559#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
560#define DPB_STATUS_REG AV_SCRATCH_J
561#define ERROR_STATUS_REG AV_SCRATCH_9
562 /*
563 NAL_SEARCH_CTL: bit 0, enable itu_t35
564 NAL_SEARCH_CTL: bit 1, enable mmu
565 */
566#define NAL_SEARCH_CTL AV_SCRATCH_9
567#define MBY_MBX MB_MOTION_MODE /*0xc07*/
568
569#define DECODE_MODE_SINGLE 0x0
570#define DECODE_MODE_MULTI_FRAMEBASE 0x1
571#define DECODE_MODE_MULTI_STREAMBASE 0x2
572#define DECODE_MODE_MULTI_DVBAL 0x3
573#define DECODE_MODE_MULTI_DVENL 0x4
574static DEFINE_MUTEX(vmh264_mutex);
575
576
577
578#ifdef MH264_USERDATA_ENABLE
579
580struct mh264_userdata_record_t {
581 struct userdata_meta_info_t meta_info;
582 u32 rec_start;
583 u32 rec_len;
584};
585
586struct mh264_ud_record_wait_node_t {
587 struct list_head list;
588 struct mh264_userdata_record_t ud_record;
589};
590#define USERDATA_FIFO_NUM 256
591#define MAX_FREE_USERDATA_NODES 5
592
593struct mh264_userdata_info_t {
594 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
595 u8 *data_buf;
596 u8 *data_buf_end;
597 u32 buf_len;
598 u32 read_index;
599 u32 write_index;
600 u32 last_wp;
601};
602
603
604#endif
605
606struct vdec_h264_hw_s {
607 spinlock_t lock;
608 spinlock_t bufspec_lock;
609 int id;
610 struct platform_device *platform_dev;
611 unsigned long cma_alloc_addr;
612 /* struct page *collocate_cma_alloc_pages; */
613 unsigned long collocate_cma_alloc_addr;
614
615 u32 prefix_aux_size;
616 u32 suffix_aux_size;
617 void *aux_addr;
618 dma_addr_t aux_phy_addr;
619
620 /* buffer for store all sei data */
621 void *sei_data_buf;
622 u32 sei_data_len;
623
624 /* buffer for storing one itu35 recored */
625 void *sei_itu_data_buf;
626 u32 sei_itu_data_len;
627
628 /* recycle buffer for user data storing all itu35 records */
629 void *sei_user_data_buffer;
630 u32 sei_user_data_wp;
631#ifdef MH264_USERDATA_ENABLE
632 struct work_struct user_data_ready_work;
633#endif
634 struct StorablePicture *last_dec_picture;
635
636 ulong lmem_addr;
637 dma_addr_t lmem_addr_remap;
638
639 void *bmmu_box;
640#ifdef H264_MMU
641 void *mmu_box;
642 void *frame_mmu_map_addr;
643 dma_addr_t frame_mmu_map_phy_addr;
644 u32 hevc_cur_buf_idx;
645 u32 losless_comp_body_size;
646 u32 losless_comp_body_size_sao;
647 u32 losless_comp_header_size;
648 u32 mc_buffer_size_u_v;
649 u32 mc_buffer_size_u_v_h;
650 u32 is_idr_frame;
651 u32 is_new_pic;
652 u32 frame_done;
653 u32 frame_busy;
654 unsigned long extif_addr;
655 int double_write_mode;
656 int mmu_enable;
657#endif
658
659 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
660 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
661
662 int cur_pool;
663 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
664 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
665 struct vframe_s switching_fense_vf;
666 struct h264_dpb_stru dpb;
667 u8 init_flag;
668 u8 first_sc_checked;
669 u8 has_i_frame;
670 u8 config_bufmgr_done;
671 u32 max_reference_size;
672 u32 decode_pic_count;
673 u32 reflist_error_count;
674 int start_search_pos;
675 u32 reg_iqidct_control;
676 u32 reg_vcop_ctrl_reg;
677 u32 reg_rv_ai_mb_count;
678 u32 vld_dec_control;
679 struct vframe_s vframe_dummy;
680
681 unsigned char buffer_empty_flag;
682
683 u32 frame_width;
684 u32 frame_height;
685 u32 frame_dur;
686 u32 frame_prog;
687 u32 frame_packing_type;
688
689 struct vframe_chunk_s *chunk;
690
691 u32 stat;
692 unsigned long buf_start;
693 u32 buf_offset;
694 u32 buf_size;
695 /* u32 ucode_map_start; */
696 u32 pts_outside;
697 u32 sync_outside;
698 u32 vh264_ratio;
699 u32 vh264_rotation;
700 u32 use_idr_framerate;
701
702 u32 seq_info;
703 u32 seq_info2;
704 u32 video_signal_from_vui; /*to do .. */
705 u32 timing_info_present_flag;
706 u32 fixed_frame_rate_flag;
707 u32 bitstream_restriction_flag;
708 u32 num_reorder_frames;
709 u32 max_dec_frame_buffering;
710 u32 iframe_count;
711 u32 aspect_ratio_info;
712 u32 num_units_in_tick;
713 u32 time_scale;
714 u32 h264_ar;
715 bool h264_first_valid_pts_ready;
716 u32 h264pts1;
717 u32 h264pts2;
718 u32 pts_duration;
719 u32 h264_pts_count;
720 u32 duration_from_pts_done;
721 u32 pts_unstable;
722 u32 unstable_pts;
723 u32 last_checkout_pts;
724 u32 max_refer_buf;
725
726 s32 vh264_stream_switching_state;
727 struct vframe_s *p_last_vf;
728 u32 last_pts;
729 u32 last_pts_remainder;
730 u32 last_duration;
731 u32 last_mb_width, last_mb_height;
732 bool check_pts_discontinue;
733 bool pts_discontinue;
734 u32 wait_buffer_counter;
735 u32 first_offset;
736 u32 first_pts;
737 u64 first_pts64;
738 bool first_pts_cached;
739 u64 last_pts64;
740#if 0
741 void *sei_data_buffer;
742 dma_addr_t sei_data_buffer_phys;
743#endif
744
745 uint error_recovery_mode;
746 uint mb_total;
747 uint mb_width;
748 uint mb_height;
749
750 uint i_only;
751 int skip_frame_count;
752 bool no_poc_reorder_flag;
753 bool send_error_frame_flag;
754 dma_addr_t mc_dma_handle;
755 void *mc_cpu_addr;
756 int vh264_reset;
757
758 atomic_t vh264_active;
759
760 struct dec_sysinfo vh264_amstream_dec_info;
761
762 int dec_result;
763 struct work_struct work;
764 struct work_struct notify_work;
765 struct work_struct timeout_work;
766 void (*vdec_cb)(struct vdec_s *, void *);
767 void *vdec_cb_arg;
768
769 struct timer_list check_timer;
770
771 /**/
772 unsigned int last_frame_time;
773 u32 vf_pre_count;
774 u32 vf_get_count;
775 u32 vf_put_count;
776
777 /* timeout handle */
778 unsigned long int start_process_time;
779 unsigned int last_mby_mbx;
780 unsigned int last_vld_level;
781 unsigned int decode_timeout_count;
782 unsigned int timeout_num;
783 unsigned int search_dataempty_num;
784 unsigned int decode_timeout_num;
785 unsigned int decode_dataempty_num;
786 unsigned int buffer_empty_recover_num;
787
788 unsigned get_data_count;
789 unsigned get_data_start_time;
790 /**/
791
792 /*log*/
793 unsigned int packet_write_success_count;
794 unsigned int packet_write_EAGAIN_count;
795 unsigned int packet_write_ENOMEM_count;
796 unsigned int packet_write_EFAULT_count;
797 unsigned int total_read_size_pre;
798 unsigned int total_read_size;
799 unsigned int frame_count_pre;
800#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
801 u8 switch_dvlayer_flag;
802 u8 got_valid_nal;
803#endif
804 u8 eos;
805 u8 data_flag;
806 u32 no_error_count;
807 u32 no_error_i_count;
808 /*
809 NODISP_FLAG
810 */
811 u8 dec_flag;
812
813 u32 ucode_pause_pos;
814
815 u8 reset_bufmgr_flag;
816 u32 reset_bufmgr_count;
817 u32 cfg_param1;
818 u32 cfg_param2;
819 u32 cfg_param3;
820 u32 cfg_param4;
821 int valve_count;
822 u8 next_again_flag;
823 u32 pre_parser_wr_ptr;
824 struct firmware_s *fw;
825 struct firmware_s *fw_mmu;
826#ifdef MH264_USERDATA_ENABLE
827 /*user data*/
828 struct mutex userdata_mutex;
829 struct mh264_userdata_info_t userdata_info;
830 struct mh264_userdata_record_t ud_record;
831 int wait_for_udr_send;
832#endif
833 u32 no_mem_count;
834 u32 canvas_mode;
835 bool is_used_v4l;
836 void *v4l2_ctx;
837 bool v4l_params_parsed;
838 wait_queue_head_t wait_q;
839 u32 reg_g_status;
840 struct mutex chunks_mutex;
841 int need_cache_size;
842 u64 sc_start_time;
843 u8 frmbase_cont_flag;
844 struct vframe_qos_s vframe_qos;
845 int frameinfo_enable;
846 bool first_head_check_flag;
847 unsigned int height_aspect_ratio;
848 unsigned int width_aspect_ratio;
849 bool new_iframe_flag;
850 bool ref_err_flush_dpb_flag;
851 unsigned int first_i_policy;
852 u32 reorder_dpb_size_margin;
853 bool wait_reset_done_flag;
854};
855
856static u32 again_threshold;
857
858static void timeout_process(struct vdec_h264_hw_s *hw);
859static void dump_bufspec(struct vdec_h264_hw_s *hw,
860 const char *caller);
861static void h264_reconfig(struct vdec_h264_hw_s *hw);
862static void h264_reset_bufmgr(struct vdec_s *vdec);
863static void vh264_local_init(struct vdec_h264_hw_s *hw);
864static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
865static int vh264_stop(struct vdec_h264_hw_s *hw);
866static s32 vh264_init(struct vdec_h264_hw_s *hw);
867static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
868 u32 index);
869static void release_aux_data(struct vdec_h264_hw_s *hw,
870 int buf_spec_num);
871#ifdef ERROR_HANDLE_TEST
872static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
873#endif
874
875#define H265_PUT_SAO_4K_SET 0x03
876#define H265_ABORT_SAO_4K_SET 0x04
877#define H265_ABORT_SAO_4K_SET_DONE 0x05
878
879#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
880#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
881#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
882#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
883#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
884
885
886#define HEVC_CM_HEADER_START_ADDR 0x3628
887#define HEVC_CM_BODY_START_ADDR 0x3626
888#define HEVC_CM_BODY_LENGTH 0x3627
889#define HEVC_CM_HEADER_LENGTH 0x3629
890#define HEVC_CM_HEADER_OFFSET 0x362b
891#define HEVC_SAO_CTRL9 0x362d
892#define HEVCD_MPP_DECOMP_CTL3 0x34c4
893#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
894#define HEVC_DBLK_CFGB 0x350b
895#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
896
897#define H265_DW_NO_SCALE
898#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
899#define H265_LOSLESS_COMPRESS_MODE
900#define MAX_FRAME_4K_NUM 0x1200
901#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
902
903/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
904static u32 mem_map_mode = H265_MEM_MAP_MODE;
905
906#define MAX_SIZE_8K (8192 * 4608)
907#define MAX_SIZE_4K (4096 * 2304)
908
909static int is_oversize(int w, int h)
910{
911 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
912 MAX_SIZE_8K : MAX_SIZE_4K;
913
914 if (w < 0 || h < 0)
915 return true;
916
917 if (h != 0 && (w > max / h))
918 return true;
919
920 return false;
921}
922
923static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
924 int frame_type,
925 u32 vpts,
926 u32 vpts_valid);
927static int compute_losless_comp_body_size(int width,
928 int height, int bit_depth_10);
929static int compute_losless_comp_header_size(int width, int height);
930
931static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
932 int pic_width, int pic_height, u16 bit_depth,
933 unsigned int *mmu_index_adr) {
934 int cur_buf_idx;
935 int bit_depth_10 = (bit_depth != 0x00);
936 int picture_size;
937 u32 cur_mmu_4k_number;
938
939 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
940 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
941 picture_size = compute_losless_comp_body_size(pic_width,
942 pic_height, bit_depth_10);
943 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
944 dpb_print(DECODE_ID(hw),
945 PRINT_FLAG_MMU_DETAIL,
946 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
947 cur_buf_idx, picture_size, cur_mmu_4k_number);
948
949 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
950 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
951 cur_mmu_4k_number);
952 return -1;
953 }
954
955 return decoder_mmu_box_alloc_idx(
956 hw->mmu_box,
957 cur_buf_idx,
958 cur_mmu_4k_number,
959 mmu_index_adr);
960}
961
962static int compute_losless_comp_body_size(int width,
963 int height, int bit_depth_10)
964{
965 int width_x64;
966 int height_x32;
967 int bsize;
968
969 width_x64 = width + 63;
970 width_x64 >>= 6;
971
972 height_x32 = height + 31;
973 height_x32 >>= 5;
974
975#ifdef H264_MMU
976 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
977#else
978 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
979#endif
980 return bsize;
981}
982
983static int compute_losless_comp_header_size(int width, int height)
984{
985 int width_x64;
986 int width_x128;
987 int height_x64;
988 int hsize;
989
990 width_x64 = width + 63;
991 width_x64 >>= 6;
992
993 width_x128 = width + 127;
994 width_x128 >>= 7;
995
996 height_x64 = height + 63;
997 height_x64 >>= 6;
998
999#ifdef H264_MMU
1000 hsize = 128*width_x64*height_x64;
1001#else
1002 hsize = 32*width_x128*height_x64;
1003#endif
1004 return hsize;
1005}
1006
1007static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1008{
1009 int ratio = 1;
1010 int dw_mode = hw->double_write_mode;
1011 if ((dw_mode == 2) ||
1012 (dw_mode == 3))
1013 ratio = 4;
1014 else if (dw_mode == 4)
1015 ratio = 2;
1016 return ratio;
1017}
1018
1019
1020static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1021{
1022 int pic_width, pic_height;
1023 int lcu_size = 16;
1024 int dw_buf_size;
1025 u32 dw_buffer_size_u_v;
1026 u32 dw_buffer_size_u_v_h;
1027 int dw_mode = hw->double_write_mode;
1028
1029 pic_width = hw->frame_width;
1030 pic_height = hw->frame_height;
1031
1032 if (dw_mode) {
1033 int pic_width_dw = pic_width /
1034 get_double_write_ratio(hw);
1035 int pic_height_dw = pic_height /
1036 get_double_write_ratio(hw);
1037
1038 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1039 pic_width_dw / lcu_size + 1 :
1040 pic_width_dw / lcu_size;
1041 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1042 pic_height_dw / lcu_size + 1 :
1043 pic_height_dw / lcu_size;
1044 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1045
1046
1047 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1048 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1049 /*64k alignment*/
1050 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1051 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1052 } else {
1053 *pdw_buffer_size_u_v_h = 0;
1054 dw_buf_size = 0;
1055 }
1056
1057 return dw_buf_size;
1058}
1059
1060
1061static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1062{
1063 int i, size;
1064 u32 canvas_addr;
1065 unsigned long maddr;
1066 int num_buff = hw->dpb.mDPB.size;
1067 int dw_size = 0;
1068 u32 dw_buffer_size_u_v_h;
1069 u32 blkmode = hw->canvas_mode;
1070 int dw_mode = hw->double_write_mode;
1071
1072 canvas_addr = ANC0_CANVAS_ADDR;
1073 for (i = 0; i < num_buff; i++)
1074 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1075
1076 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1077 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1078
1079
1080 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1081 size += dw_size;
1082 if (size > 0)
1083 size += 0x10000;
1084
1085 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1086 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1087 dw_buffer_size_u_v_h, dw_size, size);
1088
1089 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1090 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1091 hw->losless_comp_body_size,
1092 hw->losless_comp_header_size,
1093 hw->losless_comp_body_size_sao);
1094
1095 for (i = 0; i < num_buff; i++) {
1096 if (!restore) {
1097 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1098 HEADER_BUFFER_IDX(i), size,
1099 DRIVER_HEADER_NAME, &maddr) < 0) {
1100 dpb_print(DECODE_ID(hw), 0,
1101 "%s malloc compress header failed %d\n",
1102 DRIVER_HEADER_NAME, i);
1103 return;
1104 }
1105 } else
1106 maddr = hw->buffer_spec[i].alloc_header_addr;
1107 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1108 hw->buffer_spec[i].alloc_header_addr = maddr;
1109 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1110 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1111 __func__, i, (u32)maddr, size);
1112
1113 if (dw_mode) {
1114 u32 addr;
1115 int canvas_w;
1116 int canvas_h;
1117
1118 canvas_w = hw->frame_width /
1119 get_double_write_ratio(hw);
1120 canvas_h = hw->frame_height /
1121 get_double_write_ratio(hw);
1122
1123 if (hw->canvas_mode == 0)
1124 canvas_w = ALIGN(canvas_w, 32);
1125 else
1126 canvas_w = ALIGN(canvas_w, 64);
1127 canvas_h = ALIGN(canvas_h, 32);
1128
1129 hw->buffer_spec[i].dw_y_adr =
1130 maddr + hw->losless_comp_header_size;
1131
1132 hw->buffer_spec[i].dw_y_adr =
1133 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1134 << 16;
1135 hw->buffer_spec[i].dw_u_v_adr =
1136 hw->buffer_spec[i].dw_y_adr
1137 + (dw_buffer_size_u_v_h << 16) * 2;
1138
1139
1140 hw->buffer_spec[i].buf_adr
1141 = hw->buffer_spec[i].dw_y_adr;
1142 addr = hw->buffer_spec[i].buf_adr;
1143
1144
1145 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1146 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1147 hw->buffer_spec[i].dw_y_adr,
1148 hw->buffer_spec[i].dw_u_v_adr,
1149 hw->buffer_spec[i].y_addr,
1150 hw->buffer_spec[i].u_addr,
1151 hw->buffer_spec[i].v_addr,
1152 canvas_w,
1153 canvas_h);
1154
1155 hw->buffer_spec[i].canvas_config[0].phy_addr =
1156 hw->buffer_spec[i].dw_y_adr;
1157 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1158 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1159 hw->buffer_spec[i].canvas_config[0].block_mode =
1160 blkmode;
1161 hw->buffer_spec[i].canvas_config[0].endian = 7;
1162
1163 hw->buffer_spec[i].canvas_config[1].phy_addr =
1164 hw->buffer_spec[i].dw_u_v_adr;
1165 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1166 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1167 hw->buffer_spec[i].canvas_config[1].block_mode =
1168 blkmode;
1169 hw->buffer_spec[i].canvas_config[1].endian = 7;
1170 }
1171 }
1172 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1173
1174 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1175 for (i = 0; i < 32; i++)
1176 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1177 return;
1178}
1179static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1180{
1181 u32 i;
1182 u32 ref_canv;
1183 struct Slice *pSlice = &(hw->dpb.mSlice);
1184 /*REFLIST[0]*/
1185 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1186 struct StorablePicture *ref = pSlice->listX[0][i];
1187 if (ref == NULL)
1188 return;
1189 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1190 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1191 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1192 (ref->buf_spec_num & 0x3f) << 8);
1193 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1194 }
1195 /*REFLIST[1]*/
1196 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1197 struct StorablePicture *ref = pSlice->listX[1][i];
1198 if (ref == NULL)
1199 return;
1200 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1201 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1202 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1203 (ref->buf_spec_num & 0x3f) << 8);
1204 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1205 }
1206 return;
1207}
1208
1209static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1210{
1211 u32 rdata32;
1212 u32 rdata32_2;
1213 u32 slice_type;
1214 struct StorablePicture *ref;
1215 struct Slice *pSlice;
1216 slice_type = hw->dpb.mSlice.slice_type;
1217 pSlice = &(hw->dpb.mSlice);
1218 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1219 if (slice_type == I_SLICE) {
1220 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1221 return;
1222 }
1223 if (slice_type == B_SLICE) {
1224 ref = pSlice->listX[0][0];
1225 if (ref == NULL)
1226 return;
1227 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1228 ((ref->buf_spec_num & 0x3f) << 8));
1229 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1230 rdata32 = rdata32 & 0xffff;
1231 rdata32 = rdata32 | (rdata32 << 16);
1232 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1233
1234 ref = pSlice->listX[1][0];
1235 if (ref == NULL)
1236 return;
1237 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1238 ((ref->buf_spec_num & 0x3f) << 8));
1239 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1240 rdata32_2 = rdata32_2 & 0xffff;
1241 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1242 if (rdata32 == rdata32_2) {
1243 ref = pSlice->listX[1][1];
1244 if (ref == NULL)
1245 return;
1246 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1247 ((ref->buf_spec_num & 0x3f) << 8));
1248 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1249 rdata32_2 = rdata32_2 & 0xffff;
1250 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1251 }
1252 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1253 } else { /*P-PIC*/
1254 ref = pSlice->listX[0][0];
1255 if (ref == NULL)
1256 return;
1257 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1258 ((ref->buf_spec_num & 0x3f) << 8));
1259 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1260 rdata32 = rdata32 & 0xffff;
1261 rdata32 = rdata32 | (rdata32 << 16);
1262 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1263
1264 ref = pSlice->listX[0][1];
1265 if (ref == NULL)
1266 return;
1267 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1268 ((ref->buf_spec_num & 0x3f) << 8));
1269 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1270 rdata32 = rdata32 & 0xffff;
1271 rdata32 = rdata32 | (rdata32 << 16);
1272 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1273 }
1274 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1275 return;
1276}
1277
1278
1279static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1280 u32 width, u32 height) {
1281 u32 data32;
1282 u32 lcu_x_num, lcu_y_num;
1283 u32 lcu_total;
1284 u32 mc_buffer_size_u_v;
1285 u32 mc_buffer_size_u_v_h;
1286 int dw_mode = hw->double_write_mode;
1287
1288 lcu_x_num = (width + 15) >> 4;
1289 lcu_y_num = (height + 15) >> 4;
1290 lcu_total = lcu_x_num * lcu_y_num;
1291
1292 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1293 hw->mc_buffer_size_u_v_h =
1294 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1295
1296 hw->losless_comp_body_size = 0;
1297
1298 hw->losless_comp_body_size_sao =
1299 compute_losless_comp_body_size(width, height, 0);
1300 hw->losless_comp_header_size =
1301 compute_losless_comp_header_size(width, height);
1302
1303 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1304 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1305
1306 /* setup lcu_size = 16*/
1307 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1308 /*pic_width/pic_height*/
1309 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1310 (height & 0xffff) << 16 | (width & 0xffff));
1311 /* bitdepth_luma = 8*/
1312 /* bitdepth_chroma = 8*/
1313 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1314
1315#ifdef H265_LOSLESS_COMPRESS_MODE
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1317 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1318#else
1319 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1320#endif
1321 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1322 data32 &= (~0x30);
1323 data32 |= (hw->canvas_mode << 4);
1324 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1325
1326 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1327 (0x80 << 20) | (0x80 << 10) | (0xff));
1328
1329 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1330
1331 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1332 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1333 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1334 /* ipp_enable*/
1335 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1336
1337 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1338 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1339 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1340 if (dw_mode)
1341 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1342 else
1343 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1344 }
1345
1346 data32 = READ_VREG(HEVC_SAO_CTRL0);
1347 data32 &= (~0xf);
1348 data32 |= 0x4;
1349 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1350 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1351 (width & 0xffff));
1352 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1353
1354 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1355 data32 = (lcu_x_num | lcu_y_num << 16);
1356 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1357 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1358 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1359 data32 = (mc_buffer_size_u_v_h << 16);
1360 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1361
1362 data32 = READ_VREG(HEVC_SAO_CTRL1);
1363 data32 &= (~0x3000);
1364 data32 &= (~0xff0);
1365 data32 |= endian; /* Big-Endian per 64-bit */
1366
1367 if (hw->mmu_enable && dw_mode)
1368 data32 |= ((hw->canvas_mode << 12));
1369 else
1370 data32 |= ((hw->canvas_mode << 12)|2);
1371
1372 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1373
1374#ifdef H265_DW_NO_SCALE
1375 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1376 if (hw->mmu_enable && dw_mode) {
1377 data32 = READ_VREG(HEVC_SAO_CTRL5);
1378 data32 &= (~(0xff << 16));
1379 if (dw_mode == 2 ||
1380 dw_mode == 3)
1381 data32 |= (0xff<<16);
1382 else if (dw_mode == 4)
1383 data32 |= (0x33<<16);
1384 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1385 }
1386
1387
1388#endif
1389
1390
1391#ifdef H265_LOSLESS_COMPRESS_MODE
1392 data32 = READ_VREG(HEVC_SAO_CTRL5);
1393 data32 |= (1<<9); /*8-bit smem-mode*/
1394 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1395
1396 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1397 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1398 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1399#endif
1400
1401#ifdef H265_LOSLESS_COMPRESS_MODE
1402 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1403 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1404#endif
1405
1406 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1407
1408 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1409
1410 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1411 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1412 return;
1413}
1414
1415static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1416 u32 is_new_pic, u32 is_idr)
1417{
1418 hw->is_new_pic = is_new_pic;
1419 hw->is_idr_frame = is_idr;
1420 return;
1421}
1422
1423static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1424 struct StorablePicture *pic) {
1425 u32 mc_y_adr;
1426 u32 mc_u_v_adr;
1427 u32 dw_y_adr;
1428 u32 dw_u_v_adr;
1429 u32 canvas_addr;
1430 int ret;
1431 int dw_mode = hw->double_write_mode;
1432 if (hw->is_new_pic != 1)
1433 return;
1434
1435 if (hw->is_idr_frame) {
1436 /* William TBD */
1437 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1438 }
1439
1440 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1441 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1442 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1443 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1444 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1445 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1446 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1447 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1448 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1449
1450
1451 if (dw_mode) {
1452 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1453 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1454 } else {
1455 dw_y_adr = 0;
1456 dw_u_v_adr = 0;
1457 }
1458#ifdef H265_LOSLESS_COMPRESS_MODE
1459 if (dw_mode)
1460 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1461 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1462#ifdef H264_MMU
1463 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1464#else
1465 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1466 (mc_y_adr + hw->losless_comp_body_size));
1467#endif
1468#else
1469 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1470#endif
1471
1472#ifndef H265_LOSLESS_COMPRESS_MODE
1473 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1474#else
1475 if (dw_mode)
1476 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1477#endif
1478
1479#ifndef LOSLESS_COMPRESS_MODE
1480 if (dw_mode) {
1481 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1482 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1483 }
1484#else
1485 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1486 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1487#endif
1488
1489 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1490 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1491 hw->frame_mmu_map_addr);
1492 if (ret != 0) {
1493 dpb_print(DECODE_ID(hw),
1494 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1495 pic->buf_spec_num,
1496 ret);
1497 return;
1498 }
1499
1500 /*Reset SAO + Enable SAO slice_start*/
1501 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1502 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1503 WRITE_VREG(HEVC_SAO_INT_STATUS,
1504 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1505 WRITE_VREG(HEVC_SAO_INT_STATUS,
1506 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1507 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1508 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1509
1510 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1511 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1512 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1513 } else
1514 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1515 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1516 hw->frame_busy = 1;
1517 return;
1518}
1519
1520
1521static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1522 u32 buf_spec_num) {
1523 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1524 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1525 dpb_print(DECODE_ID(hw),
1526 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1527 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1528 return;
1529}
1530
1531
1532static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1533{
1534 ulong timeout = jiffies + HZ;
1535 dpb_print(DECODE_ID(hw),
1536 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1537 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1538 if (time_after(jiffies, timeout)) {
1539 dpb_print(DECODE_ID(hw),
1540 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1541 break;
1542 }
1543 }
1544 timeout = jiffies + HZ;
1545 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1546 if (time_after(jiffies, timeout)) {
1547 dpb_print(DECODE_ID(hw),
1548 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1549 break;
1550 }
1551 }
1552 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1553 hw->frame_done = 1;
1554 return;
1555}
1556
1557static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1558{
1559 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1560 if (p_H264_Dpb->mVideo.dec_picture) {
1561 release_picture(p_H264_Dpb,
1562 p_H264_Dpb->mVideo.dec_picture);
1563 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1564 p_H264_Dpb->mVideo.dec_picture = NULL;
1565 if (hw->mmu_enable)
1566 hevc_set_frame_done(hw);
1567 }
1568}
1569
1570static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1571{
1572 ulong timeout = jiffies + HZ;
1573 dpb_print(DECODE_ID(hw),
1574 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1575 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1576 if (time_after(jiffies, timeout)) {
1577 dpb_print(DECODE_ID(hw),
1578 PRINT_FLAG_MMU_DETAIL,
1579 "hevc_sao_wait_done...wait timeout!\n");
1580 break;
1581 }
1582 }
1583 timeout = jiffies + HZ;
1584 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1585 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1586 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1587 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1588 H265_ABORT_SAO_4K_SET_DONE) {
1589 if (time_after(jiffies, timeout)) {
1590 dpb_print(DECODE_ID(hw),
1591 PRINT_FLAG_MMU_DETAIL,
1592 "wait h265_abort_sao_4k_set_done timeout!\n");
1593 break;
1594 }
1595 }
1596 }
1597 amhevc_stop();
1598 hw->frame_busy = 0;
1599 hw->frame_done = 0;
1600 dpb_print(DECODE_ID(hw),
1601 PRINT_FLAG_MMU_DETAIL,
1602 "sao wait done ,hevc stop!\n");
1603 }
1604 return;
1605}
1606static void buf_spec_init(struct vdec_h264_hw_s *hw)
1607{
1608 int i;
1609 unsigned long flags;
1610 spin_lock_irqsave(&hw->bufspec_lock, flags);
1611 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1612 hw->buffer_spec[i].used = -1;
1613 hw->buffer_spec[i].canvas_pos = -1;
1614 }
1615 if (dpb_is_debug(DECODE_ID(hw),
1616 PRINT_FLAG_DUMP_BUFSPEC))
1617 dump_bufspec(hw, __func__);
1618 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1619}
1620
1621/*is active in buf management */
1622static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1623 int buf_spec_num)
1624{
1625 unsigned char ret = 0;
1626 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1627 hw->buffer_spec[buf_spec_num].used == 2 ||
1628 hw->buffer_spec[buf_spec_num].used == 3 ||
1629 hw->buffer_spec[buf_spec_num].used == 5)
1630 ret = 1;
1631 return ret;
1632}
1633
1634static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1635 int buf_spec_num)
1636{
1637 unsigned char ret = 0;
1638 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1639 hw->buffer_spec[buf_spec_num].used == 3 ||
1640 hw->buffer_spec[buf_spec_num].used == 5)
1641 ret = 1;
1642 return ret;
1643}
1644
1645static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1646{
1647 if (hw->mmu_enable) {
1648 if (hw->buffer_spec[i].alloc_header_addr)
1649 return 0;
1650 else
1651 return -1;
1652 } else {
1653
1654 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1655 int addr;
1656#ifdef VDEC_DW
1657 int orig_buf_size;
1658 orig_buf_size = buf_size;
1659 if (IS_VDEC_DW(hw) == 1)
1660 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1661 else if (IS_VDEC_DW(hw) == 2)
1662 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1663#endif
1664 if (hw->buffer_spec[i].cma_alloc_addr)
1665 return 0;
1666
1667 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1668 PAGE_ALIGN(buf_size), DRIVER_NAME,
1669 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1670 hw->buffer_spec[i].cma_alloc_addr = 0;
1671 if (hw->no_mem_count++ > 3) {
1672 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1673 hw->reset_bufmgr_flag = 1;
1674 }
1675 dpb_print(DECODE_ID(hw), 0,
1676 "%s, fail to alloc buf for bufspec%d, try later\n",
1677 __func__, i
1678 );
1679 return -1;
1680 } else {
1681 hw->no_mem_count = 0;
1682 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1683 }
1684
1685 hw->buffer_spec[i].buf_adr =
1686 hw->buffer_spec[i].cma_alloc_addr;
1687 addr = hw->buffer_spec[i].buf_adr;
1688
1689
1690 hw->buffer_spec[i].y_addr = addr;
1691 addr += hw->mb_total << 8;
1692 hw->buffer_spec[i].u_addr = addr;
1693 hw->buffer_spec[i].v_addr = addr;
1694 addr += hw->mb_total << 7;
1695
1696 hw->buffer_spec[i].canvas_config[0].phy_addr =
1697 hw->buffer_spec[i].y_addr;
1698 hw->buffer_spec[i].canvas_config[0].width =
1699 hw->mb_width << 4;
1700 hw->buffer_spec[i].canvas_config[0].height =
1701 hw->mb_height << 4;
1702 hw->buffer_spec[i].canvas_config[0].block_mode =
1703 hw->canvas_mode;
1704
1705 hw->buffer_spec[i].canvas_config[1].phy_addr =
1706 hw->buffer_spec[i].u_addr;
1707 hw->buffer_spec[i].canvas_config[1].width =
1708 hw->mb_width << 4;
1709 hw->buffer_spec[i].canvas_config[1].height =
1710 hw->mb_height << 3;
1711 hw->buffer_spec[i].canvas_config[1].block_mode =
1712 hw->canvas_mode;
1713 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1714 "%s, alloc buf for bufspec%d\n",
1715 __func__, i
1716 );
1717#ifdef VDEC_DW
1718
1719 if (!IS_VDEC_DW(hw))
1720 return 0;
1721 else if (IS_VDEC_DW(hw) == 1) {
1722 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1723 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1724 addr += hw->mb_total << 7;
1725 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1726 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1727 addr += hw->mb_total << 6;
1728
1729 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1730 hw->buffer_spec[i].vdec_dw_y_addr;
1731 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1732 hw->mb_width << 3;
1733 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1734 hw->mb_height << 4;
1735 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1736 CANVAS_BLKMODE_32X32;
1737
1738 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1739 hw->buffer_spec[i].vdec_dw_u_addr;
1740 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1741 hw->mb_width << 3;
1742 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1743 hw->mb_height << 3;
1744 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1745 CANVAS_BLKMODE_32X32;
1746 }else {
1747 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1748 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1749 addr += hw->mb_total << 6;
1750 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1751 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1752 addr += hw->mb_total << 5;
1753
1754 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1755 hw->buffer_spec[i].vdec_dw_y_addr;
1756 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1757 hw->mb_width << 3;
1758 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1759 hw->mb_height << 3;
1760 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1761 CANVAS_BLKMODE_32X32;
1762
1763 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1764 hw->buffer_spec[i].vdec_dw_u_addr;
1765 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1766 hw->mb_width << 3;
1767 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1768 hw->mb_height << 2;
1769 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1770 CANVAS_BLKMODE_32X32;
1771 }
1772 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1773 "%s, vdec_dw: alloc buf for bufspec%d\n",
1774 __func__, i
1775 );
1776#endif
1777 }
1778 return 0;
1779}
1780
1781static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1782{
1783 int ret = 0;
1784 struct aml_vcodec_ctx *ctx = NULL;
1785 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1786 struct canvas_config_s *y_canvas_cfg = NULL;
1787 struct canvas_config_s *c_canvas_cfg = NULL;
1788 struct vdec_v4l2_buffer *fb = NULL;
1789 unsigned int y_addr = 0, c_addr = 0;
1790
1791 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1792 pr_err("the v4l context has err.\n");
1793 return -1;
1794 }
1795
1796 if (bs->cma_alloc_addr)
1797 return 0;
1798
1799 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1800 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1801 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1802 ctx->id, __func__,
1803 (hw->mb_total << 8) + (hw->mb_total << 7));
1804
1805 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1806 if (ret < 0) {
1807 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1808 "[%d] get fb fail.\n", ctx->id);
1809 return ret;
1810 }
1811
1812 bs->cma_alloc_addr = (unsigned long)fb;
1813 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1814 "[%d] %s(), cma alloc addr: 0x%x\n",
1815 ctx->id, __func__, bs->cma_alloc_addr);
1816
1817 if (fb->num_planes == 1) {
1818 y_addr = fb->m.mem[0].addr;
1819 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1820 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1821 } else if (fb->num_planes == 2) {
1822 y_addr = fb->m.mem[0].addr;
1823 c_addr = fb->m.mem[1].addr;
1824 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1825 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1826 }
1827
1828 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1829 "[%d] %s(), y_addr: %x, size: %u\n",
1830 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1831 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1832 "[%d] %s(), c_addr: %x, size: %u\n",
1833 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1834
1835 bs->y_addr = y_addr;
1836 bs->u_addr = c_addr;
1837 bs->v_addr = c_addr;
1838
1839 y_canvas_cfg = &bs->canvas_config[0];
1840 c_canvas_cfg = &bs->canvas_config[1];
1841
1842 y_canvas_cfg->phy_addr = y_addr;
1843 y_canvas_cfg->width = hw->mb_width << 4;
1844 y_canvas_cfg->height = hw->mb_height << 4;
1845 y_canvas_cfg->block_mode = hw->canvas_mode;
1846 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1847 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1848 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1849 y_canvas_cfg->width,y_canvas_cfg->height);
1850
1851 c_canvas_cfg->phy_addr = c_addr;
1852 c_canvas_cfg->width = hw->mb_width << 4;
1853 c_canvas_cfg->height = hw->mb_height << 3;
1854 c_canvas_cfg->block_mode = hw->canvas_mode;
1855 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1856 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1857 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1858 c_canvas_cfg->width, c_canvas_cfg->height);
1859
1860 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1861 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1862
1863 return ret;
1864}
1865
1866static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1867{
1868 int blkmode = hw->canvas_mode;
1869 int endian = 0;
1870
1871 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1872 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1873 endian = 7;
1874 else
1875 endian = 0;
1876 }
1877
1878 if (hw->is_used_v4l)
1879 endian = 7;
1880
1881 canvas_config_ex(hw->buffer_spec[i].
1882 y_canvas_index,
1883 hw->buffer_spec[i].y_addr,
1884 hw->mb_width << 4,
1885 hw->mb_height << 4,
1886 CANVAS_ADDR_NOWRAP,
1887 blkmode,
1888 endian);
1889
1890 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1891 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1892 (1 << 11) | /* canvas_blk32_wr */
1893 (blkmode << 10) | /* canvas_blk32*/
1894 (1 << 8) | /* canvas_index_wr*/
1895 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1896 );
1897 }
1898
1899 canvas_config_ex(hw->buffer_spec[i].
1900 u_canvas_index,
1901 hw->buffer_spec[i].u_addr,
1902 hw->mb_width << 4,
1903 hw->mb_height << 3,
1904 CANVAS_ADDR_NOWRAP,
1905 blkmode,
1906 endian);
1907
1908 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1909 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1910 (1 << 11) |
1911 (blkmode << 10) |
1912 (1 << 8) |
1913 (hw->buffer_spec[i].u_canvas_index << 0));
1914 }
1915
1916 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1917 spec2canvas(&hw->buffer_spec[i]));
1918
1919
1920#ifdef VDEC_DW
1921 if (!IS_VDEC_DW(hw))
1922 return;
1923 else if (IS_VDEC_DW(hw) == 1) {
1924 canvas_config_ex(hw->buffer_spec[i].
1925 vdec_dw_y_canvas_index,
1926 hw->buffer_spec[i].vdec_dw_y_addr,
1927 hw->mb_width << 3,
1928 hw->mb_height << 4,
1929 CANVAS_ADDR_NOWRAP,
1930 blkmode,
1931 endian);
1932 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1933 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1934 (1 << 11) |
1935 (blkmode << 10) |
1936 (1 << 8) |
1937 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1938 }
1939 canvas_config_ex(hw->buffer_spec[i].
1940 vdec_dw_u_canvas_index,
1941 hw->buffer_spec[i].vdec_dw_u_addr,
1942 hw->mb_width << 3,
1943 hw->mb_height << 3,
1944 CANVAS_ADDR_NOWRAP,
1945 blkmode,
1946 endian);
1947 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1948 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1949 (1 << 11) |
1950 (blkmode << 10) |
1951 (1 << 8) |
1952 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1953 }
1954 } else {
1955 canvas_config_ex(hw->buffer_spec[i].
1956 vdec_dw_y_canvas_index,
1957 hw->buffer_spec[i].vdec_dw_y_addr,
1958 hw->mb_width << 3,
1959 hw->mb_height << 3,
1960 CANVAS_ADDR_NOWRAP,
1961 blkmode,
1962 endian);
1963 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1964 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1965 (1 << 11) |
1966 (blkmode << 10) |
1967 (1 << 8) |
1968 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1969 }
1970
1971 canvas_config_ex(hw->buffer_spec[i].
1972 vdec_dw_u_canvas_index,
1973 hw->buffer_spec[i].vdec_dw_u_addr,
1974 hw->mb_width << 3,
1975 hw->mb_height << 2,
1976 CANVAS_ADDR_NOWRAP,
1977 blkmode,
1978 endian);
1979 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1980 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1981 (1 << 11) |
1982 (blkmode << 10) |
1983 (1 << 8) |
1984 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1985 }
1986 }
1987#endif
1988}
1989
1990static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1991{
1992 u32 blkmode = hw->canvas_mode;
1993 int canvas_w;
1994 int canvas_h;
1995
1996 canvas_w = hw->frame_width /
1997 get_double_write_ratio(hw);
1998 canvas_h = hw->frame_height /
1999 get_double_write_ratio(hw);
2000
2001 if (hw->canvas_mode == 0)
2002 canvas_w = ALIGN(canvas_w, 32);
2003 else
2004 canvas_w = ALIGN(canvas_w, 64);
2005 canvas_h = ALIGN(canvas_h, 32);
2006
2007 canvas_config_ex(hw->buffer_spec[i].
2008 y_canvas_index,
2009 hw->buffer_spec[i].dw_y_adr,
2010 canvas_w,
2011 canvas_h,
2012 CANVAS_ADDR_NOWRAP,
2013 blkmode,
2014 7);
2015
2016 canvas_config_ex(hw->buffer_spec[i].
2017 u_canvas_index,
2018 hw->buffer_spec[i].dw_u_v_adr,
2019 canvas_w,
2020 canvas_h,
2021 CANVAS_ADDR_NOWRAP,
2022 blkmode,
2023 7);
2024}
2025
2026
2027int get_free_buf_idx(struct vdec_s *vdec)
2028{
2029 int i;
2030 unsigned long addr, flags;
2031 int index = -1;
2032 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2033 int buf_total = BUFSPEC_POOL_SIZE;
2034
2035 if (hw->is_used_v4l)
2036 buf_total = hw->dpb.mDPB.size;
2037
2038 spin_lock_irqsave(&hw->bufspec_lock, flags);
2039 /*hw->start_search_pos = 0;*/
2040 for (i = hw->start_search_pos; i < buf_total; i++) {
2041 if (hw->mmu_enable)
2042 addr = hw->buffer_spec[i].alloc_header_addr;
2043 else {
2044 addr = hw->buffer_spec[i].cma_alloc_addr;
2045 if (hw->is_used_v4l && !addr) {
2046 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2047 config_decode_canvas(hw, i);
2048 addr = hw->buffer_spec[i].cma_alloc_addr;
2049 }
2050 }
2051 }
2052 if (hw->buffer_spec[i].used == 0 && addr) {
2053 hw->buffer_spec[i].used = 1;
2054 hw->start_search_pos = i+1;
2055 index = i;
2056 break;
2057 }
2058 }
2059 if (index < 0) {
2060 for (i = 0; i < hw->start_search_pos; i++) {
2061 if (hw->mmu_enable)
2062 addr = hw->buffer_spec[i].alloc_header_addr;
2063 else {
2064 addr = hw->buffer_spec[i].cma_alloc_addr;
2065 if (hw->is_used_v4l && !addr) {
2066 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2067 config_decode_canvas(hw, i);
2068 addr = hw->buffer_spec[i].cma_alloc_addr;
2069 }
2070 }
2071 }
2072 if (hw->buffer_spec[i].used == 0 && addr) {
2073 hw->buffer_spec[i].used = 1;
2074 hw->start_search_pos = i+1;
2075 index = i;
2076 break;
2077 }
2078 }
2079 }
2080 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2081 if (hw->start_search_pos >= buf_total)
2082 hw->start_search_pos = 0;
2083 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2084 "%s, buf_spec_num %d\n", __func__, index);
2085
2086 if (index < 0) {
2087 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2088 "%s fail\n", __func__);
2089 vmh264_dump_state(vdec);
2090 }
2091
2092 if (dpb_is_debug(DECODE_ID(hw),
2093 PRINT_FLAG_DUMP_BUFSPEC))
2094 dump_bufspec(hw, __func__);
2095 return index;
2096}
2097
2098int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2099{
2100 /*u32 cur_buf_idx;*/
2101 unsigned long flags;
2102 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2103 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2104 "%s buf_spec_num %d used %d\n",
2105 __func__, buf_spec_num,
2106 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2107 if (buf_spec_num >= 0 &&
2108 buf_spec_num < BUFSPEC_POOL_SIZE
2109 ) {
2110 spin_lock_irqsave(&hw->bufspec_lock, flags);
2111 hw->buffer_spec[buf_spec_num].used = 0;
2112 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2113 if (hw->mmu_enable) {
2114 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2115 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2116 cur_buf_idx = cur_buf_idx&0xff;*/
2117 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2118 }
2119 release_aux_data(hw, buf_spec_num);
2120 }
2121 if (dpb_is_debug(DECODE_ID(hw),
2122 PRINT_FLAG_DUMP_BUFSPEC))
2123 dump_bufspec(hw, __func__);
2124 return 0;
2125}
2126
2127static void config_buf_specs(struct vdec_s *vdec)
2128{
2129 int i, j;
2130 unsigned long flags;
2131 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2132 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2133
2134 spin_lock_irqsave(&hw->bufspec_lock, flags);
2135 for (i = 0, j = 0;
2136 j < hw->dpb.mDPB.size
2137 && i < BUFSPEC_POOL_SIZE;
2138 i++) {
2139 int canvas;
2140 if (hw->buffer_spec[i].used != -1)
2141 continue;
2142 if (vdec->parallel_dec == 1) {
2143 if (hw->buffer_spec[i].y_canvas_index == -1)
2144 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2145 if (hw->buffer_spec[i].u_canvas_index == -1) {
2146 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2147 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2148 }
2149#ifdef VDEC_DW
2150 if (IS_VDEC_DW(hw)) {
2151 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2152 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2153 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2154 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2155 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2156 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2157 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2158 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2159 }
2160 }
2161#endif
2162 } else {
2163 canvas = vdec->get_canvas(j * mode, 2);
2164 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2165 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2166 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2167 dpb_print(DECODE_ID(hw),
2168 PRINT_FLAG_DPB_DETAIL,
2169 "config canvas (%d) %x for bufspec %d\r\n",
2170 j, canvas, i);
2171#ifdef VDEC_DW
2172 if (IS_VDEC_DW(hw)) {
2173 canvas = vdec->get_canvas(j * mode + 1, 2);
2174 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2175 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2176 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2177 dpb_print(DECODE_ID(hw),
2178 PRINT_FLAG_DPB_DETAIL,
2179 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2180 j, canvas, i);
2181 }
2182#endif
2183 }
2184
2185 hw->buffer_spec[i].used = 0;
2186 hw->buffer_spec[i].canvas_pos = j;
2187
2188
2189 j++;
2190 }
2191 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2192}
2193
2194static void config_buf_specs_ex(struct vdec_s *vdec)
2195{
2196 int i, j;
2197 unsigned long flags;
2198 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2199 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2200
2201 spin_lock_irqsave(&hw->bufspec_lock, flags);
2202 for (i = 0, j = 0;
2203 j < hw->dpb.mDPB.size
2204 && i < BUFSPEC_POOL_SIZE;
2205 i++) {
2206 int canvas = 0;
2207 if (hw->buffer_spec[i].used != -1)
2208 continue;
2209 if (vdec->parallel_dec == 1) {
2210 if (hw->buffer_spec[i].y_canvas_index == -1)
2211 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2212 if (hw->buffer_spec[i].u_canvas_index == -1) {
2213 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2214 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2215 }
2216#ifdef VDEC_DW
2217 if (IS_VDEC_DW(hw)) {
2218 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2219 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2220 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2221 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2222 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2223 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2224 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2225 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2226 }
2227 }
2228#endif
2229 } else {
2230 canvas = vdec->get_canvas(j* mode, 2);
2231 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2232 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2233 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2234
2235 dpb_print(DECODE_ID(hw),
2236 PRINT_FLAG_DPB_DETAIL,
2237 "config canvas (%d) %x for bufspec %d\r\n",
2238 j, canvas, i);
2239#ifdef VDEC_DW
2240 if (IS_VDEC_DW(hw)) {
2241 canvas = vdec->get_canvas(j*mode + 1, 2);
2242 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2243 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2244 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2245 dpb_print(DECODE_ID(hw),
2246 PRINT_FLAG_DPB_DETAIL,
2247 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2248 j, canvas, i);
2249 }
2250#endif
2251 }
2252
2253 hw->buffer_spec[i].used = 0;
2254 hw->buffer_spec[i].alloc_header_addr = 0;
2255 hw->buffer_spec[i].canvas_pos = j;
2256
2257 j++;
2258 }
2259 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2260}
2261
2262
2263static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2264 unsigned char release_all)
2265{
2266 int i;
2267 unsigned long flags;
2268 unsigned char dealloc_flag = 0;
2269 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2270 if (hw->buffer_spec[i].used == 4 ||
2271 release_all) {
2272 dealloc_flag = 1;
2273 dpb_print(DECODE_ID(hw),
2274 PRINT_FLAG_DPB_DETAIL,
2275 "%s buf_spec_num %d\n",
2276 __func__, i
2277 );
2278 spin_lock_irqsave
2279 (&hw->bufspec_lock, flags);
2280 hw->buffer_spec[i].used = -1;
2281 spin_unlock_irqrestore
2282 (&hw->bufspec_lock, flags);
2283 release_aux_data(hw, i);
2284
2285 if (!hw->mmu_enable) {
2286 if (hw->buffer_spec[i].cma_alloc_addr) {
2287 if (!hw->is_used_v4l) {
2288 decoder_bmmu_box_free_idx(
2289 hw->bmmu_box,
2290 i);
2291 }
2292 spin_lock_irqsave
2293 (&hw->bufspec_lock, flags);
2294 hw->buffer_spec[i].cma_alloc_addr = 0;
2295 hw->buffer_spec[i].buf_adr = 0;
2296 spin_unlock_irqrestore
2297 (&hw->bufspec_lock, flags);
2298 }
2299 } else {
2300 if (hw->buffer_spec[i].alloc_header_addr) {
2301 decoder_mmu_box_free_idx(
2302 hw->mmu_box,
2303 i);
2304 spin_lock_irqsave
2305 (&hw->bufspec_lock, flags);
2306 hw->buffer_spec[i].
2307 alloc_header_addr = 0;
2308 hw->buffer_spec[i].buf_adr = 0;
2309 spin_unlock_irqrestore
2310 (&hw->bufspec_lock, flags);
2311 }
2312 }
2313 }
2314 }
2315 if (dealloc_flag &&
2316 dpb_is_debug(DECODE_ID(hw),
2317 PRINT_FLAG_DUMP_BUFSPEC))
2318 dump_bufspec(hw, __func__);
2319 return;
2320}
2321
2322unsigned char have_free_buf_spec(struct vdec_s *vdec)
2323{
2324 int i;
2325 unsigned long addr;
2326 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2327 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2328 int index = -1;
2329 int ret = 0;
2330 int allocated_count = 0;
2331 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2332 if (hw->mmu_enable)
2333 addr = hw->buffer_spec[i].alloc_header_addr;
2334 else
2335 addr = hw->buffer_spec[i].cma_alloc_addr;
2336 if (hw->buffer_spec[i].used == 0) {
2337
2338 if (addr)
2339 return 1;
2340 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2341 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2342 index = i;
2343 }
2344 }
2345 if (addr)
2346 allocated_count++;
2347 }
2348 if (index >= 0) {
2349 mutex_lock(&vmh264_mutex);
2350 dealloc_buf_specs(hw, 0);
2351 if (max_alloc_buf_count == 0 ||
2352 allocated_count < max_alloc_buf_count) {
2353 if (hw->is_used_v4l)
2354 ret = 1;
2355 else if (alloc_one_buf_spec(hw, index) >= 0)
2356 ret = 1;
2357 }
2358 mutex_unlock(&vmh264_mutex);
2359 }
2360 return ret;
2361}
2362
2363static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2364 int canvas_pos)
2365{
2366 int i;
2367 int j = 0;
2368 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2369 if (hw->buffer_spec[i].canvas_pos >= 0) {
2370 if (j == canvas_pos)
2371 return i;
2372 j++;
2373 }
2374 }
2375 return -1;
2376}
2377static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2378 struct vframe_s *vf, int index)
2379{
2380 if (index < 0) {
2381 vf->mem_handle = NULL;
2382 vf->mem_head_handle = NULL;
2383 } else if (vf->type & VIDTYPE_SCATTER) {
2384 vf->mem_handle =
2385 decoder_mmu_box_get_mem_handle(
2386 hw->mmu_box, index);
2387 vf->mem_head_handle =
2388 decoder_bmmu_box_get_mem_handle(
2389 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2390 } else {
2391 vf->mem_handle =
2392 decoder_bmmu_box_get_mem_handle(
2393 hw->bmmu_box, VF_BUFFER_IDX(index));
2394 /* vf->mem_head_handle =
2395 decoder_bmmu_box_get_mem_handle(
2396 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2397 }
2398 return;
2399}
2400static int check_force_interlace(struct vdec_h264_hw_s *hw,
2401 struct FrameStore *frame)
2402{
2403 int bForceInterlace = 0;
2404 /* no di in secure mode, disable force di */
2405 if (vdec_secure(hw_to_vdec(hw)))
2406 return 0;
2407 if (frame->frame) {
2408 if (frame->frame->coded_frame
2409 && !frame->frame->frame_mbs_only_flag) {
2410 if (frame->frame->structure == FRAME)
2411 return 1;
2412 }
2413 }
2414
2415 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2416 && hw->bitstream_restriction_flag
2417 && (hw->frame_width == 1920)
2418 && (hw->frame_height >= 1080)
2419 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2420 bForceInterlace = 1;
2421 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2422 && (hw->frame_width == 720)
2423 && (hw->frame_height == 576)
2424 && (hw->frame_dur == 3840)) {
2425 bForceInterlace = 1;
2426 }
2427
2428 return bForceInterlace;
2429}
2430
2431static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2432{
2433 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2434 if (frame->slice_type == I_SLICE)
2435 vframe_qos->type = 1;
2436 else if (frame->slice_type == P_SLICE)
2437 vframe_qos->type = 2;
2438 else if (frame->slice_type == B_SLICE)
2439 vframe_qos->type = 3;
2440
2441 vframe_qos->size = frame->frame_size;
2442 vframe_qos->pts = frame->pts64;
2443
2444 vframe_qos->max_mv = frame->max_mv;
2445 vframe_qos->avg_mv = frame->avg_mv;
2446 vframe_qos->min_mv = frame->min_mv;
2447/*
2448 pr_info("mv: max:%d, avg:%d, min:%d\n",
2449 vframe_qos->max_mv,
2450 vframe_qos->avg_mv,
2451 vframe_qos->min_mv);
2452*/
2453
2454 vframe_qos->max_qp = frame->max_qp;
2455 vframe_qos->avg_qp = frame->avg_qp;
2456 vframe_qos->min_qp = frame->min_qp;
2457/*
2458 pr_info("qp: max:%d, avg:%d, min:%d\n",
2459 vframe_qos->max_qp,
2460 vframe_qos->avg_qp,
2461 vframe_qos->min_qp);
2462*/
2463
2464 vframe_qos->max_skip = frame->max_skip;
2465 vframe_qos->avg_skip = frame->avg_skip;
2466 vframe_qos->min_skip = frame->min_skip;
2467/*
2468 pr_info("skip: max:%d, avg:%d, min:%d\n",
2469 vframe_qos->max_skip,
2470 vframe_qos->avg_skip,
2471 vframe_qos->min_skip);
2472*/
2473 vframe_qos->num++;
2474 if (hw->frameinfo_enable)
2475 vdec_fill_frame_info(vframe_qos, 1);
2476}
2477
2478static int is_iframe(struct FrameStore *frame) {
2479
2480 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2481 return 1;
2482 }
2483 return 0;
2484}
2485
2486
2487
2488int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2489{
2490 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2491 struct vframe_s *vf = NULL;
2492 int buffer_index = frame->buf_spec_num;
2493 int vf_count = 1;
2494 int i;
2495 int bForceInterlace = 0;
2496
2497 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2498 dpb_print(DECODE_ID(hw), 0,
2499 "%s, buffer_index 0x%x is beyond range\n",
2500 __func__, buffer_index);
2501 return -1;
2502 }
2503 if (force_disp_bufspec_num & 0x100) {
2504 /*recycle directly*/
2505 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2506 hw->buffer_spec[frame->buf_spec_num].used != 5)
2507 set_frame_output_flag(&hw->dpb, frame->index);
2508
2509 /*make pre_output not set*/
2510 return -1;
2511 }
2512 if (error_proc_policy & 0x1000) {
2513 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2514 int error_skip_frame_count = error_skip_count & 0xfff;
2515 if (((hw->no_error_count < error_skip_frame_count)
2516 && (error_skip_i_count == 0 ||
2517 hw->no_error_i_count < error_skip_i_count))
2518 && (!(frame->data_flag & I_FLAG)))
2519 frame->data_flag |= ERROR_FLAG;
2520 }
2521 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2522 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2523 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2524 frame->poc, hw->data_flag & ERROR_FLAG,
2525 error_proc_policy);
2526 if (frame->frame == NULL &&
2527 ((frame->is_used == 1 && frame->top_field)
2528 || (frame->is_used == 2 && frame->bottom_field))) {
2529 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2530 "%s Error frame_num %d used %d\n",
2531 __func__, frame->frame_num, frame->is_used);
2532 frame->data_flag |= ERROR_FLAG;
2533 }
2534 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2535 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2536 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2537 0, &frame->pts64) == 0)) {
2538 hw->last_pts64 = frame->pts64;
2539 hw->last_pts = frame->pts;
2540 } else {
2541 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2542 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2543 }
2544 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2545 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2546 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2547 frame->offset_delimiter, frame->pts,hw->last_pts,
2548 frame->pts64, hw->last_pts64, hw->frame_dur);
2549 hw->last_pts64 = frame->pts64;
2550 hw->last_pts = frame->pts;
2551 }
2552 if ((frame->data_flag & NODISP_FLAG) ||
2553 (frame->data_flag & NULL_FLAG) ||
2554 ((!hw->send_error_frame_flag) &&
2555 (frame->data_flag & ERROR_FLAG)) ||
2556 ((hw->i_only & 0x1) &&
2557 (!(frame->data_flag & I_FLAG)))
2558 ) {
2559 set_frame_output_flag(&hw->dpb, frame->index);
2560 return 0; /*do not return -1,
2561 otherwise flush_dpb() will not flush all dbp frames*/
2562 }
2563
2564 display_frame_count[DECODE_ID(hw)]++;
2565
2566 if (dpb_is_debug(DECODE_ID(hw),
2567 PRINT_FLAG_DPB_DETAIL)) {
2568 dpb_print(DECODE_ID(hw), 0,
2569 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2570 __func__, frame->index, frame->poc,
2571 frame->buf_spec_num);
2572 print_pic_info(DECODE_ID(hw), "predis_frm",
2573 frame->frame, -1);
2574 print_pic_info(DECODE_ID(hw), "predis_top",
2575 frame->top_field, -1);
2576 print_pic_info(DECODE_ID(hw), "predis_bot",
2577 frame->bottom_field, -1);
2578 }
2579
2580 if (!is_interlace(frame))
2581 vf_count = 1;
2582 else
2583 vf_count = 2;
2584 bForceInterlace = check_force_interlace(hw, frame);
2585 if (bForceInterlace)
2586 vf_count = 2;
2587 hw->buffer_spec[buffer_index].vf_ref = 0;
2588 fill_frame_info(hw, frame);
2589 for (i = 0; i < vf_count; i++) {
2590 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2591 vf == NULL) {
2592 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2593 "%s fatal error, no available buffer slot.\n",
2594 __func__);
2595 return -1;
2596 }
2597 vf->duration_pulldown = 0;
2598 if (!(is_iframe(frame)) && hw->unstable_pts) {
2599 vf->pts = 0;
2600 vf->pts_us64 = 0;
2601 vf->timestamp = 0;
2602 vf->index = VF_INDEX(frame->index, buffer_index);
2603 } else {
2604 vf->pts = frame->pts;
2605 vf->pts_us64 = frame->pts64;
2606 vf->timestamp = frame->timestamp;
2607 vf->index = VF_INDEX(frame->index, buffer_index);
2608 }
2609
2610 if (hw->is_used_v4l) {
2611 vf->v4l_mem_handle
2612 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2613 }
2614
2615 if (hw->mmu_enable) {
2616 if (hw->double_write_mode & 0x10) {
2617 /* double write only */
2618 vf->compBodyAddr = 0;
2619 vf->compHeadAddr = 0;
2620 } else {
2621 /*head adr*/
2622 vf->compHeadAddr =
2623 hw->buffer_spec[buffer_index].alloc_header_addr;
2624 /*body adr*/
2625 vf->compBodyAddr = 0;
2626 vf->canvas0Addr = vf->canvas1Addr = 0;
2627 }
2628
2629 vf->type = VIDTYPE_SCATTER;
2630
2631 if (hw->double_write_mode) {
2632 vf->type |= VIDTYPE_PROGRESSIVE
2633 | VIDTYPE_VIU_FIELD;
2634 vf->type |= VIDTYPE_VIU_NV21;
2635 if (hw->double_write_mode == 3)
2636 vf->type |= VIDTYPE_COMPRESS;
2637
2638 vf->canvas0Addr = vf->canvas1Addr = -1;
2639 vf->plane_num = 2;
2640 vf->canvas0_config[0] =
2641 hw->buffer_spec[buffer_index].
2642 canvas_config[0];
2643 vf->canvas0_config[1] =
2644 hw->buffer_spec[buffer_index].
2645 canvas_config[1];
2646
2647 vf->canvas1_config[0] =
2648 hw->buffer_spec[buffer_index].
2649 canvas_config[0];
2650 vf->canvas1_config[1] =
2651 hw->buffer_spec[buffer_index].
2652 canvas_config[1];
2653
2654 } else {
2655 vf->type |=
2656 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2657 vf->canvas0Addr = vf->canvas1Addr = 0;
2658 }
2659
2660 vf->bitdepth =
2661 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2662
2663 vf->compWidth = hw->frame_width;
2664 vf->compHeight = hw->frame_height;
2665 } else {
2666 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2667 VIDTYPE_VIU_NV21;
2668
2669 vf->canvas0Addr = vf->canvas1Addr =
2670 spec2canvas(&hw->buffer_spec[buffer_index]);
2671#ifdef VDEC_DW
2672 if (IS_VDEC_DW(hw))
2673 vf->canvas0Addr = vf->canvas1Addr =
2674 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2675#endif
2676
2677 }
2678 set_frame_info(hw, vf, buffer_index);
2679
2680 if (hw->mmu_enable && hw->double_write_mode) {
2681 vf->width = hw->frame_width /
2682 get_double_write_ratio(hw);
2683 vf->height = hw->frame_height /
2684 get_double_write_ratio(hw);
2685 }
2686
2687 vf->flag = 0;
2688 if (frame->data_flag & I_FLAG)
2689 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2690 if (frame->data_flag & ERROR_FLAG)
2691 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2692 update_vf_memhandle(hw, vf, buffer_index);
2693 hw->buffer_spec[buffer_index].used = 2;
2694 hw->buffer_spec[buffer_index].vf_ref++;
2695
2696 if (bForceInterlace || is_interlace(frame)) {
2697 vf->type =
2698 VIDTYPE_INTERLACE_FIRST |
2699 VIDTYPE_VIU_NV21;
2700
2701 if (bForceInterlace) {
2702 vf->type |= (i == 0 ?
2703 VIDTYPE_INTERLACE_TOP :
2704 VIDTYPE_INTERLACE_BOTTOM);
2705 if (i == 1) {
2706 vf->pts = 0;
2707 vf->pts_us64 = 0;
2708 }
2709 } else if (frame->top_field->poc <=
2710 frame->bottom_field->poc) /*top first*/
2711 vf->type |= (i == 0 ?
2712 VIDTYPE_INTERLACE_TOP :
2713 VIDTYPE_INTERLACE_BOTTOM);
2714 else
2715 vf->type |= (i == 0 ?
2716 VIDTYPE_INTERLACE_BOTTOM :
2717 VIDTYPE_INTERLACE_TOP);
2718 vf->duration = vf->duration/2;
2719 }
2720
2721 if (i == 0)
2722 decoder_do_frame_check(hw_to_vdec(hw), vf);
2723
2724 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2725 vf->sar_width = hw->width_aspect_ratio;
2726 vf->sar_height = hw->height_aspect_ratio;
2727
2728 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2729 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2730 hw->vf_pre_count++;
2731 vdec->vdec_fps_detec(vdec->id);
2732 if (without_display_mode == 0) {
2733 vf_notify_receiver(vdec->vf_provider_name,
2734 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2735 } else
2736 vh264_vf_put(vh264_vf_get(vdec), vdec);
2737 }
2738 if (dpb_is_debug(DECODE_ID(hw),
2739 PRINT_FLAG_DUMP_BUFSPEC))
2740 dump_bufspec(hw, __func__);
2741
2742 return 0;
2743}
2744
2745int notify_v4l_eos(struct vdec_s *vdec)
2746{
2747 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2748 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2749 struct vframe_s *vf = &hw->vframe_dummy;
2750 struct vdec_v4l2_buffer *fb = NULL;
2751 int index = INVALID_IDX;
2752 ulong expires;
2753
2754 if (hw->is_used_v4l && hw->eos) {
2755 expires = jiffies + msecs_to_jiffies(2000);
2756 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2757 if (time_after(jiffies, expires))
2758 break;
2759 }
2760
2761 if (index == INVALID_IDX) {
2762 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2763 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2764 return -1;
2765 }
2766 }
2767
2768 vf->type |= VIDTYPE_V4L_EOS;
2769 vf->timestamp = ULONG_MAX;
2770 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2771 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2772 hw->buffer_spec[index].cma_alloc_addr;
2773
2774 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2775
2776 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2777 vf_notify_receiver(vdec->vf_provider_name,
2778 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2779
2780 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2781 }
2782
2783 return 0;
2784}
2785
2786/******************
2787 * Hardware config
2788 */
2789char *slice_type_name[] = {
2790 "P_SLICE ",
2791 "B_SLICE ",
2792 "I_SLICE ",
2793 "SP_SLICE",
2794 "SI_SLICE",
2795};
2796
2797char *picture_structure_name[] = {
2798 "FRAME",
2799 "TOP_FIELD",
2800 "BOTTOM_FIELD"
2801};
2802
2803void print_pic_info(int decindex, const char *info,
2804 struct StorablePicture *pic,
2805 int slice_type)
2806{
2807 if (pic)
2808 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2809 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2810 info,
2811 picture_structure_name[pic->structure],
2812 pic->coded_frame ? "Frame" : "Field",
2813 (slice_type < 0 ||
2814 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2815 pic->mb_aff_frame_flag,
2816 pic->poc,
2817 pic->pic_num,
2818 pic->buf_spec_num,
2819 pic->data_flag);
2820}
2821
2822static void reset_process_time(struct vdec_h264_hw_s *hw)
2823{
2824 if (hw->start_process_time) {
2825 unsigned process_time =
2826 1000 * (jiffies - hw->start_process_time) / HZ;
2827 hw->start_process_time = 0;
2828 if (process_time > max_process_time[DECODE_ID(hw)])
2829 max_process_time[DECODE_ID(hw)] = process_time;
2830 }
2831}
2832
2833static void start_process_time(struct vdec_h264_hw_s *hw)
2834{
2835 hw->decode_timeout_count = 10;
2836 hw->start_process_time = jiffies;
2837}
2838
2839static void config_aux_buf(struct vdec_h264_hw_s *hw)
2840{
2841 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2842 WRITE_VREG(H264_AUX_DATA_SIZE,
2843 ((hw->prefix_aux_size >> 4) << 16) |
2844 (hw->suffix_aux_size >> 4)
2845 );
2846}
2847
2848/*
2849* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2850*/
2851static void set_aux_data(struct vdec_h264_hw_s *hw,
2852 struct StorablePicture *pic, unsigned char suffix_flag,
2853 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2854{
2855 int i;
2856 unsigned short *aux_adr;
2857 unsigned size_reg_val =
2858 READ_VREG(H264_AUX_DATA_SIZE);
2859 unsigned aux_count = 0;
2860 int aux_size = 0;
2861 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2862 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2863 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2864 return;
2865
2866 if (suffix_flag) {
2867 aux_adr = (unsigned short *)
2868 (hw_buf->aux_addr +
2869 hw_buf->prefix_aux_size);
2870 aux_count =
2871 ((size_reg_val & 0xffff) << 4)
2872 >> 1;
2873 aux_size =
2874 hw_buf->suffix_aux_size;
2875 } else {
2876 aux_adr =
2877 (unsigned short *)hw_buf->aux_addr;
2878 aux_count =
2879 ((size_reg_val >> 16) << 4)
2880 >> 1;
2881 aux_size =
2882 hw_buf->prefix_aux_size;
2883 }
2884 if (dpb_is_debug(DECODE_ID(hw),
2885 PRINT_FLAG_DPB_DETAIL)) {
2886 dpb_print(DECODE_ID(hw), 0,
2887 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2888 __func__, AUX_DATA_SIZE(pic),
2889 aux_count, suffix_flag, dv_meta_flag);
2890 }
2891 if (aux_size > 0 && aux_count > 0) {
2892 int heads_size = 0;
2893 int new_size;
2894 char *new_buf;
2895 for (i = 0; i < aux_count; i++) {
2896 unsigned char tag = aux_adr[i] >> 8;
2897 if (tag != 0 && tag != 0xff) {
2898 if (dv_meta_flag == 0)
2899 heads_size += 8;
2900 else if (dv_meta_flag == 1 && tag == 0x1)
2901 heads_size += 8;
2902 else if (dv_meta_flag == 2 && tag != 0x1)
2903 heads_size += 8;
2904 }
2905 }
2906 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2907 new_buf = krealloc(AUX_DATA_BUF(pic),
2908 new_size,
2909 GFP_KERNEL);
2910 if (new_buf) {
2911 unsigned char valid_tag = 0;
2912 unsigned char *h =
2913 new_buf +
2914 AUX_DATA_SIZE(pic);
2915 unsigned char *p = h + 8;
2916 int len = 0;
2917 int padding_len = 0;
2918 AUX_DATA_BUF(pic) = new_buf;
2919 for (i = 0; i < aux_count; i += 4) {
2920 int ii;
2921 unsigned char tag = aux_adr[i + 3] >> 8;
2922 if (tag != 0 && tag != 0xff) {
2923 if (dv_meta_flag == 0)
2924 valid_tag = 1;
2925 else if (dv_meta_flag == 1
2926 && tag == 0x1)
2927 valid_tag = 1;
2928 else if (dv_meta_flag == 2
2929 && tag != 0x1)
2930 valid_tag = 1;
2931 else
2932 valid_tag = 0;
2933 if (valid_tag && len > 0) {
2934 AUX_DATA_SIZE(pic) +=
2935 (len + 8);
2936 h[0] =
2937 (len >> 24) & 0xff;
2938 h[1] =
2939 (len >> 16) & 0xff;
2940 h[2] =
2941 (len >> 8) & 0xff;
2942 h[3] =
2943 (len >> 0) & 0xff;
2944 h[6] =
2945 (padding_len >> 8)
2946 & 0xff;
2947 h[7] =
2948 (padding_len) & 0xff;
2949 h += (len + 8);
2950 p += 8;
2951 len = 0;
2952 padding_len = 0;
2953 }
2954 if (valid_tag) {
2955 h[4] = tag;
2956 h[5] = 0;
2957 h[6] = 0;
2958 h[7] = 0;
2959 }
2960 }
2961 if (valid_tag) {
2962 for (ii = 0; ii < 4; ii++) {
2963 unsigned short aa =
2964 aux_adr[i + 3
2965 - ii];
2966 *p = aa & 0xff;
2967 p++;
2968 len++;
2969 /*if ((aa >> 8) == 0xff)
2970 padding_len++;*/
2971 }
2972 }
2973 }
2974 if (len > 0) {
2975 AUX_DATA_SIZE(pic) += (len + 8);
2976 h[0] = (len >> 24) & 0xff;
2977 h[1] = (len >> 16) & 0xff;
2978 h[2] = (len >> 8) & 0xff;
2979 h[3] = (len >> 0) & 0xff;
2980 h[6] = (padding_len >> 8) & 0xff;
2981 h[7] = (padding_len) & 0xff;
2982 }
2983 if (dpb_is_debug(DECODE_ID(hw),
2984 PRINT_FLAG_DPB_DETAIL)) {
2985 dpb_print(DECODE_ID(hw), 0,
2986 "aux: (size %d) suffix_flag %d\n",
2987 AUX_DATA_SIZE(pic), suffix_flag);
2988 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2989 dpb_print_cont(DECODE_ID(hw), 0,
2990 "%02x ", AUX_DATA_BUF(pic)[i]);
2991 if (((i + 1) & 0xf) == 0)
2992 dpb_print_cont(
2993 DECODE_ID(hw),
2994 0, "\n");
2995 }
2996 dpb_print_cont(DECODE_ID(hw),
2997 0, "\n");
2998 }
2999
3000 }
3001 }
3002
3003}
3004
3005static void release_aux_data(struct vdec_h264_hw_s *hw,
3006 int buf_spec_num)
3007{
3008 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3009 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3010 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3011}
3012
3013static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3014{
3015 int i;
3016 unsigned short *aux_adr =
3017 (unsigned short *)
3018 hw->aux_addr;
3019 unsigned aux_size =
3020 (READ_VREG(H264_AUX_DATA_SIZE)
3021 >> 16) << 4;
3022
3023 if (hw->prefix_aux_size > 0) {
3024 dpb_print(DECODE_ID(hw),
3025 0,
3026 "prefix aux: (size %d)\n",
3027 aux_size);
3028 for (i = 0; i <
3029 (aux_size >> 1); i++) {
3030 dpb_print_cont(DECODE_ID(hw),
3031 0,
3032 "%04x ",
3033 *(aux_adr + i));
3034 if (((i + 1) & 0xf)
3035 == 0)
3036 dpb_print_cont(
3037 DECODE_ID(hw),
3038 0, "\n");
3039 }
3040 }
3041 if (hw->suffix_aux_size > 0) {
3042 aux_adr = (unsigned short *)
3043 (hw->aux_addr +
3044 hw->prefix_aux_size);
3045 aux_size =
3046 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3047 << 4;
3048 dpb_print(DECODE_ID(hw),
3049 0,
3050 "suffix aux: (size %d)\n",
3051 aux_size);
3052 for (i = 0; i <
3053 (aux_size >> 1); i++) {
3054 dpb_print_cont(DECODE_ID(hw),
3055 0,
3056 "%04x ", *(aux_adr + i));
3057 if (((i + 1) & 0xf) == 0)
3058 dpb_print_cont(DECODE_ID(hw),
3059 0, "\n");
3060 }
3061 }
3062}
3063
3064static void config_decode_mode(struct vdec_h264_hw_s *hw)
3065{
3066#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3067 struct vdec_s *vdec = hw_to_vdec(hw);
3068#endif
3069 if (input_frame_based(hw_to_vdec(hw)))
3070 WRITE_VREG(H264_DECODE_MODE,
3071 DECODE_MODE_MULTI_FRAMEBASE);
3072#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3073 else if (vdec->slave)
3074 WRITE_VREG(H264_DECODE_MODE,
3075 (hw->got_valid_nal << 8) |
3076 DECODE_MODE_MULTI_DVBAL);
3077 else if (vdec->master)
3078 WRITE_VREG(H264_DECODE_MODE,
3079 (hw->got_valid_nal << 8) |
3080 DECODE_MODE_MULTI_DVENL);
3081#endif
3082 else
3083 WRITE_VREG(H264_DECODE_MODE,
3084 DECODE_MODE_MULTI_STREAMBASE);
3085 WRITE_VREG(H264_DECODE_SEQINFO,
3086 hw->seq_info2);
3087 WRITE_VREG(HEAD_PADING_REG, 0);
3088
3089 if (hw->init_flag == 0)
3090 WRITE_VREG(INIT_FLAG_REG, 0);
3091 else
3092 WRITE_VREG(INIT_FLAG_REG, 1);
3093}
3094int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3095{
3096 /* static int count = 0; */
3097 int ret = 0;
3098 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3099 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3100 unsigned int colocate_adr_offset;
3101 unsigned int val;
3102 struct StorablePicture *last_pic = hw->last_dec_picture;
3103
3104#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3105 int colocate_buf_index;
3106#endif
3107#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3108#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3109#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3110#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3111
3112#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3113/* bit 31:30 -- L1[0] picture coding structure,
3114 * 00 - top field, 01 - bottom field,
3115 * 10 - frame, 11 - mbaff frame
3116 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3117 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3118 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3119 */
3120#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3121
3122/* bit 15 -- flush co_mb_data to DDR -- W-Only
3123 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3124 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3125 * bit 9 -- soft_reset -- W-Only
3126 * bit 8 -- upgent
3127 * bit 7:2 -- h264_co_mb_mem_wr_addr
3128 * bit 1:0 -- h264_co_mb_info_wr_ptr
3129 */
3130#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3131
3132 unsigned long canvas_adr;
3133 unsigned int ref_reg_val;
3134 unsigned int one_ref_cfg = 0;
3135 int h264_buffer_info_data_write_count;
3136 int i, j;
3137 unsigned int colocate_wr_adr;
3138 unsigned int colocate_rd_adr;
3139 unsigned char use_direct_8x8;
3140 int canvas_pos;
3141 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3142 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3143 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3144 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3145 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3146
3147 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3148 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3149 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3150 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3151 canvas_pos);
3152 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3153
3154#ifdef VDEC_DW
3155 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3156 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3157 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3158#endif
3159 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3160 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3161
3162 if (!hw->mmu_enable) {
3163 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3164 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3165 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3166#ifdef VDEC_DW
3167 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3168 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3169 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3170#endif
3171 } else
3172 hevc_sao_set_pic_buffer(hw, pic);
3173
3174 if (pic->mb_aff_frame_flag)
3175 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3176 else if (pic->structure == TOP_FIELD)
3177 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3178 else if (pic->structure == BOTTOM_FIELD)
3179 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3180 else
3181 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3182
3183 if (pic->bottom_poc < pic->top_poc)
3184 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3185
3186 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3187 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3188 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3189
3190 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3191 int long_term_flag;
3192 i = get_buf_spec_by_canvas_pos(hw, j);
3193 if (i < 0)
3194 break;
3195 long_term_flag =
3196 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3197 if (long_term_flag > 0) {
3198 if (long_term_flag & 0x1)
3199 hw->buffer_spec[i].info0 |= (1 << 4);
3200 else
3201 hw->buffer_spec[i].info0 &= ~(1 << 4);
3202
3203 if (long_term_flag & 0x2)
3204 hw->buffer_spec[i].info0 |= (1 << 5);
3205 else
3206 hw->buffer_spec[i].info0 &= ~(1 << 5);
3207 }
3208
3209 if (i == pic->buf_spec_num)
3210 WRITE_VREG(H264_BUFFER_INFO_DATA,
3211 hw->buffer_spec[i].info0 | 0xf);
3212 else
3213 WRITE_VREG(H264_BUFFER_INFO_DATA,
3214 hw->buffer_spec[i].info0);
3215 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3216 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3217 }
3218
3219 /* config reference buffer */
3220 if (hw->mmu_enable) {
3221 hevc_mcr_config_mc_ref(hw);
3222 hevc_mcr_config_mcrcc(hw);
3223 }
3224
3225 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3226 "list0 size %d\n", pSlice->listXsize[0]);
3227 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3228 ref_reg_val = 0;
3229 j = 0;
3230 h264_buffer_info_data_write_count = 0;
3231
3232 //disable this read cache when frame width <= 64 (4MBs)
3233 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3234 if (hw->frame_width <= 64)
3235 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3236 else
3237 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3238
3239 if (last_pic)
3240 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3241 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3242 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3243 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3244 last_pic && (last_pic->data_flag & ERROR_FLAG)
3245 && (!(last_pic->slice_type == B_SLICE))
3246 && (!(pSlice->slice_type == I_SLICE))) {
3247 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3248 "no i/idr error mark\n");
3249 hw->data_flag |= ERROR_FLAG;
3250 pic->data_flag |= ERROR_FLAG;
3251 }
3252
3253 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3254 /*ref list 0 */
3255 struct StorablePicture *ref = pSlice->listX[0][i];
3256 unsigned int cfg;
3257 /* bit[6:5] - frame/field info,
3258 * 01 - top, 10 - bottom, 11 - frame
3259 */
3260 #ifdef ERROR_CHECK
3261 if (ref == NULL) {
3262 hw->data_flag |= ERROR_FLAG;
3263 pic->data_flag |= ERROR_FLAG;
3264 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3265 return -1;
3266 }
3267 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3268 hw->data_flag |= ERROR_FLAG;
3269 pic->data_flag |= ERROR_FLAG;
3270 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3271 }
3272 if (ref->data_flag & NULL_FLAG)
3273 hw->data_flag |= NULL_FLAG;
3274#endif
3275 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3276
3277 if (ref->structure == TOP_FIELD)
3278 cfg = 0x1;
3279 else if (ref->structure == BOTTOM_FIELD)
3280 cfg = 0x2;
3281 else /* FRAME */
3282 cfg = 0x3;
3283
3284 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3285 ref_reg_val <<= 8;
3286 ref_reg_val |= one_ref_cfg;
3287 j++;
3288
3289 if (j == 4) {
3290 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3291 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3292 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3293 h264_buffer_info_data_write_count++;
3294 j = 0;
3295 }
3296 print_pic_info(DECODE_ID(hw), "list0",
3297 pSlice->listX[0][i], -1);
3298 }
3299 if (j != 0) {
3300 while (j != 4) {
3301 ref_reg_val <<= 8;
3302 ref_reg_val |= one_ref_cfg;
3303 j++;
3304 }
3305 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3306 "H264_BUFFER_INFO_DATA: %x\n",
3307 ref_reg_val);
3308 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3309 h264_buffer_info_data_write_count++;
3310 }
3311 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3312 (one_ref_cfg << 8) | one_ref_cfg;
3313 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3314 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3315
3316 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3317 "list1 size %d\n", pSlice->listXsize[1]);
3318 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3319 ref_reg_val = 0;
3320 j = 0;
3321
3322 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3323 /* ref list 0 */
3324 struct StorablePicture *ref = pSlice->listX[1][i];
3325 unsigned int cfg;
3326 /* bit[6:5] - frame/field info,
3327 * 01 - top, 10 - bottom, 11 - frame
3328 */
3329
3330 #ifdef ERROR_CHECK
3331 if (ref == NULL) {
3332 hw->data_flag |= ERROR_FLAG;
3333 pic->data_flag |= ERROR_FLAG;
3334 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3335 return -2;
3336 }
3337 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3338 pic->data_flag |= ERROR_FLAG;
3339 hw->data_flag |= ERROR_FLAG;
3340 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3341 }
3342 if (ref->data_flag & NULL_FLAG)
3343 hw->data_flag |= NULL_FLAG;
3344#endif
3345 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3346 if (ref->structure == TOP_FIELD)
3347 cfg = 0x1;
3348 else if (ref->structure == BOTTOM_FIELD)
3349 cfg = 0x2;
3350 else /* FRAME */
3351 cfg = 0x3;
3352 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3353 ref_reg_val <<= 8;
3354 ref_reg_val |= one_ref_cfg;
3355 j++;
3356
3357 if (j == 4) {
3358 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3359 "H264_BUFFER_INFO_DATA: %x\n",
3360 ref_reg_val);
3361 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3362 j = 0;
3363 }
3364 print_pic_info(DECODE_ID(hw), "list1",
3365 pSlice->listX[1][i], -1);
3366 }
3367 if (j != 0) {
3368 while (j != 4) {
3369 ref_reg_val <<= 8;
3370 ref_reg_val |= one_ref_cfg;
3371 j++;
3372 }
3373 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3374 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3375 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3376 }
3377
3378 /* configure co-locate buffer */
3379 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3380 ;
3381 if ((pSlice->mode_8x8_flags & 0x4) &&
3382 (pSlice->mode_8x8_flags & 0x2))
3383 use_direct_8x8 = 1;
3384 else
3385 use_direct_8x8 = 0;
3386
3387#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3388 colocate_adr_offset =
3389 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3390 ? 1 : 2) * 96;
3391 if (use_direct_8x8)
3392 colocate_adr_offset >>= 2;
3393
3394 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3395 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3396 colocate_adr_offset, pSlice->first_mb_in_slice,
3397 colocate_adr_offset * pSlice->first_mb_in_slice);
3398
3399 colocate_adr_offset *= pSlice->first_mb_in_slice;
3400
3401 if ((pic->colocated_buf_index >= 0) &&
3402 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3403 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3404 ((p_H264_Dpb->colocated_buf_size *
3405 pic->colocated_buf_index)
3406 >> (use_direct_8x8 ? 2 : 0));
3407 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3408 p_H264_Dpb->colocated_mv_addr_end) {
3409 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3410 "Error, colocate buf is not enough, index is %d\n",
3411 pic->colocated_buf_index);
3412 ret = -3;
3413 }
3414 val = colocate_wr_adr + colocate_adr_offset;
3415 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3416 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3417 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3418 val, pSlice->first_mb_in_slice, pic->structure,
3419 colocate_adr_offset, pSlice->mode_8x8_flags,
3420 p_H264_Dpb->colocated_buf_size);
3421 } else {
3422 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3423 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3424 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3425 }
3426#else
3427 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3428 colocate_adr_offset =
3429 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3430 if (use_direct_8x8)
3431 colocate_adr_offset >>= 2;
3432
3433 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3434 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3435 colocate_adr_offset, pSlice->first_mb_in_slice,
3436 colocate_adr_offset * pSlice->first_mb_in_slice);
3437
3438 colocate_adr_offset *= pSlice->first_mb_in_slice;
3439
3440 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3441 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3442 (use_direct_8x8 ? 2 : 0));
3443
3444 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3445 p_H264_Dpb->colocated_mv_addr_end) {
3446 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3447 "Error, colocate buf is not enough, col buf index is %d\n",
3448 colocate_buf_index);
3449 ret = -4;
3450 }
3451 val = colocate_wr_adr + colocate_adr_offset;
3452 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3453 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3454 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3455 val, pSlice->first_mb_in_slice, pic->structure,
3456 colocate_adr_offset, pSlice->mode_8x8_flags,
3457 p_H264_Dpb->colocated_buf_size);
3458#endif
3459 if (pSlice->listXsize[1] > 0) {
3460 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3461 /* H264_CO_MB_RD_ADDR[bit 31:30],
3462 * original picture structure of L1[0],
3463 * 00 - top field, 01 - bottom field,
3464 * 10 - frame, 11 - mbaff frame
3465 */
3466 int l10_structure;
3467 int cur_colocate_ref_type;
3468 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3469 * 0 - top, 1 - bot
3470 */
3471 unsigned int val;
3472#ifdef ERROR_CHECK
3473 if (colocate_pic == NULL) {
3474 hw->data_flag |= ERROR_FLAG;
3475 pic->data_flag |= ERROR_FLAG;
3476 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3477 return -5;
3478 }
3479 if (colocate_pic->data_flag & ERROR_FLAG) {
3480 pic->data_flag |= ERROR_FLAG;
3481 hw->data_flag |= ERROR_FLAG;
3482 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3483 }
3484 if (colocate_pic->data_flag & NULL_FLAG)
3485 hw->data_flag |= NULL_FLAG;
3486#endif
3487
3488 if (colocate_pic->mb_aff_frame_flag)
3489 l10_structure = 3;
3490 else {
3491 if (colocate_pic->coded_frame)
3492 l10_structure = 2;
3493 else
3494 l10_structure = (colocate_pic->structure ==
3495 BOTTOM_FIELD) ? 1 : 0;
3496 }
3497#if 0
3498 /*case0016, p16,
3499 *cur_colocate_ref_type should be configured base on current pic
3500 */
3501 if (pic->structure == FRAME &&
3502 pic->mb_aff_frame_flag)
3503 cur_colocate_ref_type = 0;
3504 else if (pic->structure == BOTTOM_FIELD)
3505 cur_colocate_ref_type = 1;
3506 else
3507 cur_colocate_ref_type = 0;
3508#else
3509 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3510 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3511 pic->mb_aff_frame_flag,
3512 pic->structure,
3513 pic->coded_frame);
3514 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3515 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3516 colocate_pic->mb_aff_frame_flag,
3517 colocate_pic->structure,
3518 colocate_pic->coded_frame);
3519 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3520 cur_colocate_ref_type =
3521 (abs(pic->poc - colocate_pic->top_poc)
3522 < abs(pic->poc -
3523 colocate_pic->bottom_poc)) ? 0 : 1;
3524 } else
3525 cur_colocate_ref_type =
3526 (colocate_pic->structure
3527 == BOTTOM_FIELD) ? 1 : 0;
3528#endif
3529
3530#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3531 if ((colocate_pic->colocated_buf_index >= 0) &&
3532 (colocate_pic->colocated_buf_index <
3533 p_H264_Dpb->colocated_buf_count)) {
3534 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3535 ((p_H264_Dpb->colocated_buf_size *
3536 colocate_pic->colocated_buf_index)
3537 >> (use_direct_8x8 ? 2 : 0));
3538 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3539 p_H264_Dpb->colocated_mv_addr_end) {
3540 dpb_print(DECODE_ID(hw),
3541 PRINT_FLAG_ERROR,
3542 "Error, colocate buf is not enough, index is %d\n",
3543 colocate_pic->colocated_buf_index);
3544 ret = -6;
3545 }
3546 /* bit 31:30 -- L1[0] picture coding structure,
3547 * 00 - top field, 01 - bottom field,
3548 * 10 - frame, 11 - mbaff frame
3549 * bit 29 - L1[0] top/bot for B field pciture,
3550 * 0 - top, 1 - bot
3551 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3552 * -- only used for B Picture Direct mode
3553 * [2:0] will set to 3'b000
3554 */
3555 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3556 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3557 (l10_structure << 30) |
3558 (cur_colocate_ref_type << 29);
3559 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3560 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3561 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3562 colocate_pic->colocated_buf_index,
3563 val, colocate_rd_adr + colocate_adr_offset,
3564 colocate_pic->structure,
3565 colocate_pic->mb_aff_frame_flag);
3566 } else {
3567 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3568 "Error, reference pic has no colocated buf\n");
3569 ret = -7;
3570 }
3571#else
3572 colocate_buf_index =
3573 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3574 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3575 ((p_H264_Dpb->colocated_buf_size *
3576 colocate_buf_index)
3577 >> (use_direct_8x8 ? 2 : 0));
3578 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3579 p_H264_Dpb->colocated_mv_addr_end) {
3580 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3581 "Error, colocate buf is not enough, col buf index is %d\n",
3582 colocate_buf_index);
3583 ret = -8;
3584 }
3585 /* bit 31:30 -- L1[0] picture coding structure,
3586 * 00 - top field, 01 - bottom field,
3587 * 10 - frame, 11 - mbaff frame
3588 * bit 29 - L1[0] top/bot for B field pciture,
3589 * 0 - top, 1 - bot
3590 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3591 * -- only used for B Picture Direct mode
3592 * [2:0] will set to 3'b000
3593 */
3594 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3595 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3596 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3597 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3598 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3599 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3600 val, colocate_pic->structure,
3601 colocate_pic->mb_aff_frame_flag);
3602#endif
3603 }
3604 return ret;
3605}
3606
3607static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3608{
3609 unsigned long flags;
3610 struct vdec_s *vdec = op_arg;
3611 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3612
3613 spin_lock_irqsave(&hw->lock, flags);
3614
3615 states->vf_pool_size = VF_POOL_SIZE;
3616 states->buf_free_num = kfifo_len(&hw->newframe_q);
3617 states->buf_avail_num = kfifo_len(&hw->display_q);
3618
3619 spin_unlock_irqrestore(&hw->lock, flags);
3620
3621 return 0;
3622}
3623
3624static struct vframe_s *vh264_vf_peek(void *op_arg)
3625{
3626 struct vframe_s *vf[2] = {0, 0};
3627 struct vdec_s *vdec = op_arg;
3628 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3629
3630 if (!hw)
3631 return NULL;
3632
3633 if (force_disp_bufspec_num & 0x100) {
3634 if (force_disp_bufspec_num & 0x200)
3635 return NULL;
3636 return &hw->vframe_dummy;
3637 }
3638
3639 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3640 if (vf[1]) {
3641 vf[0]->next_vf_pts_valid = true;
3642 vf[0]->next_vf_pts = vf[1]->pts;
3643 } else
3644 vf[0]->next_vf_pts_valid = false;
3645 return vf[0];
3646 }
3647
3648 return NULL;
3649}
3650
3651static struct vframe_s *vh264_vf_get(void *op_arg)
3652{
3653 struct vframe_s *vf;
3654 struct vdec_s *vdec = op_arg;
3655 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3656
3657 if (!hw)
3658 return NULL;
3659
3660 if (force_disp_bufspec_num & 0x100) {
3661 int buffer_index = force_disp_bufspec_num & 0xff;
3662 if (force_disp_bufspec_num & 0x200)
3663 return NULL;
3664
3665 vf = &hw->vframe_dummy;
3666 vf->duration_pulldown = 0;
3667 vf->pts = 0;
3668 vf->pts_us64 = 0;
3669 set_frame_info(hw, vf, buffer_index);
3670 vf->flag = 0;
3671 if (hw->mmu_enable) {
3672 if (hw->double_write_mode & 0x10) {
3673 /* double write only */
3674 vf->compBodyAddr = 0;
3675 vf->compHeadAddr = 0;
3676 } else {
3677 /*head adr*/
3678 vf->compHeadAddr =
3679 hw->buffer_spec[buffer_index].alloc_header_addr;
3680 /*body adr*/
3681 vf->compBodyAddr = 0;
3682 vf->canvas0Addr = vf->canvas1Addr = 0;
3683 }
3684
3685 vf->type = VIDTYPE_SCATTER;
3686
3687 if (hw->double_write_mode) {
3688 vf->type |= VIDTYPE_PROGRESSIVE
3689 | VIDTYPE_VIU_FIELD;
3690 vf->type |= VIDTYPE_VIU_NV21;
3691 if (hw->double_write_mode == 3)
3692 vf->type |= VIDTYPE_COMPRESS;
3693
3694 vf->canvas0Addr = vf->canvas1Addr = -1;
3695 vf->plane_num = 2;
3696 vf->canvas0_config[0] =
3697 hw->buffer_spec[buffer_index].
3698 canvas_config[0];
3699 vf->canvas0_config[1] =
3700 hw->buffer_spec[buffer_index].
3701 canvas_config[1];
3702
3703 vf->canvas1_config[0] =
3704 hw->buffer_spec[buffer_index].
3705 canvas_config[0];
3706 vf->canvas1_config[1] =
3707 hw->buffer_spec[buffer_index].
3708 canvas_config[1];
3709 } else {
3710 vf->type |=
3711 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3712 vf->canvas0Addr = vf->canvas1Addr = 0;
3713 }
3714 vf->bitdepth =
3715 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3716
3717 vf->compWidth = hw->frame_width;
3718 vf->compHeight = hw->frame_height;
3719
3720 if (hw->double_write_mode) {
3721 vf->width = hw->frame_width /
3722 get_double_write_ratio(hw);
3723 vf->height = hw->frame_height /
3724 get_double_write_ratio(hw);
3725 }
3726 } else {
3727 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3728 VIDTYPE_VIU_NV21;
3729 vf->canvas0Addr = vf->canvas1Addr =
3730 spec2canvas(&hw->buffer_spec[buffer_index]);
3731 }
3732
3733 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3734 hw->bmmu_box, buffer_index);*/
3735 update_vf_memhandle(hw, vf, buffer_index);
3736 force_disp_bufspec_num |= 0x200;
3737 return vf;
3738 }
3739
3740 if (kfifo_get(&hw->display_q, &vf)) {
3741 int time = jiffies;
3742 unsigned int frame_interval =
3743 1000*(time - hw->last_frame_time)/HZ;
3744 struct vframe_s *next_vf;
3745 if (dpb_is_debug(DECODE_ID(hw),
3746 PRINT_FLAG_VDEC_DETAIL)) {
3747 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3748 int frame_index = FRAME_INDEX(vf->index);
3749 if (frame_index < 0 ||
3750 frame_index >= DPB_SIZE_MAX) {
3751 dpb_print(DECODE_ID(hw), 0,
3752 "%s vf index 0x%x error\r\n",
3753 __func__, vf->index);
3754 } else {
3755 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3756 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3757 __func__, BUFSPEC_INDEX(vf->index), vf,
3758 p_H264_Dpb->mFrameStore[frame_index].poc,
3759 vf->duration, vf->pts, frame_interval);
3760 }
3761 }
3762 if (hw->last_frame_time > 0) {
3763 if (frame_interval >
3764 max_get_frame_interval[DECODE_ID(hw)])
3765 max_get_frame_interval[DECODE_ID(hw)]
3766 = frame_interval;
3767 }
3768 hw->last_frame_time = time;
3769 vf->index_disp = hw->vf_get_count;
3770 hw->vf_get_count++;
3771 if (kfifo_peek(&hw->display_q, &next_vf)) {
3772 vf->next_vf_pts_valid = true;
3773 vf->next_vf_pts = next_vf->pts;
3774 } else
3775 vf->next_vf_pts_valid = false;
3776 return vf;
3777 }
3778
3779 return NULL;
3780}
3781
3782static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3783{
3784 struct vdec_s *vdec = op_arg;
3785 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3786 int buf_spec_num;
3787 int frame_index;
3788
3789 if (vf == (&hw->vframe_dummy))
3790 return;
3791 if (vf->index == -1) {
3792 dpb_print(DECODE_ID(hw), 0,
3793 "Warning: %s vf %p invalid index\r\n",
3794 __func__, vf);
3795 return;
3796 }
3797 frame_index = FRAME_INDEX(vf->index);
3798 buf_spec_num = BUFSPEC_INDEX(vf->index);
3799 if (frame_index < 0 ||
3800 frame_index >= DPB_SIZE_MAX ||
3801 buf_spec_num < 0 ||
3802 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3803 dpb_print(DECODE_ID(hw), 0,
3804 "%s vf index 0x%x error\r\n",
3805 __func__, vf->index);
3806 return;
3807 }
3808 /*get_buf_spec_idx_by_canvas_config(hw,
3809 &vf->canvas0_config[0]);*/
3810 if (hw->buffer_spec[buf_spec_num].used == 2) {
3811 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3812 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3813 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3814 __func__, vf, frame_index,
3815 p_H264_Dpb->mFrameStore[frame_index].poc,
3816 buf_spec_num,
3817 hw->buffer_spec[buf_spec_num].used,
3818 hw->buffer_spec[buf_spec_num].vf_ref);
3819 hw->buffer_spec[buf_spec_num].vf_ref--;
3820 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3821 set_frame_output_flag(&hw->dpb, frame_index);
3822 } else {
3823 unsigned long flags;
3824 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3825 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3826 __func__, vf, buf_spec_num,
3827 hw->buffer_spec[buf_spec_num].used,
3828 hw->buffer_spec[buf_spec_num].vf_ref);
3829 spin_lock_irqsave(&hw->bufspec_lock, flags);
3830 hw->buffer_spec[buf_spec_num].vf_ref--;
3831 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3832 if (hw->buffer_spec[buf_spec_num].used == 3)
3833 hw->buffer_spec[buf_spec_num].used = 4;
3834 else if (hw->buffer_spec[buf_spec_num].used == 5)
3835 hw->buffer_spec[buf_spec_num].used = 0;
3836 }
3837 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3838 if (dpb_is_debug(DECODE_ID(hw),
3839 PRINT_FLAG_DUMP_BUFSPEC))
3840 dump_bufspec(hw, __func__);
3841
3842 }
3843
3844 hw->vf_put_count++;
3845 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3846
3847#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3848 if (hw->buffer_empty_flag)
3849 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3850}
3851
3852static int vh264_event_cb(int type, void *data, void *op_arg)
3853{
3854 unsigned long flags;
3855 struct vdec_s *vdec = op_arg;
3856 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3857
3858 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3859 struct provider_aux_req_s *req =
3860 (struct provider_aux_req_s *)data;
3861 int buf_spec_num;
3862
3863 if (!req->vf) {
3864 req->aux_size = hw->vf_put_count;
3865 return 0;
3866 }
3867 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3868 spin_lock_irqsave(&hw->lock, flags);
3869 req->aux_buf = NULL;
3870 req->aux_size = 0;
3871 if (buf_spec_num >= 0 &&
3872 buf_spec_num < BUFSPEC_POOL_SIZE &&
3873 is_buf_spec_in_disp_q(hw, buf_spec_num)
3874 ) {
3875 req->aux_buf =
3876 hw->buffer_spec[buf_spec_num].aux_data_buf;
3877 req->aux_size =
3878 hw->buffer_spec[buf_spec_num].aux_data_size;
3879#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3880 req->dv_enhance_exist =
3881 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3882#else
3883 req->dv_enhance_exist = 0;
3884#endif
3885 }
3886 spin_unlock_irqrestore(&hw->lock, flags);
3887
3888 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3889 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3890 __func__, type, buf_spec_num, req->aux_size);
3891 }
3892
3893 return 0;
3894}
3895
3896static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3897 u32 index)
3898{
3899 struct canvas_config_s *p_canvas_config;
3900 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3901 force_rate_framebase : force_rate_streambase;
3902 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3903 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3904 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3905
3906 /* signal_type */
3907 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3908 vf->signal_type = hw->video_signal_from_vui;
3909 if (hw->is_used_v4l) {
3910 struct aml_vdec_hdr_infos hdr;
3911 struct aml_vcodec_ctx *ctx =
3912 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3913
3914 memset(&hdr, 0, sizeof(hdr));
3915 hdr.signal_type = hw->video_signal_from_vui;
3916 vdec_v4l_set_hdr_infos(ctx, &hdr);
3917 }
3918 } else
3919 vf->signal_type = 0;
3920
3921 vf->width = hw->frame_width;
3922 vf->height = hw->frame_height;
3923 if (force_rate) {
3924 if (force_rate == -1)
3925 vf->duration = 0;
3926 else
3927 vf->duration = 96000/force_rate;
3928 } else
3929 vf->duration = hw->frame_dur;
3930 vf->ratio_control =
3931 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3932 DISP_RATIO_ASPECT_RATIO_BIT;
3933 vf->orientation = hw->vh264_rotation;
3934
3935 if (hw->mmu_enable)
3936 return;
3937
3938 vf->canvas0Addr = vf->canvas1Addr = -1;
3939#ifdef NV21
3940 vf->plane_num = 2;
3941#else
3942 vf->plane_num = 3;
3943#endif
3944
3945 if (IS_VDEC_DW(hw)) {
3946 vf->width = (hw->frame_width /2);
3947 if (IS_VDEC_DW(hw) == 2)
3948 vf->height = (hw->frame_height /2);
3949 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3950 } else
3951 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3952
3953 vf->canvas0_config[0] = p_canvas_config[0];
3954 vf->canvas0_config[1] = p_canvas_config[1];
3955#ifndef NV21
3956 vf->canvas0_config[2] = p_canvas_config[2];
3957#endif
3958 vf->canvas1_config[0] = p_canvas_config[0];
3959 vf->canvas1_config[1] = p_canvas_config[1];
3960#ifndef NV21
3961 vf->canvas1_config[2] = p_canvas_config[2];
3962#endif
3963}
3964
3965static void get_picture_qos_info(struct StorablePicture *picture)
3966{
3967 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3968 unsigned char a[3];
3969 unsigned char i, j, t;
3970 unsigned long data;
3971
3972 get_random_bytes(&data, sizeof(unsigned long));
3973 if (picture->slice_type == I_SLICE)
3974 data = 0;
3975 a[0] = data & 0xff;
3976 a[1] = (data >> 8) & 0xff;
3977 a[2] = (data >> 16) & 0xff;
3978
3979 for (i = 0; i < 3; i++)
3980 for (j = i+1; j < 3; j++) {
3981 if (a[j] < a[i]) {
3982 t = a[j];
3983 a[j] = a[i];
3984 a[i] = t;
3985 } else if (a[j] == a[i]) {
3986 a[i]++;
3987 t = a[j];
3988 a[j] = a[i];
3989 a[i] = t;
3990 }
3991 }
3992 picture->max_mv = a[2];
3993 picture->avg_mv = a[1];
3994 picture->min_mv = a[0];
3995 /*
3996 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3997 data, a[0], a[1], a[2]);
3998 */
3999
4000 get_random_bytes(&data, sizeof(unsigned long));
4001 a[0] = data & 0x1f;
4002 a[1] = (data >> 8) & 0x3f;
4003 a[2] = (data >> 16) & 0x7f;
4004
4005 for (i = 0; i < 3; i++)
4006 for (j = i+1; j < 3; j++) {
4007 if (a[j] < a[i]) {
4008 t = a[j];
4009 a[j] = a[i];
4010 a[i] = t;
4011 } else if (a[j] == a[i]) {
4012 a[i]++;
4013 t = a[j];
4014 a[j] = a[i];
4015 a[i] = t;
4016 }
4017 }
4018 picture->max_qp = a[2];
4019 picture->avg_qp = a[1];
4020 picture->min_qp = a[0];
4021 /*
4022 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4023 data, a[0], a[1], a[2]);
4024 */
4025
4026 get_random_bytes(&data, sizeof(unsigned long));
4027 a[0] = data & 0x1f;
4028 a[1] = (data >> 8) & 0x3f;
4029 a[2] = (data >> 16) & 0x7f;
4030
4031 for (i = 0; i < 3; i++)
4032 for (j = i+1; j < 3; j++) {
4033 if (a[j] < a[i]) {
4034 t = a[j];
4035 a[j] = a[i];
4036 a[i] = t;
4037 } else if (a[j] == a[i]) {
4038 a[i]++;
4039 t = a[j];
4040 a[j] = a[i];
4041 a[i] = t;
4042 }
4043 }
4044 picture->max_skip = a[2];
4045 picture->avg_skip = a[1];
4046 picture->min_skip = a[0];
4047
4048
4049 /*
4050 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4051 data,a[0], a[1], a[2]);
4052 */
4053 } else {
4054 uint32_t blk88_y_count;
4055 uint32_t blk88_c_count;
4056 uint32_t blk22_mv_count;
4057 uint32_t rdata32;
4058 int32_t mv_hi;
4059 int32_t mv_lo;
4060 uint32_t rdata32_l;
4061 uint32_t mvx_L0_hi;
4062 uint32_t mvy_L0_hi;
4063 uint32_t mvx_L1_hi;
4064 uint32_t mvy_L1_hi;
4065 int64_t value;
4066 uint64_t temp_value;
4067/*
4068#define DEBUG_QOS
4069*/
4070#ifdef DEBUG_QOS
4071 int pic_number = picture->poc;
4072#endif
4073
4074 picture->max_mv = 0;
4075 picture->avg_mv = 0;
4076 picture->min_mv = 0;
4077
4078 picture->max_skip = 0;
4079 picture->avg_skip = 0;
4080 picture->min_skip = 0;
4081
4082 picture->max_qp = 0;
4083 picture->avg_qp = 0;
4084 picture->min_qp = 0;
4085
4086
4087
4088
4089
4090 /* set rd_idx to 0 */
4091 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4092 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4093 if (blk88_y_count == 0) {
4094#ifdef DEBUG_QOS
4095 pr_info(" [Picture %d Quality] NO Data yet.\n",
4096 pic_number);
4097#endif
4098 /* reset all counts */
4099 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4100 return;
4101 }
4102 /* qp_y_sum */
4103 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4104#ifdef DEBUG_QOS
4105 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4106 pic_number, rdata32/blk88_y_count,
4107 rdata32, blk88_y_count);
4108#endif
4109 picture->avg_qp = rdata32/blk88_y_count;
4110 /* intra_y_count */
4111 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4112#ifdef DEBUG_QOS
4113 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4114 pic_number, rdata32*100/blk88_y_count,
4115 '%', rdata32);
4116#endif
4117 /* skipped_y_count */
4118 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4119#ifdef DEBUG_QOS
4120 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4121 pic_number, rdata32*100/blk88_y_count,
4122 '%', rdata32);
4123#endif
4124 picture->avg_skip = rdata32*100/blk88_y_count;
4125 /* coeff_non_zero_y_count */
4126 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4127#ifdef DEBUG_QOS
4128 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4129 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4130 '%', rdata32);
4131#endif
4132 /* blk66_c_count */
4133 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4134 if (blk88_c_count == 0) {
4135#ifdef DEBUG_QOS
4136 pr_info(" [Picture %d Quality] NO Data yet.\n",
4137 pic_number);
4138#endif
4139 /* reset all counts */
4140 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4141 return;
4142 }
4143 /* qp_c_sum */
4144 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4145#ifdef DEBUG_QOS
4146 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4147 pic_number, rdata32/blk88_c_count,
4148 rdata32, blk88_c_count);
4149#endif
4150 /* intra_c_count */
4151 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4152#ifdef DEBUG_QOS
4153 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4154 pic_number, rdata32*100/blk88_c_count,
4155 '%', rdata32);
4156#endif
4157 /* skipped_cu_c_count */
4158 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4159#ifdef DEBUG_QOS
4160 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4161 pic_number, rdata32*100/blk88_c_count,
4162 '%', rdata32);
4163#endif
4164 /* coeff_non_zero_c_count */
4165 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4166#ifdef DEBUG_QOS
4167 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4168 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4169 '%', rdata32);
4170#endif
4171
4172 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4173 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4174 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4175#ifdef DEBUG_QOS
4176 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4177 pic_number, (rdata32>>0)&0xff);
4178#endif
4179 picture->min_qp = (rdata32>>0)&0xff;
4180
4181#ifdef DEBUG_QOS
4182 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4183 pic_number, (rdata32>>8)&0xff);
4184#endif
4185 picture->max_qp = (rdata32>>8)&0xff;
4186
4187#ifdef DEBUG_QOS
4188 pr_info(" [Picture %d Quality] C QP min : %d\n",
4189 pic_number, (rdata32>>16)&0xff);
4190 pr_info(" [Picture %d Quality] C QP max : %d\n",
4191 pic_number, (rdata32>>24)&0xff);
4192#endif
4193
4194 /* blk22_mv_count */
4195 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4196 if (blk22_mv_count == 0) {
4197#ifdef DEBUG_QOS
4198 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4199 pic_number);
4200#endif
4201 /* reset all counts */
4202 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4203 return;
4204 }
4205 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4206 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4207 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4208 /* should all be 0x00 or 0xff */
4209#ifdef DEBUG_QOS
4210 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4211 pic_number, rdata32);
4212#endif
4213 mvx_L0_hi = ((rdata32>>0)&0xff);
4214 mvy_L0_hi = ((rdata32>>8)&0xff);
4215 mvx_L1_hi = ((rdata32>>16)&0xff);
4216 mvy_L1_hi = ((rdata32>>24)&0xff);
4217
4218 /* mvx_L0_count[31:0] */
4219 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4220 temp_value = mvx_L0_hi;
4221 temp_value = (temp_value << 32) | rdata32_l;
4222
4223 if (mvx_L0_hi & 0x80)
4224 value = 0xFFFFFFF000000000 | temp_value;
4225 else
4226 value = temp_value;
4227 value = div_s64(value, blk22_mv_count);
4228#ifdef DEBUG_QOS
4229 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4230 pic_number, (int)(value),
4231 value, blk22_mv_count);
4232#endif
4233 picture->avg_mv = value;
4234
4235 /* mvy_L0_count[31:0] */
4236 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4237 temp_value = mvy_L0_hi;
4238 temp_value = (temp_value << 32) | rdata32_l;
4239
4240 if (mvy_L0_hi & 0x80)
4241 value = 0xFFFFFFF000000000 | temp_value;
4242 else
4243 value = temp_value;
4244#ifdef DEBUG_QOS
4245 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4246 pic_number, rdata32_l/blk22_mv_count,
4247 value, blk22_mv_count);
4248#endif
4249
4250 /* mvx_L1_count[31:0] */
4251 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4252 temp_value = mvx_L1_hi;
4253 temp_value = (temp_value << 32) | rdata32_l;
4254 if (mvx_L1_hi & 0x80)
4255 value = 0xFFFFFFF000000000 | temp_value;
4256 else
4257 value = temp_value;
4258#ifdef DEBUG_QOS
4259 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4260 pic_number, rdata32_l/blk22_mv_count,
4261 value, blk22_mv_count);
4262#endif
4263
4264 /* mvy_L1_count[31:0] */
4265 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4266 temp_value = mvy_L1_hi;
4267 temp_value = (temp_value << 32) | rdata32_l;
4268 if (mvy_L1_hi & 0x80)
4269 value = 0xFFFFFFF000000000 | temp_value;
4270 else
4271 value = temp_value;
4272#ifdef DEBUG_QOS
4273 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4274 pic_number, rdata32_l/blk22_mv_count,
4275 value, blk22_mv_count);
4276#endif
4277
4278 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4279 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4280 mv_hi = (rdata32>>16)&0xffff;
4281 if (mv_hi & 0x8000)
4282 mv_hi = 0x8000 - mv_hi;
4283#ifdef DEBUG_QOS
4284 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4285 pic_number, mv_hi);
4286#endif
4287 picture->max_mv = mv_hi;
4288
4289 mv_lo = (rdata32>>0)&0xffff;
4290 if (mv_lo & 0x8000)
4291 mv_lo = 0x8000 - mv_lo;
4292#ifdef DEBUG_QOS
4293 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4294 pic_number, mv_lo);
4295#endif
4296 picture->min_mv = mv_lo;
4297
4298 /* {mvy_L0_max, mvy_L0_min} */
4299 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4300 mv_hi = (rdata32>>16)&0xffff;
4301 if (mv_hi & 0x8000)
4302 mv_hi = 0x8000 - mv_hi;
4303#ifdef DEBUG_QOS
4304 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4305 pic_number, mv_hi);
4306#endif
4307
4308 mv_lo = (rdata32>>0)&0xffff;
4309 if (mv_lo & 0x8000)
4310 mv_lo = 0x8000 - mv_lo;
4311#ifdef DEBUG_QOS
4312 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4313 pic_number, mv_lo);
4314#endif
4315
4316 /* {mvx_L1_max, mvx_L1_min} */
4317 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4318 mv_hi = (rdata32>>16)&0xffff;
4319 if (mv_hi & 0x8000)
4320 mv_hi = 0x8000 - mv_hi;
4321#ifdef DEBUG_QOS
4322 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4323 pic_number, mv_hi);
4324#endif
4325
4326 mv_lo = (rdata32>>0)&0xffff;
4327 if (mv_lo & 0x8000)
4328 mv_lo = 0x8000 - mv_lo;
4329#ifdef DEBUG_QOS
4330 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4331 pic_number, mv_lo);
4332#endif
4333
4334 /* {mvy_L1_max, mvy_L1_min} */
4335 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4336 mv_hi = (rdata32>>16)&0xffff;
4337 if (mv_hi & 0x8000)
4338 mv_hi = 0x8000 - mv_hi;
4339#ifdef DEBUG_QOS
4340 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4341 pic_number, mv_hi);
4342#endif
4343 mv_lo = (rdata32>>0)&0xffff;
4344 if (mv_lo & 0x8000)
4345 mv_lo = 0x8000 - mv_lo;
4346#ifdef DEBUG_QOS
4347 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4348 pic_number, mv_lo);
4349#endif
4350
4351 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4352#ifdef DEBUG_QOS
4353 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4354 pic_number, rdata32);
4355#endif
4356 /* reset all counts */
4357 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4358 }
4359}
4360
4361static int get_max_dec_frame_buf_size(int level_idc,
4362 int max_reference_frame_num, int mb_width,
4363 int mb_height)
4364{
4365 int pic_size = mb_width * mb_height * 384;
4366
4367 int size = 0;
4368
4369 switch (level_idc) {
4370 case 9:
4371 size = 152064;
4372 break;
4373 case 10:
4374 size = 152064;
4375 break;
4376 case 11:
4377 size = 345600;
4378 break;
4379 case 12:
4380 size = 912384;
4381 break;
4382 case 13:
4383 size = 912384;
4384 break;
4385 case 20:
4386 size = 912384;
4387 break;
4388 case 21:
4389 size = 1824768;
4390 break;
4391 case 22:
4392 size = 3110400;
4393 break;
4394 case 30:
4395 size = 3110400;
4396 break;
4397 case 31:
4398 size = 6912000;
4399 break;
4400 case 32:
4401 size = 7864320;
4402 break;
4403 case 40:
4404 size = 12582912;
4405 break;
4406 case 41:
4407 size = 12582912;
4408 break;
4409 case 42:
4410 size = 13369344;
4411 break;
4412 case 50:
4413 size = 42393600;
4414 break;
4415 case 51:
4416 case 52:
4417 default:
4418 size = 70778880;
4419 break;
4420 }
4421
4422 size /= pic_size;
4423 size = size + 1; /* need one more buffer */
4424
4425 if (max_reference_frame_num > size)
4426 size = max_reference_frame_num;
4427 size = imin(size, 16);
4428
4429 return size;
4430}
4431
4432static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4433{
4434 int i, j;
4435
4436 if (hw->double_write_mode) {
4437 mutex_lock(&vmh264_mutex);
4438 if (hw->decode_pic_count == 0) {
4439 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4440 i = get_buf_spec_by_canvas_pos(hw, j);
4441 if (i >= 0)
4442 config_decode_canvas_ex(hw, i);
4443 }
4444 }
4445 mutex_unlock(&vmh264_mutex);
4446 }
4447}
4448
4449static int vh264_set_params(struct vdec_h264_hw_s *hw,
4450 u32 param1, u32 param2, u32 param3, u32 param4)
4451{
4452 int i, j;
4453 int mb_width, mb_total;
4454 int max_reference_size, level_idc;
4455 int mb_height = 0;
4456 unsigned long flags;
4457 /*int mb_mv_byte;*/
4458 struct vdec_s *vdec = hw_to_vdec(hw);
4459 u32 seq_info2;
4460 int ret = 0;
4461 int active_buffer_spec_num;
4462 unsigned int buf_size;
4463 unsigned int frame_mbs_only_flag;
4464 unsigned int chroma_format_idc, chroma444;
4465 unsigned int crop_infor, crop_bottom, crop_right;
4466 unsigned int used_reorder_dpb_size_margin
4467 = hw->reorder_dpb_size_margin;
4468 u8 *colocate_vaddr = NULL;
4469
4470#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4471 if (vdec->master || vdec->slave)
4472 used_reorder_dpb_size_margin =
4473 reorder_dpb_size_margin_dv;
4474#endif
4475 seq_info2 = param1;
4476 hw->seq_info = param2;
4477
4478 mb_width = seq_info2 & 0xff;
4479 mb_total = (seq_info2 >> 8) & 0xffff;
4480 if (!mb_width && mb_total) /*for 4k2k*/
4481 mb_width = 256;
4482 if (mb_width)
4483 mb_height = mb_total/mb_width;
4484 if (mb_width <= 0 || mb_height <= 0 ||
4485 is_oversize(mb_width << 4, mb_height << 4)) {
4486 dpb_print(DECODE_ID(hw), 0,
4487 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4488 seq_info2,
4489 mb_width,
4490 mb_height);
4491 return -1;
4492 }
4493
4494 if (seq_info2 != 0 &&
4495 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4496 hw->seq_info2 != 0
4497 ) /*picture size changed*/
4498 h264_reconfig(hw);
4499
4500 if (hw->config_bufmgr_done == 0) {
4501 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4502 u32 reg_val;
4503 hw->cfg_param1 = param1;
4504 hw->cfg_param2 = param2;
4505 hw->cfg_param3 = param3;
4506 hw->cfg_param4 = param4;
4507
4508 hw->seq_info2 = seq_info2 & (~0x80000000);
4509 dpb_print(DECODE_ID(hw), 0,
4510 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4511 seq_info2, hw->seq_info);
4512
4513 dpb_init_global(&hw->dpb,
4514 DECODE_ID(hw), 0, 0);
4515
4516 p_H264_Dpb->fast_output_enable = fast_output_enable;
4517 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4518
4519#if 1
4520 /*crop*/
4521 /* AV_SCRATCH_2
4522 bit 15: frame_mbs_only_flag
4523 bit 13-14: chroma_format_idc */
4524 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4525 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4526 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4527
4528 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4529 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4530 (2 - frame_mbs_only_flag) */
4531 crop_infor = param3;
4532 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4533 crop_right = ((crop_infor >> 16) & 0xff)
4534 >> (2 - frame_mbs_only_flag);
4535
4536 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4537 hw->frame_width = mb_width << 4;
4538 hw->frame_height = mb_height << 4;
4539 if (frame_mbs_only_flag) {
4540 hw->frame_height =
4541 hw->frame_height - (2 >> chroma444) *
4542 min(crop_bottom,
4543 (unsigned int)((8 << chroma444) - 1));
4544 hw->frame_width =
4545 hw->frame_width -
4546 (2 >> chroma444) * min(crop_right,
4547 (unsigned
4548 int)((8 << chroma444) - 1));
4549 } else {
4550 hw->frame_height =
4551 hw->frame_height - (4 >> chroma444) *
4552 min(crop_bottom,
4553 (unsigned int)((8 << chroma444)
4554 - 1));
4555 hw->frame_width =
4556 hw->frame_width -
4557 (4 >> chroma444) * min(crop_right,
4558 (unsigned int)((8 << chroma444) - 1));
4559 }
4560 dpb_print(DECODE_ID(hw), 0,
4561 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4562 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4563 dpb_print(DECODE_ID(hw), 0,
4564 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4565 mb_height, crop_right,
4566 hw->frame_width, mb_width);
4567
4568 if (hw->frame_height == 1088)
4569 hw->frame_height = 1080;
4570#endif
4571 if (!hw->mmu_enable) {
4572 mb_width = (mb_width+3) & 0xfffffffc;
4573 mb_height = (mb_height+3) & 0xfffffffc;
4574 }
4575 mb_total = mb_width * mb_height;
4576 hw->mb_width = mb_width;
4577 hw->mb_height = mb_height;
4578 hw->mb_total = mb_total;
4579 if (hw->mmu_enable)
4580 hevc_mcr_sao_global_hw_init(hw,
4581 (hw->mb_width << 4), (hw->mb_height << 4));
4582
4583 reg_val = param4;
4584 level_idc = reg_val & 0xff;
4585 max_reference_size = (reg_val >> 8) & 0xff;
4586 hw->dpb.origin_max_reference = max_reference_size;
4587 dpb_print(DECODE_ID(hw), 0,
4588 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4589 mb_height, mb_width, mb_total,
4590 level_idc, max_reference_size);
4591
4592
4593 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4594 hw->dpb.reorder_pic_num =
4595 get_max_dec_frame_buf_size(level_idc,
4596 max_reference_size, mb_width, mb_height);
4597
4598 dpb_print(DECODE_ID(hw), 0,
4599 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4600 hw->bitstream_restriction_flag,
4601 hw->max_dec_frame_buffering,
4602 hw->dpb.reorder_pic_num);
4603
4604 if ((hw->bitstream_restriction_flag) &&
4605 (hw->max_dec_frame_buffering <
4606 hw->dpb.reorder_pic_num)) {
4607 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4608 dpb_print(DECODE_ID(hw), 0,
4609 "set reorder_pic_num to %d\n",
4610 hw->dpb.reorder_pic_num);
4611 }
4612
4613 active_buffer_spec_num =
4614 hw->dpb.reorder_pic_num
4615 + used_reorder_dpb_size_margin;
4616 hw->max_reference_size =
4617 max_reference_size + reference_buf_margin;
4618
4619 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4620 active_buffer_spec_num = MAX_VF_BUF_NUM;
4621 hw->dpb.reorder_pic_num = active_buffer_spec_num
4622 - used_reorder_dpb_size_margin;
4623 }
4624 hw->dpb.mDPB.size = active_buffer_spec_num;
4625 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4626 hw->max_reference_size = MAX_VF_BUF_NUM;
4627 hw->dpb.max_reference_size = hw->max_reference_size;
4628
4629 if (hw->no_poc_reorder_flag)
4630 hw->dpb.reorder_pic_num = 1;
4631 dpb_print(DECODE_ID(hw), 0,
4632 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4633 __func__, active_buffer_spec_num,
4634 hw->dpb.reorder_pic_num,
4635 hw->max_reference_size);
4636
4637 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4638
4639 mutex_lock(&vmh264_mutex);
4640 if (!hw->mmu_enable) {
4641 config_buf_specs(vdec);
4642 i = get_buf_spec_by_canvas_pos(hw, 0);
4643
4644 if (hw->is_used_v4l) {
4645 if (i != -1) {
4646 pr_info("v4l: delay alloc the buffer.\n");
4647 }
4648 } else {
4649 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4650 config_decode_canvas(hw, i);
4651 else
4652 ret = -1;
4653 }
4654 } else {
4655 if (hw->double_write_mode) {
4656 config_buf_specs_ex(vdec);
4657 } else {
4658 spin_lock_irqsave(&hw->bufspec_lock, flags);
4659 for (i = 0, j = 0;
4660 j < active_buffer_spec_num
4661 && i < BUFSPEC_POOL_SIZE;
4662 i++) {
4663 if (hw->buffer_spec[i].used != -1)
4664 continue;
4665 hw->buffer_spec[i].used = 0;
4666 hw->buffer_spec[i].
4667 alloc_header_addr = 0;
4668 hw->buffer_spec[i].canvas_pos = j;
4669 j++;
4670 }
4671 spin_unlock_irqrestore(&hw->bufspec_lock,
4672 flags);
4673 }
4674 hevc_mcr_config_canv2axitbl(hw, 0);
4675 }
4676 mutex_unlock(&vmh264_mutex);
4677 if (dpb_is_debug(DECODE_ID(hw),
4678 PRINT_FLAG_DUMP_BUFSPEC))
4679 dump_bufspec(hw, __func__);
4680
4681#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4682 buf_size = PAGE_ALIGN(
4683 p_H264_Dpb->colocated_buf_size *
4684 active_buffer_spec_num);
4685#else
4686 buf_size = PAGE_ALIGN(
4687 p_H264_Dpb->colocated_buf_size *
4688 hw->max_reference_size);
4689#endif
4690
4691 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4692 buf_size, DRIVER_NAME,
4693 &hw->collocate_cma_alloc_addr) < 0)
4694 return -1;
4695 if (!vdec_secure(vdec)) {
4696 /* clear for some mosaic problem after reset bufmgr */
4697 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4698 if (colocate_vaddr != NULL) {
4699 memset(colocate_vaddr, 0, buf_size);
4700 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4701 codec_mm_unmap_phyaddr(colocate_vaddr);
4702 }
4703 }
4704
4705 hw->dpb.colocated_mv_addr_start =
4706 hw->collocate_cma_alloc_addr;
4707#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4708 hw->dpb.colocated_mv_addr_end =
4709 hw->dpb.colocated_mv_addr_start +
4710 (p_H264_Dpb->colocated_buf_size *
4711 active_buffer_spec_num);
4712#else
4713 hw->dpb.colocated_mv_addr_end =
4714 hw->dpb.colocated_mv_addr_start +
4715 (p_H264_Dpb->colocated_buf_size *
4716 hw->max_reference_size);
4717#endif
4718 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4719 "callocate cma, %lx, %x\n",
4720 hw->collocate_cma_alloc_addr,
4721 hw->dpb.colocated_mv_addr_start);
4722
4723 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4724 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4725 hw->dpb.colocated_mv_addr_start,
4726 hw->dpb.colocated_mv_addr_end);
4727 if (!hw->mmu_enable) {
4728 mutex_lock(&vmh264_mutex);
4729 if (ret >= 0 && hw->decode_pic_count == 0) {
4730 int buf_cnt;
4731 /* h264_reconfig: alloc later*/
4732 buf_cnt = hw->dpb.mDPB.size;
4733
4734 for (j = 1; j < buf_cnt; j++) {
4735 i = get_buf_spec_by_canvas_pos(hw, j);
4736
4737 if (hw->is_used_v4l) {
4738 pr_info("v4l: delay alloc the buffer.\n");
4739 break;
4740 } else if (alloc_one_buf_spec(hw, i) < 0)
4741 break;
4742
4743 config_decode_canvas(hw, i);
4744 }
4745 }
4746 mutex_unlock(&vmh264_mutex);
4747 } else {
4748 vh264_config_canvs_for_mmu(hw);
4749 }
4750
4751 hw->config_bufmgr_done = 1;
4752
4753 /*end of config_bufmgr_done */
4754 }
4755
4756 return ret;
4757}
4758
4759static void vui_config(struct vdec_h264_hw_s *hw)
4760{
4761 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4762 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4763 /*time*/
4764 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4765 hw->time_scale = p_H264_Dpb->time_scale;
4766 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4767
4768 hw->bitstream_restriction_flag =
4769 p_H264_Dpb->bitstream_restriction_flag;
4770 hw->num_reorder_frames =
4771 p_H264_Dpb->num_reorder_frames;
4772 hw->max_dec_frame_buffering =
4773 p_H264_Dpb->max_dec_frame_buffering;
4774
4775 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4776 "vui_config: pdb %d, %d, %d\n",
4777 p_H264_Dpb->bitstream_restriction_flag,
4778 p_H264_Dpb->num_reorder_frames,
4779 p_H264_Dpb->max_dec_frame_buffering);
4780
4781 hw->fixed_frame_rate_flag = 0;
4782 if (hw->timing_info_present_flag) {
4783 hw->fixed_frame_rate_flag =
4784 p_H264_Dpb->fixed_frame_rate_flag;
4785
4786 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4787 ((!hw->sync_outside) ||
4788 (!hw->frame_dur)))
4789 && hw->num_units_in_tick && hw->time_scale) {
4790 if (hw->use_idr_framerate ||
4791 hw->fixed_frame_rate_flag ||
4792 !hw->frame_dur ||
4793 !hw->duration_from_pts_done
4794 /*|| vh264_running*/) {
4795 u32 frame_dur_es =
4796 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4797 hw->time_scale);
4798 if (hw->frame_dur != frame_dur_es) {
4799 hw->h264_first_valid_pts_ready = false;
4800 hw->h264pts1 = 0;
4801 hw->h264pts2 = 0;
4802 hw->h264_pts_count = 0;
4803 hw->duration_from_pts_done = 0;
4804 fixed_frame_rate_mode =
4805 FIX_FRAME_RATE_OFF;
4806 hw->pts_duration = 0;
4807 hw->frame_dur = frame_dur_es;
4808 vdec_schedule_work(&hw->notify_work);
4809 dpb_print(DECODE_ID(hw),
4810 PRINT_FLAG_DEC_DETAIL,
4811 "frame_dur %d from timing_info\n",
4812 hw->frame_dur);
4813 }
4814
4815 /*hack to avoid use ES frame duration when
4816 *it's half of the rate from system info
4817 * sometimes the encoder is given a wrong
4818 * frame rate but the system side information
4819 * is more reliable
4820 *if ((frame_dur * 2) != frame_dur_es) {
4821 * frame_dur = frame_dur_es;
4822 *}
4823 */
4824 }
4825 }
4826 } else {
4827 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4828 "H.264: timing_info not present\n");
4829 }
4830
4831 /*aspect ratio*/
4832 aspect_ratio_info_present_flag =
4833 p_H264_Dpb->vui_status & 0x1;
4834 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4835
4836 if (aspect_ratio_info_present_flag) {
4837 if (aspect_ratio_idc == EXTEND_SAR) {
4838 hw->h264_ar = 0x3ff;
4839 hw->height_aspect_ratio =
4840 p_H264_Dpb->aspect_ratio_sar_height;
4841 hw->width_aspect_ratio =
4842 p_H264_Dpb->aspect_ratio_sar_width;
4843 } else {
4844 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4845 aspect_ratio_idc); */
4846
4847 switch (aspect_ratio_idc) {
4848 case 1:
4849 hw->h264_ar = 0x3ff;
4850 hw->height_aspect_ratio = 1;
4851 hw->width_aspect_ratio = 1;
4852 break;
4853 case 2:
4854 hw->h264_ar = 0x3ff;
4855 hw->height_aspect_ratio = 11;
4856 hw->width_aspect_ratio = 12;
4857 break;
4858 case 3:
4859 hw->h264_ar = 0x3ff;
4860 hw->height_aspect_ratio = 11;
4861 hw->width_aspect_ratio = 10;
4862 break;
4863 case 4:
4864 hw->h264_ar = 0x3ff;
4865 hw->height_aspect_ratio = 11;
4866 hw->width_aspect_ratio = 16;
4867 break;
4868 case 5:
4869 hw->h264_ar = 0x3ff;
4870 hw->height_aspect_ratio = 33;
4871 hw->width_aspect_ratio = 40;
4872 break;
4873 case 6:
4874 hw->h264_ar = 0x3ff;
4875 hw->height_aspect_ratio = 11;
4876 hw->width_aspect_ratio = 24;
4877 break;
4878 case 7:
4879 hw->h264_ar = 0x3ff;
4880 hw->height_aspect_ratio = 11;
4881 hw->width_aspect_ratio = 20;
4882 break;
4883 case 8:
4884 hw->h264_ar = 0x3ff;
4885 hw->height_aspect_ratio = 11;
4886 hw->width_aspect_ratio = 32;
4887 break;
4888 case 9:
4889 hw->h264_ar = 0x3ff;
4890 hw->height_aspect_ratio = 33;
4891 hw->width_aspect_ratio = 80;
4892 break;
4893 case 10:
4894 hw->h264_ar = 0x3ff;
4895 hw->height_aspect_ratio = 11;
4896 hw->width_aspect_ratio = 18;
4897 break;
4898 case 11:
4899 hw->h264_ar = 0x3ff;
4900 hw->height_aspect_ratio = 11;
4901 hw->width_aspect_ratio = 15;
4902 break;
4903 case 12:
4904 hw->h264_ar = 0x3ff;
4905 hw->height_aspect_ratio = 33;
4906 hw->width_aspect_ratio = 64;
4907 break;
4908 case 13:
4909 hw->h264_ar = 0x3ff;
4910 hw->height_aspect_ratio = 99;
4911 hw->width_aspect_ratio = 160;
4912 break;
4913 case 14:
4914 hw->h264_ar = 0x3ff;
4915 hw->height_aspect_ratio = 3;
4916 hw->width_aspect_ratio = 4;
4917 break;
4918 case 15:
4919 hw->h264_ar = 0x3ff;
4920 hw->height_aspect_ratio = 2;
4921 hw->width_aspect_ratio = 3;
4922 break;
4923 case 16:
4924 hw->h264_ar = 0x3ff;
4925 hw->height_aspect_ratio = 1;
4926 hw->width_aspect_ratio = 2;
4927 break;
4928 default:
4929 if (hw->vh264_ratio >> 16) {
4930 hw->h264_ar = (hw->frame_height *
4931 (hw->vh264_ratio & 0xffff) *
4932 0x100 +
4933 ((hw->vh264_ratio >> 16) *
4934 hw->frame_width / 2)) /
4935 ((hw->vh264_ratio >> 16) *
4936 hw->frame_width);
4937 hw->height_aspect_ratio = 1;
4938 hw->width_aspect_ratio = 1;
4939 } else {
4940 hw->h264_ar = 0x3ff;
4941 hw->height_aspect_ratio = 1;
4942 hw->width_aspect_ratio = 1;
4943 }
4944 break;
4945 }
4946 }
4947 } else {
4948 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4949 "v264dec: aspect_ratio not available from source\n");
4950 if (hw->vh264_ratio >> 16) {
4951 /* high 16 bit is width, low 16 bit is height */
4952 hw->h264_ar =
4953 ((hw->vh264_ratio & 0xffff) *
4954 hw->frame_height * 0x100 +
4955 (hw->vh264_ratio >> 16) *
4956 hw->frame_width / 2) /
4957 ((hw->vh264_ratio >> 16) *
4958 hw->frame_width);
4959 hw->height_aspect_ratio = 1;
4960 hw->width_aspect_ratio = 1;
4961 } else {
4962 hw->h264_ar = 0x3ff;
4963 hw->height_aspect_ratio = 1;
4964 hw->width_aspect_ratio = 1;
4965 }
4966 }
4967
4968 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4969 if (((hw->frame_dur == RATE_2397_FPS)
4970 && (dec_control
4971 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4972 || ((RATE_2997_FPS ==
4973 hw->frame_dur) &&
4974 (dec_control &
4975 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4976 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4977 "force fix frame rate\n");
4978 hw->fixed_frame_rate_flag = 0x40;
4979 }
4980 }
4981
4982 /*video_signal_from_vui: to do .. */
4983}
4984
4985static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4986{
4987 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4988
4989 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4990 if (error_proc_policy & 0x20) {
4991 if (!hw->is_used_v4l)
4992 hw->reset_bufmgr_flag = 1;
4993 }
4994}
4995
4996void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4997{
4998 struct vdec_h264_hw_s *hw =
4999 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
5000
5001 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5002
5003 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5004 hw->reset_bufmgr_flag = 1;
5005}
5006
5007#ifdef CONSTRAIN_MAX_BUF_NUM
5008static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5009{
5010 int i;
5011 int count = 0;
5012 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5013 if (is_buf_spec_in_disp_q(hw, i) &&
5014 hw->buffer_spec[i].vf_ref > 0)
5015 count++;
5016 }
5017 return count;
5018}
5019
5020static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5021{
5022 int i;
5023 int count = 0;
5024 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5025 if (is_buf_spec_in_use(hw, i))
5026 count++;
5027 }
5028 return count;
5029}
5030#endif
5031
5032
5033static bool is_buffer_available(struct vdec_s *vdec)
5034{
5035 bool buffer_available = 1;
5036 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5037 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5038 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5039 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5040 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5041 ((p_H264_Dpb->mDPB.init_done) &&
5042 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5043 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5044 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5045 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5046 __func__,
5047 kfifo_len(&hw->newframe_q),
5048 have_free_buf_spec(vdec),
5049 p_H264_Dpb->mDPB.init_done,
5050 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5051 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5052 );
5053 buffer_available = 0;
5054 if (dpb_is_debug(DECODE_ID(hw),
5055 DEBUG_DISABLE_RUNREADY_RMBUF))
5056 return buffer_available;
5057
5058 if ((error_proc_policy & 0x4) &&
5059 (error_proc_policy & 0x8)) {
5060 if ((kfifo_len(&hw->display_q) <= 0) &&
5061 (p_H264_Dpb->mDPB.used_size ==
5062 p_H264_Dpb->mDPB.size) &&
5063 (p_Dpb->ref_frames_in_buffer >
5064 (imax(
5065 1, p_Dpb->num_ref_frames)
5066 - p_Dpb->ltref_frames_in_buffer +
5067 force_sliding_margin)))
5068 bufmgr_recover(hw);
5069 else
5070 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5071 } else if ((error_proc_policy & 0x4) &&
5072 (kfifo_len(&hw->display_q) <= 0) &&
5073 ((p_H264_Dpb->mDPB.used_size ==
5074 p_H264_Dpb->mDPB.size) ||
5075 (!have_free_buf_spec(vdec)))) {
5076 enum receviver_start_e state = RECEIVER_INACTIVE;
5077 if ((error_proc_policy & 0x10) &&
5078 vf_get_receiver(vdec->vf_provider_name)) {
5079 state =
5080 vf_notify_receiver(vdec->vf_provider_name,
5081 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5082 NULL);
5083 if ((state == RECEIVER_STATE_NULL)
5084 || (state == RECEIVER_STATE_NONE))
5085 state = RECEIVER_INACTIVE;
5086 }
5087 if (state == RECEIVER_INACTIVE)
5088 bufmgr_recover(hw);
5089 else
5090 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5091 } else if ((error_proc_policy & 0x8) &&
5092 (p_Dpb->ref_frames_in_buffer >
5093 (imax(
5094 1, p_Dpb->num_ref_frames)
5095 - p_Dpb->ltref_frames_in_buffer +
5096 force_sliding_margin)))
5097 bufmgr_recover(hw);
5098 else
5099 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5100
5101 if (hw->reset_bufmgr_flag == 1)
5102 buffer_available = 1;
5103 }
5104
5105 return buffer_available;
5106}
5107
5108#define AUX_TAG_SEI 0x2
5109
5110#define SEI_BUFFERING_PERIOD 0
5111#define SEI_PicTiming 1
5112#define SEI_USER_DATA 4
5113#define SEI_RECOVERY_POINT 6
5114
5115/*
5116 *************************************************************************
5117 * Function:Reads bits from the bitstream buffer
5118 * Input:
5119 byte buffer[]
5120 containing sei message data bits
5121 int totbitoffset
5122 bit offset from start of partition
5123 int bytecount
5124 total bytes in bitstream
5125 int numbits
5126 number of bits to read
5127 * Output:
5128 int *info
5129 * Return:
5130 -1: failed
5131 > 0: the count of bit read
5132 * Attention:
5133 *************************************************************************
5134 */
5135
5136static int get_bits(unsigned char buffer[],
5137 int totbitoffset,
5138 int *info,
5139 int bytecount,
5140 int numbits)
5141{
5142 register int inf;
5143 long byteoffset;
5144 int bitoffset;
5145
5146 int bitcounter = numbits;
5147
5148 byteoffset = totbitoffset / 8;
5149 bitoffset = 7 - (totbitoffset % 8);
5150
5151 inf = 0;
5152 while (numbits) {
5153 inf <<= 1;
5154 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5155 numbits--;
5156 bitoffset--;
5157 if (bitoffset < 0) {
5158 byteoffset++;
5159 bitoffset += 8;
5160 if (byteoffset > bytecount)
5161 return -1;
5162 }
5163 }
5164
5165 *info = inf;
5166
5167
5168 return bitcounter;
5169}
5170
5171static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5172 u8 *sei_data_buf,
5173 u8 *sei_data_buf_end)
5174{
5175 int payload_type;
5176 int payload_size;
5177 u8 *p_sei;
5178 int temp = 0;
5179 int bit_offset;
5180 int read_size;
5181 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5182
5183 p_sei = sei_data_buf;
5184 read_size = 0;
5185 payload_type = 0;
5186 do {
5187 if (p_sei >= sei_data_buf_end)
5188 return read_size;
5189
5190 payload_type += *p_sei;
5191 read_size++;
5192 } while (*p_sei++ == 255);
5193
5194
5195 payload_size = 0;
5196 do {
5197 if (p_sei >= sei_data_buf_end)
5198 return read_size;
5199
5200 payload_size += *p_sei;
5201 read_size++;
5202 } while (*p_sei++ == 255);
5203
5204
5205 if (p_sei + payload_size > sei_data_buf_end) {
5206 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5207 "%s: payload_type = %d, payload_size = %d is over\n",
5208 __func__, payload_type, payload_size);
5209 return read_size;
5210 }
5211 bit_offset = 0;
5212
5213 if (payload_size <= 0) {
5214 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5215 "%s warning: this is a null sei message for payload_type = %d\n",
5216 __func__, payload_type);
5217 return read_size;
5218 }
5219 switch (payload_type) {
5220 case SEI_BUFFERING_PERIOD:
5221 break;
5222 case SEI_PicTiming:
5223 if (p_H264_Dpb->vui_status & 0xc) {
5224 int cpb_removal_delay;
5225 int dpb_output_delay;
5226 u32 delay_len;
5227
5228 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5229 cpb_removal_delay
5230 = (delay_len & 0x1F) + 1;
5231 dpb_output_delay
5232 = ((delay_len >> 5) & 0x1F) + 1;
5233
5234 get_bits(p_sei, bit_offset,
5235 &temp, payload_size,
5236 dpb_output_delay+cpb_removal_delay);
5237 bit_offset += dpb_output_delay+cpb_removal_delay;
5238 }
5239 if (p_H264_Dpb->vui_status & 0x10) {
5240 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5241 bit_offset += 4;
5242 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5243 }
5244 break;
5245 case SEI_USER_DATA:
5246 if (enable_itu_t35) {
5247 int i;
5248 int j;
5249 int data_len;
5250 u8 *user_data_buf;
5251
5252 user_data_buf
5253 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5254 /* user data length should be align with 8 bytes,
5255 if not, then padding with zero*/
5256 for (i = 0; i < payload_size; i += 8) {
5257 for (j = 0; j < 8; j++) {
5258 int index;
5259
5260 index = i+7-j;
5261 if (index >= payload_size)
5262 user_data_buf[i+j] = 0;
5263 else
5264 user_data_buf[i+j]
5265 = p_sei[i+7-j];
5266 }
5267 }
5268
5269 data_len = payload_size;
5270 if (payload_size % 8)
5271 data_len = ((payload_size + 8) >> 3) << 3;
5272
5273 hw->sei_itu_data_len += data_len;
5274 /*
5275 dpb_print(DECODE_ID(hw), 0,
5276 "%s: user data, and len = %d:\n",
5277 __func__, hw->sei_itu_data_len);
5278 */
5279 }
5280 break;
5281 case SEI_RECOVERY_POINT:
5282 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5283 break;
5284 }
5285
5286 return read_size + payload_size;
5287}
5288
5289static void parse_sei_data(struct vdec_h264_hw_s *hw,
5290 u8 *sei_data_buf,
5291 int len)
5292{
5293 char *p_sei;
5294 char *p_sei_end;
5295 int parsed_size;
5296 int read_size;
5297
5298
5299 p_sei = sei_data_buf;
5300 p_sei_end = p_sei + len;
5301 parsed_size = 0;
5302 while (parsed_size < len) {
5303 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5304 p_sei += read_size;
5305 parsed_size += read_size;
5306 if (*p_sei == 0x80) {
5307 p_sei++;
5308 parsed_size++;
5309 }
5310 }
5311}
5312
5313static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5314{
5315 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5316 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5317 unsigned mby_mbx = READ_VREG(MBY_MBX);
5318 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5319 unsigned decode_mb_count =
5320 ((mby_mbx & 0xff) * hw->mb_width +
5321 (((mby_mbx >> 8) & 0xff) + 1));
5322 if (mby_mbx == 0)
5323 return;
5324 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5325 mb_total /= 2;
5326 if (error_proc_policy & 0x100) {
5327 if (decode_mb_count < mb_total)
5328 p->data_flag |= ERROR_FLAG;
5329 }
5330
5331 if ((error_proc_policy & 0x200) &&
5332 READ_VREG(ERROR_STATUS_REG) != 0) {
5333 p->data_flag |= ERROR_FLAG;
5334 }
5335
5336 if (p->data_flag & ERROR_FLAG) {
5337 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5338 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5339 __func__,
5340 hw->seq_info2,
5341 mby_mbx,
5342 mb_total,
5343 decode_mb_count,
5344 READ_VREG(ERROR_STATUS_REG)
5345 );
5346
5347 }
5348}
5349
5350static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5351{
5352 int i;
5353 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5354 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5355 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5356 u32 debug_tag;
5357 int ret;
5358
5359 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5360#if 1
5361 unsigned short *p = (unsigned short *)hw->lmem_addr;
5362 dma_sync_single_for_cpu(
5363 amports_get_dma_device(),
5364 hw->lmem_addr_remap,
5365 PAGE_SIZE,
5366 DMA_FROM_DEVICE);
5367 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5368 int ii;
5369 for (ii = 0; ii < 4; ii++) {
5370 p_H264_Dpb->dpb_param.l.data[i+ii] =
5371 p[i+3-ii];
5372 if (dpb_is_debug(DECODE_ID(hw),
5373 RRINT_FLAG_RPM)) {
5374 if (((i + ii) & 0xf) == 0)
5375 dpb_print(DECODE_ID(hw),
5376 0, "%04x:",
5377 i);
5378 dpb_print_cont(DECODE_ID(hw),
5379 0, "%04x ",
5380 p[i+3-ii]);
5381 if (((i + ii + 1) & 0xf) == 0)
5382 dpb_print_cont(
5383 DECODE_ID(hw),
5384 0, "\r\n");
5385 }
5386 }
5387 }
5388
5389 p_H264_Dpb->bitstream_restriction_flag =
5390 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5391 p_H264_Dpb->num_reorder_frames =
5392 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5393 p_H264_Dpb->max_dec_frame_buffering =
5394 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5395
5396 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5397 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5398 p_H264_Dpb->bitstream_restriction_flag,
5399 p_H264_Dpb->num_reorder_frames,
5400 p_H264_Dpb->max_dec_frame_buffering);
5401 hw->bitstream_restriction_flag =
5402 p_H264_Dpb->bitstream_restriction_flag;
5403 hw->num_reorder_frames =
5404 p_H264_Dpb->num_reorder_frames;
5405 hw->max_dec_frame_buffering =
5406 p_H264_Dpb->max_dec_frame_buffering;
5407#endif
5408
5409 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5410 reset_process_time(hw);
5411 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5412 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5413 vdec_schedule_work(&hw->work);
5414 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5415 u16 data_hight;
5416 u16 data_low;
5417 u32 video_signal;
5418
5419 int slice_header_process_status = 0;
5420 int I_flag;
5421 /*unsigned char is_idr;*/
5422 unsigned short *p = (unsigned short *)hw->lmem_addr;
5423 reset_process_time(hw);
5424
5425 if (hw->is_used_v4l) {
5426 struct aml_vcodec_ctx *ctx =
5427 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5428
5429 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5430 //amvdec_stop();
5431 hw->dec_result = DEC_RESULT_DONE;
5432 vdec_schedule_work(&hw->work);
5433 return IRQ_HANDLED;
5434 }
5435 }
5436
5437 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5438 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5439 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5440 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5441 if (input_frame_based(vdec) &&
5442 frmbase_cont_bitlevel2 != 0 &&
5443 READ_VREG(VIFF_BIT_CNT) <
5444 frmbase_cont_bitlevel2 &&
5445 hw->get_data_count >= 0x70000000) {
5446 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5447 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5448 __func__,
5449 READ_VREG(VIFF_BIT_CNT));
5450
5451 goto empty_proc;
5452 }
5453
5454 dma_sync_single_for_cpu(
5455 amports_get_dma_device(),
5456 hw->lmem_addr_remap,
5457 PAGE_SIZE,
5458 DMA_FROM_DEVICE);
5459#if 0
5460 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5461 if (!is_buffer_available(vdec)) {
5462 hw->buffer_empty_flag = 1;
5463 dpb_print(DECODE_ID(hw),
5464 PRINT_FLAG_UCODE_EVT,
5465 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5466 __func__,
5467 kfifo_len(&hw->newframe_q),
5468 have_free_buf_spec(vdec),
5469 p_H264_Dpb->mDPB.init_done,
5470 p_H264_Dpb->mDPB.used_size,
5471 p_H264_Dpb->mDPB.size,
5472 is_there_unused_frame_from_dpb(
5473 &p_H264_Dpb->mDPB));
5474 return IRQ_HANDLED;
5475 }
5476 }
5477
5478 hw->buffer_empty_flag = 0;
5479#endif
5480#ifdef SEND_PARAM_WITH_REG
5481 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5482 unsigned int data32;
5483
5484 do {
5485 data32 = READ_VREG(RPM_CMD_REG);
5486 /* printk("%x\n", data32); */
5487 } while ((data32&0x10000) == 0);
5488 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5489 WRITE_VREG(RPM_CMD_REG, 0);
5490 /* printk("%x:%x\n", i,data32); */
5491 }
5492#else
5493 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5494 int ii;
5495
5496 for (ii = 0; ii < 4; ii++) {
5497 p_H264_Dpb->dpb_param.l.data[i+ii] =
5498 p[i+3-ii];
5499 if (dpb_is_debug(DECODE_ID(hw),
5500 RRINT_FLAG_RPM)) {
5501 if (((i + ii) & 0xf) == 0)
5502 dpb_print(DECODE_ID(hw),
5503 0, "%04x:",
5504 i);
5505 dpb_print_cont(DECODE_ID(hw),
5506 0, "%04x ",
5507 p[i+3-ii]);
5508 if (((i + ii + 1) & 0xf) == 0)
5509 dpb_print_cont(
5510 DECODE_ID(hw),
5511 0, "\r\n");
5512 }
5513 }
5514 }
5515#endif
5516 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5517 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5518
5519 video_signal = (data_hight << 16) | data_low;
5520 hw->video_signal_from_vui =
5521 ((video_signal & 0xffff) << 8) |
5522 ((video_signal & 0xff0000) >> 16) |
5523 ((video_signal & 0x3f000000));
5524
5525
5526 /*dpb_print(DECODE_ID(hw),
5527 0,
5528 "video_signal_from_vui:0x%x, "
5529 "data_low:0x%x, data_hight:0x%x\n",
5530 hw->video_signal_from_vui,
5531 data_low,
5532 data_hight);*/
5533
5534 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5535
5536 if (hw->config_bufmgr_done == 0) {
5537 hw->dec_result = DEC_RESULT_DONE;
5538 vdec_schedule_work(&hw->work);
5539 dpb_print(DECODE_ID(hw),
5540 PRINT_FLAG_UCODE_EVT,
5541 "config_bufmgr not done, discard frame\n");
5542 return IRQ_HANDLED;
5543 } else if ((hw->first_i_policy & 0x3) != 0) {
5544 unsigned char is_i_slice =
5545 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5546 == I_Slice)
5547 ? 1 : 0;
5548 unsigned char is_idr =
5549 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5550 == 5);
5551 if ((hw->first_i_policy & 0x3) == 0x3)
5552 is_i_slice = is_idr;
5553 if (!is_i_slice) {
5554 if (hw->has_i_frame == 0) {
5555 amvdec_stop();
5556 vdec->mc_loaded = 0;
5557 hw->dec_result = DEC_RESULT_DONE;
5558 vdec_schedule_work(&hw->work);
5559 dpb_print(DECODE_ID(hw),
5560 PRINT_FLAG_UCODE_EVT,
5561 "has_i_frame is 0, discard none I(DR) frame\n");
5562 return IRQ_HANDLED;
5563 }
5564 } else {
5565 if (hw->skip_frame_count < 0 || is_idr) {
5566 /* second I */
5567 hw->dec_flag &= (~NODISP_FLAG);
5568 hw->skip_frame_count = 0;
5569 }
5570 if (hw->has_i_frame == 0 &&
5571 (!is_idr)) {
5572 int skip_count =
5573 (hw->first_i_policy >> 8) & 0xff;
5574 /* first I (not IDR) */
5575 if ((hw->first_i_policy & 0x3) == 2)
5576 hw->skip_frame_count =
5577 -1 - skip_count;
5578 else
5579 hw->skip_frame_count =
5580 skip_count;
5581 if (hw->skip_frame_count != 0)
5582 hw->dec_flag |= NODISP_FLAG;
5583 }
5584 }
5585 }
5586 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5587 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5588 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5589 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5590 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5591 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5592 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5593 ? I_FLAG : 0;
5594
5595 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5596 flush_dpb(p_H264_Dpb);
5597
5598 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5599 (p_H264_Dpb->mSlice.structure == FRAME)) {
5600 hw->data_flag = NULL_FLAG;
5601 goto pic_done_proc;
5602 }
5603
5604 slice_header_process_status =
5605 h264_slice_header_process(p_H264_Dpb);
5606 if (hw->mmu_enable)
5607 hevc_sao_set_slice_type(hw,
5608 slice_header_process_status,
5609 hw->dpb.mSlice.idr_flag);
5610 vui_config(hw);
5611
5612 if (p_H264_Dpb->mVideo.dec_picture) {
5613 int cfg_ret = 0;
5614 bool field_pic_flag = false;
5615
5616 if (slice_header_process_status == 1) {
5617 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5618 field_pic_flag =
5619 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5620 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5621 true : false;
5622 }
5623
5624 if (!field_pic_flag && (((p_H264_Dpb->mSPS.profile_idc == BASELINE) &&
5625 (p_H264_Dpb->reorder_pic_num < 2)) ||
5626 (((unsigned long)(hw->vh264_amstream_dec_info
5627 .param)) & 0x8))) {
5628 p_H264_Dpb->fast_output_enable =
5629 H264_OUTPUT_MODE_FAST;
5630 }
5631 else
5632 p_H264_Dpb->fast_output_enable
5633 = fast_output_enable;
5634 hw->data_flag = I_flag;
5635 if ((p_H264_Dpb->
5636 dpb_param.dpb.NAL_info_mmco & 0x1f)
5637 == 5)
5638 hw->data_flag |= IDR_FLAG;
5639 dpb_print(DECODE_ID(hw),
5640 PRINT_FLAG_VDEC_STATUS,
5641 "==================> frame count %d to skip %d\n",
5642 hw->decode_pic_count+1,
5643 hw->skip_frame_count);
5644 } else if (error_proc_policy & 0x100){
5645 struct StorablePicture *p =
5646 p_H264_Dpb->mVideo.dec_picture;
5647 unsigned mby_mbx = READ_VREG(MBY_MBX);
5648 unsigned decode_mb_count =
5649 ((mby_mbx & 0xff) * hw->mb_width +
5650 (((mby_mbx >> 8) & 0xff) + 1));
5651 if (decode_mb_count <
5652 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5653 (1 + p->mb_aff_frame_flag))) {
5654 dpb_print(DECODE_ID(hw),
5655 PRINT_FLAG_VDEC_STATUS,
5656 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5657 p_H264_Dpb->dpb_param.l.
5658 data[FIRST_MB_IN_SLICE],
5659 READ_VREG(MBY_MBX),
5660 decode_mb_count);
5661 p->data_flag |= ERROR_FLAG;
5662 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5663 p->data_flag |= ERROR_FLAG;
5664 goto pic_done_proc;
5665 }
5666 }
5667
5668 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5669 hw->new_iframe_flag = 1;
5670 }
5671 if (hw->new_iframe_flag) {
5672 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5673 hw->new_iframe_flag = 0;
5674 hw->ref_err_flush_dpb_flag = 1;
5675 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5676 hw->new_iframe_flag = 0;
5677 hw->ref_err_flush_dpb_flag = 0;
5678 }
5679 }
5680
5681 if (error_proc_policy & 0x400) {
5682 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5683 if (ret != 0) {
5684 hw->reflist_error_count ++;
5685 dpb_print(DECODE_ID(hw), 0,
5686 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5687 ret,
5688 hw->decode_pic_count+1,
5689 hw->skip_frame_count,
5690 hw->reflist_error_count);
5691
5692 if (hw->ref_err_flush_dpb_flag) {
5693 flush_dpb(p_H264_Dpb);
5694 p_H264_Dpb->colocated_buf_map = 0;
5695 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5696 p_H264_Dpb->colocated_buf_map |= 1 <<
5697 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5698 }
5699 }
5700
5701 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5702 if (((error_proc_policy & 0x80)
5703 && ((hw->dec_flag &
5704 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5705 hw->reset_bufmgr_flag = 1;
5706 hw->reflist_error_count =0;
5707 amvdec_stop();
5708 vdec->mc_loaded = 0;
5709 hw->dec_result = DEC_RESULT_DONE;
5710 vdec_schedule_work(&hw->work);
5711 return IRQ_HANDLED;
5712 }
5713 } else
5714 hw->reflist_error_count = 0;
5715 }
5716 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5717 && p_H264_Dpb->dpb_error_flag != 0) {
5718 dpb_print(DECODE_ID(hw), 0,
5719 "dpb error %d\n",
5720 p_H264_Dpb->dpb_error_flag);
5721 hw->data_flag |= ERROR_FLAG;
5722 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5723 if ((error_proc_policy & 0x80) &&
5724 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5725 hw->reset_bufmgr_flag = 1;
5726 amvdec_stop();
5727 vdec->mc_loaded = 0;
5728 hw->dec_result = DEC_RESULT_DONE;
5729 vdec_schedule_work(&hw->work);
5730 return IRQ_HANDLED;
5731 }
5732 }
5733
5734 cfg_ret = config_decode_buf(hw,
5735 p_H264_Dpb->mVideo.dec_picture);
5736 if (cfg_ret < 0) {
5737 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5738 "config_decode_buf fail (%d)\n",
5739 cfg_ret);
5740 if (error_proc_policy & 0x2) {
5741 release_cur_decoding_buf(hw);
5742 /*hw->data_flag |= ERROR_FLAG;*/
5743 hw->reset_bufmgr_flag = 1;
5744 hw->dec_result = DEC_RESULT_DONE;
5745 vdec_schedule_work(&hw->work);
5746 return IRQ_HANDLED;
5747 } else
5748 hw->data_flag |= ERROR_FLAG;
5749 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5750 }
5751 }
5752
5753 if (slice_header_process_status == 1)
5754 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5755 else
5756 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5757 hw->last_mby_mbx = 0;
5758 hw->last_vld_level = 0;
5759 start_process_time(hw);
5760 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5761 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5762pic_done_proc:
5763 reset_process_time(hw);
5764
5765 if (input_frame_based(vdec) &&
5766 (!(hw->i_only & 0x2)) &&
5767 frmbase_cont_bitlevel != 0 &&
5768 READ_VREG(VIFF_BIT_CNT) >
5769 frmbase_cont_bitlevel) {
5770 /*handle the case: multi pictures in one packet*/
5771 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5772 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5773 __func__,
5774 hw->decode_pic_count,
5775 READ_VREG(VIFF_BIT_CNT));
5776 hw->frmbase_cont_flag = 1;
5777 } else
5778 hw->frmbase_cont_flag = 0;
5779
5780 if (p_H264_Dpb->mVideo.dec_picture) {
5781 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5782#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5783 DEL_EXIST(hw,
5784 p_H264_Dpb->mVideo.dec_picture) = 0;
5785 if (vdec->master) {
5786 struct vdec_h264_hw_s *hw_ba =
5787 (struct vdec_h264_hw_s *)
5788 vdec->master->private;
5789 if (hw_ba->last_dec_picture)
5790 DEL_EXIST(hw_ba,
5791 hw_ba->last_dec_picture)
5792 = 1;
5793 }
5794#endif
5795 mutex_lock(&hw->chunks_mutex);
5796 if (hw->chunk) {
5797 p_H264_Dpb->mVideo.dec_picture->pts =
5798 hw->chunk->pts;
5799 p_H264_Dpb->mVideo.dec_picture->pts64 =
5800 hw->chunk->pts64;
5801 p_H264_Dpb->mVideo.dec_picture->timestamp =
5802 hw->chunk->timestamp;
5803#ifdef MH264_USERDATA_ENABLE
5804 vmh264_udc_fill_vpts(hw,
5805 p_H264_Dpb->mSlice.slice_type,
5806 hw->chunk->pts, 1);
5807#endif
5808
5809#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5810 } else if (vdec->master) {
5811 /*dv enhance layer,
5812 do not checkout pts*/
5813 struct StorablePicture *pic =
5814 p_H264_Dpb->mVideo.dec_picture;
5815 pic->pts = 0;
5816 pic->pts64 = 0;
5817#endif
5818 } else {
5819 struct StorablePicture *pic =
5820 p_H264_Dpb->mVideo.dec_picture;
5821 u32 offset = pic->offset_delimiter;
5822 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5823 offset, &pic->pts, 0, &pic->pts64)) {
5824 pic->pts = 0;
5825 pic->pts64 = 0;
5826#ifdef MH264_USERDATA_ENABLE
5827 vmh264_udc_fill_vpts(hw,
5828 p_H264_Dpb->mSlice.slice_type,
5829 pic->pts, 0);
5830#endif
5831 } else {
5832#ifdef MH264_USERDATA_ENABLE
5833 vmh264_udc_fill_vpts(hw,
5834 p_H264_Dpb->mSlice.slice_type,
5835 pic->pts, 1);
5836#endif
5837 }
5838
5839 }
5840 mutex_unlock(&hw->chunks_mutex);
5841
5842 check_decoded_pic_error(hw);
5843#ifdef ERROR_HANDLE_TEST
5844 if ((hw->data_flag & ERROR_FLAG)
5845 && (error_proc_policy & 0x80)) {
5846 release_cur_decoding_buf(hw);
5847 h264_clear_dpb(hw);
5848 hw->dec_flag = 0;
5849 hw->data_flag = 0;
5850 hw->skip_frame_count = 0;
5851 hw->has_i_frame = 0;
5852 hw->no_error_count = 0xfff;
5853 hw->no_error_i_count = 0xf;
5854 } else
5855#endif
5856 ret = store_picture_in_dpb(p_H264_Dpb,
5857 p_H264_Dpb->mVideo.dec_picture,
5858 hw->data_flag | hw->dec_flag |
5859 p_H264_Dpb->mVideo.dec_picture->data_flag);
5860
5861
5862
5863 if (ret == -1) {
5864 release_cur_decoding_buf(hw);
5865 bufmgr_force_recover(p_H264_Dpb);
5866 } else {
5867 if (hw->data_flag & ERROR_FLAG) {
5868 hw->no_error_count = 0;
5869 hw->no_error_i_count = 0;
5870 } else {
5871 hw->no_error_count++;
5872 if (hw->data_flag & I_FLAG)
5873 hw->no_error_i_count++;
5874 }
5875 if (hw->mmu_enable)
5876 hevc_set_unused_4k_buff_idx(hw,
5877 p_H264_Dpb->mVideo.
5878 dec_picture->buf_spec_num);
5879 bufmgr_post(p_H264_Dpb);
5880 hw->last_dec_picture =
5881 p_H264_Dpb->mVideo.dec_picture;
5882 p_H264_Dpb->mVideo.dec_picture = NULL;
5883 /* dump_dpb(&p_H264_Dpb->mDPB); */
5884 hw->has_i_frame = 1;
5885 if (hw->mmu_enable)
5886 hevc_set_frame_done(hw);
5887 hw->decode_pic_count++;
5888 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5889 if (hw->skip_frame_count > 0) {
5890 /*skip n frame after first I */
5891 hw->skip_frame_count--;
5892 if (hw->skip_frame_count == 0)
5893 hw->dec_flag &= (~NODISP_FLAG);
5894 } else if (hw->skip_frame_count < -1) {
5895 /*skip n frame after first I until second I */
5896 hw->skip_frame_count++;
5897 if (hw->skip_frame_count == -1)
5898 hw->dec_flag &= (~NODISP_FLAG);
5899 }
5900 }
5901 }
5902 if (hw->frmbase_cont_flag) {
5903 /*do not DEC_RESULT_GET_DATA*/
5904 hw->get_data_count = 0x7fffffff;
5905 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5906 decode_frame_count[DECODE_ID(hw)]++;
5907 start_process_time(hw);
5908 return IRQ_HANDLED;
5909 }
5910 amvdec_stop();
5911 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5912 "%s %s decode slice count %d\n",
5913 __func__,
5914 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5915 "H264_PIC_DATA_DONE" :
5916 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5917 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5918 hw->decode_pic_count);
5919 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5920 hw->dec_result = DEC_RESULT_DONE;
5921#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5922 if (vdec->slave &&
5923 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5924 struct vdec_h264_hw_s *hw_el =
5925 (struct vdec_h264_hw_s *)(vdec->slave->private);
5926 hw_el->got_valid_nal = 0;
5927 hw->switch_dvlayer_flag = 1;
5928 } else if (vdec->master &&
5929 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5930 struct vdec_h264_hw_s *hw_bl =
5931 (struct vdec_h264_hw_s *)(vdec->master->private);
5932 hw_bl->got_valid_nal = 0;
5933 hw->switch_dvlayer_flag = 1;
5934 } else {
5935 hw->switch_dvlayer_flag = 0;
5936 hw->got_valid_nal = 1;
5937 }
5938#endif
5939
5940 hw->dec_result = DEC_RESULT_DONE;
5941 vdec_schedule_work(&hw->work);
5942
5943#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5944 } else if (
5945 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5946 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5947 goto pic_done_proc;
5948#endif
5949 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5950 reset_process_time(hw);
5951 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5952 dma_sync_single_for_cpu(
5953 amports_get_dma_device(),
5954 hw->aux_phy_addr,
5955 hw->prefix_aux_size + hw->suffix_aux_size,
5956 DMA_FROM_DEVICE);
5957 if (dpb_is_debug(DECODE_ID(hw),
5958 PRINT_FLAG_DPB_DETAIL))
5959 dump_aux_buf(hw);
5960#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5961 if (vdec->dolby_meta_with_el || vdec->slave) {
5962 if (hw->last_dec_picture)
5963 set_aux_data(hw, hw->last_dec_picture,
5964 0, 0, NULL);
5965 } else {
5966 if (vdec->master) {
5967 struct vdec_h264_hw_s *hw_bl =
5968 (struct vdec_h264_hw_s *)
5969 (vdec->master->private);
5970 if (hw_bl->last_dec_picture != NULL) {
5971 set_aux_data(hw_bl,
5972 hw_bl->last_dec_picture,
5973 0, 1, hw);
5974 }
5975 set_aux_data(hw,
5976 hw->last_dec_picture,
5977 0, 2, NULL);
5978 }
5979 }
5980#else
5981 if (hw->last_dec_picture)
5982 set_aux_data(hw,
5983 hw->last_dec_picture, 0, 0, NULL);
5984#endif
5985 }
5986#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5987 hw->switch_dvlayer_flag = 0;
5988 hw->got_valid_nal = 1;
5989#endif
5990 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5991 "%s H264_AUX_DATA_READY\n", __func__);
5992 hw->dec_result = DEC_RESULT_DONE;
5993 vdec_schedule_work(&hw->work);
5994 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5995 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5996 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5997 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5998empty_proc:
5999 reset_process_time(hw);
6000 if (!hw->frmbase_cont_flag)
6001 release_cur_decoding_buf(hw);
6002
6003 if (input_frame_based(vdec) ||
6004 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6005 if (h264_debug_flag &
6006 DISABLE_ERROR_HANDLE) {
6007 dpb_print(DECODE_ID(hw),
6008 PRINT_FLAG_ERROR,
6009 "%s decoding error, level 0x%x\n",
6010 __func__,
6011 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6012 goto send_again;
6013 }
6014 amvdec_stop();
6015 vdec->mc_loaded = 0;
6016 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6017 "%s %s\n", __func__,
6018 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6019 "H264_SEARCH_BUFEMPTY" :
6020 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6021 "H264_DECODE_BUFEMPTY" :
6022 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6023 "H264_DECODE_TIMEOUT" :
6024 "OTHER");
6025 hw->dec_result = DEC_RESULT_DONE;
6026
6027 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6028 hw->search_dataempty_num++;
6029 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6030 hw->decode_timeout_num++;
6031 if (error_proc_policy & 0x4000) {
6032 hw->data_flag |= ERROR_FLAG;
6033 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6034 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6035 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6036 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6037 dpb_print(DECODE_ID(hw),
6038 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6039 p_H264_Dpb->last_dpb_status, __func__);
6040 hw->reset_bufmgr_flag = 1;
6041 }
6042 }
6043 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6044 hw->decode_dataempty_num++;
6045 if (!hw->frmbase_cont_flag)
6046 hw->data_flag |= ERROR_FLAG;
6047
6048 vdec_schedule_work(&hw->work);
6049 } else {
6050 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6051 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6052 "%s DEC_RESULT_AGAIN\n", __func__);
6053send_again:
6054 hw->dec_result = DEC_RESULT_AGAIN;
6055 vdec_schedule_work(&hw->work);
6056 }
6057 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6058 reset_process_time(hw);
6059 if (input_frame_based(vdec)) {
6060 dpb_print(DECODE_ID(hw),
6061 PRINT_FLAG_VDEC_STATUS,
6062 "%s H264_DATA_REQUEST (%d)\n",
6063 __func__, hw->get_data_count);
6064 hw->dec_result = DEC_RESULT_GET_DATA;
6065 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6066 hw->get_data_start_time = jiffies;
6067 hw->get_data_count++;
6068 if (hw->get_data_count >= frame_max_data_packet)
6069 goto empty_proc;
6070 vdec_schedule_work(&hw->work);
6071 } else
6072 goto empty_proc;
6073 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6074 dpb_print(DECODE_ID(hw), 0,
6075 "vmh264 decode oversize !!\n");
6076 release_cur_decoding_buf(hw);
6077 hw->data_flag |= ERROR_FLAG;
6078 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6079 reset_process_time(hw);
6080 hw->dec_result = DEC_RESULT_DONE;
6081 vdec_schedule_work(&hw->work);
6082 return IRQ_HANDLED;
6083 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6084 int aux_data_len;
6085 aux_data_len =
6086 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6087
6088 if (aux_data_len > SEI_DATA_SIZE) {
6089 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6090 "sei data size more than 4K: %d, discarded it\n",
6091 hw->sei_itu_data_len);
6092 hw->sei_itu_data_len = 0;
6093 }
6094
6095 if (aux_data_len != 0) {
6096 u8 *trans_data_buf;
6097 u8 *sei_data_buf;
6098 u8 swap_byte;
6099
6100 dma_sync_single_for_cpu(
6101 amports_get_dma_device(),
6102 hw->aux_phy_addr,
6103 hw->prefix_aux_size + hw->suffix_aux_size,
6104 DMA_FROM_DEVICE);
6105#if 0
6106 dump_aux_buf(hw);
6107#endif
6108 trans_data_buf = (u8 *)hw->aux_addr;
6109
6110 if (trans_data_buf[7] == AUX_TAG_SEI) {
6111 int left_len;
6112
6113 sei_data_buf = (u8 *)hw->sei_data_buf
6114 + hw->sei_data_len;
6115 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6116 if (aux_data_len/2 <= left_len) {
6117 for (i = 0; i < aux_data_len/2; i++)
6118 sei_data_buf[i]
6119 = trans_data_buf[i*2];
6120
6121 aux_data_len = aux_data_len / 2;
6122 for (i = 0; i < aux_data_len; i = i+4) {
6123 swap_byte = sei_data_buf[i];
6124 sei_data_buf[i]
6125 = sei_data_buf[i+3];
6126 sei_data_buf[i+3] = swap_byte;
6127
6128 swap_byte = sei_data_buf[i+1];
6129 sei_data_buf[i+1]
6130 = sei_data_buf[i+2];
6131 sei_data_buf[i+2] = swap_byte;
6132 }
6133
6134 for (i = aux_data_len-1; i >= 0; i--)
6135 if (sei_data_buf[i] != 0)
6136 break;
6137
6138 hw->sei_data_len += i+1;
6139 } else
6140 dpb_print(DECODE_ID(hw),
6141 PRINT_FLAG_ERROR,
6142 "sei data size %d and more than left space: %d, discarded it\n",
6143 hw->sei_itu_data_len,
6144 left_len);
6145 }
6146 }
6147 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6148
6149 return IRQ_HANDLED;
6150 }
6151
6152
6153 /* ucode debug */
6154 debug_tag = READ_VREG(DEBUG_REG1);
6155 if (debug_tag & 0x10000) {
6156 unsigned short *p = (unsigned short *)hw->lmem_addr;
6157
6158 dma_sync_single_for_cpu(
6159 amports_get_dma_device(),
6160 hw->lmem_addr_remap,
6161 PAGE_SIZE,
6162 DMA_FROM_DEVICE);
6163
6164 dpb_print(DECODE_ID(hw), 0,
6165 "LMEM<tag %x>:\n", debug_tag);
6166 for (i = 0; i < 0x400; i += 4) {
6167 int ii;
6168 if ((i & 0xf) == 0)
6169 dpb_print_cont(DECODE_ID(hw), 0,
6170 "%03x: ", i);
6171 for (ii = 0; ii < 4; ii++)
6172 dpb_print_cont(DECODE_ID(hw), 0,
6173 "%04x ", p[i+3-ii]);
6174 if (((i+ii) & 0xf) == 0)
6175 dpb_print_cont(DECODE_ID(hw), 0,
6176 "\n");
6177 }
6178 if (((udebug_pause_pos & 0xffff)
6179 == (debug_tag & 0xffff)) &&
6180 (udebug_pause_decode_idx == 0 ||
6181 udebug_pause_decode_idx ==
6182 hw->decode_pic_count) &&
6183 (udebug_pause_val == 0 ||
6184 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6185 udebug_pause_pos &= 0xffff;
6186 hw->ucode_pause_pos = udebug_pause_pos;
6187 }
6188 else if (debug_tag & 0x20000)
6189 hw->ucode_pause_pos = 0xffffffff;
6190 if (hw->ucode_pause_pos)
6191 reset_process_time(hw);
6192 else
6193 WRITE_VREG(DEBUG_REG1, 0);
6194 } else if (debug_tag != 0) {
6195 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6196 "dbg%x: %x\n", debug_tag,
6197 READ_VREG(DEBUG_REG2));
6198 if (((udebug_pause_pos & 0xffff)
6199 == (debug_tag & 0xffff)) &&
6200 (udebug_pause_decode_idx == 0 ||
6201 udebug_pause_decode_idx ==
6202 hw->decode_pic_count) &&
6203 (udebug_pause_val == 0 ||
6204 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6205 udebug_pause_pos &= 0xffff;
6206 hw->ucode_pause_pos = udebug_pause_pos;
6207 }
6208 if (hw->ucode_pause_pos)
6209 reset_process_time(hw);
6210 else
6211 WRITE_VREG(DEBUG_REG1, 0);
6212 }
6213 /**/
6214 return IRQ_HANDLED;
6215}
6216
6217static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6218{
6219 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6220 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6221
6222
6223 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6224
6225 if (!hw)
6226 return IRQ_HANDLED;
6227
6228 if (hw->eos)
6229 return IRQ_HANDLED;
6230
6231 p_H264_Dpb->vdec = vdec;
6232 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6233
6234 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6235 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6236 __func__,
6237 p_H264_Dpb->dec_dpb_status,
6238 READ_VREG(ERROR_STATUS_REG),
6239 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6240 READ_VREG(VLD_MEM_VIFIFO_WP),
6241 READ_VREG(VLD_MEM_VIFIFO_RP),
6242 READ_VREG(VIFF_BIT_CNT),
6243 READ_VREG(MBY_MBX));
6244
6245 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6246 if (hw->mmu_enable)
6247 hevc_sao_wait_done(hw);
6248 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6249 return IRQ_HANDLED;
6250 }
6251 return IRQ_WAKE_THREAD;
6252
6253}
6254
6255static void timeout_process(struct vdec_h264_hw_s *hw)
6256{
6257 struct vdec_s *vdec = hw_to_vdec(hw);
6258 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6259
6260 /*
6261 * In this very timeout point,the vh264_work arrives,
6262 * let it to handle the scenario.
6263 */
6264 if (work_pending(&hw->work))
6265 return;
6266
6267 hw->timeout_num++;
6268 amvdec_stop();
6269 vdec->mc_loaded = 0;
6270 if (hw->mmu_enable) {
6271 hevc_set_frame_done(hw);
6272 hevc_sao_wait_done(hw);
6273 }
6274 if (!hw->i_only && (error_proc_policy & 0x2))
6275 flush_dpb(p_H264_Dpb);
6276 dpb_print(DECODE_ID(hw),
6277 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6278 release_cur_decoding_buf(hw);
6279 hw->dec_result = DEC_RESULT_DONE;
6280 hw->data_flag |= ERROR_FLAG;
6281
6282 if (work_pending(&hw->work))
6283 return;
6284 vdec_schedule_work(&hw->timeout_work);
6285}
6286
6287static void dump_bufspec(struct vdec_h264_hw_s *hw,
6288 const char *caller)
6289{
6290 int i;
6291 dpb_print(DECODE_ID(hw), 0,
6292 "%s in %s:\n", __func__, caller);
6293 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6294 if (hw->buffer_spec[i].used == -1)
6295 continue;
6296 dpb_print(DECODE_ID(hw), 0,
6297 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6298 i, hw->buffer_spec[i].used,
6299 hw->buffer_spec[i].buf_adr,
6300 hw->buffer_spec[i].canvas_pos,
6301 hw->buffer_spec[i].vf_ref
6302 );
6303#ifdef CONFIG_AM_VDEC_DV
6304 dpb_print_cont(DECODE_ID(hw), 0,
6305 "dv_el_exist %d",
6306 hw->buffer_spec[i].dv_enhance_exist
6307 );
6308#endif
6309 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6310 }
6311
6312}
6313
6314static void vmh264_dump_state(struct vdec_s *vdec)
6315{
6316 struct vdec_h264_hw_s *hw =
6317 (struct vdec_h264_hw_s *)(vdec->private);
6318 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6319 dpb_print(DECODE_ID(hw), 0,
6320 "====== %s\n", __func__);
6321 dpb_print(DECODE_ID(hw), 0,
6322 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6323 hw->frame_width,
6324 hw->frame_height,
6325 hw->dpb.reorder_pic_num,
6326 hw->dpb.mDPB.size,
6327 hw->max_reference_size,
6328 hw->i_only,
6329 hw->send_error_frame_flag
6330 );
6331
6332 dpb_print(DECODE_ID(hw), 0,
6333 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6334 input_frame_based(vdec),
6335 hw->eos,
6336 hw->stat,
6337 hw->dec_result,
6338 decode_frame_count[DECODE_ID(hw)],
6339 display_frame_count[DECODE_ID(hw)],
6340 run_count[DECODE_ID(hw)],
6341 not_run_ready[DECODE_ID(hw)],
6342 input_empty[DECODE_ID(hw)],
6343 hw->reset_bufmgr_count
6344 );
6345
6346 if (vf_get_receiver(vdec->vf_provider_name)) {
6347 enum receviver_start_e state =
6348 vf_notify_receiver(vdec->vf_provider_name,
6349 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6350 NULL);
6351 dpb_print(DECODE_ID(hw), 0,
6352 "\nreceiver(%s) state %d\n",
6353 vdec->vf_provider_name,
6354 state);
6355 }
6356
6357 dpb_print(DECODE_ID(hw), 0,
6358 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x wait_reset_done_flag %d\n",
6359 __func__,
6360 kfifo_len(&hw->newframe_q),
6361 VF_POOL_SIZE,
6362 kfifo_len(&hw->display_q),
6363 VF_POOL_SIZE,
6364 hw->vf_pre_count,
6365 hw->vf_get_count,
6366 hw->vf_put_count,
6367 have_free_buf_spec(vdec),
6368 p_H264_Dpb->mDPB.init_done,
6369 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6370 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6371 p_H264_Dpb->fast_output_enable,
6372 hw->wait_reset_done_flag
6373 );
6374
6375 dump_dpb(&p_H264_Dpb->mDPB, 1);
6376 dump_pic(p_H264_Dpb);
6377 dump_bufspec(hw, __func__);
6378
6379 dpb_print(DECODE_ID(hw), 0,
6380 "DPB_STATUS_REG=0x%x\n",
6381 READ_VREG(DPB_STATUS_REG));
6382 dpb_print(DECODE_ID(hw), 0,
6383 "MPC_E=0x%x\n",
6384 READ_VREG(MPC_E));
6385 dpb_print(DECODE_ID(hw), 0,
6386 "H264_DECODE_MODE=0x%x\n",
6387 READ_VREG(H264_DECODE_MODE));
6388 dpb_print(DECODE_ID(hw), 0,
6389 "MBY_MBX=0x%x\n",
6390 READ_VREG(MBY_MBX));
6391 dpb_print(DECODE_ID(hw), 0,
6392 "H264_DECODE_SIZE=0x%x\n",
6393 READ_VREG(H264_DECODE_SIZE));
6394 dpb_print(DECODE_ID(hw), 0,
6395 "VIFF_BIT_CNT=0x%x\n",
6396 READ_VREG(VIFF_BIT_CNT));
6397 dpb_print(DECODE_ID(hw), 0,
6398 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6399 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6400 dpb_print(DECODE_ID(hw), 0,
6401 "VLD_MEM_VIFIFO_WP=0x%x\n",
6402 READ_VREG(VLD_MEM_VIFIFO_WP));
6403 dpb_print(DECODE_ID(hw), 0,
6404 "VLD_MEM_VIFIFO_RP=0x%x\n",
6405 READ_VREG(VLD_MEM_VIFIFO_RP));
6406 dpb_print(DECODE_ID(hw), 0,
6407 "PARSER_VIDEO_RP=0x%x\n",
6408 READ_PARSER_REG(PARSER_VIDEO_RP));
6409 dpb_print(DECODE_ID(hw), 0,
6410 "PARSER_VIDEO_WP=0x%x\n",
6411 READ_PARSER_REG(PARSER_VIDEO_WP));
6412
6413 if (input_frame_based(vdec) &&
6414 dpb_is_debug(DECODE_ID(hw),
6415 PRINT_FRAMEBASE_DATA)
6416 ) {
6417 int jj;
6418 if (hw->chunk && hw->chunk->block &&
6419 hw->chunk->size > 0) {
6420 u8 *data = NULL;
6421
6422 if (!hw->chunk->block->is_mapped)
6423 data = codec_mm_vmap(hw->chunk->block->start +
6424 hw->chunk->offset, hw->chunk->size);
6425 else
6426 data = ((u8 *)hw->chunk->block->start_virt)
6427 + hw->chunk->offset;
6428
6429 dpb_print(DECODE_ID(hw), 0,
6430 "frame data size 0x%x\n",
6431 hw->chunk->size);
6432 for (jj = 0; jj < hw->chunk->size; jj++) {
6433 if ((jj & 0xf) == 0)
6434 dpb_print(DECODE_ID(hw),
6435 PRINT_FRAMEBASE_DATA,
6436 "%06x:", jj);
6437 dpb_print_cont(DECODE_ID(hw),
6438 PRINT_FRAMEBASE_DATA,
6439 "%02x ", data[jj]);
6440 if (((jj + 1) & 0xf) == 0)
6441 dpb_print_cont(DECODE_ID(hw),
6442 PRINT_FRAMEBASE_DATA,
6443 "\n");
6444 }
6445
6446 if (!hw->chunk->block->is_mapped)
6447 codec_mm_unmap_phyaddr(data);
6448 }
6449 }
6450}
6451
6452
6453static void check_timer_func(unsigned long arg)
6454{
6455 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6456 struct vdec_s *vdec = hw_to_vdec(hw);
6457 int error_skip_frame_count = error_skip_count & 0xfff;
6458 unsigned int timeout_val = decode_timeout_val;
6459 if (timeout_val != 0 &&
6460 hw->no_error_count < error_skip_frame_count)
6461 timeout_val = errordata_timeout_val;
6462 if ((h264_debug_cmd & 0x100) != 0 &&
6463 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6464 hw->dec_result = DEC_RESULT_DONE;
6465 vdec_schedule_work(&hw->work);
6466 pr_info("vdec %d is forced to be disconnected\n",
6467 h264_debug_cmd & 0xff);
6468 h264_debug_cmd = 0;
6469 return;
6470 }
6471 if ((h264_debug_cmd & 0x200) != 0 &&
6472 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6473 pr_debug("vdec %d is forced to reset bufmgr\n",
6474 h264_debug_cmd & 0xff);
6475 hw->reset_bufmgr_flag = 1;
6476 h264_debug_cmd = 0;
6477 return;
6478 }
6479
6480 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6481 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6482 vdec_schedule_work(&hw->work);
6483 pr_debug("vdec requested to be disconnected\n");
6484 return;
6485 }
6486
6487 if (radr != 0) {
6488 if (rval != 0) {
6489 WRITE_VREG(radr, rval);
6490 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6491 } else
6492 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6493 rval = 0;
6494 radr = 0;
6495 }
6496
6497 if ((input_frame_based(vdec) ||
6498 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6499 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6500 (timeout_val > 0) &&
6501 (hw->start_process_time > 0) &&
6502 ((1000 * (jiffies - hw->start_process_time) / HZ)
6503 > timeout_val)
6504 ) {
6505 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6506 u32 mby_mbx = READ_VREG(MBY_MBX);
6507 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6508 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6509 if (hw->last_mby_mbx == mby_mbx) {
6510 if (hw->decode_timeout_count > 0)
6511 hw->decode_timeout_count--;
6512 if (hw->decode_timeout_count == 0)
6513 {
6514 reset_process_time(hw);
6515 timeout_process(hw);
6516 }
6517 } else
6518 start_process_time(hw);
6519 } else if (is_in_parsing_state(dpb_status)) {
6520 if (hw->last_vld_level ==
6521 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6522 if (hw->decode_timeout_count > 0)
6523 hw->decode_timeout_count--;
6524 if (hw->decode_timeout_count == 0)
6525 {
6526 reset_process_time(hw);
6527 timeout_process(hw);
6528 }
6529 }
6530 }
6531 hw->last_vld_level =
6532 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6533 hw->last_mby_mbx = mby_mbx;
6534 }
6535
6536 if ((hw->ucode_pause_pos != 0) &&
6537 (hw->ucode_pause_pos != 0xffffffff) &&
6538 udebug_pause_pos != hw->ucode_pause_pos) {
6539 hw->ucode_pause_pos = 0;
6540 WRITE_VREG(DEBUG_REG1, 0);
6541 }
6542
6543 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6544}
6545
6546static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6547{
6548 u32 ar;
6549 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6550
6551 if (!hw)
6552 return -1;
6553
6554 vstatus->frame_width = hw->frame_width;
6555 vstatus->frame_height = hw->frame_height;
6556 if (hw->frame_dur != 0)
6557 vstatus->frame_rate = 96000 / hw->frame_dur;
6558 else
6559 vstatus->frame_rate = -1;
6560 vstatus->error_count = 0;
6561 vstatus->status = hw->stat;
6562 if (hw->h264_ar == 0x3ff)
6563 hw->h264_ar = (0x100 *
6564 hw->frame_height * hw->height_aspect_ratio) /
6565 (hw->frame_width * hw->width_aspect_ratio);
6566 ar = min_t(u32,
6567 hw->h264_ar,
6568 DISP_RATIO_ASPECT_RATIO_MAX);
6569 vstatus->ratio_control =
6570 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6571
6572 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6573 "%s-%02d", DRIVER_NAME, hw->id);
6574
6575 return 0;
6576}
6577
6578static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6579{
6580 int i, j;
6581 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6582
6583 /* if (hw->init_flag == 0) { */
6584 if (h264_debug_flag & 0x40000000) {
6585 /* if (1) */
6586 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6587 "%s, reset register\n", __func__);
6588
6589 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6590 ;
6591 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6592 ; /* reg address is 0x350 */
6593
6594#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6595 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6596 WRITE_VREG(DOS_SW_RESET0, 0);
6597
6598 READ_VREG(DOS_SW_RESET0);
6599 READ_VREG(DOS_SW_RESET0);
6600 READ_VREG(DOS_SW_RESET0);
6601
6602 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6603 WRITE_VREG(DOS_SW_RESET0, 0);
6604
6605 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6606 WRITE_VREG(DOS_SW_RESET0, 0);
6607
6608 READ_VREG(DOS_SW_RESET0);
6609 READ_VREG(DOS_SW_RESET0);
6610 READ_VREG(DOS_SW_RESET0);
6611
6612#else
6613 WRITE_RESET_REG(RESET0_REGISTER,
6614 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6615 READ_RESET_REG(RESET0_REGISTER);
6616 WRITE_RESET_REG(RESET0_REGISTER,
6617 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6618
6619 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6620#endif
6621 WRITE_VREG(POWER_CTL_VLD,
6622 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6623 (1 << 9) | (1 << 6));
6624 } else {
6625 /* WRITE_VREG(POWER_CTL_VLD,
6626 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6627 */
6628 WRITE_VREG(POWER_CTL_VLD,
6629 READ_VREG(POWER_CTL_VLD) |
6630 (0 << 10) | (1 << 9) | (1 << 6));
6631 }
6632 /* disable PSCALE for hardware sharing */
6633 WRITE_VREG(PSCALE_CTRL, 0);
6634
6635 /* clear mailbox interrupt */
6636 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6637
6638 /* enable mailbox interrupt */
6639 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6640
6641#ifdef NV21
6642 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6643#endif
6644
6645 /* cbcr_merge_swap_en */
6646 if (hw->is_used_v4l
6647 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6648 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6649 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6650
6651 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6652 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6653
6654 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6655 if (hw->mmu_enable) {
6656 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6657 /* sw reset to extif hardware */
6658 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6659 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6660 } else {
6661 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6662 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6663 }
6664
6665
6666#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6667 /* pr_info("vh264 meson8 prot init\n"); */
6668 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6669#endif
6670
6671#ifdef VDEC_DW
6672 if (IS_VDEC_DW(hw)) {
6673 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6674
6675 if (IS_VDEC_DW(hw) == 2)
6676 data |= (1 << 9);
6677 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6678 }
6679#endif
6680 if (hw->dpb.mDPB.size > 0) {
6681 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6682 (hw->dpb.mDPB.size << 16) |
6683 (hw->dpb.mDPB.size << 8));
6684
6685 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6686 i = get_buf_spec_by_canvas_pos(hw, j);
6687 if (i < 0)
6688 break;
6689
6690 if (!hw->mmu_enable &&
6691 hw->buffer_spec[i].cma_alloc_addr)
6692 config_decode_canvas(hw, i);
6693 if (hw->mmu_enable && hw->double_write_mode)
6694 config_decode_canvas_ex(hw, i);
6695 }
6696 } else {
6697 WRITE_VREG(AV_SCRATCH_0, 0);
6698 WRITE_VREG(AV_SCRATCH_9, 0);
6699 }
6700
6701 if (hw->init_flag == 0)
6702 WRITE_VREG(DPB_STATUS_REG, 0);
6703 else
6704 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6705
6706 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6707 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6708 if (!tee_enabled())
6709 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6710
6711 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6712 * error_recovery_mode : error_recovery_mode_in;
6713 */
6714 /* WRITE_VREG(AV_SCRATCH_F,
6715 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6716 */
6717 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6718 ((error_recovery_mode_in & 0x1) << 4));
6719 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6720 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6721 else*/
6722 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6723
6724 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6725#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6726 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6727#endif
6728
6729 WRITE_VREG(DEBUG_REG1, 0);
6730 WRITE_VREG(DEBUG_REG2, 0);
6731
6732 if (hw->reg_iqidct_control)
6733 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6734 if (hw->reg_vcop_ctrl_reg)
6735 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6736 if (hw->vld_dec_control)
6737 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6738 return 0;
6739}
6740
6741static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6742{
6743 struct vdec_h264_hw_s *hw =
6744 (struct vdec_h264_hw_s *)vdec->private;
6745 if (i_only_flag & 0x100)
6746 return 0;
6747 if (trickmode == TRICKMODE_I)
6748 hw->i_only = 0x3;
6749 else if (trickmode == TRICKMODE_NONE)
6750 hw->i_only = 0x0;
6751 return 0;
6752}
6753
6754static unsigned char amvdec_enable_flag;
6755static void vh264_local_init(struct vdec_h264_hw_s *hw)
6756{
6757 int i;
6758 hw->init_flag = 0;
6759 hw->first_sc_checked= 0;
6760 hw->eos = 0;
6761 hw->valve_count = 0;
6762 hw->config_bufmgr_done = 0;
6763 hw->start_process_time = 0;
6764 hw->has_i_frame = 0;
6765 hw->no_error_count = 0xfff;
6766 hw->no_error_i_count = 0xf;
6767
6768 hw->dec_flag = 0;
6769 hw->data_flag = 0;
6770 hw->skip_frame_count = 0;
6771 hw->reg_iqidct_control = 0;
6772 hw->reg_vcop_ctrl_reg = 0;
6773 hw->reg_rv_ai_mb_count = 0;
6774 hw->vld_dec_control = 0;
6775 hw->decode_timeout_count = 0;
6776 hw->no_mem_count = 0;
6777 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6778 /* vh264_ratio = 0x100; */
6779
6780 hw->vh264_rotation = (((unsigned long)
6781 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6782
6783 hw->frame_prog = 0;
6784 hw->frame_width = hw->vh264_amstream_dec_info.width;
6785 hw->frame_height = hw->vh264_amstream_dec_info.height;
6786 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6787 hw->pts_outside = ((unsigned long)
6788 hw->vh264_amstream_dec_info.param) & 0x01;
6789 hw->sync_outside = ((unsigned long)
6790 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6791 hw->use_idr_framerate = ((unsigned long)
6792 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6793 hw->max_refer_buf = !(((unsigned long)
6794 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6795 if (hw->frame_dur < 96000/960) {
6796 /*more than 960fps,it should not be a correct value,
6797 *give default 30fps
6798 */
6799 hw->frame_dur = 96000/30;
6800 }
6801
6802 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6803
6804 hw->first_i_policy = first_i_policy;
6805
6806 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6807 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6808 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6809 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6810
6811 if (i_only_flag & 0x100)
6812 hw->i_only = i_only_flag & 0xff;
6813 if (hw->i_only)
6814 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6815
6816 if ((unsigned long) hw->vh264_amstream_dec_info.param
6817 & 0x08)
6818 hw->no_poc_reorder_flag = 1;
6819
6820 error_recovery_mode_in = 1; /*ucode control?*/
6821 if (error_proc_policy & 0x80000000)
6822 hw->send_error_frame_flag = error_proc_policy & 0x1;
6823 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6824 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6825
6826 INIT_KFIFO(hw->display_q);
6827 INIT_KFIFO(hw->newframe_q);
6828
6829 for (i = 0; i < VF_POOL_SIZE; i++) {
6830 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6831 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6832 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6833 kfifo_put(&hw->newframe_q, vf);
6834 }
6835
6836 hw->duration_from_pts_done = 0;
6837
6838 hw->p_last_vf = NULL;
6839 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6840 hw->hevc_cur_buf_idx = 0xffff;
6841
6842 init_waitqueue_head(&hw->wait_q);
6843
6844 return;
6845}
6846
6847static s32 vh264_init(struct vdec_h264_hw_s *hw)
6848{
6849 int size = -1;
6850 int fw_size = 0x1000 * 16;
6851 int fw_mmu_size = 0x1000 * 16;
6852 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6853
6854 /* int trickmode_fffb = 0; */
6855
6856 /* pr_info("\nvh264_init\n"); */
6857 /* init_timer(&hw->recycle_timer); */
6858
6859 /* timer init */
6860 init_timer(&hw->check_timer);
6861
6862 hw->check_timer.data = (unsigned long)hw;
6863 hw->check_timer.function = check_timer_func;
6864 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6865
6866 /* add_timer(&hw->check_timer); */
6867 hw->stat |= STAT_TIMER_ARM;
6868 hw->stat |= STAT_ISR_REG;
6869
6870 mutex_init(&hw->chunks_mutex);
6871 vh264_local_init(hw);
6872 INIT_WORK(&hw->work, vh264_work);
6873 INIT_WORK(&hw->notify_work, vh264_notify_work);
6874 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6875#ifdef MH264_USERDATA_ENABLE
6876 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6877#endif
6878
6879 if (!amvdec_enable_flag) {
6880 amvdec_enable_flag = true;
6881 amvdec_enable();
6882 if (hw->mmu_enable)
6883 amhevc_enable();
6884 }
6885 if (hw->mmu_enable) {
6886
6887 hw->frame_mmu_map_addr =
6888 dma_alloc_coherent(amports_get_dma_device(),
6889 FRAME_MMU_MAP_SIZE,
6890 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6891 if (hw->frame_mmu_map_addr == NULL) {
6892 pr_err("%s: failed to alloc count_buffer\n", __func__);
6893 return -ENOMEM;
6894 }
6895 }
6896
6897 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6898 if (IS_ERR_OR_NULL(fw))
6899 return -ENOMEM;
6900
6901 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6902 if (size < 0) {
6903 pr_err("get firmware fail.\n");
6904 vfree(fw);
6905 return -1;
6906 }
6907
6908 fw->len = size;
6909 hw->fw = fw;
6910
6911 if (hw->mmu_enable) {
6912 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6913 if (IS_ERR_OR_NULL(fw_mmu))
6914 return -ENOMEM;
6915
6916 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6917 if (size < 0) {
6918 pr_err("get mmu fw fail.\n");
6919 vfree(fw_mmu);
6920 return -1;
6921 }
6922
6923 fw_mmu->len = size;
6924 hw->fw_mmu = fw_mmu;
6925 }
6926
6927 if (!tee_enabled()) {
6928 /* -- ucode loading (amrisc and swap code) */
6929 hw->mc_cpu_addr =
6930 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6931 &hw->mc_dma_handle, GFP_KERNEL);
6932 if (!hw->mc_cpu_addr) {
6933 amvdec_enable_flag = false;
6934 amvdec_disable();
6935 if (hw->mmu_enable)
6936 amhevc_disable();
6937 pr_info("vh264_init: Can not allocate mc memory.\n");
6938 return -ENOMEM;
6939 }
6940
6941 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6942 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6943 */
6944
6945 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6946
6947 /*header*/
6948 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6949 fw->data + 0x4000, MC_SWAP_SIZE);
6950 /*data*/
6951 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6952 fw->data + 0x2000, MC_SWAP_SIZE);
6953 /*mmco*/
6954 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6955 fw->data + 0x6000, MC_SWAP_SIZE);
6956 /*list*/
6957 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6958 fw->data + 0x3000, MC_SWAP_SIZE);
6959 /*slice*/
6960 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6961 fw->data + 0x5000, MC_SWAP_SIZE);
6962 /*main*/
6963 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6964 fw->data, 0x2000);
6965 /*data*/
6966 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6967 fw->data + 0x2000, 0x1000);
6968 /*slice*/
6969 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6970 fw->data + 0x5000, 0x1000);
6971 }
6972
6973#if 1 /* #ifdef BUFFER_MGR_IN_C */
6974 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6975 if (!hw->lmem_addr) {
6976 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6977 return -ENOMEM;
6978 } else {
6979 hw->lmem_addr_remap = dma_map_single(
6980 amports_get_dma_device(),
6981 (void *)hw->lmem_addr,
6982 PAGE_SIZE, DMA_FROM_DEVICE);
6983 if (dma_mapping_error(amports_get_dma_device(),
6984 hw->lmem_addr_remap)) {
6985 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6986 "%s: failed to map lmem_addr\n", __func__);
6987 free_page(hw->lmem_addr);
6988 hw->lmem_addr = 0;
6989 hw->lmem_addr_remap = 0;
6990 return -ENOMEM;
6991 }
6992
6993 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6994 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6995 }
6996
6997 if (prefix_aux_buf_size > 0 ||
6998 suffix_aux_buf_size > 0) {
6999 u32 aux_buf_size;
7000 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7001 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7002 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7003 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7004 if (hw->aux_addr == NULL) {
7005 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7006 return -1;
7007 }
7008
7009 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7010 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7011 if (dma_mapping_error(amports_get_dma_device(),
7012 hw->aux_phy_addr)) {
7013 pr_err("%s: failed to map rpm buffer\n", __func__);
7014 kfree(hw->aux_addr);
7015 hw->aux_addr = NULL;
7016 return -1;
7017 }
7018 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7019 if (hw->sei_data_buf == NULL) {
7020 pr_err("%s: failed to alloc sei itu data buffer\n",
7021 __func__);
7022 return -1;
7023 }
7024 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7025 if (hw->sei_itu_data_buf == NULL) {
7026 pr_err("%s: failed to alloc sei itu data buffer\n",
7027 __func__);
7028 kfree(hw->aux_addr);
7029 hw->aux_addr = NULL;
7030 kfree(hw->sei_data_buf);
7031 hw->sei_data_buf = NULL;
7032
7033 return -1;
7034 }
7035
7036 if (NULL == hw->sei_user_data_buffer) {
7037 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7038 GFP_KERNEL);
7039 if (!hw->sei_user_data_buffer) {
7040 pr_info("%s: Can not allocate sei_data_buffer\n",
7041 __func__);
7042 kfree(hw->aux_addr);
7043 hw->aux_addr = NULL;
7044 kfree(hw->sei_data_buf);
7045 hw->sei_data_buf = NULL;
7046 kfree(hw->sei_itu_data_buf);
7047 hw->sei_itu_data_buf = NULL;
7048
7049 return -1;
7050 }
7051 hw->sei_user_data_wp = 0;
7052 }
7053 }
7054/* BUFFER_MGR_IN_C */
7055#endif
7056 hw->stat |= STAT_MC_LOAD;
7057
7058 /* add memory barrier */
7059 wmb();
7060
7061 return 0;
7062}
7063
7064static int vh264_stop(struct vdec_h264_hw_s *hw)
7065{
7066 if (hw->stat & STAT_VDEC_RUN) {
7067 amvdec_stop();
7068 hw->stat &= ~STAT_VDEC_RUN;
7069 }
7070#ifdef VDEC_DW
7071 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7072#endif
7073#ifdef MH264_USERDATA_ENABLE
7074 cancel_work_sync(&hw->user_data_ready_work);
7075#endif
7076 cancel_work_sync(&hw->notify_work);
7077 cancel_work_sync(&hw->timeout_work);
7078 cancel_work_sync(&hw->work);
7079
7080
7081 if (hw->stat & STAT_MC_LOAD) {
7082 if (hw->mc_cpu_addr != NULL) {
7083 dma_free_coherent(amports_get_dma_device(),
7084 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7085 hw->mc_dma_handle);
7086 hw->mc_cpu_addr = NULL;
7087 }
7088 if (hw->frame_mmu_map_addr != NULL) {
7089 dma_free_coherent(amports_get_dma_device(),
7090 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7091 hw->frame_mmu_map_phy_addr);
7092 hw->frame_mmu_map_addr = NULL;
7093 }
7094
7095 }
7096 if (hw->stat & STAT_ISR_REG) {
7097 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7098 hw->stat &= ~STAT_ISR_REG;
7099 }
7100 if (hw->lmem_addr_remap) {
7101 dma_unmap_single(amports_get_dma_device(),
7102 hw->lmem_addr_remap,
7103 PAGE_SIZE, DMA_FROM_DEVICE);
7104 hw->lmem_addr_remap = 0;
7105 }
7106 if (hw->lmem_addr) {
7107 free_page(hw->lmem_addr);
7108 hw->lmem_addr = 0;
7109 }
7110 if (hw->aux_addr) {
7111 dma_unmap_single(amports_get_dma_device(),
7112 hw->aux_phy_addr,
7113 hw->prefix_aux_size + hw->suffix_aux_size,
7114 DMA_FROM_DEVICE);
7115 kfree(hw->aux_addr);
7116 hw->aux_addr = NULL;
7117 }
7118 if (hw->sei_data_buf != NULL) {
7119 kfree(hw->sei_data_buf);
7120 hw->sei_data_buf = NULL;
7121 }
7122 if (hw->sei_itu_data_buf != NULL) {
7123 kfree(hw->sei_itu_data_buf);
7124 hw->sei_itu_data_buf = NULL;
7125 }
7126 if (hw->sei_user_data_buffer != NULL) {
7127 kfree(hw->sei_user_data_buffer);
7128 hw->sei_user_data_buffer = NULL;
7129 }
7130 /* amvdec_disable(); */
7131
7132 vfree(hw->fw);
7133 hw->fw = NULL;
7134
7135 if (hw->mmu_enable) {
7136 vfree(hw->fw_mmu);
7137 hw->fw_mmu = NULL;
7138 }
7139
7140 dpb_print(DECODE_ID(hw), 0,
7141 "%s\n",
7142 __func__);
7143 return 0;
7144}
7145
7146static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7147{
7148 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7149 int count = 0;
7150 do {
7151 usleep_range(100, 500);
7152 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7153 break;
7154 if (count > 2000) {
7155 dpb_print(DECODE_ID(hw),
7156 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7157 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7158 break;
7159 } else
7160 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7161 count++;
7162 } while (1);
7163}
7164
7165static void vh264_notify_work(struct work_struct *work)
7166{
7167 struct vdec_h264_hw_s *hw = container_of(work,
7168 struct vdec_h264_hw_s, notify_work);
7169 struct vdec_s *vdec = hw_to_vdec(hw);
7170 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7171 vf_notify_receiver(vdec->vf_provider_name,
7172 VFRAME_EVENT_PROVIDER_FR_HINT,
7173 (void *)((unsigned long)hw->frame_dur));
7174 vdec->fr_hint_state = VDEC_HINTED;
7175 }
7176
7177 return;
7178}
7179
7180#ifdef MH264_USERDATA_ENABLE
7181static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7182{
7183 hw->wait_for_udr_send = 0;
7184 hw->sei_itu_data_len = 0;
7185 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7186}
7187
7188static void vmh264_crate_userdata_manager(
7189 struct vdec_h264_hw_s *hw,
7190 u8 *userdata_buf,
7191 int buf_len)
7192{
7193 if (hw) {
7194
7195
7196 mutex_init(&hw->userdata_mutex);
7197
7198 memset(&hw->userdata_info, 0,
7199 sizeof(struct mh264_userdata_info_t));
7200 hw->userdata_info.data_buf = userdata_buf;
7201 hw->userdata_info.buf_len = buf_len;
7202 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7203
7204 vmh264_reset_udr_mgr(hw);
7205
7206 }
7207}
7208
7209static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7210{
7211 if (hw)
7212 memset(&hw->userdata_info,
7213 0,
7214 sizeof(struct mh264_userdata_info_t));
7215}
7216
7217/*
7218#define DUMP_USERDATA_RECORD
7219*/
7220#ifdef DUMP_USERDATA_RECORD
7221
7222#define MAX_USER_DATA_SIZE 3145728
7223static void *user_data_buf;
7224static unsigned char *pbuf_start;
7225static int total_len;
7226static int bskip;
7227static int n_userdata_id;
7228
7229static void print_data(unsigned char *pdata,
7230 int len,
7231 unsigned int poc_number,
7232 unsigned int flag,
7233 unsigned int duration,
7234 unsigned int vpts,
7235 unsigned int vpts_valid,
7236 int rec_id)
7237{
7238 int nLeft;
7239
7240 nLeft = len;
7241#if 0
7242 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7243 rec_id, len, flag,
7244 duration, vpts, vpts_valid, poc_number);
7245#endif
7246 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7247 rec_id, len, flag, vpts);
7248
7249 if (len == 96) {
7250 int i;
7251 nLeft = 72;
7252 while (nLeft >= 16) {
7253 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7254 pdata[0], pdata[1], pdata[2], pdata[3],
7255 pdata[4], pdata[5], pdata[6], pdata[7],
7256 pdata[8], pdata[9], pdata[10], pdata[11],
7257 pdata[12], pdata[13], pdata[14], pdata[15]);
7258 nLeft -= 16;
7259 pdata += 16;
7260 }
7261
7262
7263 while (nLeft > 0) {
7264 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7265 pdata[0], pdata[1], pdata[2], pdata[3],
7266 pdata[4], pdata[5], pdata[6], pdata[7]);
7267 nLeft -= 8;
7268 pdata += 8;
7269 }
7270
7271 i = 0;
7272 nLeft = 96-72;
7273 while (i < nLeft) {
7274 if (pdata[0] != 0) {
7275 pr_info("some data error\n");
7276 break;
7277 }
7278 pdata++;
7279 i++;
7280 }
7281 } else {
7282 while (nLeft >= 16) {
7283 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7284 pdata[0], pdata[1], pdata[2], pdata[3],
7285 pdata[4], pdata[5], pdata[6], pdata[7],
7286 pdata[8], pdata[9], pdata[10], pdata[11],
7287 pdata[12], pdata[13], pdata[14], pdata[15]);
7288 nLeft -= 16;
7289 pdata += 16;
7290 }
7291
7292
7293 while (nLeft > 0) {
7294 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7295 pdata[0], pdata[1], pdata[2], pdata[3],
7296 pdata[4], pdata[5], pdata[6], pdata[7]);
7297 nLeft -= 8;
7298 pdata += 8;
7299 }
7300
7301 }
7302}
7303
7304static void push_to_buf(struct vdec_h264_hw_s *hw,
7305 u8 *pdata,
7306 int len,
7307 struct userdata_meta_info_t *pmeta);
7308
7309static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7310 struct mh264_userdata_record_t *record)
7311{
7312 if (record && hw) {
7313 u8 *pdata;
7314
7315 pdata = hw->userdata_info.data_buf + record->rec_start;
7316/*
7317 print_data(pdata,
7318 record->rec_len,
7319 record->meta_info.flags,
7320 record->meta_info.duration,
7321 record->meta_info.vpts,
7322 record->meta_info.vpts_valid,
7323 n_record_id);
7324*/
7325 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7326 n_userdata_id++;
7327 }
7328}
7329
7330
7331static void push_to_buf(struct vdec_h264_hw_s *hw,
7332 u8 *pdata, int len,
7333 struct userdata_meta_info_t *pmeta)
7334{
7335 u32 *pLen;
7336 int info_cnt;
7337 u8 *pbuf_end;
7338
7339 if (!user_data_buf)
7340 return;
7341
7342 if (bskip) {
7343 pr_info("over size, skip\n");
7344 return;
7345 }
7346 info_cnt = 0;
7347 pLen = (u32 *)pbuf_start;
7348
7349 *pLen = len;
7350 pbuf_start += sizeof(u32);
7351 info_cnt++;
7352 pLen++;
7353
7354 *pLen = pmeta->poc_number;
7355 pbuf_start += sizeof(u32);
7356 info_cnt++;
7357 pLen++;
7358
7359 *pLen = pmeta->duration;
7360 pbuf_start += sizeof(u32);
7361 info_cnt++;
7362 pLen++;
7363
7364 *pLen = pmeta->flags;
7365 pbuf_start += sizeof(u32);
7366 info_cnt++;
7367 pLen++;
7368
7369 *pLen = pmeta->vpts;
7370 pbuf_start += sizeof(u32);
7371 info_cnt++;
7372 pLen++;
7373
7374 *pLen = pmeta->vpts_valid;
7375 pbuf_start += sizeof(u32);
7376 info_cnt++;
7377 pLen++;
7378
7379
7380 *pLen = n_userdata_id;
7381 pbuf_start += sizeof(u32);
7382 info_cnt++;
7383 pLen++;
7384
7385
7386
7387 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7388 if (pdata + len > pbuf_end) {
7389 int first_section_len;
7390
7391 first_section_len = pbuf_end - pdata;
7392 memcpy(pbuf_start, pdata, first_section_len);
7393 pdata = (u8 *)hw->sei_user_data_buffer;
7394 pbuf_start += first_section_len;
7395 memcpy(pbuf_start, pdata, len - first_section_len);
7396 pbuf_start += len - first_section_len;
7397 } else {
7398 memcpy(pbuf_start, pdata, len);
7399 pbuf_start += len;
7400 }
7401
7402 total_len += len + info_cnt * sizeof(u32);
7403 if (total_len >= MAX_USER_DATA_SIZE-4096)
7404 bskip = 1;
7405}
7406
7407static void show_user_data_buf(void)
7408{
7409 u8 *pbuf;
7410 int len;
7411 unsigned int flag;
7412 unsigned int duration;
7413 unsigned int vpts;
7414 unsigned int vpts_valid;
7415 unsigned int poc_number;
7416 int rec_id;
7417
7418 pr_info("show user data buf\n");
7419 pbuf = user_data_buf;
7420
7421 while (pbuf < pbuf_start) {
7422 u32 *pLen;
7423
7424 pLen = (u32 *)pbuf;
7425
7426 len = *pLen;
7427 pLen++;
7428 pbuf += sizeof(u32);
7429
7430 poc_number = *pLen;
7431 pLen++;
7432 pbuf += sizeof(u32);
7433
7434 duration = *pLen;
7435 pLen++;
7436 pbuf += sizeof(u32);
7437
7438 flag = *pLen;
7439 pLen++;
7440 pbuf += sizeof(u32);
7441
7442 vpts = *pLen;
7443 pLen++;
7444 pbuf += sizeof(u32);
7445
7446 vpts_valid = *pLen;
7447 pLen++;
7448 pbuf += sizeof(u32);
7449
7450 rec_id = *pLen;
7451 pLen++;
7452 pbuf += sizeof(u32);
7453
7454 print_data(pbuf, len, poc_number, flag,
7455 duration, vpts,
7456 vpts_valid, rec_id);
7457 pbuf += len;
7458 msleep(30);
7459 }
7460}
7461
7462static int vmh264_init_userdata_dump(void)
7463{
7464 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7465 if (user_data_buf)
7466 return 1;
7467 else
7468 return 0;
7469}
7470
7471static void vmh264_dump_userdata(void)
7472{
7473 if (user_data_buf) {
7474 show_user_data_buf();
7475 kfree(user_data_buf);
7476 user_data_buf = NULL;
7477 }
7478}
7479
7480static void vmh264_reset_user_data_buf(void)
7481{
7482 total_len = 0;
7483 pbuf_start = user_data_buf;
7484 bskip = 0;
7485 n_userdata_id = 0;
7486}
7487#endif
7488
7489
7490static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7491 int frame_type,
7492 u32 vpts,
7493 u32 vpts_valid)
7494{
7495 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7496
7497 unsigned char *pdata;
7498 u8 *pmax_sei_data_buffer;
7499 u8 *sei_data_buf;
7500 int i;
7501 int wp;
7502 int data_length;
7503 struct mh264_userdata_record_t *p_userdata_rec;
7504
7505
7506#ifdef MH264_USERDATA_ENABLE
7507 struct userdata_meta_info_t meta_info;
7508 memset(&meta_info, 0, sizeof(meta_info));
7509#endif
7510
7511 if (hw->sei_itu_data_len <= 0)
7512 return;
7513
7514 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7515 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7516 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7517 for (i = 0; i < hw->sei_itu_data_len; i++) {
7518 *pdata++ = sei_data_buf[i];
7519 if (pdata >= pmax_sei_data_buffer)
7520 pdata = (u8 *)hw->sei_user_data_buffer;
7521 }
7522
7523 hw->sei_user_data_wp = (hw->sei_user_data_wp
7524 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7525 hw->sei_itu_data_len = 0;
7526
7527#ifdef MH264_USERDATA_ENABLE
7528 meta_info.duration = hw->frame_dur;
7529 meta_info.flags |= (VFORMAT_H264 << 3);
7530
7531 meta_info.vpts = vpts;
7532 meta_info.vpts_valid = vpts_valid;
7533 meta_info.poc_number =
7534 p_H264_Dpb->mVideo.dec_picture->poc;
7535
7536
7537 wp = hw->sei_user_data_wp;
7538
7539 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7540 data_length = wp - hw->userdata_info.last_wp;
7541 else
7542 data_length = wp + hw->userdata_info.buf_len
7543 - hw->userdata_info.last_wp;
7544
7545 if (data_length & 0x7)
7546 data_length = (((data_length + 8) >> 3) << 3);
7547
7548 p_userdata_rec = &hw->ud_record;
7549 p_userdata_rec->meta_info = meta_info;
7550 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7551 p_userdata_rec->rec_len = data_length;
7552 hw->userdata_info.last_wp = wp;
7553
7554 p_userdata_rec->meta_info.flags |=
7555 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7556
7557 hw->wait_for_udr_send = 1;
7558 vdec_schedule_work(&hw->user_data_ready_work);
7559#endif
7560}
7561
7562
7563static void user_data_ready_notify_work(struct work_struct *work)
7564{
7565 struct vdec_h264_hw_s *hw = container_of(work,
7566 struct vdec_h264_hw_s, user_data_ready_work);
7567
7568
7569 mutex_lock(&hw->userdata_mutex);
7570
7571 hw->userdata_info.records[hw->userdata_info.write_index]
7572 = hw->ud_record;
7573 hw->userdata_info.write_index++;
7574 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7575 hw->userdata_info.write_index = 0;
7576
7577 mutex_unlock(&hw->userdata_mutex);
7578
7579#ifdef DUMP_USERDATA_RECORD
7580 dump_userdata_record(hw, &hw->ud_record);
7581#endif
7582 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7583
7584 hw->wait_for_udr_send = 0;
7585}
7586
7587static int vmh264_user_data_read(struct vdec_s *vdec,
7588 struct userdata_param_t *puserdata_para)
7589{
7590 struct vdec_h264_hw_s *hw = NULL;
7591 int rec_ri, rec_wi;
7592 int rec_len;
7593 u8 *rec_data_start;
7594 u8 *pdest_buf;
7595 struct mh264_userdata_record_t *p_userdata_rec;
7596 u32 data_size;
7597 u32 res;
7598 int copy_ok = 1;
7599
7600 hw = (struct vdec_h264_hw_s *)vdec->private;
7601
7602 pdest_buf = puserdata_para->pbuf_addr;
7603
7604 mutex_lock(&hw->userdata_mutex);
7605
7606/*
7607 pr_info("ri = %d, wi = %d\n",
7608 lg_p_mpeg12_userdata_info->read_index,
7609 lg_p_mpeg12_userdata_info->write_index);
7610*/
7611 rec_ri = hw->userdata_info.read_index;
7612 rec_wi = hw->userdata_info.write_index;
7613
7614 if (rec_ri == rec_wi) {
7615 mutex_unlock(&hw->userdata_mutex);
7616 return 0;
7617 }
7618
7619 p_userdata_rec = hw->userdata_info.records + rec_ri;
7620
7621 rec_len = p_userdata_rec->rec_len;
7622 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7623/*
7624 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7625 p_userdata_rec->rec_len,
7626 p_userdata_rec->rec_start,
7627 puserdata_para->buf_len);
7628*/
7629 if (rec_len <= puserdata_para->buf_len) {
7630 /* dvb user data buffer is enought to
7631 copy the whole recored. */
7632 data_size = rec_len;
7633 if (rec_data_start + data_size
7634 > hw->userdata_info.data_buf_end) {
7635 int first_section_len;
7636
7637 first_section_len = hw->userdata_info.buf_len -
7638 p_userdata_rec->rec_start;
7639 res = (u32)copy_to_user((void *)pdest_buf,
7640 (void *)rec_data_start,
7641 first_section_len);
7642 if (res) {
7643 pr_info("p1 read not end res=%d, request=%d\n",
7644 res, first_section_len);
7645 copy_ok = 0;
7646
7647 p_userdata_rec->rec_len -=
7648 first_section_len - res;
7649 p_userdata_rec->rec_start +=
7650 first_section_len - res;
7651 puserdata_para->data_size =
7652 first_section_len - res;
7653 } else {
7654 res = (u32)copy_to_user(
7655 (void *)(pdest_buf+first_section_len),
7656 (void *)hw->userdata_info.data_buf,
7657 data_size - first_section_len);
7658 if (res) {
7659 pr_info("p2 read not end res=%d, request=%d\n",
7660 res, data_size);
7661 copy_ok = 0;
7662 }
7663 p_userdata_rec->rec_len -=
7664 data_size - res;
7665 p_userdata_rec->rec_start =
7666 data_size - first_section_len - res;
7667 puserdata_para->data_size =
7668 data_size - res;
7669 }
7670 } else {
7671 res = (u32)copy_to_user((void *)pdest_buf,
7672 (void *)rec_data_start,
7673 data_size);
7674 if (res) {
7675 pr_info("p3 read not end res=%d, request=%d\n",
7676 res, data_size);
7677 copy_ok = 0;
7678 }
7679 p_userdata_rec->rec_len -= data_size - res;
7680 p_userdata_rec->rec_start += data_size - res;
7681 puserdata_para->data_size = data_size - res;
7682 }
7683
7684 if (copy_ok) {
7685 hw->userdata_info.read_index++;
7686 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7687 hw->userdata_info.read_index = 0;
7688 }
7689 } else {
7690 /* dvb user data buffer is not enought
7691 to copy the whole recored. */
7692 data_size = puserdata_para->buf_len;
7693 if (rec_data_start + data_size
7694 > hw->userdata_info.data_buf_end) {
7695 int first_section_len;
7696
7697 first_section_len = hw->userdata_info.buf_len -
7698 p_userdata_rec->rec_start;
7699 res = (u32)copy_to_user((void *)pdest_buf,
7700 (void *)rec_data_start,
7701 first_section_len);
7702 if (res) {
7703 pr_info("p4 read not end res=%d, request=%d\n",
7704 res, first_section_len);
7705 copy_ok = 0;
7706 p_userdata_rec->rec_len -=
7707 first_section_len - res;
7708 p_userdata_rec->rec_start +=
7709 first_section_len - res;
7710 puserdata_para->data_size =
7711 first_section_len - res;
7712 } else {
7713 /* first secton copy is ok*/
7714 res = (u32)copy_to_user(
7715 (void *)(pdest_buf+first_section_len),
7716 (void *)hw->userdata_info.data_buf,
7717 data_size - first_section_len);
7718 if (res) {
7719 pr_info("p5 read not end res=%d, request=%d\n",
7720 res,
7721 data_size - first_section_len);
7722 copy_ok = 0;
7723 }
7724
7725 p_userdata_rec->rec_len -=
7726 data_size - res;
7727 p_userdata_rec->rec_start =
7728 data_size - first_section_len - res;
7729 puserdata_para->data_size =
7730 data_size - res;
7731 }
7732 } else {
7733 res = (u32)copy_to_user((void *)pdest_buf,
7734 (void *)rec_data_start,
7735 data_size);
7736 if (res) {
7737 pr_info("p6 read not end res=%d, request=%d\n",
7738 res, data_size);
7739 copy_ok = 0;
7740 }
7741
7742 p_userdata_rec->rec_len -= data_size - res;
7743 p_userdata_rec->rec_start += data_size - res;
7744 puserdata_para->data_size = data_size - res;
7745 }
7746
7747 if (copy_ok) {
7748 hw->userdata_info.read_index++;
7749 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7750 hw->userdata_info.read_index = 0;
7751 }
7752
7753 }
7754 puserdata_para->meta_info = p_userdata_rec->meta_info;
7755
7756 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7757 puserdata_para->meta_info.records_in_que =
7758 hw->userdata_info.write_index -
7759 hw->userdata_info.read_index;
7760 else
7761 puserdata_para->meta_info.records_in_que =
7762 hw->userdata_info.write_index +
7763 USERDATA_FIFO_NUM -
7764 hw->userdata_info.read_index;
7765
7766 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7767
7768 mutex_unlock(&hw->userdata_mutex);
7769
7770 return 1;
7771}
7772
7773static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7774{
7775 struct vdec_h264_hw_s *hw = NULL;
7776
7777 hw = (struct vdec_h264_hw_s *)vdec->private;
7778
7779 if (hw) {
7780 mutex_lock(&hw->userdata_mutex);
7781 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7782 bInit,
7783 hw->userdata_info.read_index,
7784 hw->userdata_info.write_index);
7785 hw->userdata_info.read_index = 0;
7786 hw->userdata_info.write_index = 0;
7787
7788 if (bInit)
7789 hw->userdata_info.last_wp = 0;
7790 mutex_unlock(&hw->userdata_mutex);
7791 }
7792}
7793
7794static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7795{
7796 amstream_wakeup_userdata_poll(vdec);
7797}
7798
7799#endif
7800
7801
7802static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7803 struct vdec_s *vdec, int from)
7804{
7805 /* finished decoding one frame or error,
7806 * notify vdec core to switch context
7807 */
7808 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7809 "%s dec_result %d %x %x %x\n",
7810 __func__,
7811 hw->dec_result,
7812 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7813 READ_VREG(VLD_MEM_VIFIFO_WP),
7814 READ_VREG(VLD_MEM_VIFIFO_RP));
7815 if (!hw->mmu_enable) {
7816 mutex_lock(&vmh264_mutex);
7817 dealloc_buf_specs(hw, 0);
7818 mutex_unlock(&vmh264_mutex);
7819 }
7820 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7821 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7822 u32 param1 = READ_VREG(AV_SCRATCH_1);
7823 u32 param2 = READ_VREG(AV_SCRATCH_2);
7824 u32 param3 = READ_VREG(AV_SCRATCH_6);
7825 u32 param4 = READ_VREG(AV_SCRATCH_B);
7826
7827 if (vh264_set_params(hw, param1,
7828 param2, param3, param4) < 0)
7829 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7830
7831 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7832 (hw->dpb.mDPB.size<<16) |
7833 (hw->dpb.mDPB.size<<8));
7834
7835 if (hw->is_used_v4l) {
7836 struct aml_vcodec_ctx *ctx =
7837 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7838
7839 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7840 struct aml_vdec_ps_infos ps;
7841
7842 ps.visible_width = hw->frame_width;
7843 ps.visible_height = hw->frame_height;
7844 ps.coded_width = ALIGN(hw->frame_width, 64);
7845 ps.coded_height = ALIGN(hw->frame_height, 64);
7846 ps.dpb_size = hw->dpb.mDPB.size;
7847 hw->v4l_params_parsed = true;
7848 vdec_v4l_set_ps_infos(ctx, &ps);
7849 }
7850 }
7851
7852 start_process_time(hw);
7853 return;
7854 } else
7855 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7856 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7857 && (hw_to_vdec(hw)->next_status !=
7858 VDEC_STATUS_DISCONNECTED)) {
7859 if (!vdec_has_more_input(vdec)) {
7860 hw->dec_result = DEC_RESULT_EOS;
7861 vdec_schedule_work(&hw->work);
7862 return;
7863 }
7864
7865 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7866 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7867 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7868 __func__,
7869 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7870 READ_VREG(VLD_MEM_VIFIFO_WP),
7871 READ_VREG(VLD_MEM_VIFIFO_RP));
7872 mutex_lock(&hw->chunks_mutex);
7873 vdec_vframe_dirty(vdec, hw->chunk);
7874 hw->chunk = NULL;
7875 mutex_unlock(&hw->chunks_mutex);
7876 vdec_clean_input(vdec);
7877 }
7878 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7879 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7880 > get_data_timeout_val)) {
7881 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7882 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7883 __func__);
7884 goto result_done;
7885 }
7886 if (is_buffer_available(vdec)) {
7887 int r;
7888 int decode_size;
7889 r = vdec_prepare_input(vdec, &hw->chunk);
7890 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7891 VDEC_STATUS_DISCONNECTED)) {
7892 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7893
7894 dpb_print(DECODE_ID(hw),
7895 PRINT_FLAG_VDEC_DETAIL,
7896 "vdec_prepare_input: Insufficient data\n");
7897 vdec_schedule_work(&hw->work);
7898 return;
7899 }
7900 hw->dec_result = DEC_RESULT_NONE;
7901 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7902 "%s: chunk size 0x%x\n",
7903 __func__, hw->chunk->size);
7904
7905 if (dpb_is_debug(DECODE_ID(hw),
7906 PRINT_FRAMEBASE_DATA)) {
7907 int jj;
7908 u8 *data = NULL;
7909
7910 if (!hw->chunk->block->is_mapped)
7911 data = codec_mm_vmap(
7912 hw->chunk->block->start +
7913 hw->chunk->offset, r);
7914 else
7915 data = ((u8 *)
7916 hw->chunk->block->start_virt)
7917 + hw->chunk->offset;
7918
7919 for (jj = 0; jj < r; jj++) {
7920 if ((jj & 0xf) == 0)
7921 dpb_print(DECODE_ID(hw),
7922 PRINT_FRAMEBASE_DATA,
7923 "%06x:", jj);
7924 dpb_print_cont(DECODE_ID(hw),
7925 PRINT_FRAMEBASE_DATA,
7926 "%02x ", data[jj]);
7927 if (((jj + 1) & 0xf) == 0)
7928 dpb_print_cont(DECODE_ID(hw),
7929 PRINT_FRAMEBASE_DATA,
7930 "\n");
7931 }
7932
7933 if (!hw->chunk->block->is_mapped)
7934 codec_mm_unmap_phyaddr(data);
7935 }
7936 WRITE_VREG(POWER_CTL_VLD,
7937 READ_VREG(POWER_CTL_VLD) |
7938 (0 << 10) | (1 << 9) | (1 << 6));
7939 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7940 decode_size = hw->chunk->size +
7941 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7942 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7943 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7944 vdec_enable_input(vdec);
7945
7946 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7947 start_process_time(hw);
7948 } else{
7949 if (hw_to_vdec(hw)->next_status
7950 != VDEC_STATUS_DISCONNECTED) {
7951 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7952 vdec_schedule_work(&hw->work);
7953 }
7954 }
7955 return;
7956 } else if (hw->dec_result == DEC_RESULT_DONE) {
7957 /* if (!hw->ctx_valid)
7958 hw->ctx_valid = 1; */
7959result_done:
7960 if (hw->mmu_enable
7961 && hw->frame_busy && hw->frame_done) {
7962 long used_4k_num;
7963 hevc_sao_wait_done(hw);
7964 if (hw->hevc_cur_buf_idx != 0xffff) {
7965 used_4k_num =
7966 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7967 if (used_4k_num >= 0)
7968 dpb_print(DECODE_ID(hw),
7969 PRINT_FLAG_MMU_DETAIL,
7970 "release unused buf , used_4k_num %ld index %d\n",
7971 used_4k_num, hw->hevc_cur_buf_idx);
7972 hevc_mmu_dma_check(hw_to_vdec(hw));
7973 decoder_mmu_box_free_idx_tail(
7974 hw->mmu_box,
7975 hw->hevc_cur_buf_idx,
7976 used_4k_num);
7977 hw->hevc_cur_buf_idx = 0xffff;
7978 }
7979 }
7980 decode_frame_count[DECODE_ID(hw)]++;
7981 amvdec_stop();
7982 if (!vdec_is_support_4k()) {
7983 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7984 clk_adj_frame_count++;
7985 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7986 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7987 }
7988 }
7989 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7990 "%s dec_result %d %x %x %x\n",
7991 __func__,
7992 hw->dec_result,
7993 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7994 READ_VREG(VLD_MEM_VIFIFO_WP),
7995 READ_VREG(VLD_MEM_VIFIFO_RP));
7996 mutex_lock(&hw->chunks_mutex);
7997 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7998 hw->chunk = NULL;
7999 mutex_unlock(&hw->chunks_mutex);
8000 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8001 /*
8002 stream base: stream buf empty or timeout
8003 frame base: vdec_prepare_input fail
8004 */
8005 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8006 VDEC_STATUS_DISCONNECTED)) {
8007 hw->dec_result = DEC_RESULT_EOS;
8008 vdec_schedule_work(&hw->work);
8009 return;
8010 }
8011 hw->next_again_flag = 1;
8012 } else if (hw->dec_result == DEC_RESULT_EOS) {
8013 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8014 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8015 "%s: end of stream\n",
8016 __func__);
8017 amvdec_stop();
8018 if (hw->mmu_enable)
8019 amhevc_stop();
8020 hw->eos = 1;
8021 flush_dpb(p_H264_Dpb);
8022 if (hw->is_used_v4l)
8023 notify_v4l_eos(hw_to_vdec(hw));
8024 mutex_lock(&hw->chunks_mutex);
8025 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8026 hw->chunk = NULL;
8027 mutex_unlock(&hw->chunks_mutex);
8028 vdec_clean_input(vdec);
8029 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8030 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8031 "%s: force exit\n",
8032 __func__);
8033 amvdec_stop();
8034 if (hw->mmu_enable)
8035 amhevc_stop();
8036 if (hw->stat & STAT_ISR_REG) {
8037 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8038 hw->stat &= ~STAT_ISR_REG;
8039 }
8040 }
8041 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8042 del_timer_sync(&hw->check_timer);
8043 hw->stat &= ~STAT_TIMER_ARM;
8044
8045 wait_vmh264_search_done(hw);
8046 /* mark itself has all HW resource released and input released */
8047
8048#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8049 if (hw->switch_dvlayer_flag) {
8050 if (vdec->slave)
8051 vdec_set_next_sched(vdec, vdec->slave);
8052 else if (vdec->master)
8053 vdec_set_next_sched(vdec, vdec->master);
8054 } else if (vdec->slave || vdec->master)
8055 vdec_set_next_sched(vdec, vdec);
8056#endif
8057
8058 if (from == 1) {
8059 /* This is a timeout work */
8060 if (work_pending(&hw->work)) {
8061 /*
8062 * The vh264_work arrives at the last second,
8063 * give it a chance to handle the scenario.
8064 */
8065 return;
8066 }
8067 }
8068
8069 /* mark itself has all HW resource released and input released */
8070 if (vdec->parallel_dec == 1) {
8071 if (hw->mmu_enable == 0)
8072 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8073 else
8074 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8075 } else
8076 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8077
8078 wake_up_interruptible(&hw->wait_q);
8079
8080 if (hw->is_used_v4l) {
8081 struct aml_vcodec_ctx *ctx =
8082 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8083
8084 if (ctx->param_sets_from_ucode &&
8085 !hw->v4l_params_parsed)
8086 vdec_v4l_write_frame_sync(ctx);
8087 }
8088
8089 if (hw->vdec_cb)
8090 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8091}
8092
8093
8094static void vh264_work(struct work_struct *work)
8095{
8096 struct vdec_h264_hw_s *hw = container_of(work,
8097 struct vdec_h264_hw_s, work);
8098 struct vdec_s *vdec = hw_to_vdec(hw);
8099
8100 vh264_work_implement(hw, vdec, 0);
8101}
8102
8103
8104static void vh264_timeout_work(struct work_struct *work)
8105{
8106 struct vdec_h264_hw_s *hw = container_of(work,
8107 struct vdec_h264_hw_s, timeout_work);
8108 struct vdec_s *vdec = hw_to_vdec(hw);
8109
8110 if (work_pending(&hw->work))
8111 return;
8112
8113 vh264_work_implement(hw, vdec, 1);
8114}
8115
8116static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8117{
8118 bool ret = 0;
8119 struct vdec_h264_hw_s *hw =
8120 (struct vdec_h264_hw_s *)vdec->private;
8121 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8122 CODEC_MM_FLAGS_TVP : 0;
8123
8124 if (!hw->first_sc_checked && hw->mmu_enable) {
8125 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8126 hw->first_sc_checked =1;
8127 dpb_print(DECODE_ID(hw), 0,
8128 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8129 size, (hw->need_cache_size >> PAGE_SHIFT),
8130 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8131 }
8132
8133 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8134 && pre_decode_buf_level != 0) {
8135 u32 rp, wp, level;
8136
8137 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8138 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8139 if (wp < rp)
8140 level = vdec->input.size + wp - rp;
8141 else
8142 level = wp - rp;
8143
8144 if (level < pre_decode_buf_level)
8145 return 0;
8146 }
8147
8148#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8149 if (vdec->master)
8150 return 0;
8151#endif
8152 if (hw->eos)
8153 return 0;
8154
8155 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8156 return 0;
8157
8158 if (disp_vframe_valve_level &&
8159 kfifo_len(&hw->display_q) >=
8160 disp_vframe_valve_level) {
8161 hw->valve_count--;
8162 if (hw->valve_count <= 0)
8163 hw->valve_count = 2;
8164 else
8165 return 0;
8166 }
8167 if (hw->next_again_flag &&
8168 (!vdec_frame_based(vdec))) {
8169 u32 parser_wr_ptr =
8170 READ_PARSER_REG(PARSER_VIDEO_WP);
8171 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8172 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8173 again_threshold) {
8174 int r = vdec_sync_input(vdec);
8175 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8176 "%s buf lelvel:%x\n", __func__, r);
8177 return 0;
8178 }
8179 }
8180
8181 if (h264_debug_flag & 0x20000000) {
8182 /* pr_info("%s, a\n", __func__); */
8183 ret = 1;
8184 } else
8185 ret = is_buffer_available(vdec);
8186
8187#ifdef CONSTRAIN_MAX_BUF_NUM
8188 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8189 if (run_ready_max_vf_only_num > 0 &&
8190 get_vf_ref_only_buf_count(hw) >=
8191 run_ready_max_vf_only_num
8192 )
8193 ret = 0;
8194 if (run_ready_display_q_num > 0 &&
8195 kfifo_len(&hw->display_q) >=
8196 run_ready_display_q_num)
8197 ret = 0;
8198 /*avoid more buffers consumed when
8199 switching resolution*/
8200 if (run_ready_max_buf_num == 0xff &&
8201 get_used_buf_count(hw) >
8202 hw->dpb.mDPB.size)
8203 ret = 0;
8204 else if (run_ready_max_buf_num &&
8205 get_used_buf_count(hw) >=
8206 run_ready_max_buf_num)
8207 ret = 0;
8208 }
8209#endif
8210 if (hw->is_used_v4l) {
8211 struct aml_vcodec_ctx *ctx =
8212 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8213
8214 if (ctx->param_sets_from_ucode &&
8215 !ctx->v4l_codec_ready &&
8216 hw->v4l_params_parsed) {
8217 ret = 0; /*the params has parsed.*/
8218 } else if (!ctx->v4l_codec_dpb_ready) {
8219 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8220 run_ready_min_buf_num)
8221 ret = 0;
8222 }
8223 }
8224
8225 if (ret)
8226 not_run_ready[DECODE_ID(hw)] = 0;
8227 else
8228 not_run_ready[DECODE_ID(hw)]++;
8229 if (vdec->parallel_dec == 1) {
8230 if (hw->mmu_enable == 0)
8231 return ret ? (CORE_MASK_VDEC_1) : 0;
8232 else
8233 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8234 } else
8235 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8236}
8237
8238static unsigned char get_data_check_sum
8239 (struct vdec_h264_hw_s *hw, int size)
8240{
8241 int jj;
8242 int sum = 0;
8243 u8 *data = NULL;
8244
8245 if (!hw->chunk->block->is_mapped)
8246 data = codec_mm_vmap(hw->chunk->block->start +
8247 hw->chunk->offset, size);
8248 else
8249 data = ((u8 *)hw->chunk->block->start_virt)
8250 + hw->chunk->offset;
8251
8252 for (jj = 0; jj < size; jj++)
8253 sum += data[jj];
8254
8255 if (!hw->chunk->block->is_mapped)
8256 codec_mm_unmap_phyaddr(data);
8257 return sum;
8258}
8259
8260static void run(struct vdec_s *vdec, unsigned long mask,
8261 void (*callback)(struct vdec_s *, void *), void *arg)
8262{
8263 struct vdec_h264_hw_s *hw =
8264 (struct vdec_h264_hw_s *)vdec->private;
8265 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8266 int size, ret = -1;
8267
8268 run_count[DECODE_ID(hw)]++;
8269 vdec_reset_core(vdec);
8270 if (hw->mmu_enable)
8271 hevc_reset_core(vdec);
8272 hw->vdec_cb_arg = arg;
8273 hw->vdec_cb = callback;
8274
8275 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8276 hw->reset_bufmgr_flag = 1;
8277 dpb_print(DECODE_ID(hw), 0,
8278 "kfifo len:%d invaild, need bufmgr reset\n",
8279 kfifo_len(&hw->display_q));
8280 }
8281
8282 hw->pre_parser_wr_ptr =
8283 READ_PARSER_REG(PARSER_VIDEO_WP);
8284 hw->next_again_flag = 0;
8285
8286 if (hw->reset_bufmgr_flag ||
8287 ((error_proc_policy & 0x40) &&
8288 p_H264_Dpb->buf_alloc_fail)) {
8289 if (!hw->is_used_v4l)
8290 h264_reset_bufmgr(vdec);
8291 else {
8292 struct aml_vcodec_ctx *ctx =
8293 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8294 pr_info("v4l2 buffer reset\n");
8295 hw->wait_reset_done_flag = 1;
8296 hw->reset_bufmgr_flag = 0;
8297 vdec_v4l_post_evet(ctx, V4L2_EVENT_REQUEST_RESET);
8298 hw->dec_result = DEC_RESULT_NONE;
8299 vdec_schedule_work(&hw->work);
8300 return;
8301 }
8302 hw->reset_bufmgr_flag = 0;
8303 }
8304
8305 if (h264_debug_cmd & 0xf000) {
8306 if (((h264_debug_cmd >> 12) & 0xf)
8307 == (DECODE_ID(hw) + 1)) {
8308 h264_reconfig(hw);
8309 h264_debug_cmd &= (~0xf000);
8310 }
8311 }
8312 /* hw->chunk = vdec_prepare_input(vdec); */
8313#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8314 if (vdec->slave || vdec->master)
8315 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8316#endif
8317 size = vdec_prepare_input(vdec, &hw->chunk);
8318 if ((size < 0) ||
8319 (input_frame_based(vdec) && hw->chunk == NULL)) {
8320 input_empty[DECODE_ID(hw)]++;
8321 hw->dec_result = DEC_RESULT_AGAIN;
8322
8323 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8324 "vdec_prepare_input: Insufficient data\n");
8325
8326 vdec_schedule_work(&hw->work);
8327 return;
8328 }
8329 input_empty[DECODE_ID(hw)] = 0;
8330
8331 hw->dec_result = DEC_RESULT_NONE;
8332 hw->get_data_count = 0;
8333#if 0
8334 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8335 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8336 READ_VREG(VLD_MEM_VIFIFO_RP),
8337 READ_VREG(VLD_MEM_VIFIFO_WP));
8338#endif
8339
8340 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8341 u8 *data = NULL;
8342
8343 if (!hw->chunk->block->is_mapped)
8344 data = codec_mm_vmap(hw->chunk->block->start +
8345 hw->chunk->offset, size);
8346 else
8347 data = ((u8 *)hw->chunk->block->start_virt)
8348 + hw->chunk->offset;
8349
8350 if (dpb_is_debug(DECODE_ID(hw),
8351 PRINT_FLAG_VDEC_STATUS)
8352 ) {
8353 dpb_print(DECODE_ID(hw), 0,
8354 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8355 __func__, size, get_data_check_sum(hw, size),
8356 data[0], data[1], data[2], data[3],
8357 data[4], data[5], data[size - 4],
8358 data[size - 3], data[size - 2],
8359 data[size - 1]);
8360 }
8361 if (dpb_is_debug(DECODE_ID(hw),
8362 PRINT_FRAMEBASE_DATA)
8363 ) {
8364 int jj;
8365
8366 for (jj = 0; jj < size; jj++) {
8367 if ((jj & 0xf) == 0)
8368 dpb_print(DECODE_ID(hw),
8369 PRINT_FRAMEBASE_DATA,
8370 "%06x:", jj);
8371 dpb_print_cont(DECODE_ID(hw),
8372 PRINT_FRAMEBASE_DATA,
8373 "%02x ", data[jj]);
8374 if (((jj + 1) & 0xf) == 0)
8375 dpb_print_cont(DECODE_ID(hw),
8376 PRINT_FRAMEBASE_DATA,
8377 "\n");
8378 }
8379 }
8380
8381 if (!hw->chunk->block->is_mapped)
8382 codec_mm_unmap_phyaddr(data);
8383 } else
8384 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8385 "%s: %x %x %x %x %x size 0x%x\n",
8386 __func__,
8387 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8388 READ_VREG(VLD_MEM_VIFIFO_WP),
8389 READ_VREG(VLD_MEM_VIFIFO_RP),
8390 READ_PARSER_REG(PARSER_VIDEO_RP),
8391 READ_PARSER_REG(PARSER_VIDEO_WP),
8392 size);
8393
8394 start_process_time(hw);
8395 if (vdec->mc_loaded) {
8396 /*firmware have load before,
8397 and not changes to another.
8398 ignore reload.
8399 */
8400 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8401 } else {
8402
8403 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8404 if (ret < 0) {
8405 amvdec_enable_flag = false;
8406 amvdec_disable();
8407
8408 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8409 "MH264 the %s fw loading failed, err: %x\n",
8410 tee_enabled() ? "TEE" : "local", ret);
8411 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8412 vdec_schedule_work(&hw->work);
8413 return;
8414 }
8415 vdec->mc_type = VFORMAT_H264;
8416 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8417 if (hw->mmu_enable) {
8418 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8419 hw->fw_mmu->data);
8420 if (ret < 0) {
8421 amvdec_enable_flag = false;
8422 amhevc_disable();
8423
8424 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8425 "MH264_MMU the %s fw loading failed, err: %x\n",
8426 tee_enabled() ? "TEE" : "local", ret);
8427 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8428 vdec_schedule_work(&hw->work);
8429 return;
8430 }
8431 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8432 }
8433 vdec->mc_loaded = 1;
8434 }
8435 vmh264_reset_udr_mgr(hw);
8436
8437 if (vh264_hw_ctx_restore(hw) < 0) {
8438 vdec_schedule_work(&hw->work);
8439 return;
8440 }
8441 if (input_frame_based(vdec)) {
8442 int decode_size = 0;
8443
8444 decode_size = hw->chunk->size +
8445 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8446 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8447 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8448 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8449 } else {
8450 if (size <= 0)
8451 size = 0x7fffffff; /*error happen*/
8452 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8453 WRITE_VREG(H264_DECODE_SIZE, size);
8454 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8455 }
8456 config_aux_buf(hw);
8457 config_decode_mode(hw);
8458 vdec_enable_input(vdec);
8459 WRITE_VREG(NAL_SEARCH_CTL, 0);
8460 hw->sei_data_len = 0;
8461 if (enable_itu_t35)
8462 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8463 if (!hw->init_flag) {
8464 if (hw->mmu_enable)
8465 WRITE_VREG(NAL_SEARCH_CTL,
8466 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8467 else
8468 WRITE_VREG(NAL_SEARCH_CTL,
8469 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8470 }
8471 if (udebug_flag)
8472 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8473 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8474
8475 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8476
8477 if (hw->mmu_enable)
8478 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8479 else
8480 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8481 }
8482 amvdec_start();
8483 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8484 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8485 amhevc_start();
8486 if (hw->config_bufmgr_done) {
8487 hevc_mcr_sao_global_hw_init(hw,
8488 (hw->mb_width << 4), (hw->mb_height << 4));
8489 hevc_mcr_config_canv2axitbl(hw, 1);
8490 }
8491 }
8492
8493 /* if (hw->init_flag) { */
8494 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8495 /* } */
8496
8497 hw->init_flag = 1;
8498}
8499
8500static void reset(struct vdec_s *vdec)
8501{
8502 struct vdec_h264_hw_s *hw =
8503 (struct vdec_h264_hw_s *)vdec->private;
8504
8505 pr_info("vmh264 reset\n");
8506
8507 cancel_work_sync(&hw->work);
8508 cancel_work_sync(&hw->notify_work);
8509 if (hw->stat & STAT_VDEC_RUN) {
8510 amhevc_stop();
8511 hw->stat &= ~STAT_VDEC_RUN;
8512 }
8513
8514 if (hw->stat & STAT_TIMER_ARM) {
8515 del_timer_sync(&hw->check_timer);
8516 hw->stat &= ~STAT_TIMER_ARM;
8517 }
8518 hw->eos = 0;
8519 hw->decode_pic_count = 0;
8520 hw->dec_result = DEC_RESULT_NONE;
8521 reset_process_time(hw);
8522 h264_reset_bufmgr(vdec);
8523 hw->wait_reset_done_flag = 0;
8524
8525 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8526}
8527
8528static void h264_reconfig(struct vdec_h264_hw_s *hw)
8529{
8530 int i;
8531 unsigned long flags;
8532 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8533 struct vdec_s *vdec = hw_to_vdec(hw);
8534 dpb_print(DECODE_ID(hw), 0,
8535 "%s\n", __func__);
8536 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8537 all buffers are in display queue (used == 2),
8538 or free (used == 0)
8539 */
8540 if (dpb_is_debug(DECODE_ID(hw),
8541 PRINT_FLAG_DUMP_BUFSPEC))
8542 dump_bufspec(hw, "pre h264_reconfig");
8543
8544 flush_dpb(p_H264_Dpb);
8545 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8546
8547 if (hw->collocate_cma_alloc_addr) {
8548 decoder_bmmu_box_free_idx(
8549 hw->bmmu_box,
8550 BMMU_REF_IDX);
8551 hw->collocate_cma_alloc_addr = 0;
8552 hw->dpb.colocated_mv_addr_start = 0;
8553 hw->dpb.colocated_mv_addr_end = 0;
8554 }
8555 spin_lock_irqsave(&hw->bufspec_lock, flags);
8556 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8557 if (vdec->parallel_dec == 1) {
8558 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8559 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8560 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8561 hw->buffer_spec[i].y_canvas_index = -1;
8562 hw->buffer_spec[i].u_canvas_index = -1;
8563 hw->buffer_spec[i].v_canvas_index = -1;
8564#ifdef VDEC_DW
8565 if (IS_VDEC_DW(hw)) {
8566 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8567 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8568 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8569 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8570 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8571 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8572#endif
8573 }
8574 }
8575 /*make sure buffers not put back to bufmgr when
8576 vf_put is called*/
8577 if (hw->buffer_spec[i].used == 2)
8578 hw->buffer_spec[i].used = 3;
8579
8580 /* ready to release "free buffers"
8581 */
8582 if (hw->buffer_spec[i].used == 0)
8583 hw->buffer_spec[i].used = 4;
8584
8585 hw->buffer_spec[i].canvas_pos = -1;
8586 }
8587 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8588 hw->has_i_frame = 0;
8589 hw->config_bufmgr_done = 0;
8590
8591 if (hw->is_used_v4l) {
8592 mutex_lock(&vmh264_mutex);
8593 dealloc_buf_specs(hw, 1);
8594 mutex_unlock(&vmh264_mutex);
8595 }
8596
8597 if (dpb_is_debug(DECODE_ID(hw),
8598 PRINT_FLAG_DUMP_BUFSPEC))
8599 dump_bufspec(hw, "after h264_reconfig");
8600
8601}
8602
8603#ifdef ERROR_HANDLE_TEST
8604static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8605{
8606 int i;
8607 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8608 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8609 "%s\n", __func__);
8610 remove_dpb_pictures(p_H264_Dpb);
8611 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8612 /*make sure buffers not put back to bufmgr when
8613 vf_put is called*/
8614 if (hw->buffer_spec[i].used == 2)
8615 hw->buffer_spec[i].used = 5;
8616 }
8617
8618}
8619#endif
8620
8621static void h264_reset_bufmgr(struct vdec_s *vdec)
8622{
8623 int i;
8624 ulong timeout;
8625 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8626#if 0
8627 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8628 int actual_dpb_size, max_reference_size;
8629 int reorder_pic_num;
8630 unsigned int colocated_buf_size;
8631 unsigned int colocated_mv_addr_start;
8632 unsigned int colocated_mv_addr_end;
8633 dpb_print(DECODE_ID(hw), 0,
8634 "%s\n", __func__);
8635
8636 for (i = 0; i < VF_POOL_SIZE; i++)
8637 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8638
8639 actual_dpb_size = p_H264_Dpb->mDPB.size;
8640 max_reference_size = p_H264_Dpb->max_reference_size;
8641 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8642
8643 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8644 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8645 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8646
8647 hw->cur_pool++;
8648 if (hw->cur_pool >= VF_POOL_NUM)
8649 hw->cur_pool = 0;
8650
8651 INIT_KFIFO(hw->display_q);
8652 INIT_KFIFO(hw->newframe_q);
8653
8654 for (i = 0; i < VF_POOL_SIZE; i++) {
8655 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8656 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8657 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8658 kfifo_put(&hw->newframe_q, vf);
8659 }
8660
8661 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8662 hw->buffer_spec[i].used = 0;
8663
8664 dpb_init_global(&hw->dpb,
8665 DECODE_ID(hw), 0, 0);
8666 p_H264_Dpb->mDPB.size = actual_dpb_size;
8667 p_H264_Dpb->max_reference_size = max_reference_size;
8668 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8669
8670 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8671 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8672 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8673
8674 p_H264_Dpb->fast_output_enable = fast_output_enable;
8675 hw->has_i_frame = 0;
8676#else
8677 dpb_print(DECODE_ID(hw), 0,
8678 "%s frame count %d to skip %d\n\n",
8679 __func__, hw->decode_pic_count+1,
8680 hw->skip_frame_count);
8681
8682 timeout = jiffies + HZ;
8683 while (kfifo_len(&hw->display_q) > 0) {
8684 if (time_after(jiffies, timeout))
8685 break;
8686 schedule();
8687 }
8688
8689 for (i = 0; i < VF_POOL_SIZE; i++)
8690 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8691
8692 hw->cur_pool++;
8693 if (hw->cur_pool >= VF_POOL_NUM)
8694 hw->cur_pool = 0;
8695
8696 for (i = 0; i < VF_POOL_SIZE; i++)
8697 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8698
8699
8700 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8701
8702 buf_spec_init(hw);
8703
8704 vh264_local_init(hw);
8705 /*hw->decode_pic_count = 0;
8706 hw->seq_info2 = 0;*/
8707
8708 if (hw->is_used_v4l) {
8709 mutex_lock(&vmh264_mutex);
8710 /* detach relationship with v4l buffs.*/
8711 dealloc_buf_specs(hw, 1);
8712 mutex_unlock(&vmh264_mutex);
8713 }
8714
8715 if (vh264_set_params(hw,
8716 hw->cfg_param1,
8717 hw->cfg_param2,
8718 hw->cfg_param3,
8719 hw->cfg_param4) < 0)
8720 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8721
8722 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8723 if (first_i_policy & 0x01)
8724 hw->first_i_policy = (3 << 8) | first_i_policy;
8725
8726 hw->init_flag = 1;
8727 hw->reset_bufmgr_count++;
8728#endif
8729}
8730
8731int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8732{
8733 int ret = -1;
8734 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8735 CODEC_MM_FLAGS_TVP : 0;
8736 int buf_size = 64;
8737
8738 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8739 tvp_flag, hw->mmu_enable);
8740 hw->need_cache_size = buf_size * SZ_1M;
8741 hw->sc_start_time = get_jiffies_64();
8742 if (hw->mmu_enable && !hw->mmu_box) {
8743 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8744 hw->id,
8745 MMU_MAX_BUFFERS,
8746 hw->need_cache_size,
8747 tvp_flag);
8748 if (!hw->mmu_box) {
8749 pr_err("h264 4k alloc mmu box failed!!\n");
8750 return -1;
8751 }
8752 ret = 0;
8753 }
8754 if (!hw->bmmu_box) {
8755 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8756 DRIVER_NAME,
8757 hw->id,
8758 BMMU_MAX_BUFFERS,
8759 4 + PAGE_SHIFT,
8760 CODEC_MM_FLAGS_CMA_CLEAR |
8761 CODEC_MM_FLAGS_FOR_VDECODER |
8762 tvp_flag);
8763 if (hw->bmmu_box)
8764 ret = 0;
8765 }
8766 return ret;
8767}
8768int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8769{
8770 if (hw->mmu_box) {
8771 decoder_mmu_box_free(hw->mmu_box);
8772 hw->mmu_box = NULL;
8773 }
8774 if (hw->bmmu_box) {
8775 decoder_bmmu_box_free(hw->bmmu_box);
8776 hw->bmmu_box = NULL;
8777 }
8778 return 0;
8779}
8780
8781static int ammvdec_h264_probe(struct platform_device *pdev)
8782{
8783 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8784 struct vdec_h264_hw_s *hw = NULL;
8785 char *tmpbuf;
8786 int config_val;
8787
8788 if (pdata == NULL) {
8789 pr_info("\nammvdec_h264 memory resource undefined.\n");
8790 return -EFAULT;
8791 }
8792
8793 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8794 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8795 if (hw == NULL) {
8796 pr_info("\nammvdec_h264 device data allocation failed\n");
8797 return -ENOMEM;
8798 }
8799 hw->id = pdev->id;
8800 hw->platform_dev = pdev;
8801
8802 /* the ctx from v4l2 driver. */
8803 hw->v4l2_ctx = pdata->private;
8804
8805 platform_set_drvdata(pdev, pdata);
8806
8807 hw->mmu_enable = 0;
8808 hw->first_head_check_flag = 0;
8809 hw->new_iframe_flag = 0;
8810 hw->ref_err_flush_dpb_flag = 0;
8811 hw->wait_reset_done_flag = 0;
8812
8813 if (pdata->sys_info)
8814 hw->vh264_amstream_dec_info = *pdata->sys_info;
8815
8816 if (force_enable_mmu && pdata->sys_info &&
8817 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8818 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8819 (pdata->sys_info->height * pdata->sys_info->width
8820 > 1920 * 1088))
8821 hw->mmu_enable = 1;
8822
8823 if (hw->mmu_enable &&
8824 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8825 hw->mmu_enable = 0;
8826 pr_info("ionvideo needs disable mmu, path= %d \n",
8827 pdata->frame_base_video_path);
8828 }
8829
8830 if (ammvdec_h264_mmu_init(hw)) {
8831 h264_free_hw_stru(&pdev->dev, (void *)hw);
8832 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8833 return -ENOMEM;
8834 }
8835
8836 if (pdata->config_len) {
8837 /*use ptr config for doubel_write_mode, etc*/
8838 if (get_config_int(pdata->config,
8839 "mh264_double_write_mode", &config_val) == 0)
8840 hw->double_write_mode = config_val;
8841 else
8842 hw->double_write_mode = double_write_mode;
8843
8844 if (get_config_int(pdata->config,
8845 "parm_v4l_codec_enable",
8846 &config_val) == 0)
8847 hw->is_used_v4l = config_val;
8848
8849 if (get_config_int(pdata->config,
8850 "parm_v4l_buffer_margin",
8851 &config_val) == 0)
8852 hw->reorder_dpb_size_margin = config_val;
8853
8854 if (get_config_int(pdata->config,
8855 "parm_v4l_canvas_mem_mode",
8856 &config_val) == 0)
8857 hw->canvas_mode = config_val;
8858 } else
8859 hw->double_write_mode = double_write_mode;
8860
8861 if (!hw->is_used_v4l) {
8862 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8863 hw->canvas_mode = mem_map_mode;
8864
8865 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8866 hw->canvas_mode = pdata->canvas_mode;
8867 }
8868
8869 if (hw->mmu_enable)
8870 hw->double_write_mode &= 0xffff;
8871
8872 if (pdata->parallel_dec == 1) {
8873 int i;
8874 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8875 hw->buffer_spec[i].y_canvas_index = -1;
8876 hw->buffer_spec[i].u_canvas_index = -1;
8877 hw->buffer_spec[i].v_canvas_index = -1;
8878#ifdef VDEC_DW
8879 if (IS_VDEC_DW(hw)) {
8880 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8881 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8882 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8883 }
8884#endif
8885 }
8886 }
8887
8888 dpb_print(DECODE_ID(hw), 0,
8889 "%s mmu_enable %d double_write_mode 0x%x\n",
8890 __func__, hw->mmu_enable, hw->double_write_mode);
8891
8892 pdata->private = hw;
8893 pdata->dec_status = dec_status;
8894 pdata->set_trickmode = vmh264_set_trickmode;
8895 pdata->run_ready = run_ready;
8896 pdata->run = run;
8897 pdata->reset = reset;
8898 pdata->irq_handler = vh264_isr;
8899 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8900 pdata->dump_state = vmh264_dump_state;
8901
8902#ifdef MH264_USERDATA_ENABLE
8903 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8904 pdata->user_data_read = vmh264_user_data_read;
8905 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8906#else
8907 pdata->wakeup_userdata_poll = NULL;
8908 pdata->user_data_read = NULL;
8909 pdata->reset_userdata_fifo = NULL;
8910#endif
8911 if (pdata->use_vfm_path) {
8912 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8913 VFM_DEC_PROVIDER_NAME);
8914 hw->frameinfo_enable = 1;
8915 }
8916#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8917 else if (vdec_dual(pdata)) {
8918 if (dv_toggle_prov_name) /*debug purpose*/
8919 snprintf(pdata->vf_provider_name,
8920 VDEC_PROVIDER_NAME_SIZE,
8921 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8922 VFM_DEC_DVEL_PROVIDER_NAME);
8923 else
8924 snprintf(pdata->vf_provider_name,
8925 VDEC_PROVIDER_NAME_SIZE,
8926 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8927 VFM_DEC_DVBL_PROVIDER_NAME);
8928 }
8929#endif
8930 else
8931 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8932 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8933
8934 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8935 &vf_provider_ops, pdata);
8936
8937 platform_set_drvdata(pdev, pdata);
8938
8939 buf_spec_init(hw);
8940
8941 hw->platform_dev = pdev;
8942
8943#ifdef DUMP_USERDATA_RECORD
8944 vmh264_init_userdata_dump();
8945 vmh264_reset_user_data_buf();
8946#endif
8947 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8948 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8949 h264_free_hw_stru(&pdev->dev, (void *)hw);
8950 pdata->dec_status = NULL;
8951 return -ENOMEM;
8952 }
8953
8954 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8955 DCAC_READ_MARGIN;
8956 if (hw->mmu_enable) {
8957 u32 extif_size = EXTIF_BUF_SIZE;
8958 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8959 extif_size <<= 1;
8960 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8961 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8962 h264_free_hw_stru(&pdev->dev, (void *)hw);
8963 pdata->dec_status = NULL;
8964 return -ENOMEM;
8965 }
8966 }
8967 if (!vdec_secure(pdata)) {
8968#if 1
8969 /*init internal buf*/
8970 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8971 if (tmpbuf) {
8972 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8973 codec_mm_dma_flush(tmpbuf,
8974 V_BUF_ADDR_OFFSET,
8975 DMA_TO_DEVICE);
8976 } else {
8977 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8978 V_BUF_ADDR_OFFSET);
8979 if (tmpbuf) {
8980 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8981 codec_mm_dma_flush(tmpbuf,
8982 V_BUF_ADDR_OFFSET,
8983 DMA_TO_DEVICE);
8984 codec_mm_unmap_phyaddr(tmpbuf);
8985 }
8986 }
8987#else
8988 /*init sps/pps internal buf 64k*/
8989 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8990 + (mem_sps_base - DEF_BUF_START_ADDR));
8991 memset(tmpbuf, 0, 0x10000);
8992 dma_sync_single_for_device(amports_get_dma_device(),
8993 hw->cma_alloc_addr +
8994 (mem_sps_base - DEF_BUF_START_ADDR),
8995 0x10000, DMA_TO_DEVICE);
8996#endif
8997 }
8998 /**/
8999
9000#if 0
9001 if (NULL == hw->sei_data_buffer) {
9002 hw->sei_data_buffer =
9003 dma_alloc_coherent(amports_get_dma_device(),
9004 USER_DATA_SIZE,
9005 &hw->sei_data_buffer_phys, GFP_KERNEL);
9006 if (!hw->sei_data_buffer) {
9007 pr_info("%s: Can not allocate sei_data_buffer\n",
9008 __func__);
9009 ammvdec_h264_mmu_release(hw);
9010 h264_free_hw_stru(&pdev->dev, (void *)hw);
9011 return -ENOMEM;
9012 }
9013 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9014 sei_data_buffer, sei_data_buffer_phys,
9015 (u32)sei_data_buffer_remap); */
9016 }
9017#endif
9018 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9019 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9020
9021 if (vdec_is_support_4k() ||
9022 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9023 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9024 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9025 {
9026 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9027 }else
9028 {
9029 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9030 }
9031
9032 if (vh264_init(hw) < 0) {
9033 pr_info("\nammvdec_h264 init failed.\n");
9034 ammvdec_h264_mmu_release(hw);
9035 h264_free_hw_stru(&pdev->dev, (void *)hw);
9036 pdata->dec_status = NULL;
9037 return -ENODEV;
9038 }
9039#ifdef MH264_USERDATA_ENABLE
9040 vmh264_crate_userdata_manager(hw,
9041 hw->sei_user_data_buffer,
9042 USER_DATA_SIZE);
9043#endif
9044
9045 vdec_set_prepare_level(pdata, start_decode_buf_level);
9046 if (pdata->parallel_dec == 1) {
9047 if (hw->mmu_enable == 0)
9048 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9049 else {
9050 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9051 | CORE_MASK_COMBINE);
9052 }
9053 } else
9054 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9055 | CORE_MASK_COMBINE);
9056
9057 atomic_set(&hw->vh264_active, 1);
9058
9059 return 0;
9060}
9061
9062static int ammvdec_h264_remove(struct platform_device *pdev)
9063{
9064 struct vdec_h264_hw_s *hw =
9065 (struct vdec_h264_hw_s *)
9066 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9067 int i;
9068
9069 struct vdec_s *vdec = hw_to_vdec(hw);
9070
9071 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9072 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9073 dpb_print(DECODE_ID(hw), 0,
9074 "%s force exit %d\n", __func__, __LINE__);
9075 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9076 vdec_schedule_work(&hw->work);
9077 wait_event_interruptible_timeout(hw->wait_q,
9078 (vdec->status == VDEC_STATUS_CONNECTED),
9079 msecs_to_jiffies(1000)); /* wait for work done */
9080 }
9081
9082 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9083 release_aux_data(hw, i);
9084
9085 atomic_set(&hw->vh264_active, 0);
9086
9087 if (hw->stat & STAT_TIMER_ARM) {
9088 del_timer_sync(&hw->check_timer);
9089 hw->stat &= ~STAT_TIMER_ARM;
9090 }
9091
9092 vh264_stop(hw);
9093#ifdef MH264_USERDATA_ENABLE
9094#ifdef DUMP_USERDATA_RECORD
9095 vmh264_dump_userdata();
9096#endif
9097 vmh264_destroy_userdata_manager(hw);
9098#endif
9099 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9100
9101 atomic_set(&hw->vh264_active, 0);
9102 if (vdec->parallel_dec == 1) {
9103 if (hw->mmu_enable == 0)
9104 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9105 else
9106 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9107 CORE_MASK_COMBINE);
9108 } else
9109 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9110
9111 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9112 if (vdec->parallel_dec == 1) {
9113 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9114 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9115 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9116 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9117 if (IS_VDEC_DW(hw)) {
9118 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9119 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9120 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9121 }
9122 }
9123 }
9124
9125 ammvdec_h264_mmu_release(hw);
9126 h264_free_hw_stru(&pdev->dev, (void *)hw);
9127 clk_adj_frame_count = 0;
9128
9129 return 0;
9130}
9131
9132/****************************************/
9133#ifdef CONFIG_PM
9134static int mh264_suspend(struct device *dev)
9135{
9136 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9137 return 0;
9138}
9139
9140static int mh264_resume(struct device *dev)
9141{
9142 amvdec_resume(to_platform_device(dev));
9143 return 0;
9144}
9145
9146static const struct dev_pm_ops mh264_pm_ops = {
9147 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9148};
9149#endif
9150
9151static struct platform_driver ammvdec_h264_driver = {
9152 .probe = ammvdec_h264_probe,
9153 .remove = ammvdec_h264_remove,
9154 .driver = {
9155 .name = DRIVER_NAME,
9156#ifdef CONFIG_PM
9157 .pm = &mh264_pm_ops,
9158#endif
9159 }
9160};
9161
9162static struct codec_profile_t ammvdec_h264_profile = {
9163 .name = "mh264",
9164 .profile = ""
9165};
9166
9167static struct mconfig hm264_configs[] = {
9168 MC_PU32("h264_debug_flag", &h264_debug_flag),
9169 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9170 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9171 MC_PU32("decode_timeout_val", &decode_timeout_val),
9172 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9173 MC_PU32("reference_buf_margin", &reference_buf_margin),
9174 MC_PU32("radr", &radr),
9175 MC_PU32("rval", &rval),
9176 MC_PU32("h264_debug_mask", &h264_debug_mask),
9177 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9178 MC_PI32("force_rate_streambase", &force_rate_streambase),
9179 MC_PI32("dec_control", &dec_control),
9180 MC_PI32("force_rate_framebase", &force_rate_framebase),
9181 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9182 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9183 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9184#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9185 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9186 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9187 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9188#endif
9189 MC_PU32("i_only_flag", &i_only_flag),
9190 MC_PU32("force_rate_streambase", &force_rate_streambase),
9191};
9192static struct mconfig_node hm264_node;
9193
9194
9195static int __init ammvdec_h264_driver_init_module(void)
9196{
9197 pr_info("ammvdec_h264 module init\n");
9198 if (platform_driver_register(&ammvdec_h264_driver)) {
9199 pr_info("failed to register ammvdec_h264 driver\n");
9200 return -ENODEV;
9201 }
9202
9203 if (vdec_is_support_4k()) {
9204 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9205 ammvdec_h264_profile.profile =
9206 "4k, dwrite, compressed";
9207 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9208 ammvdec_h264_profile.profile = "4k";
9209 }
9210 }
9211
9212 vcodec_profile_register(&ammvdec_h264_profile);
9213 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9214 "mh264", hm264_configs, CONFIG_FOR_RW);
9215 return 0;
9216}
9217
9218static void __exit ammvdec_h264_driver_remove_module(void)
9219{
9220 pr_info("ammvdec_h264 module remove.\n");
9221
9222 platform_driver_unregister(&ammvdec_h264_driver);
9223}
9224
9225/****************************************/
9226module_param(h264_debug_flag, uint, 0664);
9227MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9228
9229module_param(start_decode_buf_level, int, 0664);
9230MODULE_PARM_DESC(start_decode_buf_level,
9231 "\n ammvdec_h264 start_decode_buf_level\n");
9232
9233module_param(pre_decode_buf_level, int, 0664);
9234MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9235
9236module_param(fixed_frame_rate_mode, uint, 0664);
9237MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9238
9239module_param(decode_timeout_val, uint, 0664);
9240MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9241
9242module_param(errordata_timeout_val, uint, 0664);
9243MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9244
9245module_param(get_data_timeout_val, uint, 0664);
9246MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9247
9248module_param(frame_max_data_packet, uint, 0664);
9249MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9250
9251module_param(reorder_dpb_size_margin, uint, 0664);
9252MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9253
9254#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9255module_param(reorder_dpb_size_margin_dv, uint, 0664);
9256MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9257 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9258#endif
9259
9260module_param(reference_buf_margin, uint, 0664);
9261MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9262
9263#ifdef CONSTRAIN_MAX_BUF_NUM
9264module_param(run_ready_max_vf_only_num, uint, 0664);
9265MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9266
9267module_param(run_ready_display_q_num, uint, 0664);
9268MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9269
9270module_param(run_ready_max_buf_num, uint, 0664);
9271MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9272#endif
9273
9274module_param(radr, uint, 0664);
9275MODULE_PARM_DESC(radr, "\nradr\n");
9276
9277module_param(rval, uint, 0664);
9278MODULE_PARM_DESC(rval, "\nrval\n");
9279
9280module_param(h264_debug_mask, uint, 0664);
9281MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9282
9283module_param(h264_debug_cmd, uint, 0664);
9284MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9285
9286module_param(force_rate_streambase, int, 0664);
9287MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9288
9289module_param(dec_control, int, 0664);
9290MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9291
9292module_param(force_rate_framebase, int, 0664);
9293MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9294
9295module_param(force_disp_bufspec_num, int, 0664);
9296MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9297
9298module_param(V_BUF_ADDR_OFFSET, int, 0664);
9299MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9300
9301module_param(prefix_aux_buf_size, uint, 0664);
9302MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9303
9304module_param(suffix_aux_buf_size, uint, 0664);
9305MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9306
9307#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9308module_param(dv_toggle_prov_name, uint, 0664);
9309MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9310
9311module_param(dolby_meta_with_el, uint, 0664);
9312MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9313
9314#endif
9315
9316module_param(fast_output_enable, uint, 0664);
9317MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9318
9319module_param(error_proc_policy, uint, 0664);
9320MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9321
9322module_param(error_skip_count, uint, 0664);
9323MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9324
9325module_param(force_sliding_margin, uint, 0664);
9326MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9327
9328module_param(i_only_flag, uint, 0664);
9329MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9330
9331module_param(first_i_policy, uint, 0664);
9332MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9333
9334module_param(frmbase_cont_bitlevel, uint, 0664);
9335MODULE_PARM_DESC(frmbase_cont_bitlevel,
9336 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9337
9338module_param(frmbase_cont_bitlevel2, uint, 0664);
9339MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9340 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9341
9342module_param(udebug_flag, uint, 0664);
9343MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9344
9345module_param(udebug_pause_pos, uint, 0664);
9346MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9347
9348module_param(udebug_pause_val, uint, 0664);
9349MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9350
9351module_param(udebug_pause_decode_idx, uint, 0664);
9352MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9353
9354module_param(max_alloc_buf_count, uint, 0664);
9355MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9356
9357module_param(enable_itu_t35, uint, 0664);
9358MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9359
9360module_param(endian, uint, 0664);
9361MODULE_PARM_DESC(endian, "\nrval\n");
9362
9363module_param(mmu_enable, uint, 0664);
9364MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9365
9366module_param(force_enable_mmu, uint, 0664);
9367MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9368
9369module_param(again_threshold, uint, 0664);
9370MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9371
9372module_param(stream_mode_start_num, uint, 0664);
9373MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9374
9375/*
9376module_param(trigger_task, uint, 0664);
9377MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9378*/
9379module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9380
9381module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9382
9383module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9384
9385module_param_array(run_count, uint,
9386 &max_decode_instance_num, 0664);
9387
9388module_param_array(not_run_ready, uint,
9389 &max_decode_instance_num, 0664);
9390
9391module_param_array(input_empty, uint,
9392 &max_decode_instance_num, 0664);
9393
9394module_param_array(max_get_frame_interval, uint,
9395 &max_decode_instance_num, 0664);
9396
9397module_param_array(step, uint, &max_decode_instance_num, 0664);
9398
9399module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9400
9401module_param(disp_vframe_valve_level, uint, 0664);
9402MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9403
9404module_param(double_write_mode, uint, 0664);
9405MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9406
9407module_param(mem_map_mode, uint, 0664);
9408MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9409
9410module_param(without_display_mode, uint, 0664);
9411MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9412
9413
9414module_init(ammvdec_h264_driver_init_module);
9415module_exit(ammvdec_h264_driver_remove_module);
9416
9417MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9418MODULE_LICENSE("GPL");
9419
generated by cgit at 2024-05-17 11:37:13 (GMT)