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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 7a3acbdaf6f68263f72884b01f5d56115174e9f9
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120#define INVALID_IDX -1 /* Invalid buffer index.*/
121
122static int mmu_enable;
123/*mmu do not support mbaff*/
124static int force_enable_mmu = 0;
125unsigned int h264_debug_flag; /* 0xa0000000; */
126unsigned int h264_debug_mask = 0xff;
127 /*
128 *h264_debug_cmd:
129 * 0x1xx, force decoder id of xx to be disconnected
130 */
131unsigned int h264_debug_cmd;
132
133static unsigned int dec_control =
134 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
135 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
136
137static unsigned int force_rate_streambase;
138static unsigned int force_rate_framebase;
139static unsigned int force_disp_bufspec_num;
140static unsigned int fixed_frame_rate_mode;
141static unsigned int error_recovery_mode_in;
142static int start_decode_buf_level = 0x4000;
143static int pre_decode_buf_level = 0x1000;
144static int stream_mode_start_num = 4;
145
146#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
147/*to make reorder size difference of bl and el not too big*/
148static unsigned int reorder_dpb_size_margin_dv = 16;
149#endif
150static unsigned int reorder_dpb_size_margin = 6;
151static unsigned int reference_buf_margin = 4;
152
153#ifdef CONSTRAIN_MAX_BUF_NUM
154static u32 run_ready_max_vf_only_num;
155static u32 run_ready_display_q_num;
156 /*0: not check
157 0xff: mDPB.size
158 */
159static u32 run_ready_max_buf_num = 0xff;
160#endif
161
162#define VDEC_ASSIST_CANVAS_BLK32 0x5
163
164
165static unsigned int max_alloc_buf_count;
166static unsigned int decode_timeout_val = 100;
167static unsigned int errordata_timeout_val = 50;
168static unsigned int get_data_timeout_val = 2000;
169#if 1
170/* H264_DATA_REQUEST does not work, disable it,
171decode has error for data in none continuous address
172*/
173static unsigned int frame_max_data_packet;
174#else
175static unsigned int frame_max_data_packet = 8;
176#endif
177static unsigned int radr;
178static unsigned int rval;
179static u32 endian = 0xff0;
180
181/*
182 udebug_flag:
183 bit 0, enable ucode print
184 bit 1, enable ucode detail print
185 bit 3, disable ucode watchdog
186 bit [31:16] not 0, pos to dump lmem
187 bit 2, pop bits to lmem
188 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
189*/
190static u32 udebug_flag;
191/*
192 when udebug_flag[1:0] is not 0
193 udebug_pause_pos not 0,
194 pause position
195*/
196static u32 udebug_pause_pos;
197/*
198 when udebug_flag[1:0] is not 0
199 and udebug_pause_pos is not 0,
200 pause only when DEBUG_REG2 is equal to this val
201*/
202static u32 udebug_pause_val;
203
204static u32 udebug_pause_decode_idx;
205
206static unsigned int disp_vframe_valve_level;
207
208static unsigned int max_decode_instance_num = H264_DEV_NUM;
209static unsigned int decode_frame_count[H264_DEV_NUM];
210static unsigned int display_frame_count[H264_DEV_NUM];
211static unsigned int max_process_time[H264_DEV_NUM];
212static unsigned int max_get_frame_interval[H264_DEV_NUM];
213static unsigned int run_count[H264_DEV_NUM];
214static unsigned int input_empty[H264_DEV_NUM];
215static unsigned int not_run_ready[H264_DEV_NUM];
216static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
217{1, 1, 1, 1, 1, 1, 1, 1, 1};
218
219#define VDEC_CLOCK_ADJUST_FRAME 30
220static unsigned int clk_adj_frame_count;
221
222/*
223 *bit[3:0]: 0, run ; 1, pause; 3, step
224 *bit[4]: 1, schedule run
225 */
226static unsigned int step[H264_DEV_NUM];
227
228#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
229static u32 prefix_aux_buf_size = (16 * 1024);
230static u32 suffix_aux_buf_size;
231
232#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
233static u32 dv_toggle_prov_name;
234
235static u32 dolby_meta_with_el;
236#endif
237
238/*
239 bit[8]
240 0: use sys_info[bit 3]
241 not 0:use i_only_flag[7:0]
242 bit[7:0]:
243 bit 0, 1: only display I picture;
244 bit 1, 1: only decode I picture;
245*/
246static unsigned int i_only_flag;
247
248/*
249 error_proc_policy:
250 bit[0] send_error_frame_flag;
251 (valid when bit[31] is 1, otherwise use sysinfo)
252 bit[1] do not decode if config_decode_buf() fail
253 bit[2] force release buf if in deadlock
254 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
255 bit[4] check inactive of receiver
256 bit[5] reset buffmgr if in deadlock
257 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
258 bit[7] reset buffmgr if dpb error
259
260 bit[8] check total mbx/mby of decoded frame
261 bit[9] check ERROR_STATUS_REG
262 bit[10] check reference list
263 bit[11] mark error if dpb error
264 bit[12] i_only when error happen
265 bit[13] 0: mark error according to last pic, 1: ignore mark error
266 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
267*/
268static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
269
270
271/*
272 error_skip_count:
273 bit[11:0] error skip frame count
274 bit[15:12] error skip i picture count
275*/
276static unsigned int error_skip_count = (0x2 << 12) | 0x40;
277
278static unsigned int force_sliding_margin;
279/*
280 bit[1:0]:
281 0, start playing from any frame
282 1, start playing from I frame
283 bit[15:8]: the count of skip frames after first I
284 2, start playing from second I frame (decode from the first I)
285 bit[15:8]: the max count of skip frames after first I
286 3, start playing from IDR
287*/
288static unsigned int first_i_policy = 1;
289
290/*
291 fast_output_enable:
292 bit [0], output frame if there is IDR in list
293 bit [1], output frame if the current poc is 1 big than the previous poc
294 bit [2], if even poc only, output frame ifthe cuurent poc
295 is 2 big than the previous poc
296 bit [3], ip only
297*/
298static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
299
300static unsigned int enable_itu_t35 = 1;
301
302static unsigned int frmbase_cont_bitlevel = 0x40;
303
304static unsigned int frmbase_cont_bitlevel2 = 0x1;
305
306
307#define MH264_USERDATA_ENABLE
308
309/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
310/* hevc->double_write_mode:
311 0, no double write
312 1, 1:1 ratio
313 2, (1/4):(1/4) ratio
314 3, (1/4):(1/4) ratio, with both compressed frame included
315 4, (1/2):(1/2) ratio
316 0x10, double write only
317 0x10000: vdec dw horizotal 1/2
318 0x20000: vdec dw horizotal/vertical 1/2
319*/
320static u32 double_write_mode;
321static u32 without_display_mode;
322#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
323
324static void vmh264_dump_state(struct vdec_s *vdec);
325
326#define is_in_parsing_state(status) \
327 ((status == H264_ACTION_SEARCH_HEAD) || \
328 ((status & 0xf0) == 0x80))
329
330#define is_interlace(frame) \
331 (frame->frame &&\
332 frame->top_field &&\
333 frame->bottom_field &&\
334 (!frame->frame->coded_frame))
335static inline bool close_to(int a, int b, int m)
336{
337 return (abs(a - b) < m) ? true : false;
338}
339
340#if 0
341#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
342#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
343#else
344#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
345#define h264_free_hw_stru(dev, hw) vfree(hw)
346#endif
347
348/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
349#define NV21
350/* #endif */
351
352/* 12M for L41 */
353#define MAX_DPB_BUFF_SIZE (12*1024*1024)
354#define DEFAULT_MEM_SIZE (32*1024*1024)
355#define AVIL_DPB_BUFF_SIZE 0x01ec2000
356
357#define DEF_BUF_START_ADDR 0x01000000
358#define mem_sps_base 0x011c3c00
359#define mem_pps_base 0x011cbc00
360/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
361u32 V_BUF_ADDR_OFFSET = 0x200000;
362#define DCAC_READ_MARGIN (64 * 1024)
363
364
365#define EXTEND_SAR 0xff
366#define BUFSPEC_POOL_SIZE 64
367#define VF_POOL_SIZE 64
368#define VF_POOL_NUM 2
369#define MAX_VF_BUF_NUM 27
370#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
371#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
372#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
373#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
374#define EXTIF_BUF_SIZE (0x10000 * 2)
375
376#define HEADER_BUFFER_IDX(n) (n)
377#define VF_BUFFER_IDX(n) (n)
378
379
380#define PUT_INTERVAL (HZ/100)
381#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
382
383#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
384#define SWITCHING_STATE_OFF 0
385#define SWITCHING_STATE_ON_CMD3 1
386#define SWITCHING_STATE_ON_CMD1 2
387
388
389
390#define INCPTR(p) ptr_atomic_wrap_inc(&p)
391
392#define SLICE_TYPE_I 2
393#define SLICE_TYPE_P 5
394#define SLICE_TYPE_B 6
395
396struct buffer_spec_s {
397 /*
398 used:
399 -1, none allocated
400 0, allocated, free
401 1, used by dpb
402 2, in disp queue;
403 3, in disp queue, isolated,
404 do not use for dpb when vf_put;
405 4, to release
406 5, in disp queue, isolated (but not to release)
407 do not use for dpb when vf_put;
408 */
409 unsigned int used;
410 unsigned int info0;
411 unsigned int info1;
412 unsigned int info2;
413 unsigned int y_addr;
414 unsigned int u_addr;
415 unsigned int v_addr;
416
417 int y_canvas_index;
418 int u_canvas_index;
419 int v_canvas_index;
420
421#ifdef VDEC_DW
422 unsigned int vdec_dw_y_addr;
423 unsigned int vdec_dw_u_addr;
424 unsigned int vdec_dw_v_addr;
425
426 int vdec_dw_y_canvas_index;
427 int vdec_dw_u_canvas_index;
428 int vdec_dw_v_canvas_index;
429#ifdef NV21
430 struct canvas_config_s vdec_dw_canvas_config[2];
431#else
432 struct canvas_config_s vdec_dw_canvas_config[3];
433#endif
434#endif
435
436#ifdef NV21
437 struct canvas_config_s canvas_config[2];
438#else
439 struct canvas_config_s canvas_config[3];
440#endif
441 unsigned long cma_alloc_addr;
442 unsigned int buf_adr;
443#ifdef H264_MMU
444 unsigned long alloc_header_addr;
445#endif
446 char *aux_data_buf;
447 int aux_data_size;
448#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
449 unsigned char dv_enhance_exist;
450#endif
451 int canvas_pos;
452 int vf_ref;
453 /*unsigned int comp_body_size;*/
454 unsigned int dw_y_adr;
455 unsigned int dw_u_v_adr;
456};
457
458#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
459#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
460#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
461
462
463#define vdec_dw_spec2canvas(x) \
464 (((x)->vdec_dw_v_canvas_index << 16) | \
465 ((x)->vdec_dw_u_canvas_index << 8) | \
466 ((x)->vdec_dw_y_canvas_index << 0))
467
468
469#define spec2canvas(x) \
470 (((x)->v_canvas_index << 16) | \
471 ((x)->u_canvas_index << 8) | \
472 ((x)->y_canvas_index << 0))
473
474#define FRAME_INDEX(vf_index) (vf_index & 0xff)
475#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
476#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
477
478static struct vframe_s *vh264_vf_peek(void *);
479static struct vframe_s *vh264_vf_get(void *);
480static void vh264_vf_put(struct vframe_s *, void *);
481static int vh264_vf_states(struct vframe_states *states, void *);
482static int vh264_event_cb(int type, void *data, void *private_data);
483static void vh264_work(struct work_struct *work);
484static void vh264_timeout_work(struct work_struct *work);
485static void vh264_notify_work(struct work_struct *work);
486#ifdef MH264_USERDATA_ENABLE
487static void user_data_ready_notify_work(struct work_struct *work);
488static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
489#endif
490
491static const char vh264_dec_id[] = "vh264-dev";
492
493#define PROVIDER_NAME "vdec.h264"
494
495static const struct vframe_operations_s vf_provider_ops = {
496 .peek = vh264_vf_peek,
497 .get = vh264_vf_get,
498 .put = vh264_vf_put,
499 .event_cb = vh264_event_cb,
500 .vf_states = vh264_vf_states,
501};
502
503#define DEC_RESULT_NONE 0
504#define DEC_RESULT_DONE 1
505#define DEC_RESULT_AGAIN 2
506#define DEC_RESULT_CONFIG_PARAM 3
507#define DEC_RESULT_GET_DATA 4
508#define DEC_RESULT_GET_DATA_RETRY 5
509#define DEC_RESULT_ERROR 6
510#define DEC_RESULT_EOS 7
511#define DEC_RESULT_FORCE_EXIT 8
512
513/*
514 *static const char *dec_result_str[] = {
515 * "DEC_RESULT_NONE ",
516 * "DEC_RESULT_DONE ",
517 * "DEC_RESULT_AGAIN ",
518 * "DEC_RESULT_CONFIG_PARAM",
519 * "DEC_RESULT_GET_DATA ",
520 * "DEC_RESULT_GET_DA_RETRY",
521 * "DEC_RESULT_ERROR ",
522 *};
523 */
524
525#define UCODE_IP_ONLY 2
526#define UCODE_IP_ONLY_PARAM 1
527
528#define MC_OFFSET_HEADER 0x0000
529#define MC_OFFSET_DATA 0x1000
530#define MC_OFFSET_MMCO 0x2000
531#define MC_OFFSET_LIST 0x3000
532#define MC_OFFSET_SLICE 0x4000
533#define MC_OFFSET_MAIN 0x5000
534
535#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
536#define MC_SWAP_SIZE (4*SZ_1K)
537#define MODE_ERROR 0
538#define MODE_FULL 1
539
540#define DFS_HIGH_THEASHOLD 3
541
542#define INIT_FLAG_REG AV_SCRATCH_2
543#define HEAD_PADING_REG AV_SCRATCH_3
544#define UCODE_WATCHDOG_REG AV_SCRATCH_7
545#define LMEM_DUMP_ADR AV_SCRATCH_L
546#define DEBUG_REG1 AV_SCRATCH_M
547#define DEBUG_REG2 AV_SCRATCH_N
548#define FRAME_COUNTER_REG AV_SCRATCH_I
549#define RPM_CMD_REG AV_SCRATCH_A
550#define H264_DECODE_SIZE AV_SCRATCH_E
551#define H264_DECODE_MODE AV_SCRATCH_4
552#define H264_DECODE_SEQINFO AV_SCRATCH_5
553#define H264_AUX_ADR AV_SCRATCH_C
554#define H264_AUX_DATA_SIZE AV_SCRATCH_H
555
556#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
557#define DPB_STATUS_REG AV_SCRATCH_J
558#define ERROR_STATUS_REG AV_SCRATCH_9
559 /*
560 NAL_SEARCH_CTL: bit 0, enable itu_t35
561 NAL_SEARCH_CTL: bit 1, enable mmu
562 */
563#define NAL_SEARCH_CTL AV_SCRATCH_9
564#define MBY_MBX MB_MOTION_MODE /*0xc07*/
565
566#define DECODE_MODE_SINGLE 0x0
567#define DECODE_MODE_MULTI_FRAMEBASE 0x1
568#define DECODE_MODE_MULTI_STREAMBASE 0x2
569#define DECODE_MODE_MULTI_DVBAL 0x3
570#define DECODE_MODE_MULTI_DVENL 0x4
571static DEFINE_MUTEX(vmh264_mutex);
572
573
574
575#ifdef MH264_USERDATA_ENABLE
576
577struct mh264_userdata_record_t {
578 struct userdata_meta_info_t meta_info;
579 u32 rec_start;
580 u32 rec_len;
581};
582
583struct mh264_ud_record_wait_node_t {
584 struct list_head list;
585 struct mh264_userdata_record_t ud_record;
586};
587#define USERDATA_FIFO_NUM 256
588#define MAX_FREE_USERDATA_NODES 5
589
590struct mh264_userdata_info_t {
591 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
592 u8 *data_buf;
593 u8 *data_buf_end;
594 u32 buf_len;
595 u32 read_index;
596 u32 write_index;
597 u32 last_wp;
598};
599
600
601#endif
602
603struct vdec_h264_hw_s {
604 spinlock_t lock;
605 spinlock_t bufspec_lock;
606 int id;
607 struct platform_device *platform_dev;
608 unsigned long cma_alloc_addr;
609 /* struct page *collocate_cma_alloc_pages; */
610 unsigned long collocate_cma_alloc_addr;
611
612 u32 prefix_aux_size;
613 u32 suffix_aux_size;
614 void *aux_addr;
615 dma_addr_t aux_phy_addr;
616
617 /* buffer for store all sei data */
618 void *sei_data_buf;
619 u32 sei_data_len;
620
621 /* buffer for storing one itu35 recored */
622 void *sei_itu_data_buf;
623 u32 sei_itu_data_len;
624
625 /* recycle buffer for user data storing all itu35 records */
626 void *sei_user_data_buffer;
627 u32 sei_user_data_wp;
628#ifdef MH264_USERDATA_ENABLE
629 struct work_struct user_data_ready_work;
630#endif
631 struct StorablePicture *last_dec_picture;
632
633 ulong lmem_addr;
634 dma_addr_t lmem_addr_remap;
635
636 void *bmmu_box;
637#ifdef H264_MMU
638 void *mmu_box;
639 void *frame_mmu_map_addr;
640 dma_addr_t frame_mmu_map_phy_addr;
641 u32 hevc_cur_buf_idx;
642 u32 losless_comp_body_size;
643 u32 losless_comp_body_size_sao;
644 u32 losless_comp_header_size;
645 u32 mc_buffer_size_u_v;
646 u32 mc_buffer_size_u_v_h;
647 u32 is_idr_frame;
648 u32 is_new_pic;
649 u32 frame_done;
650 u32 frame_busy;
651 unsigned long extif_addr;
652 int double_write_mode;
653 int mmu_enable;
654#endif
655
656 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
657 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
658
659 int cur_pool;
660 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
661 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
662 struct vframe_s switching_fense_vf;
663 struct h264_dpb_stru dpb;
664 u8 init_flag;
665 u8 first_sc_checked;
666 u8 has_i_frame;
667 u8 config_bufmgr_done;
668 u32 max_reference_size;
669 u32 decode_pic_count;
670 u32 reflist_error_count;
671 int start_search_pos;
672 u32 reg_iqidct_control;
673 u32 reg_vcop_ctrl_reg;
674 u32 reg_rv_ai_mb_count;
675 u32 vld_dec_control;
676 struct vframe_s vframe_dummy;
677
678 unsigned char buffer_empty_flag;
679
680 u32 frame_width;
681 u32 frame_height;
682 u32 frame_dur;
683 u32 frame_prog;
684 u32 frame_packing_type;
685
686 struct vframe_chunk_s *chunk;
687
688 u32 stat;
689 unsigned long buf_start;
690 u32 buf_offset;
691 u32 buf_size;
692 /* u32 ucode_map_start; */
693 u32 pts_outside;
694 u32 sync_outside;
695 u32 vh264_ratio;
696 u32 vh264_rotation;
697 u32 use_idr_framerate;
698
699 u32 seq_info;
700 u32 seq_info2;
701 u32 video_signal_from_vui; /*to do .. */
702 u32 timing_info_present_flag;
703 u32 fixed_frame_rate_flag;
704 u32 bitstream_restriction_flag;
705 u32 num_reorder_frames;
706 u32 max_dec_frame_buffering;
707 u32 iframe_count;
708 u32 aspect_ratio_info;
709 u32 num_units_in_tick;
710 u32 time_scale;
711 u32 h264_ar;
712 bool h264_first_valid_pts_ready;
713 u32 h264pts1;
714 u32 h264pts2;
715 u32 pts_duration;
716 u32 h264_pts_count;
717 u32 duration_from_pts_done;
718 u32 pts_unstable;
719 u32 unstable_pts;
720 u32 last_checkout_pts;
721 u32 max_refer_buf;
722
723 s32 vh264_stream_switching_state;
724 struct vframe_s *p_last_vf;
725 u32 last_pts;
726 u32 last_pts_remainder;
727 u32 last_duration;
728 u32 last_mb_width, last_mb_height;
729 bool check_pts_discontinue;
730 bool pts_discontinue;
731 u32 wait_buffer_counter;
732 u32 first_offset;
733 u32 first_pts;
734 u64 first_pts64;
735 bool first_pts_cached;
736 u64 last_pts64;
737#if 0
738 void *sei_data_buffer;
739 dma_addr_t sei_data_buffer_phys;
740#endif
741
742 uint error_recovery_mode;
743 uint mb_total;
744 uint mb_width;
745 uint mb_height;
746
747 uint i_only;
748 int skip_frame_count;
749 bool no_poc_reorder_flag;
750 bool send_error_frame_flag;
751 dma_addr_t mc_dma_handle;
752 void *mc_cpu_addr;
753 int vh264_reset;
754
755 atomic_t vh264_active;
756
757 struct dec_sysinfo vh264_amstream_dec_info;
758
759 int dec_result;
760 struct work_struct work;
761 struct work_struct notify_work;
762 struct work_struct timeout_work;
763 void (*vdec_cb)(struct vdec_s *, void *);
764 void *vdec_cb_arg;
765
766 struct timer_list check_timer;
767
768 /**/
769 unsigned int last_frame_time;
770 u32 vf_pre_count;
771 u32 vf_get_count;
772 u32 vf_put_count;
773
774 /* timeout handle */
775 unsigned long int start_process_time;
776 unsigned int last_mby_mbx;
777 unsigned int last_vld_level;
778 unsigned int decode_timeout_count;
779 unsigned int timeout_num;
780 unsigned int search_dataempty_num;
781 unsigned int decode_timeout_num;
782 unsigned int decode_dataempty_num;
783 unsigned int buffer_empty_recover_num;
784
785 unsigned get_data_count;
786 unsigned get_data_start_time;
787 /**/
788
789 /*log*/
790 unsigned int packet_write_success_count;
791 unsigned int packet_write_EAGAIN_count;
792 unsigned int packet_write_ENOMEM_count;
793 unsigned int packet_write_EFAULT_count;
794 unsigned int total_read_size_pre;
795 unsigned int total_read_size;
796 unsigned int frame_count_pre;
797#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
798 u8 switch_dvlayer_flag;
799 u8 got_valid_nal;
800#endif
801 u8 eos;
802 u8 data_flag;
803 u32 no_error_count;
804 u32 no_error_i_count;
805 /*
806 NODISP_FLAG
807 */
808 u8 dec_flag;
809
810 u32 ucode_pause_pos;
811
812 u8 reset_bufmgr_flag;
813 u32 reset_bufmgr_count;
814 u32 cfg_param1;
815 u32 cfg_param2;
816 u32 cfg_param3;
817 u32 cfg_param4;
818 int valve_count;
819 u8 next_again_flag;
820 u32 pre_parser_wr_ptr;
821 struct firmware_s *fw;
822 struct firmware_s *fw_mmu;
823#ifdef MH264_USERDATA_ENABLE
824 /*user data*/
825 struct mutex userdata_mutex;
826 struct mh264_userdata_info_t userdata_info;
827 struct mh264_userdata_record_t ud_record;
828 int wait_for_udr_send;
829#endif
830 u32 no_mem_count;
831 u32 canvas_mode;
832 bool is_used_v4l;
833 void *v4l2_ctx;
834 bool v4l_params_parsed;
835 wait_queue_head_t wait_q;
836 u32 reg_g_status;
837 struct mutex chunks_mutex;
838 int need_cache_size;
839 u64 sc_start_time;
840 u8 frmbase_cont_flag;
841 struct vframe_qos_s vframe_qos;
842 int frameinfo_enable;
843 bool first_head_check_flag;
844 unsigned int height_aspect_ratio;
845 unsigned int width_aspect_ratio;
846 bool new_iframe_flag;
847 bool ref_err_flush_dpb_flag;
848 unsigned int first_i_policy;
849 u32 reorder_dpb_size_margin;
850 bool wait_reset_done_flag;
851};
852
853static u32 again_threshold;
854
855static void timeout_process(struct vdec_h264_hw_s *hw);
856static void dump_bufspec(struct vdec_h264_hw_s *hw,
857 const char *caller);
858static void h264_reconfig(struct vdec_h264_hw_s *hw);
859static void h264_reset_bufmgr(struct vdec_s *vdec);
860static void vh264_local_init(struct vdec_h264_hw_s *hw);
861static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
862static int vh264_stop(struct vdec_h264_hw_s *hw);
863static s32 vh264_init(struct vdec_h264_hw_s *hw);
864static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
865 u32 index);
866static void release_aux_data(struct vdec_h264_hw_s *hw,
867 int buf_spec_num);
868#ifdef ERROR_HANDLE_TEST
869static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
870#endif
871
872#define H265_PUT_SAO_4K_SET 0x03
873#define H265_ABORT_SAO_4K_SET 0x04
874#define H265_ABORT_SAO_4K_SET_DONE 0x05
875
876#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
877#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
878#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
879#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
880#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
881
882
883#define HEVC_CM_HEADER_START_ADDR 0x3628
884#define HEVC_CM_BODY_START_ADDR 0x3626
885#define HEVC_CM_BODY_LENGTH 0x3627
886#define HEVC_CM_HEADER_LENGTH 0x3629
887#define HEVC_CM_HEADER_OFFSET 0x362b
888#define HEVC_SAO_CTRL9 0x362d
889#define HEVCD_MPP_DECOMP_CTL3 0x34c4
890#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
891#define HEVC_DBLK_CFGB 0x350b
892#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
893
894#define H265_DW_NO_SCALE
895#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
896#define H265_LOSLESS_COMPRESS_MODE
897#define MAX_FRAME_4K_NUM 0x1200
898#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
899
900/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
901static u32 mem_map_mode = H265_MEM_MAP_MODE;
902
903#define MAX_SIZE_8K (8192 * 4608)
904#define MAX_SIZE_4K (4096 * 2304)
905
906static int is_oversize(int w, int h)
907{
908 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
909 MAX_SIZE_8K : MAX_SIZE_4K;
910
911 if (w < 0 || h < 0)
912 return true;
913
914 if (h != 0 && (w > max / h))
915 return true;
916
917 return false;
918}
919
920static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
921 int frame_type,
922 u32 vpts,
923 u32 vpts_valid);
924static int compute_losless_comp_body_size(int width,
925 int height, int bit_depth_10);
926static int compute_losless_comp_header_size(int width, int height);
927
928static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
929 int pic_width, int pic_height, u16 bit_depth,
930 unsigned int *mmu_index_adr) {
931 int cur_buf_idx;
932 int bit_depth_10 = (bit_depth != 0x00);
933 int picture_size;
934 u32 cur_mmu_4k_number;
935
936 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
937 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
938 picture_size = compute_losless_comp_body_size(pic_width,
939 pic_height, bit_depth_10);
940 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
941 dpb_print(DECODE_ID(hw),
942 PRINT_FLAG_MMU_DETAIL,
943 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
944 cur_buf_idx, picture_size, cur_mmu_4k_number);
945
946 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
947 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
948 cur_mmu_4k_number);
949 return -1;
950 }
951
952 return decoder_mmu_box_alloc_idx(
953 hw->mmu_box,
954 cur_buf_idx,
955 cur_mmu_4k_number,
956 mmu_index_adr);
957}
958
959static int compute_losless_comp_body_size(int width,
960 int height, int bit_depth_10)
961{
962 int width_x64;
963 int height_x32;
964 int bsize;
965
966 width_x64 = width + 63;
967 width_x64 >>= 6;
968
969 height_x32 = height + 31;
970 height_x32 >>= 5;
971
972#ifdef H264_MMU
973 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
974#else
975 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
976#endif
977 return bsize;
978}
979
980static int compute_losless_comp_header_size(int width, int height)
981{
982 int width_x64;
983 int width_x128;
984 int height_x64;
985 int hsize;
986
987 width_x64 = width + 63;
988 width_x64 >>= 6;
989
990 width_x128 = width + 127;
991 width_x128 >>= 7;
992
993 height_x64 = height + 63;
994 height_x64 >>= 6;
995
996#ifdef H264_MMU
997 hsize = 128*width_x64*height_x64;
998#else
999 hsize = 32*width_x128*height_x64;
1000#endif
1001 return hsize;
1002}
1003
1004static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1005{
1006 int ratio = 1;
1007 int dw_mode = hw->double_write_mode;
1008 if ((dw_mode == 2) ||
1009 (dw_mode == 3))
1010 ratio = 4;
1011 else if (dw_mode == 4)
1012 ratio = 2;
1013 return ratio;
1014}
1015
1016
1017static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1018{
1019 int pic_width, pic_height;
1020 int lcu_size = 16;
1021 int dw_buf_size;
1022 u32 dw_buffer_size_u_v;
1023 u32 dw_buffer_size_u_v_h;
1024 int dw_mode = hw->double_write_mode;
1025
1026 pic_width = hw->frame_width;
1027 pic_height = hw->frame_height;
1028
1029 if (dw_mode) {
1030 int pic_width_dw = pic_width /
1031 get_double_write_ratio(hw);
1032 int pic_height_dw = pic_height /
1033 get_double_write_ratio(hw);
1034
1035 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1036 pic_width_dw / lcu_size + 1 :
1037 pic_width_dw / lcu_size;
1038 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1039 pic_height_dw / lcu_size + 1 :
1040 pic_height_dw / lcu_size;
1041 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1042
1043
1044 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1045 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1046 /*64k alignment*/
1047 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1048 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1049 } else {
1050 *pdw_buffer_size_u_v_h = 0;
1051 dw_buf_size = 0;
1052 }
1053
1054 return dw_buf_size;
1055}
1056
1057
1058static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1059{
1060 int i, size;
1061 u32 canvas_addr;
1062 unsigned long maddr;
1063 int num_buff = hw->dpb.mDPB.size;
1064 int dw_size = 0;
1065 u32 dw_buffer_size_u_v_h;
1066 u32 blkmode = hw->canvas_mode;
1067 int dw_mode = hw->double_write_mode;
1068
1069 canvas_addr = ANC0_CANVAS_ADDR;
1070 for (i = 0; i < num_buff; i++)
1071 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1072
1073 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1074 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1075
1076
1077 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1078 size += dw_size;
1079 if (size > 0)
1080 size += 0x10000;
1081
1082 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1083 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1084 dw_buffer_size_u_v_h, dw_size, size);
1085
1086 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1087 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1088 hw->losless_comp_body_size,
1089 hw->losless_comp_header_size,
1090 hw->losless_comp_body_size_sao);
1091
1092 for (i = 0; i < num_buff; i++) {
1093 if (!restore) {
1094 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1095 HEADER_BUFFER_IDX(i), size,
1096 DRIVER_HEADER_NAME, &maddr) < 0) {
1097 dpb_print(DECODE_ID(hw), 0,
1098 "%s malloc compress header failed %d\n",
1099 DRIVER_HEADER_NAME, i);
1100 return;
1101 }
1102 } else
1103 maddr = hw->buffer_spec[i].alloc_header_addr;
1104 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1105 hw->buffer_spec[i].alloc_header_addr = maddr;
1106 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1107 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1108 __func__, i, (u32)maddr, size);
1109
1110 if (dw_mode) {
1111 u32 addr;
1112 int canvas_w;
1113 int canvas_h;
1114
1115 canvas_w = hw->frame_width /
1116 get_double_write_ratio(hw);
1117 canvas_h = hw->frame_height /
1118 get_double_write_ratio(hw);
1119
1120 if (hw->canvas_mode == 0)
1121 canvas_w = ALIGN(canvas_w, 32);
1122 else
1123 canvas_w = ALIGN(canvas_w, 64);
1124 canvas_h = ALIGN(canvas_h, 32);
1125
1126 hw->buffer_spec[i].dw_y_adr =
1127 maddr + hw->losless_comp_header_size;
1128
1129 hw->buffer_spec[i].dw_y_adr =
1130 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1131 << 16;
1132 hw->buffer_spec[i].dw_u_v_adr =
1133 hw->buffer_spec[i].dw_y_adr
1134 + (dw_buffer_size_u_v_h << 16) * 2;
1135
1136
1137 hw->buffer_spec[i].buf_adr
1138 = hw->buffer_spec[i].dw_y_adr;
1139 addr = hw->buffer_spec[i].buf_adr;
1140
1141
1142 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1143 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1144 hw->buffer_spec[i].dw_y_adr,
1145 hw->buffer_spec[i].dw_u_v_adr,
1146 hw->buffer_spec[i].y_addr,
1147 hw->buffer_spec[i].u_addr,
1148 hw->buffer_spec[i].v_addr,
1149 canvas_w,
1150 canvas_h);
1151
1152 hw->buffer_spec[i].canvas_config[0].phy_addr =
1153 hw->buffer_spec[i].dw_y_adr;
1154 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1155 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1156 hw->buffer_spec[i].canvas_config[0].block_mode =
1157 blkmode;
1158 hw->buffer_spec[i].canvas_config[0].endian = 7;
1159
1160 hw->buffer_spec[i].canvas_config[1].phy_addr =
1161 hw->buffer_spec[i].dw_u_v_adr;
1162 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1163 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1164 hw->buffer_spec[i].canvas_config[1].block_mode =
1165 blkmode;
1166 hw->buffer_spec[i].canvas_config[1].endian = 7;
1167 }
1168 }
1169 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1170
1171 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1172 for (i = 0; i < 32; i++)
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1174 return;
1175}
1176static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1177{
1178 u32 i;
1179 u32 ref_canv;
1180 struct Slice *pSlice = &(hw->dpb.mSlice);
1181 /*REFLIST[0]*/
1182 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1183 struct StorablePicture *ref = pSlice->listX[0][i];
1184 if (ref == NULL)
1185 return;
1186 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1187 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1188 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1189 (ref->buf_spec_num & 0x3f) << 8);
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1191 }
1192 /*REFLIST[1]*/
1193 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1194 struct StorablePicture *ref = pSlice->listX[1][i];
1195 if (ref == NULL)
1196 return;
1197 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1198 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1199 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1200 (ref->buf_spec_num & 0x3f) << 8);
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1202 }
1203 return;
1204}
1205
1206static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1207{
1208 u32 rdata32;
1209 u32 rdata32_2;
1210 u32 slice_type;
1211 struct StorablePicture *ref;
1212 struct Slice *pSlice;
1213 slice_type = hw->dpb.mSlice.slice_type;
1214 pSlice = &(hw->dpb.mSlice);
1215 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1216 if (slice_type == I_SLICE) {
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1218 return;
1219 }
1220 if (slice_type == B_SLICE) {
1221 ref = pSlice->listX[0][0];
1222 if (ref == NULL)
1223 return;
1224 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1225 ((ref->buf_spec_num & 0x3f) << 8));
1226 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1227 rdata32 = rdata32 & 0xffff;
1228 rdata32 = rdata32 | (rdata32 << 16);
1229 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1230
1231 ref = pSlice->listX[1][0];
1232 if (ref == NULL)
1233 return;
1234 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1235 ((ref->buf_spec_num & 0x3f) << 8));
1236 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1237 rdata32_2 = rdata32_2 & 0xffff;
1238 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1239 if (rdata32 == rdata32_2) {
1240 ref = pSlice->listX[1][1];
1241 if (ref == NULL)
1242 return;
1243 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1244 ((ref->buf_spec_num & 0x3f) << 8));
1245 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1246 rdata32_2 = rdata32_2 & 0xffff;
1247 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1248 }
1249 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1250 } else { /*P-PIC*/
1251 ref = pSlice->listX[0][0];
1252 if (ref == NULL)
1253 return;
1254 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1255 ((ref->buf_spec_num & 0x3f) << 8));
1256 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1257 rdata32 = rdata32 & 0xffff;
1258 rdata32 = rdata32 | (rdata32 << 16);
1259 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1260
1261 ref = pSlice->listX[0][1];
1262 if (ref == NULL)
1263 return;
1264 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1265 ((ref->buf_spec_num & 0x3f) << 8));
1266 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1267 rdata32 = rdata32 & 0xffff;
1268 rdata32 = rdata32 | (rdata32 << 16);
1269 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1270 }
1271 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1272 return;
1273}
1274
1275
1276static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1277 u32 width, u32 height) {
1278 u32 data32;
1279 u32 lcu_x_num, lcu_y_num;
1280 u32 lcu_total;
1281 u32 mc_buffer_size_u_v;
1282 u32 mc_buffer_size_u_v_h;
1283 int dw_mode = hw->double_write_mode;
1284
1285 lcu_x_num = (width + 15) >> 4;
1286 lcu_y_num = (height + 15) >> 4;
1287 lcu_total = lcu_x_num * lcu_y_num;
1288
1289 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1290 hw->mc_buffer_size_u_v_h =
1291 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1292
1293 hw->losless_comp_body_size = 0;
1294
1295 hw->losless_comp_body_size_sao =
1296 compute_losless_comp_body_size(width, height, 0);
1297 hw->losless_comp_header_size =
1298 compute_losless_comp_header_size(width, height);
1299
1300 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1301 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1302
1303 /* setup lcu_size = 16*/
1304 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1305 /*pic_width/pic_height*/
1306 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1307 (height & 0xffff) << 16 | (width & 0xffff));
1308 /* bitdepth_luma = 8*/
1309 /* bitdepth_chroma = 8*/
1310 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1311
1312#ifdef H265_LOSLESS_COMPRESS_MODE
1313 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1314 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1315#else
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1317#endif
1318 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1319 data32 &= (~0x30);
1320 data32 |= (hw->canvas_mode << 4);
1321 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1322
1323 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1324 (0x80 << 20) | (0x80 << 10) | (0xff));
1325
1326 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1327
1328 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1329 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1330 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1331 /* ipp_enable*/
1332 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1333
1334 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1335 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1336 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1337 if (dw_mode)
1338 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1339 else
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1341 }
1342
1343 data32 = READ_VREG(HEVC_SAO_CTRL0);
1344 data32 &= (~0xf);
1345 data32 |= 0x4;
1346 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1347 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1348 (width & 0xffff));
1349 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1350
1351 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1352 data32 = (lcu_x_num | lcu_y_num << 16);
1353 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1354 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1355 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16);
1357 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1358
1359 data32 = READ_VREG(HEVC_SAO_CTRL1);
1360 data32 &= (~0x3000);
1361 data32 &= (~0xff0);
1362 data32 |= endian; /* Big-Endian per 64-bit */
1363
1364 if (hw->mmu_enable && dw_mode)
1365 data32 |= ((hw->canvas_mode << 12));
1366 else
1367 data32 |= ((hw->canvas_mode << 12)|2);
1368
1369 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1370
1371#ifdef H265_DW_NO_SCALE
1372 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1373 if (hw->mmu_enable && dw_mode) {
1374 data32 = READ_VREG(HEVC_SAO_CTRL5);
1375 data32 &= (~(0xff << 16));
1376 if (dw_mode == 2 ||
1377 dw_mode == 3)
1378 data32 |= (0xff<<16);
1379 else if (dw_mode == 4)
1380 data32 |= (0x33<<16);
1381 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1382 }
1383
1384
1385#endif
1386
1387
1388#ifdef H265_LOSLESS_COMPRESS_MODE
1389 data32 = READ_VREG(HEVC_SAO_CTRL5);
1390 data32 |= (1<<9); /*8-bit smem-mode*/
1391 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1392
1393 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1394 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1395 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1396#endif
1397
1398#ifdef H265_LOSLESS_COMPRESS_MODE
1399 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1400 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1401#endif
1402
1403 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1404
1405 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1406
1407 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1408 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1409 return;
1410}
1411
1412static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1413 u32 is_new_pic, u32 is_idr)
1414{
1415 hw->is_new_pic = is_new_pic;
1416 hw->is_idr_frame = is_idr;
1417 return;
1418}
1419
1420static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1421 struct StorablePicture *pic) {
1422 u32 mc_y_adr;
1423 u32 mc_u_v_adr;
1424 u32 dw_y_adr;
1425 u32 dw_u_v_adr;
1426 u32 canvas_addr;
1427 int ret;
1428 int dw_mode = hw->double_write_mode;
1429 if (hw->is_new_pic != 1)
1430 return;
1431
1432 if (hw->is_idr_frame) {
1433 /* William TBD */
1434 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1435 }
1436
1437 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1438 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1439 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1440 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1441 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1442 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1443 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1444 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1445 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1446
1447
1448 if (dw_mode) {
1449 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1450 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1451 } else {
1452 dw_y_adr = 0;
1453 dw_u_v_adr = 0;
1454 }
1455#ifdef H265_LOSLESS_COMPRESS_MODE
1456 if (dw_mode)
1457 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1458 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1459#ifdef H264_MMU
1460 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1461#else
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1463 (mc_y_adr + hw->losless_comp_body_size));
1464#endif
1465#else
1466 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1467#endif
1468
1469#ifndef H265_LOSLESS_COMPRESS_MODE
1470 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1471#else
1472 if (dw_mode)
1473 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1474#endif
1475
1476#ifndef LOSLESS_COMPRESS_MODE
1477 if (dw_mode) {
1478 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1479 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1480 }
1481#else
1482 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1483 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1484#endif
1485
1486 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1487 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1488 hw->frame_mmu_map_addr);
1489 if (ret != 0) {
1490 dpb_print(DECODE_ID(hw),
1491 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1492 pic->buf_spec_num,
1493 ret);
1494 return;
1495 }
1496
1497 /*Reset SAO + Enable SAO slice_start*/
1498 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1499 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1500 WRITE_VREG(HEVC_SAO_INT_STATUS,
1501 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1504 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1505 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1506
1507 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1508 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1509 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1510 } else
1511 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1512 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1513 hw->frame_busy = 1;
1514 return;
1515}
1516
1517
1518static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1519 u32 buf_spec_num) {
1520 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1521 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1522 dpb_print(DECODE_ID(hw),
1523 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1524 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1525 return;
1526}
1527
1528
1529static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1530{
1531 ulong timeout = jiffies + HZ;
1532 dpb_print(DECODE_ID(hw),
1533 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1534 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1535 if (time_after(jiffies, timeout)) {
1536 dpb_print(DECODE_ID(hw),
1537 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1538 break;
1539 }
1540 }
1541 timeout = jiffies + HZ;
1542 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1543 if (time_after(jiffies, timeout)) {
1544 dpb_print(DECODE_ID(hw),
1545 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1546 break;
1547 }
1548 }
1549 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1550 hw->frame_done = 1;
1551 return;
1552}
1553
1554static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1555{
1556 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1557 if (p_H264_Dpb->mVideo.dec_picture) {
1558 release_picture(p_H264_Dpb,
1559 p_H264_Dpb->mVideo.dec_picture);
1560 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1561 p_H264_Dpb->mVideo.dec_picture = NULL;
1562 if (hw->mmu_enable)
1563 hevc_set_frame_done(hw);
1564 }
1565}
1566
1567static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1568{
1569 ulong timeout = jiffies + HZ;
1570 dpb_print(DECODE_ID(hw),
1571 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1572 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1573 if (time_after(jiffies, timeout)) {
1574 dpb_print(DECODE_ID(hw),
1575 PRINT_FLAG_MMU_DETAIL,
1576 "hevc_sao_wait_done...wait timeout!\n");
1577 break;
1578 }
1579 }
1580 timeout = jiffies + HZ;
1581 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1582 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1583 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1584 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1585 H265_ABORT_SAO_4K_SET_DONE) {
1586 if (time_after(jiffies, timeout)) {
1587 dpb_print(DECODE_ID(hw),
1588 PRINT_FLAG_MMU_DETAIL,
1589 "wait h265_abort_sao_4k_set_done timeout!\n");
1590 break;
1591 }
1592 }
1593 }
1594 amhevc_stop();
1595 hw->frame_busy = 0;
1596 hw->frame_done = 0;
1597 dpb_print(DECODE_ID(hw),
1598 PRINT_FLAG_MMU_DETAIL,
1599 "sao wait done ,hevc stop!\n");
1600 }
1601 return;
1602}
1603static void buf_spec_init(struct vdec_h264_hw_s *hw)
1604{
1605 int i;
1606 unsigned long flags;
1607 spin_lock_irqsave(&hw->bufspec_lock, flags);
1608 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1609 hw->buffer_spec[i].used = -1;
1610 hw->buffer_spec[i].canvas_pos = -1;
1611 }
1612 if (dpb_is_debug(DECODE_ID(hw),
1613 PRINT_FLAG_DUMP_BUFSPEC))
1614 dump_bufspec(hw, __func__);
1615 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1616}
1617
1618/*is active in buf management */
1619static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1620 int buf_spec_num)
1621{
1622 unsigned char ret = 0;
1623 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1624 hw->buffer_spec[buf_spec_num].used == 2 ||
1625 hw->buffer_spec[buf_spec_num].used == 3 ||
1626 hw->buffer_spec[buf_spec_num].used == 5)
1627 ret = 1;
1628 return ret;
1629}
1630
1631static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1632 int buf_spec_num)
1633{
1634 unsigned char ret = 0;
1635 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1636 hw->buffer_spec[buf_spec_num].used == 3 ||
1637 hw->buffer_spec[buf_spec_num].used == 5)
1638 ret = 1;
1639 return ret;
1640}
1641
1642static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1643{
1644 if (hw->mmu_enable) {
1645 if (hw->buffer_spec[i].alloc_header_addr)
1646 return 0;
1647 else
1648 return -1;
1649 } else {
1650
1651 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1652 int addr;
1653#ifdef VDEC_DW
1654 int orig_buf_size;
1655 orig_buf_size = buf_size;
1656 if (IS_VDEC_DW(hw) == 1)
1657 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1658 else if (IS_VDEC_DW(hw) == 2)
1659 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1660#endif
1661 if (hw->buffer_spec[i].cma_alloc_addr)
1662 return 0;
1663
1664 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1665 PAGE_ALIGN(buf_size), DRIVER_NAME,
1666 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1667 hw->buffer_spec[i].cma_alloc_addr = 0;
1668 if (hw->no_mem_count++ > 3) {
1669 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1670 hw->reset_bufmgr_flag = 1;
1671 }
1672 dpb_print(DECODE_ID(hw), 0,
1673 "%s, fail to alloc buf for bufspec%d, try later\n",
1674 __func__, i
1675 );
1676 return -1;
1677 } else {
1678 hw->no_mem_count = 0;
1679 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1680 }
1681
1682 hw->buffer_spec[i].buf_adr =
1683 hw->buffer_spec[i].cma_alloc_addr;
1684 addr = hw->buffer_spec[i].buf_adr;
1685
1686
1687 hw->buffer_spec[i].y_addr = addr;
1688 addr += hw->mb_total << 8;
1689 hw->buffer_spec[i].u_addr = addr;
1690 hw->buffer_spec[i].v_addr = addr;
1691 addr += hw->mb_total << 7;
1692
1693 hw->buffer_spec[i].canvas_config[0].phy_addr =
1694 hw->buffer_spec[i].y_addr;
1695 hw->buffer_spec[i].canvas_config[0].width =
1696 hw->mb_width << 4;
1697 hw->buffer_spec[i].canvas_config[0].height =
1698 hw->mb_height << 4;
1699 hw->buffer_spec[i].canvas_config[0].block_mode =
1700 hw->canvas_mode;
1701
1702 hw->buffer_spec[i].canvas_config[1].phy_addr =
1703 hw->buffer_spec[i].u_addr;
1704 hw->buffer_spec[i].canvas_config[1].width =
1705 hw->mb_width << 4;
1706 hw->buffer_spec[i].canvas_config[1].height =
1707 hw->mb_height << 3;
1708 hw->buffer_spec[i].canvas_config[1].block_mode =
1709 hw->canvas_mode;
1710 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1711 "%s, alloc buf for bufspec%d\n",
1712 __func__, i
1713 );
1714#ifdef VDEC_DW
1715
1716 if (!IS_VDEC_DW(hw))
1717 return 0;
1718 else if (IS_VDEC_DW(hw) == 1) {
1719 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1720 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1721 addr += hw->mb_total << 7;
1722 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1723 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1724 addr += hw->mb_total << 6;
1725
1726 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1727 hw->buffer_spec[i].vdec_dw_y_addr;
1728 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1729 hw->mb_width << 3;
1730 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1731 hw->mb_height << 4;
1732 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1733 CANVAS_BLKMODE_32X32;
1734
1735 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1736 hw->buffer_spec[i].vdec_dw_u_addr;
1737 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1738 hw->mb_width << 3;
1739 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1740 hw->mb_height << 3;
1741 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1742 CANVAS_BLKMODE_32X32;
1743 }else {
1744 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1745 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1746 addr += hw->mb_total << 6;
1747 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1748 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1749 addr += hw->mb_total << 5;
1750
1751 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1752 hw->buffer_spec[i].vdec_dw_y_addr;
1753 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1754 hw->mb_width << 3;
1755 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1756 hw->mb_height << 3;
1757 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1758 CANVAS_BLKMODE_32X32;
1759
1760 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1761 hw->buffer_spec[i].vdec_dw_u_addr;
1762 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1763 hw->mb_width << 3;
1764 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1765 hw->mb_height << 2;
1766 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1767 CANVAS_BLKMODE_32X32;
1768 }
1769 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1770 "%s, vdec_dw: alloc buf for bufspec%d\n",
1771 __func__, i
1772 );
1773#endif
1774 }
1775 return 0;
1776}
1777
1778static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1779{
1780 int ret = 0;
1781 struct aml_vcodec_ctx *ctx = NULL;
1782 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1783 struct canvas_config_s *y_canvas_cfg = NULL;
1784 struct canvas_config_s *c_canvas_cfg = NULL;
1785 struct vdec_v4l2_buffer *fb = NULL;
1786 unsigned int y_addr = 0, c_addr = 0;
1787
1788 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1789 pr_err("the v4l context has err.\n");
1790 return -1;
1791 }
1792
1793 if (bs->cma_alloc_addr)
1794 return 0;
1795
1796 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1797 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1798 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1799 ctx->id, __func__,
1800 (hw->mb_total << 8) + (hw->mb_total << 7));
1801
1802 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1803 if (ret < 0) {
1804 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1805 "[%d] get fb fail.\n", ctx->id);
1806 return ret;
1807 }
1808
1809 bs->cma_alloc_addr = (unsigned long)fb;
1810 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1811 "[%d] %s(), cma alloc addr: 0x%x\n",
1812 ctx->id, __func__, bs->cma_alloc_addr);
1813
1814 if (fb->num_planes == 1) {
1815 y_addr = fb->m.mem[0].addr;
1816 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1817 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1818 } else if (fb->num_planes == 2) {
1819 y_addr = fb->m.mem[0].addr;
1820 c_addr = fb->m.mem[1].addr;
1821 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1822 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1823 }
1824
1825 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1826 "[%d] %s(), y_addr: %x, size: %u\n",
1827 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1828 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1829 "[%d] %s(), c_addr: %x, size: %u\n",
1830 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1831
1832 bs->y_addr = y_addr;
1833 bs->u_addr = c_addr;
1834 bs->v_addr = c_addr;
1835
1836 y_canvas_cfg = &bs->canvas_config[0];
1837 c_canvas_cfg = &bs->canvas_config[1];
1838
1839 y_canvas_cfg->phy_addr = y_addr;
1840 y_canvas_cfg->width = hw->mb_width << 4;
1841 y_canvas_cfg->height = hw->mb_height << 4;
1842 y_canvas_cfg->block_mode = hw->canvas_mode;
1843 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1844 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1845 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1846 y_canvas_cfg->width,y_canvas_cfg->height);
1847
1848 c_canvas_cfg->phy_addr = c_addr;
1849 c_canvas_cfg->width = hw->mb_width << 4;
1850 c_canvas_cfg->height = hw->mb_height << 3;
1851 c_canvas_cfg->block_mode = hw->canvas_mode;
1852 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1853 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1854 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1855 c_canvas_cfg->width, c_canvas_cfg->height);
1856
1857 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1858 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1859
1860 return ret;
1861}
1862
1863static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1864{
1865 int blkmode = hw->canvas_mode;
1866 int endian = 0;
1867
1868 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1869 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1870 endian = 7;
1871 else
1872 endian = 0;
1873 }
1874
1875 if (hw->is_used_v4l)
1876 endian = 7;
1877
1878 canvas_config_ex(hw->buffer_spec[i].
1879 y_canvas_index,
1880 hw->buffer_spec[i].y_addr,
1881 hw->mb_width << 4,
1882 hw->mb_height << 4,
1883 CANVAS_ADDR_NOWRAP,
1884 blkmode,
1885 endian);
1886
1887 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1888 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1889 (1 << 11) | /* canvas_blk32_wr */
1890 (blkmode << 10) | /* canvas_blk32*/
1891 (1 << 8) | /* canvas_index_wr*/
1892 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1893 );
1894 }
1895
1896 canvas_config_ex(hw->buffer_spec[i].
1897 u_canvas_index,
1898 hw->buffer_spec[i].u_addr,
1899 hw->mb_width << 4,
1900 hw->mb_height << 3,
1901 CANVAS_ADDR_NOWRAP,
1902 blkmode,
1903 endian);
1904
1905 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1906 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1907 (1 << 11) |
1908 (blkmode << 10) |
1909 (1 << 8) |
1910 (hw->buffer_spec[i].u_canvas_index << 0));
1911 }
1912
1913 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1914 spec2canvas(&hw->buffer_spec[i]));
1915
1916
1917#ifdef VDEC_DW
1918 if (!IS_VDEC_DW(hw))
1919 return;
1920 else if (IS_VDEC_DW(hw) == 1) {
1921 canvas_config_ex(hw->buffer_spec[i].
1922 vdec_dw_y_canvas_index,
1923 hw->buffer_spec[i].vdec_dw_y_addr,
1924 hw->mb_width << 3,
1925 hw->mb_height << 4,
1926 CANVAS_ADDR_NOWRAP,
1927 blkmode,
1928 endian);
1929 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1930 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1931 (1 << 11) |
1932 (blkmode << 10) |
1933 (1 << 8) |
1934 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1935 }
1936 canvas_config_ex(hw->buffer_spec[i].
1937 vdec_dw_u_canvas_index,
1938 hw->buffer_spec[i].vdec_dw_u_addr,
1939 hw->mb_width << 3,
1940 hw->mb_height << 3,
1941 CANVAS_ADDR_NOWRAP,
1942 blkmode,
1943 endian);
1944 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1945 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1946 (1 << 11) |
1947 (blkmode << 10) |
1948 (1 << 8) |
1949 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1950 }
1951 } else {
1952 canvas_config_ex(hw->buffer_spec[i].
1953 vdec_dw_y_canvas_index,
1954 hw->buffer_spec[i].vdec_dw_y_addr,
1955 hw->mb_width << 3,
1956 hw->mb_height << 3,
1957 CANVAS_ADDR_NOWRAP,
1958 blkmode,
1959 endian);
1960 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1961 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1962 (1 << 11) |
1963 (blkmode << 10) |
1964 (1 << 8) |
1965 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1966 }
1967
1968 canvas_config_ex(hw->buffer_spec[i].
1969 vdec_dw_u_canvas_index,
1970 hw->buffer_spec[i].vdec_dw_u_addr,
1971 hw->mb_width << 3,
1972 hw->mb_height << 2,
1973 CANVAS_ADDR_NOWRAP,
1974 blkmode,
1975 endian);
1976 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1977 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1978 (1 << 11) |
1979 (blkmode << 10) |
1980 (1 << 8) |
1981 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1982 }
1983 }
1984#endif
1985}
1986
1987static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1988{
1989 u32 blkmode = hw->canvas_mode;
1990 int canvas_w;
1991 int canvas_h;
1992
1993 canvas_w = hw->frame_width /
1994 get_double_write_ratio(hw);
1995 canvas_h = hw->frame_height /
1996 get_double_write_ratio(hw);
1997
1998 if (hw->canvas_mode == 0)
1999 canvas_w = ALIGN(canvas_w, 32);
2000 else
2001 canvas_w = ALIGN(canvas_w, 64);
2002 canvas_h = ALIGN(canvas_h, 32);
2003
2004 canvas_config_ex(hw->buffer_spec[i].
2005 y_canvas_index,
2006 hw->buffer_spec[i].dw_y_adr,
2007 canvas_w,
2008 canvas_h,
2009 CANVAS_ADDR_NOWRAP,
2010 blkmode,
2011 7);
2012
2013 canvas_config_ex(hw->buffer_spec[i].
2014 u_canvas_index,
2015 hw->buffer_spec[i].dw_u_v_adr,
2016 canvas_w,
2017 canvas_h,
2018 CANVAS_ADDR_NOWRAP,
2019 blkmode,
2020 7);
2021}
2022
2023
2024int get_free_buf_idx(struct vdec_s *vdec)
2025{
2026 int i;
2027 unsigned long addr, flags;
2028 int index = -1;
2029 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2030 int buf_total = BUFSPEC_POOL_SIZE;
2031
2032 if (hw->is_used_v4l)
2033 buf_total = hw->dpb.mDPB.size;
2034
2035 spin_lock_irqsave(&hw->bufspec_lock, flags);
2036 /*hw->start_search_pos = 0;*/
2037 for (i = hw->start_search_pos; i < buf_total; i++) {
2038 if (hw->mmu_enable)
2039 addr = hw->buffer_spec[i].alloc_header_addr;
2040 else {
2041 addr = hw->buffer_spec[i].cma_alloc_addr;
2042 if (hw->is_used_v4l && !addr) {
2043 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2044 config_decode_canvas(hw, i);
2045 addr = hw->buffer_spec[i].cma_alloc_addr;
2046 }
2047 }
2048 }
2049 if (hw->buffer_spec[i].used == 0 && addr) {
2050 hw->buffer_spec[i].used = 1;
2051 hw->start_search_pos = i+1;
2052 index = i;
2053 break;
2054 }
2055 }
2056 if (index < 0) {
2057 for (i = 0; i < hw->start_search_pos; i++) {
2058 if (hw->mmu_enable)
2059 addr = hw->buffer_spec[i].alloc_header_addr;
2060 else {
2061 addr = hw->buffer_spec[i].cma_alloc_addr;
2062 if (hw->is_used_v4l && !addr) {
2063 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2064 config_decode_canvas(hw, i);
2065 addr = hw->buffer_spec[i].cma_alloc_addr;
2066 }
2067 }
2068 }
2069 if (hw->buffer_spec[i].used == 0 && addr) {
2070 hw->buffer_spec[i].used = 1;
2071 hw->start_search_pos = i+1;
2072 index = i;
2073 break;
2074 }
2075 }
2076 }
2077 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2078 if (hw->start_search_pos >= buf_total)
2079 hw->start_search_pos = 0;
2080 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2081 "%s, buf_spec_num %d\n", __func__, index);
2082
2083 if (index < 0) {
2084 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2085 "%s fail\n", __func__);
2086 vmh264_dump_state(vdec);
2087 }
2088
2089 if (dpb_is_debug(DECODE_ID(hw),
2090 PRINT_FLAG_DUMP_BUFSPEC))
2091 dump_bufspec(hw, __func__);
2092 return index;
2093}
2094
2095int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2096{
2097 /*u32 cur_buf_idx;*/
2098 unsigned long flags;
2099 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2100 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2101 "%s buf_spec_num %d used %d\n",
2102 __func__, buf_spec_num,
2103 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2104 if (buf_spec_num >= 0 &&
2105 buf_spec_num < BUFSPEC_POOL_SIZE
2106 ) {
2107 spin_lock_irqsave(&hw->bufspec_lock, flags);
2108 hw->buffer_spec[buf_spec_num].used = 0;
2109 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2110 if (hw->mmu_enable) {
2111 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2112 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2113 cur_buf_idx = cur_buf_idx&0xff;*/
2114 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2115 }
2116 release_aux_data(hw, buf_spec_num);
2117 }
2118 if (dpb_is_debug(DECODE_ID(hw),
2119 PRINT_FLAG_DUMP_BUFSPEC))
2120 dump_bufspec(hw, __func__);
2121 return 0;
2122}
2123
2124static void config_buf_specs(struct vdec_s *vdec)
2125{
2126 int i, j;
2127 unsigned long flags;
2128 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2129 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2130
2131 spin_lock_irqsave(&hw->bufspec_lock, flags);
2132 for (i = 0, j = 0;
2133 j < hw->dpb.mDPB.size
2134 && i < BUFSPEC_POOL_SIZE;
2135 i++) {
2136 int canvas;
2137 if (hw->buffer_spec[i].used != -1)
2138 continue;
2139 if (vdec->parallel_dec == 1) {
2140 if (hw->buffer_spec[i].y_canvas_index == -1)
2141 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2142 if (hw->buffer_spec[i].u_canvas_index == -1) {
2143 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2144 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2145 }
2146#ifdef VDEC_DW
2147 if (IS_VDEC_DW(hw)) {
2148 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2149 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2150 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2151 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2152 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2153 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2154 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2155 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2156 }
2157 }
2158#endif
2159 } else {
2160 canvas = vdec->get_canvas(j * mode, 2);
2161 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2162 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2163 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2164 dpb_print(DECODE_ID(hw),
2165 PRINT_FLAG_DPB_DETAIL,
2166 "config canvas (%d) %x for bufspec %d\r\n",
2167 j, canvas, i);
2168#ifdef VDEC_DW
2169 if (IS_VDEC_DW(hw)) {
2170 canvas = vdec->get_canvas(j * mode + 1, 2);
2171 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2172 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2173 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2174 dpb_print(DECODE_ID(hw),
2175 PRINT_FLAG_DPB_DETAIL,
2176 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2177 j, canvas, i);
2178 }
2179#endif
2180 }
2181
2182 hw->buffer_spec[i].used = 0;
2183 hw->buffer_spec[i].canvas_pos = j;
2184
2185
2186 j++;
2187 }
2188 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2189}
2190
2191static void config_buf_specs_ex(struct vdec_s *vdec)
2192{
2193 int i, j;
2194 unsigned long flags;
2195 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2196 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2197
2198 spin_lock_irqsave(&hw->bufspec_lock, flags);
2199 for (i = 0, j = 0;
2200 j < hw->dpb.mDPB.size
2201 && i < BUFSPEC_POOL_SIZE;
2202 i++) {
2203 int canvas = 0;
2204 if (hw->buffer_spec[i].used != -1)
2205 continue;
2206 if (vdec->parallel_dec == 1) {
2207 if (hw->buffer_spec[i].y_canvas_index == -1)
2208 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2209 if (hw->buffer_spec[i].u_canvas_index == -1) {
2210 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2211 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2212 }
2213#ifdef VDEC_DW
2214 if (IS_VDEC_DW(hw)) {
2215 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2216 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2217 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2218 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2219 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2220 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2221 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2222 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2223 }
2224 }
2225#endif
2226 } else {
2227 canvas = vdec->get_canvas(j* mode, 2);
2228 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2229 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2230 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2231
2232 dpb_print(DECODE_ID(hw),
2233 PRINT_FLAG_DPB_DETAIL,
2234 "config canvas (%d) %x for bufspec %d\r\n",
2235 j, canvas, i);
2236#ifdef VDEC_DW
2237 if (IS_VDEC_DW(hw)) {
2238 canvas = vdec->get_canvas(j*mode + 1, 2);
2239 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2240 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2241 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2242 dpb_print(DECODE_ID(hw),
2243 PRINT_FLAG_DPB_DETAIL,
2244 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2245 j, canvas, i);
2246 }
2247#endif
2248 }
2249
2250 hw->buffer_spec[i].used = 0;
2251 hw->buffer_spec[i].alloc_header_addr = 0;
2252 hw->buffer_spec[i].canvas_pos = j;
2253
2254 j++;
2255 }
2256 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2257}
2258
2259
2260static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2261 unsigned char release_all)
2262{
2263 int i;
2264 unsigned long flags;
2265 unsigned char dealloc_flag = 0;
2266 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2267 if (hw->buffer_spec[i].used == 4 ||
2268 release_all) {
2269 dealloc_flag = 1;
2270 dpb_print(DECODE_ID(hw),
2271 PRINT_FLAG_DPB_DETAIL,
2272 "%s buf_spec_num %d\n",
2273 __func__, i
2274 );
2275 spin_lock_irqsave
2276 (&hw->bufspec_lock, flags);
2277 hw->buffer_spec[i].used = -1;
2278 spin_unlock_irqrestore
2279 (&hw->bufspec_lock, flags);
2280 release_aux_data(hw, i);
2281
2282 if (!hw->mmu_enable) {
2283 if (hw->buffer_spec[i].cma_alloc_addr) {
2284 if (!hw->is_used_v4l) {
2285 decoder_bmmu_box_free_idx(
2286 hw->bmmu_box,
2287 i);
2288 }
2289 spin_lock_irqsave
2290 (&hw->bufspec_lock, flags);
2291 hw->buffer_spec[i].cma_alloc_addr = 0;
2292 hw->buffer_spec[i].buf_adr = 0;
2293 spin_unlock_irqrestore
2294 (&hw->bufspec_lock, flags);
2295 }
2296 } else {
2297 if (hw->buffer_spec[i].alloc_header_addr) {
2298 decoder_mmu_box_free_idx(
2299 hw->mmu_box,
2300 i);
2301 spin_lock_irqsave
2302 (&hw->bufspec_lock, flags);
2303 hw->buffer_spec[i].
2304 alloc_header_addr = 0;
2305 hw->buffer_spec[i].buf_adr = 0;
2306 spin_unlock_irqrestore
2307 (&hw->bufspec_lock, flags);
2308 }
2309 }
2310 }
2311 }
2312 if (dealloc_flag &&
2313 dpb_is_debug(DECODE_ID(hw),
2314 PRINT_FLAG_DUMP_BUFSPEC))
2315 dump_bufspec(hw, __func__);
2316 return;
2317}
2318
2319unsigned char have_free_buf_spec(struct vdec_s *vdec)
2320{
2321 int i;
2322 unsigned long addr;
2323 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2324 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2325 int index = -1;
2326 int ret = 0;
2327 int allocated_count = 0;
2328 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2329 if (hw->mmu_enable)
2330 addr = hw->buffer_spec[i].alloc_header_addr;
2331 else
2332 addr = hw->buffer_spec[i].cma_alloc_addr;
2333 if (hw->buffer_spec[i].used == 0) {
2334
2335 if (addr)
2336 return 1;
2337 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2338 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2339 index = i;
2340 }
2341 }
2342 if (addr)
2343 allocated_count++;
2344 }
2345 if (index >= 0) {
2346 mutex_lock(&vmh264_mutex);
2347 dealloc_buf_specs(hw, 0);
2348 if (max_alloc_buf_count == 0 ||
2349 allocated_count < max_alloc_buf_count) {
2350 if (hw->is_used_v4l)
2351 ret = 1;
2352 else if (alloc_one_buf_spec(hw, index) >= 0)
2353 ret = 1;
2354 }
2355 mutex_unlock(&vmh264_mutex);
2356 }
2357 return ret;
2358}
2359
2360static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2361 int canvas_pos)
2362{
2363 int i;
2364 int j = 0;
2365 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2366 if (hw->buffer_spec[i].canvas_pos >= 0) {
2367 if (j == canvas_pos)
2368 return i;
2369 j++;
2370 }
2371 }
2372 return -1;
2373}
2374static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2375 struct vframe_s *vf, int index)
2376{
2377 if (index < 0) {
2378 vf->mem_handle = NULL;
2379 vf->mem_head_handle = NULL;
2380 } else if (vf->type & VIDTYPE_SCATTER) {
2381 vf->mem_handle =
2382 decoder_mmu_box_get_mem_handle(
2383 hw->mmu_box, index);
2384 vf->mem_head_handle =
2385 decoder_bmmu_box_get_mem_handle(
2386 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2387 } else {
2388 vf->mem_handle =
2389 decoder_bmmu_box_get_mem_handle(
2390 hw->bmmu_box, VF_BUFFER_IDX(index));
2391 /* vf->mem_head_handle =
2392 decoder_bmmu_box_get_mem_handle(
2393 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2394 }
2395 return;
2396}
2397static int check_force_interlace(struct vdec_h264_hw_s *hw,
2398 struct FrameStore *frame)
2399{
2400 int bForceInterlace = 0;
2401 /* no di in secure mode, disable force di */
2402 if (vdec_secure(hw_to_vdec(hw)))
2403 return 0;
2404 if (frame->frame) {
2405 if (frame->frame->coded_frame
2406 && !frame->frame->frame_mbs_only_flag) {
2407 if (frame->frame->structure == FRAME)
2408 return 1;
2409 }
2410 }
2411
2412 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2413 && hw->bitstream_restriction_flag
2414 && (hw->frame_width == 1920)
2415 && (hw->frame_height >= 1080)
2416 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2417 bForceInterlace = 1;
2418 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2419 && (hw->frame_width == 720)
2420 && (hw->frame_height == 576)
2421 && (hw->frame_dur == 3840)) {
2422 bForceInterlace = 1;
2423 }
2424
2425 return bForceInterlace;
2426}
2427
2428static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2429{
2430 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2431 if (frame->slice_type == I_SLICE)
2432 vframe_qos->type = 1;
2433 else if (frame->slice_type == P_SLICE)
2434 vframe_qos->type = 2;
2435 else if (frame->slice_type == B_SLICE)
2436 vframe_qos->type = 3;
2437
2438 vframe_qos->size = frame->frame_size;
2439 vframe_qos->pts = frame->pts64;
2440
2441 vframe_qos->max_mv = frame->max_mv;
2442 vframe_qos->avg_mv = frame->avg_mv;
2443 vframe_qos->min_mv = frame->min_mv;
2444/*
2445 pr_info("mv: max:%d, avg:%d, min:%d\n",
2446 vframe_qos->max_mv,
2447 vframe_qos->avg_mv,
2448 vframe_qos->min_mv);
2449*/
2450
2451 vframe_qos->max_qp = frame->max_qp;
2452 vframe_qos->avg_qp = frame->avg_qp;
2453 vframe_qos->min_qp = frame->min_qp;
2454/*
2455 pr_info("qp: max:%d, avg:%d, min:%d\n",
2456 vframe_qos->max_qp,
2457 vframe_qos->avg_qp,
2458 vframe_qos->min_qp);
2459*/
2460
2461 vframe_qos->max_skip = frame->max_skip;
2462 vframe_qos->avg_skip = frame->avg_skip;
2463 vframe_qos->min_skip = frame->min_skip;
2464/*
2465 pr_info("skip: max:%d, avg:%d, min:%d\n",
2466 vframe_qos->max_skip,
2467 vframe_qos->avg_skip,
2468 vframe_qos->min_skip);
2469*/
2470 vframe_qos->num++;
2471 if (hw->frameinfo_enable)
2472 vdec_fill_frame_info(vframe_qos, 1);
2473}
2474
2475static int is_iframe(struct FrameStore *frame) {
2476
2477 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2478 return 1;
2479 }
2480 return 0;
2481}
2482
2483
2484
2485int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2486{
2487 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2488 struct vframe_s *vf = NULL;
2489 int buffer_index = frame->buf_spec_num;
2490 int vf_count = 1;
2491 int i;
2492 int bForceInterlace = 0;
2493
2494 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2495 dpb_print(DECODE_ID(hw), 0,
2496 "%s, buffer_index 0x%x is beyond range\n",
2497 __func__, buffer_index);
2498 return -1;
2499 }
2500 if (force_disp_bufspec_num & 0x100) {
2501 /*recycle directly*/
2502 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2503 hw->buffer_spec[frame->buf_spec_num].used != 5)
2504 set_frame_output_flag(&hw->dpb, frame->index);
2505
2506 /*make pre_output not set*/
2507 return -1;
2508 }
2509 if (error_proc_policy & 0x1000) {
2510 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2511 int error_skip_frame_count = error_skip_count & 0xfff;
2512 if (((hw->no_error_count < error_skip_frame_count)
2513 && (error_skip_i_count == 0 ||
2514 hw->no_error_i_count < error_skip_i_count))
2515 && (!(frame->data_flag & I_FLAG)))
2516 frame->data_flag |= ERROR_FLAG;
2517 }
2518 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2519 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2520 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2521 frame->poc, hw->data_flag & ERROR_FLAG,
2522 error_proc_policy);
2523 if (frame->frame == NULL &&
2524 ((frame->is_used == 1 && frame->top_field)
2525 || (frame->is_used == 2 && frame->bottom_field))) {
2526 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2527 "%s Error frame_num %d used %d\n",
2528 __func__, frame->frame_num, frame->is_used);
2529 frame->data_flag |= ERROR_FLAG;
2530 }
2531 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2532 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2533 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2534 0, &frame->pts64) == 0)) {
2535 hw->last_pts64 = frame->pts64;
2536 hw->last_pts = frame->pts;
2537 } else {
2538 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2539 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2540 }
2541 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2542 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2543 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2544 frame->offset_delimiter, frame->pts,hw->last_pts,
2545 frame->pts64, hw->last_pts64, hw->frame_dur);
2546 hw->last_pts64 = frame->pts64;
2547 hw->last_pts = frame->pts;
2548 }
2549 if ((frame->data_flag & NODISP_FLAG) ||
2550 (frame->data_flag & NULL_FLAG) ||
2551 ((!hw->send_error_frame_flag) &&
2552 (frame->data_flag & ERROR_FLAG)) ||
2553 ((hw->i_only & 0x1) &&
2554 (!(frame->data_flag & I_FLAG)))
2555 ) {
2556 set_frame_output_flag(&hw->dpb, frame->index);
2557 return 0; /*do not return -1,
2558 otherwise flush_dpb() will not flush all dbp frames*/
2559 }
2560
2561 display_frame_count[DECODE_ID(hw)]++;
2562
2563 if (dpb_is_debug(DECODE_ID(hw),
2564 PRINT_FLAG_DPB_DETAIL)) {
2565 dpb_print(DECODE_ID(hw), 0,
2566 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2567 __func__, frame->index, frame->poc,
2568 frame->buf_spec_num);
2569 print_pic_info(DECODE_ID(hw), "predis_frm",
2570 frame->frame, -1);
2571 print_pic_info(DECODE_ID(hw), "predis_top",
2572 frame->top_field, -1);
2573 print_pic_info(DECODE_ID(hw), "predis_bot",
2574 frame->bottom_field, -1);
2575 }
2576
2577 if (!is_interlace(frame))
2578 vf_count = 1;
2579 else
2580 vf_count = 2;
2581 bForceInterlace = check_force_interlace(hw, frame);
2582 if (bForceInterlace)
2583 vf_count = 2;
2584 hw->buffer_spec[buffer_index].vf_ref = 0;
2585 fill_frame_info(hw, frame);
2586 for (i = 0; i < vf_count; i++) {
2587 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2588 vf == NULL) {
2589 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2590 "%s fatal error, no available buffer slot.\n",
2591 __func__);
2592 return -1;
2593 }
2594 vf->duration_pulldown = 0;
2595 if (!(is_iframe(frame)) && hw->unstable_pts) {
2596 vf->pts = 0;
2597 vf->pts_us64 = 0;
2598 vf->timestamp = 0;
2599 vf->index = VF_INDEX(frame->index, buffer_index);
2600 } else {
2601 vf->pts = frame->pts;
2602 vf->pts_us64 = frame->pts64;
2603 vf->timestamp = frame->timestamp;
2604 vf->index = VF_INDEX(frame->index, buffer_index);
2605 }
2606
2607 if (hw->is_used_v4l) {
2608 vf->v4l_mem_handle
2609 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2610 }
2611
2612 if (hw->mmu_enable) {
2613 if (hw->double_write_mode & 0x10) {
2614 /* double write only */
2615 vf->compBodyAddr = 0;
2616 vf->compHeadAddr = 0;
2617 } else {
2618 /*head adr*/
2619 vf->compHeadAddr =
2620 hw->buffer_spec[buffer_index].alloc_header_addr;
2621 /*body adr*/
2622 vf->compBodyAddr = 0;
2623 vf->canvas0Addr = vf->canvas1Addr = 0;
2624 }
2625
2626 vf->type = VIDTYPE_SCATTER;
2627
2628 if (hw->double_write_mode) {
2629 vf->type |= VIDTYPE_PROGRESSIVE
2630 | VIDTYPE_VIU_FIELD;
2631 vf->type |= VIDTYPE_VIU_NV21;
2632 if (hw->double_write_mode == 3)
2633 vf->type |= VIDTYPE_COMPRESS;
2634
2635 vf->canvas0Addr = vf->canvas1Addr = -1;
2636 vf->plane_num = 2;
2637 vf->canvas0_config[0] =
2638 hw->buffer_spec[buffer_index].
2639 canvas_config[0];
2640 vf->canvas0_config[1] =
2641 hw->buffer_spec[buffer_index].
2642 canvas_config[1];
2643
2644 vf->canvas1_config[0] =
2645 hw->buffer_spec[buffer_index].
2646 canvas_config[0];
2647 vf->canvas1_config[1] =
2648 hw->buffer_spec[buffer_index].
2649 canvas_config[1];
2650
2651 } else {
2652 vf->type |=
2653 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2654 vf->canvas0Addr = vf->canvas1Addr = 0;
2655 }
2656
2657 vf->bitdepth =
2658 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2659
2660 vf->compWidth = hw->frame_width;
2661 vf->compHeight = hw->frame_height;
2662 } else {
2663 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2664 VIDTYPE_VIU_NV21;
2665
2666 vf->canvas0Addr = vf->canvas1Addr =
2667 spec2canvas(&hw->buffer_spec[buffer_index]);
2668#ifdef VDEC_DW
2669 if (IS_VDEC_DW(hw))
2670 vf->canvas0Addr = vf->canvas1Addr =
2671 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2672#endif
2673
2674 }
2675 set_frame_info(hw, vf, buffer_index);
2676
2677 if (hw->mmu_enable && hw->double_write_mode) {
2678 vf->width = hw->frame_width /
2679 get_double_write_ratio(hw);
2680 vf->height = hw->frame_height /
2681 get_double_write_ratio(hw);
2682 }
2683
2684 vf->flag = 0;
2685 if (frame->data_flag & I_FLAG)
2686 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2687 if (frame->data_flag & ERROR_FLAG)
2688 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2689 update_vf_memhandle(hw, vf, buffer_index);
2690 hw->buffer_spec[buffer_index].used = 2;
2691 hw->buffer_spec[buffer_index].vf_ref++;
2692
2693 if (bForceInterlace || is_interlace(frame)) {
2694 vf->type =
2695 VIDTYPE_INTERLACE_FIRST |
2696 VIDTYPE_VIU_NV21;
2697
2698 if (bForceInterlace) {
2699 vf->type |= (i == 0 ?
2700 VIDTYPE_INTERLACE_TOP :
2701 VIDTYPE_INTERLACE_BOTTOM);
2702 if (i == 1) {
2703 vf->pts = 0;
2704 vf->pts_us64 = 0;
2705 }
2706 } else if (frame->top_field->poc <=
2707 frame->bottom_field->poc) /*top first*/
2708 vf->type |= (i == 0 ?
2709 VIDTYPE_INTERLACE_TOP :
2710 VIDTYPE_INTERLACE_BOTTOM);
2711 else
2712 vf->type |= (i == 0 ?
2713 VIDTYPE_INTERLACE_BOTTOM :
2714 VIDTYPE_INTERLACE_TOP);
2715 vf->duration = vf->duration/2;
2716 }
2717
2718 if (i == 0)
2719 decoder_do_frame_check(hw_to_vdec(hw), vf);
2720
2721 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2722 vf->sar_width = hw->width_aspect_ratio;
2723 vf->sar_height = hw->height_aspect_ratio;
2724
2725 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2726 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2727 hw->vf_pre_count++;
2728 vdec->vdec_fps_detec(vdec->id);
2729 if (without_display_mode == 0) {
2730 vf_notify_receiver(vdec->vf_provider_name,
2731 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2732 } else
2733 vh264_vf_put(vh264_vf_get(vdec), vdec);
2734 }
2735 if (dpb_is_debug(DECODE_ID(hw),
2736 PRINT_FLAG_DUMP_BUFSPEC))
2737 dump_bufspec(hw, __func__);
2738
2739 return 0;
2740}
2741
2742int notify_v4l_eos(struct vdec_s *vdec)
2743{
2744 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2745 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2746 struct vframe_s *vf = &hw->vframe_dummy;
2747 struct vdec_v4l2_buffer *fb = NULL;
2748 int index = INVALID_IDX;
2749 ulong expires;
2750
2751 if (hw->is_used_v4l && hw->eos) {
2752 expires = jiffies + msecs_to_jiffies(2000);
2753 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2754 if (time_after(jiffies, expires))
2755 break;
2756 }
2757
2758 if (index == INVALID_IDX) {
2759 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2760 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2761 return -1;
2762 }
2763 }
2764
2765 vf->type |= VIDTYPE_V4L_EOS;
2766 vf->timestamp = ULONG_MAX;
2767 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2768 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2769 hw->buffer_spec[index].cma_alloc_addr;
2770
2771 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2772
2773 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2774 vf_notify_receiver(vdec->vf_provider_name,
2775 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2776
2777 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2778 }
2779
2780 return 0;
2781}
2782
2783/******************
2784 * Hardware config
2785 */
2786char *slice_type_name[] = {
2787 "P_SLICE ",
2788 "B_SLICE ",
2789 "I_SLICE ",
2790 "SP_SLICE",
2791 "SI_SLICE",
2792};
2793
2794char *picture_structure_name[] = {
2795 "FRAME",
2796 "TOP_FIELD",
2797 "BOTTOM_FIELD"
2798};
2799
2800void print_pic_info(int decindex, const char *info,
2801 struct StorablePicture *pic,
2802 int slice_type)
2803{
2804 if (pic)
2805 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2806 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2807 info,
2808 picture_structure_name[pic->structure],
2809 pic->coded_frame ? "Frame" : "Field",
2810 (slice_type < 0 ||
2811 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2812 pic->mb_aff_frame_flag,
2813 pic->poc,
2814 pic->pic_num,
2815 pic->buf_spec_num,
2816 pic->data_flag);
2817}
2818
2819static void reset_process_time(struct vdec_h264_hw_s *hw)
2820{
2821 if (hw->start_process_time) {
2822 unsigned process_time =
2823 1000 * (jiffies - hw->start_process_time) / HZ;
2824 hw->start_process_time = 0;
2825 if (process_time > max_process_time[DECODE_ID(hw)])
2826 max_process_time[DECODE_ID(hw)] = process_time;
2827 }
2828}
2829
2830static void start_process_time(struct vdec_h264_hw_s *hw)
2831{
2832 hw->decode_timeout_count = 10;
2833 hw->start_process_time = jiffies;
2834}
2835
2836static void config_aux_buf(struct vdec_h264_hw_s *hw)
2837{
2838 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2839 WRITE_VREG(H264_AUX_DATA_SIZE,
2840 ((hw->prefix_aux_size >> 4) << 16) |
2841 (hw->suffix_aux_size >> 4)
2842 );
2843}
2844
2845/*
2846* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2847*/
2848static void set_aux_data(struct vdec_h264_hw_s *hw,
2849 struct StorablePicture *pic, unsigned char suffix_flag,
2850 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2851{
2852 int i;
2853 unsigned short *aux_adr;
2854 unsigned size_reg_val =
2855 READ_VREG(H264_AUX_DATA_SIZE);
2856 unsigned aux_count = 0;
2857 int aux_size = 0;
2858 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2859 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2860 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2861 return;
2862
2863 if (suffix_flag) {
2864 aux_adr = (unsigned short *)
2865 (hw_buf->aux_addr +
2866 hw_buf->prefix_aux_size);
2867 aux_count =
2868 ((size_reg_val & 0xffff) << 4)
2869 >> 1;
2870 aux_size =
2871 hw_buf->suffix_aux_size;
2872 } else {
2873 aux_adr =
2874 (unsigned short *)hw_buf->aux_addr;
2875 aux_count =
2876 ((size_reg_val >> 16) << 4)
2877 >> 1;
2878 aux_size =
2879 hw_buf->prefix_aux_size;
2880 }
2881 if (dpb_is_debug(DECODE_ID(hw),
2882 PRINT_FLAG_DPB_DETAIL)) {
2883 dpb_print(DECODE_ID(hw), 0,
2884 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2885 __func__, AUX_DATA_SIZE(pic),
2886 aux_count, suffix_flag, dv_meta_flag);
2887 }
2888 if (aux_size > 0 && aux_count > 0) {
2889 int heads_size = 0;
2890 int new_size;
2891 char *new_buf;
2892 for (i = 0; i < aux_count; i++) {
2893 unsigned char tag = aux_adr[i] >> 8;
2894 if (tag != 0 && tag != 0xff) {
2895 if (dv_meta_flag == 0)
2896 heads_size += 8;
2897 else if (dv_meta_flag == 1 && tag == 0x1)
2898 heads_size += 8;
2899 else if (dv_meta_flag == 2 && tag != 0x1)
2900 heads_size += 8;
2901 }
2902 }
2903 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2904 new_buf = krealloc(AUX_DATA_BUF(pic),
2905 new_size,
2906 GFP_KERNEL);
2907 if (new_buf) {
2908 unsigned char valid_tag = 0;
2909 unsigned char *h =
2910 new_buf +
2911 AUX_DATA_SIZE(pic);
2912 unsigned char *p = h + 8;
2913 int len = 0;
2914 int padding_len = 0;
2915 AUX_DATA_BUF(pic) = new_buf;
2916 for (i = 0; i < aux_count; i += 4) {
2917 int ii;
2918 unsigned char tag = aux_adr[i + 3] >> 8;
2919 if (tag != 0 && tag != 0xff) {
2920 if (dv_meta_flag == 0)
2921 valid_tag = 1;
2922 else if (dv_meta_flag == 1
2923 && tag == 0x1)
2924 valid_tag = 1;
2925 else if (dv_meta_flag == 2
2926 && tag != 0x1)
2927 valid_tag = 1;
2928 else
2929 valid_tag = 0;
2930 if (valid_tag && len > 0) {
2931 AUX_DATA_SIZE(pic) +=
2932 (len + 8);
2933 h[0] =
2934 (len >> 24) & 0xff;
2935 h[1] =
2936 (len >> 16) & 0xff;
2937 h[2] =
2938 (len >> 8) & 0xff;
2939 h[3] =
2940 (len >> 0) & 0xff;
2941 h[6] =
2942 (padding_len >> 8)
2943 & 0xff;
2944 h[7] =
2945 (padding_len) & 0xff;
2946 h += (len + 8);
2947 p += 8;
2948 len = 0;
2949 padding_len = 0;
2950 }
2951 if (valid_tag) {
2952 h[4] = tag;
2953 h[5] = 0;
2954 h[6] = 0;
2955 h[7] = 0;
2956 }
2957 }
2958 if (valid_tag) {
2959 for (ii = 0; ii < 4; ii++) {
2960 unsigned short aa =
2961 aux_adr[i + 3
2962 - ii];
2963 *p = aa & 0xff;
2964 p++;
2965 len++;
2966 /*if ((aa >> 8) == 0xff)
2967 padding_len++;*/
2968 }
2969 }
2970 }
2971 if (len > 0) {
2972 AUX_DATA_SIZE(pic) += (len + 8);
2973 h[0] = (len >> 24) & 0xff;
2974 h[1] = (len >> 16) & 0xff;
2975 h[2] = (len >> 8) & 0xff;
2976 h[3] = (len >> 0) & 0xff;
2977 h[6] = (padding_len >> 8) & 0xff;
2978 h[7] = (padding_len) & 0xff;
2979 }
2980 if (dpb_is_debug(DECODE_ID(hw),
2981 PRINT_FLAG_DPB_DETAIL)) {
2982 dpb_print(DECODE_ID(hw), 0,
2983 "aux: (size %d) suffix_flag %d\n",
2984 AUX_DATA_SIZE(pic), suffix_flag);
2985 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2986 dpb_print_cont(DECODE_ID(hw), 0,
2987 "%02x ", AUX_DATA_BUF(pic)[i]);
2988 if (((i + 1) & 0xf) == 0)
2989 dpb_print_cont(
2990 DECODE_ID(hw),
2991 0, "\n");
2992 }
2993 dpb_print_cont(DECODE_ID(hw),
2994 0, "\n");
2995 }
2996
2997 }
2998 }
2999
3000}
3001
3002static void release_aux_data(struct vdec_h264_hw_s *hw,
3003 int buf_spec_num)
3004{
3005 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3006 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3007 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3008}
3009
3010static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3011{
3012 int i;
3013 unsigned short *aux_adr =
3014 (unsigned short *)
3015 hw->aux_addr;
3016 unsigned aux_size =
3017 (READ_VREG(H264_AUX_DATA_SIZE)
3018 >> 16) << 4;
3019
3020 if (hw->prefix_aux_size > 0) {
3021 dpb_print(DECODE_ID(hw),
3022 0,
3023 "prefix aux: (size %d)\n",
3024 aux_size);
3025 for (i = 0; i <
3026 (aux_size >> 1); i++) {
3027 dpb_print_cont(DECODE_ID(hw),
3028 0,
3029 "%04x ",
3030 *(aux_adr + i));
3031 if (((i + 1) & 0xf)
3032 == 0)
3033 dpb_print_cont(
3034 DECODE_ID(hw),
3035 0, "\n");
3036 }
3037 }
3038 if (hw->suffix_aux_size > 0) {
3039 aux_adr = (unsigned short *)
3040 (hw->aux_addr +
3041 hw->prefix_aux_size);
3042 aux_size =
3043 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3044 << 4;
3045 dpb_print(DECODE_ID(hw),
3046 0,
3047 "suffix aux: (size %d)\n",
3048 aux_size);
3049 for (i = 0; i <
3050 (aux_size >> 1); i++) {
3051 dpb_print_cont(DECODE_ID(hw),
3052 0,
3053 "%04x ", *(aux_adr + i));
3054 if (((i + 1) & 0xf) == 0)
3055 dpb_print_cont(DECODE_ID(hw),
3056 0, "\n");
3057 }
3058 }
3059}
3060
3061static void config_decode_mode(struct vdec_h264_hw_s *hw)
3062{
3063#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3064 struct vdec_s *vdec = hw_to_vdec(hw);
3065#endif
3066 if (input_frame_based(hw_to_vdec(hw)))
3067 WRITE_VREG(H264_DECODE_MODE,
3068 DECODE_MODE_MULTI_FRAMEBASE);
3069#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3070 else if (vdec->slave)
3071 WRITE_VREG(H264_DECODE_MODE,
3072 (hw->got_valid_nal << 8) |
3073 DECODE_MODE_MULTI_DVBAL);
3074 else if (vdec->master)
3075 WRITE_VREG(H264_DECODE_MODE,
3076 (hw->got_valid_nal << 8) |
3077 DECODE_MODE_MULTI_DVENL);
3078#endif
3079 else
3080 WRITE_VREG(H264_DECODE_MODE,
3081 DECODE_MODE_MULTI_STREAMBASE);
3082 WRITE_VREG(H264_DECODE_SEQINFO,
3083 hw->seq_info2);
3084 WRITE_VREG(HEAD_PADING_REG, 0);
3085
3086 if (hw->init_flag == 0)
3087 WRITE_VREG(INIT_FLAG_REG, 0);
3088 else
3089 WRITE_VREG(INIT_FLAG_REG, 1);
3090}
3091int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3092{
3093 /* static int count = 0; */
3094 int ret = 0;
3095 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3096 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3097 unsigned int colocate_adr_offset;
3098 unsigned int val;
3099 struct StorablePicture *last_pic = hw->last_dec_picture;
3100
3101#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3102 int colocate_buf_index;
3103#endif
3104#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3105#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3106#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3107#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3108
3109#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3110/* bit 31:30 -- L1[0] picture coding structure,
3111 * 00 - top field, 01 - bottom field,
3112 * 10 - frame, 11 - mbaff frame
3113 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3114 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3115 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3116 */
3117#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3118
3119/* bit 15 -- flush co_mb_data to DDR -- W-Only
3120 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3121 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3122 * bit 9 -- soft_reset -- W-Only
3123 * bit 8 -- upgent
3124 * bit 7:2 -- h264_co_mb_mem_wr_addr
3125 * bit 1:0 -- h264_co_mb_info_wr_ptr
3126 */
3127#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3128
3129 unsigned long canvas_adr;
3130 unsigned int ref_reg_val;
3131 unsigned int one_ref_cfg = 0;
3132 int h264_buffer_info_data_write_count;
3133 int i, j;
3134 unsigned int colocate_wr_adr;
3135 unsigned int colocate_rd_adr;
3136 unsigned char use_direct_8x8;
3137 int canvas_pos;
3138 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3139 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3140 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3141 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3142 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3143
3144 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3145 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3146 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3147 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3148 canvas_pos);
3149 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3150
3151#ifdef VDEC_DW
3152 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3153 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3154 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3155#endif
3156 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3157 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3158
3159 if (!hw->mmu_enable) {
3160 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3161 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3162 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3163#ifdef VDEC_DW
3164 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3165 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3166 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3167#endif
3168 } else
3169 hevc_sao_set_pic_buffer(hw, pic);
3170
3171 if (pic->mb_aff_frame_flag)
3172 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3173 else if (pic->structure == TOP_FIELD)
3174 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3175 else if (pic->structure == BOTTOM_FIELD)
3176 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3177 else
3178 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3179
3180 if (pic->bottom_poc < pic->top_poc)
3181 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3182
3183 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3184 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3185 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3186
3187 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3188 int long_term_flag;
3189 i = get_buf_spec_by_canvas_pos(hw, j);
3190 if (i < 0)
3191 break;
3192 long_term_flag =
3193 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3194 if (long_term_flag > 0) {
3195 if (long_term_flag & 0x1)
3196 hw->buffer_spec[i].info0 |= (1 << 4);
3197 else
3198 hw->buffer_spec[i].info0 &= ~(1 << 4);
3199
3200 if (long_term_flag & 0x2)
3201 hw->buffer_spec[i].info0 |= (1 << 5);
3202 else
3203 hw->buffer_spec[i].info0 &= ~(1 << 5);
3204 }
3205
3206 if (i == pic->buf_spec_num)
3207 WRITE_VREG(H264_BUFFER_INFO_DATA,
3208 hw->buffer_spec[i].info0 | 0xf);
3209 else
3210 WRITE_VREG(H264_BUFFER_INFO_DATA,
3211 hw->buffer_spec[i].info0);
3212 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3213 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3214 }
3215
3216 /* config reference buffer */
3217 if (hw->mmu_enable) {
3218 hevc_mcr_config_mc_ref(hw);
3219 hevc_mcr_config_mcrcc(hw);
3220 }
3221
3222 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3223 "list0 size %d\n", pSlice->listXsize[0]);
3224 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3225 ref_reg_val = 0;
3226 j = 0;
3227 h264_buffer_info_data_write_count = 0;
3228
3229 //disable this read cache when frame width <= 64 (4MBs)
3230 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3231 if (hw->frame_width <= 64)
3232 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3233 else
3234 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3235
3236 if (last_pic)
3237 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3238 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3239 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3240 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3241 last_pic && (last_pic->data_flag & ERROR_FLAG)
3242 && (!(last_pic->slice_type == B_SLICE))
3243 && (!(pSlice->slice_type == I_SLICE))) {
3244 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3245 "no i/idr error mark\n");
3246 hw->data_flag |= ERROR_FLAG;
3247 pic->data_flag |= ERROR_FLAG;
3248 }
3249
3250 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3251 /*ref list 0 */
3252 struct StorablePicture *ref = pSlice->listX[0][i];
3253 unsigned int cfg;
3254 /* bit[6:5] - frame/field info,
3255 * 01 - top, 10 - bottom, 11 - frame
3256 */
3257 #ifdef ERROR_CHECK
3258 if (ref == NULL) {
3259 hw->data_flag |= ERROR_FLAG;
3260 pic->data_flag |= ERROR_FLAG;
3261 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3262 return -1;
3263 }
3264 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3265 hw->data_flag |= ERROR_FLAG;
3266 pic->data_flag |= ERROR_FLAG;
3267 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3268 }
3269 if (ref->data_flag & NULL_FLAG)
3270 hw->data_flag |= NULL_FLAG;
3271#endif
3272 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3273
3274 if (ref->structure == TOP_FIELD)
3275 cfg = 0x1;
3276 else if (ref->structure == BOTTOM_FIELD)
3277 cfg = 0x2;
3278 else /* FRAME */
3279 cfg = 0x3;
3280
3281 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3282 ref_reg_val <<= 8;
3283 ref_reg_val |= one_ref_cfg;
3284 j++;
3285
3286 if (j == 4) {
3287 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3288 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3289 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3290 h264_buffer_info_data_write_count++;
3291 j = 0;
3292 }
3293 print_pic_info(DECODE_ID(hw), "list0",
3294 pSlice->listX[0][i], -1);
3295 }
3296 if (j != 0) {
3297 while (j != 4) {
3298 ref_reg_val <<= 8;
3299 ref_reg_val |= one_ref_cfg;
3300 j++;
3301 }
3302 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3303 "H264_BUFFER_INFO_DATA: %x\n",
3304 ref_reg_val);
3305 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3306 h264_buffer_info_data_write_count++;
3307 }
3308 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3309 (one_ref_cfg << 8) | one_ref_cfg;
3310 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3311 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3312
3313 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3314 "list1 size %d\n", pSlice->listXsize[1]);
3315 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3316 ref_reg_val = 0;
3317 j = 0;
3318
3319 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3320 /* ref list 0 */
3321 struct StorablePicture *ref = pSlice->listX[1][i];
3322 unsigned int cfg;
3323 /* bit[6:5] - frame/field info,
3324 * 01 - top, 10 - bottom, 11 - frame
3325 */
3326
3327 #ifdef ERROR_CHECK
3328 if (ref == NULL) {
3329 hw->data_flag |= ERROR_FLAG;
3330 pic->data_flag |= ERROR_FLAG;
3331 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3332 return -2;
3333 }
3334 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3335 pic->data_flag |= ERROR_FLAG;
3336 hw->data_flag |= ERROR_FLAG;
3337 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3338 }
3339 if (ref->data_flag & NULL_FLAG)
3340 hw->data_flag |= NULL_FLAG;
3341#endif
3342 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3343 if (ref->structure == TOP_FIELD)
3344 cfg = 0x1;
3345 else if (ref->structure == BOTTOM_FIELD)
3346 cfg = 0x2;
3347 else /* FRAME */
3348 cfg = 0x3;
3349 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3350 ref_reg_val <<= 8;
3351 ref_reg_val |= one_ref_cfg;
3352 j++;
3353
3354 if (j == 4) {
3355 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3356 "H264_BUFFER_INFO_DATA: %x\n",
3357 ref_reg_val);
3358 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3359 j = 0;
3360 }
3361 print_pic_info(DECODE_ID(hw), "list1",
3362 pSlice->listX[1][i], -1);
3363 }
3364 if (j != 0) {
3365 while (j != 4) {
3366 ref_reg_val <<= 8;
3367 ref_reg_val |= one_ref_cfg;
3368 j++;
3369 }
3370 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3371 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3372 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3373 }
3374
3375 /* configure co-locate buffer */
3376 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3377 ;
3378 if ((pSlice->mode_8x8_flags & 0x4) &&
3379 (pSlice->mode_8x8_flags & 0x2))
3380 use_direct_8x8 = 1;
3381 else
3382 use_direct_8x8 = 0;
3383
3384#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3385 colocate_adr_offset =
3386 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3387 ? 1 : 2) * 96;
3388 if (use_direct_8x8)
3389 colocate_adr_offset >>= 2;
3390
3391 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3392 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3393 colocate_adr_offset, pSlice->first_mb_in_slice,
3394 colocate_adr_offset * pSlice->first_mb_in_slice);
3395
3396 colocate_adr_offset *= pSlice->first_mb_in_slice;
3397
3398 if ((pic->colocated_buf_index >= 0) &&
3399 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3400 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3401 ((p_H264_Dpb->colocated_buf_size *
3402 pic->colocated_buf_index)
3403 >> (use_direct_8x8 ? 2 : 0));
3404 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3405 p_H264_Dpb->colocated_mv_addr_end) {
3406 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3407 "Error, colocate buf is not enough, index is %d\n",
3408 pic->colocated_buf_index);
3409 ret = -3;
3410 }
3411 val = colocate_wr_adr + colocate_adr_offset;
3412 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3413 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3414 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3415 val, pSlice->first_mb_in_slice, pic->structure,
3416 colocate_adr_offset, pSlice->mode_8x8_flags,
3417 p_H264_Dpb->colocated_buf_size);
3418 } else {
3419 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3420 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3421 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3422 }
3423#else
3424 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3425 colocate_adr_offset =
3426 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3427 if (use_direct_8x8)
3428 colocate_adr_offset >>= 2;
3429
3430 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3431 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3432 colocate_adr_offset, pSlice->first_mb_in_slice,
3433 colocate_adr_offset * pSlice->first_mb_in_slice);
3434
3435 colocate_adr_offset *= pSlice->first_mb_in_slice;
3436
3437 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3438 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3439 (use_direct_8x8 ? 2 : 0));
3440
3441 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3442 p_H264_Dpb->colocated_mv_addr_end) {
3443 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3444 "Error, colocate buf is not enough, col buf index is %d\n",
3445 colocate_buf_index);
3446 ret = -4;
3447 }
3448 val = colocate_wr_adr + colocate_adr_offset;
3449 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3450 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3451 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3452 val, pSlice->first_mb_in_slice, pic->structure,
3453 colocate_adr_offset, pSlice->mode_8x8_flags,
3454 p_H264_Dpb->colocated_buf_size);
3455#endif
3456 if (pSlice->listXsize[1] > 0) {
3457 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3458 /* H264_CO_MB_RD_ADDR[bit 31:30],
3459 * original picture structure of L1[0],
3460 * 00 - top field, 01 - bottom field,
3461 * 10 - frame, 11 - mbaff frame
3462 */
3463 int l10_structure;
3464 int cur_colocate_ref_type;
3465 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3466 * 0 - top, 1 - bot
3467 */
3468 unsigned int val;
3469#ifdef ERROR_CHECK
3470 if (colocate_pic == NULL) {
3471 hw->data_flag |= ERROR_FLAG;
3472 pic->data_flag |= ERROR_FLAG;
3473 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3474 return -5;
3475 }
3476 if (colocate_pic->data_flag & ERROR_FLAG) {
3477 pic->data_flag |= ERROR_FLAG;
3478 hw->data_flag |= ERROR_FLAG;
3479 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3480 }
3481 if (colocate_pic->data_flag & NULL_FLAG)
3482 hw->data_flag |= NULL_FLAG;
3483#endif
3484
3485 if (colocate_pic->mb_aff_frame_flag)
3486 l10_structure = 3;
3487 else {
3488 if (colocate_pic->coded_frame)
3489 l10_structure = 2;
3490 else
3491 l10_structure = (colocate_pic->structure ==
3492 BOTTOM_FIELD) ? 1 : 0;
3493 }
3494#if 0
3495 /*case0016, p16,
3496 *cur_colocate_ref_type should be configured base on current pic
3497 */
3498 if (pic->structure == FRAME &&
3499 pic->mb_aff_frame_flag)
3500 cur_colocate_ref_type = 0;
3501 else if (pic->structure == BOTTOM_FIELD)
3502 cur_colocate_ref_type = 1;
3503 else
3504 cur_colocate_ref_type = 0;
3505#else
3506 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3507 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3508 pic->mb_aff_frame_flag,
3509 pic->structure,
3510 pic->coded_frame);
3511 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3512 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3513 colocate_pic->mb_aff_frame_flag,
3514 colocate_pic->structure,
3515 colocate_pic->coded_frame);
3516 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3517 cur_colocate_ref_type =
3518 (abs(pic->poc - colocate_pic->top_poc)
3519 < abs(pic->poc -
3520 colocate_pic->bottom_poc)) ? 0 : 1;
3521 } else
3522 cur_colocate_ref_type =
3523 (colocate_pic->structure
3524 == BOTTOM_FIELD) ? 1 : 0;
3525#endif
3526
3527#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3528 if ((colocate_pic->colocated_buf_index >= 0) &&
3529 (colocate_pic->colocated_buf_index <
3530 p_H264_Dpb->colocated_buf_count)) {
3531 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3532 ((p_H264_Dpb->colocated_buf_size *
3533 colocate_pic->colocated_buf_index)
3534 >> (use_direct_8x8 ? 2 : 0));
3535 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3536 p_H264_Dpb->colocated_mv_addr_end) {
3537 dpb_print(DECODE_ID(hw),
3538 PRINT_FLAG_ERROR,
3539 "Error, colocate buf is not enough, index is %d\n",
3540 colocate_pic->colocated_buf_index);
3541 ret = -6;
3542 }
3543 /* bit 31:30 -- L1[0] picture coding structure,
3544 * 00 - top field, 01 - bottom field,
3545 * 10 - frame, 11 - mbaff frame
3546 * bit 29 - L1[0] top/bot for B field pciture,
3547 * 0 - top, 1 - bot
3548 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3549 * -- only used for B Picture Direct mode
3550 * [2:0] will set to 3'b000
3551 */
3552 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3553 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3554 (l10_structure << 30) |
3555 (cur_colocate_ref_type << 29);
3556 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3557 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3558 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3559 colocate_pic->colocated_buf_index,
3560 val, colocate_rd_adr + colocate_adr_offset,
3561 colocate_pic->structure,
3562 colocate_pic->mb_aff_frame_flag);
3563 } else {
3564 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3565 "Error, reference pic has no colocated buf\n");
3566 ret = -7;
3567 }
3568#else
3569 colocate_buf_index =
3570 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3571 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3572 ((p_H264_Dpb->colocated_buf_size *
3573 colocate_buf_index)
3574 >> (use_direct_8x8 ? 2 : 0));
3575 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3576 p_H264_Dpb->colocated_mv_addr_end) {
3577 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3578 "Error, colocate buf is not enough, col buf index is %d\n",
3579 colocate_buf_index);
3580 ret = -8;
3581 }
3582 /* bit 31:30 -- L1[0] picture coding structure,
3583 * 00 - top field, 01 - bottom field,
3584 * 10 - frame, 11 - mbaff frame
3585 * bit 29 - L1[0] top/bot for B field pciture,
3586 * 0 - top, 1 - bot
3587 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3588 * -- only used for B Picture Direct mode
3589 * [2:0] will set to 3'b000
3590 */
3591 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3592 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3593 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3594 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3595 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3596 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3597 val, colocate_pic->structure,
3598 colocate_pic->mb_aff_frame_flag);
3599#endif
3600 }
3601 return ret;
3602}
3603
3604static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3605{
3606 unsigned long flags;
3607 struct vdec_s *vdec = op_arg;
3608 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3609
3610 spin_lock_irqsave(&hw->lock, flags);
3611
3612 states->vf_pool_size = VF_POOL_SIZE;
3613 states->buf_free_num = kfifo_len(&hw->newframe_q);
3614 states->buf_avail_num = kfifo_len(&hw->display_q);
3615
3616 spin_unlock_irqrestore(&hw->lock, flags);
3617
3618 return 0;
3619}
3620
3621static struct vframe_s *vh264_vf_peek(void *op_arg)
3622{
3623 struct vframe_s *vf[2] = {0, 0};
3624 struct vdec_s *vdec = op_arg;
3625 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3626
3627 if (!hw)
3628 return NULL;
3629
3630 if (force_disp_bufspec_num & 0x100) {
3631 if (force_disp_bufspec_num & 0x200)
3632 return NULL;
3633 return &hw->vframe_dummy;
3634 }
3635
3636 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3637 if (vf[1]) {
3638 vf[0]->next_vf_pts_valid = true;
3639 vf[0]->next_vf_pts = vf[1]->pts;
3640 } else
3641 vf[0]->next_vf_pts_valid = false;
3642 return vf[0];
3643 }
3644
3645 return NULL;
3646}
3647
3648static struct vframe_s *vh264_vf_get(void *op_arg)
3649{
3650 struct vframe_s *vf;
3651 struct vdec_s *vdec = op_arg;
3652 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3653
3654 if (!hw)
3655 return NULL;
3656
3657 if (force_disp_bufspec_num & 0x100) {
3658 int buffer_index = force_disp_bufspec_num & 0xff;
3659 if (force_disp_bufspec_num & 0x200)
3660 return NULL;
3661
3662 vf = &hw->vframe_dummy;
3663 vf->duration_pulldown = 0;
3664 vf->pts = 0;
3665 vf->pts_us64 = 0;
3666 set_frame_info(hw, vf, buffer_index);
3667 vf->flag = 0;
3668 if (hw->mmu_enable) {
3669 if (hw->double_write_mode & 0x10) {
3670 /* double write only */
3671 vf->compBodyAddr = 0;
3672 vf->compHeadAddr = 0;
3673 } else {
3674 /*head adr*/
3675 vf->compHeadAddr =
3676 hw->buffer_spec[buffer_index].alloc_header_addr;
3677 /*body adr*/
3678 vf->compBodyAddr = 0;
3679 vf->canvas0Addr = vf->canvas1Addr = 0;
3680 }
3681
3682 vf->type = VIDTYPE_SCATTER;
3683
3684 if (hw->double_write_mode) {
3685 vf->type |= VIDTYPE_PROGRESSIVE
3686 | VIDTYPE_VIU_FIELD;
3687 vf->type |= VIDTYPE_VIU_NV21;
3688 if (hw->double_write_mode == 3)
3689 vf->type |= VIDTYPE_COMPRESS;
3690
3691 vf->canvas0Addr = vf->canvas1Addr = -1;
3692 vf->plane_num = 2;
3693 vf->canvas0_config[0] =
3694 hw->buffer_spec[buffer_index].
3695 canvas_config[0];
3696 vf->canvas0_config[1] =
3697 hw->buffer_spec[buffer_index].
3698 canvas_config[1];
3699
3700 vf->canvas1_config[0] =
3701 hw->buffer_spec[buffer_index].
3702 canvas_config[0];
3703 vf->canvas1_config[1] =
3704 hw->buffer_spec[buffer_index].
3705 canvas_config[1];
3706 } else {
3707 vf->type |=
3708 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3709 vf->canvas0Addr = vf->canvas1Addr = 0;
3710 }
3711 vf->bitdepth =
3712 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3713
3714 vf->compWidth = hw->frame_width;
3715 vf->compHeight = hw->frame_height;
3716
3717 if (hw->double_write_mode) {
3718 vf->width = hw->frame_width /
3719 get_double_write_ratio(hw);
3720 vf->height = hw->frame_height /
3721 get_double_write_ratio(hw);
3722 }
3723 } else {
3724 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3725 VIDTYPE_VIU_NV21;
3726 vf->canvas0Addr = vf->canvas1Addr =
3727 spec2canvas(&hw->buffer_spec[buffer_index]);
3728 }
3729
3730 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3731 hw->bmmu_box, buffer_index);*/
3732 update_vf_memhandle(hw, vf, buffer_index);
3733 force_disp_bufspec_num |= 0x200;
3734 return vf;
3735 }
3736
3737 if (kfifo_get(&hw->display_q, &vf)) {
3738 int time = jiffies;
3739 unsigned int frame_interval =
3740 1000*(time - hw->last_frame_time)/HZ;
3741 struct vframe_s *next_vf;
3742 if (dpb_is_debug(DECODE_ID(hw),
3743 PRINT_FLAG_VDEC_DETAIL)) {
3744 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3745 int frame_index = FRAME_INDEX(vf->index);
3746 if (frame_index < 0 ||
3747 frame_index >= DPB_SIZE_MAX) {
3748 dpb_print(DECODE_ID(hw), 0,
3749 "%s vf index 0x%x error\r\n",
3750 __func__, vf->index);
3751 } else {
3752 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3753 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3754 __func__, BUFSPEC_INDEX(vf->index), vf,
3755 p_H264_Dpb->mFrameStore[frame_index].poc,
3756 vf->duration, vf->pts, frame_interval);
3757 }
3758 }
3759 if (hw->last_frame_time > 0) {
3760 if (frame_interval >
3761 max_get_frame_interval[DECODE_ID(hw)])
3762 max_get_frame_interval[DECODE_ID(hw)]
3763 = frame_interval;
3764 }
3765 hw->last_frame_time = time;
3766 hw->vf_get_count++;
3767 if (kfifo_peek(&hw->display_q, &next_vf)) {
3768 vf->next_vf_pts_valid = true;
3769 vf->next_vf_pts = next_vf->pts;
3770 } else
3771 vf->next_vf_pts_valid = false;
3772 return vf;
3773 }
3774
3775 return NULL;
3776}
3777
3778static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3779{
3780 struct vdec_s *vdec = op_arg;
3781 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3782 int buf_spec_num;
3783 int frame_index;
3784
3785 if (vf == (&hw->vframe_dummy))
3786 return;
3787 if (vf->index == -1) {
3788 dpb_print(DECODE_ID(hw), 0,
3789 "Warning: %s vf %p invalid index\r\n",
3790 __func__, vf);
3791 return;
3792 }
3793 frame_index = FRAME_INDEX(vf->index);
3794 buf_spec_num = BUFSPEC_INDEX(vf->index);
3795 if (frame_index < 0 ||
3796 frame_index >= DPB_SIZE_MAX ||
3797 buf_spec_num < 0 ||
3798 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3799 dpb_print(DECODE_ID(hw), 0,
3800 "%s vf index 0x%x error\r\n",
3801 __func__, vf->index);
3802 return;
3803 }
3804 /*get_buf_spec_idx_by_canvas_config(hw,
3805 &vf->canvas0_config[0]);*/
3806 if (hw->buffer_spec[buf_spec_num].used == 2) {
3807 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3808 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3809 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3810 __func__, vf, frame_index,
3811 p_H264_Dpb->mFrameStore[frame_index].poc,
3812 buf_spec_num,
3813 hw->buffer_spec[buf_spec_num].used,
3814 hw->buffer_spec[buf_spec_num].vf_ref);
3815 hw->buffer_spec[buf_spec_num].vf_ref--;
3816 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3817 set_frame_output_flag(&hw->dpb, frame_index);
3818 } else {
3819 unsigned long flags;
3820 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3821 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3822 __func__, vf, buf_spec_num,
3823 hw->buffer_spec[buf_spec_num].used,
3824 hw->buffer_spec[buf_spec_num].vf_ref);
3825 spin_lock_irqsave(&hw->bufspec_lock, flags);
3826 hw->buffer_spec[buf_spec_num].vf_ref--;
3827 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3828 if (hw->buffer_spec[buf_spec_num].used == 3)
3829 hw->buffer_spec[buf_spec_num].used = 4;
3830 else if (hw->buffer_spec[buf_spec_num].used == 5)
3831 hw->buffer_spec[buf_spec_num].used = 0;
3832 }
3833 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3834 if (dpb_is_debug(DECODE_ID(hw),
3835 PRINT_FLAG_DUMP_BUFSPEC))
3836 dump_bufspec(hw, __func__);
3837
3838 }
3839
3840 hw->vf_put_count++;
3841 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3842
3843#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3844 if (hw->buffer_empty_flag)
3845 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3846}
3847
3848static int vh264_event_cb(int type, void *data, void *op_arg)
3849{
3850 unsigned long flags;
3851 struct vdec_s *vdec = op_arg;
3852 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3853
3854 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3855 struct provider_aux_req_s *req =
3856 (struct provider_aux_req_s *)data;
3857 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3858 spin_lock_irqsave(&hw->lock, flags);
3859 req->aux_buf = NULL;
3860 req->aux_size = 0;
3861 if (buf_spec_num >= 0 &&
3862 buf_spec_num < BUFSPEC_POOL_SIZE &&
3863 is_buf_spec_in_disp_q(hw, buf_spec_num)
3864 ) {
3865 req->aux_buf =
3866 hw->buffer_spec[buf_spec_num].aux_data_buf;
3867 req->aux_size =
3868 hw->buffer_spec[buf_spec_num].aux_data_size;
3869#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3870 req->dv_enhance_exist =
3871 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3872#else
3873 req->dv_enhance_exist = 0;
3874#endif
3875 }
3876 spin_unlock_irqrestore(&hw->lock, flags);
3877
3878 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3879 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3880 __func__, type, buf_spec_num, req->aux_size);
3881 }
3882
3883 return 0;
3884}
3885
3886static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3887 u32 index)
3888{
3889 struct canvas_config_s *p_canvas_config;
3890 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3891 force_rate_framebase : force_rate_streambase;
3892 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3893 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3894 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3895
3896 /* signal_type */
3897 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3898 vf->signal_type = hw->video_signal_from_vui;
3899 if (hw->is_used_v4l) {
3900 struct aml_vdec_hdr_infos hdr;
3901 struct aml_vcodec_ctx *ctx =
3902 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3903
3904 memset(&hdr, 0, sizeof(hdr));
3905 hdr.signal_type = hw->video_signal_from_vui;
3906 vdec_v4l_set_hdr_infos(ctx, &hdr);
3907 }
3908 } else
3909 vf->signal_type = 0;
3910
3911 vf->width = hw->frame_width;
3912 vf->height = hw->frame_height;
3913 if (force_rate) {
3914 if (force_rate == -1)
3915 vf->duration = 0;
3916 else
3917 vf->duration = 96000/force_rate;
3918 } else
3919 vf->duration = hw->frame_dur;
3920 vf->ratio_control =
3921 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3922 DISP_RATIO_ASPECT_RATIO_BIT;
3923 vf->orientation = hw->vh264_rotation;
3924
3925 if (hw->mmu_enable)
3926 return;
3927
3928 vf->canvas0Addr = vf->canvas1Addr = -1;
3929#ifdef NV21
3930 vf->plane_num = 2;
3931#else
3932 vf->plane_num = 3;
3933#endif
3934
3935 if (IS_VDEC_DW(hw)) {
3936 vf->width = (hw->frame_width /2);
3937 if (IS_VDEC_DW(hw) == 2)
3938 vf->height = (hw->frame_height /2);
3939 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3940 } else
3941 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3942
3943 vf->canvas0_config[0] = p_canvas_config[0];
3944 vf->canvas0_config[1] = p_canvas_config[1];
3945#ifndef NV21
3946 vf->canvas0_config[2] = p_canvas_config[2];
3947#endif
3948 vf->canvas1_config[0] = p_canvas_config[0];
3949 vf->canvas1_config[1] = p_canvas_config[1];
3950#ifndef NV21
3951 vf->canvas1_config[2] = p_canvas_config[2];
3952#endif
3953}
3954
3955static void get_picture_qos_info(struct StorablePicture *picture)
3956{
3957 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3958 unsigned char a[3];
3959 unsigned char i, j, t;
3960 unsigned long data;
3961
3962 get_random_bytes(&data, sizeof(unsigned long));
3963 if (picture->slice_type == I_SLICE)
3964 data = 0;
3965 a[0] = data & 0xff;
3966 a[1] = (data >> 8) & 0xff;
3967 a[2] = (data >> 16) & 0xff;
3968
3969 for (i = 0; i < 3; i++)
3970 for (j = i+1; j < 3; j++) {
3971 if (a[j] < a[i]) {
3972 t = a[j];
3973 a[j] = a[i];
3974 a[i] = t;
3975 } else if (a[j] == a[i]) {
3976 a[i]++;
3977 t = a[j];
3978 a[j] = a[i];
3979 a[i] = t;
3980 }
3981 }
3982 picture->max_mv = a[2];
3983 picture->avg_mv = a[1];
3984 picture->min_mv = a[0];
3985 /*
3986 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3987 data, a[0], a[1], a[2]);
3988 */
3989
3990 get_random_bytes(&data, sizeof(unsigned long));
3991 a[0] = data & 0x1f;
3992 a[1] = (data >> 8) & 0x3f;
3993 a[2] = (data >> 16) & 0x7f;
3994
3995 for (i = 0; i < 3; i++)
3996 for (j = i+1; j < 3; j++) {
3997 if (a[j] < a[i]) {
3998 t = a[j];
3999 a[j] = a[i];
4000 a[i] = t;
4001 } else if (a[j] == a[i]) {
4002 a[i]++;
4003 t = a[j];
4004 a[j] = a[i];
4005 a[i] = t;
4006 }
4007 }
4008 picture->max_qp = a[2];
4009 picture->avg_qp = a[1];
4010 picture->min_qp = a[0];
4011 /*
4012 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4013 data, a[0], a[1], a[2]);
4014 */
4015
4016 get_random_bytes(&data, sizeof(unsigned long));
4017 a[0] = data & 0x1f;
4018 a[1] = (data >> 8) & 0x3f;
4019 a[2] = (data >> 16) & 0x7f;
4020
4021 for (i = 0; i < 3; i++)
4022 for (j = i+1; j < 3; j++) {
4023 if (a[j] < a[i]) {
4024 t = a[j];
4025 a[j] = a[i];
4026 a[i] = t;
4027 } else if (a[j] == a[i]) {
4028 a[i]++;
4029 t = a[j];
4030 a[j] = a[i];
4031 a[i] = t;
4032 }
4033 }
4034 picture->max_skip = a[2];
4035 picture->avg_skip = a[1];
4036 picture->min_skip = a[0];
4037
4038
4039 /*
4040 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4041 data,a[0], a[1], a[2]);
4042 */
4043 } else {
4044 uint32_t blk88_y_count;
4045 uint32_t blk88_c_count;
4046 uint32_t blk22_mv_count;
4047 uint32_t rdata32;
4048 int32_t mv_hi;
4049 int32_t mv_lo;
4050 uint32_t rdata32_l;
4051 uint32_t mvx_L0_hi;
4052 uint32_t mvy_L0_hi;
4053 uint32_t mvx_L1_hi;
4054 uint32_t mvy_L1_hi;
4055 int64_t value;
4056 uint64_t temp_value;
4057/*
4058#define DEBUG_QOS
4059*/
4060#ifdef DEBUG_QOS
4061 int pic_number = picture->poc;
4062#endif
4063
4064 picture->max_mv = 0;
4065 picture->avg_mv = 0;
4066 picture->min_mv = 0;
4067
4068 picture->max_skip = 0;
4069 picture->avg_skip = 0;
4070 picture->min_skip = 0;
4071
4072 picture->max_qp = 0;
4073 picture->avg_qp = 0;
4074 picture->min_qp = 0;
4075
4076
4077
4078
4079
4080 /* set rd_idx to 0 */
4081 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4082 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4083 if (blk88_y_count == 0) {
4084#ifdef DEBUG_QOS
4085 pr_info(" [Picture %d Quality] NO Data yet.\n",
4086 pic_number);
4087#endif
4088 /* reset all counts */
4089 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4090 return;
4091 }
4092 /* qp_y_sum */
4093 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4094#ifdef DEBUG_QOS
4095 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4096 pic_number, rdata32/blk88_y_count,
4097 rdata32, blk88_y_count);
4098#endif
4099 picture->avg_qp = rdata32/blk88_y_count;
4100 /* intra_y_count */
4101 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4102#ifdef DEBUG_QOS
4103 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4104 pic_number, rdata32*100/blk88_y_count,
4105 '%', rdata32);
4106#endif
4107 /* skipped_y_count */
4108 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4109#ifdef DEBUG_QOS
4110 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4111 pic_number, rdata32*100/blk88_y_count,
4112 '%', rdata32);
4113#endif
4114 picture->avg_skip = rdata32*100/blk88_y_count;
4115 /* coeff_non_zero_y_count */
4116 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4117#ifdef DEBUG_QOS
4118 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4119 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4120 '%', rdata32);
4121#endif
4122 /* blk66_c_count */
4123 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4124 if (blk88_c_count == 0) {
4125#ifdef DEBUG_QOS
4126 pr_info(" [Picture %d Quality] NO Data yet.\n",
4127 pic_number);
4128#endif
4129 /* reset all counts */
4130 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4131 return;
4132 }
4133 /* qp_c_sum */
4134 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4135#ifdef DEBUG_QOS
4136 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4137 pic_number, rdata32/blk88_c_count,
4138 rdata32, blk88_c_count);
4139#endif
4140 /* intra_c_count */
4141 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4142#ifdef DEBUG_QOS
4143 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4144 pic_number, rdata32*100/blk88_c_count,
4145 '%', rdata32);
4146#endif
4147 /* skipped_cu_c_count */
4148 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4149#ifdef DEBUG_QOS
4150 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4151 pic_number, rdata32*100/blk88_c_count,
4152 '%', rdata32);
4153#endif
4154 /* coeff_non_zero_c_count */
4155 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4156#ifdef DEBUG_QOS
4157 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4158 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4159 '%', rdata32);
4160#endif
4161
4162 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4163 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4164 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4165#ifdef DEBUG_QOS
4166 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4167 pic_number, (rdata32>>0)&0xff);
4168#endif
4169 picture->min_qp = (rdata32>>0)&0xff;
4170
4171#ifdef DEBUG_QOS
4172 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4173 pic_number, (rdata32>>8)&0xff);
4174#endif
4175 picture->max_qp = (rdata32>>8)&0xff;
4176
4177#ifdef DEBUG_QOS
4178 pr_info(" [Picture %d Quality] C QP min : %d\n",
4179 pic_number, (rdata32>>16)&0xff);
4180 pr_info(" [Picture %d Quality] C QP max : %d\n",
4181 pic_number, (rdata32>>24)&0xff);
4182#endif
4183
4184 /* blk22_mv_count */
4185 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4186 if (blk22_mv_count == 0) {
4187#ifdef DEBUG_QOS
4188 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4189 pic_number);
4190#endif
4191 /* reset all counts */
4192 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4193 return;
4194 }
4195 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4196 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4197 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4198 /* should all be 0x00 or 0xff */
4199#ifdef DEBUG_QOS
4200 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4201 pic_number, rdata32);
4202#endif
4203 mvx_L0_hi = ((rdata32>>0)&0xff);
4204 mvy_L0_hi = ((rdata32>>8)&0xff);
4205 mvx_L1_hi = ((rdata32>>16)&0xff);
4206 mvy_L1_hi = ((rdata32>>24)&0xff);
4207
4208 /* mvx_L0_count[31:0] */
4209 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4210 temp_value = mvx_L0_hi;
4211 temp_value = (temp_value << 32) | rdata32_l;
4212
4213 if (mvx_L0_hi & 0x80)
4214 value = 0xFFFFFFF000000000 | temp_value;
4215 else
4216 value = temp_value;
4217 value = div_s64(value, blk22_mv_count);
4218#ifdef DEBUG_QOS
4219 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4220 pic_number, (int)(value),
4221 value, blk22_mv_count);
4222#endif
4223 picture->avg_mv = value;
4224
4225 /* mvy_L0_count[31:0] */
4226 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4227 temp_value = mvy_L0_hi;
4228 temp_value = (temp_value << 32) | rdata32_l;
4229
4230 if (mvy_L0_hi & 0x80)
4231 value = 0xFFFFFFF000000000 | temp_value;
4232 else
4233 value = temp_value;
4234#ifdef DEBUG_QOS
4235 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4236 pic_number, rdata32_l/blk22_mv_count,
4237 value, blk22_mv_count);
4238#endif
4239
4240 /* mvx_L1_count[31:0] */
4241 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4242 temp_value = mvx_L1_hi;
4243 temp_value = (temp_value << 32) | rdata32_l;
4244 if (mvx_L1_hi & 0x80)
4245 value = 0xFFFFFFF000000000 | temp_value;
4246 else
4247 value = temp_value;
4248#ifdef DEBUG_QOS
4249 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4250 pic_number, rdata32_l/blk22_mv_count,
4251 value, blk22_mv_count);
4252#endif
4253
4254 /* mvy_L1_count[31:0] */
4255 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4256 temp_value = mvy_L1_hi;
4257 temp_value = (temp_value << 32) | rdata32_l;
4258 if (mvy_L1_hi & 0x80)
4259 value = 0xFFFFFFF000000000 | temp_value;
4260 else
4261 value = temp_value;
4262#ifdef DEBUG_QOS
4263 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4264 pic_number, rdata32_l/blk22_mv_count,
4265 value, blk22_mv_count);
4266#endif
4267
4268 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4269 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4270 mv_hi = (rdata32>>16)&0xffff;
4271 if (mv_hi & 0x8000)
4272 mv_hi = 0x8000 - mv_hi;
4273#ifdef DEBUG_QOS
4274 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4275 pic_number, mv_hi);
4276#endif
4277 picture->max_mv = mv_hi;
4278
4279 mv_lo = (rdata32>>0)&0xffff;
4280 if (mv_lo & 0x8000)
4281 mv_lo = 0x8000 - mv_lo;
4282#ifdef DEBUG_QOS
4283 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4284 pic_number, mv_lo);
4285#endif
4286 picture->min_mv = mv_lo;
4287
4288 /* {mvy_L0_max, mvy_L0_min} */
4289 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4290 mv_hi = (rdata32>>16)&0xffff;
4291 if (mv_hi & 0x8000)
4292 mv_hi = 0x8000 - mv_hi;
4293#ifdef DEBUG_QOS
4294 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4295 pic_number, mv_hi);
4296#endif
4297
4298 mv_lo = (rdata32>>0)&0xffff;
4299 if (mv_lo & 0x8000)
4300 mv_lo = 0x8000 - mv_lo;
4301#ifdef DEBUG_QOS
4302 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4303 pic_number, mv_lo);
4304#endif
4305
4306 /* {mvx_L1_max, mvx_L1_min} */
4307 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4308 mv_hi = (rdata32>>16)&0xffff;
4309 if (mv_hi & 0x8000)
4310 mv_hi = 0x8000 - mv_hi;
4311#ifdef DEBUG_QOS
4312 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4313 pic_number, mv_hi);
4314#endif
4315
4316 mv_lo = (rdata32>>0)&0xffff;
4317 if (mv_lo & 0x8000)
4318 mv_lo = 0x8000 - mv_lo;
4319#ifdef DEBUG_QOS
4320 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4321 pic_number, mv_lo);
4322#endif
4323
4324 /* {mvy_L1_max, mvy_L1_min} */
4325 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4326 mv_hi = (rdata32>>16)&0xffff;
4327 if (mv_hi & 0x8000)
4328 mv_hi = 0x8000 - mv_hi;
4329#ifdef DEBUG_QOS
4330 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4331 pic_number, mv_hi);
4332#endif
4333 mv_lo = (rdata32>>0)&0xffff;
4334 if (mv_lo & 0x8000)
4335 mv_lo = 0x8000 - mv_lo;
4336#ifdef DEBUG_QOS
4337 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4338 pic_number, mv_lo);
4339#endif
4340
4341 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4342#ifdef DEBUG_QOS
4343 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4344 pic_number, rdata32);
4345#endif
4346 /* reset all counts */
4347 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4348 }
4349}
4350
4351static int get_max_dec_frame_buf_size(int level_idc,
4352 int max_reference_frame_num, int mb_width,
4353 int mb_height)
4354{
4355 int pic_size = mb_width * mb_height * 384;
4356
4357 int size = 0;
4358
4359 switch (level_idc) {
4360 case 9:
4361 size = 152064;
4362 break;
4363 case 10:
4364 size = 152064;
4365 break;
4366 case 11:
4367 size = 345600;
4368 break;
4369 case 12:
4370 size = 912384;
4371 break;
4372 case 13:
4373 size = 912384;
4374 break;
4375 case 20:
4376 size = 912384;
4377 break;
4378 case 21:
4379 size = 1824768;
4380 break;
4381 case 22:
4382 size = 3110400;
4383 break;
4384 case 30:
4385 size = 3110400;
4386 break;
4387 case 31:
4388 size = 6912000;
4389 break;
4390 case 32:
4391 size = 7864320;
4392 break;
4393 case 40:
4394 size = 12582912;
4395 break;
4396 case 41:
4397 size = 12582912;
4398 break;
4399 case 42:
4400 size = 13369344;
4401 break;
4402 case 50:
4403 size = 42393600;
4404 break;
4405 case 51:
4406 case 52:
4407 default:
4408 size = 70778880;
4409 break;
4410 }
4411
4412 size /= pic_size;
4413 size = size + 1; /* need one more buffer */
4414
4415 if (max_reference_frame_num > size)
4416 size = max_reference_frame_num;
4417 size = imin(size, 16);
4418
4419 return size;
4420}
4421
4422static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4423{
4424 int i, j;
4425
4426 if (hw->double_write_mode) {
4427 mutex_lock(&vmh264_mutex);
4428 if (hw->decode_pic_count == 0) {
4429 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4430 i = get_buf_spec_by_canvas_pos(hw, j);
4431 if (i >= 0)
4432 config_decode_canvas_ex(hw, i);
4433 }
4434 }
4435 mutex_unlock(&vmh264_mutex);
4436 }
4437}
4438
4439static int vh264_set_params(struct vdec_h264_hw_s *hw,
4440 u32 param1, u32 param2, u32 param3, u32 param4)
4441{
4442 int i, j;
4443 int mb_width, mb_total;
4444 int max_reference_size, level_idc;
4445 int mb_height = 0;
4446 unsigned long flags;
4447 /*int mb_mv_byte;*/
4448 struct vdec_s *vdec = hw_to_vdec(hw);
4449 u32 seq_info2;
4450 int ret = 0;
4451 int active_buffer_spec_num;
4452 unsigned int buf_size;
4453 unsigned int frame_mbs_only_flag;
4454 unsigned int chroma_format_idc, chroma444;
4455 unsigned int crop_infor, crop_bottom, crop_right;
4456 unsigned int used_reorder_dpb_size_margin
4457 = hw->reorder_dpb_size_margin;
4458 u8 *colocate_vaddr = NULL;
4459
4460#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4461 if (vdec->master || vdec->slave)
4462 used_reorder_dpb_size_margin =
4463 reorder_dpb_size_margin_dv;
4464#endif
4465 seq_info2 = param1;
4466 hw->seq_info = param2;
4467
4468 mb_width = seq_info2 & 0xff;
4469 mb_total = (seq_info2 >> 8) & 0xffff;
4470 if (!mb_width && mb_total) /*for 4k2k*/
4471 mb_width = 256;
4472 if (mb_width)
4473 mb_height = mb_total/mb_width;
4474 if (mb_width <= 0 || mb_height <= 0 ||
4475 is_oversize(mb_width << 4, mb_height << 4)) {
4476 dpb_print(DECODE_ID(hw), 0,
4477 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4478 seq_info2,
4479 mb_width,
4480 mb_height);
4481 return -1;
4482 }
4483
4484 if (seq_info2 != 0 &&
4485 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4486 hw->seq_info2 != 0
4487 ) /*picture size changed*/
4488 h264_reconfig(hw);
4489
4490 if (hw->config_bufmgr_done == 0) {
4491 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4492 u32 reg_val;
4493 hw->cfg_param1 = param1;
4494 hw->cfg_param2 = param2;
4495 hw->cfg_param3 = param3;
4496 hw->cfg_param4 = param4;
4497
4498 hw->seq_info2 = seq_info2 & (~0x80000000);
4499 dpb_print(DECODE_ID(hw), 0,
4500 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4501 seq_info2, hw->seq_info);
4502
4503 dpb_init_global(&hw->dpb,
4504 DECODE_ID(hw), 0, 0);
4505
4506 p_H264_Dpb->fast_output_enable = fast_output_enable;
4507 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4508
4509#if 1
4510 /*crop*/
4511 /* AV_SCRATCH_2
4512 bit 15: frame_mbs_only_flag
4513 bit 13-14: chroma_format_idc */
4514 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4515 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4516 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4517
4518 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4519 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4520 (2 - frame_mbs_only_flag) */
4521 crop_infor = param3;
4522 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4523 crop_right = ((crop_infor >> 16) & 0xff)
4524 >> (2 - frame_mbs_only_flag);
4525
4526 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4527 hw->frame_width = mb_width << 4;
4528 hw->frame_height = mb_height << 4;
4529 if (frame_mbs_only_flag) {
4530 hw->frame_height =
4531 hw->frame_height - (2 >> chroma444) *
4532 min(crop_bottom,
4533 (unsigned int)((8 << chroma444) - 1));
4534 hw->frame_width =
4535 hw->frame_width -
4536 (2 >> chroma444) * min(crop_right,
4537 (unsigned
4538 int)((8 << chroma444) - 1));
4539 } else {
4540 hw->frame_height =
4541 hw->frame_height - (4 >> chroma444) *
4542 min(crop_bottom,
4543 (unsigned int)((8 << chroma444)
4544 - 1));
4545 hw->frame_width =
4546 hw->frame_width -
4547 (4 >> chroma444) * min(crop_right,
4548 (unsigned int)((8 << chroma444) - 1));
4549 }
4550 dpb_print(DECODE_ID(hw), 0,
4551 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4552 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4553 dpb_print(DECODE_ID(hw), 0,
4554 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4555 mb_height, crop_right,
4556 hw->frame_width, mb_width);
4557
4558 if (hw->frame_height == 1088)
4559 hw->frame_height = 1080;
4560#endif
4561 if (!hw->mmu_enable) {
4562 mb_width = (mb_width+3) & 0xfffffffc;
4563 mb_height = (mb_height+3) & 0xfffffffc;
4564 }
4565 mb_total = mb_width * mb_height;
4566 hw->mb_width = mb_width;
4567 hw->mb_height = mb_height;
4568 hw->mb_total = mb_total;
4569 if (hw->mmu_enable)
4570 hevc_mcr_sao_global_hw_init(hw,
4571 (hw->mb_width << 4), (hw->mb_height << 4));
4572
4573 reg_val = param4;
4574 level_idc = reg_val & 0xff;
4575 max_reference_size = (reg_val >> 8) & 0xff;
4576 hw->dpb.origin_max_reference = max_reference_size;
4577 dpb_print(DECODE_ID(hw), 0,
4578 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4579 mb_height, mb_width, mb_total,
4580 level_idc, max_reference_size);
4581
4582
4583 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4584 hw->dpb.reorder_pic_num =
4585 get_max_dec_frame_buf_size(level_idc,
4586 max_reference_size, mb_width, mb_height);
4587
4588 dpb_print(DECODE_ID(hw), 0,
4589 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4590 hw->bitstream_restriction_flag,
4591 hw->max_dec_frame_buffering,
4592 hw->dpb.reorder_pic_num);
4593
4594 if ((hw->bitstream_restriction_flag) &&
4595 (hw->max_dec_frame_buffering <
4596 hw->dpb.reorder_pic_num)) {
4597 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4598 dpb_print(DECODE_ID(hw), 0,
4599 "set reorder_pic_num to %d\n",
4600 hw->dpb.reorder_pic_num);
4601 }
4602
4603 active_buffer_spec_num =
4604 hw->dpb.reorder_pic_num
4605 + used_reorder_dpb_size_margin;
4606 hw->max_reference_size =
4607 max_reference_size + reference_buf_margin;
4608
4609 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4610 active_buffer_spec_num = MAX_VF_BUF_NUM;
4611 hw->dpb.reorder_pic_num = active_buffer_spec_num
4612 - used_reorder_dpb_size_margin;
4613 }
4614 hw->dpb.mDPB.size = active_buffer_spec_num;
4615 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4616 hw->max_reference_size = MAX_VF_BUF_NUM;
4617 hw->dpb.max_reference_size = hw->max_reference_size;
4618
4619 if (hw->no_poc_reorder_flag)
4620 hw->dpb.reorder_pic_num = 1;
4621 dpb_print(DECODE_ID(hw), 0,
4622 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4623 __func__, active_buffer_spec_num,
4624 hw->dpb.reorder_pic_num,
4625 hw->max_reference_size);
4626
4627 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4628
4629 mutex_lock(&vmh264_mutex);
4630 if (!hw->mmu_enable) {
4631 config_buf_specs(vdec);
4632 i = get_buf_spec_by_canvas_pos(hw, 0);
4633
4634 if (hw->is_used_v4l) {
4635 if (i != -1) {
4636 pr_info("v4l: delay alloc the buffer.\n");
4637 }
4638 } else {
4639 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4640 config_decode_canvas(hw, i);
4641 else
4642 ret = -1;
4643 }
4644 } else {
4645 if (hw->double_write_mode) {
4646 config_buf_specs_ex(vdec);
4647 } else {
4648 spin_lock_irqsave(&hw->bufspec_lock, flags);
4649 for (i = 0, j = 0;
4650 j < active_buffer_spec_num
4651 && i < BUFSPEC_POOL_SIZE;
4652 i++) {
4653 if (hw->buffer_spec[i].used != -1)
4654 continue;
4655 hw->buffer_spec[i].used = 0;
4656 hw->buffer_spec[i].
4657 alloc_header_addr = 0;
4658 hw->buffer_spec[i].canvas_pos = j;
4659 j++;
4660 }
4661 spin_unlock_irqrestore(&hw->bufspec_lock,
4662 flags);
4663 }
4664 hevc_mcr_config_canv2axitbl(hw, 0);
4665 }
4666 mutex_unlock(&vmh264_mutex);
4667 if (dpb_is_debug(DECODE_ID(hw),
4668 PRINT_FLAG_DUMP_BUFSPEC))
4669 dump_bufspec(hw, __func__);
4670
4671#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4672 buf_size = PAGE_ALIGN(
4673 p_H264_Dpb->colocated_buf_size *
4674 active_buffer_spec_num);
4675#else
4676 buf_size = PAGE_ALIGN(
4677 p_H264_Dpb->colocated_buf_size *
4678 hw->max_reference_size);
4679#endif
4680
4681 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4682 buf_size, DRIVER_NAME,
4683 &hw->collocate_cma_alloc_addr) < 0)
4684 return -1;
4685 if (!vdec_secure(vdec)) {
4686 /* clear for some mosaic problem after reset bufmgr */
4687 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4688 if (colocate_vaddr != NULL) {
4689 memset(colocate_vaddr, 0, buf_size);
4690 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4691 codec_mm_unmap_phyaddr(colocate_vaddr);
4692 }
4693 }
4694
4695 hw->dpb.colocated_mv_addr_start =
4696 hw->collocate_cma_alloc_addr;
4697#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4698 hw->dpb.colocated_mv_addr_end =
4699 hw->dpb.colocated_mv_addr_start +
4700 (p_H264_Dpb->colocated_buf_size *
4701 active_buffer_spec_num);
4702#else
4703 hw->dpb.colocated_mv_addr_end =
4704 hw->dpb.colocated_mv_addr_start +
4705 (p_H264_Dpb->colocated_buf_size *
4706 hw->max_reference_size);
4707#endif
4708 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4709 "callocate cma, %lx, %x\n",
4710 hw->collocate_cma_alloc_addr,
4711 hw->dpb.colocated_mv_addr_start);
4712
4713 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4714 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4715 hw->dpb.colocated_mv_addr_start,
4716 hw->dpb.colocated_mv_addr_end);
4717 if (!hw->mmu_enable) {
4718 mutex_lock(&vmh264_mutex);
4719 if (ret >= 0 && hw->decode_pic_count == 0) {
4720 int buf_cnt;
4721 /* h264_reconfig: alloc later*/
4722 buf_cnt = hw->dpb.mDPB.size;
4723
4724 for (j = 1; j < buf_cnt; j++) {
4725 i = get_buf_spec_by_canvas_pos(hw, j);
4726
4727 if (hw->is_used_v4l) {
4728 pr_info("v4l: delay alloc the buffer.\n");
4729 break;
4730 } else if (alloc_one_buf_spec(hw, i) < 0)
4731 break;
4732
4733 config_decode_canvas(hw, i);
4734 }
4735 }
4736 mutex_unlock(&vmh264_mutex);
4737 } else {
4738 vh264_config_canvs_for_mmu(hw);
4739 }
4740
4741 hw->config_bufmgr_done = 1;
4742
4743 /*end of config_bufmgr_done */
4744 }
4745
4746 return ret;
4747}
4748
4749static void vui_config(struct vdec_h264_hw_s *hw)
4750{
4751 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4752 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4753 /*time*/
4754 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4755 hw->time_scale = p_H264_Dpb->time_scale;
4756 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4757
4758 hw->bitstream_restriction_flag =
4759 p_H264_Dpb->bitstream_restriction_flag;
4760 hw->num_reorder_frames =
4761 p_H264_Dpb->num_reorder_frames;
4762 hw->max_dec_frame_buffering =
4763 p_H264_Dpb->max_dec_frame_buffering;
4764
4765 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4766 "vui_config: pdb %d, %d, %d\n",
4767 p_H264_Dpb->bitstream_restriction_flag,
4768 p_H264_Dpb->num_reorder_frames,
4769 p_H264_Dpb->max_dec_frame_buffering);
4770
4771 hw->fixed_frame_rate_flag = 0;
4772 if (hw->timing_info_present_flag) {
4773 hw->fixed_frame_rate_flag =
4774 p_H264_Dpb->fixed_frame_rate_flag;
4775
4776 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4777 ((!hw->sync_outside) ||
4778 (!hw->frame_dur)))
4779 && hw->num_units_in_tick && hw->time_scale) {
4780 if (hw->use_idr_framerate ||
4781 hw->fixed_frame_rate_flag ||
4782 !hw->frame_dur ||
4783 !hw->duration_from_pts_done
4784 /*|| vh264_running*/) {
4785 u32 frame_dur_es =
4786 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4787 hw->time_scale);
4788 if (hw->frame_dur != frame_dur_es) {
4789 hw->h264_first_valid_pts_ready = false;
4790 hw->h264pts1 = 0;
4791 hw->h264pts2 = 0;
4792 hw->h264_pts_count = 0;
4793 hw->duration_from_pts_done = 0;
4794 fixed_frame_rate_mode =
4795 FIX_FRAME_RATE_OFF;
4796 hw->pts_duration = 0;
4797 hw->frame_dur = frame_dur_es;
4798 vdec_schedule_work(&hw->notify_work);
4799 dpb_print(DECODE_ID(hw),
4800 PRINT_FLAG_DEC_DETAIL,
4801 "frame_dur %d from timing_info\n",
4802 hw->frame_dur);
4803 }
4804
4805 /*hack to avoid use ES frame duration when
4806 *it's half of the rate from system info
4807 * sometimes the encoder is given a wrong
4808 * frame rate but the system side information
4809 * is more reliable
4810 *if ((frame_dur * 2) != frame_dur_es) {
4811 * frame_dur = frame_dur_es;
4812 *}
4813 */
4814 }
4815 }
4816 } else {
4817 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4818 "H.264: timing_info not present\n");
4819 }
4820
4821 /*aspect ratio*/
4822 aspect_ratio_info_present_flag =
4823 p_H264_Dpb->vui_status & 0x1;
4824 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4825
4826 if (aspect_ratio_info_present_flag) {
4827 if (aspect_ratio_idc == EXTEND_SAR) {
4828 hw->h264_ar = 0x3ff;
4829 hw->height_aspect_ratio =
4830 p_H264_Dpb->aspect_ratio_sar_height;
4831 hw->width_aspect_ratio =
4832 p_H264_Dpb->aspect_ratio_sar_width;
4833 } else {
4834 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4835 aspect_ratio_idc); */
4836
4837 switch (aspect_ratio_idc) {
4838 case 1:
4839 hw->h264_ar = 0x3ff;
4840 hw->height_aspect_ratio = 1;
4841 hw->width_aspect_ratio = 1;
4842 break;
4843 case 2:
4844 hw->h264_ar = 0x3ff;
4845 hw->height_aspect_ratio = 11;
4846 hw->width_aspect_ratio = 12;
4847 break;
4848 case 3:
4849 hw->h264_ar = 0x3ff;
4850 hw->height_aspect_ratio = 11;
4851 hw->width_aspect_ratio = 10;
4852 break;
4853 case 4:
4854 hw->h264_ar = 0x3ff;
4855 hw->height_aspect_ratio = 11;
4856 hw->width_aspect_ratio = 16;
4857 break;
4858 case 5:
4859 hw->h264_ar = 0x3ff;
4860 hw->height_aspect_ratio = 33;
4861 hw->width_aspect_ratio = 40;
4862 break;
4863 case 6:
4864 hw->h264_ar = 0x3ff;
4865 hw->height_aspect_ratio = 11;
4866 hw->width_aspect_ratio = 24;
4867 break;
4868 case 7:
4869 hw->h264_ar = 0x3ff;
4870 hw->height_aspect_ratio = 11;
4871 hw->width_aspect_ratio = 20;
4872 break;
4873 case 8:
4874 hw->h264_ar = 0x3ff;
4875 hw->height_aspect_ratio = 11;
4876 hw->width_aspect_ratio = 32;
4877 break;
4878 case 9:
4879 hw->h264_ar = 0x3ff;
4880 hw->height_aspect_ratio = 33;
4881 hw->width_aspect_ratio = 80;
4882 break;
4883 case 10:
4884 hw->h264_ar = 0x3ff;
4885 hw->height_aspect_ratio = 11;
4886 hw->width_aspect_ratio = 18;
4887 break;
4888 case 11:
4889 hw->h264_ar = 0x3ff;
4890 hw->height_aspect_ratio = 11;
4891 hw->width_aspect_ratio = 15;
4892 break;
4893 case 12:
4894 hw->h264_ar = 0x3ff;
4895 hw->height_aspect_ratio = 33;
4896 hw->width_aspect_ratio = 64;
4897 break;
4898 case 13:
4899 hw->h264_ar = 0x3ff;
4900 hw->height_aspect_ratio = 99;
4901 hw->width_aspect_ratio = 160;
4902 break;
4903 case 14:
4904 hw->h264_ar = 0x3ff;
4905 hw->height_aspect_ratio = 3;
4906 hw->width_aspect_ratio = 4;
4907 break;
4908 case 15:
4909 hw->h264_ar = 0x3ff;
4910 hw->height_aspect_ratio = 2;
4911 hw->width_aspect_ratio = 3;
4912 break;
4913 case 16:
4914 hw->h264_ar = 0x3ff;
4915 hw->height_aspect_ratio = 1;
4916 hw->width_aspect_ratio = 2;
4917 break;
4918 default:
4919 if (hw->vh264_ratio >> 16) {
4920 hw->h264_ar = (hw->frame_height *
4921 (hw->vh264_ratio & 0xffff) *
4922 0x100 +
4923 ((hw->vh264_ratio >> 16) *
4924 hw->frame_width / 2)) /
4925 ((hw->vh264_ratio >> 16) *
4926 hw->frame_width);
4927 hw->height_aspect_ratio = 1;
4928 hw->width_aspect_ratio = 1;
4929 } else {
4930 hw->h264_ar = 0x3ff;
4931 hw->height_aspect_ratio = 1;
4932 hw->width_aspect_ratio = 1;
4933 }
4934 break;
4935 }
4936 }
4937 } else {
4938 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4939 "v264dec: aspect_ratio not available from source\n");
4940 if (hw->vh264_ratio >> 16) {
4941 /* high 16 bit is width, low 16 bit is height */
4942 hw->h264_ar =
4943 ((hw->vh264_ratio & 0xffff) *
4944 hw->frame_height * 0x100 +
4945 (hw->vh264_ratio >> 16) *
4946 hw->frame_width / 2) /
4947 ((hw->vh264_ratio >> 16) *
4948 hw->frame_width);
4949 hw->height_aspect_ratio = 1;
4950 hw->width_aspect_ratio = 1;
4951 } else {
4952 hw->h264_ar = 0x3ff;
4953 hw->height_aspect_ratio = 1;
4954 hw->width_aspect_ratio = 1;
4955 }
4956 }
4957
4958 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4959 if (((hw->frame_dur == RATE_2397_FPS)
4960 && (dec_control
4961 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4962 || ((RATE_2997_FPS ==
4963 hw->frame_dur) &&
4964 (dec_control &
4965 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4966 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4967 "force fix frame rate\n");
4968 hw->fixed_frame_rate_flag = 0x40;
4969 }
4970 }
4971
4972 /*video_signal_from_vui: to do .. */
4973}
4974
4975static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4976{
4977 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4978
4979 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4980 if (error_proc_policy & 0x20) {
4981 if (!hw->is_used_v4l)
4982 hw->reset_bufmgr_flag = 1;
4983 }
4984}
4985
4986void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4987{
4988 struct vdec_h264_hw_s *hw =
4989 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4990
4991 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4992
4993 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4994 hw->reset_bufmgr_flag = 1;
4995}
4996
4997#ifdef CONSTRAIN_MAX_BUF_NUM
4998static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
4999{
5000 int i;
5001 int count = 0;
5002 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5003 if (is_buf_spec_in_disp_q(hw, i) &&
5004 hw->buffer_spec[i].vf_ref > 0)
5005 count++;
5006 }
5007 return count;
5008}
5009
5010static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5011{
5012 int i;
5013 int count = 0;
5014 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5015 if (is_buf_spec_in_use(hw, i))
5016 count++;
5017 }
5018 return count;
5019}
5020#endif
5021
5022
5023static bool is_buffer_available(struct vdec_s *vdec)
5024{
5025 bool buffer_available = 1;
5026 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5027 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5028 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5029 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5030 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5031 ((p_H264_Dpb->mDPB.init_done) &&
5032 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5033 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5034 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5035 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5036 __func__,
5037 kfifo_len(&hw->newframe_q),
5038 have_free_buf_spec(vdec),
5039 p_H264_Dpb->mDPB.init_done,
5040 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5041 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5042 );
5043 buffer_available = 0;
5044 if (dpb_is_debug(DECODE_ID(hw),
5045 DEBUG_DISABLE_RUNREADY_RMBUF))
5046 return buffer_available;
5047
5048 if ((error_proc_policy & 0x4) &&
5049 (error_proc_policy & 0x8)) {
5050 if ((kfifo_len(&hw->display_q) <= 0) &&
5051 (p_H264_Dpb->mDPB.used_size ==
5052 p_H264_Dpb->mDPB.size) &&
5053 (p_Dpb->ref_frames_in_buffer >
5054 (imax(
5055 1, p_Dpb->num_ref_frames)
5056 - p_Dpb->ltref_frames_in_buffer +
5057 force_sliding_margin)))
5058 bufmgr_recover(hw);
5059 else
5060 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5061 } else if ((error_proc_policy & 0x4) &&
5062 (kfifo_len(&hw->display_q) <= 0) &&
5063 ((p_H264_Dpb->mDPB.used_size ==
5064 p_H264_Dpb->mDPB.size) ||
5065 (!have_free_buf_spec(vdec)))) {
5066 enum receviver_start_e state = RECEIVER_INACTIVE;
5067 if ((error_proc_policy & 0x10) &&
5068 vf_get_receiver(vdec->vf_provider_name)) {
5069 state =
5070 vf_notify_receiver(vdec->vf_provider_name,
5071 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5072 NULL);
5073 if ((state == RECEIVER_STATE_NULL)
5074 || (state == RECEIVER_STATE_NONE))
5075 state = RECEIVER_INACTIVE;
5076 }
5077 if (state == RECEIVER_INACTIVE)
5078 bufmgr_recover(hw);
5079 else
5080 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5081 } else if ((error_proc_policy & 0x8) &&
5082 (p_Dpb->ref_frames_in_buffer >
5083 (imax(
5084 1, p_Dpb->num_ref_frames)
5085 - p_Dpb->ltref_frames_in_buffer +
5086 force_sliding_margin)))
5087 bufmgr_recover(hw);
5088 else
5089 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5090
5091 if (hw->reset_bufmgr_flag == 1)
5092 buffer_available = 1;
5093 }
5094
5095 return buffer_available;
5096}
5097
5098#define AUX_TAG_SEI 0x2
5099
5100#define SEI_BUFFERING_PERIOD 0
5101#define SEI_PicTiming 1
5102#define SEI_USER_DATA 4
5103#define SEI_RECOVERY_POINT 6
5104
5105/*
5106 *************************************************************************
5107 * Function:Reads bits from the bitstream buffer
5108 * Input:
5109 byte buffer[]
5110 containing sei message data bits
5111 int totbitoffset
5112 bit offset from start of partition
5113 int bytecount
5114 total bytes in bitstream
5115 int numbits
5116 number of bits to read
5117 * Output:
5118 int *info
5119 * Return:
5120 -1: failed
5121 > 0: the count of bit read
5122 * Attention:
5123 *************************************************************************
5124 */
5125
5126static int get_bits(unsigned char buffer[],
5127 int totbitoffset,
5128 int *info,
5129 int bytecount,
5130 int numbits)
5131{
5132 register int inf;
5133 long byteoffset;
5134 int bitoffset;
5135
5136 int bitcounter = numbits;
5137
5138 byteoffset = totbitoffset / 8;
5139 bitoffset = 7 - (totbitoffset % 8);
5140
5141 inf = 0;
5142 while (numbits) {
5143 inf <<= 1;
5144 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5145 numbits--;
5146 bitoffset--;
5147 if (bitoffset < 0) {
5148 byteoffset++;
5149 bitoffset += 8;
5150 if (byteoffset > bytecount)
5151 return -1;
5152 }
5153 }
5154
5155 *info = inf;
5156
5157
5158 return bitcounter;
5159}
5160
5161static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5162 u8 *sei_data_buf,
5163 u8 *sei_data_buf_end)
5164{
5165 int payload_type;
5166 int payload_size;
5167 u8 *p_sei;
5168 int temp = 0;
5169 int bit_offset;
5170 int read_size;
5171 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5172
5173 p_sei = sei_data_buf;
5174 read_size = 0;
5175 payload_type = 0;
5176 do {
5177 if (p_sei >= sei_data_buf_end)
5178 return read_size;
5179
5180 payload_type += *p_sei;
5181 read_size++;
5182 } while (*p_sei++ == 255);
5183
5184
5185 payload_size = 0;
5186 do {
5187 if (p_sei >= sei_data_buf_end)
5188 return read_size;
5189
5190 payload_size += *p_sei;
5191 read_size++;
5192 } while (*p_sei++ == 255);
5193
5194
5195 if (p_sei + payload_size > sei_data_buf_end) {
5196 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5197 "%s: payload_type = %d, payload_size = %d is over\n",
5198 __func__, payload_type, payload_size);
5199 return read_size;
5200 }
5201 bit_offset = 0;
5202
5203 if (payload_size <= 0) {
5204 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5205 "%s warning: this is a null sei message for payload_type = %d\n",
5206 __func__, payload_type);
5207 return read_size;
5208 }
5209 switch (payload_type) {
5210 case SEI_BUFFERING_PERIOD:
5211 break;
5212 case SEI_PicTiming:
5213 if (p_H264_Dpb->vui_status & 0xc) {
5214 int cpb_removal_delay;
5215 int dpb_output_delay;
5216 u32 delay_len;
5217
5218 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5219 cpb_removal_delay
5220 = (delay_len & 0x1F) + 1;
5221 dpb_output_delay
5222 = ((delay_len >> 5) & 0x1F) + 1;
5223
5224 get_bits(p_sei, bit_offset,
5225 &temp, payload_size,
5226 dpb_output_delay+cpb_removal_delay);
5227 bit_offset += dpb_output_delay+cpb_removal_delay;
5228 }
5229 if (p_H264_Dpb->vui_status & 0x10) {
5230 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5231 bit_offset += 4;
5232 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5233 }
5234 break;
5235 case SEI_USER_DATA:
5236 if (enable_itu_t35) {
5237 int i;
5238 int j;
5239 int data_len;
5240 u8 *user_data_buf;
5241
5242 user_data_buf
5243 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5244 /* user data length should be align with 8 bytes,
5245 if not, then padding with zero*/
5246 for (i = 0; i < payload_size; i += 8) {
5247 for (j = 0; j < 8; j++) {
5248 int index;
5249
5250 index = i+7-j;
5251 if (index >= payload_size)
5252 user_data_buf[i+j] = 0;
5253 else
5254 user_data_buf[i+j]
5255 = p_sei[i+7-j];
5256 }
5257 }
5258
5259 data_len = payload_size;
5260 if (payload_size % 8)
5261 data_len = ((payload_size + 8) >> 3) << 3;
5262
5263 hw->sei_itu_data_len += data_len;
5264 /*
5265 dpb_print(DECODE_ID(hw), 0,
5266 "%s: user data, and len = %d:\n",
5267 __func__, hw->sei_itu_data_len);
5268 */
5269 }
5270 break;
5271 case SEI_RECOVERY_POINT:
5272 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5273 break;
5274 }
5275
5276 return read_size + payload_size;
5277}
5278
5279static void parse_sei_data(struct vdec_h264_hw_s *hw,
5280 u8 *sei_data_buf,
5281 int len)
5282{
5283 char *p_sei;
5284 char *p_sei_end;
5285 int parsed_size;
5286 int read_size;
5287
5288
5289 p_sei = sei_data_buf;
5290 p_sei_end = p_sei + len;
5291 parsed_size = 0;
5292 while (parsed_size < len) {
5293 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5294 p_sei += read_size;
5295 parsed_size += read_size;
5296 if (*p_sei == 0x80) {
5297 p_sei++;
5298 parsed_size++;
5299 }
5300 }
5301}
5302
5303static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5304{
5305 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5306 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5307 unsigned mby_mbx = READ_VREG(MBY_MBX);
5308 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5309 unsigned decode_mb_count =
5310 ((mby_mbx & 0xff) * hw->mb_width +
5311 (((mby_mbx >> 8) & 0xff) + 1));
5312 if (mby_mbx == 0)
5313 return;
5314 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5315 mb_total /= 2;
5316 if (error_proc_policy & 0x100) {
5317 if (decode_mb_count < mb_total)
5318 p->data_flag |= ERROR_FLAG;
5319 }
5320
5321 if ((error_proc_policy & 0x200) &&
5322 READ_VREG(ERROR_STATUS_REG) != 0) {
5323 p->data_flag |= ERROR_FLAG;
5324 }
5325
5326 if (p->data_flag & ERROR_FLAG) {
5327 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5328 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5329 __func__,
5330 hw->seq_info2,
5331 mby_mbx,
5332 mb_total,
5333 decode_mb_count,
5334 READ_VREG(ERROR_STATUS_REG)
5335 );
5336
5337 }
5338}
5339
5340static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5341{
5342 int i;
5343 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5344 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5345 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5346 u32 debug_tag;
5347 int ret;
5348
5349 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5350#if 1
5351 unsigned short *p = (unsigned short *)hw->lmem_addr;
5352 dma_sync_single_for_cpu(
5353 amports_get_dma_device(),
5354 hw->lmem_addr_remap,
5355 PAGE_SIZE,
5356 DMA_FROM_DEVICE);
5357 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5358 int ii;
5359 for (ii = 0; ii < 4; ii++) {
5360 p_H264_Dpb->dpb_param.l.data[i+ii] =
5361 p[i+3-ii];
5362 if (dpb_is_debug(DECODE_ID(hw),
5363 RRINT_FLAG_RPM)) {
5364 if (((i + ii) & 0xf) == 0)
5365 dpb_print(DECODE_ID(hw),
5366 0, "%04x:",
5367 i);
5368 dpb_print_cont(DECODE_ID(hw),
5369 0, "%04x ",
5370 p[i+3-ii]);
5371 if (((i + ii + 1) & 0xf) == 0)
5372 dpb_print_cont(
5373 DECODE_ID(hw),
5374 0, "\r\n");
5375 }
5376 }
5377 }
5378
5379 p_H264_Dpb->bitstream_restriction_flag =
5380 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5381 p_H264_Dpb->num_reorder_frames =
5382 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5383 p_H264_Dpb->max_dec_frame_buffering =
5384 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5385
5386 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5387 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5388 p_H264_Dpb->bitstream_restriction_flag,
5389 p_H264_Dpb->num_reorder_frames,
5390 p_H264_Dpb->max_dec_frame_buffering);
5391 hw->bitstream_restriction_flag =
5392 p_H264_Dpb->bitstream_restriction_flag;
5393 hw->num_reorder_frames =
5394 p_H264_Dpb->num_reorder_frames;
5395 hw->max_dec_frame_buffering =
5396 p_H264_Dpb->max_dec_frame_buffering;
5397#endif
5398
5399 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5400 reset_process_time(hw);
5401 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5402 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5403 vdec_schedule_work(&hw->work);
5404 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5405 u16 data_hight;
5406 u16 data_low;
5407 u32 video_signal;
5408
5409 int slice_header_process_status = 0;
5410 int I_flag;
5411 /*unsigned char is_idr;*/
5412 unsigned short *p = (unsigned short *)hw->lmem_addr;
5413 reset_process_time(hw);
5414
5415 if (hw->is_used_v4l) {
5416 struct aml_vcodec_ctx *ctx =
5417 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5418
5419 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5420 //amvdec_stop();
5421 hw->dec_result = DEC_RESULT_DONE;
5422 vdec_schedule_work(&hw->work);
5423 return IRQ_HANDLED;
5424 }
5425 }
5426
5427 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5428 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5429 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5430 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5431 if (input_frame_based(vdec) &&
5432 frmbase_cont_bitlevel2 != 0 &&
5433 READ_VREG(VIFF_BIT_CNT) <
5434 frmbase_cont_bitlevel2 &&
5435 hw->get_data_count >= 0x70000000) {
5436 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5437 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5438 __func__,
5439 READ_VREG(VIFF_BIT_CNT));
5440
5441 goto empty_proc;
5442 }
5443
5444 dma_sync_single_for_cpu(
5445 amports_get_dma_device(),
5446 hw->lmem_addr_remap,
5447 PAGE_SIZE,
5448 DMA_FROM_DEVICE);
5449#if 0
5450 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5451 if (!is_buffer_available(vdec)) {
5452 hw->buffer_empty_flag = 1;
5453 dpb_print(DECODE_ID(hw),
5454 PRINT_FLAG_UCODE_EVT,
5455 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5456 __func__,
5457 kfifo_len(&hw->newframe_q),
5458 have_free_buf_spec(vdec),
5459 p_H264_Dpb->mDPB.init_done,
5460 p_H264_Dpb->mDPB.used_size,
5461 p_H264_Dpb->mDPB.size,
5462 is_there_unused_frame_from_dpb(
5463 &p_H264_Dpb->mDPB));
5464 return IRQ_HANDLED;
5465 }
5466 }
5467
5468 hw->buffer_empty_flag = 0;
5469#endif
5470#ifdef SEND_PARAM_WITH_REG
5471 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5472 unsigned int data32;
5473
5474 do {
5475 data32 = READ_VREG(RPM_CMD_REG);
5476 /* printk("%x\n", data32); */
5477 } while ((data32&0x10000) == 0);
5478 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5479 WRITE_VREG(RPM_CMD_REG, 0);
5480 /* printk("%x:%x\n", i,data32); */
5481 }
5482#else
5483 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5484 int ii;
5485
5486 for (ii = 0; ii < 4; ii++) {
5487 p_H264_Dpb->dpb_param.l.data[i+ii] =
5488 p[i+3-ii];
5489 if (dpb_is_debug(DECODE_ID(hw),
5490 RRINT_FLAG_RPM)) {
5491 if (((i + ii) & 0xf) == 0)
5492 dpb_print(DECODE_ID(hw),
5493 0, "%04x:",
5494 i);
5495 dpb_print_cont(DECODE_ID(hw),
5496 0, "%04x ",
5497 p[i+3-ii]);
5498 if (((i + ii + 1) & 0xf) == 0)
5499 dpb_print_cont(
5500 DECODE_ID(hw),
5501 0, "\r\n");
5502 }
5503 }
5504 }
5505#endif
5506 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5507 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5508
5509 video_signal = (data_hight << 16) | data_low;
5510 hw->video_signal_from_vui =
5511 ((video_signal & 0xffff) << 8) |
5512 ((video_signal & 0xff0000) >> 16) |
5513 ((video_signal & 0x3f000000));
5514
5515
5516 /*dpb_print(DECODE_ID(hw),
5517 0,
5518 "video_signal_from_vui:0x%x, "
5519 "data_low:0x%x, data_hight:0x%x\n",
5520 hw->video_signal_from_vui,
5521 data_low,
5522 data_hight);*/
5523
5524 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5525
5526 if (hw->config_bufmgr_done == 0) {
5527 hw->dec_result = DEC_RESULT_DONE;
5528 vdec_schedule_work(&hw->work);
5529 dpb_print(DECODE_ID(hw),
5530 PRINT_FLAG_UCODE_EVT,
5531 "config_bufmgr not done, discard frame\n");
5532 return IRQ_HANDLED;
5533 } else if ((hw->first_i_policy & 0x3) != 0) {
5534 unsigned char is_i_slice =
5535 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5536 == I_Slice)
5537 ? 1 : 0;
5538 unsigned char is_idr =
5539 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5540 == 5);
5541 if ((hw->first_i_policy & 0x3) == 0x3)
5542 is_i_slice = is_idr;
5543 if (!is_i_slice) {
5544 if (hw->has_i_frame == 0) {
5545 amvdec_stop();
5546 vdec->mc_loaded = 0;
5547 hw->dec_result = DEC_RESULT_DONE;
5548 vdec_schedule_work(&hw->work);
5549 dpb_print(DECODE_ID(hw),
5550 PRINT_FLAG_UCODE_EVT,
5551 "has_i_frame is 0, discard none I(DR) frame\n");
5552 return IRQ_HANDLED;
5553 }
5554 } else {
5555 if (hw->skip_frame_count < 0 || is_idr) {
5556 /* second I */
5557 hw->dec_flag &= (~NODISP_FLAG);
5558 hw->skip_frame_count = 0;
5559 }
5560 if (hw->has_i_frame == 0 &&
5561 (!is_idr)) {
5562 int skip_count =
5563 (hw->first_i_policy >> 8) & 0xff;
5564 /* first I (not IDR) */
5565 if ((hw->first_i_policy & 0x3) == 2)
5566 hw->skip_frame_count =
5567 -1 - skip_count;
5568 else
5569 hw->skip_frame_count =
5570 skip_count;
5571 if (hw->skip_frame_count != 0)
5572 hw->dec_flag |= NODISP_FLAG;
5573 }
5574 }
5575 }
5576 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5577 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5578 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5579 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5580 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5581 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5582 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5583 ? I_FLAG : 0;
5584
5585 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5586 flush_dpb(p_H264_Dpb);
5587
5588 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5589 (p_H264_Dpb->mSlice.structure == FRAME)) {
5590 hw->data_flag = NULL_FLAG;
5591 goto pic_done_proc;
5592 }
5593
5594 slice_header_process_status =
5595 h264_slice_header_process(p_H264_Dpb);
5596 if (hw->mmu_enable)
5597 hevc_sao_set_slice_type(hw,
5598 slice_header_process_status,
5599 hw->dpb.mSlice.idr_flag);
5600 vui_config(hw);
5601
5602 if (p_H264_Dpb->mVideo.dec_picture) {
5603 int cfg_ret = 0;
5604 bool field_pic_flag = false;
5605
5606 if (slice_header_process_status == 1) {
5607 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5608 field_pic_flag =
5609 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5610 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5611 true : false;
5612 }
5613
5614 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5615 (((unsigned long)(hw->vh264_amstream_dec_info
5616 .param)) & 0x8))) {
5617 p_H264_Dpb->fast_output_enable =
5618 H264_OUTPUT_MODE_FAST;
5619 }
5620 else
5621 p_H264_Dpb->fast_output_enable
5622 = fast_output_enable;
5623 hw->data_flag = I_flag;
5624 if ((p_H264_Dpb->
5625 dpb_param.dpb.NAL_info_mmco & 0x1f)
5626 == 5)
5627 hw->data_flag |= IDR_FLAG;
5628 dpb_print(DECODE_ID(hw),
5629 PRINT_FLAG_VDEC_STATUS,
5630 "==================> frame count %d to skip %d\n",
5631 hw->decode_pic_count+1,
5632 hw->skip_frame_count);
5633 } else if (error_proc_policy & 0x100){
5634 struct StorablePicture *p =
5635 p_H264_Dpb->mVideo.dec_picture;
5636 unsigned mby_mbx = READ_VREG(MBY_MBX);
5637 unsigned decode_mb_count =
5638 ((mby_mbx & 0xff) * hw->mb_width +
5639 (((mby_mbx >> 8) & 0xff) + 1));
5640 if (decode_mb_count <
5641 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5642 (1 + p->mb_aff_frame_flag))) {
5643 dpb_print(DECODE_ID(hw),
5644 PRINT_FLAG_VDEC_STATUS,
5645 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5646 p_H264_Dpb->dpb_param.l.
5647 data[FIRST_MB_IN_SLICE],
5648 READ_VREG(MBY_MBX),
5649 decode_mb_count);
5650 p->data_flag |= ERROR_FLAG;
5651 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5652 p->data_flag |= ERROR_FLAG;
5653 goto pic_done_proc;
5654 }
5655 }
5656
5657 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5658 hw->new_iframe_flag = 1;
5659 }
5660 if (hw->new_iframe_flag) {
5661 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5662 hw->new_iframe_flag = 0;
5663 hw->ref_err_flush_dpb_flag = 1;
5664 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5665 hw->new_iframe_flag = 0;
5666 hw->ref_err_flush_dpb_flag = 0;
5667 }
5668 }
5669
5670 if (error_proc_policy & 0x400) {
5671 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5672 if (ret != 0) {
5673 hw->reflist_error_count ++;
5674 dpb_print(DECODE_ID(hw), 0,
5675 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5676 ret,
5677 hw->decode_pic_count+1,
5678 hw->skip_frame_count,
5679 hw->reflist_error_count);
5680
5681 if (hw->ref_err_flush_dpb_flag) {
5682 flush_dpb(p_H264_Dpb);
5683 p_H264_Dpb->colocated_buf_map = 0;
5684 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5685 p_H264_Dpb->colocated_buf_map |= 1 <<
5686 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5687 }
5688 }
5689
5690 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5691 if (((error_proc_policy & 0x80)
5692 && ((hw->dec_flag &
5693 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5694 hw->reset_bufmgr_flag = 1;
5695 hw->reflist_error_count =0;
5696 amvdec_stop();
5697 vdec->mc_loaded = 0;
5698 hw->dec_result = DEC_RESULT_DONE;
5699 vdec_schedule_work(&hw->work);
5700 return IRQ_HANDLED;
5701 }
5702 } else
5703 hw->reflist_error_count = 0;
5704 }
5705 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5706 && p_H264_Dpb->dpb_error_flag != 0) {
5707 dpb_print(DECODE_ID(hw), 0,
5708 "dpb error %d\n",
5709 p_H264_Dpb->dpb_error_flag);
5710 hw->data_flag |= ERROR_FLAG;
5711 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5712 if ((error_proc_policy & 0x80) &&
5713 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5714 hw->reset_bufmgr_flag = 1;
5715 amvdec_stop();
5716 vdec->mc_loaded = 0;
5717 hw->dec_result = DEC_RESULT_DONE;
5718 vdec_schedule_work(&hw->work);
5719 return IRQ_HANDLED;
5720 }
5721 }
5722
5723 cfg_ret = config_decode_buf(hw,
5724 p_H264_Dpb->mVideo.dec_picture);
5725 if (cfg_ret < 0) {
5726 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5727 "config_decode_buf fail (%d)\n",
5728 cfg_ret);
5729 if (error_proc_policy & 0x2) {
5730 release_cur_decoding_buf(hw);
5731 /*hw->data_flag |= ERROR_FLAG;*/
5732 hw->reset_bufmgr_flag = 1;
5733 hw->dec_result = DEC_RESULT_DONE;
5734 vdec_schedule_work(&hw->work);
5735 return IRQ_HANDLED;
5736 } else
5737 hw->data_flag |= ERROR_FLAG;
5738 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5739 }
5740 }
5741
5742 if (slice_header_process_status == 1)
5743 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5744 else
5745 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5746 hw->last_mby_mbx = 0;
5747 hw->last_vld_level = 0;
5748 start_process_time(hw);
5749 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5750 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5751pic_done_proc:
5752 reset_process_time(hw);
5753
5754 if (input_frame_based(vdec) &&
5755 (!(hw->i_only & 0x2)) &&
5756 frmbase_cont_bitlevel != 0 &&
5757 READ_VREG(VIFF_BIT_CNT) >
5758 frmbase_cont_bitlevel) {
5759 /*handle the case: multi pictures in one packet*/
5760 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5761 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5762 __func__,
5763 hw->decode_pic_count,
5764 READ_VREG(VIFF_BIT_CNT));
5765 hw->frmbase_cont_flag = 1;
5766 } else
5767 hw->frmbase_cont_flag = 0;
5768
5769 if (p_H264_Dpb->mVideo.dec_picture) {
5770 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5771#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5772 DEL_EXIST(hw,
5773 p_H264_Dpb->mVideo.dec_picture) = 0;
5774 if (vdec->master) {
5775 struct vdec_h264_hw_s *hw_ba =
5776 (struct vdec_h264_hw_s *)
5777 vdec->master->private;
5778 if (hw_ba->last_dec_picture)
5779 DEL_EXIST(hw_ba,
5780 hw_ba->last_dec_picture)
5781 = 1;
5782 }
5783#endif
5784 mutex_lock(&hw->chunks_mutex);
5785 if (hw->chunk) {
5786 p_H264_Dpb->mVideo.dec_picture->pts =
5787 hw->chunk->pts;
5788 p_H264_Dpb->mVideo.dec_picture->pts64 =
5789 hw->chunk->pts64;
5790 p_H264_Dpb->mVideo.dec_picture->timestamp =
5791 hw->chunk->timestamp;
5792#ifdef MH264_USERDATA_ENABLE
5793 vmh264_udc_fill_vpts(hw,
5794 p_H264_Dpb->mSlice.slice_type,
5795 hw->chunk->pts, 1);
5796#endif
5797
5798#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5799 } else if (vdec->master) {
5800 /*dv enhance layer,
5801 do not checkout pts*/
5802 struct StorablePicture *pic =
5803 p_H264_Dpb->mVideo.dec_picture;
5804 pic->pts = 0;
5805 pic->pts64 = 0;
5806#endif
5807 } else {
5808 struct StorablePicture *pic =
5809 p_H264_Dpb->mVideo.dec_picture;
5810 u32 offset = pic->offset_delimiter;
5811 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5812 offset, &pic->pts, 0, &pic->pts64)) {
5813 pic->pts = 0;
5814 pic->pts64 = 0;
5815#ifdef MH264_USERDATA_ENABLE
5816 vmh264_udc_fill_vpts(hw,
5817 p_H264_Dpb->mSlice.slice_type,
5818 pic->pts, 0);
5819#endif
5820 } else {
5821#ifdef MH264_USERDATA_ENABLE
5822 vmh264_udc_fill_vpts(hw,
5823 p_H264_Dpb->mSlice.slice_type,
5824 pic->pts, 1);
5825#endif
5826 }
5827
5828 }
5829 mutex_unlock(&hw->chunks_mutex);
5830
5831 check_decoded_pic_error(hw);
5832#ifdef ERROR_HANDLE_TEST
5833 if ((hw->data_flag & ERROR_FLAG)
5834 && (error_proc_policy & 0x80)) {
5835 release_cur_decoding_buf(hw);
5836 h264_clear_dpb(hw);
5837 hw->dec_flag = 0;
5838 hw->data_flag = 0;
5839 hw->skip_frame_count = 0;
5840 hw->has_i_frame = 0;
5841 hw->no_error_count = 0xfff;
5842 hw->no_error_i_count = 0xf;
5843 } else
5844#endif
5845 ret = store_picture_in_dpb(p_H264_Dpb,
5846 p_H264_Dpb->mVideo.dec_picture,
5847 hw->data_flag | hw->dec_flag |
5848 p_H264_Dpb->mVideo.dec_picture->data_flag);
5849
5850
5851
5852 if (ret == -1) {
5853 release_cur_decoding_buf(hw);
5854 bufmgr_force_recover(p_H264_Dpb);
5855 } else {
5856 if (hw->data_flag & ERROR_FLAG) {
5857 hw->no_error_count = 0;
5858 hw->no_error_i_count = 0;
5859 } else {
5860 hw->no_error_count++;
5861 if (hw->data_flag & I_FLAG)
5862 hw->no_error_i_count++;
5863 }
5864 if (hw->mmu_enable)
5865 hevc_set_unused_4k_buff_idx(hw,
5866 p_H264_Dpb->mVideo.
5867 dec_picture->buf_spec_num);
5868 bufmgr_post(p_H264_Dpb);
5869 hw->last_dec_picture =
5870 p_H264_Dpb->mVideo.dec_picture;
5871 p_H264_Dpb->mVideo.dec_picture = NULL;
5872 /* dump_dpb(&p_H264_Dpb->mDPB); */
5873 hw->has_i_frame = 1;
5874 if (hw->mmu_enable)
5875 hevc_set_frame_done(hw);
5876 hw->decode_pic_count++;
5877 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5878 if (hw->skip_frame_count > 0) {
5879 /*skip n frame after first I */
5880 hw->skip_frame_count--;
5881 if (hw->skip_frame_count == 0)
5882 hw->dec_flag &= (~NODISP_FLAG);
5883 } else if (hw->skip_frame_count < -1) {
5884 /*skip n frame after first I until second I */
5885 hw->skip_frame_count++;
5886 if (hw->skip_frame_count == -1)
5887 hw->dec_flag &= (~NODISP_FLAG);
5888 }
5889 }
5890 }
5891 if (hw->frmbase_cont_flag) {
5892 /*do not DEC_RESULT_GET_DATA*/
5893 hw->get_data_count = 0x7fffffff;
5894 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5895 decode_frame_count[DECODE_ID(hw)]++;
5896 start_process_time(hw);
5897 return IRQ_HANDLED;
5898 }
5899 amvdec_stop();
5900 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5901 "%s %s decode slice count %d\n",
5902 __func__,
5903 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5904 "H264_PIC_DATA_DONE" :
5905 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5906 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5907 hw->decode_pic_count);
5908 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5909 hw->dec_result = DEC_RESULT_DONE;
5910#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5911 if (vdec->slave &&
5912 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5913 struct vdec_h264_hw_s *hw_el =
5914 (struct vdec_h264_hw_s *)(vdec->slave->private);
5915 hw_el->got_valid_nal = 0;
5916 hw->switch_dvlayer_flag = 1;
5917 } else if (vdec->master &&
5918 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5919 struct vdec_h264_hw_s *hw_bl =
5920 (struct vdec_h264_hw_s *)(vdec->master->private);
5921 hw_bl->got_valid_nal = 0;
5922 hw->switch_dvlayer_flag = 1;
5923 } else {
5924 hw->switch_dvlayer_flag = 0;
5925 hw->got_valid_nal = 1;
5926 }
5927#endif
5928
5929 hw->dec_result = DEC_RESULT_DONE;
5930 vdec_schedule_work(&hw->work);
5931
5932#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5933 } else if (
5934 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5935 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5936 goto pic_done_proc;
5937#endif
5938 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5939 reset_process_time(hw);
5940 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5941 dma_sync_single_for_cpu(
5942 amports_get_dma_device(),
5943 hw->aux_phy_addr,
5944 hw->prefix_aux_size + hw->suffix_aux_size,
5945 DMA_FROM_DEVICE);
5946 if (dpb_is_debug(DECODE_ID(hw),
5947 PRINT_FLAG_DPB_DETAIL))
5948 dump_aux_buf(hw);
5949#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5950 if (vdec->dolby_meta_with_el || vdec->slave) {
5951 if (hw->last_dec_picture)
5952 set_aux_data(hw, hw->last_dec_picture,
5953 0, 0, NULL);
5954 } else {
5955 if (vdec->master) {
5956 struct vdec_h264_hw_s *hw_bl =
5957 (struct vdec_h264_hw_s *)
5958 (vdec->master->private);
5959 if (hw_bl->last_dec_picture != NULL) {
5960 set_aux_data(hw_bl,
5961 hw_bl->last_dec_picture,
5962 0, 1, hw);
5963 }
5964 set_aux_data(hw,
5965 hw->last_dec_picture,
5966 0, 2, NULL);
5967 }
5968 }
5969#else
5970 if (hw->last_dec_picture)
5971 set_aux_data(hw,
5972 hw->last_dec_picture, 0, 0, NULL);
5973#endif
5974 }
5975#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5976 hw->switch_dvlayer_flag = 0;
5977 hw->got_valid_nal = 1;
5978#endif
5979 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5980 "%s H264_AUX_DATA_READY\n", __func__);
5981 hw->dec_result = DEC_RESULT_DONE;
5982 vdec_schedule_work(&hw->work);
5983 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5984 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5985 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5986 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5987empty_proc:
5988 reset_process_time(hw);
5989 if (!hw->frmbase_cont_flag)
5990 release_cur_decoding_buf(hw);
5991
5992 if (input_frame_based(vdec) ||
5993 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
5994 if (h264_debug_flag &
5995 DISABLE_ERROR_HANDLE) {
5996 dpb_print(DECODE_ID(hw),
5997 PRINT_FLAG_ERROR,
5998 "%s decoding error, level 0x%x\n",
5999 __func__,
6000 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6001 goto send_again;
6002 }
6003 amvdec_stop();
6004 vdec->mc_loaded = 0;
6005 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6006 "%s %s\n", __func__,
6007 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6008 "H264_SEARCH_BUFEMPTY" :
6009 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6010 "H264_DECODE_BUFEMPTY" :
6011 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6012 "H264_DECODE_TIMEOUT" :
6013 "OTHER");
6014 hw->dec_result = DEC_RESULT_DONE;
6015
6016 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6017 hw->search_dataempty_num++;
6018 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6019 hw->decode_timeout_num++;
6020 if (error_proc_policy & 0x4000) {
6021 hw->data_flag |= ERROR_FLAG;
6022 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6023 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6024 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6025 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6026 dpb_print(DECODE_ID(hw),
6027 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6028 p_H264_Dpb->last_dpb_status, __func__);
6029 hw->reset_bufmgr_flag = 1;
6030 }
6031 }
6032 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6033 hw->decode_dataempty_num++;
6034 if (!hw->frmbase_cont_flag)
6035 hw->data_flag |= ERROR_FLAG;
6036
6037 vdec_schedule_work(&hw->work);
6038 } else {
6039 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6040 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6041 "%s DEC_RESULT_AGAIN\n", __func__);
6042send_again:
6043 hw->dec_result = DEC_RESULT_AGAIN;
6044 vdec_schedule_work(&hw->work);
6045 }
6046 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6047 reset_process_time(hw);
6048 if (input_frame_based(vdec)) {
6049 dpb_print(DECODE_ID(hw),
6050 PRINT_FLAG_VDEC_STATUS,
6051 "%s H264_DATA_REQUEST (%d)\n",
6052 __func__, hw->get_data_count);
6053 hw->dec_result = DEC_RESULT_GET_DATA;
6054 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6055 hw->get_data_start_time = jiffies;
6056 hw->get_data_count++;
6057 if (hw->get_data_count >= frame_max_data_packet)
6058 goto empty_proc;
6059 vdec_schedule_work(&hw->work);
6060 } else
6061 goto empty_proc;
6062 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6063 dpb_print(DECODE_ID(hw), 0,
6064 "vmh264 decode oversize !!\n");
6065 release_cur_decoding_buf(hw);
6066 hw->data_flag |= ERROR_FLAG;
6067 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6068 reset_process_time(hw);
6069 hw->dec_result = DEC_RESULT_DONE;
6070 vdec_schedule_work(&hw->work);
6071 return IRQ_HANDLED;
6072 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6073 int aux_data_len;
6074 aux_data_len =
6075 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6076
6077 if (aux_data_len > SEI_DATA_SIZE) {
6078 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6079 "sei data size more than 4K: %d, discarded it\n",
6080 hw->sei_itu_data_len);
6081 hw->sei_itu_data_len = 0;
6082 }
6083
6084 if (aux_data_len != 0) {
6085 u8 *trans_data_buf;
6086 u8 *sei_data_buf;
6087 u8 swap_byte;
6088
6089 dma_sync_single_for_cpu(
6090 amports_get_dma_device(),
6091 hw->aux_phy_addr,
6092 hw->prefix_aux_size + hw->suffix_aux_size,
6093 DMA_FROM_DEVICE);
6094#if 0
6095 dump_aux_buf(hw);
6096#endif
6097 trans_data_buf = (u8 *)hw->aux_addr;
6098
6099 if (trans_data_buf[7] == AUX_TAG_SEI) {
6100 int left_len;
6101
6102 sei_data_buf = (u8 *)hw->sei_data_buf
6103 + hw->sei_data_len;
6104 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6105 if (aux_data_len/2 <= left_len) {
6106 for (i = 0; i < aux_data_len/2; i++)
6107 sei_data_buf[i]
6108 = trans_data_buf[i*2];
6109
6110 aux_data_len = aux_data_len / 2;
6111 for (i = 0; i < aux_data_len; i = i+4) {
6112 swap_byte = sei_data_buf[i];
6113 sei_data_buf[i]
6114 = sei_data_buf[i+3];
6115 sei_data_buf[i+3] = swap_byte;
6116
6117 swap_byte = sei_data_buf[i+1];
6118 sei_data_buf[i+1]
6119 = sei_data_buf[i+2];
6120 sei_data_buf[i+2] = swap_byte;
6121 }
6122
6123 for (i = aux_data_len-1; i >= 0; i--)
6124 if (sei_data_buf[i] != 0)
6125 break;
6126
6127 hw->sei_data_len += i+1;
6128 } else
6129 dpb_print(DECODE_ID(hw),
6130 PRINT_FLAG_ERROR,
6131 "sei data size %d and more than left space: %d, discarded it\n",
6132 hw->sei_itu_data_len,
6133 left_len);
6134 }
6135 }
6136 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6137
6138 return IRQ_HANDLED;
6139 }
6140
6141
6142 /* ucode debug */
6143 debug_tag = READ_VREG(DEBUG_REG1);
6144 if (debug_tag & 0x10000) {
6145 unsigned short *p = (unsigned short *)hw->lmem_addr;
6146
6147 dma_sync_single_for_cpu(
6148 amports_get_dma_device(),
6149 hw->lmem_addr_remap,
6150 PAGE_SIZE,
6151 DMA_FROM_DEVICE);
6152
6153 dpb_print(DECODE_ID(hw), 0,
6154 "LMEM<tag %x>:\n", debug_tag);
6155 for (i = 0; i < 0x400; i += 4) {
6156 int ii;
6157 if ((i & 0xf) == 0)
6158 dpb_print_cont(DECODE_ID(hw), 0,
6159 "%03x: ", i);
6160 for (ii = 0; ii < 4; ii++)
6161 dpb_print_cont(DECODE_ID(hw), 0,
6162 "%04x ", p[i+3-ii]);
6163 if (((i+ii) & 0xf) == 0)
6164 dpb_print_cont(DECODE_ID(hw), 0,
6165 "\n");
6166 }
6167 if (((udebug_pause_pos & 0xffff)
6168 == (debug_tag & 0xffff)) &&
6169 (udebug_pause_decode_idx == 0 ||
6170 udebug_pause_decode_idx ==
6171 hw->decode_pic_count) &&
6172 (udebug_pause_val == 0 ||
6173 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6174 udebug_pause_pos &= 0xffff;
6175 hw->ucode_pause_pos = udebug_pause_pos;
6176 }
6177 else if (debug_tag & 0x20000)
6178 hw->ucode_pause_pos = 0xffffffff;
6179 if (hw->ucode_pause_pos)
6180 reset_process_time(hw);
6181 else
6182 WRITE_VREG(DEBUG_REG1, 0);
6183 } else if (debug_tag != 0) {
6184 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6185 "dbg%x: %x\n", debug_tag,
6186 READ_VREG(DEBUG_REG2));
6187 if (((udebug_pause_pos & 0xffff)
6188 == (debug_tag & 0xffff)) &&
6189 (udebug_pause_decode_idx == 0 ||
6190 udebug_pause_decode_idx ==
6191 hw->decode_pic_count) &&
6192 (udebug_pause_val == 0 ||
6193 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6194 udebug_pause_pos &= 0xffff;
6195 hw->ucode_pause_pos = udebug_pause_pos;
6196 }
6197 if (hw->ucode_pause_pos)
6198 reset_process_time(hw);
6199 else
6200 WRITE_VREG(DEBUG_REG1, 0);
6201 }
6202 /**/
6203 return IRQ_HANDLED;
6204}
6205
6206static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6207{
6208 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6209 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6210
6211
6212 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6213
6214 if (!hw)
6215 return IRQ_HANDLED;
6216
6217 if (hw->eos)
6218 return IRQ_HANDLED;
6219
6220 p_H264_Dpb->vdec = vdec;
6221 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6222
6223 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6224 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6225 __func__,
6226 p_H264_Dpb->dec_dpb_status,
6227 READ_VREG(ERROR_STATUS_REG),
6228 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6229 READ_VREG(VLD_MEM_VIFIFO_WP),
6230 READ_VREG(VLD_MEM_VIFIFO_RP),
6231 READ_VREG(VIFF_BIT_CNT),
6232 READ_VREG(MBY_MBX));
6233
6234 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6235 if (hw->mmu_enable)
6236 hevc_sao_wait_done(hw);
6237 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6238 return IRQ_HANDLED;
6239 }
6240 return IRQ_WAKE_THREAD;
6241
6242}
6243
6244static void timeout_process(struct vdec_h264_hw_s *hw)
6245{
6246 struct vdec_s *vdec = hw_to_vdec(hw);
6247 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6248
6249 /*
6250 * In this very timeout point,the vh264_work arrives,
6251 * let it to handle the scenario.
6252 */
6253 if (work_pending(&hw->work))
6254 return;
6255
6256 hw->timeout_num++;
6257 amvdec_stop();
6258 vdec->mc_loaded = 0;
6259 if (hw->mmu_enable) {
6260 hevc_set_frame_done(hw);
6261 hevc_sao_wait_done(hw);
6262 }
6263 if (!hw->i_only && (error_proc_policy & 0x2))
6264 flush_dpb(p_H264_Dpb);
6265 dpb_print(DECODE_ID(hw),
6266 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6267 release_cur_decoding_buf(hw);
6268 hw->dec_result = DEC_RESULT_DONE;
6269 hw->data_flag |= ERROR_FLAG;
6270
6271 if (work_pending(&hw->work))
6272 return;
6273 vdec_schedule_work(&hw->timeout_work);
6274}
6275
6276static void dump_bufspec(struct vdec_h264_hw_s *hw,
6277 const char *caller)
6278{
6279 int i;
6280 dpb_print(DECODE_ID(hw), 0,
6281 "%s in %s:\n", __func__, caller);
6282 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6283 if (hw->buffer_spec[i].used == -1)
6284 continue;
6285 dpb_print(DECODE_ID(hw), 0,
6286 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6287 i, hw->buffer_spec[i].used,
6288 hw->buffer_spec[i].buf_adr,
6289 hw->buffer_spec[i].canvas_pos,
6290 hw->buffer_spec[i].vf_ref
6291 );
6292#ifdef CONFIG_AM_VDEC_DV
6293 dpb_print_cont(DECODE_ID(hw), 0,
6294 "dv_el_exist %d",
6295 hw->buffer_spec[i].dv_enhance_exist
6296 );
6297#endif
6298 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6299 }
6300
6301}
6302
6303static void vmh264_dump_state(struct vdec_s *vdec)
6304{
6305 struct vdec_h264_hw_s *hw =
6306 (struct vdec_h264_hw_s *)(vdec->private);
6307 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6308 dpb_print(DECODE_ID(hw), 0,
6309 "====== %s\n", __func__);
6310 dpb_print(DECODE_ID(hw), 0,
6311 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6312 hw->frame_width,
6313 hw->frame_height,
6314 hw->dpb.reorder_pic_num,
6315 hw->dpb.mDPB.size,
6316 hw->max_reference_size,
6317 hw->i_only,
6318 hw->send_error_frame_flag
6319 );
6320
6321 dpb_print(DECODE_ID(hw), 0,
6322 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6323 input_frame_based(vdec),
6324 hw->eos,
6325 hw->stat,
6326 hw->dec_result,
6327 decode_frame_count[DECODE_ID(hw)],
6328 display_frame_count[DECODE_ID(hw)],
6329 run_count[DECODE_ID(hw)],
6330 not_run_ready[DECODE_ID(hw)],
6331 input_empty[DECODE_ID(hw)],
6332 hw->reset_bufmgr_count
6333 );
6334
6335 if (vf_get_receiver(vdec->vf_provider_name)) {
6336 enum receviver_start_e state =
6337 vf_notify_receiver(vdec->vf_provider_name,
6338 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6339 NULL);
6340 dpb_print(DECODE_ID(hw), 0,
6341 "\nreceiver(%s) state %d\n",
6342 vdec->vf_provider_name,
6343 state);
6344 }
6345
6346 dpb_print(DECODE_ID(hw), 0,
6347 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x wait_reset_done_flag %d\n",
6348 __func__,
6349 kfifo_len(&hw->newframe_q),
6350 VF_POOL_SIZE,
6351 kfifo_len(&hw->display_q),
6352 VF_POOL_SIZE,
6353 hw->vf_pre_count,
6354 hw->vf_get_count,
6355 hw->vf_put_count,
6356 have_free_buf_spec(vdec),
6357 p_H264_Dpb->mDPB.init_done,
6358 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6359 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6360 p_H264_Dpb->fast_output_enable,
6361 hw->wait_reset_done_flag
6362 );
6363
6364 dump_dpb(&p_H264_Dpb->mDPB, 1);
6365 dump_pic(p_H264_Dpb);
6366 dump_bufspec(hw, __func__);
6367
6368 dpb_print(DECODE_ID(hw), 0,
6369 "DPB_STATUS_REG=0x%x\n",
6370 READ_VREG(DPB_STATUS_REG));
6371 dpb_print(DECODE_ID(hw), 0,
6372 "MPC_E=0x%x\n",
6373 READ_VREG(MPC_E));
6374 dpb_print(DECODE_ID(hw), 0,
6375 "H264_DECODE_MODE=0x%x\n",
6376 READ_VREG(H264_DECODE_MODE));
6377 dpb_print(DECODE_ID(hw), 0,
6378 "MBY_MBX=0x%x\n",
6379 READ_VREG(MBY_MBX));
6380 dpb_print(DECODE_ID(hw), 0,
6381 "H264_DECODE_SIZE=0x%x\n",
6382 READ_VREG(H264_DECODE_SIZE));
6383 dpb_print(DECODE_ID(hw), 0,
6384 "VIFF_BIT_CNT=0x%x\n",
6385 READ_VREG(VIFF_BIT_CNT));
6386 dpb_print(DECODE_ID(hw), 0,
6387 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6388 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6389 dpb_print(DECODE_ID(hw), 0,
6390 "VLD_MEM_VIFIFO_WP=0x%x\n",
6391 READ_VREG(VLD_MEM_VIFIFO_WP));
6392 dpb_print(DECODE_ID(hw), 0,
6393 "VLD_MEM_VIFIFO_RP=0x%x\n",
6394 READ_VREG(VLD_MEM_VIFIFO_RP));
6395 dpb_print(DECODE_ID(hw), 0,
6396 "PARSER_VIDEO_RP=0x%x\n",
6397 READ_PARSER_REG(PARSER_VIDEO_RP));
6398 dpb_print(DECODE_ID(hw), 0,
6399 "PARSER_VIDEO_WP=0x%x\n",
6400 READ_PARSER_REG(PARSER_VIDEO_WP));
6401
6402 if (input_frame_based(vdec) &&
6403 dpb_is_debug(DECODE_ID(hw),
6404 PRINT_FRAMEBASE_DATA)
6405 ) {
6406 int jj;
6407 if (hw->chunk && hw->chunk->block &&
6408 hw->chunk->size > 0) {
6409 u8 *data = NULL;
6410
6411 if (!hw->chunk->block->is_mapped)
6412 data = codec_mm_vmap(hw->chunk->block->start +
6413 hw->chunk->offset, hw->chunk->size);
6414 else
6415 data = ((u8 *)hw->chunk->block->start_virt)
6416 + hw->chunk->offset;
6417
6418 dpb_print(DECODE_ID(hw), 0,
6419 "frame data size 0x%x\n",
6420 hw->chunk->size);
6421 for (jj = 0; jj < hw->chunk->size; jj++) {
6422 if ((jj & 0xf) == 0)
6423 dpb_print(DECODE_ID(hw),
6424 PRINT_FRAMEBASE_DATA,
6425 "%06x:", jj);
6426 dpb_print_cont(DECODE_ID(hw),
6427 PRINT_FRAMEBASE_DATA,
6428 "%02x ", data[jj]);
6429 if (((jj + 1) & 0xf) == 0)
6430 dpb_print_cont(DECODE_ID(hw),
6431 PRINT_FRAMEBASE_DATA,
6432 "\n");
6433 }
6434
6435 if (!hw->chunk->block->is_mapped)
6436 codec_mm_unmap_phyaddr(data);
6437 }
6438 }
6439}
6440
6441
6442static void check_timer_func(unsigned long arg)
6443{
6444 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6445 struct vdec_s *vdec = hw_to_vdec(hw);
6446 int error_skip_frame_count = error_skip_count & 0xfff;
6447 unsigned int timeout_val = decode_timeout_val;
6448 if (timeout_val != 0 &&
6449 hw->no_error_count < error_skip_frame_count)
6450 timeout_val = errordata_timeout_val;
6451 if ((h264_debug_cmd & 0x100) != 0 &&
6452 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6453 hw->dec_result = DEC_RESULT_DONE;
6454 vdec_schedule_work(&hw->work);
6455 pr_info("vdec %d is forced to be disconnected\n",
6456 h264_debug_cmd & 0xff);
6457 h264_debug_cmd = 0;
6458 return;
6459 }
6460 if ((h264_debug_cmd & 0x200) != 0 &&
6461 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6462 pr_debug("vdec %d is forced to reset bufmgr\n",
6463 h264_debug_cmd & 0xff);
6464 hw->reset_bufmgr_flag = 1;
6465 h264_debug_cmd = 0;
6466 return;
6467 }
6468
6469 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6470 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6471 vdec_schedule_work(&hw->work);
6472 pr_debug("vdec requested to be disconnected\n");
6473 return;
6474 }
6475
6476 if (radr != 0) {
6477 if (rval != 0) {
6478 WRITE_VREG(radr, rval);
6479 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6480 } else
6481 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6482 rval = 0;
6483 radr = 0;
6484 }
6485
6486 if ((input_frame_based(vdec) ||
6487 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6488 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6489 (timeout_val > 0) &&
6490 (hw->start_process_time > 0) &&
6491 ((1000 * (jiffies - hw->start_process_time) / HZ)
6492 > timeout_val)
6493 ) {
6494 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6495 u32 mby_mbx = READ_VREG(MBY_MBX);
6496 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6497 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6498 if (hw->last_mby_mbx == mby_mbx) {
6499 if (hw->decode_timeout_count > 0)
6500 hw->decode_timeout_count--;
6501 if (hw->decode_timeout_count == 0)
6502 {
6503 reset_process_time(hw);
6504 timeout_process(hw);
6505 }
6506 } else
6507 start_process_time(hw);
6508 } else if (is_in_parsing_state(dpb_status)) {
6509 if (hw->last_vld_level ==
6510 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6511 if (hw->decode_timeout_count > 0)
6512 hw->decode_timeout_count--;
6513 if (hw->decode_timeout_count == 0)
6514 {
6515 reset_process_time(hw);
6516 timeout_process(hw);
6517 }
6518 }
6519 }
6520 hw->last_vld_level =
6521 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6522 hw->last_mby_mbx = mby_mbx;
6523 }
6524
6525 if ((hw->ucode_pause_pos != 0) &&
6526 (hw->ucode_pause_pos != 0xffffffff) &&
6527 udebug_pause_pos != hw->ucode_pause_pos) {
6528 hw->ucode_pause_pos = 0;
6529 WRITE_VREG(DEBUG_REG1, 0);
6530 }
6531
6532 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6533}
6534
6535static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6536{
6537 u32 ar;
6538 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6539
6540 if (!hw)
6541 return -1;
6542
6543 vstatus->frame_width = hw->frame_width;
6544 vstatus->frame_height = hw->frame_height;
6545 if (hw->frame_dur != 0)
6546 vstatus->frame_rate = 96000 / hw->frame_dur;
6547 else
6548 vstatus->frame_rate = -1;
6549 vstatus->error_count = 0;
6550 vstatus->status = hw->stat;
6551 if (hw->h264_ar == 0x3ff)
6552 hw->h264_ar = (0x100 *
6553 hw->frame_height * hw->height_aspect_ratio) /
6554 (hw->frame_width * hw->width_aspect_ratio);
6555 ar = min_t(u32,
6556 hw->h264_ar,
6557 DISP_RATIO_ASPECT_RATIO_MAX);
6558 vstatus->ratio_control =
6559 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6560
6561 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6562 "%s-%02d", DRIVER_NAME, hw->id);
6563
6564 return 0;
6565}
6566
6567static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6568{
6569 int i, j;
6570 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6571
6572 /* if (hw->init_flag == 0) { */
6573 if (h264_debug_flag & 0x40000000) {
6574 /* if (1) */
6575 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6576 "%s, reset register\n", __func__);
6577
6578 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6579 ;
6580 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6581 ; /* reg address is 0x350 */
6582
6583#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6584 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6585 WRITE_VREG(DOS_SW_RESET0, 0);
6586
6587 READ_VREG(DOS_SW_RESET0);
6588 READ_VREG(DOS_SW_RESET0);
6589 READ_VREG(DOS_SW_RESET0);
6590
6591 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6592 WRITE_VREG(DOS_SW_RESET0, 0);
6593
6594 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6595 WRITE_VREG(DOS_SW_RESET0, 0);
6596
6597 READ_VREG(DOS_SW_RESET0);
6598 READ_VREG(DOS_SW_RESET0);
6599 READ_VREG(DOS_SW_RESET0);
6600
6601#else
6602 WRITE_RESET_REG(RESET0_REGISTER,
6603 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6604 READ_RESET_REG(RESET0_REGISTER);
6605 WRITE_RESET_REG(RESET0_REGISTER,
6606 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6607
6608 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6609#endif
6610 WRITE_VREG(POWER_CTL_VLD,
6611 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6612 (1 << 9) | (1 << 6));
6613 } else {
6614 /* WRITE_VREG(POWER_CTL_VLD,
6615 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6616 */
6617 WRITE_VREG(POWER_CTL_VLD,
6618 READ_VREG(POWER_CTL_VLD) |
6619 (0 << 10) | (1 << 9) | (1 << 6));
6620 }
6621 /* disable PSCALE for hardware sharing */
6622 WRITE_VREG(PSCALE_CTRL, 0);
6623
6624 /* clear mailbox interrupt */
6625 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6626
6627 /* enable mailbox interrupt */
6628 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6629
6630#ifdef NV21
6631 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6632#endif
6633
6634 /* cbcr_merge_swap_en */
6635 if (hw->is_used_v4l
6636 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6637 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6638 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6639
6640 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6641 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6642
6643 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6644 if (hw->mmu_enable) {
6645 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6646 /* sw reset to extif hardware */
6647 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6648 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6649 } else {
6650 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6651 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6652 }
6653
6654
6655#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6656 /* pr_info("vh264 meson8 prot init\n"); */
6657 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6658#endif
6659
6660#ifdef VDEC_DW
6661 if (IS_VDEC_DW(hw)) {
6662 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6663
6664 if (IS_VDEC_DW(hw) == 2)
6665 data |= (1 << 9);
6666 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6667 }
6668#endif
6669 if (hw->dpb.mDPB.size > 0) {
6670 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6671 (hw->dpb.mDPB.size << 16) |
6672 (hw->dpb.mDPB.size << 8));
6673
6674 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6675 i = get_buf_spec_by_canvas_pos(hw, j);
6676 if (i < 0)
6677 break;
6678
6679 if (!hw->mmu_enable &&
6680 hw->buffer_spec[i].cma_alloc_addr)
6681 config_decode_canvas(hw, i);
6682 if (hw->mmu_enable && hw->double_write_mode)
6683 config_decode_canvas_ex(hw, i);
6684 }
6685 } else {
6686 WRITE_VREG(AV_SCRATCH_0, 0);
6687 WRITE_VREG(AV_SCRATCH_9, 0);
6688 }
6689
6690 if (hw->init_flag == 0)
6691 WRITE_VREG(DPB_STATUS_REG, 0);
6692 else
6693 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6694
6695 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6696 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6697 if (!tee_enabled())
6698 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6699
6700 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6701 * error_recovery_mode : error_recovery_mode_in;
6702 */
6703 /* WRITE_VREG(AV_SCRATCH_F,
6704 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6705 */
6706 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6707 ((error_recovery_mode_in & 0x1) << 4));
6708 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6709 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6710 else*/
6711 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6712
6713 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6714#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6715 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6716#endif
6717
6718 WRITE_VREG(DEBUG_REG1, 0);
6719 WRITE_VREG(DEBUG_REG2, 0);
6720
6721 if (hw->reg_iqidct_control)
6722 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6723 if (hw->reg_vcop_ctrl_reg)
6724 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6725 if (hw->vld_dec_control)
6726 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6727 return 0;
6728}
6729
6730static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6731{
6732 struct vdec_h264_hw_s *hw =
6733 (struct vdec_h264_hw_s *)vdec->private;
6734 if (i_only_flag & 0x100)
6735 return 0;
6736 if (trickmode == TRICKMODE_I)
6737 hw->i_only = 0x3;
6738 else if (trickmode == TRICKMODE_NONE)
6739 hw->i_only = 0x0;
6740 return 0;
6741}
6742
6743static unsigned char amvdec_enable_flag;
6744static void vh264_local_init(struct vdec_h264_hw_s *hw)
6745{
6746 int i;
6747 hw->init_flag = 0;
6748 hw->first_sc_checked= 0;
6749 hw->eos = 0;
6750 hw->valve_count = 0;
6751 hw->config_bufmgr_done = 0;
6752 hw->start_process_time = 0;
6753 hw->has_i_frame = 0;
6754 hw->no_error_count = 0xfff;
6755 hw->no_error_i_count = 0xf;
6756
6757 hw->dec_flag = 0;
6758 hw->data_flag = 0;
6759 hw->skip_frame_count = 0;
6760 hw->reg_iqidct_control = 0;
6761 hw->reg_vcop_ctrl_reg = 0;
6762 hw->reg_rv_ai_mb_count = 0;
6763 hw->vld_dec_control = 0;
6764 hw->decode_timeout_count = 0;
6765 hw->no_mem_count = 0;
6766 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6767 /* vh264_ratio = 0x100; */
6768
6769 hw->vh264_rotation = (((unsigned long)
6770 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6771
6772 hw->frame_prog = 0;
6773 hw->frame_width = hw->vh264_amstream_dec_info.width;
6774 hw->frame_height = hw->vh264_amstream_dec_info.height;
6775 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6776 hw->pts_outside = ((unsigned long)
6777 hw->vh264_amstream_dec_info.param) & 0x01;
6778 hw->sync_outside = ((unsigned long)
6779 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6780 hw->use_idr_framerate = ((unsigned long)
6781 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6782 hw->max_refer_buf = !(((unsigned long)
6783 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6784 if (hw->frame_dur < 96000/960) {
6785 /*more than 960fps,it should not be a correct value,
6786 *give default 30fps
6787 */
6788 hw->frame_dur = 96000/30;
6789 }
6790
6791 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6792
6793 hw->first_i_policy = first_i_policy;
6794
6795 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6796 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6797 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6798 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6799
6800 if (i_only_flag & 0x100)
6801 hw->i_only = i_only_flag & 0xff;
6802 if (hw->i_only)
6803 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6804
6805 if ((unsigned long) hw->vh264_amstream_dec_info.param
6806 & 0x08)
6807 hw->no_poc_reorder_flag = 1;
6808
6809 error_recovery_mode_in = 1; /*ucode control?*/
6810 if (error_proc_policy & 0x80000000)
6811 hw->send_error_frame_flag = error_proc_policy & 0x1;
6812 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6813 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6814
6815 INIT_KFIFO(hw->display_q);
6816 INIT_KFIFO(hw->newframe_q);
6817
6818 for (i = 0; i < VF_POOL_SIZE; i++) {
6819 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6820 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6821 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6822 kfifo_put(&hw->newframe_q, vf);
6823 }
6824
6825 hw->duration_from_pts_done = 0;
6826
6827 hw->p_last_vf = NULL;
6828 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6829 hw->hevc_cur_buf_idx = 0xffff;
6830
6831 init_waitqueue_head(&hw->wait_q);
6832
6833 return;
6834}
6835
6836static s32 vh264_init(struct vdec_h264_hw_s *hw)
6837{
6838 int size = -1;
6839 int fw_size = 0x1000 * 16;
6840 int fw_mmu_size = 0x1000 * 16;
6841 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6842
6843 /* int trickmode_fffb = 0; */
6844
6845 /* pr_info("\nvh264_init\n"); */
6846 /* init_timer(&hw->recycle_timer); */
6847
6848 /* timer init */
6849 init_timer(&hw->check_timer);
6850
6851 hw->check_timer.data = (unsigned long)hw;
6852 hw->check_timer.function = check_timer_func;
6853 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6854
6855 /* add_timer(&hw->check_timer); */
6856 hw->stat |= STAT_TIMER_ARM;
6857 hw->stat |= STAT_ISR_REG;
6858
6859 mutex_init(&hw->chunks_mutex);
6860 vh264_local_init(hw);
6861 INIT_WORK(&hw->work, vh264_work);
6862 INIT_WORK(&hw->notify_work, vh264_notify_work);
6863 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6864#ifdef MH264_USERDATA_ENABLE
6865 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6866#endif
6867
6868 if (!amvdec_enable_flag) {
6869 amvdec_enable_flag = true;
6870 amvdec_enable();
6871 if (hw->mmu_enable)
6872 amhevc_enable();
6873 }
6874 if (hw->mmu_enable) {
6875
6876 hw->frame_mmu_map_addr =
6877 dma_alloc_coherent(amports_get_dma_device(),
6878 FRAME_MMU_MAP_SIZE,
6879 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6880 if (hw->frame_mmu_map_addr == NULL) {
6881 pr_err("%s: failed to alloc count_buffer\n", __func__);
6882 return -ENOMEM;
6883 }
6884 }
6885
6886 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6887 if (IS_ERR_OR_NULL(fw))
6888 return -ENOMEM;
6889
6890 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6891 if (size < 0) {
6892 pr_err("get firmware fail.\n");
6893 vfree(fw);
6894 return -1;
6895 }
6896
6897 fw->len = size;
6898 hw->fw = fw;
6899
6900 if (hw->mmu_enable) {
6901 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6902 if (IS_ERR_OR_NULL(fw_mmu))
6903 return -ENOMEM;
6904
6905 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6906 if (size < 0) {
6907 pr_err("get mmu fw fail.\n");
6908 vfree(fw_mmu);
6909 return -1;
6910 }
6911
6912 fw_mmu->len = size;
6913 hw->fw_mmu = fw_mmu;
6914 }
6915
6916 if (!tee_enabled()) {
6917 /* -- ucode loading (amrisc and swap code) */
6918 hw->mc_cpu_addr =
6919 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6920 &hw->mc_dma_handle, GFP_KERNEL);
6921 if (!hw->mc_cpu_addr) {
6922 amvdec_enable_flag = false;
6923 amvdec_disable();
6924 if (hw->mmu_enable)
6925 amhevc_disable();
6926 pr_info("vh264_init: Can not allocate mc memory.\n");
6927 return -ENOMEM;
6928 }
6929
6930 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6931 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6932 */
6933
6934 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6935
6936 /*header*/
6937 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6938 fw->data + 0x4000, MC_SWAP_SIZE);
6939 /*data*/
6940 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6941 fw->data + 0x2000, MC_SWAP_SIZE);
6942 /*mmco*/
6943 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6944 fw->data + 0x6000, MC_SWAP_SIZE);
6945 /*list*/
6946 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6947 fw->data + 0x3000, MC_SWAP_SIZE);
6948 /*slice*/
6949 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6950 fw->data + 0x5000, MC_SWAP_SIZE);
6951 /*main*/
6952 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6953 fw->data, 0x2000);
6954 /*data*/
6955 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6956 fw->data + 0x2000, 0x1000);
6957 /*slice*/
6958 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6959 fw->data + 0x5000, 0x1000);
6960 }
6961
6962#if 1 /* #ifdef BUFFER_MGR_IN_C */
6963 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6964 if (!hw->lmem_addr) {
6965 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6966 return -ENOMEM;
6967 } else {
6968 hw->lmem_addr_remap = dma_map_single(
6969 amports_get_dma_device(),
6970 (void *)hw->lmem_addr,
6971 PAGE_SIZE, DMA_FROM_DEVICE);
6972 if (dma_mapping_error(amports_get_dma_device(),
6973 hw->lmem_addr_remap)) {
6974 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6975 "%s: failed to map lmem_addr\n", __func__);
6976 free_page(hw->lmem_addr);
6977 hw->lmem_addr = 0;
6978 hw->lmem_addr_remap = 0;
6979 return -ENOMEM;
6980 }
6981
6982 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6983 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6984 }
6985
6986 if (prefix_aux_buf_size > 0 ||
6987 suffix_aux_buf_size > 0) {
6988 u32 aux_buf_size;
6989 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6990 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
6991 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
6992 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
6993 if (hw->aux_addr == NULL) {
6994 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6995 return -1;
6996 }
6997
6998 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
6999 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7000 if (dma_mapping_error(amports_get_dma_device(),
7001 hw->aux_phy_addr)) {
7002 pr_err("%s: failed to map rpm buffer\n", __func__);
7003 kfree(hw->aux_addr);
7004 hw->aux_addr = NULL;
7005 return -1;
7006 }
7007 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7008 if (hw->sei_data_buf == NULL) {
7009 pr_err("%s: failed to alloc sei itu data buffer\n",
7010 __func__);
7011 return -1;
7012 }
7013 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7014 if (hw->sei_itu_data_buf == NULL) {
7015 pr_err("%s: failed to alloc sei itu data buffer\n",
7016 __func__);
7017 kfree(hw->aux_addr);
7018 hw->aux_addr = NULL;
7019 kfree(hw->sei_data_buf);
7020 hw->sei_data_buf = NULL;
7021
7022 return -1;
7023 }
7024
7025 if (NULL == hw->sei_user_data_buffer) {
7026 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7027 GFP_KERNEL);
7028 if (!hw->sei_user_data_buffer) {
7029 pr_info("%s: Can not allocate sei_data_buffer\n",
7030 __func__);
7031 kfree(hw->aux_addr);
7032 hw->aux_addr = NULL;
7033 kfree(hw->sei_data_buf);
7034 hw->sei_data_buf = NULL;
7035 kfree(hw->sei_itu_data_buf);
7036 hw->sei_itu_data_buf = NULL;
7037
7038 return -1;
7039 }
7040 hw->sei_user_data_wp = 0;
7041 }
7042 }
7043/* BUFFER_MGR_IN_C */
7044#endif
7045 hw->stat |= STAT_MC_LOAD;
7046
7047 /* add memory barrier */
7048 wmb();
7049
7050 return 0;
7051}
7052
7053static int vh264_stop(struct vdec_h264_hw_s *hw)
7054{
7055 if (hw->stat & STAT_VDEC_RUN) {
7056 amvdec_stop();
7057 hw->stat &= ~STAT_VDEC_RUN;
7058 }
7059#ifdef VDEC_DW
7060 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7061#endif
7062#ifdef MH264_USERDATA_ENABLE
7063 cancel_work_sync(&hw->user_data_ready_work);
7064#endif
7065 cancel_work_sync(&hw->notify_work);
7066 cancel_work_sync(&hw->timeout_work);
7067 cancel_work_sync(&hw->work);
7068
7069
7070 if (hw->stat & STAT_MC_LOAD) {
7071 if (hw->mc_cpu_addr != NULL) {
7072 dma_free_coherent(amports_get_dma_device(),
7073 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7074 hw->mc_dma_handle);
7075 hw->mc_cpu_addr = NULL;
7076 }
7077 if (hw->frame_mmu_map_addr != NULL) {
7078 dma_free_coherent(amports_get_dma_device(),
7079 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7080 hw->frame_mmu_map_phy_addr);
7081 hw->frame_mmu_map_addr = NULL;
7082 }
7083
7084 }
7085 if (hw->stat & STAT_ISR_REG) {
7086 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7087 hw->stat &= ~STAT_ISR_REG;
7088 }
7089 if (hw->lmem_addr_remap) {
7090 dma_unmap_single(amports_get_dma_device(),
7091 hw->lmem_addr_remap,
7092 PAGE_SIZE, DMA_FROM_DEVICE);
7093 hw->lmem_addr_remap = 0;
7094 }
7095 if (hw->lmem_addr) {
7096 free_page(hw->lmem_addr);
7097 hw->lmem_addr = 0;
7098 }
7099 if (hw->aux_addr) {
7100 dma_unmap_single(amports_get_dma_device(),
7101 hw->aux_phy_addr,
7102 hw->prefix_aux_size + hw->suffix_aux_size,
7103 DMA_FROM_DEVICE);
7104 kfree(hw->aux_addr);
7105 hw->aux_addr = NULL;
7106 }
7107 if (hw->sei_data_buf != NULL) {
7108 kfree(hw->sei_data_buf);
7109 hw->sei_data_buf = NULL;
7110 }
7111 if (hw->sei_itu_data_buf != NULL) {
7112 kfree(hw->sei_itu_data_buf);
7113 hw->sei_itu_data_buf = NULL;
7114 }
7115 if (hw->sei_user_data_buffer != NULL) {
7116 kfree(hw->sei_user_data_buffer);
7117 hw->sei_user_data_buffer = NULL;
7118 }
7119 /* amvdec_disable(); */
7120
7121 vfree(hw->fw);
7122 hw->fw = NULL;
7123
7124 if (hw->mmu_enable) {
7125 vfree(hw->fw_mmu);
7126 hw->fw_mmu = NULL;
7127 }
7128
7129 dpb_print(DECODE_ID(hw), 0,
7130 "%s\n",
7131 __func__);
7132 return 0;
7133}
7134
7135static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7136{
7137 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7138 int count = 0;
7139 do {
7140 usleep_range(100, 500);
7141 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7142 break;
7143 if (count > 2000) {
7144 dpb_print(DECODE_ID(hw),
7145 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7146 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7147 break;
7148 } else
7149 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7150 count++;
7151 } while (1);
7152}
7153
7154static void vh264_notify_work(struct work_struct *work)
7155{
7156 struct vdec_h264_hw_s *hw = container_of(work,
7157 struct vdec_h264_hw_s, notify_work);
7158 struct vdec_s *vdec = hw_to_vdec(hw);
7159 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7160 vf_notify_receiver(vdec->vf_provider_name,
7161 VFRAME_EVENT_PROVIDER_FR_HINT,
7162 (void *)((unsigned long)hw->frame_dur));
7163 vdec->fr_hint_state = VDEC_HINTED;
7164 }
7165
7166 return;
7167}
7168
7169#ifdef MH264_USERDATA_ENABLE
7170static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7171{
7172 hw->wait_for_udr_send = 0;
7173 hw->sei_itu_data_len = 0;
7174 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7175}
7176
7177static void vmh264_crate_userdata_manager(
7178 struct vdec_h264_hw_s *hw,
7179 u8 *userdata_buf,
7180 int buf_len)
7181{
7182 if (hw) {
7183
7184
7185 mutex_init(&hw->userdata_mutex);
7186
7187 memset(&hw->userdata_info, 0,
7188 sizeof(struct mh264_userdata_info_t));
7189 hw->userdata_info.data_buf = userdata_buf;
7190 hw->userdata_info.buf_len = buf_len;
7191 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7192
7193 vmh264_reset_udr_mgr(hw);
7194
7195 }
7196}
7197
7198static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7199{
7200 if (hw)
7201 memset(&hw->userdata_info,
7202 0,
7203 sizeof(struct mh264_userdata_info_t));
7204}
7205
7206/*
7207#define DUMP_USERDATA_RECORD
7208*/
7209#ifdef DUMP_USERDATA_RECORD
7210
7211#define MAX_USER_DATA_SIZE 3145728
7212static void *user_data_buf;
7213static unsigned char *pbuf_start;
7214static int total_len;
7215static int bskip;
7216static int n_userdata_id;
7217
7218static void print_data(unsigned char *pdata,
7219 int len,
7220 unsigned int poc_number,
7221 unsigned int flag,
7222 unsigned int duration,
7223 unsigned int vpts,
7224 unsigned int vpts_valid,
7225 int rec_id)
7226{
7227 int nLeft;
7228
7229 nLeft = len;
7230#if 0
7231 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7232 rec_id, len, flag,
7233 duration, vpts, vpts_valid, poc_number);
7234#endif
7235 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7236 rec_id, len, flag, vpts);
7237
7238 if (len == 96) {
7239 int i;
7240 nLeft = 72;
7241 while (nLeft >= 16) {
7242 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7243 pdata[0], pdata[1], pdata[2], pdata[3],
7244 pdata[4], pdata[5], pdata[6], pdata[7],
7245 pdata[8], pdata[9], pdata[10], pdata[11],
7246 pdata[12], pdata[13], pdata[14], pdata[15]);
7247 nLeft -= 16;
7248 pdata += 16;
7249 }
7250
7251
7252 while (nLeft > 0) {
7253 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7254 pdata[0], pdata[1], pdata[2], pdata[3],
7255 pdata[4], pdata[5], pdata[6], pdata[7]);
7256 nLeft -= 8;
7257 pdata += 8;
7258 }
7259
7260 i = 0;
7261 nLeft = 96-72;
7262 while (i < nLeft) {
7263 if (pdata[0] != 0) {
7264 pr_info("some data error\n");
7265 break;
7266 }
7267 pdata++;
7268 i++;
7269 }
7270 } else {
7271 while (nLeft >= 16) {
7272 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7273 pdata[0], pdata[1], pdata[2], pdata[3],
7274 pdata[4], pdata[5], pdata[6], pdata[7],
7275 pdata[8], pdata[9], pdata[10], pdata[11],
7276 pdata[12], pdata[13], pdata[14], pdata[15]);
7277 nLeft -= 16;
7278 pdata += 16;
7279 }
7280
7281
7282 while (nLeft > 0) {
7283 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7284 pdata[0], pdata[1], pdata[2], pdata[3],
7285 pdata[4], pdata[5], pdata[6], pdata[7]);
7286 nLeft -= 8;
7287 pdata += 8;
7288 }
7289
7290 }
7291}
7292
7293static void push_to_buf(struct vdec_h264_hw_s *hw,
7294 u8 *pdata,
7295 int len,
7296 struct userdata_meta_info_t *pmeta);
7297
7298static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7299 struct mh264_userdata_record_t *record)
7300{
7301 if (record && hw) {
7302 u8 *pdata;
7303
7304 pdata = hw->userdata_info.data_buf + record->rec_start;
7305/*
7306 print_data(pdata,
7307 record->rec_len,
7308 record->meta_info.flags,
7309 record->meta_info.duration,
7310 record->meta_info.vpts,
7311 record->meta_info.vpts_valid,
7312 n_record_id);
7313*/
7314 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7315 n_userdata_id++;
7316 }
7317}
7318
7319
7320static void push_to_buf(struct vdec_h264_hw_s *hw,
7321 u8 *pdata, int len,
7322 struct userdata_meta_info_t *pmeta)
7323{
7324 u32 *pLen;
7325 int info_cnt;
7326 u8 *pbuf_end;
7327
7328 if (!user_data_buf)
7329 return;
7330
7331 if (bskip) {
7332 pr_info("over size, skip\n");
7333 return;
7334 }
7335 info_cnt = 0;
7336 pLen = (u32 *)pbuf_start;
7337
7338 *pLen = len;
7339 pbuf_start += sizeof(u32);
7340 info_cnt++;
7341 pLen++;
7342
7343 *pLen = pmeta->poc_number;
7344 pbuf_start += sizeof(u32);
7345 info_cnt++;
7346 pLen++;
7347
7348 *pLen = pmeta->duration;
7349 pbuf_start += sizeof(u32);
7350 info_cnt++;
7351 pLen++;
7352
7353 *pLen = pmeta->flags;
7354 pbuf_start += sizeof(u32);
7355 info_cnt++;
7356 pLen++;
7357
7358 *pLen = pmeta->vpts;
7359 pbuf_start += sizeof(u32);
7360 info_cnt++;
7361 pLen++;
7362
7363 *pLen = pmeta->vpts_valid;
7364 pbuf_start += sizeof(u32);
7365 info_cnt++;
7366 pLen++;
7367
7368
7369 *pLen = n_userdata_id;
7370 pbuf_start += sizeof(u32);
7371 info_cnt++;
7372 pLen++;
7373
7374
7375
7376 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7377 if (pdata + len > pbuf_end) {
7378 int first_section_len;
7379
7380 first_section_len = pbuf_end - pdata;
7381 memcpy(pbuf_start, pdata, first_section_len);
7382 pdata = (u8 *)hw->sei_user_data_buffer;
7383 pbuf_start += first_section_len;
7384 memcpy(pbuf_start, pdata, len - first_section_len);
7385 pbuf_start += len - first_section_len;
7386 } else {
7387 memcpy(pbuf_start, pdata, len);
7388 pbuf_start += len;
7389 }
7390
7391 total_len += len + info_cnt * sizeof(u32);
7392 if (total_len >= MAX_USER_DATA_SIZE-4096)
7393 bskip = 1;
7394}
7395
7396static void show_user_data_buf(void)
7397{
7398 u8 *pbuf;
7399 int len;
7400 unsigned int flag;
7401 unsigned int duration;
7402 unsigned int vpts;
7403 unsigned int vpts_valid;
7404 unsigned int poc_number;
7405 int rec_id;
7406
7407 pr_info("show user data buf\n");
7408 pbuf = user_data_buf;
7409
7410 while (pbuf < pbuf_start) {
7411 u32 *pLen;
7412
7413 pLen = (u32 *)pbuf;
7414
7415 len = *pLen;
7416 pLen++;
7417 pbuf += sizeof(u32);
7418
7419 poc_number = *pLen;
7420 pLen++;
7421 pbuf += sizeof(u32);
7422
7423 duration = *pLen;
7424 pLen++;
7425 pbuf += sizeof(u32);
7426
7427 flag = *pLen;
7428 pLen++;
7429 pbuf += sizeof(u32);
7430
7431 vpts = *pLen;
7432 pLen++;
7433 pbuf += sizeof(u32);
7434
7435 vpts_valid = *pLen;
7436 pLen++;
7437 pbuf += sizeof(u32);
7438
7439 rec_id = *pLen;
7440 pLen++;
7441 pbuf += sizeof(u32);
7442
7443 print_data(pbuf, len, poc_number, flag,
7444 duration, vpts,
7445 vpts_valid, rec_id);
7446 pbuf += len;
7447 msleep(30);
7448 }
7449}
7450
7451static int vmh264_init_userdata_dump(void)
7452{
7453 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7454 if (user_data_buf)
7455 return 1;
7456 else
7457 return 0;
7458}
7459
7460static void vmh264_dump_userdata(void)
7461{
7462 if (user_data_buf) {
7463 show_user_data_buf();
7464 kfree(user_data_buf);
7465 user_data_buf = NULL;
7466 }
7467}
7468
7469static void vmh264_reset_user_data_buf(void)
7470{
7471 total_len = 0;
7472 pbuf_start = user_data_buf;
7473 bskip = 0;
7474 n_userdata_id = 0;
7475}
7476#endif
7477
7478
7479static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7480 int frame_type,
7481 u32 vpts,
7482 u32 vpts_valid)
7483{
7484 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7485
7486 unsigned char *pdata;
7487 u8 *pmax_sei_data_buffer;
7488 u8 *sei_data_buf;
7489 int i;
7490 int wp;
7491 int data_length;
7492 struct mh264_userdata_record_t *p_userdata_rec;
7493
7494
7495#ifdef MH264_USERDATA_ENABLE
7496 struct userdata_meta_info_t meta_info;
7497 memset(&meta_info, 0, sizeof(meta_info));
7498#endif
7499
7500 if (hw->sei_itu_data_len <= 0)
7501 return;
7502
7503 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7504 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7505 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7506 for (i = 0; i < hw->sei_itu_data_len; i++) {
7507 *pdata++ = sei_data_buf[i];
7508 if (pdata >= pmax_sei_data_buffer)
7509 pdata = (u8 *)hw->sei_user_data_buffer;
7510 }
7511
7512 hw->sei_user_data_wp = (hw->sei_user_data_wp
7513 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7514 hw->sei_itu_data_len = 0;
7515
7516#ifdef MH264_USERDATA_ENABLE
7517 meta_info.duration = hw->frame_dur;
7518 meta_info.flags |= (VFORMAT_H264 << 3);
7519
7520 meta_info.vpts = vpts;
7521 meta_info.vpts_valid = vpts_valid;
7522 meta_info.poc_number =
7523 p_H264_Dpb->mVideo.dec_picture->poc;
7524
7525
7526 wp = hw->sei_user_data_wp;
7527
7528 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7529 data_length = wp - hw->userdata_info.last_wp;
7530 else
7531 data_length = wp + hw->userdata_info.buf_len
7532 - hw->userdata_info.last_wp;
7533
7534 if (data_length & 0x7)
7535 data_length = (((data_length + 8) >> 3) << 3);
7536
7537 p_userdata_rec = &hw->ud_record;
7538 p_userdata_rec->meta_info = meta_info;
7539 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7540 p_userdata_rec->rec_len = data_length;
7541 hw->userdata_info.last_wp = wp;
7542
7543 p_userdata_rec->meta_info.flags |=
7544 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7545
7546 hw->wait_for_udr_send = 1;
7547 vdec_schedule_work(&hw->user_data_ready_work);
7548#endif
7549}
7550
7551
7552static void user_data_ready_notify_work(struct work_struct *work)
7553{
7554 struct vdec_h264_hw_s *hw = container_of(work,
7555 struct vdec_h264_hw_s, user_data_ready_work);
7556
7557
7558 mutex_lock(&hw->userdata_mutex);
7559
7560 hw->userdata_info.records[hw->userdata_info.write_index]
7561 = hw->ud_record;
7562 hw->userdata_info.write_index++;
7563 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7564 hw->userdata_info.write_index = 0;
7565
7566 mutex_unlock(&hw->userdata_mutex);
7567
7568#ifdef DUMP_USERDATA_RECORD
7569 dump_userdata_record(hw, &hw->ud_record);
7570#endif
7571 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7572
7573 hw->wait_for_udr_send = 0;
7574}
7575
7576static int vmh264_user_data_read(struct vdec_s *vdec,
7577 struct userdata_param_t *puserdata_para)
7578{
7579 struct vdec_h264_hw_s *hw = NULL;
7580 int rec_ri, rec_wi;
7581 int rec_len;
7582 u8 *rec_data_start;
7583 u8 *pdest_buf;
7584 struct mh264_userdata_record_t *p_userdata_rec;
7585 u32 data_size;
7586 u32 res;
7587 int copy_ok = 1;
7588
7589 hw = (struct vdec_h264_hw_s *)vdec->private;
7590
7591 pdest_buf = puserdata_para->pbuf_addr;
7592
7593 mutex_lock(&hw->userdata_mutex);
7594
7595/*
7596 pr_info("ri = %d, wi = %d\n",
7597 lg_p_mpeg12_userdata_info->read_index,
7598 lg_p_mpeg12_userdata_info->write_index);
7599*/
7600 rec_ri = hw->userdata_info.read_index;
7601 rec_wi = hw->userdata_info.write_index;
7602
7603 if (rec_ri == rec_wi) {
7604 mutex_unlock(&hw->userdata_mutex);
7605 return 0;
7606 }
7607
7608 p_userdata_rec = hw->userdata_info.records + rec_ri;
7609
7610 rec_len = p_userdata_rec->rec_len;
7611 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7612/*
7613 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7614 p_userdata_rec->rec_len,
7615 p_userdata_rec->rec_start,
7616 puserdata_para->buf_len);
7617*/
7618 if (rec_len <= puserdata_para->buf_len) {
7619 /* dvb user data buffer is enought to
7620 copy the whole recored. */
7621 data_size = rec_len;
7622 if (rec_data_start + data_size
7623 > hw->userdata_info.data_buf_end) {
7624 int first_section_len;
7625
7626 first_section_len = hw->userdata_info.buf_len -
7627 p_userdata_rec->rec_start;
7628 res = (u32)copy_to_user((void *)pdest_buf,
7629 (void *)rec_data_start,
7630 first_section_len);
7631 if (res) {
7632 pr_info("p1 read not end res=%d, request=%d\n",
7633 res, first_section_len);
7634 copy_ok = 0;
7635
7636 p_userdata_rec->rec_len -=
7637 first_section_len - res;
7638 p_userdata_rec->rec_start +=
7639 first_section_len - res;
7640 puserdata_para->data_size =
7641 first_section_len - res;
7642 } else {
7643 res = (u32)copy_to_user(
7644 (void *)(pdest_buf+first_section_len),
7645 (void *)hw->userdata_info.data_buf,
7646 data_size - first_section_len);
7647 if (res) {
7648 pr_info("p2 read not end res=%d, request=%d\n",
7649 res, data_size);
7650 copy_ok = 0;
7651 }
7652 p_userdata_rec->rec_len -=
7653 data_size - res;
7654 p_userdata_rec->rec_start =
7655 data_size - first_section_len - res;
7656 puserdata_para->data_size =
7657 data_size - res;
7658 }
7659 } else {
7660 res = (u32)copy_to_user((void *)pdest_buf,
7661 (void *)rec_data_start,
7662 data_size);
7663 if (res) {
7664 pr_info("p3 read not end res=%d, request=%d\n",
7665 res, data_size);
7666 copy_ok = 0;
7667 }
7668 p_userdata_rec->rec_len -= data_size - res;
7669 p_userdata_rec->rec_start += data_size - res;
7670 puserdata_para->data_size = data_size - res;
7671 }
7672
7673 if (copy_ok) {
7674 hw->userdata_info.read_index++;
7675 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7676 hw->userdata_info.read_index = 0;
7677 }
7678 } else {
7679 /* dvb user data buffer is not enought
7680 to copy the whole recored. */
7681 data_size = puserdata_para->buf_len;
7682 if (rec_data_start + data_size
7683 > hw->userdata_info.data_buf_end) {
7684 int first_section_len;
7685
7686 first_section_len = hw->userdata_info.buf_len -
7687 p_userdata_rec->rec_start;
7688 res = (u32)copy_to_user((void *)pdest_buf,
7689 (void *)rec_data_start,
7690 first_section_len);
7691 if (res) {
7692 pr_info("p4 read not end res=%d, request=%d\n",
7693 res, first_section_len);
7694 copy_ok = 0;
7695 p_userdata_rec->rec_len -=
7696 first_section_len - res;
7697 p_userdata_rec->rec_start +=
7698 first_section_len - res;
7699 puserdata_para->data_size =
7700 first_section_len - res;
7701 } else {
7702 /* first secton copy is ok*/
7703 res = (u32)copy_to_user(
7704 (void *)(pdest_buf+first_section_len),
7705 (void *)hw->userdata_info.data_buf,
7706 data_size - first_section_len);
7707 if (res) {
7708 pr_info("p5 read not end res=%d, request=%d\n",
7709 res,
7710 data_size - first_section_len);
7711 copy_ok = 0;
7712 }
7713
7714 p_userdata_rec->rec_len -=
7715 data_size - res;
7716 p_userdata_rec->rec_start =
7717 data_size - first_section_len - res;
7718 puserdata_para->data_size =
7719 data_size - res;
7720 }
7721 } else {
7722 res = (u32)copy_to_user((void *)pdest_buf,
7723 (void *)rec_data_start,
7724 data_size);
7725 if (res) {
7726 pr_info("p6 read not end res=%d, request=%d\n",
7727 res, data_size);
7728 copy_ok = 0;
7729 }
7730
7731 p_userdata_rec->rec_len -= data_size - res;
7732 p_userdata_rec->rec_start += data_size - res;
7733 puserdata_para->data_size = data_size - res;
7734 }
7735
7736 if (copy_ok) {
7737 hw->userdata_info.read_index++;
7738 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7739 hw->userdata_info.read_index = 0;
7740 }
7741
7742 }
7743 puserdata_para->meta_info = p_userdata_rec->meta_info;
7744
7745 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7746 puserdata_para->meta_info.records_in_que =
7747 hw->userdata_info.write_index -
7748 hw->userdata_info.read_index;
7749 else
7750 puserdata_para->meta_info.records_in_que =
7751 hw->userdata_info.write_index +
7752 USERDATA_FIFO_NUM -
7753 hw->userdata_info.read_index;
7754
7755 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7756
7757 mutex_unlock(&hw->userdata_mutex);
7758
7759 return 1;
7760}
7761
7762static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7763{
7764 struct vdec_h264_hw_s *hw = NULL;
7765
7766 hw = (struct vdec_h264_hw_s *)vdec->private;
7767
7768 if (hw) {
7769 mutex_lock(&hw->userdata_mutex);
7770 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7771 bInit,
7772 hw->userdata_info.read_index,
7773 hw->userdata_info.write_index);
7774 hw->userdata_info.read_index = 0;
7775 hw->userdata_info.write_index = 0;
7776
7777 if (bInit)
7778 hw->userdata_info.last_wp = 0;
7779 mutex_unlock(&hw->userdata_mutex);
7780 }
7781}
7782
7783static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7784{
7785 amstream_wakeup_userdata_poll(vdec);
7786}
7787
7788#endif
7789
7790
7791static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7792 struct vdec_s *vdec, int from)
7793{
7794 /* finished decoding one frame or error,
7795 * notify vdec core to switch context
7796 */
7797 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7798 "%s dec_result %d %x %x %x\n",
7799 __func__,
7800 hw->dec_result,
7801 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7802 READ_VREG(VLD_MEM_VIFIFO_WP),
7803 READ_VREG(VLD_MEM_VIFIFO_RP));
7804 if (!hw->mmu_enable) {
7805 mutex_lock(&vmh264_mutex);
7806 dealloc_buf_specs(hw, 0);
7807 mutex_unlock(&vmh264_mutex);
7808 }
7809 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7810 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7811 u32 param1 = READ_VREG(AV_SCRATCH_1);
7812 u32 param2 = READ_VREG(AV_SCRATCH_2);
7813 u32 param3 = READ_VREG(AV_SCRATCH_6);
7814 u32 param4 = READ_VREG(AV_SCRATCH_B);
7815
7816 if (vh264_set_params(hw, param1,
7817 param2, param3, param4) < 0)
7818 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7819
7820 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7821 (hw->dpb.mDPB.size<<16) |
7822 (hw->dpb.mDPB.size<<8));
7823
7824 if (hw->is_used_v4l) {
7825 struct aml_vcodec_ctx *ctx =
7826 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7827
7828 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7829 struct aml_vdec_ps_infos ps;
7830
7831 ps.visible_width = hw->frame_width;
7832 ps.visible_height = hw->frame_height;
7833 ps.coded_width = ALIGN(hw->frame_width, 64);
7834 ps.coded_height = ALIGN(hw->frame_height, 64);
7835 ps.dpb_size = hw->dpb.mDPB.size;
7836 hw->v4l_params_parsed = true;
7837 vdec_v4l_set_ps_infos(ctx, &ps);
7838 }
7839 }
7840
7841 start_process_time(hw);
7842 return;
7843 } else
7844 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7845 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7846 && (hw_to_vdec(hw)->next_status !=
7847 VDEC_STATUS_DISCONNECTED)) {
7848 if (!vdec_has_more_input(vdec)) {
7849 hw->dec_result = DEC_RESULT_EOS;
7850 vdec_schedule_work(&hw->work);
7851 return;
7852 }
7853
7854 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7855 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7856 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7857 __func__,
7858 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7859 READ_VREG(VLD_MEM_VIFIFO_WP),
7860 READ_VREG(VLD_MEM_VIFIFO_RP));
7861 mutex_lock(&hw->chunks_mutex);
7862 vdec_vframe_dirty(vdec, hw->chunk);
7863 hw->chunk = NULL;
7864 mutex_unlock(&hw->chunks_mutex);
7865 vdec_clean_input(vdec);
7866 }
7867 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7868 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7869 > get_data_timeout_val)) {
7870 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7871 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7872 __func__);
7873 goto result_done;
7874 }
7875 if (is_buffer_available(vdec)) {
7876 int r;
7877 int decode_size;
7878 r = vdec_prepare_input(vdec, &hw->chunk);
7879 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7880 VDEC_STATUS_DISCONNECTED)) {
7881 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7882
7883 dpb_print(DECODE_ID(hw),
7884 PRINT_FLAG_VDEC_DETAIL,
7885 "vdec_prepare_input: Insufficient data\n");
7886 vdec_schedule_work(&hw->work);
7887 return;
7888 }
7889 hw->dec_result = DEC_RESULT_NONE;
7890 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7891 "%s: chunk size 0x%x\n",
7892 __func__, hw->chunk->size);
7893
7894 if (dpb_is_debug(DECODE_ID(hw),
7895 PRINT_FRAMEBASE_DATA)) {
7896 int jj;
7897 u8 *data = NULL;
7898
7899 if (!hw->chunk->block->is_mapped)
7900 data = codec_mm_vmap(
7901 hw->chunk->block->start +
7902 hw->chunk->offset, r);
7903 else
7904 data = ((u8 *)
7905 hw->chunk->block->start_virt)
7906 + hw->chunk->offset;
7907
7908 for (jj = 0; jj < r; jj++) {
7909 if ((jj & 0xf) == 0)
7910 dpb_print(DECODE_ID(hw),
7911 PRINT_FRAMEBASE_DATA,
7912 "%06x:", jj);
7913 dpb_print_cont(DECODE_ID(hw),
7914 PRINT_FRAMEBASE_DATA,
7915 "%02x ", data[jj]);
7916 if (((jj + 1) & 0xf) == 0)
7917 dpb_print_cont(DECODE_ID(hw),
7918 PRINT_FRAMEBASE_DATA,
7919 "\n");
7920 }
7921
7922 if (!hw->chunk->block->is_mapped)
7923 codec_mm_unmap_phyaddr(data);
7924 }
7925 WRITE_VREG(POWER_CTL_VLD,
7926 READ_VREG(POWER_CTL_VLD) |
7927 (0 << 10) | (1 << 9) | (1 << 6));
7928 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7929 decode_size = hw->chunk->size +
7930 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7931 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7932 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7933 vdec_enable_input(vdec);
7934
7935 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7936 start_process_time(hw);
7937 } else{
7938 if (hw_to_vdec(hw)->next_status
7939 != VDEC_STATUS_DISCONNECTED) {
7940 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7941 vdec_schedule_work(&hw->work);
7942 }
7943 }
7944 return;
7945 } else if (hw->dec_result == DEC_RESULT_DONE) {
7946 /* if (!hw->ctx_valid)
7947 hw->ctx_valid = 1; */
7948result_done:
7949 if (hw->mmu_enable
7950 && hw->frame_busy && hw->frame_done) {
7951 long used_4k_num;
7952 hevc_sao_wait_done(hw);
7953 if (hw->hevc_cur_buf_idx != 0xffff) {
7954 used_4k_num =
7955 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7956 if (used_4k_num >= 0)
7957 dpb_print(DECODE_ID(hw),
7958 PRINT_FLAG_MMU_DETAIL,
7959 "release unused buf , used_4k_num %ld index %d\n",
7960 used_4k_num, hw->hevc_cur_buf_idx);
7961 hevc_mmu_dma_check(hw_to_vdec(hw));
7962 decoder_mmu_box_free_idx_tail(
7963 hw->mmu_box,
7964 hw->hevc_cur_buf_idx,
7965 used_4k_num);
7966 hw->hevc_cur_buf_idx = 0xffff;
7967 }
7968 }
7969 decode_frame_count[DECODE_ID(hw)]++;
7970 amvdec_stop();
7971 if (!vdec_is_support_4k()) {
7972 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7973 clk_adj_frame_count++;
7974 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7975 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7976 }
7977 }
7978 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7979 "%s dec_result %d %x %x %x\n",
7980 __func__,
7981 hw->dec_result,
7982 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7983 READ_VREG(VLD_MEM_VIFIFO_WP),
7984 READ_VREG(VLD_MEM_VIFIFO_RP));
7985 mutex_lock(&hw->chunks_mutex);
7986 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7987 hw->chunk = NULL;
7988 mutex_unlock(&hw->chunks_mutex);
7989 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7990 /*
7991 stream base: stream buf empty or timeout
7992 frame base: vdec_prepare_input fail
7993 */
7994 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
7995 VDEC_STATUS_DISCONNECTED)) {
7996 hw->dec_result = DEC_RESULT_EOS;
7997 vdec_schedule_work(&hw->work);
7998 return;
7999 }
8000 hw->next_again_flag = 1;
8001 } else if (hw->dec_result == DEC_RESULT_EOS) {
8002 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8003 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8004 "%s: end of stream\n",
8005 __func__);
8006 amvdec_stop();
8007 if (hw->mmu_enable)
8008 amhevc_stop();
8009 hw->eos = 1;
8010 flush_dpb(p_H264_Dpb);
8011 if (hw->is_used_v4l)
8012 notify_v4l_eos(hw_to_vdec(hw));
8013 mutex_lock(&hw->chunks_mutex);
8014 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8015 hw->chunk = NULL;
8016 mutex_unlock(&hw->chunks_mutex);
8017 vdec_clean_input(vdec);
8018 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8019 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8020 "%s: force exit\n",
8021 __func__);
8022 amvdec_stop();
8023 if (hw->mmu_enable)
8024 amhevc_stop();
8025 if (hw->stat & STAT_ISR_REG) {
8026 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8027 hw->stat &= ~STAT_ISR_REG;
8028 }
8029 }
8030 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8031 del_timer_sync(&hw->check_timer);
8032 hw->stat &= ~STAT_TIMER_ARM;
8033
8034 wait_vmh264_search_done(hw);
8035 /* mark itself has all HW resource released and input released */
8036
8037#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8038 if (hw->switch_dvlayer_flag) {
8039 if (vdec->slave)
8040 vdec_set_next_sched(vdec, vdec->slave);
8041 else if (vdec->master)
8042 vdec_set_next_sched(vdec, vdec->master);
8043 } else if (vdec->slave || vdec->master)
8044 vdec_set_next_sched(vdec, vdec);
8045#endif
8046
8047 if (from == 1) {
8048 /* This is a timeout work */
8049 if (work_pending(&hw->work)) {
8050 /*
8051 * The vh264_work arrives at the last second,
8052 * give it a chance to handle the scenario.
8053 */
8054 return;
8055 }
8056 }
8057
8058 /* mark itself has all HW resource released and input released */
8059 if (vdec->parallel_dec == 1) {
8060 if (hw->mmu_enable == 0)
8061 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8062 else
8063 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8064 } else
8065 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8066
8067 wake_up_interruptible(&hw->wait_q);
8068
8069 if (hw->is_used_v4l) {
8070 struct aml_vcodec_ctx *ctx =
8071 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8072
8073 if (ctx->param_sets_from_ucode &&
8074 !hw->v4l_params_parsed)
8075 vdec_v4l_write_frame_sync(ctx);
8076 }
8077
8078 if (hw->vdec_cb)
8079 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8080}
8081
8082
8083static void vh264_work(struct work_struct *work)
8084{
8085 struct vdec_h264_hw_s *hw = container_of(work,
8086 struct vdec_h264_hw_s, work);
8087 struct vdec_s *vdec = hw_to_vdec(hw);
8088
8089 vh264_work_implement(hw, vdec, 0);
8090}
8091
8092
8093static void vh264_timeout_work(struct work_struct *work)
8094{
8095 struct vdec_h264_hw_s *hw = container_of(work,
8096 struct vdec_h264_hw_s, timeout_work);
8097 struct vdec_s *vdec = hw_to_vdec(hw);
8098
8099 if (work_pending(&hw->work))
8100 return;
8101
8102 vh264_work_implement(hw, vdec, 1);
8103}
8104
8105static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8106{
8107 bool ret = 0;
8108 struct vdec_h264_hw_s *hw =
8109 (struct vdec_h264_hw_s *)vdec->private;
8110 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8111 CODEC_MM_FLAGS_TVP : 0;
8112
8113 if (!hw->first_sc_checked && hw->mmu_enable) {
8114 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8115 hw->first_sc_checked =1;
8116 dpb_print(DECODE_ID(hw), 0,
8117 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8118 size, (hw->need_cache_size >> PAGE_SHIFT),
8119 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8120 }
8121
8122 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8123 && pre_decode_buf_level != 0) {
8124 u32 rp, wp, level;
8125
8126 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8127 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8128 if (wp < rp)
8129 level = vdec->input.size + wp - rp;
8130 else
8131 level = wp - rp;
8132
8133 if (level < pre_decode_buf_level)
8134 return 0;
8135 }
8136
8137#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8138 if (vdec->master)
8139 return 0;
8140#endif
8141 if (hw->eos)
8142 return 0;
8143
8144 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8145 return 0;
8146
8147 if (disp_vframe_valve_level &&
8148 kfifo_len(&hw->display_q) >=
8149 disp_vframe_valve_level) {
8150 hw->valve_count--;
8151 if (hw->valve_count <= 0)
8152 hw->valve_count = 2;
8153 else
8154 return 0;
8155 }
8156 if (hw->next_again_flag &&
8157 (!vdec_frame_based(vdec))) {
8158 u32 parser_wr_ptr =
8159 READ_PARSER_REG(PARSER_VIDEO_WP);
8160 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8161 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8162 again_threshold) {
8163 int r = vdec_sync_input(vdec);
8164 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8165 "%s buf lelvel:%x\n", __func__, r);
8166 return 0;
8167 }
8168 }
8169
8170 if (h264_debug_flag & 0x20000000) {
8171 /* pr_info("%s, a\n", __func__); */
8172 ret = 1;
8173 } else
8174 ret = is_buffer_available(vdec);
8175
8176#ifdef CONSTRAIN_MAX_BUF_NUM
8177 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8178 if (run_ready_max_vf_only_num > 0 &&
8179 get_vf_ref_only_buf_count(hw) >=
8180 run_ready_max_vf_only_num
8181 )
8182 ret = 0;
8183 if (run_ready_display_q_num > 0 &&
8184 kfifo_len(&hw->display_q) >=
8185 run_ready_display_q_num)
8186 ret = 0;
8187 /*avoid more buffers consumed when
8188 switching resolution*/
8189 if (run_ready_max_buf_num == 0xff &&
8190 get_used_buf_count(hw) >
8191 hw->dpb.mDPB.size)
8192 ret = 0;
8193 else if (run_ready_max_buf_num &&
8194 get_used_buf_count(hw) >=
8195 run_ready_max_buf_num)
8196 ret = 0;
8197 }
8198#endif
8199 if (hw->is_used_v4l) {
8200 struct aml_vcodec_ctx *ctx =
8201 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8202
8203 if (ctx->param_sets_from_ucode &&
8204 !ctx->v4l_codec_ready &&
8205 hw->v4l_params_parsed) {
8206 ret = 0; /*the params has parsed.*/
8207 } else if (!ctx->v4l_codec_dpb_ready)
8208 ret = 0;
8209 else if (hw->wait_reset_done_flag)
8210 ret = 0;
8211 }
8212
8213 if (ret)
8214 not_run_ready[DECODE_ID(hw)] = 0;
8215 else
8216 not_run_ready[DECODE_ID(hw)]++;
8217 if (vdec->parallel_dec == 1) {
8218 if (hw->mmu_enable == 0)
8219 return ret ? (CORE_MASK_VDEC_1) : 0;
8220 else
8221 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8222 } else
8223 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8224}
8225
8226static unsigned char get_data_check_sum
8227 (struct vdec_h264_hw_s *hw, int size)
8228{
8229 int jj;
8230 int sum = 0;
8231 u8 *data = NULL;
8232
8233 if (!hw->chunk->block->is_mapped)
8234 data = codec_mm_vmap(hw->chunk->block->start +
8235 hw->chunk->offset, size);
8236 else
8237 data = ((u8 *)hw->chunk->block->start_virt)
8238 + hw->chunk->offset;
8239
8240 for (jj = 0; jj < size; jj++)
8241 sum += data[jj];
8242
8243 if (!hw->chunk->block->is_mapped)
8244 codec_mm_unmap_phyaddr(data);
8245 return sum;
8246}
8247
8248static void run(struct vdec_s *vdec, unsigned long mask,
8249 void (*callback)(struct vdec_s *, void *), void *arg)
8250{
8251 struct vdec_h264_hw_s *hw =
8252 (struct vdec_h264_hw_s *)vdec->private;
8253 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8254 int size, ret = -1;
8255
8256 run_count[DECODE_ID(hw)]++;
8257 vdec_reset_core(vdec);
8258 if (hw->mmu_enable)
8259 hevc_reset_core(vdec);
8260 hw->vdec_cb_arg = arg;
8261 hw->vdec_cb = callback;
8262
8263 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8264 hw->reset_bufmgr_flag = 1;
8265 dpb_print(DECODE_ID(hw), 0,
8266 "kfifo len:%d invaild, need bufmgr reset\n",
8267 kfifo_len(&hw->display_q));
8268 }
8269
8270 hw->pre_parser_wr_ptr =
8271 READ_PARSER_REG(PARSER_VIDEO_WP);
8272 hw->next_again_flag = 0;
8273
8274 if (hw->reset_bufmgr_flag ||
8275 ((error_proc_policy & 0x40) &&
8276 p_H264_Dpb->buf_alloc_fail)) {
8277 if (!hw->is_used_v4l)
8278 h264_reset_bufmgr(vdec);
8279 else {
8280 struct aml_vcodec_ctx *ctx =
8281 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8282 pr_info("v4l2 buffer reset\n");
8283 hw->wait_reset_done_flag = 1;
8284 hw->reset_bufmgr_flag = 0;
8285 vdec_v4l_post_evet(ctx, V4L2_EVENT_REQUEST_RESET);
8286 hw->dec_result = DEC_RESULT_NONE;
8287 vdec_schedule_work(&hw->work);
8288 return;
8289 }
8290 hw->reset_bufmgr_flag = 0;
8291 }
8292
8293 if (h264_debug_cmd & 0xf000) {
8294 if (((h264_debug_cmd >> 12) & 0xf)
8295 == (DECODE_ID(hw) + 1)) {
8296 h264_reconfig(hw);
8297 h264_debug_cmd &= (~0xf000);
8298 }
8299 }
8300 /* hw->chunk = vdec_prepare_input(vdec); */
8301#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8302 if (vdec->slave || vdec->master)
8303 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8304#endif
8305 size = vdec_prepare_input(vdec, &hw->chunk);
8306 if ((size < 0) ||
8307 (input_frame_based(vdec) && hw->chunk == NULL)) {
8308 input_empty[DECODE_ID(hw)]++;
8309 hw->dec_result = DEC_RESULT_AGAIN;
8310
8311 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8312 "vdec_prepare_input: Insufficient data\n");
8313
8314 vdec_schedule_work(&hw->work);
8315 return;
8316 }
8317 input_empty[DECODE_ID(hw)] = 0;
8318
8319 hw->dec_result = DEC_RESULT_NONE;
8320 hw->get_data_count = 0;
8321#if 0
8322 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8323 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8324 READ_VREG(VLD_MEM_VIFIFO_RP),
8325 READ_VREG(VLD_MEM_VIFIFO_WP));
8326#endif
8327
8328 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8329 u8 *data = NULL;
8330
8331 if (!hw->chunk->block->is_mapped)
8332 data = codec_mm_vmap(hw->chunk->block->start +
8333 hw->chunk->offset, size);
8334 else
8335 data = ((u8 *)hw->chunk->block->start_virt)
8336 + hw->chunk->offset;
8337
8338 if (dpb_is_debug(DECODE_ID(hw),
8339 PRINT_FLAG_VDEC_STATUS)
8340 ) {
8341 dpb_print(DECODE_ID(hw), 0,
8342 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8343 __func__, size, get_data_check_sum(hw, size),
8344 data[0], data[1], data[2], data[3],
8345 data[4], data[5], data[size - 4],
8346 data[size - 3], data[size - 2],
8347 data[size - 1]);
8348 }
8349 if (dpb_is_debug(DECODE_ID(hw),
8350 PRINT_FRAMEBASE_DATA)
8351 ) {
8352 int jj;
8353
8354 for (jj = 0; jj < size; jj++) {
8355 if ((jj & 0xf) == 0)
8356 dpb_print(DECODE_ID(hw),
8357 PRINT_FRAMEBASE_DATA,
8358 "%06x:", jj);
8359 dpb_print_cont(DECODE_ID(hw),
8360 PRINT_FRAMEBASE_DATA,
8361 "%02x ", data[jj]);
8362 if (((jj + 1) & 0xf) == 0)
8363 dpb_print_cont(DECODE_ID(hw),
8364 PRINT_FRAMEBASE_DATA,
8365 "\n");
8366 }
8367 }
8368
8369 if (!hw->chunk->block->is_mapped)
8370 codec_mm_unmap_phyaddr(data);
8371 } else
8372 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8373 "%s: %x %x %x %x %x size 0x%x\n",
8374 __func__,
8375 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8376 READ_VREG(VLD_MEM_VIFIFO_WP),
8377 READ_VREG(VLD_MEM_VIFIFO_RP),
8378 READ_PARSER_REG(PARSER_VIDEO_RP),
8379 READ_PARSER_REG(PARSER_VIDEO_WP),
8380 size);
8381
8382 start_process_time(hw);
8383 if (vdec->mc_loaded) {
8384 /*firmware have load before,
8385 and not changes to another.
8386 ignore reload.
8387 */
8388 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8389 } else {
8390
8391 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8392 if (ret < 0) {
8393 amvdec_enable_flag = false;
8394 amvdec_disable();
8395
8396 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8397 "MH264 the %s fw loading failed, err: %x\n",
8398 tee_enabled() ? "TEE" : "local", ret);
8399 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8400 vdec_schedule_work(&hw->work);
8401 return;
8402 }
8403 vdec->mc_type = VFORMAT_H264;
8404 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8405 if (hw->mmu_enable) {
8406 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8407 hw->fw_mmu->data);
8408 if (ret < 0) {
8409 amvdec_enable_flag = false;
8410 amhevc_disable();
8411
8412 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8413 "MH264_MMU the %s fw loading failed, err: %x\n",
8414 tee_enabled() ? "TEE" : "local", ret);
8415 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8416 vdec_schedule_work(&hw->work);
8417 return;
8418 }
8419 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8420 }
8421 vdec->mc_loaded = 1;
8422 }
8423 vmh264_reset_udr_mgr(hw);
8424
8425 if (vh264_hw_ctx_restore(hw) < 0) {
8426 vdec_schedule_work(&hw->work);
8427 return;
8428 }
8429 if (input_frame_based(vdec)) {
8430 int decode_size = 0;
8431
8432 decode_size = hw->chunk->size +
8433 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8434 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8435 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8436 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8437 } else {
8438 if (size <= 0)
8439 size = 0x7fffffff; /*error happen*/
8440 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8441 WRITE_VREG(H264_DECODE_SIZE, size);
8442 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8443 }
8444 config_aux_buf(hw);
8445 config_decode_mode(hw);
8446 vdec_enable_input(vdec);
8447 WRITE_VREG(NAL_SEARCH_CTL, 0);
8448 hw->sei_data_len = 0;
8449 if (enable_itu_t35)
8450 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8451 if (!hw->init_flag) {
8452 if (hw->mmu_enable)
8453 WRITE_VREG(NAL_SEARCH_CTL,
8454 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8455 else
8456 WRITE_VREG(NAL_SEARCH_CTL,
8457 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8458 }
8459 if (udebug_flag)
8460 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8461 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8462
8463 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8464
8465 if (hw->mmu_enable)
8466 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8467 else
8468 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8469 }
8470 amvdec_start();
8471 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8472 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8473 amhevc_start();
8474 if (hw->config_bufmgr_done) {
8475 hevc_mcr_sao_global_hw_init(hw,
8476 (hw->mb_width << 4), (hw->mb_height << 4));
8477 hevc_mcr_config_canv2axitbl(hw, 1);
8478 }
8479 }
8480
8481 /* if (hw->init_flag) { */
8482 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8483 /* } */
8484
8485 hw->init_flag = 1;
8486}
8487
8488static void reset(struct vdec_s *vdec)
8489{
8490 struct vdec_h264_hw_s *hw =
8491 (struct vdec_h264_hw_s *)vdec->private;
8492
8493 pr_info("vmh264 reset\n");
8494
8495 cancel_work_sync(&hw->work);
8496 cancel_work_sync(&hw->notify_work);
8497 if (hw->stat & STAT_VDEC_RUN) {
8498 amhevc_stop();
8499 hw->stat &= ~STAT_VDEC_RUN;
8500 }
8501
8502 if (hw->stat & STAT_TIMER_ARM) {
8503 del_timer_sync(&hw->check_timer);
8504 hw->stat &= ~STAT_TIMER_ARM;
8505 }
8506 hw->eos = 0;
8507 hw->decode_pic_count = 0;
8508 hw->dec_result = DEC_RESULT_NONE;
8509 reset_process_time(hw);
8510 h264_reset_bufmgr(vdec);
8511 hw->wait_reset_done_flag = 0;
8512
8513 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8514}
8515
8516static void h264_reconfig(struct vdec_h264_hw_s *hw)
8517{
8518 int i;
8519 unsigned long flags;
8520 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8521 struct vdec_s *vdec = hw_to_vdec(hw);
8522 dpb_print(DECODE_ID(hw), 0,
8523 "%s\n", __func__);
8524 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8525 all buffers are in display queue (used == 2),
8526 or free (used == 0)
8527 */
8528 if (dpb_is_debug(DECODE_ID(hw),
8529 PRINT_FLAG_DUMP_BUFSPEC))
8530 dump_bufspec(hw, "pre h264_reconfig");
8531
8532 flush_dpb(p_H264_Dpb);
8533 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8534
8535 if (hw->collocate_cma_alloc_addr) {
8536 decoder_bmmu_box_free_idx(
8537 hw->bmmu_box,
8538 BMMU_REF_IDX);
8539 hw->collocate_cma_alloc_addr = 0;
8540 hw->dpb.colocated_mv_addr_start = 0;
8541 hw->dpb.colocated_mv_addr_end = 0;
8542 }
8543 spin_lock_irqsave(&hw->bufspec_lock, flags);
8544 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8545 if (vdec->parallel_dec == 1) {
8546 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8547 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8548 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8549 hw->buffer_spec[i].y_canvas_index = -1;
8550 hw->buffer_spec[i].u_canvas_index = -1;
8551 hw->buffer_spec[i].v_canvas_index = -1;
8552#ifdef VDEC_DW
8553 if (IS_VDEC_DW(hw)) {
8554 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8555 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8556 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8557 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8558 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8559 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8560#endif
8561 }
8562 }
8563 /*make sure buffers not put back to bufmgr when
8564 vf_put is called*/
8565 if (hw->buffer_spec[i].used == 2)
8566 hw->buffer_spec[i].used = 3;
8567
8568 /* ready to release "free buffers"
8569 */
8570 if (hw->buffer_spec[i].used == 0)
8571 hw->buffer_spec[i].used = 4;
8572
8573 hw->buffer_spec[i].canvas_pos = -1;
8574 }
8575 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8576 hw->has_i_frame = 0;
8577 hw->config_bufmgr_done = 0;
8578
8579 if (hw->is_used_v4l) {
8580 mutex_lock(&vmh264_mutex);
8581 dealloc_buf_specs(hw, 1);
8582 mutex_unlock(&vmh264_mutex);
8583 }
8584
8585 if (dpb_is_debug(DECODE_ID(hw),
8586 PRINT_FLAG_DUMP_BUFSPEC))
8587 dump_bufspec(hw, "after h264_reconfig");
8588
8589}
8590
8591#ifdef ERROR_HANDLE_TEST
8592static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8593{
8594 int i;
8595 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8596 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8597 "%s\n", __func__);
8598 remove_dpb_pictures(p_H264_Dpb);
8599 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8600 /*make sure buffers not put back to bufmgr when
8601 vf_put is called*/
8602 if (hw->buffer_spec[i].used == 2)
8603 hw->buffer_spec[i].used = 5;
8604 }
8605
8606}
8607#endif
8608
8609static void h264_reset_bufmgr(struct vdec_s *vdec)
8610{
8611 int i;
8612 ulong timeout;
8613 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8614#if 0
8615 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8616 int actual_dpb_size, max_reference_size;
8617 int reorder_pic_num;
8618 unsigned int colocated_buf_size;
8619 unsigned int colocated_mv_addr_start;
8620 unsigned int colocated_mv_addr_end;
8621 dpb_print(DECODE_ID(hw), 0,
8622 "%s\n", __func__);
8623
8624 for (i = 0; i < VF_POOL_SIZE; i++)
8625 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8626
8627 actual_dpb_size = p_H264_Dpb->mDPB.size;
8628 max_reference_size = p_H264_Dpb->max_reference_size;
8629 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8630
8631 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8632 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8633 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8634
8635 hw->cur_pool++;
8636 if (hw->cur_pool >= VF_POOL_NUM)
8637 hw->cur_pool = 0;
8638
8639 INIT_KFIFO(hw->display_q);
8640 INIT_KFIFO(hw->newframe_q);
8641
8642 for (i = 0; i < VF_POOL_SIZE; i++) {
8643 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8644 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8645 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8646 kfifo_put(&hw->newframe_q, vf);
8647 }
8648
8649 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8650 hw->buffer_spec[i].used = 0;
8651
8652 dpb_init_global(&hw->dpb,
8653 DECODE_ID(hw), 0, 0);
8654 p_H264_Dpb->mDPB.size = actual_dpb_size;
8655 p_H264_Dpb->max_reference_size = max_reference_size;
8656 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8657
8658 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8659 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8660 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8661
8662 p_H264_Dpb->fast_output_enable = fast_output_enable;
8663 hw->has_i_frame = 0;
8664#else
8665 dpb_print(DECODE_ID(hw), 0,
8666 "%s frame count %d to skip %d\n\n",
8667 __func__, hw->decode_pic_count+1,
8668 hw->skip_frame_count);
8669
8670 timeout = jiffies + HZ;
8671 while (kfifo_len(&hw->display_q) > 0) {
8672 if (time_after(jiffies, timeout))
8673 break;
8674 schedule();
8675 }
8676
8677 for (i = 0; i < VF_POOL_SIZE; i++)
8678 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8679
8680 hw->cur_pool++;
8681 if (hw->cur_pool >= VF_POOL_NUM)
8682 hw->cur_pool = 0;
8683
8684 for (i = 0; i < VF_POOL_SIZE; i++)
8685 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8686
8687
8688 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8689
8690 buf_spec_init(hw);
8691
8692 vh264_local_init(hw);
8693 /*hw->decode_pic_count = 0;
8694 hw->seq_info2 = 0;*/
8695
8696 if (hw->is_used_v4l) {
8697 mutex_lock(&vmh264_mutex);
8698 /* detach relationship with v4l buffs.*/
8699 dealloc_buf_specs(hw, 1);
8700 mutex_unlock(&vmh264_mutex);
8701 }
8702
8703 if (vh264_set_params(hw,
8704 hw->cfg_param1,
8705 hw->cfg_param2,
8706 hw->cfg_param3,
8707 hw->cfg_param4) < 0)
8708 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8709
8710 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8711 if (first_i_policy & 0x01)
8712 hw->first_i_policy = (3 << 8) | first_i_policy;
8713
8714 hw->init_flag = 1;
8715 hw->reset_bufmgr_count++;
8716#endif
8717}
8718
8719int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8720{
8721 int ret = -1;
8722 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8723 CODEC_MM_FLAGS_TVP : 0;
8724 int buf_size = 64;
8725
8726 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8727 tvp_flag, hw->mmu_enable);
8728 hw->need_cache_size = buf_size * SZ_1M;
8729 hw->sc_start_time = get_jiffies_64();
8730 if (hw->mmu_enable && !hw->mmu_box) {
8731 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8732 hw->id,
8733 MMU_MAX_BUFFERS,
8734 hw->need_cache_size,
8735 tvp_flag);
8736 if (!hw->mmu_box) {
8737 pr_err("h264 4k alloc mmu box failed!!\n");
8738 return -1;
8739 }
8740 ret = 0;
8741 }
8742 if (!hw->bmmu_box) {
8743 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8744 DRIVER_NAME,
8745 hw->id,
8746 BMMU_MAX_BUFFERS,
8747 4 + PAGE_SHIFT,
8748 CODEC_MM_FLAGS_CMA_CLEAR |
8749 CODEC_MM_FLAGS_FOR_VDECODER |
8750 tvp_flag);
8751 if (hw->bmmu_box)
8752 ret = 0;
8753 }
8754 return ret;
8755}
8756int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8757{
8758 if (hw->mmu_box) {
8759 decoder_mmu_box_free(hw->mmu_box);
8760 hw->mmu_box = NULL;
8761 }
8762 if (hw->bmmu_box) {
8763 decoder_bmmu_box_free(hw->bmmu_box);
8764 hw->bmmu_box = NULL;
8765 }
8766 return 0;
8767}
8768
8769static int ammvdec_h264_probe(struct platform_device *pdev)
8770{
8771 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8772 struct vdec_h264_hw_s *hw = NULL;
8773 char *tmpbuf;
8774 int config_val;
8775
8776 if (pdata == NULL) {
8777 pr_info("\nammvdec_h264 memory resource undefined.\n");
8778 return -EFAULT;
8779 }
8780
8781 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8782 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8783 if (hw == NULL) {
8784 pr_info("\nammvdec_h264 device data allocation failed\n");
8785 return -ENOMEM;
8786 }
8787 hw->id = pdev->id;
8788 hw->platform_dev = pdev;
8789
8790 /* the ctx from v4l2 driver. */
8791 hw->v4l2_ctx = pdata->private;
8792
8793 platform_set_drvdata(pdev, pdata);
8794
8795 hw->mmu_enable = 0;
8796 hw->first_head_check_flag = 0;
8797 hw->new_iframe_flag = 0;
8798 hw->ref_err_flush_dpb_flag = 0;
8799 hw->wait_reset_done_flag = 0;
8800
8801 if (pdata->sys_info)
8802 hw->vh264_amstream_dec_info = *pdata->sys_info;
8803
8804 if (force_enable_mmu && pdata->sys_info &&
8805 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8806 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8807 (pdata->sys_info->height * pdata->sys_info->width
8808 > 1920 * 1088))
8809 hw->mmu_enable = 1;
8810
8811 if (hw->mmu_enable &&
8812 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8813 hw->mmu_enable = 0;
8814 pr_info("ionvideo needs disable mmu, path= %d \n",
8815 pdata->frame_base_video_path);
8816 }
8817
8818 if (ammvdec_h264_mmu_init(hw)) {
8819 h264_free_hw_stru(&pdev->dev, (void *)hw);
8820 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8821 return -ENOMEM;
8822 }
8823
8824 if (pdata->config_len) {
8825 /*use ptr config for doubel_write_mode, etc*/
8826 if (get_config_int(pdata->config,
8827 "mh264_double_write_mode", &config_val) == 0)
8828 hw->double_write_mode = config_val;
8829 else
8830 hw->double_write_mode = double_write_mode;
8831
8832 if (get_config_int(pdata->config,
8833 "parm_v4l_codec_enable",
8834 &config_val) == 0)
8835 hw->is_used_v4l = config_val;
8836
8837 if (get_config_int(pdata->config,
8838 "parm_v4l_buffer_margin",
8839 &config_val) == 0)
8840 hw->reorder_dpb_size_margin = config_val;
8841
8842 if (get_config_int(pdata->config,
8843 "parm_v4l_canvas_mem_mode",
8844 &config_val) == 0)
8845 hw->canvas_mode = config_val;
8846 } else
8847 hw->double_write_mode = double_write_mode;
8848
8849 if (!hw->is_used_v4l) {
8850 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8851 hw->canvas_mode = mem_map_mode;
8852
8853 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8854 hw->canvas_mode = pdata->canvas_mode;
8855 }
8856
8857 if (hw->mmu_enable)
8858 hw->double_write_mode &= 0xffff;
8859
8860 if (pdata->parallel_dec == 1) {
8861 int i;
8862 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8863 hw->buffer_spec[i].y_canvas_index = -1;
8864 hw->buffer_spec[i].u_canvas_index = -1;
8865 hw->buffer_spec[i].v_canvas_index = -1;
8866#ifdef VDEC_DW
8867 if (IS_VDEC_DW(hw)) {
8868 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8869 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8870 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8871 }
8872#endif
8873 }
8874 }
8875
8876 dpb_print(DECODE_ID(hw), 0,
8877 "%s mmu_enable %d double_write_mode 0x%x\n",
8878 __func__, hw->mmu_enable, hw->double_write_mode);
8879
8880 pdata->private = hw;
8881 pdata->dec_status = dec_status;
8882 pdata->set_trickmode = vmh264_set_trickmode;
8883 pdata->run_ready = run_ready;
8884 pdata->run = run;
8885 pdata->reset = reset;
8886 pdata->irq_handler = vh264_isr;
8887 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8888 pdata->dump_state = vmh264_dump_state;
8889
8890#ifdef MH264_USERDATA_ENABLE
8891 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8892 pdata->user_data_read = vmh264_user_data_read;
8893 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8894#else
8895 pdata->wakeup_userdata_poll = NULL;
8896 pdata->user_data_read = NULL;
8897 pdata->reset_userdata_fifo = NULL;
8898#endif
8899 if (pdata->use_vfm_path) {
8900 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8901 VFM_DEC_PROVIDER_NAME);
8902 hw->frameinfo_enable = 1;
8903 }
8904#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8905 else if (vdec_dual(pdata)) {
8906 if (dv_toggle_prov_name) /*debug purpose*/
8907 snprintf(pdata->vf_provider_name,
8908 VDEC_PROVIDER_NAME_SIZE,
8909 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8910 VFM_DEC_DVEL_PROVIDER_NAME);
8911 else
8912 snprintf(pdata->vf_provider_name,
8913 VDEC_PROVIDER_NAME_SIZE,
8914 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8915 VFM_DEC_DVBL_PROVIDER_NAME);
8916 }
8917#endif
8918 else
8919 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8920 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8921
8922 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8923 &vf_provider_ops, pdata);
8924
8925 platform_set_drvdata(pdev, pdata);
8926
8927 buf_spec_init(hw);
8928
8929 hw->platform_dev = pdev;
8930
8931#ifdef DUMP_USERDATA_RECORD
8932 vmh264_init_userdata_dump();
8933 vmh264_reset_user_data_buf();
8934#endif
8935 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8936 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8937 h264_free_hw_stru(&pdev->dev, (void *)hw);
8938 pdata->dec_status = NULL;
8939 return -ENOMEM;
8940 }
8941
8942 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8943 DCAC_READ_MARGIN;
8944 if (hw->mmu_enable) {
8945 u32 extif_size = EXTIF_BUF_SIZE;
8946 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8947 extif_size <<= 1;
8948 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8949 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8950 h264_free_hw_stru(&pdev->dev, (void *)hw);
8951 pdata->dec_status = NULL;
8952 return -ENOMEM;
8953 }
8954 }
8955 if (!vdec_secure(pdata)) {
8956#if 1
8957 /*init internal buf*/
8958 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8959 if (tmpbuf) {
8960 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8961 codec_mm_dma_flush(tmpbuf,
8962 V_BUF_ADDR_OFFSET,
8963 DMA_TO_DEVICE);
8964 } else {
8965 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8966 V_BUF_ADDR_OFFSET);
8967 if (tmpbuf) {
8968 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8969 codec_mm_dma_flush(tmpbuf,
8970 V_BUF_ADDR_OFFSET,
8971 DMA_TO_DEVICE);
8972 codec_mm_unmap_phyaddr(tmpbuf);
8973 }
8974 }
8975#else
8976 /*init sps/pps internal buf 64k*/
8977 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8978 + (mem_sps_base - DEF_BUF_START_ADDR));
8979 memset(tmpbuf, 0, 0x10000);
8980 dma_sync_single_for_device(amports_get_dma_device(),
8981 hw->cma_alloc_addr +
8982 (mem_sps_base - DEF_BUF_START_ADDR),
8983 0x10000, DMA_TO_DEVICE);
8984#endif
8985 }
8986 /**/
8987
8988#if 0
8989 if (NULL == hw->sei_data_buffer) {
8990 hw->sei_data_buffer =
8991 dma_alloc_coherent(amports_get_dma_device(),
8992 USER_DATA_SIZE,
8993 &hw->sei_data_buffer_phys, GFP_KERNEL);
8994 if (!hw->sei_data_buffer) {
8995 pr_info("%s: Can not allocate sei_data_buffer\n",
8996 __func__);
8997 ammvdec_h264_mmu_release(hw);
8998 h264_free_hw_stru(&pdev->dev, (void *)hw);
8999 return -ENOMEM;
9000 }
9001 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9002 sei_data_buffer, sei_data_buffer_phys,
9003 (u32)sei_data_buffer_remap); */
9004 }
9005#endif
9006 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9007 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9008
9009 if (vdec_is_support_4k() ||
9010 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9011 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9012 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9013 {
9014 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9015 }else
9016 {
9017 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9018 }
9019
9020 if (vh264_init(hw) < 0) {
9021 pr_info("\nammvdec_h264 init failed.\n");
9022 ammvdec_h264_mmu_release(hw);
9023 h264_free_hw_stru(&pdev->dev, (void *)hw);
9024 pdata->dec_status = NULL;
9025 return -ENODEV;
9026 }
9027#ifdef MH264_USERDATA_ENABLE
9028 vmh264_crate_userdata_manager(hw,
9029 hw->sei_user_data_buffer,
9030 USER_DATA_SIZE);
9031#endif
9032
9033 vdec_set_prepare_level(pdata, start_decode_buf_level);
9034 if (pdata->parallel_dec == 1) {
9035 if (hw->mmu_enable == 0)
9036 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9037 else {
9038 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9039 | CORE_MASK_COMBINE);
9040 }
9041 } else
9042 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9043 | CORE_MASK_COMBINE);
9044
9045 atomic_set(&hw->vh264_active, 1);
9046
9047 return 0;
9048}
9049
9050static int ammvdec_h264_remove(struct platform_device *pdev)
9051{
9052 struct vdec_h264_hw_s *hw =
9053 (struct vdec_h264_hw_s *)
9054 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9055 int i;
9056
9057 struct vdec_s *vdec = hw_to_vdec(hw);
9058
9059 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9060 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9061 dpb_print(DECODE_ID(hw), 0,
9062 "%s force exit %d\n", __func__, __LINE__);
9063 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9064 vdec_schedule_work(&hw->work);
9065 wait_event_interruptible_timeout(hw->wait_q,
9066 (vdec->status == VDEC_STATUS_CONNECTED),
9067 msecs_to_jiffies(1000)); /* wait for work done */
9068 }
9069
9070 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9071 release_aux_data(hw, i);
9072
9073 atomic_set(&hw->vh264_active, 0);
9074
9075 if (hw->stat & STAT_TIMER_ARM) {
9076 del_timer_sync(&hw->check_timer);
9077 hw->stat &= ~STAT_TIMER_ARM;
9078 }
9079
9080 vh264_stop(hw);
9081#ifdef MH264_USERDATA_ENABLE
9082#ifdef DUMP_USERDATA_RECORD
9083 vmh264_dump_userdata();
9084#endif
9085 vmh264_destroy_userdata_manager(hw);
9086#endif
9087 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9088
9089 atomic_set(&hw->vh264_active, 0);
9090 if (vdec->parallel_dec == 1) {
9091 if (hw->mmu_enable == 0)
9092 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9093 else
9094 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9095 CORE_MASK_COMBINE);
9096 } else
9097 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9098
9099 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9100 if (vdec->parallel_dec == 1) {
9101 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9102 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9103 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9104 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9105 if (IS_VDEC_DW(hw)) {
9106 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9107 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9108 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9109 }
9110 }
9111 }
9112
9113 ammvdec_h264_mmu_release(hw);
9114 h264_free_hw_stru(&pdev->dev, (void *)hw);
9115 clk_adj_frame_count = 0;
9116
9117 return 0;
9118}
9119
9120/****************************************/
9121#ifdef CONFIG_PM
9122static int mh264_suspend(struct device *dev)
9123{
9124 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9125 return 0;
9126}
9127
9128static int mh264_resume(struct device *dev)
9129{
9130 amvdec_resume(to_platform_device(dev));
9131 return 0;
9132}
9133
9134static const struct dev_pm_ops mh264_pm_ops = {
9135 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9136};
9137#endif
9138
9139static struct platform_driver ammvdec_h264_driver = {
9140 .probe = ammvdec_h264_probe,
9141 .remove = ammvdec_h264_remove,
9142 .driver = {
9143 .name = DRIVER_NAME,
9144#ifdef CONFIG_PM
9145 .pm = &mh264_pm_ops,
9146#endif
9147 }
9148};
9149
9150static struct codec_profile_t ammvdec_h264_profile = {
9151 .name = "mh264",
9152 .profile = ""
9153};
9154
9155static struct mconfig hm264_configs[] = {
9156 MC_PU32("h264_debug_flag", &h264_debug_flag),
9157 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9158 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9159 MC_PU32("decode_timeout_val", &decode_timeout_val),
9160 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9161 MC_PU32("reference_buf_margin", &reference_buf_margin),
9162 MC_PU32("radr", &radr),
9163 MC_PU32("rval", &rval),
9164 MC_PU32("h264_debug_mask", &h264_debug_mask),
9165 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9166 MC_PI32("force_rate_streambase", &force_rate_streambase),
9167 MC_PI32("dec_control", &dec_control),
9168 MC_PI32("force_rate_framebase", &force_rate_framebase),
9169 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9170 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9171 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9172#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9173 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9174 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9175 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9176#endif
9177 MC_PU32("i_only_flag", &i_only_flag),
9178 MC_PU32("force_rate_streambase", &force_rate_streambase),
9179};
9180static struct mconfig_node hm264_node;
9181
9182
9183static int __init ammvdec_h264_driver_init_module(void)
9184{
9185 pr_info("ammvdec_h264 module init\n");
9186 if (platform_driver_register(&ammvdec_h264_driver)) {
9187 pr_info("failed to register ammvdec_h264 driver\n");
9188 return -ENODEV;
9189 }
9190
9191 if (vdec_is_support_4k()) {
9192 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9193 ammvdec_h264_profile.profile =
9194 "4k, dwrite, compressed";
9195 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9196 ammvdec_h264_profile.profile = "4k";
9197 }
9198 }
9199
9200 vcodec_profile_register(&ammvdec_h264_profile);
9201 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9202 "mh264", hm264_configs, CONFIG_FOR_RW);
9203 return 0;
9204}
9205
9206static void __exit ammvdec_h264_driver_remove_module(void)
9207{
9208 pr_info("ammvdec_h264 module remove.\n");
9209
9210 platform_driver_unregister(&ammvdec_h264_driver);
9211}
9212
9213/****************************************/
9214module_param(h264_debug_flag, uint, 0664);
9215MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9216
9217module_param(start_decode_buf_level, int, 0664);
9218MODULE_PARM_DESC(start_decode_buf_level,
9219 "\n ammvdec_h264 start_decode_buf_level\n");
9220
9221module_param(pre_decode_buf_level, int, 0664);
9222MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9223
9224module_param(fixed_frame_rate_mode, uint, 0664);
9225MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9226
9227module_param(decode_timeout_val, uint, 0664);
9228MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9229
9230module_param(errordata_timeout_val, uint, 0664);
9231MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9232
9233module_param(get_data_timeout_val, uint, 0664);
9234MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9235
9236module_param(frame_max_data_packet, uint, 0664);
9237MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9238
9239module_param(reorder_dpb_size_margin, uint, 0664);
9240MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9241
9242#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9243module_param(reorder_dpb_size_margin_dv, uint, 0664);
9244MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9245 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9246#endif
9247
9248module_param(reference_buf_margin, uint, 0664);
9249MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9250
9251#ifdef CONSTRAIN_MAX_BUF_NUM
9252module_param(run_ready_max_vf_only_num, uint, 0664);
9253MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9254
9255module_param(run_ready_display_q_num, uint, 0664);
9256MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9257
9258module_param(run_ready_max_buf_num, uint, 0664);
9259MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9260#endif
9261
9262module_param(radr, uint, 0664);
9263MODULE_PARM_DESC(radr, "\nradr\n");
9264
9265module_param(rval, uint, 0664);
9266MODULE_PARM_DESC(rval, "\nrval\n");
9267
9268module_param(h264_debug_mask, uint, 0664);
9269MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9270
9271module_param(h264_debug_cmd, uint, 0664);
9272MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9273
9274module_param(force_rate_streambase, int, 0664);
9275MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9276
9277module_param(dec_control, int, 0664);
9278MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9279
9280module_param(force_rate_framebase, int, 0664);
9281MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9282
9283module_param(force_disp_bufspec_num, int, 0664);
9284MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9285
9286module_param(V_BUF_ADDR_OFFSET, int, 0664);
9287MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9288
9289module_param(prefix_aux_buf_size, uint, 0664);
9290MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9291
9292module_param(suffix_aux_buf_size, uint, 0664);
9293MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9294
9295#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9296module_param(dv_toggle_prov_name, uint, 0664);
9297MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9298
9299module_param(dolby_meta_with_el, uint, 0664);
9300MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9301
9302#endif
9303
9304module_param(fast_output_enable, uint, 0664);
9305MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9306
9307module_param(error_proc_policy, uint, 0664);
9308MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9309
9310module_param(error_skip_count, uint, 0664);
9311MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9312
9313module_param(force_sliding_margin, uint, 0664);
9314MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9315
9316module_param(i_only_flag, uint, 0664);
9317MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9318
9319module_param(first_i_policy, uint, 0664);
9320MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9321
9322module_param(frmbase_cont_bitlevel, uint, 0664);
9323MODULE_PARM_DESC(frmbase_cont_bitlevel,
9324 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9325
9326module_param(frmbase_cont_bitlevel2, uint, 0664);
9327MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9328 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9329
9330module_param(udebug_flag, uint, 0664);
9331MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9332
9333module_param(udebug_pause_pos, uint, 0664);
9334MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9335
9336module_param(udebug_pause_val, uint, 0664);
9337MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9338
9339module_param(udebug_pause_decode_idx, uint, 0664);
9340MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9341
9342module_param(max_alloc_buf_count, uint, 0664);
9343MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9344
9345module_param(enable_itu_t35, uint, 0664);
9346MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9347
9348module_param(endian, uint, 0664);
9349MODULE_PARM_DESC(endian, "\nrval\n");
9350
9351module_param(mmu_enable, uint, 0664);
9352MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9353
9354module_param(force_enable_mmu, uint, 0664);
9355MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9356
9357module_param(again_threshold, uint, 0664);
9358MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9359
9360module_param(stream_mode_start_num, uint, 0664);
9361MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9362
9363/*
9364module_param(trigger_task, uint, 0664);
9365MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9366*/
9367module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9368
9369module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9370
9371module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9372
9373module_param_array(run_count, uint,
9374 &max_decode_instance_num, 0664);
9375
9376module_param_array(not_run_ready, uint,
9377 &max_decode_instance_num, 0664);
9378
9379module_param_array(input_empty, uint,
9380 &max_decode_instance_num, 0664);
9381
9382module_param_array(max_get_frame_interval, uint,
9383 &max_decode_instance_num, 0664);
9384
9385module_param_array(step, uint, &max_decode_instance_num, 0664);
9386
9387module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9388
9389module_param(disp_vframe_valve_level, uint, 0664);
9390MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9391
9392module_param(double_write_mode, uint, 0664);
9393MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9394
9395module_param(mem_map_mode, uint, 0664);
9396MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9397
9398module_param(without_display_mode, uint, 0664);
9399MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9400
9401
9402module_init(ammvdec_h264_driver_init_module);
9403module_exit(ammvdec_h264_driver_remove_module);
9404
9405MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9406MODULE_LICENSE("GPL");
9407
generated by cgit at 2024-05-17 11:37:48 (GMT)