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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: ddae0c4f9a711c9722c80608108b0bd01c533b16
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120#define INVALID_IDX -1 /* Invalid buffer index.*/
121
122static int mmu_enable;
123/*mmu do not support mbaff*/
124static int force_enable_mmu = 0;
125unsigned int h264_debug_flag; /* 0xa0000000; */
126unsigned int h264_debug_mask = 0xff;
127 /*
128 *h264_debug_cmd:
129 * 0x1xx, force decoder id of xx to be disconnected
130 */
131unsigned int h264_debug_cmd;
132
133static unsigned int dec_control =
134 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
135 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
136
137static unsigned int force_rate_streambase;
138static unsigned int force_rate_framebase;
139static unsigned int force_disp_bufspec_num;
140static unsigned int fixed_frame_rate_mode;
141static unsigned int error_recovery_mode_in;
142static int start_decode_buf_level = 0x4000;
143static int pre_decode_buf_level = 0x1000;
144static int stream_mode_start_num = 4;
145
146#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
147/*to make reorder size difference of bl and el not too big*/
148static unsigned int reorder_dpb_size_margin_dv = 16;
149#endif
150static unsigned int reorder_dpb_size_margin = 6;
151static unsigned int reference_buf_margin = 4;
152
153#ifdef CONSTRAIN_MAX_BUF_NUM
154static u32 run_ready_max_vf_only_num;
155static u32 run_ready_display_q_num;
156 /*0: not check
157 0xff: mDPB.size
158 */
159static u32 run_ready_max_buf_num = 0xff;
160#endif
161
162#define VDEC_ASSIST_CANVAS_BLK32 0x5
163
164
165static unsigned int max_alloc_buf_count;
166static unsigned int decode_timeout_val = 100;
167static unsigned int errordata_timeout_val = 50;
168static unsigned int get_data_timeout_val = 2000;
169#if 1
170/* H264_DATA_REQUEST does not work, disable it,
171decode has error for data in none continuous address
172*/
173static unsigned int frame_max_data_packet;
174#else
175static unsigned int frame_max_data_packet = 8;
176#endif
177static unsigned int radr;
178static unsigned int rval;
179static u32 endian = 0xff0;
180
181/*
182 udebug_flag:
183 bit 0, enable ucode print
184 bit 1, enable ucode detail print
185 bit 3, disable ucode watchdog
186 bit [31:16] not 0, pos to dump lmem
187 bit 2, pop bits to lmem
188 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
189*/
190static u32 udebug_flag;
191/*
192 when udebug_flag[1:0] is not 0
193 udebug_pause_pos not 0,
194 pause position
195*/
196static u32 udebug_pause_pos;
197/*
198 when udebug_flag[1:0] is not 0
199 and udebug_pause_pos is not 0,
200 pause only when DEBUG_REG2 is equal to this val
201*/
202static u32 udebug_pause_val;
203
204static u32 udebug_pause_decode_idx;
205
206static unsigned int disp_vframe_valve_level;
207
208static unsigned int max_decode_instance_num = H264_DEV_NUM;
209static unsigned int decode_frame_count[H264_DEV_NUM];
210static unsigned int display_frame_count[H264_DEV_NUM];
211static unsigned int max_process_time[H264_DEV_NUM];
212static unsigned int max_get_frame_interval[H264_DEV_NUM];
213static unsigned int run_count[H264_DEV_NUM];
214static unsigned int input_empty[H264_DEV_NUM];
215static unsigned int not_run_ready[H264_DEV_NUM];
216static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
217{1, 1, 1, 1, 1, 1, 1, 1, 1};
218
219#define VDEC_CLOCK_ADJUST_FRAME 30
220static unsigned int clk_adj_frame_count;
221
222/*
223 *bit[3:0]: 0, run ; 1, pause; 3, step
224 *bit[4]: 1, schedule run
225 */
226static unsigned int step[H264_DEV_NUM];
227
228#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
229static u32 prefix_aux_buf_size = (16 * 1024);
230static u32 suffix_aux_buf_size;
231
232#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
233static u32 dv_toggle_prov_name;
234
235static u32 dolby_meta_with_el;
236#endif
237
238/*
239 bit[8]
240 0: use sys_info[bit 3]
241 not 0:use i_only_flag[7:0]
242 bit[7:0]:
243 bit 0, 1: only display I picture;
244 bit 1, 1: only decode I picture;
245*/
246static unsigned int i_only_flag;
247
248/*
249 error_proc_policy:
250 bit[0] send_error_frame_flag;
251 (valid when bit[31] is 1, otherwise use sysinfo)
252 bit[1] do not decode if config_decode_buf() fail
253 bit[2] force release buf if in deadlock
254 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
255 bit[4] check inactive of receiver
256 bit[5] reset buffmgr if in deadlock
257 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
258 bit[7] reset buffmgr if dpb error
259
260 bit[8] check total mbx/mby of decoded frame
261 bit[9] check ERROR_STATUS_REG
262 bit[10] check reference list
263 bit[11] mark error if dpb error
264 bit[12] i_only when error happen
265 bit[13] 0: mark error according to last pic, 1: ignore mark error
266 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
267*/
268static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
269
270
271/*
272 error_skip_count:
273 bit[11:0] error skip frame count
274 bit[15:12] error skip i picture count
275*/
276static unsigned int error_skip_count = (0x2 << 12) | 0x40;
277
278static unsigned int force_sliding_margin;
279/*
280 bit[1:0]:
281 0, start playing from any frame
282 1, start playing from I frame
283 bit[15:8]: the count of skip frames after first I
284 2, start playing from second I frame (decode from the first I)
285 bit[15:8]: the max count of skip frames after first I
286 3, start playing from IDR
287*/
288static unsigned int first_i_policy = 1;
289
290/*
291 fast_output_enable:
292 bit [0], output frame if there is IDR in list
293 bit [1], output frame if the current poc is 1 big than the previous poc
294 bit [2], if even poc only, output frame ifthe cuurent poc
295 is 2 big than the previous poc
296 bit [3], ip only
297*/
298static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
299
300static unsigned int enable_itu_t35 = 1;
301
302static unsigned int frmbase_cont_bitlevel = 0x40;
303
304static unsigned int frmbase_cont_bitlevel2 = 0x1;
305
306
307#define MH264_USERDATA_ENABLE
308
309/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
310/* hevc->double_write_mode:
311 0, no double write
312 1, 1:1 ratio
313 2, (1/4):(1/4) ratio
314 3, (1/4):(1/4) ratio, with both compressed frame included
315 4, (1/2):(1/2) ratio
316 0x10, double write only
317 0x10000: vdec dw horizotal 1/2
318 0x20000: vdec dw horizotal/vertical 1/2
319*/
320static u32 double_write_mode;
321static u32 without_display_mode;
322#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
323
324static void vmh264_dump_state(struct vdec_s *vdec);
325
326#define is_in_parsing_state(status) \
327 ((status == H264_ACTION_SEARCH_HEAD) || \
328 ((status & 0xf0) == 0x80))
329
330#define is_interlace(frame) \
331 (frame->frame &&\
332 frame->top_field &&\
333 frame->bottom_field &&\
334 (!frame->frame->coded_frame))
335static inline bool close_to(int a, int b, int m)
336{
337 return (abs(a - b) < m) ? true : false;
338}
339
340#if 0
341#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
342#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
343#else
344#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
345#define h264_free_hw_stru(dev, hw) vfree(hw)
346#endif
347
348/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
349#define NV21
350/* #endif */
351
352/* 12M for L41 */
353#define MAX_DPB_BUFF_SIZE (12*1024*1024)
354#define DEFAULT_MEM_SIZE (32*1024*1024)
355#define AVIL_DPB_BUFF_SIZE 0x01ec2000
356
357#define DEF_BUF_START_ADDR 0x01000000
358#define mem_sps_base 0x011c3c00
359#define mem_pps_base 0x011cbc00
360/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
361u32 V_BUF_ADDR_OFFSET = 0x200000;
362#define DCAC_READ_MARGIN (64 * 1024)
363
364
365#define EXTEND_SAR 0xff
366#define BUFSPEC_POOL_SIZE 64
367#define VF_POOL_SIZE 64
368#define VF_POOL_NUM 2
369#define MAX_VF_BUF_NUM 27
370#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
371#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
372#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
373#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
374#define EXTIF_BUF_SIZE (0x10000 * 2)
375
376#define HEADER_BUFFER_IDX(n) (n)
377#define VF_BUFFER_IDX(n) (n)
378
379
380#define PUT_INTERVAL (HZ/100)
381#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
382
383#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
384#define SWITCHING_STATE_OFF 0
385#define SWITCHING_STATE_ON_CMD3 1
386#define SWITCHING_STATE_ON_CMD1 2
387
388
389
390#define INCPTR(p) ptr_atomic_wrap_inc(&p)
391
392#define SLICE_TYPE_I 2
393#define SLICE_TYPE_P 5
394#define SLICE_TYPE_B 6
395
396struct buffer_spec_s {
397 /*
398 used:
399 -1, none allocated
400 0, allocated, free
401 1, used by dpb
402 2, in disp queue;
403 3, in disp queue, isolated,
404 do not use for dpb when vf_put;
405 4, to release
406 5, in disp queue, isolated (but not to release)
407 do not use for dpb when vf_put;
408 */
409 unsigned int used;
410 unsigned int info0;
411 unsigned int info1;
412 unsigned int info2;
413 unsigned int y_addr;
414 unsigned int u_addr;
415 unsigned int v_addr;
416
417 int y_canvas_index;
418 int u_canvas_index;
419 int v_canvas_index;
420
421#ifdef VDEC_DW
422 unsigned int vdec_dw_y_addr;
423 unsigned int vdec_dw_u_addr;
424 unsigned int vdec_dw_v_addr;
425
426 int vdec_dw_y_canvas_index;
427 int vdec_dw_u_canvas_index;
428 int vdec_dw_v_canvas_index;
429#ifdef NV21
430 struct canvas_config_s vdec_dw_canvas_config[2];
431#else
432 struct canvas_config_s vdec_dw_canvas_config[3];
433#endif
434#endif
435
436#ifdef NV21
437 struct canvas_config_s canvas_config[2];
438#else
439 struct canvas_config_s canvas_config[3];
440#endif
441 unsigned long cma_alloc_addr;
442 unsigned int buf_adr;
443#ifdef H264_MMU
444 unsigned long alloc_header_addr;
445#endif
446 char *aux_data_buf;
447 int aux_data_size;
448#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
449 unsigned char dv_enhance_exist;
450#endif
451 int canvas_pos;
452 int vf_ref;
453 /*unsigned int comp_body_size;*/
454 unsigned int dw_y_adr;
455 unsigned int dw_u_v_adr;
456};
457
458#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
459#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
460#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
461
462
463#define vdec_dw_spec2canvas(x) \
464 (((x)->vdec_dw_v_canvas_index << 16) | \
465 ((x)->vdec_dw_u_canvas_index << 8) | \
466 ((x)->vdec_dw_y_canvas_index << 0))
467
468
469#define spec2canvas(x) \
470 (((x)->v_canvas_index << 16) | \
471 ((x)->u_canvas_index << 8) | \
472 ((x)->y_canvas_index << 0))
473
474#define FRAME_INDEX(vf_index) (vf_index & 0xff)
475#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
476#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
477
478static struct vframe_s *vh264_vf_peek(void *);
479static struct vframe_s *vh264_vf_get(void *);
480static void vh264_vf_put(struct vframe_s *, void *);
481static int vh264_vf_states(struct vframe_states *states, void *);
482static int vh264_event_cb(int type, void *data, void *private_data);
483static void vh264_work(struct work_struct *work);
484static void vh264_timeout_work(struct work_struct *work);
485static void vh264_notify_work(struct work_struct *work);
486#ifdef MH264_USERDATA_ENABLE
487static void user_data_ready_notify_work(struct work_struct *work);
488static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
489#endif
490
491static const char vh264_dec_id[] = "vh264-dev";
492
493#define PROVIDER_NAME "vdec.h264"
494
495static const struct vframe_operations_s vf_provider_ops = {
496 .peek = vh264_vf_peek,
497 .get = vh264_vf_get,
498 .put = vh264_vf_put,
499 .event_cb = vh264_event_cb,
500 .vf_states = vh264_vf_states,
501};
502
503#define DEC_RESULT_NONE 0
504#define DEC_RESULT_DONE 1
505#define DEC_RESULT_AGAIN 2
506#define DEC_RESULT_CONFIG_PARAM 3
507#define DEC_RESULT_GET_DATA 4
508#define DEC_RESULT_GET_DATA_RETRY 5
509#define DEC_RESULT_ERROR 6
510#define DEC_RESULT_EOS 7
511#define DEC_RESULT_FORCE_EXIT 8
512
513/*
514 *static const char *dec_result_str[] = {
515 * "DEC_RESULT_NONE ",
516 * "DEC_RESULT_DONE ",
517 * "DEC_RESULT_AGAIN ",
518 * "DEC_RESULT_CONFIG_PARAM",
519 * "DEC_RESULT_GET_DATA ",
520 * "DEC_RESULT_GET_DA_RETRY",
521 * "DEC_RESULT_ERROR ",
522 *};
523 */
524
525#define UCODE_IP_ONLY 2
526#define UCODE_IP_ONLY_PARAM 1
527
528#define MC_OFFSET_HEADER 0x0000
529#define MC_OFFSET_DATA 0x1000
530#define MC_OFFSET_MMCO 0x2000
531#define MC_OFFSET_LIST 0x3000
532#define MC_OFFSET_SLICE 0x4000
533#define MC_OFFSET_MAIN 0x5000
534
535#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
536#define MC_SWAP_SIZE (4*SZ_1K)
537#define MODE_ERROR 0
538#define MODE_FULL 1
539
540#define DFS_HIGH_THEASHOLD 3
541
542#define INIT_FLAG_REG AV_SCRATCH_2
543#define HEAD_PADING_REG AV_SCRATCH_3
544#define UCODE_WATCHDOG_REG AV_SCRATCH_7
545#define LMEM_DUMP_ADR AV_SCRATCH_L
546#define DEBUG_REG1 AV_SCRATCH_M
547#define DEBUG_REG2 AV_SCRATCH_N
548#define FRAME_COUNTER_REG AV_SCRATCH_I
549#define RPM_CMD_REG AV_SCRATCH_A
550#define H264_DECODE_SIZE AV_SCRATCH_E
551#define H264_DECODE_MODE AV_SCRATCH_4
552#define H264_DECODE_SEQINFO AV_SCRATCH_5
553#define H264_AUX_ADR AV_SCRATCH_C
554#define H264_AUX_DATA_SIZE AV_SCRATCH_H
555
556#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
557#define DPB_STATUS_REG AV_SCRATCH_J
558#define ERROR_STATUS_REG AV_SCRATCH_9
559 /*
560 NAL_SEARCH_CTL: bit 0, enable itu_t35
561 NAL_SEARCH_CTL: bit 1, enable mmu
562 */
563#define NAL_SEARCH_CTL AV_SCRATCH_9
564#define MBY_MBX MB_MOTION_MODE /*0xc07*/
565
566#define DECODE_MODE_SINGLE 0x0
567#define DECODE_MODE_MULTI_FRAMEBASE 0x1
568#define DECODE_MODE_MULTI_STREAMBASE 0x2
569#define DECODE_MODE_MULTI_DVBAL 0x3
570#define DECODE_MODE_MULTI_DVENL 0x4
571static DEFINE_MUTEX(vmh264_mutex);
572
573
574
575#ifdef MH264_USERDATA_ENABLE
576
577struct mh264_userdata_record_t {
578 struct userdata_meta_info_t meta_info;
579 u32 rec_start;
580 u32 rec_len;
581};
582
583struct mh264_ud_record_wait_node_t {
584 struct list_head list;
585 struct mh264_userdata_record_t ud_record;
586};
587#define USERDATA_FIFO_NUM 256
588#define MAX_FREE_USERDATA_NODES 5
589
590struct mh264_userdata_info_t {
591 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
592 u8 *data_buf;
593 u8 *data_buf_end;
594 u32 buf_len;
595 u32 read_index;
596 u32 write_index;
597 u32 last_wp;
598};
599
600
601#endif
602
603struct vdec_h264_hw_s {
604 spinlock_t lock;
605 spinlock_t bufspec_lock;
606 int id;
607 struct platform_device *platform_dev;
608 unsigned long cma_alloc_addr;
609 /* struct page *collocate_cma_alloc_pages; */
610 unsigned long collocate_cma_alloc_addr;
611
612 u32 prefix_aux_size;
613 u32 suffix_aux_size;
614 void *aux_addr;
615 dma_addr_t aux_phy_addr;
616
617 /* buffer for store all sei data */
618 void *sei_data_buf;
619 u32 sei_data_len;
620
621 /* buffer for storing one itu35 recored */
622 void *sei_itu_data_buf;
623 u32 sei_itu_data_len;
624
625 /* recycle buffer for user data storing all itu35 records */
626 void *sei_user_data_buffer;
627 u32 sei_user_data_wp;
628#ifdef MH264_USERDATA_ENABLE
629 struct work_struct user_data_ready_work;
630#endif
631 struct StorablePicture *last_dec_picture;
632
633 ulong lmem_addr;
634 dma_addr_t lmem_addr_remap;
635
636 void *bmmu_box;
637#ifdef H264_MMU
638 void *mmu_box;
639 void *frame_mmu_map_addr;
640 dma_addr_t frame_mmu_map_phy_addr;
641 u32 hevc_cur_buf_idx;
642 u32 losless_comp_body_size;
643 u32 losless_comp_body_size_sao;
644 u32 losless_comp_header_size;
645 u32 mc_buffer_size_u_v;
646 u32 mc_buffer_size_u_v_h;
647 u32 is_idr_frame;
648 u32 is_new_pic;
649 u32 frame_done;
650 u32 frame_busy;
651 unsigned long extif_addr;
652 int double_write_mode;
653 int mmu_enable;
654#endif
655
656 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
657 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
658
659 int cur_pool;
660 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
661 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
662 struct vframe_s switching_fense_vf;
663 struct h264_dpb_stru dpb;
664 u8 init_flag;
665 u8 first_sc_checked;
666 u8 has_i_frame;
667 u8 config_bufmgr_done;
668 u32 max_reference_size;
669 u32 decode_pic_count;
670 u32 reflist_error_count;
671 int start_search_pos;
672 u32 reg_iqidct_control;
673 u32 reg_vcop_ctrl_reg;
674 u32 reg_rv_ai_mb_count;
675 u32 vld_dec_control;
676 struct vframe_s vframe_dummy;
677
678 unsigned char buffer_empty_flag;
679
680 u32 frame_width;
681 u32 frame_height;
682 u32 frame_dur;
683 u32 frame_prog;
684 u32 frame_packing_type;
685
686 struct vframe_chunk_s *chunk;
687
688 u32 stat;
689 unsigned long buf_start;
690 u32 buf_offset;
691 u32 buf_size;
692 /* u32 ucode_map_start; */
693 u32 pts_outside;
694 u32 sync_outside;
695 u32 vh264_ratio;
696 u32 vh264_rotation;
697 u32 use_idr_framerate;
698
699 u32 seq_info;
700 u32 seq_info2;
701 u32 video_signal_from_vui; /*to do .. */
702 u32 timing_info_present_flag;
703 u32 fixed_frame_rate_flag;
704 u32 bitstream_restriction_flag;
705 u32 num_reorder_frames;
706 u32 max_dec_frame_buffering;
707 u32 iframe_count;
708 u32 aspect_ratio_info;
709 u32 num_units_in_tick;
710 u32 time_scale;
711 u32 h264_ar;
712 bool h264_first_valid_pts_ready;
713 u32 h264pts1;
714 u32 h264pts2;
715 u32 pts_duration;
716 u32 h264_pts_count;
717 u32 duration_from_pts_done;
718 u32 pts_unstable;
719 u32 unstable_pts;
720 u32 last_checkout_pts;
721 u32 max_refer_buf;
722
723 s32 vh264_stream_switching_state;
724 struct vframe_s *p_last_vf;
725 u32 last_pts;
726 u32 last_pts_remainder;
727 u32 last_duration;
728 u32 last_mb_width, last_mb_height;
729 bool check_pts_discontinue;
730 bool pts_discontinue;
731 u32 wait_buffer_counter;
732 u32 first_offset;
733 u32 first_pts;
734 u64 first_pts64;
735 bool first_pts_cached;
736 u64 last_pts64;
737#if 0
738 void *sei_data_buffer;
739 dma_addr_t sei_data_buffer_phys;
740#endif
741
742 uint error_recovery_mode;
743 uint mb_total;
744 uint mb_width;
745 uint mb_height;
746
747 uint i_only;
748 int skip_frame_count;
749 bool no_poc_reorder_flag;
750 bool send_error_frame_flag;
751 dma_addr_t mc_dma_handle;
752 void *mc_cpu_addr;
753 int vh264_reset;
754
755 atomic_t vh264_active;
756
757 struct dec_sysinfo vh264_amstream_dec_info;
758
759 int dec_result;
760 struct work_struct work;
761 struct work_struct notify_work;
762 struct work_struct timeout_work;
763 void (*vdec_cb)(struct vdec_s *, void *);
764 void *vdec_cb_arg;
765
766 struct timer_list check_timer;
767
768 /**/
769 unsigned int last_frame_time;
770 u32 vf_pre_count;
771 u32 vf_get_count;
772 u32 vf_put_count;
773
774 /* timeout handle */
775 unsigned long int start_process_time;
776 unsigned int last_mby_mbx;
777 unsigned int last_vld_level;
778 unsigned int decode_timeout_count;
779 unsigned int timeout_num;
780 unsigned int search_dataempty_num;
781 unsigned int decode_timeout_num;
782 unsigned int decode_dataempty_num;
783 unsigned int buffer_empty_recover_num;
784
785 unsigned get_data_count;
786 unsigned get_data_start_time;
787 /**/
788
789 /*log*/
790 unsigned int packet_write_success_count;
791 unsigned int packet_write_EAGAIN_count;
792 unsigned int packet_write_ENOMEM_count;
793 unsigned int packet_write_EFAULT_count;
794 unsigned int total_read_size_pre;
795 unsigned int total_read_size;
796 unsigned int frame_count_pre;
797#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
798 u8 switch_dvlayer_flag;
799 u8 got_valid_nal;
800#endif
801 u8 eos;
802 u8 data_flag;
803 u32 no_error_count;
804 u32 no_error_i_count;
805 /*
806 NODISP_FLAG
807 */
808 u8 dec_flag;
809
810 u32 ucode_pause_pos;
811
812 u8 reset_bufmgr_flag;
813 u32 reset_bufmgr_count;
814 u32 cfg_param1;
815 u32 cfg_param2;
816 u32 cfg_param3;
817 u32 cfg_param4;
818 int valve_count;
819 u8 next_again_flag;
820 u32 pre_parser_wr_ptr;
821 struct firmware_s *fw;
822 struct firmware_s *fw_mmu;
823#ifdef MH264_USERDATA_ENABLE
824 /*user data*/
825 struct mutex userdata_mutex;
826 struct mh264_userdata_info_t userdata_info;
827 struct mh264_userdata_record_t ud_record;
828 int wait_for_udr_send;
829#endif
830 u32 no_mem_count;
831 u32 canvas_mode;
832 bool is_used_v4l;
833 void *v4l2_ctx;
834 bool v4l_params_parsed;
835 wait_queue_head_t wait_q;
836 u32 reg_g_status;
837 struct mutex chunks_mutex;
838 int need_cache_size;
839 u64 sc_start_time;
840 u8 frmbase_cont_flag;
841 struct vframe_qos_s vframe_qos;
842 int frameinfo_enable;
843 bool first_head_check_flag;
844 unsigned int height_aspect_ratio;
845 unsigned int width_aspect_ratio;
846 bool new_iframe_flag;
847 bool ref_err_flush_dpb_flag;
848 unsigned int first_i_policy;
849 u32 reorder_dpb_size_margin;
850 bool wait_reset_done_flag;
851};
852
853static u32 again_threshold;
854
855static void timeout_process(struct vdec_h264_hw_s *hw);
856static void dump_bufspec(struct vdec_h264_hw_s *hw,
857 const char *caller);
858static void h264_reconfig(struct vdec_h264_hw_s *hw);
859static void h264_reset_bufmgr(struct vdec_s *vdec);
860static void vh264_local_init(struct vdec_h264_hw_s *hw);
861static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
862static int vh264_stop(struct vdec_h264_hw_s *hw);
863static s32 vh264_init(struct vdec_h264_hw_s *hw);
864static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
865 u32 index);
866static void release_aux_data(struct vdec_h264_hw_s *hw,
867 int buf_spec_num);
868#ifdef ERROR_HANDLE_TEST
869static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
870#endif
871
872#define H265_PUT_SAO_4K_SET 0x03
873#define H265_ABORT_SAO_4K_SET 0x04
874#define H265_ABORT_SAO_4K_SET_DONE 0x05
875
876#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
877#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
878#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
879#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
880#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
881
882
883#define HEVC_CM_HEADER_START_ADDR 0x3628
884#define HEVC_CM_BODY_START_ADDR 0x3626
885#define HEVC_CM_BODY_LENGTH 0x3627
886#define HEVC_CM_HEADER_LENGTH 0x3629
887#define HEVC_CM_HEADER_OFFSET 0x362b
888#define HEVC_SAO_CTRL9 0x362d
889#define HEVCD_MPP_DECOMP_CTL3 0x34c4
890#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
891#define HEVC_DBLK_CFGB 0x350b
892#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
893
894#define H265_DW_NO_SCALE
895#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
896#define H265_LOSLESS_COMPRESS_MODE
897#define MAX_FRAME_4K_NUM 0x1200
898#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
899
900/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
901static u32 mem_map_mode = H265_MEM_MAP_MODE;
902
903#define MAX_SIZE_8K (8192 * 4608)
904#define MAX_SIZE_4K (4096 * 2304)
905
906static int is_oversize(int w, int h)
907{
908 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
909 MAX_SIZE_8K : MAX_SIZE_4K;
910
911 if (w < 0 || h < 0)
912 return true;
913
914 if (h != 0 && (w > max / h))
915 return true;
916
917 return false;
918}
919
920static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
921 int frame_type,
922 u32 vpts,
923 u32 vpts_valid);
924static int compute_losless_comp_body_size(int width,
925 int height, int bit_depth_10);
926static int compute_losless_comp_header_size(int width, int height);
927
928static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
929 int pic_width, int pic_height, u16 bit_depth,
930 unsigned int *mmu_index_adr) {
931 int cur_buf_idx;
932 int bit_depth_10 = (bit_depth != 0x00);
933 int picture_size;
934 u32 cur_mmu_4k_number;
935
936 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
937 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
938 picture_size = compute_losless_comp_body_size(pic_width,
939 pic_height, bit_depth_10);
940 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
941 dpb_print(DECODE_ID(hw),
942 PRINT_FLAG_MMU_DETAIL,
943 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
944 cur_buf_idx, picture_size, cur_mmu_4k_number);
945
946 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
947 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
948 cur_mmu_4k_number);
949 return -1;
950 }
951
952 return decoder_mmu_box_alloc_idx(
953 hw->mmu_box,
954 cur_buf_idx,
955 cur_mmu_4k_number,
956 mmu_index_adr);
957}
958
959static int compute_losless_comp_body_size(int width,
960 int height, int bit_depth_10)
961{
962 int width_x64;
963 int height_x32;
964 int bsize;
965
966 width_x64 = width + 63;
967 width_x64 >>= 6;
968
969 height_x32 = height + 31;
970 height_x32 >>= 5;
971
972#ifdef H264_MMU
973 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
974#else
975 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
976#endif
977 return bsize;
978}
979
980static int compute_losless_comp_header_size(int width, int height)
981{
982 int width_x64;
983 int width_x128;
984 int height_x64;
985 int hsize;
986
987 width_x64 = width + 63;
988 width_x64 >>= 6;
989
990 width_x128 = width + 127;
991 width_x128 >>= 7;
992
993 height_x64 = height + 63;
994 height_x64 >>= 6;
995
996#ifdef H264_MMU
997 hsize = 128*width_x64*height_x64;
998#else
999 hsize = 32*width_x128*height_x64;
1000#endif
1001 return hsize;
1002}
1003
1004static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1005{
1006 int ratio = 1;
1007 int dw_mode = hw->double_write_mode;
1008 if ((dw_mode == 2) ||
1009 (dw_mode == 3))
1010 ratio = 4;
1011 else if (dw_mode == 4)
1012 ratio = 2;
1013 return ratio;
1014}
1015
1016
1017static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1018{
1019 int pic_width, pic_height;
1020 int lcu_size = 16;
1021 int dw_buf_size;
1022 u32 dw_buffer_size_u_v;
1023 u32 dw_buffer_size_u_v_h;
1024 int dw_mode = hw->double_write_mode;
1025
1026 pic_width = hw->frame_width;
1027 pic_height = hw->frame_height;
1028
1029 if (dw_mode) {
1030 int pic_width_dw = pic_width /
1031 get_double_write_ratio(hw);
1032 int pic_height_dw = pic_height /
1033 get_double_write_ratio(hw);
1034
1035 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1036 pic_width_dw / lcu_size + 1 :
1037 pic_width_dw / lcu_size;
1038 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1039 pic_height_dw / lcu_size + 1 :
1040 pic_height_dw / lcu_size;
1041 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1042
1043
1044 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1045 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1046 /*64k alignment*/
1047 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1048 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1049 } else {
1050 *pdw_buffer_size_u_v_h = 0;
1051 dw_buf_size = 0;
1052 }
1053
1054 return dw_buf_size;
1055}
1056
1057
1058static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1059{
1060 int i, size;
1061 u32 canvas_addr;
1062 unsigned long maddr;
1063 int num_buff = hw->dpb.mDPB.size;
1064 int dw_size = 0;
1065 u32 dw_buffer_size_u_v_h;
1066 u32 blkmode = mem_map_mode;
1067 int dw_mode = hw->double_write_mode;
1068
1069 canvas_addr = ANC0_CANVAS_ADDR;
1070 for (i = 0; i < num_buff; i++)
1071 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1072
1073 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1074 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1075
1076
1077 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1078 size += dw_size;
1079 if (size > 0)
1080 size += 0x10000;
1081
1082 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1083 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1084 dw_buffer_size_u_v_h, dw_size, size);
1085
1086 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1087 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1088 hw->losless_comp_body_size,
1089 hw->losless_comp_header_size,
1090 hw->losless_comp_body_size_sao);
1091
1092 for (i = 0; i < num_buff; i++) {
1093 if (!restore) {
1094 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1095 HEADER_BUFFER_IDX(i), size,
1096 DRIVER_HEADER_NAME, &maddr) < 0) {
1097 dpb_print(DECODE_ID(hw), 0,
1098 "%s malloc compress header failed %d\n",
1099 DRIVER_HEADER_NAME, i);
1100 return;
1101 }
1102 } else
1103 maddr = hw->buffer_spec[i].alloc_header_addr;
1104 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1105 hw->buffer_spec[i].alloc_header_addr = maddr;
1106 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1107 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1108 __func__, i, (u32)maddr, size);
1109
1110 if (dw_mode) {
1111 u32 addr;
1112 int canvas_w;
1113 int canvas_h;
1114
1115 canvas_w = hw->frame_width /
1116 get_double_write_ratio(hw);
1117 canvas_h = hw->frame_height /
1118 get_double_write_ratio(hw);
1119
1120 if (mem_map_mode == 0)
1121 canvas_w = ALIGN(canvas_w, 32);
1122 else
1123 canvas_w = ALIGN(canvas_w, 64);
1124 canvas_h = ALIGN(canvas_h, 32);
1125
1126 hw->buffer_spec[i].dw_y_adr =
1127 maddr + hw->losless_comp_header_size;
1128
1129 hw->buffer_spec[i].dw_y_adr =
1130 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1131 << 16;
1132 hw->buffer_spec[i].dw_u_v_adr =
1133 hw->buffer_spec[i].dw_y_adr
1134 + (dw_buffer_size_u_v_h << 16) * 2;
1135
1136
1137 hw->buffer_spec[i].buf_adr
1138 = hw->buffer_spec[i].dw_y_adr;
1139 addr = hw->buffer_spec[i].buf_adr;
1140
1141
1142 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1143 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1144 hw->buffer_spec[i].dw_y_adr,
1145 hw->buffer_spec[i].dw_u_v_adr,
1146 hw->buffer_spec[i].y_addr,
1147 hw->buffer_spec[i].u_addr,
1148 hw->buffer_spec[i].v_addr,
1149 canvas_w,
1150 canvas_h);
1151
1152 hw->buffer_spec[i].canvas_config[0].phy_addr =
1153 hw->buffer_spec[i].dw_y_adr;
1154 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1155 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1156 hw->buffer_spec[i].canvas_config[0].block_mode =
1157 blkmode;
1158 hw->buffer_spec[i].canvas_config[0].endian = 7;
1159
1160 hw->buffer_spec[i].canvas_config[1].phy_addr =
1161 hw->buffer_spec[i].dw_u_v_adr;
1162 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1163 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1164 hw->buffer_spec[i].canvas_config[1].block_mode =
1165 blkmode;
1166 hw->buffer_spec[i].canvas_config[1].endian = 7;
1167 }
1168 }
1169 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1170
1171 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1172 for (i = 0; i < 32; i++)
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1174 return;
1175}
1176static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1177{
1178 u32 i;
1179 u32 ref_canv;
1180 struct Slice *pSlice = &(hw->dpb.mSlice);
1181 /*REFLIST[0]*/
1182 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1183 struct StorablePicture *ref = pSlice->listX[0][i];
1184 if (ref == NULL)
1185 return;
1186 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1187 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1188 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1189 (ref->buf_spec_num & 0x3f) << 8);
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1191 }
1192 /*REFLIST[1]*/
1193 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1194 struct StorablePicture *ref = pSlice->listX[1][i];
1195 if (ref == NULL)
1196 return;
1197 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1198 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1199 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1200 (ref->buf_spec_num & 0x3f) << 8);
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1202 }
1203 return;
1204}
1205
1206static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1207{
1208 u32 rdata32;
1209 u32 rdata32_2;
1210 u32 slice_type;
1211 struct StorablePicture *ref;
1212 struct Slice *pSlice;
1213 slice_type = hw->dpb.mSlice.slice_type;
1214 pSlice = &(hw->dpb.mSlice);
1215 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1216 if (slice_type == I_SLICE) {
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1218 return;
1219 }
1220 if (slice_type == B_SLICE) {
1221 ref = pSlice->listX[0][0];
1222 if (ref == NULL)
1223 return;
1224 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1225 ((ref->buf_spec_num & 0x3f) << 8));
1226 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1227 rdata32 = rdata32 & 0xffff;
1228 rdata32 = rdata32 | (rdata32 << 16);
1229 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1230
1231 ref = pSlice->listX[1][0];
1232 if (ref == NULL)
1233 return;
1234 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1235 ((ref->buf_spec_num & 0x3f) << 8));
1236 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1237 rdata32_2 = rdata32_2 & 0xffff;
1238 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1239 if (rdata32 == rdata32_2) {
1240 ref = pSlice->listX[1][1];
1241 if (ref == NULL)
1242 return;
1243 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1244 ((ref->buf_spec_num & 0x3f) << 8));
1245 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1246 rdata32_2 = rdata32_2 & 0xffff;
1247 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1248 }
1249 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1250 } else { /*P-PIC*/
1251 ref = pSlice->listX[0][0];
1252 if (ref == NULL)
1253 return;
1254 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1255 ((ref->buf_spec_num & 0x3f) << 8));
1256 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1257 rdata32 = rdata32 & 0xffff;
1258 rdata32 = rdata32 | (rdata32 << 16);
1259 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1260
1261 ref = pSlice->listX[0][1];
1262 if (ref == NULL)
1263 return;
1264 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1265 ((ref->buf_spec_num & 0x3f) << 8));
1266 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1267 rdata32 = rdata32 & 0xffff;
1268 rdata32 = rdata32 | (rdata32 << 16);
1269 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1270 }
1271 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1272 return;
1273}
1274
1275
1276static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1277 u32 width, u32 height) {
1278 u32 data32;
1279 u32 lcu_x_num, lcu_y_num;
1280 u32 lcu_total;
1281 u32 mc_buffer_size_u_v;
1282 u32 mc_buffer_size_u_v_h;
1283 int dw_mode = hw->double_write_mode;
1284
1285 lcu_x_num = (width + 15) >> 4;
1286 lcu_y_num = (height + 15) >> 4;
1287 lcu_total = lcu_x_num * lcu_y_num;
1288
1289 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1290 hw->mc_buffer_size_u_v_h =
1291 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1292
1293 hw->losless_comp_body_size = 0;
1294
1295 hw->losless_comp_body_size_sao =
1296 compute_losless_comp_body_size(width, height, 0);
1297 hw->losless_comp_header_size =
1298 compute_losless_comp_header_size(width, height);
1299
1300 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1301 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1302
1303 /* setup lcu_size = 16*/
1304 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1305 /*pic_width/pic_height*/
1306 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1307 (height & 0xffff) << 16 | (width & 0xffff));
1308 /* bitdepth_luma = 8*/
1309 /* bitdepth_chroma = 8*/
1310 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1311
1312#ifdef H265_LOSLESS_COMPRESS_MODE
1313 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1314 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1315#else
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1317#endif
1318 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1319 data32 &= (~0x30);
1320 data32 |= (mem_map_mode << 4);
1321 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1322
1323 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1324 (0x80 << 20) | (0x80 << 10) | (0xff));
1325
1326 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1327
1328 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1329 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1330 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1331 /* ipp_enable*/
1332 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1333
1334 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1335 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1336 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1337 if (dw_mode)
1338 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1339 else
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1341 }
1342
1343 data32 = READ_VREG(HEVC_SAO_CTRL0);
1344 data32 &= (~0xf);
1345 data32 |= 0x4;
1346 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1347 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1348 (width & 0xffff));
1349 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1350
1351 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1352 data32 = (lcu_x_num | lcu_y_num << 16);
1353 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1354 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1355 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16);
1357 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1358
1359 data32 = READ_VREG(HEVC_SAO_CTRL1);
1360 data32 &= (~0x3000);
1361 data32 &= (~0xff0);
1362 data32 |= endian; /* Big-Endian per 64-bit */
1363
1364 if (hw->mmu_enable && dw_mode)
1365 data32 |= ((mem_map_mode << 12));
1366 else
1367 data32 |= ((mem_map_mode << 12)|2);
1368
1369 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1370
1371#ifdef H265_DW_NO_SCALE
1372 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1373 if (hw->mmu_enable && dw_mode) {
1374 data32 = READ_VREG(HEVC_SAO_CTRL5);
1375 data32 &= (~(0xff << 16));
1376 if (dw_mode == 2 ||
1377 dw_mode == 3)
1378 data32 |= (0xff<<16);
1379 else if (dw_mode == 4)
1380 data32 |= (0x33<<16);
1381 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1382 }
1383
1384
1385#endif
1386
1387
1388#ifdef H265_LOSLESS_COMPRESS_MODE
1389 data32 = READ_VREG(HEVC_SAO_CTRL5);
1390 data32 |= (1<<9); /*8-bit smem-mode*/
1391 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1392
1393 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1394 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1395 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1396#endif
1397
1398#ifdef H265_LOSLESS_COMPRESS_MODE
1399 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1400 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1401#endif
1402
1403 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1404
1405 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1406
1407 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1408 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1409 return;
1410}
1411
1412static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1413 u32 is_new_pic, u32 is_idr)
1414{
1415 hw->is_new_pic = is_new_pic;
1416 hw->is_idr_frame = is_idr;
1417 return;
1418}
1419
1420static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1421 struct StorablePicture *pic) {
1422 u32 mc_y_adr;
1423 u32 mc_u_v_adr;
1424 u32 dw_y_adr;
1425 u32 dw_u_v_adr;
1426 u32 canvas_addr;
1427 int ret;
1428 int dw_mode = hw->double_write_mode;
1429 if (hw->is_new_pic != 1)
1430 return;
1431
1432 if (hw->is_idr_frame) {
1433 /* William TBD */
1434 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1435 }
1436
1437 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1438 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1439 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1440 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1441 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1442 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1443 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1444 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1445 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1446
1447
1448 if (dw_mode) {
1449 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1450 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1451 } else {
1452 dw_y_adr = 0;
1453 dw_u_v_adr = 0;
1454 }
1455#ifdef H265_LOSLESS_COMPRESS_MODE
1456 if (dw_mode)
1457 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1458 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1459#ifdef H264_MMU
1460 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1461#else
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1463 (mc_y_adr + hw->losless_comp_body_size));
1464#endif
1465#else
1466 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1467#endif
1468
1469#ifndef H265_LOSLESS_COMPRESS_MODE
1470 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1471#else
1472 if (dw_mode)
1473 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1474#endif
1475
1476#ifndef LOSLESS_COMPRESS_MODE
1477 if (dw_mode) {
1478 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1479 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1480 }
1481#else
1482 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1483 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1484#endif
1485
1486 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1487 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1488 hw->frame_mmu_map_addr);
1489 if (ret != 0) {
1490 dpb_print(DECODE_ID(hw),
1491 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1492 pic->buf_spec_num,
1493 ret);
1494 return;
1495 }
1496
1497 /*Reset SAO + Enable SAO slice_start*/
1498 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1499 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1500 WRITE_VREG(HEVC_SAO_INT_STATUS,
1501 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1504 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1505 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1506
1507 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1508 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1509 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1510 } else
1511 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1512 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1513 hw->frame_busy = 1;
1514 return;
1515}
1516
1517
1518static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1519 u32 buf_spec_num) {
1520 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1521 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1522 dpb_print(DECODE_ID(hw),
1523 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1524 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1525 return;
1526}
1527
1528
1529static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1530{
1531 ulong timeout = jiffies + HZ;
1532 dpb_print(DECODE_ID(hw),
1533 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1534 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1535 if (time_after(jiffies, timeout)) {
1536 dpb_print(DECODE_ID(hw),
1537 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1538 break;
1539 }
1540 }
1541 timeout = jiffies + HZ;
1542 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1543 if (time_after(jiffies, timeout)) {
1544 dpb_print(DECODE_ID(hw),
1545 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1546 break;
1547 }
1548 }
1549 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1550 hw->frame_done = 1;
1551 return;
1552}
1553
1554static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1555{
1556 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1557 if (p_H264_Dpb->mVideo.dec_picture) {
1558 release_picture(p_H264_Dpb,
1559 p_H264_Dpb->mVideo.dec_picture);
1560 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1561 p_H264_Dpb->mVideo.dec_picture = NULL;
1562 if (hw->mmu_enable)
1563 hevc_set_frame_done(hw);
1564 }
1565}
1566
1567static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1568{
1569 ulong timeout = jiffies + HZ;
1570 dpb_print(DECODE_ID(hw),
1571 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1572 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1573 if (time_after(jiffies, timeout)) {
1574 dpb_print(DECODE_ID(hw),
1575 PRINT_FLAG_MMU_DETAIL,
1576 "hevc_sao_wait_done...wait timeout!\n");
1577 break;
1578 }
1579 }
1580 timeout = jiffies + HZ;
1581 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1582 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1583 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1584 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1585 H265_ABORT_SAO_4K_SET_DONE) {
1586 if (time_after(jiffies, timeout)) {
1587 dpb_print(DECODE_ID(hw),
1588 PRINT_FLAG_MMU_DETAIL,
1589 "wait h265_abort_sao_4k_set_done timeout!\n");
1590 break;
1591 }
1592 }
1593 }
1594 amhevc_stop();
1595 hw->frame_busy = 0;
1596 hw->frame_done = 0;
1597 dpb_print(DECODE_ID(hw),
1598 PRINT_FLAG_MMU_DETAIL,
1599 "sao wait done ,hevc stop!\n");
1600 }
1601 return;
1602}
1603static void buf_spec_init(struct vdec_h264_hw_s *hw)
1604{
1605 int i;
1606 unsigned long flags;
1607 spin_lock_irqsave(&hw->bufspec_lock, flags);
1608 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1609 hw->buffer_spec[i].used = -1;
1610 hw->buffer_spec[i].canvas_pos = -1;
1611 }
1612 if (dpb_is_debug(DECODE_ID(hw),
1613 PRINT_FLAG_DUMP_BUFSPEC))
1614 dump_bufspec(hw, __func__);
1615 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1616}
1617
1618/*is active in buf management */
1619static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1620 int buf_spec_num)
1621{
1622 unsigned char ret = 0;
1623 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1624 hw->buffer_spec[buf_spec_num].used == 2 ||
1625 hw->buffer_spec[buf_spec_num].used == 3 ||
1626 hw->buffer_spec[buf_spec_num].used == 5)
1627 ret = 1;
1628 return ret;
1629}
1630
1631static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1632 int buf_spec_num)
1633{
1634 unsigned char ret = 0;
1635 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1636 hw->buffer_spec[buf_spec_num].used == 3 ||
1637 hw->buffer_spec[buf_spec_num].used == 5)
1638 ret = 1;
1639 return ret;
1640}
1641
1642static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1643{
1644 if (hw->mmu_enable) {
1645 if (hw->buffer_spec[i].alloc_header_addr)
1646 return 0;
1647 else
1648 return -1;
1649 } else {
1650
1651 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1652 int addr;
1653#ifdef VDEC_DW
1654 int orig_buf_size;
1655 orig_buf_size = buf_size;
1656 if (IS_VDEC_DW(hw) == 1)
1657 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1658 else if (IS_VDEC_DW(hw) == 2)
1659 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1660#endif
1661 if (hw->buffer_spec[i].cma_alloc_addr)
1662 return 0;
1663
1664 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1665 PAGE_ALIGN(buf_size), DRIVER_NAME,
1666 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1667 hw->buffer_spec[i].cma_alloc_addr = 0;
1668 if (hw->no_mem_count++ > 3) {
1669 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1670 hw->reset_bufmgr_flag = 1;
1671 }
1672 dpb_print(DECODE_ID(hw), 0,
1673 "%s, fail to alloc buf for bufspec%d, try later\n",
1674 __func__, i
1675 );
1676 return -1;
1677 } else {
1678 hw->no_mem_count = 0;
1679 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1680 }
1681
1682 hw->buffer_spec[i].buf_adr =
1683 hw->buffer_spec[i].cma_alloc_addr;
1684 addr = hw->buffer_spec[i].buf_adr;
1685
1686
1687 hw->buffer_spec[i].y_addr = addr;
1688 addr += hw->mb_total << 8;
1689 hw->buffer_spec[i].u_addr = addr;
1690 hw->buffer_spec[i].v_addr = addr;
1691 addr += hw->mb_total << 7;
1692
1693 hw->buffer_spec[i].canvas_config[0].phy_addr =
1694 hw->buffer_spec[i].y_addr;
1695 hw->buffer_spec[i].canvas_config[0].width =
1696 hw->mb_width << 4;
1697 hw->buffer_spec[i].canvas_config[0].height =
1698 hw->mb_height << 4;
1699 hw->buffer_spec[i].canvas_config[0].block_mode =
1700 hw->canvas_mode;
1701
1702 hw->buffer_spec[i].canvas_config[1].phy_addr =
1703 hw->buffer_spec[i].u_addr;
1704 hw->buffer_spec[i].canvas_config[1].width =
1705 hw->mb_width << 4;
1706 hw->buffer_spec[i].canvas_config[1].height =
1707 hw->mb_height << 3;
1708 hw->buffer_spec[i].canvas_config[1].block_mode =
1709 hw->canvas_mode;
1710 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1711 "%s, alloc buf for bufspec%d\n",
1712 __func__, i
1713 );
1714#ifdef VDEC_DW
1715
1716 if (!IS_VDEC_DW(hw))
1717 return 0;
1718 else if (IS_VDEC_DW(hw) == 1) {
1719 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1720 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1721 addr += hw->mb_total << 7;
1722 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1723 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1724 addr += hw->mb_total << 6;
1725
1726 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1727 hw->buffer_spec[i].vdec_dw_y_addr;
1728 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1729 hw->mb_width << 3;
1730 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1731 hw->mb_height << 4;
1732 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1733 CANVAS_BLKMODE_32X32;
1734
1735 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1736 hw->buffer_spec[i].vdec_dw_u_addr;
1737 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1738 hw->mb_width << 3;
1739 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1740 hw->mb_height << 3;
1741 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1742 CANVAS_BLKMODE_32X32;
1743 }else {
1744 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1745 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1746 addr += hw->mb_total << 6;
1747 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1748 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1749 addr += hw->mb_total << 5;
1750
1751 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1752 hw->buffer_spec[i].vdec_dw_y_addr;
1753 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1754 hw->mb_width << 3;
1755 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1756 hw->mb_height << 3;
1757 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1758 CANVAS_BLKMODE_32X32;
1759
1760 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1761 hw->buffer_spec[i].vdec_dw_u_addr;
1762 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1763 hw->mb_width << 3;
1764 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1765 hw->mb_height << 2;
1766 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1767 CANVAS_BLKMODE_32X32;
1768 }
1769 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1770 "%s, vdec_dw: alloc buf for bufspec%d\n",
1771 __func__, i
1772 );
1773#endif
1774 }
1775 return 0;
1776}
1777
1778static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1779{
1780 int ret = 0;
1781 struct aml_vcodec_ctx *ctx = NULL;
1782 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1783 struct canvas_config_s *y_canvas_cfg = NULL;
1784 struct canvas_config_s *c_canvas_cfg = NULL;
1785 struct vdec_v4l2_buffer *fb = NULL;
1786 unsigned int y_addr = 0, c_addr = 0;
1787
1788 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1789 pr_err("the v4l context has err.\n");
1790 return -1;
1791 }
1792
1793 if (bs->cma_alloc_addr)
1794 return 0;
1795
1796 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1797 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1798 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1799 ctx->id, __func__,
1800 (hw->mb_total << 8) + (hw->mb_total << 7));
1801
1802 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1803 if (ret < 0) {
1804 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1805 "[%d] get fb fail.\n", ctx->id);
1806 return ret;
1807 }
1808
1809 bs->cma_alloc_addr = (unsigned long)fb;
1810 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1811 "[%d] %s(), cma alloc addr: 0x%x\n",
1812 ctx->id, __func__, bs->cma_alloc_addr);
1813
1814 if (fb->num_planes == 1) {
1815 y_addr = fb->m.mem[0].addr;
1816 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1817 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1818 } else if (fb->num_planes == 2) {
1819 y_addr = fb->m.mem[0].addr;
1820 c_addr = fb->m.mem[1].addr;
1821 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1822 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1823 }
1824
1825 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1826 "[%d] %s(), y_addr: %x, size: %u\n",
1827 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1828 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1829 "[%d] %s(), c_addr: %x, size: %u\n",
1830 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1831
1832 bs->y_addr = y_addr;
1833 bs->u_addr = c_addr;
1834 bs->v_addr = c_addr;
1835
1836 y_canvas_cfg = &bs->canvas_config[0];
1837 c_canvas_cfg = &bs->canvas_config[1];
1838
1839 y_canvas_cfg->phy_addr = y_addr;
1840 y_canvas_cfg->width = hw->mb_width << 4;
1841 y_canvas_cfg->height = hw->mb_height << 4;
1842 y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1843 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1844 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1845 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1846 y_canvas_cfg->width,y_canvas_cfg->height);
1847
1848 c_canvas_cfg->phy_addr = c_addr;
1849 c_canvas_cfg->width = hw->mb_width << 4;
1850 c_canvas_cfg->height = hw->mb_height << 3;
1851 c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1852 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1853 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1854 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1855 c_canvas_cfg->width, c_canvas_cfg->height);
1856
1857 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1858 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1859
1860 return ret;
1861}
1862
1863static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1864{
1865 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
1866 int blkmode = CANVAS_BLKMODE_32X32;
1867 int endian = 0;
1868
1869 if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
1870 blkmode = CANVAS_BLKMODE_LINEAR;
1871 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1872 endian = 7;
1873 else
1874 endian = 0;
1875 }
1876
1877 if (hw->is_used_v4l) {
1878 blkmode = CANVAS_BLKMODE_LINEAR;
1879 if (v4l2_ctx->ada_ctx->vfm_path
1880 != FRAME_BASE_PATH_V4L_VIDEO)
1881 endian = 7;
1882 }
1883
1884 canvas_config_ex(hw->buffer_spec[i].
1885 y_canvas_index,
1886 hw->buffer_spec[i].y_addr,
1887 hw->mb_width << 4,
1888 hw->mb_height << 4,
1889 CANVAS_ADDR_NOWRAP,
1890 blkmode,
1891 endian);
1892
1893 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1894 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1895 (1 << 11) | /* canvas_blk32_wr */
1896 (blkmode << 10) | /* canvas_blk32*/
1897 (1 << 8) | /* canvas_index_wr*/
1898 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1899 );
1900 }
1901
1902 canvas_config_ex(hw->buffer_spec[i].
1903 u_canvas_index,
1904 hw->buffer_spec[i].u_addr,
1905 hw->mb_width << 4,
1906 hw->mb_height << 3,
1907 CANVAS_ADDR_NOWRAP,
1908 blkmode,
1909 endian);
1910
1911 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1912 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1913 (1 << 11) |
1914 (blkmode << 10) |
1915 (1 << 8) |
1916 (hw->buffer_spec[i].u_canvas_index << 0));
1917 }
1918
1919 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1920 spec2canvas(&hw->buffer_spec[i]));
1921
1922
1923#ifdef VDEC_DW
1924 if (!IS_VDEC_DW(hw))
1925 return;
1926 else if (IS_VDEC_DW(hw) == 1) {
1927 canvas_config_ex(hw->buffer_spec[i].
1928 vdec_dw_y_canvas_index,
1929 hw->buffer_spec[i].vdec_dw_y_addr,
1930 hw->mb_width << 3,
1931 hw->mb_height << 4,
1932 CANVAS_ADDR_NOWRAP,
1933 blkmode,
1934 endian);
1935 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1936 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1937 (1 << 11) |
1938 (blkmode << 10) |
1939 (1 << 8) |
1940 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1941 }
1942 canvas_config_ex(hw->buffer_spec[i].
1943 vdec_dw_u_canvas_index,
1944 hw->buffer_spec[i].vdec_dw_u_addr,
1945 hw->mb_width << 3,
1946 hw->mb_height << 3,
1947 CANVAS_ADDR_NOWRAP,
1948 blkmode,
1949 endian);
1950 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1951 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1952 (1 << 11) |
1953 (blkmode << 10) |
1954 (1 << 8) |
1955 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1956 }
1957 } else {
1958 canvas_config_ex(hw->buffer_spec[i].
1959 vdec_dw_y_canvas_index,
1960 hw->buffer_spec[i].vdec_dw_y_addr,
1961 hw->mb_width << 3,
1962 hw->mb_height << 3,
1963 CANVAS_ADDR_NOWRAP,
1964 blkmode,
1965 endian);
1966 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1967 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1968 (1 << 11) |
1969 (blkmode << 10) |
1970 (1 << 8) |
1971 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1972 }
1973
1974 canvas_config_ex(hw->buffer_spec[i].
1975 vdec_dw_u_canvas_index,
1976 hw->buffer_spec[i].vdec_dw_u_addr,
1977 hw->mb_width << 3,
1978 hw->mb_height << 2,
1979 CANVAS_ADDR_NOWRAP,
1980 blkmode,
1981 endian);
1982 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1983 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1984 (1 << 11) |
1985 (blkmode << 10) |
1986 (1 << 8) |
1987 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1988 }
1989 }
1990#endif
1991}
1992
1993static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1994{
1995 u32 blkmode = mem_map_mode;
1996 int canvas_w;
1997 int canvas_h;
1998
1999 canvas_w = hw->frame_width /
2000 get_double_write_ratio(hw);
2001 canvas_h = hw->frame_height /
2002 get_double_write_ratio(hw);
2003
2004 if (mem_map_mode == 0)
2005 canvas_w = ALIGN(canvas_w, 32);
2006 else
2007 canvas_w = ALIGN(canvas_w, 64);
2008 canvas_h = ALIGN(canvas_h, 32);
2009
2010 canvas_config_ex(hw->buffer_spec[i].
2011 y_canvas_index,
2012 hw->buffer_spec[i].dw_y_adr,
2013 canvas_w,
2014 canvas_h,
2015 CANVAS_ADDR_NOWRAP,
2016 blkmode,
2017 7);
2018
2019 canvas_config_ex(hw->buffer_spec[i].
2020 u_canvas_index,
2021 hw->buffer_spec[i].dw_u_v_adr,
2022 canvas_w,
2023 canvas_h,
2024 CANVAS_ADDR_NOWRAP,
2025 blkmode,
2026 7);
2027}
2028
2029
2030int get_free_buf_idx(struct vdec_s *vdec)
2031{
2032 int i;
2033 unsigned long addr, flags;
2034 int index = -1;
2035 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2036 int buf_total = BUFSPEC_POOL_SIZE;
2037
2038 if (hw->is_used_v4l)
2039 buf_total = hw->dpb.mDPB.size;
2040
2041 spin_lock_irqsave(&hw->bufspec_lock, flags);
2042 /*hw->start_search_pos = 0;*/
2043 for (i = hw->start_search_pos; i < buf_total; i++) {
2044 if (hw->mmu_enable)
2045 addr = hw->buffer_spec[i].alloc_header_addr;
2046 else {
2047 addr = hw->buffer_spec[i].cma_alloc_addr;
2048 if (hw->is_used_v4l && !addr) {
2049 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2050 config_decode_canvas(hw, i);
2051 addr = hw->buffer_spec[i].cma_alloc_addr;
2052 }
2053 }
2054 }
2055 if (hw->buffer_spec[i].used == 0 && addr) {
2056 hw->buffer_spec[i].used = 1;
2057 hw->start_search_pos = i+1;
2058 index = i;
2059 break;
2060 }
2061 }
2062 if (index < 0) {
2063 for (i = 0; i < hw->start_search_pos; i++) {
2064 if (hw->mmu_enable)
2065 addr = hw->buffer_spec[i].alloc_header_addr;
2066 else {
2067 addr = hw->buffer_spec[i].cma_alloc_addr;
2068 if (hw->is_used_v4l && !addr) {
2069 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2070 config_decode_canvas(hw, i);
2071 addr = hw->buffer_spec[i].cma_alloc_addr;
2072 }
2073 }
2074 }
2075 if (hw->buffer_spec[i].used == 0 && addr) {
2076 hw->buffer_spec[i].used = 1;
2077 hw->start_search_pos = i+1;
2078 index = i;
2079 break;
2080 }
2081 }
2082 }
2083 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2084 if (hw->start_search_pos >= buf_total)
2085 hw->start_search_pos = 0;
2086 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2087 "%s, buf_spec_num %d\n", __func__, index);
2088
2089 if (index < 0) {
2090 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2091 "%s fail\n", __func__);
2092 vmh264_dump_state(vdec);
2093 }
2094
2095 if (dpb_is_debug(DECODE_ID(hw),
2096 PRINT_FLAG_DUMP_BUFSPEC))
2097 dump_bufspec(hw, __func__);
2098 return index;
2099}
2100
2101int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2102{
2103 /*u32 cur_buf_idx;*/
2104 unsigned long flags;
2105 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2106 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2107 "%s buf_spec_num %d used %d\n",
2108 __func__, buf_spec_num,
2109 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2110 if (buf_spec_num >= 0 &&
2111 buf_spec_num < BUFSPEC_POOL_SIZE
2112 ) {
2113 spin_lock_irqsave(&hw->bufspec_lock, flags);
2114 hw->buffer_spec[buf_spec_num].used = 0;
2115 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2116 if (hw->mmu_enable) {
2117 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2118 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2119 cur_buf_idx = cur_buf_idx&0xff;*/
2120 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2121 }
2122 release_aux_data(hw, buf_spec_num);
2123 }
2124 if (dpb_is_debug(DECODE_ID(hw),
2125 PRINT_FLAG_DUMP_BUFSPEC))
2126 dump_bufspec(hw, __func__);
2127 return 0;
2128}
2129
2130static void config_buf_specs(struct vdec_s *vdec)
2131{
2132 int i, j;
2133 unsigned long flags;
2134 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2135 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2136
2137 spin_lock_irqsave(&hw->bufspec_lock, flags);
2138 for (i = 0, j = 0;
2139 j < hw->dpb.mDPB.size
2140 && i < BUFSPEC_POOL_SIZE;
2141 i++) {
2142 int canvas;
2143 if (hw->buffer_spec[i].used != -1)
2144 continue;
2145 if (vdec->parallel_dec == 1) {
2146 if (hw->buffer_spec[i].y_canvas_index == -1)
2147 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2148 if (hw->buffer_spec[i].u_canvas_index == -1) {
2149 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2150 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2151 }
2152#ifdef VDEC_DW
2153 if (IS_VDEC_DW(hw)) {
2154 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2155 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2156 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2157 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2158 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2159 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2160 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2161 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2162 }
2163 }
2164#endif
2165 } else {
2166 canvas = vdec->get_canvas(j * mode, 2);
2167 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2168 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2169 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2170 dpb_print(DECODE_ID(hw),
2171 PRINT_FLAG_DPB_DETAIL,
2172 "config canvas (%d) %x for bufspec %d\r\n",
2173 j, canvas, i);
2174#ifdef VDEC_DW
2175 if (IS_VDEC_DW(hw)) {
2176 canvas = vdec->get_canvas(j * mode + 1, 2);
2177 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2178 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2179 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2180 dpb_print(DECODE_ID(hw),
2181 PRINT_FLAG_DPB_DETAIL,
2182 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2183 j, canvas, i);
2184 }
2185#endif
2186 }
2187
2188 hw->buffer_spec[i].used = 0;
2189 hw->buffer_spec[i].canvas_pos = j;
2190
2191
2192 j++;
2193 }
2194 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2195}
2196
2197static void config_buf_specs_ex(struct vdec_s *vdec)
2198{
2199 int i, j;
2200 unsigned long flags;
2201 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2202 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2203
2204 spin_lock_irqsave(&hw->bufspec_lock, flags);
2205 for (i = 0, j = 0;
2206 j < hw->dpb.mDPB.size
2207 && i < BUFSPEC_POOL_SIZE;
2208 i++) {
2209 int canvas = 0;
2210 if (hw->buffer_spec[i].used != -1)
2211 continue;
2212 if (vdec->parallel_dec == 1) {
2213 if (hw->buffer_spec[i].y_canvas_index == -1)
2214 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2215 if (hw->buffer_spec[i].u_canvas_index == -1) {
2216 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2217 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2218 }
2219#ifdef VDEC_DW
2220 if (IS_VDEC_DW(hw)) {
2221 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2222 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2223 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2224 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2225 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2226 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2227 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2228 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2229 }
2230 }
2231#endif
2232 } else {
2233 canvas = vdec->get_canvas(j* mode, 2);
2234 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2235 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2236 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2237
2238 dpb_print(DECODE_ID(hw),
2239 PRINT_FLAG_DPB_DETAIL,
2240 "config canvas (%d) %x for bufspec %d\r\n",
2241 j, canvas, i);
2242#ifdef VDEC_DW
2243 if (IS_VDEC_DW(hw)) {
2244 canvas = vdec->get_canvas(j*mode + 1, 2);
2245 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2246 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2247 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2248 dpb_print(DECODE_ID(hw),
2249 PRINT_FLAG_DPB_DETAIL,
2250 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2251 j, canvas, i);
2252 }
2253#endif
2254 }
2255
2256 hw->buffer_spec[i].used = 0;
2257 hw->buffer_spec[i].alloc_header_addr = 0;
2258 hw->buffer_spec[i].canvas_pos = j;
2259
2260 j++;
2261 }
2262 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2263}
2264
2265
2266static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2267 unsigned char release_all)
2268{
2269 int i;
2270 unsigned long flags;
2271 unsigned char dealloc_flag = 0;
2272 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2273 if (hw->buffer_spec[i].used == 4 ||
2274 release_all) {
2275 dealloc_flag = 1;
2276 dpb_print(DECODE_ID(hw),
2277 PRINT_FLAG_DPB_DETAIL,
2278 "%s buf_spec_num %d\n",
2279 __func__, i
2280 );
2281 spin_lock_irqsave
2282 (&hw->bufspec_lock, flags);
2283 hw->buffer_spec[i].used = -1;
2284 spin_unlock_irqrestore
2285 (&hw->bufspec_lock, flags);
2286 release_aux_data(hw, i);
2287
2288 if (!hw->mmu_enable) {
2289 if (hw->buffer_spec[i].cma_alloc_addr) {
2290 if (!hw->is_used_v4l) {
2291 decoder_bmmu_box_free_idx(
2292 hw->bmmu_box,
2293 i);
2294 }
2295 spin_lock_irqsave
2296 (&hw->bufspec_lock, flags);
2297 hw->buffer_spec[i].cma_alloc_addr = 0;
2298 hw->buffer_spec[i].buf_adr = 0;
2299 spin_unlock_irqrestore
2300 (&hw->bufspec_lock, flags);
2301 }
2302 } else {
2303 if (hw->buffer_spec[i].alloc_header_addr) {
2304 decoder_mmu_box_free_idx(
2305 hw->mmu_box,
2306 i);
2307 spin_lock_irqsave
2308 (&hw->bufspec_lock, flags);
2309 hw->buffer_spec[i].
2310 alloc_header_addr = 0;
2311 hw->buffer_spec[i].buf_adr = 0;
2312 spin_unlock_irqrestore
2313 (&hw->bufspec_lock, flags);
2314 }
2315 }
2316 }
2317 }
2318 if (dealloc_flag &&
2319 dpb_is_debug(DECODE_ID(hw),
2320 PRINT_FLAG_DUMP_BUFSPEC))
2321 dump_bufspec(hw, __func__);
2322 return;
2323}
2324
2325unsigned char have_free_buf_spec(struct vdec_s *vdec)
2326{
2327 int i;
2328 unsigned long addr;
2329 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2330 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2331 int index = -1;
2332 int ret = 0;
2333 int allocated_count = 0;
2334 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2335 if (hw->mmu_enable)
2336 addr = hw->buffer_spec[i].alloc_header_addr;
2337 else
2338 addr = hw->buffer_spec[i].cma_alloc_addr;
2339 if (hw->buffer_spec[i].used == 0) {
2340
2341 if (addr)
2342 return 1;
2343 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2344 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2345 index = i;
2346 }
2347 }
2348 if (addr)
2349 allocated_count++;
2350 }
2351 if (index >= 0) {
2352 mutex_lock(&vmh264_mutex);
2353 dealloc_buf_specs(hw, 0);
2354 if (max_alloc_buf_count == 0 ||
2355 allocated_count < max_alloc_buf_count) {
2356 if (hw->is_used_v4l)
2357 ret = 1;
2358 else if (alloc_one_buf_spec(hw, index) >= 0)
2359 ret = 1;
2360 }
2361 mutex_unlock(&vmh264_mutex);
2362 }
2363 return ret;
2364}
2365
2366static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2367 int canvas_pos)
2368{
2369 int i;
2370 int j = 0;
2371 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2372 if (hw->buffer_spec[i].canvas_pos >= 0) {
2373 if (j == canvas_pos)
2374 return i;
2375 j++;
2376 }
2377 }
2378 return -1;
2379}
2380static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2381 struct vframe_s *vf, int index)
2382{
2383 if (index < 0) {
2384 vf->mem_handle = NULL;
2385 vf->mem_head_handle = NULL;
2386 } else if (vf->type & VIDTYPE_SCATTER) {
2387 vf->mem_handle =
2388 decoder_mmu_box_get_mem_handle(
2389 hw->mmu_box, index);
2390 vf->mem_head_handle =
2391 decoder_bmmu_box_get_mem_handle(
2392 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2393 } else {
2394 vf->mem_handle =
2395 decoder_bmmu_box_get_mem_handle(
2396 hw->bmmu_box, VF_BUFFER_IDX(index));
2397 /* vf->mem_head_handle =
2398 decoder_bmmu_box_get_mem_handle(
2399 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2400 }
2401 return;
2402}
2403static int check_force_interlace(struct vdec_h264_hw_s *hw,
2404 struct FrameStore *frame)
2405{
2406 int bForceInterlace = 0;
2407 /* no di in secure mode, disable force di */
2408 if (vdec_secure(hw_to_vdec(hw)))
2409 return 0;
2410 if (frame->frame) {
2411 if (frame->frame->coded_frame
2412 && !frame->frame->frame_mbs_only_flag) {
2413 if (frame->frame->structure == FRAME)
2414 return 1;
2415 }
2416 }
2417
2418 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2419 && hw->bitstream_restriction_flag
2420 && (hw->frame_width == 1920)
2421 && (hw->frame_height >= 1080)
2422 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2423 bForceInterlace = 1;
2424 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2425 && (hw->frame_width == 720)
2426 && (hw->frame_height == 576)
2427 && (hw->frame_dur == 3840)) {
2428 bForceInterlace = 1;
2429 }
2430
2431 return bForceInterlace;
2432}
2433
2434static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2435{
2436 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2437 if (frame->slice_type == I_SLICE)
2438 vframe_qos->type = 1;
2439 else if (frame->slice_type == P_SLICE)
2440 vframe_qos->type = 2;
2441 else if (frame->slice_type == B_SLICE)
2442 vframe_qos->type = 3;
2443
2444 vframe_qos->size = frame->frame_size;
2445 vframe_qos->pts = frame->pts64;
2446
2447 vframe_qos->max_mv = frame->max_mv;
2448 vframe_qos->avg_mv = frame->avg_mv;
2449 vframe_qos->min_mv = frame->min_mv;
2450/*
2451 pr_info("mv: max:%d, avg:%d, min:%d\n",
2452 vframe_qos->max_mv,
2453 vframe_qos->avg_mv,
2454 vframe_qos->min_mv);
2455*/
2456
2457 vframe_qos->max_qp = frame->max_qp;
2458 vframe_qos->avg_qp = frame->avg_qp;
2459 vframe_qos->min_qp = frame->min_qp;
2460/*
2461 pr_info("qp: max:%d, avg:%d, min:%d\n",
2462 vframe_qos->max_qp,
2463 vframe_qos->avg_qp,
2464 vframe_qos->min_qp);
2465*/
2466
2467 vframe_qos->max_skip = frame->max_skip;
2468 vframe_qos->avg_skip = frame->avg_skip;
2469 vframe_qos->min_skip = frame->min_skip;
2470/*
2471 pr_info("skip: max:%d, avg:%d, min:%d\n",
2472 vframe_qos->max_skip,
2473 vframe_qos->avg_skip,
2474 vframe_qos->min_skip);
2475*/
2476 vframe_qos->num++;
2477 if (hw->frameinfo_enable)
2478 vdec_fill_frame_info(vframe_qos, 1);
2479}
2480
2481static int is_iframe(struct FrameStore *frame) {
2482
2483 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2484 return 1;
2485 }
2486 return 0;
2487}
2488
2489
2490
2491int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2492{
2493 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2494 struct vframe_s *vf = NULL;
2495 int buffer_index = frame->buf_spec_num;
2496 int vf_count = 1;
2497 int i;
2498 int bForceInterlace = 0;
2499
2500 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2501 dpb_print(DECODE_ID(hw), 0,
2502 "%s, buffer_index 0x%x is beyond range\n",
2503 __func__, buffer_index);
2504 return -1;
2505 }
2506 if (force_disp_bufspec_num & 0x100) {
2507 /*recycle directly*/
2508 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2509 hw->buffer_spec[frame->buf_spec_num].used != 5)
2510 set_frame_output_flag(&hw->dpb, frame->index);
2511
2512 /*make pre_output not set*/
2513 return -1;
2514 }
2515 if (error_proc_policy & 0x1000) {
2516 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2517 int error_skip_frame_count = error_skip_count & 0xfff;
2518 if (((hw->no_error_count < error_skip_frame_count)
2519 && (error_skip_i_count == 0 ||
2520 hw->no_error_i_count < error_skip_i_count))
2521 && (!(frame->data_flag & I_FLAG)))
2522 frame->data_flag |= ERROR_FLAG;
2523 }
2524 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2525 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2526 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2527 frame->poc, hw->data_flag & ERROR_FLAG,
2528 error_proc_policy);
2529 if (frame->frame == NULL &&
2530 ((frame->is_used == 1 && frame->top_field)
2531 || (frame->is_used == 2 && frame->bottom_field))) {
2532 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2533 "%s Error frame_num %d used %d\n",
2534 __func__, frame->frame_num, frame->is_used);
2535 frame->data_flag |= ERROR_FLAG;
2536 }
2537 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2538 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2539 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2540 0, &frame->pts64) == 0)) {
2541 hw->last_pts64 = frame->pts64;
2542 hw->last_pts = frame->pts;
2543 } else {
2544 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2545 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2546 }
2547 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2548 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2549 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2550 frame->offset_delimiter, frame->pts,hw->last_pts,
2551 frame->pts64, hw->last_pts64, hw->frame_dur);
2552 hw->last_pts64 = frame->pts64;
2553 hw->last_pts = frame->pts;
2554 }
2555 if ((frame->data_flag & NODISP_FLAG) ||
2556 (frame->data_flag & NULL_FLAG) ||
2557 ((!hw->send_error_frame_flag) &&
2558 (frame->data_flag & ERROR_FLAG)) ||
2559 ((hw->i_only & 0x1) &&
2560 (!(frame->data_flag & I_FLAG)))
2561 ) {
2562 set_frame_output_flag(&hw->dpb, frame->index);
2563 return 0; /*do not return -1,
2564 otherwise flush_dpb() will not flush all dbp frames*/
2565 }
2566
2567 display_frame_count[DECODE_ID(hw)]++;
2568
2569 if (dpb_is_debug(DECODE_ID(hw),
2570 PRINT_FLAG_DPB_DETAIL)) {
2571 dpb_print(DECODE_ID(hw), 0,
2572 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2573 __func__, frame->index, frame->poc,
2574 frame->buf_spec_num);
2575 print_pic_info(DECODE_ID(hw), "predis_frm",
2576 frame->frame, -1);
2577 print_pic_info(DECODE_ID(hw), "predis_top",
2578 frame->top_field, -1);
2579 print_pic_info(DECODE_ID(hw), "predis_bot",
2580 frame->bottom_field, -1);
2581 }
2582
2583 if (!is_interlace(frame))
2584 vf_count = 1;
2585 else
2586 vf_count = 2;
2587 bForceInterlace = check_force_interlace(hw, frame);
2588 if (bForceInterlace)
2589 vf_count = 2;
2590 hw->buffer_spec[buffer_index].vf_ref = 0;
2591 fill_frame_info(hw, frame);
2592 for (i = 0; i < vf_count; i++) {
2593 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2594 vf == NULL) {
2595 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2596 "%s fatal error, no available buffer slot.\n",
2597 __func__);
2598 return -1;
2599 }
2600 vf->duration_pulldown = 0;
2601 if (!(is_iframe(frame)) && hw->unstable_pts) {
2602 vf->pts = 0;
2603 vf->pts_us64 = 0;
2604 vf->timestamp = 0;
2605 vf->index = VF_INDEX(frame->index, buffer_index);
2606 } else {
2607 vf->pts = frame->pts;
2608 vf->pts_us64 = frame->pts64;
2609 vf->timestamp = frame->timestamp;
2610 vf->index = VF_INDEX(frame->index, buffer_index);
2611 }
2612
2613 if (hw->is_used_v4l) {
2614 vf->v4l_mem_handle
2615 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2616 }
2617
2618 if (hw->mmu_enable) {
2619 if (hw->double_write_mode & 0x10) {
2620 /* double write only */
2621 vf->compBodyAddr = 0;
2622 vf->compHeadAddr = 0;
2623 } else {
2624 /*head adr*/
2625 vf->compHeadAddr =
2626 hw->buffer_spec[buffer_index].alloc_header_addr;
2627 /*body adr*/
2628 vf->compBodyAddr = 0;
2629 vf->canvas0Addr = vf->canvas1Addr = 0;
2630 }
2631
2632 vf->type = VIDTYPE_SCATTER;
2633
2634 if (hw->double_write_mode) {
2635 vf->type |= VIDTYPE_PROGRESSIVE
2636 | VIDTYPE_VIU_FIELD;
2637 vf->type |= VIDTYPE_VIU_NV21;
2638 if (hw->double_write_mode == 3)
2639 vf->type |= VIDTYPE_COMPRESS;
2640
2641 vf->canvas0Addr = vf->canvas1Addr = -1;
2642 vf->plane_num = 2;
2643 vf->canvas0_config[0] =
2644 hw->buffer_spec[buffer_index].
2645 canvas_config[0];
2646 vf->canvas0_config[1] =
2647 hw->buffer_spec[buffer_index].
2648 canvas_config[1];
2649
2650 vf->canvas1_config[0] =
2651 hw->buffer_spec[buffer_index].
2652 canvas_config[0];
2653 vf->canvas1_config[1] =
2654 hw->buffer_spec[buffer_index].
2655 canvas_config[1];
2656
2657 } else {
2658 vf->type |=
2659 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2660 vf->canvas0Addr = vf->canvas1Addr = 0;
2661 }
2662
2663 vf->bitdepth =
2664 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2665
2666 vf->compWidth = hw->frame_width;
2667 vf->compHeight = hw->frame_height;
2668 } else {
2669 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2670 VIDTYPE_VIU_NV21;
2671
2672 vf->canvas0Addr = vf->canvas1Addr =
2673 spec2canvas(&hw->buffer_spec[buffer_index]);
2674#ifdef VDEC_DW
2675 if (IS_VDEC_DW(hw))
2676 vf->canvas0Addr = vf->canvas1Addr =
2677 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2678#endif
2679
2680 }
2681 set_frame_info(hw, vf, buffer_index);
2682
2683 if (hw->mmu_enable && hw->double_write_mode) {
2684 vf->width = hw->frame_width /
2685 get_double_write_ratio(hw);
2686 vf->height = hw->frame_height /
2687 get_double_write_ratio(hw);
2688 }
2689
2690 vf->flag = 0;
2691 if (frame->data_flag & I_FLAG)
2692 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2693 if (frame->data_flag & ERROR_FLAG)
2694 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2695 update_vf_memhandle(hw, vf, buffer_index);
2696 hw->buffer_spec[buffer_index].used = 2;
2697 hw->buffer_spec[buffer_index].vf_ref++;
2698
2699 if (bForceInterlace || is_interlace(frame)) {
2700 vf->type =
2701 VIDTYPE_INTERLACE_FIRST |
2702 VIDTYPE_VIU_NV21;
2703
2704 if (bForceInterlace) {
2705 vf->type |= (i == 0 ?
2706 VIDTYPE_INTERLACE_TOP :
2707 VIDTYPE_INTERLACE_BOTTOM);
2708 if (i == 1) {
2709 vf->pts = 0;
2710 vf->pts_us64 = 0;
2711 }
2712 } else if (frame->top_field->poc <=
2713 frame->bottom_field->poc) /*top first*/
2714 vf->type |= (i == 0 ?
2715 VIDTYPE_INTERLACE_TOP :
2716 VIDTYPE_INTERLACE_BOTTOM);
2717 else
2718 vf->type |= (i == 0 ?
2719 VIDTYPE_INTERLACE_BOTTOM :
2720 VIDTYPE_INTERLACE_TOP);
2721 vf->duration = vf->duration/2;
2722 }
2723
2724 if (i == 0)
2725 decoder_do_frame_check(hw_to_vdec(hw), vf);
2726
2727 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2728 vf->sar_width = hw->width_aspect_ratio;
2729 vf->sar_height = hw->height_aspect_ratio;
2730
2731 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2732 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2733 hw->vf_pre_count++;
2734 vdec->vdec_fps_detec(vdec->id);
2735 if (without_display_mode == 0) {
2736 vf_notify_receiver(vdec->vf_provider_name,
2737 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2738 } else
2739 vh264_vf_put(vh264_vf_get(vdec), vdec);
2740 }
2741 if (dpb_is_debug(DECODE_ID(hw),
2742 PRINT_FLAG_DUMP_BUFSPEC))
2743 dump_bufspec(hw, __func__);
2744
2745 return 0;
2746}
2747
2748int notify_v4l_eos(struct vdec_s *vdec)
2749{
2750 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2751 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2752 struct vframe_s *vf = &hw->vframe_dummy;
2753 struct vdec_v4l2_buffer *fb = NULL;
2754 int index = INVALID_IDX;
2755 ulong expires;
2756
2757 if (hw->is_used_v4l && hw->eos) {
2758 expires = jiffies + msecs_to_jiffies(2000);
2759 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2760 if (time_after(jiffies, expires))
2761 break;
2762 }
2763
2764 if (index == INVALID_IDX) {
2765 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2766 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2767 return -1;
2768 }
2769 }
2770
2771 vf->type |= VIDTYPE_V4L_EOS;
2772 vf->timestamp = ULONG_MAX;
2773 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2774 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2775 hw->buffer_spec[index].cma_alloc_addr;
2776
2777 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2778
2779 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2780 vf_notify_receiver(vdec->vf_provider_name,
2781 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2782
2783 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2784 }
2785
2786 return 0;
2787}
2788
2789/******************
2790 * Hardware config
2791 */
2792char *slice_type_name[] = {
2793 "P_SLICE ",
2794 "B_SLICE ",
2795 "I_SLICE ",
2796 "SP_SLICE",
2797 "SI_SLICE",
2798};
2799
2800char *picture_structure_name[] = {
2801 "FRAME",
2802 "TOP_FIELD",
2803 "BOTTOM_FIELD"
2804};
2805
2806void print_pic_info(int decindex, const char *info,
2807 struct StorablePicture *pic,
2808 int slice_type)
2809{
2810 if (pic)
2811 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2812 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2813 info,
2814 picture_structure_name[pic->structure],
2815 pic->coded_frame ? "Frame" : "Field",
2816 (slice_type < 0 ||
2817 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2818 pic->mb_aff_frame_flag,
2819 pic->poc,
2820 pic->pic_num,
2821 pic->buf_spec_num,
2822 pic->data_flag);
2823}
2824
2825static void reset_process_time(struct vdec_h264_hw_s *hw)
2826{
2827 if (hw->start_process_time) {
2828 unsigned process_time =
2829 1000 * (jiffies - hw->start_process_time) / HZ;
2830 hw->start_process_time = 0;
2831 if (process_time > max_process_time[DECODE_ID(hw)])
2832 max_process_time[DECODE_ID(hw)] = process_time;
2833 }
2834}
2835
2836static void start_process_time(struct vdec_h264_hw_s *hw)
2837{
2838 hw->decode_timeout_count = 10;
2839 hw->start_process_time = jiffies;
2840}
2841
2842static void config_aux_buf(struct vdec_h264_hw_s *hw)
2843{
2844 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2845 WRITE_VREG(H264_AUX_DATA_SIZE,
2846 ((hw->prefix_aux_size >> 4) << 16) |
2847 (hw->suffix_aux_size >> 4)
2848 );
2849}
2850
2851/*
2852* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2853*/
2854static void set_aux_data(struct vdec_h264_hw_s *hw,
2855 struct StorablePicture *pic, unsigned char suffix_flag,
2856 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2857{
2858 int i;
2859 unsigned short *aux_adr;
2860 unsigned size_reg_val =
2861 READ_VREG(H264_AUX_DATA_SIZE);
2862 unsigned aux_count = 0;
2863 int aux_size = 0;
2864 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2865 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2866 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2867 return;
2868
2869 if (suffix_flag) {
2870 aux_adr = (unsigned short *)
2871 (hw_buf->aux_addr +
2872 hw_buf->prefix_aux_size);
2873 aux_count =
2874 ((size_reg_val & 0xffff) << 4)
2875 >> 1;
2876 aux_size =
2877 hw_buf->suffix_aux_size;
2878 } else {
2879 aux_adr =
2880 (unsigned short *)hw_buf->aux_addr;
2881 aux_count =
2882 ((size_reg_val >> 16) << 4)
2883 >> 1;
2884 aux_size =
2885 hw_buf->prefix_aux_size;
2886 }
2887 if (dpb_is_debug(DECODE_ID(hw),
2888 PRINT_FLAG_DPB_DETAIL)) {
2889 dpb_print(DECODE_ID(hw), 0,
2890 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2891 __func__, AUX_DATA_SIZE(pic),
2892 aux_count, suffix_flag, dv_meta_flag);
2893 }
2894 if (aux_size > 0 && aux_count > 0) {
2895 int heads_size = 0;
2896 int new_size;
2897 char *new_buf;
2898 for (i = 0; i < aux_count; i++) {
2899 unsigned char tag = aux_adr[i] >> 8;
2900 if (tag != 0 && tag != 0xff) {
2901 if (dv_meta_flag == 0)
2902 heads_size += 8;
2903 else if (dv_meta_flag == 1 && tag == 0x1)
2904 heads_size += 8;
2905 else if (dv_meta_flag == 2 && tag != 0x1)
2906 heads_size += 8;
2907 }
2908 }
2909 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2910 new_buf = krealloc(AUX_DATA_BUF(pic),
2911 new_size,
2912 GFP_KERNEL);
2913 if (new_buf) {
2914 unsigned char valid_tag = 0;
2915 unsigned char *h =
2916 new_buf +
2917 AUX_DATA_SIZE(pic);
2918 unsigned char *p = h + 8;
2919 int len = 0;
2920 int padding_len = 0;
2921 AUX_DATA_BUF(pic) = new_buf;
2922 for (i = 0; i < aux_count; i += 4) {
2923 int ii;
2924 unsigned char tag = aux_adr[i + 3] >> 8;
2925 if (tag != 0 && tag != 0xff) {
2926 if (dv_meta_flag == 0)
2927 valid_tag = 1;
2928 else if (dv_meta_flag == 1
2929 && tag == 0x1)
2930 valid_tag = 1;
2931 else if (dv_meta_flag == 2
2932 && tag != 0x1)
2933 valid_tag = 1;
2934 else
2935 valid_tag = 0;
2936 if (valid_tag && len > 0) {
2937 AUX_DATA_SIZE(pic) +=
2938 (len + 8);
2939 h[0] =
2940 (len >> 24) & 0xff;
2941 h[1] =
2942 (len >> 16) & 0xff;
2943 h[2] =
2944 (len >> 8) & 0xff;
2945 h[3] =
2946 (len >> 0) & 0xff;
2947 h[6] =
2948 (padding_len >> 8)
2949 & 0xff;
2950 h[7] =
2951 (padding_len) & 0xff;
2952 h += (len + 8);
2953 p += 8;
2954 len = 0;
2955 padding_len = 0;
2956 }
2957 if (valid_tag) {
2958 h[4] = tag;
2959 h[5] = 0;
2960 h[6] = 0;
2961 h[7] = 0;
2962 }
2963 }
2964 if (valid_tag) {
2965 for (ii = 0; ii < 4; ii++) {
2966 unsigned short aa =
2967 aux_adr[i + 3
2968 - ii];
2969 *p = aa & 0xff;
2970 p++;
2971 len++;
2972 /*if ((aa >> 8) == 0xff)
2973 padding_len++;*/
2974 }
2975 }
2976 }
2977 if (len > 0) {
2978 AUX_DATA_SIZE(pic) += (len + 8);
2979 h[0] = (len >> 24) & 0xff;
2980 h[1] = (len >> 16) & 0xff;
2981 h[2] = (len >> 8) & 0xff;
2982 h[3] = (len >> 0) & 0xff;
2983 h[6] = (padding_len >> 8) & 0xff;
2984 h[7] = (padding_len) & 0xff;
2985 }
2986 if (dpb_is_debug(DECODE_ID(hw),
2987 PRINT_FLAG_DPB_DETAIL)) {
2988 dpb_print(DECODE_ID(hw), 0,
2989 "aux: (size %d) suffix_flag %d\n",
2990 AUX_DATA_SIZE(pic), suffix_flag);
2991 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2992 dpb_print_cont(DECODE_ID(hw), 0,
2993 "%02x ", AUX_DATA_BUF(pic)[i]);
2994 if (((i + 1) & 0xf) == 0)
2995 dpb_print_cont(
2996 DECODE_ID(hw),
2997 0, "\n");
2998 }
2999 dpb_print_cont(DECODE_ID(hw),
3000 0, "\n");
3001 }
3002
3003 }
3004 }
3005
3006}
3007
3008static void release_aux_data(struct vdec_h264_hw_s *hw,
3009 int buf_spec_num)
3010{
3011 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3012 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3013 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3014}
3015
3016static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3017{
3018 int i;
3019 unsigned short *aux_adr =
3020 (unsigned short *)
3021 hw->aux_addr;
3022 unsigned aux_size =
3023 (READ_VREG(H264_AUX_DATA_SIZE)
3024 >> 16) << 4;
3025
3026 if (hw->prefix_aux_size > 0) {
3027 dpb_print(DECODE_ID(hw),
3028 0,
3029 "prefix aux: (size %d)\n",
3030 aux_size);
3031 for (i = 0; i <
3032 (aux_size >> 1); i++) {
3033 dpb_print_cont(DECODE_ID(hw),
3034 0,
3035 "%04x ",
3036 *(aux_adr + i));
3037 if (((i + 1) & 0xf)
3038 == 0)
3039 dpb_print_cont(
3040 DECODE_ID(hw),
3041 0, "\n");
3042 }
3043 }
3044 if (hw->suffix_aux_size > 0) {
3045 aux_adr = (unsigned short *)
3046 (hw->aux_addr +
3047 hw->prefix_aux_size);
3048 aux_size =
3049 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3050 << 4;
3051 dpb_print(DECODE_ID(hw),
3052 0,
3053 "suffix aux: (size %d)\n",
3054 aux_size);
3055 for (i = 0; i <
3056 (aux_size >> 1); i++) {
3057 dpb_print_cont(DECODE_ID(hw),
3058 0,
3059 "%04x ", *(aux_adr + i));
3060 if (((i + 1) & 0xf) == 0)
3061 dpb_print_cont(DECODE_ID(hw),
3062 0, "\n");
3063 }
3064 }
3065}
3066
3067static void config_decode_mode(struct vdec_h264_hw_s *hw)
3068{
3069#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3070 struct vdec_s *vdec = hw_to_vdec(hw);
3071#endif
3072 if (input_frame_based(hw_to_vdec(hw)))
3073 WRITE_VREG(H264_DECODE_MODE,
3074 DECODE_MODE_MULTI_FRAMEBASE);
3075#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3076 else if (vdec->slave)
3077 WRITE_VREG(H264_DECODE_MODE,
3078 (hw->got_valid_nal << 8) |
3079 DECODE_MODE_MULTI_DVBAL);
3080 else if (vdec->master)
3081 WRITE_VREG(H264_DECODE_MODE,
3082 (hw->got_valid_nal << 8) |
3083 DECODE_MODE_MULTI_DVENL);
3084#endif
3085 else
3086 WRITE_VREG(H264_DECODE_MODE,
3087 DECODE_MODE_MULTI_STREAMBASE);
3088 WRITE_VREG(H264_DECODE_SEQINFO,
3089 hw->seq_info2);
3090 WRITE_VREG(HEAD_PADING_REG, 0);
3091
3092 if (hw->init_flag == 0)
3093 WRITE_VREG(INIT_FLAG_REG, 0);
3094 else
3095 WRITE_VREG(INIT_FLAG_REG, 1);
3096}
3097int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3098{
3099 /* static int count = 0; */
3100 int ret = 0;
3101 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3102 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3103 unsigned int colocate_adr_offset;
3104 unsigned int val;
3105 struct StorablePicture *last_pic = hw->last_dec_picture;
3106
3107#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3108 int colocate_buf_index;
3109#endif
3110#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3111#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3112#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3113#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3114
3115#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3116/* bit 31:30 -- L1[0] picture coding structure,
3117 * 00 - top field, 01 - bottom field,
3118 * 10 - frame, 11 - mbaff frame
3119 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3120 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3121 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3122 */
3123#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3124
3125/* bit 15 -- flush co_mb_data to DDR -- W-Only
3126 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3127 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3128 * bit 9 -- soft_reset -- W-Only
3129 * bit 8 -- upgent
3130 * bit 7:2 -- h264_co_mb_mem_wr_addr
3131 * bit 1:0 -- h264_co_mb_info_wr_ptr
3132 */
3133#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3134
3135 unsigned long canvas_adr;
3136 unsigned int ref_reg_val;
3137 unsigned int one_ref_cfg = 0;
3138 int h264_buffer_info_data_write_count;
3139 int i, j;
3140 unsigned int colocate_wr_adr;
3141 unsigned int colocate_rd_adr;
3142 unsigned char use_direct_8x8;
3143 int canvas_pos;
3144 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3145 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3146 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3147 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3148 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3149
3150 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3151 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3152 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3153 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3154 canvas_pos);
3155 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3156
3157#ifdef VDEC_DW
3158 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3159 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3160 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3161#endif
3162 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3163 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3164
3165 if (!hw->mmu_enable) {
3166 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3167 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3168 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3169#ifdef VDEC_DW
3170 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3171 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3172 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3173#endif
3174 } else
3175 hevc_sao_set_pic_buffer(hw, pic);
3176
3177 if (pic->mb_aff_frame_flag)
3178 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3179 else if (pic->structure == TOP_FIELD)
3180 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3181 else if (pic->structure == BOTTOM_FIELD)
3182 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3183 else
3184 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3185
3186 if (pic->bottom_poc < pic->top_poc)
3187 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3188
3189 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3190 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3191 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3192
3193 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3194 int long_term_flag;
3195 i = get_buf_spec_by_canvas_pos(hw, j);
3196 if (i < 0)
3197 break;
3198 long_term_flag =
3199 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3200 if (long_term_flag > 0) {
3201 if (long_term_flag & 0x1)
3202 hw->buffer_spec[i].info0 |= (1 << 4);
3203 else
3204 hw->buffer_spec[i].info0 &= ~(1 << 4);
3205
3206 if (long_term_flag & 0x2)
3207 hw->buffer_spec[i].info0 |= (1 << 5);
3208 else
3209 hw->buffer_spec[i].info0 &= ~(1 << 5);
3210 }
3211
3212 if (i == pic->buf_spec_num)
3213 WRITE_VREG(H264_BUFFER_INFO_DATA,
3214 hw->buffer_spec[i].info0 | 0xf);
3215 else
3216 WRITE_VREG(H264_BUFFER_INFO_DATA,
3217 hw->buffer_spec[i].info0);
3218 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3219 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3220 }
3221
3222 /* config reference buffer */
3223 if (hw->mmu_enable) {
3224 hevc_mcr_config_mc_ref(hw);
3225 hevc_mcr_config_mcrcc(hw);
3226 }
3227
3228 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3229 "list0 size %d\n", pSlice->listXsize[0]);
3230 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3231 ref_reg_val = 0;
3232 j = 0;
3233 h264_buffer_info_data_write_count = 0;
3234
3235 //disable this read cache when frame width <= 64 (4MBs)
3236 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3237 if (hw->frame_width <= 64)
3238 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3239 else
3240 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3241
3242 if (last_pic)
3243 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3244 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3245 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3246 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3247 last_pic && (last_pic->data_flag & ERROR_FLAG)
3248 && (!(last_pic->slice_type == B_SLICE))
3249 && (!(pSlice->slice_type == I_SLICE))) {
3250 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3251 "no i/idr error mark\n");
3252 hw->data_flag |= ERROR_FLAG;
3253 pic->data_flag |= ERROR_FLAG;
3254 }
3255
3256 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3257 /*ref list 0 */
3258 struct StorablePicture *ref = pSlice->listX[0][i];
3259 unsigned int cfg;
3260 /* bit[6:5] - frame/field info,
3261 * 01 - top, 10 - bottom, 11 - frame
3262 */
3263 #ifdef ERROR_CHECK
3264 if (ref == NULL) {
3265 hw->data_flag |= ERROR_FLAG;
3266 pic->data_flag |= ERROR_FLAG;
3267 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3268 return -1;
3269 }
3270 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3271 hw->data_flag |= ERROR_FLAG;
3272 pic->data_flag |= ERROR_FLAG;
3273 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3274 }
3275 if (ref->data_flag & NULL_FLAG)
3276 hw->data_flag |= NULL_FLAG;
3277#endif
3278 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3279
3280 if (ref->structure == TOP_FIELD)
3281 cfg = 0x1;
3282 else if (ref->structure == BOTTOM_FIELD)
3283 cfg = 0x2;
3284 else /* FRAME */
3285 cfg = 0x3;
3286
3287 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3288 ref_reg_val <<= 8;
3289 ref_reg_val |= one_ref_cfg;
3290 j++;
3291
3292 if (j == 4) {
3293 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3294 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3295 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3296 h264_buffer_info_data_write_count++;
3297 j = 0;
3298 }
3299 print_pic_info(DECODE_ID(hw), "list0",
3300 pSlice->listX[0][i], -1);
3301 }
3302 if (j != 0) {
3303 while (j != 4) {
3304 ref_reg_val <<= 8;
3305 ref_reg_val |= one_ref_cfg;
3306 j++;
3307 }
3308 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3309 "H264_BUFFER_INFO_DATA: %x\n",
3310 ref_reg_val);
3311 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3312 h264_buffer_info_data_write_count++;
3313 }
3314 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3315 (one_ref_cfg << 8) | one_ref_cfg;
3316 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3317 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3318
3319 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3320 "list1 size %d\n", pSlice->listXsize[1]);
3321 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3322 ref_reg_val = 0;
3323 j = 0;
3324
3325 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3326 /* ref list 0 */
3327 struct StorablePicture *ref = pSlice->listX[1][i];
3328 unsigned int cfg;
3329 /* bit[6:5] - frame/field info,
3330 * 01 - top, 10 - bottom, 11 - frame
3331 */
3332
3333 #ifdef ERROR_CHECK
3334 if (ref == NULL) {
3335 hw->data_flag |= ERROR_FLAG;
3336 pic->data_flag |= ERROR_FLAG;
3337 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3338 return -2;
3339 }
3340 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3341 pic->data_flag |= ERROR_FLAG;
3342 hw->data_flag |= ERROR_FLAG;
3343 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3344 }
3345 if (ref->data_flag & NULL_FLAG)
3346 hw->data_flag |= NULL_FLAG;
3347#endif
3348 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3349 if (ref->structure == TOP_FIELD)
3350 cfg = 0x1;
3351 else if (ref->structure == BOTTOM_FIELD)
3352 cfg = 0x2;
3353 else /* FRAME */
3354 cfg = 0x3;
3355 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3356 ref_reg_val <<= 8;
3357 ref_reg_val |= one_ref_cfg;
3358 j++;
3359
3360 if (j == 4) {
3361 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3362 "H264_BUFFER_INFO_DATA: %x\n",
3363 ref_reg_val);
3364 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3365 j = 0;
3366 }
3367 print_pic_info(DECODE_ID(hw), "list1",
3368 pSlice->listX[1][i], -1);
3369 }
3370 if (j != 0) {
3371 while (j != 4) {
3372 ref_reg_val <<= 8;
3373 ref_reg_val |= one_ref_cfg;
3374 j++;
3375 }
3376 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3377 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3378 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3379 }
3380
3381 /* configure co-locate buffer */
3382 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3383 ;
3384 if ((pSlice->mode_8x8_flags & 0x4) &&
3385 (pSlice->mode_8x8_flags & 0x2))
3386 use_direct_8x8 = 1;
3387 else
3388 use_direct_8x8 = 0;
3389
3390#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3391 colocate_adr_offset =
3392 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3393 ? 1 : 2) * 96;
3394 if (use_direct_8x8)
3395 colocate_adr_offset >>= 2;
3396
3397 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3398 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3399 colocate_adr_offset, pSlice->first_mb_in_slice,
3400 colocate_adr_offset * pSlice->first_mb_in_slice);
3401
3402 colocate_adr_offset *= pSlice->first_mb_in_slice;
3403
3404 if ((pic->colocated_buf_index >= 0) &&
3405 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3406 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3407 ((p_H264_Dpb->colocated_buf_size *
3408 pic->colocated_buf_index)
3409 >> (use_direct_8x8 ? 2 : 0));
3410 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3411 p_H264_Dpb->colocated_mv_addr_end) {
3412 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3413 "Error, colocate buf is not enough, index is %d\n",
3414 pic->colocated_buf_index);
3415 ret = -3;
3416 }
3417 val = colocate_wr_adr + colocate_adr_offset;
3418 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3419 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3420 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3421 val, pSlice->first_mb_in_slice, pic->structure,
3422 colocate_adr_offset, pSlice->mode_8x8_flags,
3423 p_H264_Dpb->colocated_buf_size);
3424 } else {
3425 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3426 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3427 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3428 }
3429#else
3430 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3431 colocate_adr_offset =
3432 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3433 if (use_direct_8x8)
3434 colocate_adr_offset >>= 2;
3435
3436 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3437 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3438 colocate_adr_offset, pSlice->first_mb_in_slice,
3439 colocate_adr_offset * pSlice->first_mb_in_slice);
3440
3441 colocate_adr_offset *= pSlice->first_mb_in_slice;
3442
3443 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3444 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3445 (use_direct_8x8 ? 2 : 0));
3446
3447 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3448 p_H264_Dpb->colocated_mv_addr_end) {
3449 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3450 "Error, colocate buf is not enough, col buf index is %d\n",
3451 colocate_buf_index);
3452 ret = -4;
3453 }
3454 val = colocate_wr_adr + colocate_adr_offset;
3455 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3456 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3457 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3458 val, pSlice->first_mb_in_slice, pic->structure,
3459 colocate_adr_offset, pSlice->mode_8x8_flags,
3460 p_H264_Dpb->colocated_buf_size);
3461#endif
3462 if (pSlice->listXsize[1] > 0) {
3463 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3464 /* H264_CO_MB_RD_ADDR[bit 31:30],
3465 * original picture structure of L1[0],
3466 * 00 - top field, 01 - bottom field,
3467 * 10 - frame, 11 - mbaff frame
3468 */
3469 int l10_structure;
3470 int cur_colocate_ref_type;
3471 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3472 * 0 - top, 1 - bot
3473 */
3474 unsigned int val;
3475#ifdef ERROR_CHECK
3476 if (colocate_pic == NULL) {
3477 hw->data_flag |= ERROR_FLAG;
3478 pic->data_flag |= ERROR_FLAG;
3479 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3480 return -5;
3481 }
3482 if (colocate_pic->data_flag & ERROR_FLAG) {
3483 pic->data_flag |= ERROR_FLAG;
3484 hw->data_flag |= ERROR_FLAG;
3485 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3486 }
3487 if (colocate_pic->data_flag & NULL_FLAG)
3488 hw->data_flag |= NULL_FLAG;
3489#endif
3490
3491 if (colocate_pic->mb_aff_frame_flag)
3492 l10_structure = 3;
3493 else {
3494 if (colocate_pic->coded_frame)
3495 l10_structure = 2;
3496 else
3497 l10_structure = (colocate_pic->structure ==
3498 BOTTOM_FIELD) ? 1 : 0;
3499 }
3500#if 0
3501 /*case0016, p16,
3502 *cur_colocate_ref_type should be configured base on current pic
3503 */
3504 if (pic->structure == FRAME &&
3505 pic->mb_aff_frame_flag)
3506 cur_colocate_ref_type = 0;
3507 else if (pic->structure == BOTTOM_FIELD)
3508 cur_colocate_ref_type = 1;
3509 else
3510 cur_colocate_ref_type = 0;
3511#else
3512 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3513 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3514 pic->mb_aff_frame_flag,
3515 pic->structure,
3516 pic->coded_frame);
3517 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3518 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3519 colocate_pic->mb_aff_frame_flag,
3520 colocate_pic->structure,
3521 colocate_pic->coded_frame);
3522 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3523 cur_colocate_ref_type =
3524 (abs(pic->poc - colocate_pic->top_poc)
3525 < abs(pic->poc -
3526 colocate_pic->bottom_poc)) ? 0 : 1;
3527 } else
3528 cur_colocate_ref_type =
3529 (colocate_pic->structure
3530 == BOTTOM_FIELD) ? 1 : 0;
3531#endif
3532
3533#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3534 if ((colocate_pic->colocated_buf_index >= 0) &&
3535 (colocate_pic->colocated_buf_index <
3536 p_H264_Dpb->colocated_buf_count)) {
3537 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3538 ((p_H264_Dpb->colocated_buf_size *
3539 colocate_pic->colocated_buf_index)
3540 >> (use_direct_8x8 ? 2 : 0));
3541 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3542 p_H264_Dpb->colocated_mv_addr_end) {
3543 dpb_print(DECODE_ID(hw),
3544 PRINT_FLAG_ERROR,
3545 "Error, colocate buf is not enough, index is %d\n",
3546 colocate_pic->colocated_buf_index);
3547 ret = -6;
3548 }
3549 /* bit 31:30 -- L1[0] picture coding structure,
3550 * 00 - top field, 01 - bottom field,
3551 * 10 - frame, 11 - mbaff frame
3552 * bit 29 - L1[0] top/bot for B field pciture,
3553 * 0 - top, 1 - bot
3554 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3555 * -- only used for B Picture Direct mode
3556 * [2:0] will set to 3'b000
3557 */
3558 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3559 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3560 (l10_structure << 30) |
3561 (cur_colocate_ref_type << 29);
3562 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3563 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3564 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3565 colocate_pic->colocated_buf_index,
3566 val, colocate_rd_adr + colocate_adr_offset,
3567 colocate_pic->structure,
3568 colocate_pic->mb_aff_frame_flag);
3569 } else {
3570 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3571 "Error, reference pic has no colocated buf\n");
3572 ret = -7;
3573 }
3574#else
3575 colocate_buf_index =
3576 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3577 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3578 ((p_H264_Dpb->colocated_buf_size *
3579 colocate_buf_index)
3580 >> (use_direct_8x8 ? 2 : 0));
3581 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3582 p_H264_Dpb->colocated_mv_addr_end) {
3583 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3584 "Error, colocate buf is not enough, col buf index is %d\n",
3585 colocate_buf_index);
3586 ret = -8;
3587 }
3588 /* bit 31:30 -- L1[0] picture coding structure,
3589 * 00 - top field, 01 - bottom field,
3590 * 10 - frame, 11 - mbaff frame
3591 * bit 29 - L1[0] top/bot for B field pciture,
3592 * 0 - top, 1 - bot
3593 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3594 * -- only used for B Picture Direct mode
3595 * [2:0] will set to 3'b000
3596 */
3597 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3598 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3599 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3600 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3601 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3602 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3603 val, colocate_pic->structure,
3604 colocate_pic->mb_aff_frame_flag);
3605#endif
3606 }
3607 return ret;
3608}
3609
3610static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3611{
3612 unsigned long flags;
3613 struct vdec_s *vdec = op_arg;
3614 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3615
3616 spin_lock_irqsave(&hw->lock, flags);
3617
3618 states->vf_pool_size = VF_POOL_SIZE;
3619 states->buf_free_num = kfifo_len(&hw->newframe_q);
3620 states->buf_avail_num = kfifo_len(&hw->display_q);
3621
3622 spin_unlock_irqrestore(&hw->lock, flags);
3623
3624 return 0;
3625}
3626
3627static struct vframe_s *vh264_vf_peek(void *op_arg)
3628{
3629 struct vframe_s *vf[2] = {0, 0};
3630 struct vdec_s *vdec = op_arg;
3631 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3632
3633 if (!hw)
3634 return NULL;
3635
3636 if (force_disp_bufspec_num & 0x100) {
3637 if (force_disp_bufspec_num & 0x200)
3638 return NULL;
3639 return &hw->vframe_dummy;
3640 }
3641
3642 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3643 if (vf[1]) {
3644 vf[0]->next_vf_pts_valid = true;
3645 vf[0]->next_vf_pts = vf[1]->pts;
3646 } else
3647 vf[0]->next_vf_pts_valid = false;
3648 return vf[0];
3649 }
3650
3651 return NULL;
3652}
3653
3654static struct vframe_s *vh264_vf_get(void *op_arg)
3655{
3656 struct vframe_s *vf;
3657 struct vdec_s *vdec = op_arg;
3658 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3659
3660 if (!hw)
3661 return NULL;
3662
3663 if (force_disp_bufspec_num & 0x100) {
3664 int buffer_index = force_disp_bufspec_num & 0xff;
3665 if (force_disp_bufspec_num & 0x200)
3666 return NULL;
3667
3668 vf = &hw->vframe_dummy;
3669 vf->duration_pulldown = 0;
3670 vf->pts = 0;
3671 vf->pts_us64 = 0;
3672 set_frame_info(hw, vf, buffer_index);
3673 vf->flag = 0;
3674 if (hw->mmu_enable) {
3675 if (hw->double_write_mode & 0x10) {
3676 /* double write only */
3677 vf->compBodyAddr = 0;
3678 vf->compHeadAddr = 0;
3679 } else {
3680 /*head adr*/
3681 vf->compHeadAddr =
3682 hw->buffer_spec[buffer_index].alloc_header_addr;
3683 /*body adr*/
3684 vf->compBodyAddr = 0;
3685 vf->canvas0Addr = vf->canvas1Addr = 0;
3686 }
3687
3688 vf->type = VIDTYPE_SCATTER;
3689
3690 if (hw->double_write_mode) {
3691 vf->type |= VIDTYPE_PROGRESSIVE
3692 | VIDTYPE_VIU_FIELD;
3693 vf->type |= VIDTYPE_VIU_NV21;
3694 if (hw->double_write_mode == 3)
3695 vf->type |= VIDTYPE_COMPRESS;
3696
3697 vf->canvas0Addr = vf->canvas1Addr = -1;
3698 vf->plane_num = 2;
3699 vf->canvas0_config[0] =
3700 hw->buffer_spec[buffer_index].
3701 canvas_config[0];
3702 vf->canvas0_config[1] =
3703 hw->buffer_spec[buffer_index].
3704 canvas_config[1];
3705
3706 vf->canvas1_config[0] =
3707 hw->buffer_spec[buffer_index].
3708 canvas_config[0];
3709 vf->canvas1_config[1] =
3710 hw->buffer_spec[buffer_index].
3711 canvas_config[1];
3712 } else {
3713 vf->type |=
3714 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3715 vf->canvas0Addr = vf->canvas1Addr = 0;
3716 }
3717 vf->bitdepth =
3718 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3719
3720 vf->compWidth = hw->frame_width;
3721 vf->compHeight = hw->frame_height;
3722
3723 if (hw->double_write_mode) {
3724 vf->width = hw->frame_width /
3725 get_double_write_ratio(hw);
3726 vf->height = hw->frame_height /
3727 get_double_write_ratio(hw);
3728 }
3729 } else {
3730 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3731 VIDTYPE_VIU_NV21;
3732 vf->canvas0Addr = vf->canvas1Addr =
3733 spec2canvas(&hw->buffer_spec[buffer_index]);
3734 }
3735
3736 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3737 hw->bmmu_box, buffer_index);*/
3738 update_vf_memhandle(hw, vf, buffer_index);
3739 force_disp_bufspec_num |= 0x200;
3740 return vf;
3741 }
3742
3743 if (kfifo_get(&hw->display_q, &vf)) {
3744 int time = jiffies;
3745 unsigned int frame_interval =
3746 1000*(time - hw->last_frame_time)/HZ;
3747 struct vframe_s *next_vf;
3748 if (dpb_is_debug(DECODE_ID(hw),
3749 PRINT_FLAG_VDEC_DETAIL)) {
3750 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3751 int frame_index = FRAME_INDEX(vf->index);
3752 if (frame_index < 0 ||
3753 frame_index >= DPB_SIZE_MAX) {
3754 dpb_print(DECODE_ID(hw), 0,
3755 "%s vf index 0x%x error\r\n",
3756 __func__, vf->index);
3757 } else {
3758 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3759 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3760 __func__, BUFSPEC_INDEX(vf->index), vf,
3761 p_H264_Dpb->mFrameStore[frame_index].poc,
3762 vf->duration, vf->pts, frame_interval);
3763 }
3764 }
3765 if (hw->last_frame_time > 0) {
3766 if (frame_interval >
3767 max_get_frame_interval[DECODE_ID(hw)])
3768 max_get_frame_interval[DECODE_ID(hw)]
3769 = frame_interval;
3770 }
3771 hw->last_frame_time = time;
3772 hw->vf_get_count++;
3773 if (kfifo_peek(&hw->display_q, &next_vf)) {
3774 vf->next_vf_pts_valid = true;
3775 vf->next_vf_pts = next_vf->pts;
3776 } else
3777 vf->next_vf_pts_valid = false;
3778 return vf;
3779 }
3780
3781 return NULL;
3782}
3783
3784static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3785{
3786 struct vdec_s *vdec = op_arg;
3787 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3788 int buf_spec_num;
3789 int frame_index;
3790
3791 if (vf == (&hw->vframe_dummy))
3792 return;
3793 if (vf->index == -1) {
3794 dpb_print(DECODE_ID(hw), 0,
3795 "Warning: %s vf %p invalid index\r\n",
3796 __func__, vf);
3797 return;
3798 }
3799 frame_index = FRAME_INDEX(vf->index);
3800 buf_spec_num = BUFSPEC_INDEX(vf->index);
3801 if (frame_index < 0 ||
3802 frame_index >= DPB_SIZE_MAX ||
3803 buf_spec_num < 0 ||
3804 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3805 dpb_print(DECODE_ID(hw), 0,
3806 "%s vf index 0x%x error\r\n",
3807 __func__, vf->index);
3808 return;
3809 }
3810 /*get_buf_spec_idx_by_canvas_config(hw,
3811 &vf->canvas0_config[0]);*/
3812 if (hw->buffer_spec[buf_spec_num].used == 2) {
3813 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3814 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3815 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3816 __func__, vf, frame_index,
3817 p_H264_Dpb->mFrameStore[frame_index].poc,
3818 buf_spec_num,
3819 hw->buffer_spec[buf_spec_num].used,
3820 hw->buffer_spec[buf_spec_num].vf_ref);
3821 hw->buffer_spec[buf_spec_num].vf_ref--;
3822 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3823 set_frame_output_flag(&hw->dpb, frame_index);
3824 } else {
3825 unsigned long flags;
3826 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3827 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3828 __func__, vf, buf_spec_num,
3829 hw->buffer_spec[buf_spec_num].used,
3830 hw->buffer_spec[buf_spec_num].vf_ref);
3831 spin_lock_irqsave(&hw->bufspec_lock, flags);
3832 hw->buffer_spec[buf_spec_num].vf_ref--;
3833 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3834 if (hw->buffer_spec[buf_spec_num].used == 3)
3835 hw->buffer_spec[buf_spec_num].used = 4;
3836 else if (hw->buffer_spec[buf_spec_num].used == 5)
3837 hw->buffer_spec[buf_spec_num].used = 0;
3838 }
3839 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3840 if (dpb_is_debug(DECODE_ID(hw),
3841 PRINT_FLAG_DUMP_BUFSPEC))
3842 dump_bufspec(hw, __func__);
3843
3844 }
3845
3846 hw->vf_put_count++;
3847 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3848
3849#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3850 if (hw->buffer_empty_flag)
3851 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3852}
3853
3854static int vh264_event_cb(int type, void *data, void *op_arg)
3855{
3856 unsigned long flags;
3857 struct vdec_s *vdec = op_arg;
3858 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3859
3860 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3861 struct provider_aux_req_s *req =
3862 (struct provider_aux_req_s *)data;
3863 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3864 spin_lock_irqsave(&hw->lock, flags);
3865 req->aux_buf = NULL;
3866 req->aux_size = 0;
3867 if (buf_spec_num >= 0 &&
3868 buf_spec_num < BUFSPEC_POOL_SIZE &&
3869 is_buf_spec_in_disp_q(hw, buf_spec_num)
3870 ) {
3871 req->aux_buf =
3872 hw->buffer_spec[buf_spec_num].aux_data_buf;
3873 req->aux_size =
3874 hw->buffer_spec[buf_spec_num].aux_data_size;
3875#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3876 req->dv_enhance_exist =
3877 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3878#else
3879 req->dv_enhance_exist = 0;
3880#endif
3881 }
3882 spin_unlock_irqrestore(&hw->lock, flags);
3883
3884 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3885 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3886 __func__, type, buf_spec_num, req->aux_size);
3887 }
3888
3889 return 0;
3890}
3891
3892static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3893 u32 index)
3894{
3895 struct canvas_config_s *p_canvas_config;
3896 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3897 force_rate_framebase : force_rate_streambase;
3898 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3899 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3900 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3901
3902 /* signal_type */
3903 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3904 vf->signal_type = hw->video_signal_from_vui;
3905 if (hw->is_used_v4l) {
3906 struct aml_vdec_hdr_infos hdr;
3907 struct aml_vcodec_ctx *ctx =
3908 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3909
3910 memset(&hdr, 0, sizeof(hdr));
3911 hdr.signal_type = hw->video_signal_from_vui;
3912 vdec_v4l_set_hdr_infos(ctx, &hdr);
3913 }
3914 } else
3915 vf->signal_type = 0;
3916
3917 vf->width = hw->frame_width;
3918 vf->height = hw->frame_height;
3919 if (force_rate) {
3920 if (force_rate == -1)
3921 vf->duration = 0;
3922 else
3923 vf->duration = 96000/force_rate;
3924 } else
3925 vf->duration = hw->frame_dur;
3926 vf->ratio_control =
3927 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3928 DISP_RATIO_ASPECT_RATIO_BIT;
3929 vf->orientation = hw->vh264_rotation;
3930
3931 if (hw->mmu_enable)
3932 return;
3933
3934 vf->canvas0Addr = vf->canvas1Addr = -1;
3935#ifdef NV21
3936 vf->plane_num = 2;
3937#else
3938 vf->plane_num = 3;
3939#endif
3940
3941 if (IS_VDEC_DW(hw)) {
3942 vf->width = (hw->frame_width /2);
3943 if (IS_VDEC_DW(hw) == 2)
3944 vf->height = (hw->frame_height /2);
3945 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3946 } else
3947 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3948
3949 vf->canvas0_config[0] = p_canvas_config[0];
3950 vf->canvas0_config[1] = p_canvas_config[1];
3951#ifndef NV21
3952 vf->canvas0_config[2] = p_canvas_config[2];
3953#endif
3954 vf->canvas1_config[0] = p_canvas_config[0];
3955 vf->canvas1_config[1] = p_canvas_config[1];
3956#ifndef NV21
3957 vf->canvas1_config[2] = p_canvas_config[2];
3958#endif
3959}
3960
3961static void get_picture_qos_info(struct StorablePicture *picture)
3962{
3963 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3964 unsigned char a[3];
3965 unsigned char i, j, t;
3966 unsigned long data;
3967
3968 get_random_bytes(&data, sizeof(unsigned long));
3969 if (picture->slice_type == I_SLICE)
3970 data = 0;
3971 a[0] = data & 0xff;
3972 a[1] = (data >> 8) & 0xff;
3973 a[2] = (data >> 16) & 0xff;
3974
3975 for (i = 0; i < 3; i++)
3976 for (j = i+1; j < 3; j++) {
3977 if (a[j] < a[i]) {
3978 t = a[j];
3979 a[j] = a[i];
3980 a[i] = t;
3981 } else if (a[j] == a[i]) {
3982 a[i]++;
3983 t = a[j];
3984 a[j] = a[i];
3985 a[i] = t;
3986 }
3987 }
3988 picture->max_mv = a[2];
3989 picture->avg_mv = a[1];
3990 picture->min_mv = a[0];
3991 /*
3992 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3993 data, a[0], a[1], a[2]);
3994 */
3995
3996 get_random_bytes(&data, sizeof(unsigned long));
3997 a[0] = data & 0x1f;
3998 a[1] = (data >> 8) & 0x3f;
3999 a[2] = (data >> 16) & 0x7f;
4000
4001 for (i = 0; i < 3; i++)
4002 for (j = i+1; j < 3; j++) {
4003 if (a[j] < a[i]) {
4004 t = a[j];
4005 a[j] = a[i];
4006 a[i] = t;
4007 } else if (a[j] == a[i]) {
4008 a[i]++;
4009 t = a[j];
4010 a[j] = a[i];
4011 a[i] = t;
4012 }
4013 }
4014 picture->max_qp = a[2];
4015 picture->avg_qp = a[1];
4016 picture->min_qp = a[0];
4017 /*
4018 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4019 data, a[0], a[1], a[2]);
4020 */
4021
4022 get_random_bytes(&data, sizeof(unsigned long));
4023 a[0] = data & 0x1f;
4024 a[1] = (data >> 8) & 0x3f;
4025 a[2] = (data >> 16) & 0x7f;
4026
4027 for (i = 0; i < 3; i++)
4028 for (j = i+1; j < 3; j++) {
4029 if (a[j] < a[i]) {
4030 t = a[j];
4031 a[j] = a[i];
4032 a[i] = t;
4033 } else if (a[j] == a[i]) {
4034 a[i]++;
4035 t = a[j];
4036 a[j] = a[i];
4037 a[i] = t;
4038 }
4039 }
4040 picture->max_skip = a[2];
4041 picture->avg_skip = a[1];
4042 picture->min_skip = a[0];
4043
4044
4045 /*
4046 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4047 data,a[0], a[1], a[2]);
4048 */
4049 } else {
4050 uint32_t blk88_y_count;
4051 uint32_t blk88_c_count;
4052 uint32_t blk22_mv_count;
4053 uint32_t rdata32;
4054 int32_t mv_hi;
4055 int32_t mv_lo;
4056 uint32_t rdata32_l;
4057 uint32_t mvx_L0_hi;
4058 uint32_t mvy_L0_hi;
4059 uint32_t mvx_L1_hi;
4060 uint32_t mvy_L1_hi;
4061 int64_t value;
4062 uint64_t temp_value;
4063/*
4064#define DEBUG_QOS
4065*/
4066#ifdef DEBUG_QOS
4067 int pic_number = picture->poc;
4068#endif
4069
4070 picture->max_mv = 0;
4071 picture->avg_mv = 0;
4072 picture->min_mv = 0;
4073
4074 picture->max_skip = 0;
4075 picture->avg_skip = 0;
4076 picture->min_skip = 0;
4077
4078 picture->max_qp = 0;
4079 picture->avg_qp = 0;
4080 picture->min_qp = 0;
4081
4082
4083
4084
4085
4086 /* set rd_idx to 0 */
4087 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4088 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4089 if (blk88_y_count == 0) {
4090#ifdef DEBUG_QOS
4091 pr_info(" [Picture %d Quality] NO Data yet.\n",
4092 pic_number);
4093#endif
4094 /* reset all counts */
4095 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4096 return;
4097 }
4098 /* qp_y_sum */
4099 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4100#ifdef DEBUG_QOS
4101 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4102 pic_number, rdata32/blk88_y_count,
4103 rdata32, blk88_y_count);
4104#endif
4105 picture->avg_qp = rdata32/blk88_y_count;
4106 /* intra_y_count */
4107 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4108#ifdef DEBUG_QOS
4109 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4110 pic_number, rdata32*100/blk88_y_count,
4111 '%', rdata32);
4112#endif
4113 /* skipped_y_count */
4114 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4115#ifdef DEBUG_QOS
4116 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4117 pic_number, rdata32*100/blk88_y_count,
4118 '%', rdata32);
4119#endif
4120 picture->avg_skip = rdata32*100/blk88_y_count;
4121 /* coeff_non_zero_y_count */
4122 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4123#ifdef DEBUG_QOS
4124 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4125 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4126 '%', rdata32);
4127#endif
4128 /* blk66_c_count */
4129 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4130 if (blk88_c_count == 0) {
4131#ifdef DEBUG_QOS
4132 pr_info(" [Picture %d Quality] NO Data yet.\n",
4133 pic_number);
4134#endif
4135 /* reset all counts */
4136 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4137 return;
4138 }
4139 /* qp_c_sum */
4140 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4141#ifdef DEBUG_QOS
4142 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4143 pic_number, rdata32/blk88_c_count,
4144 rdata32, blk88_c_count);
4145#endif
4146 /* intra_c_count */
4147 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4148#ifdef DEBUG_QOS
4149 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4150 pic_number, rdata32*100/blk88_c_count,
4151 '%', rdata32);
4152#endif
4153 /* skipped_cu_c_count */
4154 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4155#ifdef DEBUG_QOS
4156 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4157 pic_number, rdata32*100/blk88_c_count,
4158 '%', rdata32);
4159#endif
4160 /* coeff_non_zero_c_count */
4161 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4162#ifdef DEBUG_QOS
4163 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4164 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4165 '%', rdata32);
4166#endif
4167
4168 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4169 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4170 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4171#ifdef DEBUG_QOS
4172 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4173 pic_number, (rdata32>>0)&0xff);
4174#endif
4175 picture->min_qp = (rdata32>>0)&0xff;
4176
4177#ifdef DEBUG_QOS
4178 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4179 pic_number, (rdata32>>8)&0xff);
4180#endif
4181 picture->max_qp = (rdata32>>8)&0xff;
4182
4183#ifdef DEBUG_QOS
4184 pr_info(" [Picture %d Quality] C QP min : %d\n",
4185 pic_number, (rdata32>>16)&0xff);
4186 pr_info(" [Picture %d Quality] C QP max : %d\n",
4187 pic_number, (rdata32>>24)&0xff);
4188#endif
4189
4190 /* blk22_mv_count */
4191 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4192 if (blk22_mv_count == 0) {
4193#ifdef DEBUG_QOS
4194 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4195 pic_number);
4196#endif
4197 /* reset all counts */
4198 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4199 return;
4200 }
4201 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4202 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4203 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4204 /* should all be 0x00 or 0xff */
4205#ifdef DEBUG_QOS
4206 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4207 pic_number, rdata32);
4208#endif
4209 mvx_L0_hi = ((rdata32>>0)&0xff);
4210 mvy_L0_hi = ((rdata32>>8)&0xff);
4211 mvx_L1_hi = ((rdata32>>16)&0xff);
4212 mvy_L1_hi = ((rdata32>>24)&0xff);
4213
4214 /* mvx_L0_count[31:0] */
4215 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4216 temp_value = mvx_L0_hi;
4217 temp_value = (temp_value << 32) | rdata32_l;
4218
4219 if (mvx_L0_hi & 0x80)
4220 value = 0xFFFFFFF000000000 | temp_value;
4221 else
4222 value = temp_value;
4223 value = div_s64(value, blk22_mv_count);
4224#ifdef DEBUG_QOS
4225 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4226 pic_number, (int)(value),
4227 value, blk22_mv_count);
4228#endif
4229 picture->avg_mv = value;
4230
4231 /* mvy_L0_count[31:0] */
4232 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4233 temp_value = mvy_L0_hi;
4234 temp_value = (temp_value << 32) | rdata32_l;
4235
4236 if (mvy_L0_hi & 0x80)
4237 value = 0xFFFFFFF000000000 | temp_value;
4238 else
4239 value = temp_value;
4240#ifdef DEBUG_QOS
4241 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4242 pic_number, rdata32_l/blk22_mv_count,
4243 value, blk22_mv_count);
4244#endif
4245
4246 /* mvx_L1_count[31:0] */
4247 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4248 temp_value = mvx_L1_hi;
4249 temp_value = (temp_value << 32) | rdata32_l;
4250 if (mvx_L1_hi & 0x80)
4251 value = 0xFFFFFFF000000000 | temp_value;
4252 else
4253 value = temp_value;
4254#ifdef DEBUG_QOS
4255 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4256 pic_number, rdata32_l/blk22_mv_count,
4257 value, blk22_mv_count);
4258#endif
4259
4260 /* mvy_L1_count[31:0] */
4261 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4262 temp_value = mvy_L1_hi;
4263 temp_value = (temp_value << 32) | rdata32_l;
4264 if (mvy_L1_hi & 0x80)
4265 value = 0xFFFFFFF000000000 | temp_value;
4266 else
4267 value = temp_value;
4268#ifdef DEBUG_QOS
4269 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4270 pic_number, rdata32_l/blk22_mv_count,
4271 value, blk22_mv_count);
4272#endif
4273
4274 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4275 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4276 mv_hi = (rdata32>>16)&0xffff;
4277 if (mv_hi & 0x8000)
4278 mv_hi = 0x8000 - mv_hi;
4279#ifdef DEBUG_QOS
4280 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4281 pic_number, mv_hi);
4282#endif
4283 picture->max_mv = mv_hi;
4284
4285 mv_lo = (rdata32>>0)&0xffff;
4286 if (mv_lo & 0x8000)
4287 mv_lo = 0x8000 - mv_lo;
4288#ifdef DEBUG_QOS
4289 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4290 pic_number, mv_lo);
4291#endif
4292 picture->min_mv = mv_lo;
4293
4294 /* {mvy_L0_max, mvy_L0_min} */
4295 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4296 mv_hi = (rdata32>>16)&0xffff;
4297 if (mv_hi & 0x8000)
4298 mv_hi = 0x8000 - mv_hi;
4299#ifdef DEBUG_QOS
4300 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4301 pic_number, mv_hi);
4302#endif
4303
4304 mv_lo = (rdata32>>0)&0xffff;
4305 if (mv_lo & 0x8000)
4306 mv_lo = 0x8000 - mv_lo;
4307#ifdef DEBUG_QOS
4308 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4309 pic_number, mv_lo);
4310#endif
4311
4312 /* {mvx_L1_max, mvx_L1_min} */
4313 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4314 mv_hi = (rdata32>>16)&0xffff;
4315 if (mv_hi & 0x8000)
4316 mv_hi = 0x8000 - mv_hi;
4317#ifdef DEBUG_QOS
4318 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4319 pic_number, mv_hi);
4320#endif
4321
4322 mv_lo = (rdata32>>0)&0xffff;
4323 if (mv_lo & 0x8000)
4324 mv_lo = 0x8000 - mv_lo;
4325#ifdef DEBUG_QOS
4326 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4327 pic_number, mv_lo);
4328#endif
4329
4330 /* {mvy_L1_max, mvy_L1_min} */
4331 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4332 mv_hi = (rdata32>>16)&0xffff;
4333 if (mv_hi & 0x8000)
4334 mv_hi = 0x8000 - mv_hi;
4335#ifdef DEBUG_QOS
4336 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4337 pic_number, mv_hi);
4338#endif
4339 mv_lo = (rdata32>>0)&0xffff;
4340 if (mv_lo & 0x8000)
4341 mv_lo = 0x8000 - mv_lo;
4342#ifdef DEBUG_QOS
4343 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4344 pic_number, mv_lo);
4345#endif
4346
4347 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4348#ifdef DEBUG_QOS
4349 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4350 pic_number, rdata32);
4351#endif
4352 /* reset all counts */
4353 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4354 }
4355}
4356
4357static int get_max_dec_frame_buf_size(int level_idc,
4358 int max_reference_frame_num, int mb_width,
4359 int mb_height)
4360{
4361 int pic_size = mb_width * mb_height * 384;
4362
4363 int size = 0;
4364
4365 switch (level_idc) {
4366 case 9:
4367 size = 152064;
4368 break;
4369 case 10:
4370 size = 152064;
4371 break;
4372 case 11:
4373 size = 345600;
4374 break;
4375 case 12:
4376 size = 912384;
4377 break;
4378 case 13:
4379 size = 912384;
4380 break;
4381 case 20:
4382 size = 912384;
4383 break;
4384 case 21:
4385 size = 1824768;
4386 break;
4387 case 22:
4388 size = 3110400;
4389 break;
4390 case 30:
4391 size = 3110400;
4392 break;
4393 case 31:
4394 size = 6912000;
4395 break;
4396 case 32:
4397 size = 7864320;
4398 break;
4399 case 40:
4400 size = 12582912;
4401 break;
4402 case 41:
4403 size = 12582912;
4404 break;
4405 case 42:
4406 size = 13369344;
4407 break;
4408 case 50:
4409 size = 42393600;
4410 break;
4411 case 51:
4412 case 52:
4413 default:
4414 size = 70778880;
4415 break;
4416 }
4417
4418 size /= pic_size;
4419 size = size + 1; /* need one more buffer */
4420
4421 if (max_reference_frame_num > size)
4422 size = max_reference_frame_num;
4423 size = imin(size, 16);
4424
4425 return size;
4426}
4427
4428static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4429{
4430 int i, j;
4431
4432 if (hw->double_write_mode) {
4433 mutex_lock(&vmh264_mutex);
4434 if (hw->decode_pic_count == 0) {
4435 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4436 i = get_buf_spec_by_canvas_pos(hw, j);
4437 if (i >= 0)
4438 config_decode_canvas_ex(hw, i);
4439 }
4440 }
4441 mutex_unlock(&vmh264_mutex);
4442 }
4443}
4444
4445static int vh264_set_params(struct vdec_h264_hw_s *hw,
4446 u32 param1, u32 param2, u32 param3, u32 param4)
4447{
4448 int i, j;
4449 int mb_width, mb_total;
4450 int max_reference_size, level_idc;
4451 int mb_height = 0;
4452 unsigned long flags;
4453 /*int mb_mv_byte;*/
4454 struct vdec_s *vdec = hw_to_vdec(hw);
4455 u32 seq_info2;
4456 int ret = 0;
4457 int active_buffer_spec_num;
4458 unsigned int buf_size;
4459 unsigned int frame_mbs_only_flag;
4460 unsigned int chroma_format_idc, chroma444;
4461 unsigned int crop_infor, crop_bottom, crop_right;
4462 unsigned int used_reorder_dpb_size_margin
4463 = hw->reorder_dpb_size_margin;
4464 u8 *colocate_vaddr = NULL;
4465
4466#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4467 if (vdec->master || vdec->slave)
4468 used_reorder_dpb_size_margin =
4469 reorder_dpb_size_margin_dv;
4470#endif
4471 seq_info2 = param1;
4472 hw->seq_info = param2;
4473
4474 mb_width = seq_info2 & 0xff;
4475 mb_total = (seq_info2 >> 8) & 0xffff;
4476 if (!mb_width && mb_total) /*for 4k2k*/
4477 mb_width = 256;
4478 if (mb_width)
4479 mb_height = mb_total/mb_width;
4480 if (mb_width <= 0 || mb_height <= 0 ||
4481 is_oversize(mb_width << 4, mb_height << 4)) {
4482 dpb_print(DECODE_ID(hw), 0,
4483 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4484 seq_info2,
4485 mb_width,
4486 mb_height);
4487 return -1;
4488 }
4489
4490 if (seq_info2 != 0 &&
4491 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4492 hw->seq_info2 != 0
4493 ) /*picture size changed*/
4494 h264_reconfig(hw);
4495
4496 if (hw->config_bufmgr_done == 0) {
4497 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4498 u32 reg_val;
4499 hw->cfg_param1 = param1;
4500 hw->cfg_param2 = param2;
4501 hw->cfg_param3 = param3;
4502 hw->cfg_param4 = param4;
4503
4504 hw->seq_info2 = seq_info2 & (~0x80000000);
4505 dpb_print(DECODE_ID(hw), 0,
4506 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4507 seq_info2, hw->seq_info);
4508
4509 dpb_init_global(&hw->dpb,
4510 DECODE_ID(hw), 0, 0);
4511
4512 p_H264_Dpb->fast_output_enable = fast_output_enable;
4513 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4514
4515#if 1
4516 /*crop*/
4517 /* AV_SCRATCH_2
4518 bit 15: frame_mbs_only_flag
4519 bit 13-14: chroma_format_idc */
4520 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4521 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4522 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4523
4524 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4525 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4526 (2 - frame_mbs_only_flag) */
4527 crop_infor = param3;
4528 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4529 crop_right = ((crop_infor >> 16) & 0xff)
4530 >> (2 - frame_mbs_only_flag);
4531
4532 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4533 hw->frame_width = mb_width << 4;
4534 hw->frame_height = mb_height << 4;
4535 if (frame_mbs_only_flag) {
4536 hw->frame_height =
4537 hw->frame_height - (2 >> chroma444) *
4538 min(crop_bottom,
4539 (unsigned int)((8 << chroma444) - 1));
4540 hw->frame_width =
4541 hw->frame_width -
4542 (2 >> chroma444) * min(crop_right,
4543 (unsigned
4544 int)((8 << chroma444) - 1));
4545 } else {
4546 hw->frame_height =
4547 hw->frame_height - (4 >> chroma444) *
4548 min(crop_bottom,
4549 (unsigned int)((8 << chroma444)
4550 - 1));
4551 hw->frame_width =
4552 hw->frame_width -
4553 (4 >> chroma444) * min(crop_right,
4554 (unsigned int)((8 << chroma444) - 1));
4555 }
4556 dpb_print(DECODE_ID(hw), 0,
4557 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4558 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4559 dpb_print(DECODE_ID(hw), 0,
4560 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4561 mb_height, crop_right,
4562 hw->frame_width, mb_width);
4563
4564 if (hw->frame_height == 1088)
4565 hw->frame_height = 1080;
4566#endif
4567 if (!hw->mmu_enable) {
4568 mb_width = (mb_width+3) & 0xfffffffc;
4569 mb_height = (mb_height+3) & 0xfffffffc;
4570 }
4571 mb_total = mb_width * mb_height;
4572 hw->mb_width = mb_width;
4573 hw->mb_height = mb_height;
4574 hw->mb_total = mb_total;
4575 if (hw->mmu_enable)
4576 hevc_mcr_sao_global_hw_init(hw,
4577 (hw->mb_width << 4), (hw->mb_height << 4));
4578
4579 reg_val = param4;
4580 level_idc = reg_val & 0xff;
4581 max_reference_size = (reg_val >> 8) & 0xff;
4582 hw->dpb.origin_max_reference = max_reference_size;
4583 dpb_print(DECODE_ID(hw), 0,
4584 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4585 mb_height, mb_width, mb_total,
4586 level_idc, max_reference_size);
4587
4588
4589 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4590 hw->dpb.reorder_pic_num =
4591 get_max_dec_frame_buf_size(level_idc,
4592 max_reference_size, mb_width, mb_height);
4593
4594 dpb_print(DECODE_ID(hw), 0,
4595 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4596 hw->bitstream_restriction_flag,
4597 hw->max_dec_frame_buffering,
4598 hw->dpb.reorder_pic_num);
4599
4600 if ((hw->bitstream_restriction_flag) &&
4601 (hw->max_dec_frame_buffering <
4602 hw->dpb.reorder_pic_num)) {
4603 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4604 dpb_print(DECODE_ID(hw), 0,
4605 "set reorder_pic_num to %d\n",
4606 hw->dpb.reorder_pic_num);
4607 }
4608
4609 active_buffer_spec_num =
4610 hw->dpb.reorder_pic_num
4611 + used_reorder_dpb_size_margin;
4612 hw->max_reference_size =
4613 max_reference_size + reference_buf_margin;
4614
4615 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4616 active_buffer_spec_num = MAX_VF_BUF_NUM;
4617 hw->dpb.reorder_pic_num = active_buffer_spec_num
4618 - used_reorder_dpb_size_margin;
4619 }
4620 hw->dpb.mDPB.size = active_buffer_spec_num;
4621 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4622 hw->max_reference_size = MAX_VF_BUF_NUM;
4623 hw->dpb.max_reference_size = hw->max_reference_size;
4624
4625 if (hw->no_poc_reorder_flag)
4626 hw->dpb.reorder_pic_num = 1;
4627 dpb_print(DECODE_ID(hw), 0,
4628 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4629 __func__, active_buffer_spec_num,
4630 hw->dpb.reorder_pic_num,
4631 hw->max_reference_size);
4632
4633 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4634
4635 mutex_lock(&vmh264_mutex);
4636 if (!hw->mmu_enable) {
4637 config_buf_specs(vdec);
4638 i = get_buf_spec_by_canvas_pos(hw, 0);
4639
4640 if (hw->is_used_v4l) {
4641 if (i != -1) {
4642 pr_info("v4l: delay alloc the buffer.\n");
4643 }
4644 } else {
4645 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4646 config_decode_canvas(hw, i);
4647 else
4648 ret = -1;
4649 }
4650 } else {
4651 if (hw->double_write_mode) {
4652 config_buf_specs_ex(vdec);
4653 } else {
4654 spin_lock_irqsave(&hw->bufspec_lock, flags);
4655 for (i = 0, j = 0;
4656 j < active_buffer_spec_num
4657 && i < BUFSPEC_POOL_SIZE;
4658 i++) {
4659 if (hw->buffer_spec[i].used != -1)
4660 continue;
4661 hw->buffer_spec[i].used = 0;
4662 hw->buffer_spec[i].
4663 alloc_header_addr = 0;
4664 hw->buffer_spec[i].canvas_pos = j;
4665 j++;
4666 }
4667 spin_unlock_irqrestore(&hw->bufspec_lock,
4668 flags);
4669 }
4670 hevc_mcr_config_canv2axitbl(hw, 0);
4671 }
4672 mutex_unlock(&vmh264_mutex);
4673 if (dpb_is_debug(DECODE_ID(hw),
4674 PRINT_FLAG_DUMP_BUFSPEC))
4675 dump_bufspec(hw, __func__);
4676
4677#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4678 buf_size = PAGE_ALIGN(
4679 p_H264_Dpb->colocated_buf_size *
4680 active_buffer_spec_num);
4681#else
4682 buf_size = PAGE_ALIGN(
4683 p_H264_Dpb->colocated_buf_size *
4684 hw->max_reference_size);
4685#endif
4686
4687 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4688 buf_size, DRIVER_NAME,
4689 &hw->collocate_cma_alloc_addr) < 0)
4690 return -1;
4691 if (!vdec_secure(vdec)) {
4692 /* clear for some mosaic problem after reset bufmgr */
4693 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4694 if (colocate_vaddr != NULL) {
4695 memset(colocate_vaddr, 0, buf_size);
4696 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4697 codec_mm_unmap_phyaddr(colocate_vaddr);
4698 }
4699 }
4700
4701 hw->dpb.colocated_mv_addr_start =
4702 hw->collocate_cma_alloc_addr;
4703#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4704 hw->dpb.colocated_mv_addr_end =
4705 hw->dpb.colocated_mv_addr_start +
4706 (p_H264_Dpb->colocated_buf_size *
4707 active_buffer_spec_num);
4708#else
4709 hw->dpb.colocated_mv_addr_end =
4710 hw->dpb.colocated_mv_addr_start +
4711 (p_H264_Dpb->colocated_buf_size *
4712 hw->max_reference_size);
4713#endif
4714 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4715 "callocate cma, %lx, %x\n",
4716 hw->collocate_cma_alloc_addr,
4717 hw->dpb.colocated_mv_addr_start);
4718
4719 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4720 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4721 hw->dpb.colocated_mv_addr_start,
4722 hw->dpb.colocated_mv_addr_end);
4723 if (!hw->mmu_enable) {
4724 mutex_lock(&vmh264_mutex);
4725 if (ret >= 0 && hw->decode_pic_count == 0) {
4726 int buf_cnt;
4727 /* h264_reconfig: alloc later*/
4728 buf_cnt = hw->dpb.mDPB.size;
4729
4730 for (j = 1; j < buf_cnt; j++) {
4731 i = get_buf_spec_by_canvas_pos(hw, j);
4732
4733 if (hw->is_used_v4l) {
4734 pr_info("v4l: delay alloc the buffer.\n");
4735 break;
4736 } else if (alloc_one_buf_spec(hw, i) < 0)
4737 break;
4738
4739 config_decode_canvas(hw, i);
4740 }
4741 }
4742 mutex_unlock(&vmh264_mutex);
4743 } else {
4744 vh264_config_canvs_for_mmu(hw);
4745 }
4746
4747 hw->config_bufmgr_done = 1;
4748
4749 /*end of config_bufmgr_done */
4750 }
4751
4752 return ret;
4753}
4754
4755static void vui_config(struct vdec_h264_hw_s *hw)
4756{
4757 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4758 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4759 /*time*/
4760 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4761 hw->time_scale = p_H264_Dpb->time_scale;
4762 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4763
4764 hw->bitstream_restriction_flag =
4765 p_H264_Dpb->bitstream_restriction_flag;
4766 hw->num_reorder_frames =
4767 p_H264_Dpb->num_reorder_frames;
4768 hw->max_dec_frame_buffering =
4769 p_H264_Dpb->max_dec_frame_buffering;
4770
4771 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4772 "vui_config: pdb %d, %d, %d\n",
4773 p_H264_Dpb->bitstream_restriction_flag,
4774 p_H264_Dpb->num_reorder_frames,
4775 p_H264_Dpb->max_dec_frame_buffering);
4776
4777 hw->fixed_frame_rate_flag = 0;
4778 if (hw->timing_info_present_flag) {
4779 hw->fixed_frame_rate_flag =
4780 p_H264_Dpb->fixed_frame_rate_flag;
4781
4782 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4783 ((!hw->sync_outside) ||
4784 (!hw->frame_dur)))
4785 && hw->num_units_in_tick && hw->time_scale) {
4786 if (hw->use_idr_framerate ||
4787 hw->fixed_frame_rate_flag ||
4788 !hw->frame_dur ||
4789 !hw->duration_from_pts_done
4790 /*|| vh264_running*/) {
4791 u32 frame_dur_es =
4792 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4793 hw->time_scale);
4794 if (hw->frame_dur != frame_dur_es) {
4795 hw->h264_first_valid_pts_ready = false;
4796 hw->h264pts1 = 0;
4797 hw->h264pts2 = 0;
4798 hw->h264_pts_count = 0;
4799 hw->duration_from_pts_done = 0;
4800 fixed_frame_rate_mode =
4801 FIX_FRAME_RATE_OFF;
4802 hw->pts_duration = 0;
4803 hw->frame_dur = frame_dur_es;
4804 vdec_schedule_work(&hw->notify_work);
4805 dpb_print(DECODE_ID(hw),
4806 PRINT_FLAG_DEC_DETAIL,
4807 "frame_dur %d from timing_info\n",
4808 hw->frame_dur);
4809 }
4810
4811 /*hack to avoid use ES frame duration when
4812 *it's half of the rate from system info
4813 * sometimes the encoder is given a wrong
4814 * frame rate but the system side information
4815 * is more reliable
4816 *if ((frame_dur * 2) != frame_dur_es) {
4817 * frame_dur = frame_dur_es;
4818 *}
4819 */
4820 }
4821 }
4822 } else {
4823 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4824 "H.264: timing_info not present\n");
4825 }
4826
4827 /*aspect ratio*/
4828 aspect_ratio_info_present_flag =
4829 p_H264_Dpb->vui_status & 0x1;
4830 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4831
4832 if (aspect_ratio_info_present_flag) {
4833 if (aspect_ratio_idc == EXTEND_SAR) {
4834 hw->h264_ar = 0x3ff;
4835 hw->height_aspect_ratio =
4836 p_H264_Dpb->aspect_ratio_sar_height;
4837 hw->width_aspect_ratio =
4838 p_H264_Dpb->aspect_ratio_sar_width;
4839 } else {
4840 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4841 aspect_ratio_idc); */
4842
4843 switch (aspect_ratio_idc) {
4844 case 1:
4845 hw->h264_ar = 0x3ff;
4846 hw->height_aspect_ratio = 1;
4847 hw->width_aspect_ratio = 1;
4848 break;
4849 case 2:
4850 hw->h264_ar = 0x3ff;
4851 hw->height_aspect_ratio = 11;
4852 hw->width_aspect_ratio = 12;
4853 break;
4854 case 3:
4855 hw->h264_ar = 0x3ff;
4856 hw->height_aspect_ratio = 11;
4857 hw->width_aspect_ratio = 10;
4858 break;
4859 case 4:
4860 hw->h264_ar = 0x3ff;
4861 hw->height_aspect_ratio = 11;
4862 hw->width_aspect_ratio = 16;
4863 break;
4864 case 5:
4865 hw->h264_ar = 0x3ff;
4866 hw->height_aspect_ratio = 33;
4867 hw->width_aspect_ratio = 40;
4868 break;
4869 case 6:
4870 hw->h264_ar = 0x3ff;
4871 hw->height_aspect_ratio = 11;
4872 hw->width_aspect_ratio = 24;
4873 break;
4874 case 7:
4875 hw->h264_ar = 0x3ff;
4876 hw->height_aspect_ratio = 11;
4877 hw->width_aspect_ratio = 20;
4878 break;
4879 case 8:
4880 hw->h264_ar = 0x3ff;
4881 hw->height_aspect_ratio = 11;
4882 hw->width_aspect_ratio = 32;
4883 break;
4884 case 9:
4885 hw->h264_ar = 0x3ff;
4886 hw->height_aspect_ratio = 33;
4887 hw->width_aspect_ratio = 80;
4888 break;
4889 case 10:
4890 hw->h264_ar = 0x3ff;
4891 hw->height_aspect_ratio = 11;
4892 hw->width_aspect_ratio = 18;
4893 break;
4894 case 11:
4895 hw->h264_ar = 0x3ff;
4896 hw->height_aspect_ratio = 11;
4897 hw->width_aspect_ratio = 15;
4898 break;
4899 case 12:
4900 hw->h264_ar = 0x3ff;
4901 hw->height_aspect_ratio = 33;
4902 hw->width_aspect_ratio = 64;
4903 break;
4904 case 13:
4905 hw->h264_ar = 0x3ff;
4906 hw->height_aspect_ratio = 99;
4907 hw->width_aspect_ratio = 160;
4908 break;
4909 case 14:
4910 hw->h264_ar = 0x3ff;
4911 hw->height_aspect_ratio = 3;
4912 hw->width_aspect_ratio = 4;
4913 break;
4914 case 15:
4915 hw->h264_ar = 0x3ff;
4916 hw->height_aspect_ratio = 2;
4917 hw->width_aspect_ratio = 3;
4918 break;
4919 case 16:
4920 hw->h264_ar = 0x3ff;
4921 hw->height_aspect_ratio = 1;
4922 hw->width_aspect_ratio = 2;
4923 break;
4924 default:
4925 if (hw->vh264_ratio >> 16) {
4926 hw->h264_ar = (hw->frame_height *
4927 (hw->vh264_ratio & 0xffff) *
4928 0x100 +
4929 ((hw->vh264_ratio >> 16) *
4930 hw->frame_width / 2)) /
4931 ((hw->vh264_ratio >> 16) *
4932 hw->frame_width);
4933 hw->height_aspect_ratio = 1;
4934 hw->width_aspect_ratio = 1;
4935 } else {
4936 hw->h264_ar = 0x3ff;
4937 hw->height_aspect_ratio = 1;
4938 hw->width_aspect_ratio = 1;
4939 }
4940 break;
4941 }
4942 }
4943 } else {
4944 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4945 "v264dec: aspect_ratio not available from source\n");
4946 if (hw->vh264_ratio >> 16) {
4947 /* high 16 bit is width, low 16 bit is height */
4948 hw->h264_ar =
4949 ((hw->vh264_ratio & 0xffff) *
4950 hw->frame_height * 0x100 +
4951 (hw->vh264_ratio >> 16) *
4952 hw->frame_width / 2) /
4953 ((hw->vh264_ratio >> 16) *
4954 hw->frame_width);
4955 hw->height_aspect_ratio = 1;
4956 hw->width_aspect_ratio = 1;
4957 } else {
4958 hw->h264_ar = 0x3ff;
4959 hw->height_aspect_ratio = 1;
4960 hw->width_aspect_ratio = 1;
4961 }
4962 }
4963
4964 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4965 if (((hw->frame_dur == RATE_2397_FPS)
4966 && (dec_control
4967 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4968 || ((RATE_2997_FPS ==
4969 hw->frame_dur) &&
4970 (dec_control &
4971 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4972 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4973 "force fix frame rate\n");
4974 hw->fixed_frame_rate_flag = 0x40;
4975 }
4976 }
4977
4978 /*video_signal_from_vui: to do .. */
4979}
4980
4981static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4982{
4983 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4984
4985 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4986 if (error_proc_policy & 0x20) {
4987 if (!hw->is_used_v4l)
4988 hw->reset_bufmgr_flag = 1;
4989 }
4990}
4991
4992void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4993{
4994 struct vdec_h264_hw_s *hw =
4995 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4996
4997 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4998
4999 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5000 hw->reset_bufmgr_flag = 1;
5001}
5002
5003#ifdef CONSTRAIN_MAX_BUF_NUM
5004static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5005{
5006 int i;
5007 int count = 0;
5008 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5009 if (is_buf_spec_in_disp_q(hw, i) &&
5010 hw->buffer_spec[i].vf_ref > 0)
5011 count++;
5012 }
5013 return count;
5014}
5015
5016static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5017{
5018 int i;
5019 int count = 0;
5020 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5021 if (is_buf_spec_in_use(hw, i))
5022 count++;
5023 }
5024 return count;
5025}
5026#endif
5027
5028
5029static bool is_buffer_available(struct vdec_s *vdec)
5030{
5031 bool buffer_available = 1;
5032 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5033 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5034 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5035 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5036 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5037 ((p_H264_Dpb->mDPB.init_done) &&
5038 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5039 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5040 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5041 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5042 __func__,
5043 kfifo_len(&hw->newframe_q),
5044 have_free_buf_spec(vdec),
5045 p_H264_Dpb->mDPB.init_done,
5046 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5047 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5048 );
5049 buffer_available = 0;
5050 if (dpb_is_debug(DECODE_ID(hw),
5051 DEBUG_DISABLE_RUNREADY_RMBUF))
5052 return buffer_available;
5053
5054 if ((error_proc_policy & 0x4) &&
5055 (error_proc_policy & 0x8)) {
5056 if ((kfifo_len(&hw->display_q) <= 0) &&
5057 (p_H264_Dpb->mDPB.used_size ==
5058 p_H264_Dpb->mDPB.size) &&
5059 (p_Dpb->ref_frames_in_buffer >
5060 (imax(
5061 1, p_Dpb->num_ref_frames)
5062 - p_Dpb->ltref_frames_in_buffer +
5063 force_sliding_margin)))
5064 bufmgr_recover(hw);
5065 else
5066 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5067 } else if ((error_proc_policy & 0x4) &&
5068 (kfifo_len(&hw->display_q) <= 0) &&
5069 ((p_H264_Dpb->mDPB.used_size ==
5070 p_H264_Dpb->mDPB.size) ||
5071 (!have_free_buf_spec(vdec)))) {
5072 enum receviver_start_e state = RECEIVER_INACTIVE;
5073 if ((error_proc_policy & 0x10) &&
5074 vf_get_receiver(vdec->vf_provider_name)) {
5075 state =
5076 vf_notify_receiver(vdec->vf_provider_name,
5077 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5078 NULL);
5079 if ((state == RECEIVER_STATE_NULL)
5080 || (state == RECEIVER_STATE_NONE))
5081 state = RECEIVER_INACTIVE;
5082 }
5083 if (state == RECEIVER_INACTIVE)
5084 bufmgr_recover(hw);
5085 else
5086 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5087 } else if ((error_proc_policy & 0x8) &&
5088 (p_Dpb->ref_frames_in_buffer >
5089 (imax(
5090 1, p_Dpb->num_ref_frames)
5091 - p_Dpb->ltref_frames_in_buffer +
5092 force_sliding_margin)))
5093 bufmgr_recover(hw);
5094 else
5095 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5096
5097 if (hw->reset_bufmgr_flag == 1)
5098 buffer_available = 1;
5099 }
5100
5101 return buffer_available;
5102}
5103
5104#define AUX_TAG_SEI 0x2
5105
5106#define SEI_BUFFERING_PERIOD 0
5107#define SEI_PicTiming 1
5108#define SEI_USER_DATA 4
5109#define SEI_RECOVERY_POINT 6
5110
5111/*
5112 *************************************************************************
5113 * Function:Reads bits from the bitstream buffer
5114 * Input:
5115 byte buffer[]
5116 containing sei message data bits
5117 int totbitoffset
5118 bit offset from start of partition
5119 int bytecount
5120 total bytes in bitstream
5121 int numbits
5122 number of bits to read
5123 * Output:
5124 int *info
5125 * Return:
5126 -1: failed
5127 > 0: the count of bit read
5128 * Attention:
5129 *************************************************************************
5130 */
5131
5132static int get_bits(unsigned char buffer[],
5133 int totbitoffset,
5134 int *info,
5135 int bytecount,
5136 int numbits)
5137{
5138 register int inf;
5139 long byteoffset;
5140 int bitoffset;
5141
5142 int bitcounter = numbits;
5143
5144 byteoffset = totbitoffset / 8;
5145 bitoffset = 7 - (totbitoffset % 8);
5146
5147 inf = 0;
5148 while (numbits) {
5149 inf <<= 1;
5150 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5151 numbits--;
5152 bitoffset--;
5153 if (bitoffset < 0) {
5154 byteoffset++;
5155 bitoffset += 8;
5156 if (byteoffset > bytecount)
5157 return -1;
5158 }
5159 }
5160
5161 *info = inf;
5162
5163
5164 return bitcounter;
5165}
5166
5167static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5168 u8 *sei_data_buf,
5169 u8 *sei_data_buf_end)
5170{
5171 int payload_type;
5172 int payload_size;
5173 u8 *p_sei;
5174 int temp = 0;
5175 int bit_offset;
5176 int read_size;
5177 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5178
5179 p_sei = sei_data_buf;
5180 read_size = 0;
5181 payload_type = 0;
5182 do {
5183 if (p_sei >= sei_data_buf_end)
5184 return read_size;
5185
5186 payload_type += *p_sei;
5187 read_size++;
5188 } while (*p_sei++ == 255);
5189
5190
5191 payload_size = 0;
5192 do {
5193 if (p_sei >= sei_data_buf_end)
5194 return read_size;
5195
5196 payload_size += *p_sei;
5197 read_size++;
5198 } while (*p_sei++ == 255);
5199
5200
5201 if (p_sei + payload_size > sei_data_buf_end) {
5202 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5203 "%s: payload_type = %d, payload_size = %d is over\n",
5204 __func__, payload_type, payload_size);
5205 return read_size;
5206 }
5207 bit_offset = 0;
5208
5209 if (payload_size <= 0) {
5210 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5211 "%s warning: this is a null sei message for payload_type = %d\n",
5212 __func__, payload_type);
5213 return read_size;
5214 }
5215 switch (payload_type) {
5216 case SEI_BUFFERING_PERIOD:
5217 break;
5218 case SEI_PicTiming:
5219 if (p_H264_Dpb->vui_status & 0xc) {
5220 int cpb_removal_delay;
5221 int dpb_output_delay;
5222 u32 delay_len;
5223
5224 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5225 cpb_removal_delay
5226 = (delay_len & 0x1F) + 1;
5227 dpb_output_delay
5228 = ((delay_len >> 5) & 0x1F) + 1;
5229
5230 get_bits(p_sei, bit_offset,
5231 &temp, payload_size,
5232 dpb_output_delay+cpb_removal_delay);
5233 bit_offset += dpb_output_delay+cpb_removal_delay;
5234 }
5235 if (p_H264_Dpb->vui_status & 0x10) {
5236 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5237 bit_offset += 4;
5238 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5239 }
5240 break;
5241 case SEI_USER_DATA:
5242 if (enable_itu_t35) {
5243 int i;
5244 int j;
5245 int data_len;
5246 u8 *user_data_buf;
5247
5248 user_data_buf
5249 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5250 /* user data length should be align with 8 bytes,
5251 if not, then padding with zero*/
5252 for (i = 0; i < payload_size; i += 8) {
5253 for (j = 0; j < 8; j++) {
5254 int index;
5255
5256 index = i+7-j;
5257 if (index >= payload_size)
5258 user_data_buf[i+j] = 0;
5259 else
5260 user_data_buf[i+j]
5261 = p_sei[i+7-j];
5262 }
5263 }
5264
5265 data_len = payload_size;
5266 if (payload_size % 8)
5267 data_len = ((payload_size + 8) >> 3) << 3;
5268
5269 hw->sei_itu_data_len += data_len;
5270 /*
5271 dpb_print(DECODE_ID(hw), 0,
5272 "%s: user data, and len = %d:\n",
5273 __func__, hw->sei_itu_data_len);
5274 */
5275 }
5276 break;
5277 case SEI_RECOVERY_POINT:
5278 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5279 break;
5280 }
5281
5282 return read_size + payload_size;
5283}
5284
5285static void parse_sei_data(struct vdec_h264_hw_s *hw,
5286 u8 *sei_data_buf,
5287 int len)
5288{
5289 char *p_sei;
5290 char *p_sei_end;
5291 int parsed_size;
5292 int read_size;
5293
5294
5295 p_sei = sei_data_buf;
5296 p_sei_end = p_sei + len;
5297 parsed_size = 0;
5298 while (parsed_size < len) {
5299 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5300 p_sei += read_size;
5301 parsed_size += read_size;
5302 if (*p_sei == 0x80) {
5303 p_sei++;
5304 parsed_size++;
5305 }
5306 }
5307}
5308
5309static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5310{
5311 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5312 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5313 unsigned mby_mbx = READ_VREG(MBY_MBX);
5314 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5315 unsigned decode_mb_count =
5316 ((mby_mbx & 0xff) * hw->mb_width +
5317 (((mby_mbx >> 8) & 0xff) + 1));
5318 if (mby_mbx == 0)
5319 return;
5320 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5321 mb_total /= 2;
5322 if (error_proc_policy & 0x100) {
5323 if (decode_mb_count < mb_total)
5324 p->data_flag |= ERROR_FLAG;
5325 }
5326
5327 if ((error_proc_policy & 0x200) &&
5328 READ_VREG(ERROR_STATUS_REG) != 0) {
5329 p->data_flag |= ERROR_FLAG;
5330 }
5331
5332 if (p->data_flag & ERROR_FLAG) {
5333 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5334 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5335 __func__,
5336 hw->seq_info2,
5337 mby_mbx,
5338 mb_total,
5339 decode_mb_count,
5340 READ_VREG(ERROR_STATUS_REG)
5341 );
5342
5343 }
5344}
5345
5346static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5347{
5348 int i;
5349 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5350 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5351 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5352 u32 debug_tag;
5353 int ret;
5354
5355 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5356#if 1
5357 unsigned short *p = (unsigned short *)hw->lmem_addr;
5358 dma_sync_single_for_cpu(
5359 amports_get_dma_device(),
5360 hw->lmem_addr_remap,
5361 PAGE_SIZE,
5362 DMA_FROM_DEVICE);
5363 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5364 int ii;
5365 for (ii = 0; ii < 4; ii++) {
5366 p_H264_Dpb->dpb_param.l.data[i+ii] =
5367 p[i+3-ii];
5368 if (dpb_is_debug(DECODE_ID(hw),
5369 RRINT_FLAG_RPM)) {
5370 if (((i + ii) & 0xf) == 0)
5371 dpb_print(DECODE_ID(hw),
5372 0, "%04x:",
5373 i);
5374 dpb_print_cont(DECODE_ID(hw),
5375 0, "%04x ",
5376 p[i+3-ii]);
5377 if (((i + ii + 1) & 0xf) == 0)
5378 dpb_print_cont(
5379 DECODE_ID(hw),
5380 0, "\r\n");
5381 }
5382 }
5383 }
5384
5385 p_H264_Dpb->bitstream_restriction_flag =
5386 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5387 p_H264_Dpb->num_reorder_frames =
5388 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5389 p_H264_Dpb->max_dec_frame_buffering =
5390 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5391
5392 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5393 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5394 p_H264_Dpb->bitstream_restriction_flag,
5395 p_H264_Dpb->num_reorder_frames,
5396 p_H264_Dpb->max_dec_frame_buffering);
5397 hw->bitstream_restriction_flag =
5398 p_H264_Dpb->bitstream_restriction_flag;
5399 hw->num_reorder_frames =
5400 p_H264_Dpb->num_reorder_frames;
5401 hw->max_dec_frame_buffering =
5402 p_H264_Dpb->max_dec_frame_buffering;
5403#endif
5404
5405 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5406 reset_process_time(hw);
5407 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5408 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5409 vdec_schedule_work(&hw->work);
5410 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5411 u16 data_hight;
5412 u16 data_low;
5413 u32 video_signal;
5414
5415 int slice_header_process_status = 0;
5416 int I_flag;
5417 /*unsigned char is_idr;*/
5418 unsigned short *p = (unsigned short *)hw->lmem_addr;
5419 reset_process_time(hw);
5420
5421 if (hw->is_used_v4l) {
5422 struct aml_vcodec_ctx *ctx =
5423 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5424
5425 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5426 //amvdec_stop();
5427 hw->dec_result = DEC_RESULT_DONE;
5428 vdec_schedule_work(&hw->work);
5429 return IRQ_HANDLED;
5430 }
5431 }
5432
5433 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5434 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5435 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5436 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5437 if (input_frame_based(vdec) &&
5438 frmbase_cont_bitlevel2 != 0 &&
5439 READ_VREG(VIFF_BIT_CNT) <
5440 frmbase_cont_bitlevel2 &&
5441 hw->get_data_count >= 0x70000000) {
5442 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5443 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5444 __func__,
5445 READ_VREG(VIFF_BIT_CNT));
5446
5447 goto empty_proc;
5448 }
5449
5450 dma_sync_single_for_cpu(
5451 amports_get_dma_device(),
5452 hw->lmem_addr_remap,
5453 PAGE_SIZE,
5454 DMA_FROM_DEVICE);
5455#if 0
5456 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5457 if (!is_buffer_available(vdec)) {
5458 hw->buffer_empty_flag = 1;
5459 dpb_print(DECODE_ID(hw),
5460 PRINT_FLAG_UCODE_EVT,
5461 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5462 __func__,
5463 kfifo_len(&hw->newframe_q),
5464 have_free_buf_spec(vdec),
5465 p_H264_Dpb->mDPB.init_done,
5466 p_H264_Dpb->mDPB.used_size,
5467 p_H264_Dpb->mDPB.size,
5468 is_there_unused_frame_from_dpb(
5469 &p_H264_Dpb->mDPB));
5470 return IRQ_HANDLED;
5471 }
5472 }
5473
5474 hw->buffer_empty_flag = 0;
5475#endif
5476#ifdef SEND_PARAM_WITH_REG
5477 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5478 unsigned int data32;
5479
5480 do {
5481 data32 = READ_VREG(RPM_CMD_REG);
5482 /* printk("%x\n", data32); */
5483 } while ((data32&0x10000) == 0);
5484 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5485 WRITE_VREG(RPM_CMD_REG, 0);
5486 /* printk("%x:%x\n", i,data32); */
5487 }
5488#else
5489 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5490 int ii;
5491
5492 for (ii = 0; ii < 4; ii++) {
5493 p_H264_Dpb->dpb_param.l.data[i+ii] =
5494 p[i+3-ii];
5495 if (dpb_is_debug(DECODE_ID(hw),
5496 RRINT_FLAG_RPM)) {
5497 if (((i + ii) & 0xf) == 0)
5498 dpb_print(DECODE_ID(hw),
5499 0, "%04x:",
5500 i);
5501 dpb_print_cont(DECODE_ID(hw),
5502 0, "%04x ",
5503 p[i+3-ii]);
5504 if (((i + ii + 1) & 0xf) == 0)
5505 dpb_print_cont(
5506 DECODE_ID(hw),
5507 0, "\r\n");
5508 }
5509 }
5510 }
5511#endif
5512 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5513 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5514
5515 video_signal = (data_hight << 16) | data_low;
5516 hw->video_signal_from_vui =
5517 ((video_signal & 0xffff) << 8) |
5518 ((video_signal & 0xff0000) >> 16) |
5519 ((video_signal & 0x3f000000));
5520
5521
5522 /*dpb_print(DECODE_ID(hw),
5523 0,
5524 "video_signal_from_vui:0x%x, "
5525 "data_low:0x%x, data_hight:0x%x\n",
5526 hw->video_signal_from_vui,
5527 data_low,
5528 data_hight);*/
5529
5530 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5531
5532 if (hw->config_bufmgr_done == 0) {
5533 hw->dec_result = DEC_RESULT_DONE;
5534 vdec_schedule_work(&hw->work);
5535 dpb_print(DECODE_ID(hw),
5536 PRINT_FLAG_UCODE_EVT,
5537 "config_bufmgr not done, discard frame\n");
5538 return IRQ_HANDLED;
5539 } else if ((hw->first_i_policy & 0x3) != 0) {
5540 unsigned char is_i_slice =
5541 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5542 == I_Slice)
5543 ? 1 : 0;
5544 unsigned char is_idr =
5545 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5546 == 5);
5547 if ((hw->first_i_policy & 0x3) == 0x3)
5548 is_i_slice = is_idr;
5549 if (!is_i_slice) {
5550 if (hw->has_i_frame == 0) {
5551 amvdec_stop();
5552 vdec->mc_loaded = 0;
5553 hw->dec_result = DEC_RESULT_DONE;
5554 vdec_schedule_work(&hw->work);
5555 dpb_print(DECODE_ID(hw),
5556 PRINT_FLAG_UCODE_EVT,
5557 "has_i_frame is 0, discard none I(DR) frame\n");
5558 return IRQ_HANDLED;
5559 }
5560 } else {
5561 if (hw->skip_frame_count < 0 || is_idr) {
5562 /* second I */
5563 hw->dec_flag &= (~NODISP_FLAG);
5564 hw->skip_frame_count = 0;
5565 }
5566 if (hw->has_i_frame == 0 &&
5567 (!is_idr)) {
5568 int skip_count =
5569 (hw->first_i_policy >> 8) & 0xff;
5570 /* first I (not IDR) */
5571 if ((hw->first_i_policy & 0x3) == 2)
5572 hw->skip_frame_count =
5573 -1 - skip_count;
5574 else
5575 hw->skip_frame_count =
5576 skip_count;
5577 if (hw->skip_frame_count != 0)
5578 hw->dec_flag |= NODISP_FLAG;
5579 }
5580 }
5581 }
5582 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5583 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5584 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5585 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5586 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5587 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5588 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5589 ? I_FLAG : 0;
5590
5591 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5592 flush_dpb(p_H264_Dpb);
5593
5594 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5595 (p_H264_Dpb->mSlice.structure == FRAME)) {
5596 hw->data_flag = NULL_FLAG;
5597 goto pic_done_proc;
5598 }
5599
5600 slice_header_process_status =
5601 h264_slice_header_process(p_H264_Dpb);
5602 if (hw->mmu_enable)
5603 hevc_sao_set_slice_type(hw,
5604 slice_header_process_status,
5605 hw->dpb.mSlice.idr_flag);
5606 vui_config(hw);
5607
5608 if (p_H264_Dpb->mVideo.dec_picture) {
5609 int cfg_ret = 0;
5610 bool field_pic_flag = false;
5611
5612 if (slice_header_process_status == 1) {
5613 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5614 field_pic_flag =
5615 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5616 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5617 true : false;
5618 }
5619
5620 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5621 (((unsigned long)(hw->vh264_amstream_dec_info
5622 .param)) & 0x8))) {
5623 p_H264_Dpb->fast_output_enable =
5624 H264_OUTPUT_MODE_FAST;
5625 }
5626 else
5627 p_H264_Dpb->fast_output_enable
5628 = fast_output_enable;
5629 hw->data_flag = I_flag;
5630 if ((p_H264_Dpb->
5631 dpb_param.dpb.NAL_info_mmco & 0x1f)
5632 == 5)
5633 hw->data_flag |= IDR_FLAG;
5634 dpb_print(DECODE_ID(hw),
5635 PRINT_FLAG_VDEC_STATUS,
5636 "==================> frame count %d to skip %d\n",
5637 hw->decode_pic_count+1,
5638 hw->skip_frame_count);
5639 } else if (error_proc_policy & 0x100){
5640 struct StorablePicture *p =
5641 p_H264_Dpb->mVideo.dec_picture;
5642 unsigned mby_mbx = READ_VREG(MBY_MBX);
5643 unsigned decode_mb_count =
5644 ((mby_mbx & 0xff) * hw->mb_width +
5645 (((mby_mbx >> 8) & 0xff) + 1));
5646 if (decode_mb_count <
5647 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5648 (1 + p->mb_aff_frame_flag))) {
5649 dpb_print(DECODE_ID(hw),
5650 PRINT_FLAG_VDEC_STATUS,
5651 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5652 p_H264_Dpb->dpb_param.l.
5653 data[FIRST_MB_IN_SLICE],
5654 READ_VREG(MBY_MBX),
5655 decode_mb_count);
5656 p->data_flag |= ERROR_FLAG;
5657 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5658 p->data_flag |= ERROR_FLAG;
5659 goto pic_done_proc;
5660 }
5661 }
5662
5663 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5664 hw->new_iframe_flag = 1;
5665 }
5666 if (hw->new_iframe_flag) {
5667 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5668 hw->new_iframe_flag = 0;
5669 hw->ref_err_flush_dpb_flag = 1;
5670 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5671 hw->new_iframe_flag = 0;
5672 hw->ref_err_flush_dpb_flag = 0;
5673 }
5674 }
5675
5676 if (error_proc_policy & 0x400) {
5677 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5678 if (ret != 0) {
5679 hw->reflist_error_count ++;
5680 dpb_print(DECODE_ID(hw), 0,
5681 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5682 ret,
5683 hw->decode_pic_count+1,
5684 hw->skip_frame_count,
5685 hw->reflist_error_count);
5686
5687 if (hw->ref_err_flush_dpb_flag) {
5688 flush_dpb(p_H264_Dpb);
5689 p_H264_Dpb->colocated_buf_map = 0;
5690 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5691 p_H264_Dpb->colocated_buf_map |= 1 <<
5692 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5693 }
5694 }
5695
5696 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5697 if (((error_proc_policy & 0x80)
5698 && ((hw->dec_flag &
5699 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5700 hw->reset_bufmgr_flag = 1;
5701 hw->reflist_error_count =0;
5702 amvdec_stop();
5703 vdec->mc_loaded = 0;
5704 hw->dec_result = DEC_RESULT_DONE;
5705 vdec_schedule_work(&hw->work);
5706 return IRQ_HANDLED;
5707 }
5708 } else
5709 hw->reflist_error_count = 0;
5710 }
5711 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5712 && p_H264_Dpb->dpb_error_flag != 0) {
5713 dpb_print(DECODE_ID(hw), 0,
5714 "dpb error %d\n",
5715 p_H264_Dpb->dpb_error_flag);
5716 hw->data_flag |= ERROR_FLAG;
5717 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5718 if ((error_proc_policy & 0x80) &&
5719 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5720 hw->reset_bufmgr_flag = 1;
5721 amvdec_stop();
5722 vdec->mc_loaded = 0;
5723 hw->dec_result = DEC_RESULT_DONE;
5724 vdec_schedule_work(&hw->work);
5725 return IRQ_HANDLED;
5726 }
5727 }
5728
5729 cfg_ret = config_decode_buf(hw,
5730 p_H264_Dpb->mVideo.dec_picture);
5731 if (cfg_ret < 0) {
5732 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5733 "config_decode_buf fail (%d)\n",
5734 cfg_ret);
5735 if (error_proc_policy & 0x2) {
5736 release_cur_decoding_buf(hw);
5737 /*hw->data_flag |= ERROR_FLAG;*/
5738 hw->reset_bufmgr_flag = 1;
5739 hw->dec_result = DEC_RESULT_DONE;
5740 vdec_schedule_work(&hw->work);
5741 return IRQ_HANDLED;
5742 } else
5743 hw->data_flag |= ERROR_FLAG;
5744 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5745 }
5746 }
5747
5748 if (slice_header_process_status == 1)
5749 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5750 else
5751 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5752 hw->last_mby_mbx = 0;
5753 hw->last_vld_level = 0;
5754 start_process_time(hw);
5755 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5756 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5757pic_done_proc:
5758 reset_process_time(hw);
5759
5760 if (input_frame_based(vdec) &&
5761 (!(hw->i_only & 0x2)) &&
5762 frmbase_cont_bitlevel != 0 &&
5763 READ_VREG(VIFF_BIT_CNT) >
5764 frmbase_cont_bitlevel) {
5765 /*handle the case: multi pictures in one packet*/
5766 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5767 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5768 __func__,
5769 hw->decode_pic_count,
5770 READ_VREG(VIFF_BIT_CNT));
5771 hw->frmbase_cont_flag = 1;
5772 } else
5773 hw->frmbase_cont_flag = 0;
5774
5775 if (p_H264_Dpb->mVideo.dec_picture) {
5776 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5777#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5778 DEL_EXIST(hw,
5779 p_H264_Dpb->mVideo.dec_picture) = 0;
5780 if (vdec->master) {
5781 struct vdec_h264_hw_s *hw_ba =
5782 (struct vdec_h264_hw_s *)
5783 vdec->master->private;
5784 if (hw_ba->last_dec_picture)
5785 DEL_EXIST(hw_ba,
5786 hw_ba->last_dec_picture)
5787 = 1;
5788 }
5789#endif
5790 mutex_lock(&hw->chunks_mutex);
5791 if (hw->chunk) {
5792 p_H264_Dpb->mVideo.dec_picture->pts =
5793 hw->chunk->pts;
5794 p_H264_Dpb->mVideo.dec_picture->pts64 =
5795 hw->chunk->pts64;
5796 p_H264_Dpb->mVideo.dec_picture->timestamp =
5797 hw->chunk->timestamp;
5798#ifdef MH264_USERDATA_ENABLE
5799 vmh264_udc_fill_vpts(hw,
5800 p_H264_Dpb->mSlice.slice_type,
5801 hw->chunk->pts, 1);
5802#endif
5803
5804#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5805 } else if (vdec->master) {
5806 /*dv enhance layer,
5807 do not checkout pts*/
5808 struct StorablePicture *pic =
5809 p_H264_Dpb->mVideo.dec_picture;
5810 pic->pts = 0;
5811 pic->pts64 = 0;
5812#endif
5813 } else {
5814 struct StorablePicture *pic =
5815 p_H264_Dpb->mVideo.dec_picture;
5816 u32 offset = pic->offset_delimiter;
5817 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5818 offset, &pic->pts, 0, &pic->pts64)) {
5819 pic->pts = 0;
5820 pic->pts64 = 0;
5821#ifdef MH264_USERDATA_ENABLE
5822 vmh264_udc_fill_vpts(hw,
5823 p_H264_Dpb->mSlice.slice_type,
5824 pic->pts, 0);
5825#endif
5826 } else {
5827#ifdef MH264_USERDATA_ENABLE
5828 vmh264_udc_fill_vpts(hw,
5829 p_H264_Dpb->mSlice.slice_type,
5830 pic->pts, 1);
5831#endif
5832 }
5833
5834 }
5835 mutex_unlock(&hw->chunks_mutex);
5836
5837 check_decoded_pic_error(hw);
5838#ifdef ERROR_HANDLE_TEST
5839 if ((hw->data_flag & ERROR_FLAG)
5840 && (error_proc_policy & 0x80)) {
5841 release_cur_decoding_buf(hw);
5842 h264_clear_dpb(hw);
5843 hw->dec_flag = 0;
5844 hw->data_flag = 0;
5845 hw->skip_frame_count = 0;
5846 hw->has_i_frame = 0;
5847 hw->no_error_count = 0xfff;
5848 hw->no_error_i_count = 0xf;
5849 } else
5850#endif
5851 ret = store_picture_in_dpb(p_H264_Dpb,
5852 p_H264_Dpb->mVideo.dec_picture,
5853 hw->data_flag | hw->dec_flag |
5854 p_H264_Dpb->mVideo.dec_picture->data_flag);
5855
5856
5857
5858 if (ret == -1) {
5859 release_cur_decoding_buf(hw);
5860 bufmgr_force_recover(p_H264_Dpb);
5861 } else {
5862 if (hw->data_flag & ERROR_FLAG) {
5863 hw->no_error_count = 0;
5864 hw->no_error_i_count = 0;
5865 } else {
5866 hw->no_error_count++;
5867 if (hw->data_flag & I_FLAG)
5868 hw->no_error_i_count++;
5869 }
5870 if (hw->mmu_enable)
5871 hevc_set_unused_4k_buff_idx(hw,
5872 p_H264_Dpb->mVideo.
5873 dec_picture->buf_spec_num);
5874 bufmgr_post(p_H264_Dpb);
5875 hw->last_dec_picture =
5876 p_H264_Dpb->mVideo.dec_picture;
5877 p_H264_Dpb->mVideo.dec_picture = NULL;
5878 /* dump_dpb(&p_H264_Dpb->mDPB); */
5879 hw->has_i_frame = 1;
5880 if (hw->mmu_enable)
5881 hevc_set_frame_done(hw);
5882 hw->decode_pic_count++;
5883 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5884 if (hw->skip_frame_count > 0) {
5885 /*skip n frame after first I */
5886 hw->skip_frame_count--;
5887 if (hw->skip_frame_count == 0)
5888 hw->dec_flag &= (~NODISP_FLAG);
5889 } else if (hw->skip_frame_count < -1) {
5890 /*skip n frame after first I until second I */
5891 hw->skip_frame_count++;
5892 if (hw->skip_frame_count == -1)
5893 hw->dec_flag &= (~NODISP_FLAG);
5894 }
5895 }
5896 }
5897 if (hw->frmbase_cont_flag) {
5898 /*do not DEC_RESULT_GET_DATA*/
5899 hw->get_data_count = 0x7fffffff;
5900 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5901 decode_frame_count[DECODE_ID(hw)]++;
5902 start_process_time(hw);
5903 return IRQ_HANDLED;
5904 }
5905 amvdec_stop();
5906 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5907 "%s %s decode slice count %d\n",
5908 __func__,
5909 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5910 "H264_PIC_DATA_DONE" :
5911 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5912 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5913 hw->decode_pic_count);
5914 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5915 hw->dec_result = DEC_RESULT_DONE;
5916#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5917 if (vdec->slave &&
5918 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5919 struct vdec_h264_hw_s *hw_el =
5920 (struct vdec_h264_hw_s *)(vdec->slave->private);
5921 hw_el->got_valid_nal = 0;
5922 hw->switch_dvlayer_flag = 1;
5923 } else if (vdec->master &&
5924 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5925 struct vdec_h264_hw_s *hw_bl =
5926 (struct vdec_h264_hw_s *)(vdec->master->private);
5927 hw_bl->got_valid_nal = 0;
5928 hw->switch_dvlayer_flag = 1;
5929 } else {
5930 hw->switch_dvlayer_flag = 0;
5931 hw->got_valid_nal = 1;
5932 }
5933#endif
5934
5935 hw->dec_result = DEC_RESULT_DONE;
5936 vdec_schedule_work(&hw->work);
5937
5938#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5939 } else if (
5940 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5941 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5942 goto pic_done_proc;
5943#endif
5944 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5945 reset_process_time(hw);
5946 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5947 dma_sync_single_for_cpu(
5948 amports_get_dma_device(),
5949 hw->aux_phy_addr,
5950 hw->prefix_aux_size + hw->suffix_aux_size,
5951 DMA_FROM_DEVICE);
5952 if (dpb_is_debug(DECODE_ID(hw),
5953 PRINT_FLAG_DPB_DETAIL))
5954 dump_aux_buf(hw);
5955#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5956 if (vdec->dolby_meta_with_el || vdec->slave) {
5957 if (hw->last_dec_picture)
5958 set_aux_data(hw, hw->last_dec_picture,
5959 0, 0, NULL);
5960 } else {
5961 if (vdec->master) {
5962 struct vdec_h264_hw_s *hw_bl =
5963 (struct vdec_h264_hw_s *)
5964 (vdec->master->private);
5965 if (hw_bl->last_dec_picture != NULL) {
5966 set_aux_data(hw_bl,
5967 hw_bl->last_dec_picture,
5968 0, 1, hw);
5969 }
5970 set_aux_data(hw,
5971 hw->last_dec_picture,
5972 0, 2, NULL);
5973 }
5974 }
5975#else
5976 if (hw->last_dec_picture)
5977 set_aux_data(hw,
5978 hw->last_dec_picture, 0, 0, NULL);
5979#endif
5980 }
5981#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5982 hw->switch_dvlayer_flag = 0;
5983 hw->got_valid_nal = 1;
5984#endif
5985 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5986 "%s H264_AUX_DATA_READY\n", __func__);
5987 hw->dec_result = DEC_RESULT_DONE;
5988 vdec_schedule_work(&hw->work);
5989 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5990 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5991 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5992 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5993empty_proc:
5994 reset_process_time(hw);
5995 if (!hw->frmbase_cont_flag)
5996 release_cur_decoding_buf(hw);
5997
5998 if (input_frame_based(vdec) ||
5999 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6000 if (h264_debug_flag &
6001 DISABLE_ERROR_HANDLE) {
6002 dpb_print(DECODE_ID(hw),
6003 PRINT_FLAG_ERROR,
6004 "%s decoding error, level 0x%x\n",
6005 __func__,
6006 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6007 goto send_again;
6008 }
6009 amvdec_stop();
6010 vdec->mc_loaded = 0;
6011 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6012 "%s %s\n", __func__,
6013 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6014 "H264_SEARCH_BUFEMPTY" :
6015 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6016 "H264_DECODE_BUFEMPTY" :
6017 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6018 "H264_DECODE_TIMEOUT" :
6019 "OTHER");
6020 hw->dec_result = DEC_RESULT_DONE;
6021
6022 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6023 hw->search_dataempty_num++;
6024 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6025 hw->decode_timeout_num++;
6026 if (error_proc_policy & 0x4000) {
6027 hw->data_flag |= ERROR_FLAG;
6028 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6029 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6030 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6031 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6032 dpb_print(DECODE_ID(hw),
6033 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6034 p_H264_Dpb->last_dpb_status, __func__);
6035 hw->reset_bufmgr_flag = 1;
6036 }
6037 }
6038 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6039 hw->decode_dataempty_num++;
6040 if (!hw->frmbase_cont_flag)
6041 hw->data_flag |= ERROR_FLAG;
6042
6043 vdec_schedule_work(&hw->work);
6044 } else {
6045 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6046 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6047 "%s DEC_RESULT_AGAIN\n", __func__);
6048send_again:
6049 hw->dec_result = DEC_RESULT_AGAIN;
6050 vdec_schedule_work(&hw->work);
6051 }
6052 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6053 reset_process_time(hw);
6054 if (input_frame_based(vdec)) {
6055 dpb_print(DECODE_ID(hw),
6056 PRINT_FLAG_VDEC_STATUS,
6057 "%s H264_DATA_REQUEST (%d)\n",
6058 __func__, hw->get_data_count);
6059 hw->dec_result = DEC_RESULT_GET_DATA;
6060 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6061 hw->get_data_start_time = jiffies;
6062 hw->get_data_count++;
6063 if (hw->get_data_count >= frame_max_data_packet)
6064 goto empty_proc;
6065 vdec_schedule_work(&hw->work);
6066 } else
6067 goto empty_proc;
6068 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6069 dpb_print(DECODE_ID(hw), 0,
6070 "vmh264 decode oversize !!\n");
6071 release_cur_decoding_buf(hw);
6072 hw->data_flag |= ERROR_FLAG;
6073 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6074 reset_process_time(hw);
6075 hw->dec_result = DEC_RESULT_DONE;
6076 vdec_schedule_work(&hw->work);
6077 return IRQ_HANDLED;
6078 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6079 int aux_data_len;
6080 aux_data_len =
6081 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6082
6083 if (aux_data_len > SEI_DATA_SIZE) {
6084 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6085 "sei data size more than 4K: %d, discarded it\n",
6086 hw->sei_itu_data_len);
6087 hw->sei_itu_data_len = 0;
6088 }
6089
6090 if (aux_data_len != 0) {
6091 u8 *trans_data_buf;
6092 u8 *sei_data_buf;
6093 u8 swap_byte;
6094
6095 dma_sync_single_for_cpu(
6096 amports_get_dma_device(),
6097 hw->aux_phy_addr,
6098 hw->prefix_aux_size + hw->suffix_aux_size,
6099 DMA_FROM_DEVICE);
6100#if 0
6101 dump_aux_buf(hw);
6102#endif
6103 trans_data_buf = (u8 *)hw->aux_addr;
6104
6105 if (trans_data_buf[7] == AUX_TAG_SEI) {
6106 int left_len;
6107
6108 sei_data_buf = (u8 *)hw->sei_data_buf
6109 + hw->sei_data_len;
6110 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6111 if (aux_data_len/2 <= left_len) {
6112 for (i = 0; i < aux_data_len/2; i++)
6113 sei_data_buf[i]
6114 = trans_data_buf[i*2];
6115
6116 aux_data_len = aux_data_len / 2;
6117 for (i = 0; i < aux_data_len; i = i+4) {
6118 swap_byte = sei_data_buf[i];
6119 sei_data_buf[i]
6120 = sei_data_buf[i+3];
6121 sei_data_buf[i+3] = swap_byte;
6122
6123 swap_byte = sei_data_buf[i+1];
6124 sei_data_buf[i+1]
6125 = sei_data_buf[i+2];
6126 sei_data_buf[i+2] = swap_byte;
6127 }
6128
6129 for (i = aux_data_len-1; i >= 0; i--)
6130 if (sei_data_buf[i] != 0)
6131 break;
6132
6133 hw->sei_data_len += i+1;
6134 } else
6135 dpb_print(DECODE_ID(hw),
6136 PRINT_FLAG_ERROR,
6137 "sei data size %d and more than left space: %d, discarded it\n",
6138 hw->sei_itu_data_len,
6139 left_len);
6140 }
6141 }
6142 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6143
6144 return IRQ_HANDLED;
6145 }
6146
6147
6148 /* ucode debug */
6149 debug_tag = READ_VREG(DEBUG_REG1);
6150 if (debug_tag & 0x10000) {
6151 unsigned short *p = (unsigned short *)hw->lmem_addr;
6152
6153 dma_sync_single_for_cpu(
6154 amports_get_dma_device(),
6155 hw->lmem_addr_remap,
6156 PAGE_SIZE,
6157 DMA_FROM_DEVICE);
6158
6159 dpb_print(DECODE_ID(hw), 0,
6160 "LMEM<tag %x>:\n", debug_tag);
6161 for (i = 0; i < 0x400; i += 4) {
6162 int ii;
6163 if ((i & 0xf) == 0)
6164 dpb_print_cont(DECODE_ID(hw), 0,
6165 "%03x: ", i);
6166 for (ii = 0; ii < 4; ii++)
6167 dpb_print_cont(DECODE_ID(hw), 0,
6168 "%04x ", p[i+3-ii]);
6169 if (((i+ii) & 0xf) == 0)
6170 dpb_print_cont(DECODE_ID(hw), 0,
6171 "\n");
6172 }
6173 if (((udebug_pause_pos & 0xffff)
6174 == (debug_tag & 0xffff)) &&
6175 (udebug_pause_decode_idx == 0 ||
6176 udebug_pause_decode_idx ==
6177 hw->decode_pic_count) &&
6178 (udebug_pause_val == 0 ||
6179 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6180 udebug_pause_pos &= 0xffff;
6181 hw->ucode_pause_pos = udebug_pause_pos;
6182 }
6183 else if (debug_tag & 0x20000)
6184 hw->ucode_pause_pos = 0xffffffff;
6185 if (hw->ucode_pause_pos)
6186 reset_process_time(hw);
6187 else
6188 WRITE_VREG(DEBUG_REG1, 0);
6189 } else if (debug_tag != 0) {
6190 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6191 "dbg%x: %x\n", debug_tag,
6192 READ_VREG(DEBUG_REG2));
6193 if (((udebug_pause_pos & 0xffff)
6194 == (debug_tag & 0xffff)) &&
6195 (udebug_pause_decode_idx == 0 ||
6196 udebug_pause_decode_idx ==
6197 hw->decode_pic_count) &&
6198 (udebug_pause_val == 0 ||
6199 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6200 udebug_pause_pos &= 0xffff;
6201 hw->ucode_pause_pos = udebug_pause_pos;
6202 }
6203 if (hw->ucode_pause_pos)
6204 reset_process_time(hw);
6205 else
6206 WRITE_VREG(DEBUG_REG1, 0);
6207 }
6208 /**/
6209 return IRQ_HANDLED;
6210}
6211
6212static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6213{
6214 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6215 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6216
6217
6218 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6219
6220 if (!hw)
6221 return IRQ_HANDLED;
6222
6223 if (hw->eos)
6224 return IRQ_HANDLED;
6225
6226 p_H264_Dpb->vdec = vdec;
6227 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6228
6229 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6230 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6231 __func__,
6232 p_H264_Dpb->dec_dpb_status,
6233 READ_VREG(ERROR_STATUS_REG),
6234 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6235 READ_VREG(VLD_MEM_VIFIFO_WP),
6236 READ_VREG(VLD_MEM_VIFIFO_RP),
6237 READ_VREG(VIFF_BIT_CNT),
6238 READ_VREG(MBY_MBX));
6239
6240 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6241 if (hw->mmu_enable)
6242 hevc_sao_wait_done(hw);
6243 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6244 return IRQ_HANDLED;
6245 }
6246 return IRQ_WAKE_THREAD;
6247
6248}
6249
6250static void timeout_process(struct vdec_h264_hw_s *hw)
6251{
6252 struct vdec_s *vdec = hw_to_vdec(hw);
6253 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6254
6255 /*
6256 * In this very timeout point,the vh264_work arrives,
6257 * let it to handle the scenario.
6258 */
6259 if (work_pending(&hw->work))
6260 return;
6261
6262 hw->timeout_num++;
6263 amvdec_stop();
6264 vdec->mc_loaded = 0;
6265 if (hw->mmu_enable) {
6266 hevc_set_frame_done(hw);
6267 hevc_sao_wait_done(hw);
6268 }
6269 if (!hw->i_only && (error_proc_policy & 0x2))
6270 flush_dpb(p_H264_Dpb);
6271 dpb_print(DECODE_ID(hw),
6272 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6273 release_cur_decoding_buf(hw);
6274 hw->dec_result = DEC_RESULT_DONE;
6275 hw->data_flag |= ERROR_FLAG;
6276
6277 if (work_pending(&hw->work))
6278 return;
6279 vdec_schedule_work(&hw->timeout_work);
6280}
6281
6282static void dump_bufspec(struct vdec_h264_hw_s *hw,
6283 const char *caller)
6284{
6285 int i;
6286 dpb_print(DECODE_ID(hw), 0,
6287 "%s in %s:\n", __func__, caller);
6288 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6289 if (hw->buffer_spec[i].used == -1)
6290 continue;
6291 dpb_print(DECODE_ID(hw), 0,
6292 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6293 i, hw->buffer_spec[i].used,
6294 hw->buffer_spec[i].buf_adr,
6295 hw->buffer_spec[i].canvas_pos,
6296 hw->buffer_spec[i].vf_ref
6297 );
6298#ifdef CONFIG_AM_VDEC_DV
6299 dpb_print_cont(DECODE_ID(hw), 0,
6300 "dv_el_exist %d",
6301 hw->buffer_spec[i].dv_enhance_exist
6302 );
6303#endif
6304 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6305 }
6306
6307}
6308
6309static void vmh264_dump_state(struct vdec_s *vdec)
6310{
6311 struct vdec_h264_hw_s *hw =
6312 (struct vdec_h264_hw_s *)(vdec->private);
6313 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6314 dpb_print(DECODE_ID(hw), 0,
6315 "====== %s\n", __func__);
6316 dpb_print(DECODE_ID(hw), 0,
6317 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6318 hw->frame_width,
6319 hw->frame_height,
6320 hw->dpb.reorder_pic_num,
6321 hw->dpb.mDPB.size,
6322 hw->max_reference_size,
6323 hw->i_only,
6324 hw->send_error_frame_flag
6325 );
6326
6327 dpb_print(DECODE_ID(hw), 0,
6328 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6329 input_frame_based(vdec),
6330 hw->eos,
6331 hw->stat,
6332 hw->dec_result,
6333 decode_frame_count[DECODE_ID(hw)],
6334 display_frame_count[DECODE_ID(hw)],
6335 run_count[DECODE_ID(hw)],
6336 not_run_ready[DECODE_ID(hw)],
6337 input_empty[DECODE_ID(hw)],
6338 hw->reset_bufmgr_count
6339 );
6340
6341 if (vf_get_receiver(vdec->vf_provider_name)) {
6342 enum receviver_start_e state =
6343 vf_notify_receiver(vdec->vf_provider_name,
6344 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6345 NULL);
6346 dpb_print(DECODE_ID(hw), 0,
6347 "\nreceiver(%s) state %d\n",
6348 vdec->vf_provider_name,
6349 state);
6350 }
6351
6352 dpb_print(DECODE_ID(hw), 0,
6353 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x wait_reset_done_flag %d\n",
6354 __func__,
6355 kfifo_len(&hw->newframe_q),
6356 VF_POOL_SIZE,
6357 kfifo_len(&hw->display_q),
6358 VF_POOL_SIZE,
6359 hw->vf_pre_count,
6360 hw->vf_get_count,
6361 hw->vf_put_count,
6362 have_free_buf_spec(vdec),
6363 p_H264_Dpb->mDPB.init_done,
6364 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6365 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6366 p_H264_Dpb->fast_output_enable,
6367 hw->wait_reset_done_flag
6368 );
6369
6370 dump_dpb(&p_H264_Dpb->mDPB, 1);
6371 dump_pic(p_H264_Dpb);
6372 dump_bufspec(hw, __func__);
6373
6374 dpb_print(DECODE_ID(hw), 0,
6375 "DPB_STATUS_REG=0x%x\n",
6376 READ_VREG(DPB_STATUS_REG));
6377 dpb_print(DECODE_ID(hw), 0,
6378 "MPC_E=0x%x\n",
6379 READ_VREG(MPC_E));
6380 dpb_print(DECODE_ID(hw), 0,
6381 "H264_DECODE_MODE=0x%x\n",
6382 READ_VREG(H264_DECODE_MODE));
6383 dpb_print(DECODE_ID(hw), 0,
6384 "MBY_MBX=0x%x\n",
6385 READ_VREG(MBY_MBX));
6386 dpb_print(DECODE_ID(hw), 0,
6387 "H264_DECODE_SIZE=0x%x\n",
6388 READ_VREG(H264_DECODE_SIZE));
6389 dpb_print(DECODE_ID(hw), 0,
6390 "VIFF_BIT_CNT=0x%x\n",
6391 READ_VREG(VIFF_BIT_CNT));
6392 dpb_print(DECODE_ID(hw), 0,
6393 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6394 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6395 dpb_print(DECODE_ID(hw), 0,
6396 "VLD_MEM_VIFIFO_WP=0x%x\n",
6397 READ_VREG(VLD_MEM_VIFIFO_WP));
6398 dpb_print(DECODE_ID(hw), 0,
6399 "VLD_MEM_VIFIFO_RP=0x%x\n",
6400 READ_VREG(VLD_MEM_VIFIFO_RP));
6401 dpb_print(DECODE_ID(hw), 0,
6402 "PARSER_VIDEO_RP=0x%x\n",
6403 READ_PARSER_REG(PARSER_VIDEO_RP));
6404 dpb_print(DECODE_ID(hw), 0,
6405 "PARSER_VIDEO_WP=0x%x\n",
6406 READ_PARSER_REG(PARSER_VIDEO_WP));
6407
6408 if (input_frame_based(vdec) &&
6409 dpb_is_debug(DECODE_ID(hw),
6410 PRINT_FRAMEBASE_DATA)
6411 ) {
6412 int jj;
6413 if (hw->chunk && hw->chunk->block &&
6414 hw->chunk->size > 0) {
6415 u8 *data = NULL;
6416
6417 if (!hw->chunk->block->is_mapped)
6418 data = codec_mm_vmap(hw->chunk->block->start +
6419 hw->chunk->offset, hw->chunk->size);
6420 else
6421 data = ((u8 *)hw->chunk->block->start_virt)
6422 + hw->chunk->offset;
6423
6424 dpb_print(DECODE_ID(hw), 0,
6425 "frame data size 0x%x\n",
6426 hw->chunk->size);
6427 for (jj = 0; jj < hw->chunk->size; jj++) {
6428 if ((jj & 0xf) == 0)
6429 dpb_print(DECODE_ID(hw),
6430 PRINT_FRAMEBASE_DATA,
6431 "%06x:", jj);
6432 dpb_print_cont(DECODE_ID(hw),
6433 PRINT_FRAMEBASE_DATA,
6434 "%02x ", data[jj]);
6435 if (((jj + 1) & 0xf) == 0)
6436 dpb_print_cont(DECODE_ID(hw),
6437 PRINT_FRAMEBASE_DATA,
6438 "\n");
6439 }
6440
6441 if (!hw->chunk->block->is_mapped)
6442 codec_mm_unmap_phyaddr(data);
6443 }
6444 }
6445}
6446
6447
6448static void check_timer_func(unsigned long arg)
6449{
6450 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6451 struct vdec_s *vdec = hw_to_vdec(hw);
6452 int error_skip_frame_count = error_skip_count & 0xfff;
6453 unsigned int timeout_val = decode_timeout_val;
6454 if (timeout_val != 0 &&
6455 hw->no_error_count < error_skip_frame_count)
6456 timeout_val = errordata_timeout_val;
6457 if ((h264_debug_cmd & 0x100) != 0 &&
6458 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6459 hw->dec_result = DEC_RESULT_DONE;
6460 vdec_schedule_work(&hw->work);
6461 pr_info("vdec %d is forced to be disconnected\n",
6462 h264_debug_cmd & 0xff);
6463 h264_debug_cmd = 0;
6464 return;
6465 }
6466 if ((h264_debug_cmd & 0x200) != 0 &&
6467 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6468 pr_debug("vdec %d is forced to reset bufmgr\n",
6469 h264_debug_cmd & 0xff);
6470 hw->reset_bufmgr_flag = 1;
6471 h264_debug_cmd = 0;
6472 return;
6473 }
6474
6475 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6476 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6477 vdec_schedule_work(&hw->work);
6478 pr_debug("vdec requested to be disconnected\n");
6479 return;
6480 }
6481
6482 if (radr != 0) {
6483 if (rval != 0) {
6484 WRITE_VREG(radr, rval);
6485 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6486 } else
6487 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6488 rval = 0;
6489 radr = 0;
6490 }
6491
6492 if ((input_frame_based(vdec) ||
6493 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6494 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6495 (timeout_val > 0) &&
6496 (hw->start_process_time > 0) &&
6497 ((1000 * (jiffies - hw->start_process_time) / HZ)
6498 > timeout_val)
6499 ) {
6500 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6501 u32 mby_mbx = READ_VREG(MBY_MBX);
6502 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6503 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6504 if (hw->last_mby_mbx == mby_mbx) {
6505 if (hw->decode_timeout_count > 0)
6506 hw->decode_timeout_count--;
6507 if (hw->decode_timeout_count == 0)
6508 {
6509 reset_process_time(hw);
6510 timeout_process(hw);
6511 }
6512 } else
6513 start_process_time(hw);
6514 } else if (is_in_parsing_state(dpb_status)) {
6515 if (hw->last_vld_level ==
6516 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6517 if (hw->decode_timeout_count > 0)
6518 hw->decode_timeout_count--;
6519 if (hw->decode_timeout_count == 0)
6520 {
6521 reset_process_time(hw);
6522 timeout_process(hw);
6523 }
6524 }
6525 }
6526 hw->last_vld_level =
6527 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6528 hw->last_mby_mbx = mby_mbx;
6529 }
6530
6531 if ((hw->ucode_pause_pos != 0) &&
6532 (hw->ucode_pause_pos != 0xffffffff) &&
6533 udebug_pause_pos != hw->ucode_pause_pos) {
6534 hw->ucode_pause_pos = 0;
6535 WRITE_VREG(DEBUG_REG1, 0);
6536 }
6537
6538 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6539}
6540
6541static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6542{
6543 u32 ar;
6544 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6545
6546 if (!hw)
6547 return -1;
6548
6549 vstatus->frame_width = hw->frame_width;
6550 vstatus->frame_height = hw->frame_height;
6551 if (hw->frame_dur != 0)
6552 vstatus->frame_rate = 96000 / hw->frame_dur;
6553 else
6554 vstatus->frame_rate = -1;
6555 vstatus->error_count = 0;
6556 vstatus->status = hw->stat;
6557 if (hw->h264_ar == 0x3ff)
6558 hw->h264_ar = (0x100 *
6559 hw->frame_height * hw->height_aspect_ratio) /
6560 (hw->frame_width * hw->width_aspect_ratio);
6561 ar = min_t(u32,
6562 hw->h264_ar,
6563 DISP_RATIO_ASPECT_RATIO_MAX);
6564 vstatus->ratio_control =
6565 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6566
6567 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6568 "%s-%02d", DRIVER_NAME, hw->id);
6569
6570 return 0;
6571}
6572
6573static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6574{
6575 int i, j;
6576 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6577
6578 /* if (hw->init_flag == 0) { */
6579 if (h264_debug_flag & 0x40000000) {
6580 /* if (1) */
6581 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6582 "%s, reset register\n", __func__);
6583
6584 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6585 ;
6586 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6587 ; /* reg address is 0x350 */
6588
6589#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6590 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6591 WRITE_VREG(DOS_SW_RESET0, 0);
6592
6593 READ_VREG(DOS_SW_RESET0);
6594 READ_VREG(DOS_SW_RESET0);
6595 READ_VREG(DOS_SW_RESET0);
6596
6597 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6598 WRITE_VREG(DOS_SW_RESET0, 0);
6599
6600 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6601 WRITE_VREG(DOS_SW_RESET0, 0);
6602
6603 READ_VREG(DOS_SW_RESET0);
6604 READ_VREG(DOS_SW_RESET0);
6605 READ_VREG(DOS_SW_RESET0);
6606
6607#else
6608 WRITE_RESET_REG(RESET0_REGISTER,
6609 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6610 READ_RESET_REG(RESET0_REGISTER);
6611 WRITE_RESET_REG(RESET0_REGISTER,
6612 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6613
6614 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6615#endif
6616 WRITE_VREG(POWER_CTL_VLD,
6617 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6618 (1 << 9) | (1 << 6));
6619 } else {
6620 /* WRITE_VREG(POWER_CTL_VLD,
6621 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6622 */
6623 WRITE_VREG(POWER_CTL_VLD,
6624 READ_VREG(POWER_CTL_VLD) |
6625 (0 << 10) | (1 << 9) | (1 << 6));
6626 }
6627 /* disable PSCALE for hardware sharing */
6628 WRITE_VREG(PSCALE_CTRL, 0);
6629
6630 /* clear mailbox interrupt */
6631 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6632
6633 /* enable mailbox interrupt */
6634 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6635
6636#ifdef NV21
6637 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6638#endif
6639
6640 /* cbcr_merge_swap_en */
6641 if (hw->is_used_v4l
6642 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6643 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6644 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6645
6646 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6647 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6648
6649 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6650 if (hw->mmu_enable) {
6651 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6652 /* sw reset to extif hardware */
6653 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6654 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6655 } else {
6656 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6657 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6658 }
6659
6660
6661#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6662 /* pr_info("vh264 meson8 prot init\n"); */
6663 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6664#endif
6665
6666#ifdef VDEC_DW
6667 if (IS_VDEC_DW(hw)) {
6668 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6669
6670 if (IS_VDEC_DW(hw) == 2)
6671 data |= (1 << 9);
6672 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6673 }
6674#endif
6675 if (hw->dpb.mDPB.size > 0) {
6676 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6677 (hw->dpb.mDPB.size << 16) |
6678 (hw->dpb.mDPB.size << 8));
6679
6680 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6681 i = get_buf_spec_by_canvas_pos(hw, j);
6682 if (i < 0)
6683 break;
6684
6685 if (!hw->mmu_enable &&
6686 hw->buffer_spec[i].cma_alloc_addr)
6687 config_decode_canvas(hw, i);
6688 if (hw->mmu_enable && hw->double_write_mode)
6689 config_decode_canvas_ex(hw, i);
6690 }
6691 } else {
6692 WRITE_VREG(AV_SCRATCH_0, 0);
6693 WRITE_VREG(AV_SCRATCH_9, 0);
6694 }
6695
6696 if (hw->init_flag == 0)
6697 WRITE_VREG(DPB_STATUS_REG, 0);
6698 else
6699 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6700
6701 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6702 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6703 if (!tee_enabled())
6704 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6705
6706 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6707 * error_recovery_mode : error_recovery_mode_in;
6708 */
6709 /* WRITE_VREG(AV_SCRATCH_F,
6710 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6711 */
6712 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6713 ((error_recovery_mode_in & 0x1) << 4));
6714 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6715 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6716 else*/
6717 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6718
6719 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6720#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6721 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6722#endif
6723
6724 WRITE_VREG(DEBUG_REG1, 0);
6725 WRITE_VREG(DEBUG_REG2, 0);
6726
6727 if (hw->reg_iqidct_control)
6728 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6729 if (hw->reg_vcop_ctrl_reg)
6730 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6731 if (hw->vld_dec_control)
6732 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6733 return 0;
6734}
6735
6736static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6737{
6738 struct vdec_h264_hw_s *hw =
6739 (struct vdec_h264_hw_s *)vdec->private;
6740 if (i_only_flag & 0x100)
6741 return 0;
6742 if (trickmode == TRICKMODE_I)
6743 hw->i_only = 0x3;
6744 else if (trickmode == TRICKMODE_NONE)
6745 hw->i_only = 0x0;
6746 return 0;
6747}
6748
6749static unsigned char amvdec_enable_flag;
6750static void vh264_local_init(struct vdec_h264_hw_s *hw)
6751{
6752 int i;
6753 hw->init_flag = 0;
6754 hw->first_sc_checked= 0;
6755 hw->eos = 0;
6756 hw->valve_count = 0;
6757 hw->config_bufmgr_done = 0;
6758 hw->start_process_time = 0;
6759 hw->has_i_frame = 0;
6760 hw->no_error_count = 0xfff;
6761 hw->no_error_i_count = 0xf;
6762
6763 hw->dec_flag = 0;
6764 hw->data_flag = 0;
6765 hw->skip_frame_count = 0;
6766 hw->reg_iqidct_control = 0;
6767 hw->reg_vcop_ctrl_reg = 0;
6768 hw->reg_rv_ai_mb_count = 0;
6769 hw->vld_dec_control = 0;
6770 hw->decode_timeout_count = 0;
6771 hw->no_mem_count = 0;
6772 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6773 /* vh264_ratio = 0x100; */
6774
6775 hw->vh264_rotation = (((unsigned long)
6776 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6777
6778 hw->frame_prog = 0;
6779 hw->frame_width = hw->vh264_amstream_dec_info.width;
6780 hw->frame_height = hw->vh264_amstream_dec_info.height;
6781 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6782 hw->pts_outside = ((unsigned long)
6783 hw->vh264_amstream_dec_info.param) & 0x01;
6784 hw->sync_outside = ((unsigned long)
6785 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6786 hw->use_idr_framerate = ((unsigned long)
6787 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6788 hw->max_refer_buf = !(((unsigned long)
6789 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6790 if (hw->frame_dur < 96000/960) {
6791 /*more than 960fps,it should not be a correct value,
6792 *give default 30fps
6793 */
6794 hw->frame_dur = 96000/30;
6795 }
6796
6797 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6798
6799 hw->first_i_policy = first_i_policy;
6800
6801 if (hw->is_used_v4l)
6802 mem_map_mode = CANVAS_BLKMODE_LINEAR;
6803
6804 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6805 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6806 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6807 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6808
6809 if (i_only_flag & 0x100)
6810 hw->i_only = i_only_flag & 0xff;
6811 if (hw->i_only)
6812 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6813
6814 if ((unsigned long) hw->vh264_amstream_dec_info.param
6815 & 0x08)
6816 hw->no_poc_reorder_flag = 1;
6817
6818 error_recovery_mode_in = 1; /*ucode control?*/
6819 if (error_proc_policy & 0x80000000)
6820 hw->send_error_frame_flag = error_proc_policy & 0x1;
6821 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6822 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6823
6824 INIT_KFIFO(hw->display_q);
6825 INIT_KFIFO(hw->newframe_q);
6826
6827 for (i = 0; i < VF_POOL_SIZE; i++) {
6828 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6829 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6830 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6831 kfifo_put(&hw->newframe_q, vf);
6832 }
6833
6834 hw->duration_from_pts_done = 0;
6835
6836 hw->p_last_vf = NULL;
6837 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6838 hw->hevc_cur_buf_idx = 0xffff;
6839
6840 init_waitqueue_head(&hw->wait_q);
6841
6842 return;
6843}
6844
6845static s32 vh264_init(struct vdec_h264_hw_s *hw)
6846{
6847 int size = -1;
6848 int fw_size = 0x1000 * 16;
6849 int fw_mmu_size = 0x1000 * 16;
6850 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6851
6852 /* int trickmode_fffb = 0; */
6853
6854 /* pr_info("\nvh264_init\n"); */
6855 /* init_timer(&hw->recycle_timer); */
6856
6857 /* timer init */
6858 init_timer(&hw->check_timer);
6859
6860 hw->check_timer.data = (unsigned long)hw;
6861 hw->check_timer.function = check_timer_func;
6862 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6863
6864 /* add_timer(&hw->check_timer); */
6865 hw->stat |= STAT_TIMER_ARM;
6866 hw->stat |= STAT_ISR_REG;
6867
6868 mutex_init(&hw->chunks_mutex);
6869 vh264_local_init(hw);
6870 INIT_WORK(&hw->work, vh264_work);
6871 INIT_WORK(&hw->notify_work, vh264_notify_work);
6872 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6873#ifdef MH264_USERDATA_ENABLE
6874 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6875#endif
6876
6877 if (!amvdec_enable_flag) {
6878 amvdec_enable_flag = true;
6879 amvdec_enable();
6880 if (hw->mmu_enable)
6881 amhevc_enable();
6882 }
6883 if (hw->mmu_enable) {
6884
6885 hw->frame_mmu_map_addr =
6886 dma_alloc_coherent(amports_get_dma_device(),
6887 FRAME_MMU_MAP_SIZE,
6888 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6889 if (hw->frame_mmu_map_addr == NULL) {
6890 pr_err("%s: failed to alloc count_buffer\n", __func__);
6891 return -ENOMEM;
6892 }
6893 }
6894
6895 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6896 if (IS_ERR_OR_NULL(fw))
6897 return -ENOMEM;
6898
6899 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6900 if (size < 0) {
6901 pr_err("get firmware fail.\n");
6902 vfree(fw);
6903 return -1;
6904 }
6905
6906 fw->len = size;
6907 hw->fw = fw;
6908
6909 if (hw->mmu_enable) {
6910 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6911 if (IS_ERR_OR_NULL(fw_mmu))
6912 return -ENOMEM;
6913
6914 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6915 if (size < 0) {
6916 pr_err("get mmu fw fail.\n");
6917 vfree(fw_mmu);
6918 return -1;
6919 }
6920
6921 fw_mmu->len = size;
6922 hw->fw_mmu = fw_mmu;
6923 }
6924
6925 if (!tee_enabled()) {
6926 /* -- ucode loading (amrisc and swap code) */
6927 hw->mc_cpu_addr =
6928 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6929 &hw->mc_dma_handle, GFP_KERNEL);
6930 if (!hw->mc_cpu_addr) {
6931 amvdec_enable_flag = false;
6932 amvdec_disable();
6933 if (hw->mmu_enable)
6934 amhevc_disable();
6935 pr_info("vh264_init: Can not allocate mc memory.\n");
6936 return -ENOMEM;
6937 }
6938
6939 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6940 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6941 */
6942
6943 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6944
6945 /*header*/
6946 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6947 fw->data + 0x4000, MC_SWAP_SIZE);
6948 /*data*/
6949 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6950 fw->data + 0x2000, MC_SWAP_SIZE);
6951 /*mmco*/
6952 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6953 fw->data + 0x6000, MC_SWAP_SIZE);
6954 /*list*/
6955 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6956 fw->data + 0x3000, MC_SWAP_SIZE);
6957 /*slice*/
6958 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6959 fw->data + 0x5000, MC_SWAP_SIZE);
6960 /*main*/
6961 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6962 fw->data, 0x2000);
6963 /*data*/
6964 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6965 fw->data + 0x2000, 0x1000);
6966 /*slice*/
6967 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6968 fw->data + 0x5000, 0x1000);
6969 }
6970
6971#if 1 /* #ifdef BUFFER_MGR_IN_C */
6972 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6973 if (!hw->lmem_addr) {
6974 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6975 return -ENOMEM;
6976 } else {
6977 hw->lmem_addr_remap = dma_map_single(
6978 amports_get_dma_device(),
6979 (void *)hw->lmem_addr,
6980 PAGE_SIZE, DMA_FROM_DEVICE);
6981 if (dma_mapping_error(amports_get_dma_device(),
6982 hw->lmem_addr_remap)) {
6983 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6984 "%s: failed to map lmem_addr\n", __func__);
6985 free_page(hw->lmem_addr);
6986 hw->lmem_addr = 0;
6987 hw->lmem_addr_remap = 0;
6988 return -ENOMEM;
6989 }
6990
6991 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6992 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6993 }
6994
6995 if (prefix_aux_buf_size > 0 ||
6996 suffix_aux_buf_size > 0) {
6997 u32 aux_buf_size;
6998 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6999 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7000 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7001 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7002 if (hw->aux_addr == NULL) {
7003 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7004 return -1;
7005 }
7006
7007 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7008 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7009 if (dma_mapping_error(amports_get_dma_device(),
7010 hw->aux_phy_addr)) {
7011 pr_err("%s: failed to map rpm buffer\n", __func__);
7012 kfree(hw->aux_addr);
7013 hw->aux_addr = NULL;
7014 return -1;
7015 }
7016 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7017 if (hw->sei_data_buf == NULL) {
7018 pr_err("%s: failed to alloc sei itu data buffer\n",
7019 __func__);
7020 return -1;
7021 }
7022 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7023 if (hw->sei_itu_data_buf == NULL) {
7024 pr_err("%s: failed to alloc sei itu data buffer\n",
7025 __func__);
7026 kfree(hw->aux_addr);
7027 hw->aux_addr = NULL;
7028 kfree(hw->sei_data_buf);
7029 hw->sei_data_buf = NULL;
7030
7031 return -1;
7032 }
7033
7034 if (NULL == hw->sei_user_data_buffer) {
7035 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7036 GFP_KERNEL);
7037 if (!hw->sei_user_data_buffer) {
7038 pr_info("%s: Can not allocate sei_data_buffer\n",
7039 __func__);
7040 kfree(hw->aux_addr);
7041 hw->aux_addr = NULL;
7042 kfree(hw->sei_data_buf);
7043 hw->sei_data_buf = NULL;
7044 kfree(hw->sei_itu_data_buf);
7045 hw->sei_itu_data_buf = NULL;
7046
7047 return -1;
7048 }
7049 hw->sei_user_data_wp = 0;
7050 }
7051 }
7052/* BUFFER_MGR_IN_C */
7053#endif
7054 hw->stat |= STAT_MC_LOAD;
7055
7056 /* add memory barrier */
7057 wmb();
7058
7059 return 0;
7060}
7061
7062static int vh264_stop(struct vdec_h264_hw_s *hw)
7063{
7064 if (hw->stat & STAT_VDEC_RUN) {
7065 amvdec_stop();
7066 hw->stat &= ~STAT_VDEC_RUN;
7067 }
7068#ifdef VDEC_DW
7069 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7070#endif
7071#ifdef MH264_USERDATA_ENABLE
7072 cancel_work_sync(&hw->user_data_ready_work);
7073#endif
7074 cancel_work_sync(&hw->notify_work);
7075 cancel_work_sync(&hw->timeout_work);
7076 cancel_work_sync(&hw->work);
7077
7078
7079 if (hw->stat & STAT_MC_LOAD) {
7080 if (hw->mc_cpu_addr != NULL) {
7081 dma_free_coherent(amports_get_dma_device(),
7082 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7083 hw->mc_dma_handle);
7084 hw->mc_cpu_addr = NULL;
7085 }
7086 if (hw->frame_mmu_map_addr != NULL) {
7087 dma_free_coherent(amports_get_dma_device(),
7088 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7089 hw->frame_mmu_map_phy_addr);
7090 hw->frame_mmu_map_addr = NULL;
7091 }
7092
7093 }
7094 if (hw->stat & STAT_ISR_REG) {
7095 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7096 hw->stat &= ~STAT_ISR_REG;
7097 }
7098 if (hw->lmem_addr_remap) {
7099 dma_unmap_single(amports_get_dma_device(),
7100 hw->lmem_addr_remap,
7101 PAGE_SIZE, DMA_FROM_DEVICE);
7102 hw->lmem_addr_remap = 0;
7103 }
7104 if (hw->lmem_addr) {
7105 free_page(hw->lmem_addr);
7106 hw->lmem_addr = 0;
7107 }
7108 if (hw->aux_addr) {
7109 dma_unmap_single(amports_get_dma_device(),
7110 hw->aux_phy_addr,
7111 hw->prefix_aux_size + hw->suffix_aux_size,
7112 DMA_FROM_DEVICE);
7113 kfree(hw->aux_addr);
7114 hw->aux_addr = NULL;
7115 }
7116 if (hw->sei_data_buf != NULL) {
7117 kfree(hw->sei_data_buf);
7118 hw->sei_data_buf = NULL;
7119 }
7120 if (hw->sei_itu_data_buf != NULL) {
7121 kfree(hw->sei_itu_data_buf);
7122 hw->sei_itu_data_buf = NULL;
7123 }
7124 if (hw->sei_user_data_buffer != NULL) {
7125 kfree(hw->sei_user_data_buffer);
7126 hw->sei_user_data_buffer = NULL;
7127 }
7128 /* amvdec_disable(); */
7129
7130 vfree(hw->fw);
7131 hw->fw = NULL;
7132
7133 if (hw->mmu_enable) {
7134 vfree(hw->fw_mmu);
7135 hw->fw_mmu = NULL;
7136 }
7137
7138 dpb_print(DECODE_ID(hw), 0,
7139 "%s\n",
7140 __func__);
7141 return 0;
7142}
7143
7144static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7145{
7146 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7147 int count = 0;
7148 do {
7149 usleep_range(100, 500);
7150 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7151 break;
7152 if (count > 2000) {
7153 dpb_print(DECODE_ID(hw),
7154 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7155 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7156 break;
7157 } else
7158 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7159 count++;
7160 } while (1);
7161}
7162
7163static void vh264_notify_work(struct work_struct *work)
7164{
7165 struct vdec_h264_hw_s *hw = container_of(work,
7166 struct vdec_h264_hw_s, notify_work);
7167 struct vdec_s *vdec = hw_to_vdec(hw);
7168 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7169 vf_notify_receiver(vdec->vf_provider_name,
7170 VFRAME_EVENT_PROVIDER_FR_HINT,
7171 (void *)((unsigned long)hw->frame_dur));
7172 vdec->fr_hint_state = VDEC_HINTED;
7173 }
7174
7175 return;
7176}
7177
7178#ifdef MH264_USERDATA_ENABLE
7179static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7180{
7181 hw->wait_for_udr_send = 0;
7182 hw->sei_itu_data_len = 0;
7183 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7184}
7185
7186static void vmh264_crate_userdata_manager(
7187 struct vdec_h264_hw_s *hw,
7188 u8 *userdata_buf,
7189 int buf_len)
7190{
7191 if (hw) {
7192
7193
7194 mutex_init(&hw->userdata_mutex);
7195
7196 memset(&hw->userdata_info, 0,
7197 sizeof(struct mh264_userdata_info_t));
7198 hw->userdata_info.data_buf = userdata_buf;
7199 hw->userdata_info.buf_len = buf_len;
7200 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7201
7202 vmh264_reset_udr_mgr(hw);
7203
7204 }
7205}
7206
7207static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7208{
7209 if (hw)
7210 memset(&hw->userdata_info,
7211 0,
7212 sizeof(struct mh264_userdata_info_t));
7213}
7214
7215/*
7216#define DUMP_USERDATA_RECORD
7217*/
7218#ifdef DUMP_USERDATA_RECORD
7219
7220#define MAX_USER_DATA_SIZE 3145728
7221static void *user_data_buf;
7222static unsigned char *pbuf_start;
7223static int total_len;
7224static int bskip;
7225static int n_userdata_id;
7226
7227static void print_data(unsigned char *pdata,
7228 int len,
7229 unsigned int poc_number,
7230 unsigned int flag,
7231 unsigned int duration,
7232 unsigned int vpts,
7233 unsigned int vpts_valid,
7234 int rec_id)
7235{
7236 int nLeft;
7237
7238 nLeft = len;
7239#if 0
7240 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7241 rec_id, len, flag,
7242 duration, vpts, vpts_valid, poc_number);
7243#endif
7244 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7245 rec_id, len, flag, vpts);
7246
7247 if (len == 96) {
7248 int i;
7249 nLeft = 72;
7250 while (nLeft >= 16) {
7251 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7252 pdata[0], pdata[1], pdata[2], pdata[3],
7253 pdata[4], pdata[5], pdata[6], pdata[7],
7254 pdata[8], pdata[9], pdata[10], pdata[11],
7255 pdata[12], pdata[13], pdata[14], pdata[15]);
7256 nLeft -= 16;
7257 pdata += 16;
7258 }
7259
7260
7261 while (nLeft > 0) {
7262 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7263 pdata[0], pdata[1], pdata[2], pdata[3],
7264 pdata[4], pdata[5], pdata[6], pdata[7]);
7265 nLeft -= 8;
7266 pdata += 8;
7267 }
7268
7269 i = 0;
7270 nLeft = 96-72;
7271 while (i < nLeft) {
7272 if (pdata[0] != 0) {
7273 pr_info("some data error\n");
7274 break;
7275 }
7276 pdata++;
7277 i++;
7278 }
7279 } else {
7280 while (nLeft >= 16) {
7281 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7282 pdata[0], pdata[1], pdata[2], pdata[3],
7283 pdata[4], pdata[5], pdata[6], pdata[7],
7284 pdata[8], pdata[9], pdata[10], pdata[11],
7285 pdata[12], pdata[13], pdata[14], pdata[15]);
7286 nLeft -= 16;
7287 pdata += 16;
7288 }
7289
7290
7291 while (nLeft > 0) {
7292 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7293 pdata[0], pdata[1], pdata[2], pdata[3],
7294 pdata[4], pdata[5], pdata[6], pdata[7]);
7295 nLeft -= 8;
7296 pdata += 8;
7297 }
7298
7299 }
7300}
7301
7302static void push_to_buf(struct vdec_h264_hw_s *hw,
7303 u8 *pdata,
7304 int len,
7305 struct userdata_meta_info_t *pmeta);
7306
7307static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7308 struct mh264_userdata_record_t *record)
7309{
7310 if (record && hw) {
7311 u8 *pdata;
7312
7313 pdata = hw->userdata_info.data_buf + record->rec_start;
7314/*
7315 print_data(pdata,
7316 record->rec_len,
7317 record->meta_info.flags,
7318 record->meta_info.duration,
7319 record->meta_info.vpts,
7320 record->meta_info.vpts_valid,
7321 n_record_id);
7322*/
7323 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7324 n_userdata_id++;
7325 }
7326}
7327
7328
7329static void push_to_buf(struct vdec_h264_hw_s *hw,
7330 u8 *pdata, int len,
7331 struct userdata_meta_info_t *pmeta)
7332{
7333 u32 *pLen;
7334 int info_cnt;
7335 u8 *pbuf_end;
7336
7337 if (!user_data_buf)
7338 return;
7339
7340 if (bskip) {
7341 pr_info("over size, skip\n");
7342 return;
7343 }
7344 info_cnt = 0;
7345 pLen = (u32 *)pbuf_start;
7346
7347 *pLen = len;
7348 pbuf_start += sizeof(u32);
7349 info_cnt++;
7350 pLen++;
7351
7352 *pLen = pmeta->poc_number;
7353 pbuf_start += sizeof(u32);
7354 info_cnt++;
7355 pLen++;
7356
7357 *pLen = pmeta->duration;
7358 pbuf_start += sizeof(u32);
7359 info_cnt++;
7360 pLen++;
7361
7362 *pLen = pmeta->flags;
7363 pbuf_start += sizeof(u32);
7364 info_cnt++;
7365 pLen++;
7366
7367 *pLen = pmeta->vpts;
7368 pbuf_start += sizeof(u32);
7369 info_cnt++;
7370 pLen++;
7371
7372 *pLen = pmeta->vpts_valid;
7373 pbuf_start += sizeof(u32);
7374 info_cnt++;
7375 pLen++;
7376
7377
7378 *pLen = n_userdata_id;
7379 pbuf_start += sizeof(u32);
7380 info_cnt++;
7381 pLen++;
7382
7383
7384
7385 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7386 if (pdata + len > pbuf_end) {
7387 int first_section_len;
7388
7389 first_section_len = pbuf_end - pdata;
7390 memcpy(pbuf_start, pdata, first_section_len);
7391 pdata = (u8 *)hw->sei_user_data_buffer;
7392 pbuf_start += first_section_len;
7393 memcpy(pbuf_start, pdata, len - first_section_len);
7394 pbuf_start += len - first_section_len;
7395 } else {
7396 memcpy(pbuf_start, pdata, len);
7397 pbuf_start += len;
7398 }
7399
7400 total_len += len + info_cnt * sizeof(u32);
7401 if (total_len >= MAX_USER_DATA_SIZE-4096)
7402 bskip = 1;
7403}
7404
7405static void show_user_data_buf(void)
7406{
7407 u8 *pbuf;
7408 int len;
7409 unsigned int flag;
7410 unsigned int duration;
7411 unsigned int vpts;
7412 unsigned int vpts_valid;
7413 unsigned int poc_number;
7414 int rec_id;
7415
7416 pr_info("show user data buf\n");
7417 pbuf = user_data_buf;
7418
7419 while (pbuf < pbuf_start) {
7420 u32 *pLen;
7421
7422 pLen = (u32 *)pbuf;
7423
7424 len = *pLen;
7425 pLen++;
7426 pbuf += sizeof(u32);
7427
7428 poc_number = *pLen;
7429 pLen++;
7430 pbuf += sizeof(u32);
7431
7432 duration = *pLen;
7433 pLen++;
7434 pbuf += sizeof(u32);
7435
7436 flag = *pLen;
7437 pLen++;
7438 pbuf += sizeof(u32);
7439
7440 vpts = *pLen;
7441 pLen++;
7442 pbuf += sizeof(u32);
7443
7444 vpts_valid = *pLen;
7445 pLen++;
7446 pbuf += sizeof(u32);
7447
7448 rec_id = *pLen;
7449 pLen++;
7450 pbuf += sizeof(u32);
7451
7452 print_data(pbuf, len, poc_number, flag,
7453 duration, vpts,
7454 vpts_valid, rec_id);
7455 pbuf += len;
7456 msleep(30);
7457 }
7458}
7459
7460static int vmh264_init_userdata_dump(void)
7461{
7462 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7463 if (user_data_buf)
7464 return 1;
7465 else
7466 return 0;
7467}
7468
7469static void vmh264_dump_userdata(void)
7470{
7471 if (user_data_buf) {
7472 show_user_data_buf();
7473 kfree(user_data_buf);
7474 user_data_buf = NULL;
7475 }
7476}
7477
7478static void vmh264_reset_user_data_buf(void)
7479{
7480 total_len = 0;
7481 pbuf_start = user_data_buf;
7482 bskip = 0;
7483 n_userdata_id = 0;
7484}
7485#endif
7486
7487
7488static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7489 int frame_type,
7490 u32 vpts,
7491 u32 vpts_valid)
7492{
7493 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7494
7495 unsigned char *pdata;
7496 u8 *pmax_sei_data_buffer;
7497 u8 *sei_data_buf;
7498 int i;
7499 int wp;
7500 int data_length;
7501 struct mh264_userdata_record_t *p_userdata_rec;
7502
7503
7504#ifdef MH264_USERDATA_ENABLE
7505 struct userdata_meta_info_t meta_info;
7506 memset(&meta_info, 0, sizeof(meta_info));
7507#endif
7508
7509 if (hw->sei_itu_data_len <= 0)
7510 return;
7511
7512 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7513 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7514 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7515 for (i = 0; i < hw->sei_itu_data_len; i++) {
7516 *pdata++ = sei_data_buf[i];
7517 if (pdata >= pmax_sei_data_buffer)
7518 pdata = (u8 *)hw->sei_user_data_buffer;
7519 }
7520
7521 hw->sei_user_data_wp = (hw->sei_user_data_wp
7522 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7523 hw->sei_itu_data_len = 0;
7524
7525#ifdef MH264_USERDATA_ENABLE
7526 meta_info.duration = hw->frame_dur;
7527 meta_info.flags |= (VFORMAT_H264 << 3);
7528
7529 meta_info.vpts = vpts;
7530 meta_info.vpts_valid = vpts_valid;
7531 meta_info.poc_number =
7532 p_H264_Dpb->mVideo.dec_picture->poc;
7533
7534
7535 wp = hw->sei_user_data_wp;
7536
7537 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7538 data_length = wp - hw->userdata_info.last_wp;
7539 else
7540 data_length = wp + hw->userdata_info.buf_len
7541 - hw->userdata_info.last_wp;
7542
7543 if (data_length & 0x7)
7544 data_length = (((data_length + 8) >> 3) << 3);
7545
7546 p_userdata_rec = &hw->ud_record;
7547 p_userdata_rec->meta_info = meta_info;
7548 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7549 p_userdata_rec->rec_len = data_length;
7550 hw->userdata_info.last_wp = wp;
7551
7552 p_userdata_rec->meta_info.flags |=
7553 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7554
7555 hw->wait_for_udr_send = 1;
7556 vdec_schedule_work(&hw->user_data_ready_work);
7557#endif
7558}
7559
7560
7561static void user_data_ready_notify_work(struct work_struct *work)
7562{
7563 struct vdec_h264_hw_s *hw = container_of(work,
7564 struct vdec_h264_hw_s, user_data_ready_work);
7565
7566
7567 mutex_lock(&hw->userdata_mutex);
7568
7569 hw->userdata_info.records[hw->userdata_info.write_index]
7570 = hw->ud_record;
7571 hw->userdata_info.write_index++;
7572 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7573 hw->userdata_info.write_index = 0;
7574
7575 mutex_unlock(&hw->userdata_mutex);
7576
7577#ifdef DUMP_USERDATA_RECORD
7578 dump_userdata_record(hw, &hw->ud_record);
7579#endif
7580 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7581
7582 hw->wait_for_udr_send = 0;
7583}
7584
7585static int vmh264_user_data_read(struct vdec_s *vdec,
7586 struct userdata_param_t *puserdata_para)
7587{
7588 struct vdec_h264_hw_s *hw = NULL;
7589 int rec_ri, rec_wi;
7590 int rec_len;
7591 u8 *rec_data_start;
7592 u8 *pdest_buf;
7593 struct mh264_userdata_record_t *p_userdata_rec;
7594 u32 data_size;
7595 u32 res;
7596 int copy_ok = 1;
7597
7598 hw = (struct vdec_h264_hw_s *)vdec->private;
7599
7600 pdest_buf = puserdata_para->pbuf_addr;
7601
7602 mutex_lock(&hw->userdata_mutex);
7603
7604/*
7605 pr_info("ri = %d, wi = %d\n",
7606 lg_p_mpeg12_userdata_info->read_index,
7607 lg_p_mpeg12_userdata_info->write_index);
7608*/
7609 rec_ri = hw->userdata_info.read_index;
7610 rec_wi = hw->userdata_info.write_index;
7611
7612 if (rec_ri == rec_wi) {
7613 mutex_unlock(&hw->userdata_mutex);
7614 return 0;
7615 }
7616
7617 p_userdata_rec = hw->userdata_info.records + rec_ri;
7618
7619 rec_len = p_userdata_rec->rec_len;
7620 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7621/*
7622 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7623 p_userdata_rec->rec_len,
7624 p_userdata_rec->rec_start,
7625 puserdata_para->buf_len);
7626*/
7627 if (rec_len <= puserdata_para->buf_len) {
7628 /* dvb user data buffer is enought to
7629 copy the whole recored. */
7630 data_size = rec_len;
7631 if (rec_data_start + data_size
7632 > hw->userdata_info.data_buf_end) {
7633 int first_section_len;
7634
7635 first_section_len = hw->userdata_info.buf_len -
7636 p_userdata_rec->rec_start;
7637 res = (u32)copy_to_user((void *)pdest_buf,
7638 (void *)rec_data_start,
7639 first_section_len);
7640 if (res) {
7641 pr_info("p1 read not end res=%d, request=%d\n",
7642 res, first_section_len);
7643 copy_ok = 0;
7644
7645 p_userdata_rec->rec_len -=
7646 first_section_len - res;
7647 p_userdata_rec->rec_start +=
7648 first_section_len - res;
7649 puserdata_para->data_size =
7650 first_section_len - res;
7651 } else {
7652 res = (u32)copy_to_user(
7653 (void *)(pdest_buf+first_section_len),
7654 (void *)hw->userdata_info.data_buf,
7655 data_size - first_section_len);
7656 if (res) {
7657 pr_info("p2 read not end res=%d, request=%d\n",
7658 res, data_size);
7659 copy_ok = 0;
7660 }
7661 p_userdata_rec->rec_len -=
7662 data_size - res;
7663 p_userdata_rec->rec_start =
7664 data_size - first_section_len - res;
7665 puserdata_para->data_size =
7666 data_size - res;
7667 }
7668 } else {
7669 res = (u32)copy_to_user((void *)pdest_buf,
7670 (void *)rec_data_start,
7671 data_size);
7672 if (res) {
7673 pr_info("p3 read not end res=%d, request=%d\n",
7674 res, data_size);
7675 copy_ok = 0;
7676 }
7677 p_userdata_rec->rec_len -= data_size - res;
7678 p_userdata_rec->rec_start += data_size - res;
7679 puserdata_para->data_size = data_size - res;
7680 }
7681
7682 if (copy_ok) {
7683 hw->userdata_info.read_index++;
7684 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7685 hw->userdata_info.read_index = 0;
7686 }
7687 } else {
7688 /* dvb user data buffer is not enought
7689 to copy the whole recored. */
7690 data_size = puserdata_para->buf_len;
7691 if (rec_data_start + data_size
7692 > hw->userdata_info.data_buf_end) {
7693 int first_section_len;
7694
7695 first_section_len = hw->userdata_info.buf_len -
7696 p_userdata_rec->rec_start;
7697 res = (u32)copy_to_user((void *)pdest_buf,
7698 (void *)rec_data_start,
7699 first_section_len);
7700 if (res) {
7701 pr_info("p4 read not end res=%d, request=%d\n",
7702 res, first_section_len);
7703 copy_ok = 0;
7704 p_userdata_rec->rec_len -=
7705 first_section_len - res;
7706 p_userdata_rec->rec_start +=
7707 first_section_len - res;
7708 puserdata_para->data_size =
7709 first_section_len - res;
7710 } else {
7711 /* first secton copy is ok*/
7712 res = (u32)copy_to_user(
7713 (void *)(pdest_buf+first_section_len),
7714 (void *)hw->userdata_info.data_buf,
7715 data_size - first_section_len);
7716 if (res) {
7717 pr_info("p5 read not end res=%d, request=%d\n",
7718 res,
7719 data_size - first_section_len);
7720 copy_ok = 0;
7721 }
7722
7723 p_userdata_rec->rec_len -=
7724 data_size - res;
7725 p_userdata_rec->rec_start =
7726 data_size - first_section_len - res;
7727 puserdata_para->data_size =
7728 data_size - res;
7729 }
7730 } else {
7731 res = (u32)copy_to_user((void *)pdest_buf,
7732 (void *)rec_data_start,
7733 data_size);
7734 if (res) {
7735 pr_info("p6 read not end res=%d, request=%d\n",
7736 res, data_size);
7737 copy_ok = 0;
7738 }
7739
7740 p_userdata_rec->rec_len -= data_size - res;
7741 p_userdata_rec->rec_start += data_size - res;
7742 puserdata_para->data_size = data_size - res;
7743 }
7744
7745 if (copy_ok) {
7746 hw->userdata_info.read_index++;
7747 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7748 hw->userdata_info.read_index = 0;
7749 }
7750
7751 }
7752 puserdata_para->meta_info = p_userdata_rec->meta_info;
7753
7754 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7755 puserdata_para->meta_info.records_in_que =
7756 hw->userdata_info.write_index -
7757 hw->userdata_info.read_index;
7758 else
7759 puserdata_para->meta_info.records_in_que =
7760 hw->userdata_info.write_index +
7761 USERDATA_FIFO_NUM -
7762 hw->userdata_info.read_index;
7763
7764 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7765
7766 mutex_unlock(&hw->userdata_mutex);
7767
7768 return 1;
7769}
7770
7771static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7772{
7773 struct vdec_h264_hw_s *hw = NULL;
7774
7775 hw = (struct vdec_h264_hw_s *)vdec->private;
7776
7777 if (hw) {
7778 mutex_lock(&hw->userdata_mutex);
7779 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7780 bInit,
7781 hw->userdata_info.read_index,
7782 hw->userdata_info.write_index);
7783 hw->userdata_info.read_index = 0;
7784 hw->userdata_info.write_index = 0;
7785
7786 if (bInit)
7787 hw->userdata_info.last_wp = 0;
7788 mutex_unlock(&hw->userdata_mutex);
7789 }
7790}
7791
7792static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7793{
7794 amstream_wakeup_userdata_poll(vdec);
7795}
7796
7797#endif
7798
7799
7800static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7801 struct vdec_s *vdec, int from)
7802{
7803 /* finished decoding one frame or error,
7804 * notify vdec core to switch context
7805 */
7806 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7807 "%s dec_result %d %x %x %x\n",
7808 __func__,
7809 hw->dec_result,
7810 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7811 READ_VREG(VLD_MEM_VIFIFO_WP),
7812 READ_VREG(VLD_MEM_VIFIFO_RP));
7813 if (!hw->mmu_enable) {
7814 mutex_lock(&vmh264_mutex);
7815 dealloc_buf_specs(hw, 0);
7816 mutex_unlock(&vmh264_mutex);
7817 }
7818 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7819 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7820 u32 param1 = READ_VREG(AV_SCRATCH_1);
7821 u32 param2 = READ_VREG(AV_SCRATCH_2);
7822 u32 param3 = READ_VREG(AV_SCRATCH_6);
7823 u32 param4 = READ_VREG(AV_SCRATCH_B);
7824
7825 if (vh264_set_params(hw, param1,
7826 param2, param3, param4) < 0)
7827 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7828
7829 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7830 (hw->dpb.mDPB.size<<16) |
7831 (hw->dpb.mDPB.size<<8));
7832
7833 if (hw->is_used_v4l) {
7834 struct aml_vcodec_ctx *ctx =
7835 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7836
7837 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7838 struct aml_vdec_ps_infos ps;
7839
7840 ps.visible_width = hw->frame_width;
7841 ps.visible_height = hw->frame_height;
7842 ps.coded_width = ALIGN(hw->frame_width, 64);
7843 ps.coded_height = ALIGN(hw->frame_height, 64);
7844 ps.dpb_size = hw->dpb.mDPB.size;
7845 hw->v4l_params_parsed = true;
7846 vdec_v4l_set_ps_infos(ctx, &ps);
7847 }
7848 }
7849
7850 start_process_time(hw);
7851 return;
7852 } else
7853 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7854 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7855 && (hw_to_vdec(hw)->next_status !=
7856 VDEC_STATUS_DISCONNECTED)) {
7857 if (!vdec_has_more_input(vdec)) {
7858 hw->dec_result = DEC_RESULT_EOS;
7859 vdec_schedule_work(&hw->work);
7860 return;
7861 }
7862
7863 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7864 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7865 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7866 __func__,
7867 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7868 READ_VREG(VLD_MEM_VIFIFO_WP),
7869 READ_VREG(VLD_MEM_VIFIFO_RP));
7870 mutex_lock(&hw->chunks_mutex);
7871 vdec_vframe_dirty(vdec, hw->chunk);
7872 hw->chunk = NULL;
7873 mutex_unlock(&hw->chunks_mutex);
7874 vdec_clean_input(vdec);
7875 }
7876 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7877 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7878 > get_data_timeout_val)) {
7879 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7880 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7881 __func__);
7882 goto result_done;
7883 }
7884 if (is_buffer_available(vdec)) {
7885 int r;
7886 int decode_size;
7887 r = vdec_prepare_input(vdec, &hw->chunk);
7888 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7889 VDEC_STATUS_DISCONNECTED)) {
7890 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7891
7892 dpb_print(DECODE_ID(hw),
7893 PRINT_FLAG_VDEC_DETAIL,
7894 "vdec_prepare_input: Insufficient data\n");
7895 vdec_schedule_work(&hw->work);
7896 return;
7897 }
7898 hw->dec_result = DEC_RESULT_NONE;
7899 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7900 "%s: chunk size 0x%x\n",
7901 __func__, hw->chunk->size);
7902
7903 if (dpb_is_debug(DECODE_ID(hw),
7904 PRINT_FRAMEBASE_DATA)) {
7905 int jj;
7906 u8 *data = NULL;
7907
7908 if (!hw->chunk->block->is_mapped)
7909 data = codec_mm_vmap(
7910 hw->chunk->block->start +
7911 hw->chunk->offset, r);
7912 else
7913 data = ((u8 *)
7914 hw->chunk->block->start_virt)
7915 + hw->chunk->offset;
7916
7917 for (jj = 0; jj < r; jj++) {
7918 if ((jj & 0xf) == 0)
7919 dpb_print(DECODE_ID(hw),
7920 PRINT_FRAMEBASE_DATA,
7921 "%06x:", jj);
7922 dpb_print_cont(DECODE_ID(hw),
7923 PRINT_FRAMEBASE_DATA,
7924 "%02x ", data[jj]);
7925 if (((jj + 1) & 0xf) == 0)
7926 dpb_print_cont(DECODE_ID(hw),
7927 PRINT_FRAMEBASE_DATA,
7928 "\n");
7929 }
7930
7931 if (!hw->chunk->block->is_mapped)
7932 codec_mm_unmap_phyaddr(data);
7933 }
7934 WRITE_VREG(POWER_CTL_VLD,
7935 READ_VREG(POWER_CTL_VLD) |
7936 (0 << 10) | (1 << 9) | (1 << 6));
7937 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7938 decode_size = hw->chunk->size +
7939 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7940 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7941 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7942 vdec_enable_input(vdec);
7943
7944 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7945 start_process_time(hw);
7946 } else{
7947 if (hw_to_vdec(hw)->next_status
7948 != VDEC_STATUS_DISCONNECTED) {
7949 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7950 vdec_schedule_work(&hw->work);
7951 }
7952 }
7953 return;
7954 } else if (hw->dec_result == DEC_RESULT_DONE) {
7955 /* if (!hw->ctx_valid)
7956 hw->ctx_valid = 1; */
7957result_done:
7958 if (hw->mmu_enable
7959 && hw->frame_busy && hw->frame_done) {
7960 long used_4k_num;
7961 hevc_sao_wait_done(hw);
7962 if (hw->hevc_cur_buf_idx != 0xffff) {
7963 used_4k_num =
7964 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7965 if (used_4k_num >= 0)
7966 dpb_print(DECODE_ID(hw),
7967 PRINT_FLAG_MMU_DETAIL,
7968 "release unused buf , used_4k_num %ld index %d\n",
7969 used_4k_num, hw->hevc_cur_buf_idx);
7970 hevc_mmu_dma_check(hw_to_vdec(hw));
7971 decoder_mmu_box_free_idx_tail(
7972 hw->mmu_box,
7973 hw->hevc_cur_buf_idx,
7974 used_4k_num);
7975 hw->hevc_cur_buf_idx = 0xffff;
7976 }
7977 }
7978 decode_frame_count[DECODE_ID(hw)]++;
7979 amvdec_stop();
7980 if (!vdec_is_support_4k()) {
7981 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7982 clk_adj_frame_count++;
7983 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7984 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7985 }
7986 }
7987 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7988 "%s dec_result %d %x %x %x\n",
7989 __func__,
7990 hw->dec_result,
7991 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7992 READ_VREG(VLD_MEM_VIFIFO_WP),
7993 READ_VREG(VLD_MEM_VIFIFO_RP));
7994 mutex_lock(&hw->chunks_mutex);
7995 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7996 hw->chunk = NULL;
7997 mutex_unlock(&hw->chunks_mutex);
7998 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7999 /*
8000 stream base: stream buf empty or timeout
8001 frame base: vdec_prepare_input fail
8002 */
8003 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8004 VDEC_STATUS_DISCONNECTED)) {
8005 hw->dec_result = DEC_RESULT_EOS;
8006 vdec_schedule_work(&hw->work);
8007 return;
8008 }
8009 hw->next_again_flag = 1;
8010 } else if (hw->dec_result == DEC_RESULT_EOS) {
8011 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8012 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8013 "%s: end of stream\n",
8014 __func__);
8015 amvdec_stop();
8016 if (hw->mmu_enable)
8017 amhevc_stop();
8018 hw->eos = 1;
8019 flush_dpb(p_H264_Dpb);
8020 if (hw->is_used_v4l)
8021 notify_v4l_eos(hw_to_vdec(hw));
8022 mutex_lock(&hw->chunks_mutex);
8023 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8024 hw->chunk = NULL;
8025 mutex_unlock(&hw->chunks_mutex);
8026 vdec_clean_input(vdec);
8027 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8028 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8029 "%s: force exit\n",
8030 __func__);
8031 amvdec_stop();
8032 if (hw->mmu_enable)
8033 amhevc_stop();
8034 if (hw->stat & STAT_ISR_REG) {
8035 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8036 hw->stat &= ~STAT_ISR_REG;
8037 }
8038 }
8039 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8040 del_timer_sync(&hw->check_timer);
8041 hw->stat &= ~STAT_TIMER_ARM;
8042
8043 wait_vmh264_search_done(hw);
8044 /* mark itself has all HW resource released and input released */
8045
8046#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8047 if (hw->switch_dvlayer_flag) {
8048 if (vdec->slave)
8049 vdec_set_next_sched(vdec, vdec->slave);
8050 else if (vdec->master)
8051 vdec_set_next_sched(vdec, vdec->master);
8052 } else if (vdec->slave || vdec->master)
8053 vdec_set_next_sched(vdec, vdec);
8054#endif
8055
8056 if (from == 1) {
8057 /* This is a timeout work */
8058 if (work_pending(&hw->work)) {
8059 /*
8060 * The vh264_work arrives at the last second,
8061 * give it a chance to handle the scenario.
8062 */
8063 return;
8064 }
8065 }
8066
8067 /* mark itself has all HW resource released and input released */
8068 if (vdec->parallel_dec == 1) {
8069 if (hw->mmu_enable == 0)
8070 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8071 else
8072 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8073 } else
8074 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8075
8076 wake_up_interruptible(&hw->wait_q);
8077
8078 if (hw->is_used_v4l) {
8079 struct aml_vcodec_ctx *ctx =
8080 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8081
8082 if (ctx->param_sets_from_ucode &&
8083 !hw->v4l_params_parsed)
8084 vdec_v4l_write_frame_sync(ctx);
8085 }
8086
8087 if (hw->vdec_cb)
8088 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8089}
8090
8091
8092static void vh264_work(struct work_struct *work)
8093{
8094 struct vdec_h264_hw_s *hw = container_of(work,
8095 struct vdec_h264_hw_s, work);
8096 struct vdec_s *vdec = hw_to_vdec(hw);
8097
8098 vh264_work_implement(hw, vdec, 0);
8099}
8100
8101
8102static void vh264_timeout_work(struct work_struct *work)
8103{
8104 struct vdec_h264_hw_s *hw = container_of(work,
8105 struct vdec_h264_hw_s, timeout_work);
8106 struct vdec_s *vdec = hw_to_vdec(hw);
8107
8108 if (work_pending(&hw->work))
8109 return;
8110
8111 vh264_work_implement(hw, vdec, 1);
8112}
8113
8114static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8115{
8116 bool ret = 0;
8117 struct vdec_h264_hw_s *hw =
8118 (struct vdec_h264_hw_s *)vdec->private;
8119 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8120 CODEC_MM_FLAGS_TVP : 0;
8121
8122 if (!hw->first_sc_checked && hw->mmu_enable) {
8123 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8124 hw->first_sc_checked =1;
8125 dpb_print(DECODE_ID(hw), 0,
8126 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8127 size, (hw->need_cache_size >> PAGE_SHIFT),
8128 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8129 }
8130
8131 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8132 && pre_decode_buf_level != 0) {
8133 u32 rp, wp, level;
8134
8135 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8136 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8137 if (wp < rp)
8138 level = vdec->input.size + wp - rp;
8139 else
8140 level = wp - rp;
8141
8142 if (level < pre_decode_buf_level)
8143 return 0;
8144 }
8145
8146#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8147 if (vdec->master)
8148 return 0;
8149#endif
8150 if (hw->eos)
8151 return 0;
8152
8153 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8154 return 0;
8155
8156 if (disp_vframe_valve_level &&
8157 kfifo_len(&hw->display_q) >=
8158 disp_vframe_valve_level) {
8159 hw->valve_count--;
8160 if (hw->valve_count <= 0)
8161 hw->valve_count = 2;
8162 else
8163 return 0;
8164 }
8165 if (hw->next_again_flag &&
8166 (!vdec_frame_based(vdec))) {
8167 u32 parser_wr_ptr =
8168 READ_PARSER_REG(PARSER_VIDEO_WP);
8169 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8170 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8171 again_threshold) {
8172 int r = vdec_sync_input(vdec);
8173 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8174 "%s buf lelvel:%x\n", __func__, r);
8175 return 0;
8176 }
8177 }
8178
8179 if (h264_debug_flag & 0x20000000) {
8180 /* pr_info("%s, a\n", __func__); */
8181 ret = 1;
8182 } else
8183 ret = is_buffer_available(vdec);
8184
8185#ifdef CONSTRAIN_MAX_BUF_NUM
8186 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8187 if (run_ready_max_vf_only_num > 0 &&
8188 get_vf_ref_only_buf_count(hw) >=
8189 run_ready_max_vf_only_num
8190 )
8191 ret = 0;
8192 if (run_ready_display_q_num > 0 &&
8193 kfifo_len(&hw->display_q) >=
8194 run_ready_display_q_num)
8195 ret = 0;
8196 /*avoid more buffers consumed when
8197 switching resolution*/
8198 if (run_ready_max_buf_num == 0xff &&
8199 get_used_buf_count(hw) >
8200 hw->dpb.mDPB.size)
8201 ret = 0;
8202 else if (run_ready_max_buf_num &&
8203 get_used_buf_count(hw) >=
8204 run_ready_max_buf_num)
8205 ret = 0;
8206 }
8207#endif
8208 if (hw->is_used_v4l) {
8209 struct aml_vcodec_ctx *ctx =
8210 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8211
8212 if (ctx->param_sets_from_ucode &&
8213 !ctx->v4l_codec_ready &&
8214 hw->v4l_params_parsed) {
8215 ret = 0; /*the params has parsed.*/
8216 } else if (!ctx->v4l_codec_dpb_ready)
8217 ret = 0;
8218 else if (hw->wait_reset_done_flag)
8219 ret = 0;
8220 }
8221
8222 if (ret)
8223 not_run_ready[DECODE_ID(hw)] = 0;
8224 else
8225 not_run_ready[DECODE_ID(hw)]++;
8226 if (vdec->parallel_dec == 1) {
8227 if (hw->mmu_enable == 0)
8228 return ret ? (CORE_MASK_VDEC_1) : 0;
8229 else
8230 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8231 } else
8232 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8233}
8234
8235static unsigned char get_data_check_sum
8236 (struct vdec_h264_hw_s *hw, int size)
8237{
8238 int jj;
8239 int sum = 0;
8240 u8 *data = NULL;
8241
8242 if (!hw->chunk->block->is_mapped)
8243 data = codec_mm_vmap(hw->chunk->block->start +
8244 hw->chunk->offset, size);
8245 else
8246 data = ((u8 *)hw->chunk->block->start_virt)
8247 + hw->chunk->offset;
8248
8249 for (jj = 0; jj < size; jj++)
8250 sum += data[jj];
8251
8252 if (!hw->chunk->block->is_mapped)
8253 codec_mm_unmap_phyaddr(data);
8254 return sum;
8255}
8256
8257static void run(struct vdec_s *vdec, unsigned long mask,
8258 void (*callback)(struct vdec_s *, void *), void *arg)
8259{
8260 struct vdec_h264_hw_s *hw =
8261 (struct vdec_h264_hw_s *)vdec->private;
8262 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8263 int size, ret = -1;
8264
8265 run_count[DECODE_ID(hw)]++;
8266 vdec_reset_core(vdec);
8267 if (hw->mmu_enable)
8268 hevc_reset_core(vdec);
8269 hw->vdec_cb_arg = arg;
8270 hw->vdec_cb = callback;
8271
8272 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8273 hw->reset_bufmgr_flag = 1;
8274 dpb_print(DECODE_ID(hw), 0,
8275 "kfifo len:%d invaild, need bufmgr reset\n",
8276 kfifo_len(&hw->display_q));
8277 }
8278
8279 hw->pre_parser_wr_ptr =
8280 READ_PARSER_REG(PARSER_VIDEO_WP);
8281 hw->next_again_flag = 0;
8282
8283 if (hw->reset_bufmgr_flag ||
8284 ((error_proc_policy & 0x40) &&
8285 p_H264_Dpb->buf_alloc_fail)) {
8286 if (!hw->is_used_v4l)
8287 h264_reset_bufmgr(vdec);
8288 else {
8289 struct aml_vcodec_ctx *ctx =
8290 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8291 pr_info("v4l2 buffer reset\n");
8292 hw->wait_reset_done_flag = 1;
8293 hw->reset_bufmgr_flag = 0;
8294 vdec_v4l_post_evet(ctx, V4L2_EVENT_REQUEST_RESET);
8295 hw->dec_result = DEC_RESULT_NONE;
8296 vdec_schedule_work(&hw->work);
8297 return;
8298 }
8299 hw->reset_bufmgr_flag = 0;
8300 }
8301
8302 if (h264_debug_cmd & 0xf000) {
8303 if (((h264_debug_cmd >> 12) & 0xf)
8304 == (DECODE_ID(hw) + 1)) {
8305 h264_reconfig(hw);
8306 h264_debug_cmd &= (~0xf000);
8307 }
8308 }
8309 /* hw->chunk = vdec_prepare_input(vdec); */
8310#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8311 if (vdec->slave || vdec->master)
8312 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8313#endif
8314 size = vdec_prepare_input(vdec, &hw->chunk);
8315 if ((size < 0) ||
8316 (input_frame_based(vdec) && hw->chunk == NULL)) {
8317 input_empty[DECODE_ID(hw)]++;
8318 hw->dec_result = DEC_RESULT_AGAIN;
8319
8320 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8321 "vdec_prepare_input: Insufficient data\n");
8322
8323 vdec_schedule_work(&hw->work);
8324 return;
8325 }
8326 input_empty[DECODE_ID(hw)] = 0;
8327
8328 hw->dec_result = DEC_RESULT_NONE;
8329 hw->get_data_count = 0;
8330#if 0
8331 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8332 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8333 READ_VREG(VLD_MEM_VIFIFO_RP),
8334 READ_VREG(VLD_MEM_VIFIFO_WP));
8335#endif
8336
8337 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8338 u8 *data = NULL;
8339
8340 if (!hw->chunk->block->is_mapped)
8341 data = codec_mm_vmap(hw->chunk->block->start +
8342 hw->chunk->offset, size);
8343 else
8344 data = ((u8 *)hw->chunk->block->start_virt)
8345 + hw->chunk->offset;
8346
8347 if (dpb_is_debug(DECODE_ID(hw),
8348 PRINT_FLAG_VDEC_STATUS)
8349 ) {
8350 dpb_print(DECODE_ID(hw), 0,
8351 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8352 __func__, size, get_data_check_sum(hw, size),
8353 data[0], data[1], data[2], data[3],
8354 data[4], data[5], data[size - 4],
8355 data[size - 3], data[size - 2],
8356 data[size - 1]);
8357 }
8358 if (dpb_is_debug(DECODE_ID(hw),
8359 PRINT_FRAMEBASE_DATA)
8360 ) {
8361 int jj;
8362
8363 for (jj = 0; jj < size; jj++) {
8364 if ((jj & 0xf) == 0)
8365 dpb_print(DECODE_ID(hw),
8366 PRINT_FRAMEBASE_DATA,
8367 "%06x:", jj);
8368 dpb_print_cont(DECODE_ID(hw),
8369 PRINT_FRAMEBASE_DATA,
8370 "%02x ", data[jj]);
8371 if (((jj + 1) & 0xf) == 0)
8372 dpb_print_cont(DECODE_ID(hw),
8373 PRINT_FRAMEBASE_DATA,
8374 "\n");
8375 }
8376 }
8377
8378 if (!hw->chunk->block->is_mapped)
8379 codec_mm_unmap_phyaddr(data);
8380 } else
8381 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8382 "%s: %x %x %x %x %x size 0x%x\n",
8383 __func__,
8384 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8385 READ_VREG(VLD_MEM_VIFIFO_WP),
8386 READ_VREG(VLD_MEM_VIFIFO_RP),
8387 READ_PARSER_REG(PARSER_VIDEO_RP),
8388 READ_PARSER_REG(PARSER_VIDEO_WP),
8389 size);
8390
8391 start_process_time(hw);
8392 if (vdec->mc_loaded) {
8393 /*firmware have load before,
8394 and not changes to another.
8395 ignore reload.
8396 */
8397 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8398 } else {
8399
8400 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8401 if (ret < 0) {
8402 amvdec_enable_flag = false;
8403 amvdec_disable();
8404
8405 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8406 "MH264 the %s fw loading failed, err: %x\n",
8407 tee_enabled() ? "TEE" : "local", ret);
8408 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8409 vdec_schedule_work(&hw->work);
8410 return;
8411 }
8412 vdec->mc_type = VFORMAT_H264;
8413 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8414 if (hw->mmu_enable) {
8415 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8416 hw->fw_mmu->data);
8417 if (ret < 0) {
8418 amvdec_enable_flag = false;
8419 amhevc_disable();
8420
8421 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8422 "MH264_MMU the %s fw loading failed, err: %x\n",
8423 tee_enabled() ? "TEE" : "local", ret);
8424 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8425 vdec_schedule_work(&hw->work);
8426 return;
8427 }
8428 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8429 }
8430 vdec->mc_loaded = 1;
8431 }
8432 vmh264_reset_udr_mgr(hw);
8433
8434 if (vh264_hw_ctx_restore(hw) < 0) {
8435 vdec_schedule_work(&hw->work);
8436 return;
8437 }
8438 if (input_frame_based(vdec)) {
8439 int decode_size = 0;
8440
8441 decode_size = hw->chunk->size +
8442 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8443 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8444 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8445 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8446 } else {
8447 if (size <= 0)
8448 size = 0x7fffffff; /*error happen*/
8449 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8450 WRITE_VREG(H264_DECODE_SIZE, size);
8451 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8452 }
8453 config_aux_buf(hw);
8454 config_decode_mode(hw);
8455 vdec_enable_input(vdec);
8456 WRITE_VREG(NAL_SEARCH_CTL, 0);
8457 hw->sei_data_len = 0;
8458 if (enable_itu_t35)
8459 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8460 if (!hw->init_flag) {
8461 if (hw->mmu_enable)
8462 WRITE_VREG(NAL_SEARCH_CTL,
8463 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8464 else
8465 WRITE_VREG(NAL_SEARCH_CTL,
8466 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8467 }
8468 if (udebug_flag)
8469 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8470 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8471
8472 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8473
8474 if (hw->mmu_enable)
8475 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8476 else
8477 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8478 }
8479 amvdec_start();
8480 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8481 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8482 amhevc_start();
8483 if (hw->config_bufmgr_done) {
8484 hevc_mcr_sao_global_hw_init(hw,
8485 (hw->mb_width << 4), (hw->mb_height << 4));
8486 hevc_mcr_config_canv2axitbl(hw, 1);
8487 }
8488 }
8489
8490 /* if (hw->init_flag) { */
8491 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8492 /* } */
8493
8494 hw->init_flag = 1;
8495}
8496
8497static void reset(struct vdec_s *vdec)
8498{
8499 struct vdec_h264_hw_s *hw =
8500 (struct vdec_h264_hw_s *)vdec->private;
8501
8502 pr_info("vmh264 reset\n");
8503
8504 cancel_work_sync(&hw->work);
8505 cancel_work_sync(&hw->notify_work);
8506 if (hw->stat & STAT_VDEC_RUN) {
8507 amhevc_stop();
8508 hw->stat &= ~STAT_VDEC_RUN;
8509 }
8510
8511 if (hw->stat & STAT_TIMER_ARM) {
8512 del_timer_sync(&hw->check_timer);
8513 hw->stat &= ~STAT_TIMER_ARM;
8514 }
8515 hw->eos = 0;
8516 hw->decode_pic_count = 0;
8517 hw->dec_result = DEC_RESULT_NONE;
8518 reset_process_time(hw);
8519 h264_reset_bufmgr(vdec);
8520 hw->wait_reset_done_flag = 0;
8521
8522 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8523}
8524
8525static void h264_reconfig(struct vdec_h264_hw_s *hw)
8526{
8527 int i;
8528 unsigned long flags;
8529 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8530 struct vdec_s *vdec = hw_to_vdec(hw);
8531 dpb_print(DECODE_ID(hw), 0,
8532 "%s\n", __func__);
8533 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8534 all buffers are in display queue (used == 2),
8535 or free (used == 0)
8536 */
8537 if (dpb_is_debug(DECODE_ID(hw),
8538 PRINT_FLAG_DUMP_BUFSPEC))
8539 dump_bufspec(hw, "pre h264_reconfig");
8540
8541 flush_dpb(p_H264_Dpb);
8542 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8543
8544 if (hw->collocate_cma_alloc_addr) {
8545 decoder_bmmu_box_free_idx(
8546 hw->bmmu_box,
8547 BMMU_REF_IDX);
8548 hw->collocate_cma_alloc_addr = 0;
8549 hw->dpb.colocated_mv_addr_start = 0;
8550 hw->dpb.colocated_mv_addr_end = 0;
8551 }
8552 spin_lock_irqsave(&hw->bufspec_lock, flags);
8553 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8554 if (vdec->parallel_dec == 1) {
8555 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8556 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8557 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8558 hw->buffer_spec[i].y_canvas_index = -1;
8559 hw->buffer_spec[i].u_canvas_index = -1;
8560 hw->buffer_spec[i].v_canvas_index = -1;
8561#ifdef VDEC_DW
8562 if (IS_VDEC_DW(hw)) {
8563 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8564 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8565 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8566 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8567 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8568 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8569#endif
8570 }
8571 }
8572 /*make sure buffers not put back to bufmgr when
8573 vf_put is called*/
8574 if (hw->buffer_spec[i].used == 2)
8575 hw->buffer_spec[i].used = 3;
8576
8577 /* ready to release "free buffers"
8578 */
8579 if (hw->buffer_spec[i].used == 0)
8580 hw->buffer_spec[i].used = 4;
8581
8582 hw->buffer_spec[i].canvas_pos = -1;
8583 }
8584 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8585 hw->has_i_frame = 0;
8586 hw->config_bufmgr_done = 0;
8587
8588 if (hw->is_used_v4l) {
8589 mutex_lock(&vmh264_mutex);
8590 dealloc_buf_specs(hw, 1);
8591 mutex_unlock(&vmh264_mutex);
8592 }
8593
8594 if (dpb_is_debug(DECODE_ID(hw),
8595 PRINT_FLAG_DUMP_BUFSPEC))
8596 dump_bufspec(hw, "after h264_reconfig");
8597
8598}
8599
8600#ifdef ERROR_HANDLE_TEST
8601static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8602{
8603 int i;
8604 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8605 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8606 "%s\n", __func__);
8607 remove_dpb_pictures(p_H264_Dpb);
8608 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8609 /*make sure buffers not put back to bufmgr when
8610 vf_put is called*/
8611 if (hw->buffer_spec[i].used == 2)
8612 hw->buffer_spec[i].used = 5;
8613 }
8614
8615}
8616#endif
8617
8618static void h264_reset_bufmgr(struct vdec_s *vdec)
8619{
8620 int i;
8621 ulong timeout;
8622 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8623#if 0
8624 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8625 int actual_dpb_size, max_reference_size;
8626 int reorder_pic_num;
8627 unsigned int colocated_buf_size;
8628 unsigned int colocated_mv_addr_start;
8629 unsigned int colocated_mv_addr_end;
8630 dpb_print(DECODE_ID(hw), 0,
8631 "%s\n", __func__);
8632
8633 for (i = 0; i < VF_POOL_SIZE; i++)
8634 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8635
8636 actual_dpb_size = p_H264_Dpb->mDPB.size;
8637 max_reference_size = p_H264_Dpb->max_reference_size;
8638 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8639
8640 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8641 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8642 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8643
8644 hw->cur_pool++;
8645 if (hw->cur_pool >= VF_POOL_NUM)
8646 hw->cur_pool = 0;
8647
8648 INIT_KFIFO(hw->display_q);
8649 INIT_KFIFO(hw->newframe_q);
8650
8651 for (i = 0; i < VF_POOL_SIZE; i++) {
8652 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8653 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8654 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8655 kfifo_put(&hw->newframe_q, vf);
8656 }
8657
8658 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8659 hw->buffer_spec[i].used = 0;
8660
8661 dpb_init_global(&hw->dpb,
8662 DECODE_ID(hw), 0, 0);
8663 p_H264_Dpb->mDPB.size = actual_dpb_size;
8664 p_H264_Dpb->max_reference_size = max_reference_size;
8665 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8666
8667 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8668 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8669 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8670
8671 p_H264_Dpb->fast_output_enable = fast_output_enable;
8672 hw->has_i_frame = 0;
8673#else
8674 dpb_print(DECODE_ID(hw), 0,
8675 "%s frame count %d to skip %d\n\n",
8676 __func__, hw->decode_pic_count+1,
8677 hw->skip_frame_count);
8678
8679 timeout = jiffies + HZ;
8680 while (kfifo_len(&hw->display_q) > 0) {
8681 if (time_after(jiffies, timeout))
8682 break;
8683 schedule();
8684 }
8685
8686 for (i = 0; i < VF_POOL_SIZE; i++)
8687 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8688
8689 hw->cur_pool++;
8690 if (hw->cur_pool >= VF_POOL_NUM)
8691 hw->cur_pool = 0;
8692
8693 for (i = 0; i < VF_POOL_SIZE; i++)
8694 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8695
8696
8697 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8698
8699 buf_spec_init(hw);
8700
8701 vh264_local_init(hw);
8702 /*hw->decode_pic_count = 0;
8703 hw->seq_info2 = 0;*/
8704
8705 if (hw->is_used_v4l) {
8706 mutex_lock(&vmh264_mutex);
8707 /* detach relationship with v4l buffs.*/
8708 dealloc_buf_specs(hw, 1);
8709 mutex_unlock(&vmh264_mutex);
8710 }
8711
8712 if (vh264_set_params(hw,
8713 hw->cfg_param1,
8714 hw->cfg_param2,
8715 hw->cfg_param3,
8716 hw->cfg_param4) < 0)
8717 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8718
8719 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8720 if (first_i_policy & 0x01)
8721 hw->first_i_policy = (3 << 8) | first_i_policy;
8722
8723 hw->init_flag = 1;
8724 hw->reset_bufmgr_count++;
8725#endif
8726}
8727
8728int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8729{
8730 int ret = -1;
8731 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8732 CODEC_MM_FLAGS_TVP : 0;
8733 int buf_size = 64;
8734
8735 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8736 tvp_flag, hw->mmu_enable);
8737 hw->need_cache_size = buf_size * SZ_1M;
8738 hw->sc_start_time = get_jiffies_64();
8739 if (hw->mmu_enable && !hw->mmu_box) {
8740 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8741 hw->id,
8742 MMU_MAX_BUFFERS,
8743 hw->need_cache_size,
8744 tvp_flag);
8745 if (!hw->mmu_box) {
8746 pr_err("h264 4k alloc mmu box failed!!\n");
8747 return -1;
8748 }
8749 ret = 0;
8750 }
8751 if (!hw->bmmu_box) {
8752 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8753 DRIVER_NAME,
8754 hw->id,
8755 BMMU_MAX_BUFFERS,
8756 4 + PAGE_SHIFT,
8757 CODEC_MM_FLAGS_CMA_CLEAR |
8758 CODEC_MM_FLAGS_FOR_VDECODER |
8759 tvp_flag);
8760 if (hw->bmmu_box)
8761 ret = 0;
8762 }
8763 return ret;
8764}
8765int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8766{
8767 if (hw->mmu_box) {
8768 decoder_mmu_box_free(hw->mmu_box);
8769 hw->mmu_box = NULL;
8770 }
8771 if (hw->bmmu_box) {
8772 decoder_bmmu_box_free(hw->bmmu_box);
8773 hw->bmmu_box = NULL;
8774 }
8775 return 0;
8776}
8777
8778static int ammvdec_h264_probe(struct platform_device *pdev)
8779{
8780 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8781 struct vdec_h264_hw_s *hw = NULL;
8782 char *tmpbuf;
8783 int config_val;
8784
8785 if (pdata == NULL) {
8786 pr_info("\nammvdec_h264 memory resource undefined.\n");
8787 return -EFAULT;
8788 }
8789
8790 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8791 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8792 if (hw == NULL) {
8793 pr_info("\nammvdec_h264 device data allocation failed\n");
8794 return -ENOMEM;
8795 }
8796 hw->id = pdev->id;
8797 hw->platform_dev = pdev;
8798
8799 /* the ctx from v4l2 driver. */
8800 hw->v4l2_ctx = pdata->private;
8801
8802 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8803 hw->canvas_mode = pdata->canvas_mode;
8804 else
8805 hw->canvas_mode = mem_map_mode;
8806
8807 platform_set_drvdata(pdev, pdata);
8808
8809 hw->mmu_enable = 0;
8810 hw->first_head_check_flag = 0;
8811 hw->new_iframe_flag = 0;
8812 hw->ref_err_flush_dpb_flag = 0;
8813 hw->wait_reset_done_flag = 0;
8814
8815 if (pdata->sys_info)
8816 hw->vh264_amstream_dec_info = *pdata->sys_info;
8817
8818 if (force_enable_mmu && pdata->sys_info &&
8819 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8820 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8821 (pdata->sys_info->height * pdata->sys_info->width
8822 > 1920 * 1088))
8823 hw->mmu_enable = 1;
8824
8825 if (hw->mmu_enable &&
8826 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8827 hw->mmu_enable = 0;
8828 pr_info("ionvideo needs disable mmu, path= %d \n",
8829 pdata->frame_base_video_path);
8830 }
8831
8832 if (ammvdec_h264_mmu_init(hw)) {
8833 h264_free_hw_stru(&pdev->dev, (void *)hw);
8834 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8835 return -ENOMEM;
8836 }
8837
8838 if (pdata->config_len) {
8839 /*use ptr config for doubel_write_mode, etc*/
8840 if (get_config_int(pdata->config,
8841 "mh264_double_write_mode", &config_val) == 0)
8842 hw->double_write_mode = config_val;
8843 else
8844 hw->double_write_mode = double_write_mode;
8845
8846 if (get_config_int(pdata->config,
8847 "parm_v4l_codec_enable",
8848 &config_val) == 0)
8849 hw->is_used_v4l = config_val;
8850
8851 if (get_config_int(pdata->config,
8852 "parm_v4l_buffer_margin",
8853 &config_val) == 0)
8854 hw->reorder_dpb_size_margin = config_val;
8855 } else
8856 hw->double_write_mode = double_write_mode;
8857
8858 if (!hw->is_used_v4l)
8859 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8860
8861 if (hw->mmu_enable)
8862 hw->double_write_mode &= 0xffff;
8863
8864 if (pdata->parallel_dec == 1) {
8865 int i;
8866 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8867 hw->buffer_spec[i].y_canvas_index = -1;
8868 hw->buffer_spec[i].u_canvas_index = -1;
8869 hw->buffer_spec[i].v_canvas_index = -1;
8870#ifdef VDEC_DW
8871 if (IS_VDEC_DW(hw)) {
8872 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8873 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8874 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8875 }
8876#endif
8877 }
8878 }
8879
8880 dpb_print(DECODE_ID(hw), 0,
8881 "%s mmu_enable %d double_write_mode 0x%x\n",
8882 __func__, hw->mmu_enable, hw->double_write_mode);
8883
8884 pdata->private = hw;
8885 pdata->dec_status = dec_status;
8886 pdata->set_trickmode = vmh264_set_trickmode;
8887 pdata->run_ready = run_ready;
8888 pdata->run = run;
8889 pdata->reset = reset;
8890 pdata->irq_handler = vh264_isr;
8891 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8892 pdata->dump_state = vmh264_dump_state;
8893
8894#ifdef MH264_USERDATA_ENABLE
8895 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8896 pdata->user_data_read = vmh264_user_data_read;
8897 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8898#else
8899 pdata->wakeup_userdata_poll = NULL;
8900 pdata->user_data_read = NULL;
8901 pdata->reset_userdata_fifo = NULL;
8902#endif
8903 if (pdata->use_vfm_path) {
8904 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8905 VFM_DEC_PROVIDER_NAME);
8906 hw->frameinfo_enable = 1;
8907 }
8908#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8909 else if (vdec_dual(pdata)) {
8910 if (dv_toggle_prov_name) /*debug purpose*/
8911 snprintf(pdata->vf_provider_name,
8912 VDEC_PROVIDER_NAME_SIZE,
8913 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8914 VFM_DEC_DVEL_PROVIDER_NAME);
8915 else
8916 snprintf(pdata->vf_provider_name,
8917 VDEC_PROVIDER_NAME_SIZE,
8918 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8919 VFM_DEC_DVBL_PROVIDER_NAME);
8920 }
8921#endif
8922 else
8923 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8924 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8925
8926 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8927 &vf_provider_ops, pdata);
8928
8929 platform_set_drvdata(pdev, pdata);
8930
8931 buf_spec_init(hw);
8932
8933 hw->platform_dev = pdev;
8934
8935#ifdef DUMP_USERDATA_RECORD
8936 vmh264_init_userdata_dump();
8937 vmh264_reset_user_data_buf();
8938#endif
8939 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8940 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8941 h264_free_hw_stru(&pdev->dev, (void *)hw);
8942 pdata->dec_status = NULL;
8943 return -ENOMEM;
8944 }
8945
8946 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8947 DCAC_READ_MARGIN;
8948 if (hw->mmu_enable) {
8949 u32 extif_size = EXTIF_BUF_SIZE;
8950 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8951 extif_size <<= 1;
8952 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8953 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8954 h264_free_hw_stru(&pdev->dev, (void *)hw);
8955 pdata->dec_status = NULL;
8956 return -ENOMEM;
8957 }
8958 }
8959 if (!vdec_secure(pdata)) {
8960#if 1
8961 /*init internal buf*/
8962 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8963 if (tmpbuf) {
8964 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8965 codec_mm_dma_flush(tmpbuf,
8966 V_BUF_ADDR_OFFSET,
8967 DMA_TO_DEVICE);
8968 } else {
8969 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8970 V_BUF_ADDR_OFFSET);
8971 if (tmpbuf) {
8972 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8973 codec_mm_dma_flush(tmpbuf,
8974 V_BUF_ADDR_OFFSET,
8975 DMA_TO_DEVICE);
8976 codec_mm_unmap_phyaddr(tmpbuf);
8977 }
8978 }
8979#else
8980 /*init sps/pps internal buf 64k*/
8981 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8982 + (mem_sps_base - DEF_BUF_START_ADDR));
8983 memset(tmpbuf, 0, 0x10000);
8984 dma_sync_single_for_device(amports_get_dma_device(),
8985 hw->cma_alloc_addr +
8986 (mem_sps_base - DEF_BUF_START_ADDR),
8987 0x10000, DMA_TO_DEVICE);
8988#endif
8989 }
8990 /**/
8991
8992#if 0
8993 if (NULL == hw->sei_data_buffer) {
8994 hw->sei_data_buffer =
8995 dma_alloc_coherent(amports_get_dma_device(),
8996 USER_DATA_SIZE,
8997 &hw->sei_data_buffer_phys, GFP_KERNEL);
8998 if (!hw->sei_data_buffer) {
8999 pr_info("%s: Can not allocate sei_data_buffer\n",
9000 __func__);
9001 ammvdec_h264_mmu_release(hw);
9002 h264_free_hw_stru(&pdev->dev, (void *)hw);
9003 return -ENOMEM;
9004 }
9005 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9006 sei_data_buffer, sei_data_buffer_phys,
9007 (u32)sei_data_buffer_remap); */
9008 }
9009#endif
9010 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9011 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9012
9013 if (vdec_is_support_4k() ||
9014 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9015 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9016 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9017 {
9018 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9019 }else
9020 {
9021 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9022 }
9023
9024 if (vh264_init(hw) < 0) {
9025 pr_info("\nammvdec_h264 init failed.\n");
9026 ammvdec_h264_mmu_release(hw);
9027 h264_free_hw_stru(&pdev->dev, (void *)hw);
9028 pdata->dec_status = NULL;
9029 return -ENODEV;
9030 }
9031#ifdef MH264_USERDATA_ENABLE
9032 vmh264_crate_userdata_manager(hw,
9033 hw->sei_user_data_buffer,
9034 USER_DATA_SIZE);
9035#endif
9036
9037 vdec_set_prepare_level(pdata, start_decode_buf_level);
9038 if (pdata->parallel_dec == 1) {
9039 if (hw->mmu_enable == 0)
9040 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9041 else {
9042 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9043 | CORE_MASK_COMBINE);
9044 }
9045 } else
9046 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9047 | CORE_MASK_COMBINE);
9048
9049 atomic_set(&hw->vh264_active, 1);
9050
9051 return 0;
9052}
9053
9054static int ammvdec_h264_remove(struct platform_device *pdev)
9055{
9056 struct vdec_h264_hw_s *hw =
9057 (struct vdec_h264_hw_s *)
9058 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9059 int i;
9060
9061 struct vdec_s *vdec = hw_to_vdec(hw);
9062
9063 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9064 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9065 dpb_print(DECODE_ID(hw), 0,
9066 "%s force exit %d\n", __func__, __LINE__);
9067 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9068 vdec_schedule_work(&hw->work);
9069 wait_event_interruptible_timeout(hw->wait_q,
9070 (vdec->status == VDEC_STATUS_CONNECTED),
9071 msecs_to_jiffies(1000)); /* wait for work done */
9072 }
9073
9074 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9075 release_aux_data(hw, i);
9076
9077 atomic_set(&hw->vh264_active, 0);
9078
9079 if (hw->stat & STAT_TIMER_ARM) {
9080 del_timer_sync(&hw->check_timer);
9081 hw->stat &= ~STAT_TIMER_ARM;
9082 }
9083
9084 vh264_stop(hw);
9085#ifdef MH264_USERDATA_ENABLE
9086#ifdef DUMP_USERDATA_RECORD
9087 vmh264_dump_userdata();
9088#endif
9089 vmh264_destroy_userdata_manager(hw);
9090#endif
9091 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9092
9093 atomic_set(&hw->vh264_active, 0);
9094 if (vdec->parallel_dec == 1) {
9095 if (hw->mmu_enable == 0)
9096 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9097 else
9098 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9099 CORE_MASK_COMBINE);
9100 } else
9101 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9102
9103 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9104 if (vdec->parallel_dec == 1) {
9105 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9106 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9107 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9108 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9109 if (IS_VDEC_DW(hw)) {
9110 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9111 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9112 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9113 }
9114 }
9115 }
9116
9117 ammvdec_h264_mmu_release(hw);
9118 h264_free_hw_stru(&pdev->dev, (void *)hw);
9119 clk_adj_frame_count = 0;
9120
9121 return 0;
9122}
9123
9124/****************************************/
9125#ifdef CONFIG_PM
9126static int mh264_suspend(struct device *dev)
9127{
9128 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9129 return 0;
9130}
9131
9132static int mh264_resume(struct device *dev)
9133{
9134 amvdec_resume(to_platform_device(dev));
9135 return 0;
9136}
9137
9138static const struct dev_pm_ops mh264_pm_ops = {
9139 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9140};
9141#endif
9142
9143static struct platform_driver ammvdec_h264_driver = {
9144 .probe = ammvdec_h264_probe,
9145 .remove = ammvdec_h264_remove,
9146 .driver = {
9147 .name = DRIVER_NAME,
9148#ifdef CONFIG_PM
9149 .pm = &mh264_pm_ops,
9150#endif
9151 }
9152};
9153
9154static struct codec_profile_t ammvdec_h264_profile = {
9155 .name = "mh264",
9156 .profile = ""
9157};
9158
9159static struct mconfig hm264_configs[] = {
9160 MC_PU32("h264_debug_flag", &h264_debug_flag),
9161 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9162 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9163 MC_PU32("decode_timeout_val", &decode_timeout_val),
9164 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9165 MC_PU32("reference_buf_margin", &reference_buf_margin),
9166 MC_PU32("radr", &radr),
9167 MC_PU32("rval", &rval),
9168 MC_PU32("h264_debug_mask", &h264_debug_mask),
9169 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9170 MC_PI32("force_rate_streambase", &force_rate_streambase),
9171 MC_PI32("dec_control", &dec_control),
9172 MC_PI32("force_rate_framebase", &force_rate_framebase),
9173 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9174 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9175 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9176#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9177 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9178 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9179 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9180#endif
9181 MC_PU32("i_only_flag", &i_only_flag),
9182 MC_PU32("force_rate_streambase", &force_rate_streambase),
9183};
9184static struct mconfig_node hm264_node;
9185
9186
9187static int __init ammvdec_h264_driver_init_module(void)
9188{
9189 pr_info("ammvdec_h264 module init\n");
9190 if (platform_driver_register(&ammvdec_h264_driver)) {
9191 pr_info("failed to register ammvdec_h264 driver\n");
9192 return -ENODEV;
9193 }
9194
9195 if (vdec_is_support_4k()) {
9196 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9197 ammvdec_h264_profile.profile =
9198 "4k, dwrite, compressed";
9199 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9200 ammvdec_h264_profile.profile = "4k";
9201 }
9202 }
9203
9204 vcodec_profile_register(&ammvdec_h264_profile);
9205 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9206 "mh264", hm264_configs, CONFIG_FOR_RW);
9207 return 0;
9208}
9209
9210static void __exit ammvdec_h264_driver_remove_module(void)
9211{
9212 pr_info("ammvdec_h264 module remove.\n");
9213
9214 platform_driver_unregister(&ammvdec_h264_driver);
9215}
9216
9217/****************************************/
9218module_param(h264_debug_flag, uint, 0664);
9219MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9220
9221module_param(start_decode_buf_level, int, 0664);
9222MODULE_PARM_DESC(start_decode_buf_level,
9223 "\n ammvdec_h264 start_decode_buf_level\n");
9224
9225module_param(pre_decode_buf_level, int, 0664);
9226MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9227
9228module_param(fixed_frame_rate_mode, uint, 0664);
9229MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9230
9231module_param(decode_timeout_val, uint, 0664);
9232MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9233
9234module_param(errordata_timeout_val, uint, 0664);
9235MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9236
9237module_param(get_data_timeout_val, uint, 0664);
9238MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9239
9240module_param(frame_max_data_packet, uint, 0664);
9241MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9242
9243module_param(reorder_dpb_size_margin, uint, 0664);
9244MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9245
9246#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9247module_param(reorder_dpb_size_margin_dv, uint, 0664);
9248MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9249 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9250#endif
9251
9252module_param(reference_buf_margin, uint, 0664);
9253MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9254
9255#ifdef CONSTRAIN_MAX_BUF_NUM
9256module_param(run_ready_max_vf_only_num, uint, 0664);
9257MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9258
9259module_param(run_ready_display_q_num, uint, 0664);
9260MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9261
9262module_param(run_ready_max_buf_num, uint, 0664);
9263MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9264#endif
9265
9266module_param(radr, uint, 0664);
9267MODULE_PARM_DESC(radr, "\nradr\n");
9268
9269module_param(rval, uint, 0664);
9270MODULE_PARM_DESC(rval, "\nrval\n");
9271
9272module_param(h264_debug_mask, uint, 0664);
9273MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9274
9275module_param(h264_debug_cmd, uint, 0664);
9276MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9277
9278module_param(force_rate_streambase, int, 0664);
9279MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9280
9281module_param(dec_control, int, 0664);
9282MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9283
9284module_param(force_rate_framebase, int, 0664);
9285MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9286
9287module_param(force_disp_bufspec_num, int, 0664);
9288MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9289
9290module_param(V_BUF_ADDR_OFFSET, int, 0664);
9291MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9292
9293module_param(prefix_aux_buf_size, uint, 0664);
9294MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9295
9296module_param(suffix_aux_buf_size, uint, 0664);
9297MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9298
9299#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9300module_param(dv_toggle_prov_name, uint, 0664);
9301MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9302
9303module_param(dolby_meta_with_el, uint, 0664);
9304MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9305
9306#endif
9307
9308module_param(fast_output_enable, uint, 0664);
9309MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9310
9311module_param(error_proc_policy, uint, 0664);
9312MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9313
9314module_param(error_skip_count, uint, 0664);
9315MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9316
9317module_param(force_sliding_margin, uint, 0664);
9318MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9319
9320module_param(i_only_flag, uint, 0664);
9321MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9322
9323module_param(first_i_policy, uint, 0664);
9324MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9325
9326module_param(frmbase_cont_bitlevel, uint, 0664);
9327MODULE_PARM_DESC(frmbase_cont_bitlevel,
9328 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9329
9330module_param(frmbase_cont_bitlevel2, uint, 0664);
9331MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9332 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9333
9334module_param(udebug_flag, uint, 0664);
9335MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9336
9337module_param(udebug_pause_pos, uint, 0664);
9338MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9339
9340module_param(udebug_pause_val, uint, 0664);
9341MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9342
9343module_param(udebug_pause_decode_idx, uint, 0664);
9344MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9345
9346module_param(max_alloc_buf_count, uint, 0664);
9347MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9348
9349module_param(enable_itu_t35, uint, 0664);
9350MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9351
9352module_param(endian, uint, 0664);
9353MODULE_PARM_DESC(endian, "\nrval\n");
9354
9355module_param(mmu_enable, uint, 0664);
9356MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9357
9358module_param(force_enable_mmu, uint, 0664);
9359MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9360
9361module_param(again_threshold, uint, 0664);
9362MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9363
9364module_param(stream_mode_start_num, uint, 0664);
9365MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9366
9367/*
9368module_param(trigger_task, uint, 0664);
9369MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9370*/
9371module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9372
9373module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9374
9375module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9376
9377module_param_array(run_count, uint,
9378 &max_decode_instance_num, 0664);
9379
9380module_param_array(not_run_ready, uint,
9381 &max_decode_instance_num, 0664);
9382
9383module_param_array(input_empty, uint,
9384 &max_decode_instance_num, 0664);
9385
9386module_param_array(max_get_frame_interval, uint,
9387 &max_decode_instance_num, 0664);
9388
9389module_param_array(step, uint, &max_decode_instance_num, 0664);
9390
9391module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9392
9393module_param(disp_vframe_valve_level, uint, 0664);
9394MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9395
9396module_param(double_write_mode, uint, 0664);
9397MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9398
9399module_param(mem_map_mode, uint, 0664);
9400MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9401
9402module_param(without_display_mode, uint, 0664);
9403MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9404
9405
9406module_init(ammvdec_h264_driver_init_module);
9407module_exit(ammvdec_h264_driver_remove_module);
9408
9409MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9410MODULE_LICENSE("GPL");
9411
generated by cgit at 2024-05-17 11:37:47 (GMT)