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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 29c30157cef9d94f776d61d9099580e578cbe17e
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120#define INVALID_IDX -1 /* Invalid buffer index.*/
121
122static int mmu_enable;
123/*mmu do not support mbaff*/
124static int force_enable_mmu = 0;
125unsigned int h264_debug_flag; /* 0xa0000000; */
126unsigned int h264_debug_mask = 0xff;
127 /*
128 *h264_debug_cmd:
129 * 0x1xx, force decoder id of xx to be disconnected
130 */
131unsigned int h264_debug_cmd;
132
133static unsigned int dec_control =
134 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
135 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
136
137static unsigned int force_rate_streambase;
138static unsigned int force_rate_framebase;
139static unsigned int force_disp_bufspec_num;
140static unsigned int fixed_frame_rate_mode;
141static unsigned int error_recovery_mode_in;
142static int start_decode_buf_level = 0x4000;
143static int pre_decode_buf_level = 0x1000;
144static int stream_mode_start_num = 4;
145
146#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
147/*to make reorder size difference of bl and el not too big*/
148static unsigned int reorder_dpb_size_margin_dv = 16;
149#endif
150static unsigned int reorder_dpb_size_margin = 6;
151static unsigned int reference_buf_margin = 4;
152
153#ifdef CONSTRAIN_MAX_BUF_NUM
154static u32 run_ready_max_vf_only_num;
155static u32 run_ready_display_q_num;
156 /*0: not check
157 0xff: mDPB.size
158 */
159static u32 run_ready_max_buf_num = 0xff;
160#endif
161
162#define VDEC_ASSIST_CANVAS_BLK32 0x5
163
164
165static unsigned int max_alloc_buf_count;
166static unsigned int decode_timeout_val = 100;
167static unsigned int errordata_timeout_val = 50;
168static unsigned int get_data_timeout_val = 2000;
169#if 1
170/* H264_DATA_REQUEST does not work, disable it,
171decode has error for data in none continuous address
172*/
173static unsigned int frame_max_data_packet;
174#else
175static unsigned int frame_max_data_packet = 8;
176#endif
177static unsigned int radr;
178static unsigned int rval;
179static u32 endian = 0xff0;
180
181/*
182 udebug_flag:
183 bit 0, enable ucode print
184 bit 1, enable ucode detail print
185 bit 3, disable ucode watchdog
186 bit [31:16] not 0, pos to dump lmem
187 bit 2, pop bits to lmem
188 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
189*/
190static u32 udebug_flag;
191/*
192 when udebug_flag[1:0] is not 0
193 udebug_pause_pos not 0,
194 pause position
195*/
196static u32 udebug_pause_pos;
197/*
198 when udebug_flag[1:0] is not 0
199 and udebug_pause_pos is not 0,
200 pause only when DEBUG_REG2 is equal to this val
201*/
202static u32 udebug_pause_val;
203
204static u32 udebug_pause_decode_idx;
205
206static unsigned int disp_vframe_valve_level;
207
208static unsigned int max_decode_instance_num = H264_DEV_NUM;
209static unsigned int decode_frame_count[H264_DEV_NUM];
210static unsigned int display_frame_count[H264_DEV_NUM];
211static unsigned int max_process_time[H264_DEV_NUM];
212static unsigned int max_get_frame_interval[H264_DEV_NUM];
213static unsigned int run_count[H264_DEV_NUM];
214static unsigned int input_empty[H264_DEV_NUM];
215static unsigned int not_run_ready[H264_DEV_NUM];
216static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
217{1, 1, 1, 1, 1, 1, 1, 1, 1};
218
219#define VDEC_CLOCK_ADJUST_FRAME 30
220static unsigned int clk_adj_frame_count;
221
222/*
223 *bit[3:0]: 0, run ; 1, pause; 3, step
224 *bit[4]: 1, schedule run
225 */
226static unsigned int step[H264_DEV_NUM];
227
228#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
229static u32 prefix_aux_buf_size = (16 * 1024);
230static u32 suffix_aux_buf_size;
231
232#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
233static u32 dv_toggle_prov_name;
234
235static u32 dolby_meta_with_el;
236#endif
237
238/*
239 bit[8]
240 0: use sys_info[bit 3]
241 not 0:use i_only_flag[7:0]
242 bit[7:0]:
243 bit 0, 1: only display I picture;
244 bit 1, 1: only decode I picture;
245*/
246static unsigned int i_only_flag;
247
248/*
249 error_proc_policy:
250 bit[0] send_error_frame_flag;
251 (valid when bit[31] is 1, otherwise use sysinfo)
252 bit[1] do not decode if config_decode_buf() fail
253 bit[2] force release buf if in deadlock
254 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
255 bit[4] check inactive of receiver
256 bit[5] reset buffmgr if in deadlock
257 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
258 bit[7] reset buffmgr if dpb error
259
260 bit[8] check total mbx/mby of decoded frame
261 bit[9] check ERROR_STATUS_REG
262 bit[10] check reference list
263 bit[11] mark error if dpb error
264 bit[12] i_only when error happen
265 bit[13] 0: mark error according to last pic, 1: ignore mark error
266 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
267*/
268static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
269
270
271/*
272 error_skip_count:
273 bit[11:0] error skip frame count
274 bit[15:12] error skip i picture count
275*/
276static unsigned int error_skip_count = (0x2 << 12) | 0x40;
277
278static unsigned int force_sliding_margin;
279/*
280 bit[1:0]:
281 0, start playing from any frame
282 1, start playing from I frame
283 bit[15:8]: the count of skip frames after first I
284 2, start playing from second I frame (decode from the first I)
285 bit[15:8]: the max count of skip frames after first I
286 3, start playing from IDR
287*/
288static unsigned int first_i_policy = 1;
289
290/*
291 fast_output_enable:
292 bit [0], output frame if there is IDR in list
293 bit [1], output frame if the current poc is 1 big than the previous poc
294 bit [2], if even poc only, output frame ifthe cuurent poc
295 is 2 big than the previous poc
296 bit [3], ip only
297*/
298static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
299
300static unsigned int enable_itu_t35 = 1;
301
302static unsigned int frmbase_cont_bitlevel = 0x40;
303
304static unsigned int frmbase_cont_bitlevel2 = 0x1;
305
306
307#define MH264_USERDATA_ENABLE
308
309/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
310/* hevc->double_write_mode:
311 0, no double write
312 1, 1:1 ratio
313 2, (1/4):(1/4) ratio
314 3, (1/4):(1/4) ratio, with both compressed frame included
315 4, (1/2):(1/2) ratio
316 0x10, double write only
317 0x10000: vdec dw horizotal 1/2
318 0x20000: vdec dw horizotal/vertical 1/2
319*/
320static u32 double_write_mode;
321static u32 without_display_mode;
322#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
323
324static void vmh264_dump_state(struct vdec_s *vdec);
325
326#define is_in_parsing_state(status) \
327 ((status == H264_ACTION_SEARCH_HEAD) || \
328 ((status & 0xf0) == 0x80))
329
330#define is_interlace(frame) \
331 (frame->frame &&\
332 frame->top_field &&\
333 frame->bottom_field &&\
334 (!frame->frame->coded_frame))
335static inline bool close_to(int a, int b, int m)
336{
337 return (abs(a - b) < m) ? true : false;
338}
339
340#if 0
341#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
342#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
343#else
344#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
345#define h264_free_hw_stru(dev, hw) vfree(hw)
346#endif
347
348/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
349#define NV21
350/* #endif */
351
352/* 12M for L41 */
353#define MAX_DPB_BUFF_SIZE (12*1024*1024)
354#define DEFAULT_MEM_SIZE (32*1024*1024)
355#define AVIL_DPB_BUFF_SIZE 0x01ec2000
356
357#define DEF_BUF_START_ADDR 0x01000000
358#define mem_sps_base 0x011c3c00
359#define mem_pps_base 0x011cbc00
360/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
361u32 V_BUF_ADDR_OFFSET = 0x200000;
362#define DCAC_READ_MARGIN (64 * 1024)
363
364
365#define EXTEND_SAR 0xff
366#define BUFSPEC_POOL_SIZE 64
367#define VF_POOL_SIZE 64
368#define VF_POOL_NUM 2
369#define MAX_VF_BUF_NUM 27
370#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
371#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
372#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
373#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
374#define EXTIF_BUF_SIZE (0x10000 * 2)
375
376#define HEADER_BUFFER_IDX(n) (n)
377#define VF_BUFFER_IDX(n) (n)
378
379
380#define PUT_INTERVAL (HZ/100)
381#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
382
383#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
384#define SWITCHING_STATE_OFF 0
385#define SWITCHING_STATE_ON_CMD3 1
386#define SWITCHING_STATE_ON_CMD1 2
387
388
389
390#define INCPTR(p) ptr_atomic_wrap_inc(&p)
391
392#define SLICE_TYPE_I 2
393#define SLICE_TYPE_P 5
394#define SLICE_TYPE_B 6
395
396struct buffer_spec_s {
397 /*
398 used:
399 -1, none allocated
400 0, allocated, free
401 1, used by dpb
402 2, in disp queue;
403 3, in disp queue, isolated,
404 do not use for dpb when vf_put;
405 4, to release
406 5, in disp queue, isolated (but not to release)
407 do not use for dpb when vf_put;
408 */
409 unsigned int used;
410 unsigned int info0;
411 unsigned int info1;
412 unsigned int info2;
413 unsigned int y_addr;
414 unsigned int u_addr;
415 unsigned int v_addr;
416
417 int y_canvas_index;
418 int u_canvas_index;
419 int v_canvas_index;
420
421#ifdef VDEC_DW
422 unsigned int vdec_dw_y_addr;
423 unsigned int vdec_dw_u_addr;
424 unsigned int vdec_dw_v_addr;
425
426 int vdec_dw_y_canvas_index;
427 int vdec_dw_u_canvas_index;
428 int vdec_dw_v_canvas_index;
429#ifdef NV21
430 struct canvas_config_s vdec_dw_canvas_config[2];
431#else
432 struct canvas_config_s vdec_dw_canvas_config[3];
433#endif
434#endif
435
436#ifdef NV21
437 struct canvas_config_s canvas_config[2];
438#else
439 struct canvas_config_s canvas_config[3];
440#endif
441 unsigned long cma_alloc_addr;
442 unsigned int buf_adr;
443#ifdef H264_MMU
444 unsigned long alloc_header_addr;
445#endif
446 char *aux_data_buf;
447 int aux_data_size;
448#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
449 unsigned char dv_enhance_exist;
450#endif
451 int canvas_pos;
452 int vf_ref;
453 /*unsigned int comp_body_size;*/
454 unsigned int dw_y_adr;
455 unsigned int dw_u_v_adr;
456};
457
458#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
459#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
460#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
461
462
463#define vdec_dw_spec2canvas(x) \
464 (((x)->vdec_dw_v_canvas_index << 16) | \
465 ((x)->vdec_dw_u_canvas_index << 8) | \
466 ((x)->vdec_dw_y_canvas_index << 0))
467
468
469#define spec2canvas(x) \
470 (((x)->v_canvas_index << 16) | \
471 ((x)->u_canvas_index << 8) | \
472 ((x)->y_canvas_index << 0))
473
474#define FRAME_INDEX(vf_index) (vf_index & 0xff)
475#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
476#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
477
478static struct vframe_s *vh264_vf_peek(void *);
479static struct vframe_s *vh264_vf_get(void *);
480static void vh264_vf_put(struct vframe_s *, void *);
481static int vh264_vf_states(struct vframe_states *states, void *);
482static int vh264_event_cb(int type, void *data, void *private_data);
483static void vh264_work(struct work_struct *work);
484static void vh264_timeout_work(struct work_struct *work);
485static void vh264_notify_work(struct work_struct *work);
486#ifdef MH264_USERDATA_ENABLE
487static void user_data_ready_notify_work(struct work_struct *work);
488static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
489#endif
490
491static const char vh264_dec_id[] = "vh264-dev";
492
493#define PROVIDER_NAME "vdec.h264"
494
495static const struct vframe_operations_s vf_provider_ops = {
496 .peek = vh264_vf_peek,
497 .get = vh264_vf_get,
498 .put = vh264_vf_put,
499 .event_cb = vh264_event_cb,
500 .vf_states = vh264_vf_states,
501};
502
503#define DEC_RESULT_NONE 0
504#define DEC_RESULT_DONE 1
505#define DEC_RESULT_AGAIN 2
506#define DEC_RESULT_CONFIG_PARAM 3
507#define DEC_RESULT_GET_DATA 4
508#define DEC_RESULT_GET_DATA_RETRY 5
509#define DEC_RESULT_ERROR 6
510#define DEC_RESULT_EOS 7
511#define DEC_RESULT_FORCE_EXIT 8
512
513/*
514 *static const char *dec_result_str[] = {
515 * "DEC_RESULT_NONE ",
516 * "DEC_RESULT_DONE ",
517 * "DEC_RESULT_AGAIN ",
518 * "DEC_RESULT_CONFIG_PARAM",
519 * "DEC_RESULT_GET_DATA ",
520 * "DEC_RESULT_GET_DA_RETRY",
521 * "DEC_RESULT_ERROR ",
522 *};
523 */
524
525#define UCODE_IP_ONLY 2
526#define UCODE_IP_ONLY_PARAM 1
527
528#define MC_OFFSET_HEADER 0x0000
529#define MC_OFFSET_DATA 0x1000
530#define MC_OFFSET_MMCO 0x2000
531#define MC_OFFSET_LIST 0x3000
532#define MC_OFFSET_SLICE 0x4000
533#define MC_OFFSET_MAIN 0x5000
534
535#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
536#define MC_SWAP_SIZE (4*SZ_1K)
537#define MODE_ERROR 0
538#define MODE_FULL 1
539
540#define DFS_HIGH_THEASHOLD 3
541
542#define INIT_FLAG_REG AV_SCRATCH_2
543#define HEAD_PADING_REG AV_SCRATCH_3
544#define UCODE_WATCHDOG_REG AV_SCRATCH_7
545#define LMEM_DUMP_ADR AV_SCRATCH_L
546#define DEBUG_REG1 AV_SCRATCH_M
547#define DEBUG_REG2 AV_SCRATCH_N
548#define FRAME_COUNTER_REG AV_SCRATCH_I
549#define RPM_CMD_REG AV_SCRATCH_A
550#define H264_DECODE_SIZE AV_SCRATCH_E
551#define H264_DECODE_MODE AV_SCRATCH_4
552#define H264_DECODE_SEQINFO AV_SCRATCH_5
553#define H264_AUX_ADR AV_SCRATCH_C
554#define H264_AUX_DATA_SIZE AV_SCRATCH_H
555
556#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
557#define DPB_STATUS_REG AV_SCRATCH_J
558#define ERROR_STATUS_REG AV_SCRATCH_9
559 /*
560 NAL_SEARCH_CTL: bit 0, enable itu_t35
561 NAL_SEARCH_CTL: bit 1, enable mmu
562 */
563#define NAL_SEARCH_CTL AV_SCRATCH_9
564#define MBY_MBX MB_MOTION_MODE /*0xc07*/
565
566#define DECODE_MODE_SINGLE 0x0
567#define DECODE_MODE_MULTI_FRAMEBASE 0x1
568#define DECODE_MODE_MULTI_STREAMBASE 0x2
569#define DECODE_MODE_MULTI_DVBAL 0x3
570#define DECODE_MODE_MULTI_DVENL 0x4
571static DEFINE_MUTEX(vmh264_mutex);
572
573
574
575#ifdef MH264_USERDATA_ENABLE
576
577struct mh264_userdata_record_t {
578 struct userdata_meta_info_t meta_info;
579 u32 rec_start;
580 u32 rec_len;
581};
582
583struct mh264_ud_record_wait_node_t {
584 struct list_head list;
585 struct mh264_userdata_record_t ud_record;
586};
587#define USERDATA_FIFO_NUM 256
588#define MAX_FREE_USERDATA_NODES 5
589
590struct mh264_userdata_info_t {
591 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
592 u8 *data_buf;
593 u8 *data_buf_end;
594 u32 buf_len;
595 u32 read_index;
596 u32 write_index;
597 u32 last_wp;
598};
599
600
601#endif
602
603struct vdec_h264_hw_s {
604 spinlock_t lock;
605 spinlock_t bufspec_lock;
606 int id;
607 struct platform_device *platform_dev;
608 unsigned long cma_alloc_addr;
609 /* struct page *collocate_cma_alloc_pages; */
610 unsigned long collocate_cma_alloc_addr;
611
612 u32 prefix_aux_size;
613 u32 suffix_aux_size;
614 void *aux_addr;
615 dma_addr_t aux_phy_addr;
616
617 /* buffer for store all sei data */
618 void *sei_data_buf;
619 u32 sei_data_len;
620
621 /* buffer for storing one itu35 recored */
622 void *sei_itu_data_buf;
623 u32 sei_itu_data_len;
624
625 /* recycle buffer for user data storing all itu35 records */
626 void *sei_user_data_buffer;
627 u32 sei_user_data_wp;
628#ifdef MH264_USERDATA_ENABLE
629 struct work_struct user_data_ready_work;
630#endif
631 struct StorablePicture *last_dec_picture;
632
633 ulong lmem_addr;
634 dma_addr_t lmem_addr_remap;
635
636 void *bmmu_box;
637#ifdef H264_MMU
638 void *mmu_box;
639 void *frame_mmu_map_addr;
640 dma_addr_t frame_mmu_map_phy_addr;
641 u32 hevc_cur_buf_idx;
642 u32 losless_comp_body_size;
643 u32 losless_comp_body_size_sao;
644 u32 losless_comp_header_size;
645 u32 mc_buffer_size_u_v;
646 u32 mc_buffer_size_u_v_h;
647 u32 is_idr_frame;
648 u32 is_new_pic;
649 u32 frame_done;
650 u32 frame_busy;
651 unsigned long extif_addr;
652 int double_write_mode;
653 int mmu_enable;
654#endif
655
656 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
657 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
658
659 int cur_pool;
660 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
661 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
662 struct vframe_s switching_fense_vf;
663 struct h264_dpb_stru dpb;
664 u8 init_flag;
665 u8 first_sc_checked;
666 u8 has_i_frame;
667 u8 config_bufmgr_done;
668 u32 max_reference_size;
669 u32 decode_pic_count;
670 u32 reflist_error_count;
671 int start_search_pos;
672 u32 reg_iqidct_control;
673 u32 reg_vcop_ctrl_reg;
674 u32 reg_rv_ai_mb_count;
675 u32 vld_dec_control;
676 struct vframe_s vframe_dummy;
677
678 unsigned char buffer_empty_flag;
679
680 u32 frame_width;
681 u32 frame_height;
682 u32 frame_dur;
683 u32 frame_prog;
684 u32 frame_packing_type;
685
686 struct vframe_chunk_s *chunk;
687
688 u32 stat;
689 unsigned long buf_start;
690 u32 buf_offset;
691 u32 buf_size;
692 /* u32 ucode_map_start; */
693 u32 pts_outside;
694 u32 sync_outside;
695 u32 vh264_ratio;
696 u32 vh264_rotation;
697 u32 use_idr_framerate;
698
699 u32 seq_info;
700 u32 seq_info2;
701 u32 video_signal_from_vui; /*to do .. */
702 u32 timing_info_present_flag;
703 u32 fixed_frame_rate_flag;
704 u32 bitstream_restriction_flag;
705 u32 num_reorder_frames;
706 u32 max_dec_frame_buffering;
707 u32 iframe_count;
708 u32 aspect_ratio_info;
709 u32 num_units_in_tick;
710 u32 time_scale;
711 u32 h264_ar;
712 bool h264_first_valid_pts_ready;
713 u32 h264pts1;
714 u32 h264pts2;
715 u32 pts_duration;
716 u32 h264_pts_count;
717 u32 duration_from_pts_done;
718 u32 pts_unstable;
719 u32 unstable_pts;
720 u32 last_checkout_pts;
721 u32 max_refer_buf;
722
723 s32 vh264_stream_switching_state;
724 struct vframe_s *p_last_vf;
725 u32 last_pts;
726 u32 last_pts_remainder;
727 u32 last_duration;
728 u32 last_mb_width, last_mb_height;
729 bool check_pts_discontinue;
730 bool pts_discontinue;
731 u32 wait_buffer_counter;
732 u32 first_offset;
733 u32 first_pts;
734 u64 first_pts64;
735 bool first_pts_cached;
736 u64 last_pts64;
737#if 0
738 void *sei_data_buffer;
739 dma_addr_t sei_data_buffer_phys;
740#endif
741
742 uint error_recovery_mode;
743 uint mb_total;
744 uint mb_width;
745 uint mb_height;
746
747 uint i_only;
748 int skip_frame_count;
749 bool no_poc_reorder_flag;
750 bool send_error_frame_flag;
751 dma_addr_t mc_dma_handle;
752 void *mc_cpu_addr;
753 int vh264_reset;
754
755 atomic_t vh264_active;
756
757 struct dec_sysinfo vh264_amstream_dec_info;
758
759 int dec_result;
760 struct work_struct work;
761 struct work_struct notify_work;
762 struct work_struct timeout_work;
763 void (*vdec_cb)(struct vdec_s *, void *);
764 void *vdec_cb_arg;
765
766 struct timer_list check_timer;
767
768 /**/
769 unsigned int last_frame_time;
770 u32 vf_pre_count;
771 u32 vf_get_count;
772 u32 vf_put_count;
773
774 /* timeout handle */
775 unsigned long int start_process_time;
776 unsigned int last_mby_mbx;
777 unsigned int last_vld_level;
778 unsigned int decode_timeout_count;
779 unsigned int timeout_num;
780 unsigned int search_dataempty_num;
781 unsigned int decode_timeout_num;
782 unsigned int decode_dataempty_num;
783 unsigned int buffer_empty_recover_num;
784
785 unsigned get_data_count;
786 unsigned get_data_start_time;
787 /**/
788
789 /*log*/
790 unsigned int packet_write_success_count;
791 unsigned int packet_write_EAGAIN_count;
792 unsigned int packet_write_ENOMEM_count;
793 unsigned int packet_write_EFAULT_count;
794 unsigned int total_read_size_pre;
795 unsigned int total_read_size;
796 unsigned int frame_count_pre;
797#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
798 u8 switch_dvlayer_flag;
799 u8 got_valid_nal;
800#endif
801 u8 eos;
802 u8 data_flag;
803 u32 no_error_count;
804 u32 no_error_i_count;
805 /*
806 NODISP_FLAG
807 */
808 u8 dec_flag;
809
810 u32 ucode_pause_pos;
811
812 u8 reset_bufmgr_flag;
813 u32 reset_bufmgr_count;
814 u32 cfg_param1;
815 u32 cfg_param2;
816 u32 cfg_param3;
817 u32 cfg_param4;
818 int valve_count;
819 u8 next_again_flag;
820 u32 pre_parser_wr_ptr;
821 struct firmware_s *fw;
822 struct firmware_s *fw_mmu;
823#ifdef MH264_USERDATA_ENABLE
824 /*user data*/
825 struct mutex userdata_mutex;
826 struct mh264_userdata_info_t userdata_info;
827 struct mh264_userdata_record_t ud_record;
828 int wait_for_udr_send;
829#endif
830 u32 no_mem_count;
831 u32 canvas_mode;
832 bool is_used_v4l;
833 void *v4l2_ctx;
834 bool v4l_params_parsed;
835 wait_queue_head_t wait_q;
836 u32 reg_g_status;
837 struct mutex chunks_mutex;
838 int need_cache_size;
839 u64 sc_start_time;
840 u8 frmbase_cont_flag;
841 struct vframe_qos_s vframe_qos;
842 int frameinfo_enable;
843 bool first_head_check_flag;
844 unsigned int height_aspect_ratio;
845 unsigned int width_aspect_ratio;
846 bool new_iframe_flag;
847 bool ref_err_flush_dpb_flag;
848 unsigned int first_i_policy;
849 u32 reorder_dpb_size_margin;
850};
851
852static u32 again_threshold;
853
854static void timeout_process(struct vdec_h264_hw_s *hw);
855static void dump_bufspec(struct vdec_h264_hw_s *hw,
856 const char *caller);
857static void h264_reconfig(struct vdec_h264_hw_s *hw);
858static void h264_reset_bufmgr(struct vdec_s *vdec);
859static void vh264_local_init(struct vdec_h264_hw_s *hw);
860static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
861static int vh264_stop(struct vdec_h264_hw_s *hw);
862static s32 vh264_init(struct vdec_h264_hw_s *hw);
863static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
864 u32 index);
865static void release_aux_data(struct vdec_h264_hw_s *hw,
866 int buf_spec_num);
867#ifdef ERROR_HANDLE_TEST
868static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
869#endif
870
871#define H265_PUT_SAO_4K_SET 0x03
872#define H265_ABORT_SAO_4K_SET 0x04
873#define H265_ABORT_SAO_4K_SET_DONE 0x05
874
875#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
876#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
877#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
878#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
879#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
880
881
882#define HEVC_CM_HEADER_START_ADDR 0x3628
883#define HEVC_CM_BODY_START_ADDR 0x3626
884#define HEVC_CM_BODY_LENGTH 0x3627
885#define HEVC_CM_HEADER_LENGTH 0x3629
886#define HEVC_CM_HEADER_OFFSET 0x362b
887#define HEVC_SAO_CTRL9 0x362d
888#define HEVCD_MPP_DECOMP_CTL3 0x34c4
889#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
890#define HEVC_DBLK_CFGB 0x350b
891#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
892
893#define H265_DW_NO_SCALE
894#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
895#define H265_LOSLESS_COMPRESS_MODE
896#define MAX_FRAME_4K_NUM 0x1200
897#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
898
899/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
900static u32 mem_map_mode = H265_MEM_MAP_MODE;
901
902#define MAX_SIZE_8K (8192 * 4608)
903#define MAX_SIZE_4K (4096 * 2304)
904
905static int is_oversize(int w, int h)
906{
907 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
908 MAX_SIZE_8K : MAX_SIZE_4K;
909
910 if (w < 0 || h < 0)
911 return true;
912
913 if (h != 0 && (w > max / h))
914 return true;
915
916 return false;
917}
918
919static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
920 int frame_type,
921 u32 vpts,
922 u32 vpts_valid);
923static int compute_losless_comp_body_size(int width,
924 int height, int bit_depth_10);
925static int compute_losless_comp_header_size(int width, int height);
926
927static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
928 int pic_width, int pic_height, u16 bit_depth,
929 unsigned int *mmu_index_adr) {
930 int cur_buf_idx;
931 int bit_depth_10 = (bit_depth != 0x00);
932 int picture_size;
933 u32 cur_mmu_4k_number;
934
935 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
936 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
937 picture_size = compute_losless_comp_body_size(pic_width,
938 pic_height, bit_depth_10);
939 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
940 dpb_print(DECODE_ID(hw),
941 PRINT_FLAG_MMU_DETAIL,
942 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
943 cur_buf_idx, picture_size, cur_mmu_4k_number);
944
945 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
946 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
947 cur_mmu_4k_number);
948 return -1;
949 }
950
951 return decoder_mmu_box_alloc_idx(
952 hw->mmu_box,
953 cur_buf_idx,
954 cur_mmu_4k_number,
955 mmu_index_adr);
956}
957
958static int compute_losless_comp_body_size(int width,
959 int height, int bit_depth_10)
960{
961 int width_x64;
962 int height_x32;
963 int bsize;
964
965 width_x64 = width + 63;
966 width_x64 >>= 6;
967
968 height_x32 = height + 31;
969 height_x32 >>= 5;
970
971#ifdef H264_MMU
972 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
973#else
974 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
975#endif
976 return bsize;
977}
978
979static int compute_losless_comp_header_size(int width, int height)
980{
981 int width_x64;
982 int width_x128;
983 int height_x64;
984 int hsize;
985
986 width_x64 = width + 63;
987 width_x64 >>= 6;
988
989 width_x128 = width + 127;
990 width_x128 >>= 7;
991
992 height_x64 = height + 63;
993 height_x64 >>= 6;
994
995#ifdef H264_MMU
996 hsize = 128*width_x64*height_x64;
997#else
998 hsize = 32*width_x128*height_x64;
999#endif
1000 return hsize;
1001}
1002
1003static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1004{
1005 int ratio = 1;
1006 int dw_mode = hw->double_write_mode;
1007 if ((dw_mode == 2) ||
1008 (dw_mode == 3))
1009 ratio = 4;
1010 else if (dw_mode == 4)
1011 ratio = 2;
1012 return ratio;
1013}
1014
1015
1016static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1017{
1018 int pic_width, pic_height;
1019 int lcu_size = 16;
1020 int dw_buf_size;
1021 u32 dw_buffer_size_u_v;
1022 u32 dw_buffer_size_u_v_h;
1023 int dw_mode = hw->double_write_mode;
1024
1025 pic_width = hw->frame_width;
1026 pic_height = hw->frame_height;
1027
1028 if (dw_mode) {
1029 int pic_width_dw = pic_width /
1030 get_double_write_ratio(hw);
1031 int pic_height_dw = pic_height /
1032 get_double_write_ratio(hw);
1033
1034 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1035 pic_width_dw / lcu_size + 1 :
1036 pic_width_dw / lcu_size;
1037 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1038 pic_height_dw / lcu_size + 1 :
1039 pic_height_dw / lcu_size;
1040 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1041
1042
1043 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1044 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1045 /*64k alignment*/
1046 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1047 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1048 } else {
1049 *pdw_buffer_size_u_v_h = 0;
1050 dw_buf_size = 0;
1051 }
1052
1053 return dw_buf_size;
1054}
1055
1056
1057static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1058{
1059 int i, size;
1060 u32 canvas_addr;
1061 unsigned long maddr;
1062 int num_buff = hw->dpb.mDPB.size;
1063 int dw_size = 0;
1064 u32 dw_buffer_size_u_v_h;
1065 u32 blkmode = mem_map_mode;
1066 int dw_mode = hw->double_write_mode;
1067
1068 canvas_addr = ANC0_CANVAS_ADDR;
1069 for (i = 0; i < num_buff; i++)
1070 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1071
1072 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1073 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1074
1075
1076 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1077 size += dw_size;
1078 if (size > 0)
1079 size += 0x10000;
1080
1081 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1082 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1083 dw_buffer_size_u_v_h, dw_size, size);
1084
1085 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1086 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1087 hw->losless_comp_body_size,
1088 hw->losless_comp_header_size,
1089 hw->losless_comp_body_size_sao);
1090
1091 for (i = 0; i < num_buff; i++) {
1092 if (!restore) {
1093 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1094 HEADER_BUFFER_IDX(i), size,
1095 DRIVER_HEADER_NAME, &maddr) < 0) {
1096 dpb_print(DECODE_ID(hw), 0,
1097 "%s malloc compress header failed %d\n",
1098 DRIVER_HEADER_NAME, i);
1099 return;
1100 }
1101 } else
1102 maddr = hw->buffer_spec[i].alloc_header_addr;
1103 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1104 hw->buffer_spec[i].alloc_header_addr = maddr;
1105 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1106 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1107 __func__, i, (u32)maddr, size);
1108
1109 if (dw_mode) {
1110 u32 addr;
1111 int canvas_w;
1112 int canvas_h;
1113
1114 canvas_w = hw->frame_width /
1115 get_double_write_ratio(hw);
1116 canvas_h = hw->frame_height /
1117 get_double_write_ratio(hw);
1118
1119 if (mem_map_mode == 0)
1120 canvas_w = ALIGN(canvas_w, 32);
1121 else
1122 canvas_w = ALIGN(canvas_w, 64);
1123 canvas_h = ALIGN(canvas_h, 32);
1124
1125 hw->buffer_spec[i].dw_y_adr =
1126 maddr + hw->losless_comp_header_size;
1127
1128 hw->buffer_spec[i].dw_y_adr =
1129 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1130 << 16;
1131 hw->buffer_spec[i].dw_u_v_adr =
1132 hw->buffer_spec[i].dw_y_adr
1133 + (dw_buffer_size_u_v_h << 16) * 2;
1134
1135
1136 hw->buffer_spec[i].buf_adr
1137 = hw->buffer_spec[i].dw_y_adr;
1138 addr = hw->buffer_spec[i].buf_adr;
1139
1140
1141 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1142 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1143 hw->buffer_spec[i].dw_y_adr,
1144 hw->buffer_spec[i].dw_u_v_adr,
1145 hw->buffer_spec[i].y_addr,
1146 hw->buffer_spec[i].u_addr,
1147 hw->buffer_spec[i].v_addr,
1148 canvas_w,
1149 canvas_h);
1150
1151 hw->buffer_spec[i].canvas_config[0].phy_addr =
1152 hw->buffer_spec[i].dw_y_adr;
1153 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1154 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1155 hw->buffer_spec[i].canvas_config[0].block_mode =
1156 blkmode;
1157 hw->buffer_spec[i].canvas_config[0].endian = 7;
1158
1159 hw->buffer_spec[i].canvas_config[1].phy_addr =
1160 hw->buffer_spec[i].dw_u_v_adr;
1161 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1162 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1163 hw->buffer_spec[i].canvas_config[1].block_mode =
1164 blkmode;
1165 hw->buffer_spec[i].canvas_config[1].endian = 7;
1166 }
1167 }
1168 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1169
1170 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1171 for (i = 0; i < 32; i++)
1172 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1173 return;
1174}
1175static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1176{
1177 u32 i;
1178 u32 ref_canv;
1179 struct Slice *pSlice = &(hw->dpb.mSlice);
1180 /*REFLIST[0]*/
1181 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1182 struct StorablePicture *ref = pSlice->listX[0][i];
1183 if (ref == NULL)
1184 return;
1185 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1186 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1187 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1188 (ref->buf_spec_num & 0x3f) << 8);
1189 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1190 }
1191 /*REFLIST[1]*/
1192 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1193 struct StorablePicture *ref = pSlice->listX[1][i];
1194 if (ref == NULL)
1195 return;
1196 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1197 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1198 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1199 (ref->buf_spec_num & 0x3f) << 8);
1200 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1201 }
1202 return;
1203}
1204
1205static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1206{
1207 u32 rdata32;
1208 u32 rdata32_2;
1209 u32 slice_type;
1210 struct StorablePicture *ref;
1211 struct Slice *pSlice;
1212 slice_type = hw->dpb.mSlice.slice_type;
1213 pSlice = &(hw->dpb.mSlice);
1214 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1215 if (slice_type == I_SLICE) {
1216 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1217 return;
1218 }
1219 if (slice_type == B_SLICE) {
1220 ref = pSlice->listX[0][0];
1221 if (ref == NULL)
1222 return;
1223 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1224 ((ref->buf_spec_num & 0x3f) << 8));
1225 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1226 rdata32 = rdata32 & 0xffff;
1227 rdata32 = rdata32 | (rdata32 << 16);
1228 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1229
1230 ref = pSlice->listX[1][0];
1231 if (ref == NULL)
1232 return;
1233 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1234 ((ref->buf_spec_num & 0x3f) << 8));
1235 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1236 rdata32_2 = rdata32_2 & 0xffff;
1237 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1238 if (rdata32 == rdata32_2) {
1239 ref = pSlice->listX[1][1];
1240 if (ref == NULL)
1241 return;
1242 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1243 ((ref->buf_spec_num & 0x3f) << 8));
1244 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1245 rdata32_2 = rdata32_2 & 0xffff;
1246 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1247 }
1248 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1249 } else { /*P-PIC*/
1250 ref = pSlice->listX[0][0];
1251 if (ref == NULL)
1252 return;
1253 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1254 ((ref->buf_spec_num & 0x3f) << 8));
1255 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1256 rdata32 = rdata32 & 0xffff;
1257 rdata32 = rdata32 | (rdata32 << 16);
1258 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1259
1260 ref = pSlice->listX[0][1];
1261 if (ref == NULL)
1262 return;
1263 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1264 ((ref->buf_spec_num & 0x3f) << 8));
1265 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1266 rdata32 = rdata32 & 0xffff;
1267 rdata32 = rdata32 | (rdata32 << 16);
1268 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1269 }
1270 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1271 return;
1272}
1273
1274
1275static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1276 u32 width, u32 height) {
1277 u32 data32;
1278 u32 lcu_x_num, lcu_y_num;
1279 u32 lcu_total;
1280 u32 mc_buffer_size_u_v;
1281 u32 mc_buffer_size_u_v_h;
1282 int dw_mode = hw->double_write_mode;
1283
1284 lcu_x_num = (width + 15) >> 4;
1285 lcu_y_num = (height + 15) >> 4;
1286 lcu_total = lcu_x_num * lcu_y_num;
1287
1288 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1289 hw->mc_buffer_size_u_v_h =
1290 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1291
1292 hw->losless_comp_body_size = 0;
1293
1294 hw->losless_comp_body_size_sao =
1295 compute_losless_comp_body_size(width, height, 0);
1296 hw->losless_comp_header_size =
1297 compute_losless_comp_header_size(width, height);
1298
1299 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1300 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1301
1302 /* setup lcu_size = 16*/
1303 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1304 /*pic_width/pic_height*/
1305 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1306 (height & 0xffff) << 16 | (width & 0xffff));
1307 /* bitdepth_luma = 8*/
1308 /* bitdepth_chroma = 8*/
1309 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1310
1311#ifdef H265_LOSLESS_COMPRESS_MODE
1312 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1313 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1314#else
1315 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1316#endif
1317 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1318 data32 &= (~0x30);
1319 data32 |= (mem_map_mode << 4);
1320 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1321
1322 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1323 (0x80 << 20) | (0x80 << 10) | (0xff));
1324
1325 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1326
1327 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1328 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1329 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1330 /* ipp_enable*/
1331 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1332
1333 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1334 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1335 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1336 if (dw_mode)
1337 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1338 else
1339 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1340 }
1341
1342 data32 = READ_VREG(HEVC_SAO_CTRL0);
1343 data32 &= (~0xf);
1344 data32 |= 0x4;
1345 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1346 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1347 (width & 0xffff));
1348 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1349
1350 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1351 data32 = (lcu_x_num | lcu_y_num << 16);
1352 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1353 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1354 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1355 data32 = (mc_buffer_size_u_v_h << 16);
1356 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1357
1358 data32 = READ_VREG(HEVC_SAO_CTRL1);
1359 data32 &= (~0x3000);
1360 data32 &= (~0xff0);
1361 data32 |= endian; /* Big-Endian per 64-bit */
1362
1363 if (hw->mmu_enable && dw_mode)
1364 data32 |= ((mem_map_mode << 12));
1365 else
1366 data32 |= ((mem_map_mode << 12)|2);
1367
1368 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1369
1370#ifdef H265_DW_NO_SCALE
1371 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1372 if (hw->mmu_enable && dw_mode) {
1373 data32 = READ_VREG(HEVC_SAO_CTRL5);
1374 data32 &= (~(0xff << 16));
1375 if (dw_mode == 2 ||
1376 dw_mode == 3)
1377 data32 |= (0xff<<16);
1378 else if (dw_mode == 4)
1379 data32 |= (0x33<<16);
1380 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1381 }
1382
1383
1384#endif
1385
1386
1387#ifdef H265_LOSLESS_COMPRESS_MODE
1388 data32 = READ_VREG(HEVC_SAO_CTRL5);
1389 data32 |= (1<<9); /*8-bit smem-mode*/
1390 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1391
1392 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1393 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1394 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1395#endif
1396
1397#ifdef H265_LOSLESS_COMPRESS_MODE
1398 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1399 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1400#endif
1401
1402 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1403
1404 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1405
1406 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1407 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1408 return;
1409}
1410
1411static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1412 u32 is_new_pic, u32 is_idr)
1413{
1414 hw->is_new_pic = is_new_pic;
1415 hw->is_idr_frame = is_idr;
1416 return;
1417}
1418
1419static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1420 struct StorablePicture *pic) {
1421 u32 mc_y_adr;
1422 u32 mc_u_v_adr;
1423 u32 dw_y_adr;
1424 u32 dw_u_v_adr;
1425 u32 canvas_addr;
1426 int ret;
1427 int dw_mode = hw->double_write_mode;
1428 if (hw->is_new_pic != 1)
1429 return;
1430
1431 if (hw->is_idr_frame) {
1432 /* William TBD */
1433 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1434 }
1435
1436 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1437 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1438 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1439 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1440 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1441 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1442 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1443 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1444 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1445
1446
1447 if (dw_mode) {
1448 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1449 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1450 } else {
1451 dw_y_adr = 0;
1452 dw_u_v_adr = 0;
1453 }
1454#ifdef H265_LOSLESS_COMPRESS_MODE
1455 if (dw_mode)
1456 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1457 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1458#ifdef H264_MMU
1459 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1460#else
1461 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1462 (mc_y_adr + hw->losless_comp_body_size));
1463#endif
1464#else
1465 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1466#endif
1467
1468#ifndef H265_LOSLESS_COMPRESS_MODE
1469 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1470#else
1471 if (dw_mode)
1472 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1473#endif
1474
1475#ifndef LOSLESS_COMPRESS_MODE
1476 if (dw_mode) {
1477 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1478 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1479 }
1480#else
1481 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1482 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1483#endif
1484
1485 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1486 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1487 hw->frame_mmu_map_addr);
1488 if (ret != 0) {
1489 dpb_print(DECODE_ID(hw),
1490 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1491 pic->buf_spec_num,
1492 ret);
1493 return;
1494 }
1495
1496 /*Reset SAO + Enable SAO slice_start*/
1497 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1498 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1499 WRITE_VREG(HEVC_SAO_INT_STATUS,
1500 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1501 WRITE_VREG(HEVC_SAO_INT_STATUS,
1502 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1503 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1504 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1505
1506 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1507 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1508 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1509 } else
1510 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1511 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1512 hw->frame_busy = 1;
1513 return;
1514}
1515
1516
1517static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1518 u32 buf_spec_num) {
1519 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1520 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1521 dpb_print(DECODE_ID(hw),
1522 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1523 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1524 return;
1525}
1526
1527
1528static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1529{
1530 ulong timeout = jiffies + HZ;
1531 dpb_print(DECODE_ID(hw),
1532 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1533 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1534 if (time_after(jiffies, timeout)) {
1535 dpb_print(DECODE_ID(hw),
1536 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1537 break;
1538 }
1539 }
1540 timeout = jiffies + HZ;
1541 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1542 if (time_after(jiffies, timeout)) {
1543 dpb_print(DECODE_ID(hw),
1544 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1545 break;
1546 }
1547 }
1548 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1549 hw->frame_done = 1;
1550 return;
1551}
1552
1553static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1554{
1555 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1556 if (p_H264_Dpb->mVideo.dec_picture) {
1557 release_picture(p_H264_Dpb,
1558 p_H264_Dpb->mVideo.dec_picture);
1559 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1560 p_H264_Dpb->mVideo.dec_picture = NULL;
1561 if (hw->mmu_enable)
1562 hevc_set_frame_done(hw);
1563 }
1564}
1565
1566static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1567{
1568 ulong timeout = jiffies + HZ;
1569 dpb_print(DECODE_ID(hw),
1570 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1571 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1572 if (time_after(jiffies, timeout)) {
1573 dpb_print(DECODE_ID(hw),
1574 PRINT_FLAG_MMU_DETAIL,
1575 "hevc_sao_wait_done...wait timeout!\n");
1576 break;
1577 }
1578 }
1579 timeout = jiffies + HZ;
1580 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1581 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1582 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1583 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1584 H265_ABORT_SAO_4K_SET_DONE) {
1585 if (time_after(jiffies, timeout)) {
1586 dpb_print(DECODE_ID(hw),
1587 PRINT_FLAG_MMU_DETAIL,
1588 "wait h265_abort_sao_4k_set_done timeout!\n");
1589 break;
1590 }
1591 }
1592 }
1593 amhevc_stop();
1594 hw->frame_busy = 0;
1595 hw->frame_done = 0;
1596 dpb_print(DECODE_ID(hw),
1597 PRINT_FLAG_MMU_DETAIL,
1598 "sao wait done ,hevc stop!\n");
1599 }
1600 return;
1601}
1602static void buf_spec_init(struct vdec_h264_hw_s *hw)
1603{
1604 int i;
1605 unsigned long flags;
1606 spin_lock_irqsave(&hw->bufspec_lock, flags);
1607 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1608 hw->buffer_spec[i].used = -1;
1609 hw->buffer_spec[i].canvas_pos = -1;
1610 }
1611 if (dpb_is_debug(DECODE_ID(hw),
1612 PRINT_FLAG_DUMP_BUFSPEC))
1613 dump_bufspec(hw, __func__);
1614 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1615}
1616
1617/*is active in buf management */
1618static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1619 int buf_spec_num)
1620{
1621 unsigned char ret = 0;
1622 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1623 hw->buffer_spec[buf_spec_num].used == 2 ||
1624 hw->buffer_spec[buf_spec_num].used == 3 ||
1625 hw->buffer_spec[buf_spec_num].used == 5)
1626 ret = 1;
1627 return ret;
1628}
1629
1630static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1631 int buf_spec_num)
1632{
1633 unsigned char ret = 0;
1634 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1635 hw->buffer_spec[buf_spec_num].used == 3 ||
1636 hw->buffer_spec[buf_spec_num].used == 5)
1637 ret = 1;
1638 return ret;
1639}
1640
1641static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1642{
1643 if (hw->mmu_enable) {
1644 if (hw->buffer_spec[i].alloc_header_addr)
1645 return 0;
1646 else
1647 return -1;
1648 } else {
1649
1650 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1651 int addr;
1652#ifdef VDEC_DW
1653 int orig_buf_size;
1654 orig_buf_size = buf_size;
1655 if (IS_VDEC_DW(hw) == 1)
1656 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1657 else if (IS_VDEC_DW(hw) == 2)
1658 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1659#endif
1660 if (hw->buffer_spec[i].cma_alloc_addr)
1661 return 0;
1662
1663 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1664 PAGE_ALIGN(buf_size), DRIVER_NAME,
1665 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1666 hw->buffer_spec[i].cma_alloc_addr = 0;
1667 if (hw->no_mem_count++ > 3) {
1668 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1669 hw->reset_bufmgr_flag = 1;
1670 }
1671 dpb_print(DECODE_ID(hw), 0,
1672 "%s, fail to alloc buf for bufspec%d, try later\n",
1673 __func__, i
1674 );
1675 return -1;
1676 } else {
1677 hw->no_mem_count = 0;
1678 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1679 }
1680
1681 hw->buffer_spec[i].buf_adr =
1682 hw->buffer_spec[i].cma_alloc_addr;
1683 addr = hw->buffer_spec[i].buf_adr;
1684
1685
1686 hw->buffer_spec[i].y_addr = addr;
1687 addr += hw->mb_total << 8;
1688 hw->buffer_spec[i].u_addr = addr;
1689 hw->buffer_spec[i].v_addr = addr;
1690 addr += hw->mb_total << 7;
1691
1692 hw->buffer_spec[i].canvas_config[0].phy_addr =
1693 hw->buffer_spec[i].y_addr;
1694 hw->buffer_spec[i].canvas_config[0].width =
1695 hw->mb_width << 4;
1696 hw->buffer_spec[i].canvas_config[0].height =
1697 hw->mb_height << 4;
1698 hw->buffer_spec[i].canvas_config[0].block_mode =
1699 hw->canvas_mode;
1700
1701 hw->buffer_spec[i].canvas_config[1].phy_addr =
1702 hw->buffer_spec[i].u_addr;
1703 hw->buffer_spec[i].canvas_config[1].width =
1704 hw->mb_width << 4;
1705 hw->buffer_spec[i].canvas_config[1].height =
1706 hw->mb_height << 3;
1707 hw->buffer_spec[i].canvas_config[1].block_mode =
1708 hw->canvas_mode;
1709 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1710 "%s, alloc buf for bufspec%d\n",
1711 __func__, i
1712 );
1713#ifdef VDEC_DW
1714
1715 if (!IS_VDEC_DW(hw))
1716 return 0;
1717 else if (IS_VDEC_DW(hw) == 1) {
1718 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1719 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1720 addr += hw->mb_total << 7;
1721 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1722 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1723 addr += hw->mb_total << 6;
1724
1725 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1726 hw->buffer_spec[i].vdec_dw_y_addr;
1727 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1728 hw->mb_width << 3;
1729 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1730 hw->mb_height << 4;
1731 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1732 CANVAS_BLKMODE_32X32;
1733
1734 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1735 hw->buffer_spec[i].vdec_dw_u_addr;
1736 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1737 hw->mb_width << 3;
1738 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1739 hw->mb_height << 3;
1740 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1741 CANVAS_BLKMODE_32X32;
1742 }else {
1743 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1744 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1745 addr += hw->mb_total << 6;
1746 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1747 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1748 addr += hw->mb_total << 5;
1749
1750 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1751 hw->buffer_spec[i].vdec_dw_y_addr;
1752 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1753 hw->mb_width << 3;
1754 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1755 hw->mb_height << 3;
1756 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1757 CANVAS_BLKMODE_32X32;
1758
1759 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1760 hw->buffer_spec[i].vdec_dw_u_addr;
1761 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1762 hw->mb_width << 3;
1763 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1764 hw->mb_height << 2;
1765 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1766 CANVAS_BLKMODE_32X32;
1767 }
1768 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1769 "%s, vdec_dw: alloc buf for bufspec%d\n",
1770 __func__, i
1771 );
1772#endif
1773 }
1774 return 0;
1775}
1776
1777static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1778{
1779 int ret = 0;
1780 struct aml_vcodec_ctx *ctx = NULL;
1781 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1782 struct canvas_config_s *y_canvas_cfg = NULL;
1783 struct canvas_config_s *c_canvas_cfg = NULL;
1784 struct vdec_v4l2_buffer *fb = NULL;
1785 unsigned int y_addr = 0, c_addr = 0;
1786
1787 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1788 pr_err("the v4l context has err.\n");
1789 return -1;
1790 }
1791
1792 if (bs->cma_alloc_addr)
1793 return 0;
1794
1795 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1796 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1797 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1798 ctx->id, __func__,
1799 (hw->mb_total << 8) + (hw->mb_total << 7));
1800
1801 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1802 if (ret < 0) {
1803 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1804 "[%d] get fb fail.\n", ctx->id);
1805 return ret;
1806 }
1807
1808 bs->cma_alloc_addr = (unsigned long)fb;
1809 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1810 "[%d] %s(), cma alloc addr: 0x%x\n",
1811 ctx->id, __func__, bs->cma_alloc_addr);
1812
1813 if (fb->num_planes == 1) {
1814 y_addr = fb->m.mem[0].addr;
1815 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1816 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1817 } else if (fb->num_planes == 2) {
1818 y_addr = fb->m.mem[0].addr;
1819 c_addr = fb->m.mem[1].addr;
1820 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1821 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1822 }
1823
1824 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1825 "[%d] %s(), y_addr: %x, size: %u\n",
1826 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1827 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1828 "[%d] %s(), c_addr: %x, size: %u\n",
1829 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1830
1831 bs->y_addr = y_addr;
1832 bs->u_addr = c_addr;
1833 bs->v_addr = c_addr;
1834
1835 y_canvas_cfg = &bs->canvas_config[0];
1836 c_canvas_cfg = &bs->canvas_config[1];
1837
1838 y_canvas_cfg->phy_addr = y_addr;
1839 y_canvas_cfg->width = hw->mb_width << 4;
1840 y_canvas_cfg->height = hw->mb_height << 4;
1841 y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1842 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1843 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1844 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1845 y_canvas_cfg->width,y_canvas_cfg->height);
1846
1847 c_canvas_cfg->phy_addr = c_addr;
1848 c_canvas_cfg->width = hw->mb_width << 4;
1849 c_canvas_cfg->height = hw->mb_height << 3;
1850 c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1851 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1852 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1853 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1854 c_canvas_cfg->width, c_canvas_cfg->height);
1855
1856 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1857 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1858
1859 return ret;
1860}
1861
1862static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1863{
1864 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
1865 int blkmode = CANVAS_BLKMODE_32X32;
1866 int endian = 0;
1867
1868 if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
1869 blkmode = CANVAS_BLKMODE_LINEAR;
1870 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1871 endian = 7;
1872 else
1873 endian = 0;
1874 }
1875
1876 if (hw->is_used_v4l) {
1877 blkmode = CANVAS_BLKMODE_LINEAR;
1878 if (v4l2_ctx->ada_ctx->vfm_path
1879 != FRAME_BASE_PATH_V4L_VIDEO)
1880 endian = 7;
1881 }
1882
1883 canvas_config_ex(hw->buffer_spec[i].
1884 y_canvas_index,
1885 hw->buffer_spec[i].y_addr,
1886 hw->mb_width << 4,
1887 hw->mb_height << 4,
1888 CANVAS_ADDR_NOWRAP,
1889 blkmode,
1890 endian);
1891
1892 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1893 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1894 (1 << 11) | /* canvas_blk32_wr */
1895 (blkmode << 10) | /* canvas_blk32*/
1896 (1 << 8) | /* canvas_index_wr*/
1897 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1898 );
1899 }
1900
1901 canvas_config_ex(hw->buffer_spec[i].
1902 u_canvas_index,
1903 hw->buffer_spec[i].u_addr,
1904 hw->mb_width << 4,
1905 hw->mb_height << 3,
1906 CANVAS_ADDR_NOWRAP,
1907 blkmode,
1908 endian);
1909
1910 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1911 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1912 (1 << 11) |
1913 (blkmode << 10) |
1914 (1 << 8) |
1915 (hw->buffer_spec[i].u_canvas_index << 0));
1916 }
1917
1918 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1919 spec2canvas(&hw->buffer_spec[i]));
1920
1921
1922#ifdef VDEC_DW
1923 if (!IS_VDEC_DW(hw))
1924 return;
1925 else if (IS_VDEC_DW(hw) == 1) {
1926 canvas_config_ex(hw->buffer_spec[i].
1927 vdec_dw_y_canvas_index,
1928 hw->buffer_spec[i].vdec_dw_y_addr,
1929 hw->mb_width << 3,
1930 hw->mb_height << 4,
1931 CANVAS_ADDR_NOWRAP,
1932 blkmode,
1933 endian);
1934 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1935 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1936 (1 << 11) |
1937 (blkmode << 10) |
1938 (1 << 8) |
1939 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1940 }
1941 canvas_config_ex(hw->buffer_spec[i].
1942 vdec_dw_u_canvas_index,
1943 hw->buffer_spec[i].vdec_dw_u_addr,
1944 hw->mb_width << 3,
1945 hw->mb_height << 3,
1946 CANVAS_ADDR_NOWRAP,
1947 blkmode,
1948 endian);
1949 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1950 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1951 (1 << 11) |
1952 (blkmode << 10) |
1953 (1 << 8) |
1954 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1955 }
1956 } else {
1957 canvas_config_ex(hw->buffer_spec[i].
1958 vdec_dw_y_canvas_index,
1959 hw->buffer_spec[i].vdec_dw_y_addr,
1960 hw->mb_width << 3,
1961 hw->mb_height << 3,
1962 CANVAS_ADDR_NOWRAP,
1963 blkmode,
1964 endian);
1965 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1966 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1967 (1 << 11) |
1968 (blkmode << 10) |
1969 (1 << 8) |
1970 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1971 }
1972
1973 canvas_config_ex(hw->buffer_spec[i].
1974 vdec_dw_u_canvas_index,
1975 hw->buffer_spec[i].vdec_dw_u_addr,
1976 hw->mb_width << 3,
1977 hw->mb_height << 2,
1978 CANVAS_ADDR_NOWRAP,
1979 blkmode,
1980 endian);
1981 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1982 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1983 (1 << 11) |
1984 (blkmode << 10) |
1985 (1 << 8) |
1986 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1987 }
1988 }
1989#endif
1990}
1991
1992static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1993{
1994 u32 blkmode = mem_map_mode;
1995 int canvas_w;
1996 int canvas_h;
1997
1998 canvas_w = hw->frame_width /
1999 get_double_write_ratio(hw);
2000 canvas_h = hw->frame_height /
2001 get_double_write_ratio(hw);
2002
2003 if (mem_map_mode == 0)
2004 canvas_w = ALIGN(canvas_w, 32);
2005 else
2006 canvas_w = ALIGN(canvas_w, 64);
2007 canvas_h = ALIGN(canvas_h, 32);
2008
2009 canvas_config_ex(hw->buffer_spec[i].
2010 y_canvas_index,
2011 hw->buffer_spec[i].dw_y_adr,
2012 canvas_w,
2013 canvas_h,
2014 CANVAS_ADDR_NOWRAP,
2015 blkmode,
2016 7);
2017
2018 canvas_config_ex(hw->buffer_spec[i].
2019 u_canvas_index,
2020 hw->buffer_spec[i].dw_u_v_adr,
2021 canvas_w,
2022 canvas_h,
2023 CANVAS_ADDR_NOWRAP,
2024 blkmode,
2025 7);
2026}
2027
2028
2029int get_free_buf_idx(struct vdec_s *vdec)
2030{
2031 int i;
2032 unsigned long addr, flags;
2033 int index = -1;
2034 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2035 int buf_total = BUFSPEC_POOL_SIZE;
2036
2037 if (hw->is_used_v4l)
2038 buf_total = hw->dpb.mDPB.size;
2039
2040 spin_lock_irqsave(&hw->bufspec_lock, flags);
2041 /*hw->start_search_pos = 0;*/
2042 for (i = hw->start_search_pos; i < buf_total; i++) {
2043 if (hw->mmu_enable)
2044 addr = hw->buffer_spec[i].alloc_header_addr;
2045 else {
2046 addr = hw->buffer_spec[i].cma_alloc_addr;
2047 if (hw->is_used_v4l && !addr) {
2048 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2049 config_decode_canvas(hw, i);
2050 addr = hw->buffer_spec[i].cma_alloc_addr;
2051 }
2052 }
2053 }
2054 if (hw->buffer_spec[i].used == 0 && addr) {
2055 hw->buffer_spec[i].used = 1;
2056 hw->start_search_pos = i+1;
2057 index = i;
2058 break;
2059 }
2060 }
2061 if (index < 0) {
2062 for (i = 0; i < hw->start_search_pos; i++) {
2063 if (hw->mmu_enable)
2064 addr = hw->buffer_spec[i].alloc_header_addr;
2065 else {
2066 addr = hw->buffer_spec[i].cma_alloc_addr;
2067 if (hw->is_used_v4l && !addr) {
2068 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2069 config_decode_canvas(hw, i);
2070 addr = hw->buffer_spec[i].cma_alloc_addr;
2071 }
2072 }
2073 }
2074 if (hw->buffer_spec[i].used == 0 && addr) {
2075 hw->buffer_spec[i].used = 1;
2076 hw->start_search_pos = i+1;
2077 index = i;
2078 break;
2079 }
2080 }
2081 }
2082 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2083 if (hw->start_search_pos >= buf_total)
2084 hw->start_search_pos = 0;
2085 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2086 "%s, buf_spec_num %d\n", __func__, index);
2087
2088 if (index < 0) {
2089 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2090 "%s fail\n", __func__);
2091 vmh264_dump_state(vdec);
2092 }
2093
2094 if (dpb_is_debug(DECODE_ID(hw),
2095 PRINT_FLAG_DUMP_BUFSPEC))
2096 dump_bufspec(hw, __func__);
2097 return index;
2098}
2099
2100int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2101{
2102 /*u32 cur_buf_idx;*/
2103 unsigned long flags;
2104 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2105 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2106 "%s buf_spec_num %d used %d\n",
2107 __func__, buf_spec_num,
2108 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2109 if (buf_spec_num >= 0 &&
2110 buf_spec_num < BUFSPEC_POOL_SIZE
2111 ) {
2112 spin_lock_irqsave(&hw->bufspec_lock, flags);
2113 hw->buffer_spec[buf_spec_num].used = 0;
2114 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2115 if (hw->mmu_enable) {
2116 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2117 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2118 cur_buf_idx = cur_buf_idx&0xff;*/
2119 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2120 }
2121 release_aux_data(hw, buf_spec_num);
2122 }
2123 if (dpb_is_debug(DECODE_ID(hw),
2124 PRINT_FLAG_DUMP_BUFSPEC))
2125 dump_bufspec(hw, __func__);
2126 return 0;
2127}
2128
2129static void config_buf_specs(struct vdec_s *vdec)
2130{
2131 int i, j;
2132 unsigned long flags;
2133 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2134 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2135
2136 spin_lock_irqsave(&hw->bufspec_lock, flags);
2137 for (i = 0, j = 0;
2138 j < hw->dpb.mDPB.size
2139 && i < BUFSPEC_POOL_SIZE;
2140 i++) {
2141 int canvas;
2142 if (hw->buffer_spec[i].used != -1)
2143 continue;
2144 if (vdec->parallel_dec == 1) {
2145 if (hw->buffer_spec[i].y_canvas_index == -1)
2146 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2147 if (hw->buffer_spec[i].u_canvas_index == -1) {
2148 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2149 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2150 }
2151#ifdef VDEC_DW
2152 if (IS_VDEC_DW(hw)) {
2153 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2154 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2155 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2156 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2157 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2158 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2159 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2160 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2161 }
2162 }
2163#endif
2164 } else {
2165 canvas = vdec->get_canvas(j * mode, 2);
2166 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2167 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2168 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2169 dpb_print(DECODE_ID(hw),
2170 PRINT_FLAG_DPB_DETAIL,
2171 "config canvas (%d) %x for bufspec %d\r\n",
2172 j, canvas, i);
2173#ifdef VDEC_DW
2174 if (IS_VDEC_DW(hw)) {
2175 canvas = vdec->get_canvas(j * mode + 1, 2);
2176 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2177 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2178 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2179 dpb_print(DECODE_ID(hw),
2180 PRINT_FLAG_DPB_DETAIL,
2181 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2182 j, canvas, i);
2183 }
2184#endif
2185 }
2186
2187 hw->buffer_spec[i].used = 0;
2188 hw->buffer_spec[i].canvas_pos = j;
2189
2190
2191 j++;
2192 }
2193 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2194}
2195
2196static void config_buf_specs_ex(struct vdec_s *vdec)
2197{
2198 int i, j;
2199 unsigned long flags;
2200 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2201 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2202
2203 spin_lock_irqsave(&hw->bufspec_lock, flags);
2204 for (i = 0, j = 0;
2205 j < hw->dpb.mDPB.size
2206 && i < BUFSPEC_POOL_SIZE;
2207 i++) {
2208 int canvas = 0;
2209 if (hw->buffer_spec[i].used != -1)
2210 continue;
2211 if (vdec->parallel_dec == 1) {
2212 if (hw->buffer_spec[i].y_canvas_index == -1)
2213 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2214 if (hw->buffer_spec[i].u_canvas_index == -1) {
2215 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2216 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2217 }
2218#ifdef VDEC_DW
2219 if (IS_VDEC_DW(hw)) {
2220 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2221 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2222 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2223 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2224 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2225 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2226 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2227 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2228 }
2229 }
2230#endif
2231 } else {
2232 canvas = vdec->get_canvas(j* mode, 2);
2233 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2234 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2235 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2236
2237 dpb_print(DECODE_ID(hw),
2238 PRINT_FLAG_DPB_DETAIL,
2239 "config canvas (%d) %x for bufspec %d\r\n",
2240 j, canvas, i);
2241#ifdef VDEC_DW
2242 if (IS_VDEC_DW(hw)) {
2243 canvas = vdec->get_canvas(j*mode + 1, 2);
2244 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2245 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2246 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2247 dpb_print(DECODE_ID(hw),
2248 PRINT_FLAG_DPB_DETAIL,
2249 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2250 j, canvas, i);
2251 }
2252#endif
2253 }
2254
2255 hw->buffer_spec[i].used = 0;
2256 hw->buffer_spec[i].alloc_header_addr = 0;
2257 hw->buffer_spec[i].canvas_pos = j;
2258
2259 j++;
2260 }
2261 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2262}
2263
2264
2265static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2266 unsigned char release_all)
2267{
2268 int i;
2269 unsigned long flags;
2270 unsigned char dealloc_flag = 0;
2271 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2272 if (hw->buffer_spec[i].used == 4 ||
2273 release_all) {
2274 dealloc_flag = 1;
2275 dpb_print(DECODE_ID(hw),
2276 PRINT_FLAG_DPB_DETAIL,
2277 "%s buf_spec_num %d\n",
2278 __func__, i
2279 );
2280 spin_lock_irqsave
2281 (&hw->bufspec_lock, flags);
2282 hw->buffer_spec[i].used = -1;
2283 spin_unlock_irqrestore
2284 (&hw->bufspec_lock, flags);
2285 release_aux_data(hw, i);
2286
2287 if (!hw->mmu_enable) {
2288 if (hw->buffer_spec[i].cma_alloc_addr) {
2289 if (!hw->is_used_v4l) {
2290 decoder_bmmu_box_free_idx(
2291 hw->bmmu_box,
2292 i);
2293 }
2294 spin_lock_irqsave
2295 (&hw->bufspec_lock, flags);
2296 hw->buffer_spec[i].cma_alloc_addr = 0;
2297 hw->buffer_spec[i].buf_adr = 0;
2298 spin_unlock_irqrestore
2299 (&hw->bufspec_lock, flags);
2300 }
2301 } else {
2302 if (hw->buffer_spec[i].alloc_header_addr) {
2303 decoder_mmu_box_free_idx(
2304 hw->mmu_box,
2305 i);
2306 spin_lock_irqsave
2307 (&hw->bufspec_lock, flags);
2308 hw->buffer_spec[i].
2309 alloc_header_addr = 0;
2310 hw->buffer_spec[i].buf_adr = 0;
2311 spin_unlock_irqrestore
2312 (&hw->bufspec_lock, flags);
2313 }
2314 }
2315 }
2316 }
2317 if (dealloc_flag &&
2318 dpb_is_debug(DECODE_ID(hw),
2319 PRINT_FLAG_DUMP_BUFSPEC))
2320 dump_bufspec(hw, __func__);
2321 return;
2322}
2323
2324unsigned char have_free_buf_spec(struct vdec_s *vdec)
2325{
2326 int i;
2327 unsigned long addr;
2328 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2329 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2330 int index = -1;
2331 int ret = 0;
2332 int allocated_count = 0;
2333 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2334 if (hw->mmu_enable)
2335 addr = hw->buffer_spec[i].alloc_header_addr;
2336 else
2337 addr = hw->buffer_spec[i].cma_alloc_addr;
2338 if (hw->buffer_spec[i].used == 0) {
2339
2340 if (addr)
2341 return 1;
2342 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2343 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2344 index = i;
2345 }
2346 }
2347 if (addr)
2348 allocated_count++;
2349 }
2350 if (index >= 0) {
2351 mutex_lock(&vmh264_mutex);
2352 dealloc_buf_specs(hw, 0);
2353 if (max_alloc_buf_count == 0 ||
2354 allocated_count < max_alloc_buf_count) {
2355 if (hw->is_used_v4l)
2356 ret = 1;
2357 else if (alloc_one_buf_spec(hw, index) >= 0)
2358 ret = 1;
2359 }
2360 mutex_unlock(&vmh264_mutex);
2361 }
2362 return ret;
2363}
2364
2365static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2366 int canvas_pos)
2367{
2368 int i;
2369 int j = 0;
2370 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2371 if (hw->buffer_spec[i].canvas_pos >= 0) {
2372 if (j == canvas_pos)
2373 return i;
2374 j++;
2375 }
2376 }
2377 return -1;
2378}
2379static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2380 struct vframe_s *vf, int index)
2381{
2382 if (index < 0) {
2383 vf->mem_handle = NULL;
2384 vf->mem_head_handle = NULL;
2385 } else if (vf->type & VIDTYPE_SCATTER) {
2386 vf->mem_handle =
2387 decoder_mmu_box_get_mem_handle(
2388 hw->mmu_box, index);
2389 vf->mem_head_handle =
2390 decoder_bmmu_box_get_mem_handle(
2391 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2392 } else {
2393 vf->mem_handle =
2394 decoder_bmmu_box_get_mem_handle(
2395 hw->bmmu_box, VF_BUFFER_IDX(index));
2396 /* vf->mem_head_handle =
2397 decoder_bmmu_box_get_mem_handle(
2398 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2399 }
2400 return;
2401}
2402static int check_force_interlace(struct vdec_h264_hw_s *hw,
2403 struct FrameStore *frame)
2404{
2405 int bForceInterlace = 0;
2406 /* no di in secure mode, disable force di */
2407 if (vdec_secure(hw_to_vdec(hw)))
2408 return 0;
2409 if (frame->frame) {
2410 if (frame->frame->coded_frame
2411 && !frame->frame->frame_mbs_only_flag) {
2412 if (frame->frame->structure == FRAME)
2413 return 1;
2414 }
2415 }
2416
2417 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2418 && hw->bitstream_restriction_flag
2419 && (hw->frame_width == 1920)
2420 && (hw->frame_height >= 1080)
2421 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2422 bForceInterlace = 1;
2423 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2424 && (hw->frame_width == 720)
2425 && (hw->frame_height == 576)
2426 && (hw->frame_dur == 3840)) {
2427 bForceInterlace = 1;
2428 }
2429
2430 return bForceInterlace;
2431}
2432
2433static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2434{
2435 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2436 if (frame->slice_type == I_SLICE)
2437 vframe_qos->type = 1;
2438 else if (frame->slice_type == P_SLICE)
2439 vframe_qos->type = 2;
2440 else if (frame->slice_type == B_SLICE)
2441 vframe_qos->type = 3;
2442
2443 vframe_qos->size = frame->frame_size;
2444 vframe_qos->pts = frame->pts64;
2445
2446 vframe_qos->max_mv = frame->max_mv;
2447 vframe_qos->avg_mv = frame->avg_mv;
2448 vframe_qos->min_mv = frame->min_mv;
2449/*
2450 pr_info("mv: max:%d, avg:%d, min:%d\n",
2451 vframe_qos->max_mv,
2452 vframe_qos->avg_mv,
2453 vframe_qos->min_mv);
2454*/
2455
2456 vframe_qos->max_qp = frame->max_qp;
2457 vframe_qos->avg_qp = frame->avg_qp;
2458 vframe_qos->min_qp = frame->min_qp;
2459/*
2460 pr_info("qp: max:%d, avg:%d, min:%d\n",
2461 vframe_qos->max_qp,
2462 vframe_qos->avg_qp,
2463 vframe_qos->min_qp);
2464*/
2465
2466 vframe_qos->max_skip = frame->max_skip;
2467 vframe_qos->avg_skip = frame->avg_skip;
2468 vframe_qos->min_skip = frame->min_skip;
2469/*
2470 pr_info("skip: max:%d, avg:%d, min:%d\n",
2471 vframe_qos->max_skip,
2472 vframe_qos->avg_skip,
2473 vframe_qos->min_skip);
2474*/
2475 vframe_qos->num++;
2476 if (hw->frameinfo_enable)
2477 vdec_fill_frame_info(vframe_qos, 1);
2478}
2479
2480static int is_iframe(struct FrameStore *frame) {
2481
2482 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2483 return 1;
2484 }
2485 return 0;
2486}
2487
2488
2489
2490int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2491{
2492 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2493 struct vframe_s *vf = NULL;
2494 int buffer_index = frame->buf_spec_num;
2495 int vf_count = 1;
2496 int i;
2497 int bForceInterlace = 0;
2498
2499 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2500 dpb_print(DECODE_ID(hw), 0,
2501 "%s, buffer_index 0x%x is beyond range\n",
2502 __func__, buffer_index);
2503 return -1;
2504 }
2505 if (force_disp_bufspec_num & 0x100) {
2506 /*recycle directly*/
2507 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2508 hw->buffer_spec[frame->buf_spec_num].used != 5)
2509 set_frame_output_flag(&hw->dpb, frame->index);
2510
2511 /*make pre_output not set*/
2512 return -1;
2513 }
2514 if (error_proc_policy & 0x1000) {
2515 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2516 int error_skip_frame_count = error_skip_count & 0xfff;
2517 if (((hw->no_error_count < error_skip_frame_count)
2518 && (error_skip_i_count == 0 ||
2519 hw->no_error_i_count < error_skip_i_count))
2520 && (!(frame->data_flag & I_FLAG)))
2521 frame->data_flag |= ERROR_FLAG;
2522 }
2523 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2524 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2525 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2526 frame->poc, hw->data_flag & ERROR_FLAG,
2527 error_proc_policy);
2528 if (frame->frame == NULL &&
2529 ((frame->is_used == 1 && frame->top_field)
2530 || (frame->is_used == 2 && frame->bottom_field))) {
2531 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2532 "%s Error frame_num %d used %d\n",
2533 __func__, frame->frame_num, frame->is_used);
2534 frame->data_flag |= ERROR_FLAG;
2535 }
2536 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2537 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2538 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2539 0, &frame->pts64) == 0)) {
2540 hw->last_pts64 = frame->pts64;
2541 hw->last_pts = frame->pts;
2542 } else {
2543 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2544 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2545 }
2546 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2547 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2548 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2549 frame->offset_delimiter, frame->pts,hw->last_pts,
2550 frame->pts64, hw->last_pts64, hw->frame_dur);
2551 hw->last_pts64 = frame->pts64;
2552 hw->last_pts = frame->pts;
2553 }
2554 if ((frame->data_flag & NODISP_FLAG) ||
2555 (frame->data_flag & NULL_FLAG) ||
2556 ((!hw->send_error_frame_flag) &&
2557 (frame->data_flag & ERROR_FLAG)) ||
2558 ((hw->i_only & 0x1) &&
2559 (!(frame->data_flag & I_FLAG)))
2560 ) {
2561 set_frame_output_flag(&hw->dpb, frame->index);
2562 return 0; /*do not return -1,
2563 otherwise flush_dpb() will not flush all dbp frames*/
2564 }
2565
2566 display_frame_count[DECODE_ID(hw)]++;
2567
2568 if (dpb_is_debug(DECODE_ID(hw),
2569 PRINT_FLAG_DPB_DETAIL)) {
2570 dpb_print(DECODE_ID(hw), 0,
2571 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2572 __func__, frame->index, frame->poc,
2573 frame->buf_spec_num);
2574 print_pic_info(DECODE_ID(hw), "predis_frm",
2575 frame->frame, -1);
2576 print_pic_info(DECODE_ID(hw), "predis_top",
2577 frame->top_field, -1);
2578 print_pic_info(DECODE_ID(hw), "predis_bot",
2579 frame->bottom_field, -1);
2580 }
2581
2582 if (!is_interlace(frame))
2583 vf_count = 1;
2584 else
2585 vf_count = 2;
2586 bForceInterlace = check_force_interlace(hw, frame);
2587 if (bForceInterlace)
2588 vf_count = 2;
2589 hw->buffer_spec[buffer_index].vf_ref = 0;
2590 fill_frame_info(hw, frame);
2591 for (i = 0; i < vf_count; i++) {
2592 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2593 vf == NULL) {
2594 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2595 "%s fatal error, no available buffer slot.\n",
2596 __func__);
2597 return -1;
2598 }
2599 vf->duration_pulldown = 0;
2600 if (!(is_iframe(frame)) && hw->unstable_pts) {
2601 vf->pts = 0;
2602 vf->pts_us64 = 0;
2603 vf->timestamp = 0;
2604 vf->index = VF_INDEX(frame->index, buffer_index);
2605 } else {
2606 vf->pts = frame->pts;
2607 vf->pts_us64 = frame->pts64;
2608 vf->timestamp = frame->timestamp;
2609 vf->index = VF_INDEX(frame->index, buffer_index);
2610 }
2611
2612 if (hw->is_used_v4l) {
2613 vf->v4l_mem_handle
2614 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2615 }
2616
2617 if (hw->mmu_enable) {
2618 if (hw->double_write_mode & 0x10) {
2619 /* double write only */
2620 vf->compBodyAddr = 0;
2621 vf->compHeadAddr = 0;
2622 } else {
2623 /*head adr*/
2624 vf->compHeadAddr =
2625 hw->buffer_spec[buffer_index].alloc_header_addr;
2626 /*body adr*/
2627 vf->compBodyAddr = 0;
2628 vf->canvas0Addr = vf->canvas1Addr = 0;
2629 }
2630
2631 vf->type = VIDTYPE_SCATTER;
2632
2633 if (hw->double_write_mode) {
2634 vf->type |= VIDTYPE_PROGRESSIVE
2635 | VIDTYPE_VIU_FIELD;
2636 vf->type |= VIDTYPE_VIU_NV21;
2637 if (hw->double_write_mode == 3)
2638 vf->type |= VIDTYPE_COMPRESS;
2639
2640 vf->canvas0Addr = vf->canvas1Addr = -1;
2641 vf->plane_num = 2;
2642 vf->canvas0_config[0] =
2643 hw->buffer_spec[buffer_index].
2644 canvas_config[0];
2645 vf->canvas0_config[1] =
2646 hw->buffer_spec[buffer_index].
2647 canvas_config[1];
2648
2649 vf->canvas1_config[0] =
2650 hw->buffer_spec[buffer_index].
2651 canvas_config[0];
2652 vf->canvas1_config[1] =
2653 hw->buffer_spec[buffer_index].
2654 canvas_config[1];
2655
2656 } else {
2657 vf->type |=
2658 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2659 vf->canvas0Addr = vf->canvas1Addr = 0;
2660 }
2661
2662 vf->bitdepth =
2663 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2664
2665 vf->compWidth = hw->frame_width;
2666 vf->compHeight = hw->frame_height;
2667 } else {
2668 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2669 VIDTYPE_VIU_NV21;
2670
2671 vf->canvas0Addr = vf->canvas1Addr =
2672 spec2canvas(&hw->buffer_spec[buffer_index]);
2673#ifdef VDEC_DW
2674 if (IS_VDEC_DW(hw))
2675 vf->canvas0Addr = vf->canvas1Addr =
2676 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2677#endif
2678
2679 }
2680 set_frame_info(hw, vf, buffer_index);
2681
2682 if (hw->mmu_enable && hw->double_write_mode) {
2683 vf->width = hw->frame_width /
2684 get_double_write_ratio(hw);
2685 vf->height = hw->frame_height /
2686 get_double_write_ratio(hw);
2687 }
2688
2689 vf->flag = 0;
2690 if (frame->data_flag & I_FLAG)
2691 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2692 if (frame->data_flag & ERROR_FLAG)
2693 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2694 update_vf_memhandle(hw, vf, buffer_index);
2695 hw->buffer_spec[buffer_index].used = 2;
2696 hw->buffer_spec[buffer_index].vf_ref++;
2697
2698 if (bForceInterlace || is_interlace(frame)) {
2699 vf->type =
2700 VIDTYPE_INTERLACE_FIRST |
2701 VIDTYPE_VIU_NV21;
2702
2703 if (bForceInterlace) {
2704 vf->type |= (i == 0 ?
2705 VIDTYPE_INTERLACE_TOP :
2706 VIDTYPE_INTERLACE_BOTTOM);
2707 if (i == 1) {
2708 vf->pts = 0;
2709 vf->pts_us64 = 0;
2710 }
2711 } else if (frame->top_field->poc <=
2712 frame->bottom_field->poc) /*top first*/
2713 vf->type |= (i == 0 ?
2714 VIDTYPE_INTERLACE_TOP :
2715 VIDTYPE_INTERLACE_BOTTOM);
2716 else
2717 vf->type |= (i == 0 ?
2718 VIDTYPE_INTERLACE_BOTTOM :
2719 VIDTYPE_INTERLACE_TOP);
2720 vf->duration = vf->duration/2;
2721 }
2722
2723 if (i == 0)
2724 decoder_do_frame_check(hw_to_vdec(hw), vf);
2725
2726 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2727 vf->sar_width = hw->width_aspect_ratio;
2728 vf->sar_height = hw->height_aspect_ratio;
2729
2730 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2731 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2732 hw->vf_pre_count++;
2733 vdec->vdec_fps_detec(vdec->id);
2734 if (without_display_mode == 0) {
2735 vf_notify_receiver(vdec->vf_provider_name,
2736 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2737 } else
2738 vh264_vf_put(vh264_vf_get(vdec), vdec);
2739 }
2740 if (dpb_is_debug(DECODE_ID(hw),
2741 PRINT_FLAG_DUMP_BUFSPEC))
2742 dump_bufspec(hw, __func__);
2743
2744 return 0;
2745}
2746
2747int notify_v4l_eos(struct vdec_s *vdec)
2748{
2749 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2750 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2751 struct vframe_s *vf = NULL;
2752 int index = INVALID_IDX;
2753 ulong expires;
2754
2755 if (hw->is_used_v4l && hw->eos) {
2756 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
2757 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2758 "%s fatal error, no available buffer slot.\n",
2759 __func__);
2760 return -1;
2761 }
2762
2763 expires = jiffies + msecs_to_jiffies(2000);
2764 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2765 if (time_after(jiffies, expires))
2766 break;
2767 }
2768
2769 if (index == INVALID_IDX) {
2770 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2771 return -1;
2772 }
2773
2774 vf->type |= VIDTYPE_V4L_EOS;
2775 vf->timestamp = ULONG_MAX;
2776 vf->v4l_mem_handle = hw->buffer_spec[index].cma_alloc_addr;
2777 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2778
2779 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2780
2781 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2782 vf_notify_receiver(vdec->vf_provider_name,
2783 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2784
2785 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2786 }
2787
2788 return 0;
2789}
2790
2791/******************
2792 * Hardware config
2793 */
2794char *slice_type_name[] = {
2795 "P_SLICE ",
2796 "B_SLICE ",
2797 "I_SLICE ",
2798 "SP_SLICE",
2799 "SI_SLICE",
2800};
2801
2802char *picture_structure_name[] = {
2803 "FRAME",
2804 "TOP_FIELD",
2805 "BOTTOM_FIELD"
2806};
2807
2808void print_pic_info(int decindex, const char *info,
2809 struct StorablePicture *pic,
2810 int slice_type)
2811{
2812 if (pic)
2813 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2814 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2815 info,
2816 picture_structure_name[pic->structure],
2817 pic->coded_frame ? "Frame" : "Field",
2818 (slice_type < 0 ||
2819 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2820 pic->mb_aff_frame_flag,
2821 pic->poc,
2822 pic->pic_num,
2823 pic->buf_spec_num,
2824 pic->data_flag);
2825}
2826
2827static void reset_process_time(struct vdec_h264_hw_s *hw)
2828{
2829 if (hw->start_process_time) {
2830 unsigned process_time =
2831 1000 * (jiffies - hw->start_process_time) / HZ;
2832 hw->start_process_time = 0;
2833 if (process_time > max_process_time[DECODE_ID(hw)])
2834 max_process_time[DECODE_ID(hw)] = process_time;
2835 }
2836}
2837
2838static void start_process_time(struct vdec_h264_hw_s *hw)
2839{
2840 hw->decode_timeout_count = 10;
2841 hw->start_process_time = jiffies;
2842}
2843
2844static void config_aux_buf(struct vdec_h264_hw_s *hw)
2845{
2846 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2847 WRITE_VREG(H264_AUX_DATA_SIZE,
2848 ((hw->prefix_aux_size >> 4) << 16) |
2849 (hw->suffix_aux_size >> 4)
2850 );
2851}
2852
2853/*
2854* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2855*/
2856static void set_aux_data(struct vdec_h264_hw_s *hw,
2857 struct StorablePicture *pic, unsigned char suffix_flag,
2858 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2859{
2860 int i;
2861 unsigned short *aux_adr;
2862 unsigned size_reg_val =
2863 READ_VREG(H264_AUX_DATA_SIZE);
2864 unsigned aux_count = 0;
2865 int aux_size = 0;
2866 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2867 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2868 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2869 return;
2870
2871 if (suffix_flag) {
2872 aux_adr = (unsigned short *)
2873 (hw_buf->aux_addr +
2874 hw_buf->prefix_aux_size);
2875 aux_count =
2876 ((size_reg_val & 0xffff) << 4)
2877 >> 1;
2878 aux_size =
2879 hw_buf->suffix_aux_size;
2880 } else {
2881 aux_adr =
2882 (unsigned short *)hw_buf->aux_addr;
2883 aux_count =
2884 ((size_reg_val >> 16) << 4)
2885 >> 1;
2886 aux_size =
2887 hw_buf->prefix_aux_size;
2888 }
2889 if (dpb_is_debug(DECODE_ID(hw),
2890 PRINT_FLAG_DPB_DETAIL)) {
2891 dpb_print(DECODE_ID(hw), 0,
2892 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2893 __func__, AUX_DATA_SIZE(pic),
2894 aux_count, suffix_flag, dv_meta_flag);
2895 }
2896 if (aux_size > 0 && aux_count > 0) {
2897 int heads_size = 0;
2898 int new_size;
2899 char *new_buf;
2900 for (i = 0; i < aux_count; i++) {
2901 unsigned char tag = aux_adr[i] >> 8;
2902 if (tag != 0 && tag != 0xff) {
2903 if (dv_meta_flag == 0)
2904 heads_size += 8;
2905 else if (dv_meta_flag == 1 && tag == 0x1)
2906 heads_size += 8;
2907 else if (dv_meta_flag == 2 && tag != 0x1)
2908 heads_size += 8;
2909 }
2910 }
2911 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2912 new_buf = krealloc(AUX_DATA_BUF(pic),
2913 new_size,
2914 GFP_KERNEL);
2915 if (new_buf) {
2916 unsigned char valid_tag = 0;
2917 unsigned char *h =
2918 new_buf +
2919 AUX_DATA_SIZE(pic);
2920 unsigned char *p = h + 8;
2921 int len = 0;
2922 int padding_len = 0;
2923 AUX_DATA_BUF(pic) = new_buf;
2924 for (i = 0; i < aux_count; i += 4) {
2925 int ii;
2926 unsigned char tag = aux_adr[i + 3] >> 8;
2927 if (tag != 0 && tag != 0xff) {
2928 if (dv_meta_flag == 0)
2929 valid_tag = 1;
2930 else if (dv_meta_flag == 1
2931 && tag == 0x1)
2932 valid_tag = 1;
2933 else if (dv_meta_flag == 2
2934 && tag != 0x1)
2935 valid_tag = 1;
2936 else
2937 valid_tag = 0;
2938 if (valid_tag && len > 0) {
2939 AUX_DATA_SIZE(pic) +=
2940 (len + 8);
2941 h[0] =
2942 (len >> 24) & 0xff;
2943 h[1] =
2944 (len >> 16) & 0xff;
2945 h[2] =
2946 (len >> 8) & 0xff;
2947 h[3] =
2948 (len >> 0) & 0xff;
2949 h[6] =
2950 (padding_len >> 8)
2951 & 0xff;
2952 h[7] =
2953 (padding_len) & 0xff;
2954 h += (len + 8);
2955 p += 8;
2956 len = 0;
2957 padding_len = 0;
2958 }
2959 if (valid_tag) {
2960 h[4] = tag;
2961 h[5] = 0;
2962 h[6] = 0;
2963 h[7] = 0;
2964 }
2965 }
2966 if (valid_tag) {
2967 for (ii = 0; ii < 4; ii++) {
2968 unsigned short aa =
2969 aux_adr[i + 3
2970 - ii];
2971 *p = aa & 0xff;
2972 p++;
2973 len++;
2974 /*if ((aa >> 8) == 0xff)
2975 padding_len++;*/
2976 }
2977 }
2978 }
2979 if (len > 0) {
2980 AUX_DATA_SIZE(pic) += (len + 8);
2981 h[0] = (len >> 24) & 0xff;
2982 h[1] = (len >> 16) & 0xff;
2983 h[2] = (len >> 8) & 0xff;
2984 h[3] = (len >> 0) & 0xff;
2985 h[6] = (padding_len >> 8) & 0xff;
2986 h[7] = (padding_len) & 0xff;
2987 }
2988 if (dpb_is_debug(DECODE_ID(hw),
2989 PRINT_FLAG_DPB_DETAIL)) {
2990 dpb_print(DECODE_ID(hw), 0,
2991 "aux: (size %d) suffix_flag %d\n",
2992 AUX_DATA_SIZE(pic), suffix_flag);
2993 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2994 dpb_print_cont(DECODE_ID(hw), 0,
2995 "%02x ", AUX_DATA_BUF(pic)[i]);
2996 if (((i + 1) & 0xf) == 0)
2997 dpb_print_cont(
2998 DECODE_ID(hw),
2999 0, "\n");
3000 }
3001 dpb_print_cont(DECODE_ID(hw),
3002 0, "\n");
3003 }
3004
3005 }
3006 }
3007
3008}
3009
3010static void release_aux_data(struct vdec_h264_hw_s *hw,
3011 int buf_spec_num)
3012{
3013 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3014 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3015 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3016}
3017
3018static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3019{
3020 int i;
3021 unsigned short *aux_adr =
3022 (unsigned short *)
3023 hw->aux_addr;
3024 unsigned aux_size =
3025 (READ_VREG(H264_AUX_DATA_SIZE)
3026 >> 16) << 4;
3027
3028 if (hw->prefix_aux_size > 0) {
3029 dpb_print(DECODE_ID(hw),
3030 0,
3031 "prefix aux: (size %d)\n",
3032 aux_size);
3033 for (i = 0; i <
3034 (aux_size >> 1); i++) {
3035 dpb_print_cont(DECODE_ID(hw),
3036 0,
3037 "%04x ",
3038 *(aux_adr + i));
3039 if (((i + 1) & 0xf)
3040 == 0)
3041 dpb_print_cont(
3042 DECODE_ID(hw),
3043 0, "\n");
3044 }
3045 }
3046 if (hw->suffix_aux_size > 0) {
3047 aux_adr = (unsigned short *)
3048 (hw->aux_addr +
3049 hw->prefix_aux_size);
3050 aux_size =
3051 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3052 << 4;
3053 dpb_print(DECODE_ID(hw),
3054 0,
3055 "suffix aux: (size %d)\n",
3056 aux_size);
3057 for (i = 0; i <
3058 (aux_size >> 1); i++) {
3059 dpb_print_cont(DECODE_ID(hw),
3060 0,
3061 "%04x ", *(aux_adr + i));
3062 if (((i + 1) & 0xf) == 0)
3063 dpb_print_cont(DECODE_ID(hw),
3064 0, "\n");
3065 }
3066 }
3067}
3068
3069static void config_decode_mode(struct vdec_h264_hw_s *hw)
3070{
3071#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3072 struct vdec_s *vdec = hw_to_vdec(hw);
3073#endif
3074 if (input_frame_based(hw_to_vdec(hw)))
3075 WRITE_VREG(H264_DECODE_MODE,
3076 DECODE_MODE_MULTI_FRAMEBASE);
3077#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3078 else if (vdec->slave)
3079 WRITE_VREG(H264_DECODE_MODE,
3080 (hw->got_valid_nal << 8) |
3081 DECODE_MODE_MULTI_DVBAL);
3082 else if (vdec->master)
3083 WRITE_VREG(H264_DECODE_MODE,
3084 (hw->got_valid_nal << 8) |
3085 DECODE_MODE_MULTI_DVENL);
3086#endif
3087 else
3088 WRITE_VREG(H264_DECODE_MODE,
3089 DECODE_MODE_MULTI_STREAMBASE);
3090 WRITE_VREG(H264_DECODE_SEQINFO,
3091 hw->seq_info2);
3092 WRITE_VREG(HEAD_PADING_REG, 0);
3093
3094 if (hw->init_flag == 0)
3095 WRITE_VREG(INIT_FLAG_REG, 0);
3096 else
3097 WRITE_VREG(INIT_FLAG_REG, 1);
3098}
3099int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3100{
3101 /* static int count = 0; */
3102 int ret = 0;
3103 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3104 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3105 unsigned int colocate_adr_offset;
3106 unsigned int val;
3107 struct StorablePicture *last_pic = hw->last_dec_picture;
3108
3109#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3110 int colocate_buf_index;
3111#endif
3112#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3113#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3114#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3115#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3116
3117#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3118/* bit 31:30 -- L1[0] picture coding structure,
3119 * 00 - top field, 01 - bottom field,
3120 * 10 - frame, 11 - mbaff frame
3121 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3122 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3123 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3124 */
3125#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3126
3127/* bit 15 -- flush co_mb_data to DDR -- W-Only
3128 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3129 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3130 * bit 9 -- soft_reset -- W-Only
3131 * bit 8 -- upgent
3132 * bit 7:2 -- h264_co_mb_mem_wr_addr
3133 * bit 1:0 -- h264_co_mb_info_wr_ptr
3134 */
3135#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3136
3137 unsigned long canvas_adr;
3138 unsigned int ref_reg_val;
3139 unsigned int one_ref_cfg = 0;
3140 int h264_buffer_info_data_write_count;
3141 int i, j;
3142 unsigned int colocate_wr_adr;
3143 unsigned int colocate_rd_adr;
3144 unsigned char use_direct_8x8;
3145 int canvas_pos;
3146 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3147 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3148 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3149 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3150 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3151
3152 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3153 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3154 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3155 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3156 canvas_pos);
3157 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3158
3159#ifdef VDEC_DW
3160 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3161 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3162 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3163#endif
3164 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3165 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3166
3167 if (!hw->mmu_enable) {
3168 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3169 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3170 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3171#ifdef VDEC_DW
3172 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3173 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3174 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3175#endif
3176 } else
3177 hevc_sao_set_pic_buffer(hw, pic);
3178
3179 if (pic->mb_aff_frame_flag)
3180 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3181 else if (pic->structure == TOP_FIELD)
3182 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3183 else if (pic->structure == BOTTOM_FIELD)
3184 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3185 else
3186 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3187
3188 if (pic->bottom_poc < pic->top_poc)
3189 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3190
3191 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3192 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3193 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3194
3195 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3196 int long_term_flag;
3197 i = get_buf_spec_by_canvas_pos(hw, j);
3198 if (i < 0)
3199 break;
3200 long_term_flag =
3201 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3202 if (long_term_flag > 0) {
3203 if (long_term_flag & 0x1)
3204 hw->buffer_spec[i].info0 |= (1 << 4);
3205 else
3206 hw->buffer_spec[i].info0 &= ~(1 << 4);
3207
3208 if (long_term_flag & 0x2)
3209 hw->buffer_spec[i].info0 |= (1 << 5);
3210 else
3211 hw->buffer_spec[i].info0 &= ~(1 << 5);
3212 }
3213
3214 if (i == pic->buf_spec_num)
3215 WRITE_VREG(H264_BUFFER_INFO_DATA,
3216 hw->buffer_spec[i].info0 | 0xf);
3217 else
3218 WRITE_VREG(H264_BUFFER_INFO_DATA,
3219 hw->buffer_spec[i].info0);
3220 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3221 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3222 }
3223
3224 /* config reference buffer */
3225 if (hw->mmu_enable) {
3226 hevc_mcr_config_mc_ref(hw);
3227 hevc_mcr_config_mcrcc(hw);
3228 }
3229
3230 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3231 "list0 size %d\n", pSlice->listXsize[0]);
3232 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3233 ref_reg_val = 0;
3234 j = 0;
3235 h264_buffer_info_data_write_count = 0;
3236
3237 //disable this read cache when frame width <= 64 (4MBs)
3238 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3239 if (hw->frame_width <= 64)
3240 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3241 else
3242 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3243
3244 if (last_pic)
3245 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3246 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3247 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3248 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3249 last_pic && (last_pic->data_flag & ERROR_FLAG)
3250 && (!(last_pic->slice_type == B_SLICE))
3251 && (!(pSlice->slice_type == I_SLICE))) {
3252 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3253 "no i/idr error mark\n");
3254 hw->data_flag |= ERROR_FLAG;
3255 pic->data_flag |= ERROR_FLAG;
3256 }
3257
3258 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3259 /*ref list 0 */
3260 struct StorablePicture *ref = pSlice->listX[0][i];
3261 unsigned int cfg;
3262 /* bit[6:5] - frame/field info,
3263 * 01 - top, 10 - bottom, 11 - frame
3264 */
3265 #ifdef ERROR_CHECK
3266 if (ref == NULL) {
3267 hw->data_flag |= ERROR_FLAG;
3268 pic->data_flag |= ERROR_FLAG;
3269 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3270 return -1;
3271 }
3272 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3273 hw->data_flag |= ERROR_FLAG;
3274 pic->data_flag |= ERROR_FLAG;
3275 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3276 }
3277 if (ref->data_flag & NULL_FLAG)
3278 hw->data_flag |= NULL_FLAG;
3279#endif
3280 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3281
3282 if (ref->structure == TOP_FIELD)
3283 cfg = 0x1;
3284 else if (ref->structure == BOTTOM_FIELD)
3285 cfg = 0x2;
3286 else /* FRAME */
3287 cfg = 0x3;
3288
3289 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3290 ref_reg_val <<= 8;
3291 ref_reg_val |= one_ref_cfg;
3292 j++;
3293
3294 if (j == 4) {
3295 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3296 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3297 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3298 h264_buffer_info_data_write_count++;
3299 j = 0;
3300 }
3301 print_pic_info(DECODE_ID(hw), "list0",
3302 pSlice->listX[0][i], -1);
3303 }
3304 if (j != 0) {
3305 while (j != 4) {
3306 ref_reg_val <<= 8;
3307 ref_reg_val |= one_ref_cfg;
3308 j++;
3309 }
3310 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3311 "H264_BUFFER_INFO_DATA: %x\n",
3312 ref_reg_val);
3313 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3314 h264_buffer_info_data_write_count++;
3315 }
3316 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3317 (one_ref_cfg << 8) | one_ref_cfg;
3318 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3319 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3320
3321 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3322 "list1 size %d\n", pSlice->listXsize[1]);
3323 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3324 ref_reg_val = 0;
3325 j = 0;
3326
3327 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3328 /* ref list 0 */
3329 struct StorablePicture *ref = pSlice->listX[1][i];
3330 unsigned int cfg;
3331 /* bit[6:5] - frame/field info,
3332 * 01 - top, 10 - bottom, 11 - frame
3333 */
3334
3335 #ifdef ERROR_CHECK
3336 if (ref == NULL) {
3337 hw->data_flag |= ERROR_FLAG;
3338 pic->data_flag |= ERROR_FLAG;
3339 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3340 return -2;
3341 }
3342 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3343 pic->data_flag |= ERROR_FLAG;
3344 hw->data_flag |= ERROR_FLAG;
3345 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3346 }
3347 if (ref->data_flag & NULL_FLAG)
3348 hw->data_flag |= NULL_FLAG;
3349#endif
3350 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3351 if (ref->structure == TOP_FIELD)
3352 cfg = 0x1;
3353 else if (ref->structure == BOTTOM_FIELD)
3354 cfg = 0x2;
3355 else /* FRAME */
3356 cfg = 0x3;
3357 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3358 ref_reg_val <<= 8;
3359 ref_reg_val |= one_ref_cfg;
3360 j++;
3361
3362 if (j == 4) {
3363 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3364 "H264_BUFFER_INFO_DATA: %x\n",
3365 ref_reg_val);
3366 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3367 j = 0;
3368 }
3369 print_pic_info(DECODE_ID(hw), "list1",
3370 pSlice->listX[1][i], -1);
3371 }
3372 if (j != 0) {
3373 while (j != 4) {
3374 ref_reg_val <<= 8;
3375 ref_reg_val |= one_ref_cfg;
3376 j++;
3377 }
3378 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3379 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3380 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3381 }
3382
3383 /* configure co-locate buffer */
3384 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3385 ;
3386 if ((pSlice->mode_8x8_flags & 0x4) &&
3387 (pSlice->mode_8x8_flags & 0x2))
3388 use_direct_8x8 = 1;
3389 else
3390 use_direct_8x8 = 0;
3391
3392#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3393 colocate_adr_offset =
3394 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3395 ? 1 : 2) * 96;
3396 if (use_direct_8x8)
3397 colocate_adr_offset >>= 2;
3398
3399 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3400 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3401 colocate_adr_offset, pSlice->first_mb_in_slice,
3402 colocate_adr_offset * pSlice->first_mb_in_slice);
3403
3404 colocate_adr_offset *= pSlice->first_mb_in_slice;
3405
3406 if ((pic->colocated_buf_index >= 0) &&
3407 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3408 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3409 ((p_H264_Dpb->colocated_buf_size *
3410 pic->colocated_buf_index)
3411 >> (use_direct_8x8 ? 2 : 0));
3412 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3413 p_H264_Dpb->colocated_mv_addr_end) {
3414 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3415 "Error, colocate buf is not enough, index is %d\n",
3416 pic->colocated_buf_index);
3417 ret = -3;
3418 }
3419 val = colocate_wr_adr + colocate_adr_offset;
3420 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3421 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3422 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3423 val, pSlice->first_mb_in_slice, pic->structure,
3424 colocate_adr_offset, pSlice->mode_8x8_flags,
3425 p_H264_Dpb->colocated_buf_size);
3426 } else {
3427 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3428 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3429 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3430 }
3431#else
3432 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3433 colocate_adr_offset =
3434 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3435 if (use_direct_8x8)
3436 colocate_adr_offset >>= 2;
3437
3438 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3439 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3440 colocate_adr_offset, pSlice->first_mb_in_slice,
3441 colocate_adr_offset * pSlice->first_mb_in_slice);
3442
3443 colocate_adr_offset *= pSlice->first_mb_in_slice;
3444
3445 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3446 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3447 (use_direct_8x8 ? 2 : 0));
3448
3449 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3450 p_H264_Dpb->colocated_mv_addr_end) {
3451 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3452 "Error, colocate buf is not enough, col buf index is %d\n",
3453 colocate_buf_index);
3454 ret = -4;
3455 }
3456 val = colocate_wr_adr + colocate_adr_offset;
3457 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3458 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3459 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3460 val, pSlice->first_mb_in_slice, pic->structure,
3461 colocate_adr_offset, pSlice->mode_8x8_flags,
3462 p_H264_Dpb->colocated_buf_size);
3463#endif
3464 if (pSlice->listXsize[1] > 0) {
3465 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3466 /* H264_CO_MB_RD_ADDR[bit 31:30],
3467 * original picture structure of L1[0],
3468 * 00 - top field, 01 - bottom field,
3469 * 10 - frame, 11 - mbaff frame
3470 */
3471 int l10_structure;
3472 int cur_colocate_ref_type;
3473 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3474 * 0 - top, 1 - bot
3475 */
3476 unsigned int val;
3477#ifdef ERROR_CHECK
3478 if (colocate_pic == NULL) {
3479 hw->data_flag |= ERROR_FLAG;
3480 pic->data_flag |= ERROR_FLAG;
3481 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3482 return -5;
3483 }
3484 if (colocate_pic->data_flag & ERROR_FLAG) {
3485 pic->data_flag |= ERROR_FLAG;
3486 hw->data_flag |= ERROR_FLAG;
3487 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3488 }
3489 if (colocate_pic->data_flag & NULL_FLAG)
3490 hw->data_flag |= NULL_FLAG;
3491#endif
3492
3493 if (colocate_pic->mb_aff_frame_flag)
3494 l10_structure = 3;
3495 else {
3496 if (colocate_pic->coded_frame)
3497 l10_structure = 2;
3498 else
3499 l10_structure = (colocate_pic->structure ==
3500 BOTTOM_FIELD) ? 1 : 0;
3501 }
3502#if 0
3503 /*case0016, p16,
3504 *cur_colocate_ref_type should be configured base on current pic
3505 */
3506 if (pic->structure == FRAME &&
3507 pic->mb_aff_frame_flag)
3508 cur_colocate_ref_type = 0;
3509 else if (pic->structure == BOTTOM_FIELD)
3510 cur_colocate_ref_type = 1;
3511 else
3512 cur_colocate_ref_type = 0;
3513#else
3514 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3515 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3516 pic->mb_aff_frame_flag,
3517 pic->structure,
3518 pic->coded_frame);
3519 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3520 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3521 colocate_pic->mb_aff_frame_flag,
3522 colocate_pic->structure,
3523 colocate_pic->coded_frame);
3524 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3525 cur_colocate_ref_type =
3526 (abs(pic->poc - colocate_pic->top_poc)
3527 < abs(pic->poc -
3528 colocate_pic->bottom_poc)) ? 0 : 1;
3529 } else
3530 cur_colocate_ref_type =
3531 (colocate_pic->structure
3532 == BOTTOM_FIELD) ? 1 : 0;
3533#endif
3534
3535#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3536 if ((colocate_pic->colocated_buf_index >= 0) &&
3537 (colocate_pic->colocated_buf_index <
3538 p_H264_Dpb->colocated_buf_count)) {
3539 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3540 ((p_H264_Dpb->colocated_buf_size *
3541 colocate_pic->colocated_buf_index)
3542 >> (use_direct_8x8 ? 2 : 0));
3543 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3544 p_H264_Dpb->colocated_mv_addr_end) {
3545 dpb_print(DECODE_ID(hw),
3546 PRINT_FLAG_ERROR,
3547 "Error, colocate buf is not enough, index is %d\n",
3548 colocate_pic->colocated_buf_index);
3549 ret = -6;
3550 }
3551 /* bit 31:30 -- L1[0] picture coding structure,
3552 * 00 - top field, 01 - bottom field,
3553 * 10 - frame, 11 - mbaff frame
3554 * bit 29 - L1[0] top/bot for B field pciture,
3555 * 0 - top, 1 - bot
3556 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3557 * -- only used for B Picture Direct mode
3558 * [2:0] will set to 3'b000
3559 */
3560 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3561 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3562 (l10_structure << 30) |
3563 (cur_colocate_ref_type << 29);
3564 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3565 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3566 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3567 colocate_pic->colocated_buf_index,
3568 val, colocate_rd_adr + colocate_adr_offset,
3569 colocate_pic->structure,
3570 colocate_pic->mb_aff_frame_flag);
3571 } else {
3572 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3573 "Error, reference pic has no colocated buf\n");
3574 ret = -7;
3575 }
3576#else
3577 colocate_buf_index =
3578 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3579 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3580 ((p_H264_Dpb->colocated_buf_size *
3581 colocate_buf_index)
3582 >> (use_direct_8x8 ? 2 : 0));
3583 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3584 p_H264_Dpb->colocated_mv_addr_end) {
3585 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3586 "Error, colocate buf is not enough, col buf index is %d\n",
3587 colocate_buf_index);
3588 ret = -8;
3589 }
3590 /* bit 31:30 -- L1[0] picture coding structure,
3591 * 00 - top field, 01 - bottom field,
3592 * 10 - frame, 11 - mbaff frame
3593 * bit 29 - L1[0] top/bot for B field pciture,
3594 * 0 - top, 1 - bot
3595 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3596 * -- only used for B Picture Direct mode
3597 * [2:0] will set to 3'b000
3598 */
3599 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3600 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3601 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3602 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3603 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3604 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3605 val, colocate_pic->structure,
3606 colocate_pic->mb_aff_frame_flag);
3607#endif
3608 }
3609 return ret;
3610}
3611
3612static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3613{
3614 unsigned long flags;
3615 struct vdec_s *vdec = op_arg;
3616 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3617
3618 spin_lock_irqsave(&hw->lock, flags);
3619
3620 states->vf_pool_size = VF_POOL_SIZE;
3621 states->buf_free_num = kfifo_len(&hw->newframe_q);
3622 states->buf_avail_num = kfifo_len(&hw->display_q);
3623
3624 spin_unlock_irqrestore(&hw->lock, flags);
3625
3626 return 0;
3627}
3628
3629static struct vframe_s *vh264_vf_peek(void *op_arg)
3630{
3631 struct vframe_s *vf[2] = {0, 0};
3632 struct vdec_s *vdec = op_arg;
3633 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3634
3635 if (!hw)
3636 return NULL;
3637
3638 if (force_disp_bufspec_num & 0x100) {
3639 if (force_disp_bufspec_num & 0x200)
3640 return NULL;
3641 return &hw->vframe_dummy;
3642 }
3643
3644 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3645 if (vf[1]) {
3646 vf[0]->next_vf_pts_valid = true;
3647 vf[0]->next_vf_pts = vf[1]->pts;
3648 } else
3649 vf[0]->next_vf_pts_valid = false;
3650 return vf[0];
3651 }
3652
3653 return NULL;
3654}
3655
3656static struct vframe_s *vh264_vf_get(void *op_arg)
3657{
3658 struct vframe_s *vf;
3659 struct vdec_s *vdec = op_arg;
3660 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3661
3662 if (!hw)
3663 return NULL;
3664
3665 if (force_disp_bufspec_num & 0x100) {
3666 int buffer_index = force_disp_bufspec_num & 0xff;
3667 if (force_disp_bufspec_num & 0x200)
3668 return NULL;
3669
3670 vf = &hw->vframe_dummy;
3671 vf->duration_pulldown = 0;
3672 vf->pts = 0;
3673 vf->pts_us64 = 0;
3674 set_frame_info(hw, vf, buffer_index);
3675 vf->flag = 0;
3676 if (hw->mmu_enable) {
3677 if (hw->double_write_mode & 0x10) {
3678 /* double write only */
3679 vf->compBodyAddr = 0;
3680 vf->compHeadAddr = 0;
3681 } else {
3682 /*head adr*/
3683 vf->compHeadAddr =
3684 hw->buffer_spec[buffer_index].alloc_header_addr;
3685 /*body adr*/
3686 vf->compBodyAddr = 0;
3687 vf->canvas0Addr = vf->canvas1Addr = 0;
3688 }
3689
3690 vf->type = VIDTYPE_SCATTER;
3691
3692 if (hw->double_write_mode) {
3693 vf->type |= VIDTYPE_PROGRESSIVE
3694 | VIDTYPE_VIU_FIELD;
3695 vf->type |= VIDTYPE_VIU_NV21;
3696 if (hw->double_write_mode == 3)
3697 vf->type |= VIDTYPE_COMPRESS;
3698
3699 vf->canvas0Addr = vf->canvas1Addr = -1;
3700 vf->plane_num = 2;
3701 vf->canvas0_config[0] =
3702 hw->buffer_spec[buffer_index].
3703 canvas_config[0];
3704 vf->canvas0_config[1] =
3705 hw->buffer_spec[buffer_index].
3706 canvas_config[1];
3707
3708 vf->canvas1_config[0] =
3709 hw->buffer_spec[buffer_index].
3710 canvas_config[0];
3711 vf->canvas1_config[1] =
3712 hw->buffer_spec[buffer_index].
3713 canvas_config[1];
3714 } else {
3715 vf->type |=
3716 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3717 vf->canvas0Addr = vf->canvas1Addr = 0;
3718 }
3719 vf->bitdepth =
3720 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3721
3722 vf->compWidth = hw->frame_width;
3723 vf->compHeight = hw->frame_height;
3724
3725 if (hw->double_write_mode) {
3726 vf->width = hw->frame_width /
3727 get_double_write_ratio(hw);
3728 vf->height = hw->frame_height /
3729 get_double_write_ratio(hw);
3730 }
3731 } else {
3732 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3733 VIDTYPE_VIU_NV21;
3734 vf->canvas0Addr = vf->canvas1Addr =
3735 spec2canvas(&hw->buffer_spec[buffer_index]);
3736 }
3737
3738 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3739 hw->bmmu_box, buffer_index);*/
3740 update_vf_memhandle(hw, vf, buffer_index);
3741 force_disp_bufspec_num |= 0x200;
3742 return vf;
3743 }
3744
3745 if (kfifo_get(&hw->display_q, &vf)) {
3746 int time = jiffies;
3747 unsigned int frame_interval =
3748 1000*(time - hw->last_frame_time)/HZ;
3749 struct vframe_s *next_vf;
3750 if (dpb_is_debug(DECODE_ID(hw),
3751 PRINT_FLAG_VDEC_DETAIL)) {
3752 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3753 int frame_index = FRAME_INDEX(vf->index);
3754 if (frame_index < 0 ||
3755 frame_index >= DPB_SIZE_MAX) {
3756 dpb_print(DECODE_ID(hw), 0,
3757 "%s vf index 0x%x error\r\n",
3758 __func__, vf->index);
3759 } else {
3760 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3761 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3762 __func__, BUFSPEC_INDEX(vf->index), vf,
3763 p_H264_Dpb->mFrameStore[frame_index].poc,
3764 vf->duration, vf->pts, frame_interval);
3765 }
3766 }
3767 if (hw->last_frame_time > 0) {
3768 if (frame_interval >
3769 max_get_frame_interval[DECODE_ID(hw)])
3770 max_get_frame_interval[DECODE_ID(hw)]
3771 = frame_interval;
3772 }
3773 hw->last_frame_time = time;
3774 hw->vf_get_count++;
3775 if (kfifo_peek(&hw->display_q, &next_vf)) {
3776 vf->next_vf_pts_valid = true;
3777 vf->next_vf_pts = next_vf->pts;
3778 } else
3779 vf->next_vf_pts_valid = false;
3780 return vf;
3781 }
3782
3783 return NULL;
3784}
3785
3786static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3787{
3788 struct vdec_s *vdec = op_arg;
3789 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3790 int buf_spec_num;
3791 int frame_index;
3792
3793 if (vf == (&hw->vframe_dummy))
3794 return;
3795 if (vf->index == -1) {
3796 dpb_print(DECODE_ID(hw), 0,
3797 "Warning: %s vf %p invalid index\r\n",
3798 __func__, vf);
3799 return;
3800 }
3801 frame_index = FRAME_INDEX(vf->index);
3802 buf_spec_num = BUFSPEC_INDEX(vf->index);
3803 if (frame_index < 0 ||
3804 frame_index >= DPB_SIZE_MAX ||
3805 buf_spec_num < 0 ||
3806 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3807 dpb_print(DECODE_ID(hw), 0,
3808 "%s vf index 0x%x error\r\n",
3809 __func__, vf->index);
3810 return;
3811 }
3812 /*get_buf_spec_idx_by_canvas_config(hw,
3813 &vf->canvas0_config[0]);*/
3814 if (hw->buffer_spec[buf_spec_num].used == 2) {
3815 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3816 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3817 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3818 __func__, vf, frame_index,
3819 p_H264_Dpb->mFrameStore[frame_index].poc,
3820 buf_spec_num,
3821 hw->buffer_spec[buf_spec_num].used,
3822 hw->buffer_spec[buf_spec_num].vf_ref);
3823 hw->buffer_spec[buf_spec_num].vf_ref--;
3824 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3825 set_frame_output_flag(&hw->dpb, frame_index);
3826 } else {
3827 unsigned long flags;
3828 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3829 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3830 __func__, vf, buf_spec_num,
3831 hw->buffer_spec[buf_spec_num].used,
3832 hw->buffer_spec[buf_spec_num].vf_ref);
3833 spin_lock_irqsave(&hw->bufspec_lock, flags);
3834 hw->buffer_spec[buf_spec_num].vf_ref--;
3835 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3836 if (hw->buffer_spec[buf_spec_num].used == 3)
3837 hw->buffer_spec[buf_spec_num].used = 4;
3838 else if (hw->buffer_spec[buf_spec_num].used == 5)
3839 hw->buffer_spec[buf_spec_num].used = 0;
3840 }
3841 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3842 if (dpb_is_debug(DECODE_ID(hw),
3843 PRINT_FLAG_DUMP_BUFSPEC))
3844 dump_bufspec(hw, __func__);
3845
3846 }
3847
3848 hw->vf_put_count++;
3849 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3850
3851#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3852 if (hw->buffer_empty_flag)
3853 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3854}
3855
3856static int vh264_event_cb(int type, void *data, void *op_arg)
3857{
3858 unsigned long flags;
3859 struct vdec_s *vdec = op_arg;
3860 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3861
3862 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3863 struct provider_aux_req_s *req =
3864 (struct provider_aux_req_s *)data;
3865 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3866 spin_lock_irqsave(&hw->lock, flags);
3867 req->aux_buf = NULL;
3868 req->aux_size = 0;
3869 if (buf_spec_num >= 0 &&
3870 buf_spec_num < BUFSPEC_POOL_SIZE &&
3871 is_buf_spec_in_disp_q(hw, buf_spec_num)
3872 ) {
3873 req->aux_buf =
3874 hw->buffer_spec[buf_spec_num].aux_data_buf;
3875 req->aux_size =
3876 hw->buffer_spec[buf_spec_num].aux_data_size;
3877#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3878 req->dv_enhance_exist =
3879 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3880#else
3881 req->dv_enhance_exist = 0;
3882#endif
3883 }
3884 spin_unlock_irqrestore(&hw->lock, flags);
3885
3886 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3887 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3888 __func__, type, buf_spec_num, req->aux_size);
3889 }
3890
3891 return 0;
3892}
3893
3894static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3895 u32 index)
3896{
3897 struct canvas_config_s *p_canvas_config;
3898 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3899 force_rate_framebase : force_rate_streambase;
3900 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3901 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3902 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3903
3904 /* signal_type */
3905 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3906 vf->signal_type = hw->video_signal_from_vui;
3907 if (hw->is_used_v4l) {
3908 struct aml_vdec_hdr_infos hdr;
3909 struct aml_vcodec_ctx *ctx =
3910 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3911
3912 memset(&hdr, 0, sizeof(hdr));
3913 hdr.signal_type = hw->video_signal_from_vui;
3914 vdec_v4l_set_hdr_infos(ctx, &hdr);
3915 }
3916 } else
3917 vf->signal_type = 0;
3918
3919 vf->width = hw->frame_width;
3920 vf->height = hw->frame_height;
3921 if (force_rate) {
3922 if (force_rate == -1)
3923 vf->duration = 0;
3924 else
3925 vf->duration = 96000/force_rate;
3926 } else
3927 vf->duration = hw->frame_dur;
3928 vf->ratio_control =
3929 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3930 DISP_RATIO_ASPECT_RATIO_BIT;
3931 vf->orientation = hw->vh264_rotation;
3932
3933 if (hw->mmu_enable)
3934 return;
3935
3936 vf->canvas0Addr = vf->canvas1Addr = -1;
3937#ifdef NV21
3938 vf->plane_num = 2;
3939#else
3940 vf->plane_num = 3;
3941#endif
3942
3943 if (IS_VDEC_DW(hw)) {
3944 vf->width = (hw->frame_width /2);
3945 if (IS_VDEC_DW(hw) == 2)
3946 vf->height = (hw->frame_height /2);
3947 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3948 } else
3949 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3950
3951 vf->canvas0_config[0] = p_canvas_config[0];
3952 vf->canvas0_config[1] = p_canvas_config[1];
3953#ifndef NV21
3954 vf->canvas0_config[2] = p_canvas_config[2];
3955#endif
3956 vf->canvas1_config[0] = p_canvas_config[0];
3957 vf->canvas1_config[1] = p_canvas_config[1];
3958#ifndef NV21
3959 vf->canvas1_config[2] = p_canvas_config[2];
3960#endif
3961}
3962
3963static void get_picture_qos_info(struct StorablePicture *picture)
3964{
3965 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3966 unsigned char a[3];
3967 unsigned char i, j, t;
3968 unsigned long data;
3969
3970 get_random_bytes(&data, sizeof(unsigned long));
3971 if (picture->slice_type == I_SLICE)
3972 data = 0;
3973 a[0] = data & 0xff;
3974 a[1] = (data >> 8) & 0xff;
3975 a[2] = (data >> 16) & 0xff;
3976
3977 for (i = 0; i < 3; i++)
3978 for (j = i+1; j < 3; j++) {
3979 if (a[j] < a[i]) {
3980 t = a[j];
3981 a[j] = a[i];
3982 a[i] = t;
3983 } else if (a[j] == a[i]) {
3984 a[i]++;
3985 t = a[j];
3986 a[j] = a[i];
3987 a[i] = t;
3988 }
3989 }
3990 picture->max_mv = a[2];
3991 picture->avg_mv = a[1];
3992 picture->min_mv = a[0];
3993 /*
3994 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3995 data, a[0], a[1], a[2]);
3996 */
3997
3998 get_random_bytes(&data, sizeof(unsigned long));
3999 a[0] = data & 0x1f;
4000 a[1] = (data >> 8) & 0x3f;
4001 a[2] = (data >> 16) & 0x7f;
4002
4003 for (i = 0; i < 3; i++)
4004 for (j = i+1; j < 3; j++) {
4005 if (a[j] < a[i]) {
4006 t = a[j];
4007 a[j] = a[i];
4008 a[i] = t;
4009 } else if (a[j] == a[i]) {
4010 a[i]++;
4011 t = a[j];
4012 a[j] = a[i];
4013 a[i] = t;
4014 }
4015 }
4016 picture->max_qp = a[2];
4017 picture->avg_qp = a[1];
4018 picture->min_qp = a[0];
4019 /*
4020 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4021 data, a[0], a[1], a[2]);
4022 */
4023
4024 get_random_bytes(&data, sizeof(unsigned long));
4025 a[0] = data & 0x1f;
4026 a[1] = (data >> 8) & 0x3f;
4027 a[2] = (data >> 16) & 0x7f;
4028
4029 for (i = 0; i < 3; i++)
4030 for (j = i+1; j < 3; j++) {
4031 if (a[j] < a[i]) {
4032 t = a[j];
4033 a[j] = a[i];
4034 a[i] = t;
4035 } else if (a[j] == a[i]) {
4036 a[i]++;
4037 t = a[j];
4038 a[j] = a[i];
4039 a[i] = t;
4040 }
4041 }
4042 picture->max_skip = a[2];
4043 picture->avg_skip = a[1];
4044 picture->min_skip = a[0];
4045
4046
4047 /*
4048 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4049 data,a[0], a[1], a[2]);
4050 */
4051 } else {
4052 uint32_t blk88_y_count;
4053 uint32_t blk88_c_count;
4054 uint32_t blk22_mv_count;
4055 uint32_t rdata32;
4056 int32_t mv_hi;
4057 int32_t mv_lo;
4058 uint32_t rdata32_l;
4059 uint32_t mvx_L0_hi;
4060 uint32_t mvy_L0_hi;
4061 uint32_t mvx_L1_hi;
4062 uint32_t mvy_L1_hi;
4063 int64_t value;
4064 uint64_t temp_value;
4065/*
4066#define DEBUG_QOS
4067*/
4068#ifdef DEBUG_QOS
4069 int pic_number = picture->poc;
4070#endif
4071
4072 picture->max_mv = 0;
4073 picture->avg_mv = 0;
4074 picture->min_mv = 0;
4075
4076 picture->max_skip = 0;
4077 picture->avg_skip = 0;
4078 picture->min_skip = 0;
4079
4080 picture->max_qp = 0;
4081 picture->avg_qp = 0;
4082 picture->min_qp = 0;
4083
4084
4085
4086
4087
4088 /* set rd_idx to 0 */
4089 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4090 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4091 if (blk88_y_count == 0) {
4092#ifdef DEBUG_QOS
4093 pr_info(" [Picture %d Quality] NO Data yet.\n",
4094 pic_number);
4095#endif
4096 /* reset all counts */
4097 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4098 return;
4099 }
4100 /* qp_y_sum */
4101 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4102#ifdef DEBUG_QOS
4103 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4104 pic_number, rdata32/blk88_y_count,
4105 rdata32, blk88_y_count);
4106#endif
4107 picture->avg_qp = rdata32/blk88_y_count;
4108 /* intra_y_count */
4109 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4110#ifdef DEBUG_QOS
4111 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4112 pic_number, rdata32*100/blk88_y_count,
4113 '%', rdata32);
4114#endif
4115 /* skipped_y_count */
4116 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4117#ifdef DEBUG_QOS
4118 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4119 pic_number, rdata32*100/blk88_y_count,
4120 '%', rdata32);
4121#endif
4122 picture->avg_skip = rdata32*100/blk88_y_count;
4123 /* coeff_non_zero_y_count */
4124 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4125#ifdef DEBUG_QOS
4126 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4127 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4128 '%', rdata32);
4129#endif
4130 /* blk66_c_count */
4131 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4132 if (blk88_c_count == 0) {
4133#ifdef DEBUG_QOS
4134 pr_info(" [Picture %d Quality] NO Data yet.\n",
4135 pic_number);
4136#endif
4137 /* reset all counts */
4138 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4139 return;
4140 }
4141 /* qp_c_sum */
4142 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4143#ifdef DEBUG_QOS
4144 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4145 pic_number, rdata32/blk88_c_count,
4146 rdata32, blk88_c_count);
4147#endif
4148 /* intra_c_count */
4149 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4150#ifdef DEBUG_QOS
4151 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4152 pic_number, rdata32*100/blk88_c_count,
4153 '%', rdata32);
4154#endif
4155 /* skipped_cu_c_count */
4156 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4157#ifdef DEBUG_QOS
4158 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4159 pic_number, rdata32*100/blk88_c_count,
4160 '%', rdata32);
4161#endif
4162 /* coeff_non_zero_c_count */
4163 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4164#ifdef DEBUG_QOS
4165 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4166 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4167 '%', rdata32);
4168#endif
4169
4170 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4171 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4172 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4173#ifdef DEBUG_QOS
4174 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4175 pic_number, (rdata32>>0)&0xff);
4176#endif
4177 picture->min_qp = (rdata32>>0)&0xff;
4178
4179#ifdef DEBUG_QOS
4180 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4181 pic_number, (rdata32>>8)&0xff);
4182#endif
4183 picture->max_qp = (rdata32>>8)&0xff;
4184
4185#ifdef DEBUG_QOS
4186 pr_info(" [Picture %d Quality] C QP min : %d\n",
4187 pic_number, (rdata32>>16)&0xff);
4188 pr_info(" [Picture %d Quality] C QP max : %d\n",
4189 pic_number, (rdata32>>24)&0xff);
4190#endif
4191
4192 /* blk22_mv_count */
4193 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4194 if (blk22_mv_count == 0) {
4195#ifdef DEBUG_QOS
4196 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4197 pic_number);
4198#endif
4199 /* reset all counts */
4200 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4201 return;
4202 }
4203 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4204 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4205 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4206 /* should all be 0x00 or 0xff */
4207#ifdef DEBUG_QOS
4208 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4209 pic_number, rdata32);
4210#endif
4211 mvx_L0_hi = ((rdata32>>0)&0xff);
4212 mvy_L0_hi = ((rdata32>>8)&0xff);
4213 mvx_L1_hi = ((rdata32>>16)&0xff);
4214 mvy_L1_hi = ((rdata32>>24)&0xff);
4215
4216 /* mvx_L0_count[31:0] */
4217 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4218 temp_value = mvx_L0_hi;
4219 temp_value = (temp_value << 32) | rdata32_l;
4220
4221 if (mvx_L0_hi & 0x80)
4222 value = 0xFFFFFFF000000000 | temp_value;
4223 else
4224 value = temp_value;
4225 value = div_s64(value, blk22_mv_count);
4226#ifdef DEBUG_QOS
4227 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4228 pic_number, (int)(value),
4229 value, blk22_mv_count);
4230#endif
4231 picture->avg_mv = value;
4232
4233 /* mvy_L0_count[31:0] */
4234 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4235 temp_value = mvy_L0_hi;
4236 temp_value = (temp_value << 32) | rdata32_l;
4237
4238 if (mvy_L0_hi & 0x80)
4239 value = 0xFFFFFFF000000000 | temp_value;
4240 else
4241 value = temp_value;
4242#ifdef DEBUG_QOS
4243 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4244 pic_number, rdata32_l/blk22_mv_count,
4245 value, blk22_mv_count);
4246#endif
4247
4248 /* mvx_L1_count[31:0] */
4249 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4250 temp_value = mvx_L1_hi;
4251 temp_value = (temp_value << 32) | rdata32_l;
4252 if (mvx_L1_hi & 0x80)
4253 value = 0xFFFFFFF000000000 | temp_value;
4254 else
4255 value = temp_value;
4256#ifdef DEBUG_QOS
4257 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4258 pic_number, rdata32_l/blk22_mv_count,
4259 value, blk22_mv_count);
4260#endif
4261
4262 /* mvy_L1_count[31:0] */
4263 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4264 temp_value = mvy_L1_hi;
4265 temp_value = (temp_value << 32) | rdata32_l;
4266 if (mvy_L1_hi & 0x80)
4267 value = 0xFFFFFFF000000000 | temp_value;
4268 else
4269 value = temp_value;
4270#ifdef DEBUG_QOS
4271 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4272 pic_number, rdata32_l/blk22_mv_count,
4273 value, blk22_mv_count);
4274#endif
4275
4276 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4277 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4278 mv_hi = (rdata32>>16)&0xffff;
4279 if (mv_hi & 0x8000)
4280 mv_hi = 0x8000 - mv_hi;
4281#ifdef DEBUG_QOS
4282 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4283 pic_number, mv_hi);
4284#endif
4285 picture->max_mv = mv_hi;
4286
4287 mv_lo = (rdata32>>0)&0xffff;
4288 if (mv_lo & 0x8000)
4289 mv_lo = 0x8000 - mv_lo;
4290#ifdef DEBUG_QOS
4291 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4292 pic_number, mv_lo);
4293#endif
4294 picture->min_mv = mv_lo;
4295
4296 /* {mvy_L0_max, mvy_L0_min} */
4297 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4298 mv_hi = (rdata32>>16)&0xffff;
4299 if (mv_hi & 0x8000)
4300 mv_hi = 0x8000 - mv_hi;
4301#ifdef DEBUG_QOS
4302 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4303 pic_number, mv_hi);
4304#endif
4305
4306 mv_lo = (rdata32>>0)&0xffff;
4307 if (mv_lo & 0x8000)
4308 mv_lo = 0x8000 - mv_lo;
4309#ifdef DEBUG_QOS
4310 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4311 pic_number, mv_lo);
4312#endif
4313
4314 /* {mvx_L1_max, mvx_L1_min} */
4315 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4316 mv_hi = (rdata32>>16)&0xffff;
4317 if (mv_hi & 0x8000)
4318 mv_hi = 0x8000 - mv_hi;
4319#ifdef DEBUG_QOS
4320 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4321 pic_number, mv_hi);
4322#endif
4323
4324 mv_lo = (rdata32>>0)&0xffff;
4325 if (mv_lo & 0x8000)
4326 mv_lo = 0x8000 - mv_lo;
4327#ifdef DEBUG_QOS
4328 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4329 pic_number, mv_lo);
4330#endif
4331
4332 /* {mvy_L1_max, mvy_L1_min} */
4333 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4334 mv_hi = (rdata32>>16)&0xffff;
4335 if (mv_hi & 0x8000)
4336 mv_hi = 0x8000 - mv_hi;
4337#ifdef DEBUG_QOS
4338 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4339 pic_number, mv_hi);
4340#endif
4341 mv_lo = (rdata32>>0)&0xffff;
4342 if (mv_lo & 0x8000)
4343 mv_lo = 0x8000 - mv_lo;
4344#ifdef DEBUG_QOS
4345 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4346 pic_number, mv_lo);
4347#endif
4348
4349 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4350#ifdef DEBUG_QOS
4351 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4352 pic_number, rdata32);
4353#endif
4354 /* reset all counts */
4355 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4356 }
4357}
4358
4359static int get_max_dec_frame_buf_size(int level_idc,
4360 int max_reference_frame_num, int mb_width,
4361 int mb_height)
4362{
4363 int pic_size = mb_width * mb_height * 384;
4364
4365 int size = 0;
4366
4367 switch (level_idc) {
4368 case 9:
4369 size = 152064;
4370 break;
4371 case 10:
4372 size = 152064;
4373 break;
4374 case 11:
4375 size = 345600;
4376 break;
4377 case 12:
4378 size = 912384;
4379 break;
4380 case 13:
4381 size = 912384;
4382 break;
4383 case 20:
4384 size = 912384;
4385 break;
4386 case 21:
4387 size = 1824768;
4388 break;
4389 case 22:
4390 size = 3110400;
4391 break;
4392 case 30:
4393 size = 3110400;
4394 break;
4395 case 31:
4396 size = 6912000;
4397 break;
4398 case 32:
4399 size = 7864320;
4400 break;
4401 case 40:
4402 size = 12582912;
4403 break;
4404 case 41:
4405 size = 12582912;
4406 break;
4407 case 42:
4408 size = 13369344;
4409 break;
4410 case 50:
4411 size = 42393600;
4412 break;
4413 case 51:
4414 case 52:
4415 default:
4416 size = 70778880;
4417 break;
4418 }
4419
4420 size /= pic_size;
4421 size = size + 1; /* need one more buffer */
4422
4423 if (max_reference_frame_num > size)
4424 size = max_reference_frame_num;
4425 size = imin(size, 16);
4426
4427 return size;
4428}
4429
4430static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4431{
4432 int i, j;
4433
4434 if (hw->double_write_mode) {
4435 mutex_lock(&vmh264_mutex);
4436 if (hw->decode_pic_count == 0) {
4437 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4438 i = get_buf_spec_by_canvas_pos(hw, j);
4439 if (i >= 0)
4440 config_decode_canvas_ex(hw, i);
4441 }
4442 }
4443 mutex_unlock(&vmh264_mutex);
4444 }
4445}
4446
4447static int vh264_set_params(struct vdec_h264_hw_s *hw,
4448 u32 param1, u32 param2, u32 param3, u32 param4)
4449{
4450 int i, j;
4451 int mb_width, mb_total;
4452 int max_reference_size, level_idc;
4453 int mb_height = 0;
4454 unsigned long flags;
4455 /*int mb_mv_byte;*/
4456 struct vdec_s *vdec = hw_to_vdec(hw);
4457 u32 seq_info2;
4458 int ret = 0;
4459 int active_buffer_spec_num;
4460 unsigned int buf_size;
4461 unsigned int frame_mbs_only_flag;
4462 unsigned int chroma_format_idc, chroma444;
4463 unsigned int crop_infor, crop_bottom, crop_right;
4464 unsigned int used_reorder_dpb_size_margin
4465 = hw->reorder_dpb_size_margin;
4466 u8 *colocate_vaddr = NULL;
4467
4468#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4469 if (vdec->master || vdec->slave)
4470 used_reorder_dpb_size_margin =
4471 reorder_dpb_size_margin_dv;
4472#endif
4473 seq_info2 = param1;
4474 hw->seq_info = param2;
4475
4476 mb_width = seq_info2 & 0xff;
4477 mb_total = (seq_info2 >> 8) & 0xffff;
4478 if (!mb_width && mb_total) /*for 4k2k*/
4479 mb_width = 256;
4480 if (mb_width)
4481 mb_height = mb_total/mb_width;
4482 if (mb_width <= 0 || mb_height <= 0 ||
4483 is_oversize(mb_width << 4, mb_height << 4)) {
4484 dpb_print(DECODE_ID(hw), 0,
4485 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4486 seq_info2,
4487 mb_width,
4488 mb_height);
4489 return -1;
4490 }
4491
4492 if (seq_info2 != 0 &&
4493 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4494 hw->seq_info2 != 0
4495 ) /*picture size changed*/
4496 h264_reconfig(hw);
4497
4498 if (hw->config_bufmgr_done == 0) {
4499 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4500 u32 reg_val;
4501 hw->cfg_param1 = param1;
4502 hw->cfg_param2 = param2;
4503 hw->cfg_param3 = param3;
4504 hw->cfg_param4 = param4;
4505
4506 hw->seq_info2 = seq_info2 & (~0x80000000);
4507 dpb_print(DECODE_ID(hw), 0,
4508 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4509 seq_info2, hw->seq_info);
4510
4511 dpb_init_global(&hw->dpb,
4512 DECODE_ID(hw), 0, 0);
4513
4514 p_H264_Dpb->fast_output_enable = fast_output_enable;
4515 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4516
4517#if 1
4518 /*crop*/
4519 /* AV_SCRATCH_2
4520 bit 15: frame_mbs_only_flag
4521 bit 13-14: chroma_format_idc */
4522 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4523 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4524 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4525
4526 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4527 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4528 (2 - frame_mbs_only_flag) */
4529 crop_infor = param3;
4530 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4531 crop_right = ((crop_infor >> 16) & 0xff)
4532 >> (2 - frame_mbs_only_flag);
4533
4534 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4535 hw->frame_width = mb_width << 4;
4536 hw->frame_height = mb_height << 4;
4537 if (frame_mbs_only_flag) {
4538 hw->frame_height =
4539 hw->frame_height - (2 >> chroma444) *
4540 min(crop_bottom,
4541 (unsigned int)((8 << chroma444) - 1));
4542 hw->frame_width =
4543 hw->frame_width -
4544 (2 >> chroma444) * min(crop_right,
4545 (unsigned
4546 int)((8 << chroma444) - 1));
4547 } else {
4548 hw->frame_height =
4549 hw->frame_height - (4 >> chroma444) *
4550 min(crop_bottom,
4551 (unsigned int)((8 << chroma444)
4552 - 1));
4553 hw->frame_width =
4554 hw->frame_width -
4555 (4 >> chroma444) * min(crop_right,
4556 (unsigned int)((8 << chroma444) - 1));
4557 }
4558 dpb_print(DECODE_ID(hw), 0,
4559 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4560 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4561 dpb_print(DECODE_ID(hw), 0,
4562 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4563 mb_height, crop_right,
4564 hw->frame_width, mb_width);
4565
4566 if (hw->frame_height == 1088)
4567 hw->frame_height = 1080;
4568#endif
4569 if (!hw->mmu_enable) {
4570 mb_width = (mb_width+3) & 0xfffffffc;
4571 mb_height = (mb_height+3) & 0xfffffffc;
4572 }
4573 mb_total = mb_width * mb_height;
4574 hw->mb_width = mb_width;
4575 hw->mb_height = mb_height;
4576 hw->mb_total = mb_total;
4577 if (hw->mmu_enable)
4578 hevc_mcr_sao_global_hw_init(hw,
4579 (hw->mb_width << 4), (hw->mb_height << 4));
4580
4581 reg_val = param4;
4582 level_idc = reg_val & 0xff;
4583 max_reference_size = (reg_val >> 8) & 0xff;
4584 hw->dpb.origin_max_reference = max_reference_size;
4585 dpb_print(DECODE_ID(hw), 0,
4586 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4587 mb_height, mb_width, mb_total,
4588 level_idc, max_reference_size);
4589
4590
4591 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4592 hw->dpb.reorder_pic_num =
4593 get_max_dec_frame_buf_size(level_idc,
4594 max_reference_size, mb_width, mb_height);
4595
4596 dpb_print(DECODE_ID(hw), 0,
4597 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4598 hw->bitstream_restriction_flag,
4599 hw->max_dec_frame_buffering,
4600 hw->dpb.reorder_pic_num);
4601
4602 if ((hw->bitstream_restriction_flag) &&
4603 (hw->max_dec_frame_buffering <
4604 hw->dpb.reorder_pic_num)) {
4605 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4606 dpb_print(DECODE_ID(hw), 0,
4607 "set reorder_pic_num to %d\n",
4608 hw->dpb.reorder_pic_num);
4609 }
4610
4611 active_buffer_spec_num =
4612 hw->dpb.reorder_pic_num
4613 + used_reorder_dpb_size_margin;
4614 hw->max_reference_size =
4615 max_reference_size + reference_buf_margin;
4616
4617 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4618 active_buffer_spec_num = MAX_VF_BUF_NUM;
4619 hw->dpb.reorder_pic_num = active_buffer_spec_num
4620 - used_reorder_dpb_size_margin;
4621 }
4622 hw->dpb.mDPB.size = active_buffer_spec_num;
4623 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4624 hw->max_reference_size = MAX_VF_BUF_NUM;
4625 hw->dpb.max_reference_size = hw->max_reference_size;
4626
4627 if (hw->no_poc_reorder_flag)
4628 hw->dpb.reorder_pic_num = 1;
4629 dpb_print(DECODE_ID(hw), 0,
4630 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4631 __func__, active_buffer_spec_num,
4632 hw->dpb.reorder_pic_num,
4633 hw->max_reference_size);
4634
4635 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4636
4637 mutex_lock(&vmh264_mutex);
4638 if (!hw->mmu_enable) {
4639 config_buf_specs(vdec);
4640 i = get_buf_spec_by_canvas_pos(hw, 0);
4641
4642 if (hw->is_used_v4l) {
4643 if (i != -1) {
4644 pr_info("v4l: delay alloc the buffer.\n");
4645 }
4646 } else {
4647 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4648 config_decode_canvas(hw, i);
4649 else
4650 ret = -1;
4651 }
4652 } else {
4653 if (hw->double_write_mode) {
4654 config_buf_specs_ex(vdec);
4655 } else {
4656 spin_lock_irqsave(&hw->bufspec_lock, flags);
4657 for (i = 0, j = 0;
4658 j < active_buffer_spec_num
4659 && i < BUFSPEC_POOL_SIZE;
4660 i++) {
4661 if (hw->buffer_spec[i].used != -1)
4662 continue;
4663 hw->buffer_spec[i].used = 0;
4664 hw->buffer_spec[i].
4665 alloc_header_addr = 0;
4666 hw->buffer_spec[i].canvas_pos = j;
4667 j++;
4668 }
4669 spin_unlock_irqrestore(&hw->bufspec_lock,
4670 flags);
4671 }
4672 hevc_mcr_config_canv2axitbl(hw, 0);
4673 }
4674 mutex_unlock(&vmh264_mutex);
4675 if (dpb_is_debug(DECODE_ID(hw),
4676 PRINT_FLAG_DUMP_BUFSPEC))
4677 dump_bufspec(hw, __func__);
4678
4679#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4680 buf_size = PAGE_ALIGN(
4681 p_H264_Dpb->colocated_buf_size *
4682 active_buffer_spec_num);
4683#else
4684 buf_size = PAGE_ALIGN(
4685 p_H264_Dpb->colocated_buf_size *
4686 hw->max_reference_size);
4687#endif
4688
4689 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4690 buf_size, DRIVER_NAME,
4691 &hw->collocate_cma_alloc_addr) < 0)
4692 return -1;
4693 if (!vdec_secure(vdec)) {
4694 /* clear for some mosaic problem after reset bufmgr */
4695 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4696 if (colocate_vaddr != NULL) {
4697 memset(colocate_vaddr, 0, buf_size);
4698 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4699 codec_mm_unmap_phyaddr(colocate_vaddr);
4700 }
4701 }
4702
4703 hw->dpb.colocated_mv_addr_start =
4704 hw->collocate_cma_alloc_addr;
4705#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4706 hw->dpb.colocated_mv_addr_end =
4707 hw->dpb.colocated_mv_addr_start +
4708 (p_H264_Dpb->colocated_buf_size *
4709 active_buffer_spec_num);
4710#else
4711 hw->dpb.colocated_mv_addr_end =
4712 hw->dpb.colocated_mv_addr_start +
4713 (p_H264_Dpb->colocated_buf_size *
4714 hw->max_reference_size);
4715#endif
4716 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4717 "callocate cma, %lx, %x\n",
4718 hw->collocate_cma_alloc_addr,
4719 hw->dpb.colocated_mv_addr_start);
4720
4721 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4722 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4723 hw->dpb.colocated_mv_addr_start,
4724 hw->dpb.colocated_mv_addr_end);
4725 if (!hw->mmu_enable) {
4726 mutex_lock(&vmh264_mutex);
4727 if (ret >= 0 && hw->decode_pic_count == 0) {
4728 int buf_cnt;
4729 /* h264_reconfig: alloc later*/
4730 buf_cnt = hw->dpb.mDPB.size;
4731
4732 for (j = 1; j < buf_cnt; j++) {
4733 i = get_buf_spec_by_canvas_pos(hw, j);
4734
4735 if (hw->is_used_v4l) {
4736 pr_info("v4l: delay alloc the buffer.\n");
4737 break;
4738 } else if (alloc_one_buf_spec(hw, i) < 0)
4739 break;
4740
4741 config_decode_canvas(hw, i);
4742 }
4743 }
4744 mutex_unlock(&vmh264_mutex);
4745 } else {
4746 vh264_config_canvs_for_mmu(hw);
4747 }
4748
4749 hw->config_bufmgr_done = 1;
4750
4751 /*end of config_bufmgr_done */
4752 }
4753
4754 return ret;
4755}
4756
4757static void vui_config(struct vdec_h264_hw_s *hw)
4758{
4759 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4760 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4761 /*time*/
4762 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4763 hw->time_scale = p_H264_Dpb->time_scale;
4764 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4765
4766 hw->bitstream_restriction_flag =
4767 p_H264_Dpb->bitstream_restriction_flag;
4768 hw->num_reorder_frames =
4769 p_H264_Dpb->num_reorder_frames;
4770 hw->max_dec_frame_buffering =
4771 p_H264_Dpb->max_dec_frame_buffering;
4772
4773 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4774 "vui_config: pdb %d, %d, %d\n",
4775 p_H264_Dpb->bitstream_restriction_flag,
4776 p_H264_Dpb->num_reorder_frames,
4777 p_H264_Dpb->max_dec_frame_buffering);
4778
4779 hw->fixed_frame_rate_flag = 0;
4780 if (hw->timing_info_present_flag) {
4781 hw->fixed_frame_rate_flag =
4782 p_H264_Dpb->fixed_frame_rate_flag;
4783
4784 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4785 ((!hw->sync_outside) ||
4786 (!hw->frame_dur)))
4787 && hw->num_units_in_tick && hw->time_scale) {
4788 if (hw->use_idr_framerate ||
4789 hw->fixed_frame_rate_flag ||
4790 !hw->frame_dur ||
4791 !hw->duration_from_pts_done
4792 /*|| vh264_running*/) {
4793 u32 frame_dur_es =
4794 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4795 hw->time_scale);
4796 if (hw->frame_dur != frame_dur_es) {
4797 hw->h264_first_valid_pts_ready = false;
4798 hw->h264pts1 = 0;
4799 hw->h264pts2 = 0;
4800 hw->h264_pts_count = 0;
4801 hw->duration_from_pts_done = 0;
4802 fixed_frame_rate_mode =
4803 FIX_FRAME_RATE_OFF;
4804 hw->pts_duration = 0;
4805 hw->frame_dur = frame_dur_es;
4806 vdec_schedule_work(&hw->notify_work);
4807 dpb_print(DECODE_ID(hw),
4808 PRINT_FLAG_DEC_DETAIL,
4809 "frame_dur %d from timing_info\n",
4810 hw->frame_dur);
4811 }
4812
4813 /*hack to avoid use ES frame duration when
4814 *it's half of the rate from system info
4815 * sometimes the encoder is given a wrong
4816 * frame rate but the system side information
4817 * is more reliable
4818 *if ((frame_dur * 2) != frame_dur_es) {
4819 * frame_dur = frame_dur_es;
4820 *}
4821 */
4822 }
4823 }
4824 } else {
4825 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4826 "H.264: timing_info not present\n");
4827 }
4828
4829 /*aspect ratio*/
4830 aspect_ratio_info_present_flag =
4831 p_H264_Dpb->vui_status & 0x1;
4832 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4833
4834 if (aspect_ratio_info_present_flag) {
4835 if (aspect_ratio_idc == EXTEND_SAR) {
4836 hw->h264_ar = 0x3ff;
4837 hw->height_aspect_ratio =
4838 p_H264_Dpb->aspect_ratio_sar_height;
4839 hw->width_aspect_ratio =
4840 p_H264_Dpb->aspect_ratio_sar_width;
4841 } else {
4842 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4843 aspect_ratio_idc); */
4844
4845 switch (aspect_ratio_idc) {
4846 case 1:
4847 hw->h264_ar = 0x3ff;
4848 hw->height_aspect_ratio = 1;
4849 hw->width_aspect_ratio = 1;
4850 break;
4851 case 2:
4852 hw->h264_ar = 0x3ff;
4853 hw->height_aspect_ratio = 11;
4854 hw->width_aspect_ratio = 12;
4855 break;
4856 case 3:
4857 hw->h264_ar = 0x3ff;
4858 hw->height_aspect_ratio = 11;
4859 hw->width_aspect_ratio = 10;
4860 break;
4861 case 4:
4862 hw->h264_ar = 0x3ff;
4863 hw->height_aspect_ratio = 11;
4864 hw->width_aspect_ratio = 16;
4865 break;
4866 case 5:
4867 hw->h264_ar = 0x3ff;
4868 hw->height_aspect_ratio = 33;
4869 hw->width_aspect_ratio = 40;
4870 break;
4871 case 6:
4872 hw->h264_ar = 0x3ff;
4873 hw->height_aspect_ratio = 11;
4874 hw->width_aspect_ratio = 24;
4875 break;
4876 case 7:
4877 hw->h264_ar = 0x3ff;
4878 hw->height_aspect_ratio = 11;
4879 hw->width_aspect_ratio = 20;
4880 break;
4881 case 8:
4882 hw->h264_ar = 0x3ff;
4883 hw->height_aspect_ratio = 11;
4884 hw->width_aspect_ratio = 32;
4885 break;
4886 case 9:
4887 hw->h264_ar = 0x3ff;
4888 hw->height_aspect_ratio = 33;
4889 hw->width_aspect_ratio = 80;
4890 break;
4891 case 10:
4892 hw->h264_ar = 0x3ff;
4893 hw->height_aspect_ratio = 11;
4894 hw->width_aspect_ratio = 18;
4895 break;
4896 case 11:
4897 hw->h264_ar = 0x3ff;
4898 hw->height_aspect_ratio = 11;
4899 hw->width_aspect_ratio = 15;
4900 break;
4901 case 12:
4902 hw->h264_ar = 0x3ff;
4903 hw->height_aspect_ratio = 33;
4904 hw->width_aspect_ratio = 64;
4905 break;
4906 case 13:
4907 hw->h264_ar = 0x3ff;
4908 hw->height_aspect_ratio = 99;
4909 hw->width_aspect_ratio = 160;
4910 break;
4911 case 14:
4912 hw->h264_ar = 0x3ff;
4913 hw->height_aspect_ratio = 3;
4914 hw->width_aspect_ratio = 4;
4915 break;
4916 case 15:
4917 hw->h264_ar = 0x3ff;
4918 hw->height_aspect_ratio = 2;
4919 hw->width_aspect_ratio = 3;
4920 break;
4921 case 16:
4922 hw->h264_ar = 0x3ff;
4923 hw->height_aspect_ratio = 1;
4924 hw->width_aspect_ratio = 2;
4925 break;
4926 default:
4927 if (hw->vh264_ratio >> 16) {
4928 hw->h264_ar = (hw->frame_height *
4929 (hw->vh264_ratio & 0xffff) *
4930 0x100 +
4931 ((hw->vh264_ratio >> 16) *
4932 hw->frame_width / 2)) /
4933 ((hw->vh264_ratio >> 16) *
4934 hw->frame_width);
4935 hw->height_aspect_ratio = 1;
4936 hw->width_aspect_ratio = 1;
4937 } else {
4938 hw->h264_ar = 0x3ff;
4939 hw->height_aspect_ratio = 1;
4940 hw->width_aspect_ratio = 1;
4941 }
4942 break;
4943 }
4944 }
4945 } else {
4946 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4947 "v264dec: aspect_ratio not available from source\n");
4948 if (hw->vh264_ratio >> 16) {
4949 /* high 16 bit is width, low 16 bit is height */
4950 hw->h264_ar =
4951 ((hw->vh264_ratio & 0xffff) *
4952 hw->frame_height * 0x100 +
4953 (hw->vh264_ratio >> 16) *
4954 hw->frame_width / 2) /
4955 ((hw->vh264_ratio >> 16) *
4956 hw->frame_width);
4957 hw->height_aspect_ratio = 1;
4958 hw->width_aspect_ratio = 1;
4959 } else {
4960 hw->h264_ar = 0x3ff;
4961 hw->height_aspect_ratio = 1;
4962 hw->width_aspect_ratio = 1;
4963 }
4964 }
4965
4966 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4967 if (((hw->frame_dur == RATE_2397_FPS)
4968 && (dec_control
4969 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4970 || ((RATE_2997_FPS ==
4971 hw->frame_dur) &&
4972 (dec_control &
4973 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4974 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4975 "force fix frame rate\n");
4976 hw->fixed_frame_rate_flag = 0x40;
4977 }
4978 }
4979
4980 /*video_signal_from_vui: to do .. */
4981}
4982
4983static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4984{
4985 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4986
4987 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4988 if (error_proc_policy & 0x20) {
4989 if (!hw->is_used_v4l)
4990 hw->reset_bufmgr_flag = 1;
4991 }
4992}
4993
4994void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4995{
4996 struct vdec_h264_hw_s *hw =
4997 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4998
4999 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5000
5001 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5002 hw->reset_bufmgr_flag = 1;
5003}
5004
5005#ifdef CONSTRAIN_MAX_BUF_NUM
5006static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5007{
5008 int i;
5009 int count = 0;
5010 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5011 if (is_buf_spec_in_disp_q(hw, i) &&
5012 hw->buffer_spec[i].vf_ref > 0)
5013 count++;
5014 }
5015 return count;
5016}
5017
5018static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5019{
5020 int i;
5021 int count = 0;
5022 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5023 if (is_buf_spec_in_use(hw, i))
5024 count++;
5025 }
5026 return count;
5027}
5028#endif
5029
5030
5031static bool is_buffer_available(struct vdec_s *vdec)
5032{
5033 bool buffer_available = 1;
5034 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5035 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5036 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5037 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5038 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5039 ((p_H264_Dpb->mDPB.init_done) &&
5040 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5041 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5042 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5043 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5044 __func__,
5045 kfifo_len(&hw->newframe_q),
5046 have_free_buf_spec(vdec),
5047 p_H264_Dpb->mDPB.init_done,
5048 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5049 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5050 );
5051 buffer_available = 0;
5052 if (dpb_is_debug(DECODE_ID(hw),
5053 DEBUG_DISABLE_RUNREADY_RMBUF))
5054 return buffer_available;
5055
5056 if ((error_proc_policy & 0x4) &&
5057 (error_proc_policy & 0x8)) {
5058 if ((kfifo_len(&hw->display_q) <= 0) &&
5059 (p_H264_Dpb->mDPB.used_size ==
5060 p_H264_Dpb->mDPB.size) &&
5061 (p_Dpb->ref_frames_in_buffer >
5062 (imax(
5063 1, p_Dpb->num_ref_frames)
5064 - p_Dpb->ltref_frames_in_buffer +
5065 force_sliding_margin)))
5066 bufmgr_recover(hw);
5067 else
5068 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5069 } else if ((error_proc_policy & 0x4) &&
5070 (kfifo_len(&hw->display_q) <= 0) &&
5071 ((p_H264_Dpb->mDPB.used_size ==
5072 p_H264_Dpb->mDPB.size) ||
5073 (!have_free_buf_spec(vdec)))) {
5074 enum receviver_start_e state = RECEIVER_INACTIVE;
5075 if ((error_proc_policy & 0x10) &&
5076 vf_get_receiver(vdec->vf_provider_name)) {
5077 state =
5078 vf_notify_receiver(vdec->vf_provider_name,
5079 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5080 NULL);
5081 if ((state == RECEIVER_STATE_NULL)
5082 || (state == RECEIVER_STATE_NONE))
5083 state = RECEIVER_INACTIVE;
5084 }
5085 if (state == RECEIVER_INACTIVE)
5086 bufmgr_recover(hw);
5087 else
5088 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5089 } else if ((error_proc_policy & 0x8) &&
5090 (p_Dpb->ref_frames_in_buffer >
5091 (imax(
5092 1, p_Dpb->num_ref_frames)
5093 - p_Dpb->ltref_frames_in_buffer +
5094 force_sliding_margin)))
5095 bufmgr_recover(hw);
5096 else
5097 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5098
5099 if (hw->reset_bufmgr_flag == 1)
5100 buffer_available = 1;
5101 }
5102
5103 return buffer_available;
5104}
5105
5106#define AUX_TAG_SEI 0x2
5107
5108#define SEI_BUFFERING_PERIOD 0
5109#define SEI_PicTiming 1
5110#define SEI_USER_DATA 4
5111#define SEI_RECOVERY_POINT 6
5112
5113/*
5114 *************************************************************************
5115 * Function:Reads bits from the bitstream buffer
5116 * Input:
5117 byte buffer[]
5118 containing sei message data bits
5119 int totbitoffset
5120 bit offset from start of partition
5121 int bytecount
5122 total bytes in bitstream
5123 int numbits
5124 number of bits to read
5125 * Output:
5126 int *info
5127 * Return:
5128 -1: failed
5129 > 0: the count of bit read
5130 * Attention:
5131 *************************************************************************
5132 */
5133
5134static int get_bits(unsigned char buffer[],
5135 int totbitoffset,
5136 int *info,
5137 int bytecount,
5138 int numbits)
5139{
5140 register int inf;
5141 long byteoffset;
5142 int bitoffset;
5143
5144 int bitcounter = numbits;
5145
5146 byteoffset = totbitoffset / 8;
5147 bitoffset = 7 - (totbitoffset % 8);
5148
5149 inf = 0;
5150 while (numbits) {
5151 inf <<= 1;
5152 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5153 numbits--;
5154 bitoffset--;
5155 if (bitoffset < 0) {
5156 byteoffset++;
5157 bitoffset += 8;
5158 if (byteoffset > bytecount)
5159 return -1;
5160 }
5161 }
5162
5163 *info = inf;
5164
5165
5166 return bitcounter;
5167}
5168
5169static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5170 u8 *sei_data_buf,
5171 u8 *sei_data_buf_end)
5172{
5173 int payload_type;
5174 int payload_size;
5175 u8 *p_sei;
5176 int temp = 0;
5177 int bit_offset;
5178 int read_size;
5179 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5180
5181 p_sei = sei_data_buf;
5182 read_size = 0;
5183 payload_type = 0;
5184 do {
5185 if (p_sei >= sei_data_buf_end)
5186 return read_size;
5187
5188 payload_type += *p_sei;
5189 read_size++;
5190 } while (*p_sei++ == 255);
5191
5192
5193 payload_size = 0;
5194 do {
5195 if (p_sei >= sei_data_buf_end)
5196 return read_size;
5197
5198 payload_size += *p_sei;
5199 read_size++;
5200 } while (*p_sei++ == 255);
5201
5202
5203 if (p_sei + payload_size > sei_data_buf_end) {
5204 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5205 "%s: payload_type = %d, payload_size = %d is over\n",
5206 __func__, payload_type, payload_size);
5207 return read_size;
5208 }
5209 bit_offset = 0;
5210
5211 if (payload_size <= 0) {
5212 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5213 "%s warning: this is a null sei message for payload_type = %d\n",
5214 __func__, payload_type);
5215 return read_size;
5216 }
5217 switch (payload_type) {
5218 case SEI_BUFFERING_PERIOD:
5219 break;
5220 case SEI_PicTiming:
5221 if (p_H264_Dpb->vui_status & 0xc) {
5222 int cpb_removal_delay;
5223 int dpb_output_delay;
5224 u32 delay_len;
5225
5226 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5227 cpb_removal_delay
5228 = (delay_len & 0x1F) + 1;
5229 dpb_output_delay
5230 = ((delay_len >> 5) & 0x1F) + 1;
5231
5232 get_bits(p_sei, bit_offset,
5233 &temp, payload_size,
5234 dpb_output_delay+cpb_removal_delay);
5235 bit_offset += dpb_output_delay+cpb_removal_delay;
5236 }
5237 if (p_H264_Dpb->vui_status & 0x10) {
5238 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5239 bit_offset += 4;
5240 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5241 }
5242 break;
5243 case SEI_USER_DATA:
5244 if (enable_itu_t35) {
5245 int i;
5246 int j;
5247 int data_len;
5248 u8 *user_data_buf;
5249
5250 user_data_buf
5251 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5252 /* user data length should be align with 8 bytes,
5253 if not, then padding with zero*/
5254 for (i = 0; i < payload_size; i += 8) {
5255 for (j = 0; j < 8; j++) {
5256 int index;
5257
5258 index = i+7-j;
5259 if (index >= payload_size)
5260 user_data_buf[i+j] = 0;
5261 else
5262 user_data_buf[i+j]
5263 = p_sei[i+7-j];
5264 }
5265 }
5266
5267 data_len = payload_size;
5268 if (payload_size % 8)
5269 data_len = ((payload_size + 8) >> 3) << 3;
5270
5271 hw->sei_itu_data_len += data_len;
5272 /*
5273 dpb_print(DECODE_ID(hw), 0,
5274 "%s: user data, and len = %d:\n",
5275 __func__, hw->sei_itu_data_len);
5276 */
5277 }
5278 break;
5279 case SEI_RECOVERY_POINT:
5280 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5281 break;
5282 }
5283
5284 return read_size + payload_size;
5285}
5286
5287static void parse_sei_data(struct vdec_h264_hw_s *hw,
5288 u8 *sei_data_buf,
5289 int len)
5290{
5291 char *p_sei;
5292 char *p_sei_end;
5293 int parsed_size;
5294 int read_size;
5295
5296
5297 p_sei = sei_data_buf;
5298 p_sei_end = p_sei + len;
5299 parsed_size = 0;
5300 while (parsed_size < len) {
5301 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5302 p_sei += read_size;
5303 parsed_size += read_size;
5304 if (*p_sei == 0x80) {
5305 p_sei++;
5306 parsed_size++;
5307 }
5308 }
5309}
5310
5311static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5312{
5313 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5314 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5315 unsigned mby_mbx = READ_VREG(MBY_MBX);
5316 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5317 unsigned decode_mb_count =
5318 ((mby_mbx & 0xff) * hw->mb_width +
5319 (((mby_mbx >> 8) & 0xff) + 1));
5320 if (mby_mbx == 0)
5321 return;
5322 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5323 mb_total /= 2;
5324 if (error_proc_policy & 0x100) {
5325 if (decode_mb_count < mb_total)
5326 p->data_flag |= ERROR_FLAG;
5327 }
5328
5329 if ((error_proc_policy & 0x200) &&
5330 READ_VREG(ERROR_STATUS_REG) != 0) {
5331 p->data_flag |= ERROR_FLAG;
5332 }
5333
5334 if (p->data_flag & ERROR_FLAG) {
5335 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5336 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5337 __func__,
5338 hw->seq_info2,
5339 mby_mbx,
5340 mb_total,
5341 decode_mb_count,
5342 READ_VREG(ERROR_STATUS_REG)
5343 );
5344
5345 }
5346}
5347
5348static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5349{
5350 int i;
5351 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5352 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5353 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5354 u32 debug_tag;
5355 int ret;
5356
5357 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5358#if 1
5359 unsigned short *p = (unsigned short *)hw->lmem_addr;
5360 dma_sync_single_for_cpu(
5361 amports_get_dma_device(),
5362 hw->lmem_addr_remap,
5363 PAGE_SIZE,
5364 DMA_FROM_DEVICE);
5365 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5366 int ii;
5367 for (ii = 0; ii < 4; ii++) {
5368 p_H264_Dpb->dpb_param.l.data[i+ii] =
5369 p[i+3-ii];
5370 if (dpb_is_debug(DECODE_ID(hw),
5371 RRINT_FLAG_RPM)) {
5372 if (((i + ii) & 0xf) == 0)
5373 dpb_print(DECODE_ID(hw),
5374 0, "%04x:",
5375 i);
5376 dpb_print_cont(DECODE_ID(hw),
5377 0, "%04x ",
5378 p[i+3-ii]);
5379 if (((i + ii + 1) & 0xf) == 0)
5380 dpb_print_cont(
5381 DECODE_ID(hw),
5382 0, "\r\n");
5383 }
5384 }
5385 }
5386
5387 p_H264_Dpb->bitstream_restriction_flag =
5388 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5389 p_H264_Dpb->num_reorder_frames =
5390 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5391 p_H264_Dpb->max_dec_frame_buffering =
5392 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5393
5394 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5395 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5396 p_H264_Dpb->bitstream_restriction_flag,
5397 p_H264_Dpb->num_reorder_frames,
5398 p_H264_Dpb->max_dec_frame_buffering);
5399 hw->bitstream_restriction_flag =
5400 p_H264_Dpb->bitstream_restriction_flag;
5401 hw->num_reorder_frames =
5402 p_H264_Dpb->num_reorder_frames;
5403 hw->max_dec_frame_buffering =
5404 p_H264_Dpb->max_dec_frame_buffering;
5405#endif
5406
5407 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5408 reset_process_time(hw);
5409 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5410 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5411 vdec_schedule_work(&hw->work);
5412 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5413 u16 data_hight;
5414 u16 data_low;
5415 u32 video_signal;
5416
5417 int slice_header_process_status = 0;
5418 int I_flag;
5419 /*unsigned char is_idr;*/
5420 unsigned short *p = (unsigned short *)hw->lmem_addr;
5421 reset_process_time(hw);
5422
5423 if (hw->is_used_v4l) {
5424 struct aml_vcodec_ctx *ctx =
5425 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5426
5427 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5428 //amvdec_stop();
5429 hw->dec_result = DEC_RESULT_DONE;
5430 vdec_schedule_work(&hw->work);
5431 return IRQ_HANDLED;
5432 }
5433 }
5434
5435 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5436 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5437 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5438 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5439 if (input_frame_based(vdec) &&
5440 frmbase_cont_bitlevel2 != 0 &&
5441 READ_VREG(VIFF_BIT_CNT) <
5442 frmbase_cont_bitlevel2 &&
5443 hw->get_data_count >= 0x70000000) {
5444 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5445 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5446 __func__,
5447 READ_VREG(VIFF_BIT_CNT));
5448
5449 goto empty_proc;
5450 }
5451
5452 dma_sync_single_for_cpu(
5453 amports_get_dma_device(),
5454 hw->lmem_addr_remap,
5455 PAGE_SIZE,
5456 DMA_FROM_DEVICE);
5457#if 0
5458 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5459 if (!is_buffer_available(vdec)) {
5460 hw->buffer_empty_flag = 1;
5461 dpb_print(DECODE_ID(hw),
5462 PRINT_FLAG_UCODE_EVT,
5463 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5464 __func__,
5465 kfifo_len(&hw->newframe_q),
5466 have_free_buf_spec(vdec),
5467 p_H264_Dpb->mDPB.init_done,
5468 p_H264_Dpb->mDPB.used_size,
5469 p_H264_Dpb->mDPB.size,
5470 is_there_unused_frame_from_dpb(
5471 &p_H264_Dpb->mDPB));
5472 return IRQ_HANDLED;
5473 }
5474 }
5475
5476 hw->buffer_empty_flag = 0;
5477#endif
5478#ifdef SEND_PARAM_WITH_REG
5479 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5480 unsigned int data32;
5481
5482 do {
5483 data32 = READ_VREG(RPM_CMD_REG);
5484 /* printk("%x\n", data32); */
5485 } while ((data32&0x10000) == 0);
5486 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5487 WRITE_VREG(RPM_CMD_REG, 0);
5488 /* printk("%x:%x\n", i,data32); */
5489 }
5490#else
5491 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5492 int ii;
5493
5494 for (ii = 0; ii < 4; ii++) {
5495 p_H264_Dpb->dpb_param.l.data[i+ii] =
5496 p[i+3-ii];
5497 if (dpb_is_debug(DECODE_ID(hw),
5498 RRINT_FLAG_RPM)) {
5499 if (((i + ii) & 0xf) == 0)
5500 dpb_print(DECODE_ID(hw),
5501 0, "%04x:",
5502 i);
5503 dpb_print_cont(DECODE_ID(hw),
5504 0, "%04x ",
5505 p[i+3-ii]);
5506 if (((i + ii + 1) & 0xf) == 0)
5507 dpb_print_cont(
5508 DECODE_ID(hw),
5509 0, "\r\n");
5510 }
5511 }
5512 }
5513#endif
5514 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5515 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5516
5517 video_signal = (data_hight << 16) | data_low;
5518 hw->video_signal_from_vui =
5519 ((video_signal & 0xffff) << 8) |
5520 ((video_signal & 0xff0000) >> 16) |
5521 ((video_signal & 0x3f000000));
5522
5523
5524 /*dpb_print(DECODE_ID(hw),
5525 0,
5526 "video_signal_from_vui:0x%x, "
5527 "data_low:0x%x, data_hight:0x%x\n",
5528 hw->video_signal_from_vui,
5529 data_low,
5530 data_hight);*/
5531
5532 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5533
5534 if (hw->config_bufmgr_done == 0) {
5535 hw->dec_result = DEC_RESULT_DONE;
5536 vdec_schedule_work(&hw->work);
5537 dpb_print(DECODE_ID(hw),
5538 PRINT_FLAG_UCODE_EVT,
5539 "config_bufmgr not done, discard frame\n");
5540 return IRQ_HANDLED;
5541 } else if ((hw->first_i_policy & 0x3) != 0) {
5542 unsigned char is_i_slice =
5543 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5544 == I_Slice)
5545 ? 1 : 0;
5546 unsigned char is_idr =
5547 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5548 == 5);
5549 if ((hw->first_i_policy & 0x3) == 0x3)
5550 is_i_slice = is_idr;
5551 if (!is_i_slice) {
5552 if (hw->has_i_frame == 0) {
5553 amvdec_stop();
5554 vdec->mc_loaded = 0;
5555 hw->dec_result = DEC_RESULT_DONE;
5556 vdec_schedule_work(&hw->work);
5557 dpb_print(DECODE_ID(hw),
5558 PRINT_FLAG_UCODE_EVT,
5559 "has_i_frame is 0, discard none I(DR) frame\n");
5560 return IRQ_HANDLED;
5561 }
5562 } else {
5563 if (hw->skip_frame_count < 0 || is_idr) {
5564 /* second I */
5565 hw->dec_flag &= (~NODISP_FLAG);
5566 hw->skip_frame_count = 0;
5567 }
5568 if (hw->has_i_frame == 0 &&
5569 (!is_idr)) {
5570 int skip_count =
5571 (hw->first_i_policy >> 8) & 0xff;
5572 /* first I (not IDR) */
5573 if ((hw->first_i_policy & 0x3) == 2)
5574 hw->skip_frame_count =
5575 -1 - skip_count;
5576 else
5577 hw->skip_frame_count =
5578 skip_count;
5579 if (hw->skip_frame_count != 0)
5580 hw->dec_flag |= NODISP_FLAG;
5581 }
5582 }
5583 }
5584 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5585 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5586 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5587 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5588 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5589 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5590 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5591 ? I_FLAG : 0;
5592
5593 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5594 flush_dpb(p_H264_Dpb);
5595
5596 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5597 (p_H264_Dpb->mSlice.structure == FRAME)) {
5598 hw->data_flag = NULL_FLAG;
5599 goto pic_done_proc;
5600 }
5601
5602 slice_header_process_status =
5603 h264_slice_header_process(p_H264_Dpb);
5604 if (hw->mmu_enable)
5605 hevc_sao_set_slice_type(hw,
5606 slice_header_process_status,
5607 hw->dpb.mSlice.idr_flag);
5608 vui_config(hw);
5609
5610 if (p_H264_Dpb->mVideo.dec_picture) {
5611 int cfg_ret = 0;
5612 bool field_pic_flag = false;
5613
5614 if (slice_header_process_status == 1) {
5615 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5616 field_pic_flag =
5617 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5618 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5619 true : false;
5620 }
5621
5622 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5623 (((unsigned long)(hw->vh264_amstream_dec_info
5624 .param)) & 0x8))) {
5625 p_H264_Dpb->fast_output_enable =
5626 H264_OUTPUT_MODE_FAST;
5627 }
5628 else
5629 p_H264_Dpb->fast_output_enable
5630 = fast_output_enable;
5631 hw->data_flag = I_flag;
5632 if ((p_H264_Dpb->
5633 dpb_param.dpb.NAL_info_mmco & 0x1f)
5634 == 5)
5635 hw->data_flag |= IDR_FLAG;
5636 dpb_print(DECODE_ID(hw),
5637 PRINT_FLAG_VDEC_STATUS,
5638 "==================> frame count %d to skip %d\n",
5639 hw->decode_pic_count+1,
5640 hw->skip_frame_count);
5641 } else if (error_proc_policy & 0x100){
5642 struct StorablePicture *p =
5643 p_H264_Dpb->mVideo.dec_picture;
5644 unsigned mby_mbx = READ_VREG(MBY_MBX);
5645 unsigned decode_mb_count =
5646 ((mby_mbx & 0xff) * hw->mb_width +
5647 (((mby_mbx >> 8) & 0xff) + 1));
5648 if (decode_mb_count <
5649 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5650 (1 + p->mb_aff_frame_flag))) {
5651 dpb_print(DECODE_ID(hw),
5652 PRINT_FLAG_VDEC_STATUS,
5653 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5654 p_H264_Dpb->dpb_param.l.
5655 data[FIRST_MB_IN_SLICE],
5656 READ_VREG(MBY_MBX),
5657 decode_mb_count);
5658 p->data_flag |= ERROR_FLAG;
5659 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5660 p->data_flag |= ERROR_FLAG;
5661 goto pic_done_proc;
5662 }
5663 }
5664
5665 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5666 hw->new_iframe_flag = 1;
5667 }
5668 if (hw->new_iframe_flag) {
5669 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5670 hw->new_iframe_flag = 0;
5671 hw->ref_err_flush_dpb_flag = 1;
5672 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5673 hw->new_iframe_flag = 0;
5674 hw->ref_err_flush_dpb_flag = 0;
5675 }
5676 }
5677
5678 if (error_proc_policy & 0x400) {
5679 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5680 if (ret != 0) {
5681 hw->reflist_error_count ++;
5682 dpb_print(DECODE_ID(hw), 0,
5683 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5684 ret,
5685 hw->decode_pic_count+1,
5686 hw->skip_frame_count,
5687 hw->reflist_error_count);
5688
5689 if (hw->ref_err_flush_dpb_flag) {
5690 flush_dpb(p_H264_Dpb);
5691 p_H264_Dpb->colocated_buf_map = 0;
5692 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5693 p_H264_Dpb->colocated_buf_map |= 1 <<
5694 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5695 }
5696 }
5697
5698 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5699 if (((error_proc_policy & 0x80)
5700 && ((hw->dec_flag &
5701 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5702 hw->reset_bufmgr_flag = 1;
5703 hw->reflist_error_count =0;
5704 amvdec_stop();
5705 vdec->mc_loaded = 0;
5706 hw->dec_result = DEC_RESULT_DONE;
5707 vdec_schedule_work(&hw->work);
5708 return IRQ_HANDLED;
5709 }
5710 } else
5711 hw->reflist_error_count = 0;
5712 }
5713 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5714 && p_H264_Dpb->dpb_error_flag != 0) {
5715 dpb_print(DECODE_ID(hw), 0,
5716 "dpb error %d\n",
5717 p_H264_Dpb->dpb_error_flag);
5718 hw->data_flag |= ERROR_FLAG;
5719 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5720 if ((error_proc_policy & 0x80) &&
5721 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5722 hw->reset_bufmgr_flag = 1;
5723 amvdec_stop();
5724 vdec->mc_loaded = 0;
5725 hw->dec_result = DEC_RESULT_DONE;
5726 vdec_schedule_work(&hw->work);
5727 return IRQ_HANDLED;
5728 }
5729 }
5730
5731 cfg_ret = config_decode_buf(hw,
5732 p_H264_Dpb->mVideo.dec_picture);
5733 if (cfg_ret < 0) {
5734 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5735 "config_decode_buf fail (%d)\n",
5736 cfg_ret);
5737 if (error_proc_policy & 0x2) {
5738 release_cur_decoding_buf(hw);
5739 /*hw->data_flag |= ERROR_FLAG;*/
5740 hw->reset_bufmgr_flag = 1;
5741 hw->dec_result = DEC_RESULT_DONE;
5742 vdec_schedule_work(&hw->work);
5743 return IRQ_HANDLED;
5744 } else
5745 hw->data_flag |= ERROR_FLAG;
5746 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5747 }
5748 }
5749
5750 if (slice_header_process_status == 1)
5751 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5752 else
5753 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5754 hw->last_mby_mbx = 0;
5755 hw->last_vld_level = 0;
5756 start_process_time(hw);
5757 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5758 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5759pic_done_proc:
5760 reset_process_time(hw);
5761
5762 if (input_frame_based(vdec) &&
5763 (!(hw->i_only & 0x2)) &&
5764 frmbase_cont_bitlevel != 0 &&
5765 READ_VREG(VIFF_BIT_CNT) >
5766 frmbase_cont_bitlevel) {
5767 /*handle the case: multi pictures in one packet*/
5768 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5769 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5770 __func__,
5771 hw->decode_pic_count,
5772 READ_VREG(VIFF_BIT_CNT));
5773 hw->frmbase_cont_flag = 1;
5774 } else
5775 hw->frmbase_cont_flag = 0;
5776
5777 if (p_H264_Dpb->mVideo.dec_picture) {
5778 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5779#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5780 DEL_EXIST(hw,
5781 p_H264_Dpb->mVideo.dec_picture) = 0;
5782 if (vdec->master) {
5783 struct vdec_h264_hw_s *hw_ba =
5784 (struct vdec_h264_hw_s *)
5785 vdec->master->private;
5786 if (hw_ba->last_dec_picture)
5787 DEL_EXIST(hw_ba,
5788 hw_ba->last_dec_picture)
5789 = 1;
5790 }
5791#endif
5792 mutex_lock(&hw->chunks_mutex);
5793 if (hw->chunk) {
5794 p_H264_Dpb->mVideo.dec_picture->pts =
5795 hw->chunk->pts;
5796 p_H264_Dpb->mVideo.dec_picture->pts64 =
5797 hw->chunk->pts64;
5798 p_H264_Dpb->mVideo.dec_picture->timestamp =
5799 hw->chunk->timestamp;
5800#ifdef MH264_USERDATA_ENABLE
5801 vmh264_udc_fill_vpts(hw,
5802 p_H264_Dpb->mSlice.slice_type,
5803 hw->chunk->pts, 1);
5804#endif
5805
5806#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5807 } else if (vdec->master) {
5808 /*dv enhance layer,
5809 do not checkout pts*/
5810 struct StorablePicture *pic =
5811 p_H264_Dpb->mVideo.dec_picture;
5812 pic->pts = 0;
5813 pic->pts64 = 0;
5814#endif
5815 } else {
5816 struct StorablePicture *pic =
5817 p_H264_Dpb->mVideo.dec_picture;
5818 u32 offset = pic->offset_delimiter;
5819 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5820 offset, &pic->pts, 0, &pic->pts64)) {
5821 pic->pts = 0;
5822 pic->pts64 = 0;
5823#ifdef MH264_USERDATA_ENABLE
5824 vmh264_udc_fill_vpts(hw,
5825 p_H264_Dpb->mSlice.slice_type,
5826 pic->pts, 0);
5827#endif
5828 } else {
5829#ifdef MH264_USERDATA_ENABLE
5830 vmh264_udc_fill_vpts(hw,
5831 p_H264_Dpb->mSlice.slice_type,
5832 pic->pts, 1);
5833#endif
5834 }
5835
5836 }
5837 mutex_unlock(&hw->chunks_mutex);
5838
5839 check_decoded_pic_error(hw);
5840#ifdef ERROR_HANDLE_TEST
5841 if ((hw->data_flag & ERROR_FLAG)
5842 && (error_proc_policy & 0x80)) {
5843 release_cur_decoding_buf(hw);
5844 h264_clear_dpb(hw);
5845 hw->dec_flag = 0;
5846 hw->data_flag = 0;
5847 hw->skip_frame_count = 0;
5848 hw->has_i_frame = 0;
5849 hw->no_error_count = 0xfff;
5850 hw->no_error_i_count = 0xf;
5851 } else
5852#endif
5853 ret = store_picture_in_dpb(p_H264_Dpb,
5854 p_H264_Dpb->mVideo.dec_picture,
5855 hw->data_flag | hw->dec_flag |
5856 p_H264_Dpb->mVideo.dec_picture->data_flag);
5857
5858
5859
5860 if (ret == -1) {
5861 release_cur_decoding_buf(hw);
5862 bufmgr_force_recover(p_H264_Dpb);
5863 } else {
5864 if (hw->data_flag & ERROR_FLAG) {
5865 hw->no_error_count = 0;
5866 hw->no_error_i_count = 0;
5867 } else {
5868 hw->no_error_count++;
5869 if (hw->data_flag & I_FLAG)
5870 hw->no_error_i_count++;
5871 }
5872 if (hw->mmu_enable)
5873 hevc_set_unused_4k_buff_idx(hw,
5874 p_H264_Dpb->mVideo.
5875 dec_picture->buf_spec_num);
5876 bufmgr_post(p_H264_Dpb);
5877 hw->last_dec_picture =
5878 p_H264_Dpb->mVideo.dec_picture;
5879 p_H264_Dpb->mVideo.dec_picture = NULL;
5880 /* dump_dpb(&p_H264_Dpb->mDPB); */
5881 hw->has_i_frame = 1;
5882 if (hw->mmu_enable)
5883 hevc_set_frame_done(hw);
5884 hw->decode_pic_count++;
5885 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5886 if (hw->skip_frame_count > 0) {
5887 /*skip n frame after first I */
5888 hw->skip_frame_count--;
5889 if (hw->skip_frame_count == 0)
5890 hw->dec_flag &= (~NODISP_FLAG);
5891 } else if (hw->skip_frame_count < -1) {
5892 /*skip n frame after first I until second I */
5893 hw->skip_frame_count++;
5894 if (hw->skip_frame_count == -1)
5895 hw->dec_flag &= (~NODISP_FLAG);
5896 }
5897 }
5898 }
5899 if (hw->frmbase_cont_flag) {
5900 /*do not DEC_RESULT_GET_DATA*/
5901 hw->get_data_count = 0x7fffffff;
5902 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5903 decode_frame_count[DECODE_ID(hw)]++;
5904 start_process_time(hw);
5905 return IRQ_HANDLED;
5906 }
5907 amvdec_stop();
5908 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5909 "%s %s decode slice count %d\n",
5910 __func__,
5911 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5912 "H264_PIC_DATA_DONE" :
5913 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5914 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5915 hw->decode_pic_count);
5916 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5917 hw->dec_result = DEC_RESULT_DONE;
5918#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5919 if (vdec->slave &&
5920 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5921 struct vdec_h264_hw_s *hw_el =
5922 (struct vdec_h264_hw_s *)(vdec->slave->private);
5923 hw_el->got_valid_nal = 0;
5924 hw->switch_dvlayer_flag = 1;
5925 } else if (vdec->master &&
5926 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5927 struct vdec_h264_hw_s *hw_bl =
5928 (struct vdec_h264_hw_s *)(vdec->master->private);
5929 hw_bl->got_valid_nal = 0;
5930 hw->switch_dvlayer_flag = 1;
5931 } else {
5932 hw->switch_dvlayer_flag = 0;
5933 hw->got_valid_nal = 1;
5934 }
5935#endif
5936
5937 hw->dec_result = DEC_RESULT_DONE;
5938 vdec_schedule_work(&hw->work);
5939
5940#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5941 } else if (
5942 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5943 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5944 goto pic_done_proc;
5945#endif
5946 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5947 reset_process_time(hw);
5948 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5949 dma_sync_single_for_cpu(
5950 amports_get_dma_device(),
5951 hw->aux_phy_addr,
5952 hw->prefix_aux_size + hw->suffix_aux_size,
5953 DMA_FROM_DEVICE);
5954 if (dpb_is_debug(DECODE_ID(hw),
5955 PRINT_FLAG_DPB_DETAIL))
5956 dump_aux_buf(hw);
5957#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5958 if (vdec->dolby_meta_with_el || vdec->slave) {
5959 if (hw->last_dec_picture)
5960 set_aux_data(hw, hw->last_dec_picture,
5961 0, 0, NULL);
5962 } else {
5963 if (vdec->master) {
5964 struct vdec_h264_hw_s *hw_bl =
5965 (struct vdec_h264_hw_s *)
5966 (vdec->master->private);
5967 if (hw_bl->last_dec_picture != NULL) {
5968 set_aux_data(hw_bl,
5969 hw_bl->last_dec_picture,
5970 0, 1, hw);
5971 }
5972 set_aux_data(hw,
5973 hw->last_dec_picture,
5974 0, 2, NULL);
5975 }
5976 }
5977#else
5978 if (hw->last_dec_picture)
5979 set_aux_data(hw,
5980 hw->last_dec_picture, 0, 0, NULL);
5981#endif
5982 }
5983#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5984 hw->switch_dvlayer_flag = 0;
5985 hw->got_valid_nal = 1;
5986#endif
5987 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5988 "%s H264_AUX_DATA_READY\n", __func__);
5989 hw->dec_result = DEC_RESULT_DONE;
5990 vdec_schedule_work(&hw->work);
5991 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5992 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5993 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5994 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5995empty_proc:
5996 reset_process_time(hw);
5997 if (!hw->frmbase_cont_flag)
5998 release_cur_decoding_buf(hw);
5999
6000 if (input_frame_based(vdec) ||
6001 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6002 if (h264_debug_flag &
6003 DISABLE_ERROR_HANDLE) {
6004 dpb_print(DECODE_ID(hw),
6005 PRINT_FLAG_ERROR,
6006 "%s decoding error, level 0x%x\n",
6007 __func__,
6008 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6009 goto send_again;
6010 }
6011 amvdec_stop();
6012 vdec->mc_loaded = 0;
6013 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6014 "%s %s\n", __func__,
6015 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6016 "H264_SEARCH_BUFEMPTY" :
6017 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6018 "H264_DECODE_BUFEMPTY" :
6019 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6020 "H264_DECODE_TIMEOUT" :
6021 "OTHER");
6022 hw->dec_result = DEC_RESULT_DONE;
6023
6024 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6025 hw->search_dataempty_num++;
6026 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6027 hw->decode_timeout_num++;
6028 if (error_proc_policy & 0x4000) {
6029 hw->data_flag |= ERROR_FLAG;
6030 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6031 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6032 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6033 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6034 dpb_print(DECODE_ID(hw),
6035 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6036 p_H264_Dpb->last_dpb_status, __func__);
6037 hw->reset_bufmgr_flag = 1;
6038 }
6039 }
6040 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6041 hw->decode_dataempty_num++;
6042 if (!hw->frmbase_cont_flag)
6043 hw->data_flag |= ERROR_FLAG;
6044
6045 vdec_schedule_work(&hw->work);
6046 } else {
6047 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6048 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6049 "%s DEC_RESULT_AGAIN\n", __func__);
6050send_again:
6051 hw->dec_result = DEC_RESULT_AGAIN;
6052 vdec_schedule_work(&hw->work);
6053 }
6054 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6055 reset_process_time(hw);
6056 if (input_frame_based(vdec)) {
6057 dpb_print(DECODE_ID(hw),
6058 PRINT_FLAG_VDEC_STATUS,
6059 "%s H264_DATA_REQUEST (%d)\n",
6060 __func__, hw->get_data_count);
6061 hw->dec_result = DEC_RESULT_GET_DATA;
6062 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6063 hw->get_data_start_time = jiffies;
6064 hw->get_data_count++;
6065 if (hw->get_data_count >= frame_max_data_packet)
6066 goto empty_proc;
6067 vdec_schedule_work(&hw->work);
6068 } else
6069 goto empty_proc;
6070 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6071 dpb_print(DECODE_ID(hw), 0,
6072 "vmh264 decode oversize !!\n");
6073 release_cur_decoding_buf(hw);
6074 hw->data_flag |= ERROR_FLAG;
6075 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6076 reset_process_time(hw);
6077 hw->dec_result = DEC_RESULT_DONE;
6078 vdec_schedule_work(&hw->work);
6079 return IRQ_HANDLED;
6080 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6081 int aux_data_len;
6082 aux_data_len =
6083 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6084
6085 if (aux_data_len > SEI_DATA_SIZE) {
6086 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6087 "sei data size more than 4K: %d, discarded it\n",
6088 hw->sei_itu_data_len);
6089 hw->sei_itu_data_len = 0;
6090 }
6091
6092 if (aux_data_len != 0) {
6093 u8 *trans_data_buf;
6094 u8 *sei_data_buf;
6095 u8 swap_byte;
6096
6097 dma_sync_single_for_cpu(
6098 amports_get_dma_device(),
6099 hw->aux_phy_addr,
6100 hw->prefix_aux_size + hw->suffix_aux_size,
6101 DMA_FROM_DEVICE);
6102#if 0
6103 dump_aux_buf(hw);
6104#endif
6105 trans_data_buf = (u8 *)hw->aux_addr;
6106
6107 if (trans_data_buf[7] == AUX_TAG_SEI) {
6108 int left_len;
6109
6110 sei_data_buf = (u8 *)hw->sei_data_buf
6111 + hw->sei_data_len;
6112 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6113 if (aux_data_len/2 <= left_len) {
6114 for (i = 0; i < aux_data_len/2; i++)
6115 sei_data_buf[i]
6116 = trans_data_buf[i*2];
6117
6118 aux_data_len = aux_data_len / 2;
6119 for (i = 0; i < aux_data_len; i = i+4) {
6120 swap_byte = sei_data_buf[i];
6121 sei_data_buf[i]
6122 = sei_data_buf[i+3];
6123 sei_data_buf[i+3] = swap_byte;
6124
6125 swap_byte = sei_data_buf[i+1];
6126 sei_data_buf[i+1]
6127 = sei_data_buf[i+2];
6128 sei_data_buf[i+2] = swap_byte;
6129 }
6130
6131 for (i = aux_data_len-1; i >= 0; i--)
6132 if (sei_data_buf[i] != 0)
6133 break;
6134
6135 hw->sei_data_len += i+1;
6136 } else
6137 dpb_print(DECODE_ID(hw),
6138 PRINT_FLAG_ERROR,
6139 "sei data size %d and more than left space: %d, discarded it\n",
6140 hw->sei_itu_data_len,
6141 left_len);
6142 }
6143 }
6144 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6145
6146 return IRQ_HANDLED;
6147 }
6148
6149
6150 /* ucode debug */
6151 debug_tag = READ_VREG(DEBUG_REG1);
6152 if (debug_tag & 0x10000) {
6153 unsigned short *p = (unsigned short *)hw->lmem_addr;
6154
6155 dma_sync_single_for_cpu(
6156 amports_get_dma_device(),
6157 hw->lmem_addr_remap,
6158 PAGE_SIZE,
6159 DMA_FROM_DEVICE);
6160
6161 dpb_print(DECODE_ID(hw), 0,
6162 "LMEM<tag %x>:\n", debug_tag);
6163 for (i = 0; i < 0x400; i += 4) {
6164 int ii;
6165 if ((i & 0xf) == 0)
6166 dpb_print_cont(DECODE_ID(hw), 0,
6167 "%03x: ", i);
6168 for (ii = 0; ii < 4; ii++)
6169 dpb_print_cont(DECODE_ID(hw), 0,
6170 "%04x ", p[i+3-ii]);
6171 if (((i+ii) & 0xf) == 0)
6172 dpb_print_cont(DECODE_ID(hw), 0,
6173 "\n");
6174 }
6175 if (((udebug_pause_pos & 0xffff)
6176 == (debug_tag & 0xffff)) &&
6177 (udebug_pause_decode_idx == 0 ||
6178 udebug_pause_decode_idx ==
6179 hw->decode_pic_count) &&
6180 (udebug_pause_val == 0 ||
6181 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6182 udebug_pause_pos &= 0xffff;
6183 hw->ucode_pause_pos = udebug_pause_pos;
6184 }
6185 else if (debug_tag & 0x20000)
6186 hw->ucode_pause_pos = 0xffffffff;
6187 if (hw->ucode_pause_pos)
6188 reset_process_time(hw);
6189 else
6190 WRITE_VREG(DEBUG_REG1, 0);
6191 } else if (debug_tag != 0) {
6192 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6193 "dbg%x: %x\n", debug_tag,
6194 READ_VREG(DEBUG_REG2));
6195 if (((udebug_pause_pos & 0xffff)
6196 == (debug_tag & 0xffff)) &&
6197 (udebug_pause_decode_idx == 0 ||
6198 udebug_pause_decode_idx ==
6199 hw->decode_pic_count) &&
6200 (udebug_pause_val == 0 ||
6201 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6202 udebug_pause_pos &= 0xffff;
6203 hw->ucode_pause_pos = udebug_pause_pos;
6204 }
6205 if (hw->ucode_pause_pos)
6206 reset_process_time(hw);
6207 else
6208 WRITE_VREG(DEBUG_REG1, 0);
6209 }
6210 /**/
6211 return IRQ_HANDLED;
6212}
6213
6214static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6215{
6216 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6217 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6218
6219
6220 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6221
6222 if (!hw)
6223 return IRQ_HANDLED;
6224
6225 if (hw->eos)
6226 return IRQ_HANDLED;
6227
6228 p_H264_Dpb->vdec = vdec;
6229 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6230
6231 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6232 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6233 __func__,
6234 p_H264_Dpb->dec_dpb_status,
6235 READ_VREG(ERROR_STATUS_REG),
6236 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6237 READ_VREG(VLD_MEM_VIFIFO_WP),
6238 READ_VREG(VLD_MEM_VIFIFO_RP),
6239 READ_VREG(VIFF_BIT_CNT),
6240 READ_VREG(MBY_MBX));
6241
6242 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6243 if (hw->mmu_enable)
6244 hevc_sao_wait_done(hw);
6245 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6246 return IRQ_HANDLED;
6247 }
6248 return IRQ_WAKE_THREAD;
6249
6250}
6251
6252static void timeout_process(struct vdec_h264_hw_s *hw)
6253{
6254 struct vdec_s *vdec = hw_to_vdec(hw);
6255 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6256
6257 /*
6258 * In this very timeout point,the vh264_work arrives,
6259 * let it to handle the scenario.
6260 */
6261 if (work_pending(&hw->work))
6262 return;
6263
6264 hw->timeout_num++;
6265 amvdec_stop();
6266 vdec->mc_loaded = 0;
6267 if (hw->mmu_enable) {
6268 hevc_set_frame_done(hw);
6269 hevc_sao_wait_done(hw);
6270 }
6271 if (!hw->i_only && (error_proc_policy & 0x2))
6272 flush_dpb(p_H264_Dpb);
6273 dpb_print(DECODE_ID(hw),
6274 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6275 release_cur_decoding_buf(hw);
6276 hw->dec_result = DEC_RESULT_DONE;
6277 hw->data_flag |= ERROR_FLAG;
6278
6279 if (work_pending(&hw->work))
6280 return;
6281 vdec_schedule_work(&hw->timeout_work);
6282}
6283
6284static void dump_bufspec(struct vdec_h264_hw_s *hw,
6285 const char *caller)
6286{
6287 int i;
6288 dpb_print(DECODE_ID(hw), 0,
6289 "%s in %s:\n", __func__, caller);
6290 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6291 if (hw->buffer_spec[i].used == -1)
6292 continue;
6293 dpb_print(DECODE_ID(hw), 0,
6294 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6295 i, hw->buffer_spec[i].used,
6296 hw->buffer_spec[i].buf_adr,
6297 hw->buffer_spec[i].canvas_pos,
6298 hw->buffer_spec[i].vf_ref
6299 );
6300#ifdef CONFIG_AM_VDEC_DV
6301 dpb_print_cont(DECODE_ID(hw), 0,
6302 "dv_el_exist %d",
6303 hw->buffer_spec[i].dv_enhance_exist
6304 );
6305#endif
6306 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6307 }
6308
6309}
6310
6311static void vmh264_dump_state(struct vdec_s *vdec)
6312{
6313 struct vdec_h264_hw_s *hw =
6314 (struct vdec_h264_hw_s *)(vdec->private);
6315 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6316 dpb_print(DECODE_ID(hw), 0,
6317 "====== %s\n", __func__);
6318 dpb_print(DECODE_ID(hw), 0,
6319 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6320 hw->frame_width,
6321 hw->frame_height,
6322 hw->dpb.reorder_pic_num,
6323 hw->dpb.mDPB.size,
6324 hw->max_reference_size,
6325 hw->i_only,
6326 hw->send_error_frame_flag
6327 );
6328
6329 dpb_print(DECODE_ID(hw), 0,
6330 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6331 input_frame_based(vdec),
6332 hw->eos,
6333 hw->stat,
6334 hw->dec_result,
6335 decode_frame_count[DECODE_ID(hw)],
6336 display_frame_count[DECODE_ID(hw)],
6337 run_count[DECODE_ID(hw)],
6338 not_run_ready[DECODE_ID(hw)],
6339 input_empty[DECODE_ID(hw)],
6340 hw->reset_bufmgr_count
6341 );
6342
6343 if (vf_get_receiver(vdec->vf_provider_name)) {
6344 enum receviver_start_e state =
6345 vf_notify_receiver(vdec->vf_provider_name,
6346 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6347 NULL);
6348 dpb_print(DECODE_ID(hw), 0,
6349 "\nreceiver(%s) state %d\n",
6350 vdec->vf_provider_name,
6351 state);
6352 }
6353
6354 dpb_print(DECODE_ID(hw), 0,
6355 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x\n",
6356 __func__,
6357 kfifo_len(&hw->newframe_q),
6358 VF_POOL_SIZE,
6359 kfifo_len(&hw->display_q),
6360 VF_POOL_SIZE,
6361 hw->vf_pre_count,
6362 hw->vf_get_count,
6363 hw->vf_put_count,
6364 have_free_buf_spec(vdec),
6365 p_H264_Dpb->mDPB.init_done,
6366 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6367 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6368 p_H264_Dpb->fast_output_enable
6369 );
6370
6371 dump_dpb(&p_H264_Dpb->mDPB, 1);
6372 dump_pic(p_H264_Dpb);
6373 dump_bufspec(hw, __func__);
6374
6375 dpb_print(DECODE_ID(hw), 0,
6376 "DPB_STATUS_REG=0x%x\n",
6377 READ_VREG(DPB_STATUS_REG));
6378 dpb_print(DECODE_ID(hw), 0,
6379 "MPC_E=0x%x\n",
6380 READ_VREG(MPC_E));
6381 dpb_print(DECODE_ID(hw), 0,
6382 "H264_DECODE_MODE=0x%x\n",
6383 READ_VREG(H264_DECODE_MODE));
6384 dpb_print(DECODE_ID(hw), 0,
6385 "MBY_MBX=0x%x\n",
6386 READ_VREG(MBY_MBX));
6387 dpb_print(DECODE_ID(hw), 0,
6388 "H264_DECODE_SIZE=0x%x\n",
6389 READ_VREG(H264_DECODE_SIZE));
6390 dpb_print(DECODE_ID(hw), 0,
6391 "VIFF_BIT_CNT=0x%x\n",
6392 READ_VREG(VIFF_BIT_CNT));
6393 dpb_print(DECODE_ID(hw), 0,
6394 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6395 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6396 dpb_print(DECODE_ID(hw), 0,
6397 "VLD_MEM_VIFIFO_WP=0x%x\n",
6398 READ_VREG(VLD_MEM_VIFIFO_WP));
6399 dpb_print(DECODE_ID(hw), 0,
6400 "VLD_MEM_VIFIFO_RP=0x%x\n",
6401 READ_VREG(VLD_MEM_VIFIFO_RP));
6402 dpb_print(DECODE_ID(hw), 0,
6403 "PARSER_VIDEO_RP=0x%x\n",
6404 READ_PARSER_REG(PARSER_VIDEO_RP));
6405 dpb_print(DECODE_ID(hw), 0,
6406 "PARSER_VIDEO_WP=0x%x\n",
6407 READ_PARSER_REG(PARSER_VIDEO_WP));
6408
6409 if (input_frame_based(vdec) &&
6410 dpb_is_debug(DECODE_ID(hw),
6411 PRINT_FRAMEBASE_DATA)
6412 ) {
6413 int jj;
6414 if (hw->chunk && hw->chunk->block &&
6415 hw->chunk->size > 0) {
6416 u8 *data = NULL;
6417
6418 if (!hw->chunk->block->is_mapped)
6419 data = codec_mm_vmap(hw->chunk->block->start +
6420 hw->chunk->offset, hw->chunk->size);
6421 else
6422 data = ((u8 *)hw->chunk->block->start_virt)
6423 + hw->chunk->offset;
6424
6425 dpb_print(DECODE_ID(hw), 0,
6426 "frame data size 0x%x\n",
6427 hw->chunk->size);
6428 for (jj = 0; jj < hw->chunk->size; jj++) {
6429 if ((jj & 0xf) == 0)
6430 dpb_print(DECODE_ID(hw),
6431 PRINT_FRAMEBASE_DATA,
6432 "%06x:", jj);
6433 dpb_print_cont(DECODE_ID(hw),
6434 PRINT_FRAMEBASE_DATA,
6435 "%02x ", data[jj]);
6436 if (((jj + 1) & 0xf) == 0)
6437 dpb_print_cont(DECODE_ID(hw),
6438 PRINT_FRAMEBASE_DATA,
6439 "\n");
6440 }
6441
6442 if (!hw->chunk->block->is_mapped)
6443 codec_mm_unmap_phyaddr(data);
6444 }
6445 }
6446}
6447
6448
6449static void check_timer_func(unsigned long arg)
6450{
6451 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6452 struct vdec_s *vdec = hw_to_vdec(hw);
6453 int error_skip_frame_count = error_skip_count & 0xfff;
6454 unsigned int timeout_val = decode_timeout_val;
6455 if (timeout_val != 0 &&
6456 hw->no_error_count < error_skip_frame_count)
6457 timeout_val = errordata_timeout_val;
6458 if ((h264_debug_cmd & 0x100) != 0 &&
6459 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6460 hw->dec_result = DEC_RESULT_DONE;
6461 vdec_schedule_work(&hw->work);
6462 pr_info("vdec %d is forced to be disconnected\n",
6463 h264_debug_cmd & 0xff);
6464 h264_debug_cmd = 0;
6465 return;
6466 }
6467 if ((h264_debug_cmd & 0x200) != 0 &&
6468 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6469 pr_debug("vdec %d is forced to reset bufmgr\n",
6470 h264_debug_cmd & 0xff);
6471 hw->reset_bufmgr_flag = 1;
6472 h264_debug_cmd = 0;
6473 return;
6474 }
6475
6476 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6477 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6478 vdec_schedule_work(&hw->work);
6479 pr_debug("vdec requested to be disconnected\n");
6480 return;
6481 }
6482
6483 if (radr != 0) {
6484 if (rval != 0) {
6485 WRITE_VREG(radr, rval);
6486 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6487 } else
6488 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6489 rval = 0;
6490 radr = 0;
6491 }
6492
6493 if ((input_frame_based(vdec) ||
6494 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6495 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6496 (timeout_val > 0) &&
6497 (hw->start_process_time > 0) &&
6498 ((1000 * (jiffies - hw->start_process_time) / HZ)
6499 > timeout_val)
6500 ) {
6501 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6502 u32 mby_mbx = READ_VREG(MBY_MBX);
6503 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6504 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6505 if (hw->last_mby_mbx == mby_mbx) {
6506 if (hw->decode_timeout_count > 0)
6507 hw->decode_timeout_count--;
6508 if (hw->decode_timeout_count == 0)
6509 {
6510 reset_process_time(hw);
6511 timeout_process(hw);
6512 }
6513 } else
6514 start_process_time(hw);
6515 } else if (is_in_parsing_state(dpb_status)) {
6516 if (hw->last_vld_level ==
6517 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6518 if (hw->decode_timeout_count > 0)
6519 hw->decode_timeout_count--;
6520 if (hw->decode_timeout_count == 0)
6521 {
6522 reset_process_time(hw);
6523 timeout_process(hw);
6524 }
6525 }
6526 }
6527 hw->last_vld_level =
6528 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6529 hw->last_mby_mbx = mby_mbx;
6530 }
6531
6532 if ((hw->ucode_pause_pos != 0) &&
6533 (hw->ucode_pause_pos != 0xffffffff) &&
6534 udebug_pause_pos != hw->ucode_pause_pos) {
6535 hw->ucode_pause_pos = 0;
6536 WRITE_VREG(DEBUG_REG1, 0);
6537 }
6538
6539 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6540}
6541
6542static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6543{
6544 u32 ar;
6545 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6546
6547 if (!hw)
6548 return -1;
6549
6550 vstatus->frame_width = hw->frame_width;
6551 vstatus->frame_height = hw->frame_height;
6552 if (hw->frame_dur != 0)
6553 vstatus->frame_rate = 96000 / hw->frame_dur;
6554 else
6555 vstatus->frame_rate = -1;
6556 vstatus->error_count = 0;
6557 vstatus->status = hw->stat;
6558 if (hw->h264_ar == 0x3ff)
6559 hw->h264_ar = (0x100 *
6560 hw->frame_height * hw->height_aspect_ratio) /
6561 (hw->frame_width * hw->width_aspect_ratio);
6562 ar = min_t(u32,
6563 hw->h264_ar,
6564 DISP_RATIO_ASPECT_RATIO_MAX);
6565 vstatus->ratio_control =
6566 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6567
6568 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6569 "%s-%02d", DRIVER_NAME, hw->id);
6570
6571 return 0;
6572}
6573
6574static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6575{
6576 int i, j;
6577 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6578
6579 /* if (hw->init_flag == 0) { */
6580 if (h264_debug_flag & 0x40000000) {
6581 /* if (1) */
6582 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6583 "%s, reset register\n", __func__);
6584
6585 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6586 ;
6587 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6588 ; /* reg address is 0x350 */
6589
6590#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6591 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6592 WRITE_VREG(DOS_SW_RESET0, 0);
6593
6594 READ_VREG(DOS_SW_RESET0);
6595 READ_VREG(DOS_SW_RESET0);
6596 READ_VREG(DOS_SW_RESET0);
6597
6598 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6599 WRITE_VREG(DOS_SW_RESET0, 0);
6600
6601 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6602 WRITE_VREG(DOS_SW_RESET0, 0);
6603
6604 READ_VREG(DOS_SW_RESET0);
6605 READ_VREG(DOS_SW_RESET0);
6606 READ_VREG(DOS_SW_RESET0);
6607
6608#else
6609 WRITE_RESET_REG(RESET0_REGISTER,
6610 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6611 READ_RESET_REG(RESET0_REGISTER);
6612 WRITE_RESET_REG(RESET0_REGISTER,
6613 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6614
6615 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6616#endif
6617 WRITE_VREG(POWER_CTL_VLD,
6618 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6619 (1 << 9) | (1 << 6));
6620 } else {
6621 /* WRITE_VREG(POWER_CTL_VLD,
6622 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6623 */
6624 WRITE_VREG(POWER_CTL_VLD,
6625 READ_VREG(POWER_CTL_VLD) |
6626 (0 << 10) | (1 << 9) | (1 << 6));
6627 }
6628 /* disable PSCALE for hardware sharing */
6629 WRITE_VREG(PSCALE_CTRL, 0);
6630
6631 /* clear mailbox interrupt */
6632 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6633
6634 /* enable mailbox interrupt */
6635 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6636
6637#ifdef NV21
6638 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6639#endif
6640
6641 /* cbcr_merge_swap_en */
6642 if (hw->is_used_v4l
6643 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6644 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6645 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6646
6647 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6648 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6649
6650 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6651 if (hw->mmu_enable) {
6652 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6653 /* sw reset to extif hardware */
6654 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6655 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6656 } else {
6657 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6658 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6659 }
6660
6661
6662#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6663 /* pr_info("vh264 meson8 prot init\n"); */
6664 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6665#endif
6666
6667#ifdef VDEC_DW
6668 if (IS_VDEC_DW(hw)) {
6669 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6670
6671 if (IS_VDEC_DW(hw) == 2)
6672 data |= (1 << 9);
6673 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6674 }
6675#endif
6676 if (hw->dpb.mDPB.size > 0) {
6677 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6678 (hw->dpb.mDPB.size << 16) |
6679 (hw->dpb.mDPB.size << 8));
6680
6681 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6682 i = get_buf_spec_by_canvas_pos(hw, j);
6683 if (i < 0)
6684 break;
6685
6686 if (!hw->mmu_enable &&
6687 hw->buffer_spec[i].cma_alloc_addr)
6688 config_decode_canvas(hw, i);
6689 if (hw->mmu_enable && hw->double_write_mode)
6690 config_decode_canvas_ex(hw, i);
6691 }
6692 } else {
6693 WRITE_VREG(AV_SCRATCH_0, 0);
6694 WRITE_VREG(AV_SCRATCH_9, 0);
6695 }
6696
6697 if (hw->init_flag == 0)
6698 WRITE_VREG(DPB_STATUS_REG, 0);
6699 else
6700 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6701
6702 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6703 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6704 if (!tee_enabled())
6705 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6706
6707 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6708 * error_recovery_mode : error_recovery_mode_in;
6709 */
6710 /* WRITE_VREG(AV_SCRATCH_F,
6711 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6712 */
6713 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6714 ((error_recovery_mode_in & 0x1) << 4));
6715 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6716 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6717 else*/
6718 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6719
6720 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6721#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6722 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6723#endif
6724
6725 WRITE_VREG(DEBUG_REG1, 0);
6726 WRITE_VREG(DEBUG_REG2, 0);
6727
6728 if (hw->reg_iqidct_control)
6729 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6730 if (hw->reg_vcop_ctrl_reg)
6731 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6732 if (hw->vld_dec_control)
6733 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6734 return 0;
6735}
6736
6737static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6738{
6739 struct vdec_h264_hw_s *hw =
6740 (struct vdec_h264_hw_s *)vdec->private;
6741 if (i_only_flag & 0x100)
6742 return 0;
6743 if (trickmode == TRICKMODE_I)
6744 hw->i_only = 0x3;
6745 else if (trickmode == TRICKMODE_NONE)
6746 hw->i_only = 0x0;
6747 return 0;
6748}
6749
6750static unsigned char amvdec_enable_flag;
6751static void vh264_local_init(struct vdec_h264_hw_s *hw)
6752{
6753 int i;
6754 hw->init_flag = 0;
6755 hw->first_sc_checked= 0;
6756 hw->eos = 0;
6757 hw->valve_count = 0;
6758 hw->config_bufmgr_done = 0;
6759 hw->start_process_time = 0;
6760 hw->has_i_frame = 0;
6761 hw->no_error_count = 0xfff;
6762 hw->no_error_i_count = 0xf;
6763
6764 hw->dec_flag = 0;
6765 hw->data_flag = 0;
6766 hw->skip_frame_count = 0;
6767 hw->reg_iqidct_control = 0;
6768 hw->reg_vcop_ctrl_reg = 0;
6769 hw->reg_rv_ai_mb_count = 0;
6770 hw->vld_dec_control = 0;
6771 hw->decode_timeout_count = 0;
6772 hw->no_mem_count = 0;
6773 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6774 /* vh264_ratio = 0x100; */
6775
6776 hw->vh264_rotation = (((unsigned long)
6777 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6778
6779 hw->frame_prog = 0;
6780 hw->frame_width = hw->vh264_amstream_dec_info.width;
6781 hw->frame_height = hw->vh264_amstream_dec_info.height;
6782 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6783 hw->pts_outside = ((unsigned long)
6784 hw->vh264_amstream_dec_info.param) & 0x01;
6785 hw->sync_outside = ((unsigned long)
6786 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6787 hw->use_idr_framerate = ((unsigned long)
6788 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6789 hw->max_refer_buf = !(((unsigned long)
6790 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6791 if (hw->frame_dur < 96000/960) {
6792 /*more than 960fps,it should not be a correct value,
6793 *give default 30fps
6794 */
6795 hw->frame_dur = 96000/30;
6796 }
6797
6798 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6799
6800 hw->first_i_policy = first_i_policy;
6801
6802 if (hw->is_used_v4l)
6803 mem_map_mode = CANVAS_BLKMODE_LINEAR;
6804
6805 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6806 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6807 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6808 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6809
6810 if (i_only_flag & 0x100)
6811 hw->i_only = i_only_flag & 0xff;
6812 if (hw->i_only)
6813 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6814
6815 if ((unsigned long) hw->vh264_amstream_dec_info.param
6816 & 0x08)
6817 hw->no_poc_reorder_flag = 1;
6818
6819 error_recovery_mode_in = 1; /*ucode control?*/
6820 if (error_proc_policy & 0x80000000)
6821 hw->send_error_frame_flag = error_proc_policy & 0x1;
6822 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6823 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6824
6825 INIT_KFIFO(hw->display_q);
6826 INIT_KFIFO(hw->newframe_q);
6827
6828 for (i = 0; i < VF_POOL_SIZE; i++) {
6829 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6830 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6831 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6832 kfifo_put(&hw->newframe_q, vf);
6833 }
6834
6835 hw->duration_from_pts_done = 0;
6836
6837 hw->p_last_vf = NULL;
6838 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6839 hw->hevc_cur_buf_idx = 0xffff;
6840
6841 init_waitqueue_head(&hw->wait_q);
6842
6843 return;
6844}
6845
6846static s32 vh264_init(struct vdec_h264_hw_s *hw)
6847{
6848 int size = -1;
6849 int fw_size = 0x1000 * 16;
6850 int fw_mmu_size = 0x1000 * 16;
6851 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6852
6853 /* int trickmode_fffb = 0; */
6854
6855 /* pr_info("\nvh264_init\n"); */
6856 /* init_timer(&hw->recycle_timer); */
6857
6858 /* timer init */
6859 init_timer(&hw->check_timer);
6860
6861 hw->check_timer.data = (unsigned long)hw;
6862 hw->check_timer.function = check_timer_func;
6863 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6864
6865 /* add_timer(&hw->check_timer); */
6866 hw->stat |= STAT_TIMER_ARM;
6867 hw->stat |= STAT_ISR_REG;
6868
6869 mutex_init(&hw->chunks_mutex);
6870 vh264_local_init(hw);
6871 INIT_WORK(&hw->work, vh264_work);
6872 INIT_WORK(&hw->notify_work, vh264_notify_work);
6873 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6874#ifdef MH264_USERDATA_ENABLE
6875 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6876#endif
6877
6878 if (!amvdec_enable_flag) {
6879 amvdec_enable_flag = true;
6880 amvdec_enable();
6881 if (hw->mmu_enable)
6882 amhevc_enable();
6883 }
6884 if (hw->mmu_enable) {
6885
6886 hw->frame_mmu_map_addr =
6887 dma_alloc_coherent(amports_get_dma_device(),
6888 FRAME_MMU_MAP_SIZE,
6889 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6890 if (hw->frame_mmu_map_addr == NULL) {
6891 pr_err("%s: failed to alloc count_buffer\n", __func__);
6892 return -ENOMEM;
6893 }
6894 }
6895
6896 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6897 if (IS_ERR_OR_NULL(fw))
6898 return -ENOMEM;
6899
6900 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6901 if (size < 0) {
6902 pr_err("get firmware fail.\n");
6903 vfree(fw);
6904 return -1;
6905 }
6906
6907 fw->len = size;
6908 hw->fw = fw;
6909
6910 if (hw->mmu_enable) {
6911 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6912 if (IS_ERR_OR_NULL(fw_mmu))
6913 return -ENOMEM;
6914
6915 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6916 if (size < 0) {
6917 pr_err("get mmu fw fail.\n");
6918 vfree(fw_mmu);
6919 return -1;
6920 }
6921
6922 fw_mmu->len = size;
6923 hw->fw_mmu = fw_mmu;
6924 }
6925
6926 if (!tee_enabled()) {
6927 /* -- ucode loading (amrisc and swap code) */
6928 hw->mc_cpu_addr =
6929 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6930 &hw->mc_dma_handle, GFP_KERNEL);
6931 if (!hw->mc_cpu_addr) {
6932 amvdec_enable_flag = false;
6933 amvdec_disable();
6934 if (hw->mmu_enable)
6935 amhevc_disable();
6936 pr_info("vh264_init: Can not allocate mc memory.\n");
6937 return -ENOMEM;
6938 }
6939
6940 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6941 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6942 */
6943
6944 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6945
6946 /*header*/
6947 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6948 fw->data + 0x4000, MC_SWAP_SIZE);
6949 /*data*/
6950 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6951 fw->data + 0x2000, MC_SWAP_SIZE);
6952 /*mmco*/
6953 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6954 fw->data + 0x6000, MC_SWAP_SIZE);
6955 /*list*/
6956 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6957 fw->data + 0x3000, MC_SWAP_SIZE);
6958 /*slice*/
6959 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6960 fw->data + 0x5000, MC_SWAP_SIZE);
6961 /*main*/
6962 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6963 fw->data, 0x2000);
6964 /*data*/
6965 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6966 fw->data + 0x2000, 0x1000);
6967 /*slice*/
6968 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6969 fw->data + 0x5000, 0x1000);
6970 }
6971
6972#if 1 /* #ifdef BUFFER_MGR_IN_C */
6973 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6974 if (!hw->lmem_addr) {
6975 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6976 return -ENOMEM;
6977 } else {
6978 hw->lmem_addr_remap = dma_map_single(
6979 amports_get_dma_device(),
6980 (void *)hw->lmem_addr,
6981 PAGE_SIZE, DMA_FROM_DEVICE);
6982 if (dma_mapping_error(amports_get_dma_device(),
6983 hw->lmem_addr_remap)) {
6984 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6985 "%s: failed to map lmem_addr\n", __func__);
6986 free_page(hw->lmem_addr);
6987 hw->lmem_addr = 0;
6988 hw->lmem_addr_remap = 0;
6989 return -ENOMEM;
6990 }
6991
6992 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6993 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6994 }
6995
6996 if (prefix_aux_buf_size > 0 ||
6997 suffix_aux_buf_size > 0) {
6998 u32 aux_buf_size;
6999 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7000 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7001 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7002 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7003 if (hw->aux_addr == NULL) {
7004 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7005 return -1;
7006 }
7007
7008 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7009 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7010 if (dma_mapping_error(amports_get_dma_device(),
7011 hw->aux_phy_addr)) {
7012 pr_err("%s: failed to map rpm buffer\n", __func__);
7013 kfree(hw->aux_addr);
7014 hw->aux_addr = NULL;
7015 return -1;
7016 }
7017 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7018 if (hw->sei_data_buf == NULL) {
7019 pr_err("%s: failed to alloc sei itu data buffer\n",
7020 __func__);
7021 return -1;
7022 }
7023 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7024 if (hw->sei_itu_data_buf == NULL) {
7025 pr_err("%s: failed to alloc sei itu data buffer\n",
7026 __func__);
7027 kfree(hw->aux_addr);
7028 hw->aux_addr = NULL;
7029 kfree(hw->sei_data_buf);
7030 hw->sei_data_buf = NULL;
7031
7032 return -1;
7033 }
7034
7035 if (NULL == hw->sei_user_data_buffer) {
7036 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7037 GFP_KERNEL);
7038 if (!hw->sei_user_data_buffer) {
7039 pr_info("%s: Can not allocate sei_data_buffer\n",
7040 __func__);
7041 kfree(hw->aux_addr);
7042 hw->aux_addr = NULL;
7043 kfree(hw->sei_data_buf);
7044 hw->sei_data_buf = NULL;
7045 kfree(hw->sei_itu_data_buf);
7046 hw->sei_itu_data_buf = NULL;
7047
7048 return -1;
7049 }
7050 hw->sei_user_data_wp = 0;
7051 }
7052 }
7053/* BUFFER_MGR_IN_C */
7054#endif
7055 hw->stat |= STAT_MC_LOAD;
7056
7057 /* add memory barrier */
7058 wmb();
7059
7060 return 0;
7061}
7062
7063static int vh264_stop(struct vdec_h264_hw_s *hw)
7064{
7065 if (hw->stat & STAT_VDEC_RUN) {
7066 amvdec_stop();
7067 hw->stat &= ~STAT_VDEC_RUN;
7068 }
7069#ifdef VDEC_DW
7070 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7071#endif
7072#ifdef MH264_USERDATA_ENABLE
7073 cancel_work_sync(&hw->user_data_ready_work);
7074#endif
7075 cancel_work_sync(&hw->notify_work);
7076 cancel_work_sync(&hw->timeout_work);
7077 cancel_work_sync(&hw->work);
7078
7079
7080 if (hw->stat & STAT_MC_LOAD) {
7081 if (hw->mc_cpu_addr != NULL) {
7082 dma_free_coherent(amports_get_dma_device(),
7083 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7084 hw->mc_dma_handle);
7085 hw->mc_cpu_addr = NULL;
7086 }
7087 if (hw->frame_mmu_map_addr != NULL) {
7088 dma_free_coherent(amports_get_dma_device(),
7089 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7090 hw->frame_mmu_map_phy_addr);
7091 hw->frame_mmu_map_addr = NULL;
7092 }
7093
7094 }
7095 if (hw->stat & STAT_ISR_REG) {
7096 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7097 hw->stat &= ~STAT_ISR_REG;
7098 }
7099 if (hw->lmem_addr_remap) {
7100 dma_unmap_single(amports_get_dma_device(),
7101 hw->lmem_addr_remap,
7102 PAGE_SIZE, DMA_FROM_DEVICE);
7103 hw->lmem_addr_remap = 0;
7104 }
7105 if (hw->lmem_addr) {
7106 free_page(hw->lmem_addr);
7107 hw->lmem_addr = 0;
7108 }
7109 if (hw->aux_addr) {
7110 dma_unmap_single(amports_get_dma_device(),
7111 hw->aux_phy_addr,
7112 hw->prefix_aux_size + hw->suffix_aux_size,
7113 DMA_FROM_DEVICE);
7114 kfree(hw->aux_addr);
7115 hw->aux_addr = NULL;
7116 }
7117 if (hw->sei_data_buf != NULL) {
7118 kfree(hw->sei_data_buf);
7119 hw->sei_data_buf = NULL;
7120 }
7121 if (hw->sei_itu_data_buf != NULL) {
7122 kfree(hw->sei_itu_data_buf);
7123 hw->sei_itu_data_buf = NULL;
7124 }
7125 if (hw->sei_user_data_buffer != NULL) {
7126 kfree(hw->sei_user_data_buffer);
7127 hw->sei_user_data_buffer = NULL;
7128 }
7129 /* amvdec_disable(); */
7130
7131 vfree(hw->fw);
7132 hw->fw = NULL;
7133
7134 if (hw->mmu_enable) {
7135 vfree(hw->fw_mmu);
7136 hw->fw_mmu = NULL;
7137 }
7138
7139 dpb_print(DECODE_ID(hw), 0,
7140 "%s\n",
7141 __func__);
7142 return 0;
7143}
7144
7145static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7146{
7147 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7148 int count = 0;
7149 do {
7150 usleep_range(100, 500);
7151 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7152 break;
7153 if (count > 2000) {
7154 dpb_print(DECODE_ID(hw),
7155 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7156 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7157 break;
7158 } else
7159 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7160 count++;
7161 } while (1);
7162}
7163
7164static void vh264_notify_work(struct work_struct *work)
7165{
7166 struct vdec_h264_hw_s *hw = container_of(work,
7167 struct vdec_h264_hw_s, notify_work);
7168 struct vdec_s *vdec = hw_to_vdec(hw);
7169 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7170 vf_notify_receiver(vdec->vf_provider_name,
7171 VFRAME_EVENT_PROVIDER_FR_HINT,
7172 (void *)((unsigned long)hw->frame_dur));
7173 vdec->fr_hint_state = VDEC_HINTED;
7174 }
7175
7176 return;
7177}
7178
7179#ifdef MH264_USERDATA_ENABLE
7180static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7181{
7182 hw->wait_for_udr_send = 0;
7183 hw->sei_itu_data_len = 0;
7184 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7185}
7186
7187static void vmh264_crate_userdata_manager(
7188 struct vdec_h264_hw_s *hw,
7189 u8 *userdata_buf,
7190 int buf_len)
7191{
7192 if (hw) {
7193
7194
7195 mutex_init(&hw->userdata_mutex);
7196
7197 memset(&hw->userdata_info, 0,
7198 sizeof(struct mh264_userdata_info_t));
7199 hw->userdata_info.data_buf = userdata_buf;
7200 hw->userdata_info.buf_len = buf_len;
7201 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7202
7203 vmh264_reset_udr_mgr(hw);
7204
7205 }
7206}
7207
7208static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7209{
7210 if (hw)
7211 memset(&hw->userdata_info,
7212 0,
7213 sizeof(struct mh264_userdata_info_t));
7214}
7215
7216/*
7217#define DUMP_USERDATA_RECORD
7218*/
7219#ifdef DUMP_USERDATA_RECORD
7220
7221#define MAX_USER_DATA_SIZE 3145728
7222static void *user_data_buf;
7223static unsigned char *pbuf_start;
7224static int total_len;
7225static int bskip;
7226static int n_userdata_id;
7227
7228static void print_data(unsigned char *pdata,
7229 int len,
7230 unsigned int poc_number,
7231 unsigned int flag,
7232 unsigned int duration,
7233 unsigned int vpts,
7234 unsigned int vpts_valid,
7235 int rec_id)
7236{
7237 int nLeft;
7238
7239 nLeft = len;
7240#if 0
7241 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7242 rec_id, len, flag,
7243 duration, vpts, vpts_valid, poc_number);
7244#endif
7245 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7246 rec_id, len, flag, vpts);
7247
7248 if (len == 96) {
7249 int i;
7250 nLeft = 72;
7251 while (nLeft >= 16) {
7252 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7253 pdata[0], pdata[1], pdata[2], pdata[3],
7254 pdata[4], pdata[5], pdata[6], pdata[7],
7255 pdata[8], pdata[9], pdata[10], pdata[11],
7256 pdata[12], pdata[13], pdata[14], pdata[15]);
7257 nLeft -= 16;
7258 pdata += 16;
7259 }
7260
7261
7262 while (nLeft > 0) {
7263 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7264 pdata[0], pdata[1], pdata[2], pdata[3],
7265 pdata[4], pdata[5], pdata[6], pdata[7]);
7266 nLeft -= 8;
7267 pdata += 8;
7268 }
7269
7270 i = 0;
7271 nLeft = 96-72;
7272 while (i < nLeft) {
7273 if (pdata[0] != 0) {
7274 pr_info("some data error\n");
7275 break;
7276 }
7277 pdata++;
7278 i++;
7279 }
7280 } else {
7281 while (nLeft >= 16) {
7282 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7283 pdata[0], pdata[1], pdata[2], pdata[3],
7284 pdata[4], pdata[5], pdata[6], pdata[7],
7285 pdata[8], pdata[9], pdata[10], pdata[11],
7286 pdata[12], pdata[13], pdata[14], pdata[15]);
7287 nLeft -= 16;
7288 pdata += 16;
7289 }
7290
7291
7292 while (nLeft > 0) {
7293 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7294 pdata[0], pdata[1], pdata[2], pdata[3],
7295 pdata[4], pdata[5], pdata[6], pdata[7]);
7296 nLeft -= 8;
7297 pdata += 8;
7298 }
7299
7300 }
7301}
7302
7303static void push_to_buf(struct vdec_h264_hw_s *hw,
7304 u8 *pdata,
7305 int len,
7306 struct userdata_meta_info_t *pmeta);
7307
7308static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7309 struct mh264_userdata_record_t *record)
7310{
7311 if (record && hw) {
7312 u8 *pdata;
7313
7314 pdata = hw->userdata_info.data_buf + record->rec_start;
7315/*
7316 print_data(pdata,
7317 record->rec_len,
7318 record->meta_info.flags,
7319 record->meta_info.duration,
7320 record->meta_info.vpts,
7321 record->meta_info.vpts_valid,
7322 n_record_id);
7323*/
7324 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7325 n_userdata_id++;
7326 }
7327}
7328
7329
7330static void push_to_buf(struct vdec_h264_hw_s *hw,
7331 u8 *pdata, int len,
7332 struct userdata_meta_info_t *pmeta)
7333{
7334 u32 *pLen;
7335 int info_cnt;
7336 u8 *pbuf_end;
7337
7338 if (!user_data_buf)
7339 return;
7340
7341 if (bskip) {
7342 pr_info("over size, skip\n");
7343 return;
7344 }
7345 info_cnt = 0;
7346 pLen = (u32 *)pbuf_start;
7347
7348 *pLen = len;
7349 pbuf_start += sizeof(u32);
7350 info_cnt++;
7351 pLen++;
7352
7353 *pLen = pmeta->poc_number;
7354 pbuf_start += sizeof(u32);
7355 info_cnt++;
7356 pLen++;
7357
7358 *pLen = pmeta->duration;
7359 pbuf_start += sizeof(u32);
7360 info_cnt++;
7361 pLen++;
7362
7363 *pLen = pmeta->flags;
7364 pbuf_start += sizeof(u32);
7365 info_cnt++;
7366 pLen++;
7367
7368 *pLen = pmeta->vpts;
7369 pbuf_start += sizeof(u32);
7370 info_cnt++;
7371 pLen++;
7372
7373 *pLen = pmeta->vpts_valid;
7374 pbuf_start += sizeof(u32);
7375 info_cnt++;
7376 pLen++;
7377
7378
7379 *pLen = n_userdata_id;
7380 pbuf_start += sizeof(u32);
7381 info_cnt++;
7382 pLen++;
7383
7384
7385
7386 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7387 if (pdata + len > pbuf_end) {
7388 int first_section_len;
7389
7390 first_section_len = pbuf_end - pdata;
7391 memcpy(pbuf_start, pdata, first_section_len);
7392 pdata = (u8 *)hw->sei_user_data_buffer;
7393 pbuf_start += first_section_len;
7394 memcpy(pbuf_start, pdata, len - first_section_len);
7395 pbuf_start += len - first_section_len;
7396 } else {
7397 memcpy(pbuf_start, pdata, len);
7398 pbuf_start += len;
7399 }
7400
7401 total_len += len + info_cnt * sizeof(u32);
7402 if (total_len >= MAX_USER_DATA_SIZE-4096)
7403 bskip = 1;
7404}
7405
7406static void show_user_data_buf(void)
7407{
7408 u8 *pbuf;
7409 int len;
7410 unsigned int flag;
7411 unsigned int duration;
7412 unsigned int vpts;
7413 unsigned int vpts_valid;
7414 unsigned int poc_number;
7415 int rec_id;
7416
7417 pr_info("show user data buf\n");
7418 pbuf = user_data_buf;
7419
7420 while (pbuf < pbuf_start) {
7421 u32 *pLen;
7422
7423 pLen = (u32 *)pbuf;
7424
7425 len = *pLen;
7426 pLen++;
7427 pbuf += sizeof(u32);
7428
7429 poc_number = *pLen;
7430 pLen++;
7431 pbuf += sizeof(u32);
7432
7433 duration = *pLen;
7434 pLen++;
7435 pbuf += sizeof(u32);
7436
7437 flag = *pLen;
7438 pLen++;
7439 pbuf += sizeof(u32);
7440
7441 vpts = *pLen;
7442 pLen++;
7443 pbuf += sizeof(u32);
7444
7445 vpts_valid = *pLen;
7446 pLen++;
7447 pbuf += sizeof(u32);
7448
7449 rec_id = *pLen;
7450 pLen++;
7451 pbuf += sizeof(u32);
7452
7453 print_data(pbuf, len, poc_number, flag,
7454 duration, vpts,
7455 vpts_valid, rec_id);
7456 pbuf += len;
7457 msleep(30);
7458 }
7459}
7460
7461static int vmh264_init_userdata_dump(void)
7462{
7463 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7464 if (user_data_buf)
7465 return 1;
7466 else
7467 return 0;
7468}
7469
7470static void vmh264_dump_userdata(void)
7471{
7472 if (user_data_buf) {
7473 show_user_data_buf();
7474 kfree(user_data_buf);
7475 user_data_buf = NULL;
7476 }
7477}
7478
7479static void vmh264_reset_user_data_buf(void)
7480{
7481 total_len = 0;
7482 pbuf_start = user_data_buf;
7483 bskip = 0;
7484 n_userdata_id = 0;
7485}
7486#endif
7487
7488
7489static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7490 int frame_type,
7491 u32 vpts,
7492 u32 vpts_valid)
7493{
7494 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7495
7496 unsigned char *pdata;
7497 u8 *pmax_sei_data_buffer;
7498 u8 *sei_data_buf;
7499 int i;
7500 int wp;
7501 int data_length;
7502 struct mh264_userdata_record_t *p_userdata_rec;
7503
7504
7505#ifdef MH264_USERDATA_ENABLE
7506 struct userdata_meta_info_t meta_info;
7507 memset(&meta_info, 0, sizeof(meta_info));
7508#endif
7509
7510 if (hw->sei_itu_data_len <= 0)
7511 return;
7512
7513 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7514 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7515 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7516 for (i = 0; i < hw->sei_itu_data_len; i++) {
7517 *pdata++ = sei_data_buf[i];
7518 if (pdata >= pmax_sei_data_buffer)
7519 pdata = (u8 *)hw->sei_user_data_buffer;
7520 }
7521
7522 hw->sei_user_data_wp = (hw->sei_user_data_wp
7523 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7524 hw->sei_itu_data_len = 0;
7525
7526#ifdef MH264_USERDATA_ENABLE
7527 meta_info.duration = hw->frame_dur;
7528 meta_info.flags |= (VFORMAT_H264 << 3);
7529
7530 meta_info.vpts = vpts;
7531 meta_info.vpts_valid = vpts_valid;
7532 meta_info.poc_number =
7533 p_H264_Dpb->mVideo.dec_picture->poc;
7534
7535
7536 wp = hw->sei_user_data_wp;
7537
7538 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7539 data_length = wp - hw->userdata_info.last_wp;
7540 else
7541 data_length = wp + hw->userdata_info.buf_len
7542 - hw->userdata_info.last_wp;
7543
7544 if (data_length & 0x7)
7545 data_length = (((data_length + 8) >> 3) << 3);
7546
7547 p_userdata_rec = &hw->ud_record;
7548 p_userdata_rec->meta_info = meta_info;
7549 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7550 p_userdata_rec->rec_len = data_length;
7551 hw->userdata_info.last_wp = wp;
7552
7553 p_userdata_rec->meta_info.flags |=
7554 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7555
7556 hw->wait_for_udr_send = 1;
7557 vdec_schedule_work(&hw->user_data_ready_work);
7558#endif
7559}
7560
7561
7562static void user_data_ready_notify_work(struct work_struct *work)
7563{
7564 struct vdec_h264_hw_s *hw = container_of(work,
7565 struct vdec_h264_hw_s, user_data_ready_work);
7566
7567
7568 mutex_lock(&hw->userdata_mutex);
7569
7570 hw->userdata_info.records[hw->userdata_info.write_index]
7571 = hw->ud_record;
7572 hw->userdata_info.write_index++;
7573 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7574 hw->userdata_info.write_index = 0;
7575
7576 mutex_unlock(&hw->userdata_mutex);
7577
7578#ifdef DUMP_USERDATA_RECORD
7579 dump_userdata_record(hw, &hw->ud_record);
7580#endif
7581 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7582
7583 hw->wait_for_udr_send = 0;
7584}
7585
7586static int vmh264_user_data_read(struct vdec_s *vdec,
7587 struct userdata_param_t *puserdata_para)
7588{
7589 struct vdec_h264_hw_s *hw = NULL;
7590 int rec_ri, rec_wi;
7591 int rec_len;
7592 u8 *rec_data_start;
7593 u8 *pdest_buf;
7594 struct mh264_userdata_record_t *p_userdata_rec;
7595 u32 data_size;
7596 u32 res;
7597 int copy_ok = 1;
7598
7599 hw = (struct vdec_h264_hw_s *)vdec->private;
7600
7601 pdest_buf = puserdata_para->pbuf_addr;
7602
7603 mutex_lock(&hw->userdata_mutex);
7604
7605/*
7606 pr_info("ri = %d, wi = %d\n",
7607 lg_p_mpeg12_userdata_info->read_index,
7608 lg_p_mpeg12_userdata_info->write_index);
7609*/
7610 rec_ri = hw->userdata_info.read_index;
7611 rec_wi = hw->userdata_info.write_index;
7612
7613 if (rec_ri == rec_wi) {
7614 mutex_unlock(&hw->userdata_mutex);
7615 return 0;
7616 }
7617
7618 p_userdata_rec = hw->userdata_info.records + rec_ri;
7619
7620 rec_len = p_userdata_rec->rec_len;
7621 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7622/*
7623 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7624 p_userdata_rec->rec_len,
7625 p_userdata_rec->rec_start,
7626 puserdata_para->buf_len);
7627*/
7628 if (rec_len <= puserdata_para->buf_len) {
7629 /* dvb user data buffer is enought to
7630 copy the whole recored. */
7631 data_size = rec_len;
7632 if (rec_data_start + data_size
7633 > hw->userdata_info.data_buf_end) {
7634 int first_section_len;
7635
7636 first_section_len = hw->userdata_info.buf_len -
7637 p_userdata_rec->rec_start;
7638 res = (u32)copy_to_user((void *)pdest_buf,
7639 (void *)rec_data_start,
7640 first_section_len);
7641 if (res) {
7642 pr_info("p1 read not end res=%d, request=%d\n",
7643 res, first_section_len);
7644 copy_ok = 0;
7645
7646 p_userdata_rec->rec_len -=
7647 first_section_len - res;
7648 p_userdata_rec->rec_start +=
7649 first_section_len - res;
7650 puserdata_para->data_size =
7651 first_section_len - res;
7652 } else {
7653 res = (u32)copy_to_user(
7654 (void *)(pdest_buf+first_section_len),
7655 (void *)hw->userdata_info.data_buf,
7656 data_size - first_section_len);
7657 if (res) {
7658 pr_info("p2 read not end res=%d, request=%d\n",
7659 res, data_size);
7660 copy_ok = 0;
7661 }
7662 p_userdata_rec->rec_len -=
7663 data_size - res;
7664 p_userdata_rec->rec_start =
7665 data_size - first_section_len - res;
7666 puserdata_para->data_size =
7667 data_size - res;
7668 }
7669 } else {
7670 res = (u32)copy_to_user((void *)pdest_buf,
7671 (void *)rec_data_start,
7672 data_size);
7673 if (res) {
7674 pr_info("p3 read not end res=%d, request=%d\n",
7675 res, data_size);
7676 copy_ok = 0;
7677 }
7678 p_userdata_rec->rec_len -= data_size - res;
7679 p_userdata_rec->rec_start += data_size - res;
7680 puserdata_para->data_size = data_size - res;
7681 }
7682
7683 if (copy_ok) {
7684 hw->userdata_info.read_index++;
7685 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7686 hw->userdata_info.read_index = 0;
7687 }
7688 } else {
7689 /* dvb user data buffer is not enought
7690 to copy the whole recored. */
7691 data_size = puserdata_para->buf_len;
7692 if (rec_data_start + data_size
7693 > hw->userdata_info.data_buf_end) {
7694 int first_section_len;
7695
7696 first_section_len = hw->userdata_info.buf_len -
7697 p_userdata_rec->rec_start;
7698 res = (u32)copy_to_user((void *)pdest_buf,
7699 (void *)rec_data_start,
7700 first_section_len);
7701 if (res) {
7702 pr_info("p4 read not end res=%d, request=%d\n",
7703 res, first_section_len);
7704 copy_ok = 0;
7705 p_userdata_rec->rec_len -=
7706 first_section_len - res;
7707 p_userdata_rec->rec_start +=
7708 first_section_len - res;
7709 puserdata_para->data_size =
7710 first_section_len - res;
7711 } else {
7712 /* first secton copy is ok*/
7713 res = (u32)copy_to_user(
7714 (void *)(pdest_buf+first_section_len),
7715 (void *)hw->userdata_info.data_buf,
7716 data_size - first_section_len);
7717 if (res) {
7718 pr_info("p5 read not end res=%d, request=%d\n",
7719 res,
7720 data_size - first_section_len);
7721 copy_ok = 0;
7722 }
7723
7724 p_userdata_rec->rec_len -=
7725 data_size - res;
7726 p_userdata_rec->rec_start =
7727 data_size - first_section_len - res;
7728 puserdata_para->data_size =
7729 data_size - res;
7730 }
7731 } else {
7732 res = (u32)copy_to_user((void *)pdest_buf,
7733 (void *)rec_data_start,
7734 data_size);
7735 if (res) {
7736 pr_info("p6 read not end res=%d, request=%d\n",
7737 res, data_size);
7738 copy_ok = 0;
7739 }
7740
7741 p_userdata_rec->rec_len -= data_size - res;
7742 p_userdata_rec->rec_start += data_size - res;
7743 puserdata_para->data_size = data_size - res;
7744 }
7745
7746 if (copy_ok) {
7747 hw->userdata_info.read_index++;
7748 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7749 hw->userdata_info.read_index = 0;
7750 }
7751
7752 }
7753 puserdata_para->meta_info = p_userdata_rec->meta_info;
7754
7755 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7756 puserdata_para->meta_info.records_in_que =
7757 hw->userdata_info.write_index -
7758 hw->userdata_info.read_index;
7759 else
7760 puserdata_para->meta_info.records_in_que =
7761 hw->userdata_info.write_index +
7762 USERDATA_FIFO_NUM -
7763 hw->userdata_info.read_index;
7764
7765 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7766
7767 mutex_unlock(&hw->userdata_mutex);
7768
7769 return 1;
7770}
7771
7772static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7773{
7774 struct vdec_h264_hw_s *hw = NULL;
7775
7776 hw = (struct vdec_h264_hw_s *)vdec->private;
7777
7778 if (hw) {
7779 mutex_lock(&hw->userdata_mutex);
7780 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7781 bInit,
7782 hw->userdata_info.read_index,
7783 hw->userdata_info.write_index);
7784 hw->userdata_info.read_index = 0;
7785 hw->userdata_info.write_index = 0;
7786
7787 if (bInit)
7788 hw->userdata_info.last_wp = 0;
7789 mutex_unlock(&hw->userdata_mutex);
7790 }
7791}
7792
7793static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7794{
7795 amstream_wakeup_userdata_poll(vdec);
7796}
7797
7798#endif
7799
7800
7801static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7802 struct vdec_s *vdec, int from)
7803{
7804 /* finished decoding one frame or error,
7805 * notify vdec core to switch context
7806 */
7807 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7808 "%s dec_result %d %x %x %x\n",
7809 __func__,
7810 hw->dec_result,
7811 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7812 READ_VREG(VLD_MEM_VIFIFO_WP),
7813 READ_VREG(VLD_MEM_VIFIFO_RP));
7814 if (!hw->mmu_enable) {
7815 mutex_lock(&vmh264_mutex);
7816 dealloc_buf_specs(hw, 0);
7817 mutex_unlock(&vmh264_mutex);
7818 }
7819 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7820 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7821 u32 param1 = READ_VREG(AV_SCRATCH_1);
7822 u32 param2 = READ_VREG(AV_SCRATCH_2);
7823 u32 param3 = READ_VREG(AV_SCRATCH_6);
7824 u32 param4 = READ_VREG(AV_SCRATCH_B);
7825
7826 if (vh264_set_params(hw, param1,
7827 param2, param3, param4) < 0)
7828 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7829
7830 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7831 (hw->dpb.mDPB.size<<16) |
7832 (hw->dpb.mDPB.size<<8));
7833
7834 if (hw->is_used_v4l) {
7835 struct aml_vcodec_ctx *ctx =
7836 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7837
7838 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7839 struct aml_vdec_pic_infos info;
7840
7841 info.visible_width = hw->frame_width;
7842 info.visible_height = hw->frame_height;
7843 info.coded_width = ALIGN(hw->frame_width, 64);
7844 info.coded_height = ALIGN(hw->frame_height, 64);
7845 info.dpb_size = hw->dpb.mDPB.size;
7846 hw->v4l_params_parsed = true;
7847 vdec_v4l_set_pic_infos(ctx, &info);
7848 }
7849 }
7850
7851 start_process_time(hw);
7852 return;
7853 } else
7854 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7855 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7856 && (hw_to_vdec(hw)->next_status !=
7857 VDEC_STATUS_DISCONNECTED)) {
7858 if (!vdec_has_more_input(vdec)) {
7859 hw->dec_result = DEC_RESULT_EOS;
7860 vdec_schedule_work(&hw->work);
7861 return;
7862 }
7863
7864 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7865 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7866 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7867 __func__,
7868 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7869 READ_VREG(VLD_MEM_VIFIFO_WP),
7870 READ_VREG(VLD_MEM_VIFIFO_RP));
7871 mutex_lock(&hw->chunks_mutex);
7872 vdec_vframe_dirty(vdec, hw->chunk);
7873 hw->chunk = NULL;
7874 mutex_unlock(&hw->chunks_mutex);
7875 vdec_clean_input(vdec);
7876 }
7877 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7878 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7879 > get_data_timeout_val)) {
7880 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7881 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7882 __func__);
7883 goto result_done;
7884 }
7885 if (is_buffer_available(vdec)) {
7886 int r;
7887 int decode_size;
7888 r = vdec_prepare_input(vdec, &hw->chunk);
7889 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7890 VDEC_STATUS_DISCONNECTED)) {
7891 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7892
7893 dpb_print(DECODE_ID(hw),
7894 PRINT_FLAG_VDEC_DETAIL,
7895 "vdec_prepare_input: Insufficient data\n");
7896 vdec_schedule_work(&hw->work);
7897 return;
7898 }
7899 hw->dec_result = DEC_RESULT_NONE;
7900 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7901 "%s: chunk size 0x%x\n",
7902 __func__, hw->chunk->size);
7903
7904 if (dpb_is_debug(DECODE_ID(hw),
7905 PRINT_FRAMEBASE_DATA)) {
7906 int jj;
7907 u8 *data = NULL;
7908
7909 if (!hw->chunk->block->is_mapped)
7910 data = codec_mm_vmap(
7911 hw->chunk->block->start +
7912 hw->chunk->offset, r);
7913 else
7914 data = ((u8 *)
7915 hw->chunk->block->start_virt)
7916 + hw->chunk->offset;
7917
7918 for (jj = 0; jj < r; jj++) {
7919 if ((jj & 0xf) == 0)
7920 dpb_print(DECODE_ID(hw),
7921 PRINT_FRAMEBASE_DATA,
7922 "%06x:", jj);
7923 dpb_print_cont(DECODE_ID(hw),
7924 PRINT_FRAMEBASE_DATA,
7925 "%02x ", data[jj]);
7926 if (((jj + 1) & 0xf) == 0)
7927 dpb_print_cont(DECODE_ID(hw),
7928 PRINT_FRAMEBASE_DATA,
7929 "\n");
7930 }
7931
7932 if (!hw->chunk->block->is_mapped)
7933 codec_mm_unmap_phyaddr(data);
7934 }
7935 WRITE_VREG(POWER_CTL_VLD,
7936 READ_VREG(POWER_CTL_VLD) |
7937 (0 << 10) | (1 << 9) | (1 << 6));
7938 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7939 decode_size = hw->chunk->size +
7940 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7941 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7942 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7943 vdec_enable_input(vdec);
7944
7945 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7946 start_process_time(hw);
7947 } else{
7948 if (hw_to_vdec(hw)->next_status
7949 != VDEC_STATUS_DISCONNECTED) {
7950 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7951 vdec_schedule_work(&hw->work);
7952 }
7953 }
7954 return;
7955 } else if (hw->dec_result == DEC_RESULT_DONE) {
7956 /* if (!hw->ctx_valid)
7957 hw->ctx_valid = 1; */
7958result_done:
7959 if (hw->mmu_enable
7960 && hw->frame_busy && hw->frame_done) {
7961 long used_4k_num;
7962 hevc_sao_wait_done(hw);
7963 if (hw->hevc_cur_buf_idx != 0xffff) {
7964 used_4k_num =
7965 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7966 if (used_4k_num >= 0)
7967 dpb_print(DECODE_ID(hw),
7968 PRINT_FLAG_MMU_DETAIL,
7969 "release unused buf , used_4k_num %ld index %d\n",
7970 used_4k_num, hw->hevc_cur_buf_idx);
7971 hevc_mmu_dma_check(hw_to_vdec(hw));
7972 decoder_mmu_box_free_idx_tail(
7973 hw->mmu_box,
7974 hw->hevc_cur_buf_idx,
7975 used_4k_num);
7976 hw->hevc_cur_buf_idx = 0xffff;
7977 }
7978 }
7979 decode_frame_count[DECODE_ID(hw)]++;
7980 amvdec_stop();
7981 if (!vdec_is_support_4k()) {
7982 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7983 clk_adj_frame_count++;
7984 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7985 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7986 }
7987 }
7988 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7989 "%s dec_result %d %x %x %x\n",
7990 __func__,
7991 hw->dec_result,
7992 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7993 READ_VREG(VLD_MEM_VIFIFO_WP),
7994 READ_VREG(VLD_MEM_VIFIFO_RP));
7995 mutex_lock(&hw->chunks_mutex);
7996 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7997 hw->chunk = NULL;
7998 mutex_unlock(&hw->chunks_mutex);
7999 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
8000 /*
8001 stream base: stream buf empty or timeout
8002 frame base: vdec_prepare_input fail
8003 */
8004 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8005 VDEC_STATUS_DISCONNECTED)) {
8006 hw->dec_result = DEC_RESULT_EOS;
8007 vdec_schedule_work(&hw->work);
8008 return;
8009 }
8010 hw->next_again_flag = 1;
8011 } else if (hw->dec_result == DEC_RESULT_EOS) {
8012 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8013 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8014 "%s: end of stream\n",
8015 __func__);
8016 amvdec_stop();
8017 if (hw->mmu_enable)
8018 amhevc_stop();
8019 hw->eos = 1;
8020 flush_dpb(p_H264_Dpb);
8021 if (hw->is_used_v4l)
8022 notify_v4l_eos(hw_to_vdec(hw));
8023 mutex_lock(&hw->chunks_mutex);
8024 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8025 hw->chunk = NULL;
8026 mutex_unlock(&hw->chunks_mutex);
8027 vdec_clean_input(vdec);
8028 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8029 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8030 "%s: force exit\n",
8031 __func__);
8032 amvdec_stop();
8033 if (hw->mmu_enable)
8034 amhevc_stop();
8035 if (hw->stat & STAT_ISR_REG) {
8036 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8037 hw->stat &= ~STAT_ISR_REG;
8038 }
8039 }
8040 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8041 del_timer_sync(&hw->check_timer);
8042 hw->stat &= ~STAT_TIMER_ARM;
8043
8044 wait_vmh264_search_done(hw);
8045 /* mark itself has all HW resource released and input released */
8046
8047#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8048 if (hw->switch_dvlayer_flag) {
8049 if (vdec->slave)
8050 vdec_set_next_sched(vdec, vdec->slave);
8051 else if (vdec->master)
8052 vdec_set_next_sched(vdec, vdec->master);
8053 } else if (vdec->slave || vdec->master)
8054 vdec_set_next_sched(vdec, vdec);
8055#endif
8056
8057 if (from == 1) {
8058 /* This is a timeout work */
8059 if (work_pending(&hw->work)) {
8060 /*
8061 * The vh264_work arrives at the last second,
8062 * give it a chance to handle the scenario.
8063 */
8064 return;
8065 }
8066 }
8067
8068 /* mark itself has all HW resource released and input released */
8069 if (vdec->parallel_dec == 1) {
8070 if (hw->mmu_enable == 0)
8071 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8072 else
8073 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8074 } else
8075 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8076
8077 wake_up_interruptible(&hw->wait_q);
8078
8079 if (hw->is_used_v4l) {
8080 struct aml_vcodec_ctx *ctx =
8081 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8082
8083 if (ctx->param_sets_from_ucode &&
8084 !hw->v4l_params_parsed)
8085 vdec_v4l_write_frame_sync(ctx);
8086 }
8087
8088 if (hw->vdec_cb)
8089 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8090}
8091
8092
8093static void vh264_work(struct work_struct *work)
8094{
8095 struct vdec_h264_hw_s *hw = container_of(work,
8096 struct vdec_h264_hw_s, work);
8097 struct vdec_s *vdec = hw_to_vdec(hw);
8098
8099 vh264_work_implement(hw, vdec, 0);
8100}
8101
8102
8103static void vh264_timeout_work(struct work_struct *work)
8104{
8105 struct vdec_h264_hw_s *hw = container_of(work,
8106 struct vdec_h264_hw_s, timeout_work);
8107 struct vdec_s *vdec = hw_to_vdec(hw);
8108
8109 if (work_pending(&hw->work))
8110 return;
8111
8112 vh264_work_implement(hw, vdec, 1);
8113}
8114
8115static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8116{
8117 bool ret = 0;
8118 struct vdec_h264_hw_s *hw =
8119 (struct vdec_h264_hw_s *)vdec->private;
8120 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8121 CODEC_MM_FLAGS_TVP : 0;
8122
8123 if (!hw->first_sc_checked && hw->mmu_enable) {
8124 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8125 hw->first_sc_checked =1;
8126 dpb_print(DECODE_ID(hw), 0,
8127 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8128 size, (hw->need_cache_size >> PAGE_SHIFT),
8129 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8130 }
8131
8132 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8133 && pre_decode_buf_level != 0) {
8134 u32 rp, wp, level;
8135
8136 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8137 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8138 if (wp < rp)
8139 level = vdec->input.size + wp - rp;
8140 else
8141 level = wp - rp;
8142
8143 if (level < pre_decode_buf_level)
8144 return 0;
8145 }
8146
8147#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8148 if (vdec->master)
8149 return 0;
8150#endif
8151 if (hw->eos)
8152 return 0;
8153
8154 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8155 return 0;
8156
8157 if (disp_vframe_valve_level &&
8158 kfifo_len(&hw->display_q) >=
8159 disp_vframe_valve_level) {
8160 hw->valve_count--;
8161 if (hw->valve_count <= 0)
8162 hw->valve_count = 2;
8163 else
8164 return 0;
8165 }
8166 if (hw->next_again_flag &&
8167 (!vdec_frame_based(vdec))) {
8168 u32 parser_wr_ptr =
8169 READ_PARSER_REG(PARSER_VIDEO_WP);
8170 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8171 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8172 again_threshold) {
8173 int r = vdec_sync_input(vdec);
8174 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8175 "%s buf lelvel:%x\n", __func__, r);
8176 return 0;
8177 }
8178 }
8179
8180 if (h264_debug_flag & 0x20000000) {
8181 /* pr_info("%s, a\n", __func__); */
8182 ret = 1;
8183 } else
8184 ret = is_buffer_available(vdec);
8185
8186#ifdef CONSTRAIN_MAX_BUF_NUM
8187 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8188 if (run_ready_max_vf_only_num > 0 &&
8189 get_vf_ref_only_buf_count(hw) >=
8190 run_ready_max_vf_only_num
8191 )
8192 ret = 0;
8193 if (run_ready_display_q_num > 0 &&
8194 kfifo_len(&hw->display_q) >=
8195 run_ready_display_q_num)
8196 ret = 0;
8197 /*avoid more buffers consumed when
8198 switching resolution*/
8199 if (run_ready_max_buf_num == 0xff &&
8200 get_used_buf_count(hw) >
8201 hw->dpb.mDPB.size)
8202 ret = 0;
8203 else if (run_ready_max_buf_num &&
8204 get_used_buf_count(hw) >=
8205 run_ready_max_buf_num)
8206 ret = 0;
8207
8208 if (hw->is_used_v4l) {
8209 struct aml_vcodec_ctx *ctx =
8210 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8211
8212 if (ctx->param_sets_from_ucode &&
8213 !ctx->v4l_codec_ready &&
8214 hw->v4l_params_parsed) {
8215 ret = 0; /*the params has parsed.*/
8216 } else if (!ctx->v4l_codec_dpb_ready)
8217 ret = 0;
8218 }
8219 }
8220#endif
8221 if (ret)
8222 not_run_ready[DECODE_ID(hw)] = 0;
8223 else
8224 not_run_ready[DECODE_ID(hw)]++;
8225 if (vdec->parallel_dec == 1) {
8226 if (hw->mmu_enable == 0)
8227 return ret ? (CORE_MASK_VDEC_1) : 0;
8228 else
8229 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8230 } else
8231 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8232}
8233
8234static unsigned char get_data_check_sum
8235 (struct vdec_h264_hw_s *hw, int size)
8236{
8237 int jj;
8238 int sum = 0;
8239 u8 *data = NULL;
8240
8241 if (!hw->chunk->block->is_mapped)
8242 data = codec_mm_vmap(hw->chunk->block->start +
8243 hw->chunk->offset, size);
8244 else
8245 data = ((u8 *)hw->chunk->block->start_virt)
8246 + hw->chunk->offset;
8247
8248 for (jj = 0; jj < size; jj++)
8249 sum += data[jj];
8250
8251 if (!hw->chunk->block->is_mapped)
8252 codec_mm_unmap_phyaddr(data);
8253 return sum;
8254}
8255
8256static void run(struct vdec_s *vdec, unsigned long mask,
8257 void (*callback)(struct vdec_s *, void *), void *arg)
8258{
8259 struct vdec_h264_hw_s *hw =
8260 (struct vdec_h264_hw_s *)vdec->private;
8261 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8262 int size, ret = -1;
8263
8264 run_count[DECODE_ID(hw)]++;
8265 vdec_reset_core(vdec);
8266 if (hw->mmu_enable)
8267 hevc_reset_core(vdec);
8268 hw->vdec_cb_arg = arg;
8269 hw->vdec_cb = callback;
8270
8271 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8272 hw->reset_bufmgr_flag = 1;
8273 dpb_print(DECODE_ID(hw), 0,
8274 "kfifo len:%d invaild, need bufmgr reset\n",
8275 kfifo_len(&hw->display_q));
8276 }
8277
8278 hw->pre_parser_wr_ptr =
8279 READ_PARSER_REG(PARSER_VIDEO_WP);
8280 hw->next_again_flag = 0;
8281
8282 if (hw->reset_bufmgr_flag ||
8283 ((error_proc_policy & 0x40) &&
8284 p_H264_Dpb->buf_alloc_fail)) {
8285 h264_reset_bufmgr(vdec);
8286 hw->reset_bufmgr_flag = 0;
8287 }
8288
8289 if (h264_debug_cmd & 0xf000) {
8290 if (((h264_debug_cmd >> 12) & 0xf)
8291 == (DECODE_ID(hw) + 1)) {
8292 h264_reconfig(hw);
8293 h264_debug_cmd &= (~0xf000);
8294 }
8295 }
8296 /* hw->chunk = vdec_prepare_input(vdec); */
8297#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8298 if (vdec->slave || vdec->master)
8299 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8300#endif
8301 size = vdec_prepare_input(vdec, &hw->chunk);
8302 if ((size < 0) ||
8303 (input_frame_based(vdec) && hw->chunk == NULL)) {
8304 input_empty[DECODE_ID(hw)]++;
8305 hw->dec_result = DEC_RESULT_AGAIN;
8306
8307 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8308 "vdec_prepare_input: Insufficient data\n");
8309
8310 vdec_schedule_work(&hw->work);
8311 return;
8312 }
8313 input_empty[DECODE_ID(hw)] = 0;
8314
8315 hw->dec_result = DEC_RESULT_NONE;
8316 hw->get_data_count = 0;
8317#if 0
8318 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8319 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8320 READ_VREG(VLD_MEM_VIFIFO_RP),
8321 READ_VREG(VLD_MEM_VIFIFO_WP));
8322#endif
8323
8324 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8325 u8 *data = NULL;
8326
8327 if (!hw->chunk->block->is_mapped)
8328 data = codec_mm_vmap(hw->chunk->block->start +
8329 hw->chunk->offset, size);
8330 else
8331 data = ((u8 *)hw->chunk->block->start_virt)
8332 + hw->chunk->offset;
8333
8334 if (dpb_is_debug(DECODE_ID(hw),
8335 PRINT_FLAG_VDEC_STATUS)
8336 ) {
8337 dpb_print(DECODE_ID(hw), 0,
8338 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8339 __func__, size, get_data_check_sum(hw, size),
8340 data[0], data[1], data[2], data[3],
8341 data[4], data[5], data[size - 4],
8342 data[size - 3], data[size - 2],
8343 data[size - 1]);
8344 }
8345 if (dpb_is_debug(DECODE_ID(hw),
8346 PRINT_FRAMEBASE_DATA)
8347 ) {
8348 int jj;
8349
8350 for (jj = 0; jj < size; jj++) {
8351 if ((jj & 0xf) == 0)
8352 dpb_print(DECODE_ID(hw),
8353 PRINT_FRAMEBASE_DATA,
8354 "%06x:", jj);
8355 dpb_print_cont(DECODE_ID(hw),
8356 PRINT_FRAMEBASE_DATA,
8357 "%02x ", data[jj]);
8358 if (((jj + 1) & 0xf) == 0)
8359 dpb_print_cont(DECODE_ID(hw),
8360 PRINT_FRAMEBASE_DATA,
8361 "\n");
8362 }
8363 }
8364
8365 if (!hw->chunk->block->is_mapped)
8366 codec_mm_unmap_phyaddr(data);
8367 } else
8368 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8369 "%s: %x %x %x %x %x size 0x%x\n",
8370 __func__,
8371 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8372 READ_VREG(VLD_MEM_VIFIFO_WP),
8373 READ_VREG(VLD_MEM_VIFIFO_RP),
8374 READ_PARSER_REG(PARSER_VIDEO_RP),
8375 READ_PARSER_REG(PARSER_VIDEO_WP),
8376 size);
8377
8378 start_process_time(hw);
8379 if (vdec->mc_loaded) {
8380 /*firmware have load before,
8381 and not changes to another.
8382 ignore reload.
8383 */
8384 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8385 } else {
8386
8387 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8388 if (ret < 0) {
8389 amvdec_enable_flag = false;
8390 amvdec_disable();
8391
8392 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8393 "MH264 the %s fw loading failed, err: %x\n",
8394 tee_enabled() ? "TEE" : "local", ret);
8395 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8396 vdec_schedule_work(&hw->work);
8397 return;
8398 }
8399 vdec->mc_type = VFORMAT_H264;
8400 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8401 if (hw->mmu_enable) {
8402 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8403 hw->fw_mmu->data);
8404 if (ret < 0) {
8405 amvdec_enable_flag = false;
8406 amhevc_disable();
8407
8408 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8409 "MH264_MMU the %s fw loading failed, err: %x\n",
8410 tee_enabled() ? "TEE" : "local", ret);
8411 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8412 vdec_schedule_work(&hw->work);
8413 return;
8414 }
8415 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8416 }
8417 vdec->mc_loaded = 1;
8418 }
8419 vmh264_reset_udr_mgr(hw);
8420
8421 if (vh264_hw_ctx_restore(hw) < 0) {
8422 vdec_schedule_work(&hw->work);
8423 return;
8424 }
8425 if (input_frame_based(vdec)) {
8426 int decode_size = 0;
8427
8428 decode_size = hw->chunk->size +
8429 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8430 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8431 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8432 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8433 } else {
8434 if (size <= 0)
8435 size = 0x7fffffff; /*error happen*/
8436 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8437 WRITE_VREG(H264_DECODE_SIZE, size);
8438 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8439 }
8440 config_aux_buf(hw);
8441 config_decode_mode(hw);
8442 vdec_enable_input(vdec);
8443 WRITE_VREG(NAL_SEARCH_CTL, 0);
8444 hw->sei_data_len = 0;
8445 if (enable_itu_t35)
8446 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8447 if (!hw->init_flag) {
8448 if (hw->mmu_enable)
8449 WRITE_VREG(NAL_SEARCH_CTL,
8450 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8451 else
8452 WRITE_VREG(NAL_SEARCH_CTL,
8453 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8454 }
8455 if (udebug_flag)
8456 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8457 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8458
8459 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8460
8461 if (hw->mmu_enable)
8462 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8463 else
8464 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8465 }
8466 amvdec_start();
8467 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8468 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8469 amhevc_start();
8470 if (hw->config_bufmgr_done) {
8471 hevc_mcr_sao_global_hw_init(hw,
8472 (hw->mb_width << 4), (hw->mb_height << 4));
8473 hevc_mcr_config_canv2axitbl(hw, 1);
8474 }
8475 }
8476
8477 /* if (hw->init_flag) { */
8478 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8479 /* } */
8480
8481 hw->init_flag = 1;
8482}
8483
8484static void reset(struct vdec_s *vdec)
8485{
8486 struct vdec_h264_hw_s *hw =
8487 (struct vdec_h264_hw_s *)vdec->private;
8488
8489 pr_info("vmh264 reset\n");
8490
8491 cancel_work_sync(&hw->work);
8492 cancel_work_sync(&hw->notify_work);
8493 if (hw->stat & STAT_VDEC_RUN) {
8494 amhevc_stop();
8495 hw->stat &= ~STAT_VDEC_RUN;
8496 }
8497
8498 if (hw->stat & STAT_TIMER_ARM) {
8499 del_timer_sync(&hw->check_timer);
8500 hw->stat &= ~STAT_TIMER_ARM;
8501 }
8502 hw->eos = 0;
8503 hw->decode_pic_count = 0;
8504 hw->dec_result = DEC_RESULT_NONE;
8505 reset_process_time(hw);
8506 h264_reset_bufmgr(vdec);
8507
8508 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8509}
8510
8511static void h264_reconfig(struct vdec_h264_hw_s *hw)
8512{
8513 int i;
8514 unsigned long flags;
8515 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8516 struct vdec_s *vdec = hw_to_vdec(hw);
8517 dpb_print(DECODE_ID(hw), 0,
8518 "%s\n", __func__);
8519 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8520 all buffers are in display queue (used == 2),
8521 or free (used == 0)
8522 */
8523 if (dpb_is_debug(DECODE_ID(hw),
8524 PRINT_FLAG_DUMP_BUFSPEC))
8525 dump_bufspec(hw, "pre h264_reconfig");
8526
8527 flush_dpb(p_H264_Dpb);
8528 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8529
8530 if (hw->collocate_cma_alloc_addr) {
8531 decoder_bmmu_box_free_idx(
8532 hw->bmmu_box,
8533 BMMU_REF_IDX);
8534 hw->collocate_cma_alloc_addr = 0;
8535 hw->dpb.colocated_mv_addr_start = 0;
8536 hw->dpb.colocated_mv_addr_end = 0;
8537 }
8538 spin_lock_irqsave(&hw->bufspec_lock, flags);
8539 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8540 if (vdec->parallel_dec == 1) {
8541 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8542 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8543 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8544 hw->buffer_spec[i].y_canvas_index = -1;
8545 hw->buffer_spec[i].u_canvas_index = -1;
8546 hw->buffer_spec[i].v_canvas_index = -1;
8547#ifdef VDEC_DW
8548 if (IS_VDEC_DW(hw)) {
8549 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8550 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8551 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8552 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8553 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8554 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8555#endif
8556 }
8557 }
8558 /*make sure buffers not put back to bufmgr when
8559 vf_put is called*/
8560 if (hw->buffer_spec[i].used == 2)
8561 hw->buffer_spec[i].used = 3;
8562
8563 /* ready to release "free buffers"
8564 */
8565 if (hw->buffer_spec[i].used == 0)
8566 hw->buffer_spec[i].used = 4;
8567
8568 hw->buffer_spec[i].canvas_pos = -1;
8569 }
8570 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8571 hw->has_i_frame = 0;
8572 hw->config_bufmgr_done = 0;
8573
8574 if (hw->is_used_v4l) {
8575 mutex_lock(&vmh264_mutex);
8576 dealloc_buf_specs(hw, 1);
8577 mutex_unlock(&vmh264_mutex);
8578 }
8579
8580 if (dpb_is_debug(DECODE_ID(hw),
8581 PRINT_FLAG_DUMP_BUFSPEC))
8582 dump_bufspec(hw, "after h264_reconfig");
8583
8584}
8585
8586#ifdef ERROR_HANDLE_TEST
8587static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8588{
8589 int i;
8590 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8591 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8592 "%s\n", __func__);
8593 remove_dpb_pictures(p_H264_Dpb);
8594 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8595 /*make sure buffers not put back to bufmgr when
8596 vf_put is called*/
8597 if (hw->buffer_spec[i].used == 2)
8598 hw->buffer_spec[i].used = 5;
8599 }
8600
8601}
8602#endif
8603
8604static void h264_reset_bufmgr(struct vdec_s *vdec)
8605{
8606 int i;
8607 ulong timeout;
8608 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8609#if 0
8610 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8611 int actual_dpb_size, max_reference_size;
8612 int reorder_pic_num;
8613 unsigned int colocated_buf_size;
8614 unsigned int colocated_mv_addr_start;
8615 unsigned int colocated_mv_addr_end;
8616 dpb_print(DECODE_ID(hw), 0,
8617 "%s\n", __func__);
8618
8619 for (i = 0; i < VF_POOL_SIZE; i++)
8620 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8621
8622 actual_dpb_size = p_H264_Dpb->mDPB.size;
8623 max_reference_size = p_H264_Dpb->max_reference_size;
8624 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8625
8626 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8627 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8628 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8629
8630 hw->cur_pool++;
8631 if (hw->cur_pool >= VF_POOL_NUM)
8632 hw->cur_pool = 0;
8633
8634 INIT_KFIFO(hw->display_q);
8635 INIT_KFIFO(hw->newframe_q);
8636
8637 for (i = 0; i < VF_POOL_SIZE; i++) {
8638 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8639 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8640 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8641 kfifo_put(&hw->newframe_q, vf);
8642 }
8643
8644 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8645 hw->buffer_spec[i].used = 0;
8646
8647 dpb_init_global(&hw->dpb,
8648 DECODE_ID(hw), 0, 0);
8649 p_H264_Dpb->mDPB.size = actual_dpb_size;
8650 p_H264_Dpb->max_reference_size = max_reference_size;
8651 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8652
8653 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8654 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8655 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8656
8657 p_H264_Dpb->fast_output_enable = fast_output_enable;
8658 hw->has_i_frame = 0;
8659#else
8660 dpb_print(DECODE_ID(hw), 0,
8661 "%s frame count %d to skip %d\n\n",
8662 __func__, hw->decode_pic_count+1,
8663 hw->skip_frame_count);
8664
8665 timeout = jiffies + HZ;
8666 while (kfifo_len(&hw->display_q) > 0) {
8667 if (time_after(jiffies, timeout))
8668 break;
8669 schedule();
8670 }
8671
8672 for (i = 0; i < VF_POOL_SIZE; i++)
8673 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8674
8675 hw->cur_pool++;
8676 if (hw->cur_pool >= VF_POOL_NUM)
8677 hw->cur_pool = 0;
8678
8679 for (i = 0; i < VF_POOL_SIZE; i++)
8680 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8681
8682
8683 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8684
8685 buf_spec_init(hw);
8686
8687 vh264_local_init(hw);
8688 /*hw->decode_pic_count = 0;
8689 hw->seq_info2 = 0;*/
8690
8691 if (hw->is_used_v4l) {
8692 mutex_lock(&vmh264_mutex);
8693 /* detach relationship with v4l buffs.*/
8694 dealloc_buf_specs(hw, 1);
8695 mutex_unlock(&vmh264_mutex);
8696 }
8697
8698 if (vh264_set_params(hw,
8699 hw->cfg_param1,
8700 hw->cfg_param2,
8701 hw->cfg_param3,
8702 hw->cfg_param4) < 0)
8703 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8704
8705 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8706 if (first_i_policy & 0x01)
8707 hw->first_i_policy = (3 << 8) | first_i_policy;
8708
8709 hw->init_flag = 1;
8710 hw->reset_bufmgr_count++;
8711#endif
8712}
8713
8714int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8715{
8716 int ret = -1;
8717 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8718 CODEC_MM_FLAGS_TVP : 0;
8719 int buf_size = 64;
8720
8721 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8722 tvp_flag, hw->mmu_enable);
8723 hw->need_cache_size = buf_size * SZ_1M;
8724 hw->sc_start_time = get_jiffies_64();
8725 if (hw->mmu_enable && !hw->mmu_box) {
8726 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8727 hw->id,
8728 MMU_MAX_BUFFERS,
8729 hw->need_cache_size,
8730 tvp_flag);
8731 if (!hw->mmu_box) {
8732 pr_err("h264 4k alloc mmu box failed!!\n");
8733 return -1;
8734 }
8735 ret = 0;
8736 }
8737 if (!hw->bmmu_box) {
8738 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8739 DRIVER_NAME,
8740 hw->id,
8741 BMMU_MAX_BUFFERS,
8742 4 + PAGE_SHIFT,
8743 CODEC_MM_FLAGS_CMA_CLEAR |
8744 CODEC_MM_FLAGS_FOR_VDECODER |
8745 tvp_flag);
8746 if (hw->bmmu_box)
8747 ret = 0;
8748 }
8749 return ret;
8750}
8751int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8752{
8753 if (hw->mmu_box) {
8754 decoder_mmu_box_free(hw->mmu_box);
8755 hw->mmu_box = NULL;
8756 }
8757 if (hw->bmmu_box) {
8758 decoder_bmmu_box_free(hw->bmmu_box);
8759 hw->bmmu_box = NULL;
8760 }
8761 return 0;
8762}
8763
8764static int ammvdec_h264_probe(struct platform_device *pdev)
8765{
8766 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8767 struct vdec_h264_hw_s *hw = NULL;
8768 char *tmpbuf;
8769 int config_val;
8770
8771 if (pdata == NULL) {
8772 pr_info("\nammvdec_h264 memory resource undefined.\n");
8773 return -EFAULT;
8774 }
8775
8776 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8777 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8778 if (hw == NULL) {
8779 pr_info("\nammvdec_h264 device data allocation failed\n");
8780 return -ENOMEM;
8781 }
8782 hw->id = pdev->id;
8783 hw->platform_dev = pdev;
8784
8785 /* the ctx from v4l2 driver. */
8786 hw->v4l2_ctx = pdata->private;
8787
8788 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8789 hw->canvas_mode = pdata->canvas_mode;
8790 else
8791 hw->canvas_mode = mem_map_mode;
8792
8793 platform_set_drvdata(pdev, pdata);
8794
8795 hw->mmu_enable = 0;
8796 hw->first_head_check_flag = 0;
8797 hw->new_iframe_flag = 0;
8798 hw->ref_err_flush_dpb_flag = 0;
8799
8800 if (pdata->sys_info)
8801 hw->vh264_amstream_dec_info = *pdata->sys_info;
8802
8803 if (force_enable_mmu && pdata->sys_info &&
8804 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8805 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8806 (pdata->sys_info->height * pdata->sys_info->width
8807 > 1920 * 1088))
8808 hw->mmu_enable = 1;
8809
8810 if (hw->mmu_enable &&
8811 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8812 hw->mmu_enable = 0;
8813 pr_info("ionvideo needs disable mmu, path= %d \n",
8814 pdata->frame_base_video_path);
8815 }
8816
8817 if (ammvdec_h264_mmu_init(hw)) {
8818 h264_free_hw_stru(&pdev->dev, (void *)hw);
8819 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8820 return -ENOMEM;
8821 }
8822
8823 if (pdata->config_len) {
8824 /*use ptr config for doubel_write_mode, etc*/
8825 if (get_config_int(pdata->config,
8826 "mh264_double_write_mode", &config_val) == 0)
8827 hw->double_write_mode = config_val;
8828 else
8829 hw->double_write_mode = double_write_mode;
8830
8831 if (get_config_int(pdata->config,
8832 "parm_v4l_codec_enable",
8833 &config_val) == 0)
8834 hw->is_used_v4l = config_val;
8835
8836 if (get_config_int(pdata->config,
8837 "parm_v4l_buffer_margin",
8838 &config_val) == 0)
8839 hw->reorder_dpb_size_margin = config_val;
8840 } else
8841 hw->double_write_mode = double_write_mode;
8842
8843 if (!hw->is_used_v4l)
8844 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8845
8846 if (hw->mmu_enable)
8847 hw->double_write_mode &= 0xffff;
8848
8849 if (pdata->parallel_dec == 1) {
8850 int i;
8851 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8852 hw->buffer_spec[i].y_canvas_index = -1;
8853 hw->buffer_spec[i].u_canvas_index = -1;
8854 hw->buffer_spec[i].v_canvas_index = -1;
8855#ifdef VDEC_DW
8856 if (IS_VDEC_DW(hw)) {
8857 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8858 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8859 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8860 }
8861#endif
8862 }
8863 }
8864
8865 dpb_print(DECODE_ID(hw), 0,
8866 "%s mmu_enable %d double_write_mode 0x%x\n",
8867 __func__, hw->mmu_enable, hw->double_write_mode);
8868
8869 pdata->private = hw;
8870 pdata->dec_status = dec_status;
8871 pdata->set_trickmode = vmh264_set_trickmode;
8872 pdata->run_ready = run_ready;
8873 pdata->run = run;
8874 pdata->reset = reset;
8875 pdata->irq_handler = vh264_isr;
8876 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8877 pdata->dump_state = vmh264_dump_state;
8878
8879#ifdef MH264_USERDATA_ENABLE
8880 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8881 pdata->user_data_read = vmh264_user_data_read;
8882 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8883#else
8884 pdata->wakeup_userdata_poll = NULL;
8885 pdata->user_data_read = NULL;
8886 pdata->reset_userdata_fifo = NULL;
8887#endif
8888 if (pdata->use_vfm_path) {
8889 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8890 VFM_DEC_PROVIDER_NAME);
8891 hw->frameinfo_enable = 1;
8892 }
8893#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8894 else if (vdec_dual(pdata)) {
8895 if (dv_toggle_prov_name) /*debug purpose*/
8896 snprintf(pdata->vf_provider_name,
8897 VDEC_PROVIDER_NAME_SIZE,
8898 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8899 VFM_DEC_DVEL_PROVIDER_NAME);
8900 else
8901 snprintf(pdata->vf_provider_name,
8902 VDEC_PROVIDER_NAME_SIZE,
8903 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8904 VFM_DEC_DVBL_PROVIDER_NAME);
8905 }
8906#endif
8907 else
8908 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8909 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8910
8911 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8912 &vf_provider_ops, pdata);
8913
8914 platform_set_drvdata(pdev, pdata);
8915
8916 buf_spec_init(hw);
8917
8918 hw->platform_dev = pdev;
8919
8920#ifdef DUMP_USERDATA_RECORD
8921 vmh264_init_userdata_dump();
8922 vmh264_reset_user_data_buf();
8923#endif
8924 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8925 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8926 h264_free_hw_stru(&pdev->dev, (void *)hw);
8927 pdata->dec_status = NULL;
8928 return -ENOMEM;
8929 }
8930
8931 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8932 DCAC_READ_MARGIN;
8933 if (hw->mmu_enable) {
8934 u32 extif_size = EXTIF_BUF_SIZE;
8935 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8936 extif_size <<= 1;
8937 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8938 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8939 h264_free_hw_stru(&pdev->dev, (void *)hw);
8940 pdata->dec_status = NULL;
8941 return -ENOMEM;
8942 }
8943 }
8944 if (!vdec_secure(pdata)) {
8945#if 1
8946 /*init internal buf*/
8947 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8948 if (tmpbuf) {
8949 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8950 codec_mm_dma_flush(tmpbuf,
8951 V_BUF_ADDR_OFFSET,
8952 DMA_TO_DEVICE);
8953 } else {
8954 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8955 V_BUF_ADDR_OFFSET);
8956 if (tmpbuf) {
8957 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8958 codec_mm_dma_flush(tmpbuf,
8959 V_BUF_ADDR_OFFSET,
8960 DMA_TO_DEVICE);
8961 codec_mm_unmap_phyaddr(tmpbuf);
8962 }
8963 }
8964#else
8965 /*init sps/pps internal buf 64k*/
8966 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8967 + (mem_sps_base - DEF_BUF_START_ADDR));
8968 memset(tmpbuf, 0, 0x10000);
8969 dma_sync_single_for_device(amports_get_dma_device(),
8970 hw->cma_alloc_addr +
8971 (mem_sps_base - DEF_BUF_START_ADDR),
8972 0x10000, DMA_TO_DEVICE);
8973#endif
8974 }
8975 /**/
8976
8977#if 0
8978 if (NULL == hw->sei_data_buffer) {
8979 hw->sei_data_buffer =
8980 dma_alloc_coherent(amports_get_dma_device(),
8981 USER_DATA_SIZE,
8982 &hw->sei_data_buffer_phys, GFP_KERNEL);
8983 if (!hw->sei_data_buffer) {
8984 pr_info("%s: Can not allocate sei_data_buffer\n",
8985 __func__);
8986 ammvdec_h264_mmu_release(hw);
8987 h264_free_hw_stru(&pdev->dev, (void *)hw);
8988 return -ENOMEM;
8989 }
8990 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
8991 sei_data_buffer, sei_data_buffer_phys,
8992 (u32)sei_data_buffer_remap); */
8993 }
8994#endif
8995 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
8996 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
8997
8998 if (vdec_is_support_4k() ||
8999 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9000 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9001 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9002 {
9003 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9004 }else
9005 {
9006 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9007 }
9008
9009 if (vh264_init(hw) < 0) {
9010 pr_info("\nammvdec_h264 init failed.\n");
9011 ammvdec_h264_mmu_release(hw);
9012 h264_free_hw_stru(&pdev->dev, (void *)hw);
9013 pdata->dec_status = NULL;
9014 return -ENODEV;
9015 }
9016#ifdef MH264_USERDATA_ENABLE
9017 vmh264_crate_userdata_manager(hw,
9018 hw->sei_user_data_buffer,
9019 USER_DATA_SIZE);
9020#endif
9021
9022 vdec_set_prepare_level(pdata, start_decode_buf_level);
9023 if (pdata->parallel_dec == 1) {
9024 if (hw->mmu_enable == 0)
9025 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9026 else {
9027 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9028 | CORE_MASK_COMBINE);
9029 }
9030 } else
9031 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9032 | CORE_MASK_COMBINE);
9033
9034 atomic_set(&hw->vh264_active, 1);
9035
9036 return 0;
9037}
9038
9039static int ammvdec_h264_remove(struct platform_device *pdev)
9040{
9041 struct vdec_h264_hw_s *hw =
9042 (struct vdec_h264_hw_s *)
9043 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9044 int i;
9045
9046 struct vdec_s *vdec = hw_to_vdec(hw);
9047
9048 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9049 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9050 dpb_print(DECODE_ID(hw), 0,
9051 "%s force exit %d\n", __func__, __LINE__);
9052 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9053 vdec_schedule_work(&hw->work);
9054 wait_event_interruptible_timeout(hw->wait_q,
9055 (vdec->status == VDEC_STATUS_CONNECTED),
9056 msecs_to_jiffies(1000)); /* wait for work done */
9057 }
9058
9059 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9060 release_aux_data(hw, i);
9061
9062 atomic_set(&hw->vh264_active, 0);
9063
9064 if (hw->stat & STAT_TIMER_ARM) {
9065 del_timer_sync(&hw->check_timer);
9066 hw->stat &= ~STAT_TIMER_ARM;
9067 }
9068
9069 vh264_stop(hw);
9070#ifdef MH264_USERDATA_ENABLE
9071#ifdef DUMP_USERDATA_RECORD
9072 vmh264_dump_userdata();
9073#endif
9074 vmh264_destroy_userdata_manager(hw);
9075#endif
9076 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9077
9078 atomic_set(&hw->vh264_active, 0);
9079 if (vdec->parallel_dec == 1) {
9080 if (hw->mmu_enable == 0)
9081 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9082 else
9083 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9084 CORE_MASK_COMBINE);
9085 } else
9086 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9087
9088 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9089 if (vdec->parallel_dec == 1) {
9090 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9091 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9092 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9093 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9094 if (IS_VDEC_DW(hw)) {
9095 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9096 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9097 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9098 }
9099 }
9100 }
9101
9102 ammvdec_h264_mmu_release(hw);
9103 h264_free_hw_stru(&pdev->dev, (void *)hw);
9104 clk_adj_frame_count = 0;
9105
9106 return 0;
9107}
9108
9109/****************************************/
9110#ifdef CONFIG_PM
9111static int mh264_suspend(struct device *dev)
9112{
9113 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9114 return 0;
9115}
9116
9117static int mh264_resume(struct device *dev)
9118{
9119 amvdec_resume(to_platform_device(dev));
9120 return 0;
9121}
9122
9123static const struct dev_pm_ops mh264_pm_ops = {
9124 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9125};
9126#endif
9127
9128static struct platform_driver ammvdec_h264_driver = {
9129 .probe = ammvdec_h264_probe,
9130 .remove = ammvdec_h264_remove,
9131 .driver = {
9132 .name = DRIVER_NAME,
9133#ifdef CONFIG_PM
9134 .pm = &mh264_pm_ops,
9135#endif
9136 }
9137};
9138
9139static struct codec_profile_t ammvdec_h264_profile = {
9140 .name = "mh264",
9141 .profile = ""
9142};
9143
9144static struct mconfig hm264_configs[] = {
9145 MC_PU32("h264_debug_flag", &h264_debug_flag),
9146 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9147 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9148 MC_PU32("decode_timeout_val", &decode_timeout_val),
9149 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9150 MC_PU32("reference_buf_margin", &reference_buf_margin),
9151 MC_PU32("radr", &radr),
9152 MC_PU32("rval", &rval),
9153 MC_PU32("h264_debug_mask", &h264_debug_mask),
9154 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9155 MC_PI32("force_rate_streambase", &force_rate_streambase),
9156 MC_PI32("dec_control", &dec_control),
9157 MC_PI32("force_rate_framebase", &force_rate_framebase),
9158 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9159 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9160 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9161#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9162 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9163 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9164 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9165#endif
9166 MC_PU32("i_only_flag", &i_only_flag),
9167 MC_PU32("force_rate_streambase", &force_rate_streambase),
9168};
9169static struct mconfig_node hm264_node;
9170
9171
9172static int __init ammvdec_h264_driver_init_module(void)
9173{
9174 pr_info("ammvdec_h264 module init\n");
9175 if (platform_driver_register(&ammvdec_h264_driver)) {
9176 pr_info("failed to register ammvdec_h264 driver\n");
9177 return -ENODEV;
9178 }
9179
9180 if (vdec_is_support_4k()) {
9181 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9182 ammvdec_h264_profile.profile =
9183 "4k, dwrite, compressed";
9184 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9185 ammvdec_h264_profile.profile = "4k";
9186 }
9187 }
9188
9189 vcodec_profile_register(&ammvdec_h264_profile);
9190 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9191 "mh264", hm264_configs, CONFIG_FOR_RW);
9192 return 0;
9193}
9194
9195static void __exit ammvdec_h264_driver_remove_module(void)
9196{
9197 pr_info("ammvdec_h264 module remove.\n");
9198
9199 platform_driver_unregister(&ammvdec_h264_driver);
9200}
9201
9202/****************************************/
9203module_param(h264_debug_flag, uint, 0664);
9204MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9205
9206module_param(start_decode_buf_level, int, 0664);
9207MODULE_PARM_DESC(start_decode_buf_level,
9208 "\n ammvdec_h264 start_decode_buf_level\n");
9209
9210module_param(pre_decode_buf_level, int, 0664);
9211MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9212
9213module_param(fixed_frame_rate_mode, uint, 0664);
9214MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9215
9216module_param(decode_timeout_val, uint, 0664);
9217MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9218
9219module_param(errordata_timeout_val, uint, 0664);
9220MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9221
9222module_param(get_data_timeout_val, uint, 0664);
9223MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9224
9225module_param(frame_max_data_packet, uint, 0664);
9226MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9227
9228module_param(reorder_dpb_size_margin, uint, 0664);
9229MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9230
9231#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9232module_param(reorder_dpb_size_margin_dv, uint, 0664);
9233MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9234 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9235#endif
9236
9237module_param(reference_buf_margin, uint, 0664);
9238MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9239
9240#ifdef CONSTRAIN_MAX_BUF_NUM
9241module_param(run_ready_max_vf_only_num, uint, 0664);
9242MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9243
9244module_param(run_ready_display_q_num, uint, 0664);
9245MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9246
9247module_param(run_ready_max_buf_num, uint, 0664);
9248MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9249#endif
9250
9251module_param(radr, uint, 0664);
9252MODULE_PARM_DESC(radr, "\nradr\n");
9253
9254module_param(rval, uint, 0664);
9255MODULE_PARM_DESC(rval, "\nrval\n");
9256
9257module_param(h264_debug_mask, uint, 0664);
9258MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9259
9260module_param(h264_debug_cmd, uint, 0664);
9261MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9262
9263module_param(force_rate_streambase, int, 0664);
9264MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9265
9266module_param(dec_control, int, 0664);
9267MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9268
9269module_param(force_rate_framebase, int, 0664);
9270MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9271
9272module_param(force_disp_bufspec_num, int, 0664);
9273MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9274
9275module_param(V_BUF_ADDR_OFFSET, int, 0664);
9276MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9277
9278module_param(prefix_aux_buf_size, uint, 0664);
9279MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9280
9281module_param(suffix_aux_buf_size, uint, 0664);
9282MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9283
9284#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9285module_param(dv_toggle_prov_name, uint, 0664);
9286MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9287
9288module_param(dolby_meta_with_el, uint, 0664);
9289MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9290
9291#endif
9292
9293module_param(fast_output_enable, uint, 0664);
9294MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9295
9296module_param(error_proc_policy, uint, 0664);
9297MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9298
9299module_param(error_skip_count, uint, 0664);
9300MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9301
9302module_param(force_sliding_margin, uint, 0664);
9303MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9304
9305module_param(i_only_flag, uint, 0664);
9306MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9307
9308module_param(first_i_policy, uint, 0664);
9309MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9310
9311module_param(frmbase_cont_bitlevel, uint, 0664);
9312MODULE_PARM_DESC(frmbase_cont_bitlevel,
9313 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9314
9315module_param(frmbase_cont_bitlevel2, uint, 0664);
9316MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9317 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9318
9319module_param(udebug_flag, uint, 0664);
9320MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9321
9322module_param(udebug_pause_pos, uint, 0664);
9323MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9324
9325module_param(udebug_pause_val, uint, 0664);
9326MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9327
9328module_param(udebug_pause_decode_idx, uint, 0664);
9329MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9330
9331module_param(max_alloc_buf_count, uint, 0664);
9332MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9333
9334module_param(enable_itu_t35, uint, 0664);
9335MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9336
9337module_param(endian, uint, 0664);
9338MODULE_PARM_DESC(endian, "\nrval\n");
9339
9340module_param(mmu_enable, uint, 0664);
9341MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9342
9343module_param(force_enable_mmu, uint, 0664);
9344MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9345
9346module_param(again_threshold, uint, 0664);
9347MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9348
9349module_param(stream_mode_start_num, uint, 0664);
9350MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9351
9352/*
9353module_param(trigger_task, uint, 0664);
9354MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9355*/
9356module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9357
9358module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9359
9360module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9361
9362module_param_array(run_count, uint,
9363 &max_decode_instance_num, 0664);
9364
9365module_param_array(not_run_ready, uint,
9366 &max_decode_instance_num, 0664);
9367
9368module_param_array(input_empty, uint,
9369 &max_decode_instance_num, 0664);
9370
9371module_param_array(max_get_frame_interval, uint,
9372 &max_decode_instance_num, 0664);
9373
9374module_param_array(step, uint, &max_decode_instance_num, 0664);
9375
9376module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9377
9378module_param(disp_vframe_valve_level, uint, 0664);
9379MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9380
9381module_param(double_write_mode, uint, 0664);
9382MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9383
9384module_param(mem_map_mode, uint, 0664);
9385MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9386
9387module_param(without_display_mode, uint, 0664);
9388MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9389
9390
9391module_init(ammvdec_h264_driver_init_module);
9392module_exit(ammvdec_h264_driver_remove_module);
9393
9394MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9395MODULE_LICENSE("GPL");
9396
generated by cgit at 2024-05-17 11:58:23 (GMT)