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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 144cd9fafb937d5cd8d7bf9854d6c776dbb133bf
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120#define INVALID_IDX -1 /* Invalid buffer index.*/
121
122static int mmu_enable;
123/*mmu do not support mbaff*/
124static int force_enable_mmu = 0;
125unsigned int h264_debug_flag; /* 0xa0000000; */
126unsigned int h264_debug_mask = 0xff;
127 /*
128 *h264_debug_cmd:
129 * 0x1xx, force decoder id of xx to be disconnected
130 */
131unsigned int h264_debug_cmd;
132
133static unsigned int dec_control =
134 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
135 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
136
137static unsigned int force_rate_streambase;
138static unsigned int force_rate_framebase;
139static unsigned int force_disp_bufspec_num;
140static unsigned int fixed_frame_rate_mode;
141static unsigned int error_recovery_mode_in;
142static int start_decode_buf_level = 0x4000;
143static int pre_decode_buf_level = 0x1000;
144static int stream_mode_start_num = 4;
145
146#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
147/*to make reorder size difference of bl and el not too big*/
148static unsigned int reorder_dpb_size_margin_dv = 16;
149#endif
150static unsigned int reorder_dpb_size_margin = 6;
151static unsigned int reference_buf_margin = 4;
152
153#ifdef CONSTRAIN_MAX_BUF_NUM
154static u32 run_ready_max_vf_only_num;
155static u32 run_ready_display_q_num;
156 /*0: not check
157 0xff: mDPB.size
158 */
159static u32 run_ready_max_buf_num = 0xff;
160#endif
161
162#define VDEC_ASSIST_CANVAS_BLK32 0x5
163
164
165static unsigned int max_alloc_buf_count;
166static unsigned int decode_timeout_val = 100;
167static unsigned int errordata_timeout_val = 50;
168static unsigned int get_data_timeout_val = 2000;
169#if 1
170/* H264_DATA_REQUEST does not work, disable it,
171decode has error for data in none continuous address
172*/
173static unsigned int frame_max_data_packet;
174#else
175static unsigned int frame_max_data_packet = 8;
176#endif
177static unsigned int radr;
178static unsigned int rval;
179static u32 endian = 0xff0;
180
181/*
182 udebug_flag:
183 bit 0, enable ucode print
184 bit 1, enable ucode detail print
185 bit 3, disable ucode watchdog
186 bit [31:16] not 0, pos to dump lmem
187 bit 2, pop bits to lmem
188 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
189*/
190static u32 udebug_flag;
191/*
192 when udebug_flag[1:0] is not 0
193 udebug_pause_pos not 0,
194 pause position
195*/
196static u32 udebug_pause_pos;
197/*
198 when udebug_flag[1:0] is not 0
199 and udebug_pause_pos is not 0,
200 pause only when DEBUG_REG2 is equal to this val
201*/
202static u32 udebug_pause_val;
203
204static u32 udebug_pause_decode_idx;
205
206static unsigned int disp_vframe_valve_level;
207
208static unsigned int max_decode_instance_num = H264_DEV_NUM;
209static unsigned int decode_frame_count[H264_DEV_NUM];
210static unsigned int display_frame_count[H264_DEV_NUM];
211static unsigned int max_process_time[H264_DEV_NUM];
212static unsigned int max_get_frame_interval[H264_DEV_NUM];
213static unsigned int run_count[H264_DEV_NUM];
214static unsigned int input_empty[H264_DEV_NUM];
215static unsigned int not_run_ready[H264_DEV_NUM];
216static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
217{1, 1, 1, 1, 1, 1, 1, 1, 1};
218
219#define VDEC_CLOCK_ADJUST_FRAME 30
220static unsigned int clk_adj_frame_count;
221
222/*
223 *bit[3:0]: 0, run ; 1, pause; 3, step
224 *bit[4]: 1, schedule run
225 */
226static unsigned int step[H264_DEV_NUM];
227
228#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
229static u32 prefix_aux_buf_size = (16 * 1024);
230static u32 suffix_aux_buf_size;
231
232#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
233static u32 dv_toggle_prov_name;
234
235static u32 dolby_meta_with_el;
236#endif
237
238/*
239 bit[8]
240 0: use sys_info[bit 3]
241 not 0:use i_only_flag[7:0]
242 bit[7:0]:
243 bit 0, 1: only display I picture;
244 bit 1, 1: only decode I picture;
245*/
246static unsigned int i_only_flag;
247
248/*
249 error_proc_policy:
250 bit[0] send_error_frame_flag;
251 (valid when bit[31] is 1, otherwise use sysinfo)
252 bit[1] do not decode if config_decode_buf() fail
253 bit[2] force release buf if in deadlock
254 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
255 bit[4] check inactive of receiver
256 bit[5] reset buffmgr if in deadlock
257 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
258 bit[7] reset buffmgr if dpb error
259
260 bit[8] check total mbx/mby of decoded frame
261 bit[9] check ERROR_STATUS_REG
262 bit[10] check reference list
263 bit[11] mark error if dpb error
264 bit[12] i_only when error happen
265 bit[13] 0: mark error according to last pic, 1: ignore mark error
266 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
267*/
268static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
269
270
271/*
272 error_skip_count:
273 bit[11:0] error skip frame count
274 bit[15:12] error skip i picture count
275*/
276static unsigned int error_skip_count = (0x2 << 12) | 0x40;
277
278static unsigned int force_sliding_margin;
279/*
280 bit[1:0]:
281 0, start playing from any frame
282 1, start playing from I frame
283 bit[15:8]: the count of skip frames after first I
284 2, start playing from second I frame (decode from the first I)
285 bit[15:8]: the max count of skip frames after first I
286 3, start playing from IDR
287*/
288static unsigned int first_i_policy = 1;
289
290/*
291 fast_output_enable:
292 bit [0], output frame if there is IDR in list
293 bit [1], output frame if the current poc is 1 big than the previous poc
294 bit [2], if even poc only, output frame ifthe cuurent poc
295 is 2 big than the previous poc
296 bit [3], ip only
297*/
298static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
299
300static unsigned int enable_itu_t35 = 1;
301
302static unsigned int frmbase_cont_bitlevel = 0x40;
303
304static unsigned int frmbase_cont_bitlevel2 = 0x1;
305
306
307#define MH264_USERDATA_ENABLE
308
309/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
310/* hevc->double_write_mode:
311 0, no double write
312 1, 1:1 ratio
313 2, (1/4):(1/4) ratio
314 3, (1/4):(1/4) ratio, with both compressed frame included
315 4, (1/2):(1/2) ratio
316 0x10, double write only
317 0x10000: vdec dw horizotal 1/2
318 0x20000: vdec dw horizotal/vertical 1/2
319*/
320static u32 double_write_mode;
321static u32 without_display_mode;
322#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
323
324static void vmh264_dump_state(struct vdec_s *vdec);
325
326#define is_in_parsing_state(status) \
327 ((status == H264_ACTION_SEARCH_HEAD) || \
328 ((status & 0xf0) == 0x80))
329
330#define is_interlace(frame) \
331 (frame->frame &&\
332 frame->top_field &&\
333 frame->bottom_field &&\
334 (!frame->frame->coded_frame))
335static inline bool close_to(int a, int b, int m)
336{
337 return (abs(a - b) < m) ? true : false;
338}
339
340#if 0
341#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
342#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
343#else
344#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
345#define h264_free_hw_stru(dev, hw) vfree(hw)
346#endif
347
348/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
349#define NV21
350/* #endif */
351
352/* 12M for L41 */
353#define MAX_DPB_BUFF_SIZE (12*1024*1024)
354#define DEFAULT_MEM_SIZE (32*1024*1024)
355#define AVIL_DPB_BUFF_SIZE 0x01ec2000
356
357#define DEF_BUF_START_ADDR 0x01000000
358#define mem_sps_base 0x011c3c00
359#define mem_pps_base 0x011cbc00
360/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
361u32 V_BUF_ADDR_OFFSET = 0x200000;
362#define DCAC_READ_MARGIN (64 * 1024)
363
364
365#define EXTEND_SAR 0xff
366#define BUFSPEC_POOL_SIZE 64
367#define VF_POOL_SIZE 64
368#define VF_POOL_NUM 2
369#define MAX_VF_BUF_NUM 27
370#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
371#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
372#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
373#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
374#define EXTIF_BUF_SIZE (0x10000 * 2)
375
376#define HEADER_BUFFER_IDX(n) (n)
377#define VF_BUFFER_IDX(n) (n)
378
379
380#define PUT_INTERVAL (HZ/100)
381#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
382
383#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
384#define SWITCHING_STATE_OFF 0
385#define SWITCHING_STATE_ON_CMD3 1
386#define SWITCHING_STATE_ON_CMD1 2
387
388
389
390#define INCPTR(p) ptr_atomic_wrap_inc(&p)
391
392#define SLICE_TYPE_I 2
393#define SLICE_TYPE_P 5
394#define SLICE_TYPE_B 6
395
396struct buffer_spec_s {
397 /*
398 used:
399 -1, none allocated
400 0, allocated, free
401 1, used by dpb
402 2, in disp queue;
403 3, in disp queue, isolated,
404 do not use for dpb when vf_put;
405 4, to release
406 5, in disp queue, isolated (but not to release)
407 do not use for dpb when vf_put;
408 */
409 unsigned int used;
410 unsigned int info0;
411 unsigned int info1;
412 unsigned int info2;
413 unsigned int y_addr;
414 unsigned int u_addr;
415 unsigned int v_addr;
416
417 int y_canvas_index;
418 int u_canvas_index;
419 int v_canvas_index;
420
421#ifdef VDEC_DW
422 unsigned int vdec_dw_y_addr;
423 unsigned int vdec_dw_u_addr;
424 unsigned int vdec_dw_v_addr;
425
426 int vdec_dw_y_canvas_index;
427 int vdec_dw_u_canvas_index;
428 int vdec_dw_v_canvas_index;
429#ifdef NV21
430 struct canvas_config_s vdec_dw_canvas_config[2];
431#else
432 struct canvas_config_s vdec_dw_canvas_config[3];
433#endif
434#endif
435
436#ifdef NV21
437 struct canvas_config_s canvas_config[2];
438#else
439 struct canvas_config_s canvas_config[3];
440#endif
441 unsigned long cma_alloc_addr;
442 unsigned int buf_adr;
443#ifdef H264_MMU
444 unsigned long alloc_header_addr;
445#endif
446 char *aux_data_buf;
447 int aux_data_size;
448#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
449 unsigned char dv_enhance_exist;
450#endif
451 int canvas_pos;
452 int vf_ref;
453 /*unsigned int comp_body_size;*/
454 unsigned int dw_y_adr;
455 unsigned int dw_u_v_adr;
456};
457
458#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
459#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
460#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
461
462
463#define vdec_dw_spec2canvas(x) \
464 (((x)->vdec_dw_v_canvas_index << 16) | \
465 ((x)->vdec_dw_u_canvas_index << 8) | \
466 ((x)->vdec_dw_y_canvas_index << 0))
467
468
469#define spec2canvas(x) \
470 (((x)->v_canvas_index << 16) | \
471 ((x)->u_canvas_index << 8) | \
472 ((x)->y_canvas_index << 0))
473
474#define FRAME_INDEX(vf_index) (vf_index & 0xff)
475#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
476#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
477
478static struct vframe_s *vh264_vf_peek(void *);
479static struct vframe_s *vh264_vf_get(void *);
480static void vh264_vf_put(struct vframe_s *, void *);
481static int vh264_vf_states(struct vframe_states *states, void *);
482static int vh264_event_cb(int type, void *data, void *private_data);
483static void vh264_work(struct work_struct *work);
484static void vh264_timeout_work(struct work_struct *work);
485static void vh264_notify_work(struct work_struct *work);
486#ifdef MH264_USERDATA_ENABLE
487static void user_data_ready_notify_work(struct work_struct *work);
488static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
489#endif
490
491static const char vh264_dec_id[] = "vh264-dev";
492
493#define PROVIDER_NAME "vdec.h264"
494
495static const struct vframe_operations_s vf_provider_ops = {
496 .peek = vh264_vf_peek,
497 .get = vh264_vf_get,
498 .put = vh264_vf_put,
499 .event_cb = vh264_event_cb,
500 .vf_states = vh264_vf_states,
501};
502
503#define DEC_RESULT_NONE 0
504#define DEC_RESULT_DONE 1
505#define DEC_RESULT_AGAIN 2
506#define DEC_RESULT_CONFIG_PARAM 3
507#define DEC_RESULT_GET_DATA 4
508#define DEC_RESULT_GET_DATA_RETRY 5
509#define DEC_RESULT_ERROR 6
510#define DEC_RESULT_EOS 7
511#define DEC_RESULT_FORCE_EXIT 8
512
513/*
514 *static const char *dec_result_str[] = {
515 * "DEC_RESULT_NONE ",
516 * "DEC_RESULT_DONE ",
517 * "DEC_RESULT_AGAIN ",
518 * "DEC_RESULT_CONFIG_PARAM",
519 * "DEC_RESULT_GET_DATA ",
520 * "DEC_RESULT_GET_DA_RETRY",
521 * "DEC_RESULT_ERROR ",
522 *};
523 */
524
525#define UCODE_IP_ONLY 2
526#define UCODE_IP_ONLY_PARAM 1
527
528#define MC_OFFSET_HEADER 0x0000
529#define MC_OFFSET_DATA 0x1000
530#define MC_OFFSET_MMCO 0x2000
531#define MC_OFFSET_LIST 0x3000
532#define MC_OFFSET_SLICE 0x4000
533#define MC_OFFSET_MAIN 0x5000
534
535#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
536#define MC_SWAP_SIZE (4*SZ_1K)
537#define MODE_ERROR 0
538#define MODE_FULL 1
539
540#define DFS_HIGH_THEASHOLD 3
541
542#define INIT_FLAG_REG AV_SCRATCH_2
543#define HEAD_PADING_REG AV_SCRATCH_3
544#define UCODE_WATCHDOG_REG AV_SCRATCH_7
545#define LMEM_DUMP_ADR AV_SCRATCH_L
546#define DEBUG_REG1 AV_SCRATCH_M
547#define DEBUG_REG2 AV_SCRATCH_N
548#define FRAME_COUNTER_REG AV_SCRATCH_I
549#define RPM_CMD_REG AV_SCRATCH_A
550#define H264_DECODE_SIZE AV_SCRATCH_E
551#define H264_DECODE_MODE AV_SCRATCH_4
552#define H264_DECODE_SEQINFO AV_SCRATCH_5
553#define H264_AUX_ADR AV_SCRATCH_C
554#define H264_AUX_DATA_SIZE AV_SCRATCH_H
555
556#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
557#define DPB_STATUS_REG AV_SCRATCH_J
558#define ERROR_STATUS_REG AV_SCRATCH_9
559 /*
560 NAL_SEARCH_CTL: bit 0, enable itu_t35
561 NAL_SEARCH_CTL: bit 1, enable mmu
562 */
563#define NAL_SEARCH_CTL AV_SCRATCH_9
564#define MBY_MBX MB_MOTION_MODE /*0xc07*/
565
566#define DECODE_MODE_SINGLE 0x0
567#define DECODE_MODE_MULTI_FRAMEBASE 0x1
568#define DECODE_MODE_MULTI_STREAMBASE 0x2
569#define DECODE_MODE_MULTI_DVBAL 0x3
570#define DECODE_MODE_MULTI_DVENL 0x4
571static DEFINE_MUTEX(vmh264_mutex);
572
573
574
575#ifdef MH264_USERDATA_ENABLE
576
577struct mh264_userdata_record_t {
578 struct userdata_meta_info_t meta_info;
579 u32 rec_start;
580 u32 rec_len;
581};
582
583struct mh264_ud_record_wait_node_t {
584 struct list_head list;
585 struct mh264_userdata_record_t ud_record;
586};
587#define USERDATA_FIFO_NUM 256
588#define MAX_FREE_USERDATA_NODES 5
589
590struct mh264_userdata_info_t {
591 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
592 u8 *data_buf;
593 u8 *data_buf_end;
594 u32 buf_len;
595 u32 read_index;
596 u32 write_index;
597 u32 last_wp;
598};
599
600
601#endif
602
603struct vdec_h264_hw_s {
604 spinlock_t lock;
605 spinlock_t bufspec_lock;
606 int id;
607 struct platform_device *platform_dev;
608 unsigned long cma_alloc_addr;
609 /* struct page *collocate_cma_alloc_pages; */
610 unsigned long collocate_cma_alloc_addr;
611
612 u32 prefix_aux_size;
613 u32 suffix_aux_size;
614 void *aux_addr;
615 dma_addr_t aux_phy_addr;
616
617 /* buffer for store all sei data */
618 void *sei_data_buf;
619 u32 sei_data_len;
620
621 /* buffer for storing one itu35 recored */
622 void *sei_itu_data_buf;
623 u32 sei_itu_data_len;
624
625 /* recycle buffer for user data storing all itu35 records */
626 void *sei_user_data_buffer;
627 u32 sei_user_data_wp;
628#ifdef MH264_USERDATA_ENABLE
629 struct work_struct user_data_ready_work;
630#endif
631 struct StorablePicture *last_dec_picture;
632
633 ulong lmem_addr;
634 dma_addr_t lmem_addr_remap;
635
636 void *bmmu_box;
637#ifdef H264_MMU
638 void *mmu_box;
639 void *frame_mmu_map_addr;
640 dma_addr_t frame_mmu_map_phy_addr;
641 u32 hevc_cur_buf_idx;
642 u32 losless_comp_body_size;
643 u32 losless_comp_body_size_sao;
644 u32 losless_comp_header_size;
645 u32 mc_buffer_size_u_v;
646 u32 mc_buffer_size_u_v_h;
647 u32 is_idr_frame;
648 u32 is_new_pic;
649 u32 frame_done;
650 u32 frame_busy;
651 unsigned long extif_addr;
652 int double_write_mode;
653 int mmu_enable;
654#endif
655
656 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
657 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
658
659 int cur_pool;
660 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
661 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
662 struct vframe_s switching_fense_vf;
663 struct h264_dpb_stru dpb;
664 u8 init_flag;
665 u8 first_sc_checked;
666 u8 has_i_frame;
667 u8 config_bufmgr_done;
668 u32 max_reference_size;
669 u32 decode_pic_count;
670 u32 reflist_error_count;
671 int start_search_pos;
672 u32 reg_iqidct_control;
673 u32 reg_vcop_ctrl_reg;
674 u32 reg_rv_ai_mb_count;
675 u32 vld_dec_control;
676 struct vframe_s vframe_dummy;
677
678 unsigned char buffer_empty_flag;
679
680 u32 frame_width;
681 u32 frame_height;
682 u32 frame_dur;
683 u32 frame_prog;
684 u32 frame_packing_type;
685
686 struct vframe_chunk_s *chunk;
687
688 u32 stat;
689 unsigned long buf_start;
690 u32 buf_offset;
691 u32 buf_size;
692 /* u32 ucode_map_start; */
693 u32 pts_outside;
694 u32 sync_outside;
695 u32 vh264_ratio;
696 u32 vh264_rotation;
697 u32 use_idr_framerate;
698
699 u32 seq_info;
700 u32 seq_info2;
701 u32 video_signal_from_vui; /*to do .. */
702 u32 timing_info_present_flag;
703 u32 fixed_frame_rate_flag;
704 u32 bitstream_restriction_flag;
705 u32 num_reorder_frames;
706 u32 max_dec_frame_buffering;
707 u32 iframe_count;
708 u32 aspect_ratio_info;
709 u32 num_units_in_tick;
710 u32 time_scale;
711 u32 h264_ar;
712 bool h264_first_valid_pts_ready;
713 u32 h264pts1;
714 u32 h264pts2;
715 u32 pts_duration;
716 u32 h264_pts_count;
717 u32 duration_from_pts_done;
718 u32 pts_unstable;
719 u32 unstable_pts;
720 u32 last_checkout_pts;
721 u32 max_refer_buf;
722
723 s32 vh264_stream_switching_state;
724 struct vframe_s *p_last_vf;
725 u32 last_pts;
726 u32 last_pts_remainder;
727 u32 last_duration;
728 u32 last_mb_width, last_mb_height;
729 bool check_pts_discontinue;
730 bool pts_discontinue;
731 u32 wait_buffer_counter;
732 u32 first_offset;
733 u32 first_pts;
734 u64 first_pts64;
735 bool first_pts_cached;
736 u64 last_pts64;
737#if 0
738 void *sei_data_buffer;
739 dma_addr_t sei_data_buffer_phys;
740#endif
741
742 uint error_recovery_mode;
743 uint mb_total;
744 uint mb_width;
745 uint mb_height;
746
747 uint i_only;
748 int skip_frame_count;
749 bool no_poc_reorder_flag;
750 bool send_error_frame_flag;
751 dma_addr_t mc_dma_handle;
752 void *mc_cpu_addr;
753 int vh264_reset;
754
755 atomic_t vh264_active;
756
757 struct dec_sysinfo vh264_amstream_dec_info;
758
759 int dec_result;
760 struct work_struct work;
761 struct work_struct notify_work;
762 struct work_struct timeout_work;
763 void (*vdec_cb)(struct vdec_s *, void *);
764 void *vdec_cb_arg;
765
766 struct timer_list check_timer;
767
768 /**/
769 unsigned int last_frame_time;
770 u32 vf_pre_count;
771 u32 vf_get_count;
772 u32 vf_put_count;
773
774 /* timeout handle */
775 unsigned long int start_process_time;
776 unsigned int last_mby_mbx;
777 unsigned int last_vld_level;
778 unsigned int decode_timeout_count;
779 unsigned int timeout_num;
780 unsigned int search_dataempty_num;
781 unsigned int decode_timeout_num;
782 unsigned int decode_dataempty_num;
783 unsigned int buffer_empty_recover_num;
784
785 unsigned get_data_count;
786 unsigned get_data_start_time;
787 /**/
788
789 /*log*/
790 unsigned int packet_write_success_count;
791 unsigned int packet_write_EAGAIN_count;
792 unsigned int packet_write_ENOMEM_count;
793 unsigned int packet_write_EFAULT_count;
794 unsigned int total_read_size_pre;
795 unsigned int total_read_size;
796 unsigned int frame_count_pre;
797#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
798 u8 switch_dvlayer_flag;
799 u8 got_valid_nal;
800#endif
801 u8 eos;
802 u8 data_flag;
803 u32 no_error_count;
804 u32 no_error_i_count;
805 /*
806 NODISP_FLAG
807 */
808 u8 dec_flag;
809
810 u32 ucode_pause_pos;
811
812 u8 reset_bufmgr_flag;
813 u32 reset_bufmgr_count;
814 u32 cfg_param1;
815 u32 cfg_param2;
816 u32 cfg_param3;
817 u32 cfg_param4;
818 int valve_count;
819 u8 next_again_flag;
820 u32 pre_parser_wr_ptr;
821 struct firmware_s *fw;
822 struct firmware_s *fw_mmu;
823#ifdef MH264_USERDATA_ENABLE
824 /*user data*/
825 struct mutex userdata_mutex;
826 struct mh264_userdata_info_t userdata_info;
827 struct mh264_userdata_record_t ud_record;
828 int wait_for_udr_send;
829#endif
830 u32 no_mem_count;
831 u32 canvas_mode;
832 bool is_used_v4l;
833 void *v4l2_ctx;
834 bool v4l_params_parsed;
835 wait_queue_head_t wait_q;
836 u32 reg_g_status;
837 struct mutex chunks_mutex;
838 int need_cache_size;
839 u64 sc_start_time;
840 u8 frmbase_cont_flag;
841 struct vframe_qos_s vframe_qos;
842 int frameinfo_enable;
843 bool first_head_check_flag;
844 unsigned int height_aspect_ratio;
845 unsigned int width_aspect_ratio;
846 bool new_iframe_flag;
847 bool ref_err_flush_dpb_flag;
848 unsigned int first_i_policy;
849 u32 reorder_dpb_size_margin;
850 bool wait_reset_done_flag;
851};
852
853static u32 again_threshold;
854
855static void timeout_process(struct vdec_h264_hw_s *hw);
856static void dump_bufspec(struct vdec_h264_hw_s *hw,
857 const char *caller);
858static void h264_reconfig(struct vdec_h264_hw_s *hw);
859static void h264_reset_bufmgr(struct vdec_s *vdec);
860static void vh264_local_init(struct vdec_h264_hw_s *hw);
861static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
862static int vh264_stop(struct vdec_h264_hw_s *hw);
863static s32 vh264_init(struct vdec_h264_hw_s *hw);
864static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
865 u32 index);
866static void release_aux_data(struct vdec_h264_hw_s *hw,
867 int buf_spec_num);
868#ifdef ERROR_HANDLE_TEST
869static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
870#endif
871
872#define H265_PUT_SAO_4K_SET 0x03
873#define H265_ABORT_SAO_4K_SET 0x04
874#define H265_ABORT_SAO_4K_SET_DONE 0x05
875
876#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
877#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
878#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
879#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
880#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
881
882
883#define HEVC_CM_HEADER_START_ADDR 0x3628
884#define HEVC_CM_BODY_START_ADDR 0x3626
885#define HEVC_CM_BODY_LENGTH 0x3627
886#define HEVC_CM_HEADER_LENGTH 0x3629
887#define HEVC_CM_HEADER_OFFSET 0x362b
888#define HEVC_SAO_CTRL9 0x362d
889#define HEVCD_MPP_DECOMP_CTL3 0x34c4
890#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
891#define HEVC_DBLK_CFGB 0x350b
892#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
893
894#define H265_DW_NO_SCALE
895#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
896#define H265_LOSLESS_COMPRESS_MODE
897#define MAX_FRAME_4K_NUM 0x1200
898#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
899
900/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
901static u32 mem_map_mode = H265_MEM_MAP_MODE;
902
903#define MAX_SIZE_8K (8192 * 4608)
904#define MAX_SIZE_4K (4096 * 2304)
905
906static int is_oversize(int w, int h)
907{
908 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
909 MAX_SIZE_8K : MAX_SIZE_4K;
910
911 if (w < 0 || h < 0)
912 return true;
913
914 if (h != 0 && (w > max / h))
915 return true;
916
917 return false;
918}
919
920static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
921 int frame_type,
922 u32 vpts,
923 u32 vpts_valid);
924static int compute_losless_comp_body_size(int width,
925 int height, int bit_depth_10);
926static int compute_losless_comp_header_size(int width, int height);
927
928static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
929 int pic_width, int pic_height, u16 bit_depth,
930 unsigned int *mmu_index_adr) {
931 int cur_buf_idx;
932 int bit_depth_10 = (bit_depth != 0x00);
933 int picture_size;
934 u32 cur_mmu_4k_number;
935
936 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
937 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
938 picture_size = compute_losless_comp_body_size(pic_width,
939 pic_height, bit_depth_10);
940 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
941 dpb_print(DECODE_ID(hw),
942 PRINT_FLAG_MMU_DETAIL,
943 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
944 cur_buf_idx, picture_size, cur_mmu_4k_number);
945
946 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
947 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
948 cur_mmu_4k_number);
949 return -1;
950 }
951
952 return decoder_mmu_box_alloc_idx(
953 hw->mmu_box,
954 cur_buf_idx,
955 cur_mmu_4k_number,
956 mmu_index_adr);
957}
958
959static int compute_losless_comp_body_size(int width,
960 int height, int bit_depth_10)
961{
962 int width_x64;
963 int height_x32;
964 int bsize;
965
966 width_x64 = width + 63;
967 width_x64 >>= 6;
968
969 height_x32 = height + 31;
970 height_x32 >>= 5;
971
972#ifdef H264_MMU
973 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
974#else
975 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
976#endif
977 return bsize;
978}
979
980static int compute_losless_comp_header_size(int width, int height)
981{
982 int width_x64;
983 int width_x128;
984 int height_x64;
985 int hsize;
986
987 width_x64 = width + 63;
988 width_x64 >>= 6;
989
990 width_x128 = width + 127;
991 width_x128 >>= 7;
992
993 height_x64 = height + 63;
994 height_x64 >>= 6;
995
996#ifdef H264_MMU
997 hsize = 128*width_x64*height_x64;
998#else
999 hsize = 32*width_x128*height_x64;
1000#endif
1001 return hsize;
1002}
1003
1004static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1005{
1006 int ratio = 1;
1007 int dw_mode = hw->double_write_mode;
1008 if ((dw_mode == 2) ||
1009 (dw_mode == 3))
1010 ratio = 4;
1011 else if (dw_mode == 4)
1012 ratio = 2;
1013 return ratio;
1014}
1015
1016
1017static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1018{
1019 int pic_width, pic_height;
1020 int lcu_size = 16;
1021 int dw_buf_size;
1022 u32 dw_buffer_size_u_v;
1023 u32 dw_buffer_size_u_v_h;
1024 int dw_mode = hw->double_write_mode;
1025
1026 pic_width = hw->frame_width;
1027 pic_height = hw->frame_height;
1028
1029 if (dw_mode) {
1030 int pic_width_dw = pic_width /
1031 get_double_write_ratio(hw);
1032 int pic_height_dw = pic_height /
1033 get_double_write_ratio(hw);
1034
1035 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1036 pic_width_dw / lcu_size + 1 :
1037 pic_width_dw / lcu_size;
1038 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1039 pic_height_dw / lcu_size + 1 :
1040 pic_height_dw / lcu_size;
1041 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1042
1043
1044 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1045 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1046 /*64k alignment*/
1047 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1048 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1049 } else {
1050 *pdw_buffer_size_u_v_h = 0;
1051 dw_buf_size = 0;
1052 }
1053
1054 return dw_buf_size;
1055}
1056
1057
1058static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1059{
1060 int i, size;
1061 u32 canvas_addr;
1062 unsigned long maddr;
1063 int num_buff = hw->dpb.mDPB.size;
1064 int dw_size = 0;
1065 u32 dw_buffer_size_u_v_h;
1066 u32 blkmode = hw->canvas_mode;
1067 int dw_mode = hw->double_write_mode;
1068
1069 canvas_addr = ANC0_CANVAS_ADDR;
1070 for (i = 0; i < num_buff; i++)
1071 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1072
1073 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1074 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1075
1076
1077 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1078 size += dw_size;
1079 if (size > 0)
1080 size += 0x10000;
1081
1082 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1083 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1084 dw_buffer_size_u_v_h, dw_size, size);
1085
1086 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1087 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1088 hw->losless_comp_body_size,
1089 hw->losless_comp_header_size,
1090 hw->losless_comp_body_size_sao);
1091
1092 for (i = 0; i < num_buff; i++) {
1093 if (!restore) {
1094 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1095 HEADER_BUFFER_IDX(i), size,
1096 DRIVER_HEADER_NAME, &maddr) < 0) {
1097 dpb_print(DECODE_ID(hw), 0,
1098 "%s malloc compress header failed %d\n",
1099 DRIVER_HEADER_NAME, i);
1100 return;
1101 }
1102 } else
1103 maddr = hw->buffer_spec[i].alloc_header_addr;
1104 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1105 hw->buffer_spec[i].alloc_header_addr = maddr;
1106 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1107 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1108 __func__, i, (u32)maddr, size);
1109
1110 if (dw_mode) {
1111 u32 addr;
1112 int canvas_w;
1113 int canvas_h;
1114
1115 canvas_w = hw->frame_width /
1116 get_double_write_ratio(hw);
1117 canvas_h = hw->frame_height /
1118 get_double_write_ratio(hw);
1119
1120 if (hw->canvas_mode == 0)
1121 canvas_w = ALIGN(canvas_w, 32);
1122 else
1123 canvas_w = ALIGN(canvas_w, 64);
1124 canvas_h = ALIGN(canvas_h, 32);
1125
1126 hw->buffer_spec[i].dw_y_adr =
1127 maddr + hw->losless_comp_header_size;
1128
1129 hw->buffer_spec[i].dw_y_adr =
1130 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1131 << 16;
1132 hw->buffer_spec[i].dw_u_v_adr =
1133 hw->buffer_spec[i].dw_y_adr
1134 + (dw_buffer_size_u_v_h << 16) * 2;
1135
1136
1137 hw->buffer_spec[i].buf_adr
1138 = hw->buffer_spec[i].dw_y_adr;
1139 addr = hw->buffer_spec[i].buf_adr;
1140
1141
1142 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1143 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1144 hw->buffer_spec[i].dw_y_adr,
1145 hw->buffer_spec[i].dw_u_v_adr,
1146 hw->buffer_spec[i].y_addr,
1147 hw->buffer_spec[i].u_addr,
1148 hw->buffer_spec[i].v_addr,
1149 canvas_w,
1150 canvas_h);
1151
1152 hw->buffer_spec[i].canvas_config[0].phy_addr =
1153 hw->buffer_spec[i].dw_y_adr;
1154 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1155 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1156 hw->buffer_spec[i].canvas_config[0].block_mode =
1157 blkmode;
1158 hw->buffer_spec[i].canvas_config[0].endian = 7;
1159
1160 hw->buffer_spec[i].canvas_config[1].phy_addr =
1161 hw->buffer_spec[i].dw_u_v_adr;
1162 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1163 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1164 hw->buffer_spec[i].canvas_config[1].block_mode =
1165 blkmode;
1166 hw->buffer_spec[i].canvas_config[1].endian = 7;
1167 }
1168 }
1169 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1170
1171 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1172 for (i = 0; i < 32; i++)
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1174 return;
1175}
1176static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1177{
1178 u32 i;
1179 u32 ref_canv;
1180 struct Slice *pSlice = &(hw->dpb.mSlice);
1181 /*REFLIST[0]*/
1182 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1183 struct StorablePicture *ref = pSlice->listX[0][i];
1184 if (ref == NULL)
1185 return;
1186 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1187 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1188 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1189 (ref->buf_spec_num & 0x3f) << 8);
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1191 }
1192 /*REFLIST[1]*/
1193 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1194 struct StorablePicture *ref = pSlice->listX[1][i];
1195 if (ref == NULL)
1196 return;
1197 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1198 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1199 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1200 (ref->buf_spec_num & 0x3f) << 8);
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1202 }
1203 return;
1204}
1205
1206static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1207{
1208 u32 rdata32;
1209 u32 rdata32_2;
1210 u32 slice_type;
1211 struct StorablePicture *ref;
1212 struct Slice *pSlice;
1213 slice_type = hw->dpb.mSlice.slice_type;
1214 pSlice = &(hw->dpb.mSlice);
1215 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1216 if (slice_type == I_SLICE) {
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1218 return;
1219 }
1220 if (slice_type == B_SLICE) {
1221 ref = pSlice->listX[0][0];
1222 if (ref == NULL)
1223 return;
1224 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1225 ((ref->buf_spec_num & 0x3f) << 8));
1226 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1227 rdata32 = rdata32 & 0xffff;
1228 rdata32 = rdata32 | (rdata32 << 16);
1229 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1230
1231 ref = pSlice->listX[1][0];
1232 if (ref == NULL)
1233 return;
1234 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1235 ((ref->buf_spec_num & 0x3f) << 8));
1236 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1237 rdata32_2 = rdata32_2 & 0xffff;
1238 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1239 if (rdata32 == rdata32_2) {
1240 ref = pSlice->listX[1][1];
1241 if (ref == NULL)
1242 return;
1243 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1244 ((ref->buf_spec_num & 0x3f) << 8));
1245 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1246 rdata32_2 = rdata32_2 & 0xffff;
1247 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1248 }
1249 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1250 } else { /*P-PIC*/
1251 ref = pSlice->listX[0][0];
1252 if (ref == NULL)
1253 return;
1254 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1255 ((ref->buf_spec_num & 0x3f) << 8));
1256 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1257 rdata32 = rdata32 & 0xffff;
1258 rdata32 = rdata32 | (rdata32 << 16);
1259 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1260
1261 ref = pSlice->listX[0][1];
1262 if (ref == NULL)
1263 return;
1264 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1265 ((ref->buf_spec_num & 0x3f) << 8));
1266 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1267 rdata32 = rdata32 & 0xffff;
1268 rdata32 = rdata32 | (rdata32 << 16);
1269 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1270 }
1271 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1272 return;
1273}
1274
1275
1276static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1277 u32 width, u32 height) {
1278 u32 data32;
1279 u32 lcu_x_num, lcu_y_num;
1280 u32 lcu_total;
1281 u32 mc_buffer_size_u_v;
1282 u32 mc_buffer_size_u_v_h;
1283 int dw_mode = hw->double_write_mode;
1284
1285 lcu_x_num = (width + 15) >> 4;
1286 lcu_y_num = (height + 15) >> 4;
1287 lcu_total = lcu_x_num * lcu_y_num;
1288
1289 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1290 hw->mc_buffer_size_u_v_h =
1291 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1292
1293 hw->losless_comp_body_size = 0;
1294
1295 hw->losless_comp_body_size_sao =
1296 compute_losless_comp_body_size(width, height, 0);
1297 hw->losless_comp_header_size =
1298 compute_losless_comp_header_size(width, height);
1299
1300 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1301 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1302
1303 /* setup lcu_size = 16*/
1304 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1305 /*pic_width/pic_height*/
1306 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1307 (height & 0xffff) << 16 | (width & 0xffff));
1308 /* bitdepth_luma = 8*/
1309 /* bitdepth_chroma = 8*/
1310 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1311
1312#ifdef H265_LOSLESS_COMPRESS_MODE
1313 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1314 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1315#else
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1317#endif
1318 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1319 data32 &= (~0x30);
1320 data32 |= (hw->canvas_mode << 4);
1321 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1322
1323 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1324 (0x80 << 20) | (0x80 << 10) | (0xff));
1325
1326 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1327
1328 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1329 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1330 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1331 /* ipp_enable*/
1332 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1333
1334 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1335 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1336 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1337 if (dw_mode)
1338 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1339 else
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1341 }
1342
1343 data32 = READ_VREG(HEVC_SAO_CTRL0);
1344 data32 &= (~0xf);
1345 data32 |= 0x4;
1346 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1347 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1348 (width & 0xffff));
1349 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1350
1351 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1352 data32 = (lcu_x_num | lcu_y_num << 16);
1353 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1354 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1355 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16);
1357 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1358
1359 data32 = READ_VREG(HEVC_SAO_CTRL1);
1360 data32 &= (~0x3000);
1361 data32 &= (~0xff0);
1362 data32 |= endian; /* Big-Endian per 64-bit */
1363
1364 if (hw->mmu_enable && dw_mode)
1365 data32 |= ((hw->canvas_mode << 12));
1366 else
1367 data32 |= ((hw->canvas_mode << 12)|2);
1368
1369 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1370
1371#ifdef H265_DW_NO_SCALE
1372 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1373 if (hw->mmu_enable && dw_mode) {
1374 data32 = READ_VREG(HEVC_SAO_CTRL5);
1375 data32 &= (~(0xff << 16));
1376 if (dw_mode == 2 ||
1377 dw_mode == 3)
1378 data32 |= (0xff<<16);
1379 else if (dw_mode == 4)
1380 data32 |= (0x33<<16);
1381 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1382 }
1383
1384
1385#endif
1386
1387
1388#ifdef H265_LOSLESS_COMPRESS_MODE
1389 data32 = READ_VREG(HEVC_SAO_CTRL5);
1390 data32 |= (1<<9); /*8-bit smem-mode*/
1391 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1392
1393 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1394 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1395 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1396#endif
1397
1398#ifdef H265_LOSLESS_COMPRESS_MODE
1399 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1400 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1401#endif
1402
1403 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1404
1405 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1406
1407 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1408 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1409 return;
1410}
1411
1412static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1413 u32 is_new_pic, u32 is_idr)
1414{
1415 hw->is_new_pic = is_new_pic;
1416 hw->is_idr_frame = is_idr;
1417 return;
1418}
1419
1420static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1421 struct StorablePicture *pic) {
1422 u32 mc_y_adr;
1423 u32 mc_u_v_adr;
1424 u32 dw_y_adr;
1425 u32 dw_u_v_adr;
1426 u32 canvas_addr;
1427 int ret;
1428 int dw_mode = hw->double_write_mode;
1429 if (hw->is_new_pic != 1)
1430 return;
1431
1432 if (hw->is_idr_frame) {
1433 /* William TBD */
1434 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1435 }
1436
1437 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1438 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1439 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1440 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1441 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1442 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1443 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1444 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1445 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1446
1447
1448 if (dw_mode) {
1449 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1450 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1451 } else {
1452 dw_y_adr = 0;
1453 dw_u_v_adr = 0;
1454 }
1455#ifdef H265_LOSLESS_COMPRESS_MODE
1456 if (dw_mode)
1457 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1458 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1459#ifdef H264_MMU
1460 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1461#else
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1463 (mc_y_adr + hw->losless_comp_body_size));
1464#endif
1465#else
1466 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1467#endif
1468
1469#ifndef H265_LOSLESS_COMPRESS_MODE
1470 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1471#else
1472 if (dw_mode)
1473 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1474#endif
1475
1476#ifndef LOSLESS_COMPRESS_MODE
1477 if (dw_mode) {
1478 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1479 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1480 }
1481#else
1482 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1483 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1484#endif
1485
1486 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1487 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1488 hw->frame_mmu_map_addr);
1489 if (ret != 0) {
1490 dpb_print(DECODE_ID(hw),
1491 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1492 pic->buf_spec_num,
1493 ret);
1494 return;
1495 }
1496
1497 /*Reset SAO + Enable SAO slice_start*/
1498 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1499 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1500 WRITE_VREG(HEVC_SAO_INT_STATUS,
1501 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1504 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1505 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1506
1507 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1508 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1509 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1510 } else
1511 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1512 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1513 hw->frame_busy = 1;
1514 return;
1515}
1516
1517
1518static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1519 u32 buf_spec_num) {
1520 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1521 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1522 dpb_print(DECODE_ID(hw),
1523 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1524 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1525 return;
1526}
1527
1528
1529static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1530{
1531 ulong timeout = jiffies + HZ;
1532 dpb_print(DECODE_ID(hw),
1533 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1534 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1535 if (time_after(jiffies, timeout)) {
1536 dpb_print(DECODE_ID(hw),
1537 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1538 break;
1539 }
1540 }
1541 timeout = jiffies + HZ;
1542 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1543 if (time_after(jiffies, timeout)) {
1544 dpb_print(DECODE_ID(hw),
1545 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1546 break;
1547 }
1548 }
1549 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1550 hw->frame_done = 1;
1551 return;
1552}
1553
1554static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1555{
1556 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1557 if (p_H264_Dpb->mVideo.dec_picture) {
1558 release_picture(p_H264_Dpb,
1559 p_H264_Dpb->mVideo.dec_picture);
1560 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1561 p_H264_Dpb->mVideo.dec_picture = NULL;
1562 if (hw->mmu_enable)
1563 hevc_set_frame_done(hw);
1564 }
1565}
1566
1567static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1568{
1569 ulong timeout = jiffies + HZ;
1570 dpb_print(DECODE_ID(hw),
1571 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1572 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1573 if (time_after(jiffies, timeout)) {
1574 dpb_print(DECODE_ID(hw),
1575 PRINT_FLAG_MMU_DETAIL,
1576 "hevc_sao_wait_done...wait timeout!\n");
1577 break;
1578 }
1579 }
1580 timeout = jiffies + HZ;
1581 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1582 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1583 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1584 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1585 H265_ABORT_SAO_4K_SET_DONE) {
1586 if (time_after(jiffies, timeout)) {
1587 dpb_print(DECODE_ID(hw),
1588 PRINT_FLAG_MMU_DETAIL,
1589 "wait h265_abort_sao_4k_set_done timeout!\n");
1590 break;
1591 }
1592 }
1593 }
1594 amhevc_stop();
1595 hw->frame_busy = 0;
1596 hw->frame_done = 0;
1597 dpb_print(DECODE_ID(hw),
1598 PRINT_FLAG_MMU_DETAIL,
1599 "sao wait done ,hevc stop!\n");
1600 }
1601 return;
1602}
1603static void buf_spec_init(struct vdec_h264_hw_s *hw)
1604{
1605 int i;
1606 unsigned long flags;
1607 spin_lock_irqsave(&hw->bufspec_lock, flags);
1608 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1609 hw->buffer_spec[i].used = -1;
1610 hw->buffer_spec[i].canvas_pos = -1;
1611 }
1612 if (dpb_is_debug(DECODE_ID(hw),
1613 PRINT_FLAG_DUMP_BUFSPEC))
1614 dump_bufspec(hw, __func__);
1615 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1616}
1617
1618/*is active in buf management */
1619static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1620 int buf_spec_num)
1621{
1622 unsigned char ret = 0;
1623 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1624 hw->buffer_spec[buf_spec_num].used == 2 ||
1625 hw->buffer_spec[buf_spec_num].used == 3 ||
1626 hw->buffer_spec[buf_spec_num].used == 5)
1627 ret = 1;
1628 return ret;
1629}
1630
1631static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1632 int buf_spec_num)
1633{
1634 unsigned char ret = 0;
1635 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1636 hw->buffer_spec[buf_spec_num].used == 3 ||
1637 hw->buffer_spec[buf_spec_num].used == 5)
1638 ret = 1;
1639 return ret;
1640}
1641
1642static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1643{
1644 if (hw->mmu_enable) {
1645 if (hw->buffer_spec[i].alloc_header_addr)
1646 return 0;
1647 else
1648 return -1;
1649 } else {
1650
1651 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1652 int addr;
1653#ifdef VDEC_DW
1654 int orig_buf_size;
1655 orig_buf_size = buf_size;
1656 if (IS_VDEC_DW(hw) == 1)
1657 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1658 else if (IS_VDEC_DW(hw) == 2)
1659 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1660#endif
1661 if (hw->buffer_spec[i].cma_alloc_addr)
1662 return 0;
1663
1664 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1665 PAGE_ALIGN(buf_size), DRIVER_NAME,
1666 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1667 hw->buffer_spec[i].cma_alloc_addr = 0;
1668 if (hw->no_mem_count++ > 3) {
1669 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1670 hw->reset_bufmgr_flag = 1;
1671 }
1672 dpb_print(DECODE_ID(hw), 0,
1673 "%s, fail to alloc buf for bufspec%d, try later\n",
1674 __func__, i
1675 );
1676 return -1;
1677 } else {
1678 hw->no_mem_count = 0;
1679 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1680 }
1681
1682 hw->buffer_spec[i].buf_adr =
1683 hw->buffer_spec[i].cma_alloc_addr;
1684 addr = hw->buffer_spec[i].buf_adr;
1685
1686
1687 hw->buffer_spec[i].y_addr = addr;
1688 addr += hw->mb_total << 8;
1689 hw->buffer_spec[i].u_addr = addr;
1690 hw->buffer_spec[i].v_addr = addr;
1691 addr += hw->mb_total << 7;
1692
1693 hw->buffer_spec[i].canvas_config[0].phy_addr =
1694 hw->buffer_spec[i].y_addr;
1695 hw->buffer_spec[i].canvas_config[0].width =
1696 hw->mb_width << 4;
1697 hw->buffer_spec[i].canvas_config[0].height =
1698 hw->mb_height << 4;
1699 hw->buffer_spec[i].canvas_config[0].block_mode =
1700 hw->canvas_mode;
1701
1702 hw->buffer_spec[i].canvas_config[1].phy_addr =
1703 hw->buffer_spec[i].u_addr;
1704 hw->buffer_spec[i].canvas_config[1].width =
1705 hw->mb_width << 4;
1706 hw->buffer_spec[i].canvas_config[1].height =
1707 hw->mb_height << 3;
1708 hw->buffer_spec[i].canvas_config[1].block_mode =
1709 hw->canvas_mode;
1710 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1711 "%s, alloc buf for bufspec%d\n",
1712 __func__, i
1713 );
1714#ifdef VDEC_DW
1715
1716 if (!IS_VDEC_DW(hw))
1717 return 0;
1718 else if (IS_VDEC_DW(hw) == 1) {
1719 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1720 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1721 addr += hw->mb_total << 7;
1722 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1723 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1724 addr += hw->mb_total << 6;
1725
1726 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1727 hw->buffer_spec[i].vdec_dw_y_addr;
1728 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1729 hw->mb_width << 3;
1730 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1731 hw->mb_height << 4;
1732 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1733 CANVAS_BLKMODE_32X32;
1734
1735 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1736 hw->buffer_spec[i].vdec_dw_u_addr;
1737 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1738 hw->mb_width << 3;
1739 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1740 hw->mb_height << 3;
1741 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1742 CANVAS_BLKMODE_32X32;
1743 }else {
1744 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1745 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1746 addr += hw->mb_total << 6;
1747 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1748 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1749 addr += hw->mb_total << 5;
1750
1751 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1752 hw->buffer_spec[i].vdec_dw_y_addr;
1753 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1754 hw->mb_width << 3;
1755 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1756 hw->mb_height << 3;
1757 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1758 CANVAS_BLKMODE_32X32;
1759
1760 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1761 hw->buffer_spec[i].vdec_dw_u_addr;
1762 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1763 hw->mb_width << 3;
1764 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1765 hw->mb_height << 2;
1766 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1767 CANVAS_BLKMODE_32X32;
1768 }
1769 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1770 "%s, vdec_dw: alloc buf for bufspec%d\n",
1771 __func__, i
1772 );
1773#endif
1774 }
1775 return 0;
1776}
1777
1778static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1779{
1780 int ret = 0;
1781 struct aml_vcodec_ctx *ctx = NULL;
1782 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1783 struct canvas_config_s *y_canvas_cfg = NULL;
1784 struct canvas_config_s *c_canvas_cfg = NULL;
1785 struct vdec_v4l2_buffer *fb = NULL;
1786 unsigned int y_addr = 0, c_addr = 0;
1787
1788 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1789 pr_err("the v4l context has err.\n");
1790 return -1;
1791 }
1792
1793 if (bs->cma_alloc_addr)
1794 return 0;
1795
1796 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1797 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1798 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1799 ctx->id, __func__,
1800 (hw->mb_total << 8) + (hw->mb_total << 7));
1801
1802 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1803 if (ret < 0) {
1804 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1805 "[%d] get fb fail.\n", ctx->id);
1806 return ret;
1807 }
1808
1809 bs->cma_alloc_addr = (unsigned long)fb;
1810 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1811 "[%d] %s(), cma alloc addr: 0x%x\n",
1812 ctx->id, __func__, bs->cma_alloc_addr);
1813
1814 if (fb->num_planes == 1) {
1815 y_addr = fb->m.mem[0].addr;
1816 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1817 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1818 } else if (fb->num_planes == 2) {
1819 y_addr = fb->m.mem[0].addr;
1820 c_addr = fb->m.mem[1].addr;
1821 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1822 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1823 }
1824
1825 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1826 "[%d] %s(), y_addr: %x, size: %u\n",
1827 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1828 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1829 "[%d] %s(), c_addr: %x, size: %u\n",
1830 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1831
1832 bs->y_addr = y_addr;
1833 bs->u_addr = c_addr;
1834 bs->v_addr = c_addr;
1835
1836 y_canvas_cfg = &bs->canvas_config[0];
1837 c_canvas_cfg = &bs->canvas_config[1];
1838
1839 y_canvas_cfg->phy_addr = y_addr;
1840 y_canvas_cfg->width = hw->mb_width << 4;
1841 y_canvas_cfg->height = hw->mb_height << 4;
1842 y_canvas_cfg->block_mode = hw->canvas_mode;
1843 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1844 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1845 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1846 y_canvas_cfg->width,y_canvas_cfg->height);
1847
1848 c_canvas_cfg->phy_addr = c_addr;
1849 c_canvas_cfg->width = hw->mb_width << 4;
1850 c_canvas_cfg->height = hw->mb_height << 3;
1851 c_canvas_cfg->block_mode = hw->canvas_mode;
1852 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1853 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1854 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1855 c_canvas_cfg->width, c_canvas_cfg->height);
1856
1857 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1858 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1859
1860 return ret;
1861}
1862
1863static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1864{
1865 int blkmode = hw->canvas_mode;
1866 int endian = 0;
1867
1868 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1869 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1870 endian = 7;
1871 else
1872 endian = 0;
1873 }
1874
1875 if (hw->is_used_v4l)
1876 endian = 7;
1877
1878 canvas_config_ex(hw->buffer_spec[i].
1879 y_canvas_index,
1880 hw->buffer_spec[i].y_addr,
1881 hw->mb_width << 4,
1882 hw->mb_height << 4,
1883 CANVAS_ADDR_NOWRAP,
1884 blkmode,
1885 endian);
1886
1887 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1888 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1889 (1 << 11) | /* canvas_blk32_wr */
1890 (blkmode << 10) | /* canvas_blk32*/
1891 (1 << 8) | /* canvas_index_wr*/
1892 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1893 );
1894 }
1895
1896 canvas_config_ex(hw->buffer_spec[i].
1897 u_canvas_index,
1898 hw->buffer_spec[i].u_addr,
1899 hw->mb_width << 4,
1900 hw->mb_height << 3,
1901 CANVAS_ADDR_NOWRAP,
1902 blkmode,
1903 endian);
1904
1905 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1906 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1907 (1 << 11) |
1908 (blkmode << 10) |
1909 (1 << 8) |
1910 (hw->buffer_spec[i].u_canvas_index << 0));
1911 }
1912
1913 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1914 spec2canvas(&hw->buffer_spec[i]));
1915
1916
1917#ifdef VDEC_DW
1918 if (!IS_VDEC_DW(hw))
1919 return;
1920 else if (IS_VDEC_DW(hw) == 1) {
1921 canvas_config_ex(hw->buffer_spec[i].
1922 vdec_dw_y_canvas_index,
1923 hw->buffer_spec[i].vdec_dw_y_addr,
1924 hw->mb_width << 3,
1925 hw->mb_height << 4,
1926 CANVAS_ADDR_NOWRAP,
1927 blkmode,
1928 endian);
1929 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1930 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1931 (1 << 11) |
1932 (blkmode << 10) |
1933 (1 << 8) |
1934 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1935 }
1936 canvas_config_ex(hw->buffer_spec[i].
1937 vdec_dw_u_canvas_index,
1938 hw->buffer_spec[i].vdec_dw_u_addr,
1939 hw->mb_width << 3,
1940 hw->mb_height << 3,
1941 CANVAS_ADDR_NOWRAP,
1942 blkmode,
1943 endian);
1944 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1945 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1946 (1 << 11) |
1947 (blkmode << 10) |
1948 (1 << 8) |
1949 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1950 }
1951 } else {
1952 canvas_config_ex(hw->buffer_spec[i].
1953 vdec_dw_y_canvas_index,
1954 hw->buffer_spec[i].vdec_dw_y_addr,
1955 hw->mb_width << 3,
1956 hw->mb_height << 3,
1957 CANVAS_ADDR_NOWRAP,
1958 blkmode,
1959 endian);
1960 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1961 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1962 (1 << 11) |
1963 (blkmode << 10) |
1964 (1 << 8) |
1965 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1966 }
1967
1968 canvas_config_ex(hw->buffer_spec[i].
1969 vdec_dw_u_canvas_index,
1970 hw->buffer_spec[i].vdec_dw_u_addr,
1971 hw->mb_width << 3,
1972 hw->mb_height << 2,
1973 CANVAS_ADDR_NOWRAP,
1974 blkmode,
1975 endian);
1976 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1977 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1978 (1 << 11) |
1979 (blkmode << 10) |
1980 (1 << 8) |
1981 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1982 }
1983 }
1984#endif
1985}
1986
1987static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1988{
1989 u32 blkmode = hw->canvas_mode;
1990 int canvas_w;
1991 int canvas_h;
1992
1993 canvas_w = hw->frame_width /
1994 get_double_write_ratio(hw);
1995 canvas_h = hw->frame_height /
1996 get_double_write_ratio(hw);
1997
1998 if (hw->canvas_mode == 0)
1999 canvas_w = ALIGN(canvas_w, 32);
2000 else
2001 canvas_w = ALIGN(canvas_w, 64);
2002 canvas_h = ALIGN(canvas_h, 32);
2003
2004 canvas_config_ex(hw->buffer_spec[i].
2005 y_canvas_index,
2006 hw->buffer_spec[i].dw_y_adr,
2007 canvas_w,
2008 canvas_h,
2009 CANVAS_ADDR_NOWRAP,
2010 blkmode,
2011 7);
2012
2013 canvas_config_ex(hw->buffer_spec[i].
2014 u_canvas_index,
2015 hw->buffer_spec[i].dw_u_v_adr,
2016 canvas_w,
2017 canvas_h,
2018 CANVAS_ADDR_NOWRAP,
2019 blkmode,
2020 7);
2021}
2022
2023
2024int get_free_buf_idx(struct vdec_s *vdec)
2025{
2026 int i;
2027 unsigned long addr, flags;
2028 int index = -1;
2029 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2030 int buf_total = BUFSPEC_POOL_SIZE;
2031
2032 if (hw->is_used_v4l)
2033 buf_total = hw->dpb.mDPB.size;
2034
2035 spin_lock_irqsave(&hw->bufspec_lock, flags);
2036 /*hw->start_search_pos = 0;*/
2037 for (i = hw->start_search_pos; i < buf_total; i++) {
2038 if (hw->mmu_enable)
2039 addr = hw->buffer_spec[i].alloc_header_addr;
2040 else {
2041 addr = hw->buffer_spec[i].cma_alloc_addr;
2042 if (hw->is_used_v4l && !addr) {
2043 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2044 config_decode_canvas(hw, i);
2045 addr = hw->buffer_spec[i].cma_alloc_addr;
2046 }
2047 }
2048 }
2049 if (hw->buffer_spec[i].used == 0 && addr) {
2050 hw->buffer_spec[i].used = 1;
2051 hw->start_search_pos = i+1;
2052 index = i;
2053 break;
2054 }
2055 }
2056 if (index < 0) {
2057 for (i = 0; i < hw->start_search_pos; i++) {
2058 if (hw->mmu_enable)
2059 addr = hw->buffer_spec[i].alloc_header_addr;
2060 else {
2061 addr = hw->buffer_spec[i].cma_alloc_addr;
2062 if (hw->is_used_v4l && !addr) {
2063 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2064 config_decode_canvas(hw, i);
2065 addr = hw->buffer_spec[i].cma_alloc_addr;
2066 }
2067 }
2068 }
2069 if (hw->buffer_spec[i].used == 0 && addr) {
2070 hw->buffer_spec[i].used = 1;
2071 hw->start_search_pos = i+1;
2072 index = i;
2073 break;
2074 }
2075 }
2076 }
2077 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2078 if (hw->start_search_pos >= buf_total)
2079 hw->start_search_pos = 0;
2080 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2081 "%s, buf_spec_num %d\n", __func__, index);
2082
2083 if (index < 0) {
2084 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2085 "%s fail\n", __func__);
2086 vmh264_dump_state(vdec);
2087 }
2088
2089 if (dpb_is_debug(DECODE_ID(hw),
2090 PRINT_FLAG_DUMP_BUFSPEC))
2091 dump_bufspec(hw, __func__);
2092 return index;
2093}
2094
2095int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2096{
2097 /*u32 cur_buf_idx;*/
2098 unsigned long flags;
2099 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2100 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2101 "%s buf_spec_num %d used %d\n",
2102 __func__, buf_spec_num,
2103 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2104 if (buf_spec_num >= 0 &&
2105 buf_spec_num < BUFSPEC_POOL_SIZE
2106 ) {
2107 spin_lock_irqsave(&hw->bufspec_lock, flags);
2108 hw->buffer_spec[buf_spec_num].used = 0;
2109 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2110 if (hw->mmu_enable) {
2111 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2112 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2113 cur_buf_idx = cur_buf_idx&0xff;*/
2114 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2115 }
2116 release_aux_data(hw, buf_spec_num);
2117 }
2118 if (dpb_is_debug(DECODE_ID(hw),
2119 PRINT_FLAG_DUMP_BUFSPEC))
2120 dump_bufspec(hw, __func__);
2121 return 0;
2122}
2123
2124static void config_buf_specs(struct vdec_s *vdec)
2125{
2126 int i, j;
2127 unsigned long flags;
2128 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2129 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2130
2131 spin_lock_irqsave(&hw->bufspec_lock, flags);
2132 for (i = 0, j = 0;
2133 j < hw->dpb.mDPB.size
2134 && i < BUFSPEC_POOL_SIZE;
2135 i++) {
2136 int canvas;
2137 if (hw->buffer_spec[i].used != -1)
2138 continue;
2139 if (vdec->parallel_dec == 1) {
2140 if (hw->buffer_spec[i].y_canvas_index == -1)
2141 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2142 if (hw->buffer_spec[i].u_canvas_index == -1) {
2143 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2144 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2145 }
2146#ifdef VDEC_DW
2147 if (IS_VDEC_DW(hw)) {
2148 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2149 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2150 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2151 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2152 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2153 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2154 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2155 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2156 }
2157 }
2158#endif
2159 } else {
2160 canvas = vdec->get_canvas(j * mode, 2);
2161 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2162 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2163 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2164 dpb_print(DECODE_ID(hw),
2165 PRINT_FLAG_DPB_DETAIL,
2166 "config canvas (%d) %x for bufspec %d\r\n",
2167 j, canvas, i);
2168#ifdef VDEC_DW
2169 if (IS_VDEC_DW(hw)) {
2170 canvas = vdec->get_canvas(j * mode + 1, 2);
2171 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2172 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2173 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2174 dpb_print(DECODE_ID(hw),
2175 PRINT_FLAG_DPB_DETAIL,
2176 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2177 j, canvas, i);
2178 }
2179#endif
2180 }
2181
2182 hw->buffer_spec[i].used = 0;
2183 hw->buffer_spec[i].canvas_pos = j;
2184
2185
2186 j++;
2187 }
2188 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2189}
2190
2191static void config_buf_specs_ex(struct vdec_s *vdec)
2192{
2193 int i, j;
2194 unsigned long flags;
2195 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2196 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2197
2198 spin_lock_irqsave(&hw->bufspec_lock, flags);
2199 for (i = 0, j = 0;
2200 j < hw->dpb.mDPB.size
2201 && i < BUFSPEC_POOL_SIZE;
2202 i++) {
2203 int canvas = 0;
2204 if (hw->buffer_spec[i].used != -1)
2205 continue;
2206 if (vdec->parallel_dec == 1) {
2207 if (hw->buffer_spec[i].y_canvas_index == -1)
2208 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2209 if (hw->buffer_spec[i].u_canvas_index == -1) {
2210 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2211 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2212 }
2213#ifdef VDEC_DW
2214 if (IS_VDEC_DW(hw)) {
2215 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2216 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2217 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2218 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2219 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2220 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2221 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2222 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2223 }
2224 }
2225#endif
2226 } else {
2227 canvas = vdec->get_canvas(j* mode, 2);
2228 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2229 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2230 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2231
2232 dpb_print(DECODE_ID(hw),
2233 PRINT_FLAG_DPB_DETAIL,
2234 "config canvas (%d) %x for bufspec %d\r\n",
2235 j, canvas, i);
2236#ifdef VDEC_DW
2237 if (IS_VDEC_DW(hw)) {
2238 canvas = vdec->get_canvas(j*mode + 1, 2);
2239 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2240 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2241 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2242 dpb_print(DECODE_ID(hw),
2243 PRINT_FLAG_DPB_DETAIL,
2244 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2245 j, canvas, i);
2246 }
2247#endif
2248 }
2249
2250 hw->buffer_spec[i].used = 0;
2251 hw->buffer_spec[i].alloc_header_addr = 0;
2252 hw->buffer_spec[i].canvas_pos = j;
2253
2254 j++;
2255 }
2256 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2257}
2258
2259
2260static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2261 unsigned char release_all)
2262{
2263 int i;
2264 unsigned long flags;
2265 unsigned char dealloc_flag = 0;
2266 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2267 if (hw->buffer_spec[i].used == 4 ||
2268 release_all) {
2269 dealloc_flag = 1;
2270 dpb_print(DECODE_ID(hw),
2271 PRINT_FLAG_DPB_DETAIL,
2272 "%s buf_spec_num %d\n",
2273 __func__, i
2274 );
2275 spin_lock_irqsave
2276 (&hw->bufspec_lock, flags);
2277 hw->buffer_spec[i].used = -1;
2278 spin_unlock_irqrestore
2279 (&hw->bufspec_lock, flags);
2280 release_aux_data(hw, i);
2281
2282 if (!hw->mmu_enable) {
2283 if (hw->buffer_spec[i].cma_alloc_addr) {
2284 if (!hw->is_used_v4l) {
2285 decoder_bmmu_box_free_idx(
2286 hw->bmmu_box,
2287 i);
2288 }
2289 spin_lock_irqsave
2290 (&hw->bufspec_lock, flags);
2291 hw->buffer_spec[i].cma_alloc_addr = 0;
2292 hw->buffer_spec[i].buf_adr = 0;
2293 spin_unlock_irqrestore
2294 (&hw->bufspec_lock, flags);
2295 }
2296 } else {
2297 if (hw->buffer_spec[i].alloc_header_addr) {
2298 decoder_mmu_box_free_idx(
2299 hw->mmu_box,
2300 i);
2301 spin_lock_irqsave
2302 (&hw->bufspec_lock, flags);
2303 hw->buffer_spec[i].
2304 alloc_header_addr = 0;
2305 hw->buffer_spec[i].buf_adr = 0;
2306 spin_unlock_irqrestore
2307 (&hw->bufspec_lock, flags);
2308 }
2309 }
2310 }
2311 }
2312 if (dealloc_flag &&
2313 dpb_is_debug(DECODE_ID(hw),
2314 PRINT_FLAG_DUMP_BUFSPEC))
2315 dump_bufspec(hw, __func__);
2316 return;
2317}
2318
2319unsigned char have_free_buf_spec(struct vdec_s *vdec)
2320{
2321 int i;
2322 unsigned long addr;
2323 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2324 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2325 int index = -1;
2326 int ret = 0;
2327 int allocated_count = 0;
2328 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2329 if (hw->mmu_enable)
2330 addr = hw->buffer_spec[i].alloc_header_addr;
2331 else
2332 addr = hw->buffer_spec[i].cma_alloc_addr;
2333 if (hw->buffer_spec[i].used == 0) {
2334
2335 if (addr)
2336 return 1;
2337 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2338 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2339 index = i;
2340 }
2341 }
2342 if (addr)
2343 allocated_count++;
2344 }
2345 if (index >= 0) {
2346 mutex_lock(&vmh264_mutex);
2347 dealloc_buf_specs(hw, 0);
2348 if (max_alloc_buf_count == 0 ||
2349 allocated_count < max_alloc_buf_count) {
2350 if (hw->is_used_v4l)
2351 ret = 1;
2352 else if (alloc_one_buf_spec(hw, index) >= 0)
2353 ret = 1;
2354 }
2355 mutex_unlock(&vmh264_mutex);
2356 }
2357 return ret;
2358}
2359
2360static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2361 int canvas_pos)
2362{
2363 int i;
2364 int j = 0;
2365 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2366 if (hw->buffer_spec[i].canvas_pos >= 0) {
2367 if (j == canvas_pos)
2368 return i;
2369 j++;
2370 }
2371 }
2372 return -1;
2373}
2374static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2375 struct vframe_s *vf, int index)
2376{
2377 if (index < 0) {
2378 vf->mem_handle = NULL;
2379 vf->mem_head_handle = NULL;
2380 } else if (vf->type & VIDTYPE_SCATTER) {
2381 vf->mem_handle =
2382 decoder_mmu_box_get_mem_handle(
2383 hw->mmu_box, index);
2384 vf->mem_head_handle =
2385 decoder_bmmu_box_get_mem_handle(
2386 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2387 } else {
2388 vf->mem_handle =
2389 decoder_bmmu_box_get_mem_handle(
2390 hw->bmmu_box, VF_BUFFER_IDX(index));
2391 /* vf->mem_head_handle =
2392 decoder_bmmu_box_get_mem_handle(
2393 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2394 }
2395 return;
2396}
2397static int check_force_interlace(struct vdec_h264_hw_s *hw,
2398 struct FrameStore *frame)
2399{
2400 int bForceInterlace = 0;
2401 /* no di in secure mode, disable force di */
2402 if (vdec_secure(hw_to_vdec(hw)))
2403 return 0;
2404 if (frame->frame) {
2405 if (frame->frame->coded_frame
2406 && !frame->frame->frame_mbs_only_flag) {
2407 if (frame->frame->structure == FRAME)
2408 return 1;
2409 }
2410 }
2411
2412 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2413 && hw->bitstream_restriction_flag
2414 && (hw->frame_width == 1920)
2415 && (hw->frame_height >= 1080)
2416 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2417 bForceInterlace = 1;
2418 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2419 && (hw->frame_width == 720)
2420 && (hw->frame_height == 576)
2421 && (hw->frame_dur == 3840)) {
2422 bForceInterlace = 1;
2423 }
2424
2425 return bForceInterlace;
2426}
2427
2428static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2429{
2430 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2431 if (frame->slice_type == I_SLICE)
2432 vframe_qos->type = 1;
2433 else if (frame->slice_type == P_SLICE)
2434 vframe_qos->type = 2;
2435 else if (frame->slice_type == B_SLICE)
2436 vframe_qos->type = 3;
2437
2438 vframe_qos->size = frame->frame_size;
2439 vframe_qos->pts = frame->pts64;
2440
2441 vframe_qos->max_mv = frame->max_mv;
2442 vframe_qos->avg_mv = frame->avg_mv;
2443 vframe_qos->min_mv = frame->min_mv;
2444/*
2445 pr_info("mv: max:%d, avg:%d, min:%d\n",
2446 vframe_qos->max_mv,
2447 vframe_qos->avg_mv,
2448 vframe_qos->min_mv);
2449*/
2450
2451 vframe_qos->max_qp = frame->max_qp;
2452 vframe_qos->avg_qp = frame->avg_qp;
2453 vframe_qos->min_qp = frame->min_qp;
2454/*
2455 pr_info("qp: max:%d, avg:%d, min:%d\n",
2456 vframe_qos->max_qp,
2457 vframe_qos->avg_qp,
2458 vframe_qos->min_qp);
2459*/
2460
2461 vframe_qos->max_skip = frame->max_skip;
2462 vframe_qos->avg_skip = frame->avg_skip;
2463 vframe_qos->min_skip = frame->min_skip;
2464/*
2465 pr_info("skip: max:%d, avg:%d, min:%d\n",
2466 vframe_qos->max_skip,
2467 vframe_qos->avg_skip,
2468 vframe_qos->min_skip);
2469*/
2470 vframe_qos->num++;
2471 if (hw->frameinfo_enable)
2472 vdec_fill_frame_info(vframe_qos, 1);
2473}
2474
2475static int is_iframe(struct FrameStore *frame) {
2476
2477 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2478 return 1;
2479 }
2480 return 0;
2481}
2482
2483
2484
2485int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2486{
2487 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2488 struct vframe_s *vf = NULL;
2489 int buffer_index = frame->buf_spec_num;
2490 int vf_count = 1;
2491 int i;
2492 int bForceInterlace = 0;
2493
2494 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2495 dpb_print(DECODE_ID(hw), 0,
2496 "%s, buffer_index 0x%x is beyond range\n",
2497 __func__, buffer_index);
2498 return -1;
2499 }
2500 if (force_disp_bufspec_num & 0x100) {
2501 /*recycle directly*/
2502 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2503 hw->buffer_spec[frame->buf_spec_num].used != 5)
2504 set_frame_output_flag(&hw->dpb, frame->index);
2505
2506 /*make pre_output not set*/
2507 return -1;
2508 }
2509 if (error_proc_policy & 0x1000) {
2510 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2511 int error_skip_frame_count = error_skip_count & 0xfff;
2512 if (((hw->no_error_count < error_skip_frame_count)
2513 && (error_skip_i_count == 0 ||
2514 hw->no_error_i_count < error_skip_i_count))
2515 && (!(frame->data_flag & I_FLAG)))
2516 frame->data_flag |= ERROR_FLAG;
2517 }
2518 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2519 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2520 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2521 frame->poc, hw->data_flag & ERROR_FLAG,
2522 error_proc_policy);
2523 if (frame->frame == NULL &&
2524 ((frame->is_used == 1 && frame->top_field)
2525 || (frame->is_used == 2 && frame->bottom_field))) {
2526 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2527 "%s Error frame_num %d used %d\n",
2528 __func__, frame->frame_num, frame->is_used);
2529 frame->data_flag |= ERROR_FLAG;
2530 }
2531 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2532 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2533 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2534 0, &frame->pts64) == 0)) {
2535 hw->last_pts64 = frame->pts64;
2536 hw->last_pts = frame->pts;
2537 } else {
2538 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2539 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2540 }
2541 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2542 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2543 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2544 frame->offset_delimiter, frame->pts,hw->last_pts,
2545 frame->pts64, hw->last_pts64, hw->frame_dur);
2546 hw->last_pts64 = frame->pts64;
2547 hw->last_pts = frame->pts;
2548 }
2549 if ((frame->data_flag & NODISP_FLAG) ||
2550 (frame->data_flag & NULL_FLAG) ||
2551 ((!hw->send_error_frame_flag) &&
2552 (frame->data_flag & ERROR_FLAG)) ||
2553 ((hw->i_only & 0x1) &&
2554 (!(frame->data_flag & I_FLAG)))
2555 ) {
2556 set_frame_output_flag(&hw->dpb, frame->index);
2557 return 0; /*do not return -1,
2558 otherwise flush_dpb() will not flush all dbp frames*/
2559 }
2560
2561 display_frame_count[DECODE_ID(hw)]++;
2562
2563 if (dpb_is_debug(DECODE_ID(hw),
2564 PRINT_FLAG_DPB_DETAIL)) {
2565 dpb_print(DECODE_ID(hw), 0,
2566 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2567 __func__, frame->index, frame->poc,
2568 frame->buf_spec_num);
2569 print_pic_info(DECODE_ID(hw), "predis_frm",
2570 frame->frame, -1);
2571 print_pic_info(DECODE_ID(hw), "predis_top",
2572 frame->top_field, -1);
2573 print_pic_info(DECODE_ID(hw), "predis_bot",
2574 frame->bottom_field, -1);
2575 }
2576
2577 if (!is_interlace(frame))
2578 vf_count = 1;
2579 else
2580 vf_count = 2;
2581 bForceInterlace = check_force_interlace(hw, frame);
2582 if (bForceInterlace)
2583 vf_count = 2;
2584 hw->buffer_spec[buffer_index].vf_ref = 0;
2585 fill_frame_info(hw, frame);
2586 for (i = 0; i < vf_count; i++) {
2587 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2588 vf == NULL) {
2589 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2590 "%s fatal error, no available buffer slot.\n",
2591 __func__);
2592 return -1;
2593 }
2594 vf->duration_pulldown = 0;
2595 if (!(is_iframe(frame)) && hw->unstable_pts) {
2596 vf->pts = 0;
2597 vf->pts_us64 = 0;
2598 vf->timestamp = 0;
2599 vf->index = VF_INDEX(frame->index, buffer_index);
2600 } else {
2601 vf->pts = frame->pts;
2602 vf->pts_us64 = frame->pts64;
2603 vf->timestamp = frame->timestamp;
2604 vf->index = VF_INDEX(frame->index, buffer_index);
2605 }
2606
2607 if (hw->is_used_v4l) {
2608 vf->v4l_mem_handle
2609 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2610 }
2611
2612 if (hw->mmu_enable) {
2613 if (hw->double_write_mode & 0x10) {
2614 /* double write only */
2615 vf->compBodyAddr = 0;
2616 vf->compHeadAddr = 0;
2617 } else {
2618 /*head adr*/
2619 vf->compHeadAddr =
2620 hw->buffer_spec[buffer_index].alloc_header_addr;
2621 /*body adr*/
2622 vf->compBodyAddr = 0;
2623 vf->canvas0Addr = vf->canvas1Addr = 0;
2624 }
2625
2626 vf->type = VIDTYPE_SCATTER;
2627
2628 if (hw->double_write_mode) {
2629 vf->type |= VIDTYPE_PROGRESSIVE
2630 | VIDTYPE_VIU_FIELD;
2631 vf->type |= VIDTYPE_VIU_NV21;
2632 if (hw->double_write_mode == 3)
2633 vf->type |= VIDTYPE_COMPRESS;
2634
2635 vf->canvas0Addr = vf->canvas1Addr = -1;
2636 vf->plane_num = 2;
2637 vf->canvas0_config[0] =
2638 hw->buffer_spec[buffer_index].
2639 canvas_config[0];
2640 vf->canvas0_config[1] =
2641 hw->buffer_spec[buffer_index].
2642 canvas_config[1];
2643
2644 vf->canvas1_config[0] =
2645 hw->buffer_spec[buffer_index].
2646 canvas_config[0];
2647 vf->canvas1_config[1] =
2648 hw->buffer_spec[buffer_index].
2649 canvas_config[1];
2650
2651 } else {
2652 vf->type |=
2653 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2654 vf->canvas0Addr = vf->canvas1Addr = 0;
2655 }
2656
2657 vf->bitdepth =
2658 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2659
2660 vf->compWidth = hw->frame_width;
2661 vf->compHeight = hw->frame_height;
2662 } else {
2663 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2664 VIDTYPE_VIU_NV21;
2665
2666 vf->canvas0Addr = vf->canvas1Addr =
2667 spec2canvas(&hw->buffer_spec[buffer_index]);
2668#ifdef VDEC_DW
2669 if (IS_VDEC_DW(hw))
2670 vf->canvas0Addr = vf->canvas1Addr =
2671 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2672#endif
2673
2674 }
2675 set_frame_info(hw, vf, buffer_index);
2676
2677 if (hw->mmu_enable && hw->double_write_mode) {
2678 vf->width = hw->frame_width /
2679 get_double_write_ratio(hw);
2680 vf->height = hw->frame_height /
2681 get_double_write_ratio(hw);
2682 }
2683
2684 vf->flag = 0;
2685 if (frame->data_flag & I_FLAG)
2686 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2687 if (frame->data_flag & ERROR_FLAG)
2688 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2689 update_vf_memhandle(hw, vf, buffer_index);
2690 hw->buffer_spec[buffer_index].used = 2;
2691 hw->buffer_spec[buffer_index].vf_ref++;
2692
2693 if (bForceInterlace || is_interlace(frame)) {
2694 vf->type =
2695 VIDTYPE_INTERLACE_FIRST |
2696 VIDTYPE_VIU_NV21;
2697
2698 if (bForceInterlace) {
2699 vf->type |= (i == 0 ?
2700 VIDTYPE_INTERLACE_TOP :
2701 VIDTYPE_INTERLACE_BOTTOM);
2702 if (i == 1) {
2703 vf->pts = 0;
2704 vf->pts_us64 = 0;
2705 }
2706 } else if (frame->top_field->poc <=
2707 frame->bottom_field->poc) /*top first*/
2708 vf->type |= (i == 0 ?
2709 VIDTYPE_INTERLACE_TOP :
2710 VIDTYPE_INTERLACE_BOTTOM);
2711 else
2712 vf->type |= (i == 0 ?
2713 VIDTYPE_INTERLACE_BOTTOM :
2714 VIDTYPE_INTERLACE_TOP);
2715 vf->duration = vf->duration/2;
2716 }
2717
2718 if (i == 0)
2719 decoder_do_frame_check(hw_to_vdec(hw), vf);
2720
2721 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2722 vf->sar_width = hw->width_aspect_ratio;
2723 vf->sar_height = hw->height_aspect_ratio;
2724
2725 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2726 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2727 hw->vf_pre_count++;
2728 vdec->vdec_fps_detec(vdec->id);
2729 if (without_display_mode == 0) {
2730 vf_notify_receiver(vdec->vf_provider_name,
2731 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2732 } else
2733 vh264_vf_put(vh264_vf_get(vdec), vdec);
2734 }
2735 if (dpb_is_debug(DECODE_ID(hw),
2736 PRINT_FLAG_DUMP_BUFSPEC))
2737 dump_bufspec(hw, __func__);
2738
2739 return 0;
2740}
2741
2742int notify_v4l_eos(struct vdec_s *vdec)
2743{
2744 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2745 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2746 struct vframe_s *vf = &hw->vframe_dummy;
2747 struct vdec_v4l2_buffer *fb = NULL;
2748 int index = INVALID_IDX;
2749 ulong expires;
2750
2751 if (hw->is_used_v4l && hw->eos) {
2752 expires = jiffies + msecs_to_jiffies(2000);
2753 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2754 if (time_after(jiffies, expires))
2755 break;
2756 }
2757
2758 if (index == INVALID_IDX) {
2759 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2760 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2761 return -1;
2762 }
2763 }
2764
2765 vf->type |= VIDTYPE_V4L_EOS;
2766 vf->timestamp = ULONG_MAX;
2767 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2768 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2769 hw->buffer_spec[index].cma_alloc_addr;
2770
2771 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2772
2773 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2774 vf_notify_receiver(vdec->vf_provider_name,
2775 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2776
2777 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2778 }
2779
2780 return 0;
2781}
2782
2783/******************
2784 * Hardware config
2785 */
2786char *slice_type_name[] = {
2787 "P_SLICE ",
2788 "B_SLICE ",
2789 "I_SLICE ",
2790 "SP_SLICE",
2791 "SI_SLICE",
2792};
2793
2794char *picture_structure_name[] = {
2795 "FRAME",
2796 "TOP_FIELD",
2797 "BOTTOM_FIELD"
2798};
2799
2800void print_pic_info(int decindex, const char *info,
2801 struct StorablePicture *pic,
2802 int slice_type)
2803{
2804 if (pic)
2805 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2806 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2807 info,
2808 picture_structure_name[pic->structure],
2809 pic->coded_frame ? "Frame" : "Field",
2810 (slice_type < 0 ||
2811 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2812 pic->mb_aff_frame_flag,
2813 pic->poc,
2814 pic->pic_num,
2815 pic->buf_spec_num,
2816 pic->data_flag);
2817}
2818
2819static void reset_process_time(struct vdec_h264_hw_s *hw)
2820{
2821 if (hw->start_process_time) {
2822 unsigned process_time =
2823 1000 * (jiffies - hw->start_process_time) / HZ;
2824 hw->start_process_time = 0;
2825 if (process_time > max_process_time[DECODE_ID(hw)])
2826 max_process_time[DECODE_ID(hw)] = process_time;
2827 }
2828}
2829
2830static void start_process_time(struct vdec_h264_hw_s *hw)
2831{
2832 hw->decode_timeout_count = 10;
2833 hw->start_process_time = jiffies;
2834}
2835
2836static void config_aux_buf(struct vdec_h264_hw_s *hw)
2837{
2838 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2839 WRITE_VREG(H264_AUX_DATA_SIZE,
2840 ((hw->prefix_aux_size >> 4) << 16) |
2841 (hw->suffix_aux_size >> 4)
2842 );
2843}
2844
2845/*
2846* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2847*/
2848static void set_aux_data(struct vdec_h264_hw_s *hw,
2849 struct StorablePicture *pic, unsigned char suffix_flag,
2850 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2851{
2852 int i;
2853 unsigned short *aux_adr;
2854 unsigned size_reg_val =
2855 READ_VREG(H264_AUX_DATA_SIZE);
2856 unsigned aux_count = 0;
2857 int aux_size = 0;
2858 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2859 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2860 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2861 return;
2862
2863 if (suffix_flag) {
2864 aux_adr = (unsigned short *)
2865 (hw_buf->aux_addr +
2866 hw_buf->prefix_aux_size);
2867 aux_count =
2868 ((size_reg_val & 0xffff) << 4)
2869 >> 1;
2870 aux_size =
2871 hw_buf->suffix_aux_size;
2872 } else {
2873 aux_adr =
2874 (unsigned short *)hw_buf->aux_addr;
2875 aux_count =
2876 ((size_reg_val >> 16) << 4)
2877 >> 1;
2878 aux_size =
2879 hw_buf->prefix_aux_size;
2880 }
2881 if (dpb_is_debug(DECODE_ID(hw),
2882 PRINT_FLAG_DPB_DETAIL)) {
2883 dpb_print(DECODE_ID(hw), 0,
2884 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2885 __func__, AUX_DATA_SIZE(pic),
2886 aux_count, suffix_flag, dv_meta_flag);
2887 }
2888 if (aux_size > 0 && aux_count > 0) {
2889 int heads_size = 0;
2890 int new_size;
2891 char *new_buf;
2892 for (i = 0; i < aux_count; i++) {
2893 unsigned char tag = aux_adr[i] >> 8;
2894 if (tag != 0 && tag != 0xff) {
2895 if (dv_meta_flag == 0)
2896 heads_size += 8;
2897 else if (dv_meta_flag == 1 && tag == 0x1)
2898 heads_size += 8;
2899 else if (dv_meta_flag == 2 && tag != 0x1)
2900 heads_size += 8;
2901 }
2902 }
2903 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2904 new_buf = krealloc(AUX_DATA_BUF(pic),
2905 new_size,
2906 GFP_KERNEL);
2907 if (new_buf) {
2908 unsigned char valid_tag = 0;
2909 unsigned char *h =
2910 new_buf +
2911 AUX_DATA_SIZE(pic);
2912 unsigned char *p = h + 8;
2913 int len = 0;
2914 int padding_len = 0;
2915 AUX_DATA_BUF(pic) = new_buf;
2916 for (i = 0; i < aux_count; i += 4) {
2917 int ii;
2918 unsigned char tag = aux_adr[i + 3] >> 8;
2919 if (tag != 0 && tag != 0xff) {
2920 if (dv_meta_flag == 0)
2921 valid_tag = 1;
2922 else if (dv_meta_flag == 1
2923 && tag == 0x1)
2924 valid_tag = 1;
2925 else if (dv_meta_flag == 2
2926 && tag != 0x1)
2927 valid_tag = 1;
2928 else
2929 valid_tag = 0;
2930 if (valid_tag && len > 0) {
2931 AUX_DATA_SIZE(pic) +=
2932 (len + 8);
2933 h[0] =
2934 (len >> 24) & 0xff;
2935 h[1] =
2936 (len >> 16) & 0xff;
2937 h[2] =
2938 (len >> 8) & 0xff;
2939 h[3] =
2940 (len >> 0) & 0xff;
2941 h[6] =
2942 (padding_len >> 8)
2943 & 0xff;
2944 h[7] =
2945 (padding_len) & 0xff;
2946 h += (len + 8);
2947 p += 8;
2948 len = 0;
2949 padding_len = 0;
2950 }
2951 if (valid_tag) {
2952 h[4] = tag;
2953 h[5] = 0;
2954 h[6] = 0;
2955 h[7] = 0;
2956 }
2957 }
2958 if (valid_tag) {
2959 for (ii = 0; ii < 4; ii++) {
2960 unsigned short aa =
2961 aux_adr[i + 3
2962 - ii];
2963 *p = aa & 0xff;
2964 p++;
2965 len++;
2966 /*if ((aa >> 8) == 0xff)
2967 padding_len++;*/
2968 }
2969 }
2970 }
2971 if (len > 0) {
2972 AUX_DATA_SIZE(pic) += (len + 8);
2973 h[0] = (len >> 24) & 0xff;
2974 h[1] = (len >> 16) & 0xff;
2975 h[2] = (len >> 8) & 0xff;
2976 h[3] = (len >> 0) & 0xff;
2977 h[6] = (padding_len >> 8) & 0xff;
2978 h[7] = (padding_len) & 0xff;
2979 }
2980 if (dpb_is_debug(DECODE_ID(hw),
2981 PRINT_FLAG_DPB_DETAIL)) {
2982 dpb_print(DECODE_ID(hw), 0,
2983 "aux: (size %d) suffix_flag %d\n",
2984 AUX_DATA_SIZE(pic), suffix_flag);
2985 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2986 dpb_print_cont(DECODE_ID(hw), 0,
2987 "%02x ", AUX_DATA_BUF(pic)[i]);
2988 if (((i + 1) & 0xf) == 0)
2989 dpb_print_cont(
2990 DECODE_ID(hw),
2991 0, "\n");
2992 }
2993 dpb_print_cont(DECODE_ID(hw),
2994 0, "\n");
2995 }
2996
2997 }
2998 }
2999
3000}
3001
3002static void release_aux_data(struct vdec_h264_hw_s *hw,
3003 int buf_spec_num)
3004{
3005 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3006 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3007 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3008}
3009
3010static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3011{
3012 int i;
3013 unsigned short *aux_adr =
3014 (unsigned short *)
3015 hw->aux_addr;
3016 unsigned aux_size =
3017 (READ_VREG(H264_AUX_DATA_SIZE)
3018 >> 16) << 4;
3019
3020 if (hw->prefix_aux_size > 0) {
3021 dpb_print(DECODE_ID(hw),
3022 0,
3023 "prefix aux: (size %d)\n",
3024 aux_size);
3025 for (i = 0; i <
3026 (aux_size >> 1); i++) {
3027 dpb_print_cont(DECODE_ID(hw),
3028 0,
3029 "%04x ",
3030 *(aux_adr + i));
3031 if (((i + 1) & 0xf)
3032 == 0)
3033 dpb_print_cont(
3034 DECODE_ID(hw),
3035 0, "\n");
3036 }
3037 }
3038 if (hw->suffix_aux_size > 0) {
3039 aux_adr = (unsigned short *)
3040 (hw->aux_addr +
3041 hw->prefix_aux_size);
3042 aux_size =
3043 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3044 << 4;
3045 dpb_print(DECODE_ID(hw),
3046 0,
3047 "suffix aux: (size %d)\n",
3048 aux_size);
3049 for (i = 0; i <
3050 (aux_size >> 1); i++) {
3051 dpb_print_cont(DECODE_ID(hw),
3052 0,
3053 "%04x ", *(aux_adr + i));
3054 if (((i + 1) & 0xf) == 0)
3055 dpb_print_cont(DECODE_ID(hw),
3056 0, "\n");
3057 }
3058 }
3059}
3060
3061static void config_decode_mode(struct vdec_h264_hw_s *hw)
3062{
3063#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3064 struct vdec_s *vdec = hw_to_vdec(hw);
3065#endif
3066 if (input_frame_based(hw_to_vdec(hw)))
3067 WRITE_VREG(H264_DECODE_MODE,
3068 DECODE_MODE_MULTI_FRAMEBASE);
3069#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3070 else if (vdec->slave)
3071 WRITE_VREG(H264_DECODE_MODE,
3072 (hw->got_valid_nal << 8) |
3073 DECODE_MODE_MULTI_DVBAL);
3074 else if (vdec->master)
3075 WRITE_VREG(H264_DECODE_MODE,
3076 (hw->got_valid_nal << 8) |
3077 DECODE_MODE_MULTI_DVENL);
3078#endif
3079 else
3080 WRITE_VREG(H264_DECODE_MODE,
3081 DECODE_MODE_MULTI_STREAMBASE);
3082 WRITE_VREG(H264_DECODE_SEQINFO,
3083 hw->seq_info2);
3084 WRITE_VREG(HEAD_PADING_REG, 0);
3085
3086 if (hw->init_flag == 0)
3087 WRITE_VREG(INIT_FLAG_REG, 0);
3088 else
3089 WRITE_VREG(INIT_FLAG_REG, 1);
3090}
3091int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3092{
3093 /* static int count = 0; */
3094 int ret = 0;
3095 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3096 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3097 unsigned int colocate_adr_offset;
3098 unsigned int val;
3099 struct StorablePicture *last_pic = hw->last_dec_picture;
3100
3101#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3102 int colocate_buf_index;
3103#endif
3104#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3105#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3106#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3107#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3108
3109#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3110/* bit 31:30 -- L1[0] picture coding structure,
3111 * 00 - top field, 01 - bottom field,
3112 * 10 - frame, 11 - mbaff frame
3113 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3114 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3115 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3116 */
3117#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3118
3119/* bit 15 -- flush co_mb_data to DDR -- W-Only
3120 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3121 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3122 * bit 9 -- soft_reset -- W-Only
3123 * bit 8 -- upgent
3124 * bit 7:2 -- h264_co_mb_mem_wr_addr
3125 * bit 1:0 -- h264_co_mb_info_wr_ptr
3126 */
3127#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3128
3129 unsigned long canvas_adr;
3130 unsigned int ref_reg_val;
3131 unsigned int one_ref_cfg = 0;
3132 int h264_buffer_info_data_write_count;
3133 int i, j;
3134 unsigned int colocate_wr_adr;
3135 unsigned int colocate_rd_adr;
3136 unsigned char use_direct_8x8;
3137 int canvas_pos;
3138 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3139 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3140 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3141 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3142 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3143
3144 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3145 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3146 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3147 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3148 canvas_pos);
3149 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3150
3151#ifdef VDEC_DW
3152 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3153 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3154 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3155#endif
3156 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3157 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3158
3159 if (!hw->mmu_enable) {
3160 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3161 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3162 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3163#ifdef VDEC_DW
3164 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3165 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3166 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3167#endif
3168 } else
3169 hevc_sao_set_pic_buffer(hw, pic);
3170
3171 if (pic->mb_aff_frame_flag)
3172 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3173 else if (pic->structure == TOP_FIELD)
3174 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3175 else if (pic->structure == BOTTOM_FIELD)
3176 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3177 else
3178 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3179
3180 if (pic->bottom_poc < pic->top_poc)
3181 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3182
3183 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3184 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3185 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3186
3187 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3188 int long_term_flag;
3189 i = get_buf_spec_by_canvas_pos(hw, j);
3190 if (i < 0)
3191 break;
3192 long_term_flag =
3193 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3194 if (long_term_flag > 0) {
3195 if (long_term_flag & 0x1)
3196 hw->buffer_spec[i].info0 |= (1 << 4);
3197 else
3198 hw->buffer_spec[i].info0 &= ~(1 << 4);
3199
3200 if (long_term_flag & 0x2)
3201 hw->buffer_spec[i].info0 |= (1 << 5);
3202 else
3203 hw->buffer_spec[i].info0 &= ~(1 << 5);
3204 }
3205
3206 if (i == pic->buf_spec_num)
3207 WRITE_VREG(H264_BUFFER_INFO_DATA,
3208 hw->buffer_spec[i].info0 | 0xf);
3209 else
3210 WRITE_VREG(H264_BUFFER_INFO_DATA,
3211 hw->buffer_spec[i].info0);
3212 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3213 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3214 }
3215
3216 /* config reference buffer */
3217 if (hw->mmu_enable) {
3218 hevc_mcr_config_mc_ref(hw);
3219 hevc_mcr_config_mcrcc(hw);
3220 }
3221
3222 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3223 "list0 size %d\n", pSlice->listXsize[0]);
3224 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3225 ref_reg_val = 0;
3226 j = 0;
3227 h264_buffer_info_data_write_count = 0;
3228
3229 //disable this read cache when frame width <= 64 (4MBs)
3230 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3231 if (hw->frame_width <= 64)
3232 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3233 else
3234 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3235
3236 if (last_pic)
3237 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3238 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3239 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3240 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3241 last_pic && (last_pic->data_flag & ERROR_FLAG)
3242 && (!(last_pic->slice_type == B_SLICE))
3243 && (!(pSlice->slice_type == I_SLICE))) {
3244 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3245 "no i/idr error mark\n");
3246 hw->data_flag |= ERROR_FLAG;
3247 pic->data_flag |= ERROR_FLAG;
3248 }
3249
3250 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3251 /*ref list 0 */
3252 struct StorablePicture *ref = pSlice->listX[0][i];
3253 unsigned int cfg;
3254 /* bit[6:5] - frame/field info,
3255 * 01 - top, 10 - bottom, 11 - frame
3256 */
3257 #ifdef ERROR_CHECK
3258 if (ref == NULL) {
3259 hw->data_flag |= ERROR_FLAG;
3260 pic->data_flag |= ERROR_FLAG;
3261 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3262 return -1;
3263 }
3264 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3265 hw->data_flag |= ERROR_FLAG;
3266 pic->data_flag |= ERROR_FLAG;
3267 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3268 }
3269 if (ref->data_flag & NULL_FLAG)
3270 hw->data_flag |= NULL_FLAG;
3271#endif
3272 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3273
3274 if (ref->structure == TOP_FIELD)
3275 cfg = 0x1;
3276 else if (ref->structure == BOTTOM_FIELD)
3277 cfg = 0x2;
3278 else /* FRAME */
3279 cfg = 0x3;
3280
3281 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3282 ref_reg_val <<= 8;
3283 ref_reg_val |= one_ref_cfg;
3284 j++;
3285
3286 if (j == 4) {
3287 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3288 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3289 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3290 h264_buffer_info_data_write_count++;
3291 j = 0;
3292 }
3293 print_pic_info(DECODE_ID(hw), "list0",
3294 pSlice->listX[0][i], -1);
3295 }
3296 if (j != 0) {
3297 while (j != 4) {
3298 ref_reg_val <<= 8;
3299 ref_reg_val |= one_ref_cfg;
3300 j++;
3301 }
3302 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3303 "H264_BUFFER_INFO_DATA: %x\n",
3304 ref_reg_val);
3305 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3306 h264_buffer_info_data_write_count++;
3307 }
3308 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3309 (one_ref_cfg << 8) | one_ref_cfg;
3310 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3311 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3312
3313 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3314 "list1 size %d\n", pSlice->listXsize[1]);
3315 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3316 ref_reg_val = 0;
3317 j = 0;
3318
3319 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3320 /* ref list 0 */
3321 struct StorablePicture *ref = pSlice->listX[1][i];
3322 unsigned int cfg;
3323 /* bit[6:5] - frame/field info,
3324 * 01 - top, 10 - bottom, 11 - frame
3325 */
3326
3327 #ifdef ERROR_CHECK
3328 if (ref == NULL) {
3329 hw->data_flag |= ERROR_FLAG;
3330 pic->data_flag |= ERROR_FLAG;
3331 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3332 return -2;
3333 }
3334 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3335 pic->data_flag |= ERROR_FLAG;
3336 hw->data_flag |= ERROR_FLAG;
3337 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3338 }
3339 if (ref->data_flag & NULL_FLAG)
3340 hw->data_flag |= NULL_FLAG;
3341#endif
3342 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3343 if (ref->structure == TOP_FIELD)
3344 cfg = 0x1;
3345 else if (ref->structure == BOTTOM_FIELD)
3346 cfg = 0x2;
3347 else /* FRAME */
3348 cfg = 0x3;
3349 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3350 ref_reg_val <<= 8;
3351 ref_reg_val |= one_ref_cfg;
3352 j++;
3353
3354 if (j == 4) {
3355 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3356 "H264_BUFFER_INFO_DATA: %x\n",
3357 ref_reg_val);
3358 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3359 j = 0;
3360 }
3361 print_pic_info(DECODE_ID(hw), "list1",
3362 pSlice->listX[1][i], -1);
3363 }
3364 if (j != 0) {
3365 while (j != 4) {
3366 ref_reg_val <<= 8;
3367 ref_reg_val |= one_ref_cfg;
3368 j++;
3369 }
3370 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3371 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3372 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3373 }
3374
3375 /* configure co-locate buffer */
3376 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3377 ;
3378 if ((pSlice->mode_8x8_flags & 0x4) &&
3379 (pSlice->mode_8x8_flags & 0x2))
3380 use_direct_8x8 = 1;
3381 else
3382 use_direct_8x8 = 0;
3383
3384#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3385 colocate_adr_offset =
3386 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3387 ? 1 : 2) * 96;
3388 if (use_direct_8x8)
3389 colocate_adr_offset >>= 2;
3390
3391 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3392 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3393 colocate_adr_offset, pSlice->first_mb_in_slice,
3394 colocate_adr_offset * pSlice->first_mb_in_slice);
3395
3396 colocate_adr_offset *= pSlice->first_mb_in_slice;
3397
3398 if ((pic->colocated_buf_index >= 0) &&
3399 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3400 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3401 ((p_H264_Dpb->colocated_buf_size *
3402 pic->colocated_buf_index)
3403 >> (use_direct_8x8 ? 2 : 0));
3404 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3405 p_H264_Dpb->colocated_mv_addr_end) {
3406 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3407 "Error, colocate buf is not enough, index is %d\n",
3408 pic->colocated_buf_index);
3409 ret = -3;
3410 }
3411 val = colocate_wr_adr + colocate_adr_offset;
3412 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3413 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3414 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3415 val, pSlice->first_mb_in_slice, pic->structure,
3416 colocate_adr_offset, pSlice->mode_8x8_flags,
3417 p_H264_Dpb->colocated_buf_size);
3418 } else {
3419 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3420 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3421 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3422 }
3423#else
3424 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3425 colocate_adr_offset =
3426 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3427 if (use_direct_8x8)
3428 colocate_adr_offset >>= 2;
3429
3430 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3431 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3432 colocate_adr_offset, pSlice->first_mb_in_slice,
3433 colocate_adr_offset * pSlice->first_mb_in_slice);
3434
3435 colocate_adr_offset *= pSlice->first_mb_in_slice;
3436
3437 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3438 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3439 (use_direct_8x8 ? 2 : 0));
3440
3441 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3442 p_H264_Dpb->colocated_mv_addr_end) {
3443 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3444 "Error, colocate buf is not enough, col buf index is %d\n",
3445 colocate_buf_index);
3446 ret = -4;
3447 }
3448 val = colocate_wr_adr + colocate_adr_offset;
3449 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3450 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3451 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3452 val, pSlice->first_mb_in_slice, pic->structure,
3453 colocate_adr_offset, pSlice->mode_8x8_flags,
3454 p_H264_Dpb->colocated_buf_size);
3455#endif
3456 if (pSlice->listXsize[1] > 0) {
3457 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3458 /* H264_CO_MB_RD_ADDR[bit 31:30],
3459 * original picture structure of L1[0],
3460 * 00 - top field, 01 - bottom field,
3461 * 10 - frame, 11 - mbaff frame
3462 */
3463 int l10_structure;
3464 int cur_colocate_ref_type;
3465 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3466 * 0 - top, 1 - bot
3467 */
3468 unsigned int val;
3469#ifdef ERROR_CHECK
3470 if (colocate_pic == NULL) {
3471 hw->data_flag |= ERROR_FLAG;
3472 pic->data_flag |= ERROR_FLAG;
3473 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3474 return -5;
3475 }
3476 if (colocate_pic->data_flag & ERROR_FLAG) {
3477 pic->data_flag |= ERROR_FLAG;
3478 hw->data_flag |= ERROR_FLAG;
3479 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3480 }
3481 if (colocate_pic->data_flag & NULL_FLAG)
3482 hw->data_flag |= NULL_FLAG;
3483#endif
3484
3485 if (colocate_pic->mb_aff_frame_flag)
3486 l10_structure = 3;
3487 else {
3488 if (colocate_pic->coded_frame)
3489 l10_structure = 2;
3490 else
3491 l10_structure = (colocate_pic->structure ==
3492 BOTTOM_FIELD) ? 1 : 0;
3493 }
3494#if 0
3495 /*case0016, p16,
3496 *cur_colocate_ref_type should be configured base on current pic
3497 */
3498 if (pic->structure == FRAME &&
3499 pic->mb_aff_frame_flag)
3500 cur_colocate_ref_type = 0;
3501 else if (pic->structure == BOTTOM_FIELD)
3502 cur_colocate_ref_type = 1;
3503 else
3504 cur_colocate_ref_type = 0;
3505#else
3506 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3507 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3508 pic->mb_aff_frame_flag,
3509 pic->structure,
3510 pic->coded_frame);
3511 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3512 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3513 colocate_pic->mb_aff_frame_flag,
3514 colocate_pic->structure,
3515 colocate_pic->coded_frame);
3516 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3517 cur_colocate_ref_type =
3518 (abs(pic->poc - colocate_pic->top_poc)
3519 < abs(pic->poc -
3520 colocate_pic->bottom_poc)) ? 0 : 1;
3521 } else
3522 cur_colocate_ref_type =
3523 (colocate_pic->structure
3524 == BOTTOM_FIELD) ? 1 : 0;
3525#endif
3526
3527#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3528 if ((colocate_pic->colocated_buf_index >= 0) &&
3529 (colocate_pic->colocated_buf_index <
3530 p_H264_Dpb->colocated_buf_count)) {
3531 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3532 ((p_H264_Dpb->colocated_buf_size *
3533 colocate_pic->colocated_buf_index)
3534 >> (use_direct_8x8 ? 2 : 0));
3535 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3536 p_H264_Dpb->colocated_mv_addr_end) {
3537 dpb_print(DECODE_ID(hw),
3538 PRINT_FLAG_ERROR,
3539 "Error, colocate buf is not enough, index is %d\n",
3540 colocate_pic->colocated_buf_index);
3541 ret = -6;
3542 }
3543 /* bit 31:30 -- L1[0] picture coding structure,
3544 * 00 - top field, 01 - bottom field,
3545 * 10 - frame, 11 - mbaff frame
3546 * bit 29 - L1[0] top/bot for B field pciture,
3547 * 0 - top, 1 - bot
3548 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3549 * -- only used for B Picture Direct mode
3550 * [2:0] will set to 3'b000
3551 */
3552 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3553 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3554 (l10_structure << 30) |
3555 (cur_colocate_ref_type << 29);
3556 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3557 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3558 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3559 colocate_pic->colocated_buf_index,
3560 val, colocate_rd_adr + colocate_adr_offset,
3561 colocate_pic->structure,
3562 colocate_pic->mb_aff_frame_flag);
3563 } else {
3564 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3565 "Error, reference pic has no colocated buf\n");
3566 ret = -7;
3567 }
3568#else
3569 colocate_buf_index =
3570 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3571 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3572 ((p_H264_Dpb->colocated_buf_size *
3573 colocate_buf_index)
3574 >> (use_direct_8x8 ? 2 : 0));
3575 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3576 p_H264_Dpb->colocated_mv_addr_end) {
3577 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3578 "Error, colocate buf is not enough, col buf index is %d\n",
3579 colocate_buf_index);
3580 ret = -8;
3581 }
3582 /* bit 31:30 -- L1[0] picture coding structure,
3583 * 00 - top field, 01 - bottom field,
3584 * 10 - frame, 11 - mbaff frame
3585 * bit 29 - L1[0] top/bot for B field pciture,
3586 * 0 - top, 1 - bot
3587 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3588 * -- only used for B Picture Direct mode
3589 * [2:0] will set to 3'b000
3590 */
3591 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3592 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3593 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3594 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3595 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3596 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3597 val, colocate_pic->structure,
3598 colocate_pic->mb_aff_frame_flag);
3599#endif
3600 }
3601 return ret;
3602}
3603
3604static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3605{
3606 unsigned long flags;
3607 struct vdec_s *vdec = op_arg;
3608 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3609
3610 spin_lock_irqsave(&hw->lock, flags);
3611
3612 states->vf_pool_size = VF_POOL_SIZE;
3613 states->buf_free_num = kfifo_len(&hw->newframe_q);
3614 states->buf_avail_num = kfifo_len(&hw->display_q);
3615
3616 spin_unlock_irqrestore(&hw->lock, flags);
3617
3618 return 0;
3619}
3620
3621static struct vframe_s *vh264_vf_peek(void *op_arg)
3622{
3623 struct vframe_s *vf[2] = {0, 0};
3624 struct vdec_s *vdec = op_arg;
3625 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3626
3627 if (!hw)
3628 return NULL;
3629
3630 if (force_disp_bufspec_num & 0x100) {
3631 if (force_disp_bufspec_num & 0x200)
3632 return NULL;
3633 return &hw->vframe_dummy;
3634 }
3635
3636 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3637 if (vf[1]) {
3638 vf[0]->next_vf_pts_valid = true;
3639 vf[0]->next_vf_pts = vf[1]->pts;
3640 } else
3641 vf[0]->next_vf_pts_valid = false;
3642 return vf[0];
3643 }
3644
3645 return NULL;
3646}
3647
3648static struct vframe_s *vh264_vf_get(void *op_arg)
3649{
3650 struct vframe_s *vf;
3651 struct vdec_s *vdec = op_arg;
3652 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3653
3654 if (!hw)
3655 return NULL;
3656
3657 if (force_disp_bufspec_num & 0x100) {
3658 int buffer_index = force_disp_bufspec_num & 0xff;
3659 if (force_disp_bufspec_num & 0x200)
3660 return NULL;
3661
3662 vf = &hw->vframe_dummy;
3663 vf->duration_pulldown = 0;
3664 vf->pts = 0;
3665 vf->pts_us64 = 0;
3666 set_frame_info(hw, vf, buffer_index);
3667 vf->flag = 0;
3668 if (hw->mmu_enable) {
3669 if (hw->double_write_mode & 0x10) {
3670 /* double write only */
3671 vf->compBodyAddr = 0;
3672 vf->compHeadAddr = 0;
3673 } else {
3674 /*head adr*/
3675 vf->compHeadAddr =
3676 hw->buffer_spec[buffer_index].alloc_header_addr;
3677 /*body adr*/
3678 vf->compBodyAddr = 0;
3679 vf->canvas0Addr = vf->canvas1Addr = 0;
3680 }
3681
3682 vf->type = VIDTYPE_SCATTER;
3683
3684 if (hw->double_write_mode) {
3685 vf->type |= VIDTYPE_PROGRESSIVE
3686 | VIDTYPE_VIU_FIELD;
3687 vf->type |= VIDTYPE_VIU_NV21;
3688 if (hw->double_write_mode == 3)
3689 vf->type |= VIDTYPE_COMPRESS;
3690
3691 vf->canvas0Addr = vf->canvas1Addr = -1;
3692 vf->plane_num = 2;
3693 vf->canvas0_config[0] =
3694 hw->buffer_spec[buffer_index].
3695 canvas_config[0];
3696 vf->canvas0_config[1] =
3697 hw->buffer_spec[buffer_index].
3698 canvas_config[1];
3699
3700 vf->canvas1_config[0] =
3701 hw->buffer_spec[buffer_index].
3702 canvas_config[0];
3703 vf->canvas1_config[1] =
3704 hw->buffer_spec[buffer_index].
3705 canvas_config[1];
3706 } else {
3707 vf->type |=
3708 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3709 vf->canvas0Addr = vf->canvas1Addr = 0;
3710 }
3711 vf->bitdepth =
3712 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3713
3714 vf->compWidth = hw->frame_width;
3715 vf->compHeight = hw->frame_height;
3716
3717 if (hw->double_write_mode) {
3718 vf->width = hw->frame_width /
3719 get_double_write_ratio(hw);
3720 vf->height = hw->frame_height /
3721 get_double_write_ratio(hw);
3722 }
3723 } else {
3724 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3725 VIDTYPE_VIU_NV21;
3726 vf->canvas0Addr = vf->canvas1Addr =
3727 spec2canvas(&hw->buffer_spec[buffer_index]);
3728 }
3729
3730 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3731 hw->bmmu_box, buffer_index);*/
3732 update_vf_memhandle(hw, vf, buffer_index);
3733 force_disp_bufspec_num |= 0x200;
3734 return vf;
3735 }
3736
3737 if (kfifo_get(&hw->display_q, &vf)) {
3738 int time = jiffies;
3739 unsigned int frame_interval =
3740 1000*(time - hw->last_frame_time)/HZ;
3741 struct vframe_s *next_vf;
3742 if (dpb_is_debug(DECODE_ID(hw),
3743 PRINT_FLAG_VDEC_DETAIL)) {
3744 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3745 int frame_index = FRAME_INDEX(vf->index);
3746 if (frame_index < 0 ||
3747 frame_index >= DPB_SIZE_MAX) {
3748 dpb_print(DECODE_ID(hw), 0,
3749 "%s vf index 0x%x error\r\n",
3750 __func__, vf->index);
3751 } else {
3752 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3753 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3754 __func__, BUFSPEC_INDEX(vf->index), vf,
3755 p_H264_Dpb->mFrameStore[frame_index].poc,
3756 vf->duration, vf->pts, frame_interval);
3757 }
3758 }
3759 if (hw->last_frame_time > 0) {
3760 if (frame_interval >
3761 max_get_frame_interval[DECODE_ID(hw)])
3762 max_get_frame_interval[DECODE_ID(hw)]
3763 = frame_interval;
3764 }
3765 hw->last_frame_time = time;
3766 hw->vf_get_count++;
3767 if (kfifo_peek(&hw->display_q, &next_vf)) {
3768 vf->next_vf_pts_valid = true;
3769 vf->next_vf_pts = next_vf->pts;
3770 } else
3771 vf->next_vf_pts_valid = false;
3772 return vf;
3773 }
3774
3775 return NULL;
3776}
3777
3778static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3779{
3780 struct vdec_s *vdec = op_arg;
3781 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3782 int buf_spec_num;
3783 int frame_index;
3784
3785 if (vf == (&hw->vframe_dummy))
3786 return;
3787 if (vf->index == -1) {
3788 dpb_print(DECODE_ID(hw), 0,
3789 "Warning: %s vf %p invalid index\r\n",
3790 __func__, vf);
3791 return;
3792 }
3793 frame_index = FRAME_INDEX(vf->index);
3794 buf_spec_num = BUFSPEC_INDEX(vf->index);
3795 if (frame_index < 0 ||
3796 frame_index >= DPB_SIZE_MAX ||
3797 buf_spec_num < 0 ||
3798 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3799 dpb_print(DECODE_ID(hw), 0,
3800 "%s vf index 0x%x error\r\n",
3801 __func__, vf->index);
3802 return;
3803 }
3804 /*get_buf_spec_idx_by_canvas_config(hw,
3805 &vf->canvas0_config[0]);*/
3806 if (hw->buffer_spec[buf_spec_num].used == 2) {
3807 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3808 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3809 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3810 __func__, vf, frame_index,
3811 p_H264_Dpb->mFrameStore[frame_index].poc,
3812 buf_spec_num,
3813 hw->buffer_spec[buf_spec_num].used,
3814 hw->buffer_spec[buf_spec_num].vf_ref);
3815 hw->buffer_spec[buf_spec_num].vf_ref--;
3816 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3817 set_frame_output_flag(&hw->dpb, frame_index);
3818 } else {
3819 unsigned long flags;
3820 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3821 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3822 __func__, vf, buf_spec_num,
3823 hw->buffer_spec[buf_spec_num].used,
3824 hw->buffer_spec[buf_spec_num].vf_ref);
3825 spin_lock_irqsave(&hw->bufspec_lock, flags);
3826 hw->buffer_spec[buf_spec_num].vf_ref--;
3827 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3828 if (hw->buffer_spec[buf_spec_num].used == 3)
3829 hw->buffer_spec[buf_spec_num].used = 4;
3830 else if (hw->buffer_spec[buf_spec_num].used == 5)
3831 hw->buffer_spec[buf_spec_num].used = 0;
3832 }
3833 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3834 if (dpb_is_debug(DECODE_ID(hw),
3835 PRINT_FLAG_DUMP_BUFSPEC))
3836 dump_bufspec(hw, __func__);
3837
3838 }
3839
3840 hw->vf_put_count++;
3841 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3842
3843#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3844 if (hw->buffer_empty_flag)
3845 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3846}
3847
3848static int vh264_event_cb(int type, void *data, void *op_arg)
3849{
3850 unsigned long flags;
3851 struct vdec_s *vdec = op_arg;
3852 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3853
3854 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3855 struct provider_aux_req_s *req =
3856 (struct provider_aux_req_s *)data;
3857 int buf_spec_num;
3858
3859 if (!req->vf) {
3860 req->aux_size = hw->vf_put_count;
3861 return 0;
3862 }
3863 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3864 spin_lock_irqsave(&hw->lock, flags);
3865 req->aux_buf = NULL;
3866 req->aux_size = 0;
3867 if (buf_spec_num >= 0 &&
3868 buf_spec_num < BUFSPEC_POOL_SIZE &&
3869 is_buf_spec_in_disp_q(hw, buf_spec_num)
3870 ) {
3871 req->aux_buf =
3872 hw->buffer_spec[buf_spec_num].aux_data_buf;
3873 req->aux_size =
3874 hw->buffer_spec[buf_spec_num].aux_data_size;
3875#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3876 req->dv_enhance_exist =
3877 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3878#else
3879 req->dv_enhance_exist = 0;
3880#endif
3881 }
3882 spin_unlock_irqrestore(&hw->lock, flags);
3883
3884 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3885 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3886 __func__, type, buf_spec_num, req->aux_size);
3887 }
3888
3889 return 0;
3890}
3891
3892static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3893 u32 index)
3894{
3895 struct canvas_config_s *p_canvas_config;
3896 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3897 force_rate_framebase : force_rate_streambase;
3898 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3899 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3900 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3901
3902 /* signal_type */
3903 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3904 vf->signal_type = hw->video_signal_from_vui;
3905 if (hw->is_used_v4l) {
3906 struct aml_vdec_hdr_infos hdr;
3907 struct aml_vcodec_ctx *ctx =
3908 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3909
3910 memset(&hdr, 0, sizeof(hdr));
3911 hdr.signal_type = hw->video_signal_from_vui;
3912 vdec_v4l_set_hdr_infos(ctx, &hdr);
3913 }
3914 } else
3915 vf->signal_type = 0;
3916
3917 vf->width = hw->frame_width;
3918 vf->height = hw->frame_height;
3919 if (force_rate) {
3920 if (force_rate == -1)
3921 vf->duration = 0;
3922 else
3923 vf->duration = 96000/force_rate;
3924 } else
3925 vf->duration = hw->frame_dur;
3926 vf->ratio_control =
3927 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3928 DISP_RATIO_ASPECT_RATIO_BIT;
3929 vf->orientation = hw->vh264_rotation;
3930
3931 if (hw->mmu_enable)
3932 return;
3933
3934 vf->canvas0Addr = vf->canvas1Addr = -1;
3935#ifdef NV21
3936 vf->plane_num = 2;
3937#else
3938 vf->plane_num = 3;
3939#endif
3940
3941 if (IS_VDEC_DW(hw)) {
3942 vf->width = (hw->frame_width /2);
3943 if (IS_VDEC_DW(hw) == 2)
3944 vf->height = (hw->frame_height /2);
3945 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3946 } else
3947 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3948
3949 vf->canvas0_config[0] = p_canvas_config[0];
3950 vf->canvas0_config[1] = p_canvas_config[1];
3951#ifndef NV21
3952 vf->canvas0_config[2] = p_canvas_config[2];
3953#endif
3954 vf->canvas1_config[0] = p_canvas_config[0];
3955 vf->canvas1_config[1] = p_canvas_config[1];
3956#ifndef NV21
3957 vf->canvas1_config[2] = p_canvas_config[2];
3958#endif
3959}
3960
3961static void get_picture_qos_info(struct StorablePicture *picture)
3962{
3963 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3964 unsigned char a[3];
3965 unsigned char i, j, t;
3966 unsigned long data;
3967
3968 get_random_bytes(&data, sizeof(unsigned long));
3969 if (picture->slice_type == I_SLICE)
3970 data = 0;
3971 a[0] = data & 0xff;
3972 a[1] = (data >> 8) & 0xff;
3973 a[2] = (data >> 16) & 0xff;
3974
3975 for (i = 0; i < 3; i++)
3976 for (j = i+1; j < 3; j++) {
3977 if (a[j] < a[i]) {
3978 t = a[j];
3979 a[j] = a[i];
3980 a[i] = t;
3981 } else if (a[j] == a[i]) {
3982 a[i]++;
3983 t = a[j];
3984 a[j] = a[i];
3985 a[i] = t;
3986 }
3987 }
3988 picture->max_mv = a[2];
3989 picture->avg_mv = a[1];
3990 picture->min_mv = a[0];
3991 /*
3992 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3993 data, a[0], a[1], a[2]);
3994 */
3995
3996 get_random_bytes(&data, sizeof(unsigned long));
3997 a[0] = data & 0x1f;
3998 a[1] = (data >> 8) & 0x3f;
3999 a[2] = (data >> 16) & 0x7f;
4000
4001 for (i = 0; i < 3; i++)
4002 for (j = i+1; j < 3; j++) {
4003 if (a[j] < a[i]) {
4004 t = a[j];
4005 a[j] = a[i];
4006 a[i] = t;
4007 } else if (a[j] == a[i]) {
4008 a[i]++;
4009 t = a[j];
4010 a[j] = a[i];
4011 a[i] = t;
4012 }
4013 }
4014 picture->max_qp = a[2];
4015 picture->avg_qp = a[1];
4016 picture->min_qp = a[0];
4017 /*
4018 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4019 data, a[0], a[1], a[2]);
4020 */
4021
4022 get_random_bytes(&data, sizeof(unsigned long));
4023 a[0] = data & 0x1f;
4024 a[1] = (data >> 8) & 0x3f;
4025 a[2] = (data >> 16) & 0x7f;
4026
4027 for (i = 0; i < 3; i++)
4028 for (j = i+1; j < 3; j++) {
4029 if (a[j] < a[i]) {
4030 t = a[j];
4031 a[j] = a[i];
4032 a[i] = t;
4033 } else if (a[j] == a[i]) {
4034 a[i]++;
4035 t = a[j];
4036 a[j] = a[i];
4037 a[i] = t;
4038 }
4039 }
4040 picture->max_skip = a[2];
4041 picture->avg_skip = a[1];
4042 picture->min_skip = a[0];
4043
4044
4045 /*
4046 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4047 data,a[0], a[1], a[2]);
4048 */
4049 } else {
4050 uint32_t blk88_y_count;
4051 uint32_t blk88_c_count;
4052 uint32_t blk22_mv_count;
4053 uint32_t rdata32;
4054 int32_t mv_hi;
4055 int32_t mv_lo;
4056 uint32_t rdata32_l;
4057 uint32_t mvx_L0_hi;
4058 uint32_t mvy_L0_hi;
4059 uint32_t mvx_L1_hi;
4060 uint32_t mvy_L1_hi;
4061 int64_t value;
4062 uint64_t temp_value;
4063/*
4064#define DEBUG_QOS
4065*/
4066#ifdef DEBUG_QOS
4067 int pic_number = picture->poc;
4068#endif
4069
4070 picture->max_mv = 0;
4071 picture->avg_mv = 0;
4072 picture->min_mv = 0;
4073
4074 picture->max_skip = 0;
4075 picture->avg_skip = 0;
4076 picture->min_skip = 0;
4077
4078 picture->max_qp = 0;
4079 picture->avg_qp = 0;
4080 picture->min_qp = 0;
4081
4082
4083
4084
4085
4086 /* set rd_idx to 0 */
4087 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4088 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4089 if (blk88_y_count == 0) {
4090#ifdef DEBUG_QOS
4091 pr_info(" [Picture %d Quality] NO Data yet.\n",
4092 pic_number);
4093#endif
4094 /* reset all counts */
4095 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4096 return;
4097 }
4098 /* qp_y_sum */
4099 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4100#ifdef DEBUG_QOS
4101 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4102 pic_number, rdata32/blk88_y_count,
4103 rdata32, blk88_y_count);
4104#endif
4105 picture->avg_qp = rdata32/blk88_y_count;
4106 /* intra_y_count */
4107 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4108#ifdef DEBUG_QOS
4109 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4110 pic_number, rdata32*100/blk88_y_count,
4111 '%', rdata32);
4112#endif
4113 /* skipped_y_count */
4114 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4115#ifdef DEBUG_QOS
4116 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4117 pic_number, rdata32*100/blk88_y_count,
4118 '%', rdata32);
4119#endif
4120 picture->avg_skip = rdata32*100/blk88_y_count;
4121 /* coeff_non_zero_y_count */
4122 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4123#ifdef DEBUG_QOS
4124 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4125 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4126 '%', rdata32);
4127#endif
4128 /* blk66_c_count */
4129 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4130 if (blk88_c_count == 0) {
4131#ifdef DEBUG_QOS
4132 pr_info(" [Picture %d Quality] NO Data yet.\n",
4133 pic_number);
4134#endif
4135 /* reset all counts */
4136 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4137 return;
4138 }
4139 /* qp_c_sum */
4140 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4141#ifdef DEBUG_QOS
4142 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4143 pic_number, rdata32/blk88_c_count,
4144 rdata32, blk88_c_count);
4145#endif
4146 /* intra_c_count */
4147 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4148#ifdef DEBUG_QOS
4149 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4150 pic_number, rdata32*100/blk88_c_count,
4151 '%', rdata32);
4152#endif
4153 /* skipped_cu_c_count */
4154 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4155#ifdef DEBUG_QOS
4156 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4157 pic_number, rdata32*100/blk88_c_count,
4158 '%', rdata32);
4159#endif
4160 /* coeff_non_zero_c_count */
4161 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4162#ifdef DEBUG_QOS
4163 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4164 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4165 '%', rdata32);
4166#endif
4167
4168 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4169 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4170 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4171#ifdef DEBUG_QOS
4172 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4173 pic_number, (rdata32>>0)&0xff);
4174#endif
4175 picture->min_qp = (rdata32>>0)&0xff;
4176
4177#ifdef DEBUG_QOS
4178 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4179 pic_number, (rdata32>>8)&0xff);
4180#endif
4181 picture->max_qp = (rdata32>>8)&0xff;
4182
4183#ifdef DEBUG_QOS
4184 pr_info(" [Picture %d Quality] C QP min : %d\n",
4185 pic_number, (rdata32>>16)&0xff);
4186 pr_info(" [Picture %d Quality] C QP max : %d\n",
4187 pic_number, (rdata32>>24)&0xff);
4188#endif
4189
4190 /* blk22_mv_count */
4191 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4192 if (blk22_mv_count == 0) {
4193#ifdef DEBUG_QOS
4194 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4195 pic_number);
4196#endif
4197 /* reset all counts */
4198 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4199 return;
4200 }
4201 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4202 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4203 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4204 /* should all be 0x00 or 0xff */
4205#ifdef DEBUG_QOS
4206 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4207 pic_number, rdata32);
4208#endif
4209 mvx_L0_hi = ((rdata32>>0)&0xff);
4210 mvy_L0_hi = ((rdata32>>8)&0xff);
4211 mvx_L1_hi = ((rdata32>>16)&0xff);
4212 mvy_L1_hi = ((rdata32>>24)&0xff);
4213
4214 /* mvx_L0_count[31:0] */
4215 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4216 temp_value = mvx_L0_hi;
4217 temp_value = (temp_value << 32) | rdata32_l;
4218
4219 if (mvx_L0_hi & 0x80)
4220 value = 0xFFFFFFF000000000 | temp_value;
4221 else
4222 value = temp_value;
4223 value = div_s64(value, blk22_mv_count);
4224#ifdef DEBUG_QOS
4225 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4226 pic_number, (int)(value),
4227 value, blk22_mv_count);
4228#endif
4229 picture->avg_mv = value;
4230
4231 /* mvy_L0_count[31:0] */
4232 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4233 temp_value = mvy_L0_hi;
4234 temp_value = (temp_value << 32) | rdata32_l;
4235
4236 if (mvy_L0_hi & 0x80)
4237 value = 0xFFFFFFF000000000 | temp_value;
4238 else
4239 value = temp_value;
4240#ifdef DEBUG_QOS
4241 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4242 pic_number, rdata32_l/blk22_mv_count,
4243 value, blk22_mv_count);
4244#endif
4245
4246 /* mvx_L1_count[31:0] */
4247 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4248 temp_value = mvx_L1_hi;
4249 temp_value = (temp_value << 32) | rdata32_l;
4250 if (mvx_L1_hi & 0x80)
4251 value = 0xFFFFFFF000000000 | temp_value;
4252 else
4253 value = temp_value;
4254#ifdef DEBUG_QOS
4255 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4256 pic_number, rdata32_l/blk22_mv_count,
4257 value, blk22_mv_count);
4258#endif
4259
4260 /* mvy_L1_count[31:0] */
4261 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4262 temp_value = mvy_L1_hi;
4263 temp_value = (temp_value << 32) | rdata32_l;
4264 if (mvy_L1_hi & 0x80)
4265 value = 0xFFFFFFF000000000 | temp_value;
4266 else
4267 value = temp_value;
4268#ifdef DEBUG_QOS
4269 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4270 pic_number, rdata32_l/blk22_mv_count,
4271 value, blk22_mv_count);
4272#endif
4273
4274 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4275 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4276 mv_hi = (rdata32>>16)&0xffff;
4277 if (mv_hi & 0x8000)
4278 mv_hi = 0x8000 - mv_hi;
4279#ifdef DEBUG_QOS
4280 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4281 pic_number, mv_hi);
4282#endif
4283 picture->max_mv = mv_hi;
4284
4285 mv_lo = (rdata32>>0)&0xffff;
4286 if (mv_lo & 0x8000)
4287 mv_lo = 0x8000 - mv_lo;
4288#ifdef DEBUG_QOS
4289 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4290 pic_number, mv_lo);
4291#endif
4292 picture->min_mv = mv_lo;
4293
4294 /* {mvy_L0_max, mvy_L0_min} */
4295 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4296 mv_hi = (rdata32>>16)&0xffff;
4297 if (mv_hi & 0x8000)
4298 mv_hi = 0x8000 - mv_hi;
4299#ifdef DEBUG_QOS
4300 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4301 pic_number, mv_hi);
4302#endif
4303
4304 mv_lo = (rdata32>>0)&0xffff;
4305 if (mv_lo & 0x8000)
4306 mv_lo = 0x8000 - mv_lo;
4307#ifdef DEBUG_QOS
4308 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4309 pic_number, mv_lo);
4310#endif
4311
4312 /* {mvx_L1_max, mvx_L1_min} */
4313 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4314 mv_hi = (rdata32>>16)&0xffff;
4315 if (mv_hi & 0x8000)
4316 mv_hi = 0x8000 - mv_hi;
4317#ifdef DEBUG_QOS
4318 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4319 pic_number, mv_hi);
4320#endif
4321
4322 mv_lo = (rdata32>>0)&0xffff;
4323 if (mv_lo & 0x8000)
4324 mv_lo = 0x8000 - mv_lo;
4325#ifdef DEBUG_QOS
4326 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4327 pic_number, mv_lo);
4328#endif
4329
4330 /* {mvy_L1_max, mvy_L1_min} */
4331 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4332 mv_hi = (rdata32>>16)&0xffff;
4333 if (mv_hi & 0x8000)
4334 mv_hi = 0x8000 - mv_hi;
4335#ifdef DEBUG_QOS
4336 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4337 pic_number, mv_hi);
4338#endif
4339 mv_lo = (rdata32>>0)&0xffff;
4340 if (mv_lo & 0x8000)
4341 mv_lo = 0x8000 - mv_lo;
4342#ifdef DEBUG_QOS
4343 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4344 pic_number, mv_lo);
4345#endif
4346
4347 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4348#ifdef DEBUG_QOS
4349 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4350 pic_number, rdata32);
4351#endif
4352 /* reset all counts */
4353 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4354 }
4355}
4356
4357static int get_max_dec_frame_buf_size(int level_idc,
4358 int max_reference_frame_num, int mb_width,
4359 int mb_height)
4360{
4361 int pic_size = mb_width * mb_height * 384;
4362
4363 int size = 0;
4364
4365 switch (level_idc) {
4366 case 9:
4367 size = 152064;
4368 break;
4369 case 10:
4370 size = 152064;
4371 break;
4372 case 11:
4373 size = 345600;
4374 break;
4375 case 12:
4376 size = 912384;
4377 break;
4378 case 13:
4379 size = 912384;
4380 break;
4381 case 20:
4382 size = 912384;
4383 break;
4384 case 21:
4385 size = 1824768;
4386 break;
4387 case 22:
4388 size = 3110400;
4389 break;
4390 case 30:
4391 size = 3110400;
4392 break;
4393 case 31:
4394 size = 6912000;
4395 break;
4396 case 32:
4397 size = 7864320;
4398 break;
4399 case 40:
4400 size = 12582912;
4401 break;
4402 case 41:
4403 size = 12582912;
4404 break;
4405 case 42:
4406 size = 13369344;
4407 break;
4408 case 50:
4409 size = 42393600;
4410 break;
4411 case 51:
4412 case 52:
4413 default:
4414 size = 70778880;
4415 break;
4416 }
4417
4418 size /= pic_size;
4419 size = size + 1; /* need one more buffer */
4420
4421 if (max_reference_frame_num > size)
4422 size = max_reference_frame_num;
4423 size = imin(size, 16);
4424
4425 return size;
4426}
4427
4428static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4429{
4430 int i, j;
4431
4432 if (hw->double_write_mode) {
4433 mutex_lock(&vmh264_mutex);
4434 if (hw->decode_pic_count == 0) {
4435 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4436 i = get_buf_spec_by_canvas_pos(hw, j);
4437 if (i >= 0)
4438 config_decode_canvas_ex(hw, i);
4439 }
4440 }
4441 mutex_unlock(&vmh264_mutex);
4442 }
4443}
4444
4445static int vh264_set_params(struct vdec_h264_hw_s *hw,
4446 u32 param1, u32 param2, u32 param3, u32 param4)
4447{
4448 int i, j;
4449 int mb_width, mb_total;
4450 int max_reference_size, level_idc;
4451 int mb_height = 0;
4452 unsigned long flags;
4453 /*int mb_mv_byte;*/
4454 struct vdec_s *vdec = hw_to_vdec(hw);
4455 u32 seq_info2;
4456 int ret = 0;
4457 int active_buffer_spec_num;
4458 unsigned int buf_size;
4459 unsigned int frame_mbs_only_flag;
4460 unsigned int chroma_format_idc, chroma444;
4461 unsigned int crop_infor, crop_bottom, crop_right;
4462 unsigned int used_reorder_dpb_size_margin
4463 = hw->reorder_dpb_size_margin;
4464 u8 *colocate_vaddr = NULL;
4465
4466#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4467 if (vdec->master || vdec->slave)
4468 used_reorder_dpb_size_margin =
4469 reorder_dpb_size_margin_dv;
4470#endif
4471 seq_info2 = param1;
4472 hw->seq_info = param2;
4473
4474 mb_width = seq_info2 & 0xff;
4475 mb_total = (seq_info2 >> 8) & 0xffff;
4476 if (!mb_width && mb_total) /*for 4k2k*/
4477 mb_width = 256;
4478 if (mb_width)
4479 mb_height = mb_total/mb_width;
4480 if (mb_width <= 0 || mb_height <= 0 ||
4481 is_oversize(mb_width << 4, mb_height << 4)) {
4482 dpb_print(DECODE_ID(hw), 0,
4483 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4484 seq_info2,
4485 mb_width,
4486 mb_height);
4487 return -1;
4488 }
4489
4490 if (seq_info2 != 0 &&
4491 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4492 hw->seq_info2 != 0
4493 ) /*picture size changed*/
4494 h264_reconfig(hw);
4495
4496 if (hw->config_bufmgr_done == 0) {
4497 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4498 u32 reg_val;
4499 hw->cfg_param1 = param1;
4500 hw->cfg_param2 = param2;
4501 hw->cfg_param3 = param3;
4502 hw->cfg_param4 = param4;
4503
4504 hw->seq_info2 = seq_info2 & (~0x80000000);
4505 dpb_print(DECODE_ID(hw), 0,
4506 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4507 seq_info2, hw->seq_info);
4508
4509 dpb_init_global(&hw->dpb,
4510 DECODE_ID(hw), 0, 0);
4511
4512 p_H264_Dpb->fast_output_enable = fast_output_enable;
4513 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4514
4515#if 1
4516 /*crop*/
4517 /* AV_SCRATCH_2
4518 bit 15: frame_mbs_only_flag
4519 bit 13-14: chroma_format_idc */
4520 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4521 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4522 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4523
4524 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4525 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4526 (2 - frame_mbs_only_flag) */
4527 crop_infor = param3;
4528 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4529 crop_right = ((crop_infor >> 16) & 0xff)
4530 >> (2 - frame_mbs_only_flag);
4531
4532 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4533 hw->frame_width = mb_width << 4;
4534 hw->frame_height = mb_height << 4;
4535 if (frame_mbs_only_flag) {
4536 hw->frame_height =
4537 hw->frame_height - (2 >> chroma444) *
4538 min(crop_bottom,
4539 (unsigned int)((8 << chroma444) - 1));
4540 hw->frame_width =
4541 hw->frame_width -
4542 (2 >> chroma444) * min(crop_right,
4543 (unsigned
4544 int)((8 << chroma444) - 1));
4545 } else {
4546 hw->frame_height =
4547 hw->frame_height - (4 >> chroma444) *
4548 min(crop_bottom,
4549 (unsigned int)((8 << chroma444)
4550 - 1));
4551 hw->frame_width =
4552 hw->frame_width -
4553 (4 >> chroma444) * min(crop_right,
4554 (unsigned int)((8 << chroma444) - 1));
4555 }
4556 dpb_print(DECODE_ID(hw), 0,
4557 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4558 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4559 dpb_print(DECODE_ID(hw), 0,
4560 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4561 mb_height, crop_right,
4562 hw->frame_width, mb_width);
4563
4564 if (hw->frame_height == 1088)
4565 hw->frame_height = 1080;
4566#endif
4567 if (!hw->mmu_enable) {
4568 mb_width = (mb_width+3) & 0xfffffffc;
4569 mb_height = (mb_height+3) & 0xfffffffc;
4570 }
4571 mb_total = mb_width * mb_height;
4572 hw->mb_width = mb_width;
4573 hw->mb_height = mb_height;
4574 hw->mb_total = mb_total;
4575 if (hw->mmu_enable)
4576 hevc_mcr_sao_global_hw_init(hw,
4577 (hw->mb_width << 4), (hw->mb_height << 4));
4578
4579 reg_val = param4;
4580 level_idc = reg_val & 0xff;
4581 max_reference_size = (reg_val >> 8) & 0xff;
4582 hw->dpb.origin_max_reference = max_reference_size;
4583 dpb_print(DECODE_ID(hw), 0,
4584 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4585 mb_height, mb_width, mb_total,
4586 level_idc, max_reference_size);
4587
4588
4589 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4590 hw->dpb.reorder_pic_num =
4591 get_max_dec_frame_buf_size(level_idc,
4592 max_reference_size, mb_width, mb_height);
4593
4594 dpb_print(DECODE_ID(hw), 0,
4595 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4596 hw->bitstream_restriction_flag,
4597 hw->max_dec_frame_buffering,
4598 hw->dpb.reorder_pic_num);
4599
4600 if ((hw->bitstream_restriction_flag) &&
4601 (hw->max_dec_frame_buffering <
4602 hw->dpb.reorder_pic_num)) {
4603 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4604 dpb_print(DECODE_ID(hw), 0,
4605 "set reorder_pic_num to %d\n",
4606 hw->dpb.reorder_pic_num);
4607 }
4608
4609 active_buffer_spec_num =
4610 hw->dpb.reorder_pic_num
4611 + used_reorder_dpb_size_margin;
4612 hw->max_reference_size =
4613 max_reference_size + reference_buf_margin;
4614
4615 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4616 active_buffer_spec_num = MAX_VF_BUF_NUM;
4617 hw->dpb.reorder_pic_num = active_buffer_spec_num
4618 - used_reorder_dpb_size_margin;
4619 }
4620 hw->dpb.mDPB.size = active_buffer_spec_num;
4621 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4622 hw->max_reference_size = MAX_VF_BUF_NUM;
4623 hw->dpb.max_reference_size = hw->max_reference_size;
4624
4625 if (hw->no_poc_reorder_flag)
4626 hw->dpb.reorder_pic_num = 1;
4627 dpb_print(DECODE_ID(hw), 0,
4628 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4629 __func__, active_buffer_spec_num,
4630 hw->dpb.reorder_pic_num,
4631 hw->max_reference_size);
4632
4633 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4634
4635 mutex_lock(&vmh264_mutex);
4636 if (!hw->mmu_enable) {
4637 config_buf_specs(vdec);
4638 i = get_buf_spec_by_canvas_pos(hw, 0);
4639
4640 if (hw->is_used_v4l) {
4641 if (i != -1) {
4642 pr_info("v4l: delay alloc the buffer.\n");
4643 }
4644 } else {
4645 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4646 config_decode_canvas(hw, i);
4647 else
4648 ret = -1;
4649 }
4650 } else {
4651 if (hw->double_write_mode) {
4652 config_buf_specs_ex(vdec);
4653 } else {
4654 spin_lock_irqsave(&hw->bufspec_lock, flags);
4655 for (i = 0, j = 0;
4656 j < active_buffer_spec_num
4657 && i < BUFSPEC_POOL_SIZE;
4658 i++) {
4659 if (hw->buffer_spec[i].used != -1)
4660 continue;
4661 hw->buffer_spec[i].used = 0;
4662 hw->buffer_spec[i].
4663 alloc_header_addr = 0;
4664 hw->buffer_spec[i].canvas_pos = j;
4665 j++;
4666 }
4667 spin_unlock_irqrestore(&hw->bufspec_lock,
4668 flags);
4669 }
4670 hevc_mcr_config_canv2axitbl(hw, 0);
4671 }
4672 mutex_unlock(&vmh264_mutex);
4673 if (dpb_is_debug(DECODE_ID(hw),
4674 PRINT_FLAG_DUMP_BUFSPEC))
4675 dump_bufspec(hw, __func__);
4676
4677#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4678 buf_size = PAGE_ALIGN(
4679 p_H264_Dpb->colocated_buf_size *
4680 active_buffer_spec_num);
4681#else
4682 buf_size = PAGE_ALIGN(
4683 p_H264_Dpb->colocated_buf_size *
4684 hw->max_reference_size);
4685#endif
4686
4687 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4688 buf_size, DRIVER_NAME,
4689 &hw->collocate_cma_alloc_addr) < 0)
4690 return -1;
4691 if (!vdec_secure(vdec)) {
4692 /* clear for some mosaic problem after reset bufmgr */
4693 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4694 if (colocate_vaddr != NULL) {
4695 memset(colocate_vaddr, 0, buf_size);
4696 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4697 codec_mm_unmap_phyaddr(colocate_vaddr);
4698 }
4699 }
4700
4701 hw->dpb.colocated_mv_addr_start =
4702 hw->collocate_cma_alloc_addr;
4703#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4704 hw->dpb.colocated_mv_addr_end =
4705 hw->dpb.colocated_mv_addr_start +
4706 (p_H264_Dpb->colocated_buf_size *
4707 active_buffer_spec_num);
4708#else
4709 hw->dpb.colocated_mv_addr_end =
4710 hw->dpb.colocated_mv_addr_start +
4711 (p_H264_Dpb->colocated_buf_size *
4712 hw->max_reference_size);
4713#endif
4714 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4715 "callocate cma, %lx, %x\n",
4716 hw->collocate_cma_alloc_addr,
4717 hw->dpb.colocated_mv_addr_start);
4718
4719 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4720 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4721 hw->dpb.colocated_mv_addr_start,
4722 hw->dpb.colocated_mv_addr_end);
4723 if (!hw->mmu_enable) {
4724 mutex_lock(&vmh264_mutex);
4725 if (ret >= 0 && hw->decode_pic_count == 0) {
4726 int buf_cnt;
4727 /* h264_reconfig: alloc later*/
4728 buf_cnt = hw->dpb.mDPB.size;
4729
4730 for (j = 1; j < buf_cnt; j++) {
4731 i = get_buf_spec_by_canvas_pos(hw, j);
4732
4733 if (hw->is_used_v4l) {
4734 pr_info("v4l: delay alloc the buffer.\n");
4735 break;
4736 } else if (alloc_one_buf_spec(hw, i) < 0)
4737 break;
4738
4739 config_decode_canvas(hw, i);
4740 }
4741 }
4742 mutex_unlock(&vmh264_mutex);
4743 } else {
4744 vh264_config_canvs_for_mmu(hw);
4745 }
4746
4747 hw->config_bufmgr_done = 1;
4748
4749 /*end of config_bufmgr_done */
4750 }
4751
4752 return ret;
4753}
4754
4755static void vui_config(struct vdec_h264_hw_s *hw)
4756{
4757 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4758 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4759 /*time*/
4760 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4761 hw->time_scale = p_H264_Dpb->time_scale;
4762 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4763
4764 hw->bitstream_restriction_flag =
4765 p_H264_Dpb->bitstream_restriction_flag;
4766 hw->num_reorder_frames =
4767 p_H264_Dpb->num_reorder_frames;
4768 hw->max_dec_frame_buffering =
4769 p_H264_Dpb->max_dec_frame_buffering;
4770
4771 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4772 "vui_config: pdb %d, %d, %d\n",
4773 p_H264_Dpb->bitstream_restriction_flag,
4774 p_H264_Dpb->num_reorder_frames,
4775 p_H264_Dpb->max_dec_frame_buffering);
4776
4777 hw->fixed_frame_rate_flag = 0;
4778 if (hw->timing_info_present_flag) {
4779 hw->fixed_frame_rate_flag =
4780 p_H264_Dpb->fixed_frame_rate_flag;
4781
4782 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4783 ((!hw->sync_outside) ||
4784 (!hw->frame_dur)))
4785 && hw->num_units_in_tick && hw->time_scale) {
4786 if (hw->use_idr_framerate ||
4787 hw->fixed_frame_rate_flag ||
4788 !hw->frame_dur ||
4789 !hw->duration_from_pts_done
4790 /*|| vh264_running*/) {
4791 u32 frame_dur_es =
4792 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4793 hw->time_scale);
4794 if (hw->frame_dur != frame_dur_es) {
4795 hw->h264_first_valid_pts_ready = false;
4796 hw->h264pts1 = 0;
4797 hw->h264pts2 = 0;
4798 hw->h264_pts_count = 0;
4799 hw->duration_from_pts_done = 0;
4800 fixed_frame_rate_mode =
4801 FIX_FRAME_RATE_OFF;
4802 hw->pts_duration = 0;
4803 hw->frame_dur = frame_dur_es;
4804 vdec_schedule_work(&hw->notify_work);
4805 dpb_print(DECODE_ID(hw),
4806 PRINT_FLAG_DEC_DETAIL,
4807 "frame_dur %d from timing_info\n",
4808 hw->frame_dur);
4809 }
4810
4811 /*hack to avoid use ES frame duration when
4812 *it's half of the rate from system info
4813 * sometimes the encoder is given a wrong
4814 * frame rate but the system side information
4815 * is more reliable
4816 *if ((frame_dur * 2) != frame_dur_es) {
4817 * frame_dur = frame_dur_es;
4818 *}
4819 */
4820 }
4821 }
4822 } else {
4823 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4824 "H.264: timing_info not present\n");
4825 }
4826
4827 /*aspect ratio*/
4828 aspect_ratio_info_present_flag =
4829 p_H264_Dpb->vui_status & 0x1;
4830 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4831
4832 if (aspect_ratio_info_present_flag) {
4833 if (aspect_ratio_idc == EXTEND_SAR) {
4834 hw->h264_ar = 0x3ff;
4835 hw->height_aspect_ratio =
4836 p_H264_Dpb->aspect_ratio_sar_height;
4837 hw->width_aspect_ratio =
4838 p_H264_Dpb->aspect_ratio_sar_width;
4839 } else {
4840 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4841 aspect_ratio_idc); */
4842
4843 switch (aspect_ratio_idc) {
4844 case 1:
4845 hw->h264_ar = 0x3ff;
4846 hw->height_aspect_ratio = 1;
4847 hw->width_aspect_ratio = 1;
4848 break;
4849 case 2:
4850 hw->h264_ar = 0x3ff;
4851 hw->height_aspect_ratio = 11;
4852 hw->width_aspect_ratio = 12;
4853 break;
4854 case 3:
4855 hw->h264_ar = 0x3ff;
4856 hw->height_aspect_ratio = 11;
4857 hw->width_aspect_ratio = 10;
4858 break;
4859 case 4:
4860 hw->h264_ar = 0x3ff;
4861 hw->height_aspect_ratio = 11;
4862 hw->width_aspect_ratio = 16;
4863 break;
4864 case 5:
4865 hw->h264_ar = 0x3ff;
4866 hw->height_aspect_ratio = 33;
4867 hw->width_aspect_ratio = 40;
4868 break;
4869 case 6:
4870 hw->h264_ar = 0x3ff;
4871 hw->height_aspect_ratio = 11;
4872 hw->width_aspect_ratio = 24;
4873 break;
4874 case 7:
4875 hw->h264_ar = 0x3ff;
4876 hw->height_aspect_ratio = 11;
4877 hw->width_aspect_ratio = 20;
4878 break;
4879 case 8:
4880 hw->h264_ar = 0x3ff;
4881 hw->height_aspect_ratio = 11;
4882 hw->width_aspect_ratio = 32;
4883 break;
4884 case 9:
4885 hw->h264_ar = 0x3ff;
4886 hw->height_aspect_ratio = 33;
4887 hw->width_aspect_ratio = 80;
4888 break;
4889 case 10:
4890 hw->h264_ar = 0x3ff;
4891 hw->height_aspect_ratio = 11;
4892 hw->width_aspect_ratio = 18;
4893 break;
4894 case 11:
4895 hw->h264_ar = 0x3ff;
4896 hw->height_aspect_ratio = 11;
4897 hw->width_aspect_ratio = 15;
4898 break;
4899 case 12:
4900 hw->h264_ar = 0x3ff;
4901 hw->height_aspect_ratio = 33;
4902 hw->width_aspect_ratio = 64;
4903 break;
4904 case 13:
4905 hw->h264_ar = 0x3ff;
4906 hw->height_aspect_ratio = 99;
4907 hw->width_aspect_ratio = 160;
4908 break;
4909 case 14:
4910 hw->h264_ar = 0x3ff;
4911 hw->height_aspect_ratio = 3;
4912 hw->width_aspect_ratio = 4;
4913 break;
4914 case 15:
4915 hw->h264_ar = 0x3ff;
4916 hw->height_aspect_ratio = 2;
4917 hw->width_aspect_ratio = 3;
4918 break;
4919 case 16:
4920 hw->h264_ar = 0x3ff;
4921 hw->height_aspect_ratio = 1;
4922 hw->width_aspect_ratio = 2;
4923 break;
4924 default:
4925 if (hw->vh264_ratio >> 16) {
4926 hw->h264_ar = (hw->frame_height *
4927 (hw->vh264_ratio & 0xffff) *
4928 0x100 +
4929 ((hw->vh264_ratio >> 16) *
4930 hw->frame_width / 2)) /
4931 ((hw->vh264_ratio >> 16) *
4932 hw->frame_width);
4933 hw->height_aspect_ratio = 1;
4934 hw->width_aspect_ratio = 1;
4935 } else {
4936 hw->h264_ar = 0x3ff;
4937 hw->height_aspect_ratio = 1;
4938 hw->width_aspect_ratio = 1;
4939 }
4940 break;
4941 }
4942 }
4943 } else {
4944 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4945 "v264dec: aspect_ratio not available from source\n");
4946 if (hw->vh264_ratio >> 16) {
4947 /* high 16 bit is width, low 16 bit is height */
4948 hw->h264_ar =
4949 ((hw->vh264_ratio & 0xffff) *
4950 hw->frame_height * 0x100 +
4951 (hw->vh264_ratio >> 16) *
4952 hw->frame_width / 2) /
4953 ((hw->vh264_ratio >> 16) *
4954 hw->frame_width);
4955 hw->height_aspect_ratio = 1;
4956 hw->width_aspect_ratio = 1;
4957 } else {
4958 hw->h264_ar = 0x3ff;
4959 hw->height_aspect_ratio = 1;
4960 hw->width_aspect_ratio = 1;
4961 }
4962 }
4963
4964 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4965 if (((hw->frame_dur == RATE_2397_FPS)
4966 && (dec_control
4967 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4968 || ((RATE_2997_FPS ==
4969 hw->frame_dur) &&
4970 (dec_control &
4971 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4972 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4973 "force fix frame rate\n");
4974 hw->fixed_frame_rate_flag = 0x40;
4975 }
4976 }
4977
4978 /*video_signal_from_vui: to do .. */
4979}
4980
4981static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4982{
4983 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4984
4985 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4986 if (error_proc_policy & 0x20) {
4987 if (!hw->is_used_v4l)
4988 hw->reset_bufmgr_flag = 1;
4989 }
4990}
4991
4992void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4993{
4994 struct vdec_h264_hw_s *hw =
4995 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4996
4997 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4998
4999 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5000 hw->reset_bufmgr_flag = 1;
5001}
5002
5003#ifdef CONSTRAIN_MAX_BUF_NUM
5004static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5005{
5006 int i;
5007 int count = 0;
5008 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5009 if (is_buf_spec_in_disp_q(hw, i) &&
5010 hw->buffer_spec[i].vf_ref > 0)
5011 count++;
5012 }
5013 return count;
5014}
5015
5016static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5017{
5018 int i;
5019 int count = 0;
5020 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5021 if (is_buf_spec_in_use(hw, i))
5022 count++;
5023 }
5024 return count;
5025}
5026#endif
5027
5028
5029static bool is_buffer_available(struct vdec_s *vdec)
5030{
5031 bool buffer_available = 1;
5032 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5033 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5034 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5035 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5036 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5037 ((p_H264_Dpb->mDPB.init_done) &&
5038 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5039 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5040 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5041 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5042 __func__,
5043 kfifo_len(&hw->newframe_q),
5044 have_free_buf_spec(vdec),
5045 p_H264_Dpb->mDPB.init_done,
5046 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5047 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5048 );
5049 buffer_available = 0;
5050 if (dpb_is_debug(DECODE_ID(hw),
5051 DEBUG_DISABLE_RUNREADY_RMBUF))
5052 return buffer_available;
5053
5054 if ((error_proc_policy & 0x4) &&
5055 (error_proc_policy & 0x8)) {
5056 if ((kfifo_len(&hw->display_q) <= 0) &&
5057 (p_H264_Dpb->mDPB.used_size ==
5058 p_H264_Dpb->mDPB.size) &&
5059 (p_Dpb->ref_frames_in_buffer >
5060 (imax(
5061 1, p_Dpb->num_ref_frames)
5062 - p_Dpb->ltref_frames_in_buffer +
5063 force_sliding_margin)))
5064 bufmgr_recover(hw);
5065 else
5066 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5067 } else if ((error_proc_policy & 0x4) &&
5068 (kfifo_len(&hw->display_q) <= 0) &&
5069 ((p_H264_Dpb->mDPB.used_size ==
5070 p_H264_Dpb->mDPB.size) ||
5071 (!have_free_buf_spec(vdec)))) {
5072 enum receviver_start_e state = RECEIVER_INACTIVE;
5073 if ((error_proc_policy & 0x10) &&
5074 vf_get_receiver(vdec->vf_provider_name)) {
5075 state =
5076 vf_notify_receiver(vdec->vf_provider_name,
5077 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5078 NULL);
5079 if ((state == RECEIVER_STATE_NULL)
5080 || (state == RECEIVER_STATE_NONE))
5081 state = RECEIVER_INACTIVE;
5082 }
5083 if (state == RECEIVER_INACTIVE)
5084 bufmgr_recover(hw);
5085 else
5086 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5087 } else if ((error_proc_policy & 0x8) &&
5088 (p_Dpb->ref_frames_in_buffer >
5089 (imax(
5090 1, p_Dpb->num_ref_frames)
5091 - p_Dpb->ltref_frames_in_buffer +
5092 force_sliding_margin)))
5093 bufmgr_recover(hw);
5094 else
5095 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5096
5097 if (hw->reset_bufmgr_flag == 1)
5098 buffer_available = 1;
5099 }
5100
5101 return buffer_available;
5102}
5103
5104#define AUX_TAG_SEI 0x2
5105
5106#define SEI_BUFFERING_PERIOD 0
5107#define SEI_PicTiming 1
5108#define SEI_USER_DATA 4
5109#define SEI_RECOVERY_POINT 6
5110
5111/*
5112 *************************************************************************
5113 * Function:Reads bits from the bitstream buffer
5114 * Input:
5115 byte buffer[]
5116 containing sei message data bits
5117 int totbitoffset
5118 bit offset from start of partition
5119 int bytecount
5120 total bytes in bitstream
5121 int numbits
5122 number of bits to read
5123 * Output:
5124 int *info
5125 * Return:
5126 -1: failed
5127 > 0: the count of bit read
5128 * Attention:
5129 *************************************************************************
5130 */
5131
5132static int get_bits(unsigned char buffer[],
5133 int totbitoffset,
5134 int *info,
5135 int bytecount,
5136 int numbits)
5137{
5138 register int inf;
5139 long byteoffset;
5140 int bitoffset;
5141
5142 int bitcounter = numbits;
5143
5144 byteoffset = totbitoffset / 8;
5145 bitoffset = 7 - (totbitoffset % 8);
5146
5147 inf = 0;
5148 while (numbits) {
5149 inf <<= 1;
5150 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5151 numbits--;
5152 bitoffset--;
5153 if (bitoffset < 0) {
5154 byteoffset++;
5155 bitoffset += 8;
5156 if (byteoffset > bytecount)
5157 return -1;
5158 }
5159 }
5160
5161 *info = inf;
5162
5163
5164 return bitcounter;
5165}
5166
5167static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5168 u8 *sei_data_buf,
5169 u8 *sei_data_buf_end)
5170{
5171 int payload_type;
5172 int payload_size;
5173 u8 *p_sei;
5174 int temp = 0;
5175 int bit_offset;
5176 int read_size;
5177 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5178
5179 p_sei = sei_data_buf;
5180 read_size = 0;
5181 payload_type = 0;
5182 do {
5183 if (p_sei >= sei_data_buf_end)
5184 return read_size;
5185
5186 payload_type += *p_sei;
5187 read_size++;
5188 } while (*p_sei++ == 255);
5189
5190
5191 payload_size = 0;
5192 do {
5193 if (p_sei >= sei_data_buf_end)
5194 return read_size;
5195
5196 payload_size += *p_sei;
5197 read_size++;
5198 } while (*p_sei++ == 255);
5199
5200
5201 if (p_sei + payload_size > sei_data_buf_end) {
5202 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5203 "%s: payload_type = %d, payload_size = %d is over\n",
5204 __func__, payload_type, payload_size);
5205 return read_size;
5206 }
5207 bit_offset = 0;
5208
5209 if (payload_size <= 0) {
5210 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5211 "%s warning: this is a null sei message for payload_type = %d\n",
5212 __func__, payload_type);
5213 return read_size;
5214 }
5215 switch (payload_type) {
5216 case SEI_BUFFERING_PERIOD:
5217 break;
5218 case SEI_PicTiming:
5219 if (p_H264_Dpb->vui_status & 0xc) {
5220 int cpb_removal_delay;
5221 int dpb_output_delay;
5222 u32 delay_len;
5223
5224 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5225 cpb_removal_delay
5226 = (delay_len & 0x1F) + 1;
5227 dpb_output_delay
5228 = ((delay_len >> 5) & 0x1F) + 1;
5229
5230 get_bits(p_sei, bit_offset,
5231 &temp, payload_size,
5232 dpb_output_delay+cpb_removal_delay);
5233 bit_offset += dpb_output_delay+cpb_removal_delay;
5234 }
5235 if (p_H264_Dpb->vui_status & 0x10) {
5236 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5237 bit_offset += 4;
5238 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5239 }
5240 break;
5241 case SEI_USER_DATA:
5242 if (enable_itu_t35) {
5243 int i;
5244 int j;
5245 int data_len;
5246 u8 *user_data_buf;
5247
5248 user_data_buf
5249 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5250 /* user data length should be align with 8 bytes,
5251 if not, then padding with zero*/
5252 for (i = 0; i < payload_size; i += 8) {
5253 for (j = 0; j < 8; j++) {
5254 int index;
5255
5256 index = i+7-j;
5257 if (index >= payload_size)
5258 user_data_buf[i+j] = 0;
5259 else
5260 user_data_buf[i+j]
5261 = p_sei[i+7-j];
5262 }
5263 }
5264
5265 data_len = payload_size;
5266 if (payload_size % 8)
5267 data_len = ((payload_size + 8) >> 3) << 3;
5268
5269 hw->sei_itu_data_len += data_len;
5270 /*
5271 dpb_print(DECODE_ID(hw), 0,
5272 "%s: user data, and len = %d:\n",
5273 __func__, hw->sei_itu_data_len);
5274 */
5275 }
5276 break;
5277 case SEI_RECOVERY_POINT:
5278 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5279 break;
5280 }
5281
5282 return read_size + payload_size;
5283}
5284
5285static void parse_sei_data(struct vdec_h264_hw_s *hw,
5286 u8 *sei_data_buf,
5287 int len)
5288{
5289 char *p_sei;
5290 char *p_sei_end;
5291 int parsed_size;
5292 int read_size;
5293
5294
5295 p_sei = sei_data_buf;
5296 p_sei_end = p_sei + len;
5297 parsed_size = 0;
5298 while (parsed_size < len) {
5299 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5300 p_sei += read_size;
5301 parsed_size += read_size;
5302 if (*p_sei == 0x80) {
5303 p_sei++;
5304 parsed_size++;
5305 }
5306 }
5307}
5308
5309static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5310{
5311 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5312 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5313 unsigned mby_mbx = READ_VREG(MBY_MBX);
5314 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5315 unsigned decode_mb_count =
5316 ((mby_mbx & 0xff) * hw->mb_width +
5317 (((mby_mbx >> 8) & 0xff) + 1));
5318 if (mby_mbx == 0)
5319 return;
5320 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5321 mb_total /= 2;
5322 if (error_proc_policy & 0x100) {
5323 if (decode_mb_count < mb_total)
5324 p->data_flag |= ERROR_FLAG;
5325 }
5326
5327 if ((error_proc_policy & 0x200) &&
5328 READ_VREG(ERROR_STATUS_REG) != 0) {
5329 p->data_flag |= ERROR_FLAG;
5330 }
5331
5332 if (p->data_flag & ERROR_FLAG) {
5333 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5334 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5335 __func__,
5336 hw->seq_info2,
5337 mby_mbx,
5338 mb_total,
5339 decode_mb_count,
5340 READ_VREG(ERROR_STATUS_REG)
5341 );
5342
5343 }
5344}
5345
5346static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5347{
5348 int i;
5349 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5350 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5351 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5352 u32 debug_tag;
5353 int ret;
5354
5355 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5356#if 1
5357 unsigned short *p = (unsigned short *)hw->lmem_addr;
5358 dma_sync_single_for_cpu(
5359 amports_get_dma_device(),
5360 hw->lmem_addr_remap,
5361 PAGE_SIZE,
5362 DMA_FROM_DEVICE);
5363 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5364 int ii;
5365 for (ii = 0; ii < 4; ii++) {
5366 p_H264_Dpb->dpb_param.l.data[i+ii] =
5367 p[i+3-ii];
5368 if (dpb_is_debug(DECODE_ID(hw),
5369 RRINT_FLAG_RPM)) {
5370 if (((i + ii) & 0xf) == 0)
5371 dpb_print(DECODE_ID(hw),
5372 0, "%04x:",
5373 i);
5374 dpb_print_cont(DECODE_ID(hw),
5375 0, "%04x ",
5376 p[i+3-ii]);
5377 if (((i + ii + 1) & 0xf) == 0)
5378 dpb_print_cont(
5379 DECODE_ID(hw),
5380 0, "\r\n");
5381 }
5382 }
5383 }
5384
5385 p_H264_Dpb->bitstream_restriction_flag =
5386 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5387 p_H264_Dpb->num_reorder_frames =
5388 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5389 p_H264_Dpb->max_dec_frame_buffering =
5390 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5391
5392 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5393 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5394 p_H264_Dpb->bitstream_restriction_flag,
5395 p_H264_Dpb->num_reorder_frames,
5396 p_H264_Dpb->max_dec_frame_buffering);
5397 hw->bitstream_restriction_flag =
5398 p_H264_Dpb->bitstream_restriction_flag;
5399 hw->num_reorder_frames =
5400 p_H264_Dpb->num_reorder_frames;
5401 hw->max_dec_frame_buffering =
5402 p_H264_Dpb->max_dec_frame_buffering;
5403#endif
5404
5405 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5406 reset_process_time(hw);
5407 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5408 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5409 vdec_schedule_work(&hw->work);
5410 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5411 u16 data_hight;
5412 u16 data_low;
5413 u32 video_signal;
5414
5415 int slice_header_process_status = 0;
5416 int I_flag;
5417 /*unsigned char is_idr;*/
5418 unsigned short *p = (unsigned short *)hw->lmem_addr;
5419 reset_process_time(hw);
5420
5421 if (hw->is_used_v4l) {
5422 struct aml_vcodec_ctx *ctx =
5423 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5424
5425 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5426 //amvdec_stop();
5427 hw->dec_result = DEC_RESULT_DONE;
5428 vdec_schedule_work(&hw->work);
5429 return IRQ_HANDLED;
5430 }
5431 }
5432
5433 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5434 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5435 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5436 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5437 if (input_frame_based(vdec) &&
5438 frmbase_cont_bitlevel2 != 0 &&
5439 READ_VREG(VIFF_BIT_CNT) <
5440 frmbase_cont_bitlevel2 &&
5441 hw->get_data_count >= 0x70000000) {
5442 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5443 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5444 __func__,
5445 READ_VREG(VIFF_BIT_CNT));
5446
5447 goto empty_proc;
5448 }
5449
5450 dma_sync_single_for_cpu(
5451 amports_get_dma_device(),
5452 hw->lmem_addr_remap,
5453 PAGE_SIZE,
5454 DMA_FROM_DEVICE);
5455#if 0
5456 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5457 if (!is_buffer_available(vdec)) {
5458 hw->buffer_empty_flag = 1;
5459 dpb_print(DECODE_ID(hw),
5460 PRINT_FLAG_UCODE_EVT,
5461 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5462 __func__,
5463 kfifo_len(&hw->newframe_q),
5464 have_free_buf_spec(vdec),
5465 p_H264_Dpb->mDPB.init_done,
5466 p_H264_Dpb->mDPB.used_size,
5467 p_H264_Dpb->mDPB.size,
5468 is_there_unused_frame_from_dpb(
5469 &p_H264_Dpb->mDPB));
5470 return IRQ_HANDLED;
5471 }
5472 }
5473
5474 hw->buffer_empty_flag = 0;
5475#endif
5476#ifdef SEND_PARAM_WITH_REG
5477 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5478 unsigned int data32;
5479
5480 do {
5481 data32 = READ_VREG(RPM_CMD_REG);
5482 /* printk("%x\n", data32); */
5483 } while ((data32&0x10000) == 0);
5484 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5485 WRITE_VREG(RPM_CMD_REG, 0);
5486 /* printk("%x:%x\n", i,data32); */
5487 }
5488#else
5489 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5490 int ii;
5491
5492 for (ii = 0; ii < 4; ii++) {
5493 p_H264_Dpb->dpb_param.l.data[i+ii] =
5494 p[i+3-ii];
5495 if (dpb_is_debug(DECODE_ID(hw),
5496 RRINT_FLAG_RPM)) {
5497 if (((i + ii) & 0xf) == 0)
5498 dpb_print(DECODE_ID(hw),
5499 0, "%04x:",
5500 i);
5501 dpb_print_cont(DECODE_ID(hw),
5502 0, "%04x ",
5503 p[i+3-ii]);
5504 if (((i + ii + 1) & 0xf) == 0)
5505 dpb_print_cont(
5506 DECODE_ID(hw),
5507 0, "\r\n");
5508 }
5509 }
5510 }
5511#endif
5512 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5513 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5514
5515 video_signal = (data_hight << 16) | data_low;
5516 hw->video_signal_from_vui =
5517 ((video_signal & 0xffff) << 8) |
5518 ((video_signal & 0xff0000) >> 16) |
5519 ((video_signal & 0x3f000000));
5520
5521
5522 /*dpb_print(DECODE_ID(hw),
5523 0,
5524 "video_signal_from_vui:0x%x, "
5525 "data_low:0x%x, data_hight:0x%x\n",
5526 hw->video_signal_from_vui,
5527 data_low,
5528 data_hight);*/
5529
5530 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5531
5532 if (hw->config_bufmgr_done == 0) {
5533 hw->dec_result = DEC_RESULT_DONE;
5534 vdec_schedule_work(&hw->work);
5535 dpb_print(DECODE_ID(hw),
5536 PRINT_FLAG_UCODE_EVT,
5537 "config_bufmgr not done, discard frame\n");
5538 return IRQ_HANDLED;
5539 } else if ((hw->first_i_policy & 0x3) != 0) {
5540 unsigned char is_i_slice =
5541 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5542 == I_Slice)
5543 ? 1 : 0;
5544 unsigned char is_idr =
5545 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5546 == 5);
5547 if ((hw->first_i_policy & 0x3) == 0x3)
5548 is_i_slice = is_idr;
5549 if (!is_i_slice) {
5550 if (hw->has_i_frame == 0) {
5551 amvdec_stop();
5552 vdec->mc_loaded = 0;
5553 hw->dec_result = DEC_RESULT_DONE;
5554 vdec_schedule_work(&hw->work);
5555 dpb_print(DECODE_ID(hw),
5556 PRINT_FLAG_UCODE_EVT,
5557 "has_i_frame is 0, discard none I(DR) frame\n");
5558 return IRQ_HANDLED;
5559 }
5560 } else {
5561 if (hw->skip_frame_count < 0 || is_idr) {
5562 /* second I */
5563 hw->dec_flag &= (~NODISP_FLAG);
5564 hw->skip_frame_count = 0;
5565 }
5566 if (hw->has_i_frame == 0 &&
5567 (!is_idr)) {
5568 int skip_count =
5569 (hw->first_i_policy >> 8) & 0xff;
5570 /* first I (not IDR) */
5571 if ((hw->first_i_policy & 0x3) == 2)
5572 hw->skip_frame_count =
5573 -1 - skip_count;
5574 else
5575 hw->skip_frame_count =
5576 skip_count;
5577 if (hw->skip_frame_count != 0)
5578 hw->dec_flag |= NODISP_FLAG;
5579 }
5580 }
5581 }
5582 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5583 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5584 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5585 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5586 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5587 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5588 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5589 ? I_FLAG : 0;
5590
5591 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5592 flush_dpb(p_H264_Dpb);
5593
5594 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5595 (p_H264_Dpb->mSlice.structure == FRAME)) {
5596 hw->data_flag = NULL_FLAG;
5597 goto pic_done_proc;
5598 }
5599
5600 slice_header_process_status =
5601 h264_slice_header_process(p_H264_Dpb);
5602 if (hw->mmu_enable)
5603 hevc_sao_set_slice_type(hw,
5604 slice_header_process_status,
5605 hw->dpb.mSlice.idr_flag);
5606 vui_config(hw);
5607
5608 if (p_H264_Dpb->mVideo.dec_picture) {
5609 int cfg_ret = 0;
5610 bool field_pic_flag = false;
5611
5612 if (slice_header_process_status == 1) {
5613 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5614 field_pic_flag =
5615 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5616 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5617 true : false;
5618 }
5619
5620 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5621 (((unsigned long)(hw->vh264_amstream_dec_info
5622 .param)) & 0x8))) {
5623 p_H264_Dpb->fast_output_enable =
5624 H264_OUTPUT_MODE_FAST;
5625 }
5626 else
5627 p_H264_Dpb->fast_output_enable
5628 = fast_output_enable;
5629 hw->data_flag = I_flag;
5630 if ((p_H264_Dpb->
5631 dpb_param.dpb.NAL_info_mmco & 0x1f)
5632 == 5)
5633 hw->data_flag |= IDR_FLAG;
5634 dpb_print(DECODE_ID(hw),
5635 PRINT_FLAG_VDEC_STATUS,
5636 "==================> frame count %d to skip %d\n",
5637 hw->decode_pic_count+1,
5638 hw->skip_frame_count);
5639 } else if (error_proc_policy & 0x100){
5640 struct StorablePicture *p =
5641 p_H264_Dpb->mVideo.dec_picture;
5642 unsigned mby_mbx = READ_VREG(MBY_MBX);
5643 unsigned decode_mb_count =
5644 ((mby_mbx & 0xff) * hw->mb_width +
5645 (((mby_mbx >> 8) & 0xff) + 1));
5646 if (decode_mb_count <
5647 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5648 (1 + p->mb_aff_frame_flag))) {
5649 dpb_print(DECODE_ID(hw),
5650 PRINT_FLAG_VDEC_STATUS,
5651 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5652 p_H264_Dpb->dpb_param.l.
5653 data[FIRST_MB_IN_SLICE],
5654 READ_VREG(MBY_MBX),
5655 decode_mb_count);
5656 p->data_flag |= ERROR_FLAG;
5657 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5658 p->data_flag |= ERROR_FLAG;
5659 goto pic_done_proc;
5660 }
5661 }
5662
5663 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5664 hw->new_iframe_flag = 1;
5665 }
5666 if (hw->new_iframe_flag) {
5667 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5668 hw->new_iframe_flag = 0;
5669 hw->ref_err_flush_dpb_flag = 1;
5670 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5671 hw->new_iframe_flag = 0;
5672 hw->ref_err_flush_dpb_flag = 0;
5673 }
5674 }
5675
5676 if (error_proc_policy & 0x400) {
5677 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5678 if (ret != 0) {
5679 hw->reflist_error_count ++;
5680 dpb_print(DECODE_ID(hw), 0,
5681 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5682 ret,
5683 hw->decode_pic_count+1,
5684 hw->skip_frame_count,
5685 hw->reflist_error_count);
5686
5687 if (hw->ref_err_flush_dpb_flag) {
5688 flush_dpb(p_H264_Dpb);
5689 p_H264_Dpb->colocated_buf_map = 0;
5690 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5691 p_H264_Dpb->colocated_buf_map |= 1 <<
5692 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5693 }
5694 }
5695
5696 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5697 if (((error_proc_policy & 0x80)
5698 && ((hw->dec_flag &
5699 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5700 hw->reset_bufmgr_flag = 1;
5701 hw->reflist_error_count =0;
5702 amvdec_stop();
5703 vdec->mc_loaded = 0;
5704 hw->dec_result = DEC_RESULT_DONE;
5705 vdec_schedule_work(&hw->work);
5706 return IRQ_HANDLED;
5707 }
5708 } else
5709 hw->reflist_error_count = 0;
5710 }
5711 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5712 && p_H264_Dpb->dpb_error_flag != 0) {
5713 dpb_print(DECODE_ID(hw), 0,
5714 "dpb error %d\n",
5715 p_H264_Dpb->dpb_error_flag);
5716 hw->data_flag |= ERROR_FLAG;
5717 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5718 if ((error_proc_policy & 0x80) &&
5719 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5720 hw->reset_bufmgr_flag = 1;
5721 amvdec_stop();
5722 vdec->mc_loaded = 0;
5723 hw->dec_result = DEC_RESULT_DONE;
5724 vdec_schedule_work(&hw->work);
5725 return IRQ_HANDLED;
5726 }
5727 }
5728
5729 cfg_ret = config_decode_buf(hw,
5730 p_H264_Dpb->mVideo.dec_picture);
5731 if (cfg_ret < 0) {
5732 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5733 "config_decode_buf fail (%d)\n",
5734 cfg_ret);
5735 if (error_proc_policy & 0x2) {
5736 release_cur_decoding_buf(hw);
5737 /*hw->data_flag |= ERROR_FLAG;*/
5738 hw->reset_bufmgr_flag = 1;
5739 hw->dec_result = DEC_RESULT_DONE;
5740 vdec_schedule_work(&hw->work);
5741 return IRQ_HANDLED;
5742 } else
5743 hw->data_flag |= ERROR_FLAG;
5744 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5745 }
5746 }
5747
5748 if (slice_header_process_status == 1)
5749 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5750 else
5751 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5752 hw->last_mby_mbx = 0;
5753 hw->last_vld_level = 0;
5754 start_process_time(hw);
5755 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5756 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5757pic_done_proc:
5758 reset_process_time(hw);
5759
5760 if (input_frame_based(vdec) &&
5761 (!(hw->i_only & 0x2)) &&
5762 frmbase_cont_bitlevel != 0 &&
5763 READ_VREG(VIFF_BIT_CNT) >
5764 frmbase_cont_bitlevel) {
5765 /*handle the case: multi pictures in one packet*/
5766 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5767 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5768 __func__,
5769 hw->decode_pic_count,
5770 READ_VREG(VIFF_BIT_CNT));
5771 hw->frmbase_cont_flag = 1;
5772 } else
5773 hw->frmbase_cont_flag = 0;
5774
5775 if (p_H264_Dpb->mVideo.dec_picture) {
5776 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5777#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5778 DEL_EXIST(hw,
5779 p_H264_Dpb->mVideo.dec_picture) = 0;
5780 if (vdec->master) {
5781 struct vdec_h264_hw_s *hw_ba =
5782 (struct vdec_h264_hw_s *)
5783 vdec->master->private;
5784 if (hw_ba->last_dec_picture)
5785 DEL_EXIST(hw_ba,
5786 hw_ba->last_dec_picture)
5787 = 1;
5788 }
5789#endif
5790 mutex_lock(&hw->chunks_mutex);
5791 if (hw->chunk) {
5792 p_H264_Dpb->mVideo.dec_picture->pts =
5793 hw->chunk->pts;
5794 p_H264_Dpb->mVideo.dec_picture->pts64 =
5795 hw->chunk->pts64;
5796 p_H264_Dpb->mVideo.dec_picture->timestamp =
5797 hw->chunk->timestamp;
5798#ifdef MH264_USERDATA_ENABLE
5799 vmh264_udc_fill_vpts(hw,
5800 p_H264_Dpb->mSlice.slice_type,
5801 hw->chunk->pts, 1);
5802#endif
5803
5804#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5805 } else if (vdec->master) {
5806 /*dv enhance layer,
5807 do not checkout pts*/
5808 struct StorablePicture *pic =
5809 p_H264_Dpb->mVideo.dec_picture;
5810 pic->pts = 0;
5811 pic->pts64 = 0;
5812#endif
5813 } else {
5814 struct StorablePicture *pic =
5815 p_H264_Dpb->mVideo.dec_picture;
5816 u32 offset = pic->offset_delimiter;
5817 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5818 offset, &pic->pts, 0, &pic->pts64)) {
5819 pic->pts = 0;
5820 pic->pts64 = 0;
5821#ifdef MH264_USERDATA_ENABLE
5822 vmh264_udc_fill_vpts(hw,
5823 p_H264_Dpb->mSlice.slice_type,
5824 pic->pts, 0);
5825#endif
5826 } else {
5827#ifdef MH264_USERDATA_ENABLE
5828 vmh264_udc_fill_vpts(hw,
5829 p_H264_Dpb->mSlice.slice_type,
5830 pic->pts, 1);
5831#endif
5832 }
5833
5834 }
5835 mutex_unlock(&hw->chunks_mutex);
5836
5837 check_decoded_pic_error(hw);
5838#ifdef ERROR_HANDLE_TEST
5839 if ((hw->data_flag & ERROR_FLAG)
5840 && (error_proc_policy & 0x80)) {
5841 release_cur_decoding_buf(hw);
5842 h264_clear_dpb(hw);
5843 hw->dec_flag = 0;
5844 hw->data_flag = 0;
5845 hw->skip_frame_count = 0;
5846 hw->has_i_frame = 0;
5847 hw->no_error_count = 0xfff;
5848 hw->no_error_i_count = 0xf;
5849 } else
5850#endif
5851 ret = store_picture_in_dpb(p_H264_Dpb,
5852 p_H264_Dpb->mVideo.dec_picture,
5853 hw->data_flag | hw->dec_flag |
5854 p_H264_Dpb->mVideo.dec_picture->data_flag);
5855
5856
5857
5858 if (ret == -1) {
5859 release_cur_decoding_buf(hw);
5860 bufmgr_force_recover(p_H264_Dpb);
5861 } else {
5862 if (hw->data_flag & ERROR_FLAG) {
5863 hw->no_error_count = 0;
5864 hw->no_error_i_count = 0;
5865 } else {
5866 hw->no_error_count++;
5867 if (hw->data_flag & I_FLAG)
5868 hw->no_error_i_count++;
5869 }
5870 if (hw->mmu_enable)
5871 hevc_set_unused_4k_buff_idx(hw,
5872 p_H264_Dpb->mVideo.
5873 dec_picture->buf_spec_num);
5874 bufmgr_post(p_H264_Dpb);
5875 hw->last_dec_picture =
5876 p_H264_Dpb->mVideo.dec_picture;
5877 p_H264_Dpb->mVideo.dec_picture = NULL;
5878 /* dump_dpb(&p_H264_Dpb->mDPB); */
5879 hw->has_i_frame = 1;
5880 if (hw->mmu_enable)
5881 hevc_set_frame_done(hw);
5882 hw->decode_pic_count++;
5883 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5884 if (hw->skip_frame_count > 0) {
5885 /*skip n frame after first I */
5886 hw->skip_frame_count--;
5887 if (hw->skip_frame_count == 0)
5888 hw->dec_flag &= (~NODISP_FLAG);
5889 } else if (hw->skip_frame_count < -1) {
5890 /*skip n frame after first I until second I */
5891 hw->skip_frame_count++;
5892 if (hw->skip_frame_count == -1)
5893 hw->dec_flag &= (~NODISP_FLAG);
5894 }
5895 }
5896 }
5897 if (hw->frmbase_cont_flag) {
5898 /*do not DEC_RESULT_GET_DATA*/
5899 hw->get_data_count = 0x7fffffff;
5900 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5901 decode_frame_count[DECODE_ID(hw)]++;
5902 start_process_time(hw);
5903 return IRQ_HANDLED;
5904 }
5905 amvdec_stop();
5906 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5907 "%s %s decode slice count %d\n",
5908 __func__,
5909 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5910 "H264_PIC_DATA_DONE" :
5911 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5912 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5913 hw->decode_pic_count);
5914 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5915 hw->dec_result = DEC_RESULT_DONE;
5916#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5917 if (vdec->slave &&
5918 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5919 struct vdec_h264_hw_s *hw_el =
5920 (struct vdec_h264_hw_s *)(vdec->slave->private);
5921 hw_el->got_valid_nal = 0;
5922 hw->switch_dvlayer_flag = 1;
5923 } else if (vdec->master &&
5924 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5925 struct vdec_h264_hw_s *hw_bl =
5926 (struct vdec_h264_hw_s *)(vdec->master->private);
5927 hw_bl->got_valid_nal = 0;
5928 hw->switch_dvlayer_flag = 1;
5929 } else {
5930 hw->switch_dvlayer_flag = 0;
5931 hw->got_valid_nal = 1;
5932 }
5933#endif
5934
5935 hw->dec_result = DEC_RESULT_DONE;
5936 vdec_schedule_work(&hw->work);
5937
5938#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5939 } else if (
5940 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5941 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5942 goto pic_done_proc;
5943#endif
5944 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5945 reset_process_time(hw);
5946 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5947 dma_sync_single_for_cpu(
5948 amports_get_dma_device(),
5949 hw->aux_phy_addr,
5950 hw->prefix_aux_size + hw->suffix_aux_size,
5951 DMA_FROM_DEVICE);
5952 if (dpb_is_debug(DECODE_ID(hw),
5953 PRINT_FLAG_DPB_DETAIL))
5954 dump_aux_buf(hw);
5955#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5956 if (vdec->dolby_meta_with_el || vdec->slave) {
5957 if (hw->last_dec_picture)
5958 set_aux_data(hw, hw->last_dec_picture,
5959 0, 0, NULL);
5960 } else {
5961 if (vdec->master) {
5962 struct vdec_h264_hw_s *hw_bl =
5963 (struct vdec_h264_hw_s *)
5964 (vdec->master->private);
5965 if (hw_bl->last_dec_picture != NULL) {
5966 set_aux_data(hw_bl,
5967 hw_bl->last_dec_picture,
5968 0, 1, hw);
5969 }
5970 set_aux_data(hw,
5971 hw->last_dec_picture,
5972 0, 2, NULL);
5973 }
5974 }
5975#else
5976 if (hw->last_dec_picture)
5977 set_aux_data(hw,
5978 hw->last_dec_picture, 0, 0, NULL);
5979#endif
5980 }
5981#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5982 hw->switch_dvlayer_flag = 0;
5983 hw->got_valid_nal = 1;
5984#endif
5985 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5986 "%s H264_AUX_DATA_READY\n", __func__);
5987 hw->dec_result = DEC_RESULT_DONE;
5988 vdec_schedule_work(&hw->work);
5989 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5990 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5991 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5992 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5993empty_proc:
5994 reset_process_time(hw);
5995 if (!hw->frmbase_cont_flag)
5996 release_cur_decoding_buf(hw);
5997
5998 if (input_frame_based(vdec) ||
5999 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6000 if (h264_debug_flag &
6001 DISABLE_ERROR_HANDLE) {
6002 dpb_print(DECODE_ID(hw),
6003 PRINT_FLAG_ERROR,
6004 "%s decoding error, level 0x%x\n",
6005 __func__,
6006 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6007 goto send_again;
6008 }
6009 amvdec_stop();
6010 vdec->mc_loaded = 0;
6011 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6012 "%s %s\n", __func__,
6013 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6014 "H264_SEARCH_BUFEMPTY" :
6015 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6016 "H264_DECODE_BUFEMPTY" :
6017 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6018 "H264_DECODE_TIMEOUT" :
6019 "OTHER");
6020 hw->dec_result = DEC_RESULT_DONE;
6021
6022 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6023 hw->search_dataempty_num++;
6024 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6025 hw->decode_timeout_num++;
6026 if (error_proc_policy & 0x4000) {
6027 hw->data_flag |= ERROR_FLAG;
6028 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6029 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6030 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6031 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6032 dpb_print(DECODE_ID(hw),
6033 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6034 p_H264_Dpb->last_dpb_status, __func__);
6035 hw->reset_bufmgr_flag = 1;
6036 }
6037 }
6038 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6039 hw->decode_dataempty_num++;
6040 if (!hw->frmbase_cont_flag)
6041 hw->data_flag |= ERROR_FLAG;
6042
6043 vdec_schedule_work(&hw->work);
6044 } else {
6045 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6046 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6047 "%s DEC_RESULT_AGAIN\n", __func__);
6048send_again:
6049 hw->dec_result = DEC_RESULT_AGAIN;
6050 vdec_schedule_work(&hw->work);
6051 }
6052 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6053 reset_process_time(hw);
6054 if (input_frame_based(vdec)) {
6055 dpb_print(DECODE_ID(hw),
6056 PRINT_FLAG_VDEC_STATUS,
6057 "%s H264_DATA_REQUEST (%d)\n",
6058 __func__, hw->get_data_count);
6059 hw->dec_result = DEC_RESULT_GET_DATA;
6060 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6061 hw->get_data_start_time = jiffies;
6062 hw->get_data_count++;
6063 if (hw->get_data_count >= frame_max_data_packet)
6064 goto empty_proc;
6065 vdec_schedule_work(&hw->work);
6066 } else
6067 goto empty_proc;
6068 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6069 dpb_print(DECODE_ID(hw), 0,
6070 "vmh264 decode oversize !!\n");
6071 release_cur_decoding_buf(hw);
6072 hw->data_flag |= ERROR_FLAG;
6073 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6074 reset_process_time(hw);
6075 hw->dec_result = DEC_RESULT_DONE;
6076 vdec_schedule_work(&hw->work);
6077 return IRQ_HANDLED;
6078 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6079 int aux_data_len;
6080 aux_data_len =
6081 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6082
6083 if (aux_data_len > SEI_DATA_SIZE) {
6084 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6085 "sei data size more than 4K: %d, discarded it\n",
6086 hw->sei_itu_data_len);
6087 hw->sei_itu_data_len = 0;
6088 }
6089
6090 if (aux_data_len != 0) {
6091 u8 *trans_data_buf;
6092 u8 *sei_data_buf;
6093 u8 swap_byte;
6094
6095 dma_sync_single_for_cpu(
6096 amports_get_dma_device(),
6097 hw->aux_phy_addr,
6098 hw->prefix_aux_size + hw->suffix_aux_size,
6099 DMA_FROM_DEVICE);
6100#if 0
6101 dump_aux_buf(hw);
6102#endif
6103 trans_data_buf = (u8 *)hw->aux_addr;
6104
6105 if (trans_data_buf[7] == AUX_TAG_SEI) {
6106 int left_len;
6107
6108 sei_data_buf = (u8 *)hw->sei_data_buf
6109 + hw->sei_data_len;
6110 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6111 if (aux_data_len/2 <= left_len) {
6112 for (i = 0; i < aux_data_len/2; i++)
6113 sei_data_buf[i]
6114 = trans_data_buf[i*2];
6115
6116 aux_data_len = aux_data_len / 2;
6117 for (i = 0; i < aux_data_len; i = i+4) {
6118 swap_byte = sei_data_buf[i];
6119 sei_data_buf[i]
6120 = sei_data_buf[i+3];
6121 sei_data_buf[i+3] = swap_byte;
6122
6123 swap_byte = sei_data_buf[i+1];
6124 sei_data_buf[i+1]
6125 = sei_data_buf[i+2];
6126 sei_data_buf[i+2] = swap_byte;
6127 }
6128
6129 for (i = aux_data_len-1; i >= 0; i--)
6130 if (sei_data_buf[i] != 0)
6131 break;
6132
6133 hw->sei_data_len += i+1;
6134 } else
6135 dpb_print(DECODE_ID(hw),
6136 PRINT_FLAG_ERROR,
6137 "sei data size %d and more than left space: %d, discarded it\n",
6138 hw->sei_itu_data_len,
6139 left_len);
6140 }
6141 }
6142 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6143
6144 return IRQ_HANDLED;
6145 }
6146
6147
6148 /* ucode debug */
6149 debug_tag = READ_VREG(DEBUG_REG1);
6150 if (debug_tag & 0x10000) {
6151 unsigned short *p = (unsigned short *)hw->lmem_addr;
6152
6153 dma_sync_single_for_cpu(
6154 amports_get_dma_device(),
6155 hw->lmem_addr_remap,
6156 PAGE_SIZE,
6157 DMA_FROM_DEVICE);
6158
6159 dpb_print(DECODE_ID(hw), 0,
6160 "LMEM<tag %x>:\n", debug_tag);
6161 for (i = 0; i < 0x400; i += 4) {
6162 int ii;
6163 if ((i & 0xf) == 0)
6164 dpb_print_cont(DECODE_ID(hw), 0,
6165 "%03x: ", i);
6166 for (ii = 0; ii < 4; ii++)
6167 dpb_print_cont(DECODE_ID(hw), 0,
6168 "%04x ", p[i+3-ii]);
6169 if (((i+ii) & 0xf) == 0)
6170 dpb_print_cont(DECODE_ID(hw), 0,
6171 "\n");
6172 }
6173 if (((udebug_pause_pos & 0xffff)
6174 == (debug_tag & 0xffff)) &&
6175 (udebug_pause_decode_idx == 0 ||
6176 udebug_pause_decode_idx ==
6177 hw->decode_pic_count) &&
6178 (udebug_pause_val == 0 ||
6179 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6180 udebug_pause_pos &= 0xffff;
6181 hw->ucode_pause_pos = udebug_pause_pos;
6182 }
6183 else if (debug_tag & 0x20000)
6184 hw->ucode_pause_pos = 0xffffffff;
6185 if (hw->ucode_pause_pos)
6186 reset_process_time(hw);
6187 else
6188 WRITE_VREG(DEBUG_REG1, 0);
6189 } else if (debug_tag != 0) {
6190 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6191 "dbg%x: %x\n", debug_tag,
6192 READ_VREG(DEBUG_REG2));
6193 if (((udebug_pause_pos & 0xffff)
6194 == (debug_tag & 0xffff)) &&
6195 (udebug_pause_decode_idx == 0 ||
6196 udebug_pause_decode_idx ==
6197 hw->decode_pic_count) &&
6198 (udebug_pause_val == 0 ||
6199 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6200 udebug_pause_pos &= 0xffff;
6201 hw->ucode_pause_pos = udebug_pause_pos;
6202 }
6203 if (hw->ucode_pause_pos)
6204 reset_process_time(hw);
6205 else
6206 WRITE_VREG(DEBUG_REG1, 0);
6207 }
6208 /**/
6209 return IRQ_HANDLED;
6210}
6211
6212static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6213{
6214 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6215 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6216
6217
6218 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6219
6220 if (!hw)
6221 return IRQ_HANDLED;
6222
6223 if (hw->eos)
6224 return IRQ_HANDLED;
6225
6226 p_H264_Dpb->vdec = vdec;
6227 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6228
6229 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6230 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6231 __func__,
6232 p_H264_Dpb->dec_dpb_status,
6233 READ_VREG(ERROR_STATUS_REG),
6234 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6235 READ_VREG(VLD_MEM_VIFIFO_WP),
6236 READ_VREG(VLD_MEM_VIFIFO_RP),
6237 READ_VREG(VIFF_BIT_CNT),
6238 READ_VREG(MBY_MBX));
6239
6240 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6241 if (hw->mmu_enable)
6242 hevc_sao_wait_done(hw);
6243 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6244 return IRQ_HANDLED;
6245 }
6246 return IRQ_WAKE_THREAD;
6247
6248}
6249
6250static void timeout_process(struct vdec_h264_hw_s *hw)
6251{
6252 struct vdec_s *vdec = hw_to_vdec(hw);
6253 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6254
6255 /*
6256 * In this very timeout point,the vh264_work arrives,
6257 * let it to handle the scenario.
6258 */
6259 if (work_pending(&hw->work))
6260 return;
6261
6262 hw->timeout_num++;
6263 amvdec_stop();
6264 vdec->mc_loaded = 0;
6265 if (hw->mmu_enable) {
6266 hevc_set_frame_done(hw);
6267 hevc_sao_wait_done(hw);
6268 }
6269 if (!hw->i_only && (error_proc_policy & 0x2))
6270 flush_dpb(p_H264_Dpb);
6271 dpb_print(DECODE_ID(hw),
6272 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6273 release_cur_decoding_buf(hw);
6274 hw->dec_result = DEC_RESULT_DONE;
6275 hw->data_flag |= ERROR_FLAG;
6276
6277 if (work_pending(&hw->work))
6278 return;
6279 vdec_schedule_work(&hw->timeout_work);
6280}
6281
6282static void dump_bufspec(struct vdec_h264_hw_s *hw,
6283 const char *caller)
6284{
6285 int i;
6286 dpb_print(DECODE_ID(hw), 0,
6287 "%s in %s:\n", __func__, caller);
6288 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6289 if (hw->buffer_spec[i].used == -1)
6290 continue;
6291 dpb_print(DECODE_ID(hw), 0,
6292 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6293 i, hw->buffer_spec[i].used,
6294 hw->buffer_spec[i].buf_adr,
6295 hw->buffer_spec[i].canvas_pos,
6296 hw->buffer_spec[i].vf_ref
6297 );
6298#ifdef CONFIG_AM_VDEC_DV
6299 dpb_print_cont(DECODE_ID(hw), 0,
6300 "dv_el_exist %d",
6301 hw->buffer_spec[i].dv_enhance_exist
6302 );
6303#endif
6304 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6305 }
6306
6307}
6308
6309static void vmh264_dump_state(struct vdec_s *vdec)
6310{
6311 struct vdec_h264_hw_s *hw =
6312 (struct vdec_h264_hw_s *)(vdec->private);
6313 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6314 dpb_print(DECODE_ID(hw), 0,
6315 "====== %s\n", __func__);
6316 dpb_print(DECODE_ID(hw), 0,
6317 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6318 hw->frame_width,
6319 hw->frame_height,
6320 hw->dpb.reorder_pic_num,
6321 hw->dpb.mDPB.size,
6322 hw->max_reference_size,
6323 hw->i_only,
6324 hw->send_error_frame_flag
6325 );
6326
6327 dpb_print(DECODE_ID(hw), 0,
6328 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6329 input_frame_based(vdec),
6330 hw->eos,
6331 hw->stat,
6332 hw->dec_result,
6333 decode_frame_count[DECODE_ID(hw)],
6334 display_frame_count[DECODE_ID(hw)],
6335 run_count[DECODE_ID(hw)],
6336 not_run_ready[DECODE_ID(hw)],
6337 input_empty[DECODE_ID(hw)],
6338 hw->reset_bufmgr_count
6339 );
6340
6341 if (vf_get_receiver(vdec->vf_provider_name)) {
6342 enum receviver_start_e state =
6343 vf_notify_receiver(vdec->vf_provider_name,
6344 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6345 NULL);
6346 dpb_print(DECODE_ID(hw), 0,
6347 "\nreceiver(%s) state %d\n",
6348 vdec->vf_provider_name,
6349 state);
6350 }
6351
6352 dpb_print(DECODE_ID(hw), 0,
6353 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x wait_reset_done_flag %d\n",
6354 __func__,
6355 kfifo_len(&hw->newframe_q),
6356 VF_POOL_SIZE,
6357 kfifo_len(&hw->display_q),
6358 VF_POOL_SIZE,
6359 hw->vf_pre_count,
6360 hw->vf_get_count,
6361 hw->vf_put_count,
6362 have_free_buf_spec(vdec),
6363 p_H264_Dpb->mDPB.init_done,
6364 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6365 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6366 p_H264_Dpb->fast_output_enable,
6367 hw->wait_reset_done_flag
6368 );
6369
6370 dump_dpb(&p_H264_Dpb->mDPB, 1);
6371 dump_pic(p_H264_Dpb);
6372 dump_bufspec(hw, __func__);
6373
6374 dpb_print(DECODE_ID(hw), 0,
6375 "DPB_STATUS_REG=0x%x\n",
6376 READ_VREG(DPB_STATUS_REG));
6377 dpb_print(DECODE_ID(hw), 0,
6378 "MPC_E=0x%x\n",
6379 READ_VREG(MPC_E));
6380 dpb_print(DECODE_ID(hw), 0,
6381 "H264_DECODE_MODE=0x%x\n",
6382 READ_VREG(H264_DECODE_MODE));
6383 dpb_print(DECODE_ID(hw), 0,
6384 "MBY_MBX=0x%x\n",
6385 READ_VREG(MBY_MBX));
6386 dpb_print(DECODE_ID(hw), 0,
6387 "H264_DECODE_SIZE=0x%x\n",
6388 READ_VREG(H264_DECODE_SIZE));
6389 dpb_print(DECODE_ID(hw), 0,
6390 "VIFF_BIT_CNT=0x%x\n",
6391 READ_VREG(VIFF_BIT_CNT));
6392 dpb_print(DECODE_ID(hw), 0,
6393 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6394 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6395 dpb_print(DECODE_ID(hw), 0,
6396 "VLD_MEM_VIFIFO_WP=0x%x\n",
6397 READ_VREG(VLD_MEM_VIFIFO_WP));
6398 dpb_print(DECODE_ID(hw), 0,
6399 "VLD_MEM_VIFIFO_RP=0x%x\n",
6400 READ_VREG(VLD_MEM_VIFIFO_RP));
6401 dpb_print(DECODE_ID(hw), 0,
6402 "PARSER_VIDEO_RP=0x%x\n",
6403 READ_PARSER_REG(PARSER_VIDEO_RP));
6404 dpb_print(DECODE_ID(hw), 0,
6405 "PARSER_VIDEO_WP=0x%x\n",
6406 READ_PARSER_REG(PARSER_VIDEO_WP));
6407
6408 if (input_frame_based(vdec) &&
6409 dpb_is_debug(DECODE_ID(hw),
6410 PRINT_FRAMEBASE_DATA)
6411 ) {
6412 int jj;
6413 if (hw->chunk && hw->chunk->block &&
6414 hw->chunk->size > 0) {
6415 u8 *data = NULL;
6416
6417 if (!hw->chunk->block->is_mapped)
6418 data = codec_mm_vmap(hw->chunk->block->start +
6419 hw->chunk->offset, hw->chunk->size);
6420 else
6421 data = ((u8 *)hw->chunk->block->start_virt)
6422 + hw->chunk->offset;
6423
6424 dpb_print(DECODE_ID(hw), 0,
6425 "frame data size 0x%x\n",
6426 hw->chunk->size);
6427 for (jj = 0; jj < hw->chunk->size; jj++) {
6428 if ((jj & 0xf) == 0)
6429 dpb_print(DECODE_ID(hw),
6430 PRINT_FRAMEBASE_DATA,
6431 "%06x:", jj);
6432 dpb_print_cont(DECODE_ID(hw),
6433 PRINT_FRAMEBASE_DATA,
6434 "%02x ", data[jj]);
6435 if (((jj + 1) & 0xf) == 0)
6436 dpb_print_cont(DECODE_ID(hw),
6437 PRINT_FRAMEBASE_DATA,
6438 "\n");
6439 }
6440
6441 if (!hw->chunk->block->is_mapped)
6442 codec_mm_unmap_phyaddr(data);
6443 }
6444 }
6445}
6446
6447
6448static void check_timer_func(unsigned long arg)
6449{
6450 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6451 struct vdec_s *vdec = hw_to_vdec(hw);
6452 int error_skip_frame_count = error_skip_count & 0xfff;
6453 unsigned int timeout_val = decode_timeout_val;
6454 if (timeout_val != 0 &&
6455 hw->no_error_count < error_skip_frame_count)
6456 timeout_val = errordata_timeout_val;
6457 if ((h264_debug_cmd & 0x100) != 0 &&
6458 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6459 hw->dec_result = DEC_RESULT_DONE;
6460 vdec_schedule_work(&hw->work);
6461 pr_info("vdec %d is forced to be disconnected\n",
6462 h264_debug_cmd & 0xff);
6463 h264_debug_cmd = 0;
6464 return;
6465 }
6466 if ((h264_debug_cmd & 0x200) != 0 &&
6467 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6468 pr_debug("vdec %d is forced to reset bufmgr\n",
6469 h264_debug_cmd & 0xff);
6470 hw->reset_bufmgr_flag = 1;
6471 h264_debug_cmd = 0;
6472 return;
6473 }
6474
6475 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6476 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6477 vdec_schedule_work(&hw->work);
6478 pr_debug("vdec requested to be disconnected\n");
6479 return;
6480 }
6481
6482 if (radr != 0) {
6483 if (rval != 0) {
6484 WRITE_VREG(radr, rval);
6485 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6486 } else
6487 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6488 rval = 0;
6489 radr = 0;
6490 }
6491
6492 if ((input_frame_based(vdec) ||
6493 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6494 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6495 (timeout_val > 0) &&
6496 (hw->start_process_time > 0) &&
6497 ((1000 * (jiffies - hw->start_process_time) / HZ)
6498 > timeout_val)
6499 ) {
6500 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6501 u32 mby_mbx = READ_VREG(MBY_MBX);
6502 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6503 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6504 if (hw->last_mby_mbx == mby_mbx) {
6505 if (hw->decode_timeout_count > 0)
6506 hw->decode_timeout_count--;
6507 if (hw->decode_timeout_count == 0)
6508 {
6509 reset_process_time(hw);
6510 timeout_process(hw);
6511 }
6512 } else
6513 start_process_time(hw);
6514 } else if (is_in_parsing_state(dpb_status)) {
6515 if (hw->last_vld_level ==
6516 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6517 if (hw->decode_timeout_count > 0)
6518 hw->decode_timeout_count--;
6519 if (hw->decode_timeout_count == 0)
6520 {
6521 reset_process_time(hw);
6522 timeout_process(hw);
6523 }
6524 }
6525 }
6526 hw->last_vld_level =
6527 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6528 hw->last_mby_mbx = mby_mbx;
6529 }
6530
6531 if ((hw->ucode_pause_pos != 0) &&
6532 (hw->ucode_pause_pos != 0xffffffff) &&
6533 udebug_pause_pos != hw->ucode_pause_pos) {
6534 hw->ucode_pause_pos = 0;
6535 WRITE_VREG(DEBUG_REG1, 0);
6536 }
6537
6538 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6539}
6540
6541static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6542{
6543 u32 ar;
6544 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6545
6546 if (!hw)
6547 return -1;
6548
6549 vstatus->frame_width = hw->frame_width;
6550 vstatus->frame_height = hw->frame_height;
6551 if (hw->frame_dur != 0)
6552 vstatus->frame_rate = 96000 / hw->frame_dur;
6553 else
6554 vstatus->frame_rate = -1;
6555 vstatus->error_count = 0;
6556 vstatus->status = hw->stat;
6557 if (hw->h264_ar == 0x3ff)
6558 hw->h264_ar = (0x100 *
6559 hw->frame_height * hw->height_aspect_ratio) /
6560 (hw->frame_width * hw->width_aspect_ratio);
6561 ar = min_t(u32,
6562 hw->h264_ar,
6563 DISP_RATIO_ASPECT_RATIO_MAX);
6564 vstatus->ratio_control =
6565 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6566
6567 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6568 "%s-%02d", DRIVER_NAME, hw->id);
6569
6570 return 0;
6571}
6572
6573static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6574{
6575 int i, j;
6576 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6577
6578 /* if (hw->init_flag == 0) { */
6579 if (h264_debug_flag & 0x40000000) {
6580 /* if (1) */
6581 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6582 "%s, reset register\n", __func__);
6583
6584 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6585 ;
6586 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6587 ; /* reg address is 0x350 */
6588
6589#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6590 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6591 WRITE_VREG(DOS_SW_RESET0, 0);
6592
6593 READ_VREG(DOS_SW_RESET0);
6594 READ_VREG(DOS_SW_RESET0);
6595 READ_VREG(DOS_SW_RESET0);
6596
6597 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6598 WRITE_VREG(DOS_SW_RESET0, 0);
6599
6600 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6601 WRITE_VREG(DOS_SW_RESET0, 0);
6602
6603 READ_VREG(DOS_SW_RESET0);
6604 READ_VREG(DOS_SW_RESET0);
6605 READ_VREG(DOS_SW_RESET0);
6606
6607#else
6608 WRITE_RESET_REG(RESET0_REGISTER,
6609 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6610 READ_RESET_REG(RESET0_REGISTER);
6611 WRITE_RESET_REG(RESET0_REGISTER,
6612 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6613
6614 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6615#endif
6616 WRITE_VREG(POWER_CTL_VLD,
6617 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6618 (1 << 9) | (1 << 6));
6619 } else {
6620 /* WRITE_VREG(POWER_CTL_VLD,
6621 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6622 */
6623 WRITE_VREG(POWER_CTL_VLD,
6624 READ_VREG(POWER_CTL_VLD) |
6625 (0 << 10) | (1 << 9) | (1 << 6));
6626 }
6627 /* disable PSCALE for hardware sharing */
6628 WRITE_VREG(PSCALE_CTRL, 0);
6629
6630 /* clear mailbox interrupt */
6631 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6632
6633 /* enable mailbox interrupt */
6634 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6635
6636#ifdef NV21
6637 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6638#endif
6639
6640 /* cbcr_merge_swap_en */
6641 if (hw->is_used_v4l
6642 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6643 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6644 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6645
6646 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6647 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6648
6649 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6650 if (hw->mmu_enable) {
6651 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6652 /* sw reset to extif hardware */
6653 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6654 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6655 } else {
6656 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6657 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6658 }
6659
6660
6661#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6662 /* pr_info("vh264 meson8 prot init\n"); */
6663 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6664#endif
6665
6666#ifdef VDEC_DW
6667 if (IS_VDEC_DW(hw)) {
6668 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6669
6670 if (IS_VDEC_DW(hw) == 2)
6671 data |= (1 << 9);
6672 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6673 }
6674#endif
6675 if (hw->dpb.mDPB.size > 0) {
6676 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6677 (hw->dpb.mDPB.size << 16) |
6678 (hw->dpb.mDPB.size << 8));
6679
6680 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6681 i = get_buf_spec_by_canvas_pos(hw, j);
6682 if (i < 0)
6683 break;
6684
6685 if (!hw->mmu_enable &&
6686 hw->buffer_spec[i].cma_alloc_addr)
6687 config_decode_canvas(hw, i);
6688 if (hw->mmu_enable && hw->double_write_mode)
6689 config_decode_canvas_ex(hw, i);
6690 }
6691 } else {
6692 WRITE_VREG(AV_SCRATCH_0, 0);
6693 WRITE_VREG(AV_SCRATCH_9, 0);
6694 }
6695
6696 if (hw->init_flag == 0)
6697 WRITE_VREG(DPB_STATUS_REG, 0);
6698 else
6699 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6700
6701 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6702 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6703 if (!tee_enabled())
6704 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6705
6706 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6707 * error_recovery_mode : error_recovery_mode_in;
6708 */
6709 /* WRITE_VREG(AV_SCRATCH_F,
6710 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6711 */
6712 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6713 ((error_recovery_mode_in & 0x1) << 4));
6714 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6715 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6716 else*/
6717 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6718
6719 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6720#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6721 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6722#endif
6723
6724 WRITE_VREG(DEBUG_REG1, 0);
6725 WRITE_VREG(DEBUG_REG2, 0);
6726
6727 if (hw->reg_iqidct_control)
6728 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6729 if (hw->reg_vcop_ctrl_reg)
6730 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6731 if (hw->vld_dec_control)
6732 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6733 return 0;
6734}
6735
6736static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6737{
6738 struct vdec_h264_hw_s *hw =
6739 (struct vdec_h264_hw_s *)vdec->private;
6740 if (i_only_flag & 0x100)
6741 return 0;
6742 if (trickmode == TRICKMODE_I)
6743 hw->i_only = 0x3;
6744 else if (trickmode == TRICKMODE_NONE)
6745 hw->i_only = 0x0;
6746 return 0;
6747}
6748
6749static unsigned char amvdec_enable_flag;
6750static void vh264_local_init(struct vdec_h264_hw_s *hw)
6751{
6752 int i;
6753 hw->init_flag = 0;
6754 hw->first_sc_checked= 0;
6755 hw->eos = 0;
6756 hw->valve_count = 0;
6757 hw->config_bufmgr_done = 0;
6758 hw->start_process_time = 0;
6759 hw->has_i_frame = 0;
6760 hw->no_error_count = 0xfff;
6761 hw->no_error_i_count = 0xf;
6762
6763 hw->dec_flag = 0;
6764 hw->data_flag = 0;
6765 hw->skip_frame_count = 0;
6766 hw->reg_iqidct_control = 0;
6767 hw->reg_vcop_ctrl_reg = 0;
6768 hw->reg_rv_ai_mb_count = 0;
6769 hw->vld_dec_control = 0;
6770 hw->decode_timeout_count = 0;
6771 hw->no_mem_count = 0;
6772 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6773 /* vh264_ratio = 0x100; */
6774
6775 hw->vh264_rotation = (((unsigned long)
6776 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6777
6778 hw->frame_prog = 0;
6779 hw->frame_width = hw->vh264_amstream_dec_info.width;
6780 hw->frame_height = hw->vh264_amstream_dec_info.height;
6781 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6782 hw->pts_outside = ((unsigned long)
6783 hw->vh264_amstream_dec_info.param) & 0x01;
6784 hw->sync_outside = ((unsigned long)
6785 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6786 hw->use_idr_framerate = ((unsigned long)
6787 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6788 hw->max_refer_buf = !(((unsigned long)
6789 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6790 if (hw->frame_dur < 96000/960) {
6791 /*more than 960fps,it should not be a correct value,
6792 *give default 30fps
6793 */
6794 hw->frame_dur = 96000/30;
6795 }
6796
6797 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6798
6799 hw->first_i_policy = first_i_policy;
6800
6801 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6802 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6803 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6804 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6805
6806 if (i_only_flag & 0x100)
6807 hw->i_only = i_only_flag & 0xff;
6808 if (hw->i_only)
6809 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6810
6811 if ((unsigned long) hw->vh264_amstream_dec_info.param
6812 & 0x08)
6813 hw->no_poc_reorder_flag = 1;
6814
6815 error_recovery_mode_in = 1; /*ucode control?*/
6816 if (error_proc_policy & 0x80000000)
6817 hw->send_error_frame_flag = error_proc_policy & 0x1;
6818 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6819 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6820
6821 INIT_KFIFO(hw->display_q);
6822 INIT_KFIFO(hw->newframe_q);
6823
6824 for (i = 0; i < VF_POOL_SIZE; i++) {
6825 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6826 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6827 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6828 kfifo_put(&hw->newframe_q, vf);
6829 }
6830
6831 hw->duration_from_pts_done = 0;
6832
6833 hw->p_last_vf = NULL;
6834 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6835 hw->hevc_cur_buf_idx = 0xffff;
6836
6837 init_waitqueue_head(&hw->wait_q);
6838
6839 return;
6840}
6841
6842static s32 vh264_init(struct vdec_h264_hw_s *hw)
6843{
6844 int size = -1;
6845 int fw_size = 0x1000 * 16;
6846 int fw_mmu_size = 0x1000 * 16;
6847 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6848
6849 /* int trickmode_fffb = 0; */
6850
6851 /* pr_info("\nvh264_init\n"); */
6852 /* init_timer(&hw->recycle_timer); */
6853
6854 /* timer init */
6855 init_timer(&hw->check_timer);
6856
6857 hw->check_timer.data = (unsigned long)hw;
6858 hw->check_timer.function = check_timer_func;
6859 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6860
6861 /* add_timer(&hw->check_timer); */
6862 hw->stat |= STAT_TIMER_ARM;
6863 hw->stat |= STAT_ISR_REG;
6864
6865 mutex_init(&hw->chunks_mutex);
6866 vh264_local_init(hw);
6867 INIT_WORK(&hw->work, vh264_work);
6868 INIT_WORK(&hw->notify_work, vh264_notify_work);
6869 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6870#ifdef MH264_USERDATA_ENABLE
6871 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6872#endif
6873
6874 if (!amvdec_enable_flag) {
6875 amvdec_enable_flag = true;
6876 amvdec_enable();
6877 if (hw->mmu_enable)
6878 amhevc_enable();
6879 }
6880 if (hw->mmu_enable) {
6881
6882 hw->frame_mmu_map_addr =
6883 dma_alloc_coherent(amports_get_dma_device(),
6884 FRAME_MMU_MAP_SIZE,
6885 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6886 if (hw->frame_mmu_map_addr == NULL) {
6887 pr_err("%s: failed to alloc count_buffer\n", __func__);
6888 return -ENOMEM;
6889 }
6890 }
6891
6892 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6893 if (IS_ERR_OR_NULL(fw))
6894 return -ENOMEM;
6895
6896 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6897 if (size < 0) {
6898 pr_err("get firmware fail.\n");
6899 vfree(fw);
6900 return -1;
6901 }
6902
6903 fw->len = size;
6904 hw->fw = fw;
6905
6906 if (hw->mmu_enable) {
6907 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6908 if (IS_ERR_OR_NULL(fw_mmu))
6909 return -ENOMEM;
6910
6911 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6912 if (size < 0) {
6913 pr_err("get mmu fw fail.\n");
6914 vfree(fw_mmu);
6915 return -1;
6916 }
6917
6918 fw_mmu->len = size;
6919 hw->fw_mmu = fw_mmu;
6920 }
6921
6922 if (!tee_enabled()) {
6923 /* -- ucode loading (amrisc and swap code) */
6924 hw->mc_cpu_addr =
6925 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6926 &hw->mc_dma_handle, GFP_KERNEL);
6927 if (!hw->mc_cpu_addr) {
6928 amvdec_enable_flag = false;
6929 amvdec_disable();
6930 if (hw->mmu_enable)
6931 amhevc_disable();
6932 pr_info("vh264_init: Can not allocate mc memory.\n");
6933 return -ENOMEM;
6934 }
6935
6936 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6937 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6938 */
6939
6940 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6941
6942 /*header*/
6943 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6944 fw->data + 0x4000, MC_SWAP_SIZE);
6945 /*data*/
6946 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6947 fw->data + 0x2000, MC_SWAP_SIZE);
6948 /*mmco*/
6949 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6950 fw->data + 0x6000, MC_SWAP_SIZE);
6951 /*list*/
6952 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6953 fw->data + 0x3000, MC_SWAP_SIZE);
6954 /*slice*/
6955 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6956 fw->data + 0x5000, MC_SWAP_SIZE);
6957 /*main*/
6958 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6959 fw->data, 0x2000);
6960 /*data*/
6961 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6962 fw->data + 0x2000, 0x1000);
6963 /*slice*/
6964 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6965 fw->data + 0x5000, 0x1000);
6966 }
6967
6968#if 1 /* #ifdef BUFFER_MGR_IN_C */
6969 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6970 if (!hw->lmem_addr) {
6971 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6972 return -ENOMEM;
6973 } else {
6974 hw->lmem_addr_remap = dma_map_single(
6975 amports_get_dma_device(),
6976 (void *)hw->lmem_addr,
6977 PAGE_SIZE, DMA_FROM_DEVICE);
6978 if (dma_mapping_error(amports_get_dma_device(),
6979 hw->lmem_addr_remap)) {
6980 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6981 "%s: failed to map lmem_addr\n", __func__);
6982 free_page(hw->lmem_addr);
6983 hw->lmem_addr = 0;
6984 hw->lmem_addr_remap = 0;
6985 return -ENOMEM;
6986 }
6987
6988 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6989 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6990 }
6991
6992 if (prefix_aux_buf_size > 0 ||
6993 suffix_aux_buf_size > 0) {
6994 u32 aux_buf_size;
6995 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6996 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
6997 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
6998 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
6999 if (hw->aux_addr == NULL) {
7000 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7001 return -1;
7002 }
7003
7004 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7005 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7006 if (dma_mapping_error(amports_get_dma_device(),
7007 hw->aux_phy_addr)) {
7008 pr_err("%s: failed to map rpm buffer\n", __func__);
7009 kfree(hw->aux_addr);
7010 hw->aux_addr = NULL;
7011 return -1;
7012 }
7013 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7014 if (hw->sei_data_buf == NULL) {
7015 pr_err("%s: failed to alloc sei itu data buffer\n",
7016 __func__);
7017 return -1;
7018 }
7019 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7020 if (hw->sei_itu_data_buf == NULL) {
7021 pr_err("%s: failed to alloc sei itu data buffer\n",
7022 __func__);
7023 kfree(hw->aux_addr);
7024 hw->aux_addr = NULL;
7025 kfree(hw->sei_data_buf);
7026 hw->sei_data_buf = NULL;
7027
7028 return -1;
7029 }
7030
7031 if (NULL == hw->sei_user_data_buffer) {
7032 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7033 GFP_KERNEL);
7034 if (!hw->sei_user_data_buffer) {
7035 pr_info("%s: Can not allocate sei_data_buffer\n",
7036 __func__);
7037 kfree(hw->aux_addr);
7038 hw->aux_addr = NULL;
7039 kfree(hw->sei_data_buf);
7040 hw->sei_data_buf = NULL;
7041 kfree(hw->sei_itu_data_buf);
7042 hw->sei_itu_data_buf = NULL;
7043
7044 return -1;
7045 }
7046 hw->sei_user_data_wp = 0;
7047 }
7048 }
7049/* BUFFER_MGR_IN_C */
7050#endif
7051 hw->stat |= STAT_MC_LOAD;
7052
7053 /* add memory barrier */
7054 wmb();
7055
7056 return 0;
7057}
7058
7059static int vh264_stop(struct vdec_h264_hw_s *hw)
7060{
7061 if (hw->stat & STAT_VDEC_RUN) {
7062 amvdec_stop();
7063 hw->stat &= ~STAT_VDEC_RUN;
7064 }
7065#ifdef VDEC_DW
7066 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7067#endif
7068#ifdef MH264_USERDATA_ENABLE
7069 cancel_work_sync(&hw->user_data_ready_work);
7070#endif
7071 cancel_work_sync(&hw->notify_work);
7072 cancel_work_sync(&hw->timeout_work);
7073 cancel_work_sync(&hw->work);
7074
7075
7076 if (hw->stat & STAT_MC_LOAD) {
7077 if (hw->mc_cpu_addr != NULL) {
7078 dma_free_coherent(amports_get_dma_device(),
7079 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7080 hw->mc_dma_handle);
7081 hw->mc_cpu_addr = NULL;
7082 }
7083 if (hw->frame_mmu_map_addr != NULL) {
7084 dma_free_coherent(amports_get_dma_device(),
7085 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7086 hw->frame_mmu_map_phy_addr);
7087 hw->frame_mmu_map_addr = NULL;
7088 }
7089
7090 }
7091 if (hw->stat & STAT_ISR_REG) {
7092 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7093 hw->stat &= ~STAT_ISR_REG;
7094 }
7095 if (hw->lmem_addr_remap) {
7096 dma_unmap_single(amports_get_dma_device(),
7097 hw->lmem_addr_remap,
7098 PAGE_SIZE, DMA_FROM_DEVICE);
7099 hw->lmem_addr_remap = 0;
7100 }
7101 if (hw->lmem_addr) {
7102 free_page(hw->lmem_addr);
7103 hw->lmem_addr = 0;
7104 }
7105 if (hw->aux_addr) {
7106 dma_unmap_single(amports_get_dma_device(),
7107 hw->aux_phy_addr,
7108 hw->prefix_aux_size + hw->suffix_aux_size,
7109 DMA_FROM_DEVICE);
7110 kfree(hw->aux_addr);
7111 hw->aux_addr = NULL;
7112 }
7113 if (hw->sei_data_buf != NULL) {
7114 kfree(hw->sei_data_buf);
7115 hw->sei_data_buf = NULL;
7116 }
7117 if (hw->sei_itu_data_buf != NULL) {
7118 kfree(hw->sei_itu_data_buf);
7119 hw->sei_itu_data_buf = NULL;
7120 }
7121 if (hw->sei_user_data_buffer != NULL) {
7122 kfree(hw->sei_user_data_buffer);
7123 hw->sei_user_data_buffer = NULL;
7124 }
7125 /* amvdec_disable(); */
7126
7127 vfree(hw->fw);
7128 hw->fw = NULL;
7129
7130 if (hw->mmu_enable) {
7131 vfree(hw->fw_mmu);
7132 hw->fw_mmu = NULL;
7133 }
7134
7135 dpb_print(DECODE_ID(hw), 0,
7136 "%s\n",
7137 __func__);
7138 return 0;
7139}
7140
7141static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7142{
7143 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7144 int count = 0;
7145 do {
7146 usleep_range(100, 500);
7147 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7148 break;
7149 if (count > 2000) {
7150 dpb_print(DECODE_ID(hw),
7151 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7152 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7153 break;
7154 } else
7155 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7156 count++;
7157 } while (1);
7158}
7159
7160static void vh264_notify_work(struct work_struct *work)
7161{
7162 struct vdec_h264_hw_s *hw = container_of(work,
7163 struct vdec_h264_hw_s, notify_work);
7164 struct vdec_s *vdec = hw_to_vdec(hw);
7165 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7166 vf_notify_receiver(vdec->vf_provider_name,
7167 VFRAME_EVENT_PROVIDER_FR_HINT,
7168 (void *)((unsigned long)hw->frame_dur));
7169 vdec->fr_hint_state = VDEC_HINTED;
7170 }
7171
7172 return;
7173}
7174
7175#ifdef MH264_USERDATA_ENABLE
7176static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7177{
7178 hw->wait_for_udr_send = 0;
7179 hw->sei_itu_data_len = 0;
7180 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7181}
7182
7183static void vmh264_crate_userdata_manager(
7184 struct vdec_h264_hw_s *hw,
7185 u8 *userdata_buf,
7186 int buf_len)
7187{
7188 if (hw) {
7189
7190
7191 mutex_init(&hw->userdata_mutex);
7192
7193 memset(&hw->userdata_info, 0,
7194 sizeof(struct mh264_userdata_info_t));
7195 hw->userdata_info.data_buf = userdata_buf;
7196 hw->userdata_info.buf_len = buf_len;
7197 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7198
7199 vmh264_reset_udr_mgr(hw);
7200
7201 }
7202}
7203
7204static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7205{
7206 if (hw)
7207 memset(&hw->userdata_info,
7208 0,
7209 sizeof(struct mh264_userdata_info_t));
7210}
7211
7212/*
7213#define DUMP_USERDATA_RECORD
7214*/
7215#ifdef DUMP_USERDATA_RECORD
7216
7217#define MAX_USER_DATA_SIZE 3145728
7218static void *user_data_buf;
7219static unsigned char *pbuf_start;
7220static int total_len;
7221static int bskip;
7222static int n_userdata_id;
7223
7224static void print_data(unsigned char *pdata,
7225 int len,
7226 unsigned int poc_number,
7227 unsigned int flag,
7228 unsigned int duration,
7229 unsigned int vpts,
7230 unsigned int vpts_valid,
7231 int rec_id)
7232{
7233 int nLeft;
7234
7235 nLeft = len;
7236#if 0
7237 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7238 rec_id, len, flag,
7239 duration, vpts, vpts_valid, poc_number);
7240#endif
7241 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7242 rec_id, len, flag, vpts);
7243
7244 if (len == 96) {
7245 int i;
7246 nLeft = 72;
7247 while (nLeft >= 16) {
7248 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7249 pdata[0], pdata[1], pdata[2], pdata[3],
7250 pdata[4], pdata[5], pdata[6], pdata[7],
7251 pdata[8], pdata[9], pdata[10], pdata[11],
7252 pdata[12], pdata[13], pdata[14], pdata[15]);
7253 nLeft -= 16;
7254 pdata += 16;
7255 }
7256
7257
7258 while (nLeft > 0) {
7259 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7260 pdata[0], pdata[1], pdata[2], pdata[3],
7261 pdata[4], pdata[5], pdata[6], pdata[7]);
7262 nLeft -= 8;
7263 pdata += 8;
7264 }
7265
7266 i = 0;
7267 nLeft = 96-72;
7268 while (i < nLeft) {
7269 if (pdata[0] != 0) {
7270 pr_info("some data error\n");
7271 break;
7272 }
7273 pdata++;
7274 i++;
7275 }
7276 } else {
7277 while (nLeft >= 16) {
7278 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7279 pdata[0], pdata[1], pdata[2], pdata[3],
7280 pdata[4], pdata[5], pdata[6], pdata[7],
7281 pdata[8], pdata[9], pdata[10], pdata[11],
7282 pdata[12], pdata[13], pdata[14], pdata[15]);
7283 nLeft -= 16;
7284 pdata += 16;
7285 }
7286
7287
7288 while (nLeft > 0) {
7289 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7290 pdata[0], pdata[1], pdata[2], pdata[3],
7291 pdata[4], pdata[5], pdata[6], pdata[7]);
7292 nLeft -= 8;
7293 pdata += 8;
7294 }
7295
7296 }
7297}
7298
7299static void push_to_buf(struct vdec_h264_hw_s *hw,
7300 u8 *pdata,
7301 int len,
7302 struct userdata_meta_info_t *pmeta);
7303
7304static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7305 struct mh264_userdata_record_t *record)
7306{
7307 if (record && hw) {
7308 u8 *pdata;
7309
7310 pdata = hw->userdata_info.data_buf + record->rec_start;
7311/*
7312 print_data(pdata,
7313 record->rec_len,
7314 record->meta_info.flags,
7315 record->meta_info.duration,
7316 record->meta_info.vpts,
7317 record->meta_info.vpts_valid,
7318 n_record_id);
7319*/
7320 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7321 n_userdata_id++;
7322 }
7323}
7324
7325
7326static void push_to_buf(struct vdec_h264_hw_s *hw,
7327 u8 *pdata, int len,
7328 struct userdata_meta_info_t *pmeta)
7329{
7330 u32 *pLen;
7331 int info_cnt;
7332 u8 *pbuf_end;
7333
7334 if (!user_data_buf)
7335 return;
7336
7337 if (bskip) {
7338 pr_info("over size, skip\n");
7339 return;
7340 }
7341 info_cnt = 0;
7342 pLen = (u32 *)pbuf_start;
7343
7344 *pLen = len;
7345 pbuf_start += sizeof(u32);
7346 info_cnt++;
7347 pLen++;
7348
7349 *pLen = pmeta->poc_number;
7350 pbuf_start += sizeof(u32);
7351 info_cnt++;
7352 pLen++;
7353
7354 *pLen = pmeta->duration;
7355 pbuf_start += sizeof(u32);
7356 info_cnt++;
7357 pLen++;
7358
7359 *pLen = pmeta->flags;
7360 pbuf_start += sizeof(u32);
7361 info_cnt++;
7362 pLen++;
7363
7364 *pLen = pmeta->vpts;
7365 pbuf_start += sizeof(u32);
7366 info_cnt++;
7367 pLen++;
7368
7369 *pLen = pmeta->vpts_valid;
7370 pbuf_start += sizeof(u32);
7371 info_cnt++;
7372 pLen++;
7373
7374
7375 *pLen = n_userdata_id;
7376 pbuf_start += sizeof(u32);
7377 info_cnt++;
7378 pLen++;
7379
7380
7381
7382 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7383 if (pdata + len > pbuf_end) {
7384 int first_section_len;
7385
7386 first_section_len = pbuf_end - pdata;
7387 memcpy(pbuf_start, pdata, first_section_len);
7388 pdata = (u8 *)hw->sei_user_data_buffer;
7389 pbuf_start += first_section_len;
7390 memcpy(pbuf_start, pdata, len - first_section_len);
7391 pbuf_start += len - first_section_len;
7392 } else {
7393 memcpy(pbuf_start, pdata, len);
7394 pbuf_start += len;
7395 }
7396
7397 total_len += len + info_cnt * sizeof(u32);
7398 if (total_len >= MAX_USER_DATA_SIZE-4096)
7399 bskip = 1;
7400}
7401
7402static void show_user_data_buf(void)
7403{
7404 u8 *pbuf;
7405 int len;
7406 unsigned int flag;
7407 unsigned int duration;
7408 unsigned int vpts;
7409 unsigned int vpts_valid;
7410 unsigned int poc_number;
7411 int rec_id;
7412
7413 pr_info("show user data buf\n");
7414 pbuf = user_data_buf;
7415
7416 while (pbuf < pbuf_start) {
7417 u32 *pLen;
7418
7419 pLen = (u32 *)pbuf;
7420
7421 len = *pLen;
7422 pLen++;
7423 pbuf += sizeof(u32);
7424
7425 poc_number = *pLen;
7426 pLen++;
7427 pbuf += sizeof(u32);
7428
7429 duration = *pLen;
7430 pLen++;
7431 pbuf += sizeof(u32);
7432
7433 flag = *pLen;
7434 pLen++;
7435 pbuf += sizeof(u32);
7436
7437 vpts = *pLen;
7438 pLen++;
7439 pbuf += sizeof(u32);
7440
7441 vpts_valid = *pLen;
7442 pLen++;
7443 pbuf += sizeof(u32);
7444
7445 rec_id = *pLen;
7446 pLen++;
7447 pbuf += sizeof(u32);
7448
7449 print_data(pbuf, len, poc_number, flag,
7450 duration, vpts,
7451 vpts_valid, rec_id);
7452 pbuf += len;
7453 msleep(30);
7454 }
7455}
7456
7457static int vmh264_init_userdata_dump(void)
7458{
7459 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7460 if (user_data_buf)
7461 return 1;
7462 else
7463 return 0;
7464}
7465
7466static void vmh264_dump_userdata(void)
7467{
7468 if (user_data_buf) {
7469 show_user_data_buf();
7470 kfree(user_data_buf);
7471 user_data_buf = NULL;
7472 }
7473}
7474
7475static void vmh264_reset_user_data_buf(void)
7476{
7477 total_len = 0;
7478 pbuf_start = user_data_buf;
7479 bskip = 0;
7480 n_userdata_id = 0;
7481}
7482#endif
7483
7484
7485static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7486 int frame_type,
7487 u32 vpts,
7488 u32 vpts_valid)
7489{
7490 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7491
7492 unsigned char *pdata;
7493 u8 *pmax_sei_data_buffer;
7494 u8 *sei_data_buf;
7495 int i;
7496 int wp;
7497 int data_length;
7498 struct mh264_userdata_record_t *p_userdata_rec;
7499
7500
7501#ifdef MH264_USERDATA_ENABLE
7502 struct userdata_meta_info_t meta_info;
7503 memset(&meta_info, 0, sizeof(meta_info));
7504#endif
7505
7506 if (hw->sei_itu_data_len <= 0)
7507 return;
7508
7509 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7510 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7511 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7512 for (i = 0; i < hw->sei_itu_data_len; i++) {
7513 *pdata++ = sei_data_buf[i];
7514 if (pdata >= pmax_sei_data_buffer)
7515 pdata = (u8 *)hw->sei_user_data_buffer;
7516 }
7517
7518 hw->sei_user_data_wp = (hw->sei_user_data_wp
7519 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7520 hw->sei_itu_data_len = 0;
7521
7522#ifdef MH264_USERDATA_ENABLE
7523 meta_info.duration = hw->frame_dur;
7524 meta_info.flags |= (VFORMAT_H264 << 3);
7525
7526 meta_info.vpts = vpts;
7527 meta_info.vpts_valid = vpts_valid;
7528 meta_info.poc_number =
7529 p_H264_Dpb->mVideo.dec_picture->poc;
7530
7531
7532 wp = hw->sei_user_data_wp;
7533
7534 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7535 data_length = wp - hw->userdata_info.last_wp;
7536 else
7537 data_length = wp + hw->userdata_info.buf_len
7538 - hw->userdata_info.last_wp;
7539
7540 if (data_length & 0x7)
7541 data_length = (((data_length + 8) >> 3) << 3);
7542
7543 p_userdata_rec = &hw->ud_record;
7544 p_userdata_rec->meta_info = meta_info;
7545 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7546 p_userdata_rec->rec_len = data_length;
7547 hw->userdata_info.last_wp = wp;
7548
7549 p_userdata_rec->meta_info.flags |=
7550 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7551
7552 hw->wait_for_udr_send = 1;
7553 vdec_schedule_work(&hw->user_data_ready_work);
7554#endif
7555}
7556
7557
7558static void user_data_ready_notify_work(struct work_struct *work)
7559{
7560 struct vdec_h264_hw_s *hw = container_of(work,
7561 struct vdec_h264_hw_s, user_data_ready_work);
7562
7563
7564 mutex_lock(&hw->userdata_mutex);
7565
7566 hw->userdata_info.records[hw->userdata_info.write_index]
7567 = hw->ud_record;
7568 hw->userdata_info.write_index++;
7569 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7570 hw->userdata_info.write_index = 0;
7571
7572 mutex_unlock(&hw->userdata_mutex);
7573
7574#ifdef DUMP_USERDATA_RECORD
7575 dump_userdata_record(hw, &hw->ud_record);
7576#endif
7577 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7578
7579 hw->wait_for_udr_send = 0;
7580}
7581
7582static int vmh264_user_data_read(struct vdec_s *vdec,
7583 struct userdata_param_t *puserdata_para)
7584{
7585 struct vdec_h264_hw_s *hw = NULL;
7586 int rec_ri, rec_wi;
7587 int rec_len;
7588 u8 *rec_data_start;
7589 u8 *pdest_buf;
7590 struct mh264_userdata_record_t *p_userdata_rec;
7591 u32 data_size;
7592 u32 res;
7593 int copy_ok = 1;
7594
7595 hw = (struct vdec_h264_hw_s *)vdec->private;
7596
7597 pdest_buf = puserdata_para->pbuf_addr;
7598
7599 mutex_lock(&hw->userdata_mutex);
7600
7601/*
7602 pr_info("ri = %d, wi = %d\n",
7603 lg_p_mpeg12_userdata_info->read_index,
7604 lg_p_mpeg12_userdata_info->write_index);
7605*/
7606 rec_ri = hw->userdata_info.read_index;
7607 rec_wi = hw->userdata_info.write_index;
7608
7609 if (rec_ri == rec_wi) {
7610 mutex_unlock(&hw->userdata_mutex);
7611 return 0;
7612 }
7613
7614 p_userdata_rec = hw->userdata_info.records + rec_ri;
7615
7616 rec_len = p_userdata_rec->rec_len;
7617 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7618/*
7619 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7620 p_userdata_rec->rec_len,
7621 p_userdata_rec->rec_start,
7622 puserdata_para->buf_len);
7623*/
7624 if (rec_len <= puserdata_para->buf_len) {
7625 /* dvb user data buffer is enought to
7626 copy the whole recored. */
7627 data_size = rec_len;
7628 if (rec_data_start + data_size
7629 > hw->userdata_info.data_buf_end) {
7630 int first_section_len;
7631
7632 first_section_len = hw->userdata_info.buf_len -
7633 p_userdata_rec->rec_start;
7634 res = (u32)copy_to_user((void *)pdest_buf,
7635 (void *)rec_data_start,
7636 first_section_len);
7637 if (res) {
7638 pr_info("p1 read not end res=%d, request=%d\n",
7639 res, first_section_len);
7640 copy_ok = 0;
7641
7642 p_userdata_rec->rec_len -=
7643 first_section_len - res;
7644 p_userdata_rec->rec_start +=
7645 first_section_len - res;
7646 puserdata_para->data_size =
7647 first_section_len - res;
7648 } else {
7649 res = (u32)copy_to_user(
7650 (void *)(pdest_buf+first_section_len),
7651 (void *)hw->userdata_info.data_buf,
7652 data_size - first_section_len);
7653 if (res) {
7654 pr_info("p2 read not end res=%d, request=%d\n",
7655 res, data_size);
7656 copy_ok = 0;
7657 }
7658 p_userdata_rec->rec_len -=
7659 data_size - res;
7660 p_userdata_rec->rec_start =
7661 data_size - first_section_len - res;
7662 puserdata_para->data_size =
7663 data_size - res;
7664 }
7665 } else {
7666 res = (u32)copy_to_user((void *)pdest_buf,
7667 (void *)rec_data_start,
7668 data_size);
7669 if (res) {
7670 pr_info("p3 read not end res=%d, request=%d\n",
7671 res, data_size);
7672 copy_ok = 0;
7673 }
7674 p_userdata_rec->rec_len -= data_size - res;
7675 p_userdata_rec->rec_start += data_size - res;
7676 puserdata_para->data_size = data_size - res;
7677 }
7678
7679 if (copy_ok) {
7680 hw->userdata_info.read_index++;
7681 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7682 hw->userdata_info.read_index = 0;
7683 }
7684 } else {
7685 /* dvb user data buffer is not enought
7686 to copy the whole recored. */
7687 data_size = puserdata_para->buf_len;
7688 if (rec_data_start + data_size
7689 > hw->userdata_info.data_buf_end) {
7690 int first_section_len;
7691
7692 first_section_len = hw->userdata_info.buf_len -
7693 p_userdata_rec->rec_start;
7694 res = (u32)copy_to_user((void *)pdest_buf,
7695 (void *)rec_data_start,
7696 first_section_len);
7697 if (res) {
7698 pr_info("p4 read not end res=%d, request=%d\n",
7699 res, first_section_len);
7700 copy_ok = 0;
7701 p_userdata_rec->rec_len -=
7702 first_section_len - res;
7703 p_userdata_rec->rec_start +=
7704 first_section_len - res;
7705 puserdata_para->data_size =
7706 first_section_len - res;
7707 } else {
7708 /* first secton copy is ok*/
7709 res = (u32)copy_to_user(
7710 (void *)(pdest_buf+first_section_len),
7711 (void *)hw->userdata_info.data_buf,
7712 data_size - first_section_len);
7713 if (res) {
7714 pr_info("p5 read not end res=%d, request=%d\n",
7715 res,
7716 data_size - first_section_len);
7717 copy_ok = 0;
7718 }
7719
7720 p_userdata_rec->rec_len -=
7721 data_size - res;
7722 p_userdata_rec->rec_start =
7723 data_size - first_section_len - res;
7724 puserdata_para->data_size =
7725 data_size - res;
7726 }
7727 } else {
7728 res = (u32)copy_to_user((void *)pdest_buf,
7729 (void *)rec_data_start,
7730 data_size);
7731 if (res) {
7732 pr_info("p6 read not end res=%d, request=%d\n",
7733 res, data_size);
7734 copy_ok = 0;
7735 }
7736
7737 p_userdata_rec->rec_len -= data_size - res;
7738 p_userdata_rec->rec_start += data_size - res;
7739 puserdata_para->data_size = data_size - res;
7740 }
7741
7742 if (copy_ok) {
7743 hw->userdata_info.read_index++;
7744 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7745 hw->userdata_info.read_index = 0;
7746 }
7747
7748 }
7749 puserdata_para->meta_info = p_userdata_rec->meta_info;
7750
7751 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7752 puserdata_para->meta_info.records_in_que =
7753 hw->userdata_info.write_index -
7754 hw->userdata_info.read_index;
7755 else
7756 puserdata_para->meta_info.records_in_que =
7757 hw->userdata_info.write_index +
7758 USERDATA_FIFO_NUM -
7759 hw->userdata_info.read_index;
7760
7761 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7762
7763 mutex_unlock(&hw->userdata_mutex);
7764
7765 return 1;
7766}
7767
7768static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7769{
7770 struct vdec_h264_hw_s *hw = NULL;
7771
7772 hw = (struct vdec_h264_hw_s *)vdec->private;
7773
7774 if (hw) {
7775 mutex_lock(&hw->userdata_mutex);
7776 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7777 bInit,
7778 hw->userdata_info.read_index,
7779 hw->userdata_info.write_index);
7780 hw->userdata_info.read_index = 0;
7781 hw->userdata_info.write_index = 0;
7782
7783 if (bInit)
7784 hw->userdata_info.last_wp = 0;
7785 mutex_unlock(&hw->userdata_mutex);
7786 }
7787}
7788
7789static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7790{
7791 amstream_wakeup_userdata_poll(vdec);
7792}
7793
7794#endif
7795
7796
7797static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7798 struct vdec_s *vdec, int from)
7799{
7800 /* finished decoding one frame or error,
7801 * notify vdec core to switch context
7802 */
7803 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7804 "%s dec_result %d %x %x %x\n",
7805 __func__,
7806 hw->dec_result,
7807 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7808 READ_VREG(VLD_MEM_VIFIFO_WP),
7809 READ_VREG(VLD_MEM_VIFIFO_RP));
7810 if (!hw->mmu_enable) {
7811 mutex_lock(&vmh264_mutex);
7812 dealloc_buf_specs(hw, 0);
7813 mutex_unlock(&vmh264_mutex);
7814 }
7815 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7816 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7817 u32 param1 = READ_VREG(AV_SCRATCH_1);
7818 u32 param2 = READ_VREG(AV_SCRATCH_2);
7819 u32 param3 = READ_VREG(AV_SCRATCH_6);
7820 u32 param4 = READ_VREG(AV_SCRATCH_B);
7821
7822 if (vh264_set_params(hw, param1,
7823 param2, param3, param4) < 0)
7824 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7825
7826 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7827 (hw->dpb.mDPB.size<<16) |
7828 (hw->dpb.mDPB.size<<8));
7829
7830 if (hw->is_used_v4l) {
7831 struct aml_vcodec_ctx *ctx =
7832 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7833
7834 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7835 struct aml_vdec_ps_infos ps;
7836
7837 ps.visible_width = hw->frame_width;
7838 ps.visible_height = hw->frame_height;
7839 ps.coded_width = ALIGN(hw->frame_width, 64);
7840 ps.coded_height = ALIGN(hw->frame_height, 64);
7841 ps.dpb_size = hw->dpb.mDPB.size;
7842 hw->v4l_params_parsed = true;
7843 vdec_v4l_set_ps_infos(ctx, &ps);
7844 }
7845 }
7846
7847 start_process_time(hw);
7848 return;
7849 } else
7850 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7851 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7852 && (hw_to_vdec(hw)->next_status !=
7853 VDEC_STATUS_DISCONNECTED)) {
7854 if (!vdec_has_more_input(vdec)) {
7855 hw->dec_result = DEC_RESULT_EOS;
7856 vdec_schedule_work(&hw->work);
7857 return;
7858 }
7859
7860 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7861 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7862 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7863 __func__,
7864 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7865 READ_VREG(VLD_MEM_VIFIFO_WP),
7866 READ_VREG(VLD_MEM_VIFIFO_RP));
7867 mutex_lock(&hw->chunks_mutex);
7868 vdec_vframe_dirty(vdec, hw->chunk);
7869 hw->chunk = NULL;
7870 mutex_unlock(&hw->chunks_mutex);
7871 vdec_clean_input(vdec);
7872 }
7873 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7874 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7875 > get_data_timeout_val)) {
7876 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7877 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7878 __func__);
7879 goto result_done;
7880 }
7881 if (is_buffer_available(vdec)) {
7882 int r;
7883 int decode_size;
7884 r = vdec_prepare_input(vdec, &hw->chunk);
7885 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7886 VDEC_STATUS_DISCONNECTED)) {
7887 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7888
7889 dpb_print(DECODE_ID(hw),
7890 PRINT_FLAG_VDEC_DETAIL,
7891 "vdec_prepare_input: Insufficient data\n");
7892 vdec_schedule_work(&hw->work);
7893 return;
7894 }
7895 hw->dec_result = DEC_RESULT_NONE;
7896 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7897 "%s: chunk size 0x%x\n",
7898 __func__, hw->chunk->size);
7899
7900 if (dpb_is_debug(DECODE_ID(hw),
7901 PRINT_FRAMEBASE_DATA)) {
7902 int jj;
7903 u8 *data = NULL;
7904
7905 if (!hw->chunk->block->is_mapped)
7906 data = codec_mm_vmap(
7907 hw->chunk->block->start +
7908 hw->chunk->offset, r);
7909 else
7910 data = ((u8 *)
7911 hw->chunk->block->start_virt)
7912 + hw->chunk->offset;
7913
7914 for (jj = 0; jj < r; jj++) {
7915 if ((jj & 0xf) == 0)
7916 dpb_print(DECODE_ID(hw),
7917 PRINT_FRAMEBASE_DATA,
7918 "%06x:", jj);
7919 dpb_print_cont(DECODE_ID(hw),
7920 PRINT_FRAMEBASE_DATA,
7921 "%02x ", data[jj]);
7922 if (((jj + 1) & 0xf) == 0)
7923 dpb_print_cont(DECODE_ID(hw),
7924 PRINT_FRAMEBASE_DATA,
7925 "\n");
7926 }
7927
7928 if (!hw->chunk->block->is_mapped)
7929 codec_mm_unmap_phyaddr(data);
7930 }
7931 WRITE_VREG(POWER_CTL_VLD,
7932 READ_VREG(POWER_CTL_VLD) |
7933 (0 << 10) | (1 << 9) | (1 << 6));
7934 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7935 decode_size = hw->chunk->size +
7936 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7937 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7938 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7939 vdec_enable_input(vdec);
7940
7941 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7942 start_process_time(hw);
7943 } else{
7944 if (hw_to_vdec(hw)->next_status
7945 != VDEC_STATUS_DISCONNECTED) {
7946 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7947 vdec_schedule_work(&hw->work);
7948 }
7949 }
7950 return;
7951 } else if (hw->dec_result == DEC_RESULT_DONE) {
7952 /* if (!hw->ctx_valid)
7953 hw->ctx_valid = 1; */
7954result_done:
7955 if (hw->mmu_enable
7956 && hw->frame_busy && hw->frame_done) {
7957 long used_4k_num;
7958 hevc_sao_wait_done(hw);
7959 if (hw->hevc_cur_buf_idx != 0xffff) {
7960 used_4k_num =
7961 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7962 if (used_4k_num >= 0)
7963 dpb_print(DECODE_ID(hw),
7964 PRINT_FLAG_MMU_DETAIL,
7965 "release unused buf , used_4k_num %ld index %d\n",
7966 used_4k_num, hw->hevc_cur_buf_idx);
7967 hevc_mmu_dma_check(hw_to_vdec(hw));
7968 decoder_mmu_box_free_idx_tail(
7969 hw->mmu_box,
7970 hw->hevc_cur_buf_idx,
7971 used_4k_num);
7972 hw->hevc_cur_buf_idx = 0xffff;
7973 }
7974 }
7975 decode_frame_count[DECODE_ID(hw)]++;
7976 amvdec_stop();
7977 if (!vdec_is_support_4k()) {
7978 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7979 clk_adj_frame_count++;
7980 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7981 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7982 }
7983 }
7984 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7985 "%s dec_result %d %x %x %x\n",
7986 __func__,
7987 hw->dec_result,
7988 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7989 READ_VREG(VLD_MEM_VIFIFO_WP),
7990 READ_VREG(VLD_MEM_VIFIFO_RP));
7991 mutex_lock(&hw->chunks_mutex);
7992 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7993 hw->chunk = NULL;
7994 mutex_unlock(&hw->chunks_mutex);
7995 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7996 /*
7997 stream base: stream buf empty or timeout
7998 frame base: vdec_prepare_input fail
7999 */
8000 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8001 VDEC_STATUS_DISCONNECTED)) {
8002 hw->dec_result = DEC_RESULT_EOS;
8003 vdec_schedule_work(&hw->work);
8004 return;
8005 }
8006 hw->next_again_flag = 1;
8007 } else if (hw->dec_result == DEC_RESULT_EOS) {
8008 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8009 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8010 "%s: end of stream\n",
8011 __func__);
8012 amvdec_stop();
8013 if (hw->mmu_enable)
8014 amhevc_stop();
8015 hw->eos = 1;
8016 flush_dpb(p_H264_Dpb);
8017 if (hw->is_used_v4l)
8018 notify_v4l_eos(hw_to_vdec(hw));
8019 mutex_lock(&hw->chunks_mutex);
8020 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8021 hw->chunk = NULL;
8022 mutex_unlock(&hw->chunks_mutex);
8023 vdec_clean_input(vdec);
8024 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8025 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8026 "%s: force exit\n",
8027 __func__);
8028 amvdec_stop();
8029 if (hw->mmu_enable)
8030 amhevc_stop();
8031 if (hw->stat & STAT_ISR_REG) {
8032 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8033 hw->stat &= ~STAT_ISR_REG;
8034 }
8035 }
8036 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8037 del_timer_sync(&hw->check_timer);
8038 hw->stat &= ~STAT_TIMER_ARM;
8039
8040 wait_vmh264_search_done(hw);
8041 /* mark itself has all HW resource released and input released */
8042
8043#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8044 if (hw->switch_dvlayer_flag) {
8045 if (vdec->slave)
8046 vdec_set_next_sched(vdec, vdec->slave);
8047 else if (vdec->master)
8048 vdec_set_next_sched(vdec, vdec->master);
8049 } else if (vdec->slave || vdec->master)
8050 vdec_set_next_sched(vdec, vdec);
8051#endif
8052
8053 if (from == 1) {
8054 /* This is a timeout work */
8055 if (work_pending(&hw->work)) {
8056 /*
8057 * The vh264_work arrives at the last second,
8058 * give it a chance to handle the scenario.
8059 */
8060 return;
8061 }
8062 }
8063
8064 /* mark itself has all HW resource released and input released */
8065 if (vdec->parallel_dec == 1) {
8066 if (hw->mmu_enable == 0)
8067 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8068 else
8069 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8070 } else
8071 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8072
8073 wake_up_interruptible(&hw->wait_q);
8074
8075 if (hw->is_used_v4l) {
8076 struct aml_vcodec_ctx *ctx =
8077 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8078
8079 if (ctx->param_sets_from_ucode &&
8080 !hw->v4l_params_parsed)
8081 vdec_v4l_write_frame_sync(ctx);
8082 }
8083
8084 if (hw->vdec_cb)
8085 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8086}
8087
8088
8089static void vh264_work(struct work_struct *work)
8090{
8091 struct vdec_h264_hw_s *hw = container_of(work,
8092 struct vdec_h264_hw_s, work);
8093 struct vdec_s *vdec = hw_to_vdec(hw);
8094
8095 vh264_work_implement(hw, vdec, 0);
8096}
8097
8098
8099static void vh264_timeout_work(struct work_struct *work)
8100{
8101 struct vdec_h264_hw_s *hw = container_of(work,
8102 struct vdec_h264_hw_s, timeout_work);
8103 struct vdec_s *vdec = hw_to_vdec(hw);
8104
8105 if (work_pending(&hw->work))
8106 return;
8107
8108 vh264_work_implement(hw, vdec, 1);
8109}
8110
8111static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8112{
8113 bool ret = 0;
8114 struct vdec_h264_hw_s *hw =
8115 (struct vdec_h264_hw_s *)vdec->private;
8116 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8117 CODEC_MM_FLAGS_TVP : 0;
8118
8119 if (!hw->first_sc_checked && hw->mmu_enable) {
8120 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8121 hw->first_sc_checked =1;
8122 dpb_print(DECODE_ID(hw), 0,
8123 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8124 size, (hw->need_cache_size >> PAGE_SHIFT),
8125 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8126 }
8127
8128 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8129 && pre_decode_buf_level != 0) {
8130 u32 rp, wp, level;
8131
8132 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8133 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8134 if (wp < rp)
8135 level = vdec->input.size + wp - rp;
8136 else
8137 level = wp - rp;
8138
8139 if (level < pre_decode_buf_level)
8140 return 0;
8141 }
8142
8143#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8144 if (vdec->master)
8145 return 0;
8146#endif
8147 if (hw->eos)
8148 return 0;
8149
8150 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8151 return 0;
8152
8153 if (disp_vframe_valve_level &&
8154 kfifo_len(&hw->display_q) >=
8155 disp_vframe_valve_level) {
8156 hw->valve_count--;
8157 if (hw->valve_count <= 0)
8158 hw->valve_count = 2;
8159 else
8160 return 0;
8161 }
8162 if (hw->next_again_flag &&
8163 (!vdec_frame_based(vdec))) {
8164 u32 parser_wr_ptr =
8165 READ_PARSER_REG(PARSER_VIDEO_WP);
8166 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8167 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8168 again_threshold) {
8169 int r = vdec_sync_input(vdec);
8170 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8171 "%s buf lelvel:%x\n", __func__, r);
8172 return 0;
8173 }
8174 }
8175
8176 if (h264_debug_flag & 0x20000000) {
8177 /* pr_info("%s, a\n", __func__); */
8178 ret = 1;
8179 } else
8180 ret = is_buffer_available(vdec);
8181
8182#ifdef CONSTRAIN_MAX_BUF_NUM
8183 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8184 if (run_ready_max_vf_only_num > 0 &&
8185 get_vf_ref_only_buf_count(hw) >=
8186 run_ready_max_vf_only_num
8187 )
8188 ret = 0;
8189 if (run_ready_display_q_num > 0 &&
8190 kfifo_len(&hw->display_q) >=
8191 run_ready_display_q_num)
8192 ret = 0;
8193 /*avoid more buffers consumed when
8194 switching resolution*/
8195 if (run_ready_max_buf_num == 0xff &&
8196 get_used_buf_count(hw) >
8197 hw->dpb.mDPB.size)
8198 ret = 0;
8199 else if (run_ready_max_buf_num &&
8200 get_used_buf_count(hw) >=
8201 run_ready_max_buf_num)
8202 ret = 0;
8203 }
8204#endif
8205 if (hw->is_used_v4l) {
8206 struct aml_vcodec_ctx *ctx =
8207 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8208
8209 if (ctx->param_sets_from_ucode &&
8210 !ctx->v4l_codec_ready &&
8211 hw->v4l_params_parsed) {
8212 ret = 0; /*the params has parsed.*/
8213 } else if (!ctx->v4l_codec_dpb_ready)
8214 ret = 0;
8215 else if (hw->wait_reset_done_flag)
8216 ret = 0;
8217 }
8218
8219 if (ret)
8220 not_run_ready[DECODE_ID(hw)] = 0;
8221 else
8222 not_run_ready[DECODE_ID(hw)]++;
8223 if (vdec->parallel_dec == 1) {
8224 if (hw->mmu_enable == 0)
8225 return ret ? (CORE_MASK_VDEC_1) : 0;
8226 else
8227 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8228 } else
8229 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8230}
8231
8232static unsigned char get_data_check_sum
8233 (struct vdec_h264_hw_s *hw, int size)
8234{
8235 int jj;
8236 int sum = 0;
8237 u8 *data = NULL;
8238
8239 if (!hw->chunk->block->is_mapped)
8240 data = codec_mm_vmap(hw->chunk->block->start +
8241 hw->chunk->offset, size);
8242 else
8243 data = ((u8 *)hw->chunk->block->start_virt)
8244 + hw->chunk->offset;
8245
8246 for (jj = 0; jj < size; jj++)
8247 sum += data[jj];
8248
8249 if (!hw->chunk->block->is_mapped)
8250 codec_mm_unmap_phyaddr(data);
8251 return sum;
8252}
8253
8254static void run(struct vdec_s *vdec, unsigned long mask,
8255 void (*callback)(struct vdec_s *, void *), void *arg)
8256{
8257 struct vdec_h264_hw_s *hw =
8258 (struct vdec_h264_hw_s *)vdec->private;
8259 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8260 int size, ret = -1;
8261
8262 run_count[DECODE_ID(hw)]++;
8263 vdec_reset_core(vdec);
8264 if (hw->mmu_enable)
8265 hevc_reset_core(vdec);
8266 hw->vdec_cb_arg = arg;
8267 hw->vdec_cb = callback;
8268
8269 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8270 hw->reset_bufmgr_flag = 1;
8271 dpb_print(DECODE_ID(hw), 0,
8272 "kfifo len:%d invaild, need bufmgr reset\n",
8273 kfifo_len(&hw->display_q));
8274 }
8275
8276 hw->pre_parser_wr_ptr =
8277 READ_PARSER_REG(PARSER_VIDEO_WP);
8278 hw->next_again_flag = 0;
8279
8280 if (hw->reset_bufmgr_flag ||
8281 ((error_proc_policy & 0x40) &&
8282 p_H264_Dpb->buf_alloc_fail)) {
8283 if (!hw->is_used_v4l)
8284 h264_reset_bufmgr(vdec);
8285 else {
8286 struct aml_vcodec_ctx *ctx =
8287 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8288 pr_info("v4l2 buffer reset\n");
8289 hw->wait_reset_done_flag = 1;
8290 hw->reset_bufmgr_flag = 0;
8291 vdec_v4l_post_evet(ctx, V4L2_EVENT_REQUEST_RESET);
8292 hw->dec_result = DEC_RESULT_NONE;
8293 vdec_schedule_work(&hw->work);
8294 return;
8295 }
8296 hw->reset_bufmgr_flag = 0;
8297 }
8298
8299 if (h264_debug_cmd & 0xf000) {
8300 if (((h264_debug_cmd >> 12) & 0xf)
8301 == (DECODE_ID(hw) + 1)) {
8302 h264_reconfig(hw);
8303 h264_debug_cmd &= (~0xf000);
8304 }
8305 }
8306 /* hw->chunk = vdec_prepare_input(vdec); */
8307#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8308 if (vdec->slave || vdec->master)
8309 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8310#endif
8311 size = vdec_prepare_input(vdec, &hw->chunk);
8312 if ((size < 0) ||
8313 (input_frame_based(vdec) && hw->chunk == NULL)) {
8314 input_empty[DECODE_ID(hw)]++;
8315 hw->dec_result = DEC_RESULT_AGAIN;
8316
8317 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8318 "vdec_prepare_input: Insufficient data\n");
8319
8320 vdec_schedule_work(&hw->work);
8321 return;
8322 }
8323 input_empty[DECODE_ID(hw)] = 0;
8324
8325 hw->dec_result = DEC_RESULT_NONE;
8326 hw->get_data_count = 0;
8327#if 0
8328 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8329 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8330 READ_VREG(VLD_MEM_VIFIFO_RP),
8331 READ_VREG(VLD_MEM_VIFIFO_WP));
8332#endif
8333
8334 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8335 u8 *data = NULL;
8336
8337 if (!hw->chunk->block->is_mapped)
8338 data = codec_mm_vmap(hw->chunk->block->start +
8339 hw->chunk->offset, size);
8340 else
8341 data = ((u8 *)hw->chunk->block->start_virt)
8342 + hw->chunk->offset;
8343
8344 if (dpb_is_debug(DECODE_ID(hw),
8345 PRINT_FLAG_VDEC_STATUS)
8346 ) {
8347 dpb_print(DECODE_ID(hw), 0,
8348 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8349 __func__, size, get_data_check_sum(hw, size),
8350 data[0], data[1], data[2], data[3],
8351 data[4], data[5], data[size - 4],
8352 data[size - 3], data[size - 2],
8353 data[size - 1]);
8354 }
8355 if (dpb_is_debug(DECODE_ID(hw),
8356 PRINT_FRAMEBASE_DATA)
8357 ) {
8358 int jj;
8359
8360 for (jj = 0; jj < size; jj++) {
8361 if ((jj & 0xf) == 0)
8362 dpb_print(DECODE_ID(hw),
8363 PRINT_FRAMEBASE_DATA,
8364 "%06x:", jj);
8365 dpb_print_cont(DECODE_ID(hw),
8366 PRINT_FRAMEBASE_DATA,
8367 "%02x ", data[jj]);
8368 if (((jj + 1) & 0xf) == 0)
8369 dpb_print_cont(DECODE_ID(hw),
8370 PRINT_FRAMEBASE_DATA,
8371 "\n");
8372 }
8373 }
8374
8375 if (!hw->chunk->block->is_mapped)
8376 codec_mm_unmap_phyaddr(data);
8377 } else
8378 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8379 "%s: %x %x %x %x %x size 0x%x\n",
8380 __func__,
8381 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8382 READ_VREG(VLD_MEM_VIFIFO_WP),
8383 READ_VREG(VLD_MEM_VIFIFO_RP),
8384 READ_PARSER_REG(PARSER_VIDEO_RP),
8385 READ_PARSER_REG(PARSER_VIDEO_WP),
8386 size);
8387
8388 start_process_time(hw);
8389 if (vdec->mc_loaded) {
8390 /*firmware have load before,
8391 and not changes to another.
8392 ignore reload.
8393 */
8394 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8395 } else {
8396
8397 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8398 if (ret < 0) {
8399 amvdec_enable_flag = false;
8400 amvdec_disable();
8401
8402 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8403 "MH264 the %s fw loading failed, err: %x\n",
8404 tee_enabled() ? "TEE" : "local", ret);
8405 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8406 vdec_schedule_work(&hw->work);
8407 return;
8408 }
8409 vdec->mc_type = VFORMAT_H264;
8410 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8411 if (hw->mmu_enable) {
8412 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8413 hw->fw_mmu->data);
8414 if (ret < 0) {
8415 amvdec_enable_flag = false;
8416 amhevc_disable();
8417
8418 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8419 "MH264_MMU the %s fw loading failed, err: %x\n",
8420 tee_enabled() ? "TEE" : "local", ret);
8421 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8422 vdec_schedule_work(&hw->work);
8423 return;
8424 }
8425 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8426 }
8427 vdec->mc_loaded = 1;
8428 }
8429 vmh264_reset_udr_mgr(hw);
8430
8431 if (vh264_hw_ctx_restore(hw) < 0) {
8432 vdec_schedule_work(&hw->work);
8433 return;
8434 }
8435 if (input_frame_based(vdec)) {
8436 int decode_size = 0;
8437
8438 decode_size = hw->chunk->size +
8439 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8440 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8441 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8442 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8443 } else {
8444 if (size <= 0)
8445 size = 0x7fffffff; /*error happen*/
8446 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8447 WRITE_VREG(H264_DECODE_SIZE, size);
8448 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8449 }
8450 config_aux_buf(hw);
8451 config_decode_mode(hw);
8452 vdec_enable_input(vdec);
8453 WRITE_VREG(NAL_SEARCH_CTL, 0);
8454 hw->sei_data_len = 0;
8455 if (enable_itu_t35)
8456 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8457 if (!hw->init_flag) {
8458 if (hw->mmu_enable)
8459 WRITE_VREG(NAL_SEARCH_CTL,
8460 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8461 else
8462 WRITE_VREG(NAL_SEARCH_CTL,
8463 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8464 }
8465 if (udebug_flag)
8466 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8467 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8468
8469 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8470
8471 if (hw->mmu_enable)
8472 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8473 else
8474 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8475 }
8476 amvdec_start();
8477 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8478 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8479 amhevc_start();
8480 if (hw->config_bufmgr_done) {
8481 hevc_mcr_sao_global_hw_init(hw,
8482 (hw->mb_width << 4), (hw->mb_height << 4));
8483 hevc_mcr_config_canv2axitbl(hw, 1);
8484 }
8485 }
8486
8487 /* if (hw->init_flag) { */
8488 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8489 /* } */
8490
8491 hw->init_flag = 1;
8492}
8493
8494static void reset(struct vdec_s *vdec)
8495{
8496 struct vdec_h264_hw_s *hw =
8497 (struct vdec_h264_hw_s *)vdec->private;
8498
8499 pr_info("vmh264 reset\n");
8500
8501 cancel_work_sync(&hw->work);
8502 cancel_work_sync(&hw->notify_work);
8503 if (hw->stat & STAT_VDEC_RUN) {
8504 amhevc_stop();
8505 hw->stat &= ~STAT_VDEC_RUN;
8506 }
8507
8508 if (hw->stat & STAT_TIMER_ARM) {
8509 del_timer_sync(&hw->check_timer);
8510 hw->stat &= ~STAT_TIMER_ARM;
8511 }
8512 hw->eos = 0;
8513 hw->decode_pic_count = 0;
8514 hw->dec_result = DEC_RESULT_NONE;
8515 reset_process_time(hw);
8516 h264_reset_bufmgr(vdec);
8517 hw->wait_reset_done_flag = 0;
8518
8519 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8520}
8521
8522static void h264_reconfig(struct vdec_h264_hw_s *hw)
8523{
8524 int i;
8525 unsigned long flags;
8526 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8527 struct vdec_s *vdec = hw_to_vdec(hw);
8528 dpb_print(DECODE_ID(hw), 0,
8529 "%s\n", __func__);
8530 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8531 all buffers are in display queue (used == 2),
8532 or free (used == 0)
8533 */
8534 if (dpb_is_debug(DECODE_ID(hw),
8535 PRINT_FLAG_DUMP_BUFSPEC))
8536 dump_bufspec(hw, "pre h264_reconfig");
8537
8538 flush_dpb(p_H264_Dpb);
8539 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8540
8541 if (hw->collocate_cma_alloc_addr) {
8542 decoder_bmmu_box_free_idx(
8543 hw->bmmu_box,
8544 BMMU_REF_IDX);
8545 hw->collocate_cma_alloc_addr = 0;
8546 hw->dpb.colocated_mv_addr_start = 0;
8547 hw->dpb.colocated_mv_addr_end = 0;
8548 }
8549 spin_lock_irqsave(&hw->bufspec_lock, flags);
8550 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8551 if (vdec->parallel_dec == 1) {
8552 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8553 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8554 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8555 hw->buffer_spec[i].y_canvas_index = -1;
8556 hw->buffer_spec[i].u_canvas_index = -1;
8557 hw->buffer_spec[i].v_canvas_index = -1;
8558#ifdef VDEC_DW
8559 if (IS_VDEC_DW(hw)) {
8560 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8561 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8562 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8563 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8564 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8565 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8566#endif
8567 }
8568 }
8569 /*make sure buffers not put back to bufmgr when
8570 vf_put is called*/
8571 if (hw->buffer_spec[i].used == 2)
8572 hw->buffer_spec[i].used = 3;
8573
8574 /* ready to release "free buffers"
8575 */
8576 if (hw->buffer_spec[i].used == 0)
8577 hw->buffer_spec[i].used = 4;
8578
8579 hw->buffer_spec[i].canvas_pos = -1;
8580 }
8581 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8582 hw->has_i_frame = 0;
8583 hw->config_bufmgr_done = 0;
8584
8585 if (hw->is_used_v4l) {
8586 mutex_lock(&vmh264_mutex);
8587 dealloc_buf_specs(hw, 1);
8588 mutex_unlock(&vmh264_mutex);
8589 }
8590
8591 if (dpb_is_debug(DECODE_ID(hw),
8592 PRINT_FLAG_DUMP_BUFSPEC))
8593 dump_bufspec(hw, "after h264_reconfig");
8594
8595}
8596
8597#ifdef ERROR_HANDLE_TEST
8598static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8599{
8600 int i;
8601 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8602 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8603 "%s\n", __func__);
8604 remove_dpb_pictures(p_H264_Dpb);
8605 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8606 /*make sure buffers not put back to bufmgr when
8607 vf_put is called*/
8608 if (hw->buffer_spec[i].used == 2)
8609 hw->buffer_spec[i].used = 5;
8610 }
8611
8612}
8613#endif
8614
8615static void h264_reset_bufmgr(struct vdec_s *vdec)
8616{
8617 int i;
8618 ulong timeout;
8619 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8620#if 0
8621 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8622 int actual_dpb_size, max_reference_size;
8623 int reorder_pic_num;
8624 unsigned int colocated_buf_size;
8625 unsigned int colocated_mv_addr_start;
8626 unsigned int colocated_mv_addr_end;
8627 dpb_print(DECODE_ID(hw), 0,
8628 "%s\n", __func__);
8629
8630 for (i = 0; i < VF_POOL_SIZE; i++)
8631 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8632
8633 actual_dpb_size = p_H264_Dpb->mDPB.size;
8634 max_reference_size = p_H264_Dpb->max_reference_size;
8635 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8636
8637 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8638 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8639 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8640
8641 hw->cur_pool++;
8642 if (hw->cur_pool >= VF_POOL_NUM)
8643 hw->cur_pool = 0;
8644
8645 INIT_KFIFO(hw->display_q);
8646 INIT_KFIFO(hw->newframe_q);
8647
8648 for (i = 0; i < VF_POOL_SIZE; i++) {
8649 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8650 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8651 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8652 kfifo_put(&hw->newframe_q, vf);
8653 }
8654
8655 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8656 hw->buffer_spec[i].used = 0;
8657
8658 dpb_init_global(&hw->dpb,
8659 DECODE_ID(hw), 0, 0);
8660 p_H264_Dpb->mDPB.size = actual_dpb_size;
8661 p_H264_Dpb->max_reference_size = max_reference_size;
8662 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8663
8664 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8665 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8666 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8667
8668 p_H264_Dpb->fast_output_enable = fast_output_enable;
8669 hw->has_i_frame = 0;
8670#else
8671 dpb_print(DECODE_ID(hw), 0,
8672 "%s frame count %d to skip %d\n\n",
8673 __func__, hw->decode_pic_count+1,
8674 hw->skip_frame_count);
8675
8676 timeout = jiffies + HZ;
8677 while (kfifo_len(&hw->display_q) > 0) {
8678 if (time_after(jiffies, timeout))
8679 break;
8680 schedule();
8681 }
8682
8683 for (i = 0; i < VF_POOL_SIZE; i++)
8684 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8685
8686 hw->cur_pool++;
8687 if (hw->cur_pool >= VF_POOL_NUM)
8688 hw->cur_pool = 0;
8689
8690 for (i = 0; i < VF_POOL_SIZE; i++)
8691 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8692
8693
8694 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8695
8696 buf_spec_init(hw);
8697
8698 vh264_local_init(hw);
8699 /*hw->decode_pic_count = 0;
8700 hw->seq_info2 = 0;*/
8701
8702 if (hw->is_used_v4l) {
8703 mutex_lock(&vmh264_mutex);
8704 /* detach relationship with v4l buffs.*/
8705 dealloc_buf_specs(hw, 1);
8706 mutex_unlock(&vmh264_mutex);
8707 }
8708
8709 if (vh264_set_params(hw,
8710 hw->cfg_param1,
8711 hw->cfg_param2,
8712 hw->cfg_param3,
8713 hw->cfg_param4) < 0)
8714 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8715
8716 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8717 if (first_i_policy & 0x01)
8718 hw->first_i_policy = (3 << 8) | first_i_policy;
8719
8720 hw->init_flag = 1;
8721 hw->reset_bufmgr_count++;
8722#endif
8723}
8724
8725int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8726{
8727 int ret = -1;
8728 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8729 CODEC_MM_FLAGS_TVP : 0;
8730 int buf_size = 64;
8731
8732 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8733 tvp_flag, hw->mmu_enable);
8734 hw->need_cache_size = buf_size * SZ_1M;
8735 hw->sc_start_time = get_jiffies_64();
8736 if (hw->mmu_enable && !hw->mmu_box) {
8737 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8738 hw->id,
8739 MMU_MAX_BUFFERS,
8740 hw->need_cache_size,
8741 tvp_flag);
8742 if (!hw->mmu_box) {
8743 pr_err("h264 4k alloc mmu box failed!!\n");
8744 return -1;
8745 }
8746 ret = 0;
8747 }
8748 if (!hw->bmmu_box) {
8749 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8750 DRIVER_NAME,
8751 hw->id,
8752 BMMU_MAX_BUFFERS,
8753 4 + PAGE_SHIFT,
8754 CODEC_MM_FLAGS_CMA_CLEAR |
8755 CODEC_MM_FLAGS_FOR_VDECODER |
8756 tvp_flag);
8757 if (hw->bmmu_box)
8758 ret = 0;
8759 }
8760 return ret;
8761}
8762int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8763{
8764 if (hw->mmu_box) {
8765 decoder_mmu_box_free(hw->mmu_box);
8766 hw->mmu_box = NULL;
8767 }
8768 if (hw->bmmu_box) {
8769 decoder_bmmu_box_free(hw->bmmu_box);
8770 hw->bmmu_box = NULL;
8771 }
8772 return 0;
8773}
8774
8775static int ammvdec_h264_probe(struct platform_device *pdev)
8776{
8777 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8778 struct vdec_h264_hw_s *hw = NULL;
8779 char *tmpbuf;
8780 int config_val;
8781
8782 if (pdata == NULL) {
8783 pr_info("\nammvdec_h264 memory resource undefined.\n");
8784 return -EFAULT;
8785 }
8786
8787 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8788 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8789 if (hw == NULL) {
8790 pr_info("\nammvdec_h264 device data allocation failed\n");
8791 return -ENOMEM;
8792 }
8793 hw->id = pdev->id;
8794 hw->platform_dev = pdev;
8795
8796 /* the ctx from v4l2 driver. */
8797 hw->v4l2_ctx = pdata->private;
8798
8799 platform_set_drvdata(pdev, pdata);
8800
8801 hw->mmu_enable = 0;
8802 hw->first_head_check_flag = 0;
8803 hw->new_iframe_flag = 0;
8804 hw->ref_err_flush_dpb_flag = 0;
8805 hw->wait_reset_done_flag = 0;
8806
8807 if (pdata->sys_info)
8808 hw->vh264_amstream_dec_info = *pdata->sys_info;
8809
8810 if (force_enable_mmu && pdata->sys_info &&
8811 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8812 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8813 (pdata->sys_info->height * pdata->sys_info->width
8814 > 1920 * 1088))
8815 hw->mmu_enable = 1;
8816
8817 if (hw->mmu_enable &&
8818 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8819 hw->mmu_enable = 0;
8820 pr_info("ionvideo needs disable mmu, path= %d \n",
8821 pdata->frame_base_video_path);
8822 }
8823
8824 if (ammvdec_h264_mmu_init(hw)) {
8825 h264_free_hw_stru(&pdev->dev, (void *)hw);
8826 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8827 return -ENOMEM;
8828 }
8829
8830 if (pdata->config_len) {
8831 /*use ptr config for doubel_write_mode, etc*/
8832 if (get_config_int(pdata->config,
8833 "mh264_double_write_mode", &config_val) == 0)
8834 hw->double_write_mode = config_val;
8835 else
8836 hw->double_write_mode = double_write_mode;
8837
8838 if (get_config_int(pdata->config,
8839 "parm_v4l_codec_enable",
8840 &config_val) == 0)
8841 hw->is_used_v4l = config_val;
8842
8843 if (get_config_int(pdata->config,
8844 "parm_v4l_buffer_margin",
8845 &config_val) == 0)
8846 hw->reorder_dpb_size_margin = config_val;
8847
8848 if (get_config_int(pdata->config,
8849 "parm_v4l_canvas_mem_mode",
8850 &config_val) == 0)
8851 hw->canvas_mode = config_val;
8852 } else
8853 hw->double_write_mode = double_write_mode;
8854
8855 if (!hw->is_used_v4l) {
8856 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8857 hw->canvas_mode = mem_map_mode;
8858
8859 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8860 hw->canvas_mode = pdata->canvas_mode;
8861 }
8862
8863 if (hw->mmu_enable)
8864 hw->double_write_mode &= 0xffff;
8865
8866 if (pdata->parallel_dec == 1) {
8867 int i;
8868 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8869 hw->buffer_spec[i].y_canvas_index = -1;
8870 hw->buffer_spec[i].u_canvas_index = -1;
8871 hw->buffer_spec[i].v_canvas_index = -1;
8872#ifdef VDEC_DW
8873 if (IS_VDEC_DW(hw)) {
8874 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8875 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8876 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8877 }
8878#endif
8879 }
8880 }
8881
8882 dpb_print(DECODE_ID(hw), 0,
8883 "%s mmu_enable %d double_write_mode 0x%x\n",
8884 __func__, hw->mmu_enable, hw->double_write_mode);
8885
8886 pdata->private = hw;
8887 pdata->dec_status = dec_status;
8888 pdata->set_trickmode = vmh264_set_trickmode;
8889 pdata->run_ready = run_ready;
8890 pdata->run = run;
8891 pdata->reset = reset;
8892 pdata->irq_handler = vh264_isr;
8893 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8894 pdata->dump_state = vmh264_dump_state;
8895
8896#ifdef MH264_USERDATA_ENABLE
8897 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8898 pdata->user_data_read = vmh264_user_data_read;
8899 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8900#else
8901 pdata->wakeup_userdata_poll = NULL;
8902 pdata->user_data_read = NULL;
8903 pdata->reset_userdata_fifo = NULL;
8904#endif
8905 if (pdata->use_vfm_path) {
8906 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8907 VFM_DEC_PROVIDER_NAME);
8908 hw->frameinfo_enable = 1;
8909 }
8910#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8911 else if (vdec_dual(pdata)) {
8912 if (dv_toggle_prov_name) /*debug purpose*/
8913 snprintf(pdata->vf_provider_name,
8914 VDEC_PROVIDER_NAME_SIZE,
8915 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8916 VFM_DEC_DVEL_PROVIDER_NAME);
8917 else
8918 snprintf(pdata->vf_provider_name,
8919 VDEC_PROVIDER_NAME_SIZE,
8920 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8921 VFM_DEC_DVBL_PROVIDER_NAME);
8922 }
8923#endif
8924 else
8925 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8926 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8927
8928 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8929 &vf_provider_ops, pdata);
8930
8931 platform_set_drvdata(pdev, pdata);
8932
8933 buf_spec_init(hw);
8934
8935 hw->platform_dev = pdev;
8936
8937#ifdef DUMP_USERDATA_RECORD
8938 vmh264_init_userdata_dump();
8939 vmh264_reset_user_data_buf();
8940#endif
8941 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8942 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8943 h264_free_hw_stru(&pdev->dev, (void *)hw);
8944 pdata->dec_status = NULL;
8945 return -ENOMEM;
8946 }
8947
8948 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8949 DCAC_READ_MARGIN;
8950 if (hw->mmu_enable) {
8951 u32 extif_size = EXTIF_BUF_SIZE;
8952 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8953 extif_size <<= 1;
8954 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8955 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8956 h264_free_hw_stru(&pdev->dev, (void *)hw);
8957 pdata->dec_status = NULL;
8958 return -ENOMEM;
8959 }
8960 }
8961 if (!vdec_secure(pdata)) {
8962#if 1
8963 /*init internal buf*/
8964 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8965 if (tmpbuf) {
8966 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8967 codec_mm_dma_flush(tmpbuf,
8968 V_BUF_ADDR_OFFSET,
8969 DMA_TO_DEVICE);
8970 } else {
8971 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8972 V_BUF_ADDR_OFFSET);
8973 if (tmpbuf) {
8974 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8975 codec_mm_dma_flush(tmpbuf,
8976 V_BUF_ADDR_OFFSET,
8977 DMA_TO_DEVICE);
8978 codec_mm_unmap_phyaddr(tmpbuf);
8979 }
8980 }
8981#else
8982 /*init sps/pps internal buf 64k*/
8983 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8984 + (mem_sps_base - DEF_BUF_START_ADDR));
8985 memset(tmpbuf, 0, 0x10000);
8986 dma_sync_single_for_device(amports_get_dma_device(),
8987 hw->cma_alloc_addr +
8988 (mem_sps_base - DEF_BUF_START_ADDR),
8989 0x10000, DMA_TO_DEVICE);
8990#endif
8991 }
8992 /**/
8993
8994#if 0
8995 if (NULL == hw->sei_data_buffer) {
8996 hw->sei_data_buffer =
8997 dma_alloc_coherent(amports_get_dma_device(),
8998 USER_DATA_SIZE,
8999 &hw->sei_data_buffer_phys, GFP_KERNEL);
9000 if (!hw->sei_data_buffer) {
9001 pr_info("%s: Can not allocate sei_data_buffer\n",
9002 __func__);
9003 ammvdec_h264_mmu_release(hw);
9004 h264_free_hw_stru(&pdev->dev, (void *)hw);
9005 return -ENOMEM;
9006 }
9007 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9008 sei_data_buffer, sei_data_buffer_phys,
9009 (u32)sei_data_buffer_remap); */
9010 }
9011#endif
9012 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9013 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9014
9015 if (vdec_is_support_4k() ||
9016 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9017 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9018 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9019 {
9020 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9021 }else
9022 {
9023 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9024 }
9025
9026 if (vh264_init(hw) < 0) {
9027 pr_info("\nammvdec_h264 init failed.\n");
9028 ammvdec_h264_mmu_release(hw);
9029 h264_free_hw_stru(&pdev->dev, (void *)hw);
9030 pdata->dec_status = NULL;
9031 return -ENODEV;
9032 }
9033#ifdef MH264_USERDATA_ENABLE
9034 vmh264_crate_userdata_manager(hw,
9035 hw->sei_user_data_buffer,
9036 USER_DATA_SIZE);
9037#endif
9038
9039 vdec_set_prepare_level(pdata, start_decode_buf_level);
9040 if (pdata->parallel_dec == 1) {
9041 if (hw->mmu_enable == 0)
9042 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9043 else {
9044 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9045 | CORE_MASK_COMBINE);
9046 }
9047 } else
9048 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9049 | CORE_MASK_COMBINE);
9050
9051 atomic_set(&hw->vh264_active, 1);
9052
9053 return 0;
9054}
9055
9056static int ammvdec_h264_remove(struct platform_device *pdev)
9057{
9058 struct vdec_h264_hw_s *hw =
9059 (struct vdec_h264_hw_s *)
9060 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9061 int i;
9062
9063 struct vdec_s *vdec = hw_to_vdec(hw);
9064
9065 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9066 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9067 dpb_print(DECODE_ID(hw), 0,
9068 "%s force exit %d\n", __func__, __LINE__);
9069 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9070 vdec_schedule_work(&hw->work);
9071 wait_event_interruptible_timeout(hw->wait_q,
9072 (vdec->status == VDEC_STATUS_CONNECTED),
9073 msecs_to_jiffies(1000)); /* wait for work done */
9074 }
9075
9076 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9077 release_aux_data(hw, i);
9078
9079 atomic_set(&hw->vh264_active, 0);
9080
9081 if (hw->stat & STAT_TIMER_ARM) {
9082 del_timer_sync(&hw->check_timer);
9083 hw->stat &= ~STAT_TIMER_ARM;
9084 }
9085
9086 vh264_stop(hw);
9087#ifdef MH264_USERDATA_ENABLE
9088#ifdef DUMP_USERDATA_RECORD
9089 vmh264_dump_userdata();
9090#endif
9091 vmh264_destroy_userdata_manager(hw);
9092#endif
9093 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9094
9095 atomic_set(&hw->vh264_active, 0);
9096 if (vdec->parallel_dec == 1) {
9097 if (hw->mmu_enable == 0)
9098 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9099 else
9100 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9101 CORE_MASK_COMBINE);
9102 } else
9103 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9104
9105 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9106 if (vdec->parallel_dec == 1) {
9107 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9108 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9109 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9110 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9111 if (IS_VDEC_DW(hw)) {
9112 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9113 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9114 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9115 }
9116 }
9117 }
9118
9119 ammvdec_h264_mmu_release(hw);
9120 h264_free_hw_stru(&pdev->dev, (void *)hw);
9121 clk_adj_frame_count = 0;
9122
9123 return 0;
9124}
9125
9126/****************************************/
9127#ifdef CONFIG_PM
9128static int mh264_suspend(struct device *dev)
9129{
9130 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9131 return 0;
9132}
9133
9134static int mh264_resume(struct device *dev)
9135{
9136 amvdec_resume(to_platform_device(dev));
9137 return 0;
9138}
9139
9140static const struct dev_pm_ops mh264_pm_ops = {
9141 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9142};
9143#endif
9144
9145static struct platform_driver ammvdec_h264_driver = {
9146 .probe = ammvdec_h264_probe,
9147 .remove = ammvdec_h264_remove,
9148 .driver = {
9149 .name = DRIVER_NAME,
9150#ifdef CONFIG_PM
9151 .pm = &mh264_pm_ops,
9152#endif
9153 }
9154};
9155
9156static struct codec_profile_t ammvdec_h264_profile = {
9157 .name = "mh264",
9158 .profile = ""
9159};
9160
9161static struct mconfig hm264_configs[] = {
9162 MC_PU32("h264_debug_flag", &h264_debug_flag),
9163 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9164 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9165 MC_PU32("decode_timeout_val", &decode_timeout_val),
9166 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9167 MC_PU32("reference_buf_margin", &reference_buf_margin),
9168 MC_PU32("radr", &radr),
9169 MC_PU32("rval", &rval),
9170 MC_PU32("h264_debug_mask", &h264_debug_mask),
9171 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9172 MC_PI32("force_rate_streambase", &force_rate_streambase),
9173 MC_PI32("dec_control", &dec_control),
9174 MC_PI32("force_rate_framebase", &force_rate_framebase),
9175 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9176 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9177 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9178#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9179 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9180 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9181 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9182#endif
9183 MC_PU32("i_only_flag", &i_only_flag),
9184 MC_PU32("force_rate_streambase", &force_rate_streambase),
9185};
9186static struct mconfig_node hm264_node;
9187
9188
9189static int __init ammvdec_h264_driver_init_module(void)
9190{
9191 pr_info("ammvdec_h264 module init\n");
9192 if (platform_driver_register(&ammvdec_h264_driver)) {
9193 pr_info("failed to register ammvdec_h264 driver\n");
9194 return -ENODEV;
9195 }
9196
9197 if (vdec_is_support_4k()) {
9198 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9199 ammvdec_h264_profile.profile =
9200 "4k, dwrite, compressed";
9201 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9202 ammvdec_h264_profile.profile = "4k";
9203 }
9204 }
9205
9206 vcodec_profile_register(&ammvdec_h264_profile);
9207 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9208 "mh264", hm264_configs, CONFIG_FOR_RW);
9209 return 0;
9210}
9211
9212static void __exit ammvdec_h264_driver_remove_module(void)
9213{
9214 pr_info("ammvdec_h264 module remove.\n");
9215
9216 platform_driver_unregister(&ammvdec_h264_driver);
9217}
9218
9219/****************************************/
9220module_param(h264_debug_flag, uint, 0664);
9221MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9222
9223module_param(start_decode_buf_level, int, 0664);
9224MODULE_PARM_DESC(start_decode_buf_level,
9225 "\n ammvdec_h264 start_decode_buf_level\n");
9226
9227module_param(pre_decode_buf_level, int, 0664);
9228MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9229
9230module_param(fixed_frame_rate_mode, uint, 0664);
9231MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9232
9233module_param(decode_timeout_val, uint, 0664);
9234MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9235
9236module_param(errordata_timeout_val, uint, 0664);
9237MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9238
9239module_param(get_data_timeout_val, uint, 0664);
9240MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9241
9242module_param(frame_max_data_packet, uint, 0664);
9243MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9244
9245module_param(reorder_dpb_size_margin, uint, 0664);
9246MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9247
9248#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9249module_param(reorder_dpb_size_margin_dv, uint, 0664);
9250MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9251 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9252#endif
9253
9254module_param(reference_buf_margin, uint, 0664);
9255MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9256
9257#ifdef CONSTRAIN_MAX_BUF_NUM
9258module_param(run_ready_max_vf_only_num, uint, 0664);
9259MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9260
9261module_param(run_ready_display_q_num, uint, 0664);
9262MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9263
9264module_param(run_ready_max_buf_num, uint, 0664);
9265MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9266#endif
9267
9268module_param(radr, uint, 0664);
9269MODULE_PARM_DESC(radr, "\nradr\n");
9270
9271module_param(rval, uint, 0664);
9272MODULE_PARM_DESC(rval, "\nrval\n");
9273
9274module_param(h264_debug_mask, uint, 0664);
9275MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9276
9277module_param(h264_debug_cmd, uint, 0664);
9278MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9279
9280module_param(force_rate_streambase, int, 0664);
9281MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9282
9283module_param(dec_control, int, 0664);
9284MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9285
9286module_param(force_rate_framebase, int, 0664);
9287MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9288
9289module_param(force_disp_bufspec_num, int, 0664);
9290MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9291
9292module_param(V_BUF_ADDR_OFFSET, int, 0664);
9293MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9294
9295module_param(prefix_aux_buf_size, uint, 0664);
9296MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9297
9298module_param(suffix_aux_buf_size, uint, 0664);
9299MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9300
9301#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9302module_param(dv_toggle_prov_name, uint, 0664);
9303MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9304
9305module_param(dolby_meta_with_el, uint, 0664);
9306MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9307
9308#endif
9309
9310module_param(fast_output_enable, uint, 0664);
9311MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9312
9313module_param(error_proc_policy, uint, 0664);
9314MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9315
9316module_param(error_skip_count, uint, 0664);
9317MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9318
9319module_param(force_sliding_margin, uint, 0664);
9320MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9321
9322module_param(i_only_flag, uint, 0664);
9323MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9324
9325module_param(first_i_policy, uint, 0664);
9326MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9327
9328module_param(frmbase_cont_bitlevel, uint, 0664);
9329MODULE_PARM_DESC(frmbase_cont_bitlevel,
9330 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9331
9332module_param(frmbase_cont_bitlevel2, uint, 0664);
9333MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9334 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9335
9336module_param(udebug_flag, uint, 0664);
9337MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9338
9339module_param(udebug_pause_pos, uint, 0664);
9340MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9341
9342module_param(udebug_pause_val, uint, 0664);
9343MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9344
9345module_param(udebug_pause_decode_idx, uint, 0664);
9346MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9347
9348module_param(max_alloc_buf_count, uint, 0664);
9349MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9350
9351module_param(enable_itu_t35, uint, 0664);
9352MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9353
9354module_param(endian, uint, 0664);
9355MODULE_PARM_DESC(endian, "\nrval\n");
9356
9357module_param(mmu_enable, uint, 0664);
9358MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9359
9360module_param(force_enable_mmu, uint, 0664);
9361MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9362
9363module_param(again_threshold, uint, 0664);
9364MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9365
9366module_param(stream_mode_start_num, uint, 0664);
9367MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9368
9369/*
9370module_param(trigger_task, uint, 0664);
9371MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9372*/
9373module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9374
9375module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9376
9377module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9378
9379module_param_array(run_count, uint,
9380 &max_decode_instance_num, 0664);
9381
9382module_param_array(not_run_ready, uint,
9383 &max_decode_instance_num, 0664);
9384
9385module_param_array(input_empty, uint,
9386 &max_decode_instance_num, 0664);
9387
9388module_param_array(max_get_frame_interval, uint,
9389 &max_decode_instance_num, 0664);
9390
9391module_param_array(step, uint, &max_decode_instance_num, 0664);
9392
9393module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9394
9395module_param(disp_vframe_valve_level, uint, 0664);
9396MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9397
9398module_param(double_write_mode, uint, 0664);
9399MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9400
9401module_param(mem_map_mode, uint, 0664);
9402MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9403
9404module_param(without_display_mode, uint, 0664);
9405MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9406
9407
9408module_init(ammvdec_h264_driver_init_module);
9409module_exit(ammvdec_h264_driver_remove_module);
9410
9411MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9412MODULE_LICENSE("GPL");
9413
generated by cgit at 2024-05-17 10:21:49 (GMT)