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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: bcdb59a031ef7ef3115759ffc11876b8a1652c5f
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25
26#include <linux/amlogic/media/utils/amstream.h>
27#include <linux/amlogic/media/frame_sync/ptsserv.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/tsync.h>
34#include <linux/workqueue.h>
35#include <linux/dma-mapping.h>
36#include <linux/atomic.h>
37#include <linux/module.h>
38#include <linux/slab.h>
39#include <linux/dma-mapping.h>
40#include <linux/dma-contiguous.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43
44#include "../utils/vdec_input.h"
45#include <linux/amlogic/tee.h>
46
47#include <linux/amlogic/media/utils/vdec_reg.h>
48#include "../utils/vdec.h"
49#include "../utils/amvdec.h"
50#include "../h264/vh264.h"
51#include "../../../stream_input/parser/streambuf.h"
52#include <linux/delay.h>
53#include <linux/amlogic/media/codec_mm/configs.h>
54#include "../utils/decoder_mmu_box.h"
55#include "../utils/decoder_bmmu_box.h"
56#include "../utils/firmware.h"
57#include <linux/amlogic/tee.h>
58
59#undef pr_info
60#define pr_info printk
61
62#define DEBUG_UCODE
63#define MEM_NAME "codec_m264"
64#define MULTI_INSTANCE_FRAMEWORK
65/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
66#include "h264_dpb.h"
67/* #define SEND_PARAM_WITH_REG */
68
69#define DRIVER_NAME "ammvdec_h264"
70#define MODULE_NAME "ammvdec_h264"
71#define DRIVER_HEADER_NAME "ammvdec_h264_header"
72
73#define CHECK_INTERVAL (HZ/100)
74
75#define SEI_ITU_DATA_SIZE (4*1024)
76
77#define RATE_MEASURE_NUM 8
78#define RATE_CORRECTION_THRESHOLD 5
79#define RATE_2397_FPS 4004 /* 23.97 */
80#define RATE_25_FPS 3840 /* 25 */
81#define RATE_2997_FPS 3203 /* 29.97 */
82#define DUR2PTS(x) ((x)*90/96)
83#define PTS2DUR(x) ((x)*96/90)
84#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
85#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
86
87#define FIX_FRAME_RATE_OFF 0
88#define FIX_FRAME_RATE_ON 1
89#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
90
91#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
92#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
93#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
94#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
95
96#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
97
98#define RATE_MEASURE_NUM 8
99#define RATE_CORRECTION_THRESHOLD 5
100#define RATE_24_FPS 4004 /* 23.97 */
101#define RATE_25_FPS 3840 /* 25 */
102#define DUR2PTS(x) ((x)*90/96)
103#define PTS2DUR(x) ((x)*96/90)
104#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
105#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
106
107#define H264_DEV_NUM 9
108
109#define H264_MMU
110static int mmu_enable;
111static int force_enable_mmu = 1;
112unsigned int h264_debug_flag; /* 0xa0000000; */
113unsigned int h264_debug_mask = 0xff;
114 /*
115 *h264_debug_cmd:
116 * 0x1xx, force decoder id of xx to be disconnected
117 */
118unsigned int h264_debug_cmd;
119static unsigned int dec_control;
120static unsigned int force_rate_streambase;
121static unsigned int force_rate_framebase;
122static unsigned int force_disp_bufspec_num;
123static unsigned int fixed_frame_rate_mode;
124static unsigned int error_recovery_mode_in;
125static int start_decode_buf_level = 0x8000;
126
127#ifdef CONFIG_AM_VDEC_DV
128/*to make reorder size difference of bl and el not too big*/
129static unsigned int reorder_dpb_size_margin_dv = 16;
130#endif
131static unsigned int reorder_dpb_size_margin = 6;
132static unsigned int reference_buf_margin = 4;
133
134static unsigned int max_alloc_buf_count;
135static unsigned int decode_timeout_val = 100;
136static unsigned int errordata_timeout_val = 50;
137static unsigned int get_data_timeout_val = 2000;
138static unsigned int frame_max_data_packet = 8;
139
140static unsigned int radr;
141static unsigned int rval;
142
143/*
144 udebug_flag:
145 bit 0, enable ucode print
146 bit 1, enable ucode detail print
147 bit 3, disable ucode watchdog
148 bit [31:16] not 0, pos to dump lmem
149 bit 2, pop bits to lmem
150 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
151*/
152static u32 udebug_flag;
153/*
154 when udebug_flag[1:0] is not 0
155 udebug_pause_pos not 0,
156 pause position
157*/
158static u32 udebug_pause_pos;
159/*
160 when udebug_flag[1:0] is not 0
161 and udebug_pause_pos is not 0,
162 pause only when DEBUG_REG2 is equal to this val
163*/
164static u32 udebug_pause_val;
165
166static u32 udebug_pause_decode_idx;
167
168static unsigned int disp_vframe_valve_level;
169
170static unsigned int max_decode_instance_num = H264_DEV_NUM;
171static unsigned int decode_frame_count[H264_DEV_NUM];
172static unsigned int display_frame_count[H264_DEV_NUM];
173static unsigned int max_process_time[H264_DEV_NUM];
174static unsigned int max_get_frame_interval[H264_DEV_NUM];
175static unsigned int run_count[H264_DEV_NUM];
176static unsigned int input_empty[H264_DEV_NUM];
177static unsigned int not_run_ready[H264_DEV_NUM];
178 /* bit[3:0]:
179 *0, run ; 1, pause; 3, step
180 *bit[4]:
181 *1, schedule run
182 */
183static unsigned int step[H264_DEV_NUM];
184
185#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
186static u32 prefix_aux_buf_size = (16 * 1024);
187static u32 suffix_aux_buf_size;
188
189#ifdef CONFIG_AM_VDEC_DV
190static u32 dv_toggle_prov_name;
191
192static u32 dolby_meta_with_el;
193#endif
194
195/*
196 bit[8]
197 0: use sys_info[bit 3]
198 not 0:use i_only_flag[7:0]
199 bit[7:0]:
200 bit 0, 1: only display I picture;
201 bit 1, 1: only decode I picture;
202*/
203static unsigned int i_only_flag;
204
205/*
206 error_proc_policy:
207 bit[0] send_error_frame_flag;
208 (valid when bit[31] is 1, otherwise use sysinfo)
209 bit[1] do not decode if config_decode_buf() fail
210 bit[2] force release buf if in deadlock
211 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
212 bit[4] check inactive of receiver
213 bit[5] reset buffmgr if in deadlock
214 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
215 bit[7] reset buffmgr if dpb error
216
217 bit[8] check total mbx/mby of decoded frame
218 bit[9] check ERROR_STATUS_REG
219 bit[10] check reference list
220 bit[11] mark error if dpb error
221
222 bit[12] i_only when error happen
223*/
224static unsigned int error_proc_policy = 0x1f94; /*0x1f14*/
225
226/*
227 error_skip_count:
228 bit[11:0] error skip frame count
229 bit[15:12] error skip i picture count
230*/
231static unsigned int error_skip_count = (0x2 << 12) | 0x40;
232
233static unsigned int force_sliding_margin;
234/*
235 bit[1:0]:
236 0, start playing from any frame
237 1, start playing from I frame
238 bit[15:8]: the count of skip frames after first I
239 2, start playing from second I frame (decode from the first I)
240 bit[15:8]: the max count of skip frames after first I
241 3, start playing from IDR
242*/
243static unsigned int first_i_policy = (15 << 8) | 2;
244
245/*
246 fast_output_enable:
247 bit [0], output frame if there is IDR in list
248 bit [1], output frame if the current poc is 1 big than the previous poc
249 bit [2], if even poc only, output frame ifthe cuurent poc
250 is 2 big than the previous poc
251*/
252static unsigned int fast_output_enable = 4;
253
254static unsigned int enable_itu_t35 = 1;
255
256static unsigned int frmbase_cont_bitlevel = 0x40;
257
258static unsigned int frmbase_cont_bitlevel2 = 0x1;
259
260static void vmh264_dump_state(struct vdec_s *vdec);
261
262#define is_in_parsing_state(status) \
263 ((status == H264_ACTION_SEARCH_HEAD) || \
264 ((status & 0xf0) == 0x80))
265
266#define is_interlace(frame) \
267 (frame->frame &&\
268 frame->top_field &&\
269 frame->bottom_field &&\
270 (!frame->frame->coded_frame))
271static inline bool close_to(int a, int b, int m)
272{
273 return (abs(a - b) < m) ? true : false;
274}
275
276#if 0
277#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
278#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
279#else
280#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
281#define h264_free_hw_stru(dev, hw) vfree(hw)
282#endif
283
284/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
285#define NV21
286/* #endif */
287
288/* 12M for L41 */
289#define MAX_DPB_BUFF_SIZE (12*1024*1024)
290#define DEFAULT_MEM_SIZE (32*1024*1024)
291#define AVIL_DPB_BUFF_SIZE 0x01ec2000
292
293#define DEF_BUF_START_ADDR 0x01000000
294#define mem_sps_base 0x011c3c00
295#define mem_pps_base 0x011cbc00
296/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
297u32 V_BUF_ADDR_OFFSET = 0x200000;
298#define DCAC_READ_MARGIN (64 * 1024)
299#define PIC_SINGLE_FRAME 0
300#define PIC_TOP_BOT_TOP 1
301#define PIC_BOT_TOP_BOT 2
302#define PIC_DOUBLE_FRAME 3
303#define PIC_TRIPLE_FRAME 4
304#define PIC_TOP_BOT 5
305#define PIC_BOT_TOP 6
306#define PIC_INVALID 7
307
308#define EXTEND_SAR 0xff
309
310#define BUFSPEC_POOL_SIZE 64
311#define VF_POOL_SIZE 64
312#define VF_POOL_NUM 2
313#define MAX_VF_BUF_NUM 27
314#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
315#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
316#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
317#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
318#define EXTIF_BUF_SIZE 0x10000
319
320#define HEADER_BUFFER_IDX(n) (n)
321#define VF_BUFFER_IDX(n) (n)
322
323
324#define PUT_INTERVAL (HZ/100)
325#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
326
327#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
328#define SWITCHING_STATE_OFF 0
329#define SWITCHING_STATE_ON_CMD3 1
330#define SWITCHING_STATE_ON_CMD1 2
331
332
333
334#define INCPTR(p) ptr_atomic_wrap_inc(&p)
335
336#define SLICE_TYPE_I 2
337#define SLICE_TYPE_P 5
338#define SLICE_TYPE_B 6
339
340struct buffer_spec_s {
341 /*
342 used:
343 -1, none allocated
344 0, allocated, free
345 1, used by dpb
346 2, in disp queue;
347 3, in disp queue, isolated,
348 do not use for dpb when vf_put;
349 4, to release
350 5, in disp queue, isolated (but not to release)
351 do not use for dpb when vf_put;
352 */
353 unsigned int used;
354 unsigned int info0;
355 unsigned int info1;
356 unsigned int info2;
357 unsigned int y_addr;
358 unsigned int u_addr;
359 unsigned int v_addr;
360
361 int y_canvas_index;
362 int u_canvas_index;
363 int v_canvas_index;
364
365#ifdef NV21
366 struct canvas_config_s canvas_config[2];
367#else
368 struct canvas_config_s canvas_config[3];
369#endif
370 unsigned long cma_alloc_addr;
371 unsigned int buf_adr;
372#ifdef H264_MMU
373 unsigned long alloc_header_addr;
374#endif
375 char *aux_data_buf;
376 int aux_data_size;
377#ifdef CONFIG_AM_VDEC_DV
378 unsigned char dv_enhance_exist;
379#endif
380 int canvas_pos;
381 int vf_ref;
382};
383
384#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
385#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
386#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
387
388#define spec2canvas(x) \
389 (((x)->v_canvas_index << 16) | \
390 ((x)->u_canvas_index << 8) | \
391 ((x)->y_canvas_index << 0))
392
393#define FRAME_INDEX(vf_index) (vf_index & 0xff)
394#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
395#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
396
397static struct vframe_s *vh264_vf_peek(void *);
398static struct vframe_s *vh264_vf_get(void *);
399static void vh264_vf_put(struct vframe_s *, void *);
400static int vh264_vf_states(struct vframe_states *states, void *);
401static int vh264_event_cb(int type, void *data, void *private_data);
402static void vh264_work(struct work_struct *work);
403static void vh264_notify_work(struct work_struct *work);
404static void user_data_push_work(struct work_struct *work);
405
406static const char vh264_dec_id[] = "vh264-dev";
407
408#define PROVIDER_NAME "vdec.h264"
409
410static const struct vframe_operations_s vf_provider_ops = {
411 .peek = vh264_vf_peek,
412 .get = vh264_vf_get,
413 .put = vh264_vf_put,
414 .event_cb = vh264_event_cb,
415 .vf_states = vh264_vf_states,
416};
417
418#define DEC_RESULT_NONE 0
419#define DEC_RESULT_DONE 1
420#define DEC_RESULT_AGAIN 2
421#define DEC_RESULT_CONFIG_PARAM 3
422#define DEC_RESULT_GET_DATA 4
423#define DEC_RESULT_GET_DATA_RETRY 5
424#define DEC_RESULT_ERROR 6
425#define DEC_RESULT_EOS 7
426#define DEC_RESULT_FORCE_EXIT 8
427
428/*
429 *static const char *dec_result_str[] = {
430 * "DEC_RESULT_NONE ",
431 * "DEC_RESULT_DONE ",
432 * "DEC_RESULT_AGAIN ",
433 * "DEC_RESULT_CONFIG_PARAM",
434 * "DEC_RESULT_GET_DATA ",
435 * "DEC_RESULT_GET_DA_RETRY",
436 * "DEC_RESULT_ERROR ",
437 *};
438 */
439
440#define UCODE_IP_ONLY 2
441#define UCODE_IP_ONLY_PARAM 1
442
443#define MC_OFFSET_HEADER 0x0000
444#define MC_OFFSET_DATA 0x1000
445#define MC_OFFSET_MMCO 0x2000
446#define MC_OFFSET_LIST 0x3000
447#define MC_OFFSET_SLICE 0x4000
448#define MC_OFFSET_MAIN 0x5000
449
450#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
451#define MC_SWAP_SIZE (4*SZ_1K)
452#define MODE_ERROR 0
453#define MODE_FULL 1
454
455#define DFS_HIGH_THEASHOLD 3
456
457#define INIT_FLAG_REG AV_SCRATCH_2
458#define HEAD_PADING_REG AV_SCRATCH_3
459#define UCODE_WATCHDOG_REG AV_SCRATCH_7
460#define LMEM_DUMP_ADR AV_SCRATCH_L
461#define DEBUG_REG1 AV_SCRATCH_M
462#define DEBUG_REG2 AV_SCRATCH_N
463#define FRAME_COUNTER_REG AV_SCRATCH_I
464#define RPM_CMD_REG AV_SCRATCH_A
465#define H264_DECODE_SIZE AV_SCRATCH_E
466#define H264_DECODE_MODE AV_SCRATCH_4
467#define H264_DECODE_SEQINFO AV_SCRATCH_5
468#define H264_AUX_ADR AV_SCRATCH_C
469#define H264_AUX_DATA_SIZE AV_SCRATCH_H
470
471#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
472#define DPB_STATUS_REG AV_SCRATCH_J
473#define ERROR_STATUS_REG AV_SCRATCH_9
474 /*
475 NAL_SEARCH_CTL: bit 0, enable itu_t35
476 NAL_SEARCH_CTL: bit 1, enable mmu
477 */
478#define NAL_SEARCH_CTL AV_SCRATCH_9
479#define MBY_MBX MB_MOTION_MODE /*0xc07*/
480
481#define DECODE_MODE_SINGLE 0x0
482#define DECODE_MODE_MULTI_FRAMEBASE 0x1
483#define DECODE_MODE_MULTI_STREAMBASE 0x2
484#define DECODE_MODE_MULTI_DVBAL 0x3
485#define DECODE_MODE_MULTI_DVENL 0x4
486static DEFINE_MUTEX(vmh264_mutex);
487
488struct vdec_h264_hw_s {
489 spinlock_t lock;
490 spinlock_t bufspec_lock;
491 int id;
492 struct platform_device *platform_dev;
493 unsigned long cma_alloc_addr;
494 /* struct page *collocate_cma_alloc_pages; */
495 unsigned long collocate_cma_alloc_addr;
496
497 u32 prefix_aux_size;
498 u32 suffix_aux_size;
499 void *aux_addr;
500 dma_addr_t aux_phy_addr;
501 /* buffer for storing one itu35 recored */
502 void *sei_itu_data_buf;
503 u32 sei_itu_data_len;
504
505 /* recycle buffer for user data storing all itu35 records */
506 void *sei_user_data_buffer;
507 u32 sei_user_data_wp;
508 int sei_poc;
509 struct work_struct user_data_work;
510 struct StorablePicture *last_dec_picture;
511
512 ulong lmem_addr;
513 dma_addr_t lmem_addr_remap;
514
515 void *bmmu_box;
516#ifdef H264_MMU
517 void *mmu_box;
518 void *frame_mmu_map_addr;
519 dma_addr_t frame_mmu_map_phy_addr;
520 u32 hevc_cur_buf_idx;
521 u32 losless_comp_body_size;
522 u32 losless_comp_body_size_sao;
523 u32 losless_comp_header_size;
524 u32 mc_buffer_size_u_v;
525 u32 mc_buffer_size_u_v_h;
526 u32 is_idr_frame;
527 u32 is_new_pic;
528 u32 frame_done;
529 u32 frame_busy;
530 unsigned long extif_addr;
531
532#endif
533
534 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
535 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
536
537 int cur_pool;
538 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
539 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
540 struct vframe_s switching_fense_vf;
541 struct h264_dpb_stru dpb;
542 u8 init_flag;
543 u8 has_i_frame;
544 u8 config_bufmgr_done;
545 u32 max_reference_size;
546 u32 decode_pic_count;
547 int start_search_pos;
548 struct vframe_s vframe_dummy;
549
550 unsigned char buffer_empty_flag;
551
552 u32 frame_width;
553 u32 frame_height;
554 u32 frame_dur;
555 u32 frame_prog;
556 u32 frame_packing_type;
557
558 struct vframe_chunk_s *chunk;
559
560 u32 stat;
561 unsigned long buf_start;
562 u32 buf_offset;
563 u32 buf_size;
564 /* u32 ucode_map_start; */
565 u32 pts_outside;
566 u32 sync_outside;
567 u32 vh264_ratio;
568 u32 vh264_rotation;
569 u32 use_idr_framerate;
570
571 u32 seq_info;
572 u32 seq_info2;
573 u32 video_signal_from_vui; /*to do .. */
574 u32 timing_info_present_flag;
575 u32 fixed_frame_rate_flag;
576 u32 iframe_count;
577 u32 aspect_ratio_info;
578 u32 num_units_in_tick;
579 u32 time_scale;
580 u32 h264_ar;
581 bool h264_first_valid_pts_ready;
582 u32 h264pts1;
583 u32 h264pts2;
584 u32 pts_duration;
585 u32 h264_pts_count;
586 u32 duration_from_pts_done;
587 u32 pts_unstable;
588 u32 last_checkout_pts;
589 u32 max_refer_buf;
590
591 s32 vh264_stream_switching_state;
592 struct vframe_s *p_last_vf;
593 u32 last_pts;
594 u32 last_pts_remainder;
595 u32 last_duration;
596 u32 last_mb_width, last_mb_height;
597 bool check_pts_discontinue;
598 bool pts_discontinue;
599 u32 wait_buffer_counter;
600 u32 first_offset;
601 u32 first_pts;
602 u64 first_pts64;
603 bool first_pts_cached;
604
605#if 0
606 void *sei_data_buffer;
607 dma_addr_t sei_data_buffer_phys;
608#endif
609
610 uint error_recovery_mode;
611 uint mb_total;
612 uint mb_width;
613 uint mb_height;
614
615 uint i_only;
616 int skip_frame_count;
617 bool no_poc_reorder_flag;
618 bool send_error_frame_flag;
619 dma_addr_t mc_dma_handle;
620 void *mc_cpu_addr;
621 int vh264_reset;
622
623 atomic_t vh264_active;
624
625 struct dec_sysinfo vh264_amstream_dec_info;
626
627 int dec_result;
628 struct work_struct work;
629 struct work_struct notify_work;
630
631 void (*vdec_cb)(struct vdec_s *, void *);
632 void *vdec_cb_arg;
633
634 struct timer_list check_timer;
635
636 /**/
637 unsigned int last_frame_time;
638 u32 vf_pre_count;
639 u32 vf_get_count;
640 u32 vf_put_count;
641
642 /* timeout handle */
643 unsigned long int start_process_time;
644 unsigned int last_mby_mbx;
645 unsigned int last_vld_level;
646 unsigned int decode_timeout_count;
647 unsigned int timeout_num;
648 unsigned int search_dataempty_num;
649 unsigned int decode_timeout_num;
650 unsigned int decode_dataempty_num;
651 unsigned int buffer_empty_recover_num;
652
653 unsigned get_data_count;
654 unsigned get_data_start_time;
655 /**/
656
657 /*log*/
658 unsigned int packet_write_success_count;
659 unsigned int packet_write_EAGAIN_count;
660 unsigned int packet_write_ENOMEM_count;
661 unsigned int packet_write_EFAULT_count;
662 unsigned int total_read_size_pre;
663 unsigned int total_read_size;
664 unsigned int frame_count_pre;
665#ifdef CONFIG_AM_VDEC_DV
666 u8 switch_dvlayer_flag;
667 u8 got_valid_nal;
668#endif
669 u8 eos;
670 u8 data_flag;
671 u32 no_error_count;
672 u32 no_error_i_count;
673 /*
674 NODISP_FLAG
675 */
676 u8 dec_flag;
677
678 u32 ucode_pause_pos;
679
680 u8 reset_bufmgr_flag;
681 u32 reset_bufmgr_count;
682 u32 cfg_param1;
683 u32 cfg_param2;
684 u32 cfg_param3;
685 u32 cfg_param4;
686 int valve_count;
687 struct firmware_s *fw;
688 struct firmware_s *fw_mmu;
689};
690
691
692static void h264_reconfig(struct vdec_h264_hw_s *hw);
693static void h264_reset_bufmgr(struct vdec_h264_hw_s *hw);
694static void vh264_local_init(struct vdec_h264_hw_s *hw);
695static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
696static int vh264_stop(struct vdec_h264_hw_s *hw);
697static s32 vh264_init(struct vdec_h264_hw_s *hw);
698static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
699 u32 index);
700static void release_aux_data(struct vdec_h264_hw_s *hw,
701 int buf_spec_num);
702#ifdef ERROR_HANDLE_TEST
703static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
704#endif
705
706#define H265_PUT_SAO_4K_SET 0x03
707#define H265_ABORT_SAO_4K_SET 0x04
708#define H265_ABORT_SAO_4K_SET_DONE 0x05
709
710#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
711#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
712#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
713#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
714#define HEVC_SAO_MMU_STATUS 0x3639
715#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
716
717#define HEVC_CM_HEADER_START_ADDR 0x3628
718#define HEVC_CM_BODY_START_ADDR 0x3626
719#define HEVC_CM_BODY_LENGTH 0x3627
720#define HEVC_CM_HEADER_LENGTH 0x3629
721#define HEVC_CM_HEADER_OFFSET 0x362b
722#define HEVC_SAO_CTRL9 0x362d
723#define HEVCD_MPP_DECOMP_CTL3 0x34c4
724#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
725
726
727#define H265_DW_NO_SCALE
728#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
729#define H265_LOSLESS_COMPRESS_MODE
730#define MAX_FRAME_4K_NUM 0x1200
731#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
732
733static int compute_losless_comp_body_size(int width,
734 int height, int bit_depth_10);
735static int compute_losless_comp_header_size(int width, int height);
736
737
738
739static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
740 int pic_width, int pic_height, u16 bit_depth,
741 unsigned int *mmu_index_adr) {
742 int cur_buf_idx;
743 int bit_depth_10 = (bit_depth != 0x00);
744 int picture_size;
745 u32 cur_mmu_4k_number;
746
747 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
748 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
749 picture_size = compute_losless_comp_body_size(pic_width,
750 pic_height, bit_depth_10);
751 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
752 dpb_print(DECODE_ID(hw),
753 PRINT_FLAG_MMU_DETAIL,
754 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
755 cur_buf_idx, picture_size, cur_mmu_4k_number);
756 return decoder_mmu_box_alloc_idx(
757 hw->mmu_box,
758 cur_buf_idx,
759 cur_mmu_4k_number,
760 mmu_index_adr);
761
762}
763
764static int compute_losless_comp_body_size(int width,
765 int height, int bit_depth_10)
766{
767 int width_x64;
768 int height_x32;
769 int bsize;
770
771 width_x64 = width + 63;
772 width_x64 >>= 6;
773
774 height_x32 = height + 31;
775 height_x32 >>= 5;
776
777#ifdef H264_MMU
778 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
779#else
780 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
781#endif
782 return bsize;
783}
784
785static int compute_losless_comp_header_size(int width, int height)
786{
787 int width_x64;
788 int width_x128;
789 int height_x64;
790 int hsize;
791
792 width_x64 = width + 63;
793 width_x64 >>= 6;
794
795 width_x128 = width + 127;
796 width_x128 >>= 7;
797
798 height_x64 = height + 63;
799 height_x64 >>= 6;
800
801#ifdef H264_MMU
802 hsize = 128*width_x64*height_x64;
803#else
804 hsize = 32*width_x128*height_x64;
805#endif
806 return hsize;
807}
808
809static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw)
810{
811 int i, size;
812 u32 canvas_addr;
813 unsigned long maddr;
814 int num_buff = hw->dpb.mDPB.size;
815
816 canvas_addr = ANC0_CANVAS_ADDR;
817 for (i = 0; i < num_buff; i++)
818 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
819
820 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
821 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
822 for (i = 0; i < num_buff; i++) {
823 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
824 HEADER_BUFFER_IDX(i), size,
825 DRIVER_HEADER_NAME, &maddr) < 0) {
826 dpb_print(DECODE_ID(hw), 0,
827 "%s malloc compress header failed %d\n",
828 DRIVER_HEADER_NAME, i);
829 /*hw->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;*/
830 return;
831 }
832 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
833 hw->buffer_spec[i].alloc_header_addr = maddr;
834 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
835 "%s : canvas: %d axiaddr:%x size 0x%x\n",
836 __func__, i, (u32)maddr, size);
837 }
838 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
839
840 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
841 for (i = 0; i < 32; i++)
842 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
843 return;
844}
845static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
846{
847 u32 i;
848 u32 ref_canv;
849 struct Slice *pSlice = &(hw->dpb.mSlice);
850 /*REFLIST[0]*/
851 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
852 struct StorablePicture *ref = pSlice->listX[0][i];
853 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
854 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
855 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
856 (ref->buf_spec_num & 0x3f) << 8);
857 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
858 }
859 /*REFLIST[1]*/
860 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
861 struct StorablePicture *ref = pSlice->listX[1][i];
862 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
863 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
864 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
865 (ref->buf_spec_num & 0x3f) << 8);
866 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
867 }
868 return;
869}
870
871static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
872{
873 u32 rdata32;
874 u32 rdata32_2;
875 u32 slice_type;
876 struct StorablePicture *ref;
877 struct Slice *pSlice;
878 slice_type = hw->dpb.mSlice.slice_type;
879 pSlice = &(hw->dpb.mSlice);
880 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
881 if (slice_type == I_SLICE) {
882 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
883 return;
884 }
885 if (slice_type == B_SLICE) {
886 ref = pSlice->listX[0][0];
887 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
888 ((ref->buf_spec_num & 0x3f) << 8));
889 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
890 rdata32 = rdata32 & 0xffff;
891 rdata32 = rdata32 | (rdata32 << 16);
892 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
893
894 ref = pSlice->listX[1][0];
895 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
896 ((ref->buf_spec_num & 0x3f) << 8));
897 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
898 rdata32_2 = rdata32_2 & 0xffff;
899 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
900 if (rdata32 == rdata32_2) {
901 ref = pSlice->listX[1][1];
902 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
903 ((ref->buf_spec_num & 0x3f) << 8));
904 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
905 rdata32_2 = rdata32_2 & 0xffff;
906 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
907 }
908 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
909 } else { /*P-PIC*/
910 ref = pSlice->listX[0][0];
911 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
912 ((ref->buf_spec_num & 0x3f) << 8));
913 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
914 rdata32 = rdata32 & 0xffff;
915 rdata32 = rdata32 | (rdata32 << 16);
916 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
917
918 ref = pSlice->listX[0][1];
919 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
920 ((ref->buf_spec_num & 0x3f) << 8));
921 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
922 rdata32 = rdata32 & 0xffff;
923 rdata32 = rdata32 | (rdata32 << 16);
924 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
925 }
926 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
927 return;
928}
929
930static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
931 u32 width, u32 height) {
932 u32 data32;
933 u32 lcu_x_num, lcu_y_num;
934 u32 lcu_total;
935 u32 mc_buffer_size_u_v;
936 u32 mc_buffer_size_u_v_h;
937
938 lcu_x_num = (width + 15) >> 4;
939 lcu_y_num = (height + 15) >> 4;
940 lcu_total = lcu_x_num * lcu_y_num;
941
942 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
943 hw->mc_buffer_size_u_v_h =
944 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
945
946 hw->losless_comp_body_size = 0;
947
948 hw->losless_comp_body_size_sao =
949 compute_losless_comp_body_size(width, height, 0);
950 hw->losless_comp_header_size =
951 compute_losless_comp_header_size(width, height);
952
953 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
954 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
955
956 /* setup lcu_size = 16*/
957 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
958 /*pic_width/pic_height*/
959 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
960 (height & 0xffff) << 16 | (width & 0xffff));
961 /* bitdepth_luma = 8*/
962 /* bitdepth_chroma = 8*/
963 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
964
965#ifdef H265_LOSLESS_COMPRESS_MODE
966 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
967 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
968#else
969 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
970#endif
971 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
972 data32 &= (~0x30);
973 data32 |= (H265_MEM_MAP_MODE << 4);
974 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
975
976 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
977 (0x80 << 20) | (0x80 << 10) | (0xff));
978
979 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
980
981 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
982 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
983 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
984 /* ipp_enable*/
985 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
986
987 data32 = READ_VREG(HEVC_SAO_CTRL0);
988 data32 &= (~0xf);
989 data32 |= 0x4;
990 WRITE_VREG(HEVC_SAO_CTRL0, data32);
991 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
992 (width & 0xffff));
993 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
994
995 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
996 data32 = (lcu_x_num | lcu_y_num << 16);
997 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
998 data32 = (mc_buffer_size_u_v_h << 16) << 1;
999 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1000 data32 = (mc_buffer_size_u_v_h << 16);
1001 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1002
1003 data32 = READ_VREG(HEVC_SAO_CTRL1);
1004 data32 &= (~0x3000);
1005 data32 |= ((H265_MEM_MAP_MODE << 12) | 2); /* bit1 : 1 .disable dw */
1006 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1007
1008#ifdef H265_DW_NO_SCALE
1009 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1010#endif
1011
1012
1013#ifdef H265_LOSLESS_COMPRESS_MODE
1014 data32 = READ_VREG(HEVC_SAO_CTRL5);
1015 data32 |= (1<<9); /*8-bit smem-mode*/
1016 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1017
1018 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1019 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1020 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1021#endif
1022
1023#ifdef H265_LOSLESS_COMPRESS_MODE
1024 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1025 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1026#endif
1027
1028 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1029
1030 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1031
1032 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1033 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1034 return;
1035}
1036
1037static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1038 u32 is_new_pic, u32 is_idr)
1039{
1040 hw->is_new_pic = is_new_pic;
1041 hw->is_idr_frame = is_idr;
1042 return;
1043}
1044
1045static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1046 struct StorablePicture *pic) {
1047 long used_4k_num;
1048 u32 mc_y_adr;
1049 u32 mc_u_v_adr;
1050 /*u32 dw_y_adr;*/
1051 /*u32 dw_u_v_adr;*/
1052 u32 canvas_addr;
1053 int ret;
1054 if (hw->is_new_pic != 1)
1055 return;
1056
1057 if (hw->is_idr_frame) {
1058 /* William TBD */
1059 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1060 }
1061 if (hw->hevc_cur_buf_idx != 0xffff) {
1062 used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
1063 if (used_4k_num >= 0)
1064 dpb_print(DECODE_ID(hw),
1065 PRINT_FLAG_MMU_DETAIL,
1066 "release unused buf , used_4k_num %ld index %d\n",
1067 used_4k_num, hw->hevc_cur_buf_idx);
1068 decoder_mmu_box_free_idx_tail(
1069 hw->mmu_box,
1070 hw->hevc_cur_buf_idx,
1071 used_4k_num);
1072 hw->hevc_cur_buf_idx = 0xffff;
1073 }
1074
1075 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1076 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1077 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1078 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1079 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1080 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1081 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1082 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1083 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1084
1085 /*dw_y_adr = H265_DOUBLE_WRITE_YSTART_TEMP;*/
1086 /*dw_u_v_adr = H265_DOUBLE_WRITE_CSTART_TEMP;*/
1087#ifdef H265_LOSLESS_COMPRESS_MODE
1088 /*WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);*/
1089 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1090#ifdef H264_MMU
1091 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1092#else
1093 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1094 (mc_y_adr + hw->losless_comp_body_size));
1095#endif
1096#else
1097 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1098#endif
1099
1100#ifndef H265_LOSLESS_COMPRESS_MODE
1101 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1102#else
1103 /*WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);*/
1104#endif
1105
1106#ifndef LOSLESS_COMPRESS_MODE
1107/* WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);*/
1108/* WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr); */
1109#else
1110 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1111 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1112#endif
1113
1114 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1115 hw->frame_width, hw->frame_height, 0x0,
1116 hw->frame_mmu_map_addr);
1117 if (ret != 0) {
1118 dpb_print(DECODE_ID(hw),
1119 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1120 pic->buf_spec_num,
1121 ret);
1122 return;
1123 }
1124
1125 /*Reset SAO + Enable SAO slice_start*/
1126 WRITE_VREG(HEVC_SAO_INT_STATUS,
1127 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1128 WRITE_VREG(HEVC_SAO_INT_STATUS,
1129 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1130 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1131 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1132 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1133 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1134 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1135 hw->frame_busy = 1;
1136 return;
1137}
1138
1139
1140static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1141 u32 buf_spec_num) {
1142 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1143 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1144 dpb_print(DECODE_ID(hw),
1145 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1146 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1147 return;
1148}
1149
1150
1151static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1152{
1153 ulong timeout = jiffies + HZ;
1154 dpb_print(DECODE_ID(hw),
1155 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1156 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1157 if (time_after(jiffies, timeout)) {
1158 dpb_print(DECODE_ID(hw),
1159 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1160 break;
1161 }
1162 }
1163 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1164 hw->frame_done = 1;
1165 return;
1166}
1167
1168static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1169{
1170 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1171 if (p_H264_Dpb->mVideo.dec_picture) {
1172 release_picture(p_H264_Dpb,
1173 p_H264_Dpb->mVideo.dec_picture);
1174 p_H264_Dpb->mVideo.dec_picture = NULL;
1175 if (mmu_enable)
1176 hevc_set_frame_done(hw);
1177 }
1178}
1179
1180static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1181{
1182 ulong timeout = jiffies + HZ;
1183 dpb_print(DECODE_ID(hw),
1184 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1185 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1186 if (time_after(jiffies, timeout)) {
1187 dpb_print(DECODE_ID(hw),
1188 PRINT_FLAG_MMU_DETAIL,
1189 "hevc_sao_wait_done...wait timeout!\n");
1190 break;
1191 }
1192 }
1193 timeout = jiffies + HZ;
1194 if ((hw->frame_busy == 1) && (hw->frame_done == 1)) {
1195 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1196 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1197 H265_ABORT_SAO_4K_SET_DONE) {
1198 if (time_after(jiffies, timeout)) {
1199 dpb_print(DECODE_ID(hw),
1200 PRINT_FLAG_MMU_DETAIL,
1201 "wait h265_abort_sao_4k_set_done timeout!\n");
1202 break;
1203 }
1204 }
1205 hw->frame_busy = 0;
1206 hw->frame_done = 0;
1207 }
1208 return;
1209}
1210static void buf_spec_init(struct vdec_h264_hw_s *hw)
1211{
1212 int i;
1213 unsigned long flags;
1214 spin_lock_irqsave(&hw->bufspec_lock, flags);
1215 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1216 hw->buffer_spec[i].used = -1;
1217 hw->buffer_spec[i].canvas_pos = -1;
1218 }
1219 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1220}
1221
1222/*is active in buf management */
1223static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1224 int buf_spec_num)
1225{
1226 unsigned char ret = 0;
1227 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1228 hw->buffer_spec[buf_spec_num].used == 2 ||
1229 hw->buffer_spec[buf_spec_num].used == 3 ||
1230 hw->buffer_spec[buf_spec_num].used == 5)
1231 ret = 1;
1232 return ret;
1233}
1234
1235static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1236 int buf_spec_num)
1237{
1238 unsigned char ret = 0;
1239 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1240 hw->buffer_spec[buf_spec_num].used == 3 ||
1241 hw->buffer_spec[buf_spec_num].used == 5)
1242 ret = 1;
1243 return ret;
1244}
1245
1246static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1247{
1248 if (mmu_enable) {
1249 if (hw->buffer_spec[i].alloc_header_addr)
1250 return 0;
1251 else
1252 return -1;
1253 } else {
1254
1255 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1256 int addr;
1257 if (hw->buffer_spec[i].cma_alloc_addr)
1258 return 0;
1259
1260 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1261 PAGE_ALIGN(buf_size), DRIVER_NAME,
1262 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1263 hw->buffer_spec[i].cma_alloc_addr = 0;
1264 dpb_print(DECODE_ID(hw), 0,
1265 "%s, fail to alloc buf for bufspec%d, try later\n",
1266 __func__, i
1267 );
1268 return -1;
1269 }
1270 hw->buffer_spec[i].buf_adr =
1271 hw->buffer_spec[i].cma_alloc_addr;
1272 addr = hw->buffer_spec[i].buf_adr;
1273
1274
1275 hw->buffer_spec[i].y_addr = addr;
1276 addr += hw->mb_total << 8;
1277
1278 hw->buffer_spec[i].u_addr = addr;
1279 hw->buffer_spec[i].v_addr = addr;
1280 addr += hw->mb_total << 7;
1281
1282 hw->buffer_spec[i].canvas_config[0].phy_addr =
1283 hw->buffer_spec[i].y_addr;
1284 hw->buffer_spec[i].canvas_config[0].width =
1285 hw->mb_width << 4;
1286 hw->buffer_spec[i].canvas_config[0].height =
1287 hw->mb_height << 4;
1288 hw->buffer_spec[i].canvas_config[0].block_mode =
1289 CANVAS_BLKMODE_32X32;
1290
1291 hw->buffer_spec[i].canvas_config[1].phy_addr =
1292 hw->buffer_spec[i].u_addr;
1293 hw->buffer_spec[i].canvas_config[1].width =
1294 hw->mb_width << 4;
1295 hw->buffer_spec[i].canvas_config[1].height =
1296 hw->mb_height << 3;
1297 hw->buffer_spec[i].canvas_config[1].block_mode =
1298 CANVAS_BLKMODE_32X32;
1299 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1300 "%s, alloc buf for bufspec%d\n",
1301 __func__, i
1302 );
1303 }
1304 return 0;
1305}
1306
1307static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1308{
1309 canvas_config(hw->buffer_spec[i].
1310 y_canvas_index,
1311 hw->buffer_spec[i].y_addr,
1312 hw->mb_width << 4,
1313 hw->mb_height << 4,
1314 CANVAS_ADDR_NOWRAP,
1315 CANVAS_BLKMODE_32X32);
1316
1317 canvas_config(hw->buffer_spec[i].
1318 u_canvas_index,
1319 hw->buffer_spec[i].u_addr,
1320 hw->mb_width << 4,
1321 hw->mb_height << 3,
1322 CANVAS_ADDR_NOWRAP,
1323 CANVAS_BLKMODE_32X32);
1324 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1325 spec2canvas(&hw->buffer_spec[i]));
1326}
1327
1328int get_free_buf_idx(struct vdec_s *vdec)
1329{
1330 int i;
1331 unsigned long addr, flags;
1332 int index = -1;
1333 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
1334 int buf_total = BUFSPEC_POOL_SIZE;
1335 spin_lock_irqsave(&hw->bufspec_lock, flags);
1336 for (i = hw->start_search_pos; i < buf_total; i++) {
1337 if (mmu_enable)
1338 addr = hw->buffer_spec[i].alloc_header_addr;
1339 else
1340 addr = hw->buffer_spec[i].cma_alloc_addr;
1341 if (hw->buffer_spec[i].used == 0 && addr) {
1342 hw->buffer_spec[i].used = 1;
1343 hw->start_search_pos = i+1;
1344 index = i;
1345 break;
1346 }
1347 }
1348 if (index < 0) {
1349 for (i = 0; i < hw->start_search_pos; i++) {
1350 if (mmu_enable)
1351 addr = hw->buffer_spec[i].alloc_header_addr;
1352 else
1353 addr = hw->buffer_spec[i].cma_alloc_addr;
1354 if (hw->buffer_spec[i].used == 0 && addr) {
1355 hw->buffer_spec[i].used = 1;
1356 hw->start_search_pos = i+1;
1357 index = i;
1358 break;
1359 }
1360 }
1361 }
1362 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1363 if (hw->start_search_pos >= buf_total)
1364 hw->start_search_pos = 0;
1365 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
1366 "%s, buf_spec_num %d\n", __func__, index);
1367
1368 if (index < 0) {
1369 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1370 "%s fail\n", __func__);
1371 vmh264_dump_state(vdec);
1372 }
1373 return index;
1374}
1375
1376int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
1377{
1378 u32 cur_buf_idx;
1379 unsigned long flags;
1380 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
1381 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1382 "%s buf_spec_num %d used %d\n",
1383 __func__, buf_spec_num,
1384 hw->buffer_spec[buf_spec_num].used);
1385 if (buf_spec_num >= 0 &&
1386 buf_spec_num < BUFSPEC_POOL_SIZE
1387 ) {
1388 spin_lock_irqsave(&hw->bufspec_lock, flags);
1389 hw->buffer_spec[buf_spec_num].used = 0;
1390 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1391 if (mmu_enable) {
1392 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1393 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
1394 cur_buf_idx = cur_buf_idx&0xff;
1395 decoder_mmu_box_free_idx(hw->mmu_box, cur_buf_idx);
1396 }
1397 release_aux_data(hw, buf_spec_num);
1398 }
1399 return 0;
1400}
1401
1402static void config_buf_specs(struct vdec_s *vdec)
1403{
1404 int i, j;
1405 unsigned long flags;
1406 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
1407 spin_lock_irqsave(&hw->bufspec_lock, flags);
1408 for (i = 0, j = 0;
1409 j < hw->dpb.mDPB.size
1410 && i < BUFSPEC_POOL_SIZE;
1411 i++) {
1412 int canvas;
1413 if (hw->buffer_spec[i].used != -1)
1414 continue;
1415 canvas = vdec->get_canvas(j, 2);
1416 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
1417 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
1418 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
1419 hw->buffer_spec[i].used = 0;
1420
1421 hw->buffer_spec[i].canvas_pos = j;
1422
1423 /*pr_info("config canvas (%d) %x for bufspec %d\r\n",
1424 j, canvas, i);*/
1425 j++;
1426 }
1427 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1428}
1429
1430static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
1431 unsigned char release_all)
1432{
1433 int i;
1434 unsigned long flags;
1435 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1436 if (hw->buffer_spec[i].used == 4 ||
1437 release_all) {
1438 dpb_print(DECODE_ID(hw),
1439 PRINT_FLAG_DPB_DETAIL,
1440 "%s buf_spec_num %d\n",
1441 __func__, i
1442 );
1443 spin_lock_irqsave
1444 (&hw->bufspec_lock, flags);
1445 hw->buffer_spec[i].used = -1;
1446 spin_unlock_irqrestore
1447 (&hw->bufspec_lock, flags);
1448 release_aux_data(hw, i);
1449
1450 if (!mmu_enable) {
1451 if (hw->buffer_spec[i].cma_alloc_addr) {
1452 decoder_bmmu_box_free_idx(
1453 hw->bmmu_box,
1454 i);
1455 spin_lock_irqsave
1456 (&hw->bufspec_lock, flags);
1457 hw->buffer_spec[i].cma_alloc_addr = 0;
1458 hw->buffer_spec[i].buf_adr = 0;
1459 spin_unlock_irqrestore
1460 (&hw->bufspec_lock, flags);
1461 }
1462 } else {
1463 if (hw->buffer_spec[i].alloc_header_addr) {
1464 decoder_mmu_box_free_idx(
1465 hw->mmu_box,
1466 i);
1467 spin_lock_irqsave
1468 (&hw->bufspec_lock, flags);
1469 hw->buffer_spec[i].
1470 alloc_header_addr = 0;
1471 hw->buffer_spec[i].buf_adr = 0;
1472 spin_unlock_irqrestore
1473 (&hw->bufspec_lock, flags);
1474 }
1475 }
1476 }
1477 }
1478 return;
1479}
1480
1481unsigned char have_free_buf_spec(struct vdec_s *vdec)
1482{
1483 int i;
1484 unsigned long addr;
1485 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
1486 int canvas_pos_min = BUFSPEC_POOL_SIZE;
1487 int index = -1;
1488 int ret = 0;
1489 int allocated_count = 0;
1490 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1491 if (mmu_enable)
1492 addr = hw->buffer_spec[i].alloc_header_addr;
1493 else
1494 addr = hw->buffer_spec[i].cma_alloc_addr;
1495 if (hw->buffer_spec[i].used == 0) {
1496
1497 if (addr)
1498 return 1;
1499 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
1500 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
1501 index = i;
1502 }
1503 }
1504 if (addr)
1505 allocated_count++;
1506 }
1507 if (index >= 0) {
1508 mutex_lock(&vmh264_mutex);
1509 dealloc_buf_specs(hw, 0);
1510 if (max_alloc_buf_count == 0 ||
1511 allocated_count < max_alloc_buf_count) {
1512 if (alloc_one_buf_spec(hw, index) >= 0)
1513 ret = 1;
1514 }
1515 mutex_unlock(&vmh264_mutex);
1516 }
1517 return ret;
1518}
1519
1520static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
1521 int canvas_pos)
1522{
1523 int i;
1524 int j = 0;
1525 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1526 if (hw->buffer_spec[i].canvas_pos >= 0) {
1527 if (j == canvas_pos)
1528 return i;
1529 j++;
1530 }
1531 }
1532 return -1;
1533}
1534static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
1535 struct vframe_s *vf, int index)
1536{
1537 if (index < 0) {
1538 vf->mem_handle = NULL;
1539 vf->mem_head_handle = NULL;
1540 } else if (vf->type & VIDTYPE_SCATTER) {
1541 vf->mem_handle =
1542 decoder_mmu_box_get_mem_handle(
1543 hw->mmu_box, index);
1544 vf->mem_head_handle =
1545 decoder_bmmu_box_get_mem_handle(
1546 hw->bmmu_box, HEADER_BUFFER_IDX(index));
1547 } else {
1548 vf->mem_handle =
1549 decoder_bmmu_box_get_mem_handle(
1550 hw->bmmu_box, VF_BUFFER_IDX(index));
1551 /* vf->mem_head_handle =
1552 decoder_bmmu_box_get_mem_handle(
1553 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
1554 }
1555 return;
1556}
1557static int check_force_interlace(struct vdec_h264_hw_s *hw,
1558 struct FrameStore *frame)
1559{
1560 int bForceInterlace = 0;
1561
1562 if (frame->frame) {
1563 if (frame->frame->coded_frame
1564 && !frame->frame->frame_mbs_only_flag) {
1565 if (frame->frame->structure == FRAME)
1566 return 1;
1567 }
1568 }
1569
1570 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
1571 && (hw->frame_width == 1920)
1572 && (hw->frame_height >= 1080)
1573 && (hw->frame_dur == 3203)) {
1574 bForceInterlace = 1;
1575 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
1576 && (hw->frame_width == 720)
1577 && (hw->frame_height == 576)
1578 && (hw->frame_dur == 3840)) {
1579 bForceInterlace = 1;
1580 }
1581
1582 return bForceInterlace;
1583}
1584
1585int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
1586{
1587 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
1588 struct vframe_s *vf = NULL;
1589 int buffer_index = frame->buf_spec_num;
1590 int vf_count = 1;
1591 int i;
1592 int bForceInterlace = 0;
1593
1594 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
1595 dpb_print(DECODE_ID(hw), 0,
1596 "%s, buffer_index 0x%x is beyond range\n",
1597 __func__, buffer_index);
1598 return -1;
1599 }
1600 if (force_disp_bufspec_num & 0x100) {
1601 /*recycle directly*/
1602 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
1603 hw->buffer_spec[frame->buf_spec_num].used != 5)
1604 set_frame_output_flag(&hw->dpb, frame->index);
1605
1606 /*make pre_output not set*/
1607 return -1;
1608 }
1609 if (error_proc_policy & 0x1000) {
1610 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
1611 int error_skip_frame_count = error_skip_count & 0xfff;
1612 if (((hw->no_error_count < error_skip_frame_count)
1613 && (error_skip_i_count == 0 ||
1614 hw->no_error_i_count < error_skip_i_count))
1615 && (!(frame->data_flag & I_FLAG)))
1616 frame->data_flag |= ERROR_FLAG;
1617 }
1618 if ((frame->data_flag & NODISP_FLAG) ||
1619 (frame->data_flag & NULL_FLAG) ||
1620 ((!hw->send_error_frame_flag) &&
1621 (frame->data_flag & ERROR_FLAG)) ||
1622 ((hw->i_only & 0x1) &&
1623 (!(frame->data_flag & I_FLAG)))
1624 ) {
1625 set_frame_output_flag(&hw->dpb, frame->index);
1626 return -1;
1627 }
1628 display_frame_count[DECODE_ID(hw)]++;
1629
1630 if (dpb_is_debug(DECODE_ID(hw),
1631 PRINT_FLAG_DPB_DETAIL)) {
1632 dpb_print(DECODE_ID(hw), 0,
1633 "%s, fs[%d] poc %d, buf_spec_num %d\n",
1634 __func__, frame->index, frame->poc,
1635 frame->buf_spec_num);
1636 print_pic_info(DECODE_ID(hw), "predis_frm",
1637 frame->frame, -1);
1638 print_pic_info(DECODE_ID(hw), "predis_top",
1639 frame->top_field, -1);
1640 print_pic_info(DECODE_ID(hw), "predis_bot",
1641 frame->bottom_field, -1);
1642 }
1643
1644 if (!is_interlace(frame))
1645 vf_count = 1;
1646 else
1647 vf_count = 2;
1648 bForceInterlace = check_force_interlace(hw, frame);
1649 if (bForceInterlace)
1650 vf_count = 2;
1651 hw->buffer_spec[buffer_index].vf_ref = 0;
1652 for (i = 0; i < vf_count; i++) {
1653 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
1654 vf == NULL) {
1655 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1656 "%s fatal error, no available buffer slot.\n",
1657 __func__);
1658 return -1;
1659 }
1660 vf->duration_pulldown = 0;
1661 vf->pts = frame->pts;
1662 vf->pts_us64 = frame->pts64;
1663 vf->index = VF_INDEX(frame->index, buffer_index);
1664 if (mmu_enable) {
1665 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
1666 vf->type |= VIDTYPE_SCATTER;
1667 vf->bitdepth =
1668 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
1669 vf->bitdepth |= BITDEPTH_SAVING_MODE;
1670 vf->compWidth = hw->frame_width;
1671 vf->compHeight = hw->frame_height;
1672 vf->compHeadAddr =
1673 hw->buffer_spec[buffer_index].alloc_header_addr;
1674 vf->compBodyAddr = 0;
1675 vf->canvas0Addr = vf->canvas1Addr = 0;
1676 } else {
1677 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
1678 VIDTYPE_VIU_NV21;
1679 vf->canvas0Addr = vf->canvas1Addr =
1680 spec2canvas(&hw->buffer_spec[buffer_index]);
1681 }
1682 set_frame_info(hw, vf, buffer_index);
1683 vf->flag = 0;
1684 if (frame->data_flag & I_FLAG)
1685 vf->flag |= VFRAME_FLAG_SYNCFRAME;
1686 if (frame->data_flag & ERROR_FLAG)
1687 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
1688 update_vf_memhandle(hw, vf, buffer_index);
1689 hw->buffer_spec[buffer_index].used = 2;
1690 hw->buffer_spec[buffer_index].vf_ref++;
1691
1692 if (bForceInterlace || is_interlace(frame)) {
1693 vf->type =
1694 VIDTYPE_INTERLACE_FIRST |
1695 VIDTYPE_VIU_NV21;
1696
1697 if (bForceInterlace) {
1698 vf->type |= (i == 0 ?
1699 VIDTYPE_INTERLACE_TOP :
1700 VIDTYPE_INTERLACE_BOTTOM);
1701 if (i == 1) {
1702 vf->pts = 0;
1703 vf->pts_us64 = 0;
1704 }
1705 } else if (frame->top_field->poc <=
1706 frame->bottom_field->poc) /*top first*/
1707 vf->type |= (i == 0 ?
1708 VIDTYPE_INTERLACE_TOP :
1709 VIDTYPE_INTERLACE_BOTTOM);
1710 else
1711 vf->type |= (i == 0 ?
1712 VIDTYPE_INTERLACE_BOTTOM :
1713 VIDTYPE_INTERLACE_TOP);
1714 vf->duration = vf->duration/2;
1715 }
1716 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
1717 hw->vf_pre_count++;
1718 vf_notify_receiver(vdec->vf_provider_name,
1719 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
1720 }
1721
1722 return 0;
1723}
1724
1725/******************
1726 * Hardware config
1727 */
1728char *slice_type_name[] = {
1729 "P_SLICE ",
1730 "B_SLICE ",
1731 "I_SLICE ",
1732 "SP_SLICE",
1733 "SI_SLICE",
1734};
1735
1736char *picture_structure_name[] = {
1737 "FRAME",
1738 "TOP_FIELD",
1739 "BOTTOM_FIELD"
1740};
1741
1742void print_pic_info(int decindex, const char *info,
1743 struct StorablePicture *pic,
1744 int slice_type)
1745{
1746 if (pic)
1747 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
1748 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
1749 info,
1750 picture_structure_name[pic->structure],
1751 pic->coded_frame ? "Frame" : "Field",
1752 (slice_type < 0) ? "" : slice_type_name[slice_type],
1753 pic->mb_aff_frame_flag,
1754 pic->poc,
1755 pic->pic_num,
1756 pic->buf_spec_num,
1757 pic->data_flag);
1758}
1759
1760static void reset_process_time(struct vdec_h264_hw_s *hw)
1761{
1762 if (hw->start_process_time) {
1763 unsigned process_time =
1764 1000 * (jiffies - hw->start_process_time) / HZ;
1765 hw->start_process_time = 0;
1766 if (process_time > max_process_time[DECODE_ID(hw)])
1767 max_process_time[DECODE_ID(hw)] = process_time;
1768 }
1769}
1770
1771static void start_process_time(struct vdec_h264_hw_s *hw)
1772{
1773 hw->decode_timeout_count = 2;
1774 hw->start_process_time = jiffies;
1775}
1776
1777static void config_aux_buf(struct vdec_h264_hw_s *hw)
1778{
1779 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
1780 WRITE_VREG(H264_AUX_DATA_SIZE,
1781 ((hw->prefix_aux_size >> 4) << 16) |
1782 (hw->suffix_aux_size >> 4)
1783 );
1784}
1785
1786/*
1787* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
1788*/
1789static void set_aux_data(struct vdec_h264_hw_s *hw,
1790 struct StorablePicture *pic, unsigned char suffix_flag,
1791 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
1792{
1793 int i;
1794 unsigned short *aux_adr;
1795 unsigned size_reg_val =
1796 READ_VREG(H264_AUX_DATA_SIZE);
1797 unsigned aux_count = 0;
1798 int aux_size = 0;
1799 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
1800 if (pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
1801 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
1802 return;
1803
1804 if (suffix_flag) {
1805 aux_adr = (unsigned short *)
1806 (hw_buf->aux_addr +
1807 hw_buf->prefix_aux_size);
1808 aux_count =
1809 ((size_reg_val & 0xffff) << 4)
1810 >> 1;
1811 aux_size =
1812 hw_buf->suffix_aux_size;
1813 } else {
1814 aux_adr =
1815 (unsigned short *)hw_buf->aux_addr;
1816 aux_count =
1817 ((size_reg_val >> 16) << 4)
1818 >> 1;
1819 aux_size =
1820 hw_buf->prefix_aux_size;
1821 }
1822 if (dpb_is_debug(DECODE_ID(hw),
1823 PRINT_FLAG_DPB_DETAIL)) {
1824 dpb_print(DECODE_ID(hw), 0,
1825 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
1826 __func__, AUX_DATA_SIZE(pic),
1827 aux_count, suffix_flag, dv_meta_flag);
1828 }
1829 if (aux_size > 0 && aux_count > 0) {
1830 int heads_size = 0;
1831 int new_size;
1832 char *new_buf;
1833 for (i = 0; i < aux_count; i++) {
1834 unsigned char tag = aux_adr[i] >> 8;
1835 if (tag != 0 && tag != 0xff) {
1836 if (dv_meta_flag == 0)
1837 heads_size += 8;
1838 else if (dv_meta_flag == 1 && tag == 0x1)
1839 heads_size += 8;
1840 else if (dv_meta_flag == 2 && tag != 0x1)
1841 heads_size += 8;
1842 }
1843 }
1844 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
1845 new_buf = krealloc(AUX_DATA_BUF(pic),
1846 new_size,
1847 GFP_KERNEL);
1848 if (new_buf) {
1849 unsigned char valid_tag = 0;
1850 unsigned char *h =
1851 new_buf +
1852 AUX_DATA_SIZE(pic);
1853 unsigned char *p = h + 8;
1854 int len = 0;
1855 int padding_len = 0;
1856 AUX_DATA_BUF(pic) = new_buf;
1857 for (i = 0; i < aux_count; i += 4) {
1858 int ii;
1859 unsigned char tag = aux_adr[i + 3] >> 8;
1860 if (tag != 0 && tag != 0xff) {
1861 if (dv_meta_flag == 0)
1862 valid_tag = 1;
1863 else if (dv_meta_flag == 1
1864 && tag == 0x1)
1865 valid_tag = 1;
1866 else if (dv_meta_flag == 2
1867 && tag != 0x1)
1868 valid_tag = 1;
1869 else
1870 valid_tag = 0;
1871 if (valid_tag && len > 0) {
1872 AUX_DATA_SIZE(pic) +=
1873 (len + 8);
1874 h[0] =
1875 (len >> 24) & 0xff;
1876 h[1] =
1877 (len >> 16) & 0xff;
1878 h[2] =
1879 (len >> 8) & 0xff;
1880 h[3] =
1881 (len >> 0) & 0xff;
1882 h[6] =
1883 (padding_len >> 8)
1884 & 0xff;
1885 h[7] =
1886 (padding_len) & 0xff;
1887 h += (len + 8);
1888 p += 8;
1889 len = 0;
1890 padding_len = 0;
1891 }
1892 if (valid_tag) {
1893 h[4] = tag;
1894 h[5] = 0;
1895 h[6] = 0;
1896 h[7] = 0;
1897 }
1898 }
1899 if (valid_tag) {
1900 for (ii = 0; ii < 4; ii++) {
1901 unsigned short aa =
1902 aux_adr[i + 3
1903 - ii];
1904 *p = aa & 0xff;
1905 p++;
1906 len++;
1907 /*if ((aa >> 8) == 0xff)
1908 padding_len++;*/
1909 }
1910 }
1911 }
1912 if (len > 0) {
1913 AUX_DATA_SIZE(pic) += (len + 8);
1914 h[0] = (len >> 24) & 0xff;
1915 h[1] = (len >> 16) & 0xff;
1916 h[2] = (len >> 8) & 0xff;
1917 h[3] = (len >> 0) & 0xff;
1918 h[6] = (padding_len >> 8) & 0xff;
1919 h[7] = (padding_len) & 0xff;
1920 }
1921 if (dpb_is_debug(DECODE_ID(hw),
1922 PRINT_FLAG_DPB_DETAIL)) {
1923 dpb_print(DECODE_ID(hw), 0,
1924 "aux: (size %d) suffix_flag %d\n",
1925 AUX_DATA_SIZE(pic), suffix_flag);
1926 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
1927 dpb_print_cont(DECODE_ID(hw), 0,
1928 "%02x ", AUX_DATA_BUF(pic)[i]);
1929 if (((i + 1) & 0xf) == 0)
1930 dpb_print_cont(
1931 DECODE_ID(hw),
1932 0, "\n");
1933 }
1934 dpb_print_cont(DECODE_ID(hw),
1935 0, "\n");
1936 }
1937
1938 }
1939 }
1940
1941}
1942
1943static void release_aux_data(struct vdec_h264_hw_s *hw,
1944 int buf_spec_num)
1945{
1946 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
1947 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
1948 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
1949}
1950
1951static void dump_aux_buf(struct vdec_h264_hw_s *hw)
1952{
1953 int i;
1954 unsigned short *aux_adr =
1955 (unsigned short *)
1956 hw->aux_addr;
1957 unsigned aux_size =
1958 (READ_VREG(H264_AUX_DATA_SIZE)
1959 >> 16) << 4;
1960
1961 if (hw->prefix_aux_size > 0) {
1962 dpb_print(DECODE_ID(hw),
1963 0,
1964 "prefix aux: (size %d)\n",
1965 aux_size);
1966 for (i = 0; i <
1967 (aux_size >> 1); i++) {
1968 dpb_print_cont(DECODE_ID(hw),
1969 0,
1970 "%04x ",
1971 *(aux_adr + i));
1972 if (((i + 1) & 0xf)
1973 == 0)
1974 dpb_print_cont(
1975 DECODE_ID(hw),
1976 0, "\n");
1977 }
1978 }
1979 if (hw->suffix_aux_size > 0) {
1980 aux_adr = (unsigned short *)
1981 (hw->aux_addr +
1982 hw->prefix_aux_size);
1983 aux_size =
1984 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
1985 << 4;
1986 dpb_print(DECODE_ID(hw),
1987 0,
1988 "suffix aux: (size %d)\n",
1989 aux_size);
1990 for (i = 0; i <
1991 (aux_size >> 1); i++) {
1992 dpb_print_cont(DECODE_ID(hw),
1993 0,
1994 "%04x ", *(aux_adr + i));
1995 if (((i + 1) & 0xf) == 0)
1996 dpb_print_cont(DECODE_ID(hw),
1997 0, "\n");
1998 }
1999 }
2000}
2001
2002static void config_decode_mode(struct vdec_h264_hw_s *hw)
2003{
2004#ifdef CONFIG_AM_VDEC_DV
2005 struct vdec_s *vdec = hw_to_vdec(hw);
2006#endif
2007 if (input_frame_based(hw_to_vdec(hw)))
2008 WRITE_VREG(H264_DECODE_MODE,
2009 DECODE_MODE_MULTI_FRAMEBASE);
2010#ifdef CONFIG_AM_VDEC_DV
2011 else if (vdec->slave)
2012 WRITE_VREG(H264_DECODE_MODE,
2013 (hw->got_valid_nal << 8) |
2014 DECODE_MODE_MULTI_DVBAL);
2015 else if (vdec->master)
2016 WRITE_VREG(H264_DECODE_MODE,
2017 (hw->got_valid_nal << 8) |
2018 DECODE_MODE_MULTI_DVENL);
2019#endif
2020 else
2021 WRITE_VREG(H264_DECODE_MODE,
2022 DECODE_MODE_MULTI_STREAMBASE);
2023 WRITE_VREG(H264_DECODE_SEQINFO,
2024 hw->seq_info2);
2025 WRITE_VREG(HEAD_PADING_REG, 0);
2026
2027 if (hw->init_flag == 0)
2028 WRITE_VREG(INIT_FLAG_REG, 0);
2029 else
2030 WRITE_VREG(INIT_FLAG_REG, 1);
2031}
2032int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
2033{
2034 /* static int count = 0; */
2035 int ret = 0;
2036 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
2037 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
2038 unsigned int colocate_adr_offset;
2039 unsigned int val;
2040#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
2041 int colocate_buf_index;
2042#endif
2043#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
2044#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
2045#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
2046#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
2047
2048#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
2049/* bit 31:30 -- L1[0] picture coding structure,
2050 * 00 - top field, 01 - bottom field,
2051 * 10 - frame, 11 - mbaff frame
2052 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
2053 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
2054 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
2055 */
2056#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
2057
2058/* bit 15 -- flush co_mb_data to DDR -- W-Only
2059 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
2060 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
2061 * bit 9 -- soft_reset -- W-Only
2062 * bit 8 -- upgent
2063 * bit 7:2 -- h264_co_mb_mem_wr_addr
2064 * bit 1:0 -- h264_co_mb_info_wr_ptr
2065 */
2066#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
2067
2068 unsigned long canvas_adr;
2069 unsigned int ref_reg_val;
2070 unsigned int one_ref_cfg = 0;
2071 int h264_buffer_info_data_write_count;
2072 int i, j;
2073 unsigned int colocate_wr_adr;
2074 unsigned int colocate_rd_adr;
2075 unsigned char use_direct_8x8;
2076 int canvas_pos;
2077 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
2078 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
2079 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
2080 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
2081 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
2082
2083 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2084 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
2085 __func__, pic->pic_num, pic->poc, pic->frame_poc,
2086 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
2087 canvas_pos);
2088 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
2089
2090 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
2091 if (!mmu_enable) {
2092 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
2093 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
2094 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
2095 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
2096 } else
2097 hevc_sao_set_pic_buffer(hw, pic);
2098
2099 if (pic->mb_aff_frame_flag)
2100 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
2101 else if (pic->structure == TOP_FIELD)
2102 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
2103 else if (pic->structure == BOTTOM_FIELD)
2104 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
2105 else
2106 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
2107
2108 if (pic->bottom_poc < pic->top_poc)
2109 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
2110
2111 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
2112 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
2113 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
2114
2115 for (j = 0; j < hw->dpb.mDPB.size; j++) {
2116 int long_term_flag;
2117 i = get_buf_spec_by_canvas_pos(hw, j);
2118 if (i < 0)
2119 break;
2120 long_term_flag =
2121 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
2122 if (long_term_flag > 0) {
2123 if (long_term_flag & 0x1)
2124 hw->buffer_spec[i].info0 |= (1 << 4);
2125 else
2126 hw->buffer_spec[i].info0 &= ~(1 << 4);
2127
2128 if (long_term_flag & 0x2)
2129 hw->buffer_spec[i].info0 |= (1 << 5);
2130 else
2131 hw->buffer_spec[i].info0 &= ~(1 << 5);
2132 }
2133
2134 if (i == pic->buf_spec_num)
2135 WRITE_VREG(H264_BUFFER_INFO_DATA,
2136 hw->buffer_spec[i].info0 | 0xf);
2137 else
2138 WRITE_VREG(H264_BUFFER_INFO_DATA,
2139 hw->buffer_spec[i].info0);
2140 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
2141 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
2142 }
2143
2144 /* config reference buffer */
2145 if (mmu_enable) {
2146 hevc_mcr_config_mc_ref(hw);
2147 hevc_mcr_config_mcrcc(hw);
2148 }
2149
2150 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2151 "list0 size %d\n", pSlice->listXsize[0]);
2152 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
2153 ref_reg_val = 0;
2154 j = 0;
2155 h264_buffer_info_data_write_count = 0;
2156
2157 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
2158 /*ref list 0 */
2159 struct StorablePicture *ref = pSlice->listX[0][i];
2160 unsigned int cfg;
2161 /* bit[6:5] - frame/field info,
2162 * 01 - top, 10 - bottom, 11 - frame
2163 */
2164#ifdef ERROR_CHECK
2165 if (ref == NULL) {
2166 hw->data_flag |= ERROR_FLAG;
2167 return -1;
2168 }
2169 if (ref->data_flag & ERROR_FLAG)
2170 hw->data_flag |= ERROR_FLAG;
2171 if (ref->data_flag & NULL_FLAG)
2172 hw->data_flag |= NULL_FLAG;
2173#endif
2174 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
2175
2176 if (ref->structure == TOP_FIELD)
2177 cfg = 0x1;
2178 else if (ref->structure == BOTTOM_FIELD)
2179 cfg = 0x2;
2180 else /* FRAME */
2181 cfg = 0x3;
2182 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
2183 ref_reg_val <<= 8;
2184 ref_reg_val |= one_ref_cfg;
2185 j++;
2186
2187 if (j == 4) {
2188 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2189 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
2190 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
2191 h264_buffer_info_data_write_count++;
2192 j = 0;
2193 }
2194 print_pic_info(DECODE_ID(hw), "list0",
2195 pSlice->listX[0][i], -1);
2196 }
2197 if (j != 0) {
2198 while (j != 4) {
2199 ref_reg_val <<= 8;
2200 ref_reg_val |= one_ref_cfg;
2201 j++;
2202 }
2203 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2204 "H264_BUFFER_INFO_DATA: %x\n",
2205 ref_reg_val);
2206 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
2207 h264_buffer_info_data_write_count++;
2208 }
2209 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
2210 (one_ref_cfg << 8) | one_ref_cfg;
2211 for (i = h264_buffer_info_data_write_count; i < 8; i++)
2212 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
2213
2214 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2215 "list1 size %d\n", pSlice->listXsize[1]);
2216 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
2217 ref_reg_val = 0;
2218 j = 0;
2219
2220 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
2221 /* ref list 0 */
2222 struct StorablePicture *ref = pSlice->listX[1][i];
2223 unsigned int cfg;
2224 /* bit[6:5] - frame/field info,
2225 * 01 - top, 10 - bottom, 11 - frame
2226 */
2227#ifdef ERROR_CHECK
2228 if (ref == NULL) {
2229 hw->data_flag |= ERROR_FLAG;
2230 return -2;
2231 }
2232 if (ref->data_flag & ERROR_FLAG)
2233 hw->data_flag |= ERROR_FLAG;
2234 if (ref->data_flag & NULL_FLAG)
2235 hw->data_flag |= NULL_FLAG;
2236#endif
2237 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
2238 if (ref->structure == TOP_FIELD)
2239 cfg = 0x1;
2240 else if (ref->structure == BOTTOM_FIELD)
2241 cfg = 0x2;
2242 else /* FRAME */
2243 cfg = 0x3;
2244 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
2245 ref_reg_val <<= 8;
2246 ref_reg_val |= one_ref_cfg;
2247 j++;
2248
2249 if (j == 4) {
2250 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2251 "H264_BUFFER_INFO_DATA: %x\n",
2252 ref_reg_val);
2253 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
2254 j = 0;
2255 }
2256 print_pic_info(DECODE_ID(hw), "list1",
2257 pSlice->listX[1][i], -1);
2258 }
2259 if (j != 0) {
2260 while (j != 4) {
2261 ref_reg_val <<= 8;
2262 ref_reg_val |= one_ref_cfg;
2263 j++;
2264 }
2265 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2266 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
2267 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
2268 }
2269
2270 /* configure co-locate buffer */
2271 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
2272 ;
2273 if ((pSlice->mode_8x8_flags & 0x4) &&
2274 (pSlice->mode_8x8_flags & 0x2))
2275 use_direct_8x8 = 1;
2276 else
2277 use_direct_8x8 = 0;
2278
2279#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
2280 colocate_adr_offset =
2281 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
2282 ? 1 : 2) * 96;
2283 if (use_direct_8x8)
2284 colocate_adr_offset >>= 2;
2285
2286 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2287 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
2288 colocate_adr_offset, pSlice->first_mb_in_slice,
2289 colocate_adr_offset * pSlice->first_mb_in_slice);
2290
2291 colocate_adr_offset *= pSlice->first_mb_in_slice;
2292
2293 if ((pic->colocated_buf_index >= 0) &&
2294 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
2295 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
2296 ((p_H264_Dpb->colocated_buf_size *
2297 pic->colocated_buf_index)
2298 >> (use_direct_8x8 ? 2 : 0));
2299 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
2300 p_H264_Dpb->colocated_mv_addr_end) {
2301 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2302 "Error, colocate buf is not enough, index is %d\n",
2303 pic->colocated_buf_index);
2304 ret = -3;
2305 }
2306 val = colocate_wr_adr + colocate_adr_offset;
2307 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
2308 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2309 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
2310 val, pSlice->first_mb_in_slice, pic->structure,
2311 colocate_adr_offset, pSlice->mode_8x8_flags,
2312 p_H264_Dpb->colocated_buf_size);
2313 } else {
2314 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
2315 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2316 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
2317 }
2318#else
2319 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
2320 colocate_adr_offset =
2321 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
2322 if (use_direct_8x8)
2323 colocate_adr_offset >>= 2;
2324
2325 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2326 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
2327 colocate_adr_offset, pSlice->first_mb_in_slice,
2328 colocate_adr_offset * pSlice->first_mb_in_slice);
2329
2330 colocate_adr_offset *= pSlice->first_mb_in_slice;
2331
2332 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
2333 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
2334 (use_direct_8x8 ? 2 : 0));
2335
2336 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
2337 p_H264_Dpb->colocated_mv_addr_end) {
2338 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2339 "Error, colocate buf is not enough, col buf index is %d\n",
2340 colocate_buf_index);
2341 ret = -4;
2342 }
2343 val = colocate_wr_adr + colocate_adr_offset;
2344 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
2345 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2346 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
2347 val, pSlice->first_mb_in_slice, pic->structure,
2348 colocate_adr_offset, pSlice->mode_8x8_flags,
2349 p_H264_Dpb->colocated_buf_size);
2350#endif
2351 if (pSlice->listXsize[1] > 0) {
2352 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
2353 /* H264_CO_MB_RD_ADDR[bit 31:30],
2354 * original picture structure of L1[0],
2355 * 00 - top field, 01 - bottom field,
2356 * 10 - frame, 11 - mbaff frame
2357 */
2358 int l10_structure;
2359 int cur_colocate_ref_type;
2360 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
2361 * 0 - top, 1 - bot
2362 */
2363 unsigned int val;
2364#ifdef ERROR_CHECK
2365 if (colocate_pic == NULL) {
2366 hw->data_flag |= ERROR_FLAG;
2367 return -5;
2368 }
2369 if (colocate_pic->data_flag & ERROR_FLAG)
2370 hw->data_flag |= ERROR_FLAG;
2371 if (colocate_pic->data_flag & NULL_FLAG)
2372 hw->data_flag |= NULL_FLAG;
2373#endif
2374
2375 if (colocate_pic->mb_aff_frame_flag)
2376 l10_structure = 3;
2377 else {
2378 if (colocate_pic->coded_frame)
2379 l10_structure = 2;
2380 else
2381 l10_structure = (colocate_pic->structure ==
2382 BOTTOM_FIELD) ? 1 : 0;
2383 }
2384#if 0
2385 /*case0016, p16,
2386 *cur_colocate_ref_type should be configured base on current pic
2387 */
2388 if (pic->structure == FRAME &&
2389 pic->mb_aff_frame_flag)
2390 cur_colocate_ref_type = 0;
2391 else if (pic->structure == BOTTOM_FIELD)
2392 cur_colocate_ref_type = 1;
2393 else
2394 cur_colocate_ref_type = 0;
2395#else
2396 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2397 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
2398 pic->mb_aff_frame_flag,
2399 pic->structure,
2400 pic->coded_frame);
2401 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2402 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
2403 colocate_pic->mb_aff_frame_flag,
2404 colocate_pic->structure,
2405 colocate_pic->coded_frame);
2406 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
2407 cur_colocate_ref_type =
2408 (abs(pic->poc - colocate_pic->top_poc)
2409 < abs(pic->poc -
2410 colocate_pic->bottom_poc)) ? 0 : 1;
2411 } else
2412 cur_colocate_ref_type =
2413 (colocate_pic->structure
2414 == BOTTOM_FIELD) ? 1 : 0;
2415#endif
2416
2417#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
2418 if ((colocate_pic->colocated_buf_index >= 0) &&
2419 (colocate_pic->colocated_buf_index <
2420 p_H264_Dpb->colocated_buf_count)) {
2421 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
2422 ((p_H264_Dpb->colocated_buf_size *
2423 colocate_pic->colocated_buf_index)
2424 >> (use_direct_8x8 ? 2 : 0));
2425 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
2426 p_H264_Dpb->colocated_mv_addr_end) {
2427 dpb_print(DECODE_ID(hw),
2428 PRINT_FLAG_ERROR,
2429 "Error, colocate buf is not enough, index is %d\n",
2430 colocate_pic->colocated_buf_index);
2431 ret = -6;
2432 }
2433 /* bit 31:30 -- L1[0] picture coding structure,
2434 * 00 - top field, 01 - bottom field,
2435 * 10 - frame, 11 - mbaff frame
2436 * bit 29 - L1[0] top/bot for B field pciture,
2437 * 0 - top, 1 - bot
2438 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
2439 * -- only used for B Picture Direct mode
2440 * [2:0] will set to 3'b000
2441 */
2442 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
2443 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
2444 (l10_structure << 30) |
2445 (cur_colocate_ref_type << 29);
2446 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
2447 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2448 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
2449 colocate_pic->colocated_buf_index,
2450 val, colocate_rd_adr + colocate_adr_offset,
2451 colocate_pic->structure,
2452 colocate_pic->mb_aff_frame_flag);
2453 } else {
2454 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2455 "Error, reference pic has no colocated buf\n");
2456 ret = -7;
2457 }
2458#else
2459 colocate_buf_index =
2460 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
2461 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
2462 ((p_H264_Dpb->colocated_buf_size *
2463 colocate_buf_index)
2464 >> (use_direct_8x8 ? 2 : 0));
2465 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
2466 p_H264_Dpb->colocated_mv_addr_end) {
2467 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2468 "Error, colocate buf is not enough, col buf index is %d\n",
2469 colocate_buf_index);
2470 ret = -8;
2471 }
2472 /* bit 31:30 -- L1[0] picture coding structure,
2473 * 00 - top field, 01 - bottom field,
2474 * 10 - frame, 11 - mbaff frame
2475 * bit 29 - L1[0] top/bot for B field pciture,
2476 * 0 - top, 1 - bot
2477 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
2478 * -- only used for B Picture Direct mode
2479 * [2:0] will set to 3'b000
2480 */
2481 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
2482 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
2483 (l10_structure << 30) | (cur_colocate_ref_type << 29);
2484 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
2485 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
2486 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
2487 val, colocate_pic->structure,
2488 colocate_pic->mb_aff_frame_flag);
2489#endif
2490 }
2491 return ret;
2492}
2493
2494static int vh264_vf_states(struct vframe_states *states, void *op_arg)
2495{
2496 unsigned long flags;
2497 struct vdec_s *vdec = op_arg;
2498 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2499
2500 spin_lock_irqsave(&hw->lock, flags);
2501
2502 states->vf_pool_size = VF_POOL_SIZE;
2503 states->buf_free_num = kfifo_len(&hw->newframe_q);
2504 states->buf_avail_num = kfifo_len(&hw->display_q);
2505
2506 spin_unlock_irqrestore(&hw->lock, flags);
2507
2508 return 0;
2509}
2510
2511static struct vframe_s *vh264_vf_peek(void *op_arg)
2512{
2513 struct vframe_s *vf;
2514 struct vdec_s *vdec = op_arg;
2515 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2516
2517 if (!hw)
2518 return NULL;
2519
2520 if (force_disp_bufspec_num & 0x100) {
2521 if (force_disp_bufspec_num & 0x200)
2522 return NULL;
2523 return &hw->vframe_dummy;
2524 }
2525
2526 if (kfifo_peek(&hw->display_q, &vf))
2527 return vf;
2528
2529 return NULL;
2530}
2531
2532static struct vframe_s *vh264_vf_get(void *op_arg)
2533{
2534 struct vframe_s *vf;
2535 struct vdec_s *vdec = op_arg;
2536 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2537
2538 if (!hw)
2539 return NULL;
2540
2541 if (force_disp_bufspec_num & 0x100) {
2542 int buffer_index = force_disp_bufspec_num & 0xff;
2543 if (force_disp_bufspec_num & 0x200)
2544 return NULL;
2545
2546 vf = &hw->vframe_dummy;
2547 vf->duration_pulldown = 0;
2548 vf->pts = 0;
2549 vf->pts_us64 = 0;
2550 set_frame_info(hw, vf, buffer_index);
2551 vf->flag = 0;
2552 if (mmu_enable) {
2553 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2554 vf->type |= VIDTYPE_SCATTER;
2555 vf->bitdepth =
2556 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2557 vf->compWidth = hw->frame_width;
2558 vf->compHeight = hw->frame_height;
2559 vf->compHeadAddr =
2560 hw->buffer_spec[buffer_index].alloc_header_addr;
2561 vf->compBodyAddr = 0;
2562 vf->canvas0Addr = vf->canvas1Addr = 0;
2563 } else {
2564 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2565 VIDTYPE_VIU_NV21;
2566 vf->canvas0Addr = vf->canvas1Addr =
2567 spec2canvas(&hw->buffer_spec[buffer_index]);
2568 }
2569
2570 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
2571 hw->bmmu_box, buffer_index);*/
2572 update_vf_memhandle(hw, vf, buffer_index);
2573 force_disp_bufspec_num |= 0x200;
2574 return vf;
2575 }
2576
2577 if (kfifo_get(&hw->display_q, &vf)) {
2578 int time = jiffies;
2579 unsigned int frame_interval =
2580 1000*(time - hw->last_frame_time)/HZ;
2581 if (dpb_is_debug(DECODE_ID(hw),
2582 PRINT_FLAG_VDEC_STATUS)) {
2583 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
2584 int frame_index = FRAME_INDEX(vf->index);
2585 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2586 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
2587 __func__, BUFSPEC_INDEX(vf->index), vf,
2588 p_H264_Dpb->mFrameStore[frame_index].poc,
2589 vf->duration, vf->pts, frame_interval);
2590 }
2591 if (hw->last_frame_time > 0) {
2592 if (frame_interval >
2593 max_get_frame_interval[DECODE_ID(hw)])
2594 max_get_frame_interval[DECODE_ID(hw)]
2595 = frame_interval;
2596 }
2597 hw->last_frame_time = time;
2598 hw->vf_get_count++;
2599 return vf;
2600 }
2601
2602 return NULL;
2603}
2604
2605static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
2606{
2607 struct vdec_s *vdec = op_arg;
2608 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2609 int buf_spec_num;
2610 int frame_index;
2611 if (vf == (&hw->vframe_dummy))
2612 return;
2613 if (vf->index == -1) {
2614 dpb_print(DECODE_ID(hw), 0,
2615 "Warning: %s vf %p invalid index\r\n",
2616 __func__, vf);
2617 return;
2618 }
2619 frame_index = FRAME_INDEX(vf->index);
2620 buf_spec_num = BUFSPEC_INDEX(vf->index);
2621 if (frame_index < 0 ||
2622 frame_index >= DPB_SIZE_MAX ||
2623 buf_spec_num < 0 ||
2624 buf_spec_num >= BUFSPEC_POOL_SIZE) {
2625 dpb_print(DECODE_ID(hw), 0,
2626 "%s vf index 0x%x error\r\n",
2627 __func__, vf->index);
2628 return;
2629 }
2630 /*get_buf_spec_idx_by_canvas_config(hw,
2631 &vf->canvas0_config[0]);*/
2632 if (hw->buffer_spec[buf_spec_num].used == 2) {
2633 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
2634 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2635 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
2636 __func__, vf, frame_index,
2637 p_H264_Dpb->mFrameStore[frame_index].poc,
2638 buf_spec_num,
2639 hw->buffer_spec[buf_spec_num].used,
2640 hw->buffer_spec[buf_spec_num].vf_ref);
2641 hw->buffer_spec[buf_spec_num].vf_ref--;
2642 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
2643 set_frame_output_flag(&hw->dpb, frame_index);
2644 } else {
2645 unsigned long flags;
2646 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2647 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
2648 __func__, vf, buf_spec_num,
2649 hw->buffer_spec[buf_spec_num].used,
2650 hw->buffer_spec[buf_spec_num].vf_ref);
2651 spin_lock_irqsave(&hw->bufspec_lock, flags);
2652 hw->buffer_spec[buf_spec_num].vf_ref--;
2653 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
2654 if (hw->buffer_spec[buf_spec_num].used == 3)
2655 hw->buffer_spec[buf_spec_num].used = 4;
2656 else if (hw->buffer_spec[buf_spec_num].used == 5)
2657 hw->buffer_spec[buf_spec_num].used = 0;
2658 }
2659 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2660 }
2661
2662 hw->vf_put_count++;
2663 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
2664
2665#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
2666 if (hw->buffer_empty_flag)
2667 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
2668}
2669
2670static int vh264_event_cb(int type, void *data, void *op_arg)
2671{
2672 unsigned long flags;
2673 struct vdec_s *vdec = op_arg;
2674 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2675
2676 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
2677 struct provider_aux_req_s *req =
2678 (struct provider_aux_req_s *)data;
2679 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
2680 spin_lock_irqsave(&hw->lock, flags);
2681 req->aux_buf = NULL;
2682 req->aux_size = 0;
2683 if (buf_spec_num >= 0 &&
2684 buf_spec_num < BUFSPEC_POOL_SIZE &&
2685 is_buf_spec_in_disp_q(hw, buf_spec_num)
2686 ) {
2687 req->aux_buf =
2688 hw->buffer_spec[buf_spec_num].aux_data_buf;
2689 req->aux_size =
2690 hw->buffer_spec[buf_spec_num].aux_data_size;
2691#ifdef CONFIG_AM_VDEC_DV
2692 req->dv_enhance_exist =
2693 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
2694#else
2695 req->dv_enhance_exist = 0;
2696#endif
2697 }
2698 spin_unlock_irqrestore(&hw->lock, flags);
2699
2700 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2701 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
2702 __func__, type, buf_spec_num, req->aux_size);
2703 }
2704
2705 return 0;
2706}
2707
2708static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
2709 u32 index)
2710{
2711 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
2712 force_rate_framebase : force_rate_streambase;
2713 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2714 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
2715 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
2716
2717 vf->width = hw->frame_width;
2718 vf->height = hw->frame_height;
2719 if (force_rate) {
2720 if (force_rate == -1)
2721 vf->duration = 0;
2722 else
2723 vf->duration = 96000/force_rate;
2724 } else
2725 vf->duration = hw->frame_dur;
2726 vf->ratio_control =
2727 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
2728 DISP_RATIO_ASPECT_RATIO_BIT;
2729 vf->orientation = hw->vh264_rotation;
2730 if (mmu_enable)
2731 return;
2732 vf->canvas0Addr = vf->canvas1Addr = -1;
2733#ifdef NV21
2734 vf->plane_num = 2;
2735#else
2736 vf->plane_num = 3;
2737#endif
2738 vf->canvas0_config[0] = hw->buffer_spec[index].canvas_config[0];
2739 vf->canvas0_config[1] = hw->buffer_spec[index].canvas_config[1];
2740#ifndef NV21
2741 vf->canvas0_config[2] = hw->buffer_spec[index].canvas_config[2];
2742#endif
2743 vf->canvas1_config[0] = hw->buffer_spec[index].canvas_config[0];
2744 vf->canvas1_config[1] = hw->buffer_spec[index].canvas_config[1];
2745#ifndef NV21
2746 vf->canvas1_config[2] = hw->buffer_spec[index].canvas_config[2];
2747#endif
2748}
2749
2750static int get_max_dec_frame_buf_size(int level_idc,
2751 int max_reference_frame_num, int mb_width,
2752 int mb_height)
2753{
2754 int pic_size = mb_width * mb_height * 384;
2755
2756 int size = 0;
2757
2758 switch (level_idc) {
2759 case 9:
2760 size = 152064;
2761 break;
2762 case 10:
2763 size = 152064;
2764 break;
2765 case 11:
2766 size = 345600;
2767 break;
2768 case 12:
2769 size = 912384;
2770 break;
2771 case 13:
2772 size = 912384;
2773 break;
2774 case 20:
2775 size = 912384;
2776 break;
2777 case 21:
2778 size = 1824768;
2779 break;
2780 case 22:
2781 size = 3110400;
2782 break;
2783 case 30:
2784 size = 3110400;
2785 break;
2786 case 31:
2787 size = 6912000;
2788 break;
2789 case 32:
2790 size = 7864320;
2791 break;
2792 case 40:
2793 size = 12582912;
2794 break;
2795 case 41:
2796 size = 12582912;
2797 break;
2798 case 42:
2799 size = 13369344;
2800 break;
2801 case 50:
2802 size = 42393600;
2803 break;
2804 case 51:
2805 case 52:
2806 default:
2807 size = 70778880;
2808 break;
2809 }
2810
2811 size /= pic_size;
2812 size = size + 1; /* need one more buffer */
2813
2814 if (max_reference_frame_num > size)
2815 size = max_reference_frame_num;
2816
2817 return size;
2818}
2819
2820static int vh264_set_params(struct vdec_h264_hw_s *hw,
2821 u32 param1, u32 param2, u32 param3, u32 param4)
2822{
2823 int i, j;
2824 int mb_width, mb_total;
2825 int max_reference_size, level_idc;
2826 int mb_height;
2827 unsigned long flags;
2828 /*int mb_mv_byte;*/
2829 struct vdec_s *vdec = hw_to_vdec(hw);
2830 u32 seq_info2;
2831 int ret = 0;
2832 int active_buffer_spec_num;
2833 unsigned int buf_size;
2834 unsigned int frame_mbs_only_flag;
2835 unsigned int chroma_format_idc, chroma444;
2836 unsigned int crop_infor, crop_bottom, crop_right;
2837 unsigned int used_reorder_dpb_size_margin
2838 = reorder_dpb_size_margin;
2839#ifdef CONFIG_AM_VDEC_DV
2840 if (vdec->master || vdec->slave)
2841 used_reorder_dpb_size_margin =
2842 reorder_dpb_size_margin_dv;
2843#endif
2844 seq_info2 = param1;
2845 hw->seq_info = param2;
2846
2847 mb_width = seq_info2 & 0xff;
2848 mb_total = (seq_info2 >> 8) & 0xffff;
2849 if (!mb_width && mb_total) /*for 4k2k*/
2850 mb_width = 256;
2851 mb_height = mb_total/mb_width;
2852 if (mb_width > 0x110 ||
2853 mb_height > 0xa0 ||
2854 mb_width <= 0 ||
2855 mb_height <= 0) {
2856 dpb_print(DECODE_ID(hw), 0,
2857 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
2858 seq_info2,
2859 mb_width,
2860 mb_height);
2861 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
2862 (hw->dpb.mDPB.size<<16) |
2863 (hw->dpb.mDPB.size<<8));
2864 return 0;
2865 }
2866
2867 if (seq_info2 != 0 &&
2868 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
2869 hw->seq_info2 != 0
2870 ) /*picture size changed*/
2871 h264_reconfig(hw);
2872
2873 if (hw->config_bufmgr_done == 0) {
2874 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
2875 u32 reg_val;
2876 hw->cfg_param1 = param1;
2877 hw->cfg_param2 = param2;
2878 hw->cfg_param3 = param3;
2879 hw->cfg_param4 = param4;
2880
2881 hw->seq_info2 = seq_info2 & (~0x80000000);
2882 dpb_print(DECODE_ID(hw), 0,
2883 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
2884 seq_info2, hw->seq_info);
2885
2886 dpb_init_global(&hw->dpb,
2887 DECODE_ID(hw), 0, 0);
2888
2889 p_H264_Dpb->fast_output_enable = fast_output_enable;
2890 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
2891
2892#if 1
2893 /*crop*/
2894 /* AV_SCRATCH_2
2895 bit 15: frame_mbs_only_flag
2896 bit 13-14: chroma_format_idc */
2897 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
2898 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
2899 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
2900
2901 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
2902 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
2903 (2 - frame_mbs_only_flag) */
2904 crop_infor = param3;
2905 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
2906 crop_right = ((crop_infor >> 16) & 0xff)
2907 >> (2 - frame_mbs_only_flag);
2908
2909 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
2910 hw->frame_width = mb_width << 4;
2911 hw->frame_height = mb_height << 4;
2912 if (frame_mbs_only_flag) {
2913 hw->frame_height =
2914 hw->frame_height - (2 >> chroma444) *
2915 min(crop_bottom,
2916 (unsigned int)((8 << chroma444) - 1));
2917 hw->frame_width =
2918 hw->frame_width -
2919 (2 >> chroma444) * min(crop_right,
2920 (unsigned
2921 int)((8 << chroma444) - 1));
2922 } else {
2923 hw->frame_height =
2924 hw->frame_height - (4 >> chroma444) *
2925 min(crop_bottom,
2926 (unsigned int)((8 << chroma444)
2927 - 1));
2928 hw->frame_width =
2929 hw->frame_width -
2930 (4 >> chroma444) * min(crop_right,
2931 (unsigned int)((8 << chroma444) - 1));
2932 }
2933 dpb_print(DECODE_ID(hw), 0,
2934 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d, ",
2935 frame_mbs_only_flag, crop_bottom, hw->frame_height);
2936 dpb_print(DECODE_ID(hw), 0,
2937 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
2938 mb_height, crop_right,
2939 hw->frame_width, mb_width);
2940
2941 if (hw->frame_height == 1088)
2942 hw->frame_height = 1080;
2943#endif
2944
2945 mb_width = (mb_width+3) & 0xfffffffc;
2946 mb_height = (mb_height+3) & 0xfffffffc;
2947 mb_total = mb_width * mb_height;
2948 if (mmu_enable)
2949 hevc_mcr_sao_global_hw_init(hw,
2950 hw->frame_width, hw->frame_height);
2951
2952 reg_val = param4;
2953 level_idc = reg_val & 0xff;
2954 max_reference_size = (reg_val >> 8) & 0xff;
2955 pr_info("%d: mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
2956 DECODE_ID(hw), mb_height, mb_width, mb_total,
2957 level_idc, max_reference_size);
2958
2959 p_H264_Dpb->colocated_buf_size = mb_total * 96;
2960 hw->mb_total = mb_total;
2961 hw->mb_width = mb_width;
2962 hw->mb_height = mb_height;
2963
2964 hw->dpb.reorder_pic_num =
2965 get_max_dec_frame_buf_size(level_idc,
2966 max_reference_size, mb_width, mb_height);
2967 active_buffer_spec_num =
2968 hw->dpb.reorder_pic_num
2969 + used_reorder_dpb_size_margin;
2970 hw->max_reference_size =
2971 max_reference_size + reference_buf_margin;
2972
2973 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
2974 active_buffer_spec_num = MAX_VF_BUF_NUM;
2975 hw->dpb.reorder_pic_num = active_buffer_spec_num
2976 - used_reorder_dpb_size_margin;
2977 }
2978 hw->dpb.mDPB.size = active_buffer_spec_num;
2979 if (hw->max_reference_size > MAX_VF_BUF_NUM)
2980 hw->max_reference_size = MAX_VF_BUF_NUM;
2981 hw->dpb.max_reference_size = hw->max_reference_size;
2982
2983 if (hw->no_poc_reorder_flag)
2984 hw->dpb.reorder_pic_num = 1;
2985 pr_debug("%d: %s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
2986 DECODE_ID(hw), __func__, active_buffer_spec_num,
2987 hw->dpb.reorder_pic_num,
2988 hw->max_reference_size);
2989
2990 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
2991
2992 mutex_lock(&vmh264_mutex);
2993 if (!mmu_enable) {
2994 config_buf_specs(vdec);
2995 i = get_buf_spec_by_canvas_pos(hw, 0);
2996 if (alloc_one_buf_spec(hw, i) >= 0)
2997 config_decode_canvas(hw, i);
2998 else
2999 ret = -1;
3000 } else {
3001 spin_lock_irqsave(&hw->bufspec_lock, flags);
3002 for (i = 0, j = 0;
3003 j < active_buffer_spec_num
3004 && i < BUFSPEC_POOL_SIZE;
3005 i++) {
3006 if (hw->buffer_spec[i].used != -1)
3007 continue;
3008 hw->buffer_spec[i].used = 0;
3009 hw->buffer_spec[i].alloc_header_addr = 0;
3010 hw->buffer_spec[i].canvas_pos = j;
3011 j++;
3012 }
3013 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3014 hevc_mcr_config_canv2axitbl(hw);
3015 }
3016 mutex_unlock(&vmh264_mutex);
3017
3018#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3019 buf_size = PAGE_ALIGN(
3020 p_H264_Dpb->colocated_buf_size *
3021 active_buffer_spec_num);
3022#else
3023 buf_size = PAGE_ALIGN(
3024 p_H264_Dpb->colocated_buf_size *
3025 hw->max_reference_size);
3026#endif
3027
3028 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
3029 buf_size, DRIVER_NAME,
3030 &hw->collocate_cma_alloc_addr) < 0)
3031 return -1;
3032
3033 hw->dpb.colocated_mv_addr_start =
3034 hw->collocate_cma_alloc_addr;
3035#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3036 hw->dpb.colocated_mv_addr_end =
3037 hw->dpb.colocated_mv_addr_start +
3038 (p_H264_Dpb->colocated_buf_size *
3039 active_buffer_spec_num);
3040#else
3041 hw->dpb.colocated_mv_addr_end =
3042 hw->dpb.colocated_mv_addr_start +
3043 (p_H264_Dpb->colocated_buf_size *
3044 hw->max_reference_size);
3045#endif
3046 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3047 "callocate cma, %lx, %x\n",
3048 hw->collocate_cma_alloc_addr,
3049 hw->dpb.colocated_mv_addr_start);
3050
3051 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3052 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
3053 hw->dpb.colocated_mv_addr_start,
3054 hw->dpb.colocated_mv_addr_end);
3055 if (!mmu_enable) {
3056 mutex_lock(&vmh264_mutex);
3057 if (ret >= 0 && hw->decode_pic_count == 0) {
3058 /* h264_reconfig: alloc later*/
3059 for (j = 1; j < hw->dpb.mDPB.size; j++) {
3060 i = get_buf_spec_by_canvas_pos(hw, j);
3061 if (alloc_one_buf_spec(hw, i) < 0)
3062 break;
3063 config_decode_canvas(hw, i);
3064 }
3065 }
3066 mutex_unlock(&vmh264_mutex);
3067 }
3068
3069 hw->config_bufmgr_done = 1;
3070
3071 /*end of config_bufmgr_done */
3072 }
3073
3074 return ret;
3075}
3076
3077static void vui_config(struct vdec_h264_hw_s *hw)
3078{
3079 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3080 int aspect_ratio_info_present_flag, aspect_ratio_idc;
3081 /*time*/
3082 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
3083 hw->time_scale = p_H264_Dpb->time_scale;
3084 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
3085
3086 hw->fixed_frame_rate_flag = 0;
3087 if (hw->timing_info_present_flag) {
3088 hw->fixed_frame_rate_flag =
3089 p_H264_Dpb->fixed_frame_rate_flag;
3090
3091 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
3092 ((!hw->sync_outside) ||
3093 (!hw->frame_dur)))
3094 && hw->num_units_in_tick && hw->time_scale) {
3095 if (hw->use_idr_framerate ||
3096 hw->fixed_frame_rate_flag ||
3097 !hw->frame_dur ||
3098 !hw->duration_from_pts_done
3099 /*|| vh264_running*/) {
3100 u32 frame_dur_es =
3101 div_u64(96000ULL * 2 * hw->num_units_in_tick,
3102 hw->time_scale);
3103 if (hw->frame_dur != frame_dur_es) {
3104 hw->h264_first_valid_pts_ready = false;
3105 hw->h264pts1 = 0;
3106 hw->h264pts2 = 0;
3107 hw->h264_pts_count = 0;
3108 hw->duration_from_pts_done = 0;
3109 fixed_frame_rate_mode =
3110 FIX_FRAME_RATE_OFF;
3111 hw->pts_duration = 0;
3112 hw->frame_dur = frame_dur_es;
3113 schedule_work(&hw->notify_work);
3114 dpb_print(DECODE_ID(hw),
3115 PRINT_FLAG_DEC_DETAIL,
3116 "frame_dur %d from timing_info\n",
3117 hw->frame_dur);
3118 }
3119
3120 /*hack to avoid use ES frame duration when
3121 *it's half of the rate from system info
3122 * sometimes the encoder is given a wrong
3123 * frame rate but the system side information
3124 * is more reliable
3125 *if ((frame_dur * 2) != frame_dur_es) {
3126 * frame_dur = frame_dur_es;
3127 *}
3128 */
3129 }
3130 }
3131 } else {
3132 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3133 "H.264: timing_info not present\n");
3134 }
3135
3136 /*aspect ratio*/
3137 aspect_ratio_info_present_flag =
3138 p_H264_Dpb->vui_status & 0x1;
3139 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
3140
3141 if (aspect_ratio_info_present_flag) {
3142 if (aspect_ratio_idc == EXTEND_SAR) {
3143 hw->h264_ar =
3144 div_u64(256ULL *
3145 p_H264_Dpb->aspect_ratio_sar_height *
3146 hw->frame_height,
3147 p_H264_Dpb->aspect_ratio_sar_width *
3148 hw->frame_width);
3149 } else {
3150 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
3151 aspect_ratio_idc); */
3152
3153 switch (aspect_ratio_idc) {
3154 case 1:
3155 hw->h264_ar = 0x100 * hw->frame_height /
3156 hw->frame_width;
3157 break;
3158 case 2:
3159 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3160 (hw->frame_width * 12);
3161 break;
3162 case 3:
3163 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3164 (hw->frame_width * 10);
3165 break;
3166 case 4:
3167 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3168 (hw->frame_width * 16);
3169 break;
3170 case 5:
3171 hw->h264_ar = 0x100 * hw->frame_height * 33 /
3172 (hw->frame_width * 40);
3173 break;
3174 case 6:
3175 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3176 (hw->frame_width * 24);
3177 break;
3178 case 7:
3179 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3180 (hw->frame_width * 20);
3181 break;
3182 case 8:
3183 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3184 (hw->frame_width * 32);
3185 break;
3186 case 9:
3187 hw->h264_ar = 0x100 * hw->frame_height * 33 /
3188 (hw->frame_width * 80);
3189 break;
3190 case 10:
3191 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3192 (hw->frame_width * 18);
3193 break;
3194 case 11:
3195 hw->h264_ar = 0x100 * hw->frame_height * 11 /
3196 (hw->frame_width * 15);
3197 break;
3198 case 12:
3199 hw->h264_ar = 0x100 * hw->frame_height * 33 /
3200 (hw->frame_width * 64);
3201 break;
3202 case 13:
3203 hw->h264_ar = 0x100 * hw->frame_height * 99 /
3204 (hw->frame_width * 160);
3205 break;
3206 case 14:
3207 hw->h264_ar = 0x100 * hw->frame_height * 3 /
3208 (hw->frame_width * 4);
3209 break;
3210 case 15:
3211 hw->h264_ar = 0x100 * hw->frame_height * 2 /
3212 (hw->frame_width * 3);
3213 break;
3214 case 16:
3215 hw->h264_ar = 0x100 * hw->frame_height * 1 /
3216 (hw->frame_width * 2);
3217 break;
3218 default:
3219 if (hw->vh264_ratio >> 16) {
3220 hw->h264_ar = (hw->frame_height *
3221 (hw->vh264_ratio & 0xffff) *
3222 0x100 +
3223 ((hw->vh264_ratio >> 16) *
3224 hw->frame_width / 2)) /
3225 ((hw->vh264_ratio >> 16) *
3226 hw->frame_width);
3227 } else {
3228 hw->h264_ar = hw->frame_height * 0x100 /
3229 hw->frame_width;
3230 }
3231 break;
3232 }
3233 }
3234 } else {
3235 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3236 "v264dec: aspect_ratio not available from source\n");
3237 if (hw->vh264_ratio >> 16) {
3238 /* high 16 bit is width, low 16 bit is height */
3239 hw->h264_ar =
3240 ((hw->vh264_ratio & 0xffff) *
3241 hw->frame_height * 0x100 +
3242 (hw->vh264_ratio >> 16) *
3243 hw->frame_width / 2) /
3244 ((hw->vh264_ratio >> 16) *
3245 hw->frame_width);
3246 } else
3247 hw->h264_ar = hw->frame_height * 0x100 /
3248 hw->frame_width;
3249 }
3250
3251 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
3252 if (((hw->frame_dur == RATE_2397_FPS)
3253 && (dec_control
3254 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
3255 || ((RATE_2997_FPS ==
3256 hw->frame_dur) &&
3257 (dec_control &
3258 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
3259 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3260 "force fix frame rate\n");
3261 hw->fixed_frame_rate_flag = 0x40;
3262 }
3263 }
3264
3265 /*video_signal_from_vui: to do .. */
3266}
3267
3268static void bufmgr_recover(struct vdec_h264_hw_s *hw)
3269{
3270 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3271 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
3272 if (error_proc_policy & 0x20)
3273 hw->reset_bufmgr_flag = 1;
3274}
3275
3276static bool is_buffer_available(struct vdec_s *vdec)
3277{
3278 bool buffer_available = 1;
3279 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
3280 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3281 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
3282 if ((kfifo_len(&hw->newframe_q) <= 0) ||
3283 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
3284 ((p_H264_Dpb->mDPB.init_done) &&
3285 (p_H264_Dpb->mDPB.used_size == p_H264_Dpb->mDPB.size) &&
3286 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
3287 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3288 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
3289 __func__,
3290 kfifo_len(&hw->newframe_q),
3291 have_free_buf_spec(vdec),
3292 p_H264_Dpb->mDPB.init_done,
3293 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
3294 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
3295 );
3296 buffer_available = 0;
3297 if (dpb_is_debug(DECODE_ID(hw),
3298 DEBUG_DISABLE_RUNREADY_RMBUF))
3299 return buffer_available;
3300
3301 if ((error_proc_policy & 0x4) &&
3302 (error_proc_policy & 0x8)) {
3303 if ((kfifo_len(&hw->display_q) <= 0) &&
3304 (p_H264_Dpb->mDPB.used_size ==
3305 p_H264_Dpb->mDPB.size) &&
3306 (p_Dpb->ref_frames_in_buffer >
3307 (imax(
3308 1, p_Dpb->num_ref_frames)
3309 - p_Dpb->ltref_frames_in_buffer +
3310 force_sliding_margin)))
3311 bufmgr_recover(hw);
3312 else
3313 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
3314 } else if ((error_proc_policy & 0x4) &&
3315 (kfifo_len(&hw->display_q) <= 0) &&
3316 ((p_H264_Dpb->mDPB.used_size ==
3317 p_H264_Dpb->mDPB.size) ||
3318 (!have_free_buf_spec(vdec)))) {
3319 enum receviver_start_e state = RECEIVER_INACTIVE;
3320 if ((error_proc_policy & 0x10) &&
3321 vf_get_receiver(vdec->vf_provider_name)) {
3322 state =
3323 vf_notify_receiver(vdec->vf_provider_name,
3324 VFRAME_EVENT_PROVIDER_QUREY_STATE,
3325 NULL);
3326 if ((state == RECEIVER_STATE_NULL)
3327 || (state == RECEIVER_STATE_NONE))
3328 state = RECEIVER_INACTIVE;
3329 }
3330 if (state == RECEIVER_INACTIVE)
3331 bufmgr_recover(hw);
3332 else
3333 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
3334 } else if ((error_proc_policy & 0x8) &&
3335 (p_Dpb->ref_frames_in_buffer >
3336 (imax(
3337 1, p_Dpb->num_ref_frames)
3338 - p_Dpb->ltref_frames_in_buffer +
3339 force_sliding_margin)))
3340 bufmgr_recover(hw);
3341 else
3342 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
3343 }
3344
3345 return buffer_available;
3346}
3347
3348static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
3349{
3350 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3351 unsigned mby_mbx = READ_VREG(MBY_MBX);
3352 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
3353 unsigned decode_mb_count =
3354 (((mby_mbx & 0xff) + 1) *
3355 (((mby_mbx >> 8) & 0xff) + 1));
3356 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
3357 mb_total /= 2;
3358 if ((error_proc_policy & 0x100) &&
3359 decode_mb_count != mb_total)
3360 hw->data_flag |= ERROR_FLAG;
3361
3362 if ((error_proc_policy & 0x200) &&
3363 READ_VREG(ERROR_STATUS_REG) != 0)
3364 hw->data_flag |= ERROR_FLAG;
3365
3366 if (hw->data_flag & ERROR_FLAG) {
3367 dpb_print(DECODE_ID(hw), 0,
3368 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
3369 __func__,
3370 hw->seq_info2,
3371 mby_mbx,
3372 mb_total,
3373 decode_mb_count,
3374 READ_VREG(ERROR_STATUS_REG)
3375 );
3376
3377 }
3378}
3379
3380static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec)
3381{
3382 int i;
3383 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
3384 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3385 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
3386 u32 debug_tag;
3387
3388 if (dec_dpb_status == H264_CONFIG_REQUEST) {
3389 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
3390 reset_process_time(hw);
3391 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
3392 vdec_schedule_work(&hw->work);
3393 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
3394 int slice_header_process_status = 0;
3395 /*unsigned char is_idr;*/
3396 unsigned short *p = (unsigned short *)hw->lmem_addr;
3397 reset_process_time(hw);
3398
3399 if (input_frame_based(vdec) &&
3400 frmbase_cont_bitlevel2 != 0 &&
3401 READ_VREG(VIFF_BIT_CNT) <
3402 frmbase_cont_bitlevel2 &&
3403 hw->get_data_count >= 0x70000000) {
3404 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3405 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
3406 __func__,
3407 READ_VREG(VIFF_BIT_CNT));
3408
3409 goto empty_proc;
3410 }
3411
3412 dma_sync_single_for_cpu(
3413 amports_get_dma_device(),
3414 hw->lmem_addr_remap,
3415 PAGE_SIZE,
3416 DMA_FROM_DEVICE);
3417#if 0
3418 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
3419 if (!is_buffer_available(vdec)) {
3420 hw->buffer_empty_flag = 1;
3421 dpb_print(DECODE_ID(hw),
3422 PRINT_FLAG_UCODE_EVT,
3423 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
3424 __func__,
3425 kfifo_len(&hw->newframe_q),
3426 have_free_buf_spec(vdec),
3427 p_H264_Dpb->mDPB.init_done,
3428 p_H264_Dpb->mDPB.used_size,
3429 p_H264_Dpb->mDPB.size,
3430 is_there_unused_frame_from_dpb(
3431 &p_H264_Dpb->mDPB));
3432 return IRQ_HANDLED;
3433 }
3434 }
3435
3436 hw->buffer_empty_flag = 0;
3437#endif
3438#ifdef SEND_PARAM_WITH_REG
3439 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
3440 unsigned int data32;
3441
3442 do {
3443 data32 = READ_VREG(RPM_CMD_REG);
3444 /* printk("%x\n", data32); */
3445 } while ((data32&0x10000) == 0);
3446 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
3447 WRITE_VREG(RPM_CMD_REG, 0);
3448 /* printk("%x:%x\n", i,data32); */
3449 }
3450#else
3451 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
3452 int ii;
3453
3454 for (ii = 0; ii < 4; ii++) {
3455 p_H264_Dpb->dpb_param.l.data[i+ii] =
3456 p[i+3-ii];
3457 if (dpb_is_debug(DECODE_ID(hw),
3458 RRINT_FLAG_RPM)) {
3459 if (((i + ii) & 0xf) == 0)
3460 dpb_print(DECODE_ID(hw),
3461 0, "%04x:",
3462 i);
3463 dpb_print_cont(DECODE_ID(hw),
3464 0, "%04x ",
3465 p[i+3-ii]);
3466 if (((i + ii + 1) & 0xf) == 0)
3467 dpb_print_cont(
3468 DECODE_ID(hw),
3469 0, "\r\n");
3470 }
3471 }
3472 }
3473#endif
3474 if (hw->config_bufmgr_done == 0) {
3475 hw->dec_result = DEC_RESULT_DONE;
3476 vdec_schedule_work(&hw->work);
3477 dpb_print(DECODE_ID(hw),
3478 PRINT_FLAG_UCODE_EVT,
3479 "config_bufmgr not done, discard frame\n");
3480 return IRQ_HANDLED;
3481 } else if ((first_i_policy & 0x3) != 0) {
3482 unsigned char is_i_slice =
3483 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
3484 == I_Slice)
3485 ? 1 : 0;
3486 unsigned char is_idr =
3487 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
3488 == 5);
3489 if ((first_i_policy & 0x3) == 0x3)
3490 is_i_slice = is_idr;
3491 if (!is_i_slice) {
3492 if (hw->has_i_frame == 0) {
3493 amvdec_stop();
3494 hw->dec_result = DEC_RESULT_DONE;
3495 vdec_schedule_work(&hw->work);
3496 dpb_print(DECODE_ID(hw),
3497 PRINT_FLAG_UCODE_EVT,
3498 "has_i_frame is 0, discard none I(DR) frame\n");
3499 return IRQ_HANDLED;
3500 }
3501 } else {
3502 if (hw->skip_frame_count < 0 || is_idr) {
3503 /* second I */
3504 hw->dec_flag &= (~NODISP_FLAG);
3505 hw->skip_frame_count = 0;
3506 }
3507 if (hw->has_i_frame == 0 &&
3508 (!is_idr)) {
3509 int skip_count =
3510 (first_i_policy >> 8) & 0xff;
3511 /* first I (not IDR) */
3512 if ((first_i_policy & 0x3) == 2)
3513 hw->skip_frame_count =
3514 -1 - skip_count;
3515 else
3516 hw->skip_frame_count =
3517 skip_count;
3518 if (hw->skip_frame_count != 0)
3519 hw->dec_flag |= NODISP_FLAG;
3520 }
3521 }
3522 }
3523 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
3524 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
3525 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
3526 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
3527 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
3528 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
3529
3530 slice_header_process_status =
3531 h264_slice_header_process(p_H264_Dpb);
3532 if (mmu_enable)
3533 hevc_sao_set_slice_type(hw,
3534 slice_header_process_status,
3535 hw->dpb.mSlice.idr_flag);
3536 vui_config(hw);
3537
3538 if (p_H264_Dpb->mVideo.dec_picture) {
3539 int cfg_ret = 0;
3540 if (hw->sei_itu_data_len) {
3541 hw->sei_poc =
3542 p_H264_Dpb->mVideo.dec_picture->poc;
3543 schedule_work(&hw->user_data_work);
3544 }
3545 if (slice_header_process_status == 1) {
3546 /* for baseline , set fast_output mode */
3547 if (p_H264_Dpb->mSPS.profile_idc == BASELINE)
3548 p_H264_Dpb->fast_output_enable = 4;
3549 else
3550 p_H264_Dpb->fast_output_enable
3551 = fast_output_enable;
3552 hw->data_flag =
3553 (p_H264_Dpb->
3554 dpb_param.l.data[SLICE_TYPE]
3555 == I_Slice)
3556 ? I_FLAG : 0;
3557 if ((hw->i_only & 0x2) &&
3558 (!(hw->data_flag & I_FLAG))) {
3559 hw->data_flag = NULL_FLAG;
3560 goto pic_done_proc;
3561 }
3562 if ((p_H264_Dpb->
3563 dpb_param.dpb.NAL_info_mmco & 0x1f)
3564 == 5)
3565 hw->data_flag |= IDR_FLAG;
3566 dpb_print(DECODE_ID(hw),
3567 PRINT_FLAG_VDEC_STATUS,
3568 "==================> frame count %d to skip %d\n",
3569 hw->decode_pic_count+1,
3570 hw->skip_frame_count);
3571 }
3572 if (error_proc_policy & 0x400) {
3573 int ret = dpb_check_ref_list_error(p_H264_Dpb);
3574 if (ret != 0) {
3575 dpb_print(DECODE_ID(hw), 0,
3576 "reference list error %d frame count %d to skip %d\n",
3577 ret,
3578 hw->decode_pic_count+1,
3579 hw->skip_frame_count);
3580 hw->data_flag |= ERROR_FLAG;
3581 if ((error_proc_policy & 0x80)
3582 && ((hw->dec_flag &
3583 NODISP_FLAG) == 0))
3584 hw->reset_bufmgr_flag = 1;
3585 }
3586 }
3587 if ((error_proc_policy & 0x800)
3588 && p_H264_Dpb->dpb_error_flag != 0) {
3589 dpb_print(DECODE_ID(hw), 0,
3590 "dpb error %d\n",
3591 p_H264_Dpb->dpb_error_flag);
3592 hw->data_flag |= ERROR_FLAG;
3593 if ((error_proc_policy & 0x80)
3594 && ((hw->dec_flag & NODISP_FLAG) == 0))
3595 hw->reset_bufmgr_flag = 1;
3596 }
3597
3598 cfg_ret = config_decode_buf(hw,
3599 p_H264_Dpb->mVideo.dec_picture);
3600 if (cfg_ret < 0) {
3601 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3602 "config_decode_buf fail (%d)\n",
3603 cfg_ret);
3604 if (error_proc_policy & 0x2) {
3605 release_cur_decoding_buf(hw);
3606 /*hw->data_flag |= ERROR_FLAG;*/
3607 hw->dec_result = DEC_RESULT_DONE;
3608 vdec_schedule_work(&hw->work);
3609 return IRQ_HANDLED;
3610 } else
3611 hw->data_flag |= ERROR_FLAG;
3612 }
3613 }
3614
3615 if (slice_header_process_status == 1)
3616 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
3617 else
3618 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
3619 hw->last_mby_mbx = 0;
3620 hw->last_vld_level = 0;
3621 start_process_time(hw);
3622 } else if (dec_dpb_status == H264_PIC_DATA_DONE) {
3623pic_done_proc:
3624 reset_process_time(hw);
3625 if (p_H264_Dpb->mVideo.dec_picture) {
3626#ifdef CONFIG_AM_VDEC_DV
3627 DEL_EXIST(hw,
3628 p_H264_Dpb->mVideo.dec_picture) = 0;
3629 if (vdec->master) {
3630 struct vdec_h264_hw_s *hw_ba =
3631 (struct vdec_h264_hw_s *)
3632 vdec->master->private;
3633 if (hw_ba->last_dec_picture)
3634 DEL_EXIST(hw_ba,
3635 hw_ba->last_dec_picture)
3636 = 1;
3637 }
3638#endif
3639 if (hw->chunk) {
3640 p_H264_Dpb->mVideo.dec_picture->pts =
3641 hw->chunk->pts;
3642 p_H264_Dpb->mVideo.dec_picture->pts64 =
3643 hw->chunk->pts64;
3644#ifdef CONFIG_AM_VDEC_DV
3645 } else if (vdec->master) {
3646 /*dv enhance layer,
3647 do not checkout pts*/
3648 struct StorablePicture *pic =
3649 p_H264_Dpb->mVideo.dec_picture;
3650 pic->pts = 0;
3651 pic->pts64 = 0;
3652#endif
3653 } else {
3654 struct StorablePicture *pic =
3655 p_H264_Dpb->mVideo.dec_picture;
3656 u32 offset = pic->offset_delimiter_lo |
3657 (pic->offset_delimiter_hi << 16);
3658 if (pts_lookup_offset_us64(PTS_TYPE_VIDEO,
3659 offset, &pic->pts, 0, &pic->pts64)) {
3660 pic->pts = 0;
3661 pic->pts64 = 0;
3662 }
3663 }
3664 check_decoded_pic_error(hw);
3665#ifdef ERROR_HANDLE_TEST
3666 if ((hw->data_flag & ERROR_FLAG)
3667 && (error_proc_policy & 0x80)) {
3668 release_cur_decoding_buf(hw);
3669 h264_clear_dpb(hw);
3670 hw->dec_flag = 0;
3671 hw->data_flag = 0;
3672 hw->skip_frame_count = 0;
3673 hw->has_i_frame = 0;
3674 hw->no_error_count = 0xfff;
3675 hw->no_error_i_count = 0xf;
3676 } else
3677#endif
3678 store_picture_in_dpb(p_H264_Dpb,
3679 p_H264_Dpb->mVideo.dec_picture,
3680 hw->data_flag | hw->dec_flag);
3681 if (hw->data_flag & ERROR_FLAG) {
3682 hw->no_error_count = 0;
3683 hw->no_error_i_count = 0;
3684 } else {
3685 hw->no_error_count++;
3686 if (hw->data_flag & I_FLAG)
3687 hw->no_error_i_count++;
3688 }
3689 if (mmu_enable)
3690 hevc_set_unused_4k_buff_idx(hw,
3691 p_H264_Dpb->mVideo.
3692 dec_picture->buf_spec_num);
3693 bufmgr_post(p_H264_Dpb);
3694 hw->last_dec_picture = p_H264_Dpb->mVideo.dec_picture;
3695 p_H264_Dpb->mVideo.dec_picture = NULL;
3696 /* dump_dpb(&p_H264_Dpb->mDPB); */
3697 hw->has_i_frame = 1;
3698 if (mmu_enable)
3699 hevc_set_frame_done(hw);
3700 hw->decode_pic_count++;
3701 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
3702 if (hw->skip_frame_count > 0) {
3703 /*skip n frame after first I */
3704 hw->skip_frame_count--;
3705 if (hw->skip_frame_count == 0)
3706 hw->dec_flag &= (~NODISP_FLAG);
3707 } else if (hw->skip_frame_count < -1) {
3708 /*skip n frame after first I until second I */
3709 hw->skip_frame_count++;
3710 if (hw->skip_frame_count == -1)
3711 hw->dec_flag &= (~NODISP_FLAG);
3712 }
3713 }
3714 if (input_frame_based(vdec) &&
3715 frmbase_cont_bitlevel != 0 &&
3716 READ_VREG(VIFF_BIT_CNT) >
3717 frmbase_cont_bitlevel) {
3718 /*handle the case: multi pictures in one packet*/
3719 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3720 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
3721 __func__,
3722 hw->decode_pic_count,
3723 READ_VREG(VIFF_BIT_CNT));
3724 /*do not DEC_RESULT_GET_DATA*/
3725 hw->get_data_count = 0x7fffffff;
3726 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
3727 decode_frame_count[DECODE_ID(hw)]++;
3728 start_process_time(hw);
3729 return IRQ_HANDLED;
3730 }
3731 amvdec_stop();
3732 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3733 "%s %s decode slice count %d\n",
3734 __func__,
3735 (dec_dpb_status == H264_PIC_DATA_DONE) ?
3736 "H264_PIC_DATA_DONE" :
3737 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
3738 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
3739 hw->decode_pic_count);
3740 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
3741 hw->dec_result = DEC_RESULT_DONE;
3742#ifdef CONFIG_AM_VDEC_DV
3743 if (vdec->slave &&
3744 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
3745 struct vdec_h264_hw_s *hw_el =
3746 (struct vdec_h264_hw_s *)(vdec->slave->private);
3747 hw_el->got_valid_nal = 0;
3748 hw->switch_dvlayer_flag = 1;
3749 } else if (vdec->master &&
3750 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
3751 struct vdec_h264_hw_s *hw_bl =
3752 (struct vdec_h264_hw_s *)(vdec->master->private);
3753 hw_bl->got_valid_nal = 0;
3754 hw->switch_dvlayer_flag = 1;
3755 } else {
3756 hw->switch_dvlayer_flag = 0;
3757 hw->got_valid_nal = 1;
3758 }
3759#endif
3760 vdec_schedule_work(&hw->work);
3761#ifdef CONFIG_AM_VDEC_DV
3762 } else if (
3763 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
3764 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
3765 goto pic_done_proc;
3766#endif
3767 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
3768 reset_process_time(hw);
3769 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
3770 dma_sync_single_for_cpu(
3771 amports_get_dma_device(),
3772 hw->aux_phy_addr,
3773 hw->prefix_aux_size + hw->suffix_aux_size,
3774 DMA_FROM_DEVICE);
3775 if (dpb_is_debug(DECODE_ID(hw),
3776 PRINT_FLAG_DPB_DETAIL))
3777 dump_aux_buf(hw);
3778#ifdef CONFIG_AM_VDEC_DV
3779 if (vdec->dolby_meta_with_el || vdec->slave) {
3780 if (hw->last_dec_picture)
3781 set_aux_data(hw, hw->last_dec_picture,
3782 0, 0, NULL);
3783 } else {
3784 if (vdec->master) {
3785 struct vdec_h264_hw_s *hw_bl =
3786 (struct vdec_h264_hw_s *)
3787 (vdec->master->private);
3788 if (hw_bl->last_dec_picture != NULL) {
3789 set_aux_data(hw_bl,
3790 hw_bl->last_dec_picture,
3791 0, 1, hw);
3792 }
3793 set_aux_data(hw,
3794 hw->last_dec_picture,
3795 0, 2, NULL);
3796 }
3797 }
3798#else
3799 if (hw->last_dec_picture)
3800 set_aux_data(hw,
3801 hw->last_dec_picture, 0, 0, NULL);
3802#endif
3803 }
3804#ifdef CONFIG_AM_VDEC_DV
3805 hw->switch_dvlayer_flag = 0;
3806 hw->got_valid_nal = 1;
3807#endif
3808 hw->dec_result = DEC_RESULT_DONE;
3809 vdec_schedule_work(&hw->work);
3810 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
3811 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
3812 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
3813 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
3814empty_proc:
3815 reset_process_time(hw);
3816
3817 release_cur_decoding_buf(hw);
3818
3819 if (input_frame_based(vdec) ||
3820 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
3821 if (h264_debug_flag &
3822 DISABLE_ERROR_HANDLE) {
3823 dpb_print(DECODE_ID(hw),
3824 PRINT_FLAG_ERROR,
3825 "%s decoding error, level 0x%x\n",
3826 __func__,
3827 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
3828 goto send_again;
3829 }
3830 amvdec_stop();
3831 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3832 "%s %s\n", __func__,
3833 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
3834 "H264_SEARCH_BUFEMPTY" :
3835 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
3836 "H264_DECODE_BUFEMPTY" :
3837 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
3838 "H264_DECODE_TIMEOUT" :
3839 "OTHER");
3840 hw->dec_result = DEC_RESULT_DONE;
3841
3842 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
3843 hw->search_dataempty_num++;
3844 else if (dec_dpb_status == H264_DECODE_TIMEOUT)
3845 hw->decode_timeout_num++;
3846 else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
3847 hw->decode_dataempty_num++;
3848
3849 hw->data_flag |= ERROR_FLAG;
3850
3851 vdec_schedule_work(&hw->work);
3852 } else {
3853 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
3854 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3855 "%s DEC_RESULT_AGAIN\n", __func__);
3856send_again:
3857 hw->dec_result = DEC_RESULT_AGAIN;
3858 vdec_schedule_work(&hw->work);
3859 }
3860 } else if (dec_dpb_status == H264_DATA_REQUEST) {
3861 reset_process_time(hw);
3862 if (input_frame_based(vdec)) {
3863 dpb_print(DECODE_ID(hw),
3864 PRINT_FLAG_VDEC_STATUS,
3865 "%s H264_DATA_REQUEST (%d)\n",
3866 __func__, hw->get_data_count);
3867 hw->dec_result = DEC_RESULT_GET_DATA;
3868 hw->get_data_start_time = jiffies;
3869 hw->get_data_count++;
3870 if (hw->get_data_count >= frame_max_data_packet)
3871 goto empty_proc;
3872 vdec_schedule_work(&hw->work);
3873 } else
3874 goto empty_proc;
3875 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
3876 dpb_print(DECODE_ID(hw), 0,
3877 "vmh264 decode oversize !!\n");
3878 release_cur_decoding_buf(hw);
3879 hw->data_flag |= ERROR_FLAG;
3880 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
3881 reset_process_time(hw);
3882 hw->dec_result = DEC_RESULT_DONE;
3883 vdec_schedule_work(&hw->work);
3884 return IRQ_HANDLED;
3885 }
3886
3887 if (READ_VREG(AV_SCRATCH_G) == 1) {
3888 hw->sei_itu_data_len =
3889 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
3890 if (hw->sei_itu_data_len > SEI_ITU_DATA_SIZE * 2) {
3891 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3892 "itu data size more than 4K: %d, discarded it\n",
3893 hw->sei_itu_data_len);
3894 hw->sei_itu_data_len = 0;
3895 }
3896
3897 if (hw->sei_itu_data_len != 0) {
3898 u8 *trans_data_buf;
3899 u8 *sei_data_buf;
3900 u32 temp;
3901 u32 *pswap_data;
3902
3903 dma_sync_single_for_cpu(
3904 amports_get_dma_device(),
3905 hw->aux_phy_addr,
3906 hw->prefix_aux_size + hw->suffix_aux_size,
3907 DMA_FROM_DEVICE);
3908#if 0
3909 dump_aux_buf(hw);
3910#endif
3911
3912 trans_data_buf = (u8 *)hw->aux_addr;
3913 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
3914 for (i = 0; i < hw->sei_itu_data_len/2; i++)
3915 sei_data_buf[i] = trans_data_buf[i*2];
3916 hw->sei_itu_data_len = hw->sei_itu_data_len / 2;
3917
3918 pswap_data = (u32 *)hw->sei_itu_data_buf;
3919 for (i = 0; i < hw->sei_itu_data_len/4; i = i+2) {
3920 temp = pswap_data[i];
3921 pswap_data[i] = pswap_data[i+1];
3922 pswap_data[i+1] = temp;
3923 }
3924 }
3925 WRITE_VREG(AV_SCRATCH_G, 0);
3926 return IRQ_HANDLED;
3927 }
3928
3929
3930 /* ucode debug */
3931 debug_tag = READ_VREG(DEBUG_REG1);
3932 if (debug_tag & 0x10000) {
3933 unsigned short *p = (unsigned short *)hw->lmem_addr;
3934
3935 dma_sync_single_for_cpu(
3936 amports_get_dma_device(),
3937 hw->lmem_addr_remap,
3938 PAGE_SIZE,
3939 DMA_FROM_DEVICE);
3940
3941 dpb_print(DECODE_ID(hw), 0,
3942 "LMEM<tag %x>:\n", debug_tag);
3943 for (i = 0; i < 0x400; i += 4) {
3944 int ii;
3945 if ((i & 0xf) == 0)
3946 dpb_print_cont(DECODE_ID(hw), 0,
3947 "%03x: ", i);
3948 for (ii = 0; ii < 4; ii++)
3949 dpb_print_cont(DECODE_ID(hw), 0,
3950 "%04x ", p[i+3-ii]);
3951 if (((i+ii) & 0xf) == 0)
3952 dpb_print_cont(DECODE_ID(hw), 0,
3953 "\n");
3954 }
3955 if (((udebug_pause_pos & 0xffff)
3956 == (debug_tag & 0xffff)) &&
3957 (udebug_pause_decode_idx == 0 ||
3958 udebug_pause_decode_idx ==
3959 hw->decode_pic_count) &&
3960 (udebug_pause_val == 0 ||
3961 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
3962 udebug_pause_pos &= 0xffff;
3963 hw->ucode_pause_pos = udebug_pause_pos;
3964 }
3965 else if (debug_tag & 0x20000)
3966 hw->ucode_pause_pos = 0xffffffff;
3967 if (hw->ucode_pause_pos)
3968 reset_process_time(hw);
3969 else
3970 WRITE_VREG(DEBUG_REG1, 0);
3971 } else if (debug_tag != 0) {
3972 dpb_print(DECODE_ID(hw), 0,
3973 "dbg%x: %x\n", debug_tag,
3974 READ_VREG(DEBUG_REG2));
3975 if (((udebug_pause_pos & 0xffff)
3976 == (debug_tag & 0xffff)) &&
3977 (udebug_pause_decode_idx == 0 ||
3978 udebug_pause_decode_idx ==
3979 hw->decode_pic_count) &&
3980 (udebug_pause_val == 0 ||
3981 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
3982 udebug_pause_pos &= 0xffff;
3983 hw->ucode_pause_pos = udebug_pause_pos;
3984 }
3985 if (hw->ucode_pause_pos)
3986 reset_process_time(hw);
3987 else
3988 WRITE_VREG(DEBUG_REG1, 0);
3989 }
3990 /**/
3991 return IRQ_HANDLED;
3992}
3993static irqreturn_t vh264_isr(struct vdec_s *vdec)
3994{
3995 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
3996 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3997
3998
3999 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
4000
4001 if (!hw) {
4002 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
4003 "decoder is not running\n");
4004 return IRQ_HANDLED;
4005 }
4006 if (hw->eos)
4007 return IRQ_HANDLED;
4008
4009 p_H264_Dpb->vdec = vdec;
4010 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
4011
4012 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
4013 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
4014 __func__,
4015 p_H264_Dpb->dec_dpb_status,
4016 READ_VREG(ERROR_STATUS_REG),
4017 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
4018 READ_VREG(VLD_MEM_VIFIFO_WP),
4019 READ_VREG(VLD_MEM_VIFIFO_RP),
4020 READ_VREG(VIFF_BIT_CNT),
4021 READ_VREG(MBY_MBX));
4022
4023 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
4024 if (mmu_enable)
4025 hevc_sao_wait_done(hw);
4026 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
4027 return IRQ_HANDLED;
4028 }
4029 return IRQ_WAKE_THREAD;
4030
4031}
4032
4033static void timeout_process(struct vdec_h264_hw_s *hw)
4034{
4035 hw->timeout_num++;
4036 amvdec_stop();
4037 dpb_print(DECODE_ID(hw),
4038 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
4039 release_cur_decoding_buf(hw);
4040 hw->dec_result = DEC_RESULT_DONE;
4041 hw->data_flag |= ERROR_FLAG;
4042 reset_process_time(hw);
4043 vdec_schedule_work(&hw->work);
4044}
4045
4046static void vmh264_dump_state(struct vdec_s *vdec)
4047{
4048 struct vdec_h264_hw_s *hw =
4049 (struct vdec_h264_hw_s *)(vdec->private);
4050 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4051 int i;
4052 dpb_print(DECODE_ID(hw), 0,
4053 "====== %s\n", __func__);
4054 dpb_print(DECODE_ID(hw), 0,
4055 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d\n",
4056 hw->frame_width,
4057 hw->frame_height,
4058 hw->dpb.reorder_pic_num,
4059 hw->dpb.mDPB.size,
4060 hw->max_reference_size
4061 );
4062
4063 dpb_print(DECODE_ID(hw), 0,
4064 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
4065 input_frame_based(vdec),
4066 hw->eos,
4067 hw->stat,
4068 hw->dec_result,
4069 decode_frame_count[DECODE_ID(hw)],
4070 display_frame_count[DECODE_ID(hw)],
4071 run_count[DECODE_ID(hw)],
4072 not_run_ready[DECODE_ID(hw)],
4073 input_empty[DECODE_ID(hw)],
4074 hw->reset_bufmgr_count
4075 );
4076
4077 if (vf_get_receiver(vdec->vf_provider_name)) {
4078 enum receviver_start_e state =
4079 vf_notify_receiver(vdec->vf_provider_name,
4080 VFRAME_EVENT_PROVIDER_QUREY_STATE,
4081 NULL);
4082 dpb_print(DECODE_ID(hw), 0,
4083 "\nreceiver(%s) state %d\n",
4084 vdec->vf_provider_name,
4085 state);
4086 }
4087
4088 dpb_print(DECODE_ID(hw), 0,
4089 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
4090 __func__,
4091 kfifo_len(&hw->newframe_q),
4092 VF_POOL_SIZE,
4093 kfifo_len(&hw->display_q),
4094 VF_POOL_SIZE,
4095 hw->vf_pre_count,
4096 hw->vf_get_count,
4097 hw->vf_put_count,
4098 have_free_buf_spec(vdec),
4099 p_H264_Dpb->mDPB.init_done,
4100 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
4101 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
4102 );
4103
4104 dump_dpb(&p_H264_Dpb->mDPB, 1);
4105 dump_pic(p_H264_Dpb);
4106 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
4107 if (hw->buffer_spec[i].used == -1)
4108 continue;
4109 dpb_print(DECODE_ID(hw), 0,
4110 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
4111 i, hw->buffer_spec[i].used,
4112 hw->buffer_spec[i].buf_adr,
4113 hw->buffer_spec[i].canvas_pos,
4114 hw->buffer_spec[i].vf_ref
4115 );
4116#ifdef CONFIG_AM_VDEC_DV
4117 dpb_print_cont(DECODE_ID(hw), 0,
4118 "dv_el_exist %d",
4119 hw->buffer_spec[i].dv_enhance_exist
4120 );
4121#endif
4122 dpb_print_cont(DECODE_ID(hw), 0, "\n");
4123 }
4124
4125 dpb_print(DECODE_ID(hw), 0,
4126 "DPB_STATUS_REG=0x%x\n",
4127 READ_VREG(DPB_STATUS_REG));
4128 dpb_print(DECODE_ID(hw), 0,
4129 "MPC_E=0x%x\n",
4130 READ_VREG(MPC_E));
4131 dpb_print(DECODE_ID(hw), 0,
4132 "H264_DECODE_MODE=0x%x\n",
4133 READ_VREG(H264_DECODE_MODE));
4134 dpb_print(DECODE_ID(hw), 0,
4135 "MBY_MBX=0x%x\n",
4136 READ_VREG(MBY_MBX));
4137 dpb_print(DECODE_ID(hw), 0,
4138 "H264_DECODE_SIZE=0x%x\n",
4139 READ_VREG(H264_DECODE_SIZE));
4140 dpb_print(DECODE_ID(hw), 0,
4141 "VIFF_BIT_CNT=0x%x\n",
4142 READ_VREG(VIFF_BIT_CNT));
4143 dpb_print(DECODE_ID(hw), 0,
4144 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
4145 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
4146 dpb_print(DECODE_ID(hw), 0,
4147 "VLD_MEM_VIFIFO_WP=0x%x\n",
4148 READ_VREG(VLD_MEM_VIFIFO_WP));
4149 dpb_print(DECODE_ID(hw), 0,
4150 "VLD_MEM_VIFIFO_RP=0x%x\n",
4151 READ_VREG(VLD_MEM_VIFIFO_RP));
4152 dpb_print(DECODE_ID(hw), 0,
4153 "PARSER_VIDEO_RP=0x%x\n",
4154 READ_PARSER_REG(PARSER_VIDEO_RP));
4155 dpb_print(DECODE_ID(hw), 0,
4156 "PARSER_VIDEO_WP=0x%x\n",
4157 READ_PARSER_REG(PARSER_VIDEO_WP));
4158
4159 if (input_frame_based(vdec) &&
4160 dpb_is_debug(DECODE_ID(hw),
4161 PRINT_FRAMEBASE_DATA)
4162 ) {
4163 int jj;
4164 if (hw->chunk && hw->chunk->block &&
4165 hw->chunk->size > 0) {
4166 u8 *data =
4167 ((u8 *)hw->chunk->block->start_virt) +
4168 hw->chunk->offset;
4169 dpb_print(DECODE_ID(hw), 0,
4170 "frame data size 0x%x\n",
4171 hw->chunk->size);
4172 for (jj = 0; jj < hw->chunk->size; jj++) {
4173 if ((jj & 0xf) == 0)
4174 dpb_print(DECODE_ID(hw),
4175 PRINT_FRAMEBASE_DATA,
4176 "%06x:", jj);
4177 dpb_print_cont(DECODE_ID(hw),
4178 PRINT_FRAMEBASE_DATA,
4179 "%02x ", data[jj]);
4180 if (((jj + 1) & 0xf) == 0)
4181 dpb_print_cont(DECODE_ID(hw),
4182 PRINT_FRAMEBASE_DATA,
4183 "\n");
4184 }
4185 }
4186 }
4187}
4188
4189
4190static void check_timer_func(unsigned long arg)
4191{
4192 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
4193 struct vdec_s *vdec = hw_to_vdec(hw);
4194 int error_skip_frame_count = error_skip_count & 0xfff;
4195 unsigned int timeout_val = decode_timeout_val;
4196 if (timeout_val != 0 &&
4197 hw->no_error_count < error_skip_frame_count)
4198 timeout_val = errordata_timeout_val;
4199 if ((h264_debug_cmd & 0x100) != 0 &&
4200 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
4201 hw->dec_result = DEC_RESULT_DONE;
4202 vdec_schedule_work(&hw->work);
4203 pr_info("vdec %d is forced to be disconnected\n",
4204 h264_debug_cmd & 0xff);
4205 h264_debug_cmd = 0;
4206 return;
4207 }
4208 if ((h264_debug_cmd & 0x200) != 0 &&
4209 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
4210 pr_debug("vdec %d is forced to reset bufmgr\n",
4211 h264_debug_cmd & 0xff);
4212 hw->reset_bufmgr_flag = 1;
4213 h264_debug_cmd = 0;
4214 return;
4215 }
4216
4217 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
4218 hw->dec_result = DEC_RESULT_FORCE_EXIT;
4219 vdec_schedule_work(&hw->work);
4220 pr_debug("vdec requested to be disconnected\n");
4221 return;
4222 }
4223
4224 if (radr != 0) {
4225 if (rval != 0) {
4226 WRITE_VREG(radr, rval);
4227 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
4228 } else
4229 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
4230 rval = 0;
4231 radr = 0;
4232 }
4233
4234 if ((input_frame_based(vdec) ||
4235 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) &&
4236 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
4237 (timeout_val > 0) &&
4238 (hw->start_process_time > 0) &&
4239 ((1000 * (jiffies - hw->start_process_time) / HZ)
4240 > timeout_val)
4241 ) {
4242 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
4243 u32 mby_mbx = READ_VREG(MBY_MBX);
4244 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
4245 (dpb_status == H264_ACTION_DECODE_SLICE)) {
4246 if (hw->last_mby_mbx == mby_mbx) {
4247 if (hw->decode_timeout_count > 0)
4248 hw->decode_timeout_count--;
4249 if (hw->decode_timeout_count == 0)
4250 timeout_process(hw);
4251 } else
4252 start_process_time(hw);
4253 } else if (is_in_parsing_state(dpb_status)) {
4254 if (hw->last_vld_level ==
4255 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
4256 if (hw->decode_timeout_count > 0)
4257 hw->decode_timeout_count--;
4258 if (hw->decode_timeout_count == 0)
4259 timeout_process(hw);
4260 }
4261 }
4262 hw->last_vld_level =
4263 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
4264 hw->last_mby_mbx = mby_mbx;
4265 }
4266
4267 if ((hw->ucode_pause_pos != 0) &&
4268 (hw->ucode_pause_pos != 0xffffffff) &&
4269 udebug_pause_pos != hw->ucode_pause_pos) {
4270 hw->ucode_pause_pos = 0;
4271 WRITE_VREG(DEBUG_REG1, 0);
4272 }
4273
4274 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
4275}
4276
4277static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
4278{
4279 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
4280 vstatus->frame_width = hw->frame_width;
4281 vstatus->frame_height = hw->frame_height;
4282 if (hw->frame_dur != 0)
4283 vstatus->frame_rate = 96000 / hw->frame_dur;
4284 else
4285 vstatus->frame_rate = -1;
4286 vstatus->error_count = 0;
4287 vstatus->status = hw->stat;
4288 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
4289 "%s-%02d", DRIVER_NAME, hw->id);
4290
4291 return 0;
4292}
4293
4294static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
4295{
4296 int i, j;
4297
4298 /* if (hw->init_flag == 0) { */
4299 if (h264_debug_flag & 0x40000000) {
4300 /* if (1) */
4301 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4302 "%s, reset register\n", __func__);
4303
4304 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
4305 ;
4306 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
4307 ; /* reg address is 0x350 */
4308
4309#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
4310 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
4311 WRITE_VREG(DOS_SW_RESET0, 0);
4312
4313 READ_VREG(DOS_SW_RESET0);
4314 READ_VREG(DOS_SW_RESET0);
4315 READ_VREG(DOS_SW_RESET0);
4316
4317 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
4318 WRITE_VREG(DOS_SW_RESET0, 0);
4319
4320 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
4321 WRITE_VREG(DOS_SW_RESET0, 0);
4322
4323 READ_VREG(DOS_SW_RESET0);
4324 READ_VREG(DOS_SW_RESET0);
4325 READ_VREG(DOS_SW_RESET0);
4326
4327#else
4328 WRITE_RESET_REG(RESET0_REGISTER,
4329 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
4330 READ_RESET_REG(RESET0_REGISTER);
4331 WRITE_RESET_REG(RESET0_REGISTER,
4332 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
4333
4334 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
4335#endif
4336 WRITE_VREG(POWER_CTL_VLD,
4337 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
4338 (1 << 9) | (1 << 6));
4339 } else {
4340 /* WRITE_VREG(POWER_CTL_VLD,
4341 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
4342 */
4343 WRITE_VREG(POWER_CTL_VLD,
4344 READ_VREG(POWER_CTL_VLD) |
4345 (0 << 10) | (1 << 9) | (1 << 6));
4346 }
4347 /* disable PSCALE for hardware sharing */
4348 WRITE_VREG(PSCALE_CTRL, 0);
4349
4350 /* clear mailbox interrupt */
4351 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
4352
4353 /* enable mailbox interrupt */
4354 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
4355
4356#ifdef NV21
4357 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
4358#endif
4359
4360#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
4361 /* pr_info("vh264 meson8 prot init\n"); */
4362 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
4363#endif
4364 if (hw->dpb.mDPB.size > 0) {
4365 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
4366 (hw->dpb.mDPB.size << 16) |
4367 (hw->dpb.mDPB.size << 8));
4368
4369 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4370 i = get_buf_spec_by_canvas_pos(hw, j);
4371 if (i < 0)
4372 break;
4373
4374 if (!mmu_enable &&
4375 hw->buffer_spec[i].cma_alloc_addr)
4376 config_decode_canvas(hw, i);
4377 }
4378 } else {
4379 WRITE_VREG(AV_SCRATCH_0, 0);
4380 WRITE_VREG(AV_SCRATCH_9, 0);
4381 }
4382
4383 if (hw->init_flag == 0)
4384 WRITE_VREG(DPB_STATUS_REG, 0);
4385 else
4386 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
4387
4388 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
4389 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
4390 if (!tee_enabled())
4391 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
4392
4393 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
4394 * error_recovery_mode : error_recovery_mode_in;
4395 */
4396 /* WRITE_VREG(AV_SCRATCH_F,
4397 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
4398 */
4399 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
4400 ((error_recovery_mode_in & 0x1) << 4));
4401 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
4402 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
4403 else*/
4404 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
4405
4406 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
4407#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
4408 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
4409#endif
4410
4411 WRITE_VREG(DEBUG_REG1, 0);
4412 WRITE_VREG(DEBUG_REG2, 0);
4413 return 0;
4414}
4415
4416static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
4417{
4418 struct vdec_h264_hw_s *hw =
4419 (struct vdec_h264_hw_s *)vdec->private;
4420 if (i_only_flag & 0x100)
4421 return 0;
4422 if (trickmode == TRICKMODE_I)
4423 hw->i_only = 0x3;
4424 else if (trickmode == TRICKMODE_NONE)
4425 hw->i_only = 0x0;
4426 return 0;
4427}
4428
4429static unsigned char amvdec_enable_flag;
4430static void vh264_local_init(struct vdec_h264_hw_s *hw)
4431{
4432 int i;
4433 hw->init_flag = 0;
4434 hw->eos = 0;
4435 hw->valve_count = 0;
4436 hw->config_bufmgr_done = 0;
4437 hw->start_process_time = 0;
4438 hw->has_i_frame = 0;
4439 hw->no_error_count = 0xfff;
4440 hw->no_error_i_count = 0xf;
4441
4442 hw->dec_flag = 0;
4443 hw->data_flag = 0;
4444 hw->skip_frame_count = 0;
4445
4446 hw->decode_timeout_count = 0;
4447
4448 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
4449 /* vh264_ratio = 0x100; */
4450
4451 hw->vh264_rotation = (((unsigned long)
4452 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
4453
4454 hw->frame_prog = 0;
4455 hw->frame_width = hw->vh264_amstream_dec_info.width;
4456 hw->frame_height = hw->vh264_amstream_dec_info.height;
4457 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
4458 hw->pts_outside = ((unsigned long)
4459 hw->vh264_amstream_dec_info.param) & 0x01;
4460 hw->sync_outside = ((unsigned long)
4461 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
4462 hw->use_idr_framerate = ((unsigned long)
4463 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
4464 hw->max_refer_buf = !(((unsigned long)
4465 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
4466 if (hw->frame_dur < 96000/960) {
4467 /*more than 960fps,it should not be a correct value,
4468 *give default 30fps
4469 */
4470 hw->frame_dur = 96000/30;
4471 }
4472
4473 pr_info
4474 ("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
4475 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
4476 pr_debug("sync_outside=%d, use_idr_framerate=%d\n",
4477 hw->sync_outside, hw->use_idr_framerate);
4478 if (i_only_flag & 0x100)
4479 hw->i_only = i_only_flag & 0xff;
4480
4481 if ((unsigned long) hw->vh264_amstream_dec_info.param
4482 & 0x08)
4483 hw->no_poc_reorder_flag = 1;
4484
4485 error_recovery_mode_in = 1; /*ucode control?*/
4486 if (error_proc_policy & 0x80000000)
4487 hw->send_error_frame_flag = error_proc_policy & 0x1;
4488 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
4489 hw->send_error_frame_flag = 1;
4490
4491 INIT_KFIFO(hw->display_q);
4492 INIT_KFIFO(hw->newframe_q);
4493
4494 for (i = 0; i < VF_POOL_SIZE; i++) {
4495 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
4496 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
4497 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
4498 kfifo_put(&hw->newframe_q, vf);
4499 }
4500
4501 hw->duration_from_pts_done = 0;
4502
4503 hw->p_last_vf = NULL;
4504 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
4505 hw->hevc_cur_buf_idx = 0xffff;
4506
4507 return;
4508}
4509
4510static s32 vh264_init(struct vdec_h264_hw_s *hw)
4511{
4512 /* int trickmode_fffb = 0; */
4513 int firmwareloaded = 0;
4514
4515 /* pr_info("\nvh264_init\n"); */
4516 /* init_timer(&hw->recycle_timer); */
4517
4518 /* timer init */
4519 init_timer(&hw->check_timer);
4520
4521 hw->check_timer.data = (unsigned long)hw;
4522 hw->check_timer.function = check_timer_func;
4523 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
4524
4525 /* add_timer(&hw->check_timer); */
4526 hw->stat |= STAT_TIMER_ARM;
4527 hw->stat |= STAT_ISR_REG;
4528
4529 vh264_local_init(hw);
4530 INIT_WORK(&hw->work, vh264_work);
4531 INIT_WORK(&hw->notify_work, vh264_notify_work);
4532 INIT_WORK(&hw->user_data_work, user_data_push_work);
4533
4534 if (!amvdec_enable_flag) {
4535 amvdec_enable_flag = true;
4536 amvdec_enable();
4537 if (mmu_enable)
4538 amhevc_enable();
4539 }
4540 if (mmu_enable) {
4541
4542 hw->frame_mmu_map_addr =
4543 dma_alloc_coherent(amports_get_dma_device(),
4544 FRAME_MMU_MAP_SIZE,
4545 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
4546 if (hw->frame_mmu_map_addr == NULL) {
4547 pr_err("%s: failed to alloc count_buffer\n", __func__);
4548 return -ENOMEM;
4549 }
4550 }
4551 if (tee_enabled() && !firmwareloaded) {
4552 pr_info("VMH264 start load sec firmware ...\n");
4553 } else {
4554 /* -- ucode loading (amrisc and swap code) */
4555 hw->mc_cpu_addr =
4556 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
4557 &hw->mc_dma_handle, GFP_KERNEL);
4558 if (!hw->mc_cpu_addr) {
4559 amvdec_enable_flag = false;
4560 amvdec_disable();
4561 if (mmu_enable)
4562 amhevc_disable();
4563 pr_info("vh264_init: Can not allocate mc memory.\n");
4564 return -ENOMEM;
4565 }
4566
4567 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
4568 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
4569 */
4570 if (!firmwareloaded) {
4571 int ret = 0, size = -1;
4572 int fw_size = 0x1000 * 16;
4573 struct firmware_s *fw = NULL;
4574
4575 pr_debug("start load orignal firmware ...\n");
4576
4577 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
4578 if (IS_ERR_OR_NULL(fw))
4579 return -ENOMEM;
4580
4581 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
4582 if (size < 0) {
4583 pr_err("get firmware fail.\n");
4584 vfree(fw);
4585 return -1;
4586 }
4587
4588 fw->len = size;
4589 hw->fw = fw;
4590
4591 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
4592
4593 /*header*/
4594 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
4595 fw->data + 0x4000, MC_SWAP_SIZE);
4596 /*data*/
4597 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
4598 fw->data + 0x2000, MC_SWAP_SIZE);
4599 /*mmco*/
4600 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
4601 fw->data + 0x6000, MC_SWAP_SIZE);
4602 /*list*/
4603 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
4604 fw->data + 0x3000, MC_SWAP_SIZE);
4605 /*slice*/
4606 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
4607 fw->data + 0x5000, MC_SWAP_SIZE);
4608 /*main*/
4609 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
4610 fw->data, 0x2000);
4611 /*data*/
4612 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
4613 fw->data + 0x2000, 0x1000);
4614 /*slice*/
4615 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
4616 fw->data + 0x5000, 0x1000);
4617
4618 if (mmu_enable) {
4619 int fw_mmu_size = 0x1000 * 16;
4620 struct firmware_s *fw_mmu = NULL;
4621
4622 pr_debug("start load mmu fw ...\n");
4623
4624 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
4625 if (IS_ERR_OR_NULL(fw_mmu))
4626 return -ENOMEM;
4627
4628 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU,
4629 fw_mmu->data);
4630 if (size < 0) {
4631 pr_err("get mmu fw fail.\n");
4632 vfree(fw_mmu);
4633 return -1;
4634 }
4635
4636 ret = amhevc_loadmc_ex(VFORMAT_HEVC,
4637 NULL, fw_mmu->data);
4638
4639 fw_mmu->len = size;
4640 hw->fw_mmu = fw_mmu;
4641 }
4642
4643 if (ret < 0) {
4644 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
4645 "264 load orignal firmware error.\n");
4646 amvdec_disable();
4647 if (mmu_enable)
4648 amhevc_disable();
4649 if (hw->mc_cpu_addr) {
4650 dma_free_coherent(amports_get_dma_device(),
4651 MC_TOTAL_SIZE, hw->mc_cpu_addr,
4652 hw->mc_dma_handle);
4653 hw->mc_cpu_addr = NULL;
4654 }
4655 return -EBUSY;
4656 }
4657 }
4658 }
4659#if 1 /* #ifdef BUFFER_MGR_IN_C */
4660 hw->lmem_addr = __get_free_page(GFP_KERNEL);
4661 if (!hw->lmem_addr) {
4662 pr_info("%s: failed to alloc lmem_addr\n", __func__);
4663 return -ENOMEM;
4664 }
4665 {
4666 hw->lmem_addr_remap = dma_map_single(
4667 amports_get_dma_device(),
4668 (void *)hw->lmem_addr,
4669 PAGE_SIZE, DMA_FROM_DEVICE);
4670 if (dma_mapping_error(amports_get_dma_device(),
4671 hw->lmem_addr_remap)) {
4672 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
4673 "%s: failed to map lmem_addr\n", __func__);
4674 free_page(hw->lmem_addr);
4675 hw->lmem_addr = 0;
4676 hw->lmem_addr_remap = 0;
4677 return -ENOMEM;
4678 }
4679
4680 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
4681 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
4682 }
4683
4684 if (prefix_aux_buf_size > 0 ||
4685 suffix_aux_buf_size > 0) {
4686 u32 aux_buf_size;
4687 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
4688 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
4689 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
4690 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
4691 if (hw->aux_addr == NULL) {
4692 pr_err("%s: failed to alloc rpm buffer\n", __func__);
4693 return -1;
4694 }
4695
4696 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
4697 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
4698 if (dma_mapping_error(amports_get_dma_device(),
4699 hw->aux_phy_addr)) {
4700 pr_err("%s: failed to map rpm buffer\n", __func__);
4701 kfree(hw->aux_addr);
4702 hw->aux_addr = NULL;
4703 return -1;
4704 }
4705 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
4706 if (hw->sei_itu_data_buf == NULL) {
4707 pr_err("%s: failed to alloc sei itu data buffer\n",
4708 __func__);
4709 return -1;
4710 }
4711
4712 if (NULL == hw->sei_user_data_buffer) {
4713 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
4714 GFP_KERNEL);
4715 if (!hw->sei_user_data_buffer) {
4716 pr_info("%s: Can not allocate sei_data_buffer\n",
4717 __func__);
4718 return -1;
4719 }
4720 hw->sei_user_data_wp = 0;
4721 }
4722 }
4723/* BUFFER_MGR_IN_C */
4724#endif
4725 hw->stat |= STAT_MC_LOAD;
4726 if (mmu_enable) {
4727 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
4728 amhevc_start();
4729 }
4730 /* add memory barrier */
4731 wmb();
4732
4733 return 0;
4734}
4735
4736static int vh264_stop(struct vdec_h264_hw_s *hw)
4737{
4738 cancel_work_sync(&hw->work);
4739 cancel_work_sync(&hw->notify_work);
4740 cancel_work_sync(&hw->user_data_work);
4741
4742 if (hw->stat & STAT_MC_LOAD) {
4743 if (hw->mc_cpu_addr != NULL) {
4744 dma_free_coherent(amports_get_dma_device(),
4745 MC_TOTAL_SIZE, hw->mc_cpu_addr,
4746 hw->mc_dma_handle);
4747 hw->mc_cpu_addr = NULL;
4748 }
4749 if (hw->frame_mmu_map_addr != NULL) {
4750 dma_free_coherent(amports_get_dma_device(),
4751 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
4752 hw->frame_mmu_map_phy_addr);
4753 hw->frame_mmu_map_addr = NULL;
4754 }
4755
4756 }
4757 if (hw->stat & STAT_ISR_REG) {
4758 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
4759 hw->stat &= ~STAT_ISR_REG;
4760 }
4761 if (hw->lmem_addr_remap) {
4762 dma_unmap_single(amports_get_dma_device(),
4763 hw->lmem_addr_remap,
4764 PAGE_SIZE, DMA_FROM_DEVICE);
4765 hw->lmem_addr_remap = 0;
4766 }
4767 if (hw->lmem_addr) {
4768 free_page(hw->lmem_addr);
4769 hw->lmem_addr = 0;
4770 }
4771 if (hw->aux_addr) {
4772 dma_unmap_single(amports_get_dma_device(),
4773 hw->aux_phy_addr,
4774 hw->prefix_aux_size + hw->suffix_aux_size,
4775 DMA_FROM_DEVICE);
4776 kfree(hw->aux_addr);
4777 hw->aux_addr = NULL;
4778 }
4779 if (hw->sei_itu_data_buf != NULL) {
4780 kfree(hw->sei_itu_data_buf);
4781 hw->sei_itu_data_buf = NULL;
4782 }
4783 if (hw->sei_user_data_buffer != NULL) {
4784 kfree(hw->sei_user_data_buffer);
4785 hw->sei_user_data_buffer = NULL;
4786 }
4787 /* amvdec_disable(); */
4788
4789 vfree(hw->fw);
4790 hw->fw = NULL;
4791
4792 if (mmu_enable) {
4793 vfree(hw->fw_mmu);
4794 hw->fw_mmu = NULL;
4795 }
4796
4797 dpb_print(DECODE_ID(hw), 0,
4798 "%s\n",
4799 __func__);
4800 return 0;
4801}
4802
4803static void vh264_notify_work(struct work_struct *work)
4804{
4805 struct vdec_h264_hw_s *hw = container_of(work,
4806 struct vdec_h264_hw_s, notify_work);
4807 struct vdec_s *vdec = hw_to_vdec(hw);
4808 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
4809 vf_notify_receiver(vdec->vf_provider_name,
4810 VFRAME_EVENT_PROVIDER_FR_HINT,
4811 (void *)((unsigned long)hw->frame_dur));
4812 vdec->fr_hint_state = VDEC_HINTED;
4813 }
4814
4815 return;
4816}
4817
4818static void user_data_push_work(struct work_struct *work)
4819{
4820 struct vdec_h264_hw_s *hw = container_of(work,
4821 struct vdec_h264_hw_s, user_data_work);
4822
4823 struct userdata_poc_info_t user_data_poc;
4824 unsigned char *pdata;
4825 u8 *pmax_sei_data_buffer;
4826 u8 *sei_data_buf;
4827 int i;
4828
4829 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
4830 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
4831 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
4832 for (i = 0; i < hw->sei_itu_data_len; i++) {
4833 *pdata++ = sei_data_buf[i];
4834 if (pdata >= pmax_sei_data_buffer)
4835 pdata = (u8 *)hw->sei_user_data_buffer;
4836 }
4837
4838 hw->sei_user_data_wp = (hw->sei_user_data_wp
4839 + hw->sei_itu_data_len) % USER_DATA_SIZE;
4840 user_data_poc.poc_number = hw->sei_poc;
4841
4842 wakeup_userdata_poll(user_data_poc, hw->sei_user_data_wp,
4843 (unsigned long)hw->sei_user_data_buffer,
4844 USER_DATA_SIZE, hw->sei_itu_data_len);
4845 hw->sei_itu_data_len = 0;
4846/*
4847 pr_info("sei_itu35_wp = %d, poc = %d\n",
4848 hw->sei_user_data_wp, hw->sei_poc);
4849*/
4850}
4851
4852static void vh264_work(struct work_struct *work)
4853{
4854 struct vdec_h264_hw_s *hw = container_of(work,
4855 struct vdec_h264_hw_s, work);
4856 struct vdec_s *vdec = hw_to_vdec(hw);
4857
4858 /* finished decoding one frame or error,
4859 * notify vdec core to switch context
4860 */
4861 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
4862 "%s dec_result %d %x %x %x\n",
4863 __func__,
4864 hw->dec_result,
4865 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
4866 READ_VREG(VLD_MEM_VIFIFO_WP),
4867 READ_VREG(VLD_MEM_VIFIFO_RP));
4868 if (!mmu_enable) {
4869 mutex_lock(&vmh264_mutex);
4870 dealloc_buf_specs(hw, 0);
4871 mutex_unlock(&vmh264_mutex);
4872 }
4873 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
4874 u32 param1 = READ_VREG(AV_SCRATCH_1);
4875 u32 param2 = READ_VREG(AV_SCRATCH_2);
4876 u32 param3 = READ_VREG(AV_SCRATCH_6);
4877 u32 param4 = READ_VREG(AV_SCRATCH_B);
4878 if (vh264_set_params(hw, param1,
4879 param2, param3, param4) < 0)
4880 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
4881 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
4882 (hw->dpb.mDPB.size<<16) |
4883 (hw->dpb.mDPB.size<<8));
4884 start_process_time(hw);
4885 return;
4886 } else
4887 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
4888 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
4889 && (hw_to_vdec(hw)->next_status !=
4890 VDEC_STATUS_DISCONNECTED)) {
4891 if (!vdec_has_more_input(vdec)) {
4892 hw->dec_result = DEC_RESULT_EOS;
4893 vdec_schedule_work(&hw->work);
4894 return;
4895 }
4896
4897 if (hw->dec_result == DEC_RESULT_GET_DATA) {
4898 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4899 "%s DEC_RESULT_GET_DATA %x %x %x\n",
4900 __func__,
4901 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
4902 READ_VREG(VLD_MEM_VIFIFO_WP),
4903 READ_VREG(VLD_MEM_VIFIFO_RP));
4904 vdec_vframe_dirty(vdec, hw->chunk);
4905 vdec_clean_input(vdec);
4906 }
4907 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
4908 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
4909 > get_data_timeout_val)) {
4910 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4911 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
4912 __func__);
4913 goto result_done;
4914 }
4915 if (is_buffer_available(vdec)) {
4916 int r;
4917 int decode_size;
4918 r = vdec_prepare_input(vdec, &hw->chunk);
4919 if (r < 0) {
4920 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
4921
4922 dpb_print(DECODE_ID(hw),
4923 PRINT_FLAG_VDEC_DETAIL,
4924 "vdec_prepare_input: Insufficient data\n");
4925
4926 vdec_schedule_work(&hw->work);
4927 return;
4928 }
4929 hw->dec_result = DEC_RESULT_NONE;
4930 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4931 "%s: chunk size 0x%x\n",
4932 __func__, hw->chunk->size);
4933
4934 if (dpb_is_debug(DECODE_ID(hw),
4935 PRINT_FRAMEBASE_DATA)) {
4936 int jj;
4937 u8 *data =
4938 ((u8 *)hw->chunk->block->start_virt) +
4939 hw->chunk->offset;
4940 for (jj = 0; jj < r; jj++) {
4941 if ((jj & 0xf) == 0)
4942 dpb_print(DECODE_ID(hw),
4943 PRINT_FRAMEBASE_DATA,
4944 "%06x:", jj);
4945 dpb_print_cont(DECODE_ID(hw),
4946 PRINT_FRAMEBASE_DATA,
4947 "%02x ", data[jj]);
4948 if (((jj + 1) & 0xf) == 0)
4949 dpb_print_cont(DECODE_ID(hw),
4950 PRINT_FRAMEBASE_DATA,
4951 "\n");
4952 }
4953 }
4954 WRITE_VREG(POWER_CTL_VLD,
4955 READ_VREG(POWER_CTL_VLD) |
4956 (0 << 10) | (1 << 9) | (1 << 6));
4957 WRITE_VREG(H264_DECODE_INFO, (1<<13));
4958 decode_size = hw->chunk->size +
4959 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
4960 WRITE_VREG(H264_DECODE_SIZE, decode_size);
4961 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
4962 vdec_enable_input(vdec);
4963
4964 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
4965 start_process_time(hw);
4966 } else{
4967 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
4968 vdec_schedule_work(&hw->work);
4969 }
4970 return;
4971 } else if (hw->dec_result == DEC_RESULT_DONE) {
4972 /* if (!hw->ctx_valid)
4973 hw->ctx_valid = 1; */
4974result_done:
4975 decode_frame_count[DECODE_ID(hw)]++;
4976 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
4977 "%s dec_result %d %x %x %x\n",
4978 __func__,
4979 hw->dec_result,
4980 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
4981 READ_VREG(VLD_MEM_VIFIFO_WP),
4982 READ_VREG(VLD_MEM_VIFIFO_RP));
4983 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
4984 amvdec_stop();
4985 /*if (mmu_enable)
4986 *amhevc_stop();
4987 */
4988 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
4989 /*
4990 stream base: stream buf empty or timeout
4991 frame base: vdec_prepare_input fail
4992 */
4993 if (!vdec_has_more_input(vdec)) {
4994 hw->dec_result = DEC_RESULT_EOS;
4995 vdec_schedule_work(&hw->work);
4996 return;
4997 }
4998
4999 } else if (hw->dec_result == DEC_RESULT_EOS) {
5000 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5001 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5002 "%s: end of stream\n",
5003 __func__);
5004
5005 hw->eos = 1;
5006 flush_dpb(p_H264_Dpb);
5007 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
5008 amvdec_stop();
5009 if (mmu_enable)
5010 amhevc_stop();
5011 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
5012 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5013 "%s: force exit\n",
5014 __func__);
5015 amvdec_stop();
5016 if (mmu_enable)
5017 amhevc_stop();
5018 if (hw->stat & STAT_ISR_REG) {
5019 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
5020 hw->stat &= ~STAT_ISR_REG;
5021 }
5022 }
5023
5024 del_timer_sync(&hw->check_timer);
5025 hw->stat &= ~STAT_TIMER_ARM;
5026
5027 /* mark itself has all HW resource released and input released */
5028 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_CONNECTED);
5029
5030#ifdef CONFIG_AM_VDEC_DV
5031 if (hw->switch_dvlayer_flag) {
5032 if (vdec->slave)
5033 vdec_set_next_sched(vdec, vdec->slave);
5034 else if (vdec->master)
5035 vdec_set_next_sched(vdec, vdec->master);
5036 } else if (vdec->slave || vdec->master)
5037 vdec_set_next_sched(vdec, vdec);
5038#endif
5039
5040 if (hw->vdec_cb)
5041 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
5042}
5043
5044static bool run_ready(struct vdec_s *vdec)
5045{
5046 bool ret = 0;
5047 struct vdec_h264_hw_s *hw =
5048 (struct vdec_h264_hw_s *)vdec->private;
5049
5050#ifndef CONFIG_AM_VDEC_DV
5051 if (vdec->master)
5052 return false;
5053#endif
5054 if (hw->eos)
5055 return 0;
5056
5057 if (disp_vframe_valve_level &&
5058 kfifo_len(&hw->display_q) >=
5059 disp_vframe_valve_level) {
5060 hw->valve_count--;
5061 if (hw->valve_count <= 0)
5062 hw->valve_count = 2;
5063 else
5064 return 0;
5065 }
5066
5067 if (h264_debug_flag & 0x20000000) {
5068 /* pr_info("%s, a\n", __func__); */
5069 ret = 1;
5070 } else
5071 ret = is_buffer_available(vdec);
5072
5073 if (ret)
5074 not_run_ready[DECODE_ID(hw)] = 0;
5075 else
5076 not_run_ready[DECODE_ID(hw)]++;
5077 return ret;
5078}
5079
5080static unsigned char get_data_check_sum
5081 (struct vdec_h264_hw_s *hw, int size)
5082{
5083 int jj;
5084 int sum = 0;
5085 u8 *data = ((u8 *)hw->chunk->block->start_virt) +
5086 hw->chunk->offset;
5087 for (jj = 0; jj < size; jj++)
5088 sum += data[jj];
5089 return sum;
5090}
5091
5092static void run(struct vdec_s *vdec,
5093 void (*callback)(struct vdec_s *, void *), void *arg)
5094{
5095 struct vdec_h264_hw_s *hw =
5096 (struct vdec_h264_hw_s *)vdec->private;
5097 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5098 int size;
5099
5100 run_count[DECODE_ID(hw)]++;
5101
5102 hw->vdec_cb_arg = arg;
5103 hw->vdec_cb = callback;
5104
5105 if (hw->reset_bufmgr_flag ||
5106 ((error_proc_policy & 0x40) &&
5107 p_H264_Dpb->buf_alloc_fail)) {
5108 h264_reset_bufmgr(hw);
5109 hw->reset_bufmgr_flag = 0;
5110 }
5111
5112 if (h264_debug_cmd & 0xf000) {
5113 if (((h264_debug_cmd >> 12) & 0xf)
5114 == (DECODE_ID(hw) + 1)) {
5115 h264_reconfig(hw);
5116 h264_debug_cmd &= (~0xf000);
5117 }
5118 }
5119 /* hw->chunk = vdec_prepare_input(vdec); */
5120#ifdef CONFIG_AM_VDEC_DV
5121 if (vdec->slave || vdec->master)
5122 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
5123#endif
5124 size = vdec_prepare_input(vdec, &hw->chunk);
5125 if ((size < 0) ||
5126 (input_frame_based(vdec) && hw->chunk == NULL)) {
5127 input_empty[DECODE_ID(hw)]++;
5128 hw->dec_result = DEC_RESULT_AGAIN;
5129
5130 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5131 "vdec_prepare_input: Insufficient data\n");
5132
5133 vdec_schedule_work(&hw->work);
5134 return;
5135 }
5136 input_empty[DECODE_ID(hw)] = 0;
5137
5138 hw->dec_result = DEC_RESULT_NONE;
5139 hw->get_data_count = 0;
5140#if 0
5141 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
5142 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
5143 READ_VREG(VLD_MEM_VIFIFO_RP),
5144 READ_VREG(VLD_MEM_VIFIFO_WP));
5145#endif
5146
5147 if (input_frame_based(vdec)) {
5148 u8 *data = ((u8 *)hw->chunk->block->start_virt) +
5149 hw->chunk->offset;
5150 if (dpb_is_debug(DECODE_ID(hw),
5151 PRINT_FLAG_VDEC_STATUS)
5152 ) {
5153 dpb_print(DECODE_ID(hw), 0,
5154 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
5155 __func__, size, get_data_check_sum(hw, size),
5156 data[0], data[1], data[2], data[3],
5157 data[4], data[5], data[size - 4],
5158 data[size - 3], data[size - 2],
5159 data[size - 1]);
5160 }
5161 if (dpb_is_debug(DECODE_ID(hw),
5162 PRINT_FRAMEBASE_DATA)
5163 ) {
5164 int jj;
5165 u8 *data =
5166 ((u8 *)hw->chunk->block->start_virt) +
5167 hw->chunk->offset;
5168 for (jj = 0; jj < size; jj++) {
5169 if ((jj & 0xf) == 0)
5170 dpb_print(DECODE_ID(hw),
5171 PRINT_FRAMEBASE_DATA,
5172 "%06x:", jj);
5173 dpb_print_cont(DECODE_ID(hw),
5174 PRINT_FRAMEBASE_DATA,
5175 "%02x ", data[jj]);
5176 if (((jj + 1) & 0xf) == 0)
5177 dpb_print_cont(DECODE_ID(hw),
5178 PRINT_FRAMEBASE_DATA,
5179 "\n");
5180 }
5181 }
5182
5183 } else
5184 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5185 "%s: %x %x %x %x %x size 0x%x\n",
5186 __func__,
5187 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
5188 READ_VREG(VLD_MEM_VIFIFO_WP),
5189 READ_VREG(VLD_MEM_VIFIFO_RP),
5190 READ_PARSER_REG(PARSER_VIDEO_RP),
5191 READ_PARSER_REG(PARSER_VIDEO_WP),
5192 size);
5193
5194 start_process_time(hw);
5195
5196 if (tee_enabled()) {
5197 if (tee_load_video_fw((u32)VIDEO_DEC_H264_MULTI)
5198 != 0) {
5199 amvdec_enable_flag = false;
5200 amvdec_disable();
5201 pr_info("%s: Error amvdec_vdec_loadmc fail\n",
5202 __func__);
5203 return;
5204 }
5205 } else if (amvdec_vdec_loadmc_ex(vdec, NULL, hw->fw->data) < 0) {
5206 amvdec_enable_flag = false;
5207 amvdec_disable();
5208 pr_info("%s: Error amvdec_vdec_loadmc fail\n",
5209 __func__);
5210 return;
5211 }
5212
5213 if (vh264_hw_ctx_restore(hw) < 0) {
5214 vdec_schedule_work(&hw->work);
5215 return;
5216 }
5217 if (input_frame_based(vdec)) {
5218 int decode_size = hw->chunk->size +
5219 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
5220 WRITE_VREG(H264_DECODE_INFO, (1<<13));
5221 WRITE_VREG(H264_DECODE_SIZE, decode_size);
5222 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
5223 } else {
5224 if (size <= 0)
5225 size = 0x7fffffff; /*error happen*/
5226 WRITE_VREG(H264_DECODE_INFO, (1<<13));
5227 WRITE_VREG(H264_DECODE_SIZE, size);
5228 WRITE_VREG(VIFF_BIT_CNT, size * 8);
5229 }
5230 config_aux_buf(hw);
5231 config_decode_mode(hw);
5232 vdec_enable_input(vdec);
5233 WRITE_VREG(NAL_SEARCH_CTL, 0);
5234 if (enable_itu_t35)
5235 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
5236 if (mmu_enable)
5237 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x2);
5238 if (udebug_flag)
5239 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
5240 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
5241
5242 amvdec_start();
5243
5244 /* if (hw->init_flag) { */
5245 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5246 /* } */
5247
5248 hw->init_flag = 1;
5249}
5250
5251static void reset(struct vdec_s *vdec)
5252{
5253 pr_info("ammvdec_h264: reset.\n");
5254}
5255
5256static void h264_reconfig(struct vdec_h264_hw_s *hw)
5257{
5258 int i;
5259 unsigned long flags;
5260 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5261 dpb_print(DECODE_ID(hw), 0,
5262 "%s\n", __func__);
5263 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
5264 all buffers are in display queue (used == 2),
5265 or free (used == 0)
5266 */
5267 flush_dpb(p_H264_Dpb);
5268 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
5269
5270 if (hw->collocate_cma_alloc_addr) {
5271 decoder_bmmu_box_free_idx(
5272 hw->bmmu_box,
5273 BMMU_REF_IDX);
5274 hw->collocate_cma_alloc_addr = 0;
5275 hw->dpb.colocated_mv_addr_start = 0;
5276 hw->dpb.colocated_mv_addr_end = 0;
5277 }
5278 spin_lock_irqsave(&hw->bufspec_lock, flags);
5279 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5280 /*make sure buffers not put back to bufmgr when
5281 vf_put is called*/
5282 if (hw->buffer_spec[i].used == 2)
5283 hw->buffer_spec[i].used = 3;
5284
5285 /* ready to release "free buffers"
5286 */
5287 if (hw->buffer_spec[i].used == 0)
5288 hw->buffer_spec[i].used = 4;
5289
5290 hw->buffer_spec[i].canvas_pos = -1;
5291 }
5292 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
5293 hw->has_i_frame = 0;
5294 hw->config_bufmgr_done = 0;
5295
5296}
5297
5298#ifdef ERROR_HANDLE_TEST
5299static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
5300{
5301 int i;
5302 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5303 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5304 "%s\n", __func__);
5305 remove_dpb_pictures(p_H264_Dpb);
5306 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5307 /*make sure buffers not put back to bufmgr when
5308 vf_put is called*/
5309 if (hw->buffer_spec[i].used == 2)
5310 hw->buffer_spec[i].used = 5;
5311 }
5312
5313}
5314#endif
5315
5316static void h264_reset_bufmgr(struct vdec_h264_hw_s *hw)
5317{
5318 int i;
5319#if 0
5320 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5321 int actual_dpb_size, max_reference_size;
5322 int reorder_pic_num;
5323 unsigned int colocated_buf_size;
5324 unsigned int colocated_mv_addr_start;
5325 unsigned int colocated_mv_addr_end;
5326 dpb_print(DECODE_ID(hw), 0,
5327 "%s\n", __func__);
5328
5329 for (i = 0; i < VF_POOL_SIZE; i++)
5330 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
5331
5332 actual_dpb_size = p_H264_Dpb->mDPB.size;
5333 max_reference_size = p_H264_Dpb->max_reference_size;
5334 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
5335
5336 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
5337 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
5338 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
5339
5340 hw->cur_pool++;
5341 if (hw->cur_pool >= VF_POOL_NUM)
5342 hw->cur_pool = 0;
5343
5344 INIT_KFIFO(hw->display_q);
5345 INIT_KFIFO(hw->newframe_q);
5346
5347 for (i = 0; i < VF_POOL_SIZE; i++) {
5348 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
5349 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
5350 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
5351 kfifo_put(&hw->newframe_q, vf);
5352 }
5353
5354 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
5355 hw->buffer_spec[i].used = 0;
5356
5357 dpb_init_global(&hw->dpb,
5358 DECODE_ID(hw), 0, 0);
5359 p_H264_Dpb->mDPB.size = actual_dpb_size;
5360 p_H264_Dpb->max_reference_size = max_reference_size;
5361 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
5362
5363 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
5364 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
5365 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
5366
5367 p_H264_Dpb->fast_output_enable = fast_output_enable;
5368 hw->has_i_frame = 0;
5369#else
5370 dpb_print(DECODE_ID(hw), 0,
5371 "%s frame count %d to skip %d\n\n",
5372 __func__, hw->decode_pic_count+1,
5373 hw->skip_frame_count);
5374
5375 for (i = 0; i < VF_POOL_SIZE; i++)
5376 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
5377
5378 hw->cur_pool++;
5379 if (hw->cur_pool >= VF_POOL_NUM)
5380 hw->cur_pool = 0;
5381
5382 if (hw->collocate_cma_alloc_addr) {
5383 decoder_bmmu_box_free_idx(
5384 hw->bmmu_box,
5385 BMMU_REF_IDX);
5386 hw->collocate_cma_alloc_addr = 0;
5387 hw->dpb.colocated_mv_addr_start = 0;
5388 hw->dpb.colocated_mv_addr_end = 0;
5389 }
5390
5391 dealloc_buf_specs(hw, 1);
5392 buf_spec_init(hw);
5393
5394 vh264_local_init(hw);
5395 /*hw->decode_pic_count = 0;
5396 hw->seq_info2 = 0;*/
5397 if (vh264_set_params(hw,
5398 hw->cfg_param1,
5399 hw->cfg_param2,
5400 hw->cfg_param3,
5401 hw->cfg_param4) < 0)
5402 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
5403 hw->init_flag = 1;
5404 hw->reset_bufmgr_count++;
5405#endif
5406
5407}
5408
5409int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
5410{
5411 int ret = -1;
5412 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
5413 CODEC_MM_FLAGS_TVP : 0;
5414
5415 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
5416 tvp_flag, mmu_enable);
5417 if (mmu_enable && !hw->mmu_box) {
5418 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
5419 hw->id,
5420 MMU_MAX_BUFFERS,
5421 64 * SZ_1M,
5422 tvp_flag);
5423 if (!hw->mmu_box) {
5424 pr_err("h264 4k alloc mmu box failed!!\n");
5425 return -1;
5426 }
5427 ret = 0;
5428 }
5429 if (!hw->bmmu_box) {
5430 hw->bmmu_box = decoder_bmmu_box_alloc_box(
5431 DRIVER_NAME,
5432 hw->id,
5433 BMMU_MAX_BUFFERS,
5434 4 + PAGE_SHIFT,
5435 CODEC_MM_FLAGS_CMA_CLEAR |
5436 CODEC_MM_FLAGS_FOR_VDECODER |
5437 tvp_flag);
5438 if (hw->bmmu_box)
5439 ret = 0;
5440 }
5441 return ret;
5442}
5443int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
5444{
5445 if (hw->mmu_box) {
5446 decoder_mmu_box_free(hw->mmu_box);
5447 hw->mmu_box = NULL;
5448 }
5449 if (hw->bmmu_box) {
5450 decoder_bmmu_box_free(hw->bmmu_box);
5451 hw->bmmu_box = NULL;
5452 }
5453 return 0;
5454}
5455
5456static int ammvdec_h264_probe(struct platform_device *pdev)
5457{
5458 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
5459 struct vdec_h264_hw_s *hw = NULL;
5460 char *tmpbuf;
5461
5462 if (pdata == NULL) {
5463 pr_info("\nammvdec_h264 memory resource undefined.\n");
5464 return -EFAULT;
5465 }
5466
5467 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
5468 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
5469 if (hw == NULL) {
5470 pr_info("\nammvdec_h264 device data allocation failed\n");
5471 return -ENOMEM;
5472 }
5473 hw->id = pdev->id;
5474 hw->platform_dev = pdev;
5475 platform_set_drvdata(pdev, pdata);
5476
5477 mmu_enable = 0;
5478 if (force_enable_mmu && pdata->sys_info &&
5479 (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) &&
5480 (pdata->sys_info->height * pdata->sys_info->width
5481 > 1920 * 1088))
5482 mmu_enable = 1;
5483 if (ammvdec_h264_mmu_init(hw)) {
5484 h264_free_hw_stru(&pdev->dev, (void *)hw);
5485 pr_info("\nammvdec_h264 mmu alloc failed!\n");
5486 return -ENOMEM;
5487 }
5488 pdata->private = hw;
5489 pdata->dec_status = dec_status;
5490 pdata->set_trickmode = vmh264_set_trickmode;
5491 pdata->run_ready = run_ready;
5492 pdata->run = run;
5493 pdata->reset = reset;
5494 pdata->irq_handler = vh264_isr;
5495 pdata->threaded_irq_handler = vh264_isr_thread_fn;
5496 pdata->dump_state = vmh264_dump_state;
5497
5498
5499 if (pdata->use_vfm_path)
5500 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
5501 VFM_DEC_PROVIDER_NAME);
5502#ifdef CONFIG_AM_VDEC_DV
5503 else if (vdec_dual(pdata)) {
5504 if (dv_toggle_prov_name) /*debug purpose*/
5505 snprintf(pdata->vf_provider_name,
5506 VDEC_PROVIDER_NAME_SIZE,
5507 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
5508 VFM_DEC_DVEL_PROVIDER_NAME);
5509 else
5510 snprintf(pdata->vf_provider_name,
5511 VDEC_PROVIDER_NAME_SIZE,
5512 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
5513 VFM_DEC_DVBL_PROVIDER_NAME);
5514 }
5515#endif
5516 else
5517 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
5518 PROVIDER_NAME ".%02x", pdev->id & 0xff);
5519
5520 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
5521 &vf_provider_ops, pdata);
5522
5523 platform_set_drvdata(pdev, pdata);
5524
5525 buf_spec_init(hw);
5526
5527 hw->platform_dev = pdev;
5528
5529
5530 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
5531 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
5532 h264_free_hw_stru(&pdev->dev, (void *)hw);
5533 return -ENOMEM;
5534 }
5535
5536 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
5537 DCAC_READ_MARGIN;
5538 if (mmu_enable)
5539 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
5540 EXTIF_BUF_SIZE, DRIVER_NAME, &hw->extif_addr) < 0) {
5541 h264_free_hw_stru(&pdev->dev, (void *)hw);
5542 return -ENOMEM;
5543 }
5544 if (!vdec_secure(pdata)) {
5545#if 1
5546 /*init internal buf*/
5547 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
5548 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
5549 dma_sync_single_for_device(amports_get_dma_device(),
5550 hw->cma_alloc_addr,
5551 V_BUF_ADDR_OFFSET, DMA_TO_DEVICE);
5552#else
5553 /*init sps/pps internal buf 64k*/
5554 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
5555 + (mem_sps_base - DEF_BUF_START_ADDR));
5556 memset(tmpbuf, 0, 0x10000);
5557 dma_sync_single_for_device(amports_get_dma_device(),
5558 hw->cma_alloc_addr +
5559 (mem_sps_base - DEF_BUF_START_ADDR),
5560 0x10000, DMA_TO_DEVICE);
5561#endif
5562 }
5563 /**/
5564
5565 if (pdata->sys_info)
5566 hw->vh264_amstream_dec_info = *pdata->sys_info;
5567#if 0
5568 if (NULL == hw->sei_data_buffer) {
5569 hw->sei_data_buffer =
5570 dma_alloc_coherent(amports_get_dma_device(),
5571 USER_DATA_SIZE,
5572 &hw->sei_data_buffer_phys, GFP_KERNEL);
5573 if (!hw->sei_data_buffer) {
5574 pr_info("%s: Can not allocate sei_data_buffer\n",
5575 __func__);
5576 ammvdec_h264_mmu_release(hw);
5577 h264_free_hw_stru(&pdev->dev, (void *)hw);
5578 return -ENOMEM;
5579 }
5580 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
5581 sei_data_buffer, sei_data_buffer_phys,
5582 (u32)sei_data_buffer_remap); */
5583 }
5584#endif
5585 pr_debug("ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
5586 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
5587
5588
5589 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
5590
5591 if (vh264_init(hw) < 0) {
5592 pr_info("\nammvdec_h264 init failed.\n");
5593 ammvdec_h264_mmu_release(hw);
5594 h264_free_hw_stru(&pdev->dev, (void *)hw);
5595 return -ENODEV;
5596 }
5597
5598 vdec_set_prepare_level(pdata, start_decode_buf_level);
5599
5600 atomic_set(&hw->vh264_active, 1);
5601
5602 return 0;
5603}
5604
5605static int ammvdec_h264_remove(struct platform_device *pdev)
5606{
5607 struct vdec_h264_hw_s *hw =
5608 (struct vdec_h264_hw_s *)
5609 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
5610 int i;
5611
5612 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
5613 release_aux_data(hw, i);
5614
5615 atomic_set(&hw->vh264_active, 0);
5616
5617 if (hw->stat & STAT_TIMER_ARM) {
5618 del_timer_sync(&hw->check_timer);
5619 hw->stat &= ~STAT_TIMER_ARM;
5620 }
5621
5622 vh264_stop(hw);
5623
5624 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
5625
5626 atomic_set(&hw->vh264_active, 0);
5627
5628 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
5629 ammvdec_h264_mmu_release(hw);
5630 h264_free_hw_stru(&pdev->dev, (void *)hw);
5631 return 0;
5632}
5633
5634/****************************************/
5635
5636static struct platform_driver ammvdec_h264_driver = {
5637 .probe = ammvdec_h264_probe,
5638 .remove = ammvdec_h264_remove,
5639#ifdef CONFIG_PM
5640 .suspend = amvdec_suspend,
5641 .resume = amvdec_resume,
5642#endif
5643 .driver = {
5644 .name = DRIVER_NAME,
5645 }
5646};
5647
5648static struct codec_profile_t ammvdec_h264_profile = {
5649 .name = "mh264",
5650 .profile = ""
5651};
5652
5653static struct mconfig hm264_configs[] = {
5654 MC_PU32("h264_debug_flag", &h264_debug_flag),
5655 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
5656 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
5657 MC_PU32("decode_timeout_val", &decode_timeout_val),
5658 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
5659 MC_PU32("reference_buf_margin", &reference_buf_margin),
5660 MC_PU32("radr", &radr),
5661 MC_PU32("rval", &rval),
5662 MC_PU32("h264_debug_mask", &h264_debug_mask),
5663 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
5664 MC_PI32("force_rate_streambase", &force_rate_streambase),
5665 MC_PI32("dec_control", &dec_control),
5666 MC_PI32("force_rate_framebase", &force_rate_framebase),
5667 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
5668 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
5669 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
5670#ifdef CONFIG_AM_VDEC_DV
5671 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
5672 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
5673 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
5674#endif
5675 MC_PU32("i_only_flag", &i_only_flag),
5676 MC_PU32("force_rate_streambase", &force_rate_streambase),
5677};
5678static struct mconfig_node hm264_node;
5679
5680
5681static int __init ammvdec_h264_driver_init_module(void)
5682{
5683 pr_info("ammvdec_h264 module init\n");
5684 if (platform_driver_register(&ammvdec_h264_driver)) {
5685 pr_info("failed to register ammvdec_h264 driver\n");
5686 return -ENODEV;
5687 }
5688 vcodec_profile_register(&ammvdec_h264_profile);
5689 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
5690 "mh264", hm264_configs, CONFIG_FOR_RW);
5691 return 0;
5692}
5693
5694static void __exit ammvdec_h264_driver_remove_module(void)
5695{
5696 pr_info("ammvdec_h264 module remove.\n");
5697
5698 platform_driver_unregister(&ammvdec_h264_driver);
5699}
5700
5701/****************************************/
5702
5703module_param(h264_debug_flag, uint, 0664);
5704MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
5705
5706module_param(start_decode_buf_level, int, 0664);
5707MODULE_PARM_DESC(start_decode_buf_level,
5708 "\n ammvdec_h264 start_decode_buf_level\n");
5709
5710module_param(fixed_frame_rate_mode, uint, 0664);
5711MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
5712
5713module_param(decode_timeout_val, uint, 0664);
5714MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
5715
5716module_param(errordata_timeout_val, uint, 0664);
5717MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
5718
5719module_param(get_data_timeout_val, uint, 0664);
5720MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
5721
5722module_param(frame_max_data_packet, uint, 0664);
5723MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
5724
5725module_param(reorder_dpb_size_margin, uint, 0664);
5726MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
5727
5728#ifdef CONFIG_AM_VDEC_DV
5729module_param(reorder_dpb_size_margin_dv, uint, 0664);
5730MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
5731 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
5732#endif
5733
5734module_param(reference_buf_margin, uint, 0664);
5735MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
5736
5737module_param(radr, uint, 0664);
5738MODULE_PARM_DESC(radr, "\nradr\n");
5739
5740module_param(rval, uint, 0664);
5741MODULE_PARM_DESC(rval, "\nrval\n");
5742
5743module_param(h264_debug_mask, uint, 0664);
5744MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
5745
5746module_param(h264_debug_cmd, uint, 0664);
5747MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
5748
5749module_param(force_rate_streambase, int, 0664);
5750MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
5751
5752module_param(dec_control, int, 0664);
5753MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
5754
5755module_param(force_rate_framebase, int, 0664);
5756MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
5757
5758module_param(force_disp_bufspec_num, int, 0664);
5759MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
5760
5761module_param(V_BUF_ADDR_OFFSET, int, 0664);
5762MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
5763
5764module_param(prefix_aux_buf_size, uint, 0664);
5765MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
5766
5767module_param(suffix_aux_buf_size, uint, 0664);
5768MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
5769
5770#ifdef CONFIG_AM_VDEC_DV
5771module_param(dv_toggle_prov_name, uint, 0664);
5772MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
5773
5774module_param(dolby_meta_with_el, uint, 0664);
5775MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
5776
5777#endif
5778
5779module_param(fast_output_enable, uint, 0664);
5780MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
5781
5782module_param(error_proc_policy, uint, 0664);
5783MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
5784
5785module_param(error_skip_count, uint, 0664);
5786MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
5787
5788module_param(force_sliding_margin, uint, 0664);
5789MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
5790
5791module_param(i_only_flag, uint, 0664);
5792MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
5793
5794module_param(first_i_policy, uint, 0664);
5795MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
5796
5797module_param(frmbase_cont_bitlevel, uint, 0664);
5798MODULE_PARM_DESC(frmbase_cont_bitlevel,
5799 "\n amvdec_h264 frmbase_cont_bitlevel\n");
5800
5801module_param(frmbase_cont_bitlevel2, uint, 0664);
5802MODULE_PARM_DESC(frmbase_cont_bitlevel2,
5803 "\n amvdec_h264 frmbase_cont_bitlevel\n");
5804
5805module_param(udebug_flag, uint, 0664);
5806MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
5807
5808module_param(udebug_pause_pos, uint, 0664);
5809MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
5810
5811module_param(udebug_pause_val, uint, 0664);
5812MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
5813
5814module_param(udebug_pause_decode_idx, uint, 0664);
5815MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
5816
5817module_param(max_alloc_buf_count, uint, 0664);
5818MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
5819
5820module_param(enable_itu_t35, uint, 0664);
5821MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
5822
5823module_param(mmu_enable, uint, 0664);
5824MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
5825
5826module_param(force_enable_mmu, uint, 0664);
5827MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
5828
5829/*
5830module_param(trigger_task, uint, 0664);
5831MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
5832*/
5833module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
5834
5835module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
5836
5837module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
5838
5839module_param_array(run_count, uint,
5840 &max_decode_instance_num, 0664);
5841
5842module_param_array(not_run_ready, uint,
5843 &max_decode_instance_num, 0664);
5844
5845module_param_array(input_empty, uint,
5846 &max_decode_instance_num, 0664);
5847
5848module_param_array(max_get_frame_interval, uint,
5849 &max_decode_instance_num, 0664);
5850
5851module_param_array(step, uint, &max_decode_instance_num, 0664);
5852
5853module_param(disp_vframe_valve_level, uint, 0664);
5854MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
5855module_init(ammvdec_h264_driver_init_module);
5856module_exit(ammvdec_h264_driver_remove_module);
5857
5858MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
5859MODULE_LICENSE("GPL");
5860
generated by cgit at 2024-05-19 21:22:38 (GMT)