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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
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1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64#include <media/v4l2-mem2mem.h>
65
66#undef pr_info
67#define pr_info printk
68#define VDEC_DW
69#define DEBUG_UCODE
70#define MEM_NAME "codec_m264"
71#define MULTI_INSTANCE_FRAMEWORK
72/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
73#include "h264_dpb.h"
74/* #define SEND_PARAM_WITH_REG */
75
76#define DRIVER_NAME "ammvdec_h264"
77#define MODULE_NAME "ammvdec_h264"
78#define DRIVER_HEADER_NAME "ammvdec_h264_header"
79
80#define CHECK_INTERVAL (HZ/100)
81
82#define SEI_DATA_SIZE (8*1024)
83#define SEI_ITU_DATA_SIZE (4*1024)
84
85#define RATE_MEASURE_NUM 8
86#define RATE_CORRECTION_THRESHOLD 5
87#define RATE_2397_FPS 4004 /* 23.97 */
88#define RATE_25_FPS 3840 /* 25 */
89#define RATE_2997_FPS 3203 /* 29.97 */
90#define DUR2PTS(x) ((x)*90/96)
91#define PTS2DUR(x) ((x)*96/90)
92#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
93#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
94
95#define FIX_FRAME_RATE_OFF 0
96#define FIX_FRAME_RATE_ON 1
97#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
98
99#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
100#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
101#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
102#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
103
104#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
105
106#define RATE_MEASURE_NUM 8
107#define RATE_CORRECTION_THRESHOLD 5
108#define RATE_24_FPS 4004 /* 23.97 */
109#define RATE_25_FPS 3840 /* 25 */
110#define DUR2PTS(x) ((x)*90/96)
111#define PTS2DUR(x) ((x)*96/90)
112#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
113#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
114
115#define H264_DEV_NUM 9
116
117#define CONSTRAIN_MAX_BUF_NUM
118
119#define H264_MMU
120#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
121#define INVALID_IDX -1 /* Invalid buffer index.*/
122
123static int mmu_enable;
124/*mmu do not support mbaff*/
125static int force_enable_mmu = 0;
126unsigned int h264_debug_flag; /* 0xa0000000; */
127unsigned int h264_debug_mask = 0xff;
128 /*
129 *h264_debug_cmd:
130 * 0x1xx, force decoder id of xx to be disconnected
131 */
132unsigned int h264_debug_cmd;
133
134static unsigned int dec_control =
135 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
136 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
137
138static unsigned int force_rate_streambase;
139static unsigned int force_rate_framebase;
140static unsigned int force_disp_bufspec_num;
141static unsigned int fixed_frame_rate_mode;
142static unsigned int error_recovery_mode_in;
143static int start_decode_buf_level = 0x4000;
144static int pre_decode_buf_level = 0x1000;
145static int stream_mode_start_num = 4;
146
147#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
148/*to make reorder size difference of bl and el not too big*/
149static unsigned int reorder_dpb_size_margin_dv = 16;
150#endif
151static unsigned int reorder_dpb_size_margin = 6;
152static unsigned int reference_buf_margin = 4;
153
154#ifdef CONSTRAIN_MAX_BUF_NUM
155static u32 run_ready_max_vf_only_num;
156static u32 run_ready_display_q_num;
157 /*0: not check
158 0xff: mDPB.size
159 */
160static u32 run_ready_max_buf_num = 0xff;
161#endif
162
163static u32 run_ready_min_buf_num = 2;
164
165#define VDEC_ASSIST_CANVAS_BLK32 0x5
166
167
168static unsigned int max_alloc_buf_count;
169static unsigned int decode_timeout_val = 100;
170static unsigned int errordata_timeout_val = 50;
171static unsigned int get_data_timeout_val = 2000;
172#if 1
173/* H264_DATA_REQUEST does not work, disable it,
174decode has error for data in none continuous address
175*/
176static unsigned int frame_max_data_packet;
177#else
178static unsigned int frame_max_data_packet = 8;
179#endif
180static unsigned int radr;
181static unsigned int rval;
182static u32 endian = 0xff0;
183
184/*
185 udebug_flag:
186 bit 0, enable ucode print
187 bit 1, enable ucode detail print
188 bit 3, disable ucode watchdog
189 bit [31:16] not 0, pos to dump lmem
190 bit 2, pop bits to lmem
191 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
192*/
193static u32 udebug_flag;
194/*
195 when udebug_flag[1:0] is not 0
196 udebug_pause_pos not 0,
197 pause position
198*/
199static u32 udebug_pause_pos;
200/*
201 when udebug_flag[1:0] is not 0
202 and udebug_pause_pos is not 0,
203 pause only when DEBUG_REG2 is equal to this val
204*/
205static u32 udebug_pause_val;
206
207static u32 udebug_pause_decode_idx;
208
209static unsigned int disp_vframe_valve_level;
210
211static unsigned int max_decode_instance_num = H264_DEV_NUM;
212static unsigned int decode_frame_count[H264_DEV_NUM];
213static unsigned int display_frame_count[H264_DEV_NUM];
214static unsigned int max_process_time[H264_DEV_NUM];
215static unsigned int max_get_frame_interval[H264_DEV_NUM];
216static unsigned int run_count[H264_DEV_NUM];
217static unsigned int input_empty[H264_DEV_NUM];
218static unsigned int not_run_ready[H264_DEV_NUM];
219static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
220{1, 1, 1, 1, 1, 1, 1, 1, 1};
221
222#define VDEC_CLOCK_ADJUST_FRAME 30
223static unsigned int clk_adj_frame_count;
224
225/*
226 *bit[3:0]: 0, run ; 1, pause; 3, step
227 *bit[4]: 1, schedule run
228 */
229static unsigned int step[H264_DEV_NUM];
230
231#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
232static u32 prefix_aux_buf_size = (16 * 1024);
233static u32 suffix_aux_buf_size;
234
235#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
236static u32 dv_toggle_prov_name;
237
238static u32 dolby_meta_with_el;
239#endif
240
241/*
242 bit[8]
243 0: use sys_info[bit 3]
244 not 0:use i_only_flag[7:0]
245 bit[7:0]:
246 bit 0, 1: only display I picture;
247 bit 1, 1: only decode I picture;
248*/
249static unsigned int i_only_flag;
250
251/*
252 error_proc_policy:
253 bit[0] send_error_frame_flag;
254 (valid when bit[31] is 1, otherwise use sysinfo)
255 bit[1] do not decode if config_decode_buf() fail
256 bit[2] force release buf if in deadlock
257 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
258 bit[4] check inactive of receiver
259 bit[5] reset buffmgr if in deadlock
260 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
261 bit[7] reset buffmgr if dpb error
262
263 bit[8] check total mbx/mby of decoded frame
264 bit[9] check ERROR_STATUS_REG
265 bit[10] check reference list
266 bit[11] mark error if dpb error
267 bit[12] i_only when error happen
268 bit[13] 0: mark error according to last pic, 1: ignore mark error
269 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
270*/
271static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
272
273
274/*
275 error_skip_count:
276 bit[11:0] error skip frame count
277 bit[15:12] error skip i picture count
278*/
279static unsigned int error_skip_count = (0x2 << 12) | 0x40;
280
281static unsigned int force_sliding_margin;
282/*
283 bit[1:0]:
284 0, start playing from any frame
285 1, start playing from I frame
286 bit[15:8]: the count of skip frames after first I
287 2, start playing from second I frame (decode from the first I)
288 bit[15:8]: the max count of skip frames after first I
289 3, start playing from IDR
290*/
291static unsigned int first_i_policy = 1;
292
293/*
294 fast_output_enable:
295 bit [0], output frame if there is IDR in list
296 bit [1], output frame if the current poc is 1 big than the previous poc
297 bit [2], if even poc only, output frame ifthe cuurent poc
298 is 2 big than the previous poc
299 bit [3], ip only
300*/
301static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
302
303static unsigned int enable_itu_t35 = 1;
304
305static unsigned int frmbase_cont_bitlevel = 0x40;
306
307static unsigned int frmbase_cont_bitlevel2 = 0x1;
308
309
310#define MH264_USERDATA_ENABLE
311
312/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
313/* hevc->double_write_mode:
314 0, no double write
315 1, 1:1 ratio
316 2, (1/4):(1/4) ratio
317 3, (1/4):(1/4) ratio, with both compressed frame included
318 4, (1/2):(1/2) ratio
319 0x10, double write only
320 0x10000: vdec dw horizotal 1/2
321 0x20000: vdec dw horizotal/vertical 1/2
322*/
323static u32 double_write_mode;
324static u32 without_display_mode;
325#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
326
327static void vmh264_dump_state(struct vdec_s *vdec);
328
329#define is_in_parsing_state(status) \
330 ((status == H264_ACTION_SEARCH_HEAD) || \
331 ((status & 0xf0) == 0x80))
332
333#define is_interlace(frame) \
334 (frame->frame &&\
335 frame->top_field &&\
336 frame->bottom_field &&\
337 (!frame->frame->coded_frame))
338static inline bool close_to(int a, int b, int m)
339{
340 return (abs(a - b) < m) ? true : false;
341}
342
343#if 0
344#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
345#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
346#else
347#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
348#define h264_free_hw_stru(dev, hw) vfree(hw)
349#endif
350
351/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
352#define NV21
353/* #endif */
354
355/* 12M for L41 */
356#define MAX_DPB_BUFF_SIZE (12*1024*1024)
357#define DEFAULT_MEM_SIZE (32*1024*1024)
358#define AVIL_DPB_BUFF_SIZE 0x01ec2000
359
360#define DEF_BUF_START_ADDR 0x01000000
361#define mem_sps_base 0x011c3c00
362#define mem_pps_base 0x011cbc00
363/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
364u32 V_BUF_ADDR_OFFSET = 0x200000;
365#define DCAC_READ_MARGIN (64 * 1024)
366
367
368#define EXTEND_SAR 0xff
369#define BUFSPEC_POOL_SIZE 64
370#define VF_POOL_SIZE 64
371#define VF_POOL_NUM 2
372#define MAX_VF_BUF_NUM 27
373#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
374#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
375#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
376#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
377#define EXTIF_BUF_SIZE (0x10000 * 2)
378
379#define HEADER_BUFFER_IDX(n) (n)
380#define VF_BUFFER_IDX(n) (n)
381
382
383#define PUT_INTERVAL (HZ/100)
384#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
385
386#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
387#define SWITCHING_STATE_OFF 0
388#define SWITCHING_STATE_ON_CMD3 1
389#define SWITCHING_STATE_ON_CMD1 2
390
391
392
393#define INCPTR(p) ptr_atomic_wrap_inc(&p)
394
395#define SLICE_TYPE_I 2
396#define SLICE_TYPE_P 5
397#define SLICE_TYPE_B 6
398
399struct buffer_spec_s {
400 /*
401 used:
402 -1, none allocated
403 0, allocated, free
404 1, used by dpb
405 2, in disp queue;
406 3, in disp queue, isolated,
407 do not use for dpb when vf_put;
408 4, to release
409 5, in disp queue, isolated (but not to release)
410 do not use for dpb when vf_put;
411 */
412 unsigned int used;
413 unsigned int info0;
414 unsigned int info1;
415 unsigned int info2;
416 unsigned int y_addr;
417 unsigned int u_addr;
418 unsigned int v_addr;
419
420 int y_canvas_index;
421 int u_canvas_index;
422 int v_canvas_index;
423
424#ifdef VDEC_DW
425 unsigned int vdec_dw_y_addr;
426 unsigned int vdec_dw_u_addr;
427 unsigned int vdec_dw_v_addr;
428
429 int vdec_dw_y_canvas_index;
430 int vdec_dw_u_canvas_index;
431 int vdec_dw_v_canvas_index;
432#ifdef NV21
433 struct canvas_config_s vdec_dw_canvas_config[2];
434#else
435 struct canvas_config_s vdec_dw_canvas_config[3];
436#endif
437#endif
438
439#ifdef NV21
440 struct canvas_config_s canvas_config[2];
441#else
442 struct canvas_config_s canvas_config[3];
443#endif
444 unsigned long cma_alloc_addr;
445 unsigned int buf_adr;
446#ifdef H264_MMU
447 unsigned long alloc_header_addr;
448#endif
449 char *aux_data_buf;
450 int aux_data_size;
451#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
452 unsigned char dv_enhance_exist;
453#endif
454 int canvas_pos;
455 int vf_ref;
456 /*unsigned int comp_body_size;*/
457 unsigned int dw_y_adr;
458 unsigned int dw_u_v_adr;
459};
460
461#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
462#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
463#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
464
465
466#define vdec_dw_spec2canvas(x) \
467 (((x)->vdec_dw_v_canvas_index << 16) | \
468 ((x)->vdec_dw_u_canvas_index << 8) | \
469 ((x)->vdec_dw_y_canvas_index << 0))
470
471
472#define spec2canvas(x) \
473 (((x)->v_canvas_index << 16) | \
474 ((x)->u_canvas_index << 8) | \
475 ((x)->y_canvas_index << 0))
476
477#define FRAME_INDEX(vf_index) (vf_index & 0xff)
478#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
479#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
480
481static struct vframe_s *vh264_vf_peek(void *);
482static struct vframe_s *vh264_vf_get(void *);
483static void vh264_vf_put(struct vframe_s *, void *);
484static int vh264_vf_states(struct vframe_states *states, void *);
485static int vh264_event_cb(int type, void *data, void *private_data);
486static void vh264_work(struct work_struct *work);
487static void vh264_timeout_work(struct work_struct *work);
488static void vh264_notify_work(struct work_struct *work);
489#ifdef MH264_USERDATA_ENABLE
490static void user_data_ready_notify_work(struct work_struct *work);
491static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
492#endif
493
494static const char vh264_dec_id[] = "vh264-dev";
495
496#define PROVIDER_NAME "vdec.h264"
497
498static const struct vframe_operations_s vf_provider_ops = {
499 .peek = vh264_vf_peek,
500 .get = vh264_vf_get,
501 .put = vh264_vf_put,
502 .event_cb = vh264_event_cb,
503 .vf_states = vh264_vf_states,
504};
505
506#define DEC_RESULT_NONE 0
507#define DEC_RESULT_DONE 1
508#define DEC_RESULT_AGAIN 2
509#define DEC_RESULT_CONFIG_PARAM 3
510#define DEC_RESULT_GET_DATA 4
511#define DEC_RESULT_GET_DATA_RETRY 5
512#define DEC_RESULT_ERROR 6
513#define DEC_RESULT_EOS 7
514#define DEC_RESULT_FORCE_EXIT 8
515
516/*
517 *static const char *dec_result_str[] = {
518 * "DEC_RESULT_NONE ",
519 * "DEC_RESULT_DONE ",
520 * "DEC_RESULT_AGAIN ",
521 * "DEC_RESULT_CONFIG_PARAM",
522 * "DEC_RESULT_GET_DATA ",
523 * "DEC_RESULT_GET_DA_RETRY",
524 * "DEC_RESULT_ERROR ",
525 *};
526 */
527
528#define UCODE_IP_ONLY 2
529#define UCODE_IP_ONLY_PARAM 1
530
531#define MC_OFFSET_HEADER 0x0000
532#define MC_OFFSET_DATA 0x1000
533#define MC_OFFSET_MMCO 0x2000
534#define MC_OFFSET_LIST 0x3000
535#define MC_OFFSET_SLICE 0x4000
536#define MC_OFFSET_MAIN 0x5000
537
538#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
539#define MC_SWAP_SIZE (4*SZ_1K)
540#define MODE_ERROR 0
541#define MODE_FULL 1
542
543#define DFS_HIGH_THEASHOLD 3
544
545#define INIT_FLAG_REG AV_SCRATCH_2
546#define HEAD_PADING_REG AV_SCRATCH_3
547#define UCODE_WATCHDOG_REG AV_SCRATCH_7
548#define LMEM_DUMP_ADR AV_SCRATCH_L
549#define DEBUG_REG1 AV_SCRATCH_M
550#define DEBUG_REG2 AV_SCRATCH_N
551#define FRAME_COUNTER_REG AV_SCRATCH_I
552#define RPM_CMD_REG AV_SCRATCH_A
553#define H264_DECODE_SIZE AV_SCRATCH_E
554#define H264_DECODE_MODE AV_SCRATCH_4
555#define H264_DECODE_SEQINFO AV_SCRATCH_5
556#define H264_AUX_ADR AV_SCRATCH_C
557#define H264_AUX_DATA_SIZE AV_SCRATCH_H
558
559#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
560#define DPB_STATUS_REG AV_SCRATCH_J
561#define ERROR_STATUS_REG AV_SCRATCH_9
562 /*
563 NAL_SEARCH_CTL: bit 0, enable itu_t35
564 NAL_SEARCH_CTL: bit 1, enable mmu
565 */
566#define NAL_SEARCH_CTL AV_SCRATCH_9
567#define MBY_MBX MB_MOTION_MODE /*0xc07*/
568
569#define DECODE_MODE_SINGLE 0x0
570#define DECODE_MODE_MULTI_FRAMEBASE 0x1
571#define DECODE_MODE_MULTI_STREAMBASE 0x2
572#define DECODE_MODE_MULTI_DVBAL 0x3
573#define DECODE_MODE_MULTI_DVENL 0x4
574static DEFINE_MUTEX(vmh264_mutex);
575
576
577
578#ifdef MH264_USERDATA_ENABLE
579
580struct mh264_userdata_record_t {
581 struct userdata_meta_info_t meta_info;
582 u32 rec_start;
583 u32 rec_len;
584};
585
586struct mh264_ud_record_wait_node_t {
587 struct list_head list;
588 struct mh264_userdata_record_t ud_record;
589};
590#define USERDATA_FIFO_NUM 256
591#define MAX_FREE_USERDATA_NODES 5
592
593struct mh264_userdata_info_t {
594 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
595 u8 *data_buf;
596 u8 *data_buf_end;
597 u32 buf_len;
598 u32 read_index;
599 u32 write_index;
600 u32 last_wp;
601};
602
603
604#endif
605
606struct vdec_h264_hw_s {
607 spinlock_t lock;
608 spinlock_t bufspec_lock;
609 int id;
610 struct platform_device *platform_dev;
611 unsigned long cma_alloc_addr;
612 /* struct page *collocate_cma_alloc_pages; */
613 unsigned long collocate_cma_alloc_addr;
614
615 u32 prefix_aux_size;
616 u32 suffix_aux_size;
617 void *aux_addr;
618 dma_addr_t aux_phy_addr;
619
620 /* buffer for store all sei data */
621 void *sei_data_buf;
622 u32 sei_data_len;
623
624 /* buffer for storing one itu35 recored */
625 void *sei_itu_data_buf;
626 u32 sei_itu_data_len;
627
628 /* recycle buffer for user data storing all itu35 records */
629 void *sei_user_data_buffer;
630 u32 sei_user_data_wp;
631#ifdef MH264_USERDATA_ENABLE
632 struct work_struct user_data_ready_work;
633#endif
634 struct StorablePicture *last_dec_picture;
635
636 ulong lmem_addr;
637 dma_addr_t lmem_addr_remap;
638
639 void *bmmu_box;
640#ifdef H264_MMU
641 void *mmu_box;
642 void *frame_mmu_map_addr;
643 dma_addr_t frame_mmu_map_phy_addr;
644 u32 hevc_cur_buf_idx;
645 u32 losless_comp_body_size;
646 u32 losless_comp_body_size_sao;
647 u32 losless_comp_header_size;
648 u32 mc_buffer_size_u_v;
649 u32 mc_buffer_size_u_v_h;
650 u32 is_idr_frame;
651 u32 is_new_pic;
652 u32 frame_done;
653 u32 frame_busy;
654 unsigned long extif_addr;
655 int double_write_mode;
656 int mmu_enable;
657#endif
658
659 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
660 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
661
662 int cur_pool;
663 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
664 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
665 struct vframe_s switching_fense_vf;
666 struct h264_dpb_stru dpb;
667 u8 init_flag;
668 u8 first_sc_checked;
669 u8 has_i_frame;
670 u8 config_bufmgr_done;
671 u32 max_reference_size;
672 u32 decode_pic_count;
673 u32 reflist_error_count;
674 int start_search_pos;
675 u32 reg_iqidct_control;
676 u32 reg_vcop_ctrl_reg;
677 u32 reg_rv_ai_mb_count;
678 u32 vld_dec_control;
679 struct vframe_s vframe_dummy;
680
681 unsigned char buffer_empty_flag;
682
683 u32 frame_width;
684 u32 frame_height;
685 u32 frame_dur;
686 u32 frame_prog;
687 u32 frame_packing_type;
688
689 struct vframe_chunk_s *chunk;
690
691 u32 stat;
692 unsigned long buf_start;
693 u32 buf_offset;
694 u32 buf_size;
695 /* u32 ucode_map_start; */
696 u32 pts_outside;
697 u32 sync_outside;
698 u32 vh264_ratio;
699 u32 vh264_rotation;
700 u32 use_idr_framerate;
701
702 u32 seq_info;
703 u32 seq_info2;
704 u32 video_signal_from_vui; /*to do .. */
705 u32 timing_info_present_flag;
706 u32 fixed_frame_rate_flag;
707 u32 bitstream_restriction_flag;
708 u32 num_reorder_frames;
709 u32 max_dec_frame_buffering;
710 u32 iframe_count;
711 u32 aspect_ratio_info;
712 u32 num_units_in_tick;
713 u32 time_scale;
714 u32 h264_ar;
715 bool h264_first_valid_pts_ready;
716 u32 h264pts1;
717 u32 h264pts2;
718 u32 pts_duration;
719 u32 h264_pts_count;
720 u32 duration_from_pts_done;
721 u32 pts_unstable;
722 u32 unstable_pts;
723 u32 last_checkout_pts;
724 u32 max_refer_buf;
725
726 s32 vh264_stream_switching_state;
727 struct vframe_s *p_last_vf;
728 u32 last_pts;
729 u32 last_pts_remainder;
730 u32 last_duration;
731 u32 last_mb_width, last_mb_height;
732 bool check_pts_discontinue;
733 bool pts_discontinue;
734 u32 wait_buffer_counter;
735 u32 first_offset;
736 u32 first_pts;
737 u64 first_pts64;
738 bool first_pts_cached;
739 u64 last_pts64;
740#if 0
741 void *sei_data_buffer;
742 dma_addr_t sei_data_buffer_phys;
743#endif
744
745 uint error_recovery_mode;
746 uint mb_total;
747 uint mb_width;
748 uint mb_height;
749
750 uint i_only;
751 int skip_frame_count;
752 bool no_poc_reorder_flag;
753 bool send_error_frame_flag;
754 dma_addr_t mc_dma_handle;
755 void *mc_cpu_addr;
756 int vh264_reset;
757
758 atomic_t vh264_active;
759
760 struct dec_sysinfo vh264_amstream_dec_info;
761
762 int dec_result;
763 struct work_struct work;
764 struct work_struct notify_work;
765 struct work_struct timeout_work;
766 void (*vdec_cb)(struct vdec_s *, void *);
767 void *vdec_cb_arg;
768
769 struct timer_list check_timer;
770
771 /**/
772 unsigned int last_frame_time;
773 u32 vf_pre_count;
774 u32 vf_get_count;
775 u32 vf_put_count;
776
777 /* timeout handle */
778 unsigned long int start_process_time;
779 unsigned int last_mby_mbx;
780 unsigned int last_vld_level;
781 unsigned int decode_timeout_count;
782 unsigned int timeout_num;
783 unsigned int search_dataempty_num;
784 unsigned int decode_timeout_num;
785 unsigned int decode_dataempty_num;
786 unsigned int buffer_empty_recover_num;
787
788 unsigned get_data_count;
789 unsigned get_data_start_time;
790 /**/
791
792 /*log*/
793 unsigned int packet_write_success_count;
794 unsigned int packet_write_EAGAIN_count;
795 unsigned int packet_write_ENOMEM_count;
796 unsigned int packet_write_EFAULT_count;
797 unsigned int total_read_size_pre;
798 unsigned int total_read_size;
799 unsigned int frame_count_pre;
800#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
801 u8 switch_dvlayer_flag;
802 u8 got_valid_nal;
803#endif
804 u8 eos;
805 u8 data_flag;
806 u32 no_error_count;
807 u32 no_error_i_count;
808 /*
809 NODISP_FLAG
810 */
811 u8 dec_flag;
812
813 u32 ucode_pause_pos;
814
815 u8 reset_bufmgr_flag;
816 u32 reset_bufmgr_count;
817 u32 cfg_param1;
818 u32 cfg_param2;
819 u32 cfg_param3;
820 u32 cfg_param4;
821 int valve_count;
822 u8 next_again_flag;
823 u32 pre_parser_wr_ptr;
824 struct firmware_s *fw;
825 struct firmware_s *fw_mmu;
826#ifdef MH264_USERDATA_ENABLE
827 /*user data*/
828 struct mutex userdata_mutex;
829 struct mh264_userdata_info_t userdata_info;
830 struct mh264_userdata_record_t ud_record;
831 int wait_for_udr_send;
832#endif
833 u32 no_mem_count;
834 u32 canvas_mode;
835 bool is_used_v4l;
836 void *v4l2_ctx;
837 bool v4l_params_parsed;
838 wait_queue_head_t wait_q;
839 u32 reg_g_status;
840 struct mutex chunks_mutex;
841 int need_cache_size;
842 u64 sc_start_time;
843 u8 frmbase_cont_flag;
844 struct vframe_qos_s vframe_qos;
845 int frameinfo_enable;
846 bool first_head_check_flag;
847 unsigned int height_aspect_ratio;
848 unsigned int width_aspect_ratio;
849 bool new_iframe_flag;
850 bool ref_err_flush_dpb_flag;
851 unsigned int first_i_policy;
852 u32 reorder_dpb_size_margin;
853 bool wait_reset_done_flag;
854};
855
856static u32 again_threshold;
857
858static void timeout_process(struct vdec_h264_hw_s *hw);
859static void dump_bufspec(struct vdec_h264_hw_s *hw,
860 const char *caller);
861static void h264_reconfig(struct vdec_h264_hw_s *hw);
862static void h264_reset_bufmgr(struct vdec_s *vdec);
863static void vh264_local_init(struct vdec_h264_hw_s *hw);
864static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
865static int vh264_stop(struct vdec_h264_hw_s *hw);
866static s32 vh264_init(struct vdec_h264_hw_s *hw);
867static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
868 u32 index);
869static void release_aux_data(struct vdec_h264_hw_s *hw,
870 int buf_spec_num);
871#ifdef ERROR_HANDLE_TEST
872static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
873#endif
874
875#define H265_PUT_SAO_4K_SET 0x03
876#define H265_ABORT_SAO_4K_SET 0x04
877#define H265_ABORT_SAO_4K_SET_DONE 0x05
878
879#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
880#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
881#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
882#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
883#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
884
885
886#define HEVC_CM_HEADER_START_ADDR 0x3628
887#define HEVC_CM_BODY_START_ADDR 0x3626
888#define HEVC_CM_BODY_LENGTH 0x3627
889#define HEVC_CM_HEADER_LENGTH 0x3629
890#define HEVC_CM_HEADER_OFFSET 0x362b
891#define HEVC_SAO_CTRL9 0x362d
892#define HEVCD_MPP_DECOMP_CTL3 0x34c4
893#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
894#define HEVC_DBLK_CFGB 0x350b
895#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
896
897#define H265_DW_NO_SCALE
898#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
899#define H265_LOSLESS_COMPRESS_MODE
900#define MAX_FRAME_4K_NUM 0x1200
901#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
902
903/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
904static u32 mem_map_mode = H265_MEM_MAP_MODE;
905
906#define MAX_SIZE_8K (8192 * 4608)
907#define MAX_SIZE_4K (4096 * 2304)
908
909static int is_oversize(int w, int h)
910{
911 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
912 MAX_SIZE_8K : MAX_SIZE_4K;
913
914 if (w < 0 || h < 0)
915 return true;
916
917 if (h != 0 && (w > max / h))
918 return true;
919
920 return false;
921}
922
923static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
924 int frame_type,
925 u32 vpts,
926 u32 vpts_valid);
927static int compute_losless_comp_body_size(int width,
928 int height, int bit_depth_10);
929static int compute_losless_comp_header_size(int width, int height);
930
931static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
932 int pic_width, int pic_height, u16 bit_depth,
933 unsigned int *mmu_index_adr) {
934 int cur_buf_idx;
935 int bit_depth_10 = (bit_depth != 0x00);
936 int picture_size;
937 u32 cur_mmu_4k_number;
938
939 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
940 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
941 picture_size = compute_losless_comp_body_size(pic_width,
942 pic_height, bit_depth_10);
943 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
944 dpb_print(DECODE_ID(hw),
945 PRINT_FLAG_MMU_DETAIL,
946 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
947 cur_buf_idx, picture_size, cur_mmu_4k_number);
948
949 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
950 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
951 cur_mmu_4k_number);
952 return -1;
953 }
954
955 return decoder_mmu_box_alloc_idx(
956 hw->mmu_box,
957 cur_buf_idx,
958 cur_mmu_4k_number,
959 mmu_index_adr);
960}
961
962static int compute_losless_comp_body_size(int width,
963 int height, int bit_depth_10)
964{
965 int width_x64;
966 int height_x32;
967 int bsize;
968
969 width_x64 = width + 63;
970 width_x64 >>= 6;
971
972 height_x32 = height + 31;
973 height_x32 >>= 5;
974
975#ifdef H264_MMU
976 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
977#else
978 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
979#endif
980 return bsize;
981}
982
983static int compute_losless_comp_header_size(int width, int height)
984{
985 int width_x64;
986 int width_x128;
987 int height_x64;
988 int hsize;
989
990 width_x64 = width + 63;
991 width_x64 >>= 6;
992
993 width_x128 = width + 127;
994 width_x128 >>= 7;
995
996 height_x64 = height + 63;
997 height_x64 >>= 6;
998
999#ifdef H264_MMU
1000 hsize = 128*width_x64*height_x64;
1001#else
1002 hsize = 32*width_x128*height_x64;
1003#endif
1004 return hsize;
1005}
1006
1007static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1008{
1009 int ratio = 1;
1010 int dw_mode = hw->double_write_mode;
1011 if ((dw_mode == 2) ||
1012 (dw_mode == 3))
1013 ratio = 4;
1014 else if (dw_mode == 4)
1015 ratio = 2;
1016 return ratio;
1017}
1018
1019
1020static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1021{
1022 int pic_width, pic_height;
1023 int lcu_size = 16;
1024 int dw_buf_size;
1025 u32 dw_buffer_size_u_v;
1026 u32 dw_buffer_size_u_v_h;
1027 int dw_mode = hw->double_write_mode;
1028
1029 pic_width = hw->frame_width;
1030 pic_height = hw->frame_height;
1031
1032 if (dw_mode) {
1033 int pic_width_dw = pic_width /
1034 get_double_write_ratio(hw);
1035 int pic_height_dw = pic_height /
1036 get_double_write_ratio(hw);
1037
1038 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1039 pic_width_dw / lcu_size + 1 :
1040 pic_width_dw / lcu_size;
1041 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1042 pic_height_dw / lcu_size + 1 :
1043 pic_height_dw / lcu_size;
1044 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1045
1046
1047 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1048 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1049 /*64k alignment*/
1050 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1051 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1052 } else {
1053 *pdw_buffer_size_u_v_h = 0;
1054 dw_buf_size = 0;
1055 }
1056
1057 return dw_buf_size;
1058}
1059
1060
1061static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1062{
1063 int i, size;
1064 u32 canvas_addr;
1065 unsigned long maddr;
1066 int num_buff = hw->dpb.mDPB.size;
1067 int dw_size = 0;
1068 u32 dw_buffer_size_u_v_h;
1069 u32 blkmode = hw->canvas_mode;
1070 int dw_mode = hw->double_write_mode;
1071
1072 canvas_addr = ANC0_CANVAS_ADDR;
1073 for (i = 0; i < num_buff; i++)
1074 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1075
1076 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1077 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1078
1079
1080 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1081 size += dw_size;
1082 if (size > 0)
1083 size += 0x10000;
1084
1085 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1086 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1087 dw_buffer_size_u_v_h, dw_size, size);
1088
1089 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1090 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1091 hw->losless_comp_body_size,
1092 hw->losless_comp_header_size,
1093 hw->losless_comp_body_size_sao);
1094
1095 for (i = 0; i < num_buff; i++) {
1096 if (!restore) {
1097 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1098 HEADER_BUFFER_IDX(i), size,
1099 DRIVER_HEADER_NAME, &maddr) < 0) {
1100 dpb_print(DECODE_ID(hw), 0,
1101 "%s malloc compress header failed %d\n",
1102 DRIVER_HEADER_NAME, i);
1103 return;
1104 }
1105 } else
1106 maddr = hw->buffer_spec[i].alloc_header_addr;
1107 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1108 hw->buffer_spec[i].alloc_header_addr = maddr;
1109 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1110 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1111 __func__, i, (u32)maddr, size);
1112
1113 if (dw_mode) {
1114 u32 addr;
1115 int canvas_w;
1116 int canvas_h;
1117
1118 canvas_w = hw->frame_width /
1119 get_double_write_ratio(hw);
1120 canvas_h = hw->frame_height /
1121 get_double_write_ratio(hw);
1122
1123 if (hw->canvas_mode == 0)
1124 canvas_w = ALIGN(canvas_w, 32);
1125 else
1126 canvas_w = ALIGN(canvas_w, 64);
1127 canvas_h = ALIGN(canvas_h, 32);
1128
1129 hw->buffer_spec[i].dw_y_adr =
1130 maddr + hw->losless_comp_header_size;
1131
1132 hw->buffer_spec[i].dw_y_adr =
1133 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1134 << 16;
1135 hw->buffer_spec[i].dw_u_v_adr =
1136 hw->buffer_spec[i].dw_y_adr
1137 + (dw_buffer_size_u_v_h << 16) * 2;
1138
1139
1140 hw->buffer_spec[i].buf_adr
1141 = hw->buffer_spec[i].dw_y_adr;
1142 addr = hw->buffer_spec[i].buf_adr;
1143
1144
1145 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1146 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1147 hw->buffer_spec[i].dw_y_adr,
1148 hw->buffer_spec[i].dw_u_v_adr,
1149 hw->buffer_spec[i].y_addr,
1150 hw->buffer_spec[i].u_addr,
1151 hw->buffer_spec[i].v_addr,
1152 canvas_w,
1153 canvas_h);
1154
1155 hw->buffer_spec[i].canvas_config[0].phy_addr =
1156 hw->buffer_spec[i].dw_y_adr;
1157 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1158 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1159 hw->buffer_spec[i].canvas_config[0].block_mode =
1160 blkmode;
1161 hw->buffer_spec[i].canvas_config[0].endian = 7;
1162
1163 hw->buffer_spec[i].canvas_config[1].phy_addr =
1164 hw->buffer_spec[i].dw_u_v_adr;
1165 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1166 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1167 hw->buffer_spec[i].canvas_config[1].block_mode =
1168 blkmode;
1169 hw->buffer_spec[i].canvas_config[1].endian = 7;
1170 }
1171 }
1172 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1173
1174 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1175 for (i = 0; i < 32; i++)
1176 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1177 return;
1178}
1179static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1180{
1181 u32 i;
1182 u32 ref_canv;
1183 struct Slice *pSlice = &(hw->dpb.mSlice);
1184 /*REFLIST[0]*/
1185 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1186 struct StorablePicture *ref = pSlice->listX[0][i];
1187 if (ref == NULL)
1188 return;
1189 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1190 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1191 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1192 (ref->buf_spec_num & 0x3f) << 8);
1193 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1194 }
1195 /*REFLIST[1]*/
1196 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1197 struct StorablePicture *ref = pSlice->listX[1][i];
1198 if (ref == NULL)
1199 return;
1200 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1201 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1202 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1203 (ref->buf_spec_num & 0x3f) << 8);
1204 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1205 }
1206 return;
1207}
1208
1209static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1210{
1211 u32 rdata32;
1212 u32 rdata32_2;
1213 u32 slice_type;
1214 struct StorablePicture *ref;
1215 struct Slice *pSlice;
1216 slice_type = hw->dpb.mSlice.slice_type;
1217 pSlice = &(hw->dpb.mSlice);
1218 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1219 if (slice_type == I_SLICE) {
1220 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1221 return;
1222 }
1223 if (slice_type == B_SLICE) {
1224 ref = pSlice->listX[0][0];
1225 if (ref == NULL)
1226 return;
1227 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1228 ((ref->buf_spec_num & 0x3f) << 8));
1229 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1230 rdata32 = rdata32 & 0xffff;
1231 rdata32 = rdata32 | (rdata32 << 16);
1232 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1233
1234 ref = pSlice->listX[1][0];
1235 if (ref == NULL)
1236 return;
1237 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1238 ((ref->buf_spec_num & 0x3f) << 8));
1239 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1240 rdata32_2 = rdata32_2 & 0xffff;
1241 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1242 if (rdata32 == rdata32_2) {
1243 ref = pSlice->listX[1][1];
1244 if (ref == NULL)
1245 return;
1246 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1247 ((ref->buf_spec_num & 0x3f) << 8));
1248 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1249 rdata32_2 = rdata32_2 & 0xffff;
1250 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1251 }
1252 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1253 } else { /*P-PIC*/
1254 ref = pSlice->listX[0][0];
1255 if (ref == NULL)
1256 return;
1257 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1258 ((ref->buf_spec_num & 0x3f) << 8));
1259 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1260 rdata32 = rdata32 & 0xffff;
1261 rdata32 = rdata32 | (rdata32 << 16);
1262 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1263
1264 ref = pSlice->listX[0][1];
1265 if (ref == NULL)
1266 return;
1267 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1268 ((ref->buf_spec_num & 0x3f) << 8));
1269 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1270 rdata32 = rdata32 & 0xffff;
1271 rdata32 = rdata32 | (rdata32 << 16);
1272 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1273 }
1274 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1275 return;
1276}
1277
1278
1279static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1280 u32 width, u32 height) {
1281 u32 data32;
1282 u32 lcu_x_num, lcu_y_num;
1283 u32 lcu_total;
1284 u32 mc_buffer_size_u_v;
1285 u32 mc_buffer_size_u_v_h;
1286 int dw_mode = hw->double_write_mode;
1287
1288 lcu_x_num = (width + 15) >> 4;
1289 lcu_y_num = (height + 15) >> 4;
1290 lcu_total = lcu_x_num * lcu_y_num;
1291
1292 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1293 hw->mc_buffer_size_u_v_h =
1294 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1295
1296 hw->losless_comp_body_size = 0;
1297
1298 hw->losless_comp_body_size_sao =
1299 compute_losless_comp_body_size(width, height, 0);
1300 hw->losless_comp_header_size =
1301 compute_losless_comp_header_size(width, height);
1302
1303 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1304 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1305
1306 /* setup lcu_size = 16*/
1307 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1308 /*pic_width/pic_height*/
1309 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1310 (height & 0xffff) << 16 | (width & 0xffff));
1311 /* bitdepth_luma = 8*/
1312 /* bitdepth_chroma = 8*/
1313 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1314
1315#ifdef H265_LOSLESS_COMPRESS_MODE
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1317 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1318#else
1319 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1320#endif
1321 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1322 data32 &= (~0x30);
1323 data32 |= (hw->canvas_mode << 4);
1324 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1325
1326 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1327 (0x80 << 20) | (0x80 << 10) | (0xff));
1328
1329 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1330
1331 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1332 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1333 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1334 /* ipp_enable*/
1335 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1336
1337 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1338 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1339 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1340 if (dw_mode)
1341 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1342 else
1343 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1344 }
1345
1346 data32 = READ_VREG(HEVC_SAO_CTRL0);
1347 data32 &= (~0xf);
1348 data32 |= 0x4;
1349 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1350 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1351 (width & 0xffff));
1352 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1353
1354 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1355 data32 = (lcu_x_num | lcu_y_num << 16);
1356 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1357 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1358 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1359 data32 = (mc_buffer_size_u_v_h << 16);
1360 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1361
1362 data32 = READ_VREG(HEVC_SAO_CTRL1);
1363 data32 &= (~0x3000);
1364 data32 &= (~0xff0);
1365 data32 |= endian; /* Big-Endian per 64-bit */
1366
1367 if (hw->mmu_enable && dw_mode)
1368 data32 |= ((hw->canvas_mode << 12));
1369 else
1370 data32 |= ((hw->canvas_mode << 12)|2);
1371
1372 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1373
1374#ifdef H265_DW_NO_SCALE
1375 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1376 if (hw->mmu_enable && dw_mode) {
1377 data32 = READ_VREG(HEVC_SAO_CTRL5);
1378 data32 &= (~(0xff << 16));
1379 if (dw_mode == 2 ||
1380 dw_mode == 3)
1381 data32 |= (0xff<<16);
1382 else if (dw_mode == 4)
1383 data32 |= (0x33<<16);
1384 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1385 }
1386
1387
1388#endif
1389
1390
1391#ifdef H265_LOSLESS_COMPRESS_MODE
1392 data32 = READ_VREG(HEVC_SAO_CTRL5);
1393 data32 |= (1<<9); /*8-bit smem-mode*/
1394 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1395
1396 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1397 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1398 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1399#endif
1400
1401#ifdef H265_LOSLESS_COMPRESS_MODE
1402 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1403 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1404#endif
1405
1406 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1407
1408 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1409
1410 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1411 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1412 return;
1413}
1414
1415static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1416 u32 is_new_pic, u32 is_idr)
1417{
1418 hw->is_new_pic = is_new_pic;
1419 hw->is_idr_frame = is_idr;
1420 return;
1421}
1422
1423static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1424 struct StorablePicture *pic) {
1425 u32 mc_y_adr;
1426 u32 mc_u_v_adr;
1427 u32 dw_y_adr;
1428 u32 dw_u_v_adr;
1429 u32 canvas_addr;
1430 int ret;
1431 int dw_mode = hw->double_write_mode;
1432 if (hw->is_new_pic != 1)
1433 return;
1434
1435 if (hw->is_idr_frame) {
1436 /* William TBD */
1437 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1438 }
1439
1440 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1441 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1442 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1443 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1444 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1445 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1446 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1447 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1448 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1449
1450
1451 if (dw_mode) {
1452 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1453 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1454 } else {
1455 dw_y_adr = 0;
1456 dw_u_v_adr = 0;
1457 }
1458#ifdef H265_LOSLESS_COMPRESS_MODE
1459 if (dw_mode)
1460 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1461 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1462#ifdef H264_MMU
1463 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1464#else
1465 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1466 (mc_y_adr + hw->losless_comp_body_size));
1467#endif
1468#else
1469 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1470#endif
1471
1472#ifndef H265_LOSLESS_COMPRESS_MODE
1473 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1474#else
1475 if (dw_mode)
1476 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1477#endif
1478
1479#ifndef LOSLESS_COMPRESS_MODE
1480 if (dw_mode) {
1481 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1482 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1483 }
1484#else
1485 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1486 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1487#endif
1488
1489 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1490 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1491 hw->frame_mmu_map_addr);
1492 if (ret != 0) {
1493 dpb_print(DECODE_ID(hw),
1494 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1495 pic->buf_spec_num,
1496 ret);
1497 return;
1498 }
1499
1500 /*Reset SAO + Enable SAO slice_start*/
1501 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1502 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1503 WRITE_VREG(HEVC_SAO_INT_STATUS,
1504 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1505 WRITE_VREG(HEVC_SAO_INT_STATUS,
1506 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1507 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1508 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1509
1510 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1511 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1512 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1513 } else
1514 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1515 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1516 hw->frame_busy = 1;
1517 return;
1518}
1519
1520
1521static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1522 u32 buf_spec_num) {
1523 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1524 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1525 dpb_print(DECODE_ID(hw),
1526 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1527 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1528 return;
1529}
1530
1531
1532static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1533{
1534 ulong timeout = jiffies + HZ;
1535 dpb_print(DECODE_ID(hw),
1536 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1537 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1538 if (time_after(jiffies, timeout)) {
1539 dpb_print(DECODE_ID(hw),
1540 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1541 break;
1542 }
1543 }
1544 timeout = jiffies + HZ;
1545 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1546 if (time_after(jiffies, timeout)) {
1547 dpb_print(DECODE_ID(hw),
1548 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1549 break;
1550 }
1551 }
1552 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1553 hw->frame_done = 1;
1554 return;
1555}
1556
1557static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1558{
1559 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1560 if (p_H264_Dpb->mVideo.dec_picture) {
1561 release_picture(p_H264_Dpb,
1562 p_H264_Dpb->mVideo.dec_picture);
1563 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1564 p_H264_Dpb->mVideo.dec_picture = NULL;
1565 if (hw->mmu_enable)
1566 hevc_set_frame_done(hw);
1567 }
1568}
1569
1570static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1571{
1572 ulong timeout = jiffies + HZ;
1573 dpb_print(DECODE_ID(hw),
1574 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1575 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1576 if (time_after(jiffies, timeout)) {
1577 dpb_print(DECODE_ID(hw),
1578 PRINT_FLAG_MMU_DETAIL,
1579 "hevc_sao_wait_done...wait timeout!\n");
1580 break;
1581 }
1582 }
1583 timeout = jiffies + HZ;
1584 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1585 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1586 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1587 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1588 H265_ABORT_SAO_4K_SET_DONE) {
1589 if (time_after(jiffies, timeout)) {
1590 dpb_print(DECODE_ID(hw),
1591 PRINT_FLAG_MMU_DETAIL,
1592 "wait h265_abort_sao_4k_set_done timeout!\n");
1593 break;
1594 }
1595 }
1596 }
1597 amhevc_stop();
1598 hw->frame_busy = 0;
1599 hw->frame_done = 0;
1600 dpb_print(DECODE_ID(hw),
1601 PRINT_FLAG_MMU_DETAIL,
1602 "sao wait done ,hevc stop!\n");
1603 }
1604 return;
1605}
1606static void buf_spec_init(struct vdec_h264_hw_s *hw)
1607{
1608 int i;
1609 unsigned long flags;
1610 spin_lock_irqsave(&hw->bufspec_lock, flags);
1611 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1612 hw->buffer_spec[i].used = -1;
1613 hw->buffer_spec[i].canvas_pos = -1;
1614 }
1615 if (dpb_is_debug(DECODE_ID(hw),
1616 PRINT_FLAG_DUMP_BUFSPEC))
1617 dump_bufspec(hw, __func__);
1618 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1619}
1620
1621/*is active in buf management */
1622static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1623 int buf_spec_num)
1624{
1625 unsigned char ret = 0;
1626 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1627 hw->buffer_spec[buf_spec_num].used == 2 ||
1628 hw->buffer_spec[buf_spec_num].used == 3 ||
1629 hw->buffer_spec[buf_spec_num].used == 5)
1630 ret = 1;
1631 return ret;
1632}
1633
1634static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1635 int buf_spec_num)
1636{
1637 unsigned char ret = 0;
1638 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1639 hw->buffer_spec[buf_spec_num].used == 3 ||
1640 hw->buffer_spec[buf_spec_num].used == 5)
1641 ret = 1;
1642 return ret;
1643}
1644
1645static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1646{
1647 if (hw->mmu_enable) {
1648 if (hw->buffer_spec[i].alloc_header_addr)
1649 return 0;
1650 else
1651 return -1;
1652 } else {
1653
1654 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1655 int addr;
1656#ifdef VDEC_DW
1657 int orig_buf_size;
1658 orig_buf_size = buf_size;
1659 if (IS_VDEC_DW(hw) == 1)
1660 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1661 else if (IS_VDEC_DW(hw) == 2)
1662 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1663#endif
1664 if (hw->buffer_spec[i].cma_alloc_addr)
1665 return 0;
1666
1667 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1668 PAGE_ALIGN(buf_size), DRIVER_NAME,
1669 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1670 hw->buffer_spec[i].cma_alloc_addr = 0;
1671 if (hw->no_mem_count++ > 3) {
1672 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1673 hw->reset_bufmgr_flag = 1;
1674 }
1675 dpb_print(DECODE_ID(hw), 0,
1676 "%s, fail to alloc buf for bufspec%d, try later\n",
1677 __func__, i
1678 );
1679 return -1;
1680 } else {
1681 hw->no_mem_count = 0;
1682 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1683 }
1684
1685 hw->buffer_spec[i].buf_adr =
1686 hw->buffer_spec[i].cma_alloc_addr;
1687 addr = hw->buffer_spec[i].buf_adr;
1688
1689
1690 hw->buffer_spec[i].y_addr = addr;
1691 addr += hw->mb_total << 8;
1692 hw->buffer_spec[i].u_addr = addr;
1693 hw->buffer_spec[i].v_addr = addr;
1694 addr += hw->mb_total << 7;
1695
1696 hw->buffer_spec[i].canvas_config[0].phy_addr =
1697 hw->buffer_spec[i].y_addr;
1698 hw->buffer_spec[i].canvas_config[0].width =
1699 hw->mb_width << 4;
1700 hw->buffer_spec[i].canvas_config[0].height =
1701 hw->mb_height << 4;
1702 hw->buffer_spec[i].canvas_config[0].block_mode =
1703 hw->canvas_mode;
1704
1705 hw->buffer_spec[i].canvas_config[1].phy_addr =
1706 hw->buffer_spec[i].u_addr;
1707 hw->buffer_spec[i].canvas_config[1].width =
1708 hw->mb_width << 4;
1709 hw->buffer_spec[i].canvas_config[1].height =
1710 hw->mb_height << 3;
1711 hw->buffer_spec[i].canvas_config[1].block_mode =
1712 hw->canvas_mode;
1713 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1714 "%s, alloc buf for bufspec%d\n",
1715 __func__, i
1716 );
1717#ifdef VDEC_DW
1718
1719 if (!IS_VDEC_DW(hw))
1720 return 0;
1721 else if (IS_VDEC_DW(hw) == 1) {
1722 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1723 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1724 addr += hw->mb_total << 7;
1725 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1726 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1727 addr += hw->mb_total << 6;
1728
1729 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1730 hw->buffer_spec[i].vdec_dw_y_addr;
1731 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1732 hw->mb_width << 3;
1733 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1734 hw->mb_height << 4;
1735 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1736 CANVAS_BLKMODE_32X32;
1737
1738 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1739 hw->buffer_spec[i].vdec_dw_u_addr;
1740 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1741 hw->mb_width << 3;
1742 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1743 hw->mb_height << 3;
1744 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1745 CANVAS_BLKMODE_32X32;
1746 }else {
1747 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1748 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1749 addr += hw->mb_total << 6;
1750 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1751 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1752 addr += hw->mb_total << 5;
1753
1754 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1755 hw->buffer_spec[i].vdec_dw_y_addr;
1756 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1757 hw->mb_width << 3;
1758 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1759 hw->mb_height << 3;
1760 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1761 CANVAS_BLKMODE_32X32;
1762
1763 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1764 hw->buffer_spec[i].vdec_dw_u_addr;
1765 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1766 hw->mb_width << 3;
1767 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1768 hw->mb_height << 2;
1769 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1770 CANVAS_BLKMODE_32X32;
1771 }
1772 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1773 "%s, vdec_dw: alloc buf for bufspec%d\n",
1774 __func__, i
1775 );
1776#endif
1777 }
1778 return 0;
1779}
1780
1781static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1782{
1783 int ret = 0;
1784 struct aml_vcodec_ctx *ctx = NULL;
1785 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1786 struct canvas_config_s *y_canvas_cfg = NULL;
1787 struct canvas_config_s *c_canvas_cfg = NULL;
1788 struct vdec_v4l2_buffer *fb = NULL;
1789 unsigned int y_addr = 0, c_addr = 0;
1790
1791 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1792 pr_err("the v4l context has err.\n");
1793 return -1;
1794 }
1795
1796 if (bs->cma_alloc_addr)
1797 return 0;
1798
1799 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1800 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1801 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1802 ctx->id, __func__,
1803 (hw->mb_total << 8) + (hw->mb_total << 7));
1804
1805 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1806 if (ret < 0) {
1807 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1808 "[%d] get fb fail.\n", ctx->id);
1809 return ret;
1810 }
1811
1812 bs->cma_alloc_addr = (unsigned long)fb;
1813 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1814 "[%d] %s(), cma alloc addr: 0x%x\n",
1815 ctx->id, __func__, bs->cma_alloc_addr);
1816
1817 if (fb->num_planes == 1) {
1818 y_addr = fb->m.mem[0].addr;
1819 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1820 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1821 } else if (fb->num_planes == 2) {
1822 y_addr = fb->m.mem[0].addr;
1823 c_addr = fb->m.mem[1].addr;
1824 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1825 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1826 }
1827
1828 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1829 "[%d] %s(), y_addr: %x, size: %u\n",
1830 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1831 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1832 "[%d] %s(), c_addr: %x, size: %u\n",
1833 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1834
1835 bs->y_addr = y_addr;
1836 bs->u_addr = c_addr;
1837 bs->v_addr = c_addr;
1838
1839 y_canvas_cfg = &bs->canvas_config[0];
1840 c_canvas_cfg = &bs->canvas_config[1];
1841
1842 y_canvas_cfg->phy_addr = y_addr;
1843 y_canvas_cfg->width = hw->mb_width << 4;
1844 y_canvas_cfg->height = hw->mb_height << 4;
1845 y_canvas_cfg->block_mode = hw->canvas_mode;
1846 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1847 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1848 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1849 y_canvas_cfg->width,y_canvas_cfg->height);
1850
1851 c_canvas_cfg->phy_addr = c_addr;
1852 c_canvas_cfg->width = hw->mb_width << 4;
1853 c_canvas_cfg->height = hw->mb_height << 3;
1854 c_canvas_cfg->block_mode = hw->canvas_mode;
1855 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1856 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1857 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1858 c_canvas_cfg->width, c_canvas_cfg->height);
1859
1860 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1861 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1862
1863 return ret;
1864}
1865
1866static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1867{
1868 int blkmode = hw->canvas_mode;
1869 int endian = 0;
1870
1871 if (blkmode == CANVAS_BLKMODE_LINEAR) {
1872 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1873 endian = 7;
1874 else
1875 endian = 0;
1876 }
1877
1878 if (hw->is_used_v4l)
1879 endian = 7;
1880
1881 canvas_config_ex(hw->buffer_spec[i].
1882 y_canvas_index,
1883 hw->buffer_spec[i].y_addr,
1884 hw->mb_width << 4,
1885 hw->mb_height << 4,
1886 CANVAS_ADDR_NOWRAP,
1887 blkmode,
1888 endian);
1889
1890 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1891 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1892 (1 << 11) | /* canvas_blk32_wr */
1893 (blkmode << 10) | /* canvas_blk32*/
1894 (1 << 8) | /* canvas_index_wr*/
1895 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1896 );
1897 }
1898
1899 canvas_config_ex(hw->buffer_spec[i].
1900 u_canvas_index,
1901 hw->buffer_spec[i].u_addr,
1902 hw->mb_width << 4,
1903 hw->mb_height << 3,
1904 CANVAS_ADDR_NOWRAP,
1905 blkmode,
1906 endian);
1907
1908 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1909 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1910 (1 << 11) |
1911 (blkmode << 10) |
1912 (1 << 8) |
1913 (hw->buffer_spec[i].u_canvas_index << 0));
1914 }
1915
1916 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1917 spec2canvas(&hw->buffer_spec[i]));
1918
1919
1920#ifdef VDEC_DW
1921 if (!IS_VDEC_DW(hw))
1922 return;
1923 else if (IS_VDEC_DW(hw) == 1) {
1924 canvas_config_ex(hw->buffer_spec[i].
1925 vdec_dw_y_canvas_index,
1926 hw->buffer_spec[i].vdec_dw_y_addr,
1927 hw->mb_width << 3,
1928 hw->mb_height << 4,
1929 CANVAS_ADDR_NOWRAP,
1930 blkmode,
1931 endian);
1932 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1933 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1934 (1 << 11) |
1935 (blkmode << 10) |
1936 (1 << 8) |
1937 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1938 }
1939 canvas_config_ex(hw->buffer_spec[i].
1940 vdec_dw_u_canvas_index,
1941 hw->buffer_spec[i].vdec_dw_u_addr,
1942 hw->mb_width << 3,
1943 hw->mb_height << 3,
1944 CANVAS_ADDR_NOWRAP,
1945 blkmode,
1946 endian);
1947 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1948 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1949 (1 << 11) |
1950 (blkmode << 10) |
1951 (1 << 8) |
1952 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1953 }
1954 } else {
1955 canvas_config_ex(hw->buffer_spec[i].
1956 vdec_dw_y_canvas_index,
1957 hw->buffer_spec[i].vdec_dw_y_addr,
1958 hw->mb_width << 3,
1959 hw->mb_height << 3,
1960 CANVAS_ADDR_NOWRAP,
1961 blkmode,
1962 endian);
1963 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1964 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1965 (1 << 11) |
1966 (blkmode << 10) |
1967 (1 << 8) |
1968 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1969 }
1970
1971 canvas_config_ex(hw->buffer_spec[i].
1972 vdec_dw_u_canvas_index,
1973 hw->buffer_spec[i].vdec_dw_u_addr,
1974 hw->mb_width << 3,
1975 hw->mb_height << 2,
1976 CANVAS_ADDR_NOWRAP,
1977 blkmode,
1978 endian);
1979 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1980 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1981 (1 << 11) |
1982 (blkmode << 10) |
1983 (1 << 8) |
1984 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1985 }
1986 }
1987#endif
1988}
1989
1990static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1991{
1992 u32 blkmode = hw->canvas_mode;
1993 int canvas_w;
1994 int canvas_h;
1995
1996 canvas_w = hw->frame_width /
1997 get_double_write_ratio(hw);
1998 canvas_h = hw->frame_height /
1999 get_double_write_ratio(hw);
2000
2001 if (hw->canvas_mode == 0)
2002 canvas_w = ALIGN(canvas_w, 32);
2003 else
2004 canvas_w = ALIGN(canvas_w, 64);
2005 canvas_h = ALIGN(canvas_h, 32);
2006
2007 canvas_config_ex(hw->buffer_spec[i].
2008 y_canvas_index,
2009 hw->buffer_spec[i].dw_y_adr,
2010 canvas_w,
2011 canvas_h,
2012 CANVAS_ADDR_NOWRAP,
2013 blkmode,
2014 7);
2015
2016 canvas_config_ex(hw->buffer_spec[i].
2017 u_canvas_index,
2018 hw->buffer_spec[i].dw_u_v_adr,
2019 canvas_w,
2020 canvas_h,
2021 CANVAS_ADDR_NOWRAP,
2022 blkmode,
2023 7);
2024}
2025
2026
2027int get_free_buf_idx(struct vdec_s *vdec)
2028{
2029 int i;
2030 unsigned long addr, flags;
2031 int index = -1;
2032 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2033 int buf_total = BUFSPEC_POOL_SIZE;
2034
2035 if (hw->is_used_v4l)
2036 buf_total = hw->dpb.mDPB.size;
2037
2038 spin_lock_irqsave(&hw->bufspec_lock, flags);
2039 /*hw->start_search_pos = 0;*/
2040 for (i = hw->start_search_pos; i < buf_total; i++) {
2041 if (hw->mmu_enable)
2042 addr = hw->buffer_spec[i].alloc_header_addr;
2043 else {
2044 addr = hw->buffer_spec[i].cma_alloc_addr;
2045 if (hw->is_used_v4l && !addr) {
2046 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2047 config_decode_canvas(hw, i);
2048 addr = hw->buffer_spec[i].cma_alloc_addr;
2049 }
2050 }
2051 }
2052 if (hw->buffer_spec[i].used == 0 && addr) {
2053 hw->buffer_spec[i].used = 1;
2054 hw->start_search_pos = i+1;
2055 index = i;
2056 break;
2057 }
2058 }
2059 if (index < 0) {
2060 for (i = 0; i < hw->start_search_pos; i++) {
2061 if (hw->mmu_enable)
2062 addr = hw->buffer_spec[i].alloc_header_addr;
2063 else {
2064 addr = hw->buffer_spec[i].cma_alloc_addr;
2065 if (hw->is_used_v4l && !addr) {
2066 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2067 config_decode_canvas(hw, i);
2068 addr = hw->buffer_spec[i].cma_alloc_addr;
2069 }
2070 }
2071 }
2072 if (hw->buffer_spec[i].used == 0 && addr) {
2073 hw->buffer_spec[i].used = 1;
2074 hw->start_search_pos = i+1;
2075 index = i;
2076 break;
2077 }
2078 }
2079 }
2080 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2081 if (hw->start_search_pos >= buf_total)
2082 hw->start_search_pos = 0;
2083 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2084 "%s, buf_spec_num %d\n", __func__, index);
2085
2086 if (index < 0) {
2087 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2088 "%s fail\n", __func__);
2089 vmh264_dump_state(vdec);
2090 }
2091
2092 if (dpb_is_debug(DECODE_ID(hw),
2093 PRINT_FLAG_DUMP_BUFSPEC))
2094 dump_bufspec(hw, __func__);
2095 return index;
2096}
2097
2098int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2099{
2100 /*u32 cur_buf_idx;*/
2101 unsigned long flags;
2102 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2103 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2104 "%s buf_spec_num %d used %d\n",
2105 __func__, buf_spec_num,
2106 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2107 if (buf_spec_num >= 0 &&
2108 buf_spec_num < BUFSPEC_POOL_SIZE
2109 ) {
2110 spin_lock_irqsave(&hw->bufspec_lock, flags);
2111 hw->buffer_spec[buf_spec_num].used = 0;
2112 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2113 if (hw->mmu_enable) {
2114 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2115 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2116 cur_buf_idx = cur_buf_idx&0xff;*/
2117 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2118 }
2119 release_aux_data(hw, buf_spec_num);
2120 }
2121 if (dpb_is_debug(DECODE_ID(hw),
2122 PRINT_FLAG_DUMP_BUFSPEC))
2123 dump_bufspec(hw, __func__);
2124 return 0;
2125}
2126
2127static void config_buf_specs(struct vdec_s *vdec)
2128{
2129 int i, j;
2130 unsigned long flags;
2131 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2132 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2133
2134 spin_lock_irqsave(&hw->bufspec_lock, flags);
2135 for (i = 0, j = 0;
2136 j < hw->dpb.mDPB.size
2137 && i < BUFSPEC_POOL_SIZE;
2138 i++) {
2139 int canvas;
2140 if (hw->buffer_spec[i].used != -1)
2141 continue;
2142 if (vdec->parallel_dec == 1) {
2143 if (hw->buffer_spec[i].y_canvas_index == -1)
2144 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2145 if (hw->buffer_spec[i].u_canvas_index == -1) {
2146 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2147 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2148 }
2149#ifdef VDEC_DW
2150 if (IS_VDEC_DW(hw)) {
2151 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2152 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2153 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2154 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2155 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2156 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2157 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2158 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2159 }
2160 }
2161#endif
2162 } else {
2163 canvas = vdec->get_canvas(j * mode, 2);
2164 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2165 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2166 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2167 dpb_print(DECODE_ID(hw),
2168 PRINT_FLAG_DPB_DETAIL,
2169 "config canvas (%d) %x for bufspec %d\r\n",
2170 j, canvas, i);
2171#ifdef VDEC_DW
2172 if (IS_VDEC_DW(hw)) {
2173 canvas = vdec->get_canvas(j * mode + 1, 2);
2174 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2175 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2176 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2177 dpb_print(DECODE_ID(hw),
2178 PRINT_FLAG_DPB_DETAIL,
2179 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2180 j, canvas, i);
2181 }
2182#endif
2183 }
2184
2185 hw->buffer_spec[i].used = 0;
2186 hw->buffer_spec[i].canvas_pos = j;
2187
2188
2189 j++;
2190 }
2191 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2192}
2193
2194static void config_buf_specs_ex(struct vdec_s *vdec)
2195{
2196 int i, j;
2197 unsigned long flags;
2198 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2199 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2200
2201 spin_lock_irqsave(&hw->bufspec_lock, flags);
2202 for (i = 0, j = 0;
2203 j < hw->dpb.mDPB.size
2204 && i < BUFSPEC_POOL_SIZE;
2205 i++) {
2206 int canvas = 0;
2207 if (hw->buffer_spec[i].used != -1)
2208 continue;
2209 if (vdec->parallel_dec == 1) {
2210 if (hw->buffer_spec[i].y_canvas_index == -1)
2211 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2212 if (hw->buffer_spec[i].u_canvas_index == -1) {
2213 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2214 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2215 }
2216#ifdef VDEC_DW
2217 if (IS_VDEC_DW(hw)) {
2218 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2219 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2220 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2221 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2222 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2223 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2224 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2225 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2226 }
2227 }
2228#endif
2229 } else {
2230 canvas = vdec->get_canvas(j* mode, 2);
2231 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2232 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2233 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2234
2235 dpb_print(DECODE_ID(hw),
2236 PRINT_FLAG_DPB_DETAIL,
2237 "config canvas (%d) %x for bufspec %d\r\n",
2238 j, canvas, i);
2239#ifdef VDEC_DW
2240 if (IS_VDEC_DW(hw)) {
2241 canvas = vdec->get_canvas(j*mode + 1, 2);
2242 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2243 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2244 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2245 dpb_print(DECODE_ID(hw),
2246 PRINT_FLAG_DPB_DETAIL,
2247 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2248 j, canvas, i);
2249 }
2250#endif
2251 }
2252
2253 hw->buffer_spec[i].used = 0;
2254 hw->buffer_spec[i].alloc_header_addr = 0;
2255 hw->buffer_spec[i].canvas_pos = j;
2256
2257 j++;
2258 }
2259 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2260}
2261
2262
2263static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2264 unsigned char release_all)
2265{
2266 int i;
2267 unsigned long flags;
2268 unsigned char dealloc_flag = 0;
2269 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2270 if (hw->buffer_spec[i].used == 4 ||
2271 release_all) {
2272 dealloc_flag = 1;
2273 dpb_print(DECODE_ID(hw),
2274 PRINT_FLAG_DPB_DETAIL,
2275 "%s buf_spec_num %d\n",
2276 __func__, i
2277 );
2278 spin_lock_irqsave
2279 (&hw->bufspec_lock, flags);
2280 hw->buffer_spec[i].used = -1;
2281 spin_unlock_irqrestore
2282 (&hw->bufspec_lock, flags);
2283 release_aux_data(hw, i);
2284
2285 if (!hw->mmu_enable) {
2286 if (hw->buffer_spec[i].cma_alloc_addr) {
2287 if (!hw->is_used_v4l) {
2288 decoder_bmmu_box_free_idx(
2289 hw->bmmu_box,
2290 i);
2291 }
2292 spin_lock_irqsave
2293 (&hw->bufspec_lock, flags);
2294 hw->buffer_spec[i].cma_alloc_addr = 0;
2295 hw->buffer_spec[i].buf_adr = 0;
2296 spin_unlock_irqrestore
2297 (&hw->bufspec_lock, flags);
2298 }
2299 } else {
2300 if (hw->buffer_spec[i].alloc_header_addr) {
2301 decoder_mmu_box_free_idx(
2302 hw->mmu_box,
2303 i);
2304 spin_lock_irqsave
2305 (&hw->bufspec_lock, flags);
2306 hw->buffer_spec[i].
2307 alloc_header_addr = 0;
2308 hw->buffer_spec[i].buf_adr = 0;
2309 spin_unlock_irqrestore
2310 (&hw->bufspec_lock, flags);
2311 }
2312 }
2313 }
2314 }
2315 if (dealloc_flag &&
2316 dpb_is_debug(DECODE_ID(hw),
2317 PRINT_FLAG_DUMP_BUFSPEC))
2318 dump_bufspec(hw, __func__);
2319 return;
2320}
2321
2322unsigned char have_free_buf_spec(struct vdec_s *vdec)
2323{
2324 int i;
2325 unsigned long addr;
2326 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2327 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2328 int index = -1;
2329 int ret = 0;
2330 int allocated_count = 0;
2331 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2332 if (hw->mmu_enable)
2333 addr = hw->buffer_spec[i].alloc_header_addr;
2334 else
2335 addr = hw->buffer_spec[i].cma_alloc_addr;
2336 if (hw->buffer_spec[i].used == 0) {
2337
2338 if (addr)
2339 return 1;
2340 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2341 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2342 index = i;
2343 }
2344 }
2345 if (addr)
2346 allocated_count++;
2347 }
2348 if (index >= 0) {
2349 mutex_lock(&vmh264_mutex);
2350 dealloc_buf_specs(hw, 0);
2351 if (max_alloc_buf_count == 0 ||
2352 allocated_count < max_alloc_buf_count) {
2353 if (hw->is_used_v4l)
2354 ret = 1;
2355 else if (alloc_one_buf_spec(hw, index) >= 0)
2356 ret = 1;
2357 }
2358 mutex_unlock(&vmh264_mutex);
2359 }
2360 return ret;
2361}
2362
2363static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2364 int canvas_pos)
2365{
2366 int i;
2367 int j = 0;
2368 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2369 if (hw->buffer_spec[i].canvas_pos >= 0) {
2370 if (j == canvas_pos)
2371 return i;
2372 j++;
2373 }
2374 }
2375 return -1;
2376}
2377static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2378 struct vframe_s *vf, int index)
2379{
2380 if (index < 0) {
2381 vf->mem_handle = NULL;
2382 vf->mem_head_handle = NULL;
2383 } else if (vf->type & VIDTYPE_SCATTER) {
2384 vf->mem_handle =
2385 decoder_mmu_box_get_mem_handle(
2386 hw->mmu_box, index);
2387 vf->mem_head_handle =
2388 decoder_bmmu_box_get_mem_handle(
2389 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2390 } else {
2391 vf->mem_handle =
2392 decoder_bmmu_box_get_mem_handle(
2393 hw->bmmu_box, VF_BUFFER_IDX(index));
2394 /* vf->mem_head_handle =
2395 decoder_bmmu_box_get_mem_handle(
2396 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2397 }
2398 return;
2399}
2400static int check_force_interlace(struct vdec_h264_hw_s *hw,
2401 struct FrameStore *frame)
2402{
2403 int bForceInterlace = 0;
2404 /* no di in secure mode, disable force di */
2405 if (vdec_secure(hw_to_vdec(hw)))
2406 return 0;
2407 if (frame->frame) {
2408 if (frame->frame->coded_frame
2409 && !frame->frame->frame_mbs_only_flag) {
2410 if (frame->frame->structure == FRAME)
2411 return 1;
2412 }
2413 }
2414
2415 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2416 && hw->bitstream_restriction_flag
2417 && (hw->frame_width == 1920)
2418 && (hw->frame_height >= 1080)
2419 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2420 bForceInterlace = 1;
2421 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2422 && (hw->frame_width == 720)
2423 && (hw->frame_height == 576)
2424 && (hw->frame_dur == 3840)) {
2425 bForceInterlace = 1;
2426 }
2427
2428 return bForceInterlace;
2429}
2430
2431static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2432{
2433 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2434 if (frame->slice_type == I_SLICE)
2435 vframe_qos->type = 1;
2436 else if (frame->slice_type == P_SLICE)
2437 vframe_qos->type = 2;
2438 else if (frame->slice_type == B_SLICE)
2439 vframe_qos->type = 3;
2440
2441 vframe_qos->size = frame->frame_size;
2442 vframe_qos->pts = frame->pts64;
2443
2444 vframe_qos->max_mv = frame->max_mv;
2445 vframe_qos->avg_mv = frame->avg_mv;
2446 vframe_qos->min_mv = frame->min_mv;
2447/*
2448 pr_info("mv: max:%d, avg:%d, min:%d\n",
2449 vframe_qos->max_mv,
2450 vframe_qos->avg_mv,
2451 vframe_qos->min_mv);
2452*/
2453
2454 vframe_qos->max_qp = frame->max_qp;
2455 vframe_qos->avg_qp = frame->avg_qp;
2456 vframe_qos->min_qp = frame->min_qp;
2457/*
2458 pr_info("qp: max:%d, avg:%d, min:%d\n",
2459 vframe_qos->max_qp,
2460 vframe_qos->avg_qp,
2461 vframe_qos->min_qp);
2462*/
2463
2464 vframe_qos->max_skip = frame->max_skip;
2465 vframe_qos->avg_skip = frame->avg_skip;
2466 vframe_qos->min_skip = frame->min_skip;
2467/*
2468 pr_info("skip: max:%d, avg:%d, min:%d\n",
2469 vframe_qos->max_skip,
2470 vframe_qos->avg_skip,
2471 vframe_qos->min_skip);
2472*/
2473 vframe_qos->num++;
2474 if (hw->frameinfo_enable)
2475 vdec_fill_frame_info(vframe_qos, 1);
2476}
2477
2478static int is_iframe(struct FrameStore *frame) {
2479
2480 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2481 return 1;
2482 }
2483 return 0;
2484}
2485
2486
2487
2488int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2489{
2490 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2491 struct vframe_s *vf = NULL;
2492 int buffer_index = frame->buf_spec_num;
2493 int vf_count = 1;
2494 int i;
2495 int bForceInterlace = 0;
2496
2497 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2498 dpb_print(DECODE_ID(hw), 0,
2499 "%s, buffer_index 0x%x is beyond range\n",
2500 __func__, buffer_index);
2501 return -1;
2502 }
2503 if (force_disp_bufspec_num & 0x100) {
2504 /*recycle directly*/
2505 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2506 hw->buffer_spec[frame->buf_spec_num].used != 5)
2507 set_frame_output_flag(&hw->dpb, frame->index);
2508
2509 /*make pre_output not set*/
2510 return -1;
2511 }
2512 if (error_proc_policy & 0x1000) {
2513 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2514 int error_skip_frame_count = error_skip_count & 0xfff;
2515 if (((hw->no_error_count < error_skip_frame_count)
2516 && (error_skip_i_count == 0 ||
2517 hw->no_error_i_count < error_skip_i_count))
2518 && (!(frame->data_flag & I_FLAG)))
2519 frame->data_flag |= ERROR_FLAG;
2520 }
2521 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2522 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2523 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2524 frame->poc, hw->data_flag & ERROR_FLAG,
2525 error_proc_policy);
2526 if (frame->frame == NULL &&
2527 ((frame->is_used == 1 && frame->top_field)
2528 || (frame->is_used == 2 && frame->bottom_field))) {
2529 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2530 "%s Error frame_num %d used %d\n",
2531 __func__, frame->frame_num, frame->is_used);
2532 frame->data_flag |= ERROR_FLAG;
2533 }
2534 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2535 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2536 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2537 0, &frame->pts64) == 0)) {
2538 hw->last_pts64 = frame->pts64;
2539 hw->last_pts = frame->pts;
2540 } else {
2541 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2542 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2543 }
2544 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2545 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2546 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2547 frame->offset_delimiter, frame->pts,hw->last_pts,
2548 frame->pts64, hw->last_pts64, hw->frame_dur);
2549 hw->last_pts64 = frame->pts64;
2550 hw->last_pts = frame->pts;
2551 }
2552 if ((frame->data_flag & NODISP_FLAG) ||
2553 (frame->data_flag & NULL_FLAG) ||
2554 ((!hw->send_error_frame_flag) &&
2555 (frame->data_flag & ERROR_FLAG)) ||
2556 ((hw->i_only & 0x1) &&
2557 (!(frame->data_flag & I_FLAG)))
2558 ) {
2559 set_frame_output_flag(&hw->dpb, frame->index);
2560 return 0; /*do not return -1,
2561 otherwise flush_dpb() will not flush all dbp frames*/
2562 }
2563
2564 display_frame_count[DECODE_ID(hw)]++;
2565
2566 if (dpb_is_debug(DECODE_ID(hw),
2567 PRINT_FLAG_DPB_DETAIL)) {
2568 dpb_print(DECODE_ID(hw), 0,
2569 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2570 __func__, frame->index, frame->poc,
2571 frame->buf_spec_num);
2572 print_pic_info(DECODE_ID(hw), "predis_frm",
2573 frame->frame, -1);
2574 print_pic_info(DECODE_ID(hw), "predis_top",
2575 frame->top_field, -1);
2576 print_pic_info(DECODE_ID(hw), "predis_bot",
2577 frame->bottom_field, -1);
2578 }
2579
2580 if (!is_interlace(frame))
2581 vf_count = 1;
2582 else
2583 vf_count = 2;
2584 bForceInterlace = check_force_interlace(hw, frame);
2585 if (bForceInterlace)
2586 vf_count = 2;
2587 hw->buffer_spec[buffer_index].vf_ref = 0;
2588 fill_frame_info(hw, frame);
2589 for (i = 0; i < vf_count; i++) {
2590 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2591 vf == NULL) {
2592 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2593 "%s fatal error, no available buffer slot.\n",
2594 __func__);
2595 return -1;
2596 }
2597 vf->duration_pulldown = 0;
2598 if (!(is_iframe(frame)) && hw->unstable_pts) {
2599 vf->pts = 0;
2600 vf->pts_us64 = 0;
2601 vf->timestamp = 0;
2602 vf->index = VF_INDEX(frame->index, buffer_index);
2603 } else {
2604 vf->pts = frame->pts;
2605 vf->pts_us64 = frame->pts64;
2606 vf->timestamp = frame->timestamp;
2607 vf->index = VF_INDEX(frame->index, buffer_index);
2608 }
2609
2610 if (hw->is_used_v4l) {
2611 vf->v4l_mem_handle
2612 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2613 }
2614
2615 if (hw->mmu_enable) {
2616 if (hw->double_write_mode & 0x10) {
2617 /* double write only */
2618 vf->compBodyAddr = 0;
2619 vf->compHeadAddr = 0;
2620 } else {
2621 /*head adr*/
2622 vf->compHeadAddr =
2623 hw->buffer_spec[buffer_index].alloc_header_addr;
2624 /*body adr*/
2625 vf->compBodyAddr = 0;
2626 vf->canvas0Addr = vf->canvas1Addr = 0;
2627 }
2628
2629 vf->type = VIDTYPE_SCATTER;
2630
2631 if (hw->double_write_mode) {
2632 vf->type |= VIDTYPE_PROGRESSIVE
2633 | VIDTYPE_VIU_FIELD;
2634 vf->type |= VIDTYPE_VIU_NV21;
2635 if (hw->double_write_mode == 3)
2636 vf->type |= VIDTYPE_COMPRESS;
2637
2638 vf->canvas0Addr = vf->canvas1Addr = -1;
2639 vf->plane_num = 2;
2640 vf->canvas0_config[0] =
2641 hw->buffer_spec[buffer_index].
2642 canvas_config[0];
2643 vf->canvas0_config[1] =
2644 hw->buffer_spec[buffer_index].
2645 canvas_config[1];
2646
2647 vf->canvas1_config[0] =
2648 hw->buffer_spec[buffer_index].
2649 canvas_config[0];
2650 vf->canvas1_config[1] =
2651 hw->buffer_spec[buffer_index].
2652 canvas_config[1];
2653
2654 } else {
2655 vf->type |=
2656 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2657 vf->canvas0Addr = vf->canvas1Addr = 0;
2658 }
2659
2660 vf->bitdepth =
2661 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2662
2663 vf->compWidth = hw->frame_width;
2664 vf->compHeight = hw->frame_height;
2665 } else {
2666 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2667 VIDTYPE_VIU_NV21;
2668
2669 vf->canvas0Addr = vf->canvas1Addr =
2670 spec2canvas(&hw->buffer_spec[buffer_index]);
2671#ifdef VDEC_DW
2672 if (IS_VDEC_DW(hw))
2673 vf->canvas0Addr = vf->canvas1Addr =
2674 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2675#endif
2676
2677 }
2678 set_frame_info(hw, vf, buffer_index);
2679
2680 if (hw->mmu_enable && hw->double_write_mode) {
2681 vf->width = hw->frame_width /
2682 get_double_write_ratio(hw);
2683 vf->height = hw->frame_height /
2684 get_double_write_ratio(hw);
2685 }
2686
2687 vf->flag = 0;
2688 if (frame->data_flag & I_FLAG)
2689 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2690 if (frame->data_flag & ERROR_FLAG)
2691 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2692 update_vf_memhandle(hw, vf, buffer_index);
2693 hw->buffer_spec[buffer_index].used = 2;
2694 hw->buffer_spec[buffer_index].vf_ref++;
2695
2696 if (bForceInterlace || is_interlace(frame)) {
2697 vf->type =
2698 VIDTYPE_INTERLACE_FIRST |
2699 VIDTYPE_VIU_NV21;
2700
2701 if (bForceInterlace) {
2702 vf->type |= (i == 0 ?
2703 VIDTYPE_INTERLACE_TOP :
2704 VIDTYPE_INTERLACE_BOTTOM);
2705 if (i == 1) {
2706 vf->pts = 0;
2707 vf->pts_us64 = 0;
2708 }
2709 } else if (frame->top_field->poc <=
2710 frame->bottom_field->poc) /*top first*/
2711 vf->type |= (i == 0 ?
2712 VIDTYPE_INTERLACE_TOP :
2713 VIDTYPE_INTERLACE_BOTTOM);
2714 else
2715 vf->type |= (i == 0 ?
2716 VIDTYPE_INTERLACE_BOTTOM :
2717 VIDTYPE_INTERLACE_TOP);
2718 vf->duration = vf->duration/2;
2719 }
2720
2721 if (i == 0)
2722 decoder_do_frame_check(hw_to_vdec(hw), vf);
2723
2724 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2725 vf->sar_width = hw->width_aspect_ratio;
2726 vf->sar_height = hw->height_aspect_ratio;
2727
2728 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2729 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2730 hw->vf_pre_count++;
2731 vdec->vdec_fps_detec(vdec->id);
2732 if (without_display_mode == 0) {
2733 vf_notify_receiver(vdec->vf_provider_name,
2734 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2735 } else
2736 vh264_vf_put(vh264_vf_get(vdec), vdec);
2737 }
2738 if (dpb_is_debug(DECODE_ID(hw),
2739 PRINT_FLAG_DUMP_BUFSPEC))
2740 dump_bufspec(hw, __func__);
2741
2742 return 0;
2743}
2744
2745int notify_v4l_eos(struct vdec_s *vdec)
2746{
2747 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2748 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2749 struct vframe_s *vf = &hw->vframe_dummy;
2750 struct vdec_v4l2_buffer *fb = NULL;
2751 int index = INVALID_IDX;
2752 ulong expires;
2753
2754 if (hw->is_used_v4l && hw->eos) {
2755 expires = jiffies + msecs_to_jiffies(2000);
2756 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2757 if (time_after(jiffies, expires))
2758 break;
2759 }
2760
2761 if (index == INVALID_IDX) {
2762 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2763 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2764 return -1;
2765 }
2766 }
2767
2768 vf->type |= VIDTYPE_V4L_EOS;
2769 vf->timestamp = ULONG_MAX;
2770 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2771 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2772 hw->buffer_spec[index].cma_alloc_addr;
2773
2774 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2775
2776 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2777 vf_notify_receiver(vdec->vf_provider_name,
2778 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2779
2780 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2781 }
2782
2783 return 0;
2784}
2785
2786/******************
2787 * Hardware config
2788 */
2789char *slice_type_name[] = {
2790 "P_SLICE ",
2791 "B_SLICE ",
2792 "I_SLICE ",
2793 "SP_SLICE",
2794 "SI_SLICE",
2795};
2796
2797char *picture_structure_name[] = {
2798 "FRAME",
2799 "TOP_FIELD",
2800 "BOTTOM_FIELD"
2801};
2802
2803void print_pic_info(int decindex, const char *info,
2804 struct StorablePicture *pic,
2805 int slice_type)
2806{
2807 if (pic)
2808 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2809 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2810 info,
2811 picture_structure_name[pic->structure],
2812 pic->coded_frame ? "Frame" : "Field",
2813 (slice_type < 0 ||
2814 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2815 pic->mb_aff_frame_flag,
2816 pic->poc,
2817 pic->pic_num,
2818 pic->buf_spec_num,
2819 pic->data_flag);
2820}
2821
2822static void reset_process_time(struct vdec_h264_hw_s *hw)
2823{
2824 if (hw->start_process_time) {
2825 unsigned process_time =
2826 1000 * (jiffies - hw->start_process_time) / HZ;
2827 hw->start_process_time = 0;
2828 if (process_time > max_process_time[DECODE_ID(hw)])
2829 max_process_time[DECODE_ID(hw)] = process_time;
2830 }
2831}
2832
2833static void start_process_time(struct vdec_h264_hw_s *hw)
2834{
2835 hw->decode_timeout_count = 10;
2836 hw->start_process_time = jiffies;
2837}
2838
2839static void config_aux_buf(struct vdec_h264_hw_s *hw)
2840{
2841 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2842 WRITE_VREG(H264_AUX_DATA_SIZE,
2843 ((hw->prefix_aux_size >> 4) << 16) |
2844 (hw->suffix_aux_size >> 4)
2845 );
2846}
2847
2848/*
2849* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2850*/
2851static void set_aux_data(struct vdec_h264_hw_s *hw,
2852 struct StorablePicture *pic, unsigned char suffix_flag,
2853 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2854{
2855 int i;
2856 unsigned short *aux_adr;
2857 unsigned size_reg_val =
2858 READ_VREG(H264_AUX_DATA_SIZE);
2859 unsigned aux_count = 0;
2860 int aux_size = 0;
2861 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2862 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2863 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2864 return;
2865
2866 if (suffix_flag) {
2867 aux_adr = (unsigned short *)
2868 (hw_buf->aux_addr +
2869 hw_buf->prefix_aux_size);
2870 aux_count =
2871 ((size_reg_val & 0xffff) << 4)
2872 >> 1;
2873 aux_size =
2874 hw_buf->suffix_aux_size;
2875 } else {
2876 aux_adr =
2877 (unsigned short *)hw_buf->aux_addr;
2878 aux_count =
2879 ((size_reg_val >> 16) << 4)
2880 >> 1;
2881 aux_size =
2882 hw_buf->prefix_aux_size;
2883 }
2884 if (dpb_is_debug(DECODE_ID(hw),
2885 PRINT_FLAG_DPB_DETAIL)) {
2886 dpb_print(DECODE_ID(hw), 0,
2887 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2888 __func__, AUX_DATA_SIZE(pic),
2889 aux_count, suffix_flag, dv_meta_flag);
2890 }
2891 if (aux_size > 0 && aux_count > 0) {
2892 int heads_size = 0;
2893 int new_size;
2894 char *new_buf;
2895 for (i = 0; i < aux_count; i++) {
2896 unsigned char tag = aux_adr[i] >> 8;
2897 if (tag != 0 && tag != 0xff) {
2898 if (dv_meta_flag == 0)
2899 heads_size += 8;
2900 else if (dv_meta_flag == 1 && tag == 0x1)
2901 heads_size += 8;
2902 else if (dv_meta_flag == 2 && tag != 0x1)
2903 heads_size += 8;
2904 }
2905 }
2906 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2907 new_buf = krealloc(AUX_DATA_BUF(pic),
2908 new_size,
2909 GFP_KERNEL);
2910 if (new_buf) {
2911 unsigned char valid_tag = 0;
2912 unsigned char *h =
2913 new_buf +
2914 AUX_DATA_SIZE(pic);
2915 unsigned char *p = h + 8;
2916 int len = 0;
2917 int padding_len = 0;
2918 AUX_DATA_BUF(pic) = new_buf;
2919 for (i = 0; i < aux_count; i += 4) {
2920 int ii;
2921 unsigned char tag = aux_adr[i + 3] >> 8;
2922 if (tag != 0 && tag != 0xff) {
2923 if (dv_meta_flag == 0)
2924 valid_tag = 1;
2925 else if (dv_meta_flag == 1
2926 && tag == 0x1)
2927 valid_tag = 1;
2928 else if (dv_meta_flag == 2
2929 && tag != 0x1)
2930 valid_tag = 1;
2931 else
2932 valid_tag = 0;
2933 if (valid_tag && len > 0) {
2934 AUX_DATA_SIZE(pic) +=
2935 (len + 8);
2936 h[0] =
2937 (len >> 24) & 0xff;
2938 h[1] =
2939 (len >> 16) & 0xff;
2940 h[2] =
2941 (len >> 8) & 0xff;
2942 h[3] =
2943 (len >> 0) & 0xff;
2944 h[6] =
2945 (padding_len >> 8)
2946 & 0xff;
2947 h[7] =
2948 (padding_len) & 0xff;
2949 h += (len + 8);
2950 p += 8;
2951 len = 0;
2952 padding_len = 0;
2953 }
2954 if (valid_tag) {
2955 h[4] = tag;
2956 h[5] = 0;
2957 h[6] = 0;
2958 h[7] = 0;
2959 }
2960 }
2961 if (valid_tag) {
2962 for (ii = 0; ii < 4; ii++) {
2963 unsigned short aa =
2964 aux_adr[i + 3
2965 - ii];
2966 *p = aa & 0xff;
2967 p++;
2968 len++;
2969 /*if ((aa >> 8) == 0xff)
2970 padding_len++;*/
2971 }
2972 }
2973 }
2974 if (len > 0) {
2975 AUX_DATA_SIZE(pic) += (len + 8);
2976 h[0] = (len >> 24) & 0xff;
2977 h[1] = (len >> 16) & 0xff;
2978 h[2] = (len >> 8) & 0xff;
2979 h[3] = (len >> 0) & 0xff;
2980 h[6] = (padding_len >> 8) & 0xff;
2981 h[7] = (padding_len) & 0xff;
2982 }
2983 if (dpb_is_debug(DECODE_ID(hw),
2984 PRINT_FLAG_DPB_DETAIL)) {
2985 dpb_print(DECODE_ID(hw), 0,
2986 "aux: (size %d) suffix_flag %d\n",
2987 AUX_DATA_SIZE(pic), suffix_flag);
2988 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2989 dpb_print_cont(DECODE_ID(hw), 0,
2990 "%02x ", AUX_DATA_BUF(pic)[i]);
2991 if (((i + 1) & 0xf) == 0)
2992 dpb_print_cont(
2993 DECODE_ID(hw),
2994 0, "\n");
2995 }
2996 dpb_print_cont(DECODE_ID(hw),
2997 0, "\n");
2998 }
2999
3000 }
3001 }
3002
3003}
3004
3005static void release_aux_data(struct vdec_h264_hw_s *hw,
3006 int buf_spec_num)
3007{
3008 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3009 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3010 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3011}
3012
3013static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3014{
3015 int i;
3016 unsigned short *aux_adr =
3017 (unsigned short *)
3018 hw->aux_addr;
3019 unsigned aux_size =
3020 (READ_VREG(H264_AUX_DATA_SIZE)
3021 >> 16) << 4;
3022
3023 if (hw->prefix_aux_size > 0) {
3024 dpb_print(DECODE_ID(hw),
3025 0,
3026 "prefix aux: (size %d)\n",
3027 aux_size);
3028 for (i = 0; i <
3029 (aux_size >> 1); i++) {
3030 dpb_print_cont(DECODE_ID(hw),
3031 0,
3032 "%04x ",
3033 *(aux_adr + i));
3034 if (((i + 1) & 0xf)
3035 == 0)
3036 dpb_print_cont(
3037 DECODE_ID(hw),
3038 0, "\n");
3039 }
3040 }
3041 if (hw->suffix_aux_size > 0) {
3042 aux_adr = (unsigned short *)
3043 (hw->aux_addr +
3044 hw->prefix_aux_size);
3045 aux_size =
3046 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3047 << 4;
3048 dpb_print(DECODE_ID(hw),
3049 0,
3050 "suffix aux: (size %d)\n",
3051 aux_size);
3052 for (i = 0; i <
3053 (aux_size >> 1); i++) {
3054 dpb_print_cont(DECODE_ID(hw),
3055 0,
3056 "%04x ", *(aux_adr + i));
3057 if (((i + 1) & 0xf) == 0)
3058 dpb_print_cont(DECODE_ID(hw),
3059 0, "\n");
3060 }
3061 }
3062}
3063
3064static void config_decode_mode(struct vdec_h264_hw_s *hw)
3065{
3066#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3067 struct vdec_s *vdec = hw_to_vdec(hw);
3068#endif
3069 if (input_frame_based(hw_to_vdec(hw)))
3070 WRITE_VREG(H264_DECODE_MODE,
3071 DECODE_MODE_MULTI_FRAMEBASE);
3072#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3073 else if (vdec->slave)
3074 WRITE_VREG(H264_DECODE_MODE,
3075 (hw->got_valid_nal << 8) |
3076 DECODE_MODE_MULTI_DVBAL);
3077 else if (vdec->master)
3078 WRITE_VREG(H264_DECODE_MODE,
3079 (hw->got_valid_nal << 8) |
3080 DECODE_MODE_MULTI_DVENL);
3081#endif
3082 else
3083 WRITE_VREG(H264_DECODE_MODE,
3084 DECODE_MODE_MULTI_STREAMBASE);
3085 WRITE_VREG(H264_DECODE_SEQINFO,
3086 hw->seq_info2);
3087 WRITE_VREG(HEAD_PADING_REG, 0);
3088
3089 if (hw->init_flag == 0)
3090 WRITE_VREG(INIT_FLAG_REG, 0);
3091 else
3092 WRITE_VREG(INIT_FLAG_REG, 1);
3093}
3094int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3095{
3096 /* static int count = 0; */
3097 int ret = 0;
3098 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3099 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3100 unsigned int colocate_adr_offset;
3101 unsigned int val;
3102 struct StorablePicture *last_pic = hw->last_dec_picture;
3103
3104#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3105 int colocate_buf_index;
3106#endif
3107#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3108#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3109#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3110#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3111
3112#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3113/* bit 31:30 -- L1[0] picture coding structure,
3114 * 00 - top field, 01 - bottom field,
3115 * 10 - frame, 11 - mbaff frame
3116 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3117 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3118 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3119 */
3120#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3121
3122/* bit 15 -- flush co_mb_data to DDR -- W-Only
3123 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3124 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3125 * bit 9 -- soft_reset -- W-Only
3126 * bit 8 -- upgent
3127 * bit 7:2 -- h264_co_mb_mem_wr_addr
3128 * bit 1:0 -- h264_co_mb_info_wr_ptr
3129 */
3130#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3131
3132 unsigned long canvas_adr;
3133 unsigned int ref_reg_val;
3134 unsigned int one_ref_cfg = 0;
3135 int h264_buffer_info_data_write_count;
3136 int i, j;
3137 unsigned int colocate_wr_adr;
3138 unsigned int colocate_rd_adr;
3139 unsigned char use_direct_8x8;
3140 int canvas_pos;
3141 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3142 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3143 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3144 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3145 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3146
3147 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3148 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3149 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3150 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3151 canvas_pos);
3152 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3153
3154#ifdef VDEC_DW
3155 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3156 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3157 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3158#endif
3159 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3160 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3161
3162 if (!hw->mmu_enable) {
3163 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3164 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3165 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3166#ifdef VDEC_DW
3167 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3168 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3169 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3170#endif
3171 } else
3172 hevc_sao_set_pic_buffer(hw, pic);
3173
3174 if (pic->mb_aff_frame_flag)
3175 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3176 else if (pic->structure == TOP_FIELD)
3177 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3178 else if (pic->structure == BOTTOM_FIELD)
3179 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3180 else
3181 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3182
3183 if (pic->bottom_poc < pic->top_poc)
3184 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3185
3186 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3187 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3188 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3189
3190 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3191 int long_term_flag;
3192 i = get_buf_spec_by_canvas_pos(hw, j);
3193 if (i < 0)
3194 break;
3195 long_term_flag =
3196 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3197 if (long_term_flag > 0) {
3198 if (long_term_flag & 0x1)
3199 hw->buffer_spec[i].info0 |= (1 << 4);
3200 else
3201 hw->buffer_spec[i].info0 &= ~(1 << 4);
3202
3203 if (long_term_flag & 0x2)
3204 hw->buffer_spec[i].info0 |= (1 << 5);
3205 else
3206 hw->buffer_spec[i].info0 &= ~(1 << 5);
3207 }
3208
3209 if (i == pic->buf_spec_num)
3210 WRITE_VREG(H264_BUFFER_INFO_DATA,
3211 hw->buffer_spec[i].info0 | 0xf);
3212 else
3213 WRITE_VREG(H264_BUFFER_INFO_DATA,
3214 hw->buffer_spec[i].info0);
3215 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3216 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3217 }
3218
3219 /* config reference buffer */
3220 if (hw->mmu_enable) {
3221 hevc_mcr_config_mc_ref(hw);
3222 hevc_mcr_config_mcrcc(hw);
3223 }
3224
3225 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3226 "list0 size %d\n", pSlice->listXsize[0]);
3227 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3228 ref_reg_val = 0;
3229 j = 0;
3230 h264_buffer_info_data_write_count = 0;
3231
3232 //disable this read cache when frame width <= 64 (4MBs)
3233 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3234 if (hw->frame_width <= 64)
3235 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3236 else
3237 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3238
3239 if (last_pic)
3240 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3241 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3242 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3243 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3244 last_pic && (last_pic->data_flag & ERROR_FLAG)
3245 && (!(last_pic->slice_type == B_SLICE))
3246 && (!(pSlice->slice_type == I_SLICE))) {
3247 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3248 "no i/idr error mark\n");
3249 hw->data_flag |= ERROR_FLAG;
3250 pic->data_flag |= ERROR_FLAG;
3251 }
3252
3253 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3254 /*ref list 0 */
3255 struct StorablePicture *ref = pSlice->listX[0][i];
3256 unsigned int cfg;
3257 /* bit[6:5] - frame/field info,
3258 * 01 - top, 10 - bottom, 11 - frame
3259 */
3260 #ifdef ERROR_CHECK
3261 if (ref == NULL) {
3262 hw->data_flag |= ERROR_FLAG;
3263 pic->data_flag |= ERROR_FLAG;
3264 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3265 return -1;
3266 }
3267 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3268 hw->data_flag |= ERROR_FLAG;
3269 pic->data_flag |= ERROR_FLAG;
3270 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3271 }
3272 if (ref->data_flag & NULL_FLAG)
3273 hw->data_flag |= NULL_FLAG;
3274#endif
3275 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3276
3277 if (ref->structure == TOP_FIELD)
3278 cfg = 0x1;
3279 else if (ref->structure == BOTTOM_FIELD)
3280 cfg = 0x2;
3281 else /* FRAME */
3282 cfg = 0x3;
3283
3284 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3285 ref_reg_val <<= 8;
3286 ref_reg_val |= one_ref_cfg;
3287 j++;
3288
3289 if (j == 4) {
3290 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3291 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3292 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3293 h264_buffer_info_data_write_count++;
3294 j = 0;
3295 }
3296 print_pic_info(DECODE_ID(hw), "list0",
3297 pSlice->listX[0][i], -1);
3298 }
3299 if (j != 0) {
3300 while (j != 4) {
3301 ref_reg_val <<= 8;
3302 ref_reg_val |= one_ref_cfg;
3303 j++;
3304 }
3305 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3306 "H264_BUFFER_INFO_DATA: %x\n",
3307 ref_reg_val);
3308 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3309 h264_buffer_info_data_write_count++;
3310 }
3311 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3312 (one_ref_cfg << 8) | one_ref_cfg;
3313 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3314 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3315
3316 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3317 "list1 size %d\n", pSlice->listXsize[1]);
3318 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3319 ref_reg_val = 0;
3320 j = 0;
3321
3322 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3323 /* ref list 0 */
3324 struct StorablePicture *ref = pSlice->listX[1][i];
3325 unsigned int cfg;
3326 /* bit[6:5] - frame/field info,
3327 * 01 - top, 10 - bottom, 11 - frame
3328 */
3329
3330 #ifdef ERROR_CHECK
3331 if (ref == NULL) {
3332 hw->data_flag |= ERROR_FLAG;
3333 pic->data_flag |= ERROR_FLAG;
3334 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3335 return -2;
3336 }
3337 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3338 pic->data_flag |= ERROR_FLAG;
3339 hw->data_flag |= ERROR_FLAG;
3340 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3341 }
3342 if (ref->data_flag & NULL_FLAG)
3343 hw->data_flag |= NULL_FLAG;
3344#endif
3345 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3346 if (ref->structure == TOP_FIELD)
3347 cfg = 0x1;
3348 else if (ref->structure == BOTTOM_FIELD)
3349 cfg = 0x2;
3350 else /* FRAME */
3351 cfg = 0x3;
3352 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3353 ref_reg_val <<= 8;
3354 ref_reg_val |= one_ref_cfg;
3355 j++;
3356
3357 if (j == 4) {
3358 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3359 "H264_BUFFER_INFO_DATA: %x\n",
3360 ref_reg_val);
3361 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3362 j = 0;
3363 }
3364 print_pic_info(DECODE_ID(hw), "list1",
3365 pSlice->listX[1][i], -1);
3366 }
3367 if (j != 0) {
3368 while (j != 4) {
3369 ref_reg_val <<= 8;
3370 ref_reg_val |= one_ref_cfg;
3371 j++;
3372 }
3373 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3374 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3375 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3376 }
3377
3378 /* configure co-locate buffer */
3379 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3380 ;
3381 if ((pSlice->mode_8x8_flags & 0x4) &&
3382 (pSlice->mode_8x8_flags & 0x2))
3383 use_direct_8x8 = 1;
3384 else
3385 use_direct_8x8 = 0;
3386
3387#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3388 colocate_adr_offset =
3389 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3390 ? 1 : 2) * 96;
3391 if (use_direct_8x8)
3392 colocate_adr_offset >>= 2;
3393
3394 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3395 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3396 colocate_adr_offset, pSlice->first_mb_in_slice,
3397 colocate_adr_offset * pSlice->first_mb_in_slice);
3398
3399 colocate_adr_offset *= pSlice->first_mb_in_slice;
3400
3401 if ((pic->colocated_buf_index >= 0) &&
3402 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3403 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3404 ((p_H264_Dpb->colocated_buf_size *
3405 pic->colocated_buf_index)
3406 >> (use_direct_8x8 ? 2 : 0));
3407 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3408 p_H264_Dpb->colocated_mv_addr_end) {
3409 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3410 "Error, colocate buf is not enough, index is %d\n",
3411 pic->colocated_buf_index);
3412 ret = -3;
3413 }
3414 val = colocate_wr_adr + colocate_adr_offset;
3415 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3416 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3417 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3418 val, pSlice->first_mb_in_slice, pic->structure,
3419 colocate_adr_offset, pSlice->mode_8x8_flags,
3420 p_H264_Dpb->colocated_buf_size);
3421 } else {
3422 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3423 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3424 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3425 }
3426#else
3427 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3428 colocate_adr_offset =
3429 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3430 if (use_direct_8x8)
3431 colocate_adr_offset >>= 2;
3432
3433 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3434 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3435 colocate_adr_offset, pSlice->first_mb_in_slice,
3436 colocate_adr_offset * pSlice->first_mb_in_slice);
3437
3438 colocate_adr_offset *= pSlice->first_mb_in_slice;
3439
3440 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3441 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3442 (use_direct_8x8 ? 2 : 0));
3443
3444 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3445 p_H264_Dpb->colocated_mv_addr_end) {
3446 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3447 "Error, colocate buf is not enough, col buf index is %d\n",
3448 colocate_buf_index);
3449 ret = -4;
3450 }
3451 val = colocate_wr_adr + colocate_adr_offset;
3452 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3453 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3454 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3455 val, pSlice->first_mb_in_slice, pic->structure,
3456 colocate_adr_offset, pSlice->mode_8x8_flags,
3457 p_H264_Dpb->colocated_buf_size);
3458#endif
3459 if (pSlice->listXsize[1] > 0) {
3460 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3461 /* H264_CO_MB_RD_ADDR[bit 31:30],
3462 * original picture structure of L1[0],
3463 * 00 - top field, 01 - bottom field,
3464 * 10 - frame, 11 - mbaff frame
3465 */
3466 int l10_structure;
3467 int cur_colocate_ref_type;
3468 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3469 * 0 - top, 1 - bot
3470 */
3471 unsigned int val;
3472#ifdef ERROR_CHECK
3473 if (colocate_pic == NULL) {
3474 hw->data_flag |= ERROR_FLAG;
3475 pic->data_flag |= ERROR_FLAG;
3476 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3477 return -5;
3478 }
3479 if (colocate_pic->data_flag & ERROR_FLAG) {
3480 pic->data_flag |= ERROR_FLAG;
3481 hw->data_flag |= ERROR_FLAG;
3482 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3483 }
3484 if (colocate_pic->data_flag & NULL_FLAG)
3485 hw->data_flag |= NULL_FLAG;
3486#endif
3487
3488 if (colocate_pic->mb_aff_frame_flag)
3489 l10_structure = 3;
3490 else {
3491 if (colocate_pic->coded_frame)
3492 l10_structure = 2;
3493 else
3494 l10_structure = (colocate_pic->structure ==
3495 BOTTOM_FIELD) ? 1 : 0;
3496 }
3497#if 0
3498 /*case0016, p16,
3499 *cur_colocate_ref_type should be configured base on current pic
3500 */
3501 if (pic->structure == FRAME &&
3502 pic->mb_aff_frame_flag)
3503 cur_colocate_ref_type = 0;
3504 else if (pic->structure == BOTTOM_FIELD)
3505 cur_colocate_ref_type = 1;
3506 else
3507 cur_colocate_ref_type = 0;
3508#else
3509 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3510 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3511 pic->mb_aff_frame_flag,
3512 pic->structure,
3513 pic->coded_frame);
3514 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3515 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3516 colocate_pic->mb_aff_frame_flag,
3517 colocate_pic->structure,
3518 colocate_pic->coded_frame);
3519 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3520 cur_colocate_ref_type =
3521 (abs(pic->poc - colocate_pic->top_poc)
3522 < abs(pic->poc -
3523 colocate_pic->bottom_poc)) ? 0 : 1;
3524 } else
3525 cur_colocate_ref_type =
3526 (colocate_pic->structure
3527 == BOTTOM_FIELD) ? 1 : 0;
3528#endif
3529
3530#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3531 if ((colocate_pic->colocated_buf_index >= 0) &&
3532 (colocate_pic->colocated_buf_index <
3533 p_H264_Dpb->colocated_buf_count)) {
3534 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3535 ((p_H264_Dpb->colocated_buf_size *
3536 colocate_pic->colocated_buf_index)
3537 >> (use_direct_8x8 ? 2 : 0));
3538 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3539 p_H264_Dpb->colocated_mv_addr_end) {
3540 dpb_print(DECODE_ID(hw),
3541 PRINT_FLAG_ERROR,
3542 "Error, colocate buf is not enough, index is %d\n",
3543 colocate_pic->colocated_buf_index);
3544 ret = -6;
3545 }
3546 /* bit 31:30 -- L1[0] picture coding structure,
3547 * 00 - top field, 01 - bottom field,
3548 * 10 - frame, 11 - mbaff frame
3549 * bit 29 - L1[0] top/bot for B field pciture,
3550 * 0 - top, 1 - bot
3551 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3552 * -- only used for B Picture Direct mode
3553 * [2:0] will set to 3'b000
3554 */
3555 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3556 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3557 (l10_structure << 30) |
3558 (cur_colocate_ref_type << 29);
3559 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3560 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3561 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3562 colocate_pic->colocated_buf_index,
3563 val, colocate_rd_adr + colocate_adr_offset,
3564 colocate_pic->structure,
3565 colocate_pic->mb_aff_frame_flag);
3566 } else {
3567 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3568 "Error, reference pic has no colocated buf\n");
3569 ret = -7;
3570 }
3571#else
3572 colocate_buf_index =
3573 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3574 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3575 ((p_H264_Dpb->colocated_buf_size *
3576 colocate_buf_index)
3577 >> (use_direct_8x8 ? 2 : 0));
3578 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3579 p_H264_Dpb->colocated_mv_addr_end) {
3580 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3581 "Error, colocate buf is not enough, col buf index is %d\n",
3582 colocate_buf_index);
3583 ret = -8;
3584 }
3585 /* bit 31:30 -- L1[0] picture coding structure,
3586 * 00 - top field, 01 - bottom field,
3587 * 10 - frame, 11 - mbaff frame
3588 * bit 29 - L1[0] top/bot for B field pciture,
3589 * 0 - top, 1 - bot
3590 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3591 * -- only used for B Picture Direct mode
3592 * [2:0] will set to 3'b000
3593 */
3594 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3595 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3596 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3597 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3598 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3599 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3600 val, colocate_pic->structure,
3601 colocate_pic->mb_aff_frame_flag);
3602#endif
3603 }
3604 return ret;
3605}
3606
3607static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3608{
3609 unsigned long flags;
3610 struct vdec_s *vdec = op_arg;
3611 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3612
3613 spin_lock_irqsave(&hw->lock, flags);
3614
3615 states->vf_pool_size = VF_POOL_SIZE;
3616 states->buf_free_num = kfifo_len(&hw->newframe_q);
3617 states->buf_avail_num = kfifo_len(&hw->display_q);
3618
3619 spin_unlock_irqrestore(&hw->lock, flags);
3620
3621 return 0;
3622}
3623
3624static struct vframe_s *vh264_vf_peek(void *op_arg)
3625{
3626 struct vframe_s *vf[2] = {0, 0};
3627 struct vdec_s *vdec = op_arg;
3628 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3629
3630 if (!hw)
3631 return NULL;
3632
3633 if (force_disp_bufspec_num & 0x100) {
3634 if (force_disp_bufspec_num & 0x200)
3635 return NULL;
3636 return &hw->vframe_dummy;
3637 }
3638
3639 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3640 if (vf[1]) {
3641 vf[0]->next_vf_pts_valid = true;
3642 vf[0]->next_vf_pts = vf[1]->pts;
3643 } else
3644 vf[0]->next_vf_pts_valid = false;
3645 return vf[0];
3646 }
3647
3648 return NULL;
3649}
3650
3651static struct vframe_s *vh264_vf_get(void *op_arg)
3652{
3653 struct vframe_s *vf;
3654 struct vdec_s *vdec = op_arg;
3655 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3656
3657 if (!hw)
3658 return NULL;
3659
3660 if (force_disp_bufspec_num & 0x100) {
3661 int buffer_index = force_disp_bufspec_num & 0xff;
3662 if (force_disp_bufspec_num & 0x200)
3663 return NULL;
3664
3665 vf = &hw->vframe_dummy;
3666 vf->duration_pulldown = 0;
3667 vf->pts = 0;
3668 vf->pts_us64 = 0;
3669 set_frame_info(hw, vf, buffer_index);
3670 vf->flag = 0;
3671 if (hw->mmu_enable) {
3672 if (hw->double_write_mode & 0x10) {
3673 /* double write only */
3674 vf->compBodyAddr = 0;
3675 vf->compHeadAddr = 0;
3676 } else {
3677 /*head adr*/
3678 vf->compHeadAddr =
3679 hw->buffer_spec[buffer_index].alloc_header_addr;
3680 /*body adr*/
3681 vf->compBodyAddr = 0;
3682 vf->canvas0Addr = vf->canvas1Addr = 0;
3683 }
3684
3685 vf->type = VIDTYPE_SCATTER;
3686
3687 if (hw->double_write_mode) {
3688 vf->type |= VIDTYPE_PROGRESSIVE
3689 | VIDTYPE_VIU_FIELD;
3690 vf->type |= VIDTYPE_VIU_NV21;
3691 if (hw->double_write_mode == 3)
3692 vf->type |= VIDTYPE_COMPRESS;
3693
3694 vf->canvas0Addr = vf->canvas1Addr = -1;
3695 vf->plane_num = 2;
3696 vf->canvas0_config[0] =
3697 hw->buffer_spec[buffer_index].
3698 canvas_config[0];
3699 vf->canvas0_config[1] =
3700 hw->buffer_spec[buffer_index].
3701 canvas_config[1];
3702
3703 vf->canvas1_config[0] =
3704 hw->buffer_spec[buffer_index].
3705 canvas_config[0];
3706 vf->canvas1_config[1] =
3707 hw->buffer_spec[buffer_index].
3708 canvas_config[1];
3709 } else {
3710 vf->type |=
3711 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3712 vf->canvas0Addr = vf->canvas1Addr = 0;
3713 }
3714 vf->bitdepth =
3715 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3716
3717 vf->compWidth = hw->frame_width;
3718 vf->compHeight = hw->frame_height;
3719
3720 if (hw->double_write_mode) {
3721 vf->width = hw->frame_width /
3722 get_double_write_ratio(hw);
3723 vf->height = hw->frame_height /
3724 get_double_write_ratio(hw);
3725 }
3726 } else {
3727 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3728 VIDTYPE_VIU_NV21;
3729 vf->canvas0Addr = vf->canvas1Addr =
3730 spec2canvas(&hw->buffer_spec[buffer_index]);
3731 }
3732
3733 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3734 hw->bmmu_box, buffer_index);*/
3735 update_vf_memhandle(hw, vf, buffer_index);
3736 force_disp_bufspec_num |= 0x200;
3737 return vf;
3738 }
3739
3740 if (kfifo_get(&hw->display_q, &vf)) {
3741 int time = jiffies;
3742 unsigned int frame_interval =
3743 1000*(time - hw->last_frame_time)/HZ;
3744 struct vframe_s *next_vf;
3745 if (dpb_is_debug(DECODE_ID(hw),
3746 PRINT_FLAG_VDEC_DETAIL)) {
3747 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3748 int frame_index = FRAME_INDEX(vf->index);
3749 if (frame_index < 0 ||
3750 frame_index >= DPB_SIZE_MAX) {
3751 dpb_print(DECODE_ID(hw), 0,
3752 "%s vf index 0x%x error\r\n",
3753 __func__, vf->index);
3754 } else {
3755 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3756 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3757 __func__, BUFSPEC_INDEX(vf->index), vf,
3758 p_H264_Dpb->mFrameStore[frame_index].poc,
3759 vf->duration, vf->pts, frame_interval);
3760 }
3761 }
3762 if (hw->last_frame_time > 0) {
3763 if (frame_interval >
3764 max_get_frame_interval[DECODE_ID(hw)])
3765 max_get_frame_interval[DECODE_ID(hw)]
3766 = frame_interval;
3767 }
3768 hw->last_frame_time = time;
3769 hw->vf_get_count++;
3770 if (kfifo_peek(&hw->display_q, &next_vf)) {
3771 vf->next_vf_pts_valid = true;
3772 vf->next_vf_pts = next_vf->pts;
3773 } else
3774 vf->next_vf_pts_valid = false;
3775 return vf;
3776 }
3777
3778 return NULL;
3779}
3780
3781static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3782{
3783 struct vdec_s *vdec = op_arg;
3784 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3785 int buf_spec_num;
3786 int frame_index;
3787
3788 if (vf == (&hw->vframe_dummy))
3789 return;
3790 if (vf->index == -1) {
3791 dpb_print(DECODE_ID(hw), 0,
3792 "Warning: %s vf %p invalid index\r\n",
3793 __func__, vf);
3794 return;
3795 }
3796 frame_index = FRAME_INDEX(vf->index);
3797 buf_spec_num = BUFSPEC_INDEX(vf->index);
3798 if (frame_index < 0 ||
3799 frame_index >= DPB_SIZE_MAX ||
3800 buf_spec_num < 0 ||
3801 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3802 dpb_print(DECODE_ID(hw), 0,
3803 "%s vf index 0x%x error\r\n",
3804 __func__, vf->index);
3805 return;
3806 }
3807 /*get_buf_spec_idx_by_canvas_config(hw,
3808 &vf->canvas0_config[0]);*/
3809 if (hw->buffer_spec[buf_spec_num].used == 2) {
3810 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3811 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3812 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3813 __func__, vf, frame_index,
3814 p_H264_Dpb->mFrameStore[frame_index].poc,
3815 buf_spec_num,
3816 hw->buffer_spec[buf_spec_num].used,
3817 hw->buffer_spec[buf_spec_num].vf_ref);
3818 hw->buffer_spec[buf_spec_num].vf_ref--;
3819 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3820 set_frame_output_flag(&hw->dpb, frame_index);
3821 } else {
3822 unsigned long flags;
3823 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3824 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3825 __func__, vf, buf_spec_num,
3826 hw->buffer_spec[buf_spec_num].used,
3827 hw->buffer_spec[buf_spec_num].vf_ref);
3828 spin_lock_irqsave(&hw->bufspec_lock, flags);
3829 hw->buffer_spec[buf_spec_num].vf_ref--;
3830 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3831 if (hw->buffer_spec[buf_spec_num].used == 3)
3832 hw->buffer_spec[buf_spec_num].used = 4;
3833 else if (hw->buffer_spec[buf_spec_num].used == 5)
3834 hw->buffer_spec[buf_spec_num].used = 0;
3835 }
3836 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3837 if (dpb_is_debug(DECODE_ID(hw),
3838 PRINT_FLAG_DUMP_BUFSPEC))
3839 dump_bufspec(hw, __func__);
3840
3841 }
3842
3843 hw->vf_put_count++;
3844 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3845
3846#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3847 if (hw->buffer_empty_flag)
3848 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3849}
3850
3851static int vh264_event_cb(int type, void *data, void *op_arg)
3852{
3853 unsigned long flags;
3854 struct vdec_s *vdec = op_arg;
3855 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3856
3857 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3858 struct provider_aux_req_s *req =
3859 (struct provider_aux_req_s *)data;
3860 int buf_spec_num;
3861
3862 if (!req->vf) {
3863 req->aux_size = hw->vf_put_count;
3864 return 0;
3865 }
3866 buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3867 spin_lock_irqsave(&hw->lock, flags);
3868 req->aux_buf = NULL;
3869 req->aux_size = 0;
3870 if (buf_spec_num >= 0 &&
3871 buf_spec_num < BUFSPEC_POOL_SIZE &&
3872 is_buf_spec_in_disp_q(hw, buf_spec_num)
3873 ) {
3874 req->aux_buf =
3875 hw->buffer_spec[buf_spec_num].aux_data_buf;
3876 req->aux_size =
3877 hw->buffer_spec[buf_spec_num].aux_data_size;
3878#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3879 req->dv_enhance_exist =
3880 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3881#else
3882 req->dv_enhance_exist = 0;
3883#endif
3884 }
3885 spin_unlock_irqrestore(&hw->lock, flags);
3886
3887 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3888 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3889 __func__, type, buf_spec_num, req->aux_size);
3890 }
3891
3892 return 0;
3893}
3894
3895static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3896 u32 index)
3897{
3898 struct canvas_config_s *p_canvas_config;
3899 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3900 force_rate_framebase : force_rate_streambase;
3901 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3902 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3903 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3904
3905 /* signal_type */
3906 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3907 vf->signal_type = hw->video_signal_from_vui;
3908 if (hw->is_used_v4l) {
3909 struct aml_vdec_hdr_infos hdr;
3910 struct aml_vcodec_ctx *ctx =
3911 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3912
3913 memset(&hdr, 0, sizeof(hdr));
3914 hdr.signal_type = hw->video_signal_from_vui;
3915 vdec_v4l_set_hdr_infos(ctx, &hdr);
3916 }
3917 } else
3918 vf->signal_type = 0;
3919
3920 vf->width = hw->frame_width;
3921 vf->height = hw->frame_height;
3922 if (force_rate) {
3923 if (force_rate == -1)
3924 vf->duration = 0;
3925 else
3926 vf->duration = 96000/force_rate;
3927 } else
3928 vf->duration = hw->frame_dur;
3929 vf->ratio_control =
3930 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3931 DISP_RATIO_ASPECT_RATIO_BIT;
3932 vf->orientation = hw->vh264_rotation;
3933
3934 if (hw->mmu_enable)
3935 return;
3936
3937 vf->canvas0Addr = vf->canvas1Addr = -1;
3938#ifdef NV21
3939 vf->plane_num = 2;
3940#else
3941 vf->plane_num = 3;
3942#endif
3943
3944 if (IS_VDEC_DW(hw)) {
3945 vf->width = (hw->frame_width /2);
3946 if (IS_VDEC_DW(hw) == 2)
3947 vf->height = (hw->frame_height /2);
3948 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3949 } else
3950 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3951
3952 vf->canvas0_config[0] = p_canvas_config[0];
3953 vf->canvas0_config[1] = p_canvas_config[1];
3954#ifndef NV21
3955 vf->canvas0_config[2] = p_canvas_config[2];
3956#endif
3957 vf->canvas1_config[0] = p_canvas_config[0];
3958 vf->canvas1_config[1] = p_canvas_config[1];
3959#ifndef NV21
3960 vf->canvas1_config[2] = p_canvas_config[2];
3961#endif
3962}
3963
3964static void get_picture_qos_info(struct StorablePicture *picture)
3965{
3966 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3967 unsigned char a[3];
3968 unsigned char i, j, t;
3969 unsigned long data;
3970
3971 get_random_bytes(&data, sizeof(unsigned long));
3972 if (picture->slice_type == I_SLICE)
3973 data = 0;
3974 a[0] = data & 0xff;
3975 a[1] = (data >> 8) & 0xff;
3976 a[2] = (data >> 16) & 0xff;
3977
3978 for (i = 0; i < 3; i++)
3979 for (j = i+1; j < 3; j++) {
3980 if (a[j] < a[i]) {
3981 t = a[j];
3982 a[j] = a[i];
3983 a[i] = t;
3984 } else if (a[j] == a[i]) {
3985 a[i]++;
3986 t = a[j];
3987 a[j] = a[i];
3988 a[i] = t;
3989 }
3990 }
3991 picture->max_mv = a[2];
3992 picture->avg_mv = a[1];
3993 picture->min_mv = a[0];
3994 /*
3995 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3996 data, a[0], a[1], a[2]);
3997 */
3998
3999 get_random_bytes(&data, sizeof(unsigned long));
4000 a[0] = data & 0x1f;
4001 a[1] = (data >> 8) & 0x3f;
4002 a[2] = (data >> 16) & 0x7f;
4003
4004 for (i = 0; i < 3; i++)
4005 for (j = i+1; j < 3; j++) {
4006 if (a[j] < a[i]) {
4007 t = a[j];
4008 a[j] = a[i];
4009 a[i] = t;
4010 } else if (a[j] == a[i]) {
4011 a[i]++;
4012 t = a[j];
4013 a[j] = a[i];
4014 a[i] = t;
4015 }
4016 }
4017 picture->max_qp = a[2];
4018 picture->avg_qp = a[1];
4019 picture->min_qp = a[0];
4020 /*
4021 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4022 data, a[0], a[1], a[2]);
4023 */
4024
4025 get_random_bytes(&data, sizeof(unsigned long));
4026 a[0] = data & 0x1f;
4027 a[1] = (data >> 8) & 0x3f;
4028 a[2] = (data >> 16) & 0x7f;
4029
4030 for (i = 0; i < 3; i++)
4031 for (j = i+1; j < 3; j++) {
4032 if (a[j] < a[i]) {
4033 t = a[j];
4034 a[j] = a[i];
4035 a[i] = t;
4036 } else if (a[j] == a[i]) {
4037 a[i]++;
4038 t = a[j];
4039 a[j] = a[i];
4040 a[i] = t;
4041 }
4042 }
4043 picture->max_skip = a[2];
4044 picture->avg_skip = a[1];
4045 picture->min_skip = a[0];
4046
4047
4048 /*
4049 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4050 data,a[0], a[1], a[2]);
4051 */
4052 } else {
4053 uint32_t blk88_y_count;
4054 uint32_t blk88_c_count;
4055 uint32_t blk22_mv_count;
4056 uint32_t rdata32;
4057 int32_t mv_hi;
4058 int32_t mv_lo;
4059 uint32_t rdata32_l;
4060 uint32_t mvx_L0_hi;
4061 uint32_t mvy_L0_hi;
4062 uint32_t mvx_L1_hi;
4063 uint32_t mvy_L1_hi;
4064 int64_t value;
4065 uint64_t temp_value;
4066/*
4067#define DEBUG_QOS
4068*/
4069#ifdef DEBUG_QOS
4070 int pic_number = picture->poc;
4071#endif
4072
4073 picture->max_mv = 0;
4074 picture->avg_mv = 0;
4075 picture->min_mv = 0;
4076
4077 picture->max_skip = 0;
4078 picture->avg_skip = 0;
4079 picture->min_skip = 0;
4080
4081 picture->max_qp = 0;
4082 picture->avg_qp = 0;
4083 picture->min_qp = 0;
4084
4085
4086
4087
4088
4089 /* set rd_idx to 0 */
4090 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4091 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4092 if (blk88_y_count == 0) {
4093#ifdef DEBUG_QOS
4094 pr_info(" [Picture %d Quality] NO Data yet.\n",
4095 pic_number);
4096#endif
4097 /* reset all counts */
4098 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4099 return;
4100 }
4101 /* qp_y_sum */
4102 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4103#ifdef DEBUG_QOS
4104 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4105 pic_number, rdata32/blk88_y_count,
4106 rdata32, blk88_y_count);
4107#endif
4108 picture->avg_qp = rdata32/blk88_y_count;
4109 /* intra_y_count */
4110 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4111#ifdef DEBUG_QOS
4112 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4113 pic_number, rdata32*100/blk88_y_count,
4114 '%', rdata32);
4115#endif
4116 /* skipped_y_count */
4117 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4118#ifdef DEBUG_QOS
4119 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4120 pic_number, rdata32*100/blk88_y_count,
4121 '%', rdata32);
4122#endif
4123 picture->avg_skip = rdata32*100/blk88_y_count;
4124 /* coeff_non_zero_y_count */
4125 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4126#ifdef DEBUG_QOS
4127 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4128 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4129 '%', rdata32);
4130#endif
4131 /* blk66_c_count */
4132 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4133 if (blk88_c_count == 0) {
4134#ifdef DEBUG_QOS
4135 pr_info(" [Picture %d Quality] NO Data yet.\n",
4136 pic_number);
4137#endif
4138 /* reset all counts */
4139 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4140 return;
4141 }
4142 /* qp_c_sum */
4143 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4144#ifdef DEBUG_QOS
4145 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4146 pic_number, rdata32/blk88_c_count,
4147 rdata32, blk88_c_count);
4148#endif
4149 /* intra_c_count */
4150 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4151#ifdef DEBUG_QOS
4152 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4153 pic_number, rdata32*100/blk88_c_count,
4154 '%', rdata32);
4155#endif
4156 /* skipped_cu_c_count */
4157 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4158#ifdef DEBUG_QOS
4159 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4160 pic_number, rdata32*100/blk88_c_count,
4161 '%', rdata32);
4162#endif
4163 /* coeff_non_zero_c_count */
4164 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4165#ifdef DEBUG_QOS
4166 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4167 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4168 '%', rdata32);
4169#endif
4170
4171 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4172 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4173 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4174#ifdef DEBUG_QOS
4175 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4176 pic_number, (rdata32>>0)&0xff);
4177#endif
4178 picture->min_qp = (rdata32>>0)&0xff;
4179
4180#ifdef DEBUG_QOS
4181 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4182 pic_number, (rdata32>>8)&0xff);
4183#endif
4184 picture->max_qp = (rdata32>>8)&0xff;
4185
4186#ifdef DEBUG_QOS
4187 pr_info(" [Picture %d Quality] C QP min : %d\n",
4188 pic_number, (rdata32>>16)&0xff);
4189 pr_info(" [Picture %d Quality] C QP max : %d\n",
4190 pic_number, (rdata32>>24)&0xff);
4191#endif
4192
4193 /* blk22_mv_count */
4194 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4195 if (blk22_mv_count == 0) {
4196#ifdef DEBUG_QOS
4197 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4198 pic_number);
4199#endif
4200 /* reset all counts */
4201 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4202 return;
4203 }
4204 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4205 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4206 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4207 /* should all be 0x00 or 0xff */
4208#ifdef DEBUG_QOS
4209 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4210 pic_number, rdata32);
4211#endif
4212 mvx_L0_hi = ((rdata32>>0)&0xff);
4213 mvy_L0_hi = ((rdata32>>8)&0xff);
4214 mvx_L1_hi = ((rdata32>>16)&0xff);
4215 mvy_L1_hi = ((rdata32>>24)&0xff);
4216
4217 /* mvx_L0_count[31:0] */
4218 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4219 temp_value = mvx_L0_hi;
4220 temp_value = (temp_value << 32) | rdata32_l;
4221
4222 if (mvx_L0_hi & 0x80)
4223 value = 0xFFFFFFF000000000 | temp_value;
4224 else
4225 value = temp_value;
4226 value = div_s64(value, blk22_mv_count);
4227#ifdef DEBUG_QOS
4228 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4229 pic_number, (int)(value),
4230 value, blk22_mv_count);
4231#endif
4232 picture->avg_mv = value;
4233
4234 /* mvy_L0_count[31:0] */
4235 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4236 temp_value = mvy_L0_hi;
4237 temp_value = (temp_value << 32) | rdata32_l;
4238
4239 if (mvy_L0_hi & 0x80)
4240 value = 0xFFFFFFF000000000 | temp_value;
4241 else
4242 value = temp_value;
4243#ifdef DEBUG_QOS
4244 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4245 pic_number, rdata32_l/blk22_mv_count,
4246 value, blk22_mv_count);
4247#endif
4248
4249 /* mvx_L1_count[31:0] */
4250 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4251 temp_value = mvx_L1_hi;
4252 temp_value = (temp_value << 32) | rdata32_l;
4253 if (mvx_L1_hi & 0x80)
4254 value = 0xFFFFFFF000000000 | temp_value;
4255 else
4256 value = temp_value;
4257#ifdef DEBUG_QOS
4258 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4259 pic_number, rdata32_l/blk22_mv_count,
4260 value, blk22_mv_count);
4261#endif
4262
4263 /* mvy_L1_count[31:0] */
4264 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4265 temp_value = mvy_L1_hi;
4266 temp_value = (temp_value << 32) | rdata32_l;
4267 if (mvy_L1_hi & 0x80)
4268 value = 0xFFFFFFF000000000 | temp_value;
4269 else
4270 value = temp_value;
4271#ifdef DEBUG_QOS
4272 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4273 pic_number, rdata32_l/blk22_mv_count,
4274 value, blk22_mv_count);
4275#endif
4276
4277 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4278 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4279 mv_hi = (rdata32>>16)&0xffff;
4280 if (mv_hi & 0x8000)
4281 mv_hi = 0x8000 - mv_hi;
4282#ifdef DEBUG_QOS
4283 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4284 pic_number, mv_hi);
4285#endif
4286 picture->max_mv = mv_hi;
4287
4288 mv_lo = (rdata32>>0)&0xffff;
4289 if (mv_lo & 0x8000)
4290 mv_lo = 0x8000 - mv_lo;
4291#ifdef DEBUG_QOS
4292 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4293 pic_number, mv_lo);
4294#endif
4295 picture->min_mv = mv_lo;
4296
4297 /* {mvy_L0_max, mvy_L0_min} */
4298 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4299 mv_hi = (rdata32>>16)&0xffff;
4300 if (mv_hi & 0x8000)
4301 mv_hi = 0x8000 - mv_hi;
4302#ifdef DEBUG_QOS
4303 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4304 pic_number, mv_hi);
4305#endif
4306
4307 mv_lo = (rdata32>>0)&0xffff;
4308 if (mv_lo & 0x8000)
4309 mv_lo = 0x8000 - mv_lo;
4310#ifdef DEBUG_QOS
4311 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4312 pic_number, mv_lo);
4313#endif
4314
4315 /* {mvx_L1_max, mvx_L1_min} */
4316 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4317 mv_hi = (rdata32>>16)&0xffff;
4318 if (mv_hi & 0x8000)
4319 mv_hi = 0x8000 - mv_hi;
4320#ifdef DEBUG_QOS
4321 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4322 pic_number, mv_hi);
4323#endif
4324
4325 mv_lo = (rdata32>>0)&0xffff;
4326 if (mv_lo & 0x8000)
4327 mv_lo = 0x8000 - mv_lo;
4328#ifdef DEBUG_QOS
4329 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4330 pic_number, mv_lo);
4331#endif
4332
4333 /* {mvy_L1_max, mvy_L1_min} */
4334 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4335 mv_hi = (rdata32>>16)&0xffff;
4336 if (mv_hi & 0x8000)
4337 mv_hi = 0x8000 - mv_hi;
4338#ifdef DEBUG_QOS
4339 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4340 pic_number, mv_hi);
4341#endif
4342 mv_lo = (rdata32>>0)&0xffff;
4343 if (mv_lo & 0x8000)
4344 mv_lo = 0x8000 - mv_lo;
4345#ifdef DEBUG_QOS
4346 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4347 pic_number, mv_lo);
4348#endif
4349
4350 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4351#ifdef DEBUG_QOS
4352 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4353 pic_number, rdata32);
4354#endif
4355 /* reset all counts */
4356 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4357 }
4358}
4359
4360static int get_max_dec_frame_buf_size(int level_idc,
4361 int max_reference_frame_num, int mb_width,
4362 int mb_height)
4363{
4364 int pic_size = mb_width * mb_height * 384;
4365
4366 int size = 0;
4367
4368 switch (level_idc) {
4369 case 9:
4370 size = 152064;
4371 break;
4372 case 10:
4373 size = 152064;
4374 break;
4375 case 11:
4376 size = 345600;
4377 break;
4378 case 12:
4379 size = 912384;
4380 break;
4381 case 13:
4382 size = 912384;
4383 break;
4384 case 20:
4385 size = 912384;
4386 break;
4387 case 21:
4388 size = 1824768;
4389 break;
4390 case 22:
4391 size = 3110400;
4392 break;
4393 case 30:
4394 size = 3110400;
4395 break;
4396 case 31:
4397 size = 6912000;
4398 break;
4399 case 32:
4400 size = 7864320;
4401 break;
4402 case 40:
4403 size = 12582912;
4404 break;
4405 case 41:
4406 size = 12582912;
4407 break;
4408 case 42:
4409 size = 13369344;
4410 break;
4411 case 50:
4412 size = 42393600;
4413 break;
4414 case 51:
4415 case 52:
4416 default:
4417 size = 70778880;
4418 break;
4419 }
4420
4421 size /= pic_size;
4422 size = size + 1; /* need one more buffer */
4423
4424 if (max_reference_frame_num > size)
4425 size = max_reference_frame_num;
4426 size = imin(size, 16);
4427
4428 return size;
4429}
4430
4431static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4432{
4433 int i, j;
4434
4435 if (hw->double_write_mode) {
4436 mutex_lock(&vmh264_mutex);
4437 if (hw->decode_pic_count == 0) {
4438 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4439 i = get_buf_spec_by_canvas_pos(hw, j);
4440 if (i >= 0)
4441 config_decode_canvas_ex(hw, i);
4442 }
4443 }
4444 mutex_unlock(&vmh264_mutex);
4445 }
4446}
4447
4448static int vh264_set_params(struct vdec_h264_hw_s *hw,
4449 u32 param1, u32 param2, u32 param3, u32 param4)
4450{
4451 int i, j;
4452 int mb_width, mb_total;
4453 int max_reference_size, level_idc;
4454 int mb_height = 0;
4455 unsigned long flags;
4456 /*int mb_mv_byte;*/
4457 struct vdec_s *vdec = hw_to_vdec(hw);
4458 u32 seq_info2;
4459 int ret = 0;
4460 int active_buffer_spec_num;
4461 unsigned int buf_size;
4462 unsigned int frame_mbs_only_flag;
4463 unsigned int chroma_format_idc, chroma444;
4464 unsigned int crop_infor, crop_bottom, crop_right;
4465 unsigned int used_reorder_dpb_size_margin
4466 = hw->reorder_dpb_size_margin;
4467 u8 *colocate_vaddr = NULL;
4468
4469#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4470 if (vdec->master || vdec->slave)
4471 used_reorder_dpb_size_margin =
4472 reorder_dpb_size_margin_dv;
4473#endif
4474 seq_info2 = param1;
4475 hw->seq_info = param2;
4476
4477 mb_width = seq_info2 & 0xff;
4478 mb_total = (seq_info2 >> 8) & 0xffff;
4479 if (!mb_width && mb_total) /*for 4k2k*/
4480 mb_width = 256;
4481 if (mb_width)
4482 mb_height = mb_total/mb_width;
4483 if (mb_width <= 0 || mb_height <= 0 ||
4484 is_oversize(mb_width << 4, mb_height << 4)) {
4485 dpb_print(DECODE_ID(hw), 0,
4486 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4487 seq_info2,
4488 mb_width,
4489 mb_height);
4490 return -1;
4491 }
4492
4493 if (seq_info2 != 0 &&
4494 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4495 hw->seq_info2 != 0
4496 ) /*picture size changed*/
4497 h264_reconfig(hw);
4498
4499 if (hw->config_bufmgr_done == 0) {
4500 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4501 u32 reg_val;
4502 hw->cfg_param1 = param1;
4503 hw->cfg_param2 = param2;
4504 hw->cfg_param3 = param3;
4505 hw->cfg_param4 = param4;
4506
4507 hw->seq_info2 = seq_info2 & (~0x80000000);
4508 dpb_print(DECODE_ID(hw), 0,
4509 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4510 seq_info2, hw->seq_info);
4511
4512 dpb_init_global(&hw->dpb,
4513 DECODE_ID(hw), 0, 0);
4514
4515 p_H264_Dpb->fast_output_enable = fast_output_enable;
4516 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4517
4518#if 1
4519 /*crop*/
4520 /* AV_SCRATCH_2
4521 bit 15: frame_mbs_only_flag
4522 bit 13-14: chroma_format_idc */
4523 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4524 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4525 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4526
4527 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4528 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4529 (2 - frame_mbs_only_flag) */
4530 crop_infor = param3;
4531 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4532 crop_right = ((crop_infor >> 16) & 0xff)
4533 >> (2 - frame_mbs_only_flag);
4534
4535 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4536 hw->frame_width = mb_width << 4;
4537 hw->frame_height = mb_height << 4;
4538 if (frame_mbs_only_flag) {
4539 hw->frame_height =
4540 hw->frame_height - (2 >> chroma444) *
4541 min(crop_bottom,
4542 (unsigned int)((8 << chroma444) - 1));
4543 hw->frame_width =
4544 hw->frame_width -
4545 (2 >> chroma444) * min(crop_right,
4546 (unsigned
4547 int)((8 << chroma444) - 1));
4548 } else {
4549 hw->frame_height =
4550 hw->frame_height - (4 >> chroma444) *
4551 min(crop_bottom,
4552 (unsigned int)((8 << chroma444)
4553 - 1));
4554 hw->frame_width =
4555 hw->frame_width -
4556 (4 >> chroma444) * min(crop_right,
4557 (unsigned int)((8 << chroma444) - 1));
4558 }
4559 dpb_print(DECODE_ID(hw), 0,
4560 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4561 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4562 dpb_print(DECODE_ID(hw), 0,
4563 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4564 mb_height, crop_right,
4565 hw->frame_width, mb_width);
4566
4567 if (hw->frame_height == 1088)
4568 hw->frame_height = 1080;
4569#endif
4570 if (!hw->mmu_enable) {
4571 mb_width = (mb_width+3) & 0xfffffffc;
4572 mb_height = (mb_height+3) & 0xfffffffc;
4573 }
4574 mb_total = mb_width * mb_height;
4575 hw->mb_width = mb_width;
4576 hw->mb_height = mb_height;
4577 hw->mb_total = mb_total;
4578 if (hw->mmu_enable)
4579 hevc_mcr_sao_global_hw_init(hw,
4580 (hw->mb_width << 4), (hw->mb_height << 4));
4581
4582 reg_val = param4;
4583 level_idc = reg_val & 0xff;
4584 max_reference_size = (reg_val >> 8) & 0xff;
4585 hw->dpb.origin_max_reference = max_reference_size;
4586 dpb_print(DECODE_ID(hw), 0,
4587 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4588 mb_height, mb_width, mb_total,
4589 level_idc, max_reference_size);
4590
4591
4592 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4593 hw->dpb.reorder_pic_num =
4594 get_max_dec_frame_buf_size(level_idc,
4595 max_reference_size, mb_width, mb_height);
4596
4597 dpb_print(DECODE_ID(hw), 0,
4598 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4599 hw->bitstream_restriction_flag,
4600 hw->max_dec_frame_buffering,
4601 hw->dpb.reorder_pic_num);
4602
4603 if ((hw->bitstream_restriction_flag) &&
4604 (hw->max_dec_frame_buffering <
4605 hw->dpb.reorder_pic_num)) {
4606 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4607 dpb_print(DECODE_ID(hw), 0,
4608 "set reorder_pic_num to %d\n",
4609 hw->dpb.reorder_pic_num);
4610 }
4611
4612 active_buffer_spec_num =
4613 hw->dpb.reorder_pic_num
4614 + used_reorder_dpb_size_margin;
4615 hw->max_reference_size =
4616 max_reference_size + reference_buf_margin;
4617
4618 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4619 active_buffer_spec_num = MAX_VF_BUF_NUM;
4620 hw->dpb.reorder_pic_num = active_buffer_spec_num
4621 - used_reorder_dpb_size_margin;
4622 }
4623 hw->dpb.mDPB.size = active_buffer_spec_num;
4624 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4625 hw->max_reference_size = MAX_VF_BUF_NUM;
4626 hw->dpb.max_reference_size = hw->max_reference_size;
4627
4628 if (hw->no_poc_reorder_flag)
4629 hw->dpb.reorder_pic_num = 1;
4630 dpb_print(DECODE_ID(hw), 0,
4631 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4632 __func__, active_buffer_spec_num,
4633 hw->dpb.reorder_pic_num,
4634 hw->max_reference_size);
4635
4636 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4637
4638 mutex_lock(&vmh264_mutex);
4639 if (!hw->mmu_enable) {
4640 config_buf_specs(vdec);
4641 i = get_buf_spec_by_canvas_pos(hw, 0);
4642
4643 if (hw->is_used_v4l) {
4644 if (i != -1) {
4645 pr_info("v4l: delay alloc the buffer.\n");
4646 }
4647 } else {
4648 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4649 config_decode_canvas(hw, i);
4650 else
4651 ret = -1;
4652 }
4653 } else {
4654 if (hw->double_write_mode) {
4655 config_buf_specs_ex(vdec);
4656 } else {
4657 spin_lock_irqsave(&hw->bufspec_lock, flags);
4658 for (i = 0, j = 0;
4659 j < active_buffer_spec_num
4660 && i < BUFSPEC_POOL_SIZE;
4661 i++) {
4662 if (hw->buffer_spec[i].used != -1)
4663 continue;
4664 hw->buffer_spec[i].used = 0;
4665 hw->buffer_spec[i].
4666 alloc_header_addr = 0;
4667 hw->buffer_spec[i].canvas_pos = j;
4668 j++;
4669 }
4670 spin_unlock_irqrestore(&hw->bufspec_lock,
4671 flags);
4672 }
4673 hevc_mcr_config_canv2axitbl(hw, 0);
4674 }
4675 mutex_unlock(&vmh264_mutex);
4676 if (dpb_is_debug(DECODE_ID(hw),
4677 PRINT_FLAG_DUMP_BUFSPEC))
4678 dump_bufspec(hw, __func__);
4679
4680#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4681 buf_size = PAGE_ALIGN(
4682 p_H264_Dpb->colocated_buf_size *
4683 active_buffer_spec_num);
4684#else
4685 buf_size = PAGE_ALIGN(
4686 p_H264_Dpb->colocated_buf_size *
4687 hw->max_reference_size);
4688#endif
4689
4690 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4691 buf_size, DRIVER_NAME,
4692 &hw->collocate_cma_alloc_addr) < 0)
4693 return -1;
4694 if (!vdec_secure(vdec)) {
4695 /* clear for some mosaic problem after reset bufmgr */
4696 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4697 if (colocate_vaddr != NULL) {
4698 memset(colocate_vaddr, 0, buf_size);
4699 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4700 codec_mm_unmap_phyaddr(colocate_vaddr);
4701 }
4702 }
4703
4704 hw->dpb.colocated_mv_addr_start =
4705 hw->collocate_cma_alloc_addr;
4706#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4707 hw->dpb.colocated_mv_addr_end =
4708 hw->dpb.colocated_mv_addr_start +
4709 (p_H264_Dpb->colocated_buf_size *
4710 active_buffer_spec_num);
4711#else
4712 hw->dpb.colocated_mv_addr_end =
4713 hw->dpb.colocated_mv_addr_start +
4714 (p_H264_Dpb->colocated_buf_size *
4715 hw->max_reference_size);
4716#endif
4717 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4718 "callocate cma, %lx, %x\n",
4719 hw->collocate_cma_alloc_addr,
4720 hw->dpb.colocated_mv_addr_start);
4721
4722 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4723 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4724 hw->dpb.colocated_mv_addr_start,
4725 hw->dpb.colocated_mv_addr_end);
4726 if (!hw->mmu_enable) {
4727 mutex_lock(&vmh264_mutex);
4728 if (ret >= 0 && hw->decode_pic_count == 0) {
4729 int buf_cnt;
4730 /* h264_reconfig: alloc later*/
4731 buf_cnt = hw->dpb.mDPB.size;
4732
4733 for (j = 1; j < buf_cnt; j++) {
4734 i = get_buf_spec_by_canvas_pos(hw, j);
4735
4736 if (hw->is_used_v4l) {
4737 pr_info("v4l: delay alloc the buffer.\n");
4738 break;
4739 } else if (alloc_one_buf_spec(hw, i) < 0)
4740 break;
4741
4742 config_decode_canvas(hw, i);
4743 }
4744 }
4745 mutex_unlock(&vmh264_mutex);
4746 } else {
4747 vh264_config_canvs_for_mmu(hw);
4748 }
4749
4750 hw->config_bufmgr_done = 1;
4751
4752 /*end of config_bufmgr_done */
4753 }
4754
4755 return ret;
4756}
4757
4758static void vui_config(struct vdec_h264_hw_s *hw)
4759{
4760 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4761 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4762 /*time*/
4763 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4764 hw->time_scale = p_H264_Dpb->time_scale;
4765 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4766
4767 hw->bitstream_restriction_flag =
4768 p_H264_Dpb->bitstream_restriction_flag;
4769 hw->num_reorder_frames =
4770 p_H264_Dpb->num_reorder_frames;
4771 hw->max_dec_frame_buffering =
4772 p_H264_Dpb->max_dec_frame_buffering;
4773
4774 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4775 "vui_config: pdb %d, %d, %d\n",
4776 p_H264_Dpb->bitstream_restriction_flag,
4777 p_H264_Dpb->num_reorder_frames,
4778 p_H264_Dpb->max_dec_frame_buffering);
4779
4780 hw->fixed_frame_rate_flag = 0;
4781 if (hw->timing_info_present_flag) {
4782 hw->fixed_frame_rate_flag =
4783 p_H264_Dpb->fixed_frame_rate_flag;
4784
4785 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4786 ((!hw->sync_outside) ||
4787 (!hw->frame_dur)))
4788 && hw->num_units_in_tick && hw->time_scale) {
4789 if (hw->use_idr_framerate ||
4790 hw->fixed_frame_rate_flag ||
4791 !hw->frame_dur ||
4792 !hw->duration_from_pts_done
4793 /*|| vh264_running*/) {
4794 u32 frame_dur_es =
4795 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4796 hw->time_scale);
4797 if (hw->frame_dur != frame_dur_es) {
4798 hw->h264_first_valid_pts_ready = false;
4799 hw->h264pts1 = 0;
4800 hw->h264pts2 = 0;
4801 hw->h264_pts_count = 0;
4802 hw->duration_from_pts_done = 0;
4803 fixed_frame_rate_mode =
4804 FIX_FRAME_RATE_OFF;
4805 hw->pts_duration = 0;
4806 hw->frame_dur = frame_dur_es;
4807 vdec_schedule_work(&hw->notify_work);
4808 dpb_print(DECODE_ID(hw),
4809 PRINT_FLAG_DEC_DETAIL,
4810 "frame_dur %d from timing_info\n",
4811 hw->frame_dur);
4812 }
4813
4814 /*hack to avoid use ES frame duration when
4815 *it's half of the rate from system info
4816 * sometimes the encoder is given a wrong
4817 * frame rate but the system side information
4818 * is more reliable
4819 *if ((frame_dur * 2) != frame_dur_es) {
4820 * frame_dur = frame_dur_es;
4821 *}
4822 */
4823 }
4824 }
4825 } else {
4826 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4827 "H.264: timing_info not present\n");
4828 }
4829
4830 /*aspect ratio*/
4831 aspect_ratio_info_present_flag =
4832 p_H264_Dpb->vui_status & 0x1;
4833 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4834
4835 if (aspect_ratio_info_present_flag) {
4836 if (aspect_ratio_idc == EXTEND_SAR) {
4837 hw->h264_ar = 0x3ff;
4838 hw->height_aspect_ratio =
4839 p_H264_Dpb->aspect_ratio_sar_height;
4840 hw->width_aspect_ratio =
4841 p_H264_Dpb->aspect_ratio_sar_width;
4842 } else {
4843 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4844 aspect_ratio_idc); */
4845
4846 switch (aspect_ratio_idc) {
4847 case 1:
4848 hw->h264_ar = 0x3ff;
4849 hw->height_aspect_ratio = 1;
4850 hw->width_aspect_ratio = 1;
4851 break;
4852 case 2:
4853 hw->h264_ar = 0x3ff;
4854 hw->height_aspect_ratio = 11;
4855 hw->width_aspect_ratio = 12;
4856 break;
4857 case 3:
4858 hw->h264_ar = 0x3ff;
4859 hw->height_aspect_ratio = 11;
4860 hw->width_aspect_ratio = 10;
4861 break;
4862 case 4:
4863 hw->h264_ar = 0x3ff;
4864 hw->height_aspect_ratio = 11;
4865 hw->width_aspect_ratio = 16;
4866 break;
4867 case 5:
4868 hw->h264_ar = 0x3ff;
4869 hw->height_aspect_ratio = 33;
4870 hw->width_aspect_ratio = 40;
4871 break;
4872 case 6:
4873 hw->h264_ar = 0x3ff;
4874 hw->height_aspect_ratio = 11;
4875 hw->width_aspect_ratio = 24;
4876 break;
4877 case 7:
4878 hw->h264_ar = 0x3ff;
4879 hw->height_aspect_ratio = 11;
4880 hw->width_aspect_ratio = 20;
4881 break;
4882 case 8:
4883 hw->h264_ar = 0x3ff;
4884 hw->height_aspect_ratio = 11;
4885 hw->width_aspect_ratio = 32;
4886 break;
4887 case 9:
4888 hw->h264_ar = 0x3ff;
4889 hw->height_aspect_ratio = 33;
4890 hw->width_aspect_ratio = 80;
4891 break;
4892 case 10:
4893 hw->h264_ar = 0x3ff;
4894 hw->height_aspect_ratio = 11;
4895 hw->width_aspect_ratio = 18;
4896 break;
4897 case 11:
4898 hw->h264_ar = 0x3ff;
4899 hw->height_aspect_ratio = 11;
4900 hw->width_aspect_ratio = 15;
4901 break;
4902 case 12:
4903 hw->h264_ar = 0x3ff;
4904 hw->height_aspect_ratio = 33;
4905 hw->width_aspect_ratio = 64;
4906 break;
4907 case 13:
4908 hw->h264_ar = 0x3ff;
4909 hw->height_aspect_ratio = 99;
4910 hw->width_aspect_ratio = 160;
4911 break;
4912 case 14:
4913 hw->h264_ar = 0x3ff;
4914 hw->height_aspect_ratio = 3;
4915 hw->width_aspect_ratio = 4;
4916 break;
4917 case 15:
4918 hw->h264_ar = 0x3ff;
4919 hw->height_aspect_ratio = 2;
4920 hw->width_aspect_ratio = 3;
4921 break;
4922 case 16:
4923 hw->h264_ar = 0x3ff;
4924 hw->height_aspect_ratio = 1;
4925 hw->width_aspect_ratio = 2;
4926 break;
4927 default:
4928 if (hw->vh264_ratio >> 16) {
4929 hw->h264_ar = (hw->frame_height *
4930 (hw->vh264_ratio & 0xffff) *
4931 0x100 +
4932 ((hw->vh264_ratio >> 16) *
4933 hw->frame_width / 2)) /
4934 ((hw->vh264_ratio >> 16) *
4935 hw->frame_width);
4936 hw->height_aspect_ratio = 1;
4937 hw->width_aspect_ratio = 1;
4938 } else {
4939 hw->h264_ar = 0x3ff;
4940 hw->height_aspect_ratio = 1;
4941 hw->width_aspect_ratio = 1;
4942 }
4943 break;
4944 }
4945 }
4946 } else {
4947 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4948 "v264dec: aspect_ratio not available from source\n");
4949 if (hw->vh264_ratio >> 16) {
4950 /* high 16 bit is width, low 16 bit is height */
4951 hw->h264_ar =
4952 ((hw->vh264_ratio & 0xffff) *
4953 hw->frame_height * 0x100 +
4954 (hw->vh264_ratio >> 16) *
4955 hw->frame_width / 2) /
4956 ((hw->vh264_ratio >> 16) *
4957 hw->frame_width);
4958 hw->height_aspect_ratio = 1;
4959 hw->width_aspect_ratio = 1;
4960 } else {
4961 hw->h264_ar = 0x3ff;
4962 hw->height_aspect_ratio = 1;
4963 hw->width_aspect_ratio = 1;
4964 }
4965 }
4966
4967 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4968 if (((hw->frame_dur == RATE_2397_FPS)
4969 && (dec_control
4970 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4971 || ((RATE_2997_FPS ==
4972 hw->frame_dur) &&
4973 (dec_control &
4974 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4975 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4976 "force fix frame rate\n");
4977 hw->fixed_frame_rate_flag = 0x40;
4978 }
4979 }
4980
4981 /*video_signal_from_vui: to do .. */
4982}
4983
4984static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4985{
4986 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4987
4988 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4989 if (error_proc_policy & 0x20) {
4990 if (!hw->is_used_v4l)
4991 hw->reset_bufmgr_flag = 1;
4992 }
4993}
4994
4995void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4996{
4997 struct vdec_h264_hw_s *hw =
4998 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4999
5000 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
5001
5002 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
5003 hw->reset_bufmgr_flag = 1;
5004}
5005
5006#ifdef CONSTRAIN_MAX_BUF_NUM
5007static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5008{
5009 int i;
5010 int count = 0;
5011 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5012 if (is_buf_spec_in_disp_q(hw, i) &&
5013 hw->buffer_spec[i].vf_ref > 0)
5014 count++;
5015 }
5016 return count;
5017}
5018
5019static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5020{
5021 int i;
5022 int count = 0;
5023 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5024 if (is_buf_spec_in_use(hw, i))
5025 count++;
5026 }
5027 return count;
5028}
5029#endif
5030
5031
5032static bool is_buffer_available(struct vdec_s *vdec)
5033{
5034 bool buffer_available = 1;
5035 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5036 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5037 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5038 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5039 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5040 ((p_H264_Dpb->mDPB.init_done) &&
5041 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5042 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5043 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5044 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5045 __func__,
5046 kfifo_len(&hw->newframe_q),
5047 have_free_buf_spec(vdec),
5048 p_H264_Dpb->mDPB.init_done,
5049 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5050 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5051 );
5052 buffer_available = 0;
5053 if (dpb_is_debug(DECODE_ID(hw),
5054 DEBUG_DISABLE_RUNREADY_RMBUF))
5055 return buffer_available;
5056
5057 if ((error_proc_policy & 0x4) &&
5058 (error_proc_policy & 0x8)) {
5059 if ((kfifo_len(&hw->display_q) <= 0) &&
5060 (p_H264_Dpb->mDPB.used_size ==
5061 p_H264_Dpb->mDPB.size) &&
5062 (p_Dpb->ref_frames_in_buffer >
5063 (imax(
5064 1, p_Dpb->num_ref_frames)
5065 - p_Dpb->ltref_frames_in_buffer +
5066 force_sliding_margin)))
5067 bufmgr_recover(hw);
5068 else
5069 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5070 } else if ((error_proc_policy & 0x4) &&
5071 (kfifo_len(&hw->display_q) <= 0) &&
5072 ((p_H264_Dpb->mDPB.used_size ==
5073 p_H264_Dpb->mDPB.size) ||
5074 (!have_free_buf_spec(vdec)))) {
5075 enum receviver_start_e state = RECEIVER_INACTIVE;
5076 if ((error_proc_policy & 0x10) &&
5077 vf_get_receiver(vdec->vf_provider_name)) {
5078 state =
5079 vf_notify_receiver(vdec->vf_provider_name,
5080 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5081 NULL);
5082 if ((state == RECEIVER_STATE_NULL)
5083 || (state == RECEIVER_STATE_NONE))
5084 state = RECEIVER_INACTIVE;
5085 }
5086 if (state == RECEIVER_INACTIVE)
5087 bufmgr_recover(hw);
5088 else
5089 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5090 } else if ((error_proc_policy & 0x8) &&
5091 (p_Dpb->ref_frames_in_buffer >
5092 (imax(
5093 1, p_Dpb->num_ref_frames)
5094 - p_Dpb->ltref_frames_in_buffer +
5095 force_sliding_margin)))
5096 bufmgr_recover(hw);
5097 else
5098 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5099
5100 if (hw->reset_bufmgr_flag == 1)
5101 buffer_available = 1;
5102 }
5103
5104 return buffer_available;
5105}
5106
5107#define AUX_TAG_SEI 0x2
5108
5109#define SEI_BUFFERING_PERIOD 0
5110#define SEI_PicTiming 1
5111#define SEI_USER_DATA 4
5112#define SEI_RECOVERY_POINT 6
5113
5114/*
5115 *************************************************************************
5116 * Function:Reads bits from the bitstream buffer
5117 * Input:
5118 byte buffer[]
5119 containing sei message data bits
5120 int totbitoffset
5121 bit offset from start of partition
5122 int bytecount
5123 total bytes in bitstream
5124 int numbits
5125 number of bits to read
5126 * Output:
5127 int *info
5128 * Return:
5129 -1: failed
5130 > 0: the count of bit read
5131 * Attention:
5132 *************************************************************************
5133 */
5134
5135static int get_bits(unsigned char buffer[],
5136 int totbitoffset,
5137 int *info,
5138 int bytecount,
5139 int numbits)
5140{
5141 register int inf;
5142 long byteoffset;
5143 int bitoffset;
5144
5145 int bitcounter = numbits;
5146
5147 byteoffset = totbitoffset / 8;
5148 bitoffset = 7 - (totbitoffset % 8);
5149
5150 inf = 0;
5151 while (numbits) {
5152 inf <<= 1;
5153 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5154 numbits--;
5155 bitoffset--;
5156 if (bitoffset < 0) {
5157 byteoffset++;
5158 bitoffset += 8;
5159 if (byteoffset > bytecount)
5160 return -1;
5161 }
5162 }
5163
5164 *info = inf;
5165
5166
5167 return bitcounter;
5168}
5169
5170static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5171 u8 *sei_data_buf,
5172 u8 *sei_data_buf_end)
5173{
5174 int payload_type;
5175 int payload_size;
5176 u8 *p_sei;
5177 int temp = 0;
5178 int bit_offset;
5179 int read_size;
5180 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5181
5182 p_sei = sei_data_buf;
5183 read_size = 0;
5184 payload_type = 0;
5185 do {
5186 if (p_sei >= sei_data_buf_end)
5187 return read_size;
5188
5189 payload_type += *p_sei;
5190 read_size++;
5191 } while (*p_sei++ == 255);
5192
5193
5194 payload_size = 0;
5195 do {
5196 if (p_sei >= sei_data_buf_end)
5197 return read_size;
5198
5199 payload_size += *p_sei;
5200 read_size++;
5201 } while (*p_sei++ == 255);
5202
5203
5204 if (p_sei + payload_size > sei_data_buf_end) {
5205 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5206 "%s: payload_type = %d, payload_size = %d is over\n",
5207 __func__, payload_type, payload_size);
5208 return read_size;
5209 }
5210 bit_offset = 0;
5211
5212 if (payload_size <= 0) {
5213 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5214 "%s warning: this is a null sei message for payload_type = %d\n",
5215 __func__, payload_type);
5216 return read_size;
5217 }
5218 switch (payload_type) {
5219 case SEI_BUFFERING_PERIOD:
5220 break;
5221 case SEI_PicTiming:
5222 if (p_H264_Dpb->vui_status & 0xc) {
5223 int cpb_removal_delay;
5224 int dpb_output_delay;
5225 u32 delay_len;
5226
5227 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5228 cpb_removal_delay
5229 = (delay_len & 0x1F) + 1;
5230 dpb_output_delay
5231 = ((delay_len >> 5) & 0x1F) + 1;
5232
5233 get_bits(p_sei, bit_offset,
5234 &temp, payload_size,
5235 dpb_output_delay+cpb_removal_delay);
5236 bit_offset += dpb_output_delay+cpb_removal_delay;
5237 }
5238 if (p_H264_Dpb->vui_status & 0x10) {
5239 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5240 bit_offset += 4;
5241 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5242 }
5243 break;
5244 case SEI_USER_DATA:
5245 if (enable_itu_t35) {
5246 int i;
5247 int j;
5248 int data_len;
5249 u8 *user_data_buf;
5250
5251 user_data_buf
5252 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5253 /* user data length should be align with 8 bytes,
5254 if not, then padding with zero*/
5255 for (i = 0; i < payload_size; i += 8) {
5256 for (j = 0; j < 8; j++) {
5257 int index;
5258
5259 index = i+7-j;
5260 if (index >= payload_size)
5261 user_data_buf[i+j] = 0;
5262 else
5263 user_data_buf[i+j]
5264 = p_sei[i+7-j];
5265 }
5266 }
5267
5268 data_len = payload_size;
5269 if (payload_size % 8)
5270 data_len = ((payload_size + 8) >> 3) << 3;
5271
5272 hw->sei_itu_data_len += data_len;
5273 /*
5274 dpb_print(DECODE_ID(hw), 0,
5275 "%s: user data, and len = %d:\n",
5276 __func__, hw->sei_itu_data_len);
5277 */
5278 }
5279 break;
5280 case SEI_RECOVERY_POINT:
5281 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5282 break;
5283 }
5284
5285 return read_size + payload_size;
5286}
5287
5288static void parse_sei_data(struct vdec_h264_hw_s *hw,
5289 u8 *sei_data_buf,
5290 int len)
5291{
5292 char *p_sei;
5293 char *p_sei_end;
5294 int parsed_size;
5295 int read_size;
5296
5297
5298 p_sei = sei_data_buf;
5299 p_sei_end = p_sei + len;
5300 parsed_size = 0;
5301 while (parsed_size < len) {
5302 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5303 p_sei += read_size;
5304 parsed_size += read_size;
5305 if (*p_sei == 0x80) {
5306 p_sei++;
5307 parsed_size++;
5308 }
5309 }
5310}
5311
5312static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5313{
5314 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5315 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5316 unsigned mby_mbx = READ_VREG(MBY_MBX);
5317 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5318 unsigned decode_mb_count =
5319 ((mby_mbx & 0xff) * hw->mb_width +
5320 (((mby_mbx >> 8) & 0xff) + 1));
5321 if (mby_mbx == 0)
5322 return;
5323 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5324 mb_total /= 2;
5325 if (error_proc_policy & 0x100) {
5326 if (decode_mb_count < mb_total)
5327 p->data_flag |= ERROR_FLAG;
5328 }
5329
5330 if ((error_proc_policy & 0x200) &&
5331 READ_VREG(ERROR_STATUS_REG) != 0) {
5332 p->data_flag |= ERROR_FLAG;
5333 }
5334
5335 if (p->data_flag & ERROR_FLAG) {
5336 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5337 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5338 __func__,
5339 hw->seq_info2,
5340 mby_mbx,
5341 mb_total,
5342 decode_mb_count,
5343 READ_VREG(ERROR_STATUS_REG)
5344 );
5345
5346 }
5347}
5348
5349static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5350{
5351 int i;
5352 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5353 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5354 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5355 u32 debug_tag;
5356 int ret;
5357
5358 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5359#if 1
5360 unsigned short *p = (unsigned short *)hw->lmem_addr;
5361 dma_sync_single_for_cpu(
5362 amports_get_dma_device(),
5363 hw->lmem_addr_remap,
5364 PAGE_SIZE,
5365 DMA_FROM_DEVICE);
5366 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5367 int ii;
5368 for (ii = 0; ii < 4; ii++) {
5369 p_H264_Dpb->dpb_param.l.data[i+ii] =
5370 p[i+3-ii];
5371 if (dpb_is_debug(DECODE_ID(hw),
5372 RRINT_FLAG_RPM)) {
5373 if (((i + ii) & 0xf) == 0)
5374 dpb_print(DECODE_ID(hw),
5375 0, "%04x:",
5376 i);
5377 dpb_print_cont(DECODE_ID(hw),
5378 0, "%04x ",
5379 p[i+3-ii]);
5380 if (((i + ii + 1) & 0xf) == 0)
5381 dpb_print_cont(
5382 DECODE_ID(hw),
5383 0, "\r\n");
5384 }
5385 }
5386 }
5387
5388 p_H264_Dpb->bitstream_restriction_flag =
5389 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5390 p_H264_Dpb->num_reorder_frames =
5391 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5392 p_H264_Dpb->max_dec_frame_buffering =
5393 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5394
5395 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5396 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5397 p_H264_Dpb->bitstream_restriction_flag,
5398 p_H264_Dpb->num_reorder_frames,
5399 p_H264_Dpb->max_dec_frame_buffering);
5400 hw->bitstream_restriction_flag =
5401 p_H264_Dpb->bitstream_restriction_flag;
5402 hw->num_reorder_frames =
5403 p_H264_Dpb->num_reorder_frames;
5404 hw->max_dec_frame_buffering =
5405 p_H264_Dpb->max_dec_frame_buffering;
5406#endif
5407
5408 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5409 reset_process_time(hw);
5410 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5411 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5412 vdec_schedule_work(&hw->work);
5413 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5414 u16 data_hight;
5415 u16 data_low;
5416 u32 video_signal;
5417
5418 int slice_header_process_status = 0;
5419 int I_flag;
5420 /*unsigned char is_idr;*/
5421 unsigned short *p = (unsigned short *)hw->lmem_addr;
5422 reset_process_time(hw);
5423
5424 if (hw->is_used_v4l) {
5425 struct aml_vcodec_ctx *ctx =
5426 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5427
5428 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5429 //amvdec_stop();
5430 hw->dec_result = DEC_RESULT_DONE;
5431 vdec_schedule_work(&hw->work);
5432 return IRQ_HANDLED;
5433 }
5434 }
5435
5436 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5437 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5438 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5439 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5440 if (input_frame_based(vdec) &&
5441 frmbase_cont_bitlevel2 != 0 &&
5442 READ_VREG(VIFF_BIT_CNT) <
5443 frmbase_cont_bitlevel2 &&
5444 hw->get_data_count >= 0x70000000) {
5445 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5446 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5447 __func__,
5448 READ_VREG(VIFF_BIT_CNT));
5449
5450 goto empty_proc;
5451 }
5452
5453 dma_sync_single_for_cpu(
5454 amports_get_dma_device(),
5455 hw->lmem_addr_remap,
5456 PAGE_SIZE,
5457 DMA_FROM_DEVICE);
5458#if 0
5459 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5460 if (!is_buffer_available(vdec)) {
5461 hw->buffer_empty_flag = 1;
5462 dpb_print(DECODE_ID(hw),
5463 PRINT_FLAG_UCODE_EVT,
5464 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5465 __func__,
5466 kfifo_len(&hw->newframe_q),
5467 have_free_buf_spec(vdec),
5468 p_H264_Dpb->mDPB.init_done,
5469 p_H264_Dpb->mDPB.used_size,
5470 p_H264_Dpb->mDPB.size,
5471 is_there_unused_frame_from_dpb(
5472 &p_H264_Dpb->mDPB));
5473 return IRQ_HANDLED;
5474 }
5475 }
5476
5477 hw->buffer_empty_flag = 0;
5478#endif
5479#ifdef SEND_PARAM_WITH_REG
5480 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5481 unsigned int data32;
5482
5483 do {
5484 data32 = READ_VREG(RPM_CMD_REG);
5485 /* printk("%x\n", data32); */
5486 } while ((data32&0x10000) == 0);
5487 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5488 WRITE_VREG(RPM_CMD_REG, 0);
5489 /* printk("%x:%x\n", i,data32); */
5490 }
5491#else
5492 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5493 int ii;
5494
5495 for (ii = 0; ii < 4; ii++) {
5496 p_H264_Dpb->dpb_param.l.data[i+ii] =
5497 p[i+3-ii];
5498 if (dpb_is_debug(DECODE_ID(hw),
5499 RRINT_FLAG_RPM)) {
5500 if (((i + ii) & 0xf) == 0)
5501 dpb_print(DECODE_ID(hw),
5502 0, "%04x:",
5503 i);
5504 dpb_print_cont(DECODE_ID(hw),
5505 0, "%04x ",
5506 p[i+3-ii]);
5507 if (((i + ii + 1) & 0xf) == 0)
5508 dpb_print_cont(
5509 DECODE_ID(hw),
5510 0, "\r\n");
5511 }
5512 }
5513 }
5514#endif
5515 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5516 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5517
5518 video_signal = (data_hight << 16) | data_low;
5519 hw->video_signal_from_vui =
5520 ((video_signal & 0xffff) << 8) |
5521 ((video_signal & 0xff0000) >> 16) |
5522 ((video_signal & 0x3f000000));
5523
5524
5525 /*dpb_print(DECODE_ID(hw),
5526 0,
5527 "video_signal_from_vui:0x%x, "
5528 "data_low:0x%x, data_hight:0x%x\n",
5529 hw->video_signal_from_vui,
5530 data_low,
5531 data_hight);*/
5532
5533 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5534
5535 if (hw->config_bufmgr_done == 0) {
5536 hw->dec_result = DEC_RESULT_DONE;
5537 vdec_schedule_work(&hw->work);
5538 dpb_print(DECODE_ID(hw),
5539 PRINT_FLAG_UCODE_EVT,
5540 "config_bufmgr not done, discard frame\n");
5541 return IRQ_HANDLED;
5542 } else if ((hw->first_i_policy & 0x3) != 0) {
5543 unsigned char is_i_slice =
5544 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5545 == I_Slice)
5546 ? 1 : 0;
5547 unsigned char is_idr =
5548 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5549 == 5);
5550 if ((hw->first_i_policy & 0x3) == 0x3)
5551 is_i_slice = is_idr;
5552 if (!is_i_slice) {
5553 if (hw->has_i_frame == 0) {
5554 amvdec_stop();
5555 vdec->mc_loaded = 0;
5556 hw->dec_result = DEC_RESULT_DONE;
5557 vdec_schedule_work(&hw->work);
5558 dpb_print(DECODE_ID(hw),
5559 PRINT_FLAG_UCODE_EVT,
5560 "has_i_frame is 0, discard none I(DR) frame\n");
5561 return IRQ_HANDLED;
5562 }
5563 } else {
5564 if (hw->skip_frame_count < 0 || is_idr) {
5565 /* second I */
5566 hw->dec_flag &= (~NODISP_FLAG);
5567 hw->skip_frame_count = 0;
5568 }
5569 if (hw->has_i_frame == 0 &&
5570 (!is_idr)) {
5571 int skip_count =
5572 (hw->first_i_policy >> 8) & 0xff;
5573 /* first I (not IDR) */
5574 if ((hw->first_i_policy & 0x3) == 2)
5575 hw->skip_frame_count =
5576 -1 - skip_count;
5577 else
5578 hw->skip_frame_count =
5579 skip_count;
5580 if (hw->skip_frame_count != 0)
5581 hw->dec_flag |= NODISP_FLAG;
5582 }
5583 }
5584 }
5585 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5586 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5587 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5588 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5589 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5590 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5591 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5592 ? I_FLAG : 0;
5593
5594 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5595 flush_dpb(p_H264_Dpb);
5596
5597 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5598 (p_H264_Dpb->mSlice.structure == FRAME)) {
5599 hw->data_flag = NULL_FLAG;
5600 goto pic_done_proc;
5601 }
5602
5603 slice_header_process_status =
5604 h264_slice_header_process(p_H264_Dpb);
5605 if (hw->mmu_enable)
5606 hevc_sao_set_slice_type(hw,
5607 slice_header_process_status,
5608 hw->dpb.mSlice.idr_flag);
5609 vui_config(hw);
5610
5611 if (p_H264_Dpb->mVideo.dec_picture) {
5612 int cfg_ret = 0;
5613 bool field_pic_flag = false;
5614
5615 if (slice_header_process_status == 1) {
5616 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5617 field_pic_flag =
5618 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5619 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5620 true : false;
5621 }
5622
5623 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5624 (((unsigned long)(hw->vh264_amstream_dec_info
5625 .param)) & 0x8))) {
5626 p_H264_Dpb->fast_output_enable =
5627 H264_OUTPUT_MODE_FAST;
5628 }
5629 else
5630 p_H264_Dpb->fast_output_enable
5631 = fast_output_enable;
5632 hw->data_flag = I_flag;
5633 if ((p_H264_Dpb->
5634 dpb_param.dpb.NAL_info_mmco & 0x1f)
5635 == 5)
5636 hw->data_flag |= IDR_FLAG;
5637 dpb_print(DECODE_ID(hw),
5638 PRINT_FLAG_VDEC_STATUS,
5639 "==================> frame count %d to skip %d\n",
5640 hw->decode_pic_count+1,
5641 hw->skip_frame_count);
5642 } else if (error_proc_policy & 0x100){
5643 struct StorablePicture *p =
5644 p_H264_Dpb->mVideo.dec_picture;
5645 unsigned mby_mbx = READ_VREG(MBY_MBX);
5646 unsigned decode_mb_count =
5647 ((mby_mbx & 0xff) * hw->mb_width +
5648 (((mby_mbx >> 8) & 0xff) + 1));
5649 if (decode_mb_count <
5650 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5651 (1 + p->mb_aff_frame_flag))) {
5652 dpb_print(DECODE_ID(hw),
5653 PRINT_FLAG_VDEC_STATUS,
5654 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5655 p_H264_Dpb->dpb_param.l.
5656 data[FIRST_MB_IN_SLICE],
5657 READ_VREG(MBY_MBX),
5658 decode_mb_count);
5659 p->data_flag |= ERROR_FLAG;
5660 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5661 p->data_flag |= ERROR_FLAG;
5662 goto pic_done_proc;
5663 }
5664 }
5665
5666 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5667 hw->new_iframe_flag = 1;
5668 }
5669 if (hw->new_iframe_flag) {
5670 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5671 hw->new_iframe_flag = 0;
5672 hw->ref_err_flush_dpb_flag = 1;
5673 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5674 hw->new_iframe_flag = 0;
5675 hw->ref_err_flush_dpb_flag = 0;
5676 }
5677 }
5678
5679 if (error_proc_policy & 0x400) {
5680 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5681 if (ret != 0) {
5682 hw->reflist_error_count ++;
5683 dpb_print(DECODE_ID(hw), 0,
5684 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5685 ret,
5686 hw->decode_pic_count+1,
5687 hw->skip_frame_count,
5688 hw->reflist_error_count);
5689
5690 if (hw->ref_err_flush_dpb_flag) {
5691 flush_dpb(p_H264_Dpb);
5692 p_H264_Dpb->colocated_buf_map = 0;
5693 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5694 p_H264_Dpb->colocated_buf_map |= 1 <<
5695 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5696 }
5697 }
5698
5699 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5700 if (((error_proc_policy & 0x80)
5701 && ((hw->dec_flag &
5702 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5703 hw->reset_bufmgr_flag = 1;
5704 hw->reflist_error_count =0;
5705 amvdec_stop();
5706 vdec->mc_loaded = 0;
5707 hw->dec_result = DEC_RESULT_DONE;
5708 vdec_schedule_work(&hw->work);
5709 return IRQ_HANDLED;
5710 }
5711 } else
5712 hw->reflist_error_count = 0;
5713 }
5714 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5715 && p_H264_Dpb->dpb_error_flag != 0) {
5716 dpb_print(DECODE_ID(hw), 0,
5717 "dpb error %d\n",
5718 p_H264_Dpb->dpb_error_flag);
5719 hw->data_flag |= ERROR_FLAG;
5720 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5721 if ((error_proc_policy & 0x80) &&
5722 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5723 hw->reset_bufmgr_flag = 1;
5724 amvdec_stop();
5725 vdec->mc_loaded = 0;
5726 hw->dec_result = DEC_RESULT_DONE;
5727 vdec_schedule_work(&hw->work);
5728 return IRQ_HANDLED;
5729 }
5730 }
5731
5732 cfg_ret = config_decode_buf(hw,
5733 p_H264_Dpb->mVideo.dec_picture);
5734 if (cfg_ret < 0) {
5735 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5736 "config_decode_buf fail (%d)\n",
5737 cfg_ret);
5738 if (error_proc_policy & 0x2) {
5739 release_cur_decoding_buf(hw);
5740 /*hw->data_flag |= ERROR_FLAG;*/
5741 hw->reset_bufmgr_flag = 1;
5742 hw->dec_result = DEC_RESULT_DONE;
5743 vdec_schedule_work(&hw->work);
5744 return IRQ_HANDLED;
5745 } else
5746 hw->data_flag |= ERROR_FLAG;
5747 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5748 }
5749 }
5750
5751 if (slice_header_process_status == 1)
5752 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5753 else
5754 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5755 hw->last_mby_mbx = 0;
5756 hw->last_vld_level = 0;
5757 start_process_time(hw);
5758 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5759 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5760pic_done_proc:
5761 reset_process_time(hw);
5762
5763 if (input_frame_based(vdec) &&
5764 (!(hw->i_only & 0x2)) &&
5765 frmbase_cont_bitlevel != 0 &&
5766 READ_VREG(VIFF_BIT_CNT) >
5767 frmbase_cont_bitlevel) {
5768 /*handle the case: multi pictures in one packet*/
5769 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5770 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5771 __func__,
5772 hw->decode_pic_count,
5773 READ_VREG(VIFF_BIT_CNT));
5774 hw->frmbase_cont_flag = 1;
5775 } else
5776 hw->frmbase_cont_flag = 0;
5777
5778 if (p_H264_Dpb->mVideo.dec_picture) {
5779 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5780#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5781 DEL_EXIST(hw,
5782 p_H264_Dpb->mVideo.dec_picture) = 0;
5783 if (vdec->master) {
5784 struct vdec_h264_hw_s *hw_ba =
5785 (struct vdec_h264_hw_s *)
5786 vdec->master->private;
5787 if (hw_ba->last_dec_picture)
5788 DEL_EXIST(hw_ba,
5789 hw_ba->last_dec_picture)
5790 = 1;
5791 }
5792#endif
5793 mutex_lock(&hw->chunks_mutex);
5794 if (hw->chunk) {
5795 p_H264_Dpb->mVideo.dec_picture->pts =
5796 hw->chunk->pts;
5797 p_H264_Dpb->mVideo.dec_picture->pts64 =
5798 hw->chunk->pts64;
5799 p_H264_Dpb->mVideo.dec_picture->timestamp =
5800 hw->chunk->timestamp;
5801#ifdef MH264_USERDATA_ENABLE
5802 vmh264_udc_fill_vpts(hw,
5803 p_H264_Dpb->mSlice.slice_type,
5804 hw->chunk->pts, 1);
5805#endif
5806
5807#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5808 } else if (vdec->master) {
5809 /*dv enhance layer,
5810 do not checkout pts*/
5811 struct StorablePicture *pic =
5812 p_H264_Dpb->mVideo.dec_picture;
5813 pic->pts = 0;
5814 pic->pts64 = 0;
5815#endif
5816 } else {
5817 struct StorablePicture *pic =
5818 p_H264_Dpb->mVideo.dec_picture;
5819 u32 offset = pic->offset_delimiter;
5820 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5821 offset, &pic->pts, 0, &pic->pts64)) {
5822 pic->pts = 0;
5823 pic->pts64 = 0;
5824#ifdef MH264_USERDATA_ENABLE
5825 vmh264_udc_fill_vpts(hw,
5826 p_H264_Dpb->mSlice.slice_type,
5827 pic->pts, 0);
5828#endif
5829 } else {
5830#ifdef MH264_USERDATA_ENABLE
5831 vmh264_udc_fill_vpts(hw,
5832 p_H264_Dpb->mSlice.slice_type,
5833 pic->pts, 1);
5834#endif
5835 }
5836
5837 }
5838 mutex_unlock(&hw->chunks_mutex);
5839
5840 check_decoded_pic_error(hw);
5841#ifdef ERROR_HANDLE_TEST
5842 if ((hw->data_flag & ERROR_FLAG)
5843 && (error_proc_policy & 0x80)) {
5844 release_cur_decoding_buf(hw);
5845 h264_clear_dpb(hw);
5846 hw->dec_flag = 0;
5847 hw->data_flag = 0;
5848 hw->skip_frame_count = 0;
5849 hw->has_i_frame = 0;
5850 hw->no_error_count = 0xfff;
5851 hw->no_error_i_count = 0xf;
5852 } else
5853#endif
5854 ret = store_picture_in_dpb(p_H264_Dpb,
5855 p_H264_Dpb->mVideo.dec_picture,
5856 hw->data_flag | hw->dec_flag |
5857 p_H264_Dpb->mVideo.dec_picture->data_flag);
5858
5859
5860
5861 if (ret == -1) {
5862 release_cur_decoding_buf(hw);
5863 bufmgr_force_recover(p_H264_Dpb);
5864 } else {
5865 if (hw->data_flag & ERROR_FLAG) {
5866 hw->no_error_count = 0;
5867 hw->no_error_i_count = 0;
5868 } else {
5869 hw->no_error_count++;
5870 if (hw->data_flag & I_FLAG)
5871 hw->no_error_i_count++;
5872 }
5873 if (hw->mmu_enable)
5874 hevc_set_unused_4k_buff_idx(hw,
5875 p_H264_Dpb->mVideo.
5876 dec_picture->buf_spec_num);
5877 bufmgr_post(p_H264_Dpb);
5878 hw->last_dec_picture =
5879 p_H264_Dpb->mVideo.dec_picture;
5880 p_H264_Dpb->mVideo.dec_picture = NULL;
5881 /* dump_dpb(&p_H264_Dpb->mDPB); */
5882 hw->has_i_frame = 1;
5883 if (hw->mmu_enable)
5884 hevc_set_frame_done(hw);
5885 hw->decode_pic_count++;
5886 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5887 if (hw->skip_frame_count > 0) {
5888 /*skip n frame after first I */
5889 hw->skip_frame_count--;
5890 if (hw->skip_frame_count == 0)
5891 hw->dec_flag &= (~NODISP_FLAG);
5892 } else if (hw->skip_frame_count < -1) {
5893 /*skip n frame after first I until second I */
5894 hw->skip_frame_count++;
5895 if (hw->skip_frame_count == -1)
5896 hw->dec_flag &= (~NODISP_FLAG);
5897 }
5898 }
5899 }
5900 if (hw->frmbase_cont_flag) {
5901 /*do not DEC_RESULT_GET_DATA*/
5902 hw->get_data_count = 0x7fffffff;
5903 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5904 decode_frame_count[DECODE_ID(hw)]++;
5905 start_process_time(hw);
5906 return IRQ_HANDLED;
5907 }
5908 amvdec_stop();
5909 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5910 "%s %s decode slice count %d\n",
5911 __func__,
5912 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5913 "H264_PIC_DATA_DONE" :
5914 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5915 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5916 hw->decode_pic_count);
5917 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5918 hw->dec_result = DEC_RESULT_DONE;
5919#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5920 if (vdec->slave &&
5921 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5922 struct vdec_h264_hw_s *hw_el =
5923 (struct vdec_h264_hw_s *)(vdec->slave->private);
5924 hw_el->got_valid_nal = 0;
5925 hw->switch_dvlayer_flag = 1;
5926 } else if (vdec->master &&
5927 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5928 struct vdec_h264_hw_s *hw_bl =
5929 (struct vdec_h264_hw_s *)(vdec->master->private);
5930 hw_bl->got_valid_nal = 0;
5931 hw->switch_dvlayer_flag = 1;
5932 } else {
5933 hw->switch_dvlayer_flag = 0;
5934 hw->got_valid_nal = 1;
5935 }
5936#endif
5937
5938 hw->dec_result = DEC_RESULT_DONE;
5939 vdec_schedule_work(&hw->work);
5940
5941#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5942 } else if (
5943 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5944 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5945 goto pic_done_proc;
5946#endif
5947 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5948 reset_process_time(hw);
5949 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5950 dma_sync_single_for_cpu(
5951 amports_get_dma_device(),
5952 hw->aux_phy_addr,
5953 hw->prefix_aux_size + hw->suffix_aux_size,
5954 DMA_FROM_DEVICE);
5955 if (dpb_is_debug(DECODE_ID(hw),
5956 PRINT_FLAG_DPB_DETAIL))
5957 dump_aux_buf(hw);
5958#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5959 if (vdec->dolby_meta_with_el || vdec->slave) {
5960 if (hw->last_dec_picture)
5961 set_aux_data(hw, hw->last_dec_picture,
5962 0, 0, NULL);
5963 } else {
5964 if (vdec->master) {
5965 struct vdec_h264_hw_s *hw_bl =
5966 (struct vdec_h264_hw_s *)
5967 (vdec->master->private);
5968 if (hw_bl->last_dec_picture != NULL) {
5969 set_aux_data(hw_bl,
5970 hw_bl->last_dec_picture,
5971 0, 1, hw);
5972 }
5973 set_aux_data(hw,
5974 hw->last_dec_picture,
5975 0, 2, NULL);
5976 }
5977 }
5978#else
5979 if (hw->last_dec_picture)
5980 set_aux_data(hw,
5981 hw->last_dec_picture, 0, 0, NULL);
5982#endif
5983 }
5984#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5985 hw->switch_dvlayer_flag = 0;
5986 hw->got_valid_nal = 1;
5987#endif
5988 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5989 "%s H264_AUX_DATA_READY\n", __func__);
5990 hw->dec_result = DEC_RESULT_DONE;
5991 vdec_schedule_work(&hw->work);
5992 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5993 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5994 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5995 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5996empty_proc:
5997 reset_process_time(hw);
5998 if (!hw->frmbase_cont_flag)
5999 release_cur_decoding_buf(hw);
6000
6001 if (input_frame_based(vdec) ||
6002 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6003 if (h264_debug_flag &
6004 DISABLE_ERROR_HANDLE) {
6005 dpb_print(DECODE_ID(hw),
6006 PRINT_FLAG_ERROR,
6007 "%s decoding error, level 0x%x\n",
6008 __func__,
6009 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6010 goto send_again;
6011 }
6012 amvdec_stop();
6013 vdec->mc_loaded = 0;
6014 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6015 "%s %s\n", __func__,
6016 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6017 "H264_SEARCH_BUFEMPTY" :
6018 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6019 "H264_DECODE_BUFEMPTY" :
6020 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6021 "H264_DECODE_TIMEOUT" :
6022 "OTHER");
6023 hw->dec_result = DEC_RESULT_DONE;
6024
6025 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6026 hw->search_dataempty_num++;
6027 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6028 hw->decode_timeout_num++;
6029 if (error_proc_policy & 0x4000) {
6030 hw->data_flag |= ERROR_FLAG;
6031 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6032 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6033 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6034 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6035 dpb_print(DECODE_ID(hw),
6036 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6037 p_H264_Dpb->last_dpb_status, __func__);
6038 hw->reset_bufmgr_flag = 1;
6039 }
6040 }
6041 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6042 hw->decode_dataempty_num++;
6043 if (!hw->frmbase_cont_flag)
6044 hw->data_flag |= ERROR_FLAG;
6045
6046 vdec_schedule_work(&hw->work);
6047 } else {
6048 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6049 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6050 "%s DEC_RESULT_AGAIN\n", __func__);
6051send_again:
6052 hw->dec_result = DEC_RESULT_AGAIN;
6053 vdec_schedule_work(&hw->work);
6054 }
6055 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6056 reset_process_time(hw);
6057 if (input_frame_based(vdec)) {
6058 dpb_print(DECODE_ID(hw),
6059 PRINT_FLAG_VDEC_STATUS,
6060 "%s H264_DATA_REQUEST (%d)\n",
6061 __func__, hw->get_data_count);
6062 hw->dec_result = DEC_RESULT_GET_DATA;
6063 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6064 hw->get_data_start_time = jiffies;
6065 hw->get_data_count++;
6066 if (hw->get_data_count >= frame_max_data_packet)
6067 goto empty_proc;
6068 vdec_schedule_work(&hw->work);
6069 } else
6070 goto empty_proc;
6071 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6072 dpb_print(DECODE_ID(hw), 0,
6073 "vmh264 decode oversize !!\n");
6074 release_cur_decoding_buf(hw);
6075 hw->data_flag |= ERROR_FLAG;
6076 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6077 reset_process_time(hw);
6078 hw->dec_result = DEC_RESULT_DONE;
6079 vdec_schedule_work(&hw->work);
6080 return IRQ_HANDLED;
6081 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6082 int aux_data_len;
6083 aux_data_len =
6084 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6085
6086 if (aux_data_len > SEI_DATA_SIZE) {
6087 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6088 "sei data size more than 4K: %d, discarded it\n",
6089 hw->sei_itu_data_len);
6090 hw->sei_itu_data_len = 0;
6091 }
6092
6093 if (aux_data_len != 0) {
6094 u8 *trans_data_buf;
6095 u8 *sei_data_buf;
6096 u8 swap_byte;
6097
6098 dma_sync_single_for_cpu(
6099 amports_get_dma_device(),
6100 hw->aux_phy_addr,
6101 hw->prefix_aux_size + hw->suffix_aux_size,
6102 DMA_FROM_DEVICE);
6103#if 0
6104 dump_aux_buf(hw);
6105#endif
6106 trans_data_buf = (u8 *)hw->aux_addr;
6107
6108 if (trans_data_buf[7] == AUX_TAG_SEI) {
6109 int left_len;
6110
6111 sei_data_buf = (u8 *)hw->sei_data_buf
6112 + hw->sei_data_len;
6113 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6114 if (aux_data_len/2 <= left_len) {
6115 for (i = 0; i < aux_data_len/2; i++)
6116 sei_data_buf[i]
6117 = trans_data_buf[i*2];
6118
6119 aux_data_len = aux_data_len / 2;
6120 for (i = 0; i < aux_data_len; i = i+4) {
6121 swap_byte = sei_data_buf[i];
6122 sei_data_buf[i]
6123 = sei_data_buf[i+3];
6124 sei_data_buf[i+3] = swap_byte;
6125
6126 swap_byte = sei_data_buf[i+1];
6127 sei_data_buf[i+1]
6128 = sei_data_buf[i+2];
6129 sei_data_buf[i+2] = swap_byte;
6130 }
6131
6132 for (i = aux_data_len-1; i >= 0; i--)
6133 if (sei_data_buf[i] != 0)
6134 break;
6135
6136 hw->sei_data_len += i+1;
6137 } else
6138 dpb_print(DECODE_ID(hw),
6139 PRINT_FLAG_ERROR,
6140 "sei data size %d and more than left space: %d, discarded it\n",
6141 hw->sei_itu_data_len,
6142 left_len);
6143 }
6144 }
6145 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6146
6147 return IRQ_HANDLED;
6148 }
6149
6150
6151 /* ucode debug */
6152 debug_tag = READ_VREG(DEBUG_REG1);
6153 if (debug_tag & 0x10000) {
6154 unsigned short *p = (unsigned short *)hw->lmem_addr;
6155
6156 dma_sync_single_for_cpu(
6157 amports_get_dma_device(),
6158 hw->lmem_addr_remap,
6159 PAGE_SIZE,
6160 DMA_FROM_DEVICE);
6161
6162 dpb_print(DECODE_ID(hw), 0,
6163 "LMEM<tag %x>:\n", debug_tag);
6164 for (i = 0; i < 0x400; i += 4) {
6165 int ii;
6166 if ((i & 0xf) == 0)
6167 dpb_print_cont(DECODE_ID(hw), 0,
6168 "%03x: ", i);
6169 for (ii = 0; ii < 4; ii++)
6170 dpb_print_cont(DECODE_ID(hw), 0,
6171 "%04x ", p[i+3-ii]);
6172 if (((i+ii) & 0xf) == 0)
6173 dpb_print_cont(DECODE_ID(hw), 0,
6174 "\n");
6175 }
6176 if (((udebug_pause_pos & 0xffff)
6177 == (debug_tag & 0xffff)) &&
6178 (udebug_pause_decode_idx == 0 ||
6179 udebug_pause_decode_idx ==
6180 hw->decode_pic_count) &&
6181 (udebug_pause_val == 0 ||
6182 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6183 udebug_pause_pos &= 0xffff;
6184 hw->ucode_pause_pos = udebug_pause_pos;
6185 }
6186 else if (debug_tag & 0x20000)
6187 hw->ucode_pause_pos = 0xffffffff;
6188 if (hw->ucode_pause_pos)
6189 reset_process_time(hw);
6190 else
6191 WRITE_VREG(DEBUG_REG1, 0);
6192 } else if (debug_tag != 0) {
6193 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6194 "dbg%x: %x\n", debug_tag,
6195 READ_VREG(DEBUG_REG2));
6196 if (((udebug_pause_pos & 0xffff)
6197 == (debug_tag & 0xffff)) &&
6198 (udebug_pause_decode_idx == 0 ||
6199 udebug_pause_decode_idx ==
6200 hw->decode_pic_count) &&
6201 (udebug_pause_val == 0 ||
6202 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6203 udebug_pause_pos &= 0xffff;
6204 hw->ucode_pause_pos = udebug_pause_pos;
6205 }
6206 if (hw->ucode_pause_pos)
6207 reset_process_time(hw);
6208 else
6209 WRITE_VREG(DEBUG_REG1, 0);
6210 }
6211 /**/
6212 return IRQ_HANDLED;
6213}
6214
6215static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6216{
6217 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6218 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6219
6220
6221 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6222
6223 if (!hw)
6224 return IRQ_HANDLED;
6225
6226 if (hw->eos)
6227 return IRQ_HANDLED;
6228
6229 p_H264_Dpb->vdec = vdec;
6230 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6231
6232 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6233 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6234 __func__,
6235 p_H264_Dpb->dec_dpb_status,
6236 READ_VREG(ERROR_STATUS_REG),
6237 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6238 READ_VREG(VLD_MEM_VIFIFO_WP),
6239 READ_VREG(VLD_MEM_VIFIFO_RP),
6240 READ_VREG(VIFF_BIT_CNT),
6241 READ_VREG(MBY_MBX));
6242
6243 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6244 if (hw->mmu_enable)
6245 hevc_sao_wait_done(hw);
6246 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6247 return IRQ_HANDLED;
6248 }
6249 return IRQ_WAKE_THREAD;
6250
6251}
6252
6253static void timeout_process(struct vdec_h264_hw_s *hw)
6254{
6255 struct vdec_s *vdec = hw_to_vdec(hw);
6256 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6257
6258 /*
6259 * In this very timeout point,the vh264_work arrives,
6260 * let it to handle the scenario.
6261 */
6262 if (work_pending(&hw->work))
6263 return;
6264
6265 hw->timeout_num++;
6266 amvdec_stop();
6267 vdec->mc_loaded = 0;
6268 if (hw->mmu_enable) {
6269 hevc_set_frame_done(hw);
6270 hevc_sao_wait_done(hw);
6271 }
6272 if (!hw->i_only && (error_proc_policy & 0x2))
6273 flush_dpb(p_H264_Dpb);
6274 dpb_print(DECODE_ID(hw),
6275 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6276 release_cur_decoding_buf(hw);
6277 hw->dec_result = DEC_RESULT_DONE;
6278 hw->data_flag |= ERROR_FLAG;
6279
6280 if (work_pending(&hw->work))
6281 return;
6282 vdec_schedule_work(&hw->timeout_work);
6283}
6284
6285static void dump_bufspec(struct vdec_h264_hw_s *hw,
6286 const char *caller)
6287{
6288 int i;
6289 dpb_print(DECODE_ID(hw), 0,
6290 "%s in %s:\n", __func__, caller);
6291 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6292 if (hw->buffer_spec[i].used == -1)
6293 continue;
6294 dpb_print(DECODE_ID(hw), 0,
6295 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6296 i, hw->buffer_spec[i].used,
6297 hw->buffer_spec[i].buf_adr,
6298 hw->buffer_spec[i].canvas_pos,
6299 hw->buffer_spec[i].vf_ref
6300 );
6301#ifdef CONFIG_AM_VDEC_DV
6302 dpb_print_cont(DECODE_ID(hw), 0,
6303 "dv_el_exist %d",
6304 hw->buffer_spec[i].dv_enhance_exist
6305 );
6306#endif
6307 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6308 }
6309
6310}
6311
6312static void vmh264_dump_state(struct vdec_s *vdec)
6313{
6314 struct vdec_h264_hw_s *hw =
6315 (struct vdec_h264_hw_s *)(vdec->private);
6316 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6317 dpb_print(DECODE_ID(hw), 0,
6318 "====== %s\n", __func__);
6319 dpb_print(DECODE_ID(hw), 0,
6320 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6321 hw->frame_width,
6322 hw->frame_height,
6323 hw->dpb.reorder_pic_num,
6324 hw->dpb.mDPB.size,
6325 hw->max_reference_size,
6326 hw->i_only,
6327 hw->send_error_frame_flag
6328 );
6329
6330 dpb_print(DECODE_ID(hw), 0,
6331 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6332 input_frame_based(vdec),
6333 hw->eos,
6334 hw->stat,
6335 hw->dec_result,
6336 decode_frame_count[DECODE_ID(hw)],
6337 display_frame_count[DECODE_ID(hw)],
6338 run_count[DECODE_ID(hw)],
6339 not_run_ready[DECODE_ID(hw)],
6340 input_empty[DECODE_ID(hw)],
6341 hw->reset_bufmgr_count
6342 );
6343
6344 if (vf_get_receiver(vdec->vf_provider_name)) {
6345 enum receviver_start_e state =
6346 vf_notify_receiver(vdec->vf_provider_name,
6347 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6348 NULL);
6349 dpb_print(DECODE_ID(hw), 0,
6350 "\nreceiver(%s) state %d\n",
6351 vdec->vf_provider_name,
6352 state);
6353 }
6354
6355 dpb_print(DECODE_ID(hw), 0,
6356 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x wait_reset_done_flag %d\n",
6357 __func__,
6358 kfifo_len(&hw->newframe_q),
6359 VF_POOL_SIZE,
6360 kfifo_len(&hw->display_q),
6361 VF_POOL_SIZE,
6362 hw->vf_pre_count,
6363 hw->vf_get_count,
6364 hw->vf_put_count,
6365 have_free_buf_spec(vdec),
6366 p_H264_Dpb->mDPB.init_done,
6367 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6368 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6369 p_H264_Dpb->fast_output_enable,
6370 hw->wait_reset_done_flag
6371 );
6372
6373 dump_dpb(&p_H264_Dpb->mDPB, 1);
6374 dump_pic(p_H264_Dpb);
6375 dump_bufspec(hw, __func__);
6376
6377 dpb_print(DECODE_ID(hw), 0,
6378 "DPB_STATUS_REG=0x%x\n",
6379 READ_VREG(DPB_STATUS_REG));
6380 dpb_print(DECODE_ID(hw), 0,
6381 "MPC_E=0x%x\n",
6382 READ_VREG(MPC_E));
6383 dpb_print(DECODE_ID(hw), 0,
6384 "H264_DECODE_MODE=0x%x\n",
6385 READ_VREG(H264_DECODE_MODE));
6386 dpb_print(DECODE_ID(hw), 0,
6387 "MBY_MBX=0x%x\n",
6388 READ_VREG(MBY_MBX));
6389 dpb_print(DECODE_ID(hw), 0,
6390 "H264_DECODE_SIZE=0x%x\n",
6391 READ_VREG(H264_DECODE_SIZE));
6392 dpb_print(DECODE_ID(hw), 0,
6393 "VIFF_BIT_CNT=0x%x\n",
6394 READ_VREG(VIFF_BIT_CNT));
6395 dpb_print(DECODE_ID(hw), 0,
6396 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6397 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6398 dpb_print(DECODE_ID(hw), 0,
6399 "VLD_MEM_VIFIFO_WP=0x%x\n",
6400 READ_VREG(VLD_MEM_VIFIFO_WP));
6401 dpb_print(DECODE_ID(hw), 0,
6402 "VLD_MEM_VIFIFO_RP=0x%x\n",
6403 READ_VREG(VLD_MEM_VIFIFO_RP));
6404 dpb_print(DECODE_ID(hw), 0,
6405 "PARSER_VIDEO_RP=0x%x\n",
6406 READ_PARSER_REG(PARSER_VIDEO_RP));
6407 dpb_print(DECODE_ID(hw), 0,
6408 "PARSER_VIDEO_WP=0x%x\n",
6409 READ_PARSER_REG(PARSER_VIDEO_WP));
6410
6411 if (input_frame_based(vdec) &&
6412 dpb_is_debug(DECODE_ID(hw),
6413 PRINT_FRAMEBASE_DATA)
6414 ) {
6415 int jj;
6416 if (hw->chunk && hw->chunk->block &&
6417 hw->chunk->size > 0) {
6418 u8 *data = NULL;
6419
6420 if (!hw->chunk->block->is_mapped)
6421 data = codec_mm_vmap(hw->chunk->block->start +
6422 hw->chunk->offset, hw->chunk->size);
6423 else
6424 data = ((u8 *)hw->chunk->block->start_virt)
6425 + hw->chunk->offset;
6426
6427 dpb_print(DECODE_ID(hw), 0,
6428 "frame data size 0x%x\n",
6429 hw->chunk->size);
6430 for (jj = 0; jj < hw->chunk->size; jj++) {
6431 if ((jj & 0xf) == 0)
6432 dpb_print(DECODE_ID(hw),
6433 PRINT_FRAMEBASE_DATA,
6434 "%06x:", jj);
6435 dpb_print_cont(DECODE_ID(hw),
6436 PRINT_FRAMEBASE_DATA,
6437 "%02x ", data[jj]);
6438 if (((jj + 1) & 0xf) == 0)
6439 dpb_print_cont(DECODE_ID(hw),
6440 PRINT_FRAMEBASE_DATA,
6441 "\n");
6442 }
6443
6444 if (!hw->chunk->block->is_mapped)
6445 codec_mm_unmap_phyaddr(data);
6446 }
6447 }
6448}
6449
6450
6451static void check_timer_func(unsigned long arg)
6452{
6453 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6454 struct vdec_s *vdec = hw_to_vdec(hw);
6455 int error_skip_frame_count = error_skip_count & 0xfff;
6456 unsigned int timeout_val = decode_timeout_val;
6457 if (timeout_val != 0 &&
6458 hw->no_error_count < error_skip_frame_count)
6459 timeout_val = errordata_timeout_val;
6460 if ((h264_debug_cmd & 0x100) != 0 &&
6461 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6462 hw->dec_result = DEC_RESULT_DONE;
6463 vdec_schedule_work(&hw->work);
6464 pr_info("vdec %d is forced to be disconnected\n",
6465 h264_debug_cmd & 0xff);
6466 h264_debug_cmd = 0;
6467 return;
6468 }
6469 if ((h264_debug_cmd & 0x200) != 0 &&
6470 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6471 pr_debug("vdec %d is forced to reset bufmgr\n",
6472 h264_debug_cmd & 0xff);
6473 hw->reset_bufmgr_flag = 1;
6474 h264_debug_cmd = 0;
6475 return;
6476 }
6477
6478 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6479 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6480 vdec_schedule_work(&hw->work);
6481 pr_debug("vdec requested to be disconnected\n");
6482 return;
6483 }
6484
6485 if (radr != 0) {
6486 if (rval != 0) {
6487 WRITE_VREG(radr, rval);
6488 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6489 } else
6490 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6491 rval = 0;
6492 radr = 0;
6493 }
6494
6495 if ((input_frame_based(vdec) ||
6496 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6497 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6498 (timeout_val > 0) &&
6499 (hw->start_process_time > 0) &&
6500 ((1000 * (jiffies - hw->start_process_time) / HZ)
6501 > timeout_val)
6502 ) {
6503 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6504 u32 mby_mbx = READ_VREG(MBY_MBX);
6505 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6506 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6507 if (hw->last_mby_mbx == mby_mbx) {
6508 if (hw->decode_timeout_count > 0)
6509 hw->decode_timeout_count--;
6510 if (hw->decode_timeout_count == 0)
6511 {
6512 reset_process_time(hw);
6513 timeout_process(hw);
6514 }
6515 } else
6516 start_process_time(hw);
6517 } else if (is_in_parsing_state(dpb_status)) {
6518 if (hw->last_vld_level ==
6519 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6520 if (hw->decode_timeout_count > 0)
6521 hw->decode_timeout_count--;
6522 if (hw->decode_timeout_count == 0)
6523 {
6524 reset_process_time(hw);
6525 timeout_process(hw);
6526 }
6527 }
6528 }
6529 hw->last_vld_level =
6530 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6531 hw->last_mby_mbx = mby_mbx;
6532 }
6533
6534 if ((hw->ucode_pause_pos != 0) &&
6535 (hw->ucode_pause_pos != 0xffffffff) &&
6536 udebug_pause_pos != hw->ucode_pause_pos) {
6537 hw->ucode_pause_pos = 0;
6538 WRITE_VREG(DEBUG_REG1, 0);
6539 }
6540
6541 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6542}
6543
6544static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6545{
6546 u32 ar;
6547 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6548
6549 if (!hw)
6550 return -1;
6551
6552 vstatus->frame_width = hw->frame_width;
6553 vstatus->frame_height = hw->frame_height;
6554 if (hw->frame_dur != 0)
6555 vstatus->frame_rate = 96000 / hw->frame_dur;
6556 else
6557 vstatus->frame_rate = -1;
6558 vstatus->error_count = 0;
6559 vstatus->status = hw->stat;
6560 if (hw->h264_ar == 0x3ff)
6561 hw->h264_ar = (0x100 *
6562 hw->frame_height * hw->height_aspect_ratio) /
6563 (hw->frame_width * hw->width_aspect_ratio);
6564 ar = min_t(u32,
6565 hw->h264_ar,
6566 DISP_RATIO_ASPECT_RATIO_MAX);
6567 vstatus->ratio_control =
6568 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6569
6570 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6571 "%s-%02d", DRIVER_NAME, hw->id);
6572
6573 return 0;
6574}
6575
6576static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6577{
6578 int i, j;
6579 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6580
6581 /* if (hw->init_flag == 0) { */
6582 if (h264_debug_flag & 0x40000000) {
6583 /* if (1) */
6584 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6585 "%s, reset register\n", __func__);
6586
6587 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6588 ;
6589 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6590 ; /* reg address is 0x350 */
6591
6592#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6593 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6594 WRITE_VREG(DOS_SW_RESET0, 0);
6595
6596 READ_VREG(DOS_SW_RESET0);
6597 READ_VREG(DOS_SW_RESET0);
6598 READ_VREG(DOS_SW_RESET0);
6599
6600 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6601 WRITE_VREG(DOS_SW_RESET0, 0);
6602
6603 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6604 WRITE_VREG(DOS_SW_RESET0, 0);
6605
6606 READ_VREG(DOS_SW_RESET0);
6607 READ_VREG(DOS_SW_RESET0);
6608 READ_VREG(DOS_SW_RESET0);
6609
6610#else
6611 WRITE_RESET_REG(RESET0_REGISTER,
6612 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6613 READ_RESET_REG(RESET0_REGISTER);
6614 WRITE_RESET_REG(RESET0_REGISTER,
6615 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6616
6617 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6618#endif
6619 WRITE_VREG(POWER_CTL_VLD,
6620 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6621 (1 << 9) | (1 << 6));
6622 } else {
6623 /* WRITE_VREG(POWER_CTL_VLD,
6624 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6625 */
6626 WRITE_VREG(POWER_CTL_VLD,
6627 READ_VREG(POWER_CTL_VLD) |
6628 (0 << 10) | (1 << 9) | (1 << 6));
6629 }
6630 /* disable PSCALE for hardware sharing */
6631 WRITE_VREG(PSCALE_CTRL, 0);
6632
6633 /* clear mailbox interrupt */
6634 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6635
6636 /* enable mailbox interrupt */
6637 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6638
6639#ifdef NV21
6640 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6641#endif
6642
6643 /* cbcr_merge_swap_en */
6644 if (hw->is_used_v4l
6645 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6646 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6647 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6648
6649 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6650 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6651
6652 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6653 if (hw->mmu_enable) {
6654 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6655 /* sw reset to extif hardware */
6656 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6657 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6658 } else {
6659 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6660 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6661 }
6662
6663
6664#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6665 /* pr_info("vh264 meson8 prot init\n"); */
6666 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6667#endif
6668
6669#ifdef VDEC_DW
6670 if (IS_VDEC_DW(hw)) {
6671 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6672
6673 if (IS_VDEC_DW(hw) == 2)
6674 data |= (1 << 9);
6675 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6676 }
6677#endif
6678 if (hw->dpb.mDPB.size > 0) {
6679 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6680 (hw->dpb.mDPB.size << 16) |
6681 (hw->dpb.mDPB.size << 8));
6682
6683 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6684 i = get_buf_spec_by_canvas_pos(hw, j);
6685 if (i < 0)
6686 break;
6687
6688 if (!hw->mmu_enable &&
6689 hw->buffer_spec[i].cma_alloc_addr)
6690 config_decode_canvas(hw, i);
6691 if (hw->mmu_enable && hw->double_write_mode)
6692 config_decode_canvas_ex(hw, i);
6693 }
6694 } else {
6695 WRITE_VREG(AV_SCRATCH_0, 0);
6696 WRITE_VREG(AV_SCRATCH_9, 0);
6697 }
6698
6699 if (hw->init_flag == 0)
6700 WRITE_VREG(DPB_STATUS_REG, 0);
6701 else
6702 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6703
6704 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6705 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6706 if (!tee_enabled())
6707 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6708
6709 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6710 * error_recovery_mode : error_recovery_mode_in;
6711 */
6712 /* WRITE_VREG(AV_SCRATCH_F,
6713 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6714 */
6715 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6716 ((error_recovery_mode_in & 0x1) << 4));
6717 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6718 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6719 else*/
6720 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6721
6722 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6723#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6724 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6725#endif
6726
6727 WRITE_VREG(DEBUG_REG1, 0);
6728 WRITE_VREG(DEBUG_REG2, 0);
6729
6730 if (hw->reg_iqidct_control)
6731 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6732 if (hw->reg_vcop_ctrl_reg)
6733 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6734 if (hw->vld_dec_control)
6735 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6736 return 0;
6737}
6738
6739static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6740{
6741 struct vdec_h264_hw_s *hw =
6742 (struct vdec_h264_hw_s *)vdec->private;
6743 if (i_only_flag & 0x100)
6744 return 0;
6745 if (trickmode == TRICKMODE_I)
6746 hw->i_only = 0x3;
6747 else if (trickmode == TRICKMODE_NONE)
6748 hw->i_only = 0x0;
6749 return 0;
6750}
6751
6752static unsigned char amvdec_enable_flag;
6753static void vh264_local_init(struct vdec_h264_hw_s *hw)
6754{
6755 int i;
6756 hw->init_flag = 0;
6757 hw->first_sc_checked= 0;
6758 hw->eos = 0;
6759 hw->valve_count = 0;
6760 hw->config_bufmgr_done = 0;
6761 hw->start_process_time = 0;
6762 hw->has_i_frame = 0;
6763 hw->no_error_count = 0xfff;
6764 hw->no_error_i_count = 0xf;
6765
6766 hw->dec_flag = 0;
6767 hw->data_flag = 0;
6768 hw->skip_frame_count = 0;
6769 hw->reg_iqidct_control = 0;
6770 hw->reg_vcop_ctrl_reg = 0;
6771 hw->reg_rv_ai_mb_count = 0;
6772 hw->vld_dec_control = 0;
6773 hw->decode_timeout_count = 0;
6774 hw->no_mem_count = 0;
6775 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6776 /* vh264_ratio = 0x100; */
6777
6778 hw->vh264_rotation = (((unsigned long)
6779 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6780
6781 hw->frame_prog = 0;
6782 hw->frame_width = hw->vh264_amstream_dec_info.width;
6783 hw->frame_height = hw->vh264_amstream_dec_info.height;
6784 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6785 hw->pts_outside = ((unsigned long)
6786 hw->vh264_amstream_dec_info.param) & 0x01;
6787 hw->sync_outside = ((unsigned long)
6788 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6789 hw->use_idr_framerate = ((unsigned long)
6790 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6791 hw->max_refer_buf = !(((unsigned long)
6792 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6793 if (hw->frame_dur < 96000/960) {
6794 /*more than 960fps,it should not be a correct value,
6795 *give default 30fps
6796 */
6797 hw->frame_dur = 96000/30;
6798 }
6799
6800 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6801
6802 hw->first_i_policy = first_i_policy;
6803
6804 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6805 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6806 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6807 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6808
6809 if (i_only_flag & 0x100)
6810 hw->i_only = i_only_flag & 0xff;
6811 if (hw->i_only)
6812 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6813
6814 if ((unsigned long) hw->vh264_amstream_dec_info.param
6815 & 0x08)
6816 hw->no_poc_reorder_flag = 1;
6817
6818 error_recovery_mode_in = 1; /*ucode control?*/
6819 if (error_proc_policy & 0x80000000)
6820 hw->send_error_frame_flag = error_proc_policy & 0x1;
6821 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6822 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6823
6824 INIT_KFIFO(hw->display_q);
6825 INIT_KFIFO(hw->newframe_q);
6826
6827 for (i = 0; i < VF_POOL_SIZE; i++) {
6828 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6829 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6830 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6831 kfifo_put(&hw->newframe_q, vf);
6832 }
6833
6834 hw->duration_from_pts_done = 0;
6835
6836 hw->p_last_vf = NULL;
6837 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6838 hw->hevc_cur_buf_idx = 0xffff;
6839
6840 init_waitqueue_head(&hw->wait_q);
6841
6842 return;
6843}
6844
6845static s32 vh264_init(struct vdec_h264_hw_s *hw)
6846{
6847 int size = -1;
6848 int fw_size = 0x1000 * 16;
6849 int fw_mmu_size = 0x1000 * 16;
6850 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6851
6852 /* int trickmode_fffb = 0; */
6853
6854 /* pr_info("\nvh264_init\n"); */
6855 /* init_timer(&hw->recycle_timer); */
6856
6857 /* timer init */
6858 init_timer(&hw->check_timer);
6859
6860 hw->check_timer.data = (unsigned long)hw;
6861 hw->check_timer.function = check_timer_func;
6862 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6863
6864 /* add_timer(&hw->check_timer); */
6865 hw->stat |= STAT_TIMER_ARM;
6866 hw->stat |= STAT_ISR_REG;
6867
6868 mutex_init(&hw->chunks_mutex);
6869 vh264_local_init(hw);
6870 INIT_WORK(&hw->work, vh264_work);
6871 INIT_WORK(&hw->notify_work, vh264_notify_work);
6872 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6873#ifdef MH264_USERDATA_ENABLE
6874 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6875#endif
6876
6877 if (!amvdec_enable_flag) {
6878 amvdec_enable_flag = true;
6879 amvdec_enable();
6880 if (hw->mmu_enable)
6881 amhevc_enable();
6882 }
6883 if (hw->mmu_enable) {
6884
6885 hw->frame_mmu_map_addr =
6886 dma_alloc_coherent(amports_get_dma_device(),
6887 FRAME_MMU_MAP_SIZE,
6888 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6889 if (hw->frame_mmu_map_addr == NULL) {
6890 pr_err("%s: failed to alloc count_buffer\n", __func__);
6891 return -ENOMEM;
6892 }
6893 }
6894
6895 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6896 if (IS_ERR_OR_NULL(fw))
6897 return -ENOMEM;
6898
6899 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6900 if (size < 0) {
6901 pr_err("get firmware fail.\n");
6902 vfree(fw);
6903 return -1;
6904 }
6905
6906 fw->len = size;
6907 hw->fw = fw;
6908
6909 if (hw->mmu_enable) {
6910 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6911 if (IS_ERR_OR_NULL(fw_mmu))
6912 return -ENOMEM;
6913
6914 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6915 if (size < 0) {
6916 pr_err("get mmu fw fail.\n");
6917 vfree(fw_mmu);
6918 return -1;
6919 }
6920
6921 fw_mmu->len = size;
6922 hw->fw_mmu = fw_mmu;
6923 }
6924
6925 if (!tee_enabled()) {
6926 /* -- ucode loading (amrisc and swap code) */
6927 hw->mc_cpu_addr =
6928 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6929 &hw->mc_dma_handle, GFP_KERNEL);
6930 if (!hw->mc_cpu_addr) {
6931 amvdec_enable_flag = false;
6932 amvdec_disable();
6933 if (hw->mmu_enable)
6934 amhevc_disable();
6935 pr_info("vh264_init: Can not allocate mc memory.\n");
6936 return -ENOMEM;
6937 }
6938
6939 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6940 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6941 */
6942
6943 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6944
6945 /*header*/
6946 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6947 fw->data + 0x4000, MC_SWAP_SIZE);
6948 /*data*/
6949 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6950 fw->data + 0x2000, MC_SWAP_SIZE);
6951 /*mmco*/
6952 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6953 fw->data + 0x6000, MC_SWAP_SIZE);
6954 /*list*/
6955 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6956 fw->data + 0x3000, MC_SWAP_SIZE);
6957 /*slice*/
6958 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6959 fw->data + 0x5000, MC_SWAP_SIZE);
6960 /*main*/
6961 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6962 fw->data, 0x2000);
6963 /*data*/
6964 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6965 fw->data + 0x2000, 0x1000);
6966 /*slice*/
6967 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6968 fw->data + 0x5000, 0x1000);
6969 }
6970
6971#if 1 /* #ifdef BUFFER_MGR_IN_C */
6972 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6973 if (!hw->lmem_addr) {
6974 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6975 return -ENOMEM;
6976 } else {
6977 hw->lmem_addr_remap = dma_map_single(
6978 amports_get_dma_device(),
6979 (void *)hw->lmem_addr,
6980 PAGE_SIZE, DMA_FROM_DEVICE);
6981 if (dma_mapping_error(amports_get_dma_device(),
6982 hw->lmem_addr_remap)) {
6983 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6984 "%s: failed to map lmem_addr\n", __func__);
6985 free_page(hw->lmem_addr);
6986 hw->lmem_addr = 0;
6987 hw->lmem_addr_remap = 0;
6988 return -ENOMEM;
6989 }
6990
6991 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6992 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6993 }
6994
6995 if (prefix_aux_buf_size > 0 ||
6996 suffix_aux_buf_size > 0) {
6997 u32 aux_buf_size;
6998 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6999 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7000 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7001 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7002 if (hw->aux_addr == NULL) {
7003 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7004 return -1;
7005 }
7006
7007 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7008 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7009 if (dma_mapping_error(amports_get_dma_device(),
7010 hw->aux_phy_addr)) {
7011 pr_err("%s: failed to map rpm buffer\n", __func__);
7012 kfree(hw->aux_addr);
7013 hw->aux_addr = NULL;
7014 return -1;
7015 }
7016 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7017 if (hw->sei_data_buf == NULL) {
7018 pr_err("%s: failed to alloc sei itu data buffer\n",
7019 __func__);
7020 return -1;
7021 }
7022 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7023 if (hw->sei_itu_data_buf == NULL) {
7024 pr_err("%s: failed to alloc sei itu data buffer\n",
7025 __func__);
7026 kfree(hw->aux_addr);
7027 hw->aux_addr = NULL;
7028 kfree(hw->sei_data_buf);
7029 hw->sei_data_buf = NULL;
7030
7031 return -1;
7032 }
7033
7034 if (NULL == hw->sei_user_data_buffer) {
7035 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7036 GFP_KERNEL);
7037 if (!hw->sei_user_data_buffer) {
7038 pr_info("%s: Can not allocate sei_data_buffer\n",
7039 __func__);
7040 kfree(hw->aux_addr);
7041 hw->aux_addr = NULL;
7042 kfree(hw->sei_data_buf);
7043 hw->sei_data_buf = NULL;
7044 kfree(hw->sei_itu_data_buf);
7045 hw->sei_itu_data_buf = NULL;
7046
7047 return -1;
7048 }
7049 hw->sei_user_data_wp = 0;
7050 }
7051 }
7052/* BUFFER_MGR_IN_C */
7053#endif
7054 hw->stat |= STAT_MC_LOAD;
7055
7056 /* add memory barrier */
7057 wmb();
7058
7059 return 0;
7060}
7061
7062static int vh264_stop(struct vdec_h264_hw_s *hw)
7063{
7064 if (hw->stat & STAT_VDEC_RUN) {
7065 amvdec_stop();
7066 hw->stat &= ~STAT_VDEC_RUN;
7067 }
7068#ifdef VDEC_DW
7069 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7070#endif
7071#ifdef MH264_USERDATA_ENABLE
7072 cancel_work_sync(&hw->user_data_ready_work);
7073#endif
7074 cancel_work_sync(&hw->notify_work);
7075 cancel_work_sync(&hw->timeout_work);
7076 cancel_work_sync(&hw->work);
7077
7078
7079 if (hw->stat & STAT_MC_LOAD) {
7080 if (hw->mc_cpu_addr != NULL) {
7081 dma_free_coherent(amports_get_dma_device(),
7082 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7083 hw->mc_dma_handle);
7084 hw->mc_cpu_addr = NULL;
7085 }
7086 if (hw->frame_mmu_map_addr != NULL) {
7087 dma_free_coherent(amports_get_dma_device(),
7088 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7089 hw->frame_mmu_map_phy_addr);
7090 hw->frame_mmu_map_addr = NULL;
7091 }
7092
7093 }
7094 if (hw->stat & STAT_ISR_REG) {
7095 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7096 hw->stat &= ~STAT_ISR_REG;
7097 }
7098 if (hw->lmem_addr_remap) {
7099 dma_unmap_single(amports_get_dma_device(),
7100 hw->lmem_addr_remap,
7101 PAGE_SIZE, DMA_FROM_DEVICE);
7102 hw->lmem_addr_remap = 0;
7103 }
7104 if (hw->lmem_addr) {
7105 free_page(hw->lmem_addr);
7106 hw->lmem_addr = 0;
7107 }
7108 if (hw->aux_addr) {
7109 dma_unmap_single(amports_get_dma_device(),
7110 hw->aux_phy_addr,
7111 hw->prefix_aux_size + hw->suffix_aux_size,
7112 DMA_FROM_DEVICE);
7113 kfree(hw->aux_addr);
7114 hw->aux_addr = NULL;
7115 }
7116 if (hw->sei_data_buf != NULL) {
7117 kfree(hw->sei_data_buf);
7118 hw->sei_data_buf = NULL;
7119 }
7120 if (hw->sei_itu_data_buf != NULL) {
7121 kfree(hw->sei_itu_data_buf);
7122 hw->sei_itu_data_buf = NULL;
7123 }
7124 if (hw->sei_user_data_buffer != NULL) {
7125 kfree(hw->sei_user_data_buffer);
7126 hw->sei_user_data_buffer = NULL;
7127 }
7128 /* amvdec_disable(); */
7129
7130 vfree(hw->fw);
7131 hw->fw = NULL;
7132
7133 if (hw->mmu_enable) {
7134 vfree(hw->fw_mmu);
7135 hw->fw_mmu = NULL;
7136 }
7137
7138 dpb_print(DECODE_ID(hw), 0,
7139 "%s\n",
7140 __func__);
7141 return 0;
7142}
7143
7144static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7145{
7146 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7147 int count = 0;
7148 do {
7149 usleep_range(100, 500);
7150 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7151 break;
7152 if (count > 2000) {
7153 dpb_print(DECODE_ID(hw),
7154 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7155 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7156 break;
7157 } else
7158 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7159 count++;
7160 } while (1);
7161}
7162
7163static void vh264_notify_work(struct work_struct *work)
7164{
7165 struct vdec_h264_hw_s *hw = container_of(work,
7166 struct vdec_h264_hw_s, notify_work);
7167 struct vdec_s *vdec = hw_to_vdec(hw);
7168 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7169 vf_notify_receiver(vdec->vf_provider_name,
7170 VFRAME_EVENT_PROVIDER_FR_HINT,
7171 (void *)((unsigned long)hw->frame_dur));
7172 vdec->fr_hint_state = VDEC_HINTED;
7173 }
7174
7175 return;
7176}
7177
7178#ifdef MH264_USERDATA_ENABLE
7179static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7180{
7181 hw->wait_for_udr_send = 0;
7182 hw->sei_itu_data_len = 0;
7183 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7184}
7185
7186static void vmh264_crate_userdata_manager(
7187 struct vdec_h264_hw_s *hw,
7188 u8 *userdata_buf,
7189 int buf_len)
7190{
7191 if (hw) {
7192
7193
7194 mutex_init(&hw->userdata_mutex);
7195
7196 memset(&hw->userdata_info, 0,
7197 sizeof(struct mh264_userdata_info_t));
7198 hw->userdata_info.data_buf = userdata_buf;
7199 hw->userdata_info.buf_len = buf_len;
7200 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7201
7202 vmh264_reset_udr_mgr(hw);
7203
7204 }
7205}
7206
7207static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7208{
7209 if (hw)
7210 memset(&hw->userdata_info,
7211 0,
7212 sizeof(struct mh264_userdata_info_t));
7213}
7214
7215/*
7216#define DUMP_USERDATA_RECORD
7217*/
7218#ifdef DUMP_USERDATA_RECORD
7219
7220#define MAX_USER_DATA_SIZE 3145728
7221static void *user_data_buf;
7222static unsigned char *pbuf_start;
7223static int total_len;
7224static int bskip;
7225static int n_userdata_id;
7226
7227static void print_data(unsigned char *pdata,
7228 int len,
7229 unsigned int poc_number,
7230 unsigned int flag,
7231 unsigned int duration,
7232 unsigned int vpts,
7233 unsigned int vpts_valid,
7234 int rec_id)
7235{
7236 int nLeft;
7237
7238 nLeft = len;
7239#if 0
7240 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7241 rec_id, len, flag,
7242 duration, vpts, vpts_valid, poc_number);
7243#endif
7244 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7245 rec_id, len, flag, vpts);
7246
7247 if (len == 96) {
7248 int i;
7249 nLeft = 72;
7250 while (nLeft >= 16) {
7251 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7252 pdata[0], pdata[1], pdata[2], pdata[3],
7253 pdata[4], pdata[5], pdata[6], pdata[7],
7254 pdata[8], pdata[9], pdata[10], pdata[11],
7255 pdata[12], pdata[13], pdata[14], pdata[15]);
7256 nLeft -= 16;
7257 pdata += 16;
7258 }
7259
7260
7261 while (nLeft > 0) {
7262 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7263 pdata[0], pdata[1], pdata[2], pdata[3],
7264 pdata[4], pdata[5], pdata[6], pdata[7]);
7265 nLeft -= 8;
7266 pdata += 8;
7267 }
7268
7269 i = 0;
7270 nLeft = 96-72;
7271 while (i < nLeft) {
7272 if (pdata[0] != 0) {
7273 pr_info("some data error\n");
7274 break;
7275 }
7276 pdata++;
7277 i++;
7278 }
7279 } else {
7280 while (nLeft >= 16) {
7281 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7282 pdata[0], pdata[1], pdata[2], pdata[3],
7283 pdata[4], pdata[5], pdata[6], pdata[7],
7284 pdata[8], pdata[9], pdata[10], pdata[11],
7285 pdata[12], pdata[13], pdata[14], pdata[15]);
7286 nLeft -= 16;
7287 pdata += 16;
7288 }
7289
7290
7291 while (nLeft > 0) {
7292 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7293 pdata[0], pdata[1], pdata[2], pdata[3],
7294 pdata[4], pdata[5], pdata[6], pdata[7]);
7295 nLeft -= 8;
7296 pdata += 8;
7297 }
7298
7299 }
7300}
7301
7302static void push_to_buf(struct vdec_h264_hw_s *hw,
7303 u8 *pdata,
7304 int len,
7305 struct userdata_meta_info_t *pmeta);
7306
7307static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7308 struct mh264_userdata_record_t *record)
7309{
7310 if (record && hw) {
7311 u8 *pdata;
7312
7313 pdata = hw->userdata_info.data_buf + record->rec_start;
7314/*
7315 print_data(pdata,
7316 record->rec_len,
7317 record->meta_info.flags,
7318 record->meta_info.duration,
7319 record->meta_info.vpts,
7320 record->meta_info.vpts_valid,
7321 n_record_id);
7322*/
7323 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7324 n_userdata_id++;
7325 }
7326}
7327
7328
7329static void push_to_buf(struct vdec_h264_hw_s *hw,
7330 u8 *pdata, int len,
7331 struct userdata_meta_info_t *pmeta)
7332{
7333 u32 *pLen;
7334 int info_cnt;
7335 u8 *pbuf_end;
7336
7337 if (!user_data_buf)
7338 return;
7339
7340 if (bskip) {
7341 pr_info("over size, skip\n");
7342 return;
7343 }
7344 info_cnt = 0;
7345 pLen = (u32 *)pbuf_start;
7346
7347 *pLen = len;
7348 pbuf_start += sizeof(u32);
7349 info_cnt++;
7350 pLen++;
7351
7352 *pLen = pmeta->poc_number;
7353 pbuf_start += sizeof(u32);
7354 info_cnt++;
7355 pLen++;
7356
7357 *pLen = pmeta->duration;
7358 pbuf_start += sizeof(u32);
7359 info_cnt++;
7360 pLen++;
7361
7362 *pLen = pmeta->flags;
7363 pbuf_start += sizeof(u32);
7364 info_cnt++;
7365 pLen++;
7366
7367 *pLen = pmeta->vpts;
7368 pbuf_start += sizeof(u32);
7369 info_cnt++;
7370 pLen++;
7371
7372 *pLen = pmeta->vpts_valid;
7373 pbuf_start += sizeof(u32);
7374 info_cnt++;
7375 pLen++;
7376
7377
7378 *pLen = n_userdata_id;
7379 pbuf_start += sizeof(u32);
7380 info_cnt++;
7381 pLen++;
7382
7383
7384
7385 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7386 if (pdata + len > pbuf_end) {
7387 int first_section_len;
7388
7389 first_section_len = pbuf_end - pdata;
7390 memcpy(pbuf_start, pdata, first_section_len);
7391 pdata = (u8 *)hw->sei_user_data_buffer;
7392 pbuf_start += first_section_len;
7393 memcpy(pbuf_start, pdata, len - first_section_len);
7394 pbuf_start += len - first_section_len;
7395 } else {
7396 memcpy(pbuf_start, pdata, len);
7397 pbuf_start += len;
7398 }
7399
7400 total_len += len + info_cnt * sizeof(u32);
7401 if (total_len >= MAX_USER_DATA_SIZE-4096)
7402 bskip = 1;
7403}
7404
7405static void show_user_data_buf(void)
7406{
7407 u8 *pbuf;
7408 int len;
7409 unsigned int flag;
7410 unsigned int duration;
7411 unsigned int vpts;
7412 unsigned int vpts_valid;
7413 unsigned int poc_number;
7414 int rec_id;
7415
7416 pr_info("show user data buf\n");
7417 pbuf = user_data_buf;
7418
7419 while (pbuf < pbuf_start) {
7420 u32 *pLen;
7421
7422 pLen = (u32 *)pbuf;
7423
7424 len = *pLen;
7425 pLen++;
7426 pbuf += sizeof(u32);
7427
7428 poc_number = *pLen;
7429 pLen++;
7430 pbuf += sizeof(u32);
7431
7432 duration = *pLen;
7433 pLen++;
7434 pbuf += sizeof(u32);
7435
7436 flag = *pLen;
7437 pLen++;
7438 pbuf += sizeof(u32);
7439
7440 vpts = *pLen;
7441 pLen++;
7442 pbuf += sizeof(u32);
7443
7444 vpts_valid = *pLen;
7445 pLen++;
7446 pbuf += sizeof(u32);
7447
7448 rec_id = *pLen;
7449 pLen++;
7450 pbuf += sizeof(u32);
7451
7452 print_data(pbuf, len, poc_number, flag,
7453 duration, vpts,
7454 vpts_valid, rec_id);
7455 pbuf += len;
7456 msleep(30);
7457 }
7458}
7459
7460static int vmh264_init_userdata_dump(void)
7461{
7462 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7463 if (user_data_buf)
7464 return 1;
7465 else
7466 return 0;
7467}
7468
7469static void vmh264_dump_userdata(void)
7470{
7471 if (user_data_buf) {
7472 show_user_data_buf();
7473 kfree(user_data_buf);
7474 user_data_buf = NULL;
7475 }
7476}
7477
7478static void vmh264_reset_user_data_buf(void)
7479{
7480 total_len = 0;
7481 pbuf_start = user_data_buf;
7482 bskip = 0;
7483 n_userdata_id = 0;
7484}
7485#endif
7486
7487
7488static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7489 int frame_type,
7490 u32 vpts,
7491 u32 vpts_valid)
7492{
7493 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7494
7495 unsigned char *pdata;
7496 u8 *pmax_sei_data_buffer;
7497 u8 *sei_data_buf;
7498 int i;
7499 int wp;
7500 int data_length;
7501 struct mh264_userdata_record_t *p_userdata_rec;
7502
7503
7504#ifdef MH264_USERDATA_ENABLE
7505 struct userdata_meta_info_t meta_info;
7506 memset(&meta_info, 0, sizeof(meta_info));
7507#endif
7508
7509 if (hw->sei_itu_data_len <= 0)
7510 return;
7511
7512 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7513 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7514 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7515 for (i = 0; i < hw->sei_itu_data_len; i++) {
7516 *pdata++ = sei_data_buf[i];
7517 if (pdata >= pmax_sei_data_buffer)
7518 pdata = (u8 *)hw->sei_user_data_buffer;
7519 }
7520
7521 hw->sei_user_data_wp = (hw->sei_user_data_wp
7522 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7523 hw->sei_itu_data_len = 0;
7524
7525#ifdef MH264_USERDATA_ENABLE
7526 meta_info.duration = hw->frame_dur;
7527 meta_info.flags |= (VFORMAT_H264 << 3);
7528
7529 meta_info.vpts = vpts;
7530 meta_info.vpts_valid = vpts_valid;
7531 meta_info.poc_number =
7532 p_H264_Dpb->mVideo.dec_picture->poc;
7533
7534
7535 wp = hw->sei_user_data_wp;
7536
7537 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7538 data_length = wp - hw->userdata_info.last_wp;
7539 else
7540 data_length = wp + hw->userdata_info.buf_len
7541 - hw->userdata_info.last_wp;
7542
7543 if (data_length & 0x7)
7544 data_length = (((data_length + 8) >> 3) << 3);
7545
7546 p_userdata_rec = &hw->ud_record;
7547 p_userdata_rec->meta_info = meta_info;
7548 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7549 p_userdata_rec->rec_len = data_length;
7550 hw->userdata_info.last_wp = wp;
7551
7552 p_userdata_rec->meta_info.flags |=
7553 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7554
7555 hw->wait_for_udr_send = 1;
7556 vdec_schedule_work(&hw->user_data_ready_work);
7557#endif
7558}
7559
7560
7561static void user_data_ready_notify_work(struct work_struct *work)
7562{
7563 struct vdec_h264_hw_s *hw = container_of(work,
7564 struct vdec_h264_hw_s, user_data_ready_work);
7565
7566
7567 mutex_lock(&hw->userdata_mutex);
7568
7569 hw->userdata_info.records[hw->userdata_info.write_index]
7570 = hw->ud_record;
7571 hw->userdata_info.write_index++;
7572 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7573 hw->userdata_info.write_index = 0;
7574
7575 mutex_unlock(&hw->userdata_mutex);
7576
7577#ifdef DUMP_USERDATA_RECORD
7578 dump_userdata_record(hw, &hw->ud_record);
7579#endif
7580 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7581
7582 hw->wait_for_udr_send = 0;
7583}
7584
7585static int vmh264_user_data_read(struct vdec_s *vdec,
7586 struct userdata_param_t *puserdata_para)
7587{
7588 struct vdec_h264_hw_s *hw = NULL;
7589 int rec_ri, rec_wi;
7590 int rec_len;
7591 u8 *rec_data_start;
7592 u8 *pdest_buf;
7593 struct mh264_userdata_record_t *p_userdata_rec;
7594 u32 data_size;
7595 u32 res;
7596 int copy_ok = 1;
7597
7598 hw = (struct vdec_h264_hw_s *)vdec->private;
7599
7600 pdest_buf = puserdata_para->pbuf_addr;
7601
7602 mutex_lock(&hw->userdata_mutex);
7603
7604/*
7605 pr_info("ri = %d, wi = %d\n",
7606 lg_p_mpeg12_userdata_info->read_index,
7607 lg_p_mpeg12_userdata_info->write_index);
7608*/
7609 rec_ri = hw->userdata_info.read_index;
7610 rec_wi = hw->userdata_info.write_index;
7611
7612 if (rec_ri == rec_wi) {
7613 mutex_unlock(&hw->userdata_mutex);
7614 return 0;
7615 }
7616
7617 p_userdata_rec = hw->userdata_info.records + rec_ri;
7618
7619 rec_len = p_userdata_rec->rec_len;
7620 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7621/*
7622 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7623 p_userdata_rec->rec_len,
7624 p_userdata_rec->rec_start,
7625 puserdata_para->buf_len);
7626*/
7627 if (rec_len <= puserdata_para->buf_len) {
7628 /* dvb user data buffer is enought to
7629 copy the whole recored. */
7630 data_size = rec_len;
7631 if (rec_data_start + data_size
7632 > hw->userdata_info.data_buf_end) {
7633 int first_section_len;
7634
7635 first_section_len = hw->userdata_info.buf_len -
7636 p_userdata_rec->rec_start;
7637 res = (u32)copy_to_user((void *)pdest_buf,
7638 (void *)rec_data_start,
7639 first_section_len);
7640 if (res) {
7641 pr_info("p1 read not end res=%d, request=%d\n",
7642 res, first_section_len);
7643 copy_ok = 0;
7644
7645 p_userdata_rec->rec_len -=
7646 first_section_len - res;
7647 p_userdata_rec->rec_start +=
7648 first_section_len - res;
7649 puserdata_para->data_size =
7650 first_section_len - res;
7651 } else {
7652 res = (u32)copy_to_user(
7653 (void *)(pdest_buf+first_section_len),
7654 (void *)hw->userdata_info.data_buf,
7655 data_size - first_section_len);
7656 if (res) {
7657 pr_info("p2 read not end res=%d, request=%d\n",
7658 res, data_size);
7659 copy_ok = 0;
7660 }
7661 p_userdata_rec->rec_len -=
7662 data_size - res;
7663 p_userdata_rec->rec_start =
7664 data_size - first_section_len - res;
7665 puserdata_para->data_size =
7666 data_size - res;
7667 }
7668 } else {
7669 res = (u32)copy_to_user((void *)pdest_buf,
7670 (void *)rec_data_start,
7671 data_size);
7672 if (res) {
7673 pr_info("p3 read not end res=%d, request=%d\n",
7674 res, data_size);
7675 copy_ok = 0;
7676 }
7677 p_userdata_rec->rec_len -= data_size - res;
7678 p_userdata_rec->rec_start += data_size - res;
7679 puserdata_para->data_size = data_size - res;
7680 }
7681
7682 if (copy_ok) {
7683 hw->userdata_info.read_index++;
7684 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7685 hw->userdata_info.read_index = 0;
7686 }
7687 } else {
7688 /* dvb user data buffer is not enought
7689 to copy the whole recored. */
7690 data_size = puserdata_para->buf_len;
7691 if (rec_data_start + data_size
7692 > hw->userdata_info.data_buf_end) {
7693 int first_section_len;
7694
7695 first_section_len = hw->userdata_info.buf_len -
7696 p_userdata_rec->rec_start;
7697 res = (u32)copy_to_user((void *)pdest_buf,
7698 (void *)rec_data_start,
7699 first_section_len);
7700 if (res) {
7701 pr_info("p4 read not end res=%d, request=%d\n",
7702 res, first_section_len);
7703 copy_ok = 0;
7704 p_userdata_rec->rec_len -=
7705 first_section_len - res;
7706 p_userdata_rec->rec_start +=
7707 first_section_len - res;
7708 puserdata_para->data_size =
7709 first_section_len - res;
7710 } else {
7711 /* first secton copy is ok*/
7712 res = (u32)copy_to_user(
7713 (void *)(pdest_buf+first_section_len),
7714 (void *)hw->userdata_info.data_buf,
7715 data_size - first_section_len);
7716 if (res) {
7717 pr_info("p5 read not end res=%d, request=%d\n",
7718 res,
7719 data_size - first_section_len);
7720 copy_ok = 0;
7721 }
7722
7723 p_userdata_rec->rec_len -=
7724 data_size - res;
7725 p_userdata_rec->rec_start =
7726 data_size - first_section_len - res;
7727 puserdata_para->data_size =
7728 data_size - res;
7729 }
7730 } else {
7731 res = (u32)copy_to_user((void *)pdest_buf,
7732 (void *)rec_data_start,
7733 data_size);
7734 if (res) {
7735 pr_info("p6 read not end res=%d, request=%d\n",
7736 res, data_size);
7737 copy_ok = 0;
7738 }
7739
7740 p_userdata_rec->rec_len -= data_size - res;
7741 p_userdata_rec->rec_start += data_size - res;
7742 puserdata_para->data_size = data_size - res;
7743 }
7744
7745 if (copy_ok) {
7746 hw->userdata_info.read_index++;
7747 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7748 hw->userdata_info.read_index = 0;
7749 }
7750
7751 }
7752 puserdata_para->meta_info = p_userdata_rec->meta_info;
7753
7754 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7755 puserdata_para->meta_info.records_in_que =
7756 hw->userdata_info.write_index -
7757 hw->userdata_info.read_index;
7758 else
7759 puserdata_para->meta_info.records_in_que =
7760 hw->userdata_info.write_index +
7761 USERDATA_FIFO_NUM -
7762 hw->userdata_info.read_index;
7763
7764 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7765
7766 mutex_unlock(&hw->userdata_mutex);
7767
7768 return 1;
7769}
7770
7771static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7772{
7773 struct vdec_h264_hw_s *hw = NULL;
7774
7775 hw = (struct vdec_h264_hw_s *)vdec->private;
7776
7777 if (hw) {
7778 mutex_lock(&hw->userdata_mutex);
7779 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7780 bInit,
7781 hw->userdata_info.read_index,
7782 hw->userdata_info.write_index);
7783 hw->userdata_info.read_index = 0;
7784 hw->userdata_info.write_index = 0;
7785
7786 if (bInit)
7787 hw->userdata_info.last_wp = 0;
7788 mutex_unlock(&hw->userdata_mutex);
7789 }
7790}
7791
7792static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7793{
7794 amstream_wakeup_userdata_poll(vdec);
7795}
7796
7797#endif
7798
7799
7800static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7801 struct vdec_s *vdec, int from)
7802{
7803 /* finished decoding one frame or error,
7804 * notify vdec core to switch context
7805 */
7806 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7807 "%s dec_result %d %x %x %x\n",
7808 __func__,
7809 hw->dec_result,
7810 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7811 READ_VREG(VLD_MEM_VIFIFO_WP),
7812 READ_VREG(VLD_MEM_VIFIFO_RP));
7813 if (!hw->mmu_enable) {
7814 mutex_lock(&vmh264_mutex);
7815 dealloc_buf_specs(hw, 0);
7816 mutex_unlock(&vmh264_mutex);
7817 }
7818 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7819 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7820 u32 param1 = READ_VREG(AV_SCRATCH_1);
7821 u32 param2 = READ_VREG(AV_SCRATCH_2);
7822 u32 param3 = READ_VREG(AV_SCRATCH_6);
7823 u32 param4 = READ_VREG(AV_SCRATCH_B);
7824
7825 if (vh264_set_params(hw, param1,
7826 param2, param3, param4) < 0)
7827 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7828
7829 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7830 (hw->dpb.mDPB.size<<16) |
7831 (hw->dpb.mDPB.size<<8));
7832
7833 if (hw->is_used_v4l) {
7834 struct aml_vcodec_ctx *ctx =
7835 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7836
7837 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7838 struct aml_vdec_ps_infos ps;
7839
7840 ps.visible_width = hw->frame_width;
7841 ps.visible_height = hw->frame_height;
7842 ps.coded_width = ALIGN(hw->frame_width, 64);
7843 ps.coded_height = ALIGN(hw->frame_height, 64);
7844 ps.dpb_size = hw->dpb.mDPB.size;
7845 hw->v4l_params_parsed = true;
7846 vdec_v4l_set_ps_infos(ctx, &ps);
7847 }
7848 }
7849
7850 start_process_time(hw);
7851 return;
7852 } else
7853 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7854 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7855 && (hw_to_vdec(hw)->next_status !=
7856 VDEC_STATUS_DISCONNECTED)) {
7857 if (!vdec_has_more_input(vdec)) {
7858 hw->dec_result = DEC_RESULT_EOS;
7859 vdec_schedule_work(&hw->work);
7860 return;
7861 }
7862
7863 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7864 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7865 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7866 __func__,
7867 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7868 READ_VREG(VLD_MEM_VIFIFO_WP),
7869 READ_VREG(VLD_MEM_VIFIFO_RP));
7870 mutex_lock(&hw->chunks_mutex);
7871 vdec_vframe_dirty(vdec, hw->chunk);
7872 hw->chunk = NULL;
7873 mutex_unlock(&hw->chunks_mutex);
7874 vdec_clean_input(vdec);
7875 }
7876 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7877 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7878 > get_data_timeout_val)) {
7879 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7880 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7881 __func__);
7882 goto result_done;
7883 }
7884 if (is_buffer_available(vdec)) {
7885 int r;
7886 int decode_size;
7887 r = vdec_prepare_input(vdec, &hw->chunk);
7888 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7889 VDEC_STATUS_DISCONNECTED)) {
7890 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7891
7892 dpb_print(DECODE_ID(hw),
7893 PRINT_FLAG_VDEC_DETAIL,
7894 "vdec_prepare_input: Insufficient data\n");
7895 vdec_schedule_work(&hw->work);
7896 return;
7897 }
7898 hw->dec_result = DEC_RESULT_NONE;
7899 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7900 "%s: chunk size 0x%x\n",
7901 __func__, hw->chunk->size);
7902
7903 if (dpb_is_debug(DECODE_ID(hw),
7904 PRINT_FRAMEBASE_DATA)) {
7905 int jj;
7906 u8 *data = NULL;
7907
7908 if (!hw->chunk->block->is_mapped)
7909 data = codec_mm_vmap(
7910 hw->chunk->block->start +
7911 hw->chunk->offset, r);
7912 else
7913 data = ((u8 *)
7914 hw->chunk->block->start_virt)
7915 + hw->chunk->offset;
7916
7917 for (jj = 0; jj < r; jj++) {
7918 if ((jj & 0xf) == 0)
7919 dpb_print(DECODE_ID(hw),
7920 PRINT_FRAMEBASE_DATA,
7921 "%06x:", jj);
7922 dpb_print_cont(DECODE_ID(hw),
7923 PRINT_FRAMEBASE_DATA,
7924 "%02x ", data[jj]);
7925 if (((jj + 1) & 0xf) == 0)
7926 dpb_print_cont(DECODE_ID(hw),
7927 PRINT_FRAMEBASE_DATA,
7928 "\n");
7929 }
7930
7931 if (!hw->chunk->block->is_mapped)
7932 codec_mm_unmap_phyaddr(data);
7933 }
7934 WRITE_VREG(POWER_CTL_VLD,
7935 READ_VREG(POWER_CTL_VLD) |
7936 (0 << 10) | (1 << 9) | (1 << 6));
7937 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7938 decode_size = hw->chunk->size +
7939 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7940 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7941 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7942 vdec_enable_input(vdec);
7943
7944 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7945 start_process_time(hw);
7946 } else{
7947 if (hw_to_vdec(hw)->next_status
7948 != VDEC_STATUS_DISCONNECTED) {
7949 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7950 vdec_schedule_work(&hw->work);
7951 }
7952 }
7953 return;
7954 } else if (hw->dec_result == DEC_RESULT_DONE) {
7955 /* if (!hw->ctx_valid)
7956 hw->ctx_valid = 1; */
7957result_done:
7958 if (hw->mmu_enable
7959 && hw->frame_busy && hw->frame_done) {
7960 long used_4k_num;
7961 hevc_sao_wait_done(hw);
7962 if (hw->hevc_cur_buf_idx != 0xffff) {
7963 used_4k_num =
7964 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7965 if (used_4k_num >= 0)
7966 dpb_print(DECODE_ID(hw),
7967 PRINT_FLAG_MMU_DETAIL,
7968 "release unused buf , used_4k_num %ld index %d\n",
7969 used_4k_num, hw->hevc_cur_buf_idx);
7970 hevc_mmu_dma_check(hw_to_vdec(hw));
7971 decoder_mmu_box_free_idx_tail(
7972 hw->mmu_box,
7973 hw->hevc_cur_buf_idx,
7974 used_4k_num);
7975 hw->hevc_cur_buf_idx = 0xffff;
7976 }
7977 }
7978 decode_frame_count[DECODE_ID(hw)]++;
7979 amvdec_stop();
7980 if (!vdec_is_support_4k()) {
7981 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7982 clk_adj_frame_count++;
7983 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7984 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7985 }
7986 }
7987 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7988 "%s dec_result %d %x %x %x\n",
7989 __func__,
7990 hw->dec_result,
7991 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7992 READ_VREG(VLD_MEM_VIFIFO_WP),
7993 READ_VREG(VLD_MEM_VIFIFO_RP));
7994 mutex_lock(&hw->chunks_mutex);
7995 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7996 hw->chunk = NULL;
7997 mutex_unlock(&hw->chunks_mutex);
7998 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7999 /*
8000 stream base: stream buf empty or timeout
8001 frame base: vdec_prepare_input fail
8002 */
8003 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8004 VDEC_STATUS_DISCONNECTED)) {
8005 hw->dec_result = DEC_RESULT_EOS;
8006 vdec_schedule_work(&hw->work);
8007 return;
8008 }
8009 hw->next_again_flag = 1;
8010 } else if (hw->dec_result == DEC_RESULT_EOS) {
8011 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8012 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8013 "%s: end of stream\n",
8014 __func__);
8015 amvdec_stop();
8016 if (hw->mmu_enable)
8017 amhevc_stop();
8018 hw->eos = 1;
8019 flush_dpb(p_H264_Dpb);
8020 if (hw->is_used_v4l)
8021 notify_v4l_eos(hw_to_vdec(hw));
8022 mutex_lock(&hw->chunks_mutex);
8023 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8024 hw->chunk = NULL;
8025 mutex_unlock(&hw->chunks_mutex);
8026 vdec_clean_input(vdec);
8027 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8028 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8029 "%s: force exit\n",
8030 __func__);
8031 amvdec_stop();
8032 if (hw->mmu_enable)
8033 amhevc_stop();
8034 if (hw->stat & STAT_ISR_REG) {
8035 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8036 hw->stat &= ~STAT_ISR_REG;
8037 }
8038 }
8039 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8040 del_timer_sync(&hw->check_timer);
8041 hw->stat &= ~STAT_TIMER_ARM;
8042
8043 wait_vmh264_search_done(hw);
8044 /* mark itself has all HW resource released and input released */
8045
8046#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8047 if (hw->switch_dvlayer_flag) {
8048 if (vdec->slave)
8049 vdec_set_next_sched(vdec, vdec->slave);
8050 else if (vdec->master)
8051 vdec_set_next_sched(vdec, vdec->master);
8052 } else if (vdec->slave || vdec->master)
8053 vdec_set_next_sched(vdec, vdec);
8054#endif
8055
8056 if (from == 1) {
8057 /* This is a timeout work */
8058 if (work_pending(&hw->work)) {
8059 /*
8060 * The vh264_work arrives at the last second,
8061 * give it a chance to handle the scenario.
8062 */
8063 return;
8064 }
8065 }
8066
8067 /* mark itself has all HW resource released and input released */
8068 if (vdec->parallel_dec == 1) {
8069 if (hw->mmu_enable == 0)
8070 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8071 else
8072 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8073 } else
8074 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8075
8076 wake_up_interruptible(&hw->wait_q);
8077
8078 if (hw->is_used_v4l) {
8079 struct aml_vcodec_ctx *ctx =
8080 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8081
8082 if (ctx->param_sets_from_ucode &&
8083 !hw->v4l_params_parsed)
8084 vdec_v4l_write_frame_sync(ctx);
8085 }
8086
8087 if (hw->vdec_cb)
8088 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8089}
8090
8091
8092static void vh264_work(struct work_struct *work)
8093{
8094 struct vdec_h264_hw_s *hw = container_of(work,
8095 struct vdec_h264_hw_s, work);
8096 struct vdec_s *vdec = hw_to_vdec(hw);
8097
8098 vh264_work_implement(hw, vdec, 0);
8099}
8100
8101
8102static void vh264_timeout_work(struct work_struct *work)
8103{
8104 struct vdec_h264_hw_s *hw = container_of(work,
8105 struct vdec_h264_hw_s, timeout_work);
8106 struct vdec_s *vdec = hw_to_vdec(hw);
8107
8108 if (work_pending(&hw->work))
8109 return;
8110
8111 vh264_work_implement(hw, vdec, 1);
8112}
8113
8114static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8115{
8116 bool ret = 0;
8117 struct vdec_h264_hw_s *hw =
8118 (struct vdec_h264_hw_s *)vdec->private;
8119 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8120 CODEC_MM_FLAGS_TVP : 0;
8121
8122 if (!hw->first_sc_checked && hw->mmu_enable) {
8123 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8124 hw->first_sc_checked =1;
8125 dpb_print(DECODE_ID(hw), 0,
8126 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8127 size, (hw->need_cache_size >> PAGE_SHIFT),
8128 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8129 }
8130
8131 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8132 && pre_decode_buf_level != 0) {
8133 u32 rp, wp, level;
8134
8135 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8136 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8137 if (wp < rp)
8138 level = vdec->input.size + wp - rp;
8139 else
8140 level = wp - rp;
8141
8142 if (level < pre_decode_buf_level)
8143 return 0;
8144 }
8145
8146#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8147 if (vdec->master)
8148 return 0;
8149#endif
8150 if (hw->eos)
8151 return 0;
8152
8153 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8154 return 0;
8155
8156 if (disp_vframe_valve_level &&
8157 kfifo_len(&hw->display_q) >=
8158 disp_vframe_valve_level) {
8159 hw->valve_count--;
8160 if (hw->valve_count <= 0)
8161 hw->valve_count = 2;
8162 else
8163 return 0;
8164 }
8165 if (hw->next_again_flag &&
8166 (!vdec_frame_based(vdec))) {
8167 u32 parser_wr_ptr =
8168 READ_PARSER_REG(PARSER_VIDEO_WP);
8169 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8170 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8171 again_threshold) {
8172 int r = vdec_sync_input(vdec);
8173 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8174 "%s buf lelvel:%x\n", __func__, r);
8175 return 0;
8176 }
8177 }
8178
8179 if (h264_debug_flag & 0x20000000) {
8180 /* pr_info("%s, a\n", __func__); */
8181 ret = 1;
8182 } else
8183 ret = is_buffer_available(vdec);
8184
8185#ifdef CONSTRAIN_MAX_BUF_NUM
8186 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8187 if (run_ready_max_vf_only_num > 0 &&
8188 get_vf_ref_only_buf_count(hw) >=
8189 run_ready_max_vf_only_num
8190 )
8191 ret = 0;
8192 if (run_ready_display_q_num > 0 &&
8193 kfifo_len(&hw->display_q) >=
8194 run_ready_display_q_num)
8195 ret = 0;
8196 /*avoid more buffers consumed when
8197 switching resolution*/
8198 if (run_ready_max_buf_num == 0xff &&
8199 get_used_buf_count(hw) >
8200 hw->dpb.mDPB.size)
8201 ret = 0;
8202 else if (run_ready_max_buf_num &&
8203 get_used_buf_count(hw) >=
8204 run_ready_max_buf_num)
8205 ret = 0;
8206 }
8207#endif
8208 if (hw->is_used_v4l) {
8209 struct aml_vcodec_ctx *ctx =
8210 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8211
8212 if (ctx->param_sets_from_ucode &&
8213 !ctx->v4l_codec_ready &&
8214 hw->v4l_params_parsed) {
8215 ret = 0; /*the params has parsed.*/
8216 } else if (!ctx->v4l_codec_dpb_ready) {
8217 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
8218 run_ready_min_buf_num)
8219 ret = 0;
8220 }
8221 }
8222
8223 if (ret)
8224 not_run_ready[DECODE_ID(hw)] = 0;
8225 else
8226 not_run_ready[DECODE_ID(hw)]++;
8227 if (vdec->parallel_dec == 1) {
8228 if (hw->mmu_enable == 0)
8229 return ret ? (CORE_MASK_VDEC_1) : 0;
8230 else
8231 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8232 } else
8233 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8234}
8235
8236static unsigned char get_data_check_sum
8237 (struct vdec_h264_hw_s *hw, int size)
8238{
8239 int jj;
8240 int sum = 0;
8241 u8 *data = NULL;
8242
8243 if (!hw->chunk->block->is_mapped)
8244 data = codec_mm_vmap(hw->chunk->block->start +
8245 hw->chunk->offset, size);
8246 else
8247 data = ((u8 *)hw->chunk->block->start_virt)
8248 + hw->chunk->offset;
8249
8250 for (jj = 0; jj < size; jj++)
8251 sum += data[jj];
8252
8253 if (!hw->chunk->block->is_mapped)
8254 codec_mm_unmap_phyaddr(data);
8255 return sum;
8256}
8257
8258static void run(struct vdec_s *vdec, unsigned long mask,
8259 void (*callback)(struct vdec_s *, void *), void *arg)
8260{
8261 struct vdec_h264_hw_s *hw =
8262 (struct vdec_h264_hw_s *)vdec->private;
8263 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8264 int size, ret = -1;
8265
8266 run_count[DECODE_ID(hw)]++;
8267 vdec_reset_core(vdec);
8268 if (hw->mmu_enable)
8269 hevc_reset_core(vdec);
8270 hw->vdec_cb_arg = arg;
8271 hw->vdec_cb = callback;
8272
8273 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8274 hw->reset_bufmgr_flag = 1;
8275 dpb_print(DECODE_ID(hw), 0,
8276 "kfifo len:%d invaild, need bufmgr reset\n",
8277 kfifo_len(&hw->display_q));
8278 }
8279
8280 hw->pre_parser_wr_ptr =
8281 READ_PARSER_REG(PARSER_VIDEO_WP);
8282 hw->next_again_flag = 0;
8283
8284 if (hw->reset_bufmgr_flag ||
8285 ((error_proc_policy & 0x40) &&
8286 p_H264_Dpb->buf_alloc_fail)) {
8287 if (!hw->is_used_v4l)
8288 h264_reset_bufmgr(vdec);
8289 else {
8290 struct aml_vcodec_ctx *ctx =
8291 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8292 pr_info("v4l2 buffer reset\n");
8293 hw->wait_reset_done_flag = 1;
8294 hw->reset_bufmgr_flag = 0;
8295 vdec_v4l_post_evet(ctx, V4L2_EVENT_REQUEST_RESET);
8296 hw->dec_result = DEC_RESULT_NONE;
8297 vdec_schedule_work(&hw->work);
8298 return;
8299 }
8300 hw->reset_bufmgr_flag = 0;
8301 }
8302
8303 if (h264_debug_cmd & 0xf000) {
8304 if (((h264_debug_cmd >> 12) & 0xf)
8305 == (DECODE_ID(hw) + 1)) {
8306 h264_reconfig(hw);
8307 h264_debug_cmd &= (~0xf000);
8308 }
8309 }
8310 /* hw->chunk = vdec_prepare_input(vdec); */
8311#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8312 if (vdec->slave || vdec->master)
8313 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8314#endif
8315 size = vdec_prepare_input(vdec, &hw->chunk);
8316 if ((size < 0) ||
8317 (input_frame_based(vdec) && hw->chunk == NULL)) {
8318 input_empty[DECODE_ID(hw)]++;
8319 hw->dec_result = DEC_RESULT_AGAIN;
8320
8321 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8322 "vdec_prepare_input: Insufficient data\n");
8323
8324 vdec_schedule_work(&hw->work);
8325 return;
8326 }
8327 input_empty[DECODE_ID(hw)] = 0;
8328
8329 hw->dec_result = DEC_RESULT_NONE;
8330 hw->get_data_count = 0;
8331#if 0
8332 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8333 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8334 READ_VREG(VLD_MEM_VIFIFO_RP),
8335 READ_VREG(VLD_MEM_VIFIFO_WP));
8336#endif
8337
8338 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8339 u8 *data = NULL;
8340
8341 if (!hw->chunk->block->is_mapped)
8342 data = codec_mm_vmap(hw->chunk->block->start +
8343 hw->chunk->offset, size);
8344 else
8345 data = ((u8 *)hw->chunk->block->start_virt)
8346 + hw->chunk->offset;
8347
8348 if (dpb_is_debug(DECODE_ID(hw),
8349 PRINT_FLAG_VDEC_STATUS)
8350 ) {
8351 dpb_print(DECODE_ID(hw), 0,
8352 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8353 __func__, size, get_data_check_sum(hw, size),
8354 data[0], data[1], data[2], data[3],
8355 data[4], data[5], data[size - 4],
8356 data[size - 3], data[size - 2],
8357 data[size - 1]);
8358 }
8359 if (dpb_is_debug(DECODE_ID(hw),
8360 PRINT_FRAMEBASE_DATA)
8361 ) {
8362 int jj;
8363
8364 for (jj = 0; jj < size; jj++) {
8365 if ((jj & 0xf) == 0)
8366 dpb_print(DECODE_ID(hw),
8367 PRINT_FRAMEBASE_DATA,
8368 "%06x:", jj);
8369 dpb_print_cont(DECODE_ID(hw),
8370 PRINT_FRAMEBASE_DATA,
8371 "%02x ", data[jj]);
8372 if (((jj + 1) & 0xf) == 0)
8373 dpb_print_cont(DECODE_ID(hw),
8374 PRINT_FRAMEBASE_DATA,
8375 "\n");
8376 }
8377 }
8378
8379 if (!hw->chunk->block->is_mapped)
8380 codec_mm_unmap_phyaddr(data);
8381 } else
8382 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8383 "%s: %x %x %x %x %x size 0x%x\n",
8384 __func__,
8385 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8386 READ_VREG(VLD_MEM_VIFIFO_WP),
8387 READ_VREG(VLD_MEM_VIFIFO_RP),
8388 READ_PARSER_REG(PARSER_VIDEO_RP),
8389 READ_PARSER_REG(PARSER_VIDEO_WP),
8390 size);
8391
8392 start_process_time(hw);
8393 if (vdec->mc_loaded) {
8394 /*firmware have load before,
8395 and not changes to another.
8396 ignore reload.
8397 */
8398 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8399 } else {
8400
8401 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8402 if (ret < 0) {
8403 amvdec_enable_flag = false;
8404 amvdec_disable();
8405
8406 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8407 "MH264 the %s fw loading failed, err: %x\n",
8408 tee_enabled() ? "TEE" : "local", ret);
8409 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8410 vdec_schedule_work(&hw->work);
8411 return;
8412 }
8413 vdec->mc_type = VFORMAT_H264;
8414 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8415 if (hw->mmu_enable) {
8416 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8417 hw->fw_mmu->data);
8418 if (ret < 0) {
8419 amvdec_enable_flag = false;
8420 amhevc_disable();
8421
8422 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8423 "MH264_MMU the %s fw loading failed, err: %x\n",
8424 tee_enabled() ? "TEE" : "local", ret);
8425 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8426 vdec_schedule_work(&hw->work);
8427 return;
8428 }
8429 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8430 }
8431 vdec->mc_loaded = 1;
8432 }
8433 vmh264_reset_udr_mgr(hw);
8434
8435 if (vh264_hw_ctx_restore(hw) < 0) {
8436 vdec_schedule_work(&hw->work);
8437 return;
8438 }
8439 if (input_frame_based(vdec)) {
8440 int decode_size = 0;
8441
8442 decode_size = hw->chunk->size +
8443 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8444 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8445 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8446 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8447 } else {
8448 if (size <= 0)
8449 size = 0x7fffffff; /*error happen*/
8450 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8451 WRITE_VREG(H264_DECODE_SIZE, size);
8452 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8453 }
8454 config_aux_buf(hw);
8455 config_decode_mode(hw);
8456 vdec_enable_input(vdec);
8457 WRITE_VREG(NAL_SEARCH_CTL, 0);
8458 hw->sei_data_len = 0;
8459 if (enable_itu_t35)
8460 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8461 if (!hw->init_flag) {
8462 if (hw->mmu_enable)
8463 WRITE_VREG(NAL_SEARCH_CTL,
8464 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8465 else
8466 WRITE_VREG(NAL_SEARCH_CTL,
8467 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8468 }
8469 if (udebug_flag)
8470 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8471 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8472
8473 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8474
8475 if (hw->mmu_enable)
8476 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8477 else
8478 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8479 }
8480 amvdec_start();
8481 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8482 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8483 amhevc_start();
8484 if (hw->config_bufmgr_done) {
8485 hevc_mcr_sao_global_hw_init(hw,
8486 (hw->mb_width << 4), (hw->mb_height << 4));
8487 hevc_mcr_config_canv2axitbl(hw, 1);
8488 }
8489 }
8490
8491 /* if (hw->init_flag) { */
8492 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8493 /* } */
8494
8495 hw->init_flag = 1;
8496}
8497
8498static void reset(struct vdec_s *vdec)
8499{
8500 struct vdec_h264_hw_s *hw =
8501 (struct vdec_h264_hw_s *)vdec->private;
8502
8503 pr_info("vmh264 reset\n");
8504
8505 cancel_work_sync(&hw->work);
8506 cancel_work_sync(&hw->notify_work);
8507 if (hw->stat & STAT_VDEC_RUN) {
8508 amhevc_stop();
8509 hw->stat &= ~STAT_VDEC_RUN;
8510 }
8511
8512 if (hw->stat & STAT_TIMER_ARM) {
8513 del_timer_sync(&hw->check_timer);
8514 hw->stat &= ~STAT_TIMER_ARM;
8515 }
8516 hw->eos = 0;
8517 hw->decode_pic_count = 0;
8518 hw->dec_result = DEC_RESULT_NONE;
8519 reset_process_time(hw);
8520 h264_reset_bufmgr(vdec);
8521 hw->wait_reset_done_flag = 0;
8522
8523 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8524}
8525
8526static void h264_reconfig(struct vdec_h264_hw_s *hw)
8527{
8528 int i;
8529 unsigned long flags;
8530 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8531 struct vdec_s *vdec = hw_to_vdec(hw);
8532 dpb_print(DECODE_ID(hw), 0,
8533 "%s\n", __func__);
8534 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8535 all buffers are in display queue (used == 2),
8536 or free (used == 0)
8537 */
8538 if (dpb_is_debug(DECODE_ID(hw),
8539 PRINT_FLAG_DUMP_BUFSPEC))
8540 dump_bufspec(hw, "pre h264_reconfig");
8541
8542 flush_dpb(p_H264_Dpb);
8543 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8544
8545 if (hw->collocate_cma_alloc_addr) {
8546 decoder_bmmu_box_free_idx(
8547 hw->bmmu_box,
8548 BMMU_REF_IDX);
8549 hw->collocate_cma_alloc_addr = 0;
8550 hw->dpb.colocated_mv_addr_start = 0;
8551 hw->dpb.colocated_mv_addr_end = 0;
8552 }
8553 spin_lock_irqsave(&hw->bufspec_lock, flags);
8554 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8555 if (vdec->parallel_dec == 1) {
8556 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8557 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8558 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8559 hw->buffer_spec[i].y_canvas_index = -1;
8560 hw->buffer_spec[i].u_canvas_index = -1;
8561 hw->buffer_spec[i].v_canvas_index = -1;
8562#ifdef VDEC_DW
8563 if (IS_VDEC_DW(hw)) {
8564 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8565 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8566 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8567 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8568 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8569 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8570#endif
8571 }
8572 }
8573 /*make sure buffers not put back to bufmgr when
8574 vf_put is called*/
8575 if (hw->buffer_spec[i].used == 2)
8576 hw->buffer_spec[i].used = 3;
8577
8578 /* ready to release "free buffers"
8579 */
8580 if (hw->buffer_spec[i].used == 0)
8581 hw->buffer_spec[i].used = 4;
8582
8583 hw->buffer_spec[i].canvas_pos = -1;
8584 }
8585 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8586 hw->has_i_frame = 0;
8587 hw->config_bufmgr_done = 0;
8588
8589 if (hw->is_used_v4l) {
8590 mutex_lock(&vmh264_mutex);
8591 dealloc_buf_specs(hw, 1);
8592 mutex_unlock(&vmh264_mutex);
8593 }
8594
8595 if (dpb_is_debug(DECODE_ID(hw),
8596 PRINT_FLAG_DUMP_BUFSPEC))
8597 dump_bufspec(hw, "after h264_reconfig");
8598
8599}
8600
8601#ifdef ERROR_HANDLE_TEST
8602static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8603{
8604 int i;
8605 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8606 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8607 "%s\n", __func__);
8608 remove_dpb_pictures(p_H264_Dpb);
8609 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8610 /*make sure buffers not put back to bufmgr when
8611 vf_put is called*/
8612 if (hw->buffer_spec[i].used == 2)
8613 hw->buffer_spec[i].used = 5;
8614 }
8615
8616}
8617#endif
8618
8619static void h264_reset_bufmgr(struct vdec_s *vdec)
8620{
8621 int i;
8622 ulong timeout;
8623 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8624#if 0
8625 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8626 int actual_dpb_size, max_reference_size;
8627 int reorder_pic_num;
8628 unsigned int colocated_buf_size;
8629 unsigned int colocated_mv_addr_start;
8630 unsigned int colocated_mv_addr_end;
8631 dpb_print(DECODE_ID(hw), 0,
8632 "%s\n", __func__);
8633
8634 for (i = 0; i < VF_POOL_SIZE; i++)
8635 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8636
8637 actual_dpb_size = p_H264_Dpb->mDPB.size;
8638 max_reference_size = p_H264_Dpb->max_reference_size;
8639 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8640
8641 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8642 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8643 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8644
8645 hw->cur_pool++;
8646 if (hw->cur_pool >= VF_POOL_NUM)
8647 hw->cur_pool = 0;
8648
8649 INIT_KFIFO(hw->display_q);
8650 INIT_KFIFO(hw->newframe_q);
8651
8652 for (i = 0; i < VF_POOL_SIZE; i++) {
8653 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8654 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8655 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8656 kfifo_put(&hw->newframe_q, vf);
8657 }
8658
8659 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8660 hw->buffer_spec[i].used = 0;
8661
8662 dpb_init_global(&hw->dpb,
8663 DECODE_ID(hw), 0, 0);
8664 p_H264_Dpb->mDPB.size = actual_dpb_size;
8665 p_H264_Dpb->max_reference_size = max_reference_size;
8666 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8667
8668 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8669 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8670 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8671
8672 p_H264_Dpb->fast_output_enable = fast_output_enable;
8673 hw->has_i_frame = 0;
8674#else
8675 dpb_print(DECODE_ID(hw), 0,
8676 "%s frame count %d to skip %d\n\n",
8677 __func__, hw->decode_pic_count+1,
8678 hw->skip_frame_count);
8679
8680 timeout = jiffies + HZ;
8681 while (kfifo_len(&hw->display_q) > 0) {
8682 if (time_after(jiffies, timeout))
8683 break;
8684 schedule();
8685 }
8686
8687 for (i = 0; i < VF_POOL_SIZE; i++)
8688 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8689
8690 hw->cur_pool++;
8691 if (hw->cur_pool >= VF_POOL_NUM)
8692 hw->cur_pool = 0;
8693
8694 for (i = 0; i < VF_POOL_SIZE; i++)
8695 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8696
8697
8698 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8699
8700 buf_spec_init(hw);
8701
8702 vh264_local_init(hw);
8703 /*hw->decode_pic_count = 0;
8704 hw->seq_info2 = 0;*/
8705
8706 if (hw->is_used_v4l) {
8707 mutex_lock(&vmh264_mutex);
8708 /* detach relationship with v4l buffs.*/
8709 dealloc_buf_specs(hw, 1);
8710 mutex_unlock(&vmh264_mutex);
8711 }
8712
8713 if (vh264_set_params(hw,
8714 hw->cfg_param1,
8715 hw->cfg_param2,
8716 hw->cfg_param3,
8717 hw->cfg_param4) < 0)
8718 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8719
8720 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8721 if (first_i_policy & 0x01)
8722 hw->first_i_policy = (3 << 8) | first_i_policy;
8723
8724 hw->init_flag = 1;
8725 hw->reset_bufmgr_count++;
8726#endif
8727}
8728
8729int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8730{
8731 int ret = -1;
8732 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8733 CODEC_MM_FLAGS_TVP : 0;
8734 int buf_size = 64;
8735
8736 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8737 tvp_flag, hw->mmu_enable);
8738 hw->need_cache_size = buf_size * SZ_1M;
8739 hw->sc_start_time = get_jiffies_64();
8740 if (hw->mmu_enable && !hw->mmu_box) {
8741 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8742 hw->id,
8743 MMU_MAX_BUFFERS,
8744 hw->need_cache_size,
8745 tvp_flag);
8746 if (!hw->mmu_box) {
8747 pr_err("h264 4k alloc mmu box failed!!\n");
8748 return -1;
8749 }
8750 ret = 0;
8751 }
8752 if (!hw->bmmu_box) {
8753 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8754 DRIVER_NAME,
8755 hw->id,
8756 BMMU_MAX_BUFFERS,
8757 4 + PAGE_SHIFT,
8758 CODEC_MM_FLAGS_CMA_CLEAR |
8759 CODEC_MM_FLAGS_FOR_VDECODER |
8760 tvp_flag);
8761 if (hw->bmmu_box)
8762 ret = 0;
8763 }
8764 return ret;
8765}
8766int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8767{
8768 if (hw->mmu_box) {
8769 decoder_mmu_box_free(hw->mmu_box);
8770 hw->mmu_box = NULL;
8771 }
8772 if (hw->bmmu_box) {
8773 decoder_bmmu_box_free(hw->bmmu_box);
8774 hw->bmmu_box = NULL;
8775 }
8776 return 0;
8777}
8778
8779static int ammvdec_h264_probe(struct platform_device *pdev)
8780{
8781 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8782 struct vdec_h264_hw_s *hw = NULL;
8783 char *tmpbuf;
8784 int config_val;
8785
8786 if (pdata == NULL) {
8787 pr_info("\nammvdec_h264 memory resource undefined.\n");
8788 return -EFAULT;
8789 }
8790
8791 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8792 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8793 if (hw == NULL) {
8794 pr_info("\nammvdec_h264 device data allocation failed\n");
8795 return -ENOMEM;
8796 }
8797 hw->id = pdev->id;
8798 hw->platform_dev = pdev;
8799
8800 /* the ctx from v4l2 driver. */
8801 hw->v4l2_ctx = pdata->private;
8802
8803 platform_set_drvdata(pdev, pdata);
8804
8805 hw->mmu_enable = 0;
8806 hw->first_head_check_flag = 0;
8807 hw->new_iframe_flag = 0;
8808 hw->ref_err_flush_dpb_flag = 0;
8809 hw->wait_reset_done_flag = 0;
8810
8811 if (pdata->sys_info)
8812 hw->vh264_amstream_dec_info = *pdata->sys_info;
8813
8814 if (force_enable_mmu && pdata->sys_info &&
8815 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8816 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8817 (pdata->sys_info->height * pdata->sys_info->width
8818 > 1920 * 1088))
8819 hw->mmu_enable = 1;
8820
8821 if (hw->mmu_enable &&
8822 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8823 hw->mmu_enable = 0;
8824 pr_info("ionvideo needs disable mmu, path= %d \n",
8825 pdata->frame_base_video_path);
8826 }
8827
8828 if (ammvdec_h264_mmu_init(hw)) {
8829 h264_free_hw_stru(&pdev->dev, (void *)hw);
8830 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8831 return -ENOMEM;
8832 }
8833
8834 if (pdata->config_len) {
8835 /*use ptr config for doubel_write_mode, etc*/
8836 if (get_config_int(pdata->config,
8837 "mh264_double_write_mode", &config_val) == 0)
8838 hw->double_write_mode = config_val;
8839 else
8840 hw->double_write_mode = double_write_mode;
8841
8842 if (get_config_int(pdata->config,
8843 "parm_v4l_codec_enable",
8844 &config_val) == 0)
8845 hw->is_used_v4l = config_val;
8846
8847 if (get_config_int(pdata->config,
8848 "parm_v4l_buffer_margin",
8849 &config_val) == 0)
8850 hw->reorder_dpb_size_margin = config_val;
8851
8852 if (get_config_int(pdata->config,
8853 "parm_v4l_canvas_mem_mode",
8854 &config_val) == 0)
8855 hw->canvas_mode = config_val;
8856 } else
8857 hw->double_write_mode = double_write_mode;
8858
8859 if (!hw->is_used_v4l) {
8860 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8861 hw->canvas_mode = mem_map_mode;
8862
8863 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8864 hw->canvas_mode = pdata->canvas_mode;
8865 }
8866
8867 if (hw->mmu_enable)
8868 hw->double_write_mode &= 0xffff;
8869
8870 if (pdata->parallel_dec == 1) {
8871 int i;
8872 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8873 hw->buffer_spec[i].y_canvas_index = -1;
8874 hw->buffer_spec[i].u_canvas_index = -1;
8875 hw->buffer_spec[i].v_canvas_index = -1;
8876#ifdef VDEC_DW
8877 if (IS_VDEC_DW(hw)) {
8878 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8879 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8880 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8881 }
8882#endif
8883 }
8884 }
8885
8886 dpb_print(DECODE_ID(hw), 0,
8887 "%s mmu_enable %d double_write_mode 0x%x\n",
8888 __func__, hw->mmu_enable, hw->double_write_mode);
8889
8890 pdata->private = hw;
8891 pdata->dec_status = dec_status;
8892 pdata->set_trickmode = vmh264_set_trickmode;
8893 pdata->run_ready = run_ready;
8894 pdata->run = run;
8895 pdata->reset = reset;
8896 pdata->irq_handler = vh264_isr;
8897 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8898 pdata->dump_state = vmh264_dump_state;
8899
8900#ifdef MH264_USERDATA_ENABLE
8901 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8902 pdata->user_data_read = vmh264_user_data_read;
8903 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8904#else
8905 pdata->wakeup_userdata_poll = NULL;
8906 pdata->user_data_read = NULL;
8907 pdata->reset_userdata_fifo = NULL;
8908#endif
8909 if (pdata->use_vfm_path) {
8910 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8911 VFM_DEC_PROVIDER_NAME);
8912 hw->frameinfo_enable = 1;
8913 }
8914#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8915 else if (vdec_dual(pdata)) {
8916 if (dv_toggle_prov_name) /*debug purpose*/
8917 snprintf(pdata->vf_provider_name,
8918 VDEC_PROVIDER_NAME_SIZE,
8919 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8920 VFM_DEC_DVEL_PROVIDER_NAME);
8921 else
8922 snprintf(pdata->vf_provider_name,
8923 VDEC_PROVIDER_NAME_SIZE,
8924 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8925 VFM_DEC_DVBL_PROVIDER_NAME);
8926 }
8927#endif
8928 else
8929 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8930 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8931
8932 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8933 &vf_provider_ops, pdata);
8934
8935 platform_set_drvdata(pdev, pdata);
8936
8937 buf_spec_init(hw);
8938
8939 hw->platform_dev = pdev;
8940
8941#ifdef DUMP_USERDATA_RECORD
8942 vmh264_init_userdata_dump();
8943 vmh264_reset_user_data_buf();
8944#endif
8945 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8946 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8947 h264_free_hw_stru(&pdev->dev, (void *)hw);
8948 pdata->dec_status = NULL;
8949 return -ENOMEM;
8950 }
8951
8952 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8953 DCAC_READ_MARGIN;
8954 if (hw->mmu_enable) {
8955 u32 extif_size = EXTIF_BUF_SIZE;
8956 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8957 extif_size <<= 1;
8958 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8959 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8960 h264_free_hw_stru(&pdev->dev, (void *)hw);
8961 pdata->dec_status = NULL;
8962 return -ENOMEM;
8963 }
8964 }
8965 if (!vdec_secure(pdata)) {
8966#if 1
8967 /*init internal buf*/
8968 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8969 if (tmpbuf) {
8970 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8971 codec_mm_dma_flush(tmpbuf,
8972 V_BUF_ADDR_OFFSET,
8973 DMA_TO_DEVICE);
8974 } else {
8975 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8976 V_BUF_ADDR_OFFSET);
8977 if (tmpbuf) {
8978 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8979 codec_mm_dma_flush(tmpbuf,
8980 V_BUF_ADDR_OFFSET,
8981 DMA_TO_DEVICE);
8982 codec_mm_unmap_phyaddr(tmpbuf);
8983 }
8984 }
8985#else
8986 /*init sps/pps internal buf 64k*/
8987 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8988 + (mem_sps_base - DEF_BUF_START_ADDR));
8989 memset(tmpbuf, 0, 0x10000);
8990 dma_sync_single_for_device(amports_get_dma_device(),
8991 hw->cma_alloc_addr +
8992 (mem_sps_base - DEF_BUF_START_ADDR),
8993 0x10000, DMA_TO_DEVICE);
8994#endif
8995 }
8996 /**/
8997
8998#if 0
8999 if (NULL == hw->sei_data_buffer) {
9000 hw->sei_data_buffer =
9001 dma_alloc_coherent(amports_get_dma_device(),
9002 USER_DATA_SIZE,
9003 &hw->sei_data_buffer_phys, GFP_KERNEL);
9004 if (!hw->sei_data_buffer) {
9005 pr_info("%s: Can not allocate sei_data_buffer\n",
9006 __func__);
9007 ammvdec_h264_mmu_release(hw);
9008 h264_free_hw_stru(&pdev->dev, (void *)hw);
9009 return -ENOMEM;
9010 }
9011 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
9012 sei_data_buffer, sei_data_buffer_phys,
9013 (u32)sei_data_buffer_remap); */
9014 }
9015#endif
9016 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
9017 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
9018
9019 if (vdec_is_support_4k() ||
9020 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
9021 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
9022 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
9023 {
9024 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9025 }else
9026 {
9027 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9028 }
9029
9030 if (vh264_init(hw) < 0) {
9031 pr_info("\nammvdec_h264 init failed.\n");
9032 ammvdec_h264_mmu_release(hw);
9033 h264_free_hw_stru(&pdev->dev, (void *)hw);
9034 pdata->dec_status = NULL;
9035 return -ENODEV;
9036 }
9037#ifdef MH264_USERDATA_ENABLE
9038 vmh264_crate_userdata_manager(hw,
9039 hw->sei_user_data_buffer,
9040 USER_DATA_SIZE);
9041#endif
9042
9043 vdec_set_prepare_level(pdata, start_decode_buf_level);
9044 if (pdata->parallel_dec == 1) {
9045 if (hw->mmu_enable == 0)
9046 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9047 else {
9048 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9049 | CORE_MASK_COMBINE);
9050 }
9051 } else
9052 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9053 | CORE_MASK_COMBINE);
9054
9055 atomic_set(&hw->vh264_active, 1);
9056
9057 return 0;
9058}
9059
9060static int ammvdec_h264_remove(struct platform_device *pdev)
9061{
9062 struct vdec_h264_hw_s *hw =
9063 (struct vdec_h264_hw_s *)
9064 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9065 int i;
9066
9067 struct vdec_s *vdec = hw_to_vdec(hw);
9068
9069 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9070 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9071 dpb_print(DECODE_ID(hw), 0,
9072 "%s force exit %d\n", __func__, __LINE__);
9073 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9074 vdec_schedule_work(&hw->work);
9075 wait_event_interruptible_timeout(hw->wait_q,
9076 (vdec->status == VDEC_STATUS_CONNECTED),
9077 msecs_to_jiffies(1000)); /* wait for work done */
9078 }
9079
9080 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9081 release_aux_data(hw, i);
9082
9083 atomic_set(&hw->vh264_active, 0);
9084
9085 if (hw->stat & STAT_TIMER_ARM) {
9086 del_timer_sync(&hw->check_timer);
9087 hw->stat &= ~STAT_TIMER_ARM;
9088 }
9089
9090 vh264_stop(hw);
9091#ifdef MH264_USERDATA_ENABLE
9092#ifdef DUMP_USERDATA_RECORD
9093 vmh264_dump_userdata();
9094#endif
9095 vmh264_destroy_userdata_manager(hw);
9096#endif
9097 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9098
9099 atomic_set(&hw->vh264_active, 0);
9100 if (vdec->parallel_dec == 1) {
9101 if (hw->mmu_enable == 0)
9102 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9103 else
9104 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9105 CORE_MASK_COMBINE);
9106 } else
9107 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9108
9109 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9110 if (vdec->parallel_dec == 1) {
9111 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9112 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9113 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9114 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9115 if (IS_VDEC_DW(hw)) {
9116 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9117 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9118 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9119 }
9120 }
9121 }
9122
9123 ammvdec_h264_mmu_release(hw);
9124 h264_free_hw_stru(&pdev->dev, (void *)hw);
9125 clk_adj_frame_count = 0;
9126
9127 return 0;
9128}
9129
9130/****************************************/
9131#ifdef CONFIG_PM
9132static int mh264_suspend(struct device *dev)
9133{
9134 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9135 return 0;
9136}
9137
9138static int mh264_resume(struct device *dev)
9139{
9140 amvdec_resume(to_platform_device(dev));
9141 return 0;
9142}
9143
9144static const struct dev_pm_ops mh264_pm_ops = {
9145 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9146};
9147#endif
9148
9149static struct platform_driver ammvdec_h264_driver = {
9150 .probe = ammvdec_h264_probe,
9151 .remove = ammvdec_h264_remove,
9152 .driver = {
9153 .name = DRIVER_NAME,
9154#ifdef CONFIG_PM
9155 .pm = &mh264_pm_ops,
9156#endif
9157 }
9158};
9159
9160static struct codec_profile_t ammvdec_h264_profile = {
9161 .name = "mh264",
9162 .profile = ""
9163};
9164
9165static struct mconfig hm264_configs[] = {
9166 MC_PU32("h264_debug_flag", &h264_debug_flag),
9167 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9168 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9169 MC_PU32("decode_timeout_val", &decode_timeout_val),
9170 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9171 MC_PU32("reference_buf_margin", &reference_buf_margin),
9172 MC_PU32("radr", &radr),
9173 MC_PU32("rval", &rval),
9174 MC_PU32("h264_debug_mask", &h264_debug_mask),
9175 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9176 MC_PI32("force_rate_streambase", &force_rate_streambase),
9177 MC_PI32("dec_control", &dec_control),
9178 MC_PI32("force_rate_framebase", &force_rate_framebase),
9179 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9180 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9181 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9182#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9183 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9184 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9185 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9186#endif
9187 MC_PU32("i_only_flag", &i_only_flag),
9188 MC_PU32("force_rate_streambase", &force_rate_streambase),
9189};
9190static struct mconfig_node hm264_node;
9191
9192
9193static int __init ammvdec_h264_driver_init_module(void)
9194{
9195 pr_info("ammvdec_h264 module init\n");
9196 if (platform_driver_register(&ammvdec_h264_driver)) {
9197 pr_info("failed to register ammvdec_h264 driver\n");
9198 return -ENODEV;
9199 }
9200
9201 if (vdec_is_support_4k()) {
9202 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9203 ammvdec_h264_profile.profile =
9204 "4k, dwrite, compressed";
9205 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9206 ammvdec_h264_profile.profile = "4k";
9207 }
9208 }
9209
9210 vcodec_profile_register(&ammvdec_h264_profile);
9211 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9212 "mh264", hm264_configs, CONFIG_FOR_RW);
9213 return 0;
9214}
9215
9216static void __exit ammvdec_h264_driver_remove_module(void)
9217{
9218 pr_info("ammvdec_h264 module remove.\n");
9219
9220 platform_driver_unregister(&ammvdec_h264_driver);
9221}
9222
9223/****************************************/
9224module_param(h264_debug_flag, uint, 0664);
9225MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9226
9227module_param(start_decode_buf_level, int, 0664);
9228MODULE_PARM_DESC(start_decode_buf_level,
9229 "\n ammvdec_h264 start_decode_buf_level\n");
9230
9231module_param(pre_decode_buf_level, int, 0664);
9232MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9233
9234module_param(fixed_frame_rate_mode, uint, 0664);
9235MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9236
9237module_param(decode_timeout_val, uint, 0664);
9238MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9239
9240module_param(errordata_timeout_val, uint, 0664);
9241MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9242
9243module_param(get_data_timeout_val, uint, 0664);
9244MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9245
9246module_param(frame_max_data_packet, uint, 0664);
9247MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9248
9249module_param(reorder_dpb_size_margin, uint, 0664);
9250MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9251
9252#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9253module_param(reorder_dpb_size_margin_dv, uint, 0664);
9254MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9255 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9256#endif
9257
9258module_param(reference_buf_margin, uint, 0664);
9259MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9260
9261#ifdef CONSTRAIN_MAX_BUF_NUM
9262module_param(run_ready_max_vf_only_num, uint, 0664);
9263MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9264
9265module_param(run_ready_display_q_num, uint, 0664);
9266MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9267
9268module_param(run_ready_max_buf_num, uint, 0664);
9269MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9270#endif
9271
9272module_param(radr, uint, 0664);
9273MODULE_PARM_DESC(radr, "\nradr\n");
9274
9275module_param(rval, uint, 0664);
9276MODULE_PARM_DESC(rval, "\nrval\n");
9277
9278module_param(h264_debug_mask, uint, 0664);
9279MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9280
9281module_param(h264_debug_cmd, uint, 0664);
9282MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9283
9284module_param(force_rate_streambase, int, 0664);
9285MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9286
9287module_param(dec_control, int, 0664);
9288MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9289
9290module_param(force_rate_framebase, int, 0664);
9291MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9292
9293module_param(force_disp_bufspec_num, int, 0664);
9294MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9295
9296module_param(V_BUF_ADDR_OFFSET, int, 0664);
9297MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9298
9299module_param(prefix_aux_buf_size, uint, 0664);
9300MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9301
9302module_param(suffix_aux_buf_size, uint, 0664);
9303MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9304
9305#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9306module_param(dv_toggle_prov_name, uint, 0664);
9307MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9308
9309module_param(dolby_meta_with_el, uint, 0664);
9310MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9311
9312#endif
9313
9314module_param(fast_output_enable, uint, 0664);
9315MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9316
9317module_param(error_proc_policy, uint, 0664);
9318MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9319
9320module_param(error_skip_count, uint, 0664);
9321MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9322
9323module_param(force_sliding_margin, uint, 0664);
9324MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9325
9326module_param(i_only_flag, uint, 0664);
9327MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9328
9329module_param(first_i_policy, uint, 0664);
9330MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9331
9332module_param(frmbase_cont_bitlevel, uint, 0664);
9333MODULE_PARM_DESC(frmbase_cont_bitlevel,
9334 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9335
9336module_param(frmbase_cont_bitlevel2, uint, 0664);
9337MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9338 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9339
9340module_param(udebug_flag, uint, 0664);
9341MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9342
9343module_param(udebug_pause_pos, uint, 0664);
9344MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9345
9346module_param(udebug_pause_val, uint, 0664);
9347MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9348
9349module_param(udebug_pause_decode_idx, uint, 0664);
9350MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9351
9352module_param(max_alloc_buf_count, uint, 0664);
9353MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9354
9355module_param(enable_itu_t35, uint, 0664);
9356MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9357
9358module_param(endian, uint, 0664);
9359MODULE_PARM_DESC(endian, "\nrval\n");
9360
9361module_param(mmu_enable, uint, 0664);
9362MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9363
9364module_param(force_enable_mmu, uint, 0664);
9365MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9366
9367module_param(again_threshold, uint, 0664);
9368MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9369
9370module_param(stream_mode_start_num, uint, 0664);
9371MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9372
9373/*
9374module_param(trigger_task, uint, 0664);
9375MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9376*/
9377module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9378
9379module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9380
9381module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9382
9383module_param_array(run_count, uint,
9384 &max_decode_instance_num, 0664);
9385
9386module_param_array(not_run_ready, uint,
9387 &max_decode_instance_num, 0664);
9388
9389module_param_array(input_empty, uint,
9390 &max_decode_instance_num, 0664);
9391
9392module_param_array(max_get_frame_interval, uint,
9393 &max_decode_instance_num, 0664);
9394
9395module_param_array(step, uint, &max_decode_instance_num, 0664);
9396
9397module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9398
9399module_param(disp_vframe_valve_level, uint, 0664);
9400MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9401
9402module_param(double_write_mode, uint, 0664);
9403MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9404
9405module_param(mem_map_mode, uint, 0664);
9406MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9407
9408module_param(without_display_mode, uint, 0664);
9409MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9410
9411
9412module_init(ammvdec_h264_driver_init_module);
9413module_exit(ammvdec_h264_driver_remove_module);
9414
9415MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9416MODULE_LICENSE("GPL");
9417
generated by cgit at 2024-05-17 07:19:58 (GMT)