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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
blob: 38321bb4bd0272fd032fade0e54d90d773d4a1f9
1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120#define INVALID_IDX -1 /* Invalid buffer index.*/
121
122static int mmu_enable;
123/*mmu do not support mbaff*/
124static int force_enable_mmu = 0;
125unsigned int h264_debug_flag; /* 0xa0000000; */
126unsigned int h264_debug_mask = 0xff;
127 /*
128 *h264_debug_cmd:
129 * 0x1xx, force decoder id of xx to be disconnected
130 */
131unsigned int h264_debug_cmd;
132
133static unsigned int dec_control =
134 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
135 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
136
137static unsigned int force_rate_streambase;
138static unsigned int force_rate_framebase;
139static unsigned int force_disp_bufspec_num;
140static unsigned int fixed_frame_rate_mode;
141static unsigned int error_recovery_mode_in;
142static int start_decode_buf_level = 0x4000;
143static int pre_decode_buf_level = 0x1000;
144static int stream_mode_start_num = 4;
145
146#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
147/*to make reorder size difference of bl and el not too big*/
148static unsigned int reorder_dpb_size_margin_dv = 16;
149#endif
150static unsigned int reorder_dpb_size_margin = 6;
151static unsigned int reference_buf_margin = 4;
152
153#ifdef CONSTRAIN_MAX_BUF_NUM
154static u32 run_ready_max_vf_only_num;
155static u32 run_ready_display_q_num;
156 /*0: not check
157 0xff: mDPB.size
158 */
159static u32 run_ready_max_buf_num = 0xff;
160#endif
161
162#define VDEC_ASSIST_CANVAS_BLK32 0x5
163
164
165static unsigned int max_alloc_buf_count;
166static unsigned int decode_timeout_val = 100;
167static unsigned int errordata_timeout_val = 50;
168static unsigned int get_data_timeout_val = 2000;
169#if 1
170/* H264_DATA_REQUEST does not work, disable it,
171decode has error for data in none continuous address
172*/
173static unsigned int frame_max_data_packet;
174#else
175static unsigned int frame_max_data_packet = 8;
176#endif
177static unsigned int radr;
178static unsigned int rval;
179static u32 endian = 0xff0;
180
181/*
182 udebug_flag:
183 bit 0, enable ucode print
184 bit 1, enable ucode detail print
185 bit 3, disable ucode watchdog
186 bit [31:16] not 0, pos to dump lmem
187 bit 2, pop bits to lmem
188 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
189*/
190static u32 udebug_flag;
191/*
192 when udebug_flag[1:0] is not 0
193 udebug_pause_pos not 0,
194 pause position
195*/
196static u32 udebug_pause_pos;
197/*
198 when udebug_flag[1:0] is not 0
199 and udebug_pause_pos is not 0,
200 pause only when DEBUG_REG2 is equal to this val
201*/
202static u32 udebug_pause_val;
203
204static u32 udebug_pause_decode_idx;
205
206static unsigned int disp_vframe_valve_level;
207
208static unsigned int max_decode_instance_num = H264_DEV_NUM;
209static unsigned int decode_frame_count[H264_DEV_NUM];
210static unsigned int display_frame_count[H264_DEV_NUM];
211static unsigned int max_process_time[H264_DEV_NUM];
212static unsigned int max_get_frame_interval[H264_DEV_NUM];
213static unsigned int run_count[H264_DEV_NUM];
214static unsigned int input_empty[H264_DEV_NUM];
215static unsigned int not_run_ready[H264_DEV_NUM];
216static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
217{1, 1, 1, 1, 1, 1, 1, 1, 1};
218
219#define VDEC_CLOCK_ADJUST_FRAME 30
220static unsigned int clk_adj_frame_count;
221
222/*
223 *bit[3:0]: 0, run ; 1, pause; 3, step
224 *bit[4]: 1, schedule run
225 */
226static unsigned int step[H264_DEV_NUM];
227
228#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
229static u32 prefix_aux_buf_size = (16 * 1024);
230static u32 suffix_aux_buf_size;
231
232#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
233static u32 dv_toggle_prov_name;
234
235static u32 dolby_meta_with_el;
236#endif
237
238/*
239 bit[8]
240 0: use sys_info[bit 3]
241 not 0:use i_only_flag[7:0]
242 bit[7:0]:
243 bit 0, 1: only display I picture;
244 bit 1, 1: only decode I picture;
245*/
246static unsigned int i_only_flag;
247
248/*
249 error_proc_policy:
250 bit[0] send_error_frame_flag;
251 (valid when bit[31] is 1, otherwise use sysinfo)
252 bit[1] do not decode if config_decode_buf() fail
253 bit[2] force release buf if in deadlock
254 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
255 bit[4] check inactive of receiver
256 bit[5] reset buffmgr if in deadlock
257 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
258 bit[7] reset buffmgr if dpb error
259
260 bit[8] check total mbx/mby of decoded frame
261 bit[9] check ERROR_STATUS_REG
262 bit[10] check reference list
263 bit[11] mark error if dpb error
264 bit[12] i_only when error happen
265 bit[13] 0: mark error according to last pic, 1: ignore mark error
266 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
267*/
268static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
269
270
271/*
272 error_skip_count:
273 bit[11:0] error skip frame count
274 bit[15:12] error skip i picture count
275*/
276static unsigned int error_skip_count = (0x2 << 12) | 0x40;
277
278static unsigned int force_sliding_margin;
279/*
280 bit[1:0]:
281 0, start playing from any frame
282 1, start playing from I frame
283 bit[15:8]: the count of skip frames after first I
284 2, start playing from second I frame (decode from the first I)
285 bit[15:8]: the max count of skip frames after first I
286 3, start playing from IDR
287*/
288static unsigned int first_i_policy = 1;
289
290/*
291 fast_output_enable:
292 bit [0], output frame if there is IDR in list
293 bit [1], output frame if the current poc is 1 big than the previous poc
294 bit [2], if even poc only, output frame ifthe cuurent poc
295 is 2 big than the previous poc
296 bit [3], ip only
297*/
298static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
299
300static unsigned int enable_itu_t35 = 1;
301
302static unsigned int frmbase_cont_bitlevel = 0x40;
303
304static unsigned int frmbase_cont_bitlevel2 = 0x1;
305
306
307#define MH264_USERDATA_ENABLE
308
309/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
310/* hevc->double_write_mode:
311 0, no double write
312 1, 1:1 ratio
313 2, (1/4):(1/4) ratio
314 3, (1/4):(1/4) ratio, with both compressed frame included
315 4, (1/2):(1/2) ratio
316 0x10, double write only
317 0x10000: vdec dw horizotal 1/2
318 0x20000: vdec dw horizotal/vertical 1/2
319*/
320static u32 double_write_mode;
321static u32 without_display_mode;
322#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
323
324static void vmh264_dump_state(struct vdec_s *vdec);
325
326#define is_in_parsing_state(status) \
327 ((status == H264_ACTION_SEARCH_HEAD) || \
328 ((status & 0xf0) == 0x80))
329
330#define is_interlace(frame) \
331 (frame->frame &&\
332 frame->top_field &&\
333 frame->bottom_field &&\
334 (!frame->frame->coded_frame))
335static inline bool close_to(int a, int b, int m)
336{
337 return (abs(a - b) < m) ? true : false;
338}
339
340#if 0
341#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
342#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
343#else
344#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
345#define h264_free_hw_stru(dev, hw) vfree(hw)
346#endif
347
348/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
349#define NV21
350/* #endif */
351
352/* 12M for L41 */
353#define MAX_DPB_BUFF_SIZE (12*1024*1024)
354#define DEFAULT_MEM_SIZE (32*1024*1024)
355#define AVIL_DPB_BUFF_SIZE 0x01ec2000
356
357#define DEF_BUF_START_ADDR 0x01000000
358#define mem_sps_base 0x011c3c00
359#define mem_pps_base 0x011cbc00
360/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
361u32 V_BUF_ADDR_OFFSET = 0x200000;
362#define DCAC_READ_MARGIN (64 * 1024)
363
364
365#define EXTEND_SAR 0xff
366#define BUFSPEC_POOL_SIZE 64
367#define VF_POOL_SIZE 64
368#define VF_POOL_NUM 2
369#define MAX_VF_BUF_NUM 27
370#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
371#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
372#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
373#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
374#define EXTIF_BUF_SIZE (0x10000 * 2)
375
376#define HEADER_BUFFER_IDX(n) (n)
377#define VF_BUFFER_IDX(n) (n)
378
379
380#define PUT_INTERVAL (HZ/100)
381#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
382
383#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
384#define SWITCHING_STATE_OFF 0
385#define SWITCHING_STATE_ON_CMD3 1
386#define SWITCHING_STATE_ON_CMD1 2
387
388
389
390#define INCPTR(p) ptr_atomic_wrap_inc(&p)
391
392#define SLICE_TYPE_I 2
393#define SLICE_TYPE_P 5
394#define SLICE_TYPE_B 6
395
396struct buffer_spec_s {
397 /*
398 used:
399 -1, none allocated
400 0, allocated, free
401 1, used by dpb
402 2, in disp queue;
403 3, in disp queue, isolated,
404 do not use for dpb when vf_put;
405 4, to release
406 5, in disp queue, isolated (but not to release)
407 do not use for dpb when vf_put;
408 */
409 unsigned int used;
410 unsigned int info0;
411 unsigned int info1;
412 unsigned int info2;
413 unsigned int y_addr;
414 unsigned int u_addr;
415 unsigned int v_addr;
416
417 int y_canvas_index;
418 int u_canvas_index;
419 int v_canvas_index;
420
421#ifdef VDEC_DW
422 unsigned int vdec_dw_y_addr;
423 unsigned int vdec_dw_u_addr;
424 unsigned int vdec_dw_v_addr;
425
426 int vdec_dw_y_canvas_index;
427 int vdec_dw_u_canvas_index;
428 int vdec_dw_v_canvas_index;
429#ifdef NV21
430 struct canvas_config_s vdec_dw_canvas_config[2];
431#else
432 struct canvas_config_s vdec_dw_canvas_config[3];
433#endif
434#endif
435
436#ifdef NV21
437 struct canvas_config_s canvas_config[2];
438#else
439 struct canvas_config_s canvas_config[3];
440#endif
441 unsigned long cma_alloc_addr;
442 unsigned int buf_adr;
443#ifdef H264_MMU
444 unsigned long alloc_header_addr;
445#endif
446 char *aux_data_buf;
447 int aux_data_size;
448#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
449 unsigned char dv_enhance_exist;
450#endif
451 int canvas_pos;
452 int vf_ref;
453 /*unsigned int comp_body_size;*/
454 unsigned int dw_y_adr;
455 unsigned int dw_u_v_adr;
456};
457
458#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
459#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
460#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
461
462
463#define vdec_dw_spec2canvas(x) \
464 (((x)->vdec_dw_v_canvas_index << 16) | \
465 ((x)->vdec_dw_u_canvas_index << 8) | \
466 ((x)->vdec_dw_y_canvas_index << 0))
467
468
469#define spec2canvas(x) \
470 (((x)->v_canvas_index << 16) | \
471 ((x)->u_canvas_index << 8) | \
472 ((x)->y_canvas_index << 0))
473
474#define FRAME_INDEX(vf_index) (vf_index & 0xff)
475#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
476#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
477
478static struct vframe_s *vh264_vf_peek(void *);
479static struct vframe_s *vh264_vf_get(void *);
480static void vh264_vf_put(struct vframe_s *, void *);
481static int vh264_vf_states(struct vframe_states *states, void *);
482static int vh264_event_cb(int type, void *data, void *private_data);
483static void vh264_work(struct work_struct *work);
484static void vh264_timeout_work(struct work_struct *work);
485static void vh264_notify_work(struct work_struct *work);
486#ifdef MH264_USERDATA_ENABLE
487static void user_data_ready_notify_work(struct work_struct *work);
488static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
489#endif
490
491static const char vh264_dec_id[] = "vh264-dev";
492
493#define PROVIDER_NAME "vdec.h264"
494
495static const struct vframe_operations_s vf_provider_ops = {
496 .peek = vh264_vf_peek,
497 .get = vh264_vf_get,
498 .put = vh264_vf_put,
499 .event_cb = vh264_event_cb,
500 .vf_states = vh264_vf_states,
501};
502
503#define DEC_RESULT_NONE 0
504#define DEC_RESULT_DONE 1
505#define DEC_RESULT_AGAIN 2
506#define DEC_RESULT_CONFIG_PARAM 3
507#define DEC_RESULT_GET_DATA 4
508#define DEC_RESULT_GET_DATA_RETRY 5
509#define DEC_RESULT_ERROR 6
510#define DEC_RESULT_EOS 7
511#define DEC_RESULT_FORCE_EXIT 8
512
513/*
514 *static const char *dec_result_str[] = {
515 * "DEC_RESULT_NONE ",
516 * "DEC_RESULT_DONE ",
517 * "DEC_RESULT_AGAIN ",
518 * "DEC_RESULT_CONFIG_PARAM",
519 * "DEC_RESULT_GET_DATA ",
520 * "DEC_RESULT_GET_DA_RETRY",
521 * "DEC_RESULT_ERROR ",
522 *};
523 */
524
525#define UCODE_IP_ONLY 2
526#define UCODE_IP_ONLY_PARAM 1
527
528#define MC_OFFSET_HEADER 0x0000
529#define MC_OFFSET_DATA 0x1000
530#define MC_OFFSET_MMCO 0x2000
531#define MC_OFFSET_LIST 0x3000
532#define MC_OFFSET_SLICE 0x4000
533#define MC_OFFSET_MAIN 0x5000
534
535#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
536#define MC_SWAP_SIZE (4*SZ_1K)
537#define MODE_ERROR 0
538#define MODE_FULL 1
539
540#define DFS_HIGH_THEASHOLD 3
541
542#define INIT_FLAG_REG AV_SCRATCH_2
543#define HEAD_PADING_REG AV_SCRATCH_3
544#define UCODE_WATCHDOG_REG AV_SCRATCH_7
545#define LMEM_DUMP_ADR AV_SCRATCH_L
546#define DEBUG_REG1 AV_SCRATCH_M
547#define DEBUG_REG2 AV_SCRATCH_N
548#define FRAME_COUNTER_REG AV_SCRATCH_I
549#define RPM_CMD_REG AV_SCRATCH_A
550#define H264_DECODE_SIZE AV_SCRATCH_E
551#define H264_DECODE_MODE AV_SCRATCH_4
552#define H264_DECODE_SEQINFO AV_SCRATCH_5
553#define H264_AUX_ADR AV_SCRATCH_C
554#define H264_AUX_DATA_SIZE AV_SCRATCH_H
555
556#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
557#define DPB_STATUS_REG AV_SCRATCH_J
558#define ERROR_STATUS_REG AV_SCRATCH_9
559 /*
560 NAL_SEARCH_CTL: bit 0, enable itu_t35
561 NAL_SEARCH_CTL: bit 1, enable mmu
562 */
563#define NAL_SEARCH_CTL AV_SCRATCH_9
564#define MBY_MBX MB_MOTION_MODE /*0xc07*/
565
566#define DECODE_MODE_SINGLE 0x0
567#define DECODE_MODE_MULTI_FRAMEBASE 0x1
568#define DECODE_MODE_MULTI_STREAMBASE 0x2
569#define DECODE_MODE_MULTI_DVBAL 0x3
570#define DECODE_MODE_MULTI_DVENL 0x4
571static DEFINE_MUTEX(vmh264_mutex);
572
573
574
575#ifdef MH264_USERDATA_ENABLE
576
577struct mh264_userdata_record_t {
578 struct userdata_meta_info_t meta_info;
579 u32 rec_start;
580 u32 rec_len;
581};
582
583struct mh264_ud_record_wait_node_t {
584 struct list_head list;
585 struct mh264_userdata_record_t ud_record;
586};
587#define USERDATA_FIFO_NUM 256
588#define MAX_FREE_USERDATA_NODES 5
589
590struct mh264_userdata_info_t {
591 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
592 u8 *data_buf;
593 u8 *data_buf_end;
594 u32 buf_len;
595 u32 read_index;
596 u32 write_index;
597 u32 last_wp;
598};
599
600
601#endif
602
603struct vdec_h264_hw_s {
604 spinlock_t lock;
605 spinlock_t bufspec_lock;
606 int id;
607 struct platform_device *platform_dev;
608 unsigned long cma_alloc_addr;
609 /* struct page *collocate_cma_alloc_pages; */
610 unsigned long collocate_cma_alloc_addr;
611
612 u32 prefix_aux_size;
613 u32 suffix_aux_size;
614 void *aux_addr;
615 dma_addr_t aux_phy_addr;
616
617 /* buffer for store all sei data */
618 void *sei_data_buf;
619 u32 sei_data_len;
620
621 /* buffer for storing one itu35 recored */
622 void *sei_itu_data_buf;
623 u32 sei_itu_data_len;
624
625 /* recycle buffer for user data storing all itu35 records */
626 void *sei_user_data_buffer;
627 u32 sei_user_data_wp;
628#ifdef MH264_USERDATA_ENABLE
629 struct work_struct user_data_ready_work;
630#endif
631 struct StorablePicture *last_dec_picture;
632
633 ulong lmem_addr;
634 dma_addr_t lmem_addr_remap;
635
636 void *bmmu_box;
637#ifdef H264_MMU
638 void *mmu_box;
639 void *frame_mmu_map_addr;
640 dma_addr_t frame_mmu_map_phy_addr;
641 u32 hevc_cur_buf_idx;
642 u32 losless_comp_body_size;
643 u32 losless_comp_body_size_sao;
644 u32 losless_comp_header_size;
645 u32 mc_buffer_size_u_v;
646 u32 mc_buffer_size_u_v_h;
647 u32 is_idr_frame;
648 u32 is_new_pic;
649 u32 frame_done;
650 u32 frame_busy;
651 unsigned long extif_addr;
652 int double_write_mode;
653 int mmu_enable;
654#endif
655
656 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
657 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
658
659 int cur_pool;
660 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
661 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
662 struct vframe_s switching_fense_vf;
663 struct h264_dpb_stru dpb;
664 u8 init_flag;
665 u8 first_sc_checked;
666 u8 has_i_frame;
667 u8 config_bufmgr_done;
668 u32 max_reference_size;
669 u32 decode_pic_count;
670 u32 reflist_error_count;
671 int start_search_pos;
672 u32 reg_iqidct_control;
673 u32 reg_vcop_ctrl_reg;
674 u32 reg_rv_ai_mb_count;
675 u32 vld_dec_control;
676 struct vframe_s vframe_dummy;
677
678 unsigned char buffer_empty_flag;
679
680 u32 frame_width;
681 u32 frame_height;
682 u32 frame_dur;
683 u32 frame_prog;
684 u32 frame_packing_type;
685
686 struct vframe_chunk_s *chunk;
687
688 u32 stat;
689 unsigned long buf_start;
690 u32 buf_offset;
691 u32 buf_size;
692 /* u32 ucode_map_start; */
693 u32 pts_outside;
694 u32 sync_outside;
695 u32 vh264_ratio;
696 u32 vh264_rotation;
697 u32 use_idr_framerate;
698
699 u32 seq_info;
700 u32 seq_info2;
701 u32 video_signal_from_vui; /*to do .. */
702 u32 timing_info_present_flag;
703 u32 fixed_frame_rate_flag;
704 u32 bitstream_restriction_flag;
705 u32 num_reorder_frames;
706 u32 max_dec_frame_buffering;
707 u32 iframe_count;
708 u32 aspect_ratio_info;
709 u32 num_units_in_tick;
710 u32 time_scale;
711 u32 h264_ar;
712 bool h264_first_valid_pts_ready;
713 u32 h264pts1;
714 u32 h264pts2;
715 u32 pts_duration;
716 u32 h264_pts_count;
717 u32 duration_from_pts_done;
718 u32 pts_unstable;
719 u32 unstable_pts;
720 u32 last_checkout_pts;
721 u32 max_refer_buf;
722
723 s32 vh264_stream_switching_state;
724 struct vframe_s *p_last_vf;
725 u32 last_pts;
726 u32 last_pts_remainder;
727 u32 last_duration;
728 u32 last_mb_width, last_mb_height;
729 bool check_pts_discontinue;
730 bool pts_discontinue;
731 u32 wait_buffer_counter;
732 u32 first_offset;
733 u32 first_pts;
734 u64 first_pts64;
735 bool first_pts_cached;
736 u64 last_pts64;
737#if 0
738 void *sei_data_buffer;
739 dma_addr_t sei_data_buffer_phys;
740#endif
741
742 uint error_recovery_mode;
743 uint mb_total;
744 uint mb_width;
745 uint mb_height;
746
747 uint i_only;
748 int skip_frame_count;
749 bool no_poc_reorder_flag;
750 bool send_error_frame_flag;
751 dma_addr_t mc_dma_handle;
752 void *mc_cpu_addr;
753 int vh264_reset;
754
755 atomic_t vh264_active;
756
757 struct dec_sysinfo vh264_amstream_dec_info;
758
759 int dec_result;
760 struct work_struct work;
761 struct work_struct notify_work;
762 struct work_struct timeout_work;
763 void (*vdec_cb)(struct vdec_s *, void *);
764 void *vdec_cb_arg;
765
766 struct timer_list check_timer;
767
768 /**/
769 unsigned int last_frame_time;
770 u32 vf_pre_count;
771 u32 vf_get_count;
772 u32 vf_put_count;
773
774 /* timeout handle */
775 unsigned long int start_process_time;
776 unsigned int last_mby_mbx;
777 unsigned int last_vld_level;
778 unsigned int decode_timeout_count;
779 unsigned int timeout_num;
780 unsigned int search_dataempty_num;
781 unsigned int decode_timeout_num;
782 unsigned int decode_dataempty_num;
783 unsigned int buffer_empty_recover_num;
784
785 unsigned get_data_count;
786 unsigned get_data_start_time;
787 /**/
788
789 /*log*/
790 unsigned int packet_write_success_count;
791 unsigned int packet_write_EAGAIN_count;
792 unsigned int packet_write_ENOMEM_count;
793 unsigned int packet_write_EFAULT_count;
794 unsigned int total_read_size_pre;
795 unsigned int total_read_size;
796 unsigned int frame_count_pre;
797#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
798 u8 switch_dvlayer_flag;
799 u8 got_valid_nal;
800#endif
801 u8 eos;
802 u8 data_flag;
803 u32 no_error_count;
804 u32 no_error_i_count;
805 /*
806 NODISP_FLAG
807 */
808 u8 dec_flag;
809
810 u32 ucode_pause_pos;
811
812 u8 reset_bufmgr_flag;
813 u32 reset_bufmgr_count;
814 u32 cfg_param1;
815 u32 cfg_param2;
816 u32 cfg_param3;
817 u32 cfg_param4;
818 int valve_count;
819 u8 next_again_flag;
820 u32 pre_parser_wr_ptr;
821 struct firmware_s *fw;
822 struct firmware_s *fw_mmu;
823#ifdef MH264_USERDATA_ENABLE
824 /*user data*/
825 struct mutex userdata_mutex;
826 struct mh264_userdata_info_t userdata_info;
827 struct mh264_userdata_record_t ud_record;
828 int wait_for_udr_send;
829#endif
830 u32 no_mem_count;
831 u32 canvas_mode;
832 bool is_used_v4l;
833 void *v4l2_ctx;
834 bool v4l_params_parsed;
835 wait_queue_head_t wait_q;
836 u32 reg_g_status;
837 struct mutex chunks_mutex;
838 int need_cache_size;
839 u64 sc_start_time;
840 u8 frmbase_cont_flag;
841 struct vframe_qos_s vframe_qos;
842 int frameinfo_enable;
843 bool first_head_check_flag;
844 unsigned int height_aspect_ratio;
845 unsigned int width_aspect_ratio;
846 bool new_iframe_flag;
847 bool ref_err_flush_dpb_flag;
848 unsigned int first_i_policy;
849 u32 reorder_dpb_size_margin;
850};
851
852static u32 again_threshold;
853
854static void timeout_process(struct vdec_h264_hw_s *hw);
855static void dump_bufspec(struct vdec_h264_hw_s *hw,
856 const char *caller);
857static void h264_reconfig(struct vdec_h264_hw_s *hw);
858static void h264_reset_bufmgr(struct vdec_s *vdec);
859static void vh264_local_init(struct vdec_h264_hw_s *hw);
860static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
861static int vh264_stop(struct vdec_h264_hw_s *hw);
862static s32 vh264_init(struct vdec_h264_hw_s *hw);
863static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
864 u32 index);
865static void release_aux_data(struct vdec_h264_hw_s *hw,
866 int buf_spec_num);
867#ifdef ERROR_HANDLE_TEST
868static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
869#endif
870
871#define H265_PUT_SAO_4K_SET 0x03
872#define H265_ABORT_SAO_4K_SET 0x04
873#define H265_ABORT_SAO_4K_SET_DONE 0x05
874
875#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
876#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
877#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
878#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
879#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
880
881
882#define HEVC_CM_HEADER_START_ADDR 0x3628
883#define HEVC_CM_BODY_START_ADDR 0x3626
884#define HEVC_CM_BODY_LENGTH 0x3627
885#define HEVC_CM_HEADER_LENGTH 0x3629
886#define HEVC_CM_HEADER_OFFSET 0x362b
887#define HEVC_SAO_CTRL9 0x362d
888#define HEVCD_MPP_DECOMP_CTL3 0x34c4
889#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
890#define HEVC_DBLK_CFGB 0x350b
891#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
892
893#define H265_DW_NO_SCALE
894#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
895#define H265_LOSLESS_COMPRESS_MODE
896#define MAX_FRAME_4K_NUM 0x1200
897#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
898
899/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
900static u32 mem_map_mode = H265_MEM_MAP_MODE;
901
902#define MAX_SIZE_8K (8192 * 4608)
903#define MAX_SIZE_4K (4096 * 2304)
904
905static int is_oversize(int w, int h)
906{
907 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
908 MAX_SIZE_8K : MAX_SIZE_4K;
909
910 if (w < 0 || h < 0)
911 return true;
912
913 if (h != 0 && (w > max / h))
914 return true;
915
916 return false;
917}
918
919static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
920 int frame_type,
921 u32 vpts,
922 u32 vpts_valid);
923static int compute_losless_comp_body_size(int width,
924 int height, int bit_depth_10);
925static int compute_losless_comp_header_size(int width, int height);
926
927static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
928 int pic_width, int pic_height, u16 bit_depth,
929 unsigned int *mmu_index_adr) {
930 int cur_buf_idx;
931 int bit_depth_10 = (bit_depth != 0x00);
932 int picture_size;
933 u32 cur_mmu_4k_number;
934
935 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
936 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
937 picture_size = compute_losless_comp_body_size(pic_width,
938 pic_height, bit_depth_10);
939 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
940 dpb_print(DECODE_ID(hw),
941 PRINT_FLAG_MMU_DETAIL,
942 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
943 cur_buf_idx, picture_size, cur_mmu_4k_number);
944
945 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
946 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
947 cur_mmu_4k_number);
948 return -1;
949 }
950
951 return decoder_mmu_box_alloc_idx(
952 hw->mmu_box,
953 cur_buf_idx,
954 cur_mmu_4k_number,
955 mmu_index_adr);
956}
957
958static int compute_losless_comp_body_size(int width,
959 int height, int bit_depth_10)
960{
961 int width_x64;
962 int height_x32;
963 int bsize;
964
965 width_x64 = width + 63;
966 width_x64 >>= 6;
967
968 height_x32 = height + 31;
969 height_x32 >>= 5;
970
971#ifdef H264_MMU
972 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
973#else
974 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
975#endif
976 return bsize;
977}
978
979static int compute_losless_comp_header_size(int width, int height)
980{
981 int width_x64;
982 int width_x128;
983 int height_x64;
984 int hsize;
985
986 width_x64 = width + 63;
987 width_x64 >>= 6;
988
989 width_x128 = width + 127;
990 width_x128 >>= 7;
991
992 height_x64 = height + 63;
993 height_x64 >>= 6;
994
995#ifdef H264_MMU
996 hsize = 128*width_x64*height_x64;
997#else
998 hsize = 32*width_x128*height_x64;
999#endif
1000 return hsize;
1001}
1002
1003static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1004{
1005 int ratio = 1;
1006 int dw_mode = hw->double_write_mode;
1007 if ((dw_mode == 2) ||
1008 (dw_mode == 3))
1009 ratio = 4;
1010 else if (dw_mode == 4)
1011 ratio = 2;
1012 return ratio;
1013}
1014
1015
1016static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1017{
1018 int pic_width, pic_height;
1019 int lcu_size = 16;
1020 int dw_buf_size;
1021 u32 dw_buffer_size_u_v;
1022 u32 dw_buffer_size_u_v_h;
1023 int dw_mode = hw->double_write_mode;
1024
1025 pic_width = hw->frame_width;
1026 pic_height = hw->frame_height;
1027
1028 if (dw_mode) {
1029 int pic_width_dw = pic_width /
1030 get_double_write_ratio(hw);
1031 int pic_height_dw = pic_height /
1032 get_double_write_ratio(hw);
1033
1034 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1035 pic_width_dw / lcu_size + 1 :
1036 pic_width_dw / lcu_size;
1037 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1038 pic_height_dw / lcu_size + 1 :
1039 pic_height_dw / lcu_size;
1040 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1041
1042
1043 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1044 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1045 /*64k alignment*/
1046 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1047 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1048 } else {
1049 *pdw_buffer_size_u_v_h = 0;
1050 dw_buf_size = 0;
1051 }
1052
1053 return dw_buf_size;
1054}
1055
1056
1057static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1058{
1059 int i, size;
1060 u32 canvas_addr;
1061 unsigned long maddr;
1062 int num_buff = hw->dpb.mDPB.size;
1063 int dw_size = 0;
1064 u32 dw_buffer_size_u_v_h;
1065 u32 blkmode = mem_map_mode;
1066 int dw_mode = hw->double_write_mode;
1067
1068 canvas_addr = ANC0_CANVAS_ADDR;
1069 for (i = 0; i < num_buff; i++)
1070 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1071
1072 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1073 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1074
1075
1076 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1077 size += dw_size;
1078 if (size > 0)
1079 size += 0x10000;
1080
1081 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1082 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1083 dw_buffer_size_u_v_h, dw_size, size);
1084
1085 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1086 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1087 hw->losless_comp_body_size,
1088 hw->losless_comp_header_size,
1089 hw->losless_comp_body_size_sao);
1090
1091 for (i = 0; i < num_buff; i++) {
1092 if (!restore) {
1093 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1094 HEADER_BUFFER_IDX(i), size,
1095 DRIVER_HEADER_NAME, &maddr) < 0) {
1096 dpb_print(DECODE_ID(hw), 0,
1097 "%s malloc compress header failed %d\n",
1098 DRIVER_HEADER_NAME, i);
1099 return;
1100 }
1101 } else
1102 maddr = hw->buffer_spec[i].alloc_header_addr;
1103 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1104 hw->buffer_spec[i].alloc_header_addr = maddr;
1105 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1106 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1107 __func__, i, (u32)maddr, size);
1108
1109 if (dw_mode) {
1110 u32 addr;
1111 int canvas_w;
1112 int canvas_h;
1113
1114 canvas_w = hw->frame_width /
1115 get_double_write_ratio(hw);
1116 canvas_h = hw->frame_height /
1117 get_double_write_ratio(hw);
1118
1119 if (mem_map_mode == 0)
1120 canvas_w = ALIGN(canvas_w, 32);
1121 else
1122 canvas_w = ALIGN(canvas_w, 64);
1123 canvas_h = ALIGN(canvas_h, 32);
1124
1125 hw->buffer_spec[i].dw_y_adr =
1126 maddr + hw->losless_comp_header_size;
1127
1128 hw->buffer_spec[i].dw_y_adr =
1129 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1130 << 16;
1131 hw->buffer_spec[i].dw_u_v_adr =
1132 hw->buffer_spec[i].dw_y_adr
1133 + (dw_buffer_size_u_v_h << 16) * 2;
1134
1135
1136 hw->buffer_spec[i].buf_adr
1137 = hw->buffer_spec[i].dw_y_adr;
1138 addr = hw->buffer_spec[i].buf_adr;
1139
1140
1141 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1142 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1143 hw->buffer_spec[i].dw_y_adr,
1144 hw->buffer_spec[i].dw_u_v_adr,
1145 hw->buffer_spec[i].y_addr,
1146 hw->buffer_spec[i].u_addr,
1147 hw->buffer_spec[i].v_addr,
1148 canvas_w,
1149 canvas_h);
1150
1151 hw->buffer_spec[i].canvas_config[0].phy_addr =
1152 hw->buffer_spec[i].dw_y_adr;
1153 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1154 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1155 hw->buffer_spec[i].canvas_config[0].block_mode =
1156 blkmode;
1157 hw->buffer_spec[i].canvas_config[0].endian = 7;
1158
1159 hw->buffer_spec[i].canvas_config[1].phy_addr =
1160 hw->buffer_spec[i].dw_u_v_adr;
1161 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1162 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1163 hw->buffer_spec[i].canvas_config[1].block_mode =
1164 blkmode;
1165 hw->buffer_spec[i].canvas_config[1].endian = 7;
1166 }
1167 }
1168 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1169
1170 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1171 for (i = 0; i < 32; i++)
1172 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1173 return;
1174}
1175static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1176{
1177 u32 i;
1178 u32 ref_canv;
1179 struct Slice *pSlice = &(hw->dpb.mSlice);
1180 /*REFLIST[0]*/
1181 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1182 struct StorablePicture *ref = pSlice->listX[0][i];
1183 if (ref == NULL)
1184 return;
1185 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1186 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1187 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1188 (ref->buf_spec_num & 0x3f) << 8);
1189 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1190 }
1191 /*REFLIST[1]*/
1192 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1193 struct StorablePicture *ref = pSlice->listX[1][i];
1194 if (ref == NULL)
1195 return;
1196 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1197 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1198 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1199 (ref->buf_spec_num & 0x3f) << 8);
1200 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1201 }
1202 return;
1203}
1204
1205static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1206{
1207 u32 rdata32;
1208 u32 rdata32_2;
1209 u32 slice_type;
1210 struct StorablePicture *ref;
1211 struct Slice *pSlice;
1212 slice_type = hw->dpb.mSlice.slice_type;
1213 pSlice = &(hw->dpb.mSlice);
1214 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1215 if (slice_type == I_SLICE) {
1216 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1217 return;
1218 }
1219 if (slice_type == B_SLICE) {
1220 ref = pSlice->listX[0][0];
1221 if (ref == NULL)
1222 return;
1223 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1224 ((ref->buf_spec_num & 0x3f) << 8));
1225 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1226 rdata32 = rdata32 & 0xffff;
1227 rdata32 = rdata32 | (rdata32 << 16);
1228 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1229
1230 ref = pSlice->listX[1][0];
1231 if (ref == NULL)
1232 return;
1233 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1234 ((ref->buf_spec_num & 0x3f) << 8));
1235 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1236 rdata32_2 = rdata32_2 & 0xffff;
1237 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1238 if (rdata32 == rdata32_2) {
1239 ref = pSlice->listX[1][1];
1240 if (ref == NULL)
1241 return;
1242 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1243 ((ref->buf_spec_num & 0x3f) << 8));
1244 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1245 rdata32_2 = rdata32_2 & 0xffff;
1246 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1247 }
1248 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1249 } else { /*P-PIC*/
1250 ref = pSlice->listX[0][0];
1251 if (ref == NULL)
1252 return;
1253 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1254 ((ref->buf_spec_num & 0x3f) << 8));
1255 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1256 rdata32 = rdata32 & 0xffff;
1257 rdata32 = rdata32 | (rdata32 << 16);
1258 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1259
1260 ref = pSlice->listX[0][1];
1261 if (ref == NULL)
1262 return;
1263 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1264 ((ref->buf_spec_num & 0x3f) << 8));
1265 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1266 rdata32 = rdata32 & 0xffff;
1267 rdata32 = rdata32 | (rdata32 << 16);
1268 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1269 }
1270 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1271 return;
1272}
1273
1274
1275static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1276 u32 width, u32 height) {
1277 u32 data32;
1278 u32 lcu_x_num, lcu_y_num;
1279 u32 lcu_total;
1280 u32 mc_buffer_size_u_v;
1281 u32 mc_buffer_size_u_v_h;
1282 int dw_mode = hw->double_write_mode;
1283
1284 lcu_x_num = (width + 15) >> 4;
1285 lcu_y_num = (height + 15) >> 4;
1286 lcu_total = lcu_x_num * lcu_y_num;
1287
1288 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1289 hw->mc_buffer_size_u_v_h =
1290 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1291
1292 hw->losless_comp_body_size = 0;
1293
1294 hw->losless_comp_body_size_sao =
1295 compute_losless_comp_body_size(width, height, 0);
1296 hw->losless_comp_header_size =
1297 compute_losless_comp_header_size(width, height);
1298
1299 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1300 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1301
1302 /* setup lcu_size = 16*/
1303 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1304 /*pic_width/pic_height*/
1305 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1306 (height & 0xffff) << 16 | (width & 0xffff));
1307 /* bitdepth_luma = 8*/
1308 /* bitdepth_chroma = 8*/
1309 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1310
1311#ifdef H265_LOSLESS_COMPRESS_MODE
1312 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1313 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1314#else
1315 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1316#endif
1317 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1318 data32 &= (~0x30);
1319 data32 |= (mem_map_mode << 4);
1320 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1321
1322 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1323 (0x80 << 20) | (0x80 << 10) | (0xff));
1324
1325 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1326
1327 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1328 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1329 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1330 /* ipp_enable*/
1331 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1332
1333 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1334 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1335 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1336 if (dw_mode)
1337 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1338 else
1339 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1340 }
1341
1342 data32 = READ_VREG(HEVC_SAO_CTRL0);
1343 data32 &= (~0xf);
1344 data32 |= 0x4;
1345 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1346 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1347 (width & 0xffff));
1348 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1349
1350 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1351 data32 = (lcu_x_num | lcu_y_num << 16);
1352 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1353 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1354 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1355 data32 = (mc_buffer_size_u_v_h << 16);
1356 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1357
1358 data32 = READ_VREG(HEVC_SAO_CTRL1);
1359 data32 &= (~0x3000);
1360 data32 &= (~0xff0);
1361 data32 |= endian; /* Big-Endian per 64-bit */
1362
1363 if (hw->mmu_enable && dw_mode)
1364 data32 |= ((mem_map_mode << 12));
1365 else
1366 data32 |= ((mem_map_mode << 12)|2);
1367
1368 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1369
1370#ifdef H265_DW_NO_SCALE
1371 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1372 if (hw->mmu_enable && dw_mode) {
1373 data32 = READ_VREG(HEVC_SAO_CTRL5);
1374 data32 &= (~(0xff << 16));
1375 if (dw_mode == 2 ||
1376 dw_mode == 3)
1377 data32 |= (0xff<<16);
1378 else if (dw_mode == 4)
1379 data32 |= (0x33<<16);
1380 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1381 }
1382
1383
1384#endif
1385
1386
1387#ifdef H265_LOSLESS_COMPRESS_MODE
1388 data32 = READ_VREG(HEVC_SAO_CTRL5);
1389 data32 |= (1<<9); /*8-bit smem-mode*/
1390 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1391
1392 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1393 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1394 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1395#endif
1396
1397#ifdef H265_LOSLESS_COMPRESS_MODE
1398 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1399 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1400#endif
1401
1402 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1403
1404 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1405
1406 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1407 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1408 return;
1409}
1410
1411static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1412 u32 is_new_pic, u32 is_idr)
1413{
1414 hw->is_new_pic = is_new_pic;
1415 hw->is_idr_frame = is_idr;
1416 return;
1417}
1418
1419static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1420 struct StorablePicture *pic) {
1421 u32 mc_y_adr;
1422 u32 mc_u_v_adr;
1423 u32 dw_y_adr;
1424 u32 dw_u_v_adr;
1425 u32 canvas_addr;
1426 int ret;
1427 int dw_mode = hw->double_write_mode;
1428 if (hw->is_new_pic != 1)
1429 return;
1430
1431 if (hw->is_idr_frame) {
1432 /* William TBD */
1433 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1434 }
1435
1436 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1437 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1438 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1439 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1440 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1441 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1442 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1443 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1444 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1445
1446
1447 if (dw_mode) {
1448 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1449 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1450 } else {
1451 dw_y_adr = 0;
1452 dw_u_v_adr = 0;
1453 }
1454#ifdef H265_LOSLESS_COMPRESS_MODE
1455 if (dw_mode)
1456 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1457 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1458#ifdef H264_MMU
1459 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1460#else
1461 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1462 (mc_y_adr + hw->losless_comp_body_size));
1463#endif
1464#else
1465 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1466#endif
1467
1468#ifndef H265_LOSLESS_COMPRESS_MODE
1469 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1470#else
1471 if (dw_mode)
1472 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1473#endif
1474
1475#ifndef LOSLESS_COMPRESS_MODE
1476 if (dw_mode) {
1477 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1478 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1479 }
1480#else
1481 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1482 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1483#endif
1484
1485 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1486 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1487 hw->frame_mmu_map_addr);
1488 if (ret != 0) {
1489 dpb_print(DECODE_ID(hw),
1490 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1491 pic->buf_spec_num,
1492 ret);
1493 return;
1494 }
1495
1496 /*Reset SAO + Enable SAO slice_start*/
1497 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1498 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1499 WRITE_VREG(HEVC_SAO_INT_STATUS,
1500 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1501 WRITE_VREG(HEVC_SAO_INT_STATUS,
1502 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1503 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1504 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1505
1506 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1507 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1508 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1509 } else
1510 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1511 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1512 hw->frame_busy = 1;
1513 return;
1514}
1515
1516
1517static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1518 u32 buf_spec_num) {
1519 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1520 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1521 dpb_print(DECODE_ID(hw),
1522 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1523 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1524 return;
1525}
1526
1527
1528static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1529{
1530 ulong timeout = jiffies + HZ;
1531 dpb_print(DECODE_ID(hw),
1532 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1533 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1534 if (time_after(jiffies, timeout)) {
1535 dpb_print(DECODE_ID(hw),
1536 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1537 break;
1538 }
1539 }
1540 timeout = jiffies + HZ;
1541 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1542 if (time_after(jiffies, timeout)) {
1543 dpb_print(DECODE_ID(hw),
1544 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1545 break;
1546 }
1547 }
1548 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1549 hw->frame_done = 1;
1550 return;
1551}
1552
1553static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1554{
1555 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1556 if (p_H264_Dpb->mVideo.dec_picture) {
1557 release_picture(p_H264_Dpb,
1558 p_H264_Dpb->mVideo.dec_picture);
1559 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1560 p_H264_Dpb->mVideo.dec_picture = NULL;
1561 if (hw->mmu_enable)
1562 hevc_set_frame_done(hw);
1563 }
1564}
1565
1566static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1567{
1568 ulong timeout = jiffies + HZ;
1569 dpb_print(DECODE_ID(hw),
1570 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1571 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1572 if (time_after(jiffies, timeout)) {
1573 dpb_print(DECODE_ID(hw),
1574 PRINT_FLAG_MMU_DETAIL,
1575 "hevc_sao_wait_done...wait timeout!\n");
1576 break;
1577 }
1578 }
1579 timeout = jiffies + HZ;
1580 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1581 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1582 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1583 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1584 H265_ABORT_SAO_4K_SET_DONE) {
1585 if (time_after(jiffies, timeout)) {
1586 dpb_print(DECODE_ID(hw),
1587 PRINT_FLAG_MMU_DETAIL,
1588 "wait h265_abort_sao_4k_set_done timeout!\n");
1589 break;
1590 }
1591 }
1592 }
1593 amhevc_stop();
1594 hw->frame_busy = 0;
1595 hw->frame_done = 0;
1596 dpb_print(DECODE_ID(hw),
1597 PRINT_FLAG_MMU_DETAIL,
1598 "sao wait done ,hevc stop!\n");
1599 }
1600 return;
1601}
1602static void buf_spec_init(struct vdec_h264_hw_s *hw)
1603{
1604 int i;
1605 unsigned long flags;
1606 spin_lock_irqsave(&hw->bufspec_lock, flags);
1607 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1608 hw->buffer_spec[i].used = -1;
1609 hw->buffer_spec[i].canvas_pos = -1;
1610 }
1611 if (dpb_is_debug(DECODE_ID(hw),
1612 PRINT_FLAG_DUMP_BUFSPEC))
1613 dump_bufspec(hw, __func__);
1614 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1615}
1616
1617/*is active in buf management */
1618static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1619 int buf_spec_num)
1620{
1621 unsigned char ret = 0;
1622 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1623 hw->buffer_spec[buf_spec_num].used == 2 ||
1624 hw->buffer_spec[buf_spec_num].used == 3 ||
1625 hw->buffer_spec[buf_spec_num].used == 5)
1626 ret = 1;
1627 return ret;
1628}
1629
1630static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1631 int buf_spec_num)
1632{
1633 unsigned char ret = 0;
1634 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1635 hw->buffer_spec[buf_spec_num].used == 3 ||
1636 hw->buffer_spec[buf_spec_num].used == 5)
1637 ret = 1;
1638 return ret;
1639}
1640
1641static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1642{
1643 if (hw->mmu_enable) {
1644 if (hw->buffer_spec[i].alloc_header_addr)
1645 return 0;
1646 else
1647 return -1;
1648 } else {
1649
1650 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1651 int addr;
1652#ifdef VDEC_DW
1653 int orig_buf_size;
1654 orig_buf_size = buf_size;
1655 if (IS_VDEC_DW(hw) == 1)
1656 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1657 else if (IS_VDEC_DW(hw) == 2)
1658 buf_size += (hw->mb_total << 6) + (hw->mb_total << 5);
1659#endif
1660 if (hw->buffer_spec[i].cma_alloc_addr)
1661 return 0;
1662
1663 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1664 PAGE_ALIGN(buf_size), DRIVER_NAME,
1665 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1666 hw->buffer_spec[i].cma_alloc_addr = 0;
1667 if (hw->no_mem_count++ > 3) {
1668 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1669 hw->reset_bufmgr_flag = 1;
1670 }
1671 dpb_print(DECODE_ID(hw), 0,
1672 "%s, fail to alloc buf for bufspec%d, try later\n",
1673 __func__, i
1674 );
1675 return -1;
1676 } else {
1677 hw->no_mem_count = 0;
1678 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1679 }
1680
1681 hw->buffer_spec[i].buf_adr =
1682 hw->buffer_spec[i].cma_alloc_addr;
1683 addr = hw->buffer_spec[i].buf_adr;
1684
1685
1686 hw->buffer_spec[i].y_addr = addr;
1687 addr += hw->mb_total << 8;
1688 hw->buffer_spec[i].u_addr = addr;
1689 hw->buffer_spec[i].v_addr = addr;
1690 addr += hw->mb_total << 7;
1691
1692 hw->buffer_spec[i].canvas_config[0].phy_addr =
1693 hw->buffer_spec[i].y_addr;
1694 hw->buffer_spec[i].canvas_config[0].width =
1695 hw->mb_width << 4;
1696 hw->buffer_spec[i].canvas_config[0].height =
1697 hw->mb_height << 4;
1698 hw->buffer_spec[i].canvas_config[0].block_mode =
1699 hw->canvas_mode;
1700
1701 hw->buffer_spec[i].canvas_config[1].phy_addr =
1702 hw->buffer_spec[i].u_addr;
1703 hw->buffer_spec[i].canvas_config[1].width =
1704 hw->mb_width << 4;
1705 hw->buffer_spec[i].canvas_config[1].height =
1706 hw->mb_height << 3;
1707 hw->buffer_spec[i].canvas_config[1].block_mode =
1708 hw->canvas_mode;
1709 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1710 "%s, alloc buf for bufspec%d\n",
1711 __func__, i
1712 );
1713#ifdef VDEC_DW
1714
1715 if (!IS_VDEC_DW(hw))
1716 return 0;
1717 else if (IS_VDEC_DW(hw) == 1) {
1718 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1719 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1720 addr += hw->mb_total << 7;
1721 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1722 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1723 addr += hw->mb_total << 6;
1724
1725 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1726 hw->buffer_spec[i].vdec_dw_y_addr;
1727 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1728 hw->mb_width << 3;
1729 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1730 hw->mb_height << 4;
1731 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1732 CANVAS_BLKMODE_32X32;
1733
1734 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1735 hw->buffer_spec[i].vdec_dw_u_addr;
1736 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1737 hw->mb_width << 3;
1738 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1739 hw->mb_height << 3;
1740 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1741 CANVAS_BLKMODE_32X32;
1742 }else {
1743 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1744 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1745 addr += hw->mb_total << 6;
1746 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1747 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1748 addr += hw->mb_total << 5;
1749
1750 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1751 hw->buffer_spec[i].vdec_dw_y_addr;
1752 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1753 hw->mb_width << 3;
1754 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1755 hw->mb_height << 3;
1756 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1757 CANVAS_BLKMODE_32X32;
1758
1759 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1760 hw->buffer_spec[i].vdec_dw_u_addr;
1761 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1762 hw->mb_width << 3;
1763 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1764 hw->mb_height << 2;
1765 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1766 CANVAS_BLKMODE_32X32;
1767 }
1768 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1769 "%s, vdec_dw: alloc buf for bufspec%d\n",
1770 __func__, i
1771 );
1772#endif
1773 }
1774 return 0;
1775}
1776
1777static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1778{
1779 int ret = 0;
1780 struct aml_vcodec_ctx *ctx = NULL;
1781 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1782 struct canvas_config_s *y_canvas_cfg = NULL;
1783 struct canvas_config_s *c_canvas_cfg = NULL;
1784 struct vdec_v4l2_buffer *fb = NULL;
1785 unsigned int y_addr = 0, c_addr = 0;
1786
1787 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1788 pr_err("the v4l context has err.\n");
1789 return -1;
1790 }
1791
1792 if (bs->cma_alloc_addr)
1793 return 0;
1794
1795 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1796 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1797 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1798 ctx->id, __func__,
1799 (hw->mb_total << 8) + (hw->mb_total << 7));
1800
1801 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1802 if (ret < 0) {
1803 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1804 "[%d] get fb fail.\n", ctx->id);
1805 return ret;
1806 }
1807
1808 bs->cma_alloc_addr = (unsigned long)fb;
1809 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1810 "[%d] %s(), cma alloc addr: 0x%x\n",
1811 ctx->id, __func__, bs->cma_alloc_addr);
1812
1813 if (fb->num_planes == 1) {
1814 y_addr = fb->m.mem[0].addr;
1815 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1816 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1817 } else if (fb->num_planes == 2) {
1818 y_addr = fb->m.mem[0].addr;
1819 c_addr = fb->m.mem[1].addr;
1820 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1821 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1822 }
1823
1824 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1825 "[%d] %s(), y_addr: %x, size: %u\n",
1826 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1827 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1828 "[%d] %s(), c_addr: %x, size: %u\n",
1829 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1830
1831 bs->y_addr = y_addr;
1832 bs->u_addr = c_addr;
1833 bs->v_addr = c_addr;
1834
1835 y_canvas_cfg = &bs->canvas_config[0];
1836 c_canvas_cfg = &bs->canvas_config[1];
1837
1838 y_canvas_cfg->phy_addr = y_addr;
1839 y_canvas_cfg->width = hw->mb_width << 4;
1840 y_canvas_cfg->height = hw->mb_height << 4;
1841 y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1842 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1843 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1844 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1845 y_canvas_cfg->width,y_canvas_cfg->height);
1846
1847 c_canvas_cfg->phy_addr = c_addr;
1848 c_canvas_cfg->width = hw->mb_width << 4;
1849 c_canvas_cfg->height = hw->mb_height << 3;
1850 c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1851 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1852 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1853 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1854 c_canvas_cfg->width, c_canvas_cfg->height);
1855
1856 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1857 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1858
1859 return ret;
1860}
1861
1862static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1863{
1864 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
1865 int blkmode = CANVAS_BLKMODE_32X32;
1866 int endian = 0;
1867
1868 if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
1869 blkmode = CANVAS_BLKMODE_LINEAR;
1870 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1871 endian = 7;
1872 else
1873 endian = 0;
1874 }
1875
1876 if (hw->is_used_v4l) {
1877 blkmode = CANVAS_BLKMODE_LINEAR;
1878 if (v4l2_ctx->ada_ctx->vfm_path
1879 != FRAME_BASE_PATH_V4L_VIDEO)
1880 endian = 7;
1881 }
1882
1883 canvas_config_ex(hw->buffer_spec[i].
1884 y_canvas_index,
1885 hw->buffer_spec[i].y_addr,
1886 hw->mb_width << 4,
1887 hw->mb_height << 4,
1888 CANVAS_ADDR_NOWRAP,
1889 blkmode,
1890 endian);
1891
1892 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1893 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1894 (1 << 11) | /* canvas_blk32_wr */
1895 (blkmode << 10) | /* canvas_blk32*/
1896 (1 << 8) | /* canvas_index_wr*/
1897 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1898 );
1899 }
1900
1901 canvas_config_ex(hw->buffer_spec[i].
1902 u_canvas_index,
1903 hw->buffer_spec[i].u_addr,
1904 hw->mb_width << 4,
1905 hw->mb_height << 3,
1906 CANVAS_ADDR_NOWRAP,
1907 blkmode,
1908 endian);
1909
1910 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1911 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1912 (1 << 11) |
1913 (blkmode << 10) |
1914 (1 << 8) |
1915 (hw->buffer_spec[i].u_canvas_index << 0));
1916 }
1917
1918 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1919 spec2canvas(&hw->buffer_spec[i]));
1920
1921
1922#ifdef VDEC_DW
1923 if (!IS_VDEC_DW(hw))
1924 return;
1925 else if (IS_VDEC_DW(hw) == 1) {
1926 canvas_config_ex(hw->buffer_spec[i].
1927 vdec_dw_y_canvas_index,
1928 hw->buffer_spec[i].vdec_dw_y_addr,
1929 hw->mb_width << 3,
1930 hw->mb_height << 4,
1931 CANVAS_ADDR_NOWRAP,
1932 blkmode,
1933 endian);
1934 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1935 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1936 (1 << 11) |
1937 (blkmode << 10) |
1938 (1 << 8) |
1939 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1940 }
1941 canvas_config_ex(hw->buffer_spec[i].
1942 vdec_dw_u_canvas_index,
1943 hw->buffer_spec[i].vdec_dw_u_addr,
1944 hw->mb_width << 3,
1945 hw->mb_height << 3,
1946 CANVAS_ADDR_NOWRAP,
1947 blkmode,
1948 endian);
1949 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1950 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1951 (1 << 11) |
1952 (blkmode << 10) |
1953 (1 << 8) |
1954 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1955 }
1956 } else {
1957 canvas_config_ex(hw->buffer_spec[i].
1958 vdec_dw_y_canvas_index,
1959 hw->buffer_spec[i].vdec_dw_y_addr,
1960 hw->mb_width << 3,
1961 hw->mb_height << 3,
1962 CANVAS_ADDR_NOWRAP,
1963 blkmode,
1964 endian);
1965 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1966 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1967 (1 << 11) |
1968 (blkmode << 10) |
1969 (1 << 8) |
1970 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1971 }
1972
1973 canvas_config_ex(hw->buffer_spec[i].
1974 vdec_dw_u_canvas_index,
1975 hw->buffer_spec[i].vdec_dw_u_addr,
1976 hw->mb_width << 3,
1977 hw->mb_height << 2,
1978 CANVAS_ADDR_NOWRAP,
1979 blkmode,
1980 endian);
1981 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1982 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1983 (1 << 11) |
1984 (blkmode << 10) |
1985 (1 << 8) |
1986 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1987 }
1988 }
1989#endif
1990}
1991
1992static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1993{
1994 u32 blkmode = mem_map_mode;
1995 int canvas_w;
1996 int canvas_h;
1997
1998 canvas_w = hw->frame_width /
1999 get_double_write_ratio(hw);
2000 canvas_h = hw->frame_height /
2001 get_double_write_ratio(hw);
2002
2003 if (mem_map_mode == 0)
2004 canvas_w = ALIGN(canvas_w, 32);
2005 else
2006 canvas_w = ALIGN(canvas_w, 64);
2007 canvas_h = ALIGN(canvas_h, 32);
2008
2009 canvas_config_ex(hw->buffer_spec[i].
2010 y_canvas_index,
2011 hw->buffer_spec[i].dw_y_adr,
2012 canvas_w,
2013 canvas_h,
2014 CANVAS_ADDR_NOWRAP,
2015 blkmode,
2016 7);
2017
2018 canvas_config_ex(hw->buffer_spec[i].
2019 u_canvas_index,
2020 hw->buffer_spec[i].dw_u_v_adr,
2021 canvas_w,
2022 canvas_h,
2023 CANVAS_ADDR_NOWRAP,
2024 blkmode,
2025 7);
2026}
2027
2028
2029int get_free_buf_idx(struct vdec_s *vdec)
2030{
2031 int i;
2032 unsigned long addr, flags;
2033 int index = -1;
2034 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2035 int buf_total = BUFSPEC_POOL_SIZE;
2036
2037 if (hw->is_used_v4l)
2038 buf_total = hw->dpb.mDPB.size;
2039
2040 spin_lock_irqsave(&hw->bufspec_lock, flags);
2041 /*hw->start_search_pos = 0;*/
2042 for (i = hw->start_search_pos; i < buf_total; i++) {
2043 if (hw->mmu_enable)
2044 addr = hw->buffer_spec[i].alloc_header_addr;
2045 else {
2046 addr = hw->buffer_spec[i].cma_alloc_addr;
2047 if (hw->is_used_v4l && !addr) {
2048 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2049 config_decode_canvas(hw, i);
2050 addr = hw->buffer_spec[i].cma_alloc_addr;
2051 }
2052 }
2053 }
2054 if (hw->buffer_spec[i].used == 0 && addr) {
2055 hw->buffer_spec[i].used = 1;
2056 hw->start_search_pos = i+1;
2057 index = i;
2058 break;
2059 }
2060 }
2061 if (index < 0) {
2062 for (i = 0; i < hw->start_search_pos; i++) {
2063 if (hw->mmu_enable)
2064 addr = hw->buffer_spec[i].alloc_header_addr;
2065 else {
2066 addr = hw->buffer_spec[i].cma_alloc_addr;
2067 if (hw->is_used_v4l && !addr) {
2068 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2069 config_decode_canvas(hw, i);
2070 addr = hw->buffer_spec[i].cma_alloc_addr;
2071 }
2072 }
2073 }
2074 if (hw->buffer_spec[i].used == 0 && addr) {
2075 hw->buffer_spec[i].used = 1;
2076 hw->start_search_pos = i+1;
2077 index = i;
2078 break;
2079 }
2080 }
2081 }
2082 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2083 if (hw->start_search_pos >= buf_total)
2084 hw->start_search_pos = 0;
2085 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2086 "%s, buf_spec_num %d\n", __func__, index);
2087
2088 if (index < 0) {
2089 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2090 "%s fail\n", __func__);
2091 vmh264_dump_state(vdec);
2092 }
2093
2094 if (dpb_is_debug(DECODE_ID(hw),
2095 PRINT_FLAG_DUMP_BUFSPEC))
2096 dump_bufspec(hw, __func__);
2097 return index;
2098}
2099
2100int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2101{
2102 /*u32 cur_buf_idx;*/
2103 unsigned long flags;
2104 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2105 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2106 "%s buf_spec_num %d used %d\n",
2107 __func__, buf_spec_num,
2108 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2109 if (buf_spec_num >= 0 &&
2110 buf_spec_num < BUFSPEC_POOL_SIZE
2111 ) {
2112 spin_lock_irqsave(&hw->bufspec_lock, flags);
2113 hw->buffer_spec[buf_spec_num].used = 0;
2114 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2115 if (hw->mmu_enable) {
2116 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2117 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2118 cur_buf_idx = cur_buf_idx&0xff;*/
2119 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2120 }
2121 release_aux_data(hw, buf_spec_num);
2122 }
2123 if (dpb_is_debug(DECODE_ID(hw),
2124 PRINT_FLAG_DUMP_BUFSPEC))
2125 dump_bufspec(hw, __func__);
2126 return 0;
2127}
2128
2129static void config_buf_specs(struct vdec_s *vdec)
2130{
2131 int i, j;
2132 unsigned long flags;
2133 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2134 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2135
2136 spin_lock_irqsave(&hw->bufspec_lock, flags);
2137 for (i = 0, j = 0;
2138 j < hw->dpb.mDPB.size
2139 && i < BUFSPEC_POOL_SIZE;
2140 i++) {
2141 int canvas;
2142 if (hw->buffer_spec[i].used != -1)
2143 continue;
2144 if (vdec->parallel_dec == 1) {
2145 if (hw->buffer_spec[i].y_canvas_index == -1)
2146 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2147 if (hw->buffer_spec[i].u_canvas_index == -1) {
2148 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2149 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2150 }
2151#ifdef VDEC_DW
2152 if (IS_VDEC_DW(hw)) {
2153 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2154 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2155 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2156 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2157 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2158 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2159 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2160 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2161 }
2162 }
2163#endif
2164 } else {
2165 canvas = vdec->get_canvas(j * mode, 2);
2166 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2167 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2168 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2169 dpb_print(DECODE_ID(hw),
2170 PRINT_FLAG_DPB_DETAIL,
2171 "config canvas (%d) %x for bufspec %d\r\n",
2172 j, canvas, i);
2173#ifdef VDEC_DW
2174 if (IS_VDEC_DW(hw)) {
2175 canvas = vdec->get_canvas(j * mode + 1, 2);
2176 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2177 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2178 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2179 dpb_print(DECODE_ID(hw),
2180 PRINT_FLAG_DPB_DETAIL,
2181 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2182 j, canvas, i);
2183 }
2184#endif
2185 }
2186
2187 hw->buffer_spec[i].used = 0;
2188 hw->buffer_spec[i].canvas_pos = j;
2189
2190
2191 j++;
2192 }
2193 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2194}
2195
2196static void config_buf_specs_ex(struct vdec_s *vdec)
2197{
2198 int i, j;
2199 unsigned long flags;
2200 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2201 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2202
2203 spin_lock_irqsave(&hw->bufspec_lock, flags);
2204 for (i = 0, j = 0;
2205 j < hw->dpb.mDPB.size
2206 && i < BUFSPEC_POOL_SIZE;
2207 i++) {
2208 int canvas = 0;
2209 if (hw->buffer_spec[i].used != -1)
2210 continue;
2211 if (vdec->parallel_dec == 1) {
2212 if (hw->buffer_spec[i].y_canvas_index == -1)
2213 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2214 if (hw->buffer_spec[i].u_canvas_index == -1) {
2215 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2216 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2217 }
2218#ifdef VDEC_DW
2219 if (IS_VDEC_DW(hw)) {
2220 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2221 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2222 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2223 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2224 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2225 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2226 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2227 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2228 }
2229 }
2230#endif
2231 } else {
2232 canvas = vdec->get_canvas(j* mode, 2);
2233 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2234 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2235 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2236
2237 dpb_print(DECODE_ID(hw),
2238 PRINT_FLAG_DPB_DETAIL,
2239 "config canvas (%d) %x for bufspec %d\r\n",
2240 j, canvas, i);
2241#ifdef VDEC_DW
2242 if (IS_VDEC_DW(hw)) {
2243 canvas = vdec->get_canvas(j*mode + 1, 2);
2244 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2245 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2246 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2247 dpb_print(DECODE_ID(hw),
2248 PRINT_FLAG_DPB_DETAIL,
2249 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2250 j, canvas, i);
2251 }
2252#endif
2253 }
2254
2255 hw->buffer_spec[i].used = 0;
2256 hw->buffer_spec[i].alloc_header_addr = 0;
2257 hw->buffer_spec[i].canvas_pos = j;
2258
2259 j++;
2260 }
2261 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2262}
2263
2264
2265static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2266 unsigned char release_all)
2267{
2268 int i;
2269 unsigned long flags;
2270 unsigned char dealloc_flag = 0;
2271 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2272 if (hw->buffer_spec[i].used == 4 ||
2273 release_all) {
2274 dealloc_flag = 1;
2275 dpb_print(DECODE_ID(hw),
2276 PRINT_FLAG_DPB_DETAIL,
2277 "%s buf_spec_num %d\n",
2278 __func__, i
2279 );
2280 spin_lock_irqsave
2281 (&hw->bufspec_lock, flags);
2282 hw->buffer_spec[i].used = -1;
2283 spin_unlock_irqrestore
2284 (&hw->bufspec_lock, flags);
2285 release_aux_data(hw, i);
2286
2287 if (!hw->mmu_enable) {
2288 if (hw->buffer_spec[i].cma_alloc_addr) {
2289 if (!hw->is_used_v4l) {
2290 decoder_bmmu_box_free_idx(
2291 hw->bmmu_box,
2292 i);
2293 }
2294 spin_lock_irqsave
2295 (&hw->bufspec_lock, flags);
2296 hw->buffer_spec[i].cma_alloc_addr = 0;
2297 hw->buffer_spec[i].buf_adr = 0;
2298 spin_unlock_irqrestore
2299 (&hw->bufspec_lock, flags);
2300 }
2301 } else {
2302 if (hw->buffer_spec[i].alloc_header_addr) {
2303 decoder_mmu_box_free_idx(
2304 hw->mmu_box,
2305 i);
2306 spin_lock_irqsave
2307 (&hw->bufspec_lock, flags);
2308 hw->buffer_spec[i].
2309 alloc_header_addr = 0;
2310 hw->buffer_spec[i].buf_adr = 0;
2311 spin_unlock_irqrestore
2312 (&hw->bufspec_lock, flags);
2313 }
2314 }
2315 }
2316 }
2317 if (dealloc_flag &&
2318 dpb_is_debug(DECODE_ID(hw),
2319 PRINT_FLAG_DUMP_BUFSPEC))
2320 dump_bufspec(hw, __func__);
2321 return;
2322}
2323
2324unsigned char have_free_buf_spec(struct vdec_s *vdec)
2325{
2326 int i;
2327 unsigned long addr;
2328 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2329 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2330 int index = -1;
2331 int ret = 0;
2332 int allocated_count = 0;
2333 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2334 if (hw->mmu_enable)
2335 addr = hw->buffer_spec[i].alloc_header_addr;
2336 else
2337 addr = hw->buffer_spec[i].cma_alloc_addr;
2338 if (hw->buffer_spec[i].used == 0) {
2339
2340 if (addr)
2341 return 1;
2342 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2343 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2344 index = i;
2345 }
2346 }
2347 if (addr)
2348 allocated_count++;
2349 }
2350 if (index >= 0) {
2351 mutex_lock(&vmh264_mutex);
2352 dealloc_buf_specs(hw, 0);
2353 if (max_alloc_buf_count == 0 ||
2354 allocated_count < max_alloc_buf_count) {
2355 if (hw->is_used_v4l)
2356 ret = 1;
2357 else if (alloc_one_buf_spec(hw, index) >= 0)
2358 ret = 1;
2359 }
2360 mutex_unlock(&vmh264_mutex);
2361 }
2362 return ret;
2363}
2364
2365static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2366 int canvas_pos)
2367{
2368 int i;
2369 int j = 0;
2370 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2371 if (hw->buffer_spec[i].canvas_pos >= 0) {
2372 if (j == canvas_pos)
2373 return i;
2374 j++;
2375 }
2376 }
2377 return -1;
2378}
2379static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2380 struct vframe_s *vf, int index)
2381{
2382 if (index < 0) {
2383 vf->mem_handle = NULL;
2384 vf->mem_head_handle = NULL;
2385 } else if (vf->type & VIDTYPE_SCATTER) {
2386 vf->mem_handle =
2387 decoder_mmu_box_get_mem_handle(
2388 hw->mmu_box, index);
2389 vf->mem_head_handle =
2390 decoder_bmmu_box_get_mem_handle(
2391 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2392 } else {
2393 vf->mem_handle =
2394 decoder_bmmu_box_get_mem_handle(
2395 hw->bmmu_box, VF_BUFFER_IDX(index));
2396 /* vf->mem_head_handle =
2397 decoder_bmmu_box_get_mem_handle(
2398 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2399 }
2400 return;
2401}
2402static int check_force_interlace(struct vdec_h264_hw_s *hw,
2403 struct FrameStore *frame)
2404{
2405 int bForceInterlace = 0;
2406 /* no di in secure mode, disable force di */
2407 if (vdec_secure(hw_to_vdec(hw)))
2408 return 0;
2409 if (frame->frame) {
2410 if (frame->frame->coded_frame
2411 && !frame->frame->frame_mbs_only_flag) {
2412 if (frame->frame->structure == FRAME)
2413 return 1;
2414 }
2415 }
2416
2417 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2418 && hw->bitstream_restriction_flag
2419 && (hw->frame_width == 1920)
2420 && (hw->frame_height >= 1080)
2421 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2422 bForceInterlace = 1;
2423 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2424 && (hw->frame_width == 720)
2425 && (hw->frame_height == 576)
2426 && (hw->frame_dur == 3840)) {
2427 bForceInterlace = 1;
2428 }
2429
2430 return bForceInterlace;
2431}
2432
2433static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2434{
2435 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2436 if (frame->slice_type == I_SLICE)
2437 vframe_qos->type = 1;
2438 else if (frame->slice_type == P_SLICE)
2439 vframe_qos->type = 2;
2440 else if (frame->slice_type == B_SLICE)
2441 vframe_qos->type = 3;
2442
2443 vframe_qos->size = frame->frame_size;
2444 vframe_qos->pts = frame->pts64;
2445
2446 vframe_qos->max_mv = frame->max_mv;
2447 vframe_qos->avg_mv = frame->avg_mv;
2448 vframe_qos->min_mv = frame->min_mv;
2449/*
2450 pr_info("mv: max:%d, avg:%d, min:%d\n",
2451 vframe_qos->max_mv,
2452 vframe_qos->avg_mv,
2453 vframe_qos->min_mv);
2454*/
2455
2456 vframe_qos->max_qp = frame->max_qp;
2457 vframe_qos->avg_qp = frame->avg_qp;
2458 vframe_qos->min_qp = frame->min_qp;
2459/*
2460 pr_info("qp: max:%d, avg:%d, min:%d\n",
2461 vframe_qos->max_qp,
2462 vframe_qos->avg_qp,
2463 vframe_qos->min_qp);
2464*/
2465
2466 vframe_qos->max_skip = frame->max_skip;
2467 vframe_qos->avg_skip = frame->avg_skip;
2468 vframe_qos->min_skip = frame->min_skip;
2469/*
2470 pr_info("skip: max:%d, avg:%d, min:%d\n",
2471 vframe_qos->max_skip,
2472 vframe_qos->avg_skip,
2473 vframe_qos->min_skip);
2474*/
2475 vframe_qos->num++;
2476 if (hw->frameinfo_enable)
2477 vdec_fill_frame_info(vframe_qos, 1);
2478}
2479
2480static int is_iframe(struct FrameStore *frame) {
2481
2482 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2483 return 1;
2484 }
2485 return 0;
2486}
2487
2488
2489
2490int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2491{
2492 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2493 struct vframe_s *vf = NULL;
2494 int buffer_index = frame->buf_spec_num;
2495 int vf_count = 1;
2496 int i;
2497 int bForceInterlace = 0;
2498
2499 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2500 dpb_print(DECODE_ID(hw), 0,
2501 "%s, buffer_index 0x%x is beyond range\n",
2502 __func__, buffer_index);
2503 return -1;
2504 }
2505 if (force_disp_bufspec_num & 0x100) {
2506 /*recycle directly*/
2507 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2508 hw->buffer_spec[frame->buf_spec_num].used != 5)
2509 set_frame_output_flag(&hw->dpb, frame->index);
2510
2511 /*make pre_output not set*/
2512 return -1;
2513 }
2514 if (error_proc_policy & 0x1000) {
2515 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2516 int error_skip_frame_count = error_skip_count & 0xfff;
2517 if (((hw->no_error_count < error_skip_frame_count)
2518 && (error_skip_i_count == 0 ||
2519 hw->no_error_i_count < error_skip_i_count))
2520 && (!(frame->data_flag & I_FLAG)))
2521 frame->data_flag |= ERROR_FLAG;
2522 }
2523 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2524 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2525 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2526 frame->poc, hw->data_flag & ERROR_FLAG,
2527 error_proc_policy);
2528 if (frame->frame == NULL &&
2529 ((frame->is_used == 1 && frame->top_field)
2530 || (frame->is_used == 2 && frame->bottom_field))) {
2531 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2532 "%s Error frame_num %d used %d\n",
2533 __func__, frame->frame_num, frame->is_used);
2534 frame->data_flag |= ERROR_FLAG;
2535 }
2536 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2537 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2538 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2539 0, &frame->pts64) == 0)) {
2540 hw->last_pts64 = frame->pts64;
2541 hw->last_pts = frame->pts;
2542 } else {
2543 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2544 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2545 }
2546 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2547 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2548 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2549 frame->offset_delimiter, frame->pts,hw->last_pts,
2550 frame->pts64, hw->last_pts64, hw->frame_dur);
2551 hw->last_pts64 = frame->pts64;
2552 hw->last_pts = frame->pts;
2553 }
2554 if ((frame->data_flag & NODISP_FLAG) ||
2555 (frame->data_flag & NULL_FLAG) ||
2556 ((!hw->send_error_frame_flag) &&
2557 (frame->data_flag & ERROR_FLAG)) ||
2558 ((hw->i_only & 0x1) &&
2559 (!(frame->data_flag & I_FLAG)))
2560 ) {
2561 set_frame_output_flag(&hw->dpb, frame->index);
2562 return 0; /*do not return -1,
2563 otherwise flush_dpb() will not flush all dbp frames*/
2564 }
2565
2566 display_frame_count[DECODE_ID(hw)]++;
2567
2568 if (dpb_is_debug(DECODE_ID(hw),
2569 PRINT_FLAG_DPB_DETAIL)) {
2570 dpb_print(DECODE_ID(hw), 0,
2571 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2572 __func__, frame->index, frame->poc,
2573 frame->buf_spec_num);
2574 print_pic_info(DECODE_ID(hw), "predis_frm",
2575 frame->frame, -1);
2576 print_pic_info(DECODE_ID(hw), "predis_top",
2577 frame->top_field, -1);
2578 print_pic_info(DECODE_ID(hw), "predis_bot",
2579 frame->bottom_field, -1);
2580 }
2581
2582 if (!is_interlace(frame))
2583 vf_count = 1;
2584 else
2585 vf_count = 2;
2586 bForceInterlace = check_force_interlace(hw, frame);
2587 if (bForceInterlace)
2588 vf_count = 2;
2589 hw->buffer_spec[buffer_index].vf_ref = 0;
2590 fill_frame_info(hw, frame);
2591 for (i = 0; i < vf_count; i++) {
2592 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2593 vf == NULL) {
2594 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2595 "%s fatal error, no available buffer slot.\n",
2596 __func__);
2597 return -1;
2598 }
2599 vf->duration_pulldown = 0;
2600 if (!(is_iframe(frame)) && hw->unstable_pts) {
2601 vf->pts = 0;
2602 vf->pts_us64 = 0;
2603 vf->timestamp = 0;
2604 vf->index = VF_INDEX(frame->index, buffer_index);
2605 } else {
2606 vf->pts = frame->pts;
2607 vf->pts_us64 = frame->pts64;
2608 vf->timestamp = frame->timestamp;
2609 vf->index = VF_INDEX(frame->index, buffer_index);
2610 }
2611
2612 if (hw->is_used_v4l) {
2613 vf->v4l_mem_handle
2614 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2615 }
2616
2617 if (hw->mmu_enable) {
2618 if (hw->double_write_mode & 0x10) {
2619 /* double write only */
2620 vf->compBodyAddr = 0;
2621 vf->compHeadAddr = 0;
2622 } else {
2623 /*head adr*/
2624 vf->compHeadAddr =
2625 hw->buffer_spec[buffer_index].alloc_header_addr;
2626 /*body adr*/
2627 vf->compBodyAddr = 0;
2628 vf->canvas0Addr = vf->canvas1Addr = 0;
2629 }
2630
2631 vf->type = VIDTYPE_SCATTER;
2632
2633 if (hw->double_write_mode) {
2634 vf->type |= VIDTYPE_PROGRESSIVE
2635 | VIDTYPE_VIU_FIELD;
2636 vf->type |= VIDTYPE_VIU_NV21;
2637 if (hw->double_write_mode == 3)
2638 vf->type |= VIDTYPE_COMPRESS;
2639
2640 vf->canvas0Addr = vf->canvas1Addr = -1;
2641 vf->plane_num = 2;
2642 vf->canvas0_config[0] =
2643 hw->buffer_spec[buffer_index].
2644 canvas_config[0];
2645 vf->canvas0_config[1] =
2646 hw->buffer_spec[buffer_index].
2647 canvas_config[1];
2648
2649 vf->canvas1_config[0] =
2650 hw->buffer_spec[buffer_index].
2651 canvas_config[0];
2652 vf->canvas1_config[1] =
2653 hw->buffer_spec[buffer_index].
2654 canvas_config[1];
2655
2656 } else {
2657 vf->type |=
2658 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2659 vf->canvas0Addr = vf->canvas1Addr = 0;
2660 }
2661
2662 vf->bitdepth =
2663 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2664
2665 vf->compWidth = hw->frame_width;
2666 vf->compHeight = hw->frame_height;
2667 } else {
2668 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2669 VIDTYPE_VIU_NV21;
2670
2671 vf->canvas0Addr = vf->canvas1Addr =
2672 spec2canvas(&hw->buffer_spec[buffer_index]);
2673#ifdef VDEC_DW
2674 if (IS_VDEC_DW(hw))
2675 vf->canvas0Addr = vf->canvas1Addr =
2676 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2677#endif
2678
2679 }
2680 set_frame_info(hw, vf, buffer_index);
2681
2682 if (hw->mmu_enable && hw->double_write_mode) {
2683 vf->width = hw->frame_width /
2684 get_double_write_ratio(hw);
2685 vf->height = hw->frame_height /
2686 get_double_write_ratio(hw);
2687 }
2688
2689 vf->flag = 0;
2690 if (frame->data_flag & I_FLAG)
2691 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2692 if (frame->data_flag & ERROR_FLAG)
2693 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2694 update_vf_memhandle(hw, vf, buffer_index);
2695 hw->buffer_spec[buffer_index].used = 2;
2696 hw->buffer_spec[buffer_index].vf_ref++;
2697
2698 if (bForceInterlace || is_interlace(frame)) {
2699 vf->type =
2700 VIDTYPE_INTERLACE_FIRST |
2701 VIDTYPE_VIU_NV21;
2702
2703 if (bForceInterlace) {
2704 vf->type |= (i == 0 ?
2705 VIDTYPE_INTERLACE_TOP :
2706 VIDTYPE_INTERLACE_BOTTOM);
2707 if (i == 1) {
2708 vf->pts = 0;
2709 vf->pts_us64 = 0;
2710 }
2711 } else if (frame->top_field->poc <=
2712 frame->bottom_field->poc) /*top first*/
2713 vf->type |= (i == 0 ?
2714 VIDTYPE_INTERLACE_TOP :
2715 VIDTYPE_INTERLACE_BOTTOM);
2716 else
2717 vf->type |= (i == 0 ?
2718 VIDTYPE_INTERLACE_BOTTOM :
2719 VIDTYPE_INTERLACE_TOP);
2720 vf->duration = vf->duration/2;
2721 }
2722
2723 if (i == 0)
2724 decoder_do_frame_check(hw_to_vdec(hw), vf);
2725
2726 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2727 vf->sar_width = hw->width_aspect_ratio;
2728 vf->sar_height = hw->height_aspect_ratio;
2729
2730 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2731 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2732 hw->vf_pre_count++;
2733 vdec->vdec_fps_detec(vdec->id);
2734 if (without_display_mode == 0) {
2735 vf_notify_receiver(vdec->vf_provider_name,
2736 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2737 } else
2738 vh264_vf_put(vh264_vf_get(vdec), vdec);
2739 }
2740 if (dpb_is_debug(DECODE_ID(hw),
2741 PRINT_FLAG_DUMP_BUFSPEC))
2742 dump_bufspec(hw, __func__);
2743
2744 return 0;
2745}
2746
2747int notify_v4l_eos(struct vdec_s *vdec)
2748{
2749 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2750 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2751 struct vframe_s *vf = &hw->vframe_dummy;
2752 struct vdec_v4l2_buffer *fb = NULL;
2753 int index = INVALID_IDX;
2754 ulong expires;
2755
2756 if (hw->is_used_v4l && hw->eos) {
2757 expires = jiffies + msecs_to_jiffies(2000);
2758 while (INVALID_IDX == (index = get_free_buf_idx(vdec))) {
2759 if (time_after(jiffies, expires))
2760 break;
2761 }
2762
2763 if (index == INVALID_IDX) {
2764 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
2765 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
2766 return -1;
2767 }
2768 }
2769
2770 vf->type |= VIDTYPE_V4L_EOS;
2771 vf->timestamp = ULONG_MAX;
2772 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2773 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
2774 hw->buffer_spec[index].cma_alloc_addr;
2775
2776 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2777
2778 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2779 vf_notify_receiver(vdec->vf_provider_name,
2780 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2781
2782 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2783 }
2784
2785 return 0;
2786}
2787
2788/******************
2789 * Hardware config
2790 */
2791char *slice_type_name[] = {
2792 "P_SLICE ",
2793 "B_SLICE ",
2794 "I_SLICE ",
2795 "SP_SLICE",
2796 "SI_SLICE",
2797};
2798
2799char *picture_structure_name[] = {
2800 "FRAME",
2801 "TOP_FIELD",
2802 "BOTTOM_FIELD"
2803};
2804
2805void print_pic_info(int decindex, const char *info,
2806 struct StorablePicture *pic,
2807 int slice_type)
2808{
2809 if (pic)
2810 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2811 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2812 info,
2813 picture_structure_name[pic->structure],
2814 pic->coded_frame ? "Frame" : "Field",
2815 (slice_type < 0 ||
2816 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2817 pic->mb_aff_frame_flag,
2818 pic->poc,
2819 pic->pic_num,
2820 pic->buf_spec_num,
2821 pic->data_flag);
2822}
2823
2824static void reset_process_time(struct vdec_h264_hw_s *hw)
2825{
2826 if (hw->start_process_time) {
2827 unsigned process_time =
2828 1000 * (jiffies - hw->start_process_time) / HZ;
2829 hw->start_process_time = 0;
2830 if (process_time > max_process_time[DECODE_ID(hw)])
2831 max_process_time[DECODE_ID(hw)] = process_time;
2832 }
2833}
2834
2835static void start_process_time(struct vdec_h264_hw_s *hw)
2836{
2837 hw->decode_timeout_count = 10;
2838 hw->start_process_time = jiffies;
2839}
2840
2841static void config_aux_buf(struct vdec_h264_hw_s *hw)
2842{
2843 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2844 WRITE_VREG(H264_AUX_DATA_SIZE,
2845 ((hw->prefix_aux_size >> 4) << 16) |
2846 (hw->suffix_aux_size >> 4)
2847 );
2848}
2849
2850/*
2851* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2852*/
2853static void set_aux_data(struct vdec_h264_hw_s *hw,
2854 struct StorablePicture *pic, unsigned char suffix_flag,
2855 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2856{
2857 int i;
2858 unsigned short *aux_adr;
2859 unsigned size_reg_val =
2860 READ_VREG(H264_AUX_DATA_SIZE);
2861 unsigned aux_count = 0;
2862 int aux_size = 0;
2863 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2864 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2865 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2866 return;
2867
2868 if (suffix_flag) {
2869 aux_adr = (unsigned short *)
2870 (hw_buf->aux_addr +
2871 hw_buf->prefix_aux_size);
2872 aux_count =
2873 ((size_reg_val & 0xffff) << 4)
2874 >> 1;
2875 aux_size =
2876 hw_buf->suffix_aux_size;
2877 } else {
2878 aux_adr =
2879 (unsigned short *)hw_buf->aux_addr;
2880 aux_count =
2881 ((size_reg_val >> 16) << 4)
2882 >> 1;
2883 aux_size =
2884 hw_buf->prefix_aux_size;
2885 }
2886 if (dpb_is_debug(DECODE_ID(hw),
2887 PRINT_FLAG_DPB_DETAIL)) {
2888 dpb_print(DECODE_ID(hw), 0,
2889 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2890 __func__, AUX_DATA_SIZE(pic),
2891 aux_count, suffix_flag, dv_meta_flag);
2892 }
2893 if (aux_size > 0 && aux_count > 0) {
2894 int heads_size = 0;
2895 int new_size;
2896 char *new_buf;
2897 for (i = 0; i < aux_count; i++) {
2898 unsigned char tag = aux_adr[i] >> 8;
2899 if (tag != 0 && tag != 0xff) {
2900 if (dv_meta_flag == 0)
2901 heads_size += 8;
2902 else if (dv_meta_flag == 1 && tag == 0x1)
2903 heads_size += 8;
2904 else if (dv_meta_flag == 2 && tag != 0x1)
2905 heads_size += 8;
2906 }
2907 }
2908 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2909 new_buf = krealloc(AUX_DATA_BUF(pic),
2910 new_size,
2911 GFP_KERNEL);
2912 if (new_buf) {
2913 unsigned char valid_tag = 0;
2914 unsigned char *h =
2915 new_buf +
2916 AUX_DATA_SIZE(pic);
2917 unsigned char *p = h + 8;
2918 int len = 0;
2919 int padding_len = 0;
2920 AUX_DATA_BUF(pic) = new_buf;
2921 for (i = 0; i < aux_count; i += 4) {
2922 int ii;
2923 unsigned char tag = aux_adr[i + 3] >> 8;
2924 if (tag != 0 && tag != 0xff) {
2925 if (dv_meta_flag == 0)
2926 valid_tag = 1;
2927 else if (dv_meta_flag == 1
2928 && tag == 0x1)
2929 valid_tag = 1;
2930 else if (dv_meta_flag == 2
2931 && tag != 0x1)
2932 valid_tag = 1;
2933 else
2934 valid_tag = 0;
2935 if (valid_tag && len > 0) {
2936 AUX_DATA_SIZE(pic) +=
2937 (len + 8);
2938 h[0] =
2939 (len >> 24) & 0xff;
2940 h[1] =
2941 (len >> 16) & 0xff;
2942 h[2] =
2943 (len >> 8) & 0xff;
2944 h[3] =
2945 (len >> 0) & 0xff;
2946 h[6] =
2947 (padding_len >> 8)
2948 & 0xff;
2949 h[7] =
2950 (padding_len) & 0xff;
2951 h += (len + 8);
2952 p += 8;
2953 len = 0;
2954 padding_len = 0;
2955 }
2956 if (valid_tag) {
2957 h[4] = tag;
2958 h[5] = 0;
2959 h[6] = 0;
2960 h[7] = 0;
2961 }
2962 }
2963 if (valid_tag) {
2964 for (ii = 0; ii < 4; ii++) {
2965 unsigned short aa =
2966 aux_adr[i + 3
2967 - ii];
2968 *p = aa & 0xff;
2969 p++;
2970 len++;
2971 /*if ((aa >> 8) == 0xff)
2972 padding_len++;*/
2973 }
2974 }
2975 }
2976 if (len > 0) {
2977 AUX_DATA_SIZE(pic) += (len + 8);
2978 h[0] = (len >> 24) & 0xff;
2979 h[1] = (len >> 16) & 0xff;
2980 h[2] = (len >> 8) & 0xff;
2981 h[3] = (len >> 0) & 0xff;
2982 h[6] = (padding_len >> 8) & 0xff;
2983 h[7] = (padding_len) & 0xff;
2984 }
2985 if (dpb_is_debug(DECODE_ID(hw),
2986 PRINT_FLAG_DPB_DETAIL)) {
2987 dpb_print(DECODE_ID(hw), 0,
2988 "aux: (size %d) suffix_flag %d\n",
2989 AUX_DATA_SIZE(pic), suffix_flag);
2990 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
2991 dpb_print_cont(DECODE_ID(hw), 0,
2992 "%02x ", AUX_DATA_BUF(pic)[i]);
2993 if (((i + 1) & 0xf) == 0)
2994 dpb_print_cont(
2995 DECODE_ID(hw),
2996 0, "\n");
2997 }
2998 dpb_print_cont(DECODE_ID(hw),
2999 0, "\n");
3000 }
3001
3002 }
3003 }
3004
3005}
3006
3007static void release_aux_data(struct vdec_h264_hw_s *hw,
3008 int buf_spec_num)
3009{
3010 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3011 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3012 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3013}
3014
3015static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3016{
3017 int i;
3018 unsigned short *aux_adr =
3019 (unsigned short *)
3020 hw->aux_addr;
3021 unsigned aux_size =
3022 (READ_VREG(H264_AUX_DATA_SIZE)
3023 >> 16) << 4;
3024
3025 if (hw->prefix_aux_size > 0) {
3026 dpb_print(DECODE_ID(hw),
3027 0,
3028 "prefix aux: (size %d)\n",
3029 aux_size);
3030 for (i = 0; i <
3031 (aux_size >> 1); i++) {
3032 dpb_print_cont(DECODE_ID(hw),
3033 0,
3034 "%04x ",
3035 *(aux_adr + i));
3036 if (((i + 1) & 0xf)
3037 == 0)
3038 dpb_print_cont(
3039 DECODE_ID(hw),
3040 0, "\n");
3041 }
3042 }
3043 if (hw->suffix_aux_size > 0) {
3044 aux_adr = (unsigned short *)
3045 (hw->aux_addr +
3046 hw->prefix_aux_size);
3047 aux_size =
3048 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3049 << 4;
3050 dpb_print(DECODE_ID(hw),
3051 0,
3052 "suffix aux: (size %d)\n",
3053 aux_size);
3054 for (i = 0; i <
3055 (aux_size >> 1); i++) {
3056 dpb_print_cont(DECODE_ID(hw),
3057 0,
3058 "%04x ", *(aux_adr + i));
3059 if (((i + 1) & 0xf) == 0)
3060 dpb_print_cont(DECODE_ID(hw),
3061 0, "\n");
3062 }
3063 }
3064}
3065
3066static void config_decode_mode(struct vdec_h264_hw_s *hw)
3067{
3068#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3069 struct vdec_s *vdec = hw_to_vdec(hw);
3070#endif
3071 if (input_frame_based(hw_to_vdec(hw)))
3072 WRITE_VREG(H264_DECODE_MODE,
3073 DECODE_MODE_MULTI_FRAMEBASE);
3074#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3075 else if (vdec->slave)
3076 WRITE_VREG(H264_DECODE_MODE,
3077 (hw->got_valid_nal << 8) |
3078 DECODE_MODE_MULTI_DVBAL);
3079 else if (vdec->master)
3080 WRITE_VREG(H264_DECODE_MODE,
3081 (hw->got_valid_nal << 8) |
3082 DECODE_MODE_MULTI_DVENL);
3083#endif
3084 else
3085 WRITE_VREG(H264_DECODE_MODE,
3086 DECODE_MODE_MULTI_STREAMBASE);
3087 WRITE_VREG(H264_DECODE_SEQINFO,
3088 hw->seq_info2);
3089 WRITE_VREG(HEAD_PADING_REG, 0);
3090
3091 if (hw->init_flag == 0)
3092 WRITE_VREG(INIT_FLAG_REG, 0);
3093 else
3094 WRITE_VREG(INIT_FLAG_REG, 1);
3095}
3096int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3097{
3098 /* static int count = 0; */
3099 int ret = 0;
3100 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3101 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3102 unsigned int colocate_adr_offset;
3103 unsigned int val;
3104 struct StorablePicture *last_pic = hw->last_dec_picture;
3105
3106#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3107 int colocate_buf_index;
3108#endif
3109#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3110#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3111#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3112#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3113
3114#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3115/* bit 31:30 -- L1[0] picture coding structure,
3116 * 00 - top field, 01 - bottom field,
3117 * 10 - frame, 11 - mbaff frame
3118 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3119 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3120 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3121 */
3122#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3123
3124/* bit 15 -- flush co_mb_data to DDR -- W-Only
3125 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3126 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3127 * bit 9 -- soft_reset -- W-Only
3128 * bit 8 -- upgent
3129 * bit 7:2 -- h264_co_mb_mem_wr_addr
3130 * bit 1:0 -- h264_co_mb_info_wr_ptr
3131 */
3132#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3133
3134 unsigned long canvas_adr;
3135 unsigned int ref_reg_val;
3136 unsigned int one_ref_cfg = 0;
3137 int h264_buffer_info_data_write_count;
3138 int i, j;
3139 unsigned int colocate_wr_adr;
3140 unsigned int colocate_rd_adr;
3141 unsigned char use_direct_8x8;
3142 int canvas_pos;
3143 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3144 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3145 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3146 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3147 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3148
3149 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3150 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3151 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3152 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3153 canvas_pos);
3154 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3155
3156#ifdef VDEC_DW
3157 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3158 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3159 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3160#endif
3161 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3162 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3163
3164 if (!hw->mmu_enable) {
3165 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3166 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3167 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3168#ifdef VDEC_DW
3169 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3170 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3171 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3172#endif
3173 } else
3174 hevc_sao_set_pic_buffer(hw, pic);
3175
3176 if (pic->mb_aff_frame_flag)
3177 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3178 else if (pic->structure == TOP_FIELD)
3179 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3180 else if (pic->structure == BOTTOM_FIELD)
3181 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3182 else
3183 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3184
3185 if (pic->bottom_poc < pic->top_poc)
3186 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3187
3188 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3189 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3190 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3191
3192 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3193 int long_term_flag;
3194 i = get_buf_spec_by_canvas_pos(hw, j);
3195 if (i < 0)
3196 break;
3197 long_term_flag =
3198 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3199 if (long_term_flag > 0) {
3200 if (long_term_flag & 0x1)
3201 hw->buffer_spec[i].info0 |= (1 << 4);
3202 else
3203 hw->buffer_spec[i].info0 &= ~(1 << 4);
3204
3205 if (long_term_flag & 0x2)
3206 hw->buffer_spec[i].info0 |= (1 << 5);
3207 else
3208 hw->buffer_spec[i].info0 &= ~(1 << 5);
3209 }
3210
3211 if (i == pic->buf_spec_num)
3212 WRITE_VREG(H264_BUFFER_INFO_DATA,
3213 hw->buffer_spec[i].info0 | 0xf);
3214 else
3215 WRITE_VREG(H264_BUFFER_INFO_DATA,
3216 hw->buffer_spec[i].info0);
3217 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3218 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3219 }
3220
3221 /* config reference buffer */
3222 if (hw->mmu_enable) {
3223 hevc_mcr_config_mc_ref(hw);
3224 hevc_mcr_config_mcrcc(hw);
3225 }
3226
3227 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3228 "list0 size %d\n", pSlice->listXsize[0]);
3229 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3230 ref_reg_val = 0;
3231 j = 0;
3232 h264_buffer_info_data_write_count = 0;
3233
3234 //disable this read cache when frame width <= 64 (4MBs)
3235 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3236 if (hw->frame_width <= 64)
3237 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3238 else
3239 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3240
3241 if (last_pic)
3242 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3243 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3244 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3245 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3246 last_pic && (last_pic->data_flag & ERROR_FLAG)
3247 && (!(last_pic->slice_type == B_SLICE))
3248 && (!(pSlice->slice_type == I_SLICE))) {
3249 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3250 "no i/idr error mark\n");
3251 hw->data_flag |= ERROR_FLAG;
3252 pic->data_flag |= ERROR_FLAG;
3253 }
3254
3255 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3256 /*ref list 0 */
3257 struct StorablePicture *ref = pSlice->listX[0][i];
3258 unsigned int cfg;
3259 /* bit[6:5] - frame/field info,
3260 * 01 - top, 10 - bottom, 11 - frame
3261 */
3262 #ifdef ERROR_CHECK
3263 if (ref == NULL) {
3264 hw->data_flag |= ERROR_FLAG;
3265 pic->data_flag |= ERROR_FLAG;
3266 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3267 return -1;
3268 }
3269 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3270 hw->data_flag |= ERROR_FLAG;
3271 pic->data_flag |= ERROR_FLAG;
3272 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3273 }
3274 if (ref->data_flag & NULL_FLAG)
3275 hw->data_flag |= NULL_FLAG;
3276#endif
3277 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3278
3279 if (ref->structure == TOP_FIELD)
3280 cfg = 0x1;
3281 else if (ref->structure == BOTTOM_FIELD)
3282 cfg = 0x2;
3283 else /* FRAME */
3284 cfg = 0x3;
3285
3286 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3287 ref_reg_val <<= 8;
3288 ref_reg_val |= one_ref_cfg;
3289 j++;
3290
3291 if (j == 4) {
3292 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3293 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3294 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3295 h264_buffer_info_data_write_count++;
3296 j = 0;
3297 }
3298 print_pic_info(DECODE_ID(hw), "list0",
3299 pSlice->listX[0][i], -1);
3300 }
3301 if (j != 0) {
3302 while (j != 4) {
3303 ref_reg_val <<= 8;
3304 ref_reg_val |= one_ref_cfg;
3305 j++;
3306 }
3307 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3308 "H264_BUFFER_INFO_DATA: %x\n",
3309 ref_reg_val);
3310 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3311 h264_buffer_info_data_write_count++;
3312 }
3313 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3314 (one_ref_cfg << 8) | one_ref_cfg;
3315 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3316 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3317
3318 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3319 "list1 size %d\n", pSlice->listXsize[1]);
3320 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3321 ref_reg_val = 0;
3322 j = 0;
3323
3324 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3325 /* ref list 0 */
3326 struct StorablePicture *ref = pSlice->listX[1][i];
3327 unsigned int cfg;
3328 /* bit[6:5] - frame/field info,
3329 * 01 - top, 10 - bottom, 11 - frame
3330 */
3331
3332 #ifdef ERROR_CHECK
3333 if (ref == NULL) {
3334 hw->data_flag |= ERROR_FLAG;
3335 pic->data_flag |= ERROR_FLAG;
3336 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3337 return -2;
3338 }
3339 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3340 pic->data_flag |= ERROR_FLAG;
3341 hw->data_flag |= ERROR_FLAG;
3342 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3343 }
3344 if (ref->data_flag & NULL_FLAG)
3345 hw->data_flag |= NULL_FLAG;
3346#endif
3347 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3348 if (ref->structure == TOP_FIELD)
3349 cfg = 0x1;
3350 else if (ref->structure == BOTTOM_FIELD)
3351 cfg = 0x2;
3352 else /* FRAME */
3353 cfg = 0x3;
3354 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3355 ref_reg_val <<= 8;
3356 ref_reg_val |= one_ref_cfg;
3357 j++;
3358
3359 if (j == 4) {
3360 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3361 "H264_BUFFER_INFO_DATA: %x\n",
3362 ref_reg_val);
3363 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3364 j = 0;
3365 }
3366 print_pic_info(DECODE_ID(hw), "list1",
3367 pSlice->listX[1][i], -1);
3368 }
3369 if (j != 0) {
3370 while (j != 4) {
3371 ref_reg_val <<= 8;
3372 ref_reg_val |= one_ref_cfg;
3373 j++;
3374 }
3375 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3376 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3377 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3378 }
3379
3380 /* configure co-locate buffer */
3381 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3382 ;
3383 if ((pSlice->mode_8x8_flags & 0x4) &&
3384 (pSlice->mode_8x8_flags & 0x2))
3385 use_direct_8x8 = 1;
3386 else
3387 use_direct_8x8 = 0;
3388
3389#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3390 colocate_adr_offset =
3391 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3392 ? 1 : 2) * 96;
3393 if (use_direct_8x8)
3394 colocate_adr_offset >>= 2;
3395
3396 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3397 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3398 colocate_adr_offset, pSlice->first_mb_in_slice,
3399 colocate_adr_offset * pSlice->first_mb_in_slice);
3400
3401 colocate_adr_offset *= pSlice->first_mb_in_slice;
3402
3403 if ((pic->colocated_buf_index >= 0) &&
3404 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3405 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3406 ((p_H264_Dpb->colocated_buf_size *
3407 pic->colocated_buf_index)
3408 >> (use_direct_8x8 ? 2 : 0));
3409 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3410 p_H264_Dpb->colocated_mv_addr_end) {
3411 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3412 "Error, colocate buf is not enough, index is %d\n",
3413 pic->colocated_buf_index);
3414 ret = -3;
3415 }
3416 val = colocate_wr_adr + colocate_adr_offset;
3417 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3418 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3419 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3420 val, pSlice->first_mb_in_slice, pic->structure,
3421 colocate_adr_offset, pSlice->mode_8x8_flags,
3422 p_H264_Dpb->colocated_buf_size);
3423 } else {
3424 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3425 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3426 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3427 }
3428#else
3429 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3430 colocate_adr_offset =
3431 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3432 if (use_direct_8x8)
3433 colocate_adr_offset >>= 2;
3434
3435 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3436 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3437 colocate_adr_offset, pSlice->first_mb_in_slice,
3438 colocate_adr_offset * pSlice->first_mb_in_slice);
3439
3440 colocate_adr_offset *= pSlice->first_mb_in_slice;
3441
3442 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3443 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3444 (use_direct_8x8 ? 2 : 0));
3445
3446 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3447 p_H264_Dpb->colocated_mv_addr_end) {
3448 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3449 "Error, colocate buf is not enough, col buf index is %d\n",
3450 colocate_buf_index);
3451 ret = -4;
3452 }
3453 val = colocate_wr_adr + colocate_adr_offset;
3454 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3455 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3456 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3457 val, pSlice->first_mb_in_slice, pic->structure,
3458 colocate_adr_offset, pSlice->mode_8x8_flags,
3459 p_H264_Dpb->colocated_buf_size);
3460#endif
3461 if (pSlice->listXsize[1] > 0) {
3462 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3463 /* H264_CO_MB_RD_ADDR[bit 31:30],
3464 * original picture structure of L1[0],
3465 * 00 - top field, 01 - bottom field,
3466 * 10 - frame, 11 - mbaff frame
3467 */
3468 int l10_structure;
3469 int cur_colocate_ref_type;
3470 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3471 * 0 - top, 1 - bot
3472 */
3473 unsigned int val;
3474#ifdef ERROR_CHECK
3475 if (colocate_pic == NULL) {
3476 hw->data_flag |= ERROR_FLAG;
3477 pic->data_flag |= ERROR_FLAG;
3478 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3479 return -5;
3480 }
3481 if (colocate_pic->data_flag & ERROR_FLAG) {
3482 pic->data_flag |= ERROR_FLAG;
3483 hw->data_flag |= ERROR_FLAG;
3484 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3485 }
3486 if (colocate_pic->data_flag & NULL_FLAG)
3487 hw->data_flag |= NULL_FLAG;
3488#endif
3489
3490 if (colocate_pic->mb_aff_frame_flag)
3491 l10_structure = 3;
3492 else {
3493 if (colocate_pic->coded_frame)
3494 l10_structure = 2;
3495 else
3496 l10_structure = (colocate_pic->structure ==
3497 BOTTOM_FIELD) ? 1 : 0;
3498 }
3499#if 0
3500 /*case0016, p16,
3501 *cur_colocate_ref_type should be configured base on current pic
3502 */
3503 if (pic->structure == FRAME &&
3504 pic->mb_aff_frame_flag)
3505 cur_colocate_ref_type = 0;
3506 else if (pic->structure == BOTTOM_FIELD)
3507 cur_colocate_ref_type = 1;
3508 else
3509 cur_colocate_ref_type = 0;
3510#else
3511 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3512 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3513 pic->mb_aff_frame_flag,
3514 pic->structure,
3515 pic->coded_frame);
3516 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3517 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3518 colocate_pic->mb_aff_frame_flag,
3519 colocate_pic->structure,
3520 colocate_pic->coded_frame);
3521 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3522 cur_colocate_ref_type =
3523 (abs(pic->poc - colocate_pic->top_poc)
3524 < abs(pic->poc -
3525 colocate_pic->bottom_poc)) ? 0 : 1;
3526 } else
3527 cur_colocate_ref_type =
3528 (colocate_pic->structure
3529 == BOTTOM_FIELD) ? 1 : 0;
3530#endif
3531
3532#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3533 if ((colocate_pic->colocated_buf_index >= 0) &&
3534 (colocate_pic->colocated_buf_index <
3535 p_H264_Dpb->colocated_buf_count)) {
3536 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3537 ((p_H264_Dpb->colocated_buf_size *
3538 colocate_pic->colocated_buf_index)
3539 >> (use_direct_8x8 ? 2 : 0));
3540 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3541 p_H264_Dpb->colocated_mv_addr_end) {
3542 dpb_print(DECODE_ID(hw),
3543 PRINT_FLAG_ERROR,
3544 "Error, colocate buf is not enough, index is %d\n",
3545 colocate_pic->colocated_buf_index);
3546 ret = -6;
3547 }
3548 /* bit 31:30 -- L1[0] picture coding structure,
3549 * 00 - top field, 01 - bottom field,
3550 * 10 - frame, 11 - mbaff frame
3551 * bit 29 - L1[0] top/bot for B field pciture,
3552 * 0 - top, 1 - bot
3553 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3554 * -- only used for B Picture Direct mode
3555 * [2:0] will set to 3'b000
3556 */
3557 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3558 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3559 (l10_structure << 30) |
3560 (cur_colocate_ref_type << 29);
3561 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3562 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3563 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3564 colocate_pic->colocated_buf_index,
3565 val, colocate_rd_adr + colocate_adr_offset,
3566 colocate_pic->structure,
3567 colocate_pic->mb_aff_frame_flag);
3568 } else {
3569 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3570 "Error, reference pic has no colocated buf\n");
3571 ret = -7;
3572 }
3573#else
3574 colocate_buf_index =
3575 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3576 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3577 ((p_H264_Dpb->colocated_buf_size *
3578 colocate_buf_index)
3579 >> (use_direct_8x8 ? 2 : 0));
3580 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3581 p_H264_Dpb->colocated_mv_addr_end) {
3582 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3583 "Error, colocate buf is not enough, col buf index is %d\n",
3584 colocate_buf_index);
3585 ret = -8;
3586 }
3587 /* bit 31:30 -- L1[0] picture coding structure,
3588 * 00 - top field, 01 - bottom field,
3589 * 10 - frame, 11 - mbaff frame
3590 * bit 29 - L1[0] top/bot for B field pciture,
3591 * 0 - top, 1 - bot
3592 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3593 * -- only used for B Picture Direct mode
3594 * [2:0] will set to 3'b000
3595 */
3596 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3597 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3598 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3599 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3600 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3601 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3602 val, colocate_pic->structure,
3603 colocate_pic->mb_aff_frame_flag);
3604#endif
3605 }
3606 return ret;
3607}
3608
3609static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3610{
3611 unsigned long flags;
3612 struct vdec_s *vdec = op_arg;
3613 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3614
3615 spin_lock_irqsave(&hw->lock, flags);
3616
3617 states->vf_pool_size = VF_POOL_SIZE;
3618 states->buf_free_num = kfifo_len(&hw->newframe_q);
3619 states->buf_avail_num = kfifo_len(&hw->display_q);
3620
3621 spin_unlock_irqrestore(&hw->lock, flags);
3622
3623 return 0;
3624}
3625
3626static struct vframe_s *vh264_vf_peek(void *op_arg)
3627{
3628 struct vframe_s *vf[2] = {0, 0};
3629 struct vdec_s *vdec = op_arg;
3630 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3631
3632 if (!hw)
3633 return NULL;
3634
3635 if (force_disp_bufspec_num & 0x100) {
3636 if (force_disp_bufspec_num & 0x200)
3637 return NULL;
3638 return &hw->vframe_dummy;
3639 }
3640
3641 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3642 if (vf[1]) {
3643 vf[0]->next_vf_pts_valid = true;
3644 vf[0]->next_vf_pts = vf[1]->pts;
3645 } else
3646 vf[0]->next_vf_pts_valid = false;
3647 return vf[0];
3648 }
3649
3650 return NULL;
3651}
3652
3653static struct vframe_s *vh264_vf_get(void *op_arg)
3654{
3655 struct vframe_s *vf;
3656 struct vdec_s *vdec = op_arg;
3657 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3658
3659 if (!hw)
3660 return NULL;
3661
3662 if (force_disp_bufspec_num & 0x100) {
3663 int buffer_index = force_disp_bufspec_num & 0xff;
3664 if (force_disp_bufspec_num & 0x200)
3665 return NULL;
3666
3667 vf = &hw->vframe_dummy;
3668 vf->duration_pulldown = 0;
3669 vf->pts = 0;
3670 vf->pts_us64 = 0;
3671 set_frame_info(hw, vf, buffer_index);
3672 vf->flag = 0;
3673 if (hw->mmu_enable) {
3674 if (hw->double_write_mode & 0x10) {
3675 /* double write only */
3676 vf->compBodyAddr = 0;
3677 vf->compHeadAddr = 0;
3678 } else {
3679 /*head adr*/
3680 vf->compHeadAddr =
3681 hw->buffer_spec[buffer_index].alloc_header_addr;
3682 /*body adr*/
3683 vf->compBodyAddr = 0;
3684 vf->canvas0Addr = vf->canvas1Addr = 0;
3685 }
3686
3687 vf->type = VIDTYPE_SCATTER;
3688
3689 if (hw->double_write_mode) {
3690 vf->type |= VIDTYPE_PROGRESSIVE
3691 | VIDTYPE_VIU_FIELD;
3692 vf->type |= VIDTYPE_VIU_NV21;
3693 if (hw->double_write_mode == 3)
3694 vf->type |= VIDTYPE_COMPRESS;
3695
3696 vf->canvas0Addr = vf->canvas1Addr = -1;
3697 vf->plane_num = 2;
3698 vf->canvas0_config[0] =
3699 hw->buffer_spec[buffer_index].
3700 canvas_config[0];
3701 vf->canvas0_config[1] =
3702 hw->buffer_spec[buffer_index].
3703 canvas_config[1];
3704
3705 vf->canvas1_config[0] =
3706 hw->buffer_spec[buffer_index].
3707 canvas_config[0];
3708 vf->canvas1_config[1] =
3709 hw->buffer_spec[buffer_index].
3710 canvas_config[1];
3711 } else {
3712 vf->type |=
3713 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3714 vf->canvas0Addr = vf->canvas1Addr = 0;
3715 }
3716 vf->bitdepth =
3717 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3718
3719 vf->compWidth = hw->frame_width;
3720 vf->compHeight = hw->frame_height;
3721
3722 if (hw->double_write_mode) {
3723 vf->width = hw->frame_width /
3724 get_double_write_ratio(hw);
3725 vf->height = hw->frame_height /
3726 get_double_write_ratio(hw);
3727 }
3728 } else {
3729 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3730 VIDTYPE_VIU_NV21;
3731 vf->canvas0Addr = vf->canvas1Addr =
3732 spec2canvas(&hw->buffer_spec[buffer_index]);
3733 }
3734
3735 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3736 hw->bmmu_box, buffer_index);*/
3737 update_vf_memhandle(hw, vf, buffer_index);
3738 force_disp_bufspec_num |= 0x200;
3739 return vf;
3740 }
3741
3742 if (kfifo_get(&hw->display_q, &vf)) {
3743 int time = jiffies;
3744 unsigned int frame_interval =
3745 1000*(time - hw->last_frame_time)/HZ;
3746 struct vframe_s *next_vf;
3747 if (dpb_is_debug(DECODE_ID(hw),
3748 PRINT_FLAG_VDEC_DETAIL)) {
3749 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3750 int frame_index = FRAME_INDEX(vf->index);
3751 if (frame_index < 0 ||
3752 frame_index >= DPB_SIZE_MAX) {
3753 dpb_print(DECODE_ID(hw), 0,
3754 "%s vf index 0x%x error\r\n",
3755 __func__, vf->index);
3756 } else {
3757 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3758 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3759 __func__, BUFSPEC_INDEX(vf->index), vf,
3760 p_H264_Dpb->mFrameStore[frame_index].poc,
3761 vf->duration, vf->pts, frame_interval);
3762 }
3763 }
3764 if (hw->last_frame_time > 0) {
3765 if (frame_interval >
3766 max_get_frame_interval[DECODE_ID(hw)])
3767 max_get_frame_interval[DECODE_ID(hw)]
3768 = frame_interval;
3769 }
3770 hw->last_frame_time = time;
3771 hw->vf_get_count++;
3772 if (kfifo_peek(&hw->display_q, &next_vf)) {
3773 vf->next_vf_pts_valid = true;
3774 vf->next_vf_pts = next_vf->pts;
3775 } else
3776 vf->next_vf_pts_valid = false;
3777 return vf;
3778 }
3779
3780 return NULL;
3781}
3782
3783static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3784{
3785 struct vdec_s *vdec = op_arg;
3786 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3787 int buf_spec_num;
3788 int frame_index;
3789
3790 if (vf == (&hw->vframe_dummy))
3791 return;
3792 if (vf->index == -1) {
3793 dpb_print(DECODE_ID(hw), 0,
3794 "Warning: %s vf %p invalid index\r\n",
3795 __func__, vf);
3796 return;
3797 }
3798 frame_index = FRAME_INDEX(vf->index);
3799 buf_spec_num = BUFSPEC_INDEX(vf->index);
3800 if (frame_index < 0 ||
3801 frame_index >= DPB_SIZE_MAX ||
3802 buf_spec_num < 0 ||
3803 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3804 dpb_print(DECODE_ID(hw), 0,
3805 "%s vf index 0x%x error\r\n",
3806 __func__, vf->index);
3807 return;
3808 }
3809 /*get_buf_spec_idx_by_canvas_config(hw,
3810 &vf->canvas0_config[0]);*/
3811 if (hw->buffer_spec[buf_spec_num].used == 2) {
3812 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3813 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3814 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3815 __func__, vf, frame_index,
3816 p_H264_Dpb->mFrameStore[frame_index].poc,
3817 buf_spec_num,
3818 hw->buffer_spec[buf_spec_num].used,
3819 hw->buffer_spec[buf_spec_num].vf_ref);
3820 hw->buffer_spec[buf_spec_num].vf_ref--;
3821 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3822 set_frame_output_flag(&hw->dpb, frame_index);
3823 } else {
3824 unsigned long flags;
3825 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3826 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3827 __func__, vf, buf_spec_num,
3828 hw->buffer_spec[buf_spec_num].used,
3829 hw->buffer_spec[buf_spec_num].vf_ref);
3830 spin_lock_irqsave(&hw->bufspec_lock, flags);
3831 hw->buffer_spec[buf_spec_num].vf_ref--;
3832 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3833 if (hw->buffer_spec[buf_spec_num].used == 3)
3834 hw->buffer_spec[buf_spec_num].used = 4;
3835 else if (hw->buffer_spec[buf_spec_num].used == 5)
3836 hw->buffer_spec[buf_spec_num].used = 0;
3837 }
3838 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3839 if (dpb_is_debug(DECODE_ID(hw),
3840 PRINT_FLAG_DUMP_BUFSPEC))
3841 dump_bufspec(hw, __func__);
3842
3843 }
3844
3845 hw->vf_put_count++;
3846 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3847
3848#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3849 if (hw->buffer_empty_flag)
3850 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3851}
3852
3853static int vh264_event_cb(int type, void *data, void *op_arg)
3854{
3855 unsigned long flags;
3856 struct vdec_s *vdec = op_arg;
3857 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3858
3859 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3860 struct provider_aux_req_s *req =
3861 (struct provider_aux_req_s *)data;
3862 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3863 spin_lock_irqsave(&hw->lock, flags);
3864 req->aux_buf = NULL;
3865 req->aux_size = 0;
3866 if (buf_spec_num >= 0 &&
3867 buf_spec_num < BUFSPEC_POOL_SIZE &&
3868 is_buf_spec_in_disp_q(hw, buf_spec_num)
3869 ) {
3870 req->aux_buf =
3871 hw->buffer_spec[buf_spec_num].aux_data_buf;
3872 req->aux_size =
3873 hw->buffer_spec[buf_spec_num].aux_data_size;
3874#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3875 req->dv_enhance_exist =
3876 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3877#else
3878 req->dv_enhance_exist = 0;
3879#endif
3880 }
3881 spin_unlock_irqrestore(&hw->lock, flags);
3882
3883 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3884 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3885 __func__, type, buf_spec_num, req->aux_size);
3886 }
3887
3888 return 0;
3889}
3890
3891static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3892 u32 index)
3893{
3894 struct canvas_config_s *p_canvas_config;
3895 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3896 force_rate_framebase : force_rate_streambase;
3897 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3898 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3899 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3900
3901 /* signal_type */
3902 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
3903 vf->signal_type = hw->video_signal_from_vui;
3904 if (hw->is_used_v4l) {
3905 struct aml_vdec_hdr_infos hdr;
3906 struct aml_vcodec_ctx *ctx =
3907 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
3908
3909 memset(&hdr, 0, sizeof(hdr));
3910 hdr.signal_type = hw->video_signal_from_vui;
3911 vdec_v4l_set_hdr_infos(ctx, &hdr);
3912 }
3913 } else
3914 vf->signal_type = 0;
3915
3916 vf->width = hw->frame_width;
3917 vf->height = hw->frame_height;
3918 if (force_rate) {
3919 if (force_rate == -1)
3920 vf->duration = 0;
3921 else
3922 vf->duration = 96000/force_rate;
3923 } else
3924 vf->duration = hw->frame_dur;
3925 vf->ratio_control =
3926 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3927 DISP_RATIO_ASPECT_RATIO_BIT;
3928 vf->orientation = hw->vh264_rotation;
3929
3930 if (hw->mmu_enable)
3931 return;
3932
3933 vf->canvas0Addr = vf->canvas1Addr = -1;
3934#ifdef NV21
3935 vf->plane_num = 2;
3936#else
3937 vf->plane_num = 3;
3938#endif
3939
3940 if (IS_VDEC_DW(hw)) {
3941 vf->width = (hw->frame_width /2);
3942 if (IS_VDEC_DW(hw) == 2)
3943 vf->height = (hw->frame_height /2);
3944 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3945 } else
3946 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3947
3948 vf->canvas0_config[0] = p_canvas_config[0];
3949 vf->canvas0_config[1] = p_canvas_config[1];
3950#ifndef NV21
3951 vf->canvas0_config[2] = p_canvas_config[2];
3952#endif
3953 vf->canvas1_config[0] = p_canvas_config[0];
3954 vf->canvas1_config[1] = p_canvas_config[1];
3955#ifndef NV21
3956 vf->canvas1_config[2] = p_canvas_config[2];
3957#endif
3958}
3959
3960static void get_picture_qos_info(struct StorablePicture *picture)
3961{
3962 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3963 unsigned char a[3];
3964 unsigned char i, j, t;
3965 unsigned long data;
3966
3967 get_random_bytes(&data, sizeof(unsigned long));
3968 if (picture->slice_type == I_SLICE)
3969 data = 0;
3970 a[0] = data & 0xff;
3971 a[1] = (data >> 8) & 0xff;
3972 a[2] = (data >> 16) & 0xff;
3973
3974 for (i = 0; i < 3; i++)
3975 for (j = i+1; j < 3; j++) {
3976 if (a[j] < a[i]) {
3977 t = a[j];
3978 a[j] = a[i];
3979 a[i] = t;
3980 } else if (a[j] == a[i]) {
3981 a[i]++;
3982 t = a[j];
3983 a[j] = a[i];
3984 a[i] = t;
3985 }
3986 }
3987 picture->max_mv = a[2];
3988 picture->avg_mv = a[1];
3989 picture->min_mv = a[0];
3990 /*
3991 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3992 data, a[0], a[1], a[2]);
3993 */
3994
3995 get_random_bytes(&data, sizeof(unsigned long));
3996 a[0] = data & 0x1f;
3997 a[1] = (data >> 8) & 0x3f;
3998 a[2] = (data >> 16) & 0x7f;
3999
4000 for (i = 0; i < 3; i++)
4001 for (j = i+1; j < 3; j++) {
4002 if (a[j] < a[i]) {
4003 t = a[j];
4004 a[j] = a[i];
4005 a[i] = t;
4006 } else if (a[j] == a[i]) {
4007 a[i]++;
4008 t = a[j];
4009 a[j] = a[i];
4010 a[i] = t;
4011 }
4012 }
4013 picture->max_qp = a[2];
4014 picture->avg_qp = a[1];
4015 picture->min_qp = a[0];
4016 /*
4017 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4018 data, a[0], a[1], a[2]);
4019 */
4020
4021 get_random_bytes(&data, sizeof(unsigned long));
4022 a[0] = data & 0x1f;
4023 a[1] = (data >> 8) & 0x3f;
4024 a[2] = (data >> 16) & 0x7f;
4025
4026 for (i = 0; i < 3; i++)
4027 for (j = i+1; j < 3; j++) {
4028 if (a[j] < a[i]) {
4029 t = a[j];
4030 a[j] = a[i];
4031 a[i] = t;
4032 } else if (a[j] == a[i]) {
4033 a[i]++;
4034 t = a[j];
4035 a[j] = a[i];
4036 a[i] = t;
4037 }
4038 }
4039 picture->max_skip = a[2];
4040 picture->avg_skip = a[1];
4041 picture->min_skip = a[0];
4042
4043
4044 /*
4045 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4046 data,a[0], a[1], a[2]);
4047 */
4048 } else {
4049 uint32_t blk88_y_count;
4050 uint32_t blk88_c_count;
4051 uint32_t blk22_mv_count;
4052 uint32_t rdata32;
4053 int32_t mv_hi;
4054 int32_t mv_lo;
4055 uint32_t rdata32_l;
4056 uint32_t mvx_L0_hi;
4057 uint32_t mvy_L0_hi;
4058 uint32_t mvx_L1_hi;
4059 uint32_t mvy_L1_hi;
4060 int64_t value;
4061 uint64_t temp_value;
4062/*
4063#define DEBUG_QOS
4064*/
4065#ifdef DEBUG_QOS
4066 int pic_number = picture->poc;
4067#endif
4068
4069 picture->max_mv = 0;
4070 picture->avg_mv = 0;
4071 picture->min_mv = 0;
4072
4073 picture->max_skip = 0;
4074 picture->avg_skip = 0;
4075 picture->min_skip = 0;
4076
4077 picture->max_qp = 0;
4078 picture->avg_qp = 0;
4079 picture->min_qp = 0;
4080
4081
4082
4083
4084
4085 /* set rd_idx to 0 */
4086 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4087 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4088 if (blk88_y_count == 0) {
4089#ifdef DEBUG_QOS
4090 pr_info(" [Picture %d Quality] NO Data yet.\n",
4091 pic_number);
4092#endif
4093 /* reset all counts */
4094 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4095 return;
4096 }
4097 /* qp_y_sum */
4098 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4099#ifdef DEBUG_QOS
4100 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4101 pic_number, rdata32/blk88_y_count,
4102 rdata32, blk88_y_count);
4103#endif
4104 picture->avg_qp = rdata32/blk88_y_count;
4105 /* intra_y_count */
4106 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4107#ifdef DEBUG_QOS
4108 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4109 pic_number, rdata32*100/blk88_y_count,
4110 '%', rdata32);
4111#endif
4112 /* skipped_y_count */
4113 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4114#ifdef DEBUG_QOS
4115 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4116 pic_number, rdata32*100/blk88_y_count,
4117 '%', rdata32);
4118#endif
4119 picture->avg_skip = rdata32*100/blk88_y_count;
4120 /* coeff_non_zero_y_count */
4121 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4122#ifdef DEBUG_QOS
4123 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4124 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4125 '%', rdata32);
4126#endif
4127 /* blk66_c_count */
4128 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4129 if (blk88_c_count == 0) {
4130#ifdef DEBUG_QOS
4131 pr_info(" [Picture %d Quality] NO Data yet.\n",
4132 pic_number);
4133#endif
4134 /* reset all counts */
4135 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4136 return;
4137 }
4138 /* qp_c_sum */
4139 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4140#ifdef DEBUG_QOS
4141 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4142 pic_number, rdata32/blk88_c_count,
4143 rdata32, blk88_c_count);
4144#endif
4145 /* intra_c_count */
4146 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4147#ifdef DEBUG_QOS
4148 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4149 pic_number, rdata32*100/blk88_c_count,
4150 '%', rdata32);
4151#endif
4152 /* skipped_cu_c_count */
4153 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4154#ifdef DEBUG_QOS
4155 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4156 pic_number, rdata32*100/blk88_c_count,
4157 '%', rdata32);
4158#endif
4159 /* coeff_non_zero_c_count */
4160 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4161#ifdef DEBUG_QOS
4162 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4163 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4164 '%', rdata32);
4165#endif
4166
4167 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4168 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4169 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4170#ifdef DEBUG_QOS
4171 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4172 pic_number, (rdata32>>0)&0xff);
4173#endif
4174 picture->min_qp = (rdata32>>0)&0xff;
4175
4176#ifdef DEBUG_QOS
4177 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4178 pic_number, (rdata32>>8)&0xff);
4179#endif
4180 picture->max_qp = (rdata32>>8)&0xff;
4181
4182#ifdef DEBUG_QOS
4183 pr_info(" [Picture %d Quality] C QP min : %d\n",
4184 pic_number, (rdata32>>16)&0xff);
4185 pr_info(" [Picture %d Quality] C QP max : %d\n",
4186 pic_number, (rdata32>>24)&0xff);
4187#endif
4188
4189 /* blk22_mv_count */
4190 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4191 if (blk22_mv_count == 0) {
4192#ifdef DEBUG_QOS
4193 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4194 pic_number);
4195#endif
4196 /* reset all counts */
4197 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4198 return;
4199 }
4200 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4201 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4202 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4203 /* should all be 0x00 or 0xff */
4204#ifdef DEBUG_QOS
4205 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4206 pic_number, rdata32);
4207#endif
4208 mvx_L0_hi = ((rdata32>>0)&0xff);
4209 mvy_L0_hi = ((rdata32>>8)&0xff);
4210 mvx_L1_hi = ((rdata32>>16)&0xff);
4211 mvy_L1_hi = ((rdata32>>24)&0xff);
4212
4213 /* mvx_L0_count[31:0] */
4214 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4215 temp_value = mvx_L0_hi;
4216 temp_value = (temp_value << 32) | rdata32_l;
4217
4218 if (mvx_L0_hi & 0x80)
4219 value = 0xFFFFFFF000000000 | temp_value;
4220 else
4221 value = temp_value;
4222 value = div_s64(value, blk22_mv_count);
4223#ifdef DEBUG_QOS
4224 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4225 pic_number, (int)(value),
4226 value, blk22_mv_count);
4227#endif
4228 picture->avg_mv = value;
4229
4230 /* mvy_L0_count[31:0] */
4231 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4232 temp_value = mvy_L0_hi;
4233 temp_value = (temp_value << 32) | rdata32_l;
4234
4235 if (mvy_L0_hi & 0x80)
4236 value = 0xFFFFFFF000000000 | temp_value;
4237 else
4238 value = temp_value;
4239#ifdef DEBUG_QOS
4240 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4241 pic_number, rdata32_l/blk22_mv_count,
4242 value, blk22_mv_count);
4243#endif
4244
4245 /* mvx_L1_count[31:0] */
4246 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4247 temp_value = mvx_L1_hi;
4248 temp_value = (temp_value << 32) | rdata32_l;
4249 if (mvx_L1_hi & 0x80)
4250 value = 0xFFFFFFF000000000 | temp_value;
4251 else
4252 value = temp_value;
4253#ifdef DEBUG_QOS
4254 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4255 pic_number, rdata32_l/blk22_mv_count,
4256 value, blk22_mv_count);
4257#endif
4258
4259 /* mvy_L1_count[31:0] */
4260 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4261 temp_value = mvy_L1_hi;
4262 temp_value = (temp_value << 32) | rdata32_l;
4263 if (mvy_L1_hi & 0x80)
4264 value = 0xFFFFFFF000000000 | temp_value;
4265 else
4266 value = temp_value;
4267#ifdef DEBUG_QOS
4268 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4269 pic_number, rdata32_l/blk22_mv_count,
4270 value, blk22_mv_count);
4271#endif
4272
4273 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4274 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4275 mv_hi = (rdata32>>16)&0xffff;
4276 if (mv_hi & 0x8000)
4277 mv_hi = 0x8000 - mv_hi;
4278#ifdef DEBUG_QOS
4279 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4280 pic_number, mv_hi);
4281#endif
4282 picture->max_mv = mv_hi;
4283
4284 mv_lo = (rdata32>>0)&0xffff;
4285 if (mv_lo & 0x8000)
4286 mv_lo = 0x8000 - mv_lo;
4287#ifdef DEBUG_QOS
4288 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4289 pic_number, mv_lo);
4290#endif
4291 picture->min_mv = mv_lo;
4292
4293 /* {mvy_L0_max, mvy_L0_min} */
4294 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4295 mv_hi = (rdata32>>16)&0xffff;
4296 if (mv_hi & 0x8000)
4297 mv_hi = 0x8000 - mv_hi;
4298#ifdef DEBUG_QOS
4299 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4300 pic_number, mv_hi);
4301#endif
4302
4303 mv_lo = (rdata32>>0)&0xffff;
4304 if (mv_lo & 0x8000)
4305 mv_lo = 0x8000 - mv_lo;
4306#ifdef DEBUG_QOS
4307 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4308 pic_number, mv_lo);
4309#endif
4310
4311 /* {mvx_L1_max, mvx_L1_min} */
4312 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4313 mv_hi = (rdata32>>16)&0xffff;
4314 if (mv_hi & 0x8000)
4315 mv_hi = 0x8000 - mv_hi;
4316#ifdef DEBUG_QOS
4317 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4318 pic_number, mv_hi);
4319#endif
4320
4321 mv_lo = (rdata32>>0)&0xffff;
4322 if (mv_lo & 0x8000)
4323 mv_lo = 0x8000 - mv_lo;
4324#ifdef DEBUG_QOS
4325 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4326 pic_number, mv_lo);
4327#endif
4328
4329 /* {mvy_L1_max, mvy_L1_min} */
4330 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4331 mv_hi = (rdata32>>16)&0xffff;
4332 if (mv_hi & 0x8000)
4333 mv_hi = 0x8000 - mv_hi;
4334#ifdef DEBUG_QOS
4335 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4336 pic_number, mv_hi);
4337#endif
4338 mv_lo = (rdata32>>0)&0xffff;
4339 if (mv_lo & 0x8000)
4340 mv_lo = 0x8000 - mv_lo;
4341#ifdef DEBUG_QOS
4342 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4343 pic_number, mv_lo);
4344#endif
4345
4346 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4347#ifdef DEBUG_QOS
4348 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4349 pic_number, rdata32);
4350#endif
4351 /* reset all counts */
4352 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4353 }
4354}
4355
4356static int get_max_dec_frame_buf_size(int level_idc,
4357 int max_reference_frame_num, int mb_width,
4358 int mb_height)
4359{
4360 int pic_size = mb_width * mb_height * 384;
4361
4362 int size = 0;
4363
4364 switch (level_idc) {
4365 case 9:
4366 size = 152064;
4367 break;
4368 case 10:
4369 size = 152064;
4370 break;
4371 case 11:
4372 size = 345600;
4373 break;
4374 case 12:
4375 size = 912384;
4376 break;
4377 case 13:
4378 size = 912384;
4379 break;
4380 case 20:
4381 size = 912384;
4382 break;
4383 case 21:
4384 size = 1824768;
4385 break;
4386 case 22:
4387 size = 3110400;
4388 break;
4389 case 30:
4390 size = 3110400;
4391 break;
4392 case 31:
4393 size = 6912000;
4394 break;
4395 case 32:
4396 size = 7864320;
4397 break;
4398 case 40:
4399 size = 12582912;
4400 break;
4401 case 41:
4402 size = 12582912;
4403 break;
4404 case 42:
4405 size = 13369344;
4406 break;
4407 case 50:
4408 size = 42393600;
4409 break;
4410 case 51:
4411 case 52:
4412 default:
4413 size = 70778880;
4414 break;
4415 }
4416
4417 size /= pic_size;
4418 size = size + 1; /* need one more buffer */
4419
4420 if (max_reference_frame_num > size)
4421 size = max_reference_frame_num;
4422 size = imin(size, 16);
4423
4424 return size;
4425}
4426
4427static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4428{
4429 int i, j;
4430
4431 if (hw->double_write_mode) {
4432 mutex_lock(&vmh264_mutex);
4433 if (hw->decode_pic_count == 0) {
4434 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4435 i = get_buf_spec_by_canvas_pos(hw, j);
4436 if (i >= 0)
4437 config_decode_canvas_ex(hw, i);
4438 }
4439 }
4440 mutex_unlock(&vmh264_mutex);
4441 }
4442}
4443
4444static int vh264_set_params(struct vdec_h264_hw_s *hw,
4445 u32 param1, u32 param2, u32 param3, u32 param4)
4446{
4447 int i, j;
4448 int mb_width, mb_total;
4449 int max_reference_size, level_idc;
4450 int mb_height = 0;
4451 unsigned long flags;
4452 /*int mb_mv_byte;*/
4453 struct vdec_s *vdec = hw_to_vdec(hw);
4454 u32 seq_info2;
4455 int ret = 0;
4456 int active_buffer_spec_num;
4457 unsigned int buf_size;
4458 unsigned int frame_mbs_only_flag;
4459 unsigned int chroma_format_idc, chroma444;
4460 unsigned int crop_infor, crop_bottom, crop_right;
4461 unsigned int used_reorder_dpb_size_margin
4462 = hw->reorder_dpb_size_margin;
4463 u8 *colocate_vaddr = NULL;
4464
4465#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4466 if (vdec->master || vdec->slave)
4467 used_reorder_dpb_size_margin =
4468 reorder_dpb_size_margin_dv;
4469#endif
4470 seq_info2 = param1;
4471 hw->seq_info = param2;
4472
4473 mb_width = seq_info2 & 0xff;
4474 mb_total = (seq_info2 >> 8) & 0xffff;
4475 if (!mb_width && mb_total) /*for 4k2k*/
4476 mb_width = 256;
4477 if (mb_width)
4478 mb_height = mb_total/mb_width;
4479 if (mb_width <= 0 || mb_height <= 0 ||
4480 is_oversize(mb_width << 4, mb_height << 4)) {
4481 dpb_print(DECODE_ID(hw), 0,
4482 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4483 seq_info2,
4484 mb_width,
4485 mb_height);
4486 return -1;
4487 }
4488
4489 if (seq_info2 != 0 &&
4490 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4491 hw->seq_info2 != 0
4492 ) /*picture size changed*/
4493 h264_reconfig(hw);
4494
4495 if (hw->config_bufmgr_done == 0) {
4496 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4497 u32 reg_val;
4498 hw->cfg_param1 = param1;
4499 hw->cfg_param2 = param2;
4500 hw->cfg_param3 = param3;
4501 hw->cfg_param4 = param4;
4502
4503 hw->seq_info2 = seq_info2 & (~0x80000000);
4504 dpb_print(DECODE_ID(hw), 0,
4505 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4506 seq_info2, hw->seq_info);
4507
4508 dpb_init_global(&hw->dpb,
4509 DECODE_ID(hw), 0, 0);
4510
4511 p_H264_Dpb->fast_output_enable = fast_output_enable;
4512 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4513
4514#if 1
4515 /*crop*/
4516 /* AV_SCRATCH_2
4517 bit 15: frame_mbs_only_flag
4518 bit 13-14: chroma_format_idc */
4519 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4520 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4521 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4522
4523 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4524 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4525 (2 - frame_mbs_only_flag) */
4526 crop_infor = param3;
4527 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4528 crop_right = ((crop_infor >> 16) & 0xff)
4529 >> (2 - frame_mbs_only_flag);
4530
4531 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4532 hw->frame_width = mb_width << 4;
4533 hw->frame_height = mb_height << 4;
4534 if (frame_mbs_only_flag) {
4535 hw->frame_height =
4536 hw->frame_height - (2 >> chroma444) *
4537 min(crop_bottom,
4538 (unsigned int)((8 << chroma444) - 1));
4539 hw->frame_width =
4540 hw->frame_width -
4541 (2 >> chroma444) * min(crop_right,
4542 (unsigned
4543 int)((8 << chroma444) - 1));
4544 } else {
4545 hw->frame_height =
4546 hw->frame_height - (4 >> chroma444) *
4547 min(crop_bottom,
4548 (unsigned int)((8 << chroma444)
4549 - 1));
4550 hw->frame_width =
4551 hw->frame_width -
4552 (4 >> chroma444) * min(crop_right,
4553 (unsigned int)((8 << chroma444) - 1));
4554 }
4555 dpb_print(DECODE_ID(hw), 0,
4556 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4557 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4558 dpb_print(DECODE_ID(hw), 0,
4559 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4560 mb_height, crop_right,
4561 hw->frame_width, mb_width);
4562
4563 if (hw->frame_height == 1088)
4564 hw->frame_height = 1080;
4565#endif
4566 if (!hw->mmu_enable) {
4567 mb_width = (mb_width+3) & 0xfffffffc;
4568 mb_height = (mb_height+3) & 0xfffffffc;
4569 }
4570 mb_total = mb_width * mb_height;
4571 hw->mb_width = mb_width;
4572 hw->mb_height = mb_height;
4573 hw->mb_total = mb_total;
4574 if (hw->mmu_enable)
4575 hevc_mcr_sao_global_hw_init(hw,
4576 (hw->mb_width << 4), (hw->mb_height << 4));
4577
4578 reg_val = param4;
4579 level_idc = reg_val & 0xff;
4580 max_reference_size = (reg_val >> 8) & 0xff;
4581 hw->dpb.origin_max_reference = max_reference_size;
4582 dpb_print(DECODE_ID(hw), 0,
4583 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4584 mb_height, mb_width, mb_total,
4585 level_idc, max_reference_size);
4586
4587
4588 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4589 hw->dpb.reorder_pic_num =
4590 get_max_dec_frame_buf_size(level_idc,
4591 max_reference_size, mb_width, mb_height);
4592
4593 dpb_print(DECODE_ID(hw), 0,
4594 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4595 hw->bitstream_restriction_flag,
4596 hw->max_dec_frame_buffering,
4597 hw->dpb.reorder_pic_num);
4598
4599 if ((hw->bitstream_restriction_flag) &&
4600 (hw->max_dec_frame_buffering <
4601 hw->dpb.reorder_pic_num)) {
4602 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4603 dpb_print(DECODE_ID(hw), 0,
4604 "set reorder_pic_num to %d\n",
4605 hw->dpb.reorder_pic_num);
4606 }
4607
4608 active_buffer_spec_num =
4609 hw->dpb.reorder_pic_num
4610 + used_reorder_dpb_size_margin;
4611 hw->max_reference_size =
4612 max_reference_size + reference_buf_margin;
4613
4614 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4615 active_buffer_spec_num = MAX_VF_BUF_NUM;
4616 hw->dpb.reorder_pic_num = active_buffer_spec_num
4617 - used_reorder_dpb_size_margin;
4618 }
4619 hw->dpb.mDPB.size = active_buffer_spec_num;
4620 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4621 hw->max_reference_size = MAX_VF_BUF_NUM;
4622 hw->dpb.max_reference_size = hw->max_reference_size;
4623
4624 if (hw->no_poc_reorder_flag)
4625 hw->dpb.reorder_pic_num = 1;
4626 dpb_print(DECODE_ID(hw), 0,
4627 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4628 __func__, active_buffer_spec_num,
4629 hw->dpb.reorder_pic_num,
4630 hw->max_reference_size);
4631
4632 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4633
4634 mutex_lock(&vmh264_mutex);
4635 if (!hw->mmu_enable) {
4636 config_buf_specs(vdec);
4637 i = get_buf_spec_by_canvas_pos(hw, 0);
4638
4639 if (hw->is_used_v4l) {
4640 if (i != -1) {
4641 pr_info("v4l: delay alloc the buffer.\n");
4642 }
4643 } else {
4644 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4645 config_decode_canvas(hw, i);
4646 else
4647 ret = -1;
4648 }
4649 } else {
4650 if (hw->double_write_mode) {
4651 config_buf_specs_ex(vdec);
4652 } else {
4653 spin_lock_irqsave(&hw->bufspec_lock, flags);
4654 for (i = 0, j = 0;
4655 j < active_buffer_spec_num
4656 && i < BUFSPEC_POOL_SIZE;
4657 i++) {
4658 if (hw->buffer_spec[i].used != -1)
4659 continue;
4660 hw->buffer_spec[i].used = 0;
4661 hw->buffer_spec[i].
4662 alloc_header_addr = 0;
4663 hw->buffer_spec[i].canvas_pos = j;
4664 j++;
4665 }
4666 spin_unlock_irqrestore(&hw->bufspec_lock,
4667 flags);
4668 }
4669 hevc_mcr_config_canv2axitbl(hw, 0);
4670 }
4671 mutex_unlock(&vmh264_mutex);
4672 if (dpb_is_debug(DECODE_ID(hw),
4673 PRINT_FLAG_DUMP_BUFSPEC))
4674 dump_bufspec(hw, __func__);
4675
4676#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4677 buf_size = PAGE_ALIGN(
4678 p_H264_Dpb->colocated_buf_size *
4679 active_buffer_spec_num);
4680#else
4681 buf_size = PAGE_ALIGN(
4682 p_H264_Dpb->colocated_buf_size *
4683 hw->max_reference_size);
4684#endif
4685
4686 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4687 buf_size, DRIVER_NAME,
4688 &hw->collocate_cma_alloc_addr) < 0)
4689 return -1;
4690 if (!vdec_secure(vdec)) {
4691 /* clear for some mosaic problem after reset bufmgr */
4692 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4693 if (colocate_vaddr != NULL) {
4694 memset(colocate_vaddr, 0, buf_size);
4695 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4696 codec_mm_unmap_phyaddr(colocate_vaddr);
4697 }
4698 }
4699
4700 hw->dpb.colocated_mv_addr_start =
4701 hw->collocate_cma_alloc_addr;
4702#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4703 hw->dpb.colocated_mv_addr_end =
4704 hw->dpb.colocated_mv_addr_start +
4705 (p_H264_Dpb->colocated_buf_size *
4706 active_buffer_spec_num);
4707#else
4708 hw->dpb.colocated_mv_addr_end =
4709 hw->dpb.colocated_mv_addr_start +
4710 (p_H264_Dpb->colocated_buf_size *
4711 hw->max_reference_size);
4712#endif
4713 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4714 "callocate cma, %lx, %x\n",
4715 hw->collocate_cma_alloc_addr,
4716 hw->dpb.colocated_mv_addr_start);
4717
4718 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4719 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4720 hw->dpb.colocated_mv_addr_start,
4721 hw->dpb.colocated_mv_addr_end);
4722 if (!hw->mmu_enable) {
4723 mutex_lock(&vmh264_mutex);
4724 if (ret >= 0 && hw->decode_pic_count == 0) {
4725 int buf_cnt;
4726 /* h264_reconfig: alloc later*/
4727 buf_cnt = hw->dpb.mDPB.size;
4728
4729 for (j = 1; j < buf_cnt; j++) {
4730 i = get_buf_spec_by_canvas_pos(hw, j);
4731
4732 if (hw->is_used_v4l) {
4733 pr_info("v4l: delay alloc the buffer.\n");
4734 break;
4735 } else if (alloc_one_buf_spec(hw, i) < 0)
4736 break;
4737
4738 config_decode_canvas(hw, i);
4739 }
4740 }
4741 mutex_unlock(&vmh264_mutex);
4742 } else {
4743 vh264_config_canvs_for_mmu(hw);
4744 }
4745
4746 hw->config_bufmgr_done = 1;
4747
4748 /*end of config_bufmgr_done */
4749 }
4750
4751 return ret;
4752}
4753
4754static void vui_config(struct vdec_h264_hw_s *hw)
4755{
4756 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4757 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4758 /*time*/
4759 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4760 hw->time_scale = p_H264_Dpb->time_scale;
4761 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4762
4763 hw->bitstream_restriction_flag =
4764 p_H264_Dpb->bitstream_restriction_flag;
4765 hw->num_reorder_frames =
4766 p_H264_Dpb->num_reorder_frames;
4767 hw->max_dec_frame_buffering =
4768 p_H264_Dpb->max_dec_frame_buffering;
4769
4770 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4771 "vui_config: pdb %d, %d, %d\n",
4772 p_H264_Dpb->bitstream_restriction_flag,
4773 p_H264_Dpb->num_reorder_frames,
4774 p_H264_Dpb->max_dec_frame_buffering);
4775
4776 hw->fixed_frame_rate_flag = 0;
4777 if (hw->timing_info_present_flag) {
4778 hw->fixed_frame_rate_flag =
4779 p_H264_Dpb->fixed_frame_rate_flag;
4780
4781 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4782 ((!hw->sync_outside) ||
4783 (!hw->frame_dur)))
4784 && hw->num_units_in_tick && hw->time_scale) {
4785 if (hw->use_idr_framerate ||
4786 hw->fixed_frame_rate_flag ||
4787 !hw->frame_dur ||
4788 !hw->duration_from_pts_done
4789 /*|| vh264_running*/) {
4790 u32 frame_dur_es =
4791 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4792 hw->time_scale);
4793 if (hw->frame_dur != frame_dur_es) {
4794 hw->h264_first_valid_pts_ready = false;
4795 hw->h264pts1 = 0;
4796 hw->h264pts2 = 0;
4797 hw->h264_pts_count = 0;
4798 hw->duration_from_pts_done = 0;
4799 fixed_frame_rate_mode =
4800 FIX_FRAME_RATE_OFF;
4801 hw->pts_duration = 0;
4802 hw->frame_dur = frame_dur_es;
4803 vdec_schedule_work(&hw->notify_work);
4804 dpb_print(DECODE_ID(hw),
4805 PRINT_FLAG_DEC_DETAIL,
4806 "frame_dur %d from timing_info\n",
4807 hw->frame_dur);
4808 }
4809
4810 /*hack to avoid use ES frame duration when
4811 *it's half of the rate from system info
4812 * sometimes the encoder is given a wrong
4813 * frame rate but the system side information
4814 * is more reliable
4815 *if ((frame_dur * 2) != frame_dur_es) {
4816 * frame_dur = frame_dur_es;
4817 *}
4818 */
4819 }
4820 }
4821 } else {
4822 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4823 "H.264: timing_info not present\n");
4824 }
4825
4826 /*aspect ratio*/
4827 aspect_ratio_info_present_flag =
4828 p_H264_Dpb->vui_status & 0x1;
4829 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4830
4831 if (aspect_ratio_info_present_flag) {
4832 if (aspect_ratio_idc == EXTEND_SAR) {
4833 hw->h264_ar = 0x3ff;
4834 hw->height_aspect_ratio =
4835 p_H264_Dpb->aspect_ratio_sar_height;
4836 hw->width_aspect_ratio =
4837 p_H264_Dpb->aspect_ratio_sar_width;
4838 } else {
4839 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4840 aspect_ratio_idc); */
4841
4842 switch (aspect_ratio_idc) {
4843 case 1:
4844 hw->h264_ar = 0x3ff;
4845 hw->height_aspect_ratio = 1;
4846 hw->width_aspect_ratio = 1;
4847 break;
4848 case 2:
4849 hw->h264_ar = 0x3ff;
4850 hw->height_aspect_ratio = 11;
4851 hw->width_aspect_ratio = 12;
4852 break;
4853 case 3:
4854 hw->h264_ar = 0x3ff;
4855 hw->height_aspect_ratio = 11;
4856 hw->width_aspect_ratio = 10;
4857 break;
4858 case 4:
4859 hw->h264_ar = 0x3ff;
4860 hw->height_aspect_ratio = 11;
4861 hw->width_aspect_ratio = 16;
4862 break;
4863 case 5:
4864 hw->h264_ar = 0x3ff;
4865 hw->height_aspect_ratio = 33;
4866 hw->width_aspect_ratio = 40;
4867 break;
4868 case 6:
4869 hw->h264_ar = 0x3ff;
4870 hw->height_aspect_ratio = 11;
4871 hw->width_aspect_ratio = 24;
4872 break;
4873 case 7:
4874 hw->h264_ar = 0x3ff;
4875 hw->height_aspect_ratio = 11;
4876 hw->width_aspect_ratio = 20;
4877 break;
4878 case 8:
4879 hw->h264_ar = 0x3ff;
4880 hw->height_aspect_ratio = 11;
4881 hw->width_aspect_ratio = 32;
4882 break;
4883 case 9:
4884 hw->h264_ar = 0x3ff;
4885 hw->height_aspect_ratio = 33;
4886 hw->width_aspect_ratio = 80;
4887 break;
4888 case 10:
4889 hw->h264_ar = 0x3ff;
4890 hw->height_aspect_ratio = 11;
4891 hw->width_aspect_ratio = 18;
4892 break;
4893 case 11:
4894 hw->h264_ar = 0x3ff;
4895 hw->height_aspect_ratio = 11;
4896 hw->width_aspect_ratio = 15;
4897 break;
4898 case 12:
4899 hw->h264_ar = 0x3ff;
4900 hw->height_aspect_ratio = 33;
4901 hw->width_aspect_ratio = 64;
4902 break;
4903 case 13:
4904 hw->h264_ar = 0x3ff;
4905 hw->height_aspect_ratio = 99;
4906 hw->width_aspect_ratio = 160;
4907 break;
4908 case 14:
4909 hw->h264_ar = 0x3ff;
4910 hw->height_aspect_ratio = 3;
4911 hw->width_aspect_ratio = 4;
4912 break;
4913 case 15:
4914 hw->h264_ar = 0x3ff;
4915 hw->height_aspect_ratio = 2;
4916 hw->width_aspect_ratio = 3;
4917 break;
4918 case 16:
4919 hw->h264_ar = 0x3ff;
4920 hw->height_aspect_ratio = 1;
4921 hw->width_aspect_ratio = 2;
4922 break;
4923 default:
4924 if (hw->vh264_ratio >> 16) {
4925 hw->h264_ar = (hw->frame_height *
4926 (hw->vh264_ratio & 0xffff) *
4927 0x100 +
4928 ((hw->vh264_ratio >> 16) *
4929 hw->frame_width / 2)) /
4930 ((hw->vh264_ratio >> 16) *
4931 hw->frame_width);
4932 hw->height_aspect_ratio = 1;
4933 hw->width_aspect_ratio = 1;
4934 } else {
4935 hw->h264_ar = 0x3ff;
4936 hw->height_aspect_ratio = 1;
4937 hw->width_aspect_ratio = 1;
4938 }
4939 break;
4940 }
4941 }
4942 } else {
4943 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4944 "v264dec: aspect_ratio not available from source\n");
4945 if (hw->vh264_ratio >> 16) {
4946 /* high 16 bit is width, low 16 bit is height */
4947 hw->h264_ar =
4948 ((hw->vh264_ratio & 0xffff) *
4949 hw->frame_height * 0x100 +
4950 (hw->vh264_ratio >> 16) *
4951 hw->frame_width / 2) /
4952 ((hw->vh264_ratio >> 16) *
4953 hw->frame_width);
4954 hw->height_aspect_ratio = 1;
4955 hw->width_aspect_ratio = 1;
4956 } else {
4957 hw->h264_ar = 0x3ff;
4958 hw->height_aspect_ratio = 1;
4959 hw->width_aspect_ratio = 1;
4960 }
4961 }
4962
4963 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4964 if (((hw->frame_dur == RATE_2397_FPS)
4965 && (dec_control
4966 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4967 || ((RATE_2997_FPS ==
4968 hw->frame_dur) &&
4969 (dec_control &
4970 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4971 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4972 "force fix frame rate\n");
4973 hw->fixed_frame_rate_flag = 0x40;
4974 }
4975 }
4976
4977 /*video_signal_from_vui: to do .. */
4978}
4979
4980static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4981{
4982 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4983
4984 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4985 if (error_proc_policy & 0x20) {
4986 if (!hw->is_used_v4l)
4987 hw->reset_bufmgr_flag = 1;
4988 }
4989}
4990
4991void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4992{
4993 struct vdec_h264_hw_s *hw =
4994 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4995
4996 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4997
4998 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4999 hw->reset_bufmgr_flag = 1;
5000}
5001
5002#ifdef CONSTRAIN_MAX_BUF_NUM
5003static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5004{
5005 int i;
5006 int count = 0;
5007 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5008 if (is_buf_spec_in_disp_q(hw, i) &&
5009 hw->buffer_spec[i].vf_ref > 0)
5010 count++;
5011 }
5012 return count;
5013}
5014
5015static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5016{
5017 int i;
5018 int count = 0;
5019 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5020 if (is_buf_spec_in_use(hw, i))
5021 count++;
5022 }
5023 return count;
5024}
5025#endif
5026
5027
5028static bool is_buffer_available(struct vdec_s *vdec)
5029{
5030 bool buffer_available = 1;
5031 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5032 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5033 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5034 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5035 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5036 ((p_H264_Dpb->mDPB.init_done) &&
5037 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5038 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5039 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5040 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5041 __func__,
5042 kfifo_len(&hw->newframe_q),
5043 have_free_buf_spec(vdec),
5044 p_H264_Dpb->mDPB.init_done,
5045 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5046 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5047 );
5048 buffer_available = 0;
5049 if (dpb_is_debug(DECODE_ID(hw),
5050 DEBUG_DISABLE_RUNREADY_RMBUF))
5051 return buffer_available;
5052
5053 if ((error_proc_policy & 0x4) &&
5054 (error_proc_policy & 0x8)) {
5055 if ((kfifo_len(&hw->display_q) <= 0) &&
5056 (p_H264_Dpb->mDPB.used_size ==
5057 p_H264_Dpb->mDPB.size) &&
5058 (p_Dpb->ref_frames_in_buffer >
5059 (imax(
5060 1, p_Dpb->num_ref_frames)
5061 - p_Dpb->ltref_frames_in_buffer +
5062 force_sliding_margin)))
5063 bufmgr_recover(hw);
5064 else
5065 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5066 } else if ((error_proc_policy & 0x4) &&
5067 (kfifo_len(&hw->display_q) <= 0) &&
5068 ((p_H264_Dpb->mDPB.used_size ==
5069 p_H264_Dpb->mDPB.size) ||
5070 (!have_free_buf_spec(vdec)))) {
5071 enum receviver_start_e state = RECEIVER_INACTIVE;
5072 if ((error_proc_policy & 0x10) &&
5073 vf_get_receiver(vdec->vf_provider_name)) {
5074 state =
5075 vf_notify_receiver(vdec->vf_provider_name,
5076 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5077 NULL);
5078 if ((state == RECEIVER_STATE_NULL)
5079 || (state == RECEIVER_STATE_NONE))
5080 state = RECEIVER_INACTIVE;
5081 }
5082 if (state == RECEIVER_INACTIVE)
5083 bufmgr_recover(hw);
5084 else
5085 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5086 } else if ((error_proc_policy & 0x8) &&
5087 (p_Dpb->ref_frames_in_buffer >
5088 (imax(
5089 1, p_Dpb->num_ref_frames)
5090 - p_Dpb->ltref_frames_in_buffer +
5091 force_sliding_margin)))
5092 bufmgr_recover(hw);
5093 else
5094 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5095
5096 if (hw->reset_bufmgr_flag == 1)
5097 buffer_available = 1;
5098 }
5099
5100 return buffer_available;
5101}
5102
5103#define AUX_TAG_SEI 0x2
5104
5105#define SEI_BUFFERING_PERIOD 0
5106#define SEI_PicTiming 1
5107#define SEI_USER_DATA 4
5108#define SEI_RECOVERY_POINT 6
5109
5110/*
5111 *************************************************************************
5112 * Function:Reads bits from the bitstream buffer
5113 * Input:
5114 byte buffer[]
5115 containing sei message data bits
5116 int totbitoffset
5117 bit offset from start of partition
5118 int bytecount
5119 total bytes in bitstream
5120 int numbits
5121 number of bits to read
5122 * Output:
5123 int *info
5124 * Return:
5125 -1: failed
5126 > 0: the count of bit read
5127 * Attention:
5128 *************************************************************************
5129 */
5130
5131static int get_bits(unsigned char buffer[],
5132 int totbitoffset,
5133 int *info,
5134 int bytecount,
5135 int numbits)
5136{
5137 register int inf;
5138 long byteoffset;
5139 int bitoffset;
5140
5141 int bitcounter = numbits;
5142
5143 byteoffset = totbitoffset / 8;
5144 bitoffset = 7 - (totbitoffset % 8);
5145
5146 inf = 0;
5147 while (numbits) {
5148 inf <<= 1;
5149 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5150 numbits--;
5151 bitoffset--;
5152 if (bitoffset < 0) {
5153 byteoffset++;
5154 bitoffset += 8;
5155 if (byteoffset > bytecount)
5156 return -1;
5157 }
5158 }
5159
5160 *info = inf;
5161
5162
5163 return bitcounter;
5164}
5165
5166static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5167 u8 *sei_data_buf,
5168 u8 *sei_data_buf_end)
5169{
5170 int payload_type;
5171 int payload_size;
5172 u8 *p_sei;
5173 int temp = 0;
5174 int bit_offset;
5175 int read_size;
5176 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5177
5178 p_sei = sei_data_buf;
5179 read_size = 0;
5180 payload_type = 0;
5181 do {
5182 if (p_sei >= sei_data_buf_end)
5183 return read_size;
5184
5185 payload_type += *p_sei;
5186 read_size++;
5187 } while (*p_sei++ == 255);
5188
5189
5190 payload_size = 0;
5191 do {
5192 if (p_sei >= sei_data_buf_end)
5193 return read_size;
5194
5195 payload_size += *p_sei;
5196 read_size++;
5197 } while (*p_sei++ == 255);
5198
5199
5200 if (p_sei + payload_size > sei_data_buf_end) {
5201 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5202 "%s: payload_type = %d, payload_size = %d is over\n",
5203 __func__, payload_type, payload_size);
5204 return read_size;
5205 }
5206 bit_offset = 0;
5207
5208 if (payload_size <= 0) {
5209 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5210 "%s warning: this is a null sei message for payload_type = %d\n",
5211 __func__, payload_type);
5212 return read_size;
5213 }
5214 switch (payload_type) {
5215 case SEI_BUFFERING_PERIOD:
5216 break;
5217 case SEI_PicTiming:
5218 if (p_H264_Dpb->vui_status & 0xc) {
5219 int cpb_removal_delay;
5220 int dpb_output_delay;
5221 u32 delay_len;
5222
5223 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5224 cpb_removal_delay
5225 = (delay_len & 0x1F) + 1;
5226 dpb_output_delay
5227 = ((delay_len >> 5) & 0x1F) + 1;
5228
5229 get_bits(p_sei, bit_offset,
5230 &temp, payload_size,
5231 dpb_output_delay+cpb_removal_delay);
5232 bit_offset += dpb_output_delay+cpb_removal_delay;
5233 }
5234 if (p_H264_Dpb->vui_status & 0x10) {
5235 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5236 bit_offset += 4;
5237 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5238 }
5239 break;
5240 case SEI_USER_DATA:
5241 if (enable_itu_t35) {
5242 int i;
5243 int j;
5244 int data_len;
5245 u8 *user_data_buf;
5246
5247 user_data_buf
5248 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5249 /* user data length should be align with 8 bytes,
5250 if not, then padding with zero*/
5251 for (i = 0; i < payload_size; i += 8) {
5252 for (j = 0; j < 8; j++) {
5253 int index;
5254
5255 index = i+7-j;
5256 if (index >= payload_size)
5257 user_data_buf[i+j] = 0;
5258 else
5259 user_data_buf[i+j]
5260 = p_sei[i+7-j];
5261 }
5262 }
5263
5264 data_len = payload_size;
5265 if (payload_size % 8)
5266 data_len = ((payload_size + 8) >> 3) << 3;
5267
5268 hw->sei_itu_data_len += data_len;
5269 /*
5270 dpb_print(DECODE_ID(hw), 0,
5271 "%s: user data, and len = %d:\n",
5272 __func__, hw->sei_itu_data_len);
5273 */
5274 }
5275 break;
5276 case SEI_RECOVERY_POINT:
5277 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5278 break;
5279 }
5280
5281 return read_size + payload_size;
5282}
5283
5284static void parse_sei_data(struct vdec_h264_hw_s *hw,
5285 u8 *sei_data_buf,
5286 int len)
5287{
5288 char *p_sei;
5289 char *p_sei_end;
5290 int parsed_size;
5291 int read_size;
5292
5293
5294 p_sei = sei_data_buf;
5295 p_sei_end = p_sei + len;
5296 parsed_size = 0;
5297 while (parsed_size < len) {
5298 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5299 p_sei += read_size;
5300 parsed_size += read_size;
5301 if (*p_sei == 0x80) {
5302 p_sei++;
5303 parsed_size++;
5304 }
5305 }
5306}
5307
5308static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5309{
5310 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5311 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5312 unsigned mby_mbx = READ_VREG(MBY_MBX);
5313 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5314 unsigned decode_mb_count =
5315 ((mby_mbx & 0xff) * hw->mb_width +
5316 (((mby_mbx >> 8) & 0xff) + 1));
5317 if (mby_mbx == 0)
5318 return;
5319 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5320 mb_total /= 2;
5321 if (error_proc_policy & 0x100) {
5322 if (decode_mb_count < mb_total)
5323 p->data_flag |= ERROR_FLAG;
5324 }
5325
5326 if ((error_proc_policy & 0x200) &&
5327 READ_VREG(ERROR_STATUS_REG) != 0) {
5328 p->data_flag |= ERROR_FLAG;
5329 }
5330
5331 if (p->data_flag & ERROR_FLAG) {
5332 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5333 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5334 __func__,
5335 hw->seq_info2,
5336 mby_mbx,
5337 mb_total,
5338 decode_mb_count,
5339 READ_VREG(ERROR_STATUS_REG)
5340 );
5341
5342 }
5343}
5344
5345static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5346{
5347 int i;
5348 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5349 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5350 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5351 u32 debug_tag;
5352 int ret;
5353
5354 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5355#if 1
5356 unsigned short *p = (unsigned short *)hw->lmem_addr;
5357 dma_sync_single_for_cpu(
5358 amports_get_dma_device(),
5359 hw->lmem_addr_remap,
5360 PAGE_SIZE,
5361 DMA_FROM_DEVICE);
5362 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5363 int ii;
5364 for (ii = 0; ii < 4; ii++) {
5365 p_H264_Dpb->dpb_param.l.data[i+ii] =
5366 p[i+3-ii];
5367 if (dpb_is_debug(DECODE_ID(hw),
5368 RRINT_FLAG_RPM)) {
5369 if (((i + ii) & 0xf) == 0)
5370 dpb_print(DECODE_ID(hw),
5371 0, "%04x:",
5372 i);
5373 dpb_print_cont(DECODE_ID(hw),
5374 0, "%04x ",
5375 p[i+3-ii]);
5376 if (((i + ii + 1) & 0xf) == 0)
5377 dpb_print_cont(
5378 DECODE_ID(hw),
5379 0, "\r\n");
5380 }
5381 }
5382 }
5383
5384 p_H264_Dpb->bitstream_restriction_flag =
5385 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5386 p_H264_Dpb->num_reorder_frames =
5387 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5388 p_H264_Dpb->max_dec_frame_buffering =
5389 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5390
5391 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5392 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5393 p_H264_Dpb->bitstream_restriction_flag,
5394 p_H264_Dpb->num_reorder_frames,
5395 p_H264_Dpb->max_dec_frame_buffering);
5396 hw->bitstream_restriction_flag =
5397 p_H264_Dpb->bitstream_restriction_flag;
5398 hw->num_reorder_frames =
5399 p_H264_Dpb->num_reorder_frames;
5400 hw->max_dec_frame_buffering =
5401 p_H264_Dpb->max_dec_frame_buffering;
5402#endif
5403
5404 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5405 reset_process_time(hw);
5406 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5407 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5408 vdec_schedule_work(&hw->work);
5409 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5410 u16 data_hight;
5411 u16 data_low;
5412 u32 video_signal;
5413
5414 int slice_header_process_status = 0;
5415 int I_flag;
5416 /*unsigned char is_idr;*/
5417 unsigned short *p = (unsigned short *)hw->lmem_addr;
5418 reset_process_time(hw);
5419
5420 if (hw->is_used_v4l) {
5421 struct aml_vcodec_ctx *ctx =
5422 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5423
5424 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5425 //amvdec_stop();
5426 hw->dec_result = DEC_RESULT_DONE;
5427 vdec_schedule_work(&hw->work);
5428 return IRQ_HANDLED;
5429 }
5430 }
5431
5432 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5433 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5434 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5435 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5436 if (input_frame_based(vdec) &&
5437 frmbase_cont_bitlevel2 != 0 &&
5438 READ_VREG(VIFF_BIT_CNT) <
5439 frmbase_cont_bitlevel2 &&
5440 hw->get_data_count >= 0x70000000) {
5441 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5442 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5443 __func__,
5444 READ_VREG(VIFF_BIT_CNT));
5445
5446 goto empty_proc;
5447 }
5448
5449 dma_sync_single_for_cpu(
5450 amports_get_dma_device(),
5451 hw->lmem_addr_remap,
5452 PAGE_SIZE,
5453 DMA_FROM_DEVICE);
5454#if 0
5455 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5456 if (!is_buffer_available(vdec)) {
5457 hw->buffer_empty_flag = 1;
5458 dpb_print(DECODE_ID(hw),
5459 PRINT_FLAG_UCODE_EVT,
5460 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5461 __func__,
5462 kfifo_len(&hw->newframe_q),
5463 have_free_buf_spec(vdec),
5464 p_H264_Dpb->mDPB.init_done,
5465 p_H264_Dpb->mDPB.used_size,
5466 p_H264_Dpb->mDPB.size,
5467 is_there_unused_frame_from_dpb(
5468 &p_H264_Dpb->mDPB));
5469 return IRQ_HANDLED;
5470 }
5471 }
5472
5473 hw->buffer_empty_flag = 0;
5474#endif
5475#ifdef SEND_PARAM_WITH_REG
5476 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5477 unsigned int data32;
5478
5479 do {
5480 data32 = READ_VREG(RPM_CMD_REG);
5481 /* printk("%x\n", data32); */
5482 } while ((data32&0x10000) == 0);
5483 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5484 WRITE_VREG(RPM_CMD_REG, 0);
5485 /* printk("%x:%x\n", i,data32); */
5486 }
5487#else
5488 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5489 int ii;
5490
5491 for (ii = 0; ii < 4; ii++) {
5492 p_H264_Dpb->dpb_param.l.data[i+ii] =
5493 p[i+3-ii];
5494 if (dpb_is_debug(DECODE_ID(hw),
5495 RRINT_FLAG_RPM)) {
5496 if (((i + ii) & 0xf) == 0)
5497 dpb_print(DECODE_ID(hw),
5498 0, "%04x:",
5499 i);
5500 dpb_print_cont(DECODE_ID(hw),
5501 0, "%04x ",
5502 p[i+3-ii]);
5503 if (((i + ii + 1) & 0xf) == 0)
5504 dpb_print_cont(
5505 DECODE_ID(hw),
5506 0, "\r\n");
5507 }
5508 }
5509 }
5510#endif
5511 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5512 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5513
5514 video_signal = (data_hight << 16) | data_low;
5515 hw->video_signal_from_vui =
5516 ((video_signal & 0xffff) << 8) |
5517 ((video_signal & 0xff0000) >> 16) |
5518 ((video_signal & 0x3f000000));
5519
5520
5521 /*dpb_print(DECODE_ID(hw),
5522 0,
5523 "video_signal_from_vui:0x%x, "
5524 "data_low:0x%x, data_hight:0x%x\n",
5525 hw->video_signal_from_vui,
5526 data_low,
5527 data_hight);*/
5528
5529 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5530
5531 if (hw->config_bufmgr_done == 0) {
5532 hw->dec_result = DEC_RESULT_DONE;
5533 vdec_schedule_work(&hw->work);
5534 dpb_print(DECODE_ID(hw),
5535 PRINT_FLAG_UCODE_EVT,
5536 "config_bufmgr not done, discard frame\n");
5537 return IRQ_HANDLED;
5538 } else if ((hw->first_i_policy & 0x3) != 0) {
5539 unsigned char is_i_slice =
5540 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5541 == I_Slice)
5542 ? 1 : 0;
5543 unsigned char is_idr =
5544 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5545 == 5);
5546 if ((hw->first_i_policy & 0x3) == 0x3)
5547 is_i_slice = is_idr;
5548 if (!is_i_slice) {
5549 if (hw->has_i_frame == 0) {
5550 amvdec_stop();
5551 vdec->mc_loaded = 0;
5552 hw->dec_result = DEC_RESULT_DONE;
5553 vdec_schedule_work(&hw->work);
5554 dpb_print(DECODE_ID(hw),
5555 PRINT_FLAG_UCODE_EVT,
5556 "has_i_frame is 0, discard none I(DR) frame\n");
5557 return IRQ_HANDLED;
5558 }
5559 } else {
5560 if (hw->skip_frame_count < 0 || is_idr) {
5561 /* second I */
5562 hw->dec_flag &= (~NODISP_FLAG);
5563 hw->skip_frame_count = 0;
5564 }
5565 if (hw->has_i_frame == 0 &&
5566 (!is_idr)) {
5567 int skip_count =
5568 (hw->first_i_policy >> 8) & 0xff;
5569 /* first I (not IDR) */
5570 if ((hw->first_i_policy & 0x3) == 2)
5571 hw->skip_frame_count =
5572 -1 - skip_count;
5573 else
5574 hw->skip_frame_count =
5575 skip_count;
5576 if (hw->skip_frame_count != 0)
5577 hw->dec_flag |= NODISP_FLAG;
5578 }
5579 }
5580 }
5581 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5582 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5583 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5584 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5585 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5586 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5587 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5588 ? I_FLAG : 0;
5589
5590 if ((hw->i_only & 0x2) && (I_flag & I_FLAG))
5591 flush_dpb(p_H264_Dpb);
5592
5593 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5594 (p_H264_Dpb->mSlice.structure == FRAME)) {
5595 hw->data_flag = NULL_FLAG;
5596 goto pic_done_proc;
5597 }
5598
5599 slice_header_process_status =
5600 h264_slice_header_process(p_H264_Dpb);
5601 if (hw->mmu_enable)
5602 hevc_sao_set_slice_type(hw,
5603 slice_header_process_status,
5604 hw->dpb.mSlice.idr_flag);
5605 vui_config(hw);
5606
5607 if (p_H264_Dpb->mVideo.dec_picture) {
5608 int cfg_ret = 0;
5609 bool field_pic_flag = false;
5610
5611 if (slice_header_process_status == 1) {
5612 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5613 field_pic_flag =
5614 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5615 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5616 true : false;
5617 }
5618
5619 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5620 (((unsigned long)(hw->vh264_amstream_dec_info
5621 .param)) & 0x8))) {
5622 p_H264_Dpb->fast_output_enable =
5623 H264_OUTPUT_MODE_FAST;
5624 }
5625 else
5626 p_H264_Dpb->fast_output_enable
5627 = fast_output_enable;
5628 hw->data_flag = I_flag;
5629 if ((p_H264_Dpb->
5630 dpb_param.dpb.NAL_info_mmco & 0x1f)
5631 == 5)
5632 hw->data_flag |= IDR_FLAG;
5633 dpb_print(DECODE_ID(hw),
5634 PRINT_FLAG_VDEC_STATUS,
5635 "==================> frame count %d to skip %d\n",
5636 hw->decode_pic_count+1,
5637 hw->skip_frame_count);
5638 } else if (error_proc_policy & 0x100){
5639 struct StorablePicture *p =
5640 p_H264_Dpb->mVideo.dec_picture;
5641 unsigned mby_mbx = READ_VREG(MBY_MBX);
5642 unsigned decode_mb_count =
5643 ((mby_mbx & 0xff) * hw->mb_width +
5644 (((mby_mbx >> 8) & 0xff) + 1));
5645 if (decode_mb_count <
5646 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5647 (1 + p->mb_aff_frame_flag))) {
5648 dpb_print(DECODE_ID(hw),
5649 PRINT_FLAG_VDEC_STATUS,
5650 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5651 p_H264_Dpb->dpb_param.l.
5652 data[FIRST_MB_IN_SLICE],
5653 READ_VREG(MBY_MBX),
5654 decode_mb_count);
5655 p->data_flag |= ERROR_FLAG;
5656 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5657 p->data_flag |= ERROR_FLAG;
5658 goto pic_done_proc;
5659 }
5660 }
5661
5662 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5663 hw->new_iframe_flag = 1;
5664 }
5665 if (hw->new_iframe_flag) {
5666 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5667 hw->new_iframe_flag = 0;
5668 hw->ref_err_flush_dpb_flag = 1;
5669 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5670 hw->new_iframe_flag = 0;
5671 hw->ref_err_flush_dpb_flag = 0;
5672 }
5673 }
5674
5675 if (error_proc_policy & 0x400) {
5676 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5677 if (ret != 0) {
5678 hw->reflist_error_count ++;
5679 dpb_print(DECODE_ID(hw), 0,
5680 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5681 ret,
5682 hw->decode_pic_count+1,
5683 hw->skip_frame_count,
5684 hw->reflist_error_count);
5685
5686 if (hw->ref_err_flush_dpb_flag) {
5687 flush_dpb(p_H264_Dpb);
5688 p_H264_Dpb->colocated_buf_map = 0;
5689 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5690 p_H264_Dpb->colocated_buf_map |= 1 <<
5691 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5692 }
5693 }
5694
5695 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5696 if (((error_proc_policy & 0x80)
5697 && ((hw->dec_flag &
5698 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5699 hw->reset_bufmgr_flag = 1;
5700 hw->reflist_error_count =0;
5701 amvdec_stop();
5702 vdec->mc_loaded = 0;
5703 hw->dec_result = DEC_RESULT_DONE;
5704 vdec_schedule_work(&hw->work);
5705 return IRQ_HANDLED;
5706 }
5707 } else
5708 hw->reflist_error_count = 0;
5709 }
5710 if ((error_proc_policy & 0x800) && (!(hw->i_only & 0x2))
5711 && p_H264_Dpb->dpb_error_flag != 0) {
5712 dpb_print(DECODE_ID(hw), 0,
5713 "dpb error %d\n",
5714 p_H264_Dpb->dpb_error_flag);
5715 hw->data_flag |= ERROR_FLAG;
5716 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5717 if ((error_proc_policy & 0x80) &&
5718 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5719 hw->reset_bufmgr_flag = 1;
5720 amvdec_stop();
5721 vdec->mc_loaded = 0;
5722 hw->dec_result = DEC_RESULT_DONE;
5723 vdec_schedule_work(&hw->work);
5724 return IRQ_HANDLED;
5725 }
5726 }
5727
5728 cfg_ret = config_decode_buf(hw,
5729 p_H264_Dpb->mVideo.dec_picture);
5730 if (cfg_ret < 0) {
5731 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5732 "config_decode_buf fail (%d)\n",
5733 cfg_ret);
5734 if (error_proc_policy & 0x2) {
5735 release_cur_decoding_buf(hw);
5736 /*hw->data_flag |= ERROR_FLAG;*/
5737 hw->reset_bufmgr_flag = 1;
5738 hw->dec_result = DEC_RESULT_DONE;
5739 vdec_schedule_work(&hw->work);
5740 return IRQ_HANDLED;
5741 } else
5742 hw->data_flag |= ERROR_FLAG;
5743 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5744 }
5745 }
5746
5747 if (slice_header_process_status == 1)
5748 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5749 else
5750 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5751 hw->last_mby_mbx = 0;
5752 hw->last_vld_level = 0;
5753 start_process_time(hw);
5754 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5755 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5756pic_done_proc:
5757 reset_process_time(hw);
5758
5759 if (input_frame_based(vdec) &&
5760 (!(hw->i_only & 0x2)) &&
5761 frmbase_cont_bitlevel != 0 &&
5762 READ_VREG(VIFF_BIT_CNT) >
5763 frmbase_cont_bitlevel) {
5764 /*handle the case: multi pictures in one packet*/
5765 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5766 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5767 __func__,
5768 hw->decode_pic_count,
5769 READ_VREG(VIFF_BIT_CNT));
5770 hw->frmbase_cont_flag = 1;
5771 } else
5772 hw->frmbase_cont_flag = 0;
5773
5774 if (p_H264_Dpb->mVideo.dec_picture) {
5775 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5776#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5777 DEL_EXIST(hw,
5778 p_H264_Dpb->mVideo.dec_picture) = 0;
5779 if (vdec->master) {
5780 struct vdec_h264_hw_s *hw_ba =
5781 (struct vdec_h264_hw_s *)
5782 vdec->master->private;
5783 if (hw_ba->last_dec_picture)
5784 DEL_EXIST(hw_ba,
5785 hw_ba->last_dec_picture)
5786 = 1;
5787 }
5788#endif
5789 mutex_lock(&hw->chunks_mutex);
5790 if (hw->chunk) {
5791 p_H264_Dpb->mVideo.dec_picture->pts =
5792 hw->chunk->pts;
5793 p_H264_Dpb->mVideo.dec_picture->pts64 =
5794 hw->chunk->pts64;
5795 p_H264_Dpb->mVideo.dec_picture->timestamp =
5796 hw->chunk->timestamp;
5797#ifdef MH264_USERDATA_ENABLE
5798 vmh264_udc_fill_vpts(hw,
5799 p_H264_Dpb->mSlice.slice_type,
5800 hw->chunk->pts, 1);
5801#endif
5802
5803#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5804 } else if (vdec->master) {
5805 /*dv enhance layer,
5806 do not checkout pts*/
5807 struct StorablePicture *pic =
5808 p_H264_Dpb->mVideo.dec_picture;
5809 pic->pts = 0;
5810 pic->pts64 = 0;
5811#endif
5812 } else {
5813 struct StorablePicture *pic =
5814 p_H264_Dpb->mVideo.dec_picture;
5815 u32 offset = pic->offset_delimiter;
5816 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5817 offset, &pic->pts, 0, &pic->pts64)) {
5818 pic->pts = 0;
5819 pic->pts64 = 0;
5820#ifdef MH264_USERDATA_ENABLE
5821 vmh264_udc_fill_vpts(hw,
5822 p_H264_Dpb->mSlice.slice_type,
5823 pic->pts, 0);
5824#endif
5825 } else {
5826#ifdef MH264_USERDATA_ENABLE
5827 vmh264_udc_fill_vpts(hw,
5828 p_H264_Dpb->mSlice.slice_type,
5829 pic->pts, 1);
5830#endif
5831 }
5832
5833 }
5834 mutex_unlock(&hw->chunks_mutex);
5835
5836 check_decoded_pic_error(hw);
5837#ifdef ERROR_HANDLE_TEST
5838 if ((hw->data_flag & ERROR_FLAG)
5839 && (error_proc_policy & 0x80)) {
5840 release_cur_decoding_buf(hw);
5841 h264_clear_dpb(hw);
5842 hw->dec_flag = 0;
5843 hw->data_flag = 0;
5844 hw->skip_frame_count = 0;
5845 hw->has_i_frame = 0;
5846 hw->no_error_count = 0xfff;
5847 hw->no_error_i_count = 0xf;
5848 } else
5849#endif
5850 ret = store_picture_in_dpb(p_H264_Dpb,
5851 p_H264_Dpb->mVideo.dec_picture,
5852 hw->data_flag | hw->dec_flag |
5853 p_H264_Dpb->mVideo.dec_picture->data_flag);
5854
5855
5856
5857 if (ret == -1) {
5858 release_cur_decoding_buf(hw);
5859 bufmgr_force_recover(p_H264_Dpb);
5860 } else {
5861 if (hw->data_flag & ERROR_FLAG) {
5862 hw->no_error_count = 0;
5863 hw->no_error_i_count = 0;
5864 } else {
5865 hw->no_error_count++;
5866 if (hw->data_flag & I_FLAG)
5867 hw->no_error_i_count++;
5868 }
5869 if (hw->mmu_enable)
5870 hevc_set_unused_4k_buff_idx(hw,
5871 p_H264_Dpb->mVideo.
5872 dec_picture->buf_spec_num);
5873 bufmgr_post(p_H264_Dpb);
5874 hw->last_dec_picture =
5875 p_H264_Dpb->mVideo.dec_picture;
5876 p_H264_Dpb->mVideo.dec_picture = NULL;
5877 /* dump_dpb(&p_H264_Dpb->mDPB); */
5878 hw->has_i_frame = 1;
5879 if (hw->mmu_enable)
5880 hevc_set_frame_done(hw);
5881 hw->decode_pic_count++;
5882 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5883 if (hw->skip_frame_count > 0) {
5884 /*skip n frame after first I */
5885 hw->skip_frame_count--;
5886 if (hw->skip_frame_count == 0)
5887 hw->dec_flag &= (~NODISP_FLAG);
5888 } else if (hw->skip_frame_count < -1) {
5889 /*skip n frame after first I until second I */
5890 hw->skip_frame_count++;
5891 if (hw->skip_frame_count == -1)
5892 hw->dec_flag &= (~NODISP_FLAG);
5893 }
5894 }
5895 }
5896 if (hw->frmbase_cont_flag) {
5897 /*do not DEC_RESULT_GET_DATA*/
5898 hw->get_data_count = 0x7fffffff;
5899 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5900 decode_frame_count[DECODE_ID(hw)]++;
5901 start_process_time(hw);
5902 return IRQ_HANDLED;
5903 }
5904 amvdec_stop();
5905 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5906 "%s %s decode slice count %d\n",
5907 __func__,
5908 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5909 "H264_PIC_DATA_DONE" :
5910 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5911 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5912 hw->decode_pic_count);
5913 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5914 hw->dec_result = DEC_RESULT_DONE;
5915#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5916 if (vdec->slave &&
5917 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5918 struct vdec_h264_hw_s *hw_el =
5919 (struct vdec_h264_hw_s *)(vdec->slave->private);
5920 hw_el->got_valid_nal = 0;
5921 hw->switch_dvlayer_flag = 1;
5922 } else if (vdec->master &&
5923 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5924 struct vdec_h264_hw_s *hw_bl =
5925 (struct vdec_h264_hw_s *)(vdec->master->private);
5926 hw_bl->got_valid_nal = 0;
5927 hw->switch_dvlayer_flag = 1;
5928 } else {
5929 hw->switch_dvlayer_flag = 0;
5930 hw->got_valid_nal = 1;
5931 }
5932#endif
5933
5934 hw->dec_result = DEC_RESULT_DONE;
5935 vdec_schedule_work(&hw->work);
5936
5937#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5938 } else if (
5939 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5940 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5941 goto pic_done_proc;
5942#endif
5943 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5944 reset_process_time(hw);
5945 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5946 dma_sync_single_for_cpu(
5947 amports_get_dma_device(),
5948 hw->aux_phy_addr,
5949 hw->prefix_aux_size + hw->suffix_aux_size,
5950 DMA_FROM_DEVICE);
5951 if (dpb_is_debug(DECODE_ID(hw),
5952 PRINT_FLAG_DPB_DETAIL))
5953 dump_aux_buf(hw);
5954#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5955 if (vdec->dolby_meta_with_el || vdec->slave) {
5956 if (hw->last_dec_picture)
5957 set_aux_data(hw, hw->last_dec_picture,
5958 0, 0, NULL);
5959 } else {
5960 if (vdec->master) {
5961 struct vdec_h264_hw_s *hw_bl =
5962 (struct vdec_h264_hw_s *)
5963 (vdec->master->private);
5964 if (hw_bl->last_dec_picture != NULL) {
5965 set_aux_data(hw_bl,
5966 hw_bl->last_dec_picture,
5967 0, 1, hw);
5968 }
5969 set_aux_data(hw,
5970 hw->last_dec_picture,
5971 0, 2, NULL);
5972 }
5973 }
5974#else
5975 if (hw->last_dec_picture)
5976 set_aux_data(hw,
5977 hw->last_dec_picture, 0, 0, NULL);
5978#endif
5979 }
5980#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5981 hw->switch_dvlayer_flag = 0;
5982 hw->got_valid_nal = 1;
5983#endif
5984 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5985 "%s H264_AUX_DATA_READY\n", __func__);
5986 hw->dec_result = DEC_RESULT_DONE;
5987 vdec_schedule_work(&hw->work);
5988 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5989 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5990 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5991 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5992empty_proc:
5993 reset_process_time(hw);
5994 if (!hw->frmbase_cont_flag)
5995 release_cur_decoding_buf(hw);
5996
5997 if (input_frame_based(vdec) ||
5998 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
5999 if (h264_debug_flag &
6000 DISABLE_ERROR_HANDLE) {
6001 dpb_print(DECODE_ID(hw),
6002 PRINT_FLAG_ERROR,
6003 "%s decoding error, level 0x%x\n",
6004 __func__,
6005 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6006 goto send_again;
6007 }
6008 amvdec_stop();
6009 vdec->mc_loaded = 0;
6010 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6011 "%s %s\n", __func__,
6012 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6013 "H264_SEARCH_BUFEMPTY" :
6014 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6015 "H264_DECODE_BUFEMPTY" :
6016 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6017 "H264_DECODE_TIMEOUT" :
6018 "OTHER");
6019 hw->dec_result = DEC_RESULT_DONE;
6020
6021 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6022 hw->search_dataempty_num++;
6023 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6024 hw->decode_timeout_num++;
6025 if (error_proc_policy & 0x4000) {
6026 hw->data_flag |= ERROR_FLAG;
6027 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6028 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6029 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6030 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6031 dpb_print(DECODE_ID(hw),
6032 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6033 p_H264_Dpb->last_dpb_status, __func__);
6034 hw->reset_bufmgr_flag = 1;
6035 }
6036 }
6037 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6038 hw->decode_dataempty_num++;
6039 if (!hw->frmbase_cont_flag)
6040 hw->data_flag |= ERROR_FLAG;
6041
6042 vdec_schedule_work(&hw->work);
6043 } else {
6044 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6045 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6046 "%s DEC_RESULT_AGAIN\n", __func__);
6047send_again:
6048 hw->dec_result = DEC_RESULT_AGAIN;
6049 vdec_schedule_work(&hw->work);
6050 }
6051 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6052 reset_process_time(hw);
6053 if (input_frame_based(vdec)) {
6054 dpb_print(DECODE_ID(hw),
6055 PRINT_FLAG_VDEC_STATUS,
6056 "%s H264_DATA_REQUEST (%d)\n",
6057 __func__, hw->get_data_count);
6058 hw->dec_result = DEC_RESULT_GET_DATA;
6059 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6060 hw->get_data_start_time = jiffies;
6061 hw->get_data_count++;
6062 if (hw->get_data_count >= frame_max_data_packet)
6063 goto empty_proc;
6064 vdec_schedule_work(&hw->work);
6065 } else
6066 goto empty_proc;
6067 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6068 dpb_print(DECODE_ID(hw), 0,
6069 "vmh264 decode oversize !!\n");
6070 release_cur_decoding_buf(hw);
6071 hw->data_flag |= ERROR_FLAG;
6072 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6073 reset_process_time(hw);
6074 hw->dec_result = DEC_RESULT_DONE;
6075 vdec_schedule_work(&hw->work);
6076 return IRQ_HANDLED;
6077 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6078 int aux_data_len;
6079 aux_data_len =
6080 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6081
6082 if (aux_data_len > SEI_DATA_SIZE) {
6083 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6084 "sei data size more than 4K: %d, discarded it\n",
6085 hw->sei_itu_data_len);
6086 hw->sei_itu_data_len = 0;
6087 }
6088
6089 if (aux_data_len != 0) {
6090 u8 *trans_data_buf;
6091 u8 *sei_data_buf;
6092 u8 swap_byte;
6093
6094 dma_sync_single_for_cpu(
6095 amports_get_dma_device(),
6096 hw->aux_phy_addr,
6097 hw->prefix_aux_size + hw->suffix_aux_size,
6098 DMA_FROM_DEVICE);
6099#if 0
6100 dump_aux_buf(hw);
6101#endif
6102 trans_data_buf = (u8 *)hw->aux_addr;
6103
6104 if (trans_data_buf[7] == AUX_TAG_SEI) {
6105 int left_len;
6106
6107 sei_data_buf = (u8 *)hw->sei_data_buf
6108 + hw->sei_data_len;
6109 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6110 if (aux_data_len/2 <= left_len) {
6111 for (i = 0; i < aux_data_len/2; i++)
6112 sei_data_buf[i]
6113 = trans_data_buf[i*2];
6114
6115 aux_data_len = aux_data_len / 2;
6116 for (i = 0; i < aux_data_len; i = i+4) {
6117 swap_byte = sei_data_buf[i];
6118 sei_data_buf[i]
6119 = sei_data_buf[i+3];
6120 sei_data_buf[i+3] = swap_byte;
6121
6122 swap_byte = sei_data_buf[i+1];
6123 sei_data_buf[i+1]
6124 = sei_data_buf[i+2];
6125 sei_data_buf[i+2] = swap_byte;
6126 }
6127
6128 for (i = aux_data_len-1; i >= 0; i--)
6129 if (sei_data_buf[i] != 0)
6130 break;
6131
6132 hw->sei_data_len += i+1;
6133 } else
6134 dpb_print(DECODE_ID(hw),
6135 PRINT_FLAG_ERROR,
6136 "sei data size %d and more than left space: %d, discarded it\n",
6137 hw->sei_itu_data_len,
6138 left_len);
6139 }
6140 }
6141 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6142
6143 return IRQ_HANDLED;
6144 }
6145
6146
6147 /* ucode debug */
6148 debug_tag = READ_VREG(DEBUG_REG1);
6149 if (debug_tag & 0x10000) {
6150 unsigned short *p = (unsigned short *)hw->lmem_addr;
6151
6152 dma_sync_single_for_cpu(
6153 amports_get_dma_device(),
6154 hw->lmem_addr_remap,
6155 PAGE_SIZE,
6156 DMA_FROM_DEVICE);
6157
6158 dpb_print(DECODE_ID(hw), 0,
6159 "LMEM<tag %x>:\n", debug_tag);
6160 for (i = 0; i < 0x400; i += 4) {
6161 int ii;
6162 if ((i & 0xf) == 0)
6163 dpb_print_cont(DECODE_ID(hw), 0,
6164 "%03x: ", i);
6165 for (ii = 0; ii < 4; ii++)
6166 dpb_print_cont(DECODE_ID(hw), 0,
6167 "%04x ", p[i+3-ii]);
6168 if (((i+ii) & 0xf) == 0)
6169 dpb_print_cont(DECODE_ID(hw), 0,
6170 "\n");
6171 }
6172 if (((udebug_pause_pos & 0xffff)
6173 == (debug_tag & 0xffff)) &&
6174 (udebug_pause_decode_idx == 0 ||
6175 udebug_pause_decode_idx ==
6176 hw->decode_pic_count) &&
6177 (udebug_pause_val == 0 ||
6178 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6179 udebug_pause_pos &= 0xffff;
6180 hw->ucode_pause_pos = udebug_pause_pos;
6181 }
6182 else if (debug_tag & 0x20000)
6183 hw->ucode_pause_pos = 0xffffffff;
6184 if (hw->ucode_pause_pos)
6185 reset_process_time(hw);
6186 else
6187 WRITE_VREG(DEBUG_REG1, 0);
6188 } else if (debug_tag != 0) {
6189 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6190 "dbg%x: %x\n", debug_tag,
6191 READ_VREG(DEBUG_REG2));
6192 if (((udebug_pause_pos & 0xffff)
6193 == (debug_tag & 0xffff)) &&
6194 (udebug_pause_decode_idx == 0 ||
6195 udebug_pause_decode_idx ==
6196 hw->decode_pic_count) &&
6197 (udebug_pause_val == 0 ||
6198 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6199 udebug_pause_pos &= 0xffff;
6200 hw->ucode_pause_pos = udebug_pause_pos;
6201 }
6202 if (hw->ucode_pause_pos)
6203 reset_process_time(hw);
6204 else
6205 WRITE_VREG(DEBUG_REG1, 0);
6206 }
6207 /**/
6208 return IRQ_HANDLED;
6209}
6210
6211static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6212{
6213 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6214 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6215
6216
6217 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6218
6219 if (!hw)
6220 return IRQ_HANDLED;
6221
6222 if (hw->eos)
6223 return IRQ_HANDLED;
6224
6225 p_H264_Dpb->vdec = vdec;
6226 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6227
6228 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6229 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6230 __func__,
6231 p_H264_Dpb->dec_dpb_status,
6232 READ_VREG(ERROR_STATUS_REG),
6233 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6234 READ_VREG(VLD_MEM_VIFIFO_WP),
6235 READ_VREG(VLD_MEM_VIFIFO_RP),
6236 READ_VREG(VIFF_BIT_CNT),
6237 READ_VREG(MBY_MBX));
6238
6239 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6240 if (hw->mmu_enable)
6241 hevc_sao_wait_done(hw);
6242 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6243 return IRQ_HANDLED;
6244 }
6245 return IRQ_WAKE_THREAD;
6246
6247}
6248
6249static void timeout_process(struct vdec_h264_hw_s *hw)
6250{
6251 struct vdec_s *vdec = hw_to_vdec(hw);
6252 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6253
6254 /*
6255 * In this very timeout point,the vh264_work arrives,
6256 * let it to handle the scenario.
6257 */
6258 if (work_pending(&hw->work))
6259 return;
6260
6261 hw->timeout_num++;
6262 amvdec_stop();
6263 vdec->mc_loaded = 0;
6264 if (hw->mmu_enable) {
6265 hevc_set_frame_done(hw);
6266 hevc_sao_wait_done(hw);
6267 }
6268 if (!hw->i_only && (error_proc_policy & 0x2))
6269 flush_dpb(p_H264_Dpb);
6270 dpb_print(DECODE_ID(hw),
6271 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6272 release_cur_decoding_buf(hw);
6273 hw->dec_result = DEC_RESULT_DONE;
6274 hw->data_flag |= ERROR_FLAG;
6275
6276 if (work_pending(&hw->work))
6277 return;
6278 vdec_schedule_work(&hw->timeout_work);
6279}
6280
6281static void dump_bufspec(struct vdec_h264_hw_s *hw,
6282 const char *caller)
6283{
6284 int i;
6285 dpb_print(DECODE_ID(hw), 0,
6286 "%s in %s:\n", __func__, caller);
6287 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6288 if (hw->buffer_spec[i].used == -1)
6289 continue;
6290 dpb_print(DECODE_ID(hw), 0,
6291 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6292 i, hw->buffer_spec[i].used,
6293 hw->buffer_spec[i].buf_adr,
6294 hw->buffer_spec[i].canvas_pos,
6295 hw->buffer_spec[i].vf_ref
6296 );
6297#ifdef CONFIG_AM_VDEC_DV
6298 dpb_print_cont(DECODE_ID(hw), 0,
6299 "dv_el_exist %d",
6300 hw->buffer_spec[i].dv_enhance_exist
6301 );
6302#endif
6303 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6304 }
6305
6306}
6307
6308static void vmh264_dump_state(struct vdec_s *vdec)
6309{
6310 struct vdec_h264_hw_s *hw =
6311 (struct vdec_h264_hw_s *)(vdec->private);
6312 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6313 dpb_print(DECODE_ID(hw), 0,
6314 "====== %s\n", __func__);
6315 dpb_print(DECODE_ID(hw), 0,
6316 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6317 hw->frame_width,
6318 hw->frame_height,
6319 hw->dpb.reorder_pic_num,
6320 hw->dpb.mDPB.size,
6321 hw->max_reference_size,
6322 hw->i_only,
6323 hw->send_error_frame_flag
6324 );
6325
6326 dpb_print(DECODE_ID(hw), 0,
6327 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6328 input_frame_based(vdec),
6329 hw->eos,
6330 hw->stat,
6331 hw->dec_result,
6332 decode_frame_count[DECODE_ID(hw)],
6333 display_frame_count[DECODE_ID(hw)],
6334 run_count[DECODE_ID(hw)],
6335 not_run_ready[DECODE_ID(hw)],
6336 input_empty[DECODE_ID(hw)],
6337 hw->reset_bufmgr_count
6338 );
6339
6340 if (vf_get_receiver(vdec->vf_provider_name)) {
6341 enum receviver_start_e state =
6342 vf_notify_receiver(vdec->vf_provider_name,
6343 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6344 NULL);
6345 dpb_print(DECODE_ID(hw), 0,
6346 "\nreceiver(%s) state %d\n",
6347 vdec->vf_provider_name,
6348 state);
6349 }
6350
6351 dpb_print(DECODE_ID(hw), 0,
6352 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x\n",
6353 __func__,
6354 kfifo_len(&hw->newframe_q),
6355 VF_POOL_SIZE,
6356 kfifo_len(&hw->display_q),
6357 VF_POOL_SIZE,
6358 hw->vf_pre_count,
6359 hw->vf_get_count,
6360 hw->vf_put_count,
6361 have_free_buf_spec(vdec),
6362 p_H264_Dpb->mDPB.init_done,
6363 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6364 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6365 p_H264_Dpb->fast_output_enable
6366 );
6367
6368 dump_dpb(&p_H264_Dpb->mDPB, 1);
6369 dump_pic(p_H264_Dpb);
6370 dump_bufspec(hw, __func__);
6371
6372 dpb_print(DECODE_ID(hw), 0,
6373 "DPB_STATUS_REG=0x%x\n",
6374 READ_VREG(DPB_STATUS_REG));
6375 dpb_print(DECODE_ID(hw), 0,
6376 "MPC_E=0x%x\n",
6377 READ_VREG(MPC_E));
6378 dpb_print(DECODE_ID(hw), 0,
6379 "H264_DECODE_MODE=0x%x\n",
6380 READ_VREG(H264_DECODE_MODE));
6381 dpb_print(DECODE_ID(hw), 0,
6382 "MBY_MBX=0x%x\n",
6383 READ_VREG(MBY_MBX));
6384 dpb_print(DECODE_ID(hw), 0,
6385 "H264_DECODE_SIZE=0x%x\n",
6386 READ_VREG(H264_DECODE_SIZE));
6387 dpb_print(DECODE_ID(hw), 0,
6388 "VIFF_BIT_CNT=0x%x\n",
6389 READ_VREG(VIFF_BIT_CNT));
6390 dpb_print(DECODE_ID(hw), 0,
6391 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6392 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6393 dpb_print(DECODE_ID(hw), 0,
6394 "VLD_MEM_VIFIFO_WP=0x%x\n",
6395 READ_VREG(VLD_MEM_VIFIFO_WP));
6396 dpb_print(DECODE_ID(hw), 0,
6397 "VLD_MEM_VIFIFO_RP=0x%x\n",
6398 READ_VREG(VLD_MEM_VIFIFO_RP));
6399 dpb_print(DECODE_ID(hw), 0,
6400 "PARSER_VIDEO_RP=0x%x\n",
6401 READ_PARSER_REG(PARSER_VIDEO_RP));
6402 dpb_print(DECODE_ID(hw), 0,
6403 "PARSER_VIDEO_WP=0x%x\n",
6404 READ_PARSER_REG(PARSER_VIDEO_WP));
6405
6406 if (input_frame_based(vdec) &&
6407 dpb_is_debug(DECODE_ID(hw),
6408 PRINT_FRAMEBASE_DATA)
6409 ) {
6410 int jj;
6411 if (hw->chunk && hw->chunk->block &&
6412 hw->chunk->size > 0) {
6413 u8 *data = NULL;
6414
6415 if (!hw->chunk->block->is_mapped)
6416 data = codec_mm_vmap(hw->chunk->block->start +
6417 hw->chunk->offset, hw->chunk->size);
6418 else
6419 data = ((u8 *)hw->chunk->block->start_virt)
6420 + hw->chunk->offset;
6421
6422 dpb_print(DECODE_ID(hw), 0,
6423 "frame data size 0x%x\n",
6424 hw->chunk->size);
6425 for (jj = 0; jj < hw->chunk->size; jj++) {
6426 if ((jj & 0xf) == 0)
6427 dpb_print(DECODE_ID(hw),
6428 PRINT_FRAMEBASE_DATA,
6429 "%06x:", jj);
6430 dpb_print_cont(DECODE_ID(hw),
6431 PRINT_FRAMEBASE_DATA,
6432 "%02x ", data[jj]);
6433 if (((jj + 1) & 0xf) == 0)
6434 dpb_print_cont(DECODE_ID(hw),
6435 PRINT_FRAMEBASE_DATA,
6436 "\n");
6437 }
6438
6439 if (!hw->chunk->block->is_mapped)
6440 codec_mm_unmap_phyaddr(data);
6441 }
6442 }
6443}
6444
6445
6446static void check_timer_func(unsigned long arg)
6447{
6448 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6449 struct vdec_s *vdec = hw_to_vdec(hw);
6450 int error_skip_frame_count = error_skip_count & 0xfff;
6451 unsigned int timeout_val = decode_timeout_val;
6452 if (timeout_val != 0 &&
6453 hw->no_error_count < error_skip_frame_count)
6454 timeout_val = errordata_timeout_val;
6455 if ((h264_debug_cmd & 0x100) != 0 &&
6456 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6457 hw->dec_result = DEC_RESULT_DONE;
6458 vdec_schedule_work(&hw->work);
6459 pr_info("vdec %d is forced to be disconnected\n",
6460 h264_debug_cmd & 0xff);
6461 h264_debug_cmd = 0;
6462 return;
6463 }
6464 if ((h264_debug_cmd & 0x200) != 0 &&
6465 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6466 pr_debug("vdec %d is forced to reset bufmgr\n",
6467 h264_debug_cmd & 0xff);
6468 hw->reset_bufmgr_flag = 1;
6469 h264_debug_cmd = 0;
6470 return;
6471 }
6472
6473 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6474 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6475 vdec_schedule_work(&hw->work);
6476 pr_debug("vdec requested to be disconnected\n");
6477 return;
6478 }
6479
6480 if (radr != 0) {
6481 if (rval != 0) {
6482 WRITE_VREG(radr, rval);
6483 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6484 } else
6485 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6486 rval = 0;
6487 radr = 0;
6488 }
6489
6490 if ((input_frame_based(vdec) ||
6491 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6492 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6493 (timeout_val > 0) &&
6494 (hw->start_process_time > 0) &&
6495 ((1000 * (jiffies - hw->start_process_time) / HZ)
6496 > timeout_val)
6497 ) {
6498 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6499 u32 mby_mbx = READ_VREG(MBY_MBX);
6500 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6501 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6502 if (hw->last_mby_mbx == mby_mbx) {
6503 if (hw->decode_timeout_count > 0)
6504 hw->decode_timeout_count--;
6505 if (hw->decode_timeout_count == 0)
6506 {
6507 reset_process_time(hw);
6508 timeout_process(hw);
6509 }
6510 } else
6511 start_process_time(hw);
6512 } else if (is_in_parsing_state(dpb_status)) {
6513 if (hw->last_vld_level ==
6514 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6515 if (hw->decode_timeout_count > 0)
6516 hw->decode_timeout_count--;
6517 if (hw->decode_timeout_count == 0)
6518 {
6519 reset_process_time(hw);
6520 timeout_process(hw);
6521 }
6522 }
6523 }
6524 hw->last_vld_level =
6525 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6526 hw->last_mby_mbx = mby_mbx;
6527 }
6528
6529 if ((hw->ucode_pause_pos != 0) &&
6530 (hw->ucode_pause_pos != 0xffffffff) &&
6531 udebug_pause_pos != hw->ucode_pause_pos) {
6532 hw->ucode_pause_pos = 0;
6533 WRITE_VREG(DEBUG_REG1, 0);
6534 }
6535
6536 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6537}
6538
6539static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6540{
6541 u32 ar;
6542 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6543
6544 if (!hw)
6545 return -1;
6546
6547 vstatus->frame_width = hw->frame_width;
6548 vstatus->frame_height = hw->frame_height;
6549 if (hw->frame_dur != 0)
6550 vstatus->frame_rate = 96000 / hw->frame_dur;
6551 else
6552 vstatus->frame_rate = -1;
6553 vstatus->error_count = 0;
6554 vstatus->status = hw->stat;
6555 if (hw->h264_ar == 0x3ff)
6556 hw->h264_ar = (0x100 *
6557 hw->frame_height * hw->height_aspect_ratio) /
6558 (hw->frame_width * hw->width_aspect_ratio);
6559 ar = min_t(u32,
6560 hw->h264_ar,
6561 DISP_RATIO_ASPECT_RATIO_MAX);
6562 vstatus->ratio_control =
6563 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6564
6565 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6566 "%s-%02d", DRIVER_NAME, hw->id);
6567
6568 return 0;
6569}
6570
6571static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6572{
6573 int i, j;
6574 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6575
6576 /* if (hw->init_flag == 0) { */
6577 if (h264_debug_flag & 0x40000000) {
6578 /* if (1) */
6579 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6580 "%s, reset register\n", __func__);
6581
6582 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6583 ;
6584 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6585 ; /* reg address is 0x350 */
6586
6587#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6588 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6589 WRITE_VREG(DOS_SW_RESET0, 0);
6590
6591 READ_VREG(DOS_SW_RESET0);
6592 READ_VREG(DOS_SW_RESET0);
6593 READ_VREG(DOS_SW_RESET0);
6594
6595 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6596 WRITE_VREG(DOS_SW_RESET0, 0);
6597
6598 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6599 WRITE_VREG(DOS_SW_RESET0, 0);
6600
6601 READ_VREG(DOS_SW_RESET0);
6602 READ_VREG(DOS_SW_RESET0);
6603 READ_VREG(DOS_SW_RESET0);
6604
6605#else
6606 WRITE_RESET_REG(RESET0_REGISTER,
6607 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6608 READ_RESET_REG(RESET0_REGISTER);
6609 WRITE_RESET_REG(RESET0_REGISTER,
6610 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6611
6612 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6613#endif
6614 WRITE_VREG(POWER_CTL_VLD,
6615 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6616 (1 << 9) | (1 << 6));
6617 } else {
6618 /* WRITE_VREG(POWER_CTL_VLD,
6619 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6620 */
6621 WRITE_VREG(POWER_CTL_VLD,
6622 READ_VREG(POWER_CTL_VLD) |
6623 (0 << 10) | (1 << 9) | (1 << 6));
6624 }
6625 /* disable PSCALE for hardware sharing */
6626 WRITE_VREG(PSCALE_CTRL, 0);
6627
6628 /* clear mailbox interrupt */
6629 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6630
6631 /* enable mailbox interrupt */
6632 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6633
6634#ifdef NV21
6635 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6636#endif
6637
6638 /* cbcr_merge_swap_en */
6639 if (hw->is_used_v4l
6640 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6641 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6642 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6643
6644 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6645 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6646
6647 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6648 if (hw->mmu_enable) {
6649 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6650 /* sw reset to extif hardware */
6651 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6652 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6653 } else {
6654 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6655 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6656 }
6657
6658
6659#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6660 /* pr_info("vh264 meson8 prot init\n"); */
6661 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6662#endif
6663
6664#ifdef VDEC_DW
6665 if (IS_VDEC_DW(hw)) {
6666 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6667
6668 if (IS_VDEC_DW(hw) == 2)
6669 data |= (1 << 9);
6670 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6671 }
6672#endif
6673 if (hw->dpb.mDPB.size > 0) {
6674 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6675 (hw->dpb.mDPB.size << 16) |
6676 (hw->dpb.mDPB.size << 8));
6677
6678 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6679 i = get_buf_spec_by_canvas_pos(hw, j);
6680 if (i < 0)
6681 break;
6682
6683 if (!hw->mmu_enable &&
6684 hw->buffer_spec[i].cma_alloc_addr)
6685 config_decode_canvas(hw, i);
6686 if (hw->mmu_enable && hw->double_write_mode)
6687 config_decode_canvas_ex(hw, i);
6688 }
6689 } else {
6690 WRITE_VREG(AV_SCRATCH_0, 0);
6691 WRITE_VREG(AV_SCRATCH_9, 0);
6692 }
6693
6694 if (hw->init_flag == 0)
6695 WRITE_VREG(DPB_STATUS_REG, 0);
6696 else
6697 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6698
6699 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6700 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6701 if (!tee_enabled())
6702 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6703
6704 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6705 * error_recovery_mode : error_recovery_mode_in;
6706 */
6707 /* WRITE_VREG(AV_SCRATCH_F,
6708 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6709 */
6710 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6711 ((error_recovery_mode_in & 0x1) << 4));
6712 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6713 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6714 else*/
6715 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6716
6717 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6718#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6719 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6720#endif
6721
6722 WRITE_VREG(DEBUG_REG1, 0);
6723 WRITE_VREG(DEBUG_REG2, 0);
6724
6725 if (hw->reg_iqidct_control)
6726 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6727 if (hw->reg_vcop_ctrl_reg)
6728 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6729 if (hw->vld_dec_control)
6730 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6731 return 0;
6732}
6733
6734static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6735{
6736 struct vdec_h264_hw_s *hw =
6737 (struct vdec_h264_hw_s *)vdec->private;
6738 if (i_only_flag & 0x100)
6739 return 0;
6740 if (trickmode == TRICKMODE_I)
6741 hw->i_only = 0x3;
6742 else if (trickmode == TRICKMODE_NONE)
6743 hw->i_only = 0x0;
6744 return 0;
6745}
6746
6747static unsigned char amvdec_enable_flag;
6748static void vh264_local_init(struct vdec_h264_hw_s *hw)
6749{
6750 int i;
6751 hw->init_flag = 0;
6752 hw->first_sc_checked= 0;
6753 hw->eos = 0;
6754 hw->valve_count = 0;
6755 hw->config_bufmgr_done = 0;
6756 hw->start_process_time = 0;
6757 hw->has_i_frame = 0;
6758 hw->no_error_count = 0xfff;
6759 hw->no_error_i_count = 0xf;
6760
6761 hw->dec_flag = 0;
6762 hw->data_flag = 0;
6763 hw->skip_frame_count = 0;
6764 hw->reg_iqidct_control = 0;
6765 hw->reg_vcop_ctrl_reg = 0;
6766 hw->reg_rv_ai_mb_count = 0;
6767 hw->vld_dec_control = 0;
6768 hw->decode_timeout_count = 0;
6769 hw->no_mem_count = 0;
6770 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6771 /* vh264_ratio = 0x100; */
6772
6773 hw->vh264_rotation = (((unsigned long)
6774 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6775
6776 hw->frame_prog = 0;
6777 hw->frame_width = hw->vh264_amstream_dec_info.width;
6778 hw->frame_height = hw->vh264_amstream_dec_info.height;
6779 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6780 hw->pts_outside = ((unsigned long)
6781 hw->vh264_amstream_dec_info.param) & 0x01;
6782 hw->sync_outside = ((unsigned long)
6783 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6784 hw->use_idr_framerate = ((unsigned long)
6785 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6786 hw->max_refer_buf = !(((unsigned long)
6787 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6788 if (hw->frame_dur < 96000/960) {
6789 /*more than 960fps,it should not be a correct value,
6790 *give default 30fps
6791 */
6792 hw->frame_dur = 96000/30;
6793 }
6794
6795 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6796
6797 hw->first_i_policy = first_i_policy;
6798
6799 if (hw->is_used_v4l)
6800 mem_map_mode = CANVAS_BLKMODE_LINEAR;
6801
6802 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6803 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6804 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6805 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6806
6807 if (i_only_flag & 0x100)
6808 hw->i_only = i_only_flag & 0xff;
6809 if (hw->i_only)
6810 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6811
6812 if ((unsigned long) hw->vh264_amstream_dec_info.param
6813 & 0x08)
6814 hw->no_poc_reorder_flag = 1;
6815
6816 error_recovery_mode_in = 1; /*ucode control?*/
6817 if (error_proc_policy & 0x80000000)
6818 hw->send_error_frame_flag = error_proc_policy & 0x1;
6819 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6820 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6821
6822 INIT_KFIFO(hw->display_q);
6823 INIT_KFIFO(hw->newframe_q);
6824
6825 for (i = 0; i < VF_POOL_SIZE; i++) {
6826 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6827 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6828 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6829 kfifo_put(&hw->newframe_q, vf);
6830 }
6831
6832 hw->duration_from_pts_done = 0;
6833
6834 hw->p_last_vf = NULL;
6835 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6836 hw->hevc_cur_buf_idx = 0xffff;
6837
6838 init_waitqueue_head(&hw->wait_q);
6839
6840 return;
6841}
6842
6843static s32 vh264_init(struct vdec_h264_hw_s *hw)
6844{
6845 int size = -1;
6846 int fw_size = 0x1000 * 16;
6847 int fw_mmu_size = 0x1000 * 16;
6848 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6849
6850 /* int trickmode_fffb = 0; */
6851
6852 /* pr_info("\nvh264_init\n"); */
6853 /* init_timer(&hw->recycle_timer); */
6854
6855 /* timer init */
6856 init_timer(&hw->check_timer);
6857
6858 hw->check_timer.data = (unsigned long)hw;
6859 hw->check_timer.function = check_timer_func;
6860 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6861
6862 /* add_timer(&hw->check_timer); */
6863 hw->stat |= STAT_TIMER_ARM;
6864 hw->stat |= STAT_ISR_REG;
6865
6866 mutex_init(&hw->chunks_mutex);
6867 vh264_local_init(hw);
6868 INIT_WORK(&hw->work, vh264_work);
6869 INIT_WORK(&hw->notify_work, vh264_notify_work);
6870 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6871#ifdef MH264_USERDATA_ENABLE
6872 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6873#endif
6874
6875 if (!amvdec_enable_flag) {
6876 amvdec_enable_flag = true;
6877 amvdec_enable();
6878 if (hw->mmu_enable)
6879 amhevc_enable();
6880 }
6881 if (hw->mmu_enable) {
6882
6883 hw->frame_mmu_map_addr =
6884 dma_alloc_coherent(amports_get_dma_device(),
6885 FRAME_MMU_MAP_SIZE,
6886 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6887 if (hw->frame_mmu_map_addr == NULL) {
6888 pr_err("%s: failed to alloc count_buffer\n", __func__);
6889 return -ENOMEM;
6890 }
6891 }
6892
6893 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6894 if (IS_ERR_OR_NULL(fw))
6895 return -ENOMEM;
6896
6897 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6898 if (size < 0) {
6899 pr_err("get firmware fail.\n");
6900 vfree(fw);
6901 return -1;
6902 }
6903
6904 fw->len = size;
6905 hw->fw = fw;
6906
6907 if (hw->mmu_enable) {
6908 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6909 if (IS_ERR_OR_NULL(fw_mmu))
6910 return -ENOMEM;
6911
6912 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6913 if (size < 0) {
6914 pr_err("get mmu fw fail.\n");
6915 vfree(fw_mmu);
6916 return -1;
6917 }
6918
6919 fw_mmu->len = size;
6920 hw->fw_mmu = fw_mmu;
6921 }
6922
6923 if (!tee_enabled()) {
6924 /* -- ucode loading (amrisc and swap code) */
6925 hw->mc_cpu_addr =
6926 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6927 &hw->mc_dma_handle, GFP_KERNEL);
6928 if (!hw->mc_cpu_addr) {
6929 amvdec_enable_flag = false;
6930 amvdec_disable();
6931 if (hw->mmu_enable)
6932 amhevc_disable();
6933 pr_info("vh264_init: Can not allocate mc memory.\n");
6934 return -ENOMEM;
6935 }
6936
6937 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6938 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6939 */
6940
6941 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6942
6943 /*header*/
6944 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6945 fw->data + 0x4000, MC_SWAP_SIZE);
6946 /*data*/
6947 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6948 fw->data + 0x2000, MC_SWAP_SIZE);
6949 /*mmco*/
6950 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6951 fw->data + 0x6000, MC_SWAP_SIZE);
6952 /*list*/
6953 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6954 fw->data + 0x3000, MC_SWAP_SIZE);
6955 /*slice*/
6956 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6957 fw->data + 0x5000, MC_SWAP_SIZE);
6958 /*main*/
6959 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6960 fw->data, 0x2000);
6961 /*data*/
6962 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6963 fw->data + 0x2000, 0x1000);
6964 /*slice*/
6965 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6966 fw->data + 0x5000, 0x1000);
6967 }
6968
6969#if 1 /* #ifdef BUFFER_MGR_IN_C */
6970 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6971 if (!hw->lmem_addr) {
6972 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6973 return -ENOMEM;
6974 } else {
6975 hw->lmem_addr_remap = dma_map_single(
6976 amports_get_dma_device(),
6977 (void *)hw->lmem_addr,
6978 PAGE_SIZE, DMA_FROM_DEVICE);
6979 if (dma_mapping_error(amports_get_dma_device(),
6980 hw->lmem_addr_remap)) {
6981 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6982 "%s: failed to map lmem_addr\n", __func__);
6983 free_page(hw->lmem_addr);
6984 hw->lmem_addr = 0;
6985 hw->lmem_addr_remap = 0;
6986 return -ENOMEM;
6987 }
6988
6989 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6990 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6991 }
6992
6993 if (prefix_aux_buf_size > 0 ||
6994 suffix_aux_buf_size > 0) {
6995 u32 aux_buf_size;
6996 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6997 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
6998 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
6999 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7000 if (hw->aux_addr == NULL) {
7001 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7002 return -1;
7003 }
7004
7005 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7006 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7007 if (dma_mapping_error(amports_get_dma_device(),
7008 hw->aux_phy_addr)) {
7009 pr_err("%s: failed to map rpm buffer\n", __func__);
7010 kfree(hw->aux_addr);
7011 hw->aux_addr = NULL;
7012 return -1;
7013 }
7014 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7015 if (hw->sei_data_buf == NULL) {
7016 pr_err("%s: failed to alloc sei itu data buffer\n",
7017 __func__);
7018 return -1;
7019 }
7020 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7021 if (hw->sei_itu_data_buf == NULL) {
7022 pr_err("%s: failed to alloc sei itu data buffer\n",
7023 __func__);
7024 kfree(hw->aux_addr);
7025 hw->aux_addr = NULL;
7026 kfree(hw->sei_data_buf);
7027 hw->sei_data_buf = NULL;
7028
7029 return -1;
7030 }
7031
7032 if (NULL == hw->sei_user_data_buffer) {
7033 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7034 GFP_KERNEL);
7035 if (!hw->sei_user_data_buffer) {
7036 pr_info("%s: Can not allocate sei_data_buffer\n",
7037 __func__);
7038 kfree(hw->aux_addr);
7039 hw->aux_addr = NULL;
7040 kfree(hw->sei_data_buf);
7041 hw->sei_data_buf = NULL;
7042 kfree(hw->sei_itu_data_buf);
7043 hw->sei_itu_data_buf = NULL;
7044
7045 return -1;
7046 }
7047 hw->sei_user_data_wp = 0;
7048 }
7049 }
7050/* BUFFER_MGR_IN_C */
7051#endif
7052 hw->stat |= STAT_MC_LOAD;
7053
7054 /* add memory barrier */
7055 wmb();
7056
7057 return 0;
7058}
7059
7060static int vh264_stop(struct vdec_h264_hw_s *hw)
7061{
7062 if (hw->stat & STAT_VDEC_RUN) {
7063 amvdec_stop();
7064 hw->stat &= ~STAT_VDEC_RUN;
7065 }
7066#ifdef VDEC_DW
7067 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7068#endif
7069#ifdef MH264_USERDATA_ENABLE
7070 cancel_work_sync(&hw->user_data_ready_work);
7071#endif
7072 cancel_work_sync(&hw->notify_work);
7073 cancel_work_sync(&hw->timeout_work);
7074 cancel_work_sync(&hw->work);
7075
7076
7077 if (hw->stat & STAT_MC_LOAD) {
7078 if (hw->mc_cpu_addr != NULL) {
7079 dma_free_coherent(amports_get_dma_device(),
7080 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7081 hw->mc_dma_handle);
7082 hw->mc_cpu_addr = NULL;
7083 }
7084 if (hw->frame_mmu_map_addr != NULL) {
7085 dma_free_coherent(amports_get_dma_device(),
7086 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7087 hw->frame_mmu_map_phy_addr);
7088 hw->frame_mmu_map_addr = NULL;
7089 }
7090
7091 }
7092 if (hw->stat & STAT_ISR_REG) {
7093 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7094 hw->stat &= ~STAT_ISR_REG;
7095 }
7096 if (hw->lmem_addr_remap) {
7097 dma_unmap_single(amports_get_dma_device(),
7098 hw->lmem_addr_remap,
7099 PAGE_SIZE, DMA_FROM_DEVICE);
7100 hw->lmem_addr_remap = 0;
7101 }
7102 if (hw->lmem_addr) {
7103 free_page(hw->lmem_addr);
7104 hw->lmem_addr = 0;
7105 }
7106 if (hw->aux_addr) {
7107 dma_unmap_single(amports_get_dma_device(),
7108 hw->aux_phy_addr,
7109 hw->prefix_aux_size + hw->suffix_aux_size,
7110 DMA_FROM_DEVICE);
7111 kfree(hw->aux_addr);
7112 hw->aux_addr = NULL;
7113 }
7114 if (hw->sei_data_buf != NULL) {
7115 kfree(hw->sei_data_buf);
7116 hw->sei_data_buf = NULL;
7117 }
7118 if (hw->sei_itu_data_buf != NULL) {
7119 kfree(hw->sei_itu_data_buf);
7120 hw->sei_itu_data_buf = NULL;
7121 }
7122 if (hw->sei_user_data_buffer != NULL) {
7123 kfree(hw->sei_user_data_buffer);
7124 hw->sei_user_data_buffer = NULL;
7125 }
7126 /* amvdec_disable(); */
7127
7128 vfree(hw->fw);
7129 hw->fw = NULL;
7130
7131 if (hw->mmu_enable) {
7132 vfree(hw->fw_mmu);
7133 hw->fw_mmu = NULL;
7134 }
7135
7136 dpb_print(DECODE_ID(hw), 0,
7137 "%s\n",
7138 __func__);
7139 return 0;
7140}
7141
7142static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7143{
7144 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7145 int count = 0;
7146 do {
7147 usleep_range(100, 500);
7148 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7149 break;
7150 if (count > 2000) {
7151 dpb_print(DECODE_ID(hw),
7152 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7153 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7154 break;
7155 } else
7156 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7157 count++;
7158 } while (1);
7159}
7160
7161static void vh264_notify_work(struct work_struct *work)
7162{
7163 struct vdec_h264_hw_s *hw = container_of(work,
7164 struct vdec_h264_hw_s, notify_work);
7165 struct vdec_s *vdec = hw_to_vdec(hw);
7166 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7167 vf_notify_receiver(vdec->vf_provider_name,
7168 VFRAME_EVENT_PROVIDER_FR_HINT,
7169 (void *)((unsigned long)hw->frame_dur));
7170 vdec->fr_hint_state = VDEC_HINTED;
7171 }
7172
7173 return;
7174}
7175
7176#ifdef MH264_USERDATA_ENABLE
7177static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7178{
7179 hw->wait_for_udr_send = 0;
7180 hw->sei_itu_data_len = 0;
7181 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7182}
7183
7184static void vmh264_crate_userdata_manager(
7185 struct vdec_h264_hw_s *hw,
7186 u8 *userdata_buf,
7187 int buf_len)
7188{
7189 if (hw) {
7190
7191
7192 mutex_init(&hw->userdata_mutex);
7193
7194 memset(&hw->userdata_info, 0,
7195 sizeof(struct mh264_userdata_info_t));
7196 hw->userdata_info.data_buf = userdata_buf;
7197 hw->userdata_info.buf_len = buf_len;
7198 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7199
7200 vmh264_reset_udr_mgr(hw);
7201
7202 }
7203}
7204
7205static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7206{
7207 if (hw)
7208 memset(&hw->userdata_info,
7209 0,
7210 sizeof(struct mh264_userdata_info_t));
7211}
7212
7213/*
7214#define DUMP_USERDATA_RECORD
7215*/
7216#ifdef DUMP_USERDATA_RECORD
7217
7218#define MAX_USER_DATA_SIZE 3145728
7219static void *user_data_buf;
7220static unsigned char *pbuf_start;
7221static int total_len;
7222static int bskip;
7223static int n_userdata_id;
7224
7225static void print_data(unsigned char *pdata,
7226 int len,
7227 unsigned int poc_number,
7228 unsigned int flag,
7229 unsigned int duration,
7230 unsigned int vpts,
7231 unsigned int vpts_valid,
7232 int rec_id)
7233{
7234 int nLeft;
7235
7236 nLeft = len;
7237#if 0
7238 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7239 rec_id, len, flag,
7240 duration, vpts, vpts_valid, poc_number);
7241#endif
7242 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7243 rec_id, len, flag, vpts);
7244
7245 if (len == 96) {
7246 int i;
7247 nLeft = 72;
7248 while (nLeft >= 16) {
7249 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7250 pdata[0], pdata[1], pdata[2], pdata[3],
7251 pdata[4], pdata[5], pdata[6], pdata[7],
7252 pdata[8], pdata[9], pdata[10], pdata[11],
7253 pdata[12], pdata[13], pdata[14], pdata[15]);
7254 nLeft -= 16;
7255 pdata += 16;
7256 }
7257
7258
7259 while (nLeft > 0) {
7260 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7261 pdata[0], pdata[1], pdata[2], pdata[3],
7262 pdata[4], pdata[5], pdata[6], pdata[7]);
7263 nLeft -= 8;
7264 pdata += 8;
7265 }
7266
7267 i = 0;
7268 nLeft = 96-72;
7269 while (i < nLeft) {
7270 if (pdata[0] != 0) {
7271 pr_info("some data error\n");
7272 break;
7273 }
7274 pdata++;
7275 i++;
7276 }
7277 } else {
7278 while (nLeft >= 16) {
7279 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7280 pdata[0], pdata[1], pdata[2], pdata[3],
7281 pdata[4], pdata[5], pdata[6], pdata[7],
7282 pdata[8], pdata[9], pdata[10], pdata[11],
7283 pdata[12], pdata[13], pdata[14], pdata[15]);
7284 nLeft -= 16;
7285 pdata += 16;
7286 }
7287
7288
7289 while (nLeft > 0) {
7290 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7291 pdata[0], pdata[1], pdata[2], pdata[3],
7292 pdata[4], pdata[5], pdata[6], pdata[7]);
7293 nLeft -= 8;
7294 pdata += 8;
7295 }
7296
7297 }
7298}
7299
7300static void push_to_buf(struct vdec_h264_hw_s *hw,
7301 u8 *pdata,
7302 int len,
7303 struct userdata_meta_info_t *pmeta);
7304
7305static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7306 struct mh264_userdata_record_t *record)
7307{
7308 if (record && hw) {
7309 u8 *pdata;
7310
7311 pdata = hw->userdata_info.data_buf + record->rec_start;
7312/*
7313 print_data(pdata,
7314 record->rec_len,
7315 record->meta_info.flags,
7316 record->meta_info.duration,
7317 record->meta_info.vpts,
7318 record->meta_info.vpts_valid,
7319 n_record_id);
7320*/
7321 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7322 n_userdata_id++;
7323 }
7324}
7325
7326
7327static void push_to_buf(struct vdec_h264_hw_s *hw,
7328 u8 *pdata, int len,
7329 struct userdata_meta_info_t *pmeta)
7330{
7331 u32 *pLen;
7332 int info_cnt;
7333 u8 *pbuf_end;
7334
7335 if (!user_data_buf)
7336 return;
7337
7338 if (bskip) {
7339 pr_info("over size, skip\n");
7340 return;
7341 }
7342 info_cnt = 0;
7343 pLen = (u32 *)pbuf_start;
7344
7345 *pLen = len;
7346 pbuf_start += sizeof(u32);
7347 info_cnt++;
7348 pLen++;
7349
7350 *pLen = pmeta->poc_number;
7351 pbuf_start += sizeof(u32);
7352 info_cnt++;
7353 pLen++;
7354
7355 *pLen = pmeta->duration;
7356 pbuf_start += sizeof(u32);
7357 info_cnt++;
7358 pLen++;
7359
7360 *pLen = pmeta->flags;
7361 pbuf_start += sizeof(u32);
7362 info_cnt++;
7363 pLen++;
7364
7365 *pLen = pmeta->vpts;
7366 pbuf_start += sizeof(u32);
7367 info_cnt++;
7368 pLen++;
7369
7370 *pLen = pmeta->vpts_valid;
7371 pbuf_start += sizeof(u32);
7372 info_cnt++;
7373 pLen++;
7374
7375
7376 *pLen = n_userdata_id;
7377 pbuf_start += sizeof(u32);
7378 info_cnt++;
7379 pLen++;
7380
7381
7382
7383 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7384 if (pdata + len > pbuf_end) {
7385 int first_section_len;
7386
7387 first_section_len = pbuf_end - pdata;
7388 memcpy(pbuf_start, pdata, first_section_len);
7389 pdata = (u8 *)hw->sei_user_data_buffer;
7390 pbuf_start += first_section_len;
7391 memcpy(pbuf_start, pdata, len - first_section_len);
7392 pbuf_start += len - first_section_len;
7393 } else {
7394 memcpy(pbuf_start, pdata, len);
7395 pbuf_start += len;
7396 }
7397
7398 total_len += len + info_cnt * sizeof(u32);
7399 if (total_len >= MAX_USER_DATA_SIZE-4096)
7400 bskip = 1;
7401}
7402
7403static void show_user_data_buf(void)
7404{
7405 u8 *pbuf;
7406 int len;
7407 unsigned int flag;
7408 unsigned int duration;
7409 unsigned int vpts;
7410 unsigned int vpts_valid;
7411 unsigned int poc_number;
7412 int rec_id;
7413
7414 pr_info("show user data buf\n");
7415 pbuf = user_data_buf;
7416
7417 while (pbuf < pbuf_start) {
7418 u32 *pLen;
7419
7420 pLen = (u32 *)pbuf;
7421
7422 len = *pLen;
7423 pLen++;
7424 pbuf += sizeof(u32);
7425
7426 poc_number = *pLen;
7427 pLen++;
7428 pbuf += sizeof(u32);
7429
7430 duration = *pLen;
7431 pLen++;
7432 pbuf += sizeof(u32);
7433
7434 flag = *pLen;
7435 pLen++;
7436 pbuf += sizeof(u32);
7437
7438 vpts = *pLen;
7439 pLen++;
7440 pbuf += sizeof(u32);
7441
7442 vpts_valid = *pLen;
7443 pLen++;
7444 pbuf += sizeof(u32);
7445
7446 rec_id = *pLen;
7447 pLen++;
7448 pbuf += sizeof(u32);
7449
7450 print_data(pbuf, len, poc_number, flag,
7451 duration, vpts,
7452 vpts_valid, rec_id);
7453 pbuf += len;
7454 msleep(30);
7455 }
7456}
7457
7458static int vmh264_init_userdata_dump(void)
7459{
7460 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7461 if (user_data_buf)
7462 return 1;
7463 else
7464 return 0;
7465}
7466
7467static void vmh264_dump_userdata(void)
7468{
7469 if (user_data_buf) {
7470 show_user_data_buf();
7471 kfree(user_data_buf);
7472 user_data_buf = NULL;
7473 }
7474}
7475
7476static void vmh264_reset_user_data_buf(void)
7477{
7478 total_len = 0;
7479 pbuf_start = user_data_buf;
7480 bskip = 0;
7481 n_userdata_id = 0;
7482}
7483#endif
7484
7485
7486static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7487 int frame_type,
7488 u32 vpts,
7489 u32 vpts_valid)
7490{
7491 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7492
7493 unsigned char *pdata;
7494 u8 *pmax_sei_data_buffer;
7495 u8 *sei_data_buf;
7496 int i;
7497 int wp;
7498 int data_length;
7499 struct mh264_userdata_record_t *p_userdata_rec;
7500
7501
7502#ifdef MH264_USERDATA_ENABLE
7503 struct userdata_meta_info_t meta_info;
7504 memset(&meta_info, 0, sizeof(meta_info));
7505#endif
7506
7507 if (hw->sei_itu_data_len <= 0)
7508 return;
7509
7510 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7511 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7512 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7513 for (i = 0; i < hw->sei_itu_data_len; i++) {
7514 *pdata++ = sei_data_buf[i];
7515 if (pdata >= pmax_sei_data_buffer)
7516 pdata = (u8 *)hw->sei_user_data_buffer;
7517 }
7518
7519 hw->sei_user_data_wp = (hw->sei_user_data_wp
7520 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7521 hw->sei_itu_data_len = 0;
7522
7523#ifdef MH264_USERDATA_ENABLE
7524 meta_info.duration = hw->frame_dur;
7525 meta_info.flags |= (VFORMAT_H264 << 3);
7526
7527 meta_info.vpts = vpts;
7528 meta_info.vpts_valid = vpts_valid;
7529 meta_info.poc_number =
7530 p_H264_Dpb->mVideo.dec_picture->poc;
7531
7532
7533 wp = hw->sei_user_data_wp;
7534
7535 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7536 data_length = wp - hw->userdata_info.last_wp;
7537 else
7538 data_length = wp + hw->userdata_info.buf_len
7539 - hw->userdata_info.last_wp;
7540
7541 if (data_length & 0x7)
7542 data_length = (((data_length + 8) >> 3) << 3);
7543
7544 p_userdata_rec = &hw->ud_record;
7545 p_userdata_rec->meta_info = meta_info;
7546 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7547 p_userdata_rec->rec_len = data_length;
7548 hw->userdata_info.last_wp = wp;
7549
7550 p_userdata_rec->meta_info.flags |=
7551 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7552
7553 hw->wait_for_udr_send = 1;
7554 vdec_schedule_work(&hw->user_data_ready_work);
7555#endif
7556}
7557
7558
7559static void user_data_ready_notify_work(struct work_struct *work)
7560{
7561 struct vdec_h264_hw_s *hw = container_of(work,
7562 struct vdec_h264_hw_s, user_data_ready_work);
7563
7564
7565 mutex_lock(&hw->userdata_mutex);
7566
7567 hw->userdata_info.records[hw->userdata_info.write_index]
7568 = hw->ud_record;
7569 hw->userdata_info.write_index++;
7570 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7571 hw->userdata_info.write_index = 0;
7572
7573 mutex_unlock(&hw->userdata_mutex);
7574
7575#ifdef DUMP_USERDATA_RECORD
7576 dump_userdata_record(hw, &hw->ud_record);
7577#endif
7578 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7579
7580 hw->wait_for_udr_send = 0;
7581}
7582
7583static int vmh264_user_data_read(struct vdec_s *vdec,
7584 struct userdata_param_t *puserdata_para)
7585{
7586 struct vdec_h264_hw_s *hw = NULL;
7587 int rec_ri, rec_wi;
7588 int rec_len;
7589 u8 *rec_data_start;
7590 u8 *pdest_buf;
7591 struct mh264_userdata_record_t *p_userdata_rec;
7592 u32 data_size;
7593 u32 res;
7594 int copy_ok = 1;
7595
7596 hw = (struct vdec_h264_hw_s *)vdec->private;
7597
7598 pdest_buf = puserdata_para->pbuf_addr;
7599
7600 mutex_lock(&hw->userdata_mutex);
7601
7602/*
7603 pr_info("ri = %d, wi = %d\n",
7604 lg_p_mpeg12_userdata_info->read_index,
7605 lg_p_mpeg12_userdata_info->write_index);
7606*/
7607 rec_ri = hw->userdata_info.read_index;
7608 rec_wi = hw->userdata_info.write_index;
7609
7610 if (rec_ri == rec_wi) {
7611 mutex_unlock(&hw->userdata_mutex);
7612 return 0;
7613 }
7614
7615 p_userdata_rec = hw->userdata_info.records + rec_ri;
7616
7617 rec_len = p_userdata_rec->rec_len;
7618 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7619/*
7620 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7621 p_userdata_rec->rec_len,
7622 p_userdata_rec->rec_start,
7623 puserdata_para->buf_len);
7624*/
7625 if (rec_len <= puserdata_para->buf_len) {
7626 /* dvb user data buffer is enought to
7627 copy the whole recored. */
7628 data_size = rec_len;
7629 if (rec_data_start + data_size
7630 > hw->userdata_info.data_buf_end) {
7631 int first_section_len;
7632
7633 first_section_len = hw->userdata_info.buf_len -
7634 p_userdata_rec->rec_start;
7635 res = (u32)copy_to_user((void *)pdest_buf,
7636 (void *)rec_data_start,
7637 first_section_len);
7638 if (res) {
7639 pr_info("p1 read not end res=%d, request=%d\n",
7640 res, first_section_len);
7641 copy_ok = 0;
7642
7643 p_userdata_rec->rec_len -=
7644 first_section_len - res;
7645 p_userdata_rec->rec_start +=
7646 first_section_len - res;
7647 puserdata_para->data_size =
7648 first_section_len - res;
7649 } else {
7650 res = (u32)copy_to_user(
7651 (void *)(pdest_buf+first_section_len),
7652 (void *)hw->userdata_info.data_buf,
7653 data_size - first_section_len);
7654 if (res) {
7655 pr_info("p2 read not end res=%d, request=%d\n",
7656 res, data_size);
7657 copy_ok = 0;
7658 }
7659 p_userdata_rec->rec_len -=
7660 data_size - res;
7661 p_userdata_rec->rec_start =
7662 data_size - first_section_len - res;
7663 puserdata_para->data_size =
7664 data_size - res;
7665 }
7666 } else {
7667 res = (u32)copy_to_user((void *)pdest_buf,
7668 (void *)rec_data_start,
7669 data_size);
7670 if (res) {
7671 pr_info("p3 read not end res=%d, request=%d\n",
7672 res, data_size);
7673 copy_ok = 0;
7674 }
7675 p_userdata_rec->rec_len -= data_size - res;
7676 p_userdata_rec->rec_start += data_size - res;
7677 puserdata_para->data_size = data_size - res;
7678 }
7679
7680 if (copy_ok) {
7681 hw->userdata_info.read_index++;
7682 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7683 hw->userdata_info.read_index = 0;
7684 }
7685 } else {
7686 /* dvb user data buffer is not enought
7687 to copy the whole recored. */
7688 data_size = puserdata_para->buf_len;
7689 if (rec_data_start + data_size
7690 > hw->userdata_info.data_buf_end) {
7691 int first_section_len;
7692
7693 first_section_len = hw->userdata_info.buf_len -
7694 p_userdata_rec->rec_start;
7695 res = (u32)copy_to_user((void *)pdest_buf,
7696 (void *)rec_data_start,
7697 first_section_len);
7698 if (res) {
7699 pr_info("p4 read not end res=%d, request=%d\n",
7700 res, first_section_len);
7701 copy_ok = 0;
7702 p_userdata_rec->rec_len -=
7703 first_section_len - res;
7704 p_userdata_rec->rec_start +=
7705 first_section_len - res;
7706 puserdata_para->data_size =
7707 first_section_len - res;
7708 } else {
7709 /* first secton copy is ok*/
7710 res = (u32)copy_to_user(
7711 (void *)(pdest_buf+first_section_len),
7712 (void *)hw->userdata_info.data_buf,
7713 data_size - first_section_len);
7714 if (res) {
7715 pr_info("p5 read not end res=%d, request=%d\n",
7716 res,
7717 data_size - first_section_len);
7718 copy_ok = 0;
7719 }
7720
7721 p_userdata_rec->rec_len -=
7722 data_size - res;
7723 p_userdata_rec->rec_start =
7724 data_size - first_section_len - res;
7725 puserdata_para->data_size =
7726 data_size - res;
7727 }
7728 } else {
7729 res = (u32)copy_to_user((void *)pdest_buf,
7730 (void *)rec_data_start,
7731 data_size);
7732 if (res) {
7733 pr_info("p6 read not end res=%d, request=%d\n",
7734 res, data_size);
7735 copy_ok = 0;
7736 }
7737
7738 p_userdata_rec->rec_len -= data_size - res;
7739 p_userdata_rec->rec_start += data_size - res;
7740 puserdata_para->data_size = data_size - res;
7741 }
7742
7743 if (copy_ok) {
7744 hw->userdata_info.read_index++;
7745 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7746 hw->userdata_info.read_index = 0;
7747 }
7748
7749 }
7750 puserdata_para->meta_info = p_userdata_rec->meta_info;
7751
7752 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7753 puserdata_para->meta_info.records_in_que =
7754 hw->userdata_info.write_index -
7755 hw->userdata_info.read_index;
7756 else
7757 puserdata_para->meta_info.records_in_que =
7758 hw->userdata_info.write_index +
7759 USERDATA_FIFO_NUM -
7760 hw->userdata_info.read_index;
7761
7762 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7763
7764 mutex_unlock(&hw->userdata_mutex);
7765
7766 return 1;
7767}
7768
7769static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7770{
7771 struct vdec_h264_hw_s *hw = NULL;
7772
7773 hw = (struct vdec_h264_hw_s *)vdec->private;
7774
7775 if (hw) {
7776 mutex_lock(&hw->userdata_mutex);
7777 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7778 bInit,
7779 hw->userdata_info.read_index,
7780 hw->userdata_info.write_index);
7781 hw->userdata_info.read_index = 0;
7782 hw->userdata_info.write_index = 0;
7783
7784 if (bInit)
7785 hw->userdata_info.last_wp = 0;
7786 mutex_unlock(&hw->userdata_mutex);
7787 }
7788}
7789
7790static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7791{
7792 amstream_wakeup_userdata_poll(vdec);
7793}
7794
7795#endif
7796
7797
7798static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7799 struct vdec_s *vdec, int from)
7800{
7801 /* finished decoding one frame or error,
7802 * notify vdec core to switch context
7803 */
7804 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7805 "%s dec_result %d %x %x %x\n",
7806 __func__,
7807 hw->dec_result,
7808 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7809 READ_VREG(VLD_MEM_VIFIFO_WP),
7810 READ_VREG(VLD_MEM_VIFIFO_RP));
7811 if (!hw->mmu_enable) {
7812 mutex_lock(&vmh264_mutex);
7813 dealloc_buf_specs(hw, 0);
7814 mutex_unlock(&vmh264_mutex);
7815 }
7816 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7817 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7818 u32 param1 = READ_VREG(AV_SCRATCH_1);
7819 u32 param2 = READ_VREG(AV_SCRATCH_2);
7820 u32 param3 = READ_VREG(AV_SCRATCH_6);
7821 u32 param4 = READ_VREG(AV_SCRATCH_B);
7822
7823 if (vh264_set_params(hw, param1,
7824 param2, param3, param4) < 0)
7825 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7826
7827 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7828 (hw->dpb.mDPB.size<<16) |
7829 (hw->dpb.mDPB.size<<8));
7830
7831 if (hw->is_used_v4l) {
7832 struct aml_vcodec_ctx *ctx =
7833 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7834
7835 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7836 struct aml_vdec_ps_infos ps;
7837
7838 ps.visible_width = hw->frame_width;
7839 ps.visible_height = hw->frame_height;
7840 ps.coded_width = ALIGN(hw->frame_width, 64);
7841 ps.coded_height = ALIGN(hw->frame_height, 64);
7842 ps.dpb_size = hw->dpb.mDPB.size;
7843 hw->v4l_params_parsed = true;
7844 vdec_v4l_set_ps_infos(ctx, &ps);
7845 }
7846 }
7847
7848 start_process_time(hw);
7849 return;
7850 } else
7851 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7852 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7853 && (hw_to_vdec(hw)->next_status !=
7854 VDEC_STATUS_DISCONNECTED)) {
7855 if (!vdec_has_more_input(vdec)) {
7856 hw->dec_result = DEC_RESULT_EOS;
7857 vdec_schedule_work(&hw->work);
7858 return;
7859 }
7860
7861 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7862 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7863 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7864 __func__,
7865 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7866 READ_VREG(VLD_MEM_VIFIFO_WP),
7867 READ_VREG(VLD_MEM_VIFIFO_RP));
7868 mutex_lock(&hw->chunks_mutex);
7869 vdec_vframe_dirty(vdec, hw->chunk);
7870 hw->chunk = NULL;
7871 mutex_unlock(&hw->chunks_mutex);
7872 vdec_clean_input(vdec);
7873 }
7874 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7875 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7876 > get_data_timeout_val)) {
7877 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7878 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7879 __func__);
7880 goto result_done;
7881 }
7882 if (is_buffer_available(vdec)) {
7883 int r;
7884 int decode_size;
7885 r = vdec_prepare_input(vdec, &hw->chunk);
7886 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7887 VDEC_STATUS_DISCONNECTED)) {
7888 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7889
7890 dpb_print(DECODE_ID(hw),
7891 PRINT_FLAG_VDEC_DETAIL,
7892 "vdec_prepare_input: Insufficient data\n");
7893 vdec_schedule_work(&hw->work);
7894 return;
7895 }
7896 hw->dec_result = DEC_RESULT_NONE;
7897 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7898 "%s: chunk size 0x%x\n",
7899 __func__, hw->chunk->size);
7900
7901 if (dpb_is_debug(DECODE_ID(hw),
7902 PRINT_FRAMEBASE_DATA)) {
7903 int jj;
7904 u8 *data = NULL;
7905
7906 if (!hw->chunk->block->is_mapped)
7907 data = codec_mm_vmap(
7908 hw->chunk->block->start +
7909 hw->chunk->offset, r);
7910 else
7911 data = ((u8 *)
7912 hw->chunk->block->start_virt)
7913 + hw->chunk->offset;
7914
7915 for (jj = 0; jj < r; jj++) {
7916 if ((jj & 0xf) == 0)
7917 dpb_print(DECODE_ID(hw),
7918 PRINT_FRAMEBASE_DATA,
7919 "%06x:", jj);
7920 dpb_print_cont(DECODE_ID(hw),
7921 PRINT_FRAMEBASE_DATA,
7922 "%02x ", data[jj]);
7923 if (((jj + 1) & 0xf) == 0)
7924 dpb_print_cont(DECODE_ID(hw),
7925 PRINT_FRAMEBASE_DATA,
7926 "\n");
7927 }
7928
7929 if (!hw->chunk->block->is_mapped)
7930 codec_mm_unmap_phyaddr(data);
7931 }
7932 WRITE_VREG(POWER_CTL_VLD,
7933 READ_VREG(POWER_CTL_VLD) |
7934 (0 << 10) | (1 << 9) | (1 << 6));
7935 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7936 decode_size = hw->chunk->size +
7937 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7938 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7939 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7940 vdec_enable_input(vdec);
7941
7942 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7943 start_process_time(hw);
7944 } else{
7945 if (hw_to_vdec(hw)->next_status
7946 != VDEC_STATUS_DISCONNECTED) {
7947 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7948 vdec_schedule_work(&hw->work);
7949 }
7950 }
7951 return;
7952 } else if (hw->dec_result == DEC_RESULT_DONE) {
7953 /* if (!hw->ctx_valid)
7954 hw->ctx_valid = 1; */
7955result_done:
7956 if (hw->mmu_enable
7957 && hw->frame_busy && hw->frame_done) {
7958 long used_4k_num;
7959 hevc_sao_wait_done(hw);
7960 if (hw->hevc_cur_buf_idx != 0xffff) {
7961 used_4k_num =
7962 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7963 if (used_4k_num >= 0)
7964 dpb_print(DECODE_ID(hw),
7965 PRINT_FLAG_MMU_DETAIL,
7966 "release unused buf , used_4k_num %ld index %d\n",
7967 used_4k_num, hw->hevc_cur_buf_idx);
7968 hevc_mmu_dma_check(hw_to_vdec(hw));
7969 decoder_mmu_box_free_idx_tail(
7970 hw->mmu_box,
7971 hw->hevc_cur_buf_idx,
7972 used_4k_num);
7973 hw->hevc_cur_buf_idx = 0xffff;
7974 }
7975 }
7976 decode_frame_count[DECODE_ID(hw)]++;
7977 amvdec_stop();
7978 if (!vdec_is_support_4k()) {
7979 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7980 clk_adj_frame_count++;
7981 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7982 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7983 }
7984 }
7985 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7986 "%s dec_result %d %x %x %x\n",
7987 __func__,
7988 hw->dec_result,
7989 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7990 READ_VREG(VLD_MEM_VIFIFO_WP),
7991 READ_VREG(VLD_MEM_VIFIFO_RP));
7992 mutex_lock(&hw->chunks_mutex);
7993 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7994 hw->chunk = NULL;
7995 mutex_unlock(&hw->chunks_mutex);
7996 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7997 /*
7998 stream base: stream buf empty or timeout
7999 frame base: vdec_prepare_input fail
8000 */
8001 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8002 VDEC_STATUS_DISCONNECTED)) {
8003 hw->dec_result = DEC_RESULT_EOS;
8004 vdec_schedule_work(&hw->work);
8005 return;
8006 }
8007 hw->next_again_flag = 1;
8008 } else if (hw->dec_result == DEC_RESULT_EOS) {
8009 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8010 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8011 "%s: end of stream\n",
8012 __func__);
8013 amvdec_stop();
8014 if (hw->mmu_enable)
8015 amhevc_stop();
8016 hw->eos = 1;
8017 flush_dpb(p_H264_Dpb);
8018 if (hw->is_used_v4l)
8019 notify_v4l_eos(hw_to_vdec(hw));
8020 mutex_lock(&hw->chunks_mutex);
8021 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8022 hw->chunk = NULL;
8023 mutex_unlock(&hw->chunks_mutex);
8024 vdec_clean_input(vdec);
8025 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8026 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8027 "%s: force exit\n",
8028 __func__);
8029 amvdec_stop();
8030 if (hw->mmu_enable)
8031 amhevc_stop();
8032 if (hw->stat & STAT_ISR_REG) {
8033 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8034 hw->stat &= ~STAT_ISR_REG;
8035 }
8036 }
8037 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8038 del_timer_sync(&hw->check_timer);
8039 hw->stat &= ~STAT_TIMER_ARM;
8040
8041 wait_vmh264_search_done(hw);
8042 /* mark itself has all HW resource released and input released */
8043
8044#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8045 if (hw->switch_dvlayer_flag) {
8046 if (vdec->slave)
8047 vdec_set_next_sched(vdec, vdec->slave);
8048 else if (vdec->master)
8049 vdec_set_next_sched(vdec, vdec->master);
8050 } else if (vdec->slave || vdec->master)
8051 vdec_set_next_sched(vdec, vdec);
8052#endif
8053
8054 if (from == 1) {
8055 /* This is a timeout work */
8056 if (work_pending(&hw->work)) {
8057 /*
8058 * The vh264_work arrives at the last second,
8059 * give it a chance to handle the scenario.
8060 */
8061 return;
8062 }
8063 }
8064
8065 /* mark itself has all HW resource released and input released */
8066 if (vdec->parallel_dec == 1) {
8067 if (hw->mmu_enable == 0)
8068 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8069 else
8070 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8071 } else
8072 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8073
8074 wake_up_interruptible(&hw->wait_q);
8075
8076 if (hw->is_used_v4l) {
8077 struct aml_vcodec_ctx *ctx =
8078 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8079
8080 if (ctx->param_sets_from_ucode &&
8081 !hw->v4l_params_parsed)
8082 vdec_v4l_write_frame_sync(ctx);
8083 }
8084
8085 if (hw->vdec_cb)
8086 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8087}
8088
8089
8090static void vh264_work(struct work_struct *work)
8091{
8092 struct vdec_h264_hw_s *hw = container_of(work,
8093 struct vdec_h264_hw_s, work);
8094 struct vdec_s *vdec = hw_to_vdec(hw);
8095
8096 vh264_work_implement(hw, vdec, 0);
8097}
8098
8099
8100static void vh264_timeout_work(struct work_struct *work)
8101{
8102 struct vdec_h264_hw_s *hw = container_of(work,
8103 struct vdec_h264_hw_s, timeout_work);
8104 struct vdec_s *vdec = hw_to_vdec(hw);
8105
8106 if (work_pending(&hw->work))
8107 return;
8108
8109 vh264_work_implement(hw, vdec, 1);
8110}
8111
8112static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8113{
8114 bool ret = 0;
8115 struct vdec_h264_hw_s *hw =
8116 (struct vdec_h264_hw_s *)vdec->private;
8117 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8118 CODEC_MM_FLAGS_TVP : 0;
8119
8120 if (!hw->first_sc_checked && hw->mmu_enable) {
8121 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8122 hw->first_sc_checked =1;
8123 dpb_print(DECODE_ID(hw), 0,
8124 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8125 size, (hw->need_cache_size >> PAGE_SHIFT),
8126 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8127 }
8128
8129 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8130 && pre_decode_buf_level != 0) {
8131 u32 rp, wp, level;
8132
8133 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8134 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8135 if (wp < rp)
8136 level = vdec->input.size + wp - rp;
8137 else
8138 level = wp - rp;
8139
8140 if (level < pre_decode_buf_level)
8141 return 0;
8142 }
8143
8144#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8145 if (vdec->master)
8146 return 0;
8147#endif
8148 if (hw->eos)
8149 return 0;
8150
8151 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8152 return 0;
8153
8154 if (disp_vframe_valve_level &&
8155 kfifo_len(&hw->display_q) >=
8156 disp_vframe_valve_level) {
8157 hw->valve_count--;
8158 if (hw->valve_count <= 0)
8159 hw->valve_count = 2;
8160 else
8161 return 0;
8162 }
8163 if (hw->next_again_flag &&
8164 (!vdec_frame_based(vdec))) {
8165 u32 parser_wr_ptr =
8166 READ_PARSER_REG(PARSER_VIDEO_WP);
8167 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8168 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8169 again_threshold) {
8170 int r = vdec_sync_input(vdec);
8171 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8172 "%s buf lelvel:%x\n", __func__, r);
8173 return 0;
8174 }
8175 }
8176
8177 if (h264_debug_flag & 0x20000000) {
8178 /* pr_info("%s, a\n", __func__); */
8179 ret = 1;
8180 } else
8181 ret = is_buffer_available(vdec);
8182
8183#ifdef CONSTRAIN_MAX_BUF_NUM
8184 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8185 if (run_ready_max_vf_only_num > 0 &&
8186 get_vf_ref_only_buf_count(hw) >=
8187 run_ready_max_vf_only_num
8188 )
8189 ret = 0;
8190 if (run_ready_display_q_num > 0 &&
8191 kfifo_len(&hw->display_q) >=
8192 run_ready_display_q_num)
8193 ret = 0;
8194 /*avoid more buffers consumed when
8195 switching resolution*/
8196 if (run_ready_max_buf_num == 0xff &&
8197 get_used_buf_count(hw) >
8198 hw->dpb.mDPB.size)
8199 ret = 0;
8200 else if (run_ready_max_buf_num &&
8201 get_used_buf_count(hw) >=
8202 run_ready_max_buf_num)
8203 ret = 0;
8204 }
8205#endif
8206 if (hw->is_used_v4l) {
8207 struct aml_vcodec_ctx *ctx =
8208 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8209
8210 if (ctx->param_sets_from_ucode &&
8211 !ctx->v4l_codec_ready &&
8212 hw->v4l_params_parsed) {
8213 ret = 0; /*the params has parsed.*/
8214 } else if (!ctx->v4l_codec_dpb_ready)
8215 ret = 0;
8216 }
8217
8218 if (ret)
8219 not_run_ready[DECODE_ID(hw)] = 0;
8220 else
8221 not_run_ready[DECODE_ID(hw)]++;
8222 if (vdec->parallel_dec == 1) {
8223 if (hw->mmu_enable == 0)
8224 return ret ? (CORE_MASK_VDEC_1) : 0;
8225 else
8226 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8227 } else
8228 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8229}
8230
8231static unsigned char get_data_check_sum
8232 (struct vdec_h264_hw_s *hw, int size)
8233{
8234 int jj;
8235 int sum = 0;
8236 u8 *data = NULL;
8237
8238 if (!hw->chunk->block->is_mapped)
8239 data = codec_mm_vmap(hw->chunk->block->start +
8240 hw->chunk->offset, size);
8241 else
8242 data = ((u8 *)hw->chunk->block->start_virt)
8243 + hw->chunk->offset;
8244
8245 for (jj = 0; jj < size; jj++)
8246 sum += data[jj];
8247
8248 if (!hw->chunk->block->is_mapped)
8249 codec_mm_unmap_phyaddr(data);
8250 return sum;
8251}
8252
8253static void run(struct vdec_s *vdec, unsigned long mask,
8254 void (*callback)(struct vdec_s *, void *), void *arg)
8255{
8256 struct vdec_h264_hw_s *hw =
8257 (struct vdec_h264_hw_s *)vdec->private;
8258 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8259 int size, ret = -1;
8260
8261 run_count[DECODE_ID(hw)]++;
8262 vdec_reset_core(vdec);
8263 if (hw->mmu_enable)
8264 hevc_reset_core(vdec);
8265 hw->vdec_cb_arg = arg;
8266 hw->vdec_cb = callback;
8267
8268 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8269 hw->reset_bufmgr_flag = 1;
8270 dpb_print(DECODE_ID(hw), 0,
8271 "kfifo len:%d invaild, need bufmgr reset\n",
8272 kfifo_len(&hw->display_q));
8273 }
8274
8275 hw->pre_parser_wr_ptr =
8276 READ_PARSER_REG(PARSER_VIDEO_WP);
8277 hw->next_again_flag = 0;
8278
8279 if (hw->reset_bufmgr_flag ||
8280 ((error_proc_policy & 0x40) &&
8281 p_H264_Dpb->buf_alloc_fail)) {
8282 h264_reset_bufmgr(vdec);
8283 hw->reset_bufmgr_flag = 0;
8284 }
8285
8286 if (h264_debug_cmd & 0xf000) {
8287 if (((h264_debug_cmd >> 12) & 0xf)
8288 == (DECODE_ID(hw) + 1)) {
8289 h264_reconfig(hw);
8290 h264_debug_cmd &= (~0xf000);
8291 }
8292 }
8293 /* hw->chunk = vdec_prepare_input(vdec); */
8294#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8295 if (vdec->slave || vdec->master)
8296 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8297#endif
8298 size = vdec_prepare_input(vdec, &hw->chunk);
8299 if ((size < 0) ||
8300 (input_frame_based(vdec) && hw->chunk == NULL)) {
8301 input_empty[DECODE_ID(hw)]++;
8302 hw->dec_result = DEC_RESULT_AGAIN;
8303
8304 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8305 "vdec_prepare_input: Insufficient data\n");
8306
8307 vdec_schedule_work(&hw->work);
8308 return;
8309 }
8310 input_empty[DECODE_ID(hw)] = 0;
8311
8312 hw->dec_result = DEC_RESULT_NONE;
8313 hw->get_data_count = 0;
8314#if 0
8315 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8316 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8317 READ_VREG(VLD_MEM_VIFIFO_RP),
8318 READ_VREG(VLD_MEM_VIFIFO_WP));
8319#endif
8320
8321 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8322 u8 *data = NULL;
8323
8324 if (!hw->chunk->block->is_mapped)
8325 data = codec_mm_vmap(hw->chunk->block->start +
8326 hw->chunk->offset, size);
8327 else
8328 data = ((u8 *)hw->chunk->block->start_virt)
8329 + hw->chunk->offset;
8330
8331 if (dpb_is_debug(DECODE_ID(hw),
8332 PRINT_FLAG_VDEC_STATUS)
8333 ) {
8334 dpb_print(DECODE_ID(hw), 0,
8335 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8336 __func__, size, get_data_check_sum(hw, size),
8337 data[0], data[1], data[2], data[3],
8338 data[4], data[5], data[size - 4],
8339 data[size - 3], data[size - 2],
8340 data[size - 1]);
8341 }
8342 if (dpb_is_debug(DECODE_ID(hw),
8343 PRINT_FRAMEBASE_DATA)
8344 ) {
8345 int jj;
8346
8347 for (jj = 0; jj < size; jj++) {
8348 if ((jj & 0xf) == 0)
8349 dpb_print(DECODE_ID(hw),
8350 PRINT_FRAMEBASE_DATA,
8351 "%06x:", jj);
8352 dpb_print_cont(DECODE_ID(hw),
8353 PRINT_FRAMEBASE_DATA,
8354 "%02x ", data[jj]);
8355 if (((jj + 1) & 0xf) == 0)
8356 dpb_print_cont(DECODE_ID(hw),
8357 PRINT_FRAMEBASE_DATA,
8358 "\n");
8359 }
8360 }
8361
8362 if (!hw->chunk->block->is_mapped)
8363 codec_mm_unmap_phyaddr(data);
8364 } else
8365 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8366 "%s: %x %x %x %x %x size 0x%x\n",
8367 __func__,
8368 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8369 READ_VREG(VLD_MEM_VIFIFO_WP),
8370 READ_VREG(VLD_MEM_VIFIFO_RP),
8371 READ_PARSER_REG(PARSER_VIDEO_RP),
8372 READ_PARSER_REG(PARSER_VIDEO_WP),
8373 size);
8374
8375 start_process_time(hw);
8376 if (vdec->mc_loaded) {
8377 /*firmware have load before,
8378 and not changes to another.
8379 ignore reload.
8380 */
8381 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8382 } else {
8383
8384 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8385 if (ret < 0) {
8386 amvdec_enable_flag = false;
8387 amvdec_disable();
8388
8389 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8390 "MH264 the %s fw loading failed, err: %x\n",
8391 tee_enabled() ? "TEE" : "local", ret);
8392 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8393 vdec_schedule_work(&hw->work);
8394 return;
8395 }
8396 vdec->mc_type = VFORMAT_H264;
8397 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8398 if (hw->mmu_enable) {
8399 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8400 hw->fw_mmu->data);
8401 if (ret < 0) {
8402 amvdec_enable_flag = false;
8403 amhevc_disable();
8404
8405 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8406 "MH264_MMU the %s fw loading failed, err: %x\n",
8407 tee_enabled() ? "TEE" : "local", ret);
8408 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8409 vdec_schedule_work(&hw->work);
8410 return;
8411 }
8412 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8413 }
8414 vdec->mc_loaded = 1;
8415 }
8416 vmh264_reset_udr_mgr(hw);
8417
8418 if (vh264_hw_ctx_restore(hw) < 0) {
8419 vdec_schedule_work(&hw->work);
8420 return;
8421 }
8422 if (input_frame_based(vdec)) {
8423 int decode_size = 0;
8424
8425 decode_size = hw->chunk->size +
8426 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8427 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8428 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8429 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8430 } else {
8431 if (size <= 0)
8432 size = 0x7fffffff; /*error happen*/
8433 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8434 WRITE_VREG(H264_DECODE_SIZE, size);
8435 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8436 }
8437 config_aux_buf(hw);
8438 config_decode_mode(hw);
8439 vdec_enable_input(vdec);
8440 WRITE_VREG(NAL_SEARCH_CTL, 0);
8441 hw->sei_data_len = 0;
8442 if (enable_itu_t35)
8443 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8444 if (!hw->init_flag) {
8445 if (hw->mmu_enable)
8446 WRITE_VREG(NAL_SEARCH_CTL,
8447 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8448 else
8449 WRITE_VREG(NAL_SEARCH_CTL,
8450 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8451 }
8452 if (udebug_flag)
8453 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8454 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8455
8456 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8457
8458 if (hw->mmu_enable)
8459 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8460 else
8461 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8462 }
8463 amvdec_start();
8464 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8465 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8466 amhevc_start();
8467 if (hw->config_bufmgr_done) {
8468 hevc_mcr_sao_global_hw_init(hw,
8469 (hw->mb_width << 4), (hw->mb_height << 4));
8470 hevc_mcr_config_canv2axitbl(hw, 1);
8471 }
8472 }
8473
8474 /* if (hw->init_flag) { */
8475 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8476 /* } */
8477
8478 hw->init_flag = 1;
8479}
8480
8481static void reset(struct vdec_s *vdec)
8482{
8483 struct vdec_h264_hw_s *hw =
8484 (struct vdec_h264_hw_s *)vdec->private;
8485
8486 pr_info("vmh264 reset\n");
8487
8488 cancel_work_sync(&hw->work);
8489 cancel_work_sync(&hw->notify_work);
8490 if (hw->stat & STAT_VDEC_RUN) {
8491 amhevc_stop();
8492 hw->stat &= ~STAT_VDEC_RUN;
8493 }
8494
8495 if (hw->stat & STAT_TIMER_ARM) {
8496 del_timer_sync(&hw->check_timer);
8497 hw->stat &= ~STAT_TIMER_ARM;
8498 }
8499 hw->eos = 0;
8500 hw->decode_pic_count = 0;
8501 hw->dec_result = DEC_RESULT_NONE;
8502 reset_process_time(hw);
8503 h264_reset_bufmgr(vdec);
8504
8505 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8506}
8507
8508static void h264_reconfig(struct vdec_h264_hw_s *hw)
8509{
8510 int i;
8511 unsigned long flags;
8512 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8513 struct vdec_s *vdec = hw_to_vdec(hw);
8514 dpb_print(DECODE_ID(hw), 0,
8515 "%s\n", __func__);
8516 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8517 all buffers are in display queue (used == 2),
8518 or free (used == 0)
8519 */
8520 if (dpb_is_debug(DECODE_ID(hw),
8521 PRINT_FLAG_DUMP_BUFSPEC))
8522 dump_bufspec(hw, "pre h264_reconfig");
8523
8524 flush_dpb(p_H264_Dpb);
8525 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8526
8527 if (hw->collocate_cma_alloc_addr) {
8528 decoder_bmmu_box_free_idx(
8529 hw->bmmu_box,
8530 BMMU_REF_IDX);
8531 hw->collocate_cma_alloc_addr = 0;
8532 hw->dpb.colocated_mv_addr_start = 0;
8533 hw->dpb.colocated_mv_addr_end = 0;
8534 }
8535 spin_lock_irqsave(&hw->bufspec_lock, flags);
8536 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8537 if (vdec->parallel_dec == 1) {
8538 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
8539 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
8540 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
8541 hw->buffer_spec[i].y_canvas_index = -1;
8542 hw->buffer_spec[i].u_canvas_index = -1;
8543 hw->buffer_spec[i].v_canvas_index = -1;
8544#ifdef VDEC_DW
8545 if (IS_VDEC_DW(hw)) {
8546 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
8547 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
8548 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
8549 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8550 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8551 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8552#endif
8553 }
8554 }
8555 /*make sure buffers not put back to bufmgr when
8556 vf_put is called*/
8557 if (hw->buffer_spec[i].used == 2)
8558 hw->buffer_spec[i].used = 3;
8559
8560 /* ready to release "free buffers"
8561 */
8562 if (hw->buffer_spec[i].used == 0)
8563 hw->buffer_spec[i].used = 4;
8564
8565 hw->buffer_spec[i].canvas_pos = -1;
8566 }
8567 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8568 hw->has_i_frame = 0;
8569 hw->config_bufmgr_done = 0;
8570
8571 if (hw->is_used_v4l) {
8572 mutex_lock(&vmh264_mutex);
8573 dealloc_buf_specs(hw, 1);
8574 mutex_unlock(&vmh264_mutex);
8575 }
8576
8577 if (dpb_is_debug(DECODE_ID(hw),
8578 PRINT_FLAG_DUMP_BUFSPEC))
8579 dump_bufspec(hw, "after h264_reconfig");
8580
8581}
8582
8583#ifdef ERROR_HANDLE_TEST
8584static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8585{
8586 int i;
8587 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8588 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8589 "%s\n", __func__);
8590 remove_dpb_pictures(p_H264_Dpb);
8591 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8592 /*make sure buffers not put back to bufmgr when
8593 vf_put is called*/
8594 if (hw->buffer_spec[i].used == 2)
8595 hw->buffer_spec[i].used = 5;
8596 }
8597
8598}
8599#endif
8600
8601static void h264_reset_bufmgr(struct vdec_s *vdec)
8602{
8603 int i;
8604 ulong timeout;
8605 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8606#if 0
8607 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8608 int actual_dpb_size, max_reference_size;
8609 int reorder_pic_num;
8610 unsigned int colocated_buf_size;
8611 unsigned int colocated_mv_addr_start;
8612 unsigned int colocated_mv_addr_end;
8613 dpb_print(DECODE_ID(hw), 0,
8614 "%s\n", __func__);
8615
8616 for (i = 0; i < VF_POOL_SIZE; i++)
8617 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8618
8619 actual_dpb_size = p_H264_Dpb->mDPB.size;
8620 max_reference_size = p_H264_Dpb->max_reference_size;
8621 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8622
8623 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8624 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8625 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8626
8627 hw->cur_pool++;
8628 if (hw->cur_pool >= VF_POOL_NUM)
8629 hw->cur_pool = 0;
8630
8631 INIT_KFIFO(hw->display_q);
8632 INIT_KFIFO(hw->newframe_q);
8633
8634 for (i = 0; i < VF_POOL_SIZE; i++) {
8635 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8636 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8637 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8638 kfifo_put(&hw->newframe_q, vf);
8639 }
8640
8641 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8642 hw->buffer_spec[i].used = 0;
8643
8644 dpb_init_global(&hw->dpb,
8645 DECODE_ID(hw), 0, 0);
8646 p_H264_Dpb->mDPB.size = actual_dpb_size;
8647 p_H264_Dpb->max_reference_size = max_reference_size;
8648 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8649
8650 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8651 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8652 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8653
8654 p_H264_Dpb->fast_output_enable = fast_output_enable;
8655 hw->has_i_frame = 0;
8656#else
8657 dpb_print(DECODE_ID(hw), 0,
8658 "%s frame count %d to skip %d\n\n",
8659 __func__, hw->decode_pic_count+1,
8660 hw->skip_frame_count);
8661
8662 timeout = jiffies + HZ;
8663 while (kfifo_len(&hw->display_q) > 0) {
8664 if (time_after(jiffies, timeout))
8665 break;
8666 schedule();
8667 }
8668
8669 for (i = 0; i < VF_POOL_SIZE; i++)
8670 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8671
8672 hw->cur_pool++;
8673 if (hw->cur_pool >= VF_POOL_NUM)
8674 hw->cur_pool = 0;
8675
8676 for (i = 0; i < VF_POOL_SIZE; i++)
8677 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8678
8679
8680 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8681
8682 buf_spec_init(hw);
8683
8684 vh264_local_init(hw);
8685 /*hw->decode_pic_count = 0;
8686 hw->seq_info2 = 0;*/
8687
8688 if (hw->is_used_v4l) {
8689 mutex_lock(&vmh264_mutex);
8690 /* detach relationship with v4l buffs.*/
8691 dealloc_buf_specs(hw, 1);
8692 mutex_unlock(&vmh264_mutex);
8693 }
8694
8695 if (vh264_set_params(hw,
8696 hw->cfg_param1,
8697 hw->cfg_param2,
8698 hw->cfg_param3,
8699 hw->cfg_param4) < 0)
8700 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8701
8702 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8703 if (first_i_policy & 0x01)
8704 hw->first_i_policy = (3 << 8) | first_i_policy;
8705
8706 hw->init_flag = 1;
8707 hw->reset_bufmgr_count++;
8708#endif
8709}
8710
8711int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8712{
8713 int ret = -1;
8714 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8715 CODEC_MM_FLAGS_TVP : 0;
8716 int buf_size = 64;
8717
8718 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8719 tvp_flag, hw->mmu_enable);
8720 hw->need_cache_size = buf_size * SZ_1M;
8721 hw->sc_start_time = get_jiffies_64();
8722 if (hw->mmu_enable && !hw->mmu_box) {
8723 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8724 hw->id,
8725 MMU_MAX_BUFFERS,
8726 hw->need_cache_size,
8727 tvp_flag);
8728 if (!hw->mmu_box) {
8729 pr_err("h264 4k alloc mmu box failed!!\n");
8730 return -1;
8731 }
8732 ret = 0;
8733 }
8734 if (!hw->bmmu_box) {
8735 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8736 DRIVER_NAME,
8737 hw->id,
8738 BMMU_MAX_BUFFERS,
8739 4 + PAGE_SHIFT,
8740 CODEC_MM_FLAGS_CMA_CLEAR |
8741 CODEC_MM_FLAGS_FOR_VDECODER |
8742 tvp_flag);
8743 if (hw->bmmu_box)
8744 ret = 0;
8745 }
8746 return ret;
8747}
8748int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8749{
8750 if (hw->mmu_box) {
8751 decoder_mmu_box_free(hw->mmu_box);
8752 hw->mmu_box = NULL;
8753 }
8754 if (hw->bmmu_box) {
8755 decoder_bmmu_box_free(hw->bmmu_box);
8756 hw->bmmu_box = NULL;
8757 }
8758 return 0;
8759}
8760
8761static int ammvdec_h264_probe(struct platform_device *pdev)
8762{
8763 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8764 struct vdec_h264_hw_s *hw = NULL;
8765 char *tmpbuf;
8766 int config_val;
8767
8768 if (pdata == NULL) {
8769 pr_info("\nammvdec_h264 memory resource undefined.\n");
8770 return -EFAULT;
8771 }
8772
8773 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8774 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8775 if (hw == NULL) {
8776 pr_info("\nammvdec_h264 device data allocation failed\n");
8777 return -ENOMEM;
8778 }
8779 hw->id = pdev->id;
8780 hw->platform_dev = pdev;
8781
8782 /* the ctx from v4l2 driver. */
8783 hw->v4l2_ctx = pdata->private;
8784
8785 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8786 hw->canvas_mode = pdata->canvas_mode;
8787 else
8788 hw->canvas_mode = mem_map_mode;
8789
8790 platform_set_drvdata(pdev, pdata);
8791
8792 hw->mmu_enable = 0;
8793 hw->first_head_check_flag = 0;
8794 hw->new_iframe_flag = 0;
8795 hw->ref_err_flush_dpb_flag = 0;
8796
8797 if (pdata->sys_info)
8798 hw->vh264_amstream_dec_info = *pdata->sys_info;
8799
8800 if (force_enable_mmu && pdata->sys_info &&
8801 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8802 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8803 (pdata->sys_info->height * pdata->sys_info->width
8804 > 1920 * 1088))
8805 hw->mmu_enable = 1;
8806
8807 if (hw->mmu_enable &&
8808 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8809 hw->mmu_enable = 0;
8810 pr_info("ionvideo needs disable mmu, path= %d \n",
8811 pdata->frame_base_video_path);
8812 }
8813
8814 if (ammvdec_h264_mmu_init(hw)) {
8815 h264_free_hw_stru(&pdev->dev, (void *)hw);
8816 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8817 return -ENOMEM;
8818 }
8819
8820 if (pdata->config_len) {
8821 /*use ptr config for doubel_write_mode, etc*/
8822 if (get_config_int(pdata->config,
8823 "mh264_double_write_mode", &config_val) == 0)
8824 hw->double_write_mode = config_val;
8825 else
8826 hw->double_write_mode = double_write_mode;
8827
8828 if (get_config_int(pdata->config,
8829 "parm_v4l_codec_enable",
8830 &config_val) == 0)
8831 hw->is_used_v4l = config_val;
8832
8833 if (get_config_int(pdata->config,
8834 "parm_v4l_buffer_margin",
8835 &config_val) == 0)
8836 hw->reorder_dpb_size_margin = config_val;
8837 } else
8838 hw->double_write_mode = double_write_mode;
8839
8840 if (!hw->is_used_v4l)
8841 hw->reorder_dpb_size_margin = reorder_dpb_size_margin;
8842
8843 if (hw->mmu_enable)
8844 hw->double_write_mode &= 0xffff;
8845
8846 if (pdata->parallel_dec == 1) {
8847 int i;
8848 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8849 hw->buffer_spec[i].y_canvas_index = -1;
8850 hw->buffer_spec[i].u_canvas_index = -1;
8851 hw->buffer_spec[i].v_canvas_index = -1;
8852#ifdef VDEC_DW
8853 if (IS_VDEC_DW(hw)) {
8854 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8855 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8856 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8857 }
8858#endif
8859 }
8860 }
8861
8862 dpb_print(DECODE_ID(hw), 0,
8863 "%s mmu_enable %d double_write_mode 0x%x\n",
8864 __func__, hw->mmu_enable, hw->double_write_mode);
8865
8866 pdata->private = hw;
8867 pdata->dec_status = dec_status;
8868 pdata->set_trickmode = vmh264_set_trickmode;
8869 pdata->run_ready = run_ready;
8870 pdata->run = run;
8871 pdata->reset = reset;
8872 pdata->irq_handler = vh264_isr;
8873 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8874 pdata->dump_state = vmh264_dump_state;
8875
8876#ifdef MH264_USERDATA_ENABLE
8877 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8878 pdata->user_data_read = vmh264_user_data_read;
8879 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8880#else
8881 pdata->wakeup_userdata_poll = NULL;
8882 pdata->user_data_read = NULL;
8883 pdata->reset_userdata_fifo = NULL;
8884#endif
8885 if (pdata->use_vfm_path) {
8886 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8887 VFM_DEC_PROVIDER_NAME);
8888 hw->frameinfo_enable = 1;
8889 }
8890#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8891 else if (vdec_dual(pdata)) {
8892 if (dv_toggle_prov_name) /*debug purpose*/
8893 snprintf(pdata->vf_provider_name,
8894 VDEC_PROVIDER_NAME_SIZE,
8895 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8896 VFM_DEC_DVEL_PROVIDER_NAME);
8897 else
8898 snprintf(pdata->vf_provider_name,
8899 VDEC_PROVIDER_NAME_SIZE,
8900 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8901 VFM_DEC_DVBL_PROVIDER_NAME);
8902 }
8903#endif
8904 else
8905 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8906 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8907
8908 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8909 &vf_provider_ops, pdata);
8910
8911 platform_set_drvdata(pdev, pdata);
8912
8913 buf_spec_init(hw);
8914
8915 hw->platform_dev = pdev;
8916
8917#ifdef DUMP_USERDATA_RECORD
8918 vmh264_init_userdata_dump();
8919 vmh264_reset_user_data_buf();
8920#endif
8921 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8922 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8923 h264_free_hw_stru(&pdev->dev, (void *)hw);
8924 pdata->dec_status = NULL;
8925 return -ENOMEM;
8926 }
8927
8928 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8929 DCAC_READ_MARGIN;
8930 if (hw->mmu_enable) {
8931 u32 extif_size = EXTIF_BUF_SIZE;
8932 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8933 extif_size <<= 1;
8934 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8935 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8936 h264_free_hw_stru(&pdev->dev, (void *)hw);
8937 pdata->dec_status = NULL;
8938 return -ENOMEM;
8939 }
8940 }
8941 if (!vdec_secure(pdata)) {
8942#if 1
8943 /*init internal buf*/
8944 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8945 if (tmpbuf) {
8946 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8947 codec_mm_dma_flush(tmpbuf,
8948 V_BUF_ADDR_OFFSET,
8949 DMA_TO_DEVICE);
8950 } else {
8951 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8952 V_BUF_ADDR_OFFSET);
8953 if (tmpbuf) {
8954 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8955 codec_mm_dma_flush(tmpbuf,
8956 V_BUF_ADDR_OFFSET,
8957 DMA_TO_DEVICE);
8958 codec_mm_unmap_phyaddr(tmpbuf);
8959 }
8960 }
8961#else
8962 /*init sps/pps internal buf 64k*/
8963 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8964 + (mem_sps_base - DEF_BUF_START_ADDR));
8965 memset(tmpbuf, 0, 0x10000);
8966 dma_sync_single_for_device(amports_get_dma_device(),
8967 hw->cma_alloc_addr +
8968 (mem_sps_base - DEF_BUF_START_ADDR),
8969 0x10000, DMA_TO_DEVICE);
8970#endif
8971 }
8972 /**/
8973
8974#if 0
8975 if (NULL == hw->sei_data_buffer) {
8976 hw->sei_data_buffer =
8977 dma_alloc_coherent(amports_get_dma_device(),
8978 USER_DATA_SIZE,
8979 &hw->sei_data_buffer_phys, GFP_KERNEL);
8980 if (!hw->sei_data_buffer) {
8981 pr_info("%s: Can not allocate sei_data_buffer\n",
8982 __func__);
8983 ammvdec_h264_mmu_release(hw);
8984 h264_free_hw_stru(&pdev->dev, (void *)hw);
8985 return -ENOMEM;
8986 }
8987 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
8988 sei_data_buffer, sei_data_buffer_phys,
8989 (u32)sei_data_buffer_remap); */
8990 }
8991#endif
8992 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
8993 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
8994
8995 if (vdec_is_support_4k() ||
8996 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
8997 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8998 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
8999 {
9000 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
9001 }else
9002 {
9003 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
9004 }
9005
9006 if (vh264_init(hw) < 0) {
9007 pr_info("\nammvdec_h264 init failed.\n");
9008 ammvdec_h264_mmu_release(hw);
9009 h264_free_hw_stru(&pdev->dev, (void *)hw);
9010 pdata->dec_status = NULL;
9011 return -ENODEV;
9012 }
9013#ifdef MH264_USERDATA_ENABLE
9014 vmh264_crate_userdata_manager(hw,
9015 hw->sei_user_data_buffer,
9016 USER_DATA_SIZE);
9017#endif
9018
9019 vdec_set_prepare_level(pdata, start_decode_buf_level);
9020 if (pdata->parallel_dec == 1) {
9021 if (hw->mmu_enable == 0)
9022 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9023 else {
9024 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9025 | CORE_MASK_COMBINE);
9026 }
9027 } else
9028 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9029 | CORE_MASK_COMBINE);
9030
9031 atomic_set(&hw->vh264_active, 1);
9032
9033 return 0;
9034}
9035
9036static int ammvdec_h264_remove(struct platform_device *pdev)
9037{
9038 struct vdec_h264_hw_s *hw =
9039 (struct vdec_h264_hw_s *)
9040 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9041 int i;
9042
9043 struct vdec_s *vdec = hw_to_vdec(hw);
9044
9045 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9046 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9047 dpb_print(DECODE_ID(hw), 0,
9048 "%s force exit %d\n", __func__, __LINE__);
9049 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9050 vdec_schedule_work(&hw->work);
9051 wait_event_interruptible_timeout(hw->wait_q,
9052 (vdec->status == VDEC_STATUS_CONNECTED),
9053 msecs_to_jiffies(1000)); /* wait for work done */
9054 }
9055
9056 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9057 release_aux_data(hw, i);
9058
9059 atomic_set(&hw->vh264_active, 0);
9060
9061 if (hw->stat & STAT_TIMER_ARM) {
9062 del_timer_sync(&hw->check_timer);
9063 hw->stat &= ~STAT_TIMER_ARM;
9064 }
9065
9066 vh264_stop(hw);
9067#ifdef MH264_USERDATA_ENABLE
9068#ifdef DUMP_USERDATA_RECORD
9069 vmh264_dump_userdata();
9070#endif
9071 vmh264_destroy_userdata_manager(hw);
9072#endif
9073 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9074
9075 atomic_set(&hw->vh264_active, 0);
9076 if (vdec->parallel_dec == 1) {
9077 if (hw->mmu_enable == 0)
9078 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9079 else
9080 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9081 CORE_MASK_COMBINE);
9082 } else
9083 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9084
9085 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9086 if (vdec->parallel_dec == 1) {
9087 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9088 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9089 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9090 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9091 if (IS_VDEC_DW(hw)) {
9092 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9093 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9094 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9095 }
9096 }
9097 }
9098
9099 ammvdec_h264_mmu_release(hw);
9100 h264_free_hw_stru(&pdev->dev, (void *)hw);
9101 clk_adj_frame_count = 0;
9102
9103 return 0;
9104}
9105
9106/****************************************/
9107#ifdef CONFIG_PM
9108static int mh264_suspend(struct device *dev)
9109{
9110 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9111 return 0;
9112}
9113
9114static int mh264_resume(struct device *dev)
9115{
9116 amvdec_resume(to_platform_device(dev));
9117 return 0;
9118}
9119
9120static const struct dev_pm_ops mh264_pm_ops = {
9121 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9122};
9123#endif
9124
9125static struct platform_driver ammvdec_h264_driver = {
9126 .probe = ammvdec_h264_probe,
9127 .remove = ammvdec_h264_remove,
9128 .driver = {
9129 .name = DRIVER_NAME,
9130#ifdef CONFIG_PM
9131 .pm = &mh264_pm_ops,
9132#endif
9133 }
9134};
9135
9136static struct codec_profile_t ammvdec_h264_profile = {
9137 .name = "mh264",
9138 .profile = ""
9139};
9140
9141static struct mconfig hm264_configs[] = {
9142 MC_PU32("h264_debug_flag", &h264_debug_flag),
9143 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9144 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9145 MC_PU32("decode_timeout_val", &decode_timeout_val),
9146 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9147 MC_PU32("reference_buf_margin", &reference_buf_margin),
9148 MC_PU32("radr", &radr),
9149 MC_PU32("rval", &rval),
9150 MC_PU32("h264_debug_mask", &h264_debug_mask),
9151 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9152 MC_PI32("force_rate_streambase", &force_rate_streambase),
9153 MC_PI32("dec_control", &dec_control),
9154 MC_PI32("force_rate_framebase", &force_rate_framebase),
9155 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9156 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9157 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9158#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9159 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9160 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9161 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9162#endif
9163 MC_PU32("i_only_flag", &i_only_flag),
9164 MC_PU32("force_rate_streambase", &force_rate_streambase),
9165};
9166static struct mconfig_node hm264_node;
9167
9168
9169static int __init ammvdec_h264_driver_init_module(void)
9170{
9171 pr_info("ammvdec_h264 module init\n");
9172 if (platform_driver_register(&ammvdec_h264_driver)) {
9173 pr_info("failed to register ammvdec_h264 driver\n");
9174 return -ENODEV;
9175 }
9176
9177 if (vdec_is_support_4k()) {
9178 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9179 ammvdec_h264_profile.profile =
9180 "4k, dwrite, compressed";
9181 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9182 ammvdec_h264_profile.profile = "4k";
9183 }
9184 }
9185
9186 vcodec_profile_register(&ammvdec_h264_profile);
9187 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9188 "mh264", hm264_configs, CONFIG_FOR_RW);
9189 return 0;
9190}
9191
9192static void __exit ammvdec_h264_driver_remove_module(void)
9193{
9194 pr_info("ammvdec_h264 module remove.\n");
9195
9196 platform_driver_unregister(&ammvdec_h264_driver);
9197}
9198
9199/****************************************/
9200module_param(h264_debug_flag, uint, 0664);
9201MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9202
9203module_param(start_decode_buf_level, int, 0664);
9204MODULE_PARM_DESC(start_decode_buf_level,
9205 "\n ammvdec_h264 start_decode_buf_level\n");
9206
9207module_param(pre_decode_buf_level, int, 0664);
9208MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9209
9210module_param(fixed_frame_rate_mode, uint, 0664);
9211MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9212
9213module_param(decode_timeout_val, uint, 0664);
9214MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9215
9216module_param(errordata_timeout_val, uint, 0664);
9217MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9218
9219module_param(get_data_timeout_val, uint, 0664);
9220MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9221
9222module_param(frame_max_data_packet, uint, 0664);
9223MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9224
9225module_param(reorder_dpb_size_margin, uint, 0664);
9226MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9227
9228#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9229module_param(reorder_dpb_size_margin_dv, uint, 0664);
9230MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9231 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9232#endif
9233
9234module_param(reference_buf_margin, uint, 0664);
9235MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9236
9237#ifdef CONSTRAIN_MAX_BUF_NUM
9238module_param(run_ready_max_vf_only_num, uint, 0664);
9239MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9240
9241module_param(run_ready_display_q_num, uint, 0664);
9242MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9243
9244module_param(run_ready_max_buf_num, uint, 0664);
9245MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9246#endif
9247
9248module_param(radr, uint, 0664);
9249MODULE_PARM_DESC(radr, "\nradr\n");
9250
9251module_param(rval, uint, 0664);
9252MODULE_PARM_DESC(rval, "\nrval\n");
9253
9254module_param(h264_debug_mask, uint, 0664);
9255MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9256
9257module_param(h264_debug_cmd, uint, 0664);
9258MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9259
9260module_param(force_rate_streambase, int, 0664);
9261MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9262
9263module_param(dec_control, int, 0664);
9264MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9265
9266module_param(force_rate_framebase, int, 0664);
9267MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9268
9269module_param(force_disp_bufspec_num, int, 0664);
9270MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9271
9272module_param(V_BUF_ADDR_OFFSET, int, 0664);
9273MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9274
9275module_param(prefix_aux_buf_size, uint, 0664);
9276MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9277
9278module_param(suffix_aux_buf_size, uint, 0664);
9279MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9280
9281#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9282module_param(dv_toggle_prov_name, uint, 0664);
9283MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9284
9285module_param(dolby_meta_with_el, uint, 0664);
9286MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9287
9288#endif
9289
9290module_param(fast_output_enable, uint, 0664);
9291MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9292
9293module_param(error_proc_policy, uint, 0664);
9294MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9295
9296module_param(error_skip_count, uint, 0664);
9297MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9298
9299module_param(force_sliding_margin, uint, 0664);
9300MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9301
9302module_param(i_only_flag, uint, 0664);
9303MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9304
9305module_param(first_i_policy, uint, 0664);
9306MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9307
9308module_param(frmbase_cont_bitlevel, uint, 0664);
9309MODULE_PARM_DESC(frmbase_cont_bitlevel,
9310 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9311
9312module_param(frmbase_cont_bitlevel2, uint, 0664);
9313MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9314 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9315
9316module_param(udebug_flag, uint, 0664);
9317MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9318
9319module_param(udebug_pause_pos, uint, 0664);
9320MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9321
9322module_param(udebug_pause_val, uint, 0664);
9323MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9324
9325module_param(udebug_pause_decode_idx, uint, 0664);
9326MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9327
9328module_param(max_alloc_buf_count, uint, 0664);
9329MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9330
9331module_param(enable_itu_t35, uint, 0664);
9332MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9333
9334module_param(endian, uint, 0664);
9335MODULE_PARM_DESC(endian, "\nrval\n");
9336
9337module_param(mmu_enable, uint, 0664);
9338MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9339
9340module_param(force_enable_mmu, uint, 0664);
9341MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9342
9343module_param(again_threshold, uint, 0664);
9344MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9345
9346module_param(stream_mode_start_num, uint, 0664);
9347MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9348
9349/*
9350module_param(trigger_task, uint, 0664);
9351MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9352*/
9353module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9354
9355module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9356
9357module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9358
9359module_param_array(run_count, uint,
9360 &max_decode_instance_num, 0664);
9361
9362module_param_array(not_run_ready, uint,
9363 &max_decode_instance_num, 0664);
9364
9365module_param_array(input_empty, uint,
9366 &max_decode_instance_num, 0664);
9367
9368module_param_array(max_get_frame_interval, uint,
9369 &max_decode_instance_num, 0664);
9370
9371module_param_array(step, uint, &max_decode_instance_num, 0664);
9372
9373module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9374
9375module_param(disp_vframe_valve_level, uint, 0664);
9376MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9377
9378module_param(double_write_mode, uint, 0664);
9379MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9380
9381module_param(mem_map_mode, uint, 0664);
9382MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9383
9384module_param(without_display_mode, uint, 0664);
9385MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9386
9387
9388module_init(ammvdec_h264_driver_init_module);
9389module_exit(ammvdec_h264_driver_remove_module);
9390
9391MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9392MODULE_LICENSE("GPL");
9393
generated by cgit at 2024-05-17 11:09:37 (GMT)