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path: root/drivers/frame_provider/decoder/h264_multi/vmh264.c (plain)
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1/*
2 * drivers/amlogic/amports/vh264.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/random.h>
26
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/frame_sync/ptsserv.h>
29#include <linux/amlogic/media/canvas/canvas.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/vfm/vframe_provider.h>
32#include <linux/amlogic/media/vfm/vframe_receiver.h>
33#include <linux/amlogic/media/utils/vformat.h>
34#include <linux/amlogic/media/frame_sync/tsync.h>
35#include <linux/workqueue.h>
36#include <linux/dma-mapping.h>
37#include <linux/atomic.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/dma-mapping.h>
41#include <linux/dma-contiguous.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44
45#include "../utils/vdec_input.h"
46#include <linux/amlogic/tee.h>
47
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#include "../h264/vh264.h"
52#include "../../../stream_input/parser/streambuf.h"
53#include <linux/delay.h>
54#include <linux/amlogic/media/codec_mm/configs.h>
55#include "../utils/decoder_mmu_box.h"
56#include "../utils/decoder_bmmu_box.h"
57#include "../utils/firmware.h"
58#include <linux/amlogic/tee.h>
59#include <linux/uaccess.h>
60#include "../utils/config_parser.h"
61#include "../../../common/chips/decoder_cpu_ver_info.h"
62#include "../utils/vdec_v4l2_buffer_ops.h"
63#include <linux/crc32.h>
64
65#undef pr_info
66#define pr_info printk
67#define VDEC_DW
68#define DEBUG_UCODE
69#define MEM_NAME "codec_m264"
70#define MULTI_INSTANCE_FRAMEWORK
71/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */
72#include "h264_dpb.h"
73/* #define SEND_PARAM_WITH_REG */
74
75#define DRIVER_NAME "ammvdec_h264"
76#define MODULE_NAME "ammvdec_h264"
77#define DRIVER_HEADER_NAME "ammvdec_h264_header"
78
79#define CHECK_INTERVAL (HZ/100)
80
81#define SEI_DATA_SIZE (8*1024)
82#define SEI_ITU_DATA_SIZE (4*1024)
83
84#define RATE_MEASURE_NUM 8
85#define RATE_CORRECTION_THRESHOLD 5
86#define RATE_2397_FPS 4004 /* 23.97 */
87#define RATE_25_FPS 3840 /* 25 */
88#define RATE_2997_FPS 3203 /* 29.97 */
89#define DUR2PTS(x) ((x)*90/96)
90#define PTS2DUR(x) ((x)*96/90)
91#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
92#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2
93
94#define FIX_FRAME_RATE_OFF 0
95#define FIX_FRAME_RATE_ON 1
96#define FIX_FRAME_RATE_SMOOTH_CHECKING 2
97
98#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001
99#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002
100#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010
101#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020
102
103#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
104
105#define RATE_MEASURE_NUM 8
106#define RATE_CORRECTION_THRESHOLD 5
107#define RATE_24_FPS 4004 /* 23.97 */
108#define RATE_25_FPS 3840 /* 25 */
109#define DUR2PTS(x) ((x)*90/96)
110#define PTS2DUR(x) ((x)*96/90)
111#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96)
112#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2
113
114#define H264_DEV_NUM 9
115
116#define CONSTRAIN_MAX_BUF_NUM
117
118#define H264_MMU
119#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
120
121static int mmu_enable;
122/*mmu do not support mbaff*/
123static int force_enable_mmu = 0;
124unsigned int h264_debug_flag; /* 0xa0000000; */
125unsigned int h264_debug_mask = 0xff;
126 /*
127 *h264_debug_cmd:
128 * 0x1xx, force decoder id of xx to be disconnected
129 */
130unsigned int h264_debug_cmd;
131
132static unsigned int dec_control =
133 DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE |
134 DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE;
135
136static unsigned int force_rate_streambase;
137static unsigned int force_rate_framebase;
138static unsigned int force_disp_bufspec_num;
139static unsigned int fixed_frame_rate_mode;
140static unsigned int error_recovery_mode_in;
141static int start_decode_buf_level = 0x4000;
142static int pre_decode_buf_level = 0x1000;
143static int stream_mode_start_num = 4;
144
145#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
146/*to make reorder size difference of bl and el not too big*/
147static unsigned int reorder_dpb_size_margin_dv = 16;
148#endif
149static unsigned int reorder_dpb_size_margin = 6;
150static unsigned int reference_buf_margin = 4;
151
152#ifdef CONSTRAIN_MAX_BUF_NUM
153static u32 run_ready_max_vf_only_num;
154static u32 run_ready_display_q_num;
155 /*0: not check
156 0xff: mDPB.size
157 */
158static u32 run_ready_max_buf_num = 0xff;
159#endif
160
161#define VDEC_ASSIST_CANVAS_BLK32 0x5
162
163
164static unsigned int max_alloc_buf_count;
165static unsigned int decode_timeout_val = 100;
166static unsigned int errordata_timeout_val = 50;
167static unsigned int get_data_timeout_val = 2000;
168#if 1
169/* H264_DATA_REQUEST does not work, disable it,
170decode has error for data in none continuous address
171*/
172static unsigned int frame_max_data_packet;
173#else
174static unsigned int frame_max_data_packet = 8;
175#endif
176static unsigned int radr;
177static unsigned int rval;
178static u32 endian = 0xff0;
179
180/*
181 udebug_flag:
182 bit 0, enable ucode print
183 bit 1, enable ucode detail print
184 bit 3, disable ucode watchdog
185 bit [31:16] not 0, pos to dump lmem
186 bit 2, pop bits to lmem
187 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
188*/
189static u32 udebug_flag;
190/*
191 when udebug_flag[1:0] is not 0
192 udebug_pause_pos not 0,
193 pause position
194*/
195static u32 udebug_pause_pos;
196/*
197 when udebug_flag[1:0] is not 0
198 and udebug_pause_pos is not 0,
199 pause only when DEBUG_REG2 is equal to this val
200*/
201static u32 udebug_pause_val;
202
203static u32 udebug_pause_decode_idx;
204
205static unsigned int disp_vframe_valve_level;
206
207static unsigned int max_decode_instance_num = H264_DEV_NUM;
208static unsigned int decode_frame_count[H264_DEV_NUM];
209static unsigned int display_frame_count[H264_DEV_NUM];
210static unsigned int max_process_time[H264_DEV_NUM];
211static unsigned int max_get_frame_interval[H264_DEV_NUM];
212static unsigned int run_count[H264_DEV_NUM];
213static unsigned int input_empty[H264_DEV_NUM];
214static unsigned int not_run_ready[H264_DEV_NUM];
215static unsigned int ref_frame_mark_flag[H264_DEV_NUM] =
216{1, 1, 1, 1, 1, 1, 1, 1, 1};
217
218#define VDEC_CLOCK_ADJUST_FRAME 30
219static unsigned int clk_adj_frame_count;
220
221/*
222 *bit[3:0]: 0, run ; 1, pause; 3, step
223 *bit[4]: 1, schedule run
224 */
225static unsigned int step[H264_DEV_NUM];
226
227#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
228static u32 prefix_aux_buf_size = (16 * 1024);
229static u32 suffix_aux_buf_size;
230
231#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
232static u32 dv_toggle_prov_name;
233
234static u32 dolby_meta_with_el;
235#endif
236
237/*
238 bit[8]
239 0: use sys_info[bit 3]
240 not 0:use i_only_flag[7:0]
241 bit[7:0]:
242 bit 0, 1: only display I picture;
243 bit 1, 1: only decode I picture;
244*/
245static unsigned int i_only_flag;
246
247/*
248 error_proc_policy:
249 bit[0] send_error_frame_flag;
250 (valid when bit[31] is 1, otherwise use sysinfo)
251 bit[1] do not decode if config_decode_buf() fail
252 bit[2] force release buf if in deadlock
253 bit[3] force sliding window ref_frames_in_buffer > num_ref_frames
254 bit[4] check inactive of receiver
255 bit[5] reset buffmgr if in deadlock
256 bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail
257 bit[7] reset buffmgr if dpb error
258
259 bit[8] check total mbx/mby of decoded frame
260 bit[9] check ERROR_STATUS_REG
261 bit[10] check reference list
262 bit[11] mark error if dpb error
263 bit[12] i_only when error happen
264 bit[13] 0: mark error according to last pic, 1: ignore mark error
265 bit[14] 0: result done when timeout from ucode. 1: reset bufmgr when timeout.
266*/
267static unsigned int error_proc_policy = 0x4fb6; /*0x1f14*/
268
269
270/*
271 error_skip_count:
272 bit[11:0] error skip frame count
273 bit[15:12] error skip i picture count
274*/
275static unsigned int error_skip_count = (0x2 << 12) | 0x40;
276
277static unsigned int force_sliding_margin;
278/*
279 bit[1:0]:
280 0, start playing from any frame
281 1, start playing from I frame
282 bit[15:8]: the count of skip frames after first I
283 2, start playing from second I frame (decode from the first I)
284 bit[15:8]: the max count of skip frames after first I
285 3, start playing from IDR
286*/
287static unsigned int first_i_policy = 1;
288
289/*
290 fast_output_enable:
291 bit [0], output frame if there is IDR in list
292 bit [1], output frame if the current poc is 1 big than the previous poc
293 bit [2], if even poc only, output frame ifthe cuurent poc
294 is 2 big than the previous poc
295 bit [3], ip only
296*/
297static unsigned int fast_output_enable = H264_OUTPUT_MODE_NORMAL;
298
299static unsigned int enable_itu_t35 = 1;
300
301static unsigned int frmbase_cont_bitlevel = 0x40;
302
303static unsigned int frmbase_cont_bitlevel2 = 0x1;
304
305
306#define MH264_USERDATA_ENABLE
307
308/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
309/* hevc->double_write_mode:
310 0, no double write
311 1, 1:1 ratio
312 2, (1/4):(1/4) ratio
313 3, (1/4):(1/4) ratio, with both compressed frame included
314 4, (1/2):(1/2) ratio
315 0x10, double write only
316 0x10000: vdec dw horizotal 1/2
317 0x20000: vdec dw horizotal/vertical 1/2
318*/
319static u32 double_write_mode;
320static u32 without_display_mode;
321#define IS_VDEC_DW(hw) (hw->double_write_mode >> 16 & 0xf)
322
323static void vmh264_dump_state(struct vdec_s *vdec);
324
325#define is_in_parsing_state(status) \
326 ((status == H264_ACTION_SEARCH_HEAD) || \
327 ((status & 0xf0) == 0x80))
328
329#define is_interlace(frame) \
330 (frame->frame &&\
331 frame->top_field &&\
332 frame->bottom_field &&\
333 (!frame->frame->coded_frame))
334static inline bool close_to(int a, int b, int m)
335{
336 return (abs(a - b) < m) ? true : false;
337}
338
339#if 0
340#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt)
341#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw)
342#else
343#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size)
344#define h264_free_hw_stru(dev, hw) vfree(hw)
345#endif
346
347/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
348#define NV21
349/* #endif */
350
351/* 12M for L41 */
352#define MAX_DPB_BUFF_SIZE (12*1024*1024)
353#define DEFAULT_MEM_SIZE (32*1024*1024)
354#define AVIL_DPB_BUFF_SIZE 0x01ec2000
355
356#define DEF_BUF_START_ADDR 0x01000000
357#define mem_sps_base 0x011c3c00
358#define mem_pps_base 0x011cbc00
359/*#define V_BUF_ADDR_OFFSET (0x13e000)*/
360u32 V_BUF_ADDR_OFFSET = 0x200000;
361#define DCAC_READ_MARGIN (64 * 1024)
362
363
364#define EXTEND_SAR 0xff
365#define BUFSPEC_POOL_SIZE 64
366#define VF_POOL_SIZE 64
367#define VF_POOL_NUM 2
368#define MAX_VF_BUF_NUM 27
369#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3)
370#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE)
371#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1)
372#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2)
373#define EXTIF_BUF_SIZE (0x10000 * 2)
374
375#define HEADER_BUFFER_IDX(n) (n)
376#define VF_BUFFER_IDX(n) (n)
377
378
379#define PUT_INTERVAL (HZ/100)
380#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL)
381
382#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE
383#define SWITCHING_STATE_OFF 0
384#define SWITCHING_STATE_ON_CMD3 1
385#define SWITCHING_STATE_ON_CMD1 2
386
387
388
389#define INCPTR(p) ptr_atomic_wrap_inc(&p)
390
391#define SLICE_TYPE_I 2
392#define SLICE_TYPE_P 5
393#define SLICE_TYPE_B 6
394
395struct buffer_spec_s {
396 /*
397 used:
398 -1, none allocated
399 0, allocated, free
400 1, used by dpb
401 2, in disp queue;
402 3, in disp queue, isolated,
403 do not use for dpb when vf_put;
404 4, to release
405 5, in disp queue, isolated (but not to release)
406 do not use for dpb when vf_put;
407 */
408 unsigned int used;
409 unsigned int info0;
410 unsigned int info1;
411 unsigned int info2;
412 unsigned int y_addr;
413 unsigned int u_addr;
414 unsigned int v_addr;
415
416 int y_canvas_index;
417 int u_canvas_index;
418 int v_canvas_index;
419
420#ifdef VDEC_DW
421 unsigned int vdec_dw_y_addr;
422 unsigned int vdec_dw_u_addr;
423 unsigned int vdec_dw_v_addr;
424
425 int vdec_dw_y_canvas_index;
426 int vdec_dw_u_canvas_index;
427 int vdec_dw_v_canvas_index;
428#ifdef NV21
429 struct canvas_config_s vdec_dw_canvas_config[2];
430#else
431 struct canvas_config_s vdec_dw_canvas_config[3];
432#endif
433#endif
434
435#ifdef NV21
436 struct canvas_config_s canvas_config[2];
437#else
438 struct canvas_config_s canvas_config[3];
439#endif
440 unsigned long cma_alloc_addr;
441 unsigned int buf_adr;
442#ifdef H264_MMU
443 unsigned long alloc_header_addr;
444#endif
445 char *aux_data_buf;
446 int aux_data_size;
447#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
448 unsigned char dv_enhance_exist;
449#endif
450 int canvas_pos;
451 int vf_ref;
452 /*unsigned int comp_body_size;*/
453 unsigned int dw_y_adr;
454 unsigned int dw_u_v_adr;
455};
456
457#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size)
458#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf)
459#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist)
460
461
462#define vdec_dw_spec2canvas(x) \
463 (((x)->vdec_dw_v_canvas_index << 16) | \
464 ((x)->vdec_dw_u_canvas_index << 8) | \
465 ((x)->vdec_dw_y_canvas_index << 0))
466
467
468#define spec2canvas(x) \
469 (((x)->v_canvas_index << 16) | \
470 ((x)->u_canvas_index << 8) | \
471 ((x)->y_canvas_index << 0))
472
473#define FRAME_INDEX(vf_index) (vf_index & 0xff)
474#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff)
475#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8))
476
477static struct vframe_s *vh264_vf_peek(void *);
478static struct vframe_s *vh264_vf_get(void *);
479static void vh264_vf_put(struct vframe_s *, void *);
480static int vh264_vf_states(struct vframe_states *states, void *);
481static int vh264_event_cb(int type, void *data, void *private_data);
482static void vh264_work(struct work_struct *work);
483static void vh264_timeout_work(struct work_struct *work);
484static void vh264_notify_work(struct work_struct *work);
485#ifdef MH264_USERDATA_ENABLE
486static void user_data_ready_notify_work(struct work_struct *work);
487static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec);
488#endif
489
490static const char vh264_dec_id[] = "vh264-dev";
491
492#define PROVIDER_NAME "vdec.h264"
493
494static const struct vframe_operations_s vf_provider_ops = {
495 .peek = vh264_vf_peek,
496 .get = vh264_vf_get,
497 .put = vh264_vf_put,
498 .event_cb = vh264_event_cb,
499 .vf_states = vh264_vf_states,
500};
501
502#define DEC_RESULT_NONE 0
503#define DEC_RESULT_DONE 1
504#define DEC_RESULT_AGAIN 2
505#define DEC_RESULT_CONFIG_PARAM 3
506#define DEC_RESULT_GET_DATA 4
507#define DEC_RESULT_GET_DATA_RETRY 5
508#define DEC_RESULT_ERROR 6
509#define DEC_RESULT_EOS 7
510#define DEC_RESULT_FORCE_EXIT 8
511
512/*
513 *static const char *dec_result_str[] = {
514 * "DEC_RESULT_NONE ",
515 * "DEC_RESULT_DONE ",
516 * "DEC_RESULT_AGAIN ",
517 * "DEC_RESULT_CONFIG_PARAM",
518 * "DEC_RESULT_GET_DATA ",
519 * "DEC_RESULT_GET_DA_RETRY",
520 * "DEC_RESULT_ERROR ",
521 *};
522 */
523
524#define UCODE_IP_ONLY 2
525#define UCODE_IP_ONLY_PARAM 1
526
527#define MC_OFFSET_HEADER 0x0000
528#define MC_OFFSET_DATA 0x1000
529#define MC_OFFSET_MMCO 0x2000
530#define MC_OFFSET_LIST 0x3000
531#define MC_OFFSET_SLICE 0x4000
532#define MC_OFFSET_MAIN 0x5000
533
534#define MC_TOTAL_SIZE ((20+16)*SZ_1K)
535#define MC_SWAP_SIZE (4*SZ_1K)
536#define MODE_ERROR 0
537#define MODE_FULL 1
538
539#define DFS_HIGH_THEASHOLD 3
540
541#define INIT_FLAG_REG AV_SCRATCH_2
542#define HEAD_PADING_REG AV_SCRATCH_3
543#define UCODE_WATCHDOG_REG AV_SCRATCH_7
544#define LMEM_DUMP_ADR AV_SCRATCH_L
545#define DEBUG_REG1 AV_SCRATCH_M
546#define DEBUG_REG2 AV_SCRATCH_N
547#define FRAME_COUNTER_REG AV_SCRATCH_I
548#define RPM_CMD_REG AV_SCRATCH_A
549#define H264_DECODE_SIZE AV_SCRATCH_E
550#define H264_DECODE_MODE AV_SCRATCH_4
551#define H264_DECODE_SEQINFO AV_SCRATCH_5
552#define H264_AUX_ADR AV_SCRATCH_C
553#define H264_AUX_DATA_SIZE AV_SCRATCH_H
554
555#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */
556#define DPB_STATUS_REG AV_SCRATCH_J
557#define ERROR_STATUS_REG AV_SCRATCH_9
558 /*
559 NAL_SEARCH_CTL: bit 0, enable itu_t35
560 NAL_SEARCH_CTL: bit 1, enable mmu
561 */
562#define NAL_SEARCH_CTL AV_SCRATCH_9
563#define MBY_MBX MB_MOTION_MODE /*0xc07*/
564
565#define DECODE_MODE_SINGLE 0x0
566#define DECODE_MODE_MULTI_FRAMEBASE 0x1
567#define DECODE_MODE_MULTI_STREAMBASE 0x2
568#define DECODE_MODE_MULTI_DVBAL 0x3
569#define DECODE_MODE_MULTI_DVENL 0x4
570static DEFINE_MUTEX(vmh264_mutex);
571
572
573
574#ifdef MH264_USERDATA_ENABLE
575
576struct mh264_userdata_record_t {
577 struct userdata_meta_info_t meta_info;
578 u32 rec_start;
579 u32 rec_len;
580};
581
582struct mh264_ud_record_wait_node_t {
583 struct list_head list;
584 struct mh264_userdata_record_t ud_record;
585};
586#define USERDATA_FIFO_NUM 256
587#define MAX_FREE_USERDATA_NODES 5
588
589struct mh264_userdata_info_t {
590 struct mh264_userdata_record_t records[USERDATA_FIFO_NUM];
591 u8 *data_buf;
592 u8 *data_buf_end;
593 u32 buf_len;
594 u32 read_index;
595 u32 write_index;
596 u32 last_wp;
597};
598
599
600#endif
601
602struct vdec_h264_hw_s {
603 spinlock_t lock;
604 spinlock_t bufspec_lock;
605 int id;
606 struct platform_device *platform_dev;
607 unsigned long cma_alloc_addr;
608 /* struct page *collocate_cma_alloc_pages; */
609 unsigned long collocate_cma_alloc_addr;
610
611 u32 prefix_aux_size;
612 u32 suffix_aux_size;
613 void *aux_addr;
614 dma_addr_t aux_phy_addr;
615
616 /* buffer for store all sei data */
617 void *sei_data_buf;
618 u32 sei_data_len;
619
620 /* buffer for storing one itu35 recored */
621 void *sei_itu_data_buf;
622 u32 sei_itu_data_len;
623
624 /* recycle buffer for user data storing all itu35 records */
625 void *sei_user_data_buffer;
626 u32 sei_user_data_wp;
627#ifdef MH264_USERDATA_ENABLE
628 struct work_struct user_data_ready_work;
629#endif
630 struct StorablePicture *last_dec_picture;
631
632 ulong lmem_addr;
633 dma_addr_t lmem_addr_remap;
634
635 void *bmmu_box;
636#ifdef H264_MMU
637 void *mmu_box;
638 void *frame_mmu_map_addr;
639 dma_addr_t frame_mmu_map_phy_addr;
640 u32 hevc_cur_buf_idx;
641 u32 losless_comp_body_size;
642 u32 losless_comp_body_size_sao;
643 u32 losless_comp_header_size;
644 u32 mc_buffer_size_u_v;
645 u32 mc_buffer_size_u_v_h;
646 u32 is_idr_frame;
647 u32 is_new_pic;
648 u32 frame_done;
649 u32 frame_busy;
650 unsigned long extif_addr;
651 int double_write_mode;
652 int mmu_enable;
653#endif
654
655 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
656 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
657
658 int cur_pool;
659 struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE];
660 struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE];
661 struct vframe_s switching_fense_vf;
662 struct h264_dpb_stru dpb;
663 u8 init_flag;
664 u8 first_sc_checked;
665 u8 has_i_frame;
666 u8 config_bufmgr_done;
667 u32 max_reference_size;
668 u32 decode_pic_count;
669 u32 reflist_error_count;
670 int start_search_pos;
671 u32 reg_iqidct_control;
672 u32 reg_vcop_ctrl_reg;
673 u32 reg_rv_ai_mb_count;
674 u32 vld_dec_control;
675 struct vframe_s vframe_dummy;
676
677 unsigned char buffer_empty_flag;
678
679 u32 frame_width;
680 u32 frame_height;
681 u32 frame_dur;
682 u32 frame_prog;
683 u32 frame_packing_type;
684
685 struct vframe_chunk_s *chunk;
686
687 u32 stat;
688 unsigned long buf_start;
689 u32 buf_offset;
690 u32 buf_size;
691 /* u32 ucode_map_start; */
692 u32 pts_outside;
693 u32 sync_outside;
694 u32 vh264_ratio;
695 u32 vh264_rotation;
696 u32 use_idr_framerate;
697
698 u32 seq_info;
699 u32 seq_info2;
700 u32 video_signal_from_vui; /*to do .. */
701 u32 timing_info_present_flag;
702 u32 fixed_frame_rate_flag;
703 u32 bitstream_restriction_flag;
704 u32 num_reorder_frames;
705 u32 max_dec_frame_buffering;
706 u32 iframe_count;
707 u32 aspect_ratio_info;
708 u32 num_units_in_tick;
709 u32 time_scale;
710 u32 h264_ar;
711 bool h264_first_valid_pts_ready;
712 u32 h264pts1;
713 u32 h264pts2;
714 u32 pts_duration;
715 u32 h264_pts_count;
716 u32 duration_from_pts_done;
717 u32 pts_unstable;
718 u32 unstable_pts;
719 u32 last_checkout_pts;
720 u32 max_refer_buf;
721
722 s32 vh264_stream_switching_state;
723 struct vframe_s *p_last_vf;
724 u32 last_pts;
725 u32 last_pts_remainder;
726 u32 last_duration;
727 u32 last_mb_width, last_mb_height;
728 bool check_pts_discontinue;
729 bool pts_discontinue;
730 u32 wait_buffer_counter;
731 u32 first_offset;
732 u32 first_pts;
733 u64 first_pts64;
734 bool first_pts_cached;
735 u64 last_pts64;
736#if 0
737 void *sei_data_buffer;
738 dma_addr_t sei_data_buffer_phys;
739#endif
740
741 uint error_recovery_mode;
742 uint mb_total;
743 uint mb_width;
744 uint mb_height;
745
746 uint i_only;
747 int skip_frame_count;
748 bool no_poc_reorder_flag;
749 bool send_error_frame_flag;
750 dma_addr_t mc_dma_handle;
751 void *mc_cpu_addr;
752 int vh264_reset;
753
754 atomic_t vh264_active;
755
756 struct dec_sysinfo vh264_amstream_dec_info;
757
758 int dec_result;
759 struct work_struct work;
760 struct work_struct notify_work;
761 struct work_struct timeout_work;
762 void (*vdec_cb)(struct vdec_s *, void *);
763 void *vdec_cb_arg;
764
765 struct timer_list check_timer;
766
767 /**/
768 unsigned int last_frame_time;
769 u32 vf_pre_count;
770 u32 vf_get_count;
771 u32 vf_put_count;
772
773 /* timeout handle */
774 unsigned long int start_process_time;
775 unsigned int last_mby_mbx;
776 unsigned int last_vld_level;
777 unsigned int decode_timeout_count;
778 unsigned int timeout_num;
779 unsigned int search_dataempty_num;
780 unsigned int decode_timeout_num;
781 unsigned int decode_dataempty_num;
782 unsigned int buffer_empty_recover_num;
783
784 unsigned get_data_count;
785 unsigned get_data_start_time;
786 /**/
787
788 /*log*/
789 unsigned int packet_write_success_count;
790 unsigned int packet_write_EAGAIN_count;
791 unsigned int packet_write_ENOMEM_count;
792 unsigned int packet_write_EFAULT_count;
793 unsigned int total_read_size_pre;
794 unsigned int total_read_size;
795 unsigned int frame_count_pre;
796#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
797 u8 switch_dvlayer_flag;
798 u8 got_valid_nal;
799#endif
800 u8 eos;
801 u8 data_flag;
802 u32 no_error_count;
803 u32 no_error_i_count;
804 /*
805 NODISP_FLAG
806 */
807 u8 dec_flag;
808
809 u32 ucode_pause_pos;
810
811 u8 reset_bufmgr_flag;
812 u32 reset_bufmgr_count;
813 u32 cfg_param1;
814 u32 cfg_param2;
815 u32 cfg_param3;
816 u32 cfg_param4;
817 int valve_count;
818 u8 next_again_flag;
819 u32 pre_parser_wr_ptr;
820 struct firmware_s *fw;
821 struct firmware_s *fw_mmu;
822#ifdef MH264_USERDATA_ENABLE
823 /*user data*/
824 struct mutex userdata_mutex;
825 struct mh264_userdata_info_t userdata_info;
826 struct mh264_userdata_record_t ud_record;
827 int wait_for_udr_send;
828#endif
829 u32 no_mem_count;
830 u32 canvas_mode;
831 bool is_used_v4l;
832 void *v4l2_ctx;
833 bool v4l_params_parsed;
834 wait_queue_head_t wait_q;
835 u32 reg_g_status;
836 struct mutex chunks_mutex;
837 int need_cache_size;
838 u64 sc_start_time;
839 u8 frmbase_cont_flag;
840 struct vframe_qos_s vframe_qos;
841 int frameinfo_enable;
842 bool first_head_check_flag;
843 unsigned int height_aspect_ratio;
844 unsigned int width_aspect_ratio;
845 bool new_iframe_flag;
846 bool ref_err_flush_dpb_flag;
847 unsigned int first_i_policy;
848 u32 tfn_cnt;
849 u64 tfn_ns;
850};
851
852static u32 again_threshold;
853
854static void timeout_process(struct vdec_h264_hw_s *hw);
855static void dump_bufspec(struct vdec_h264_hw_s *hw,
856 const char *caller);
857static void h264_reconfig(struct vdec_h264_hw_s *hw);
858static void h264_reset_bufmgr(struct vdec_s *vdec);
859static void vh264_local_init(struct vdec_h264_hw_s *hw);
860static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw);
861static int vh264_stop(struct vdec_h264_hw_s *hw);
862static s32 vh264_init(struct vdec_h264_hw_s *hw);
863static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
864 u32 index);
865static void release_aux_data(struct vdec_h264_hw_s *hw,
866 int buf_spec_num);
867#ifdef ERROR_HANDLE_TEST
868static void h264_clear_dpb(struct vdec_h264_hw_s *hw);
869#endif
870
871#define H265_PUT_SAO_4K_SET 0x03
872#define H265_ABORT_SAO_4K_SET 0x04
873#define H265_ABORT_SAO_4K_SET_DONE 0x05
874
875#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0
876#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8
877#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9
878#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A
879#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
880
881
882#define HEVC_CM_HEADER_START_ADDR 0x3628
883#define HEVC_CM_BODY_START_ADDR 0x3626
884#define HEVC_CM_BODY_LENGTH 0x3627
885#define HEVC_CM_HEADER_LENGTH 0x3629
886#define HEVC_CM_HEADER_OFFSET 0x362b
887#define HEVC_SAO_CTRL9 0x362d
888#define HEVCD_MPP_DECOMP_CTL3 0x34c4
889#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8
890#define HEVC_DBLK_CFGB 0x350b
891#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
892
893#define H265_DW_NO_SCALE
894#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/
895#define H265_LOSLESS_COMPRESS_MODE
896#define MAX_FRAME_4K_NUM 0x1200
897#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
898
899/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
900static u32 mem_map_mode = H265_MEM_MAP_MODE;
901
902#define MAX_SIZE_8K (8192 * 4608)
903#define MAX_SIZE_4K (4096 * 2304)
904
905static int is_oversize(int w, int h)
906{
907 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
908 MAX_SIZE_8K : MAX_SIZE_4K;
909
910 if (w < 0 || h < 0)
911 return true;
912
913 if (h != 0 && (w > max / h))
914 return true;
915
916 return false;
917}
918
919static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
920 int frame_type,
921 u32 vpts,
922 u32 vpts_valid);
923static int compute_losless_comp_body_size(int width,
924 int height, int bit_depth_10);
925static int compute_losless_comp_header_size(int width, int height);
926
927static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx,
928 int pic_width, int pic_height, u16 bit_depth,
929 unsigned int *mmu_index_adr) {
930 int cur_buf_idx;
931 int bit_depth_10 = (bit_depth != 0x00);
932 int picture_size;
933 u32 cur_mmu_4k_number;
934
935 WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24);
936 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
937 picture_size = compute_losless_comp_body_size(pic_width,
938 pic_height, bit_depth_10);
939 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
940 dpb_print(DECODE_ID(hw),
941 PRINT_FLAG_MMU_DETAIL,
942 "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n",
943 cur_buf_idx, picture_size, cur_mmu_4k_number);
944
945 if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
946 pr_err("hevc_alloc_mmu cur_mmu_4k_number %d unsupport\n",
947 cur_mmu_4k_number);
948 return -1;
949 }
950
951 return decoder_mmu_box_alloc_idx(
952 hw->mmu_box,
953 cur_buf_idx,
954 cur_mmu_4k_number,
955 mmu_index_adr);
956
957}
958
959static int compute_losless_comp_body_size(int width,
960 int height, int bit_depth_10)
961{
962 int width_x64;
963 int height_x32;
964 int bsize;
965
966 width_x64 = width + 63;
967 width_x64 >>= 6;
968
969 height_x32 = height + 31;
970 height_x32 >>= 5;
971
972#ifdef H264_MMU
973 bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32;
974#else
975 bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32;
976#endif
977 return bsize;
978}
979
980static int compute_losless_comp_header_size(int width, int height)
981{
982 int width_x64;
983 int width_x128;
984 int height_x64;
985 int hsize;
986
987 width_x64 = width + 63;
988 width_x64 >>= 6;
989
990 width_x128 = width + 127;
991 width_x128 >>= 7;
992
993 height_x64 = height + 63;
994 height_x64 >>= 6;
995
996#ifdef H264_MMU
997 hsize = 128*width_x64*height_x64;
998#else
999 hsize = 32*width_x128*height_x64;
1000#endif
1001 return hsize;
1002}
1003
1004static int get_double_write_ratio(struct vdec_h264_hw_s *hw)
1005{
1006 int ratio = 1;
1007 int dw_mode = hw->double_write_mode;
1008 if ((dw_mode == 2) ||
1009 (dw_mode == 3))
1010 ratio = 4;
1011 else if (dw_mode == 4)
1012 ratio = 2;
1013 return ratio;
1014}
1015
1016
1017static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h)
1018{
1019 int pic_width, pic_height;
1020 int lcu_size = 16;
1021 int dw_buf_size;
1022 u32 dw_buffer_size_u_v;
1023 u32 dw_buffer_size_u_v_h;
1024 int dw_mode = hw->double_write_mode;
1025
1026 pic_width = hw->frame_width;
1027 pic_height = hw->frame_height;
1028
1029 if (dw_mode) {
1030 int pic_width_dw = pic_width /
1031 get_double_write_ratio(hw);
1032 int pic_height_dw = pic_height /
1033 get_double_write_ratio(hw);
1034
1035 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
1036 pic_width_dw / lcu_size + 1 :
1037 pic_width_dw / lcu_size;
1038 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
1039 pic_height_dw / lcu_size + 1 :
1040 pic_height_dw / lcu_size;
1041 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
1042
1043
1044 dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
1045 dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16;
1046 /*64k alignment*/
1047 dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3);
1048 *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h;
1049 } else {
1050 *pdw_buffer_size_u_v_h = 0;
1051 dw_buf_size = 0;
1052 }
1053
1054 return dw_buf_size;
1055}
1056
1057
1058static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore)
1059{
1060 int i, size;
1061 u32 canvas_addr;
1062 unsigned long maddr;
1063 int num_buff = hw->dpb.mDPB.size;
1064 int dw_size = 0;
1065 u32 dw_buffer_size_u_v_h;
1066 u32 blkmode = mem_map_mode;
1067 int dw_mode = hw->double_write_mode;
1068
1069 canvas_addr = ANC0_CANVAS_ADDR;
1070 for (i = 0; i < num_buff; i++)
1071 WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16));
1072
1073 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2));
1074 size = hw->losless_comp_body_size + hw->losless_comp_header_size;
1075
1076
1077 dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h);
1078 size += dw_size;
1079 if (size > 0)
1080 size += 0x10000;
1081
1082 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1083 "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n",
1084 dw_buffer_size_u_v_h, dw_size, size);
1085
1086 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1087 "body_size = %d, header_size = %d, body_size_sao = %d\n",
1088 hw->losless_comp_body_size,
1089 hw->losless_comp_header_size,
1090 hw->losless_comp_body_size_sao);
1091
1092 for (i = 0; i < num_buff; i++) {
1093 if (!restore) {
1094 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box,
1095 HEADER_BUFFER_IDX(i), size,
1096 DRIVER_HEADER_NAME, &maddr) < 0) {
1097 dpb_print(DECODE_ID(hw), 0,
1098 "%s malloc compress header failed %d\n",
1099 DRIVER_HEADER_NAME, i);
1100 return;
1101 }
1102 } else
1103 maddr = hw->buffer_spec[i].alloc_header_addr;
1104 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5);
1105 hw->buffer_spec[i].alloc_header_addr = maddr;
1106 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1107 "%s : canvas: %d axiaddr:%x size 0x%x\n",
1108 __func__, i, (u32)maddr, size);
1109
1110 if (dw_mode) {
1111 u32 addr;
1112 int canvas_w;
1113 int canvas_h;
1114
1115 canvas_w = hw->frame_width /
1116 get_double_write_ratio(hw);
1117 canvas_h = hw->frame_height /
1118 get_double_write_ratio(hw);
1119
1120 if (mem_map_mode == 0)
1121 canvas_w = ALIGN(canvas_w, 32);
1122 else
1123 canvas_w = ALIGN(canvas_w, 64);
1124 canvas_h = ALIGN(canvas_h, 32);
1125
1126 hw->buffer_spec[i].dw_y_adr =
1127 maddr + hw->losless_comp_header_size;
1128
1129 hw->buffer_spec[i].dw_y_adr =
1130 ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16)
1131 << 16;
1132 hw->buffer_spec[i].dw_u_v_adr =
1133 hw->buffer_spec[i].dw_y_adr
1134 + (dw_buffer_size_u_v_h << 16) * 2;
1135
1136
1137 hw->buffer_spec[i].buf_adr
1138 = hw->buffer_spec[i].dw_y_adr;
1139 addr = hw->buffer_spec[i].buf_adr;
1140
1141
1142 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
1143 "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n",
1144 hw->buffer_spec[i].dw_y_adr,
1145 hw->buffer_spec[i].dw_u_v_adr,
1146 hw->buffer_spec[i].y_addr,
1147 hw->buffer_spec[i].u_addr,
1148 hw->buffer_spec[i].v_addr,
1149 canvas_w,
1150 canvas_h);
1151
1152 hw->buffer_spec[i].canvas_config[0].phy_addr =
1153 hw->buffer_spec[i].dw_y_adr;
1154 hw->buffer_spec[i].canvas_config[0].width = canvas_w;
1155 hw->buffer_spec[i].canvas_config[0].height = canvas_h;
1156 hw->buffer_spec[i].canvas_config[0].block_mode =
1157 blkmode;
1158 hw->buffer_spec[i].canvas_config[0].endian = 7;
1159
1160 hw->buffer_spec[i].canvas_config[1].phy_addr =
1161 hw->buffer_spec[i].dw_u_v_adr;
1162 hw->buffer_spec[i].canvas_config[1].width = canvas_w;
1163 hw->buffer_spec[i].canvas_config[1].height = canvas_h;
1164 hw->buffer_spec[i].canvas_config[1].block_mode =
1165 blkmode;
1166 hw->buffer_spec[i].canvas_config[1].endian = 7;
1167 }
1168 }
1169 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1170
1171 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1);
1172 for (i = 0; i < 32; i++)
1173 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
1174 return;
1175}
1176static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw)
1177{
1178 u32 i;
1179 u32 ref_canv;
1180 struct Slice *pSlice = &(hw->dpb.mSlice);
1181 /*REFLIST[0]*/
1182 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
1183 struct StorablePicture *ref = pSlice->listX[0][i];
1184 if (ref == NULL)
1185 return;
1186 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1187 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1188 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1189 (ref->buf_spec_num & 0x3f) << 8);
1190 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1191 }
1192 /*REFLIST[1]*/
1193 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
1194 struct StorablePicture *ref = pSlice->listX[1][i];
1195 if (ref == NULL)
1196 return;
1197 WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24);
1198 ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1199 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1200 (ref->buf_spec_num & 0x3f) << 8);
1201 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv);
1202 }
1203 return;
1204}
1205
1206static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw)
1207{
1208 u32 rdata32;
1209 u32 rdata32_2;
1210 u32 slice_type;
1211 struct StorablePicture *ref;
1212 struct Slice *pSlice;
1213 slice_type = hw->dpb.mSlice.slice_type;
1214 pSlice = &(hw->dpb.mSlice);
1215 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);
1216 if (slice_type == I_SLICE) {
1217 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
1218 return;
1219 }
1220 if (slice_type == B_SLICE) {
1221 ref = pSlice->listX[0][0];
1222 if (ref == NULL)
1223 return;
1224 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1225 ((ref->buf_spec_num & 0x3f) << 8));
1226 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1227 rdata32 = rdata32 & 0xffff;
1228 rdata32 = rdata32 | (rdata32 << 16);
1229 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1230
1231 ref = pSlice->listX[1][0];
1232 if (ref == NULL)
1233 return;
1234 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1235 ((ref->buf_spec_num & 0x3f) << 8));
1236 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1237 rdata32_2 = rdata32_2 & 0xffff;
1238 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1239 if (rdata32 == rdata32_2) {
1240 ref = pSlice->listX[1][1];
1241 if (ref == NULL)
1242 return;
1243 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1244 ((ref->buf_spec_num & 0x3f) << 8));
1245 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1246 rdata32_2 = rdata32_2 & 0xffff;
1247 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
1248 }
1249 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
1250 } else { /*P-PIC*/
1251 ref = pSlice->listX[0][0];
1252 if (ref == NULL)
1253 return;
1254 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1255 ((ref->buf_spec_num & 0x3f) << 8));
1256 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1257 rdata32 = rdata32 & 0xffff;
1258 rdata32 = rdata32 | (rdata32 << 16);
1259 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
1260
1261 ref = pSlice->listX[0][1];
1262 if (ref == NULL)
1263 return;
1264 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
1265 ((ref->buf_spec_num & 0x3f) << 8));
1266 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
1267 rdata32 = rdata32 & 0xffff;
1268 rdata32 = rdata32 | (rdata32 << 16);
1269 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
1270 }
1271 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
1272 return;
1273}
1274
1275
1276static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
1277 u32 width, u32 height) {
1278 u32 data32;
1279 u32 lcu_x_num, lcu_y_num;
1280 u32 lcu_total;
1281 u32 mc_buffer_size_u_v;
1282 u32 mc_buffer_size_u_v_h;
1283 int dw_mode = hw->double_write_mode;
1284
1285 lcu_x_num = (width + 15) >> 4;
1286 lcu_y_num = (height + 15) >> 4;
1287 lcu_total = lcu_x_num * lcu_y_num;
1288
1289 hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2;
1290 hw->mc_buffer_size_u_v_h =
1291 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16;
1292
1293 hw->losless_comp_body_size = 0;
1294
1295 hw->losless_comp_body_size_sao =
1296 compute_losless_comp_body_size(width, height, 0);
1297 hw->losless_comp_header_size =
1298 compute_losless_comp_header_size(width, height);
1299
1300 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/
1301 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/
1302
1303 /* setup lcu_size = 16*/
1304 WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/
1305 /*pic_width/pic_height*/
1306 WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG,
1307 (height & 0xffff) << 16 | (width & 0xffff));
1308 /* bitdepth_luma = 8*/
1309 /* bitdepth_chroma = 8*/
1310 WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */
1311
1312#ifdef H265_LOSLESS_COMPRESS_MODE
1313 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
1314 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
1315#else
1316 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
1317#endif
1318 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
1319 data32 &= (~0x30);
1320 data32 |= (mem_map_mode << 4);
1321 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
1322
1323 WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
1324 (0x80 << 20) | (0x80 << 10) | (0xff));
1325
1326 WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4));
1327
1328 /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/
1329 WRITE_VREG(MDEC_PIC_DC_MUX_CTRL,
1330 READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31);
1331 /* ipp_enable*/
1332 WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
1333
1334 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
1335 WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
1336 WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
1337 if (dw_mode)
1338 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
1339 else
1340 WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
1341 }
1342
1343 data32 = READ_VREG(HEVC_SAO_CTRL0);
1344 data32 &= (~0xf);
1345 data32 |= 0x4;
1346 WRITE_VREG(HEVC_SAO_CTRL0, data32);
1347 WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 |
1348 (width & 0xffff));
1349 data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16);
1350
1351 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
1352 data32 = (lcu_x_num | lcu_y_num << 16);
1353 WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32);
1354 data32 = (mc_buffer_size_u_v_h << 16) << 1;
1355 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
1356 data32 = (mc_buffer_size_u_v_h << 16);
1357 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
1358
1359 data32 = READ_VREG(HEVC_SAO_CTRL1);
1360 data32 &= (~0x3000);
1361 data32 &= (~0xff0);
1362 data32 |= endian; /* Big-Endian per 64-bit */
1363
1364 if (hw->mmu_enable && dw_mode)
1365 data32 |= ((mem_map_mode << 12));
1366 else
1367 data32 |= ((mem_map_mode << 12)|2);
1368
1369 WRITE_VREG(HEVC_SAO_CTRL1, data32);
1370
1371#ifdef H265_DW_NO_SCALE
1372 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16));
1373 if (hw->mmu_enable && dw_mode) {
1374 data32 = READ_VREG(HEVC_SAO_CTRL5);
1375 data32 &= (~(0xff << 16));
1376 if (dw_mode == 2 ||
1377 dw_mode == 3)
1378 data32 |= (0xff<<16);
1379 else if (dw_mode == 4)
1380 data32 |= (0x33<<16);
1381 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1382 }
1383
1384
1385#endif
1386
1387
1388#ifdef H265_LOSLESS_COMPRESS_MODE
1389 data32 = READ_VREG(HEVC_SAO_CTRL5);
1390 data32 |= (1<<9); /*8-bit smem-mode*/
1391 WRITE_VREG(HEVC_SAO_CTRL5, data32);
1392
1393 WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao);
1394 WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size);
1395 WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size);
1396#endif
1397
1398#ifdef H265_LOSLESS_COMPRESS_MODE
1399 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1));
1400 WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10));
1401#endif
1402
1403 WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7);
1404
1405 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1406
1407 WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr);
1408 WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000);
1409 return;
1410}
1411
1412static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw,
1413 u32 is_new_pic, u32 is_idr)
1414{
1415 hw->is_new_pic = is_new_pic;
1416 hw->is_idr_frame = is_idr;
1417 return;
1418}
1419
1420static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
1421 struct StorablePicture *pic) {
1422 u32 mc_y_adr;
1423 u32 mc_u_v_adr;
1424 u32 dw_y_adr;
1425 u32 dw_u_v_adr;
1426 u32 canvas_addr;
1427 int ret;
1428 int dw_mode = hw->double_write_mode;
1429 if (hw->is_new_pic != 1)
1430 return;
1431
1432 if (hw->is_idr_frame) {
1433 /* William TBD */
1434 memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
1435 }
1436
1437 WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24);
1438 canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff;
1439 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1440 (0x0 << 2) | ((canvas_addr & 0xff) << 8));
1441 mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1442 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) |
1443 (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8));
1444 mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5;
1445 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
1446
1447
1448 if (dw_mode) {
1449 dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr;
1450 dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr;
1451 } else {
1452 dw_y_adr = 0;
1453 dw_u_v_adr = 0;
1454 }
1455#ifdef H265_LOSLESS_COMPRESS_MODE
1456 if (dw_mode)
1457 WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr);
1458 WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr);
1459#ifdef H264_MMU
1460 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr);
1461#else
1462 WRITE_VREG(HEVC_CM_HEADER_START_ADDR,
1463 (mc_y_adr + hw->losless_comp_body_size));
1464#endif
1465#else
1466 WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr);
1467#endif
1468
1469#ifndef H265_LOSLESS_COMPRESS_MODE
1470 WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr);
1471#else
1472 if (dw_mode)
1473 WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr);
1474#endif
1475
1476#ifndef LOSLESS_COMPRESS_MODE
1477 if (dw_mode) {
1478 WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr);
1479 WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr);
1480 }
1481#else
1482 WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr);
1483 WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr);
1484#endif
1485
1486 ret = hevc_alloc_mmu(hw, pic->buf_spec_num,
1487 (hw->mb_width << 4), (hw->mb_height << 4), 0x0,
1488 hw->frame_mmu_map_addr);
1489 if (ret != 0) {
1490 dpb_print(DECODE_ID(hw),
1491 PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n",
1492 pic->buf_spec_num,
1493 ret);
1494 return;
1495 }
1496
1497 /*Reset SAO + Enable SAO slice_start*/
1498 if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
1499 WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
1500 WRITE_VREG(HEVC_SAO_INT_STATUS,
1501 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
1502 WRITE_VREG(HEVC_SAO_INT_STATUS,
1503 READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31);
1504 /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
1505 /*Send coommand to hevc-code to supply 4k buffers to sao*/
1506
1507 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1508 WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
1509 WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
1510 } else
1511 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, (u32)hw->frame_mmu_map_phy_addr);
1512 WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET);
1513 hw->frame_busy = 1;
1514 return;
1515}
1516
1517
1518static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw,
1519 u32 buf_spec_num) {
1520 WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
1521 hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff;
1522 dpb_print(DECODE_ID(hw),
1523 PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n",
1524 __func__, hw->hevc_cur_buf_idx, buf_spec_num);
1525 return;
1526}
1527
1528
1529static void hevc_set_frame_done(struct vdec_h264_hw_s *hw)
1530{
1531 ulong timeout = jiffies + HZ;
1532 dpb_print(DECODE_ID(hw),
1533 PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n");
1534 while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) {
1535 if (time_after(jiffies, timeout)) {
1536 dpb_print(DECODE_ID(hw),
1537 PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__);
1538 break;
1539 }
1540 }
1541 timeout = jiffies + HZ;
1542 while (READ_VREG(HEVC_CM_CORE_STATUS) & 0x1) {
1543 if (time_after(jiffies, timeout)) {
1544 dpb_print(DECODE_ID(hw),
1545 PRINT_FLAG_MMU_DETAIL, " %s cm_core..timeout!\n", __func__);
1546 break;
1547 }
1548 }
1549 WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1);
1550 hw->frame_done = 1;
1551 return;
1552}
1553
1554static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw)
1555{
1556 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
1557 if (p_H264_Dpb->mVideo.dec_picture) {
1558 release_picture(p_H264_Dpb,
1559 p_H264_Dpb->mVideo.dec_picture);
1560 p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG;
1561 p_H264_Dpb->mVideo.dec_picture = NULL;
1562 if (hw->mmu_enable)
1563 hevc_set_frame_done(hw);
1564 }
1565}
1566
1567static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
1568{
1569 ulong timeout = jiffies + HZ;
1570 dpb_print(DECODE_ID(hw),
1571 PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n");
1572 while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) {
1573 if (time_after(jiffies, timeout)) {
1574 dpb_print(DECODE_ID(hw),
1575 PRINT_FLAG_MMU_DETAIL,
1576 "hevc_sao_wait_done...wait timeout!\n");
1577 break;
1578 }
1579 }
1580 timeout = jiffies + HZ;
1581 if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
1582 if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
1583 WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
1584 while ((READ_VREG(SYS_COMMAND) & 0xff) !=
1585 H265_ABORT_SAO_4K_SET_DONE) {
1586 if (time_after(jiffies, timeout)) {
1587 dpb_print(DECODE_ID(hw),
1588 PRINT_FLAG_MMU_DETAIL,
1589 "wait h265_abort_sao_4k_set_done timeout!\n");
1590 break;
1591 }
1592 }
1593 }
1594 amhevc_stop();
1595 hw->frame_busy = 0;
1596 hw->frame_done = 0;
1597 dpb_print(DECODE_ID(hw),
1598 PRINT_FLAG_MMU_DETAIL,
1599 "sao wait done ,hevc stop!\n");
1600 }
1601 return;
1602}
1603static void buf_spec_init(struct vdec_h264_hw_s *hw)
1604{
1605 int i;
1606 unsigned long flags;
1607 spin_lock_irqsave(&hw->bufspec_lock, flags);
1608 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
1609 hw->buffer_spec[i].used = -1;
1610 hw->buffer_spec[i].canvas_pos = -1;
1611 }
1612 if (dpb_is_debug(DECODE_ID(hw),
1613 PRINT_FLAG_DUMP_BUFSPEC))
1614 dump_bufspec(hw, __func__);
1615 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
1616}
1617
1618/*is active in buf management */
1619static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw,
1620 int buf_spec_num)
1621{
1622 unsigned char ret = 0;
1623 if (hw->buffer_spec[buf_spec_num].used == 1 ||
1624 hw->buffer_spec[buf_spec_num].used == 2 ||
1625 hw->buffer_spec[buf_spec_num].used == 3 ||
1626 hw->buffer_spec[buf_spec_num].used == 5)
1627 ret = 1;
1628 return ret;
1629}
1630
1631static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw,
1632 int buf_spec_num)
1633{
1634 unsigned char ret = 0;
1635 if (hw->buffer_spec[buf_spec_num].used == 2 ||
1636 hw->buffer_spec[buf_spec_num].used == 3 ||
1637 hw->buffer_spec[buf_spec_num].used == 5)
1638 ret = 1;
1639 return ret;
1640}
1641
1642static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i)
1643{
1644 if (hw->mmu_enable) {
1645 if (hw->buffer_spec[i].alloc_header_addr)
1646 return 0;
1647 else
1648 return -1;
1649 } else {
1650
1651 int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
1652 int addr;
1653#ifdef VDEC_DW
1654 int orig_buf_size;
1655 orig_buf_size = buf_size;
1656 if (IS_VDEC_DW(hw) == 1)
1657 buf_size += (hw->mb_total << 7) + (hw->mb_total << 6);
1658 else if (IS_VDEC_DW(hw) == 2)
1659 buf_size += (hw->mb_total << 6) + (hw->mb_total << 6);
1660#endif
1661 if (hw->buffer_spec[i].cma_alloc_addr)
1662 return 0;
1663
1664 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i,
1665 PAGE_ALIGN(buf_size), DRIVER_NAME,
1666 &hw->buffer_spec[i].cma_alloc_addr) < 0) {
1667 hw->buffer_spec[i].cma_alloc_addr = 0;
1668 if (hw->no_mem_count++ > 3) {
1669 hw->stat |= DECODER_FATAL_ERROR_NO_MEM;
1670 hw->reset_bufmgr_flag = 1;
1671 }
1672 dpb_print(DECODE_ID(hw), 0,
1673 "%s, fail to alloc buf for bufspec%d, try later\n",
1674 __func__, i
1675 );
1676 return -1;
1677 } else {
1678 hw->no_mem_count = 0;
1679 hw->stat &= ~DECODER_FATAL_ERROR_NO_MEM;
1680 }
1681
1682 hw->buffer_spec[i].buf_adr =
1683 hw->buffer_spec[i].cma_alloc_addr;
1684 addr = hw->buffer_spec[i].buf_adr;
1685
1686
1687 hw->buffer_spec[i].y_addr = addr;
1688 addr += hw->mb_total << 8;
1689 hw->buffer_spec[i].u_addr = addr;
1690 hw->buffer_spec[i].v_addr = addr;
1691 addr += hw->mb_total << 7;
1692
1693 hw->buffer_spec[i].canvas_config[0].phy_addr =
1694 hw->buffer_spec[i].y_addr;
1695 hw->buffer_spec[i].canvas_config[0].width =
1696 hw->mb_width << 4;
1697 hw->buffer_spec[i].canvas_config[0].height =
1698 hw->mb_height << 4;
1699 hw->buffer_spec[i].canvas_config[0].block_mode =
1700 hw->canvas_mode;
1701
1702 hw->buffer_spec[i].canvas_config[1].phy_addr =
1703 hw->buffer_spec[i].u_addr;
1704 hw->buffer_spec[i].canvas_config[1].width =
1705 hw->mb_width << 4;
1706 hw->buffer_spec[i].canvas_config[1].height =
1707 hw->mb_height << 3;
1708 hw->buffer_spec[i].canvas_config[1].block_mode =
1709 hw->canvas_mode;
1710 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1711 "%s, alloc buf for bufspec%d\n",
1712 __func__, i
1713 );
1714#ifdef VDEC_DW
1715
1716 if (!IS_VDEC_DW(hw))
1717 return 0;
1718 else if (IS_VDEC_DW(hw) == 1) {
1719 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1720 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1721 addr += hw->mb_total << 7;
1722 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1723 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1724 addr += hw->mb_total << 6;
1725
1726 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1727 hw->buffer_spec[i].vdec_dw_y_addr;
1728 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1729 hw->mb_width << 3;
1730 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1731 hw->mb_height << 4;
1732 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1733 CANVAS_BLKMODE_32X32;
1734
1735 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1736 hw->buffer_spec[i].vdec_dw_u_addr;
1737 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1738 hw->mb_width << 3;
1739 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1740 hw->mb_height << 3;
1741 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1742 CANVAS_BLKMODE_32X32;
1743 }else {
1744 addr = hw->buffer_spec[i].cma_alloc_addr + orig_buf_size;
1745 hw->buffer_spec[i].vdec_dw_y_addr = addr;
1746 addr += hw->mb_total << 6;
1747 hw->buffer_spec[i].vdec_dw_u_addr = addr;
1748 hw->buffer_spec[i].vdec_dw_v_addr = addr;
1749 addr += hw->mb_total << 5;
1750
1751 hw->buffer_spec[i].vdec_dw_canvas_config[0].phy_addr =
1752 hw->buffer_spec[i].vdec_dw_y_addr;
1753 hw->buffer_spec[i].vdec_dw_canvas_config[0].width =
1754 hw->mb_width << 3;
1755 hw->buffer_spec[i].vdec_dw_canvas_config[0].height =
1756 hw->mb_height << 3;
1757 hw->buffer_spec[i].vdec_dw_canvas_config[0].block_mode =
1758 CANVAS_BLKMODE_32X32;
1759
1760 hw->buffer_spec[i].vdec_dw_canvas_config[1].phy_addr =
1761 hw->buffer_spec[i].vdec_dw_u_addr;
1762 hw->buffer_spec[i].vdec_dw_canvas_config[1].width =
1763 hw->mb_width << 3;
1764 hw->buffer_spec[i].vdec_dw_canvas_config[1].height =
1765 hw->mb_height << 2;
1766 hw->buffer_spec[i].vdec_dw_canvas_config[1].block_mode =
1767 CANVAS_BLKMODE_32X32;
1768 }
1769 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
1770 "%s, vdec_dw: alloc buf for bufspec%d\n",
1771 __func__, i
1772 );
1773#endif
1774 }
1775 return 0;
1776}
1777
1778static int alloc_one_buf_spec_from_queue(struct vdec_h264_hw_s *hw, int idx)
1779{
1780 int ret = 0;
1781 struct aml_vcodec_ctx *ctx = NULL;
1782 struct buffer_spec_s *bs = &hw->buffer_spec[idx];
1783 struct canvas_config_s *y_canvas_cfg = NULL;
1784 struct canvas_config_s *c_canvas_cfg = NULL;
1785 struct vdec_v4l2_buffer *fb = NULL;
1786 unsigned int y_addr = 0, c_addr = 0;
1787
1788 if (IS_ERR_OR_NULL(hw->v4l2_ctx)) {
1789 pr_err("the v4l context has err.\n");
1790 return -1;
1791 }
1792
1793 if (bs->cma_alloc_addr)
1794 return 0;
1795
1796 ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1797 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1798 "[%d] %s(), try alloc from v4l queue buf size: %d\n",
1799 ctx->id, __func__,
1800 (hw->mb_total << 8) + (hw->mb_total << 7));
1801
1802 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
1803 if (ret) {
1804 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1805 "[%d] get fb fail.\n", ctx->id);
1806 return ret;
1807 }
1808
1809 bs->cma_alloc_addr = (unsigned long)fb;
1810 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1811 "[%d] %s(), cma alloc addr: 0x%x\n",
1812 ctx->id, __func__, bs->cma_alloc_addr);
1813
1814 if (fb->num_planes == 1) {
1815 y_addr = fb->m.mem[0].addr;
1816 c_addr = fb->m.mem[0].addr + fb->m.mem[0].offset;
1817 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1818 } else if (fb->num_planes == 2) {
1819 y_addr = fb->m.mem[0].addr;
1820 c_addr = fb->m.mem[1].addr;
1821 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
1822 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
1823 }
1824
1825 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1826 "[%d] %s(), y_addr: %x, size: %u\n",
1827 ctx->id, __func__, y_addr, fb->m.mem[0].size);
1828 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1829 "[%d] %s(), c_addr: %x, size: %u\n",
1830 ctx->id, __func__, c_addr, fb->m.mem[1].size);
1831
1832 bs->y_addr = y_addr;
1833 bs->u_addr = c_addr;
1834 bs->v_addr = c_addr;
1835
1836 y_canvas_cfg = &bs->canvas_config[0];
1837 c_canvas_cfg = &bs->canvas_config[1];
1838
1839 y_canvas_cfg->phy_addr = y_addr;
1840 y_canvas_cfg->width = hw->mb_width << 4;
1841 y_canvas_cfg->height = hw->mb_height << 4;
1842 y_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1843 //fb->m.mem[0].bytes_used = y_canvas_cfg->width * y_canvas_cfg->height;
1844 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1845 "[%d] %s(), y_w: %d, y_h: %d\n", ctx->id, __func__,
1846 y_canvas_cfg->width,y_canvas_cfg->height);
1847
1848 c_canvas_cfg->phy_addr = c_addr;
1849 c_canvas_cfg->width = hw->mb_width << 4;
1850 c_canvas_cfg->height = hw->mb_height << 3;
1851 c_canvas_cfg->block_mode = CANVAS_BLKMODE_LINEAR;
1852 //fb->m.mem[1].bytes_used = c_canvas_cfg->width * c_canvas_cfg->height;
1853 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1854 "[%d] %s(), c_w: %d, c_h: %d\n", ctx->id, __func__,
1855 c_canvas_cfg->width, c_canvas_cfg->height);
1856
1857 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
1858 "[%d] %s(), alloc buf for bufspec%d\n", ctx->id, __func__, idx);
1859
1860 return ret;
1861}
1862
1863static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i)
1864{
1865 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
1866 int blkmode = CANVAS_BLKMODE_32X32;
1867 int endian = 0;
1868
1869 if (hw->canvas_mode == CANVAS_BLKMODE_LINEAR) {
1870 blkmode = CANVAS_BLKMODE_LINEAR;
1871 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
1872 endian = 7;
1873 else
1874 endian = 0;
1875 }
1876
1877 if (hw->is_used_v4l) {
1878 blkmode = CANVAS_BLKMODE_LINEAR;
1879 if (v4l2_ctx->ada_ctx->vfm_path
1880 != FRAME_BASE_PATH_V4L_VIDEO)
1881 endian = 7;
1882 }
1883
1884 canvas_config_ex(hw->buffer_spec[i].
1885 y_canvas_index,
1886 hw->buffer_spec[i].y_addr,
1887 hw->mb_width << 4,
1888 hw->mb_height << 4,
1889 CANVAS_ADDR_NOWRAP,
1890 blkmode,
1891 endian);
1892
1893 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1894 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1895 (1 << 11) | /* canvas_blk32_wr */
1896 (blkmode << 10) | /* canvas_blk32*/
1897 (1 << 8) | /* canvas_index_wr*/
1898 (hw->buffer_spec[i].y_canvas_index << 0) /* canvas index*/
1899 );
1900 }
1901
1902 canvas_config_ex(hw->buffer_spec[i].
1903 u_canvas_index,
1904 hw->buffer_spec[i].u_addr,
1905 hw->mb_width << 4,
1906 hw->mb_height << 3,
1907 CANVAS_ADDR_NOWRAP,
1908 blkmode,
1909 endian);
1910
1911 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1912 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1913 (1 << 11) |
1914 (blkmode << 10) |
1915 (1 << 8) |
1916 (hw->buffer_spec[i].u_canvas_index << 0));
1917 }
1918
1919 WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos,
1920 spec2canvas(&hw->buffer_spec[i]));
1921
1922
1923#ifdef VDEC_DW
1924 if (!IS_VDEC_DW(hw))
1925 return;
1926 else if (IS_VDEC_DW(hw) == 1) {
1927 canvas_config_ex(hw->buffer_spec[i].
1928 vdec_dw_y_canvas_index,
1929 hw->buffer_spec[i].vdec_dw_y_addr,
1930 hw->mb_width << 3,
1931 hw->mb_height << 4,
1932 CANVAS_ADDR_NOWRAP,
1933 blkmode,
1934 endian);
1935 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1936 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1937 (1 << 11) |
1938 (blkmode << 10) |
1939 (1 << 8) |
1940 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1941 }
1942 canvas_config_ex(hw->buffer_spec[i].
1943 vdec_dw_u_canvas_index,
1944 hw->buffer_spec[i].vdec_dw_u_addr,
1945 hw->mb_width << 3,
1946 hw->mb_height << 3,
1947 CANVAS_ADDR_NOWRAP,
1948 blkmode,
1949 endian);
1950 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1951 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1952 (1 << 11) |
1953 (blkmode << 10) |
1954 (1 << 8) |
1955 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1956 }
1957 } else {
1958 canvas_config_ex(hw->buffer_spec[i].
1959 vdec_dw_y_canvas_index,
1960 hw->buffer_spec[i].vdec_dw_y_addr,
1961 hw->mb_width << 3,
1962 hw->mb_height << 3,
1963 CANVAS_ADDR_NOWRAP,
1964 blkmode,
1965 endian);
1966 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1967 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1968 (1 << 11) |
1969 (blkmode << 10) |
1970 (1 << 8) |
1971 (hw->buffer_spec[i].vdec_dw_y_canvas_index << 0));
1972 }
1973
1974 canvas_config_ex(hw->buffer_spec[i].
1975 vdec_dw_u_canvas_index,
1976 hw->buffer_spec[i].vdec_dw_u_addr,
1977 hw->mb_width << 3,
1978 hw->mb_height << 2,
1979 CANVAS_ADDR_NOWRAP,
1980 blkmode,
1981 endian);
1982 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
1983 WRITE_VREG(VDEC_ASSIST_CANVAS_BLK32,
1984 (1 << 11) |
1985 (blkmode << 10) |
1986 (1 << 8) |
1987 (hw->buffer_spec[i].vdec_dw_u_canvas_index << 0));
1988 }
1989 }
1990#endif
1991}
1992
1993static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i)
1994{
1995 u32 blkmode = mem_map_mode;
1996 int canvas_w;
1997 int canvas_h;
1998
1999 canvas_w = hw->frame_width /
2000 get_double_write_ratio(hw);
2001 canvas_h = hw->frame_height /
2002 get_double_write_ratio(hw);
2003
2004 if (mem_map_mode == 0)
2005 canvas_w = ALIGN(canvas_w, 32);
2006 else
2007 canvas_w = ALIGN(canvas_w, 64);
2008 canvas_h = ALIGN(canvas_h, 32);
2009
2010 canvas_config_ex(hw->buffer_spec[i].
2011 y_canvas_index,
2012 hw->buffer_spec[i].dw_y_adr,
2013 canvas_w,
2014 canvas_h,
2015 CANVAS_ADDR_NOWRAP,
2016 blkmode,
2017 7);
2018
2019 canvas_config_ex(hw->buffer_spec[i].
2020 u_canvas_index,
2021 hw->buffer_spec[i].dw_u_v_adr,
2022 canvas_w,
2023 canvas_h,
2024 CANVAS_ADDR_NOWRAP,
2025 blkmode,
2026 7);
2027}
2028
2029
2030int get_free_buf_idx(struct vdec_s *vdec)
2031{
2032 int i;
2033 unsigned long addr, flags;
2034 int index = -1;
2035 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2036 int buf_total = BUFSPEC_POOL_SIZE;
2037
2038 if (hw->is_used_v4l)
2039 buf_total = hw->dpb.mDPB.size;
2040
2041 spin_lock_irqsave(&hw->bufspec_lock, flags);
2042 /*hw->start_search_pos = 0;*/
2043 for (i = hw->start_search_pos; i < buf_total; i++) {
2044 if (hw->mmu_enable)
2045 addr = hw->buffer_spec[i].alloc_header_addr;
2046 else {
2047 addr = hw->buffer_spec[i].cma_alloc_addr;
2048 if (hw->is_used_v4l && !addr) {
2049 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2050 config_decode_canvas(hw, i);
2051 addr = hw->buffer_spec[i].cma_alloc_addr;
2052 }
2053 }
2054 }
2055 if (hw->buffer_spec[i].used == 0 && addr) {
2056 hw->buffer_spec[i].used = 1;
2057 hw->start_search_pos = i+1;
2058 index = i;
2059 break;
2060 }
2061 }
2062 if (index < 0) {
2063 for (i = 0; i < hw->start_search_pos; i++) {
2064 if (hw->mmu_enable)
2065 addr = hw->buffer_spec[i].alloc_header_addr;
2066 else {
2067 addr = hw->buffer_spec[i].cma_alloc_addr;
2068 if (hw->is_used_v4l && !addr) {
2069 if (!alloc_one_buf_spec_from_queue(hw, i)) {
2070 config_decode_canvas(hw, i);
2071 addr = hw->buffer_spec[i].cma_alloc_addr;
2072 }
2073 }
2074 }
2075 if (hw->buffer_spec[i].used == 0 && addr) {
2076 hw->buffer_spec[i].used = 1;
2077 hw->start_search_pos = i+1;
2078 index = i;
2079 break;
2080 }
2081 }
2082 }
2083 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2084 if (hw->start_search_pos >= buf_total)
2085 hw->start_search_pos = 0;
2086 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
2087 "%s, buf_spec_num %d\n", __func__, index);
2088
2089 if (index < 0) {
2090 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2091 "%s fail\n", __func__);
2092 vmh264_dump_state(vdec);
2093 }
2094
2095 if (dpb_is_debug(DECODE_ID(hw),
2096 PRINT_FLAG_DUMP_BUFSPEC))
2097 dump_bufspec(hw, __func__);
2098 return index;
2099}
2100
2101int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num)
2102{
2103 /*u32 cur_buf_idx;*/
2104 unsigned long flags;
2105 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2106 dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL,
2107 "%s buf_spec_num %d used %d\n",
2108 __func__, buf_spec_num,
2109 buf_spec_num > 0 ? hw->buffer_spec[buf_spec_num].used : 0);
2110 if (buf_spec_num >= 0 &&
2111 buf_spec_num < BUFSPEC_POOL_SIZE
2112 ) {
2113 spin_lock_irqsave(&hw->bufspec_lock, flags);
2114 hw->buffer_spec[buf_spec_num].used = 0;
2115 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2116 if (hw->mmu_enable) {
2117 /*WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24);
2118 cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL);
2119 cur_buf_idx = cur_buf_idx&0xff;*/
2120 decoder_mmu_box_free_idx(hw->mmu_box, buf_spec_num);
2121 }
2122 release_aux_data(hw, buf_spec_num);
2123 }
2124 if (dpb_is_debug(DECODE_ID(hw),
2125 PRINT_FLAG_DUMP_BUFSPEC))
2126 dump_bufspec(hw, __func__);
2127 return 0;
2128}
2129
2130static void config_buf_specs(struct vdec_s *vdec)
2131{
2132 int i, j;
2133 unsigned long flags;
2134 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2135 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2136
2137 spin_lock_irqsave(&hw->bufspec_lock, flags);
2138 for (i = 0, j = 0;
2139 j < hw->dpb.mDPB.size
2140 && i < BUFSPEC_POOL_SIZE;
2141 i++) {
2142 int canvas;
2143 if (hw->buffer_spec[i].used != -1)
2144 continue;
2145 if (vdec->parallel_dec == 1) {
2146 if (hw->buffer_spec[i].y_canvas_index == -1)
2147 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2148 if (hw->buffer_spec[i].u_canvas_index == -1) {
2149 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2150 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2151 }
2152#ifdef VDEC_DW
2153 if (IS_VDEC_DW(hw)) {
2154 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2155 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2156 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2157 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2158 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2159 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2160 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2161 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2162 }
2163 }
2164#endif
2165 } else {
2166 canvas = vdec->get_canvas(j * mode, 2);
2167 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2168 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2169 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2170 dpb_print(DECODE_ID(hw),
2171 PRINT_FLAG_DPB_DETAIL,
2172 "config canvas (%d) %x for bufspec %d\r\n",
2173 j, canvas, i);
2174#ifdef VDEC_DW
2175 if (IS_VDEC_DW(hw)) {
2176 canvas = vdec->get_canvas(j * mode + 1, 2);
2177 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2178 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2179 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2180 dpb_print(DECODE_ID(hw),
2181 PRINT_FLAG_DPB_DETAIL,
2182 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2183 j, canvas, i);
2184 }
2185#endif
2186 }
2187
2188 hw->buffer_spec[i].used = 0;
2189 hw->buffer_spec[i].canvas_pos = j;
2190
2191
2192 j++;
2193 }
2194 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2195}
2196
2197static void config_buf_specs_ex(struct vdec_s *vdec)
2198{
2199 int i, j;
2200 unsigned long flags;
2201 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2202 int mode = IS_VDEC_DW(hw) ? 2 : 1;
2203
2204 spin_lock_irqsave(&hw->bufspec_lock, flags);
2205 for (i = 0, j = 0;
2206 j < hw->dpb.mDPB.size
2207 && i < BUFSPEC_POOL_SIZE;
2208 i++) {
2209 int canvas = 0;
2210 if (hw->buffer_spec[i].used != -1)
2211 continue;
2212 if (vdec->parallel_dec == 1) {
2213 if (hw->buffer_spec[i].y_canvas_index == -1)
2214 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2215 if (hw->buffer_spec[i].u_canvas_index == -1) {
2216 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2217 hw->buffer_spec[i].v_canvas_index = hw->buffer_spec[i].u_canvas_index;
2218 }
2219#ifdef VDEC_DW
2220 if (IS_VDEC_DW(hw)) {
2221 if (hw->buffer_spec[i].vdec_dw_y_canvas_index == -1)
2222 hw->buffer_spec[i].vdec_dw_y_canvas_index =
2223 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2224 if (hw->buffer_spec[i].vdec_dw_u_canvas_index == -1) {
2225 hw->buffer_spec[i].vdec_dw_u_canvas_index =
2226 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
2227 hw->buffer_spec[i].vdec_dw_v_canvas_index =
2228 hw->buffer_spec[i].vdec_dw_u_canvas_index;
2229 }
2230 }
2231#endif
2232 } else {
2233 canvas = vdec->get_canvas(j* mode, 2);
2234 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
2235 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
2236 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
2237
2238 dpb_print(DECODE_ID(hw),
2239 PRINT_FLAG_DPB_DETAIL,
2240 "config canvas (%d) %x for bufspec %d\r\n",
2241 j, canvas, i);
2242#ifdef VDEC_DW
2243 if (IS_VDEC_DW(hw)) {
2244 canvas = vdec->get_canvas(j*mode + 1, 2);
2245 hw->buffer_spec[i].vdec_dw_y_canvas_index = canvas_y(canvas);
2246 hw->buffer_spec[i].vdec_dw_u_canvas_index = canvas_u(canvas);
2247 hw->buffer_spec[i].vdec_dw_v_canvas_index = canvas_v(canvas);
2248 dpb_print(DECODE_ID(hw),
2249 PRINT_FLAG_DPB_DETAIL,
2250 "vdec_dw: config canvas (%d) %x for bufspec %d\r\n",
2251 j, canvas, i);
2252 }
2253#endif
2254 }
2255
2256 hw->buffer_spec[i].used = 0;
2257 hw->buffer_spec[i].alloc_header_addr = 0;
2258 hw->buffer_spec[i].canvas_pos = j;
2259
2260 j++;
2261 }
2262 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
2263}
2264
2265
2266static void dealloc_buf_specs(struct vdec_h264_hw_s *hw,
2267 unsigned char release_all)
2268{
2269 int i;
2270 unsigned long flags;
2271 unsigned char dealloc_flag = 0;
2272 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2273 if (hw->buffer_spec[i].used == 4 ||
2274 release_all) {
2275 dealloc_flag = 1;
2276 dpb_print(DECODE_ID(hw),
2277 PRINT_FLAG_DPB_DETAIL,
2278 "%s buf_spec_num %d\n",
2279 __func__, i
2280 );
2281 spin_lock_irqsave
2282 (&hw->bufspec_lock, flags);
2283 hw->buffer_spec[i].used = -1;
2284 spin_unlock_irqrestore
2285 (&hw->bufspec_lock, flags);
2286 release_aux_data(hw, i);
2287
2288 if (!hw->mmu_enable) {
2289 if (hw->buffer_spec[i].cma_alloc_addr) {
2290 if (!hw->is_used_v4l) {
2291 decoder_bmmu_box_free_idx(
2292 hw->bmmu_box,
2293 i);
2294 }
2295 spin_lock_irqsave
2296 (&hw->bufspec_lock, flags);
2297 hw->buffer_spec[i].cma_alloc_addr = 0;
2298 hw->buffer_spec[i].buf_adr = 0;
2299 spin_unlock_irqrestore
2300 (&hw->bufspec_lock, flags);
2301 }
2302 } else {
2303 if (hw->buffer_spec[i].alloc_header_addr) {
2304 decoder_mmu_box_free_idx(
2305 hw->mmu_box,
2306 i);
2307 spin_lock_irqsave
2308 (&hw->bufspec_lock, flags);
2309 hw->buffer_spec[i].
2310 alloc_header_addr = 0;
2311 hw->buffer_spec[i].buf_adr = 0;
2312 spin_unlock_irqrestore
2313 (&hw->bufspec_lock, flags);
2314 }
2315 }
2316 }
2317 }
2318 if (dealloc_flag &&
2319 dpb_is_debug(DECODE_ID(hw),
2320 PRINT_FLAG_DUMP_BUFSPEC))
2321 dump_bufspec(hw, __func__);
2322 return;
2323}
2324
2325unsigned char have_free_buf_spec(struct vdec_s *vdec)
2326{
2327 int i;
2328 unsigned long addr;
2329 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2330 int canvas_pos_min = BUFSPEC_POOL_SIZE;
2331 int index = -1;
2332 int ret = 0;
2333 int allocated_count = 0;
2334 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2335 if (hw->mmu_enable)
2336 addr = hw->buffer_spec[i].alloc_header_addr;
2337 else
2338 addr = hw->buffer_spec[i].cma_alloc_addr;
2339 if (hw->buffer_spec[i].used == 0) {
2340
2341 if (addr)
2342 return 1;
2343 if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) {
2344 canvas_pos_min = hw->buffer_spec[i].canvas_pos;
2345 index = i;
2346 }
2347 }
2348 if (addr)
2349 allocated_count++;
2350 }
2351 if (index >= 0) {
2352 mutex_lock(&vmh264_mutex);
2353 dealloc_buf_specs(hw, 0);
2354 if (max_alloc_buf_count == 0 ||
2355 allocated_count < max_alloc_buf_count) {
2356 if (hw->is_used_v4l)
2357 ret = 1;
2358 else if (alloc_one_buf_spec(hw, index) >= 0)
2359 ret = 1;
2360 }
2361 mutex_unlock(&vmh264_mutex);
2362 }
2363 return ret;
2364}
2365
2366static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw,
2367 int canvas_pos)
2368{
2369 int i;
2370 int j = 0;
2371 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
2372 if (hw->buffer_spec[i].canvas_pos >= 0) {
2373 if (j == canvas_pos)
2374 return i;
2375 j++;
2376 }
2377 }
2378 return -1;
2379}
2380static void update_vf_memhandle(struct vdec_h264_hw_s *hw,
2381 struct vframe_s *vf, int index)
2382{
2383 if (index < 0) {
2384 vf->mem_handle = NULL;
2385 vf->mem_head_handle = NULL;
2386 } else if (vf->type & VIDTYPE_SCATTER) {
2387 vf->mem_handle =
2388 decoder_mmu_box_get_mem_handle(
2389 hw->mmu_box, index);
2390 vf->mem_head_handle =
2391 decoder_bmmu_box_get_mem_handle(
2392 hw->bmmu_box, HEADER_BUFFER_IDX(index));
2393 } else {
2394 vf->mem_handle =
2395 decoder_bmmu_box_get_mem_handle(
2396 hw->bmmu_box, VF_BUFFER_IDX(index));
2397 /* vf->mem_head_handle =
2398 decoder_bmmu_box_get_mem_handle(
2399 hw->bmmu_box, HEADER_BUFFER_IDX(index));*/
2400 }
2401 return;
2402}
2403static int check_force_interlace(struct vdec_h264_hw_s *hw,
2404 struct FrameStore *frame)
2405{
2406 int bForceInterlace = 0;
2407 /* no di in secure mode, disable force di */
2408 if (vdec_secure(hw_to_vdec(hw)))
2409 return 0;
2410 if (frame->frame) {
2411 if (frame->frame->coded_frame
2412 && !frame->frame->frame_mbs_only_flag) {
2413 if (frame->frame->structure == FRAME)
2414 return 1;
2415 }
2416 }
2417
2418 if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE)
2419 && hw->bitstream_restriction_flag
2420 && (hw->frame_width == 1920)
2421 && (hw->frame_height >= 1080)
2422 && (hw->frame_dur == 3203 || hw->frame_dur == 3840)) {
2423 bForceInterlace = 1;
2424 } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE)
2425 && (hw->frame_width == 720)
2426 && (hw->frame_height == 576)
2427 && (hw->frame_dur == 3840)) {
2428 bForceInterlace = 1;
2429 }
2430
2431 return bForceInterlace;
2432}
2433
2434static void fill_frame_info(struct vdec_h264_hw_s *hw, struct FrameStore *frame)
2435{
2436 struct vframe_qos_s *vframe_qos = &hw->vframe_qos;
2437 if (frame->slice_type == I_SLICE)
2438 vframe_qos->type = 1;
2439 else if (frame->slice_type == P_SLICE)
2440 vframe_qos->type = 2;
2441 else if (frame->slice_type == B_SLICE)
2442 vframe_qos->type = 3;
2443
2444 vframe_qos->size = frame->frame_size;
2445 vframe_qos->pts = frame->pts64;
2446
2447 vframe_qos->max_mv = frame->max_mv;
2448 vframe_qos->avg_mv = frame->avg_mv;
2449 vframe_qos->min_mv = frame->min_mv;
2450/*
2451 pr_info("mv: max:%d, avg:%d, min:%d\n",
2452 vframe_qos->max_mv,
2453 vframe_qos->avg_mv,
2454 vframe_qos->min_mv);
2455*/
2456
2457 vframe_qos->max_qp = frame->max_qp;
2458 vframe_qos->avg_qp = frame->avg_qp;
2459 vframe_qos->min_qp = frame->min_qp;
2460/*
2461 pr_info("qp: max:%d, avg:%d, min:%d\n",
2462 vframe_qos->max_qp,
2463 vframe_qos->avg_qp,
2464 vframe_qos->min_qp);
2465*/
2466
2467 vframe_qos->max_skip = frame->max_skip;
2468 vframe_qos->avg_skip = frame->avg_skip;
2469 vframe_qos->min_skip = frame->min_skip;
2470/*
2471 pr_info("skip: max:%d, avg:%d, min:%d\n",
2472 vframe_qos->max_skip,
2473 vframe_qos->avg_skip,
2474 vframe_qos->min_skip);
2475*/
2476 vframe_qos->num++;
2477 if (hw->frameinfo_enable)
2478 vdec_fill_frame_info(vframe_qos, 1);
2479}
2480
2481static int is_iframe(struct FrameStore *frame) {
2482
2483 if (frame->frame && frame->frame->slice_type == I_SLICE) {
2484 return 1;
2485 }
2486 return 0;
2487}
2488
2489
2490
2491int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame)
2492{
2493 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2494 struct vframe_s *vf = NULL;
2495 int buffer_index = frame->buf_spec_num;
2496 int vf_count = 1;
2497 int i;
2498 int bForceInterlace = 0;
2499
2500 if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) {
2501 dpb_print(DECODE_ID(hw), 0,
2502 "%s, buffer_index 0x%x is beyond range\n",
2503 __func__, buffer_index);
2504 return -1;
2505 }
2506 if (force_disp_bufspec_num & 0x100) {
2507 /*recycle directly*/
2508 if (hw->buffer_spec[frame->buf_spec_num].used != 3 &&
2509 hw->buffer_spec[frame->buf_spec_num].used != 5)
2510 set_frame_output_flag(&hw->dpb, frame->index);
2511
2512 /*make pre_output not set*/
2513 return -1;
2514 }
2515 if (error_proc_policy & 0x1000) {
2516 int error_skip_i_count = (error_skip_count >> 12) & 0xf;
2517 int error_skip_frame_count = error_skip_count & 0xfff;
2518 if (((hw->no_error_count < error_skip_frame_count)
2519 && (error_skip_i_count == 0 ||
2520 hw->no_error_i_count < error_skip_i_count))
2521 && (!(frame->data_flag & I_FLAG)))
2522 frame->data_flag |= ERROR_FLAG;
2523 }
2524 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2525 "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n",
2526 __func__, buffer_index, frame->data_flag & ERROR_FLAG,
2527 frame->poc, hw->data_flag & ERROR_FLAG,
2528 error_proc_policy);
2529 if (frame->frame == NULL &&
2530 ((frame->is_used == 1 && frame->top_field)
2531 || (frame->is_used == 2 && frame->bottom_field))) {
2532 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
2533 "%s Error frame_num %d used %d\n",
2534 __func__, frame->frame_num, frame->is_used);
2535 frame->data_flag |= ERROR_FLAG;
2536 }
2537 if (vdec_stream_based(vdec) && !(frame->data_flag & NODISP_FLAG)) {
2538 if ((pts_lookup_offset_us64(PTS_TYPE_VIDEO,
2539 frame->offset_delimiter, &frame->pts, &frame->frame_size,
2540 0, &frame->pts64) == 0)) {
2541 hw->last_pts64 = frame->pts64;
2542 hw->last_pts = frame->pts;
2543 } else {
2544 frame->pts64 = hw->last_pts64 +DUR2PTS(hw->frame_dur) ;
2545 frame->pts = hw->last_pts + DUR2PTS(hw->frame_dur);
2546 }
2547 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
2548 "%s error= 0x%x poc = %d offset= 0x%x pts= 0x%x last_pts =0x%x pts64 = %lld last_pts64= %lld duration = %d\n",
2549 __func__, (frame->data_flag & ERROR_FLAG), frame->poc,
2550 frame->offset_delimiter, frame->pts,hw->last_pts,
2551 frame->pts64, hw->last_pts64, hw->frame_dur);
2552 hw->last_pts64 = frame->pts64;
2553 hw->last_pts = frame->pts;
2554 }
2555 if ((frame->data_flag & NODISP_FLAG) ||
2556 (frame->data_flag & NULL_FLAG) ||
2557 ((!hw->send_error_frame_flag) &&
2558 (frame->data_flag & ERROR_FLAG)) ||
2559 ((hw->i_only & 0x1) &&
2560 (!(frame->data_flag & I_FLAG)))
2561 ) {
2562 set_frame_output_flag(&hw->dpb, frame->index);
2563 return 0; /*do not return -1,
2564 otherwise flush_dpb() will not flush all dbp frames*/
2565 }
2566
2567 display_frame_count[DECODE_ID(hw)]++;
2568
2569 if (dpb_is_debug(DECODE_ID(hw),
2570 PRINT_FLAG_DPB_DETAIL)) {
2571 dpb_print(DECODE_ID(hw), 0,
2572 "%s, fs[%d] poc %d, buf_spec_num %d\n",
2573 __func__, frame->index, frame->poc,
2574 frame->buf_spec_num);
2575 print_pic_info(DECODE_ID(hw), "predis_frm",
2576 frame->frame, -1);
2577 print_pic_info(DECODE_ID(hw), "predis_top",
2578 frame->top_field, -1);
2579 print_pic_info(DECODE_ID(hw), "predis_bot",
2580 frame->bottom_field, -1);
2581 }
2582
2583 if (!is_interlace(frame))
2584 vf_count = 1;
2585 else
2586 vf_count = 2;
2587 bForceInterlace = check_force_interlace(hw, frame);
2588 if (bForceInterlace)
2589 vf_count = 2;
2590 hw->buffer_spec[buffer_index].vf_ref = 0;
2591 fill_frame_info(hw, frame);
2592 for (i = 0; i < vf_count; i++) {
2593 if (kfifo_get(&hw->newframe_q, &vf) == 0 ||
2594 vf == NULL) {
2595 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2596 "%s fatal error, no available buffer slot.\n",
2597 __func__);
2598 return -1;
2599 }
2600 vf->duration_pulldown = 0;
2601 if (!(is_iframe(frame)) && hw->unstable_pts) {
2602 vf->pts = 0;
2603 vf->pts_us64 = 0;
2604 vf->timestamp = 0;
2605 vf->index = VF_INDEX(frame->index, buffer_index);
2606 } else {
2607 vf->pts = frame->pts;
2608 vf->pts_us64 = frame->pts64;
2609 vf->timestamp = frame->timestamp;
2610 vf->index = VF_INDEX(frame->index, buffer_index);
2611 }
2612
2613 if (hw->is_used_v4l) {
2614 vf->v4l_mem_handle
2615 = hw->buffer_spec[buffer_index].cma_alloc_addr;
2616 if (hw->mmu_enable) {
2617 if (vdec_v4l_binding_fd_and_vf(vf->v4l_mem_handle, vf) < 0) {
2618 dpb_print(DECODE_ID(hw),
2619 PRINT_FLAG_V4L_DETAIL,
2620 "v4l: binding vf fail.\n");
2621 return -1;
2622 }
2623 }
2624 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
2625 "[%d] %s(), v4l mem handle: 0x%x\n",
2626 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
2627 __func__, vf->v4l_mem_handle);
2628 }
2629
2630 if (hw->mmu_enable) {
2631 if (hw->double_write_mode & 0x10) {
2632 /* double write only */
2633 vf->compBodyAddr = 0;
2634 vf->compHeadAddr = 0;
2635 } else {
2636 /*head adr*/
2637 vf->compHeadAddr =
2638 hw->buffer_spec[buffer_index].alloc_header_addr;
2639 /*body adr*/
2640 vf->compBodyAddr = 0;
2641 vf->canvas0Addr = vf->canvas1Addr = 0;
2642 }
2643
2644 vf->type = VIDTYPE_SCATTER;
2645
2646 if (hw->double_write_mode) {
2647 vf->type |= VIDTYPE_PROGRESSIVE
2648 | VIDTYPE_VIU_FIELD;
2649 vf->type |= VIDTYPE_VIU_NV21;
2650 if (hw->double_write_mode == 3)
2651 vf->type |= VIDTYPE_COMPRESS;
2652
2653 vf->canvas0Addr = vf->canvas1Addr = -1;
2654 vf->plane_num = 2;
2655 vf->canvas0_config[0] =
2656 hw->buffer_spec[buffer_index].
2657 canvas_config[0];
2658 vf->canvas0_config[1] =
2659 hw->buffer_spec[buffer_index].
2660 canvas_config[1];
2661
2662 vf->canvas1_config[0] =
2663 hw->buffer_spec[buffer_index].
2664 canvas_config[0];
2665 vf->canvas1_config[1] =
2666 hw->buffer_spec[buffer_index].
2667 canvas_config[1];
2668
2669 } else {
2670 vf->type |=
2671 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
2672 vf->canvas0Addr = vf->canvas1Addr = 0;
2673 }
2674
2675 vf->bitdepth =
2676 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
2677
2678 vf->compWidth = hw->frame_width;
2679 vf->compHeight = hw->frame_height;
2680 } else {
2681 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
2682 VIDTYPE_VIU_NV21;
2683
2684 vf->canvas0Addr = vf->canvas1Addr =
2685 spec2canvas(&hw->buffer_spec[buffer_index]);
2686#ifdef VDEC_DW
2687 if (IS_VDEC_DW(hw))
2688 vf->canvas0Addr = vf->canvas1Addr =
2689 vdec_dw_spec2canvas(&hw->buffer_spec[buffer_index]);
2690#endif
2691
2692 }
2693 set_frame_info(hw, vf, buffer_index);
2694
2695 if (hw->mmu_enable && hw->double_write_mode) {
2696 vf->width = hw->frame_width /
2697 get_double_write_ratio(hw);
2698 vf->height = hw->frame_height /
2699 get_double_write_ratio(hw);
2700 }
2701
2702 vf->flag = 0;
2703 if (frame->data_flag & I_FLAG)
2704 vf->flag |= VFRAME_FLAG_SYNCFRAME;
2705 if (frame->data_flag & ERROR_FLAG)
2706 vf->flag |= VFRAME_FLAG_ERROR_RECOVERY;
2707 update_vf_memhandle(hw, vf, buffer_index);
2708 hw->buffer_spec[buffer_index].used = 2;
2709 hw->buffer_spec[buffer_index].vf_ref++;
2710
2711 if (bForceInterlace || is_interlace(frame)) {
2712 vf->type =
2713 VIDTYPE_INTERLACE_FIRST |
2714 VIDTYPE_VIU_NV21;
2715
2716 if (bForceInterlace) {
2717 vf->type |= (i == 0 ?
2718 VIDTYPE_INTERLACE_TOP :
2719 VIDTYPE_INTERLACE_BOTTOM);
2720 if (i == 1) {
2721 vf->pts = 0;
2722 vf->pts_us64 = 0;
2723 }
2724 } else if (frame->top_field->poc <=
2725 frame->bottom_field->poc) /*top first*/
2726 vf->type |= (i == 0 ?
2727 VIDTYPE_INTERLACE_TOP :
2728 VIDTYPE_INTERLACE_BOTTOM);
2729 else
2730 vf->type |= (i == 0 ?
2731 VIDTYPE_INTERLACE_BOTTOM :
2732 VIDTYPE_INTERLACE_TOP);
2733 vf->duration = vf->duration/2;
2734 }
2735
2736 if (i == 0)
2737 decoder_do_frame_check(hw_to_vdec(hw), vf);
2738
2739 /*vf->ratio_control |= (0x3FF << DISP_RATIO_ASPECT_RATIO_BIT);*/
2740 vf->sar_width = hw->width_aspect_ratio;
2741 vf->sar_height = hw->height_aspect_ratio;
2742
2743 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2744 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2745 hw->vf_pre_count++;
2746 vdec->vdec_fps_detec(vdec->id);
2747 if (without_display_mode == 0) {
2748 vf_notify_receiver(vdec->vf_provider_name,
2749 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2750 } else
2751 vh264_vf_put(vh264_vf_get(vdec), vdec);
2752 }
2753 if (dpb_is_debug(DECODE_ID(hw),
2754 PRINT_FLAG_DUMP_BUFSPEC))
2755 dump_bufspec(hw, __func__);
2756
2757 return 0;
2758}
2759
2760int notify_v4l_eos(struct vdec_s *vdec)
2761{
2762 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
2763 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
2764 struct vframe_s *vf = NULL;
2765 struct vdec_v4l2_buffer *fb = NULL;
2766
2767 if (hw->is_used_v4l && hw->eos) {
2768 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
2769 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
2770 "%s fatal error, no available buffer slot.\n",
2771 __func__);
2772 return -1;
2773 }
2774
2775 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
2776 pr_err("[%d] get fb fail.\n", ctx->id);
2777 return -1;
2778 }
2779
2780 vf->type |= VIDTYPE_V4L_EOS;
2781 vf->timestamp = ULONG_MAX;
2782 vf->v4l_mem_handle = (unsigned long)fb;
2783 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
2784
2785 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
2786
2787 ATRACE_COUNTER(MODULE_NAME, vf->pts);
2788 vf_notify_receiver(vdec->vf_provider_name,
2789 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
2790
2791 pr_info("[%d] H264 EOS notify.\n", ctx->id);
2792 }
2793
2794 return 0;
2795}
2796
2797/******************
2798 * Hardware config
2799 */
2800char *slice_type_name[] = {
2801 "P_SLICE ",
2802 "B_SLICE ",
2803 "I_SLICE ",
2804 "SP_SLICE",
2805 "SI_SLICE",
2806};
2807
2808char *picture_structure_name[] = {
2809 "FRAME",
2810 "TOP_FIELD",
2811 "BOTTOM_FIELD"
2812};
2813
2814void print_pic_info(int decindex, const char *info,
2815 struct StorablePicture *pic,
2816 int slice_type)
2817{
2818 if (pic)
2819 dpb_print(decindex, PRINT_FLAG_DEC_DETAIL,
2820 "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n",
2821 info,
2822 picture_structure_name[pic->structure],
2823 pic->coded_frame ? "Frame" : "Field",
2824 (slice_type < 0 ||
2825 slice_type >= (sizeof(slice_type_name) / sizeof(slice_type_name[0]))) ? "" : slice_type_name[slice_type],
2826 pic->mb_aff_frame_flag,
2827 pic->poc,
2828 pic->pic_num,
2829 pic->buf_spec_num,
2830 pic->data_flag);
2831}
2832
2833static void reset_process_time(struct vdec_h264_hw_s *hw)
2834{
2835 if (hw->start_process_time) {
2836 unsigned process_time =
2837 1000 * (jiffies - hw->start_process_time) / HZ;
2838 hw->start_process_time = 0;
2839 if (process_time > max_process_time[DECODE_ID(hw)])
2840 max_process_time[DECODE_ID(hw)] = process_time;
2841 }
2842}
2843
2844static void start_process_time(struct vdec_h264_hw_s *hw)
2845{
2846 hw->decode_timeout_count = 10;
2847 hw->start_process_time = jiffies;
2848}
2849
2850static void config_aux_buf(struct vdec_h264_hw_s *hw)
2851{
2852 WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr);
2853 WRITE_VREG(H264_AUX_DATA_SIZE,
2854 ((hw->prefix_aux_size >> 4) << 16) |
2855 (hw->suffix_aux_size >> 4)
2856 );
2857}
2858
2859/*
2860* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
2861*/
2862static void set_aux_data(struct vdec_h264_hw_s *hw,
2863 struct StorablePicture *pic, unsigned char suffix_flag,
2864 unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b)
2865{
2866 int i;
2867 unsigned short *aux_adr;
2868 unsigned size_reg_val =
2869 READ_VREG(H264_AUX_DATA_SIZE);
2870 unsigned aux_count = 0;
2871 int aux_size = 0;
2872 struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw;
2873 if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE
2874 || (!is_buf_spec_in_use(hw, pic->buf_spec_num)))
2875 return;
2876
2877 if (suffix_flag) {
2878 aux_adr = (unsigned short *)
2879 (hw_buf->aux_addr +
2880 hw_buf->prefix_aux_size);
2881 aux_count =
2882 ((size_reg_val & 0xffff) << 4)
2883 >> 1;
2884 aux_size =
2885 hw_buf->suffix_aux_size;
2886 } else {
2887 aux_adr =
2888 (unsigned short *)hw_buf->aux_addr;
2889 aux_count =
2890 ((size_reg_val >> 16) << 4)
2891 >> 1;
2892 aux_size =
2893 hw_buf->prefix_aux_size;
2894 }
2895 if (dpb_is_debug(DECODE_ID(hw),
2896 PRINT_FLAG_DPB_DETAIL)) {
2897 dpb_print(DECODE_ID(hw), 0,
2898 "%s:old size %d count %d,suf %d dv_flag %d\r\n",
2899 __func__, AUX_DATA_SIZE(pic),
2900 aux_count, suffix_flag, dv_meta_flag);
2901 }
2902 if (aux_size > 0 && aux_count > 0) {
2903 int heads_size = 0;
2904 int new_size;
2905 char *new_buf;
2906 for (i = 0; i < aux_count; i++) {
2907 unsigned char tag = aux_adr[i] >> 8;
2908 if (tag != 0 && tag != 0xff) {
2909 if (dv_meta_flag == 0)
2910 heads_size += 8;
2911 else if (dv_meta_flag == 1 && tag == 0x1)
2912 heads_size += 8;
2913 else if (dv_meta_flag == 2 && tag != 0x1)
2914 heads_size += 8;
2915 }
2916 }
2917 new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size;
2918 new_buf = krealloc(AUX_DATA_BUF(pic),
2919 new_size,
2920 GFP_KERNEL);
2921 if (new_buf) {
2922 unsigned char valid_tag = 0;
2923 unsigned char *h =
2924 new_buf +
2925 AUX_DATA_SIZE(pic);
2926 unsigned char *p = h + 8;
2927 int len = 0;
2928 int padding_len = 0;
2929 AUX_DATA_BUF(pic) = new_buf;
2930 for (i = 0; i < aux_count; i += 4) {
2931 int ii;
2932 unsigned char tag = aux_adr[i + 3] >> 8;
2933 if (tag != 0 && tag != 0xff) {
2934 if (dv_meta_flag == 0)
2935 valid_tag = 1;
2936 else if (dv_meta_flag == 1
2937 && tag == 0x1)
2938 valid_tag = 1;
2939 else if (dv_meta_flag == 2
2940 && tag != 0x1)
2941 valid_tag = 1;
2942 else
2943 valid_tag = 0;
2944 if (valid_tag && len > 0) {
2945 AUX_DATA_SIZE(pic) +=
2946 (len + 8);
2947 h[0] =
2948 (len >> 24) & 0xff;
2949 h[1] =
2950 (len >> 16) & 0xff;
2951 h[2] =
2952 (len >> 8) & 0xff;
2953 h[3] =
2954 (len >> 0) & 0xff;
2955 h[6] =
2956 (padding_len >> 8)
2957 & 0xff;
2958 h[7] =
2959 (padding_len) & 0xff;
2960 h += (len + 8);
2961 p += 8;
2962 len = 0;
2963 padding_len = 0;
2964 }
2965 if (valid_tag) {
2966 h[4] = tag;
2967 h[5] = 0;
2968 h[6] = 0;
2969 h[7] = 0;
2970 }
2971 }
2972 if (valid_tag) {
2973 for (ii = 0; ii < 4; ii++) {
2974 unsigned short aa =
2975 aux_adr[i + 3
2976 - ii];
2977 *p = aa & 0xff;
2978 p++;
2979 len++;
2980 /*if ((aa >> 8) == 0xff)
2981 padding_len++;*/
2982 }
2983 }
2984 }
2985 if (len > 0) {
2986 AUX_DATA_SIZE(pic) += (len + 8);
2987 h[0] = (len >> 24) & 0xff;
2988 h[1] = (len >> 16) & 0xff;
2989 h[2] = (len >> 8) & 0xff;
2990 h[3] = (len >> 0) & 0xff;
2991 h[6] = (padding_len >> 8) & 0xff;
2992 h[7] = (padding_len) & 0xff;
2993 }
2994 if (dpb_is_debug(DECODE_ID(hw),
2995 PRINT_FLAG_DPB_DETAIL)) {
2996 dpb_print(DECODE_ID(hw), 0,
2997 "aux: (size %d) suffix_flag %d\n",
2998 AUX_DATA_SIZE(pic), suffix_flag);
2999 for (i = 0; i < AUX_DATA_SIZE(pic); i++) {
3000 dpb_print_cont(DECODE_ID(hw), 0,
3001 "%02x ", AUX_DATA_BUF(pic)[i]);
3002 if (((i + 1) & 0xf) == 0)
3003 dpb_print_cont(
3004 DECODE_ID(hw),
3005 0, "\n");
3006 }
3007 dpb_print_cont(DECODE_ID(hw),
3008 0, "\n");
3009 }
3010
3011 }
3012 }
3013
3014}
3015
3016static void release_aux_data(struct vdec_h264_hw_s *hw,
3017 int buf_spec_num)
3018{
3019 kfree(hw->buffer_spec[buf_spec_num].aux_data_buf);
3020 hw->buffer_spec[buf_spec_num].aux_data_buf = NULL;
3021 hw->buffer_spec[buf_spec_num].aux_data_size = 0;
3022}
3023
3024static void dump_aux_buf(struct vdec_h264_hw_s *hw)
3025{
3026 int i;
3027 unsigned short *aux_adr =
3028 (unsigned short *)
3029 hw->aux_addr;
3030 unsigned aux_size =
3031 (READ_VREG(H264_AUX_DATA_SIZE)
3032 >> 16) << 4;
3033
3034 if (hw->prefix_aux_size > 0) {
3035 dpb_print(DECODE_ID(hw),
3036 0,
3037 "prefix aux: (size %d)\n",
3038 aux_size);
3039 for (i = 0; i <
3040 (aux_size >> 1); i++) {
3041 dpb_print_cont(DECODE_ID(hw),
3042 0,
3043 "%04x ",
3044 *(aux_adr + i));
3045 if (((i + 1) & 0xf)
3046 == 0)
3047 dpb_print_cont(
3048 DECODE_ID(hw),
3049 0, "\n");
3050 }
3051 }
3052 if (hw->suffix_aux_size > 0) {
3053 aux_adr = (unsigned short *)
3054 (hw->aux_addr +
3055 hw->prefix_aux_size);
3056 aux_size =
3057 (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff)
3058 << 4;
3059 dpb_print(DECODE_ID(hw),
3060 0,
3061 "suffix aux: (size %d)\n",
3062 aux_size);
3063 for (i = 0; i <
3064 (aux_size >> 1); i++) {
3065 dpb_print_cont(DECODE_ID(hw),
3066 0,
3067 "%04x ", *(aux_adr + i));
3068 if (((i + 1) & 0xf) == 0)
3069 dpb_print_cont(DECODE_ID(hw),
3070 0, "\n");
3071 }
3072 }
3073}
3074
3075static void config_decode_mode(struct vdec_h264_hw_s *hw)
3076{
3077#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3078 struct vdec_s *vdec = hw_to_vdec(hw);
3079#endif
3080 if (input_frame_based(hw_to_vdec(hw)))
3081 WRITE_VREG(H264_DECODE_MODE,
3082 DECODE_MODE_MULTI_FRAMEBASE);
3083#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3084 else if (vdec->slave)
3085 WRITE_VREG(H264_DECODE_MODE,
3086 (hw->got_valid_nal << 8) |
3087 DECODE_MODE_MULTI_DVBAL);
3088 else if (vdec->master)
3089 WRITE_VREG(H264_DECODE_MODE,
3090 (hw->got_valid_nal << 8) |
3091 DECODE_MODE_MULTI_DVENL);
3092#endif
3093 else
3094 WRITE_VREG(H264_DECODE_MODE,
3095 DECODE_MODE_MULTI_STREAMBASE);
3096 WRITE_VREG(H264_DECODE_SEQINFO,
3097 hw->seq_info2);
3098 WRITE_VREG(HEAD_PADING_REG, 0);
3099
3100 if (hw->init_flag == 0)
3101 WRITE_VREG(INIT_FLAG_REG, 0);
3102 else
3103 WRITE_VREG(INIT_FLAG_REG, 1);
3104}
3105int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic)
3106{
3107 /* static int count = 0; */
3108 int ret = 0;
3109 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3110 struct Slice *pSlice = &(p_H264_Dpb->mSlice);
3111 unsigned int colocate_adr_offset;
3112 unsigned int val;
3113 struct StorablePicture *last_pic = hw->last_dec_picture;
3114
3115#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
3116 int colocate_buf_index;
3117#endif
3118#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */
3119#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */
3120#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */
3121#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */
3122
3123#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */
3124/* bit 31:30 -- L1[0] picture coding structure,
3125 * 00 - top field, 01 - bottom field,
3126 * 10 - frame, 11 - mbaff frame
3127 * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot
3128 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3129 * -- only used for B Picture Direct mode [2:0] will set to 3'b000
3130 */
3131#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */
3132
3133/* bit 15 -- flush co_mb_data to DDR -- W-Only
3134 * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only
3135 * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only
3136 * bit 9 -- soft_reset -- W-Only
3137 * bit 8 -- upgent
3138 * bit 7:2 -- h264_co_mb_mem_wr_addr
3139 * bit 1:0 -- h264_co_mb_info_wr_ptr
3140 */
3141#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */
3142
3143 unsigned long canvas_adr;
3144 unsigned int ref_reg_val;
3145 unsigned int one_ref_cfg = 0;
3146 int h264_buffer_info_data_write_count;
3147 int i, j;
3148 unsigned int colocate_wr_adr;
3149 unsigned int colocate_rd_adr;
3150 unsigned char use_direct_8x8;
3151 int canvas_pos;
3152 canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3153 WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0);
3154 WRITE_VREG(H264_CURRENT_POC, pic->frame_poc);
3155 WRITE_VREG(H264_CURRENT_POC, pic->top_poc);
3156 WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc);
3157
3158 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3159 "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n",
3160 __func__, pic->pic_num, pic->poc, pic->frame_poc,
3161 pic->top_poc, pic->bottom_poc, pic->buf_spec_num,
3162 canvas_pos);
3163 print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type);
3164
3165#ifdef VDEC_DW
3166 if (IS_VDEC_DW(hw) && pic->mb_aff_frame_flag)
3167 WRITE_VREG(MDEC_DOUBLEW_CFG0,
3168 ( READ_VREG(MDEC_DOUBLEW_CFG0) & (~(1 << 30))));
3169#endif
3170 WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24);
3171 canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff;
3172
3173 if (!hw->mmu_enable) {
3174 WRITE_VREG(REC_CANVAS_ADDR, canvas_adr);
3175 WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr);
3176 WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr);
3177#ifdef VDEC_DW
3178 WRITE_VREG(MDEC_DOUBLEW_CFG1,
3179 (hw->buffer_spec[canvas_pos].vdec_dw_y_canvas_index
3180 | (hw->buffer_spec[canvas_pos].vdec_dw_u_canvas_index << 8)));
3181#endif
3182 } else
3183 hevc_sao_set_pic_buffer(hw, pic);
3184
3185 if (pic->mb_aff_frame_flag)
3186 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0;
3187 else if (pic->structure == TOP_FIELD)
3188 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400;
3189 else if (pic->structure == BOTTOM_FIELD)
3190 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440;
3191 else
3192 hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480;
3193
3194 if (pic->bottom_poc < pic->top_poc)
3195 hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100;
3196
3197 hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc;
3198 hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc;
3199 WRITE_VREG(H264_BUFFER_INFO_INDEX, 16);
3200
3201 for (j = 0; j < hw->dpb.mDPB.size; j++) {
3202 int long_term_flag;
3203 i = get_buf_spec_by_canvas_pos(hw, j);
3204 if (i < 0)
3205 break;
3206 long_term_flag =
3207 get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i);
3208 if (long_term_flag > 0) {
3209 if (long_term_flag & 0x1)
3210 hw->buffer_spec[i].info0 |= (1 << 4);
3211 else
3212 hw->buffer_spec[i].info0 &= ~(1 << 4);
3213
3214 if (long_term_flag & 0x2)
3215 hw->buffer_spec[i].info0 |= (1 << 5);
3216 else
3217 hw->buffer_spec[i].info0 &= ~(1 << 5);
3218 }
3219
3220 if (i == pic->buf_spec_num)
3221 WRITE_VREG(H264_BUFFER_INFO_DATA,
3222 hw->buffer_spec[i].info0 | 0xf);
3223 else
3224 WRITE_VREG(H264_BUFFER_INFO_DATA,
3225 hw->buffer_spec[i].info0);
3226 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1);
3227 WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2);
3228 }
3229
3230 /* config reference buffer */
3231 if (hw->mmu_enable) {
3232 hevc_mcr_config_mc_ref(hw);
3233 hevc_mcr_config_mcrcc(hw);
3234 }
3235
3236 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3237 "list0 size %d\n", pSlice->listXsize[0]);
3238 WRITE_VREG(H264_BUFFER_INFO_INDEX, 0);
3239 ref_reg_val = 0;
3240 j = 0;
3241 h264_buffer_info_data_write_count = 0;
3242
3243 //disable this read cache when frame width <= 64 (4MBs)
3244 //IQIDCT_CONTROL, bit[16] – dcac_dma_read_cache_disable
3245 if (hw->frame_width <= 64)
3246 SET_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3247 else
3248 CLEAR_VREG_MASK(IQIDCT_CONTROL,(1 << 16));
3249
3250 if (last_pic)
3251 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3252 "last_pic->data_flag %x slice_type %x last_pic->slice_type %x\n",
3253 last_pic->data_flag, pSlice->slice_type, last_pic->slice_type);
3254 if (!hw->i_only && !(error_proc_policy & 0x2000) &&
3255 last_pic && (last_pic->data_flag & ERROR_FLAG)
3256 && (!(last_pic->slice_type == B_SLICE))
3257 && (!(pSlice->slice_type == I_SLICE))) {
3258 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
3259 "no i/idr error mark\n");
3260 hw->data_flag |= ERROR_FLAG;
3261 pic->data_flag |= ERROR_FLAG;
3262 }
3263
3264 for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) {
3265 /*ref list 0 */
3266 struct StorablePicture *ref = pSlice->listX[0][i];
3267 unsigned int cfg;
3268 /* bit[6:5] - frame/field info,
3269 * 01 - top, 10 - bottom, 11 - frame
3270 */
3271 #ifdef ERROR_CHECK
3272 if (ref == NULL) {
3273 hw->data_flag |= ERROR_FLAG;
3274 pic->data_flag |= ERROR_FLAG;
3275 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n");
3276 return -1;
3277 }
3278 if ((ref->data_flag & ERROR_FLAG) && ref_frame_mark_flag[DECODE_ID(hw)]) {
3279 hw->data_flag |= ERROR_FLAG;
3280 pic->data_flag |= ERROR_FLAG;
3281 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n");
3282 }
3283 if (ref->data_flag & NULL_FLAG)
3284 hw->data_flag |= NULL_FLAG;
3285#endif
3286 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3287
3288 if (ref->structure == TOP_FIELD)
3289 cfg = 0x1;
3290 else if (ref->structure == BOTTOM_FIELD)
3291 cfg = 0x2;
3292 else /* FRAME */
3293 cfg = 0x3;
3294
3295 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3296 ref_reg_val <<= 8;
3297 ref_reg_val |= one_ref_cfg;
3298 j++;
3299
3300 if (j == 4) {
3301 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3302 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3303 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3304 h264_buffer_info_data_write_count++;
3305 j = 0;
3306 }
3307 print_pic_info(DECODE_ID(hw), "list0",
3308 pSlice->listX[0][i], -1);
3309 }
3310 if (j != 0) {
3311 while (j != 4) {
3312 ref_reg_val <<= 8;
3313 ref_reg_val |= one_ref_cfg;
3314 j++;
3315 }
3316 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3317 "H264_BUFFER_INFO_DATA: %x\n",
3318 ref_reg_val);
3319 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3320 h264_buffer_info_data_write_count++;
3321 }
3322 ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) |
3323 (one_ref_cfg << 8) | one_ref_cfg;
3324 for (i = h264_buffer_info_data_write_count; i < 8; i++)
3325 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3326
3327 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3328 "list1 size %d\n", pSlice->listXsize[1]);
3329 WRITE_VREG(H264_BUFFER_INFO_INDEX, 8);
3330 ref_reg_val = 0;
3331 j = 0;
3332
3333 for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) {
3334 /* ref list 0 */
3335 struct StorablePicture *ref = pSlice->listX[1][i];
3336 unsigned int cfg;
3337 /* bit[6:5] - frame/field info,
3338 * 01 - top, 10 - bottom, 11 - frame
3339 */
3340
3341 #ifdef ERROR_CHECK
3342 if (ref == NULL) {
3343 hw->data_flag |= ERROR_FLAG;
3344 pic->data_flag |= ERROR_FLAG;
3345 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n");
3346 return -2;
3347 }
3348 if ((ref->data_flag & ERROR_FLAG) && (ref_frame_mark_flag[DECODE_ID(hw)])) {
3349 pic->data_flag |= ERROR_FLAG;
3350 hw->data_flag |= ERROR_FLAG;
3351 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n");
3352 }
3353 if (ref->data_flag & NULL_FLAG)
3354 hw->data_flag |= NULL_FLAG;
3355#endif
3356 canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos;
3357 if (ref->structure == TOP_FIELD)
3358 cfg = 0x1;
3359 else if (ref->structure == BOTTOM_FIELD)
3360 cfg = 0x2;
3361 else /* FRAME */
3362 cfg = 0x3;
3363 one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5);
3364 ref_reg_val <<= 8;
3365 ref_reg_val |= one_ref_cfg;
3366 j++;
3367
3368 if (j == 4) {
3369 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3370 "H264_BUFFER_INFO_DATA: %x\n",
3371 ref_reg_val);
3372 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3373 j = 0;
3374 }
3375 print_pic_info(DECODE_ID(hw), "list1",
3376 pSlice->listX[1][i], -1);
3377 }
3378 if (j != 0) {
3379 while (j != 4) {
3380 ref_reg_val <<= 8;
3381 ref_reg_val |= one_ref_cfg;
3382 j++;
3383 }
3384 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3385 "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val);
3386 WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val);
3387 }
3388
3389 /* configure co-locate buffer */
3390 while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1)
3391 ;
3392 if ((pSlice->mode_8x8_flags & 0x4) &&
3393 (pSlice->mode_8x8_flags & 0x2))
3394 use_direct_8x8 = 1;
3395 else
3396 use_direct_8x8 = 0;
3397
3398#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3399 colocate_adr_offset =
3400 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0)
3401 ? 1 : 2) * 96;
3402 if (use_direct_8x8)
3403 colocate_adr_offset >>= 2;
3404
3405 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3406 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3407 colocate_adr_offset, pSlice->first_mb_in_slice,
3408 colocate_adr_offset * pSlice->first_mb_in_slice);
3409
3410 colocate_adr_offset *= pSlice->first_mb_in_slice;
3411
3412 if ((pic->colocated_buf_index >= 0) &&
3413 (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) {
3414 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3415 ((p_H264_Dpb->colocated_buf_size *
3416 pic->colocated_buf_index)
3417 >> (use_direct_8x8 ? 2 : 0));
3418 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3419 p_H264_Dpb->colocated_mv_addr_end) {
3420 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3421 "Error, colocate buf is not enough, index is %d\n",
3422 pic->colocated_buf_index);
3423 ret = -3;
3424 }
3425 val = colocate_wr_adr + colocate_adr_offset;
3426 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3427 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3428 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3429 val, pSlice->first_mb_in_slice, pic->structure,
3430 colocate_adr_offset, pSlice->mode_8x8_flags,
3431 p_H264_Dpb->colocated_buf_size);
3432 } else {
3433 WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff);
3434 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3435 "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n");
3436 }
3437#else
3438 colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos;
3439 colocate_adr_offset =
3440 ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96;
3441 if (use_direct_8x8)
3442 colocate_adr_offset >>= 2;
3443
3444 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3445 "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n",
3446 colocate_adr_offset, pSlice->first_mb_in_slice,
3447 colocate_adr_offset * pSlice->first_mb_in_slice);
3448
3449 colocate_adr_offset *= pSlice->first_mb_in_slice;
3450
3451 colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start +
3452 ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >>
3453 (use_direct_8x8 ? 2 : 0));
3454
3455 if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) >
3456 p_H264_Dpb->colocated_mv_addr_end) {
3457 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3458 "Error, colocate buf is not enough, col buf index is %d\n",
3459 colocate_buf_index);
3460 ret = -4;
3461 }
3462 val = colocate_wr_adr + colocate_adr_offset;
3463 WRITE_VREG(H264_CO_MB_WR_ADDR, val);
3464 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3465 "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n",
3466 val, pSlice->first_mb_in_slice, pic->structure,
3467 colocate_adr_offset, pSlice->mode_8x8_flags,
3468 p_H264_Dpb->colocated_buf_size);
3469#endif
3470 if (pSlice->listXsize[1] > 0) {
3471 struct StorablePicture *colocate_pic = pSlice->listX[1][0];
3472 /* H264_CO_MB_RD_ADDR[bit 31:30],
3473 * original picture structure of L1[0],
3474 * 00 - top field, 01 - bottom field,
3475 * 10 - frame, 11 - mbaff frame
3476 */
3477 int l10_structure;
3478 int cur_colocate_ref_type;
3479 /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture,
3480 * 0 - top, 1 - bot
3481 */
3482 unsigned int val;
3483#ifdef ERROR_CHECK
3484 if (colocate_pic == NULL) {
3485 hw->data_flag |= ERROR_FLAG;
3486 pic->data_flag |= ERROR_FLAG;
3487 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n");
3488 return -5;
3489 }
3490 if (colocate_pic->data_flag & ERROR_FLAG) {
3491 pic->data_flag |= ERROR_FLAG;
3492 hw->data_flag |= ERROR_FLAG;
3493 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n");
3494 }
3495 if (colocate_pic->data_flag & NULL_FLAG)
3496 hw->data_flag |= NULL_FLAG;
3497#endif
3498
3499 if (colocate_pic->mb_aff_frame_flag)
3500 l10_structure = 3;
3501 else {
3502 if (colocate_pic->coded_frame)
3503 l10_structure = 2;
3504 else
3505 l10_structure = (colocate_pic->structure ==
3506 BOTTOM_FIELD) ? 1 : 0;
3507 }
3508#if 0
3509 /*case0016, p16,
3510 *cur_colocate_ref_type should be configured base on current pic
3511 */
3512 if (pic->structure == FRAME &&
3513 pic->mb_aff_frame_flag)
3514 cur_colocate_ref_type = 0;
3515 else if (pic->structure == BOTTOM_FIELD)
3516 cur_colocate_ref_type = 1;
3517 else
3518 cur_colocate_ref_type = 0;
3519#else
3520 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3521 " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3522 pic->mb_aff_frame_flag,
3523 pic->structure,
3524 pic->coded_frame);
3525 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3526 " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n",
3527 colocate_pic->mb_aff_frame_flag,
3528 colocate_pic->structure,
3529 colocate_pic->coded_frame);
3530 if (pic->structure == FRAME || pic->mb_aff_frame_flag) {
3531 cur_colocate_ref_type =
3532 (abs(pic->poc - colocate_pic->top_poc)
3533 < abs(pic->poc -
3534 colocate_pic->bottom_poc)) ? 0 : 1;
3535 } else
3536 cur_colocate_ref_type =
3537 (colocate_pic->structure
3538 == BOTTOM_FIELD) ? 1 : 0;
3539#endif
3540
3541#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF
3542 if ((colocate_pic->colocated_buf_index >= 0) &&
3543 (colocate_pic->colocated_buf_index <
3544 p_H264_Dpb->colocated_buf_count)) {
3545 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3546 ((p_H264_Dpb->colocated_buf_size *
3547 colocate_pic->colocated_buf_index)
3548 >> (use_direct_8x8 ? 2 : 0));
3549 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3550 p_H264_Dpb->colocated_mv_addr_end) {
3551 dpb_print(DECODE_ID(hw),
3552 PRINT_FLAG_ERROR,
3553 "Error, colocate buf is not enough, index is %d\n",
3554 colocate_pic->colocated_buf_index);
3555 ret = -6;
3556 }
3557 /* bit 31:30 -- L1[0] picture coding structure,
3558 * 00 - top field, 01 - bottom field,
3559 * 10 - frame, 11 - mbaff frame
3560 * bit 29 - L1[0] top/bot for B field pciture,
3561 * 0 - top, 1 - bot
3562 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3563 * -- only used for B Picture Direct mode
3564 * [2:0] will set to 3'b000
3565 */
3566 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3567 val = ((colocate_rd_adr+colocate_adr_offset) >> 3) |
3568 (l10_structure << 30) |
3569 (cur_colocate_ref_type << 29);
3570 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3571 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3572 "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n",
3573 colocate_pic->colocated_buf_index,
3574 val, colocate_rd_adr + colocate_adr_offset,
3575 colocate_pic->structure,
3576 colocate_pic->mb_aff_frame_flag);
3577 } else {
3578 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3579 "Error, reference pic has no colocated buf\n");
3580 ret = -7;
3581 }
3582#else
3583 colocate_buf_index =
3584 hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos;
3585 colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start +
3586 ((p_H264_Dpb->colocated_buf_size *
3587 colocate_buf_index)
3588 >> (use_direct_8x8 ? 2 : 0));
3589 if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) >
3590 p_H264_Dpb->colocated_mv_addr_end) {
3591 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
3592 "Error, colocate buf is not enough, col buf index is %d\n",
3593 colocate_buf_index);
3594 ret = -8;
3595 }
3596 /* bit 31:30 -- L1[0] picture coding structure,
3597 * 00 - top field, 01 - bottom field,
3598 * 10 - frame, 11 - mbaff frame
3599 * bit 29 - L1[0] top/bot for B field pciture,
3600 * 0 - top, 1 - bot
3601 * bit 28:0 h264_co_mb_mem_rd_addr[31:3]
3602 * -- only used for B Picture Direct mode
3603 * [2:0] will set to 3'b000
3604 */
3605 /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */
3606 val = ((colocate_rd_adr+colocate_adr_offset)>>3) |
3607 (l10_structure << 30) | (cur_colocate_ref_type << 29);
3608 WRITE_VREG(H264_CO_MB_RD_ADDR, val);
3609 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
3610 "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n",
3611 val, colocate_pic->structure,
3612 colocate_pic->mb_aff_frame_flag);
3613#endif
3614 }
3615 return ret;
3616}
3617
3618static int vh264_vf_states(struct vframe_states *states, void *op_arg)
3619{
3620 unsigned long flags;
3621 struct vdec_s *vdec = op_arg;
3622 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3623
3624 spin_lock_irqsave(&hw->lock, flags);
3625
3626 states->vf_pool_size = VF_POOL_SIZE;
3627 states->buf_free_num = kfifo_len(&hw->newframe_q);
3628 states->buf_avail_num = kfifo_len(&hw->display_q);
3629
3630 spin_unlock_irqrestore(&hw->lock, flags);
3631
3632 return 0;
3633}
3634
3635static struct vframe_s *vh264_vf_peek(void *op_arg)
3636{
3637 struct vframe_s *vf[2] = {0, 0};
3638 struct vdec_s *vdec = op_arg;
3639 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3640
3641 if (!hw)
3642 return NULL;
3643
3644 if (force_disp_bufspec_num & 0x100) {
3645 if (force_disp_bufspec_num & 0x200)
3646 return NULL;
3647 return &hw->vframe_dummy;
3648 }
3649
3650 if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) {
3651 if (vf[1]) {
3652 vf[0]->next_vf_pts_valid = true;
3653 vf[0]->next_vf_pts = vf[1]->pts;
3654 } else
3655 vf[0]->next_vf_pts_valid = false;
3656 return vf[0];
3657 }
3658
3659 return NULL;
3660}
3661
3662static struct vframe_s *vh264_vf_get(void *op_arg)
3663{
3664 struct vframe_s *vf;
3665 struct vdec_s *vdec = op_arg;
3666 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3667
3668 if (!hw)
3669 return NULL;
3670
3671 if (force_disp_bufspec_num & 0x100) {
3672 int buffer_index = force_disp_bufspec_num & 0xff;
3673 if (force_disp_bufspec_num & 0x200)
3674 return NULL;
3675
3676 vf = &hw->vframe_dummy;
3677 vf->duration_pulldown = 0;
3678 vf->pts = 0;
3679 vf->pts_us64 = 0;
3680 set_frame_info(hw, vf, buffer_index);
3681 vf->flag = 0;
3682 if (hw->mmu_enable) {
3683 if (hw->double_write_mode & 0x10) {
3684 /* double write only */
3685 vf->compBodyAddr = 0;
3686 vf->compHeadAddr = 0;
3687 } else {
3688 /*head adr*/
3689 vf->compHeadAddr =
3690 hw->buffer_spec[buffer_index].alloc_header_addr;
3691 /*body adr*/
3692 vf->compBodyAddr = 0;
3693 vf->canvas0Addr = vf->canvas1Addr = 0;
3694 }
3695
3696 vf->type = VIDTYPE_SCATTER;
3697
3698 if (hw->double_write_mode) {
3699 vf->type |= VIDTYPE_PROGRESSIVE
3700 | VIDTYPE_VIU_FIELD;
3701 vf->type |= VIDTYPE_VIU_NV21;
3702 if (hw->double_write_mode == 3)
3703 vf->type |= VIDTYPE_COMPRESS;
3704
3705 vf->canvas0Addr = vf->canvas1Addr = -1;
3706 vf->plane_num = 2;
3707 vf->canvas0_config[0] =
3708 hw->buffer_spec[buffer_index].
3709 canvas_config[0];
3710 vf->canvas0_config[1] =
3711 hw->buffer_spec[buffer_index].
3712 canvas_config[1];
3713
3714 vf->canvas1_config[0] =
3715 hw->buffer_spec[buffer_index].
3716 canvas_config[0];
3717 vf->canvas1_config[1] =
3718 hw->buffer_spec[buffer_index].
3719 canvas_config[1];
3720 } else {
3721 vf->type |=
3722 VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
3723 vf->canvas0Addr = vf->canvas1Addr = 0;
3724 }
3725 vf->bitdepth =
3726 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
3727
3728 vf->compWidth = hw->frame_width;
3729 vf->compHeight = hw->frame_height;
3730
3731 if (hw->double_write_mode) {
3732 vf->width = hw->frame_width /
3733 get_double_write_ratio(hw);
3734 vf->height = hw->frame_height /
3735 get_double_write_ratio(hw);
3736 }
3737 } else {
3738 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
3739 VIDTYPE_VIU_NV21;
3740 vf->canvas0Addr = vf->canvas1Addr =
3741 spec2canvas(&hw->buffer_spec[buffer_index]);
3742 }
3743
3744 /*vf->mem_handle = decoder_bmmu_box_get_mem_handle(
3745 hw->bmmu_box, buffer_index);*/
3746 update_vf_memhandle(hw, vf, buffer_index);
3747 force_disp_bufspec_num |= 0x200;
3748 return vf;
3749 }
3750
3751 if (kfifo_get(&hw->display_q, &vf)) {
3752 int time = jiffies;
3753 unsigned int frame_interval =
3754 1000*(time - hw->last_frame_time)/HZ;
3755 struct vframe_s *next_vf;
3756 if (dpb_is_debug(DECODE_ID(hw),
3757 PRINT_FLAG_VDEC_DETAIL)) {
3758 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3759 int frame_index = FRAME_INDEX(vf->index);
3760 if (frame_index < 0 ||
3761 frame_index >= DPB_SIZE_MAX) {
3762 dpb_print(DECODE_ID(hw), 0,
3763 "%s vf index 0x%x error\r\n",
3764 __func__, vf->index);
3765 } else {
3766 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
3767 "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n",
3768 __func__, BUFSPEC_INDEX(vf->index), vf,
3769 p_H264_Dpb->mFrameStore[frame_index].poc,
3770 vf->duration, vf->pts, frame_interval);
3771 }
3772 }
3773 if (hw->last_frame_time > 0) {
3774 if (frame_interval >
3775 max_get_frame_interval[DECODE_ID(hw)])
3776 max_get_frame_interval[DECODE_ID(hw)]
3777 = frame_interval;
3778 }
3779 hw->last_frame_time = time;
3780 hw->vf_get_count++;
3781 if (kfifo_peek(&hw->display_q, &next_vf)) {
3782 vf->next_vf_pts_valid = true;
3783 vf->next_vf_pts = next_vf->pts;
3784 } else
3785 vf->next_vf_pts_valid = false;
3786 return vf;
3787 }
3788
3789 return NULL;
3790}
3791
3792static void vh264_vf_put(struct vframe_s *vf, void *op_arg)
3793{
3794 struct vdec_s *vdec = op_arg;
3795 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3796 int buf_spec_num;
3797 int frame_index;
3798
3799 if (vf == (&hw->vframe_dummy))
3800 return;
3801 if (vf->index == -1) {
3802 dpb_print(DECODE_ID(hw), 0,
3803 "Warning: %s vf %p invalid index\r\n",
3804 __func__, vf);
3805 return;
3806 }
3807 frame_index = FRAME_INDEX(vf->index);
3808 buf_spec_num = BUFSPEC_INDEX(vf->index);
3809 if (frame_index < 0 ||
3810 frame_index >= DPB_SIZE_MAX ||
3811 buf_spec_num < 0 ||
3812 buf_spec_num >= BUFSPEC_POOL_SIZE) {
3813 dpb_print(DECODE_ID(hw), 0,
3814 "%s vf index 0x%x error\r\n",
3815 __func__, vf->index);
3816 return;
3817 }
3818 /*get_buf_spec_idx_by_canvas_config(hw,
3819 &vf->canvas0_config[0]);*/
3820 if (hw->buffer_spec[buf_spec_num].used == 2) {
3821 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
3822 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3823 "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n",
3824 __func__, vf, frame_index,
3825 p_H264_Dpb->mFrameStore[frame_index].poc,
3826 buf_spec_num,
3827 hw->buffer_spec[buf_spec_num].used,
3828 hw->buffer_spec[buf_spec_num].vf_ref);
3829 hw->buffer_spec[buf_spec_num].vf_ref--;
3830 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0)
3831 set_frame_output_flag(&hw->dpb, frame_index);
3832 } else {
3833 unsigned long flags;
3834 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3835 "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n",
3836 __func__, vf, buf_spec_num,
3837 hw->buffer_spec[buf_spec_num].used,
3838 hw->buffer_spec[buf_spec_num].vf_ref);
3839 spin_lock_irqsave(&hw->bufspec_lock, flags);
3840 hw->buffer_spec[buf_spec_num].vf_ref--;
3841 if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) {
3842 if (hw->buffer_spec[buf_spec_num].used == 3)
3843 hw->buffer_spec[buf_spec_num].used = 4;
3844 else if (hw->buffer_spec[buf_spec_num].used == 5)
3845 hw->buffer_spec[buf_spec_num].used = 0;
3846 }
3847 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
3848 if (dpb_is_debug(DECODE_ID(hw),
3849 PRINT_FLAG_DUMP_BUFSPEC))
3850 dump_bufspec(hw, __func__);
3851
3852 }
3853
3854 hw->vf_put_count++;
3855 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
3856
3857#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG
3858 if (hw->buffer_empty_flag)
3859 WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1);
3860}
3861
3862static int vh264_event_cb(int type, void *data, void *op_arg)
3863{
3864 unsigned long flags;
3865 struct vdec_s *vdec = op_arg;
3866 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
3867
3868 if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
3869 struct provider_aux_req_s *req =
3870 (struct provider_aux_req_s *)data;
3871 int buf_spec_num = BUFSPEC_INDEX(req->vf->index);
3872 spin_lock_irqsave(&hw->lock, flags);
3873 req->aux_buf = NULL;
3874 req->aux_size = 0;
3875 if (buf_spec_num >= 0 &&
3876 buf_spec_num < BUFSPEC_POOL_SIZE &&
3877 is_buf_spec_in_disp_q(hw, buf_spec_num)
3878 ) {
3879 req->aux_buf =
3880 hw->buffer_spec[buf_spec_num].aux_data_buf;
3881 req->aux_size =
3882 hw->buffer_spec[buf_spec_num].aux_data_size;
3883#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
3884 req->dv_enhance_exist =
3885 hw->buffer_spec[buf_spec_num].dv_enhance_exist;
3886#else
3887 req->dv_enhance_exist = 0;
3888#endif
3889 }
3890 spin_unlock_irqrestore(&hw->lock, flags);
3891
3892 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
3893 "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n",
3894 __func__, type, buf_spec_num, req->aux_size);
3895 }
3896
3897 return 0;
3898}
3899
3900static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf,
3901 u32 index)
3902{
3903 struct canvas_config_s *p_canvas_config;
3904 int force_rate = input_frame_based(hw_to_vdec(hw)) ?
3905 force_rate_framebase : force_rate_streambase;
3906 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
3907 "%s (%d,%d) dur %d, vf %p, index %d\n", __func__,
3908 hw->frame_width, hw->frame_height, hw->frame_dur, vf, index);
3909
3910 vf->width = hw->frame_width;
3911 vf->height = hw->frame_height;
3912 if (force_rate) {
3913 if (force_rate == -1)
3914 vf->duration = 0;
3915 else
3916 vf->duration = 96000/force_rate;
3917 } else
3918 vf->duration = hw->frame_dur;
3919 vf->ratio_control =
3920 (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) <<
3921 DISP_RATIO_ASPECT_RATIO_BIT;
3922 vf->orientation = hw->vh264_rotation;
3923 if (hw->mmu_enable)
3924 return;
3925 vf->canvas0Addr = vf->canvas1Addr = -1;
3926#ifdef NV21
3927 vf->plane_num = 2;
3928#else
3929 vf->plane_num = 3;
3930#endif
3931
3932 if (IS_VDEC_DW(hw)) {
3933 vf->width = (hw->frame_width /2);
3934 if (IS_VDEC_DW(hw) == 2)
3935 vf->height = (hw->frame_height /2);
3936 p_canvas_config = &hw->buffer_spec[index].vdec_dw_canvas_config[0];
3937 } else
3938 p_canvas_config = &hw->buffer_spec[index].canvas_config[0];
3939
3940 vf->canvas0_config[0] = p_canvas_config[0];
3941 vf->canvas0_config[1] = p_canvas_config[1];
3942#ifndef NV21
3943 vf->canvas0_config[2] = p_canvas_config[2];
3944#endif
3945 vf->canvas1_config[0] = p_canvas_config[0];
3946 vf->canvas1_config[1] = p_canvas_config[1];
3947#ifndef NV21
3948 vf->canvas1_config[2] = p_canvas_config[2];
3949#endif
3950 /* signal_type */
3951 if (hw->video_signal_from_vui & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK)
3952 vf->signal_type = hw->video_signal_from_vui;
3953 else
3954 vf->signal_type = 0;
3955
3956}
3957
3958static void get_picture_qos_info(struct StorablePicture *picture)
3959{
3960 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
3961 unsigned char a[3];
3962 unsigned char i, j, t;
3963 unsigned long data;
3964
3965 get_random_bytes(&data, sizeof(unsigned long));
3966 if (picture->slice_type == I_SLICE)
3967 data = 0;
3968 a[0] = data & 0xff;
3969 a[1] = (data >> 8) & 0xff;
3970 a[2] = (data >> 16) & 0xff;
3971
3972 for (i = 0; i < 3; i++)
3973 for (j = i+1; j < 3; j++) {
3974 if (a[j] < a[i]) {
3975 t = a[j];
3976 a[j] = a[i];
3977 a[i] = t;
3978 } else if (a[j] == a[i]) {
3979 a[i]++;
3980 t = a[j];
3981 a[j] = a[i];
3982 a[i] = t;
3983 }
3984 }
3985 picture->max_mv = a[2];
3986 picture->avg_mv = a[1];
3987 picture->min_mv = a[0];
3988 /*
3989 pr_info("mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
3990 data, a[0], a[1], a[2]);
3991 */
3992
3993 get_random_bytes(&data, sizeof(unsigned long));
3994 a[0] = data & 0x1f;
3995 a[1] = (data >> 8) & 0x3f;
3996 a[2] = (data >> 16) & 0x7f;
3997
3998 for (i = 0; i < 3; i++)
3999 for (j = i+1; j < 3; j++) {
4000 if (a[j] < a[i]) {
4001 t = a[j];
4002 a[j] = a[i];
4003 a[i] = t;
4004 } else if (a[j] == a[i]) {
4005 a[i]++;
4006 t = a[j];
4007 a[j] = a[i];
4008 a[i] = t;
4009 }
4010 }
4011 picture->max_qp = a[2];
4012 picture->avg_qp = a[1];
4013 picture->min_qp = a[0];
4014 /*
4015 pr_info("qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
4016 data, a[0], a[1], a[2]);
4017 */
4018
4019 get_random_bytes(&data, sizeof(unsigned long));
4020 a[0] = data & 0x1f;
4021 a[1] = (data >> 8) & 0x3f;
4022 a[2] = (data >> 16) & 0x7f;
4023
4024 for (i = 0; i < 3; i++)
4025 for (j = i+1; j < 3; j++) {
4026 if (a[j] < a[i]) {
4027 t = a[j];
4028 a[j] = a[i];
4029 a[i] = t;
4030 } else if (a[j] == a[i]) {
4031 a[i]++;
4032 t = a[j];
4033 a[j] = a[i];
4034 a[i] = t;
4035 }
4036 }
4037 picture->max_skip = a[2];
4038 picture->avg_skip = a[1];
4039 picture->min_skip = a[0];
4040
4041
4042 /*
4043 pr_info("skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
4044 data,a[0], a[1], a[2]);
4045 */
4046 } else {
4047 uint32_t blk88_y_count;
4048 uint32_t blk88_c_count;
4049 uint32_t blk22_mv_count;
4050 uint32_t rdata32;
4051 int32_t mv_hi;
4052 int32_t mv_lo;
4053 uint32_t rdata32_l;
4054 uint32_t mvx_L0_hi;
4055 uint32_t mvy_L0_hi;
4056 uint32_t mvx_L1_hi;
4057 uint32_t mvy_L1_hi;
4058 int64_t value;
4059 uint64_t temp_value;
4060/*
4061#define DEBUG_QOS
4062*/
4063#ifdef DEBUG_QOS
4064 int pic_number = picture->poc;
4065#endif
4066
4067 picture->max_mv = 0;
4068 picture->avg_mv = 0;
4069 picture->min_mv = 0;
4070
4071 picture->max_skip = 0;
4072 picture->avg_skip = 0;
4073 picture->min_skip = 0;
4074
4075 picture->max_qp = 0;
4076 picture->avg_qp = 0;
4077 picture->min_qp = 0;
4078
4079
4080
4081
4082
4083 /* set rd_idx to 0 */
4084 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, 0);
4085 blk88_y_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4086 if (blk88_y_count == 0) {
4087#ifdef DEBUG_QOS
4088 pr_info(" [Picture %d Quality] NO Data yet.\n",
4089 pic_number);
4090#endif
4091 /* reset all counts */
4092 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4093 return;
4094 }
4095 /* qp_y_sum */
4096 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4097#ifdef DEBUG_QOS
4098 pr_info(" [Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
4099 pic_number, rdata32/blk88_y_count,
4100 rdata32, blk88_y_count);
4101#endif
4102 picture->avg_qp = rdata32/blk88_y_count;
4103 /* intra_y_count */
4104 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4105#ifdef DEBUG_QOS
4106 pr_info(" [Picture %d Quality] Y intra rate : %d%c (%d)\n",
4107 pic_number, rdata32*100/blk88_y_count,
4108 '%', rdata32);
4109#endif
4110 /* skipped_y_count */
4111 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4112#ifdef DEBUG_QOS
4113 pr_info(" [Picture %d Quality] Y skipped rate : %d%c (%d)\n",
4114 pic_number, rdata32*100/blk88_y_count,
4115 '%', rdata32);
4116#endif
4117 picture->avg_skip = rdata32*100/blk88_y_count;
4118 /* coeff_non_zero_y_count */
4119 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4120#ifdef DEBUG_QOS
4121 pr_info(" [Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
4122 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
4123 '%', rdata32);
4124#endif
4125 /* blk66_c_count */
4126 blk88_c_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4127 if (blk88_c_count == 0) {
4128#ifdef DEBUG_QOS
4129 pr_info(" [Picture %d Quality] NO Data yet.\n",
4130 pic_number);
4131#endif
4132 /* reset all counts */
4133 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4134 return;
4135 }
4136 /* qp_c_sum */
4137 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4138#ifdef DEBUG_QOS
4139 pr_info(" [Picture %d Quality] C QP AVG : %d (%d/%d)\n",
4140 pic_number, rdata32/blk88_c_count,
4141 rdata32, blk88_c_count);
4142#endif
4143 /* intra_c_count */
4144 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4145#ifdef DEBUG_QOS
4146 pr_info(" [Picture %d Quality] C intra rate : %d%c (%d)\n",
4147 pic_number, rdata32*100/blk88_c_count,
4148 '%', rdata32);
4149#endif
4150 /* skipped_cu_c_count */
4151 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4152#ifdef DEBUG_QOS
4153 pr_info(" [Picture %d Quality] C skipped rate : %d%c (%d)\n",
4154 pic_number, rdata32*100/blk88_c_count,
4155 '%', rdata32);
4156#endif
4157 /* coeff_non_zero_c_count */
4158 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4159#ifdef DEBUG_QOS
4160 pr_info(" [Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
4161 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
4162 '%', rdata32);
4163#endif
4164
4165 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
4166 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
4167 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4168#ifdef DEBUG_QOS
4169 pr_info(" [Picture %d Quality] Y QP min : %d\n",
4170 pic_number, (rdata32>>0)&0xff);
4171#endif
4172 picture->min_qp = (rdata32>>0)&0xff;
4173
4174#ifdef DEBUG_QOS
4175 pr_info(" [Picture %d Quality] Y QP max : %d\n",
4176 pic_number, (rdata32>>8)&0xff);
4177#endif
4178 picture->max_qp = (rdata32>>8)&0xff;
4179
4180#ifdef DEBUG_QOS
4181 pr_info(" [Picture %d Quality] C QP min : %d\n",
4182 pic_number, (rdata32>>16)&0xff);
4183 pr_info(" [Picture %d Quality] C QP max : %d\n",
4184 pic_number, (rdata32>>24)&0xff);
4185#endif
4186
4187 /* blk22_mv_count */
4188 blk22_mv_count = READ_VREG(VDEC_PIC_QUALITY_DATA);
4189 if (blk22_mv_count == 0) {
4190#ifdef DEBUG_QOS
4191 pr_info(" [Picture %d Quality] NO MV Data yet.\n",
4192 pic_number);
4193#endif
4194 /* reset all counts */
4195 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4196 return;
4197 }
4198 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
4199 mvy_L0_count[39:32], mvx_L0_count[39:32] */
4200 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4201 /* should all be 0x00 or 0xff */
4202#ifdef DEBUG_QOS
4203 pr_info(" [Picture %d Quality] MV AVG High Bits: 0x%X\n",
4204 pic_number, rdata32);
4205#endif
4206 mvx_L0_hi = ((rdata32>>0)&0xff);
4207 mvy_L0_hi = ((rdata32>>8)&0xff);
4208 mvx_L1_hi = ((rdata32>>16)&0xff);
4209 mvy_L1_hi = ((rdata32>>24)&0xff);
4210
4211 /* mvx_L0_count[31:0] */
4212 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4213 temp_value = mvx_L0_hi;
4214 temp_value = (temp_value << 32) | rdata32_l;
4215
4216 if (mvx_L0_hi & 0x80)
4217 value = 0xFFFFFFF000000000 | temp_value;
4218 else
4219 value = temp_value;
4220 value = div_s64(value, blk22_mv_count);
4221#ifdef DEBUG_QOS
4222 pr_info(" [Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
4223 pic_number, (int)(value),
4224 value, blk22_mv_count);
4225#endif
4226 picture->avg_mv = value;
4227
4228 /* mvy_L0_count[31:0] */
4229 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4230 temp_value = mvy_L0_hi;
4231 temp_value = (temp_value << 32) | rdata32_l;
4232
4233 if (mvy_L0_hi & 0x80)
4234 value = 0xFFFFFFF000000000 | temp_value;
4235 else
4236 value = temp_value;
4237#ifdef DEBUG_QOS
4238 pr_info(" [Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
4239 pic_number, rdata32_l/blk22_mv_count,
4240 value, blk22_mv_count);
4241#endif
4242
4243 /* mvx_L1_count[31:0] */
4244 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4245 temp_value = mvx_L1_hi;
4246 temp_value = (temp_value << 32) | rdata32_l;
4247 if (mvx_L1_hi & 0x80)
4248 value = 0xFFFFFFF000000000 | temp_value;
4249 else
4250 value = temp_value;
4251#ifdef DEBUG_QOS
4252 pr_info(" [Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
4253 pic_number, rdata32_l/blk22_mv_count,
4254 value, blk22_mv_count);
4255#endif
4256
4257 /* mvy_L1_count[31:0] */
4258 rdata32_l = READ_VREG(VDEC_PIC_QUALITY_DATA);
4259 temp_value = mvy_L1_hi;
4260 temp_value = (temp_value << 32) | rdata32_l;
4261 if (mvy_L1_hi & 0x80)
4262 value = 0xFFFFFFF000000000 | temp_value;
4263 else
4264 value = temp_value;
4265#ifdef DEBUG_QOS
4266 pr_info(" [Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
4267 pic_number, rdata32_l/blk22_mv_count,
4268 value, blk22_mv_count);
4269#endif
4270
4271 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
4272 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4273 mv_hi = (rdata32>>16)&0xffff;
4274 if (mv_hi & 0x8000)
4275 mv_hi = 0x8000 - mv_hi;
4276#ifdef DEBUG_QOS
4277 pr_info(" [Picture %d Quality] MVX_L0 MAX : %d\n",
4278 pic_number, mv_hi);
4279#endif
4280 picture->max_mv = mv_hi;
4281
4282 mv_lo = (rdata32>>0)&0xffff;
4283 if (mv_lo & 0x8000)
4284 mv_lo = 0x8000 - mv_lo;
4285#ifdef DEBUG_QOS
4286 pr_info(" [Picture %d Quality] MVX_L0 MIN : %d\n",
4287 pic_number, mv_lo);
4288#endif
4289 picture->min_mv = mv_lo;
4290
4291 /* {mvy_L0_max, mvy_L0_min} */
4292 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4293 mv_hi = (rdata32>>16)&0xffff;
4294 if (mv_hi & 0x8000)
4295 mv_hi = 0x8000 - mv_hi;
4296#ifdef DEBUG_QOS
4297 pr_info(" [Picture %d Quality] MVY_L0 MAX : %d\n",
4298 pic_number, mv_hi);
4299#endif
4300
4301 mv_lo = (rdata32>>0)&0xffff;
4302 if (mv_lo & 0x8000)
4303 mv_lo = 0x8000 - mv_lo;
4304#ifdef DEBUG_QOS
4305 pr_info(" [Picture %d Quality] MVY_L0 MIN : %d\n",
4306 pic_number, mv_lo);
4307#endif
4308
4309 /* {mvx_L1_max, mvx_L1_min} */
4310 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4311 mv_hi = (rdata32>>16)&0xffff;
4312 if (mv_hi & 0x8000)
4313 mv_hi = 0x8000 - mv_hi;
4314#ifdef DEBUG_QOS
4315 pr_info(" [Picture %d Quality] MVX_L1 MAX : %d\n",
4316 pic_number, mv_hi);
4317#endif
4318
4319 mv_lo = (rdata32>>0)&0xffff;
4320 if (mv_lo & 0x8000)
4321 mv_lo = 0x8000 - mv_lo;
4322#ifdef DEBUG_QOS
4323 pr_info(" [Picture %d Quality] MVX_L1 MIN : %d\n",
4324 pic_number, mv_lo);
4325#endif
4326
4327 /* {mvy_L1_max, mvy_L1_min} */
4328 rdata32 = READ_VREG(VDEC_PIC_QUALITY_DATA);
4329 mv_hi = (rdata32>>16)&0xffff;
4330 if (mv_hi & 0x8000)
4331 mv_hi = 0x8000 - mv_hi;
4332#ifdef DEBUG_QOS
4333 pr_info(" [Picture %d Quality] MVY_L1 MAX : %d\n",
4334 pic_number, mv_hi);
4335#endif
4336 mv_lo = (rdata32>>0)&0xffff;
4337 if (mv_lo & 0x8000)
4338 mv_lo = 0x8000 - mv_lo;
4339#ifdef DEBUG_QOS
4340 pr_info(" [Picture %d Quality] MVY_L1 MIN : %d\n",
4341 pic_number, mv_lo);
4342#endif
4343
4344 rdata32 = READ_VREG(VDEC_PIC_QUALITY_CTRL);
4345#ifdef DEBUG_QOS
4346 pr_info(" [Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
4347 pic_number, rdata32);
4348#endif
4349 /* reset all counts */
4350 WRITE_VREG(VDEC_PIC_QUALITY_CTRL, (1<<8));
4351 }
4352}
4353
4354static int get_max_dec_frame_buf_size(int level_idc,
4355 int max_reference_frame_num, int mb_width,
4356 int mb_height)
4357{
4358 int pic_size = mb_width * mb_height * 384;
4359
4360 int size = 0;
4361
4362 switch (level_idc) {
4363 case 9:
4364 size = 152064;
4365 break;
4366 case 10:
4367 size = 152064;
4368 break;
4369 case 11:
4370 size = 345600;
4371 break;
4372 case 12:
4373 size = 912384;
4374 break;
4375 case 13:
4376 size = 912384;
4377 break;
4378 case 20:
4379 size = 912384;
4380 break;
4381 case 21:
4382 size = 1824768;
4383 break;
4384 case 22:
4385 size = 3110400;
4386 break;
4387 case 30:
4388 size = 3110400;
4389 break;
4390 case 31:
4391 size = 6912000;
4392 break;
4393 case 32:
4394 size = 7864320;
4395 break;
4396 case 40:
4397 size = 12582912;
4398 break;
4399 case 41:
4400 size = 12582912;
4401 break;
4402 case 42:
4403 size = 13369344;
4404 break;
4405 case 50:
4406 size = 42393600;
4407 break;
4408 case 51:
4409 case 52:
4410 default:
4411 size = 70778880;
4412 break;
4413 }
4414
4415 size /= pic_size;
4416 size = size + 1; /* need one more buffer */
4417
4418 if (max_reference_frame_num < size)
4419 size = max_reference_frame_num;
4420
4421 return size;
4422}
4423
4424static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw)
4425{
4426 int i, j;
4427
4428 if (hw->double_write_mode) {
4429 mutex_lock(&vmh264_mutex);
4430 if (hw->decode_pic_count == 0) {
4431 for (j = 0; j < hw->dpb.mDPB.size; j++) {
4432 i = get_buf_spec_by_canvas_pos(hw, j);
4433 if (i >= 0)
4434 config_decode_canvas_ex(hw, i);
4435 }
4436 }
4437 mutex_unlock(&vmh264_mutex);
4438 }
4439}
4440
4441static int vh264_set_params(struct vdec_h264_hw_s *hw,
4442 u32 param1, u32 param2, u32 param3, u32 param4)
4443{
4444 int i, j;
4445 int mb_width, mb_total;
4446 int max_reference_size, level_idc;
4447 int mb_height = 0;
4448 unsigned long flags;
4449 /*int mb_mv_byte;*/
4450 struct vdec_s *vdec = hw_to_vdec(hw);
4451 u32 seq_info2;
4452 int ret = 0;
4453 int active_buffer_spec_num;
4454 unsigned int buf_size;
4455 unsigned int frame_mbs_only_flag;
4456 unsigned int chroma_format_idc, chroma444;
4457 unsigned int crop_infor, crop_bottom, crop_right;
4458 unsigned int used_reorder_dpb_size_margin
4459 = reorder_dpb_size_margin;
4460 u8 *colocate_vaddr = NULL;
4461
4462#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
4463 if (vdec->master || vdec->slave)
4464 used_reorder_dpb_size_margin =
4465 reorder_dpb_size_margin_dv;
4466#endif
4467 seq_info2 = param1;
4468 hw->seq_info = param2;
4469
4470 mb_width = seq_info2 & 0xff;
4471 mb_total = (seq_info2 >> 8) & 0xffff;
4472 if (!mb_width && mb_total) /*for 4k2k*/
4473 mb_width = 256;
4474 if (mb_width)
4475 mb_height = mb_total/mb_width;
4476 if (mb_width <= 0 || mb_height <= 0 ||
4477 is_oversize(mb_width << 4, mb_height << 4)) {
4478 dpb_print(DECODE_ID(hw), 0,
4479 "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n",
4480 seq_info2,
4481 mb_width,
4482 mb_height);
4483 return -1;
4484 }
4485
4486 if (seq_info2 != 0 &&
4487 hw->seq_info2 != (seq_info2 & (~0x80000000)) &&
4488 hw->seq_info2 != 0
4489 ) /*picture size changed*/
4490 h264_reconfig(hw);
4491
4492 if (hw->config_bufmgr_done == 0) {
4493 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4494 u32 reg_val;
4495 hw->cfg_param1 = param1;
4496 hw->cfg_param2 = param2;
4497 hw->cfg_param3 = param3;
4498 hw->cfg_param4 = param4;
4499
4500 hw->seq_info2 = seq_info2 & (~0x80000000);
4501 dpb_print(DECODE_ID(hw), 0,
4502 "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n",
4503 seq_info2, hw->seq_info);
4504
4505 dpb_init_global(&hw->dpb,
4506 DECODE_ID(hw), 0, 0);
4507
4508 p_H264_Dpb->fast_output_enable = fast_output_enable;
4509 /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/
4510
4511#if 1
4512 /*crop*/
4513 /* AV_SCRATCH_2
4514 bit 15: frame_mbs_only_flag
4515 bit 13-14: chroma_format_idc */
4516 frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01;
4517 chroma_format_idc = (hw->seq_info >> 13) & 0x03;
4518 chroma444 = (chroma_format_idc == 3) ? 1 : 0;
4519
4520 /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1
4521 @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) <<
4522 (2 - frame_mbs_only_flag) */
4523 crop_infor = param3;
4524 crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag);
4525 crop_right = ((crop_infor >> 16) & 0xff)
4526 >> (2 - frame_mbs_only_flag);
4527
4528 p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag;
4529 hw->frame_width = mb_width << 4;
4530 hw->frame_height = mb_height << 4;
4531 if (frame_mbs_only_flag) {
4532 hw->frame_height =
4533 hw->frame_height - (2 >> chroma444) *
4534 min(crop_bottom,
4535 (unsigned int)((8 << chroma444) - 1));
4536 hw->frame_width =
4537 hw->frame_width -
4538 (2 >> chroma444) * min(crop_right,
4539 (unsigned
4540 int)((8 << chroma444) - 1));
4541 } else {
4542 hw->frame_height =
4543 hw->frame_height - (4 >> chroma444) *
4544 min(crop_bottom,
4545 (unsigned int)((8 << chroma444)
4546 - 1));
4547 hw->frame_width =
4548 hw->frame_width -
4549 (4 >> chroma444) * min(crop_right,
4550 (unsigned int)((8 << chroma444) - 1));
4551 }
4552 dpb_print(DECODE_ID(hw), 0,
4553 "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d,\n",
4554 frame_mbs_only_flag, crop_bottom, hw->frame_height);
4555 dpb_print(DECODE_ID(hw), 0,
4556 "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n",
4557 mb_height, crop_right,
4558 hw->frame_width, mb_width);
4559
4560 if (hw->frame_height == 1088)
4561 hw->frame_height = 1080;
4562#endif
4563 if (!hw->mmu_enable) {
4564 mb_width = (mb_width+3) & 0xfffffffc;
4565 mb_height = (mb_height+3) & 0xfffffffc;
4566 }
4567 mb_total = mb_width * mb_height;
4568 hw->mb_width = mb_width;
4569 hw->mb_height = mb_height;
4570 hw->mb_total = mb_total;
4571 if (hw->mmu_enable)
4572 hevc_mcr_sao_global_hw_init(hw,
4573 (hw->mb_width << 4), (hw->mb_height << 4));
4574
4575 reg_val = param4;
4576 level_idc = reg_val & 0xff;
4577 max_reference_size = (reg_val >> 8) & 0xff;
4578 hw->dpb.origin_max_reference = max_reference_size;
4579 dpb_print(DECODE_ID(hw), 0,
4580 "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n",
4581 mb_height, mb_width, mb_total,
4582 level_idc, max_reference_size);
4583
4584
4585 p_H264_Dpb->colocated_buf_size = mb_total * 96;
4586 hw->dpb.reorder_pic_num =
4587 get_max_dec_frame_buf_size(level_idc,
4588 max_reference_size, mb_width, mb_height);
4589
4590 dpb_print(DECODE_ID(hw), 0,
4591 "restriction_flag=%d, max_dec_frame_buffering=%d, reorder_pic_num=%d\n",
4592 hw->bitstream_restriction_flag,
4593 hw->max_dec_frame_buffering,
4594 hw->dpb.reorder_pic_num);
4595
4596 if ((hw->bitstream_restriction_flag) &&
4597 (hw->max_dec_frame_buffering <
4598 hw->dpb.reorder_pic_num)) {
4599 hw->dpb.reorder_pic_num = hw->max_dec_frame_buffering;
4600 dpb_print(DECODE_ID(hw), 0,
4601 "set reorder_pic_num to %d\n",
4602 hw->dpb.reorder_pic_num);
4603 }
4604
4605 active_buffer_spec_num =
4606 hw->dpb.reorder_pic_num
4607 + used_reorder_dpb_size_margin;
4608 hw->max_reference_size =
4609 max_reference_size + reference_buf_margin;
4610
4611 if (active_buffer_spec_num > MAX_VF_BUF_NUM) {
4612 active_buffer_spec_num = MAX_VF_BUF_NUM;
4613 hw->dpb.reorder_pic_num = active_buffer_spec_num
4614 - used_reorder_dpb_size_margin;
4615 }
4616 hw->dpb.mDPB.size = active_buffer_spec_num;
4617 if (hw->max_reference_size > MAX_VF_BUF_NUM)
4618 hw->max_reference_size = MAX_VF_BUF_NUM;
4619 hw->dpb.max_reference_size = hw->max_reference_size;
4620
4621 if (hw->no_poc_reorder_flag)
4622 hw->dpb.reorder_pic_num = 1;
4623 dpb_print(DECODE_ID(hw), 0,
4624 "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n",
4625 __func__, active_buffer_spec_num,
4626 hw->dpb.reorder_pic_num,
4627 hw->max_reference_size);
4628
4629 buf_size = (hw->mb_total << 8) + (hw->mb_total << 7);
4630
4631 mutex_lock(&vmh264_mutex);
4632 if (!hw->mmu_enable) {
4633 config_buf_specs(vdec);
4634 i = get_buf_spec_by_canvas_pos(hw, 0);
4635
4636 if (hw->is_used_v4l) {
4637 if (i != -1) {
4638 pr_info("alloc the buf of v4l when it is about to decoding.\n");
4639 }
4640 } else {
4641 if ((i != -1) && alloc_one_buf_spec(hw, i) >= 0)
4642 config_decode_canvas(hw, i);
4643 else
4644 ret = -1;
4645 }
4646 } else {
4647 if (hw->double_write_mode) {
4648 config_buf_specs_ex(vdec);
4649 } else {
4650 spin_lock_irqsave(&hw->bufspec_lock, flags);
4651 for (i = 0, j = 0;
4652 j < active_buffer_spec_num
4653 && i < BUFSPEC_POOL_SIZE;
4654 i++) {
4655 if (hw->buffer_spec[i].used != -1)
4656 continue;
4657 hw->buffer_spec[i].used = 0;
4658 hw->buffer_spec[i].
4659 alloc_header_addr = 0;
4660 hw->buffer_spec[i].canvas_pos = j;
4661 j++;
4662 }
4663 spin_unlock_irqrestore(&hw->bufspec_lock,
4664 flags);
4665 }
4666 hevc_mcr_config_canv2axitbl(hw, 0);
4667 }
4668 mutex_unlock(&vmh264_mutex);
4669 if (dpb_is_debug(DECODE_ID(hw),
4670 PRINT_FLAG_DUMP_BUFSPEC))
4671 dump_bufspec(hw, __func__);
4672
4673#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4674 buf_size = PAGE_ALIGN(
4675 p_H264_Dpb->colocated_buf_size *
4676 active_buffer_spec_num);
4677#else
4678 buf_size = PAGE_ALIGN(
4679 p_H264_Dpb->colocated_buf_size *
4680 hw->max_reference_size);
4681#endif
4682
4683 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX,
4684 buf_size, DRIVER_NAME,
4685 &hw->collocate_cma_alloc_addr) < 0)
4686 return -1;
4687 if (!vdec_secure(vdec)) {
4688 /* clear for some mosaic problem after reset bufmgr */
4689 colocate_vaddr = codec_mm_vmap(hw->collocate_cma_alloc_addr, buf_size);
4690 if (colocate_vaddr != NULL) {
4691 memset(colocate_vaddr, 0, buf_size);
4692 codec_mm_dma_flush(colocate_vaddr, buf_size, DMA_TO_DEVICE);
4693 codec_mm_unmap_phyaddr(colocate_vaddr);
4694 }
4695 }
4696
4697 hw->dpb.colocated_mv_addr_start =
4698 hw->collocate_cma_alloc_addr;
4699#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF
4700 hw->dpb.colocated_mv_addr_end =
4701 hw->dpb.colocated_mv_addr_start +
4702 (p_H264_Dpb->colocated_buf_size *
4703 active_buffer_spec_num);
4704#else
4705 hw->dpb.colocated_mv_addr_end =
4706 hw->dpb.colocated_mv_addr_start +
4707 (p_H264_Dpb->colocated_buf_size *
4708 hw->max_reference_size);
4709#endif
4710 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4711 "callocate cma, %lx, %x\n",
4712 hw->collocate_cma_alloc_addr,
4713 hw->dpb.colocated_mv_addr_start);
4714
4715 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4716 "colocated_mv_addr_start %x colocated_mv_addr_end %x\n",
4717 hw->dpb.colocated_mv_addr_start,
4718 hw->dpb.colocated_mv_addr_end);
4719 if (!hw->mmu_enable) {
4720 mutex_lock(&vmh264_mutex);
4721 if (ret >= 0 && hw->decode_pic_count == 0) {
4722 int buf_cnt;
4723 /* h264_reconfig: alloc later*/
4724 buf_cnt = hw->dpb.mDPB.size;
4725
4726 for (j = 1; j < buf_cnt; j++) {
4727 i = get_buf_spec_by_canvas_pos(hw, j);
4728
4729 if (hw->is_used_v4l) {
4730 pr_info("alloc the buf of v4l when it is about to decoding.\n");
4731 break;
4732 } else if (alloc_one_buf_spec(hw, i) < 0)
4733 break;
4734
4735 config_decode_canvas(hw, i);
4736 }
4737 }
4738 mutex_unlock(&vmh264_mutex);
4739 } else {
4740 vh264_config_canvs_for_mmu(hw);
4741 }
4742
4743 hw->config_bufmgr_done = 1;
4744
4745 /*end of config_bufmgr_done */
4746 }
4747
4748 return ret;
4749}
4750
4751static void vui_config(struct vdec_h264_hw_s *hw)
4752{
4753 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4754 int aspect_ratio_info_present_flag, aspect_ratio_idc;
4755 /*time*/
4756 hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick;
4757 hw->time_scale = p_H264_Dpb->time_scale;
4758 hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2;
4759
4760 hw->bitstream_restriction_flag =
4761 p_H264_Dpb->bitstream_restriction_flag;
4762 hw->num_reorder_frames =
4763 p_H264_Dpb->num_reorder_frames;
4764 hw->max_dec_frame_buffering =
4765 p_H264_Dpb->max_dec_frame_buffering;
4766
4767 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
4768 "vui_config: pdb %d, %d, %d\n",
4769 p_H264_Dpb->bitstream_restriction_flag,
4770 p_H264_Dpb->num_reorder_frames,
4771 p_H264_Dpb->max_dec_frame_buffering);
4772
4773 hw->fixed_frame_rate_flag = 0;
4774 if (hw->timing_info_present_flag) {
4775 hw->fixed_frame_rate_flag =
4776 p_H264_Dpb->fixed_frame_rate_flag;
4777
4778 if (((hw->num_units_in_tick * 120) >= hw->time_scale &&
4779 ((!hw->sync_outside) ||
4780 (!hw->frame_dur)))
4781 && hw->num_units_in_tick && hw->time_scale) {
4782 if (hw->use_idr_framerate ||
4783 hw->fixed_frame_rate_flag ||
4784 !hw->frame_dur ||
4785 !hw->duration_from_pts_done
4786 /*|| vh264_running*/) {
4787 u32 frame_dur_es =
4788 div_u64(96000ULL * 2 * hw->num_units_in_tick,
4789 hw->time_scale);
4790 if (hw->frame_dur != frame_dur_es) {
4791 hw->h264_first_valid_pts_ready = false;
4792 hw->h264pts1 = 0;
4793 hw->h264pts2 = 0;
4794 hw->h264_pts_count = 0;
4795 hw->duration_from_pts_done = 0;
4796 fixed_frame_rate_mode =
4797 FIX_FRAME_RATE_OFF;
4798 hw->pts_duration = 0;
4799 hw->frame_dur = frame_dur_es;
4800 vdec_schedule_work(&hw->notify_work);
4801 dpb_print(DECODE_ID(hw),
4802 PRINT_FLAG_DEC_DETAIL,
4803 "frame_dur %d from timing_info\n",
4804 hw->frame_dur);
4805 }
4806
4807 /*hack to avoid use ES frame duration when
4808 *it's half of the rate from system info
4809 * sometimes the encoder is given a wrong
4810 * frame rate but the system side information
4811 * is more reliable
4812 *if ((frame_dur * 2) != frame_dur_es) {
4813 * frame_dur = frame_dur_es;
4814 *}
4815 */
4816 }
4817 }
4818 } else {
4819 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4820 "H.264: timing_info not present\n");
4821 }
4822
4823 /*aspect ratio*/
4824 aspect_ratio_info_present_flag =
4825 p_H264_Dpb->vui_status & 0x1;
4826 aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc;
4827
4828 if (aspect_ratio_info_present_flag) {
4829 if (aspect_ratio_idc == EXTEND_SAR) {
4830 hw->h264_ar = 0x3ff;
4831 hw->height_aspect_ratio =
4832 p_H264_Dpb->aspect_ratio_sar_height;
4833 hw->width_aspect_ratio =
4834 p_H264_Dpb->aspect_ratio_sar_width;
4835 } else {
4836 /* pr_info("v264dec: aspect_ratio_idc = %d\n",
4837 aspect_ratio_idc); */
4838
4839 switch (aspect_ratio_idc) {
4840 case 1:
4841 hw->h264_ar = 0x3ff;
4842 hw->height_aspect_ratio = 1;
4843 hw->width_aspect_ratio = 1;
4844 break;
4845 case 2:
4846 hw->h264_ar = 0x3ff;
4847 hw->height_aspect_ratio = 11;
4848 hw->width_aspect_ratio = 12;
4849 break;
4850 case 3:
4851 hw->h264_ar = 0x3ff;
4852 hw->height_aspect_ratio = 11;
4853 hw->width_aspect_ratio = 10;
4854 break;
4855 case 4:
4856 hw->h264_ar = 0x3ff;
4857 hw->height_aspect_ratio = 11;
4858 hw->width_aspect_ratio = 16;
4859 break;
4860 case 5:
4861 hw->h264_ar = 0x3ff;
4862 hw->height_aspect_ratio = 33;
4863 hw->width_aspect_ratio = 40;
4864 break;
4865 case 6:
4866 hw->h264_ar = 0x3ff;
4867 hw->height_aspect_ratio = 11;
4868 hw->width_aspect_ratio = 24;
4869 break;
4870 case 7:
4871 hw->h264_ar = 0x3ff;
4872 hw->height_aspect_ratio = 11;
4873 hw->width_aspect_ratio = 20;
4874 break;
4875 case 8:
4876 hw->h264_ar = 0x3ff;
4877 hw->height_aspect_ratio = 11;
4878 hw->width_aspect_ratio = 32;
4879 break;
4880 case 9:
4881 hw->h264_ar = 0x3ff;
4882 hw->height_aspect_ratio = 33;
4883 hw->width_aspect_ratio = 80;
4884 break;
4885 case 10:
4886 hw->h264_ar = 0x3ff;
4887 hw->height_aspect_ratio = 11;
4888 hw->width_aspect_ratio = 18;
4889 break;
4890 case 11:
4891 hw->h264_ar = 0x3ff;
4892 hw->height_aspect_ratio = 11;
4893 hw->width_aspect_ratio = 15;
4894 break;
4895 case 12:
4896 hw->h264_ar = 0x3ff;
4897 hw->height_aspect_ratio = 33;
4898 hw->width_aspect_ratio = 64;
4899 break;
4900 case 13:
4901 hw->h264_ar = 0x3ff;
4902 hw->height_aspect_ratio = 99;
4903 hw->width_aspect_ratio = 160;
4904 break;
4905 case 14:
4906 hw->h264_ar = 0x3ff;
4907 hw->height_aspect_ratio = 3;
4908 hw->width_aspect_ratio = 4;
4909 break;
4910 case 15:
4911 hw->h264_ar = 0x3ff;
4912 hw->height_aspect_ratio = 2;
4913 hw->width_aspect_ratio = 3;
4914 break;
4915 case 16:
4916 hw->h264_ar = 0x3ff;
4917 hw->height_aspect_ratio = 1;
4918 hw->width_aspect_ratio = 2;
4919 break;
4920 default:
4921 if (hw->vh264_ratio >> 16) {
4922 hw->h264_ar = (hw->frame_height *
4923 (hw->vh264_ratio & 0xffff) *
4924 0x100 +
4925 ((hw->vh264_ratio >> 16) *
4926 hw->frame_width / 2)) /
4927 ((hw->vh264_ratio >> 16) *
4928 hw->frame_width);
4929 hw->height_aspect_ratio = 1;
4930 hw->width_aspect_ratio = 1;
4931 } else {
4932 hw->h264_ar = 0x3ff;
4933 hw->height_aspect_ratio = 1;
4934 hw->width_aspect_ratio = 1;
4935 }
4936 break;
4937 }
4938 }
4939 } else {
4940 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4941 "v264dec: aspect_ratio not available from source\n");
4942 if (hw->vh264_ratio >> 16) {
4943 /* high 16 bit is width, low 16 bit is height */
4944 hw->h264_ar =
4945 ((hw->vh264_ratio & 0xffff) *
4946 hw->frame_height * 0x100 +
4947 (hw->vh264_ratio >> 16) *
4948 hw->frame_width / 2) /
4949 ((hw->vh264_ratio >> 16) *
4950 hw->frame_width);
4951 hw->height_aspect_ratio = 1;
4952 hw->width_aspect_ratio = 1;
4953 } else {
4954 hw->h264_ar = 0x3ff;
4955 hw->height_aspect_ratio = 1;
4956 hw->width_aspect_ratio = 1;
4957 }
4958 }
4959
4960 if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) {
4961 if (((hw->frame_dur == RATE_2397_FPS)
4962 && (dec_control
4963 & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE))
4964 || ((RATE_2997_FPS ==
4965 hw->frame_dur) &&
4966 (dec_control &
4967 DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) {
4968 dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL,
4969 "force fix frame rate\n");
4970 hw->fixed_frame_rate_flag = 0x40;
4971 }
4972 }
4973
4974 /*video_signal_from_vui: to do .. */
4975}
4976
4977static void bufmgr_recover(struct vdec_h264_hw_s *hw)
4978{
4979 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
4980
4981 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4982 if (error_proc_policy & 0x20) {
4983 if (!hw->is_used_v4l)
4984 hw->reset_bufmgr_flag = 1;
4985 }
4986}
4987
4988void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb)
4989{
4990 struct vdec_h264_hw_s *hw =
4991 container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb);
4992
4993 dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__);
4994
4995 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2);
4996 hw->reset_bufmgr_flag = 1;
4997}
4998
4999#ifdef CONSTRAIN_MAX_BUF_NUM
5000static int get_vf_ref_only_buf_count(struct vdec_h264_hw_s *hw)
5001{
5002 int i;
5003 int count = 0;
5004 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5005 if (is_buf_spec_in_disp_q(hw, i) &&
5006 hw->buffer_spec[i].vf_ref > 0)
5007 count++;
5008 }
5009 return count;
5010}
5011
5012static int get_used_buf_count(struct vdec_h264_hw_s *hw)
5013{
5014 int i;
5015 int count = 0;
5016 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
5017 if (is_buf_spec_in_use(hw, i))
5018 count++;
5019 }
5020 return count;
5021}
5022#endif
5023
5024
5025static bool is_buffer_available(struct vdec_s *vdec)
5026{
5027 bool buffer_available = 1;
5028 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5029 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5030 struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB;
5031 if ((kfifo_len(&hw->newframe_q) <= 0) ||
5032 ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) ||
5033 ((p_H264_Dpb->mDPB.init_done) &&
5034 (p_H264_Dpb->mDPB.used_size >= (p_H264_Dpb->mDPB.size -1)) &&
5035 (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) {
5036 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
5037 "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n",
5038 __func__,
5039 kfifo_len(&hw->newframe_q),
5040 have_free_buf_spec(vdec),
5041 p_H264_Dpb->mDPB.init_done,
5042 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
5043 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB)
5044 );
5045 buffer_available = 0;
5046 if (dpb_is_debug(DECODE_ID(hw),
5047 DEBUG_DISABLE_RUNREADY_RMBUF))
5048 return buffer_available;
5049
5050 if ((error_proc_policy & 0x4) &&
5051 (error_proc_policy & 0x8)) {
5052 if ((kfifo_len(&hw->display_q) <= 0) &&
5053 (p_H264_Dpb->mDPB.used_size ==
5054 p_H264_Dpb->mDPB.size) &&
5055 (p_Dpb->ref_frames_in_buffer >
5056 (imax(
5057 1, p_Dpb->num_ref_frames)
5058 - p_Dpb->ltref_frames_in_buffer +
5059 force_sliding_margin)))
5060 bufmgr_recover(hw);
5061 else
5062 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5063 } else if ((error_proc_policy & 0x4) &&
5064 (kfifo_len(&hw->display_q) <= 0) &&
5065 ((p_H264_Dpb->mDPB.used_size ==
5066 p_H264_Dpb->mDPB.size) ||
5067 (!have_free_buf_spec(vdec)))) {
5068 enum receviver_start_e state = RECEIVER_INACTIVE;
5069 if ((error_proc_policy & 0x10) &&
5070 vf_get_receiver(vdec->vf_provider_name)) {
5071 state =
5072 vf_notify_receiver(vdec->vf_provider_name,
5073 VFRAME_EVENT_PROVIDER_QUREY_STATE,
5074 NULL);
5075 if ((state == RECEIVER_STATE_NULL)
5076 || (state == RECEIVER_STATE_NONE))
5077 state = RECEIVER_INACTIVE;
5078 }
5079 if (state == RECEIVER_INACTIVE)
5080 bufmgr_recover(hw);
5081 else
5082 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5083 } else if ((error_proc_policy & 0x8) &&
5084 (p_Dpb->ref_frames_in_buffer >
5085 (imax(
5086 1, p_Dpb->num_ref_frames)
5087 - p_Dpb->ltref_frames_in_buffer +
5088 force_sliding_margin)))
5089 bufmgr_recover(hw);
5090 else
5091 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1);
5092
5093 if (hw->reset_bufmgr_flag == 1)
5094 buffer_available = 1;
5095 }
5096
5097 return buffer_available;
5098}
5099
5100#define AUX_TAG_SEI 0x2
5101
5102#define SEI_BUFFERING_PERIOD 0
5103#define SEI_PicTiming 1
5104#define SEI_USER_DATA 4
5105#define SEI_RECOVERY_POINT 6
5106
5107/*
5108 *************************************************************************
5109 * Function:Reads bits from the bitstream buffer
5110 * Input:
5111 byte buffer[]
5112 containing sei message data bits
5113 int totbitoffset
5114 bit offset from start of partition
5115 int bytecount
5116 total bytes in bitstream
5117 int numbits
5118 number of bits to read
5119 * Output:
5120 int *info
5121 * Return:
5122 -1: failed
5123 > 0: the count of bit read
5124 * Attention:
5125 *************************************************************************
5126 */
5127
5128static int get_bits(unsigned char buffer[],
5129 int totbitoffset,
5130 int *info,
5131 int bytecount,
5132 int numbits)
5133{
5134 register int inf;
5135 long byteoffset;
5136 int bitoffset;
5137
5138 int bitcounter = numbits;
5139
5140 byteoffset = totbitoffset / 8;
5141 bitoffset = 7 - (totbitoffset % 8);
5142
5143 inf = 0;
5144 while (numbits) {
5145 inf <<= 1;
5146 inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset;
5147 numbits--;
5148 bitoffset--;
5149 if (bitoffset < 0) {
5150 byteoffset++;
5151 bitoffset += 8;
5152 if (byteoffset > bytecount)
5153 return -1;
5154 }
5155 }
5156
5157 *info = inf;
5158
5159
5160 return bitcounter;
5161}
5162
5163static int parse_one_sei_record(struct vdec_h264_hw_s *hw,
5164 u8 *sei_data_buf,
5165 u8 *sei_data_buf_end)
5166{
5167 int payload_type;
5168 int payload_size;
5169 u8 *p_sei;
5170 int temp = 0;
5171 int bit_offset;
5172 int read_size;
5173 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5174
5175 p_sei = sei_data_buf;
5176 read_size = 0;
5177 payload_type = 0;
5178 do {
5179 if (p_sei >= sei_data_buf_end)
5180 return read_size;
5181
5182 payload_type += *p_sei;
5183 read_size++;
5184 } while (*p_sei++ == 255);
5185
5186
5187 payload_size = 0;
5188 do {
5189 if (p_sei >= sei_data_buf_end)
5190 return read_size;
5191
5192 payload_size += *p_sei;
5193 read_size++;
5194 } while (*p_sei++ == 255);
5195
5196
5197 if (p_sei + payload_size > sei_data_buf_end) {
5198 dpb_print(DECODE_ID(hw), 0,
5199 "%s: payload_type = %d, payload_size = %d is over\n",
5200 __func__, payload_type, payload_size);
5201 return read_size;
5202 }
5203 bit_offset = 0;
5204
5205 if (payload_size <= 0) {
5206 dpb_print(DECODE_ID(hw), 0,
5207 "%s warning: this is a null sei message for payload_type = %d\n",
5208 __func__, payload_type);
5209 return read_size;
5210 }
5211 switch (payload_type) {
5212 case SEI_BUFFERING_PERIOD:
5213 break;
5214 case SEI_PicTiming:
5215 if (p_H264_Dpb->vui_status & 0xc) {
5216 int cpb_removal_delay;
5217 int dpb_output_delay;
5218 u32 delay_len;
5219
5220 delay_len = p_H264_Dpb->dpb_param.l.data[DELAY_LENGTH];
5221 cpb_removal_delay
5222 = (delay_len & 0x1F) + 1;
5223 dpb_output_delay
5224 = ((delay_len >> 5) & 0x1F) + 1;
5225
5226 get_bits(p_sei, bit_offset,
5227 &temp, payload_size,
5228 dpb_output_delay+cpb_removal_delay);
5229 bit_offset += dpb_output_delay+cpb_removal_delay;
5230 }
5231 if (p_H264_Dpb->vui_status & 0x10) {
5232 get_bits(p_sei, bit_offset, &temp, payload_size, 4);
5233 bit_offset += 4;
5234 p_H264_Dpb->dpb_param.l.data[PICTURE_STRUCT] = temp;
5235 }
5236 break;
5237 case SEI_USER_DATA:
5238 if (enable_itu_t35) {
5239 int i;
5240 int j;
5241 int data_len;
5242 u8 *user_data_buf;
5243
5244 user_data_buf
5245 = hw->sei_itu_data_buf + hw->sei_itu_data_len;
5246 /* user data length should be align with 8 bytes,
5247 if not, then padding with zero*/
5248 for (i = 0; i < payload_size; i += 8) {
5249 for (j = 0; j < 8; j++) {
5250 int index;
5251
5252 index = i+7-j;
5253 if (index >= payload_size)
5254 user_data_buf[i+j] = 0;
5255 else
5256 user_data_buf[i+j]
5257 = p_sei[i+7-j];
5258 }
5259 }
5260
5261 data_len = payload_size;
5262 if (payload_size % 8)
5263 data_len = ((payload_size + 8) >> 3) << 3;
5264
5265 hw->sei_itu_data_len += data_len;
5266 /*
5267 dpb_print(DECODE_ID(hw), 0,
5268 "%s: user data, and len = %d:\n",
5269 __func__, hw->sei_itu_data_len);
5270 */
5271 }
5272 break;
5273 case SEI_RECOVERY_POINT:
5274 p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT] = 1;
5275 break;
5276 }
5277
5278 return read_size + payload_size;
5279}
5280
5281static void parse_sei_data(struct vdec_h264_hw_s *hw,
5282 u8 *sei_data_buf,
5283 int len)
5284{
5285 char *p_sei;
5286 char *p_sei_end;
5287 int parsed_size;
5288 int read_size;
5289
5290
5291 p_sei = sei_data_buf;
5292 p_sei_end = p_sei + len;
5293 parsed_size = 0;
5294 while (parsed_size < len) {
5295 read_size = parse_one_sei_record(hw, p_sei, p_sei_end);
5296 p_sei += read_size;
5297 parsed_size += read_size;
5298 if (*p_sei == 0x80) {
5299 p_sei++;
5300 parsed_size++;
5301 }
5302 }
5303}
5304
5305static void check_decoded_pic_error(struct vdec_h264_hw_s *hw)
5306{
5307 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5308 struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture;
5309 unsigned mby_mbx = READ_VREG(MBY_MBX);
5310 unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff;
5311 unsigned decode_mb_count =
5312 ((mby_mbx & 0xff) * hw->mb_width +
5313 (((mby_mbx >> 8) & 0xff) + 1));
5314 if (mby_mbx == 0)
5315 return;
5316 if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME)
5317 mb_total /= 2;
5318 if (error_proc_policy & 0x100) {
5319 if (decode_mb_count < mb_total)
5320 p->data_flag |= ERROR_FLAG;
5321 }
5322
5323 if ((error_proc_policy & 0x200) &&
5324 READ_VREG(ERROR_STATUS_REG) != 0) {
5325 p->data_flag |= ERROR_FLAG;
5326 }
5327
5328 if (p->data_flag & ERROR_FLAG) {
5329 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG,
5330 "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n",
5331 __func__,
5332 hw->seq_info2,
5333 mby_mbx,
5334 mb_total,
5335 decode_mb_count,
5336 READ_VREG(ERROR_STATUS_REG)
5337 );
5338
5339 }
5340}
5341
5342static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq)
5343{
5344 int i;
5345 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
5346 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
5347 unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status;
5348 u32 debug_tag;
5349 int ret;
5350 if (++hw->tfn_cnt == 1) {
5351 hw->tfn_ns = local_clock();
5352 } else if (hw->tfn_cnt >= 10) {
5353 u64 tenth_ns = local_clock();
5354 /* Here borrow the varible debug_tag for use */
5355 debug_tag = tenth_ns - hw->tfn_ns;
5356 hw->tfn_cnt = 1;
5357 hw->tfn_cnt = tenth_ns;
5358 if (debug_tag <= 10000000)
5359 pr_err("Within 10ms 10 vh264_isr_thread_fn!\n");
5360 }
5361
5362 if (dec_dpb_status == H264_CONFIG_REQUEST) {
5363#if 1
5364 unsigned short *p = (unsigned short *)hw->lmem_addr;
5365 dma_sync_single_for_cpu(
5366 amports_get_dma_device(),
5367 hw->lmem_addr_remap,
5368 PAGE_SIZE,
5369 DMA_FROM_DEVICE);
5370 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5371 int ii;
5372 for (ii = 0; ii < 4; ii++) {
5373 p_H264_Dpb->dpb_param.l.data[i+ii] =
5374 p[i+3-ii];
5375 if (dpb_is_debug(DECODE_ID(hw),
5376 RRINT_FLAG_RPM)) {
5377 if (((i + ii) & 0xf) == 0)
5378 dpb_print(DECODE_ID(hw),
5379 0, "%04x:",
5380 i);
5381 dpb_print_cont(DECODE_ID(hw),
5382 0, "%04x ",
5383 p[i+3-ii]);
5384 if (((i + ii + 1) & 0xf) == 0)
5385 dpb_print_cont(
5386 DECODE_ID(hw),
5387 0, "\r\n");
5388 }
5389 }
5390 }
5391
5392 p_H264_Dpb->bitstream_restriction_flag =
5393 (p_H264_Dpb->dpb_param.l.data[SPS_FLAGS2] >> 3) & 0x1;
5394 p_H264_Dpb->num_reorder_frames =
5395 p_H264_Dpb->dpb_param.l.data[NUM_REORDER_FRAMES];
5396 p_H264_Dpb->max_dec_frame_buffering =
5397 p_H264_Dpb->dpb_param.l.data[MAX_BUFFER_FRAME];
5398
5399 dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL,
5400 "H264_CONFIG_REQUEST: pdb %d, %d, %d\n",
5401 p_H264_Dpb->bitstream_restriction_flag,
5402 p_H264_Dpb->num_reorder_frames,
5403 p_H264_Dpb->max_dec_frame_buffering);
5404 hw->bitstream_restriction_flag =
5405 p_H264_Dpb->bitstream_restriction_flag;
5406 hw->num_reorder_frames =
5407 p_H264_Dpb->num_reorder_frames;
5408 hw->max_dec_frame_buffering =
5409 p_H264_Dpb->max_dec_frame_buffering;
5410#endif
5411
5412 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE);
5413 reset_process_time(hw);
5414 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5415 hw->dec_result = DEC_RESULT_CONFIG_PARAM;
5416 vdec_schedule_work(&hw->work);
5417 } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) {
5418 u16 data_hight;
5419 u16 data_low;
5420 u32 video_signal;
5421
5422 int slice_header_process_status = 0;
5423 int I_flag;
5424 /*unsigned char is_idr;*/
5425 unsigned short *p = (unsigned short *)hw->lmem_addr;
5426 reset_process_time(hw);
5427
5428 if (hw->is_used_v4l) {
5429 struct aml_vcodec_ctx *ctx =
5430 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
5431
5432 if (ctx->param_sets_from_ucode && !ctx->v4l_codec_ready) {
5433 //amvdec_stop();
5434 hw->dec_result = DEC_RESULT_DONE;
5435 vdec_schedule_work(&hw->work);
5436 return IRQ_HANDLED;
5437 }
5438 }
5439
5440 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
5441 hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG);
5442 hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT);
5443 hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL);
5444 if (input_frame_based(vdec) &&
5445 frmbase_cont_bitlevel2 != 0 &&
5446 READ_VREG(VIFF_BIT_CNT) <
5447 frmbase_cont_bitlevel2 &&
5448 hw->get_data_count >= 0x70000000) {
5449 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5450 "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n",
5451 __func__,
5452 READ_VREG(VIFF_BIT_CNT));
5453
5454 goto empty_proc;
5455 }
5456
5457 dma_sync_single_for_cpu(
5458 amports_get_dma_device(),
5459 hw->lmem_addr_remap,
5460 PAGE_SIZE,
5461 DMA_FROM_DEVICE);
5462#if 0
5463 if (p_H264_Dpb->mVideo.dec_picture == NULL) {
5464 if (!is_buffer_available(vdec)) {
5465 hw->buffer_empty_flag = 1;
5466 dpb_print(DECODE_ID(hw),
5467 PRINT_FLAG_UCODE_EVT,
5468 "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n",
5469 __func__,
5470 kfifo_len(&hw->newframe_q),
5471 have_free_buf_spec(vdec),
5472 p_H264_Dpb->mDPB.init_done,
5473 p_H264_Dpb->mDPB.used_size,
5474 p_H264_Dpb->mDPB.size,
5475 is_there_unused_frame_from_dpb(
5476 &p_H264_Dpb->mDPB));
5477 return IRQ_HANDLED;
5478 }
5479 }
5480
5481 hw->buffer_empty_flag = 0;
5482#endif
5483#ifdef SEND_PARAM_WITH_REG
5484 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
5485 unsigned int data32;
5486
5487 do {
5488 data32 = READ_VREG(RPM_CMD_REG);
5489 /* printk("%x\n", data32); */
5490 } while ((data32&0x10000) == 0);
5491 p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff;
5492 WRITE_VREG(RPM_CMD_REG, 0);
5493 /* printk("%x:%x\n", i,data32); */
5494 }
5495#else
5496 for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) {
5497 int ii;
5498
5499 for (ii = 0; ii < 4; ii++) {
5500 p_H264_Dpb->dpb_param.l.data[i+ii] =
5501 p[i+3-ii];
5502 if (dpb_is_debug(DECODE_ID(hw),
5503 RRINT_FLAG_RPM)) {
5504 if (((i + ii) & 0xf) == 0)
5505 dpb_print(DECODE_ID(hw),
5506 0, "%04x:",
5507 i);
5508 dpb_print_cont(DECODE_ID(hw),
5509 0, "%04x ",
5510 p[i+3-ii]);
5511 if (((i + ii + 1) & 0xf) == 0)
5512 dpb_print_cont(
5513 DECODE_ID(hw),
5514 0, "\r\n");
5515 }
5516 }
5517 }
5518#endif
5519 data_low = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_LOW];
5520 data_hight = p_H264_Dpb->dpb_param.l.data[VIDEO_SIGNAL_HIGHT];
5521
5522 video_signal = (data_hight << 16) | data_low;
5523 hw->video_signal_from_vui =
5524 ((video_signal & 0xffff) << 8) |
5525 ((video_signal & 0xff0000) >> 16) |
5526 ((video_signal & 0x3f000000));
5527
5528
5529 /*dpb_print(DECODE_ID(hw),
5530 0,
5531 "video_signal_from_vui:0x%x, "
5532 "data_low:0x%x, data_hight:0x%x\n",
5533 hw->video_signal_from_vui,
5534 data_low,
5535 data_hight);*/
5536
5537 parse_sei_data(hw, hw->sei_data_buf, hw->sei_data_len);
5538
5539 if (hw->config_bufmgr_done == 0) {
5540 hw->dec_result = DEC_RESULT_DONE;
5541 vdec_schedule_work(&hw->work);
5542 dpb_print(DECODE_ID(hw),
5543 PRINT_FLAG_UCODE_EVT,
5544 "config_bufmgr not done, discard frame\n");
5545 return IRQ_HANDLED;
5546 } else if ((hw->first_i_policy & 0x3) != 0) {
5547 unsigned char is_i_slice =
5548 (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]
5549 == I_Slice)
5550 ? 1 : 0;
5551 unsigned char is_idr =
5552 ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f)
5553 == 5);
5554 if ((hw->first_i_policy & 0x3) == 0x3)
5555 is_i_slice = is_idr;
5556 if (!is_i_slice) {
5557 if (hw->has_i_frame == 0) {
5558 amvdec_stop();
5559 vdec->mc_loaded = 0;
5560 hw->dec_result = DEC_RESULT_DONE;
5561 vdec_schedule_work(&hw->work);
5562 dpb_print(DECODE_ID(hw),
5563 PRINT_FLAG_UCODE_EVT,
5564 "has_i_frame is 0, discard none I(DR) frame\n");
5565 return IRQ_HANDLED;
5566 }
5567 } else {
5568 if (hw->skip_frame_count < 0 || is_idr) {
5569 /* second I */
5570 hw->dec_flag &= (~NODISP_FLAG);
5571 hw->skip_frame_count = 0;
5572 }
5573 if (hw->has_i_frame == 0 &&
5574 (!is_idr)) {
5575 int skip_count =
5576 (hw->first_i_policy >> 8) & 0xff;
5577 /* first I (not IDR) */
5578 if ((hw->first_i_policy & 0x3) == 2)
5579 hw->skip_frame_count =
5580 -1 - skip_count;
5581 else
5582 hw->skip_frame_count =
5583 skip_count;
5584 if (hw->skip_frame_count != 0)
5585 hw->dec_flag |= NODISP_FLAG;
5586 }
5587 }
5588 }
5589 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
5590 "current dpb index %d, poc %d, top/bot poc (%d,%d)\n",
5591 p_H264_Dpb->dpb_param.dpb.current_dpb_index,
5592 val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt),
5593 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt),
5594 val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt));
5595 I_flag = (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] == I_Slice)
5596 ? I_FLAG : 0;
5597 if ((hw->i_only & 0x2) && (!(I_flag & I_FLAG)) &&
5598 (p_H264_Dpb->mSlice.structure == FRAME)) {
5599 hw->data_flag = NULL_FLAG;
5600 goto pic_done_proc;
5601 }
5602
5603 slice_header_process_status =
5604 h264_slice_header_process(p_H264_Dpb);
5605 if (hw->mmu_enable)
5606 hevc_sao_set_slice_type(hw,
5607 slice_header_process_status,
5608 hw->dpb.mSlice.idr_flag);
5609 vui_config(hw);
5610
5611 if (p_H264_Dpb->mVideo.dec_picture) {
5612 int cfg_ret = 0;
5613 bool field_pic_flag = false;
5614
5615 if (slice_header_process_status == 1) {
5616 if (!p_H264_Dpb->mSPS.frame_mbs_only_flag) {
5617 field_pic_flag =
5618 (p_H264_Dpb->mSlice.structure == TOP_FIELD ||
5619 p_H264_Dpb->mSlice.structure == BOTTOM_FIELD) ?
5620 true : false;
5621 }
5622
5623 if (!field_pic_flag && ((p_H264_Dpb->mSPS.profile_idc == BASELINE) ||
5624 (((unsigned long)(hw->vh264_amstream_dec_info
5625 .param)) & 0x8))) {
5626 p_H264_Dpb->fast_output_enable =
5627 H264_OUTPUT_MODE_FAST;
5628 }
5629 else
5630 p_H264_Dpb->fast_output_enable
5631 = fast_output_enable;
5632 hw->data_flag = I_flag;
5633 if ((p_H264_Dpb->
5634 dpb_param.dpb.NAL_info_mmco & 0x1f)
5635 == 5)
5636 hw->data_flag |= IDR_FLAG;
5637 dpb_print(DECODE_ID(hw),
5638 PRINT_FLAG_VDEC_STATUS,
5639 "==================> frame count %d to skip %d\n",
5640 hw->decode_pic_count+1,
5641 hw->skip_frame_count);
5642 } else if (error_proc_policy & 0x100){
5643 struct StorablePicture *p =
5644 p_H264_Dpb->mVideo.dec_picture;
5645 unsigned mby_mbx = READ_VREG(MBY_MBX);
5646 unsigned decode_mb_count =
5647 ((mby_mbx & 0xff) * hw->mb_width +
5648 (((mby_mbx >> 8) & 0xff) + 1));
5649 if (decode_mb_count <
5650 ((p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]) *
5651 (1 + p->mb_aff_frame_flag))) {
5652 dpb_print(DECODE_ID(hw),
5653 PRINT_FLAG_VDEC_STATUS,
5654 "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n",
5655 p_H264_Dpb->dpb_param.l.
5656 data[FIRST_MB_IN_SLICE],
5657 READ_VREG(MBY_MBX),
5658 decode_mb_count);
5659 p->data_flag |= ERROR_FLAG;
5660 } else if (!p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] && decode_mb_count) {
5661 p->data_flag |= ERROR_FLAG;
5662 goto pic_done_proc;
5663 }
5664 }
5665
5666 if (p_H264_Dpb->mVideo.dec_picture->slice_type == I_SLICE) {
5667 hw->new_iframe_flag = 1;
5668 }
5669 if (hw->new_iframe_flag) {
5670 if (p_H264_Dpb->mVideo.dec_picture->slice_type == P_SLICE) {
5671 hw->new_iframe_flag = 0;
5672 hw->ref_err_flush_dpb_flag = 1;
5673 }else if (p_H264_Dpb->mVideo.dec_picture->slice_type == B_SLICE) {
5674 hw->new_iframe_flag = 0;
5675 hw->ref_err_flush_dpb_flag = 0;
5676 }
5677 }
5678
5679 if (error_proc_policy & 0x400) {
5680 int ret = dpb_check_ref_list_error(p_H264_Dpb);
5681 if (ret != 0) {
5682 hw->reflist_error_count ++;
5683 dpb_print(DECODE_ID(hw), 0,
5684 "reference list error %d frame count %d to skip %d reflist_error_count %d\n",
5685 ret,
5686 hw->decode_pic_count+1,
5687 hw->skip_frame_count,
5688 hw->reflist_error_count);
5689
5690 if (hw->ref_err_flush_dpb_flag) {
5691 flush_dpb(p_H264_Dpb);
5692 p_H264_Dpb->colocated_buf_map = 0;
5693 if (p_H264_Dpb->mVideo.dec_picture->colocated_buf_index >= 0) {
5694 p_H264_Dpb->colocated_buf_map |= 1 <<
5695 p_H264_Dpb->mVideo.dec_picture->colocated_buf_index;
5696 }
5697 }
5698
5699 p_H264_Dpb->mVideo.dec_picture->data_flag = NODISP_FLAG;
5700 if (((error_proc_policy & 0x80)
5701 && ((hw->dec_flag &
5702 NODISP_FLAG) == 0)) ||(hw->reflist_error_count > 50)) {
5703 hw->reset_bufmgr_flag = 1;
5704 hw->reflist_error_count =0;
5705 amvdec_stop();
5706 vdec->mc_loaded = 0;
5707 hw->dec_result = DEC_RESULT_DONE;
5708 vdec_schedule_work(&hw->work);
5709 return IRQ_HANDLED;
5710 }
5711 } else
5712 hw->reflist_error_count = 0;
5713 }
5714 if ((error_proc_policy & 0x800)
5715 && p_H264_Dpb->dpb_error_flag != 0) {
5716 dpb_print(DECODE_ID(hw), 0,
5717 "dpb error %d\n",
5718 p_H264_Dpb->dpb_error_flag);
5719 hw->data_flag |= ERROR_FLAG;
5720 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5721 if ((error_proc_policy & 0x80) &&
5722 ((hw->dec_flag & NODISP_FLAG) == 0)) {
5723 hw->reset_bufmgr_flag = 1;
5724 amvdec_stop();
5725 vdec->mc_loaded = 0;
5726 hw->dec_result = DEC_RESULT_DONE;
5727 vdec_schedule_work(&hw->work);
5728 return IRQ_HANDLED;
5729 }
5730 }
5731
5732 cfg_ret = config_decode_buf(hw,
5733 p_H264_Dpb->mVideo.dec_picture);
5734 if (cfg_ret < 0) {
5735 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
5736 "config_decode_buf fail (%d)\n",
5737 cfg_ret);
5738 if (error_proc_policy & 0x2) {
5739 release_cur_decoding_buf(hw);
5740 /*hw->data_flag |= ERROR_FLAG;*/
5741 hw->reset_bufmgr_flag = 1;
5742 hw->dec_result = DEC_RESULT_DONE;
5743 vdec_schedule_work(&hw->work);
5744 return IRQ_HANDLED;
5745 } else
5746 hw->data_flag |= ERROR_FLAG;
5747 p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG;
5748 }
5749 }
5750
5751 if (slice_header_process_status == 1)
5752 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC);
5753 else
5754 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE);
5755 hw->last_mby_mbx = 0;
5756 hw->last_vld_level = 0;
5757 start_process_time(hw);
5758 } else if (dec_dpb_status == H264_PIC_DATA_DONE
5759 ||((dec_dpb_status == H264_DATA_REQUEST) && input_frame_based(vdec))) {
5760pic_done_proc:
5761 reset_process_time(hw);
5762
5763 if (input_frame_based(vdec) &&
5764 frmbase_cont_bitlevel != 0 &&
5765 READ_VREG(VIFF_BIT_CNT) >
5766 frmbase_cont_bitlevel) {
5767 /*handle the case: multi pictures in one packet*/
5768 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5769 "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n",
5770 __func__,
5771 hw->decode_pic_count,
5772 READ_VREG(VIFF_BIT_CNT));
5773 hw->frmbase_cont_flag = 1;
5774 } else
5775 hw->frmbase_cont_flag = 0;
5776
5777 if (p_H264_Dpb->mVideo.dec_picture) {
5778 get_picture_qos_info(p_H264_Dpb->mVideo.dec_picture);
5779#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5780 DEL_EXIST(hw,
5781 p_H264_Dpb->mVideo.dec_picture) = 0;
5782 if (vdec->master) {
5783 struct vdec_h264_hw_s *hw_ba =
5784 (struct vdec_h264_hw_s *)
5785 vdec->master->private;
5786 if (hw_ba->last_dec_picture)
5787 DEL_EXIST(hw_ba,
5788 hw_ba->last_dec_picture)
5789 = 1;
5790 }
5791#endif
5792 mutex_lock(&hw->chunks_mutex);
5793 if (hw->chunk) {
5794 p_H264_Dpb->mVideo.dec_picture->pts =
5795 hw->chunk->pts;
5796 p_H264_Dpb->mVideo.dec_picture->pts64 =
5797 hw->chunk->pts64;
5798 p_H264_Dpb->mVideo.dec_picture->timestamp =
5799 hw->chunk->timestamp;
5800#ifdef MH264_USERDATA_ENABLE
5801 vmh264_udc_fill_vpts(hw,
5802 p_H264_Dpb->mSlice.slice_type,
5803 hw->chunk->pts, 1);
5804#endif
5805
5806#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5807 } else if (vdec->master) {
5808 /*dv enhance layer,
5809 do not checkout pts*/
5810 struct StorablePicture *pic =
5811 p_H264_Dpb->mVideo.dec_picture;
5812 pic->pts = 0;
5813 pic->pts64 = 0;
5814#endif
5815 } else {
5816 struct StorablePicture *pic =
5817 p_H264_Dpb->mVideo.dec_picture;
5818 u32 offset = pic->offset_delimiter;
5819 if (pts_pickout_offset_us64(PTS_TYPE_VIDEO,
5820 offset, &pic->pts, 0, &pic->pts64)) {
5821 pic->pts = 0;
5822 pic->pts64 = 0;
5823#ifdef MH264_USERDATA_ENABLE
5824 vmh264_udc_fill_vpts(hw,
5825 p_H264_Dpb->mSlice.slice_type,
5826 pic->pts, 0);
5827#endif
5828 } else {
5829#ifdef MH264_USERDATA_ENABLE
5830 vmh264_udc_fill_vpts(hw,
5831 p_H264_Dpb->mSlice.slice_type,
5832 pic->pts, 1);
5833#endif
5834 }
5835
5836 }
5837 mutex_unlock(&hw->chunks_mutex);
5838 check_decoded_pic_error(hw);
5839#ifdef ERROR_HANDLE_TEST
5840 if ((hw->data_flag & ERROR_FLAG)
5841 && (error_proc_policy & 0x80)) {
5842 release_cur_decoding_buf(hw);
5843 h264_clear_dpb(hw);
5844 hw->dec_flag = 0;
5845 hw->data_flag = 0;
5846 hw->skip_frame_count = 0;
5847 hw->has_i_frame = 0;
5848 hw->no_error_count = 0xfff;
5849 hw->no_error_i_count = 0xf;
5850 } else
5851#endif
5852 ret = store_picture_in_dpb(p_H264_Dpb,
5853 p_H264_Dpb->mVideo.dec_picture,
5854 hw->data_flag | hw->dec_flag |
5855 p_H264_Dpb->mVideo.dec_picture->data_flag);
5856
5857
5858
5859 if (ret == -1) {
5860 release_cur_decoding_buf(hw);
5861 bufmgr_force_recover(p_H264_Dpb);
5862 } else {
5863 if (hw->data_flag & ERROR_FLAG) {
5864 hw->no_error_count = 0;
5865 hw->no_error_i_count = 0;
5866 } else {
5867 hw->no_error_count++;
5868 if (hw->data_flag & I_FLAG)
5869 hw->no_error_i_count++;
5870 }
5871 if (hw->mmu_enable)
5872 hevc_set_unused_4k_buff_idx(hw,
5873 p_H264_Dpb->mVideo.
5874 dec_picture->buf_spec_num);
5875 bufmgr_post(p_H264_Dpb);
5876 hw->last_dec_picture =
5877 p_H264_Dpb->mVideo.dec_picture;
5878 p_H264_Dpb->mVideo.dec_picture = NULL;
5879 /* dump_dpb(&p_H264_Dpb->mDPB); */
5880 hw->has_i_frame = 1;
5881 if (hw->mmu_enable)
5882 hevc_set_frame_done(hw);
5883 hw->decode_pic_count++;
5884 p_H264_Dpb->decode_pic_count = hw->decode_pic_count;
5885 if (hw->skip_frame_count > 0) {
5886 /*skip n frame after first I */
5887 hw->skip_frame_count--;
5888 if (hw->skip_frame_count == 0)
5889 hw->dec_flag &= (~NODISP_FLAG);
5890 } else if (hw->skip_frame_count < -1) {
5891 /*skip n frame after first I until second I */
5892 hw->skip_frame_count++;
5893 if (hw->skip_frame_count == -1)
5894 hw->dec_flag &= (~NODISP_FLAG);
5895 }
5896 }
5897 }
5898 if (hw->frmbase_cont_flag) {
5899 /*do not DEC_RESULT_GET_DATA*/
5900 hw->get_data_count = 0x7fffffff;
5901 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
5902 decode_frame_count[DECODE_ID(hw)]++;
5903 start_process_time(hw);
5904 return IRQ_HANDLED;
5905 }
5906 amvdec_stop();
5907 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5908 "%s %s decode slice count %d\n",
5909 __func__,
5910 (dec_dpb_status == H264_PIC_DATA_DONE) ?
5911 "H264_PIC_DATA_DONE" :
5912 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ?
5913 "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL",
5914 hw->decode_pic_count);
5915 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */
5916 hw->dec_result = DEC_RESULT_DONE;
5917#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5918 if (vdec->slave &&
5919 dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) {
5920 struct vdec_h264_hw_s *hw_el =
5921 (struct vdec_h264_hw_s *)(vdec->slave->private);
5922 hw_el->got_valid_nal = 0;
5923 hw->switch_dvlayer_flag = 1;
5924 } else if (vdec->master &&
5925 dec_dpb_status == H264_FIND_NEXT_PIC_NAL) {
5926 struct vdec_h264_hw_s *hw_bl =
5927 (struct vdec_h264_hw_s *)(vdec->master->private);
5928 hw_bl->got_valid_nal = 0;
5929 hw->switch_dvlayer_flag = 1;
5930 } else {
5931 hw->switch_dvlayer_flag = 0;
5932 hw->got_valid_nal = 1;
5933 }
5934#endif
5935
5936 hw->dec_result = DEC_RESULT_DONE;
5937 vdec_schedule_work(&hw->work);
5938
5939#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5940 } else if (
5941 (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ||
5942 (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) {
5943 goto pic_done_proc;
5944#endif
5945 } else if (dec_dpb_status == H264_AUX_DATA_READY) {
5946 reset_process_time(hw);
5947 if (READ_VREG(H264_AUX_DATA_SIZE) != 0) {
5948 dma_sync_single_for_cpu(
5949 amports_get_dma_device(),
5950 hw->aux_phy_addr,
5951 hw->prefix_aux_size + hw->suffix_aux_size,
5952 DMA_FROM_DEVICE);
5953 if (dpb_is_debug(DECODE_ID(hw),
5954 PRINT_FLAG_DPB_DETAIL))
5955 dump_aux_buf(hw);
5956#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5957 if (vdec->dolby_meta_with_el || vdec->slave) {
5958 if (hw->last_dec_picture)
5959 set_aux_data(hw, hw->last_dec_picture,
5960 0, 0, NULL);
5961 } else {
5962 if (vdec->master) {
5963 struct vdec_h264_hw_s *hw_bl =
5964 (struct vdec_h264_hw_s *)
5965 (vdec->master->private);
5966 if (hw_bl->last_dec_picture != NULL) {
5967 set_aux_data(hw_bl,
5968 hw_bl->last_dec_picture,
5969 0, 1, hw);
5970 }
5971 set_aux_data(hw,
5972 hw->last_dec_picture,
5973 0, 2, NULL);
5974 }
5975 }
5976#else
5977 if (hw->last_dec_picture)
5978 set_aux_data(hw,
5979 hw->last_dec_picture, 0, 0, NULL);
5980#endif
5981 }
5982#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
5983 hw->switch_dvlayer_flag = 0;
5984 hw->got_valid_nal = 1;
5985#endif
5986 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
5987 "%s H264_AUX_DATA_READY\n", __func__);
5988 hw->dec_result = DEC_RESULT_DONE;
5989 vdec_schedule_work(&hw->work);
5990 } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/
5991 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ||
5992 (dec_dpb_status == H264_DECODE_BUFEMPTY) ||
5993 (dec_dpb_status == H264_DECODE_TIMEOUT)) {
5994empty_proc:
5995 reset_process_time(hw);
5996 if (!hw->frmbase_cont_flag)
5997 release_cur_decoding_buf(hw);
5998
5999 if (input_frame_based(vdec) ||
6000 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) {
6001 if (h264_debug_flag &
6002 DISABLE_ERROR_HANDLE) {
6003 dpb_print(DECODE_ID(hw),
6004 PRINT_FLAG_ERROR,
6005 "%s decoding error, level 0x%x\n",
6006 __func__,
6007 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6008 goto send_again;
6009 }
6010 amvdec_stop();
6011 vdec->mc_loaded = 0;
6012 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6013 "%s %s\n", __func__,
6014 (dec_dpb_status == H264_SEARCH_BUFEMPTY) ?
6015 "H264_SEARCH_BUFEMPTY" :
6016 (dec_dpb_status == H264_DECODE_BUFEMPTY) ?
6017 "H264_DECODE_BUFEMPTY" :
6018 (dec_dpb_status == H264_DECODE_TIMEOUT) ?
6019 "H264_DECODE_TIMEOUT" :
6020 "OTHER");
6021 hw->dec_result = DEC_RESULT_DONE;
6022
6023 if (dec_dpb_status == H264_SEARCH_BUFEMPTY)
6024 hw->search_dataempty_num++;
6025 else if (dec_dpb_status == H264_DECODE_TIMEOUT) {
6026 hw->decode_timeout_num++;
6027 if (error_proc_policy & 0x4000) {
6028 hw->data_flag |= ERROR_FLAG;
6029 if ((p_H264_Dpb->last_dpb_status == H264_DECODE_TIMEOUT) ||
6030 (p_H264_Dpb->last_dpb_status == H264_PIC_DATA_DONE) ||
6031 ((p_H264_Dpb->last_dpb_status == H264_SLICE_HEAD_DONE) &&
6032 (p_H264_Dpb->mSlice.slice_type != B_SLICE))) {
6033 dpb_print(DECODE_ID(hw),
6034 PRINT_FLAG_ERROR, "%s last dpb status 0x%x need bugmgr reset \n",
6035 p_H264_Dpb->last_dpb_status, __func__);
6036 hw->reset_bufmgr_flag = 1;
6037 }
6038 }
6039 } else if (dec_dpb_status == H264_DECODE_BUFEMPTY)
6040 hw->decode_dataempty_num++;
6041 if (!hw->frmbase_cont_flag)
6042 hw->data_flag |= ERROR_FLAG;
6043
6044 vdec_schedule_work(&hw->work);
6045 } else {
6046 /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */
6047 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6048 "%s DEC_RESULT_AGAIN\n", __func__);
6049send_again:
6050 hw->dec_result = DEC_RESULT_AGAIN;
6051 vdec_schedule_work(&hw->work);
6052 }
6053 } else if (dec_dpb_status == H264_DATA_REQUEST) {
6054 reset_process_time(hw);
6055 if (input_frame_based(vdec)) {
6056 dpb_print(DECODE_ID(hw),
6057 PRINT_FLAG_VDEC_STATUS,
6058 "%s H264_DATA_REQUEST (%d)\n",
6059 __func__, hw->get_data_count);
6060 hw->dec_result = DEC_RESULT_GET_DATA;
6061 hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL);
6062 hw->get_data_start_time = jiffies;
6063 hw->get_data_count++;
6064 if (hw->get_data_count >= frame_max_data_packet)
6065 goto empty_proc;
6066 vdec_schedule_work(&hw->work);
6067 } else
6068 goto empty_proc;
6069 } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) {
6070 dpb_print(DECODE_ID(hw), 0,
6071 "vmh264 decode oversize !!\n");
6072 release_cur_decoding_buf(hw);
6073 hw->data_flag |= ERROR_FLAG;
6074 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6075 reset_process_time(hw);
6076 hw->dec_result = DEC_RESULT_DONE;
6077 vdec_schedule_work(&hw->work);
6078 return IRQ_HANDLED;
6079 } else if (dec_dpb_status == H264_SEI_DATA_READY) {
6080 int aux_data_len;
6081 aux_data_len =
6082 (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4;
6083
6084 if (aux_data_len > SEI_DATA_SIZE) {
6085 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6086 "sei data size more than 4K: %d, discarded it\n",
6087 hw->sei_itu_data_len);
6088 hw->sei_itu_data_len = 0;
6089 }
6090
6091 if (aux_data_len != 0) {
6092 u8 *trans_data_buf;
6093 u8 *sei_data_buf;
6094 u8 swap_byte;
6095
6096 dma_sync_single_for_cpu(
6097 amports_get_dma_device(),
6098 hw->aux_phy_addr,
6099 hw->prefix_aux_size + hw->suffix_aux_size,
6100 DMA_FROM_DEVICE);
6101#if 0
6102 dump_aux_buf(hw);
6103#endif
6104 trans_data_buf = (u8 *)hw->aux_addr;
6105
6106 if (trans_data_buf[7] == AUX_TAG_SEI) {
6107 int left_len;
6108
6109 sei_data_buf = (u8 *)hw->sei_data_buf
6110 + hw->sei_data_len;
6111 left_len = SEI_DATA_SIZE - hw->sei_data_len;
6112 if (aux_data_len/2 <= left_len) {
6113 for (i = 0; i < aux_data_len/2; i++)
6114 sei_data_buf[i]
6115 = trans_data_buf[i*2];
6116
6117 aux_data_len = aux_data_len / 2;
6118 for (i = 0; i < aux_data_len; i = i+4) {
6119 swap_byte = sei_data_buf[i];
6120 sei_data_buf[i]
6121 = sei_data_buf[i+3];
6122 sei_data_buf[i+3] = swap_byte;
6123
6124 swap_byte = sei_data_buf[i+1];
6125 sei_data_buf[i+1]
6126 = sei_data_buf[i+2];
6127 sei_data_buf[i+2] = swap_byte;
6128 }
6129
6130 for (i = aux_data_len-1; i >= 0; i--)
6131 if (sei_data_buf[i] != 0)
6132 break;
6133
6134 hw->sei_data_len += i+1;
6135 } else
6136 dpb_print(DECODE_ID(hw),
6137 PRINT_FLAG_ERROR,
6138 "sei data size %d and more than left space: %d, discarded it\n",
6139 hw->sei_itu_data_len,
6140 left_len);
6141 }
6142 }
6143 WRITE_VREG(DPB_STATUS_REG, H264_SEI_DATA_DONE);
6144
6145 return IRQ_HANDLED;
6146 }
6147
6148
6149 /* ucode debug */
6150 debug_tag = READ_VREG(DEBUG_REG1);
6151 if (debug_tag & 0x10000) {
6152 unsigned short *p = (unsigned short *)hw->lmem_addr;
6153
6154 dma_sync_single_for_cpu(
6155 amports_get_dma_device(),
6156 hw->lmem_addr_remap,
6157 PAGE_SIZE,
6158 DMA_FROM_DEVICE);
6159
6160 dpb_print(DECODE_ID(hw), 0,
6161 "LMEM<tag %x>:\n", debug_tag);
6162 for (i = 0; i < 0x400; i += 4) {
6163 int ii;
6164 if ((i & 0xf) == 0)
6165 dpb_print_cont(DECODE_ID(hw), 0,
6166 "%03x: ", i);
6167 for (ii = 0; ii < 4; ii++)
6168 dpb_print_cont(DECODE_ID(hw), 0,
6169 "%04x ", p[i+3-ii]);
6170 if (((i+ii) & 0xf) == 0)
6171 dpb_print_cont(DECODE_ID(hw), 0,
6172 "\n");
6173 }
6174 if (((udebug_pause_pos & 0xffff)
6175 == (debug_tag & 0xffff)) &&
6176 (udebug_pause_decode_idx == 0 ||
6177 udebug_pause_decode_idx ==
6178 hw->decode_pic_count) &&
6179 (udebug_pause_val == 0 ||
6180 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6181 udebug_pause_pos &= 0xffff;
6182 hw->ucode_pause_pos = udebug_pause_pos;
6183 }
6184 else if (debug_tag & 0x20000)
6185 hw->ucode_pause_pos = 0xffffffff;
6186 if (hw->ucode_pause_pos)
6187 reset_process_time(hw);
6188 else
6189 WRITE_VREG(DEBUG_REG1, 0);
6190 } else if (debug_tag != 0) {
6191 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6192 "dbg%x: %x\n", debug_tag,
6193 READ_VREG(DEBUG_REG2));
6194 if (((udebug_pause_pos & 0xffff)
6195 == (debug_tag & 0xffff)) &&
6196 (udebug_pause_decode_idx == 0 ||
6197 udebug_pause_decode_idx ==
6198 hw->decode_pic_count) &&
6199 (udebug_pause_val == 0 ||
6200 udebug_pause_val == READ_VREG(DEBUG_REG2))) {
6201 udebug_pause_pos &= 0xffff;
6202 hw->ucode_pause_pos = udebug_pause_pos;
6203 }
6204 if (hw->ucode_pause_pos)
6205 reset_process_time(hw);
6206 else
6207 WRITE_VREG(DEBUG_REG1, 0);
6208 }
6209 /**/
6210 return IRQ_HANDLED;
6211}
6212
6213static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq)
6214{
6215 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private);
6216 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6217
6218
6219 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6220
6221 if (!hw)
6222 return IRQ_HANDLED;
6223
6224 if (hw->eos)
6225 return IRQ_HANDLED;
6226
6227 p_H264_Dpb->vdec = vdec;
6228 p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG);
6229
6230 dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT,
6231 "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n",
6232 __func__,
6233 p_H264_Dpb->dec_dpb_status,
6234 READ_VREG(ERROR_STATUS_REG),
6235 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
6236 READ_VREG(VLD_MEM_VIFIFO_WP),
6237 READ_VREG(VLD_MEM_VIFIFO_RP),
6238 READ_VREG(VIFF_BIT_CNT),
6239 READ_VREG(MBY_MBX));
6240
6241 if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) {
6242 if (hw->mmu_enable)
6243 hevc_sao_wait_done(hw);
6244 WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE);
6245 return IRQ_HANDLED;
6246 }
6247 return IRQ_WAKE_THREAD;
6248
6249}
6250
6251static void timeout_process(struct vdec_h264_hw_s *hw)
6252{
6253 struct vdec_s *vdec = hw_to_vdec(hw);
6254 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6255
6256 /*
6257 * In this very timeout point,the vh264_work arrives,
6258 * let it to handle the scenario.
6259 */
6260 if (work_pending(&hw->work))
6261 return;
6262
6263 hw->timeout_num++;
6264 amvdec_stop();
6265 vdec->mc_loaded = 0;
6266 if (hw->mmu_enable) {
6267 hevc_set_frame_done(hw);
6268 hevc_sao_wait_done(hw);
6269 }
6270 if (!hw->i_only && (error_proc_policy & 0x2))
6271 flush_dpb(p_H264_Dpb);
6272 dpb_print(DECODE_ID(hw),
6273 PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__);
6274 release_cur_decoding_buf(hw);
6275 hw->dec_result = DEC_RESULT_DONE;
6276 hw->data_flag |= ERROR_FLAG;
6277
6278 if (work_pending(&hw->work))
6279 return;
6280 vdec_schedule_work(&hw->timeout_work);
6281}
6282
6283static void dump_bufspec(struct vdec_h264_hw_s *hw,
6284 const char *caller)
6285{
6286 int i;
6287 dpb_print(DECODE_ID(hw), 0,
6288 "%s in %s:\n", __func__, caller);
6289 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
6290 if (hw->buffer_spec[i].used == -1)
6291 continue;
6292 dpb_print(DECODE_ID(hw), 0,
6293 "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ",
6294 i, hw->buffer_spec[i].used,
6295 hw->buffer_spec[i].buf_adr,
6296 hw->buffer_spec[i].canvas_pos,
6297 hw->buffer_spec[i].vf_ref
6298 );
6299#ifdef CONFIG_AM_VDEC_DV
6300 dpb_print_cont(DECODE_ID(hw), 0,
6301 "dv_el_exist %d",
6302 hw->buffer_spec[i].dv_enhance_exist
6303 );
6304#endif
6305 dpb_print_cont(DECODE_ID(hw), 0, "\n");
6306 }
6307
6308}
6309
6310static void vmh264_dump_state(struct vdec_s *vdec)
6311{
6312 struct vdec_h264_hw_s *hw =
6313 (struct vdec_h264_hw_s *)(vdec->private);
6314 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
6315 dpb_print(DECODE_ID(hw), 0,
6316 "====== %s\n", __func__);
6317 dpb_print(DECODE_ID(hw), 0,
6318 "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d i_only %d send_err %d\n",
6319 hw->frame_width,
6320 hw->frame_height,
6321 hw->dpb.reorder_pic_num,
6322 hw->dpb.mDPB.size,
6323 hw->max_reference_size,
6324 hw->i_only,
6325 hw->send_error_frame_flag
6326 );
6327
6328 dpb_print(DECODE_ID(hw), 0,
6329 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n",
6330 input_frame_based(vdec),
6331 hw->eos,
6332 hw->stat,
6333 hw->dec_result,
6334 decode_frame_count[DECODE_ID(hw)],
6335 display_frame_count[DECODE_ID(hw)],
6336 run_count[DECODE_ID(hw)],
6337 not_run_ready[DECODE_ID(hw)],
6338 input_empty[DECODE_ID(hw)],
6339 hw->reset_bufmgr_count
6340 );
6341
6342 if (vf_get_receiver(vdec->vf_provider_name)) {
6343 enum receviver_start_e state =
6344 vf_notify_receiver(vdec->vf_provider_name,
6345 VFRAME_EVENT_PROVIDER_QUREY_STATE,
6346 NULL);
6347 dpb_print(DECODE_ID(hw), 0,
6348 "\nreceiver(%s) state %d\n",
6349 vdec->vf_provider_name,
6350 state);
6351 }
6352
6353 dpb_print(DECODE_ID(hw), 0,
6354 "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d) fast_output_enable %x\n",
6355 __func__,
6356 kfifo_len(&hw->newframe_q),
6357 VF_POOL_SIZE,
6358 kfifo_len(&hw->display_q),
6359 VF_POOL_SIZE,
6360 hw->vf_pre_count,
6361 hw->vf_get_count,
6362 hw->vf_put_count,
6363 have_free_buf_spec(vdec),
6364 p_H264_Dpb->mDPB.init_done,
6365 p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size,
6366 is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB),
6367 p_H264_Dpb->fast_output_enable
6368 );
6369
6370 dump_dpb(&p_H264_Dpb->mDPB, 1);
6371 dump_pic(p_H264_Dpb);
6372 dump_bufspec(hw, __func__);
6373
6374 dpb_print(DECODE_ID(hw), 0,
6375 "DPB_STATUS_REG=0x%x\n",
6376 READ_VREG(DPB_STATUS_REG));
6377 dpb_print(DECODE_ID(hw), 0,
6378 "MPC_E=0x%x\n",
6379 READ_VREG(MPC_E));
6380 dpb_print(DECODE_ID(hw), 0,
6381 "H264_DECODE_MODE=0x%x\n",
6382 READ_VREG(H264_DECODE_MODE));
6383 dpb_print(DECODE_ID(hw), 0,
6384 "MBY_MBX=0x%x\n",
6385 READ_VREG(MBY_MBX));
6386 dpb_print(DECODE_ID(hw), 0,
6387 "H264_DECODE_SIZE=0x%x\n",
6388 READ_VREG(H264_DECODE_SIZE));
6389 dpb_print(DECODE_ID(hw), 0,
6390 "VIFF_BIT_CNT=0x%x\n",
6391 READ_VREG(VIFF_BIT_CNT));
6392 dpb_print(DECODE_ID(hw), 0,
6393 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
6394 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
6395 dpb_print(DECODE_ID(hw), 0,
6396 "VLD_MEM_VIFIFO_WP=0x%x\n",
6397 READ_VREG(VLD_MEM_VIFIFO_WP));
6398 dpb_print(DECODE_ID(hw), 0,
6399 "VLD_MEM_VIFIFO_RP=0x%x\n",
6400 READ_VREG(VLD_MEM_VIFIFO_RP));
6401 dpb_print(DECODE_ID(hw), 0,
6402 "PARSER_VIDEO_RP=0x%x\n",
6403 READ_PARSER_REG(PARSER_VIDEO_RP));
6404 dpb_print(DECODE_ID(hw), 0,
6405 "PARSER_VIDEO_WP=0x%x\n",
6406 READ_PARSER_REG(PARSER_VIDEO_WP));
6407
6408 if (input_frame_based(vdec) &&
6409 dpb_is_debug(DECODE_ID(hw),
6410 PRINT_FRAMEBASE_DATA)
6411 ) {
6412 int jj;
6413 if (hw->chunk && hw->chunk->block &&
6414 hw->chunk->size > 0) {
6415 u8 *data = NULL;
6416
6417 if (!hw->chunk->block->is_mapped)
6418 data = codec_mm_vmap(hw->chunk->block->start +
6419 hw->chunk->offset, hw->chunk->size);
6420 else
6421 data = ((u8 *)hw->chunk->block->start_virt)
6422 + hw->chunk->offset;
6423
6424 dpb_print(DECODE_ID(hw), 0,
6425 "frame data size 0x%x\n",
6426 hw->chunk->size);
6427 for (jj = 0; jj < hw->chunk->size; jj++) {
6428 if ((jj & 0xf) == 0)
6429 dpb_print(DECODE_ID(hw),
6430 PRINT_FRAMEBASE_DATA,
6431 "%06x:", jj);
6432 dpb_print_cont(DECODE_ID(hw),
6433 PRINT_FRAMEBASE_DATA,
6434 "%02x ", data[jj]);
6435 if (((jj + 1) & 0xf) == 0)
6436 dpb_print_cont(DECODE_ID(hw),
6437 PRINT_FRAMEBASE_DATA,
6438 "\n");
6439 }
6440
6441 if (!hw->chunk->block->is_mapped)
6442 codec_mm_unmap_phyaddr(data);
6443 }
6444 }
6445}
6446
6447
6448static void check_timer_func(unsigned long arg)
6449{
6450 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg;
6451 struct vdec_s *vdec = hw_to_vdec(hw);
6452 int error_skip_frame_count = error_skip_count & 0xfff;
6453 unsigned int timeout_val = decode_timeout_val;
6454 if (timeout_val != 0 &&
6455 hw->no_error_count < error_skip_frame_count)
6456 timeout_val = errordata_timeout_val;
6457 if ((h264_debug_cmd & 0x100) != 0 &&
6458 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6459 hw->dec_result = DEC_RESULT_DONE;
6460 vdec_schedule_work(&hw->work);
6461 pr_info("vdec %d is forced to be disconnected\n",
6462 h264_debug_cmd & 0xff);
6463 h264_debug_cmd = 0;
6464 return;
6465 }
6466 if ((h264_debug_cmd & 0x200) != 0 &&
6467 DECODE_ID(hw) == (h264_debug_cmd & 0xff)) {
6468 pr_debug("vdec %d is forced to reset bufmgr\n",
6469 h264_debug_cmd & 0xff);
6470 hw->reset_bufmgr_flag = 1;
6471 h264_debug_cmd = 0;
6472 return;
6473 }
6474
6475 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
6476 hw->dec_result = DEC_RESULT_FORCE_EXIT;
6477 vdec_schedule_work(&hw->work);
6478 pr_debug("vdec requested to be disconnected\n");
6479 return;
6480 }
6481
6482 if (radr != 0) {
6483 if (rval != 0) {
6484 WRITE_VREG(radr, rval);
6485 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
6486 } else
6487 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
6488 rval = 0;
6489 radr = 0;
6490 }
6491
6492 if ((input_frame_based(vdec) ||
6493 (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) &&
6494 ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) &&
6495 (timeout_val > 0) &&
6496 (hw->start_process_time > 0) &&
6497 ((1000 * (jiffies - hw->start_process_time) / HZ)
6498 > timeout_val)
6499 ) {
6500 u32 dpb_status = READ_VREG(DPB_STATUS_REG);
6501 u32 mby_mbx = READ_VREG(MBY_MBX);
6502 if ((dpb_status == H264_ACTION_DECODE_NEWPIC) ||
6503 (dpb_status == H264_ACTION_DECODE_SLICE)) {
6504 if (hw->last_mby_mbx == mby_mbx) {
6505 if (hw->decode_timeout_count > 0)
6506 hw->decode_timeout_count--;
6507 if (hw->decode_timeout_count == 0)
6508 {
6509 reset_process_time(hw);
6510 timeout_process(hw);
6511 }
6512 } else
6513 start_process_time(hw);
6514 } else if (is_in_parsing_state(dpb_status)) {
6515 if (hw->last_vld_level ==
6516 READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
6517 if (hw->decode_timeout_count > 0)
6518 hw->decode_timeout_count--;
6519 if (hw->decode_timeout_count == 0)
6520 {
6521 reset_process_time(hw);
6522 timeout_process(hw);
6523 }
6524 }
6525 }
6526 hw->last_vld_level =
6527 READ_VREG(VLD_MEM_VIFIFO_LEVEL);
6528 hw->last_mby_mbx = mby_mbx;
6529 }
6530
6531 if ((hw->ucode_pause_pos != 0) &&
6532 (hw->ucode_pause_pos != 0xffffffff) &&
6533 udebug_pause_pos != hw->ucode_pause_pos) {
6534 hw->ucode_pause_pos = 0;
6535 WRITE_VREG(DEBUG_REG1, 0);
6536 }
6537
6538 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
6539}
6540
6541static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
6542{
6543 u32 ar;
6544 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
6545
6546 if (!hw)
6547 return -1;
6548
6549 vstatus->frame_width = hw->frame_width;
6550 vstatus->frame_height = hw->frame_height;
6551 if (hw->frame_dur != 0)
6552 vstatus->frame_rate = 96000 / hw->frame_dur;
6553 else
6554 vstatus->frame_rate = -1;
6555 vstatus->error_count = 0;
6556 vstatus->status = hw->stat;
6557 if (hw->h264_ar == 0x3ff)
6558 hw->h264_ar = (0x100 *
6559 hw->frame_height * hw->height_aspect_ratio) /
6560 (hw->frame_width * hw->width_aspect_ratio);
6561 ar = min_t(u32,
6562 hw->h264_ar,
6563 DISP_RATIO_ASPECT_RATIO_MAX);
6564 vstatus->ratio_control =
6565 ar << DISP_RATIO_ASPECT_RATIO_BIT;
6566
6567 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
6568 "%s-%02d", DRIVER_NAME, hw->id);
6569
6570 return 0;
6571}
6572
6573static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw)
6574{
6575 int i, j;
6576 struct aml_vcodec_ctx * v4l2_ctx = hw->v4l2_ctx;
6577
6578 /* if (hw->init_flag == 0) { */
6579 if (h264_debug_flag & 0x40000000) {
6580 /* if (1) */
6581 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
6582 "%s, reset register\n", __func__);
6583
6584 while (READ_VREG(DCAC_DMA_CTRL) & 0x8000)
6585 ;
6586 while (READ_VREG(LMEM_DMA_CTRL) & 0x8000)
6587 ; /* reg address is 0x350 */
6588
6589#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
6590 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6591 WRITE_VREG(DOS_SW_RESET0, 0);
6592
6593 READ_VREG(DOS_SW_RESET0);
6594 READ_VREG(DOS_SW_RESET0);
6595 READ_VREG(DOS_SW_RESET0);
6596
6597 WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4));
6598 WRITE_VREG(DOS_SW_RESET0, 0);
6599
6600 WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8));
6601 WRITE_VREG(DOS_SW_RESET0, 0);
6602
6603 READ_VREG(DOS_SW_RESET0);
6604 READ_VREG(DOS_SW_RESET0);
6605 READ_VREG(DOS_SW_RESET0);
6606
6607#else
6608 WRITE_RESET_REG(RESET0_REGISTER,
6609 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6610 READ_RESET_REG(RESET0_REGISTER);
6611 WRITE_RESET_REG(RESET0_REGISTER,
6612 RESET_IQIDCT | RESET_MC | RESET_VLD_PART);
6613
6614 WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK);
6615#endif
6616 WRITE_VREG(POWER_CTL_VLD,
6617 READ_VREG(POWER_CTL_VLD) | (0 << 10) |
6618 (1 << 9) | (1 << 6));
6619 } else {
6620 /* WRITE_VREG(POWER_CTL_VLD,
6621 * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) );
6622 */
6623 WRITE_VREG(POWER_CTL_VLD,
6624 READ_VREG(POWER_CTL_VLD) |
6625 (0 << 10) | (1 << 9) | (1 << 6));
6626 }
6627 /* disable PSCALE for hardware sharing */
6628 WRITE_VREG(PSCALE_CTRL, 0);
6629
6630 /* clear mailbox interrupt */
6631 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
6632
6633 /* enable mailbox interrupt */
6634 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
6635
6636#ifdef NV21
6637 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17);
6638#endif
6639
6640 /* cbcr_merge_swap_en */
6641 if (hw->is_used_v4l
6642 && (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21
6643 || v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
6644 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 16);
6645
6646 SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6647 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24);
6648
6649 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
6650 if (hw->mmu_enable) {
6651 SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31);
6652 /* sw reset to extif hardware */
6653 SET_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6654 CLEAR_VREG_MASK(MDEC_EXTIF_CFG1, 1<<30);
6655 } else {
6656 CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31);
6657 WRITE_VREG(MDEC_EXTIF_CFG1, 0);
6658 }
6659
6660
6661#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6662 /* pr_info("vh264 meson8 prot init\n"); */
6663 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6664#endif
6665
6666#ifdef VDEC_DW
6667 if (IS_VDEC_DW(hw)) {
6668 u32 data = ((1 << 30) |(1 << 0) |(1 << 8));
6669
6670 if (IS_VDEC_DW(hw) == 2)
6671 data |= (1 << 9);
6672 WRITE_VREG(MDEC_DOUBLEW_CFG0, data); /* Double Write Enable*/
6673 }
6674#endif
6675 if (hw->dpb.mDPB.size > 0) {
6676 WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) |
6677 (hw->dpb.mDPB.size << 16) |
6678 (hw->dpb.mDPB.size << 8));
6679
6680 for (j = 0; j < hw->dpb.mDPB.size; j++) {
6681 i = get_buf_spec_by_canvas_pos(hw, j);
6682 if (i < 0)
6683 break;
6684
6685 if (!hw->mmu_enable &&
6686 hw->buffer_spec[i].cma_alloc_addr)
6687 config_decode_canvas(hw, i);
6688 if (hw->mmu_enable && hw->double_write_mode)
6689 config_decode_canvas_ex(hw, i);
6690 }
6691 } else {
6692 WRITE_VREG(AV_SCRATCH_0, 0);
6693 WRITE_VREG(AV_SCRATCH_9, 0);
6694 }
6695
6696 if (hw->init_flag == 0)
6697 WRITE_VREG(DPB_STATUS_REG, 0);
6698 else
6699 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START);
6700
6701 WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count);
6702 WRITE_VREG(AV_SCRATCH_8, hw->buf_offset);
6703 if (!tee_enabled())
6704 WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle);
6705
6706 /* hw->error_recovery_mode = (error_recovery_mode != 0) ?
6707 * error_recovery_mode : error_recovery_mode_in;
6708 */
6709 /* WRITE_VREG(AV_SCRATCH_F,
6710 * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) );
6711 */
6712 WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) |
6713 ((error_recovery_mode_in & 0x1) << 4));
6714 /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM)
6715 SET_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6716 else*/
6717 CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6);
6718
6719 WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap);
6720#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */
6721 WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa);
6722#endif
6723
6724 WRITE_VREG(DEBUG_REG1, 0);
6725 WRITE_VREG(DEBUG_REG2, 0);
6726
6727 if (hw->reg_iqidct_control)
6728 WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control);
6729 if (hw->reg_vcop_ctrl_reg)
6730 WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg);
6731 if (hw->vld_dec_control)
6732 WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control);
6733 return 0;
6734}
6735
6736static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode)
6737{
6738 struct vdec_h264_hw_s *hw =
6739 (struct vdec_h264_hw_s *)vdec->private;
6740 if (i_only_flag & 0x100)
6741 return 0;
6742 if (trickmode == TRICKMODE_I)
6743 hw->i_only = 0x3;
6744 else if (trickmode == TRICKMODE_NONE)
6745 hw->i_only = 0x0;
6746 return 0;
6747}
6748
6749static unsigned char amvdec_enable_flag;
6750static void vh264_local_init(struct vdec_h264_hw_s *hw)
6751{
6752 int i;
6753 hw->init_flag = 0;
6754 hw->first_sc_checked= 0;
6755 hw->eos = 0;
6756 hw->valve_count = 0;
6757 hw->config_bufmgr_done = 0;
6758 hw->start_process_time = 0;
6759 hw->has_i_frame = 0;
6760 hw->no_error_count = 0xfff;
6761 hw->no_error_i_count = 0xf;
6762
6763 hw->dec_flag = 0;
6764 hw->data_flag = 0;
6765 hw->skip_frame_count = 0;
6766 hw->reg_iqidct_control = 0;
6767 hw->reg_vcop_ctrl_reg = 0;
6768 hw->reg_rv_ai_mb_count = 0;
6769 hw->vld_dec_control = 0;
6770 hw->decode_timeout_count = 0;
6771 hw->no_mem_count = 0;
6772 hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio;
6773 /* vh264_ratio = 0x100; */
6774
6775 hw->vh264_rotation = (((unsigned long)
6776 hw->vh264_amstream_dec_info.param) >> 16) & 0xffff;
6777
6778 hw->frame_prog = 0;
6779 hw->frame_width = hw->vh264_amstream_dec_info.width;
6780 hw->frame_height = hw->vh264_amstream_dec_info.height;
6781 hw->frame_dur = hw->vh264_amstream_dec_info.rate;
6782 hw->pts_outside = ((unsigned long)
6783 hw->vh264_amstream_dec_info.param) & 0x01;
6784 hw->sync_outside = ((unsigned long)
6785 hw->vh264_amstream_dec_info.param & 0x02) >> 1;
6786 hw->use_idr_framerate = ((unsigned long)
6787 hw->vh264_amstream_dec_info.param & 0x04) >> 2;
6788 hw->max_refer_buf = !(((unsigned long)
6789 hw->vh264_amstream_dec_info.param & 0x10) >> 4);
6790 if (hw->frame_dur < 96000/960) {
6791 /*more than 960fps,it should not be a correct value,
6792 *give default 30fps
6793 */
6794 hw->frame_dur = 96000/30;
6795 }
6796
6797 hw->unstable_pts = (((unsigned long) hw->vh264_amstream_dec_info.param & 0x40) >> 6);
6798
6799 hw->first_i_policy = first_i_policy;
6800
6801 if (hw->is_used_v4l)
6802 mem_map_mode = CANVAS_BLKMODE_LINEAR;
6803
6804 pr_info("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n",
6805 hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside);
6806 pr_debug("sync_outside=%d, use_idr_framerate=%d, is_used_v4l: %d\n",
6807 hw->sync_outside, hw->use_idr_framerate, hw->is_used_v4l);
6808
6809 if (i_only_flag & 0x100)
6810 hw->i_only = i_only_flag & 0xff;
6811 if (hw->i_only)
6812 hw->dpb.first_insert_frame = FirstInsertFrm_SKIPDONE;
6813
6814 if ((unsigned long) hw->vh264_amstream_dec_info.param
6815 & 0x08)
6816 hw->no_poc_reorder_flag = 1;
6817
6818 error_recovery_mode_in = 1; /*ucode control?*/
6819 if (error_proc_policy & 0x80000000)
6820 hw->send_error_frame_flag = error_proc_policy & 0x1;
6821 else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20)
6822 hw->send_error_frame_flag = 0; /*Don't display mark err frames*/
6823
6824 INIT_KFIFO(hw->display_q);
6825 INIT_KFIFO(hw->newframe_q);
6826
6827 for (i = 0; i < VF_POOL_SIZE; i++) {
6828 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
6829 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
6830 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
6831 kfifo_put(&hw->newframe_q, vf);
6832 }
6833
6834 hw->duration_from_pts_done = 0;
6835
6836 hw->p_last_vf = NULL;
6837 hw->vh264_stream_switching_state = SWITCHING_STATE_OFF;
6838 hw->hevc_cur_buf_idx = 0xffff;
6839
6840 init_waitqueue_head(&hw->wait_q);
6841
6842 return;
6843}
6844
6845static s32 vh264_init(struct vdec_h264_hw_s *hw)
6846{
6847 int size = -1;
6848 int fw_size = 0x1000 * 16;
6849 int fw_mmu_size = 0x1000 * 16;
6850 struct firmware_s *fw = NULL, *fw_mmu = NULL;
6851
6852 /* int trickmode_fffb = 0; */
6853
6854 /* pr_info("\nvh264_init\n"); */
6855 /* init_timer(&hw->recycle_timer); */
6856
6857 /* timer init */
6858 init_timer(&hw->check_timer);
6859
6860 hw->check_timer.data = (unsigned long)hw;
6861 hw->check_timer.function = check_timer_func;
6862 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
6863
6864 /* add_timer(&hw->check_timer); */
6865 hw->stat |= STAT_TIMER_ARM;
6866 hw->stat |= STAT_ISR_REG;
6867
6868 mutex_init(&hw->chunks_mutex);
6869 vh264_local_init(hw);
6870 INIT_WORK(&hw->work, vh264_work);
6871 INIT_WORK(&hw->notify_work, vh264_notify_work);
6872 INIT_WORK(&hw->timeout_work, vh264_timeout_work);
6873#ifdef MH264_USERDATA_ENABLE
6874 INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work);
6875#endif
6876
6877 if (!amvdec_enable_flag) {
6878 amvdec_enable_flag = true;
6879 amvdec_enable();
6880 if (hw->mmu_enable)
6881 amhevc_enable();
6882 }
6883 if (hw->mmu_enable) {
6884
6885 hw->frame_mmu_map_addr =
6886 dma_alloc_coherent(amports_get_dma_device(),
6887 FRAME_MMU_MAP_SIZE,
6888 &hw->frame_mmu_map_phy_addr, GFP_KERNEL);
6889 if (hw->frame_mmu_map_addr == NULL) {
6890 pr_err("%s: failed to alloc count_buffer\n", __func__);
6891 return -ENOMEM;
6892 }
6893 }
6894
6895 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
6896 if (IS_ERR_OR_NULL(fw))
6897 return -ENOMEM;
6898
6899 size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data);
6900 if (size < 0) {
6901 pr_err("get firmware fail.\n");
6902 vfree(fw);
6903 return -1;
6904 }
6905
6906 fw->len = size;
6907 hw->fw = fw;
6908
6909 if (hw->mmu_enable) {
6910 fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size);
6911 if (IS_ERR_OR_NULL(fw_mmu))
6912 return -ENOMEM;
6913
6914 size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, fw_mmu->data);
6915 if (size < 0) {
6916 pr_err("get mmu fw fail.\n");
6917 vfree(fw_mmu);
6918 return -1;
6919 }
6920
6921 fw_mmu->len = size;
6922 hw->fw_mmu = fw_mmu;
6923 }
6924
6925 if (!tee_enabled()) {
6926 /* -- ucode loading (amrisc and swap code) */
6927 hw->mc_cpu_addr =
6928 dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE,
6929 &hw->mc_dma_handle, GFP_KERNEL);
6930 if (!hw->mc_cpu_addr) {
6931 amvdec_enable_flag = false;
6932 amvdec_disable();
6933 if (hw->mmu_enable)
6934 amhevc_disable();
6935 pr_info("vh264_init: Can not allocate mc memory.\n");
6936 return -ENOMEM;
6937 }
6938
6939 /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n",
6940 (void *)hw->mc_dma_handle, hw->mc_cpu_addr);
6941 */
6942
6943 /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/
6944
6945 /*header*/
6946 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER,
6947 fw->data + 0x4000, MC_SWAP_SIZE);
6948 /*data*/
6949 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA,
6950 fw->data + 0x2000, MC_SWAP_SIZE);
6951 /*mmco*/
6952 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO,
6953 fw->data + 0x6000, MC_SWAP_SIZE);
6954 /*list*/
6955 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST,
6956 fw->data + 0x3000, MC_SWAP_SIZE);
6957 /*slice*/
6958 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE,
6959 fw->data + 0x5000, MC_SWAP_SIZE);
6960 /*main*/
6961 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN,
6962 fw->data, 0x2000);
6963 /*data*/
6964 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000,
6965 fw->data + 0x2000, 0x1000);
6966 /*slice*/
6967 memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000,
6968 fw->data + 0x5000, 0x1000);
6969 }
6970
6971#if 1 /* #ifdef BUFFER_MGR_IN_C */
6972 hw->lmem_addr = __get_free_page(GFP_KERNEL);
6973 if (!hw->lmem_addr) {
6974 pr_info("%s: failed to alloc lmem_addr\n", __func__);
6975 return -ENOMEM;
6976 } else {
6977 hw->lmem_addr_remap = dma_map_single(
6978 amports_get_dma_device(),
6979 (void *)hw->lmem_addr,
6980 PAGE_SIZE, DMA_FROM_DEVICE);
6981 if (dma_mapping_error(amports_get_dma_device(),
6982 hw->lmem_addr_remap)) {
6983 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
6984 "%s: failed to map lmem_addr\n", __func__);
6985 free_page(hw->lmem_addr);
6986 hw->lmem_addr = 0;
6987 hw->lmem_addr_remap = 0;
6988 return -ENOMEM;
6989 }
6990
6991 pr_debug("%s, vaddr=%lx phy_addr=%p\n",
6992 __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap);
6993 }
6994
6995 if (prefix_aux_buf_size > 0 ||
6996 suffix_aux_buf_size > 0) {
6997 u32 aux_buf_size;
6998 hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
6999 hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7000 aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size;
7001 hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL);
7002 if (hw->aux_addr == NULL) {
7003 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7004 return -1;
7005 }
7006
7007 hw->aux_phy_addr = dma_map_single(amports_get_dma_device(),
7008 hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE);
7009 if (dma_mapping_error(amports_get_dma_device(),
7010 hw->aux_phy_addr)) {
7011 pr_err("%s: failed to map rpm buffer\n", __func__);
7012 kfree(hw->aux_addr);
7013 hw->aux_addr = NULL;
7014 return -1;
7015 }
7016 hw->sei_data_buf = kmalloc(SEI_DATA_SIZE, GFP_KERNEL);
7017 if (hw->sei_data_buf == NULL) {
7018 pr_err("%s: failed to alloc sei itu data buffer\n",
7019 __func__);
7020 return -1;
7021 }
7022 hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL);
7023 if (hw->sei_itu_data_buf == NULL) {
7024 pr_err("%s: failed to alloc sei itu data buffer\n",
7025 __func__);
7026 kfree(hw->aux_addr);
7027 hw->aux_addr = NULL;
7028 kfree(hw->sei_data_buf);
7029 hw->sei_data_buf = NULL;
7030
7031 return -1;
7032 }
7033
7034 if (NULL == hw->sei_user_data_buffer) {
7035 hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE,
7036 GFP_KERNEL);
7037 if (!hw->sei_user_data_buffer) {
7038 pr_info("%s: Can not allocate sei_data_buffer\n",
7039 __func__);
7040 kfree(hw->aux_addr);
7041 hw->aux_addr = NULL;
7042 kfree(hw->sei_data_buf);
7043 hw->sei_data_buf = NULL;
7044 kfree(hw->sei_itu_data_buf);
7045 hw->sei_itu_data_buf = NULL;
7046
7047 return -1;
7048 }
7049 hw->sei_user_data_wp = 0;
7050 }
7051 }
7052/* BUFFER_MGR_IN_C */
7053#endif
7054 hw->stat |= STAT_MC_LOAD;
7055
7056 /* add memory barrier */
7057 wmb();
7058
7059 return 0;
7060}
7061
7062static int vh264_stop(struct vdec_h264_hw_s *hw)
7063{
7064 if (hw->stat & STAT_VDEC_RUN) {
7065 amvdec_stop();
7066 hw->stat &= ~STAT_VDEC_RUN;
7067 }
7068#ifdef VDEC_DW
7069 WRITE_VREG(MDEC_DOUBLEW_CFG0, 0);
7070#endif
7071#ifdef MH264_USERDATA_ENABLE
7072 cancel_work_sync(&hw->user_data_ready_work);
7073#endif
7074 cancel_work_sync(&hw->notify_work);
7075 cancel_work_sync(&hw->timeout_work);
7076 cancel_work_sync(&hw->work);
7077
7078
7079 if (hw->stat & STAT_MC_LOAD) {
7080 if (hw->mc_cpu_addr != NULL) {
7081 dma_free_coherent(amports_get_dma_device(),
7082 MC_TOTAL_SIZE, hw->mc_cpu_addr,
7083 hw->mc_dma_handle);
7084 hw->mc_cpu_addr = NULL;
7085 }
7086 if (hw->frame_mmu_map_addr != NULL) {
7087 dma_free_coherent(amports_get_dma_device(),
7088 FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr,
7089 hw->frame_mmu_map_phy_addr);
7090 hw->frame_mmu_map_addr = NULL;
7091 }
7092
7093 }
7094 if (hw->stat & STAT_ISR_REG) {
7095 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
7096 hw->stat &= ~STAT_ISR_REG;
7097 }
7098 if (hw->lmem_addr_remap) {
7099 dma_unmap_single(amports_get_dma_device(),
7100 hw->lmem_addr_remap,
7101 PAGE_SIZE, DMA_FROM_DEVICE);
7102 hw->lmem_addr_remap = 0;
7103 }
7104 if (hw->lmem_addr) {
7105 free_page(hw->lmem_addr);
7106 hw->lmem_addr = 0;
7107 }
7108 if (hw->aux_addr) {
7109 dma_unmap_single(amports_get_dma_device(),
7110 hw->aux_phy_addr,
7111 hw->prefix_aux_size + hw->suffix_aux_size,
7112 DMA_FROM_DEVICE);
7113 kfree(hw->aux_addr);
7114 hw->aux_addr = NULL;
7115 }
7116 if (hw->sei_data_buf != NULL) {
7117 kfree(hw->sei_data_buf);
7118 hw->sei_data_buf = NULL;
7119 }
7120 if (hw->sei_itu_data_buf != NULL) {
7121 kfree(hw->sei_itu_data_buf);
7122 hw->sei_itu_data_buf = NULL;
7123 }
7124 if (hw->sei_user_data_buffer != NULL) {
7125 kfree(hw->sei_user_data_buffer);
7126 hw->sei_user_data_buffer = NULL;
7127 }
7128 /* amvdec_disable(); */
7129
7130 vfree(hw->fw);
7131 hw->fw = NULL;
7132
7133 if (hw->mmu_enable) {
7134 vfree(hw->fw_mmu);
7135 hw->fw_mmu = NULL;
7136 }
7137
7138 dpb_print(DECODE_ID(hw), 0,
7139 "%s\n",
7140 __func__);
7141 return 0;
7142}
7143
7144static void wait_vmh264_search_done(struct vdec_h264_hw_s *hw)
7145{
7146 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7147 int count = 0;
7148 do {
7149 usleep_range(100, 500);
7150 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
7151 break;
7152 if (count > 2000) {
7153 dpb_print(DECODE_ID(hw),
7154 PRINT_FLAG_ERROR, "%s timeout count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
7155 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
7156 break;
7157 } else
7158 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
7159 count++;
7160 } while (1);
7161}
7162
7163static void vh264_notify_work(struct work_struct *work)
7164{
7165 struct vdec_h264_hw_s *hw = container_of(work,
7166 struct vdec_h264_hw_s, notify_work);
7167 struct vdec_s *vdec = hw_to_vdec(hw);
7168 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
7169 vf_notify_receiver(vdec->vf_provider_name,
7170 VFRAME_EVENT_PROVIDER_FR_HINT,
7171 (void *)((unsigned long)hw->frame_dur));
7172 vdec->fr_hint_state = VDEC_HINTED;
7173 }
7174
7175 return;
7176}
7177
7178#ifdef MH264_USERDATA_ENABLE
7179static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw)
7180{
7181 hw->wait_for_udr_send = 0;
7182 hw->sei_itu_data_len = 0;
7183 memset(&hw->ud_record, 0, sizeof(hw->ud_record));
7184}
7185
7186static void vmh264_crate_userdata_manager(
7187 struct vdec_h264_hw_s *hw,
7188 u8 *userdata_buf,
7189 int buf_len)
7190{
7191 if (hw) {
7192
7193
7194 mutex_init(&hw->userdata_mutex);
7195
7196 memset(&hw->userdata_info, 0,
7197 sizeof(struct mh264_userdata_info_t));
7198 hw->userdata_info.data_buf = userdata_buf;
7199 hw->userdata_info.buf_len = buf_len;
7200 hw->userdata_info.data_buf_end = userdata_buf + buf_len;
7201
7202 vmh264_reset_udr_mgr(hw);
7203
7204 }
7205}
7206
7207static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw)
7208{
7209 if (hw)
7210 memset(&hw->userdata_info,
7211 0,
7212 sizeof(struct mh264_userdata_info_t));
7213}
7214
7215/*
7216#define DUMP_USERDATA_RECORD
7217*/
7218#ifdef DUMP_USERDATA_RECORD
7219
7220#define MAX_USER_DATA_SIZE 3145728
7221static void *user_data_buf;
7222static unsigned char *pbuf_start;
7223static int total_len;
7224static int bskip;
7225static int n_userdata_id;
7226
7227static void print_data(unsigned char *pdata,
7228 int len,
7229 unsigned int poc_number,
7230 unsigned int flag,
7231 unsigned int duration,
7232 unsigned int vpts,
7233 unsigned int vpts_valid,
7234 int rec_id)
7235{
7236 int nLeft;
7237
7238 nLeft = len;
7239#if 0
7240 pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n",
7241 rec_id, len, flag,
7242 duration, vpts, vpts_valid, poc_number);
7243#endif
7244 pr_info("%d len = %d, flag = %d, vpts = 0x%x\n",
7245 rec_id, len, flag, vpts);
7246
7247 if (len == 96) {
7248 int i;
7249 nLeft = 72;
7250 while (nLeft >= 16) {
7251 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7252 pdata[0], pdata[1], pdata[2], pdata[3],
7253 pdata[4], pdata[5], pdata[6], pdata[7],
7254 pdata[8], pdata[9], pdata[10], pdata[11],
7255 pdata[12], pdata[13], pdata[14], pdata[15]);
7256 nLeft -= 16;
7257 pdata += 16;
7258 }
7259
7260
7261 while (nLeft > 0) {
7262 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7263 pdata[0], pdata[1], pdata[2], pdata[3],
7264 pdata[4], pdata[5], pdata[6], pdata[7]);
7265 nLeft -= 8;
7266 pdata += 8;
7267 }
7268
7269 i = 0;
7270 nLeft = 96-72;
7271 while (i < nLeft) {
7272 if (pdata[0] != 0) {
7273 pr_info("some data error\n");
7274 break;
7275 }
7276 pdata++;
7277 i++;
7278 }
7279 } else {
7280 while (nLeft >= 16) {
7281 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
7282 pdata[0], pdata[1], pdata[2], pdata[3],
7283 pdata[4], pdata[5], pdata[6], pdata[7],
7284 pdata[8], pdata[9], pdata[10], pdata[11],
7285 pdata[12], pdata[13], pdata[14], pdata[15]);
7286 nLeft -= 16;
7287 pdata += 16;
7288 }
7289
7290
7291 while (nLeft > 0) {
7292 pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
7293 pdata[0], pdata[1], pdata[2], pdata[3],
7294 pdata[4], pdata[5], pdata[6], pdata[7]);
7295 nLeft -= 8;
7296 pdata += 8;
7297 }
7298
7299 }
7300}
7301
7302static void push_to_buf(struct vdec_h264_hw_s *hw,
7303 u8 *pdata,
7304 int len,
7305 struct userdata_meta_info_t *pmeta);
7306
7307static void dump_userdata_record(struct vdec_h264_hw_s *hw,
7308 struct mh264_userdata_record_t *record)
7309{
7310 if (record && hw) {
7311 u8 *pdata;
7312
7313 pdata = hw->userdata_info.data_buf + record->rec_start;
7314/*
7315 print_data(pdata,
7316 record->rec_len,
7317 record->meta_info.flags,
7318 record->meta_info.duration,
7319 record->meta_info.vpts,
7320 record->meta_info.vpts_valid,
7321 n_record_id);
7322*/
7323 push_to_buf(hw, pdata, record->rec_len, &record->meta_info);
7324 n_userdata_id++;
7325 }
7326}
7327
7328
7329static void push_to_buf(struct vdec_h264_hw_s *hw,
7330 u8 *pdata, int len,
7331 struct userdata_meta_info_t *pmeta)
7332{
7333 u32 *pLen;
7334 int info_cnt;
7335 u8 *pbuf_end;
7336
7337 if (!user_data_buf)
7338 return;
7339
7340 if (bskip) {
7341 pr_info("over size, skip\n");
7342 return;
7343 }
7344 info_cnt = 0;
7345 pLen = (u32 *)pbuf_start;
7346
7347 *pLen = len;
7348 pbuf_start += sizeof(u32);
7349 info_cnt++;
7350 pLen++;
7351
7352 *pLen = pmeta->poc_number;
7353 pbuf_start += sizeof(u32);
7354 info_cnt++;
7355 pLen++;
7356
7357 *pLen = pmeta->duration;
7358 pbuf_start += sizeof(u32);
7359 info_cnt++;
7360 pLen++;
7361
7362 *pLen = pmeta->flags;
7363 pbuf_start += sizeof(u32);
7364 info_cnt++;
7365 pLen++;
7366
7367 *pLen = pmeta->vpts;
7368 pbuf_start += sizeof(u32);
7369 info_cnt++;
7370 pLen++;
7371
7372 *pLen = pmeta->vpts_valid;
7373 pbuf_start += sizeof(u32);
7374 info_cnt++;
7375 pLen++;
7376
7377
7378 *pLen = n_userdata_id;
7379 pbuf_start += sizeof(u32);
7380 info_cnt++;
7381 pLen++;
7382
7383
7384
7385 pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7386 if (pdata + len > pbuf_end) {
7387 int first_section_len;
7388
7389 first_section_len = pbuf_end - pdata;
7390 memcpy(pbuf_start, pdata, first_section_len);
7391 pdata = (u8 *)hw->sei_user_data_buffer;
7392 pbuf_start += first_section_len;
7393 memcpy(pbuf_start, pdata, len - first_section_len);
7394 pbuf_start += len - first_section_len;
7395 } else {
7396 memcpy(pbuf_start, pdata, len);
7397 pbuf_start += len;
7398 }
7399
7400 total_len += len + info_cnt * sizeof(u32);
7401 if (total_len >= MAX_USER_DATA_SIZE-4096)
7402 bskip = 1;
7403}
7404
7405static void show_user_data_buf(void)
7406{
7407 u8 *pbuf;
7408 int len;
7409 unsigned int flag;
7410 unsigned int duration;
7411 unsigned int vpts;
7412 unsigned int vpts_valid;
7413 unsigned int poc_number;
7414 int rec_id;
7415
7416 pr_info("show user data buf\n");
7417 pbuf = user_data_buf;
7418
7419 while (pbuf < pbuf_start) {
7420 u32 *pLen;
7421
7422 pLen = (u32 *)pbuf;
7423
7424 len = *pLen;
7425 pLen++;
7426 pbuf += sizeof(u32);
7427
7428 poc_number = *pLen;
7429 pLen++;
7430 pbuf += sizeof(u32);
7431
7432 duration = *pLen;
7433 pLen++;
7434 pbuf += sizeof(u32);
7435
7436 flag = *pLen;
7437 pLen++;
7438 pbuf += sizeof(u32);
7439
7440 vpts = *pLen;
7441 pLen++;
7442 pbuf += sizeof(u32);
7443
7444 vpts_valid = *pLen;
7445 pLen++;
7446 pbuf += sizeof(u32);
7447
7448 rec_id = *pLen;
7449 pLen++;
7450 pbuf += sizeof(u32);
7451
7452 print_data(pbuf, len, poc_number, flag,
7453 duration, vpts,
7454 vpts_valid, rec_id);
7455 pbuf += len;
7456 msleep(30);
7457 }
7458}
7459
7460static int vmh264_init_userdata_dump(void)
7461{
7462 user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL);
7463 if (user_data_buf)
7464 return 1;
7465 else
7466 return 0;
7467}
7468
7469static void vmh264_dump_userdata(void)
7470{
7471 if (user_data_buf) {
7472 show_user_data_buf();
7473 kfree(user_data_buf);
7474 user_data_buf = NULL;
7475 }
7476}
7477
7478static void vmh264_reset_user_data_buf(void)
7479{
7480 total_len = 0;
7481 pbuf_start = user_data_buf;
7482 bskip = 0;
7483 n_userdata_id = 0;
7484}
7485#endif
7486
7487
7488static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw,
7489 int frame_type,
7490 u32 vpts,
7491 u32 vpts_valid)
7492{
7493 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
7494
7495 unsigned char *pdata;
7496 u8 *pmax_sei_data_buffer;
7497 u8 *sei_data_buf;
7498 int i;
7499 int wp;
7500 int data_length;
7501 struct mh264_userdata_record_t *p_userdata_rec;
7502
7503
7504#ifdef MH264_USERDATA_ENABLE
7505 struct userdata_meta_info_t meta_info;
7506 memset(&meta_info, 0, sizeof(meta_info));
7507#endif
7508
7509 if (hw->sei_itu_data_len <= 0)
7510 return;
7511
7512 pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp;
7513 pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE;
7514 sei_data_buf = (u8 *)hw->sei_itu_data_buf;
7515 for (i = 0; i < hw->sei_itu_data_len; i++) {
7516 *pdata++ = sei_data_buf[i];
7517 if (pdata >= pmax_sei_data_buffer)
7518 pdata = (u8 *)hw->sei_user_data_buffer;
7519 }
7520
7521 hw->sei_user_data_wp = (hw->sei_user_data_wp
7522 + hw->sei_itu_data_len) % USER_DATA_SIZE;
7523 hw->sei_itu_data_len = 0;
7524
7525#ifdef MH264_USERDATA_ENABLE
7526 meta_info.duration = hw->frame_dur;
7527 meta_info.flags |= (VFORMAT_H264 << 3);
7528
7529 meta_info.vpts = vpts;
7530 meta_info.vpts_valid = vpts_valid;
7531 meta_info.poc_number =
7532 p_H264_Dpb->mVideo.dec_picture->poc;
7533
7534
7535 wp = hw->sei_user_data_wp;
7536
7537 if (hw->sei_user_data_wp > hw->userdata_info.last_wp)
7538 data_length = wp - hw->userdata_info.last_wp;
7539 else
7540 data_length = wp + hw->userdata_info.buf_len
7541 - hw->userdata_info.last_wp;
7542
7543 if (data_length & 0x7)
7544 data_length = (((data_length + 8) >> 3) << 3);
7545
7546 p_userdata_rec = &hw->ud_record;
7547 p_userdata_rec->meta_info = meta_info;
7548 p_userdata_rec->rec_start = hw->userdata_info.last_wp;
7549 p_userdata_rec->rec_len = data_length;
7550 hw->userdata_info.last_wp = wp;
7551
7552 p_userdata_rec->meta_info.flags |=
7553 p_H264_Dpb->mVideo.dec_picture->pic_struct << 12;
7554
7555 hw->wait_for_udr_send = 1;
7556 vdec_schedule_work(&hw->user_data_ready_work);
7557#endif
7558}
7559
7560
7561static void user_data_ready_notify_work(struct work_struct *work)
7562{
7563 struct vdec_h264_hw_s *hw = container_of(work,
7564 struct vdec_h264_hw_s, user_data_ready_work);
7565
7566
7567 mutex_lock(&hw->userdata_mutex);
7568
7569 hw->userdata_info.records[hw->userdata_info.write_index]
7570 = hw->ud_record;
7571 hw->userdata_info.write_index++;
7572 if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM)
7573 hw->userdata_info.write_index = 0;
7574
7575 mutex_unlock(&hw->userdata_mutex);
7576
7577#ifdef DUMP_USERDATA_RECORD
7578 dump_userdata_record(hw, &hw->ud_record);
7579#endif
7580 vdec_wakeup_userdata_poll(hw_to_vdec(hw));
7581
7582 hw->wait_for_udr_send = 0;
7583}
7584
7585static int vmh264_user_data_read(struct vdec_s *vdec,
7586 struct userdata_param_t *puserdata_para)
7587{
7588 struct vdec_h264_hw_s *hw = NULL;
7589 int rec_ri, rec_wi;
7590 int rec_len;
7591 u8 *rec_data_start;
7592 u8 *pdest_buf;
7593 struct mh264_userdata_record_t *p_userdata_rec;
7594 u32 data_size;
7595 u32 res;
7596 int copy_ok = 1;
7597
7598 hw = (struct vdec_h264_hw_s *)vdec->private;
7599
7600 pdest_buf = puserdata_para->pbuf_addr;
7601
7602 mutex_lock(&hw->userdata_mutex);
7603
7604/*
7605 pr_info("ri = %d, wi = %d\n",
7606 lg_p_mpeg12_userdata_info->read_index,
7607 lg_p_mpeg12_userdata_info->write_index);
7608*/
7609 rec_ri = hw->userdata_info.read_index;
7610 rec_wi = hw->userdata_info.write_index;
7611
7612 if (rec_ri == rec_wi) {
7613 mutex_unlock(&hw->userdata_mutex);
7614 return 0;
7615 }
7616
7617 p_userdata_rec = hw->userdata_info.records + rec_ri;
7618
7619 rec_len = p_userdata_rec->rec_len;
7620 rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf;
7621/*
7622 pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n",
7623 p_userdata_rec->rec_len,
7624 p_userdata_rec->rec_start,
7625 puserdata_para->buf_len);
7626*/
7627 if (rec_len <= puserdata_para->buf_len) {
7628 /* dvb user data buffer is enought to
7629 copy the whole recored. */
7630 data_size = rec_len;
7631 if (rec_data_start + data_size
7632 > hw->userdata_info.data_buf_end) {
7633 int first_section_len;
7634
7635 first_section_len = hw->userdata_info.buf_len -
7636 p_userdata_rec->rec_start;
7637 res = (u32)copy_to_user((void *)pdest_buf,
7638 (void *)rec_data_start,
7639 first_section_len);
7640 if (res) {
7641 pr_info("p1 read not end res=%d, request=%d\n",
7642 res, first_section_len);
7643 copy_ok = 0;
7644
7645 p_userdata_rec->rec_len -=
7646 first_section_len - res;
7647 p_userdata_rec->rec_start +=
7648 first_section_len - res;
7649 puserdata_para->data_size =
7650 first_section_len - res;
7651 } else {
7652 res = (u32)copy_to_user(
7653 (void *)(pdest_buf+first_section_len),
7654 (void *)hw->userdata_info.data_buf,
7655 data_size - first_section_len);
7656 if (res) {
7657 pr_info("p2 read not end res=%d, request=%d\n",
7658 res, data_size);
7659 copy_ok = 0;
7660 }
7661 p_userdata_rec->rec_len -=
7662 data_size - res;
7663 p_userdata_rec->rec_start =
7664 data_size - first_section_len - res;
7665 puserdata_para->data_size =
7666 data_size - res;
7667 }
7668 } else {
7669 res = (u32)copy_to_user((void *)pdest_buf,
7670 (void *)rec_data_start,
7671 data_size);
7672 if (res) {
7673 pr_info("p3 read not end res=%d, request=%d\n",
7674 res, data_size);
7675 copy_ok = 0;
7676 }
7677 p_userdata_rec->rec_len -= data_size - res;
7678 p_userdata_rec->rec_start += data_size - res;
7679 puserdata_para->data_size = data_size - res;
7680 }
7681
7682 if (copy_ok) {
7683 hw->userdata_info.read_index++;
7684 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7685 hw->userdata_info.read_index = 0;
7686 }
7687 } else {
7688 /* dvb user data buffer is not enought
7689 to copy the whole recored. */
7690 data_size = puserdata_para->buf_len;
7691 if (rec_data_start + data_size
7692 > hw->userdata_info.data_buf_end) {
7693 int first_section_len;
7694
7695 first_section_len = hw->userdata_info.buf_len -
7696 p_userdata_rec->rec_start;
7697 res = (u32)copy_to_user((void *)pdest_buf,
7698 (void *)rec_data_start,
7699 first_section_len);
7700 if (res) {
7701 pr_info("p4 read not end res=%d, request=%d\n",
7702 res, first_section_len);
7703 copy_ok = 0;
7704 p_userdata_rec->rec_len -=
7705 first_section_len - res;
7706 p_userdata_rec->rec_start +=
7707 first_section_len - res;
7708 puserdata_para->data_size =
7709 first_section_len - res;
7710 } else {
7711 /* first secton copy is ok*/
7712 res = (u32)copy_to_user(
7713 (void *)(pdest_buf+first_section_len),
7714 (void *)hw->userdata_info.data_buf,
7715 data_size - first_section_len);
7716 if (res) {
7717 pr_info("p5 read not end res=%d, request=%d\n",
7718 res,
7719 data_size - first_section_len);
7720 copy_ok = 0;
7721 }
7722
7723 p_userdata_rec->rec_len -=
7724 data_size - res;
7725 p_userdata_rec->rec_start =
7726 data_size - first_section_len - res;
7727 puserdata_para->data_size =
7728 data_size - res;
7729 }
7730 } else {
7731 res = (u32)copy_to_user((void *)pdest_buf,
7732 (void *)rec_data_start,
7733 data_size);
7734 if (res) {
7735 pr_info("p6 read not end res=%d, request=%d\n",
7736 res, data_size);
7737 copy_ok = 0;
7738 }
7739
7740 p_userdata_rec->rec_len -= data_size - res;
7741 p_userdata_rec->rec_start += data_size - res;
7742 puserdata_para->data_size = data_size - res;
7743 }
7744
7745 if (copy_ok) {
7746 hw->userdata_info.read_index++;
7747 if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM)
7748 hw->userdata_info.read_index = 0;
7749 }
7750
7751 }
7752 puserdata_para->meta_info = p_userdata_rec->meta_info;
7753
7754 if (hw->userdata_info.read_index <= hw->userdata_info.write_index)
7755 puserdata_para->meta_info.records_in_que =
7756 hw->userdata_info.write_index -
7757 hw->userdata_info.read_index;
7758 else
7759 puserdata_para->meta_info.records_in_que =
7760 hw->userdata_info.write_index +
7761 USERDATA_FIFO_NUM -
7762 hw->userdata_info.read_index;
7763
7764 puserdata_para->version = (0<<24|0<<16|0<<8|1);
7765
7766 mutex_unlock(&hw->userdata_mutex);
7767
7768 return 1;
7769}
7770
7771static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit)
7772{
7773 struct vdec_h264_hw_s *hw = NULL;
7774
7775 hw = (struct vdec_h264_hw_s *)vdec->private;
7776
7777 if (hw) {
7778 mutex_lock(&hw->userdata_mutex);
7779 pr_info("vmh264_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n",
7780 bInit,
7781 hw->userdata_info.read_index,
7782 hw->userdata_info.write_index);
7783 hw->userdata_info.read_index = 0;
7784 hw->userdata_info.write_index = 0;
7785
7786 if (bInit)
7787 hw->userdata_info.last_wp = 0;
7788 mutex_unlock(&hw->userdata_mutex);
7789 }
7790}
7791
7792static void vmh264_wakeup_userdata_poll(struct vdec_s *vdec)
7793{
7794 amstream_wakeup_userdata_poll(vdec);
7795}
7796
7797#endif
7798
7799
7800static void vh264_work_implement(struct vdec_h264_hw_s *hw,
7801 struct vdec_s *vdec, int from)
7802{
7803 /* finished decoding one frame or error,
7804 * notify vdec core to switch context
7805 */
7806 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
7807 "%s dec_result %d %x %x %x\n",
7808 __func__,
7809 hw->dec_result,
7810 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7811 READ_VREG(VLD_MEM_VIFIFO_WP),
7812 READ_VREG(VLD_MEM_VIFIFO_RP));
7813 if (!hw->mmu_enable) {
7814 mutex_lock(&vmh264_mutex);
7815 dealloc_buf_specs(hw, 0);
7816 mutex_unlock(&vmh264_mutex);
7817 }
7818 hw->dpb.last_dpb_status = hw->dpb.dec_dpb_status;
7819 if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) {
7820 u32 param1 = READ_VREG(AV_SCRATCH_1);
7821 u32 param2 = READ_VREG(AV_SCRATCH_2);
7822 u32 param3 = READ_VREG(AV_SCRATCH_6);
7823 u32 param4 = READ_VREG(AV_SCRATCH_B);
7824
7825 if (vh264_set_params(hw, param1,
7826 param2, param3, param4) < 0)
7827 dpb_print(DECODE_ID(hw), 0, "set parameters error\n");
7828
7829 WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) |
7830 (hw->dpb.mDPB.size<<16) |
7831 (hw->dpb.mDPB.size<<8));
7832
7833 if (hw->is_used_v4l) {
7834 struct aml_vcodec_ctx *ctx =
7835 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7836
7837 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
7838 struct aml_vdec_pic_infos info;
7839
7840 info.visible_width = hw->frame_width;
7841 info.visible_height = hw->frame_height;
7842 info.coded_width = ALIGN(hw->frame_width, 64);
7843 info.coded_height = ALIGN(hw->frame_height, 64);
7844 info.dpb_size = hw->dpb.mDPB.size;
7845 hw->v4l_params_parsed = true;
7846 vdec_v4l_set_pic_infos(ctx, &info);
7847 }
7848 }
7849
7850 start_process_time(hw);
7851 return;
7852 } else
7853 if (((hw->dec_result == DEC_RESULT_GET_DATA) ||
7854 (hw->dec_result == DEC_RESULT_GET_DATA_RETRY))
7855 && (hw_to_vdec(hw)->next_status !=
7856 VDEC_STATUS_DISCONNECTED)) {
7857 if (!vdec_has_more_input(vdec)) {
7858 hw->dec_result = DEC_RESULT_EOS;
7859 vdec_schedule_work(&hw->work);
7860 return;
7861 }
7862
7863 if (hw->dec_result == DEC_RESULT_GET_DATA) {
7864 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7865 "%s DEC_RESULT_GET_DATA %x %x %x\n",
7866 __func__,
7867 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7868 READ_VREG(VLD_MEM_VIFIFO_WP),
7869 READ_VREG(VLD_MEM_VIFIFO_RP));
7870 mutex_lock(&hw->chunks_mutex);
7871 vdec_vframe_dirty(vdec, hw->chunk);
7872 hw->chunk = NULL;
7873 mutex_unlock(&hw->chunks_mutex);
7874 vdec_clean_input(vdec);
7875 }
7876 if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) &&
7877 ((1000 * (jiffies - hw->get_data_start_time) / HZ)
7878 > get_data_timeout_val)) {
7879 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7880 "%s DEC_RESULT_GET_DATA_RETRY timeout\n",
7881 __func__);
7882 goto result_done;
7883 }
7884 if (is_buffer_available(vdec)) {
7885 int r;
7886 int decode_size;
7887 r = vdec_prepare_input(vdec, &hw->chunk);
7888 if (r < 0 && (hw_to_vdec(hw)->next_status !=
7889 VDEC_STATUS_DISCONNECTED)) {
7890 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7891
7892 dpb_print(DECODE_ID(hw),
7893 PRINT_FLAG_VDEC_DETAIL,
7894 "vdec_prepare_input: Insufficient data\n");
7895 vdec_schedule_work(&hw->work);
7896 return;
7897 }
7898 hw->dec_result = DEC_RESULT_NONE;
7899 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7900 "%s: chunk size 0x%x\n",
7901 __func__, hw->chunk->size);
7902
7903 if (dpb_is_debug(DECODE_ID(hw),
7904 PRINT_FRAMEBASE_DATA)) {
7905 int jj;
7906 u8 *data = NULL;
7907
7908 if (!hw->chunk->block->is_mapped)
7909 data = codec_mm_vmap(
7910 hw->chunk->block->start +
7911 hw->chunk->offset, r);
7912 else
7913 data = ((u8 *)
7914 hw->chunk->block->start_virt)
7915 + hw->chunk->offset;
7916
7917 for (jj = 0; jj < r; jj++) {
7918 if ((jj & 0xf) == 0)
7919 dpb_print(DECODE_ID(hw),
7920 PRINT_FRAMEBASE_DATA,
7921 "%06x:", jj);
7922 dpb_print_cont(DECODE_ID(hw),
7923 PRINT_FRAMEBASE_DATA,
7924 "%02x ", data[jj]);
7925 if (((jj + 1) & 0xf) == 0)
7926 dpb_print_cont(DECODE_ID(hw),
7927 PRINT_FRAMEBASE_DATA,
7928 "\n");
7929 }
7930
7931 if (!hw->chunk->block->is_mapped)
7932 codec_mm_unmap_phyaddr(data);
7933 }
7934 WRITE_VREG(POWER_CTL_VLD,
7935 READ_VREG(POWER_CTL_VLD) |
7936 (0 << 10) | (1 << 9) | (1 << 6));
7937 WRITE_VREG(H264_DECODE_INFO, (1<<13));
7938 decode_size = hw->chunk->size +
7939 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
7940 WRITE_VREG(H264_DECODE_SIZE, decode_size);
7941 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
7942 vdec_enable_input(vdec);
7943
7944 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
7945 start_process_time(hw);
7946 } else{
7947 if (hw_to_vdec(hw)->next_status
7948 != VDEC_STATUS_DISCONNECTED) {
7949 hw->dec_result = DEC_RESULT_GET_DATA_RETRY;
7950 vdec_schedule_work(&hw->work);
7951 }
7952 }
7953 return;
7954 } else if (hw->dec_result == DEC_RESULT_DONE) {
7955 /* if (!hw->ctx_valid)
7956 hw->ctx_valid = 1; */
7957result_done:
7958 if (hw->mmu_enable
7959 && hw->frame_busy && hw->frame_done) {
7960 long used_4k_num;
7961 hevc_sao_wait_done(hw);
7962 if (hw->hevc_cur_buf_idx != 0xffff) {
7963 used_4k_num =
7964 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7965 if (used_4k_num >= 0)
7966 dpb_print(DECODE_ID(hw),
7967 PRINT_FLAG_MMU_DETAIL,
7968 "release unused buf , used_4k_num %ld index %d\n",
7969 used_4k_num, hw->hevc_cur_buf_idx);
7970 hevc_mmu_dma_check(hw_to_vdec(hw));
7971 decoder_mmu_box_free_idx_tail(
7972 hw->mmu_box,
7973 hw->hevc_cur_buf_idx,
7974 used_4k_num);
7975 hw->hevc_cur_buf_idx = 0xffff;
7976 }
7977 }
7978 decode_frame_count[DECODE_ID(hw)]++;
7979 amvdec_stop();
7980 if (!vdec_is_support_4k()) {
7981 if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) {
7982 clk_adj_frame_count++;
7983 if (clk_adj_frame_count == VDEC_CLOCK_ADJUST_FRAME)
7984 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
7985 }
7986 }
7987 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
7988 "%s dec_result %d %x %x %x\n",
7989 __func__,
7990 hw->dec_result,
7991 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
7992 READ_VREG(VLD_MEM_VIFIFO_WP),
7993 READ_VREG(VLD_MEM_VIFIFO_RP));
7994 mutex_lock(&hw->chunks_mutex);
7995 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
7996 hw->chunk = NULL;
7997 mutex_unlock(&hw->chunks_mutex);
7998 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
7999 /*
8000 stream base: stream buf empty or timeout
8001 frame base: vdec_prepare_input fail
8002 */
8003 if (!vdec_has_more_input(vdec) && (hw_to_vdec(hw)->next_status !=
8004 VDEC_STATUS_DISCONNECTED)) {
8005 hw->dec_result = DEC_RESULT_EOS;
8006 vdec_schedule_work(&hw->work);
8007 return;
8008 }
8009 hw->next_again_flag = 1;
8010 } else if (hw->dec_result == DEC_RESULT_EOS) {
8011 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8012 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8013 "%s: end of stream\n",
8014 __func__);
8015 amvdec_stop();
8016 if (hw->mmu_enable)
8017 amhevc_stop();
8018 hw->eos = 1;
8019 flush_dpb(p_H264_Dpb);
8020 if (hw->is_used_v4l)
8021 notify_v4l_eos(hw_to_vdec(hw));
8022 mutex_lock(&hw->chunks_mutex);
8023 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
8024 hw->chunk = NULL;
8025 mutex_unlock(&hw->chunks_mutex);
8026 vdec_clean_input(vdec);
8027 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
8028 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8029 "%s: force exit\n",
8030 __func__);
8031 amvdec_stop();
8032 if (hw->mmu_enable)
8033 amhevc_stop();
8034 if (hw->stat & STAT_ISR_REG) {
8035 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
8036 hw->stat &= ~STAT_ISR_REG;
8037 }
8038 }
8039 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
8040 del_timer_sync(&hw->check_timer);
8041 hw->stat &= ~STAT_TIMER_ARM;
8042
8043 wait_vmh264_search_done(hw);
8044 /* mark itself has all HW resource released and input released */
8045
8046#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8047 if (hw->switch_dvlayer_flag) {
8048 if (vdec->slave)
8049 vdec_set_next_sched(vdec, vdec->slave);
8050 else if (vdec->master)
8051 vdec_set_next_sched(vdec, vdec->master);
8052 } else if (vdec->slave || vdec->master)
8053 vdec_set_next_sched(vdec, vdec);
8054#endif
8055
8056 if (from == 1) {
8057 /* This is a timeout work */
8058 if (work_pending(&hw->work)) {
8059 /*
8060 * The vh264_work arrives at the last second,
8061 * give it a chance to handle the scenario.
8062 */
8063 return;
8064 }
8065 }
8066
8067 /* mark itself has all HW resource released and input released */
8068 if (vdec->parallel_dec == 1) {
8069 if (hw->mmu_enable == 0)
8070 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1);
8071 else
8072 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8073 } else
8074 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
8075
8076 wake_up_interruptible(&hw->wait_q);
8077
8078 if (hw->is_used_v4l) {
8079 struct aml_vcodec_ctx *ctx =
8080 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8081
8082 if (ctx->param_sets_from_ucode &&
8083 !hw->v4l_params_parsed)
8084 vdec_v4l_write_frame_sync(ctx);
8085 }
8086
8087 if (hw->vdec_cb)
8088 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
8089}
8090
8091
8092static void vh264_work(struct work_struct *work)
8093{
8094 struct vdec_h264_hw_s *hw = container_of(work,
8095 struct vdec_h264_hw_s, work);
8096 struct vdec_s *vdec = hw_to_vdec(hw);
8097
8098 vh264_work_implement(hw, vdec, 0);
8099}
8100
8101
8102static void vh264_timeout_work(struct work_struct *work)
8103{
8104 struct vdec_h264_hw_s *hw = container_of(work,
8105 struct vdec_h264_hw_s, timeout_work);
8106 struct vdec_s *vdec = hw_to_vdec(hw);
8107
8108 if (work_pending(&hw->work))
8109 return;
8110
8111 vh264_work_implement(hw, vdec, 1);
8112}
8113
8114static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
8115{
8116 bool ret = 0;
8117 struct vdec_h264_hw_s *hw =
8118 (struct vdec_h264_hw_s *)vdec->private;
8119 int tvp = vdec_secure(hw_to_vdec(hw)) ?
8120 CODEC_MM_FLAGS_TVP : 0;
8121
8122 if (!hw->first_sc_checked && hw->mmu_enable) {
8123 int size = decoder_mmu_box_sc_check(hw->mmu_box, tvp);
8124 hw->first_sc_checked =1;
8125 dpb_print(DECODE_ID(hw), 0,
8126 "vmh264 cached=%d need_size=%d speed= %d ms\n",
8127 size, (hw->need_cache_size >> PAGE_SHIFT),
8128 (int)(get_jiffies_64() - hw->sc_start_time) * 1000/HZ);
8129 }
8130
8131 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
8132 && pre_decode_buf_level != 0) {
8133 u32 rp, wp, level;
8134
8135 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
8136 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
8137 if (wp < rp)
8138 level = vdec->input.size + wp - rp;
8139 else
8140 level = wp - rp;
8141
8142 if (level < pre_decode_buf_level)
8143 return 0;
8144 }
8145
8146#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8147 if (vdec->master)
8148 return 0;
8149#endif
8150 if (hw->eos)
8151 return 0;
8152
8153 if (hw->stat & DECODER_FATAL_ERROR_NO_MEM)
8154 return 0;
8155
8156 if (disp_vframe_valve_level &&
8157 kfifo_len(&hw->display_q) >=
8158 disp_vframe_valve_level) {
8159 hw->valve_count--;
8160 if (hw->valve_count <= 0)
8161 hw->valve_count = 2;
8162 else
8163 return 0;
8164 }
8165 if (hw->next_again_flag &&
8166 (!vdec_frame_based(vdec))) {
8167 u32 parser_wr_ptr =
8168 READ_PARSER_REG(PARSER_VIDEO_WP);
8169 if (parser_wr_ptr >= hw->pre_parser_wr_ptr &&
8170 (parser_wr_ptr - hw->pre_parser_wr_ptr) <
8171 again_threshold) {
8172 int r = vdec_sync_input(vdec);
8173 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8174 "%s buf lelvel:%x\n", __func__, r);
8175 return 0;
8176 }
8177 }
8178
8179 if (h264_debug_flag & 0x20000000) {
8180 /* pr_info("%s, a\n", __func__); */
8181 ret = 1;
8182 } else
8183 ret = is_buffer_available(vdec);
8184
8185#ifdef CONSTRAIN_MAX_BUF_NUM
8186 if (hw->dpb.mDPB.size > 0) { /*make sure initilized*/
8187 if (run_ready_max_vf_only_num > 0 &&
8188 get_vf_ref_only_buf_count(hw) >=
8189 run_ready_max_vf_only_num
8190 )
8191 ret = 0;
8192 if (run_ready_display_q_num > 0 &&
8193 kfifo_len(&hw->display_q) >=
8194 run_ready_display_q_num)
8195 ret = 0;
8196 /*avoid more buffers consumed when
8197 switching resolution*/
8198 if (run_ready_max_buf_num == 0xff &&
8199 get_used_buf_count(hw) >
8200 hw->dpb.mDPB.size)
8201 ret = 0;
8202 else if (run_ready_max_buf_num &&
8203 get_used_buf_count(hw) >=
8204 run_ready_max_buf_num)
8205 ret = 0;
8206
8207 if (hw->is_used_v4l) {
8208 struct aml_vcodec_ctx *ctx =
8209 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8210
8211 if (ctx->param_sets_from_ucode &&
8212 !ctx->v4l_codec_ready &&
8213 hw->v4l_params_parsed)
8214 ret = 0; /*the params has parsed.*/
8215 }
8216 }
8217#endif
8218 if (ret)
8219 not_run_ready[DECODE_ID(hw)] = 0;
8220 else
8221 not_run_ready[DECODE_ID(hw)]++;
8222 if (vdec->parallel_dec == 1) {
8223 if (hw->mmu_enable == 0)
8224 return ret ? (CORE_MASK_VDEC_1) : 0;
8225 else
8226 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8227 } else
8228 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
8229}
8230
8231static unsigned char get_data_check_sum
8232 (struct vdec_h264_hw_s *hw, int size)
8233{
8234 int jj;
8235 int sum = 0;
8236 u8 *data = NULL;
8237
8238 if (!hw->chunk->block->is_mapped)
8239 data = codec_mm_vmap(hw->chunk->block->start +
8240 hw->chunk->offset, size);
8241 else
8242 data = ((u8 *)hw->chunk->block->start_virt)
8243 + hw->chunk->offset;
8244
8245 for (jj = 0; jj < size; jj++)
8246 sum += data[jj];
8247
8248 if (!hw->chunk->block->is_mapped)
8249 codec_mm_unmap_phyaddr(data);
8250 return sum;
8251}
8252
8253static void run(struct vdec_s *vdec, unsigned long mask,
8254 void (*callback)(struct vdec_s *, void *), void *arg)
8255{
8256 struct vdec_h264_hw_s *hw =
8257 (struct vdec_h264_hw_s *)vdec->private;
8258 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8259 int size, ret = -1;
8260
8261 run_count[DECODE_ID(hw)]++;
8262 vdec_reset_core(vdec);
8263 if (hw->mmu_enable)
8264 hevc_reset_core(vdec);
8265 hw->vdec_cb_arg = arg;
8266 hw->vdec_cb = callback;
8267
8268 if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) {
8269 hw->reset_bufmgr_flag = 1;
8270 dpb_print(DECODE_ID(hw), 0,
8271 "kfifo len:%d invaild, need bufmgr reset\n",
8272 kfifo_len(&hw->display_q));
8273 }
8274
8275 hw->pre_parser_wr_ptr =
8276 READ_PARSER_REG(PARSER_VIDEO_WP);
8277 hw->next_again_flag = 0;
8278
8279 if (hw->reset_bufmgr_flag ||
8280 ((error_proc_policy & 0x40) &&
8281 p_H264_Dpb->buf_alloc_fail)) {
8282 h264_reset_bufmgr(vdec);
8283 hw->reset_bufmgr_flag = 0;
8284 }
8285
8286 if (h264_debug_cmd & 0xf000) {
8287 if (((h264_debug_cmd >> 12) & 0xf)
8288 == (DECODE_ID(hw) + 1)) {
8289 h264_reconfig(hw);
8290 h264_debug_cmd &= (~0xf000);
8291 }
8292 }
8293 /* hw->chunk = vdec_prepare_input(vdec); */
8294#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8295 if (vdec->slave || vdec->master)
8296 vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT);
8297#endif
8298 size = vdec_prepare_input(vdec, &hw->chunk);
8299 if ((size < 0) ||
8300 (input_frame_based(vdec) && hw->chunk == NULL)) {
8301 input_empty[DECODE_ID(hw)]++;
8302 hw->dec_result = DEC_RESULT_AGAIN;
8303
8304 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL,
8305 "vdec_prepare_input: Insufficient data\n");
8306
8307 vdec_schedule_work(&hw->work);
8308 return;
8309 }
8310 input_empty[DECODE_ID(hw)] = 0;
8311
8312 hw->dec_result = DEC_RESULT_NONE;
8313 hw->get_data_count = 0;
8314#if 0
8315 pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n",
8316 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8317 READ_VREG(VLD_MEM_VIFIFO_RP),
8318 READ_VREG(VLD_MEM_VIFIFO_WP));
8319#endif
8320
8321 if (input_frame_based(vdec) && !vdec_secure(vdec)) {
8322 u8 *data = NULL;
8323
8324 if (!hw->chunk->block->is_mapped)
8325 data = codec_mm_vmap(hw->chunk->block->start +
8326 hw->chunk->offset, size);
8327 else
8328 data = ((u8 *)hw->chunk->block->start_virt)
8329 + hw->chunk->offset;
8330
8331 if (dpb_is_debug(DECODE_ID(hw),
8332 PRINT_FLAG_VDEC_STATUS)
8333 ) {
8334 dpb_print(DECODE_ID(hw), 0,
8335 "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n",
8336 __func__, size, get_data_check_sum(hw, size),
8337 data[0], data[1], data[2], data[3],
8338 data[4], data[5], data[size - 4],
8339 data[size - 3], data[size - 2],
8340 data[size - 1]);
8341 }
8342 if (dpb_is_debug(DECODE_ID(hw),
8343 PRINT_FRAMEBASE_DATA)
8344 ) {
8345 int jj;
8346
8347 for (jj = 0; jj < size; jj++) {
8348 if ((jj & 0xf) == 0)
8349 dpb_print(DECODE_ID(hw),
8350 PRINT_FRAMEBASE_DATA,
8351 "%06x:", jj);
8352 dpb_print_cont(DECODE_ID(hw),
8353 PRINT_FRAMEBASE_DATA,
8354 "%02x ", data[jj]);
8355 if (((jj + 1) & 0xf) == 0)
8356 dpb_print_cont(DECODE_ID(hw),
8357 PRINT_FRAMEBASE_DATA,
8358 "\n");
8359 }
8360 }
8361
8362 if (!hw->chunk->block->is_mapped)
8363 codec_mm_unmap_phyaddr(data);
8364 } else
8365 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8366 "%s: %x %x %x %x %x size 0x%x\n",
8367 __func__,
8368 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
8369 READ_VREG(VLD_MEM_VIFIFO_WP),
8370 READ_VREG(VLD_MEM_VIFIFO_RP),
8371 READ_PARSER_REG(PARSER_VIDEO_RP),
8372 READ_PARSER_REG(PARSER_VIDEO_WP),
8373 size);
8374
8375 start_process_time(hw);
8376 if (vdec->mc_loaded) {
8377 /*firmware have load before,
8378 and not changes to another.
8379 ignore reload.
8380 */
8381 WRITE_VREG(AV_SCRATCH_G, hw->reg_g_status);
8382 } else {
8383
8384 ret = amvdec_vdec_loadmc_ex(VFORMAT_H264, "mh264", vdec, hw->fw->data);
8385 if (ret < 0) {
8386 amvdec_enable_flag = false;
8387 amvdec_disable();
8388
8389 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8390 "MH264 the %s fw loading failed, err: %x\n",
8391 tee_enabled() ? "TEE" : "local", ret);
8392 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8393 vdec_schedule_work(&hw->work);
8394 return;
8395 }
8396 vdec->mc_type = VFORMAT_H264;
8397 hw->reg_g_status = READ_VREG(AV_SCRATCH_G);
8398 if (hw->mmu_enable) {
8399 ret = amhevc_loadmc_ex(VFORMAT_H264, "mh264_mmu",
8400 hw->fw_mmu->data);
8401 if (ret < 0) {
8402 amvdec_enable_flag = false;
8403 amhevc_disable();
8404
8405 dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
8406 "MH264_MMU the %s fw loading failed, err: %x\n",
8407 tee_enabled() ? "TEE" : "local", ret);
8408 hw->dec_result = DEC_RESULT_FORCE_EXIT;
8409 vdec_schedule_work(&hw->work);
8410 return;
8411 }
8412 vdec->mc_type = ((1 << 16) | VFORMAT_H264);
8413 }
8414 vdec->mc_loaded = 1;
8415 }
8416 vmh264_reset_udr_mgr(hw);
8417
8418 if (vh264_hw_ctx_restore(hw) < 0) {
8419 vdec_schedule_work(&hw->work);
8420 return;
8421 }
8422 if (input_frame_based(vdec)) {
8423 int decode_size = 0;
8424
8425 decode_size = hw->chunk->size +
8426 (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1));
8427 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8428 WRITE_VREG(H264_DECODE_SIZE, decode_size);
8429 WRITE_VREG(VIFF_BIT_CNT, decode_size * 8);
8430 } else {
8431 if (size <= 0)
8432 size = 0x7fffffff; /*error happen*/
8433 WRITE_VREG(H264_DECODE_INFO, (1<<13));
8434 WRITE_VREG(H264_DECODE_SIZE, size);
8435 WRITE_VREG(VIFF_BIT_CNT, size * 8);
8436 }
8437 config_aux_buf(hw);
8438 config_decode_mode(hw);
8439 vdec_enable_input(vdec);
8440 WRITE_VREG(NAL_SEARCH_CTL, 0);
8441 hw->sei_data_len = 0;
8442 if (enable_itu_t35)
8443 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1);
8444 if (!hw->init_flag) {
8445 if (hw->mmu_enable)
8446 WRITE_VREG(NAL_SEARCH_CTL,
8447 READ_VREG(NAL_SEARCH_CTL) | 0x2);
8448 else
8449 WRITE_VREG(NAL_SEARCH_CTL,
8450 READ_VREG(NAL_SEARCH_CTL) & (~0x2));
8451 }
8452 if (udebug_flag)
8453 WRITE_VREG(AV_SCRATCH_K, udebug_flag);
8454 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
8455
8456 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
8457
8458 if (hw->mmu_enable)
8459 SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8460 else
8461 CLEAR_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
8462 }
8463 amvdec_start();
8464 if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) {
8465 WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0);
8466 amhevc_start();
8467 if (hw->config_bufmgr_done) {
8468 hevc_mcr_sao_global_hw_init(hw,
8469 (hw->mb_width << 4), (hw->mb_height << 4));
8470 hevc_mcr_config_canv2axitbl(hw, 1);
8471 }
8472 }
8473
8474 /* if (hw->init_flag) { */
8475 WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD);
8476 /* } */
8477
8478 hw->init_flag = 1;
8479}
8480
8481static void reset(struct vdec_s *vdec)
8482{
8483 struct vdec_h264_hw_s *hw =
8484 (struct vdec_h264_hw_s *)vdec->private;
8485
8486 pr_info("vmh264 reset\n");
8487
8488 cancel_work_sync(&hw->work);
8489 cancel_work_sync(&hw->notify_work);
8490 if (hw->stat & STAT_VDEC_RUN) {
8491 amhevc_stop();
8492 hw->stat &= ~STAT_VDEC_RUN;
8493 }
8494
8495 if (hw->stat & STAT_TIMER_ARM) {
8496 del_timer_sync(&hw->check_timer);
8497 hw->stat &= ~STAT_TIMER_ARM;
8498 }
8499 hw->eos = 0;
8500 hw->decode_pic_count = 0;
8501 hw->dec_result = DEC_RESULT_NONE;
8502 reset_process_time(hw);
8503 h264_reset_bufmgr(vdec);
8504
8505 dpb_print(DECODE_ID(hw), 0, "%s\n", __func__);
8506}
8507
8508static void h264_reconfig(struct vdec_h264_hw_s *hw)
8509{
8510 int i;
8511 unsigned long flags;
8512 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8513 dpb_print(DECODE_ID(hw), 0,
8514 "%s\n", __func__);
8515 /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(),
8516 all buffers are in display queue (used == 2),
8517 or free (used == 0)
8518 */
8519 if (dpb_is_debug(DECODE_ID(hw),
8520 PRINT_FLAG_DUMP_BUFSPEC))
8521 dump_bufspec(hw, "pre h264_reconfig");
8522
8523 flush_dpb(p_H264_Dpb);
8524 bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0);
8525
8526 if (hw->collocate_cma_alloc_addr) {
8527 decoder_bmmu_box_free_idx(
8528 hw->bmmu_box,
8529 BMMU_REF_IDX);
8530 hw->collocate_cma_alloc_addr = 0;
8531 hw->dpb.colocated_mv_addr_start = 0;
8532 hw->dpb.colocated_mv_addr_end = 0;
8533 }
8534 spin_lock_irqsave(&hw->bufspec_lock, flags);
8535 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8536 /*make sure buffers not put back to bufmgr when
8537 vf_put is called*/
8538 if (hw->buffer_spec[i].used == 2)
8539 hw->buffer_spec[i].used = 3;
8540
8541 /* ready to release "free buffers"
8542 */
8543 if (hw->buffer_spec[i].used == 0)
8544 hw->buffer_spec[i].used = 4;
8545
8546 hw->buffer_spec[i].canvas_pos = -1;
8547 }
8548 spin_unlock_irqrestore(&hw->bufspec_lock, flags);
8549 hw->has_i_frame = 0;
8550 hw->config_bufmgr_done = 0;
8551
8552 if (hw->is_used_v4l) {
8553 mutex_lock(&vmh264_mutex);
8554 dealloc_buf_specs(hw, 1);
8555 mutex_unlock(&vmh264_mutex);
8556 }
8557
8558 if (dpb_is_debug(DECODE_ID(hw),
8559 PRINT_FLAG_DUMP_BUFSPEC))
8560 dump_bufspec(hw, "after h264_reconfig");
8561
8562}
8563
8564#ifdef ERROR_HANDLE_TEST
8565static void h264_clear_dpb(struct vdec_h264_hw_s *hw)
8566{
8567 int i;
8568 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8569 dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS,
8570 "%s\n", __func__);
8571 remove_dpb_pictures(p_H264_Dpb);
8572 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8573 /*make sure buffers not put back to bufmgr when
8574 vf_put is called*/
8575 if (hw->buffer_spec[i].used == 2)
8576 hw->buffer_spec[i].used = 5;
8577 }
8578
8579}
8580#endif
8581
8582static void h264_reset_bufmgr(struct vdec_s *vdec)
8583{
8584 int i;
8585 ulong timeout;
8586 struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private;
8587#if 0
8588 struct h264_dpb_stru *p_H264_Dpb = &hw->dpb;
8589 int actual_dpb_size, max_reference_size;
8590 int reorder_pic_num;
8591 unsigned int colocated_buf_size;
8592 unsigned int colocated_mv_addr_start;
8593 unsigned int colocated_mv_addr_end;
8594 dpb_print(DECODE_ID(hw), 0,
8595 "%s\n", __func__);
8596
8597 for (i = 0; i < VF_POOL_SIZE; i++)
8598 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8599
8600 actual_dpb_size = p_H264_Dpb->mDPB.size;
8601 max_reference_size = p_H264_Dpb->max_reference_size;
8602 reorder_pic_num = p_H264_Dpb->reorder_pic_num;
8603
8604 colocated_buf_size = p_H264_Dpb->colocated_buf_size;
8605 colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start;
8606 colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end;
8607
8608 hw->cur_pool++;
8609 if (hw->cur_pool >= VF_POOL_NUM)
8610 hw->cur_pool = 0;
8611
8612 INIT_KFIFO(hw->display_q);
8613 INIT_KFIFO(hw->newframe_q);
8614
8615 for (i = 0; i < VF_POOL_SIZE; i++) {
8616 const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]);
8617 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8618 hw->vfpool[hw->cur_pool][i].bufWidth = 1920;
8619 kfifo_put(&hw->newframe_q, vf);
8620 }
8621
8622 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
8623 hw->buffer_spec[i].used = 0;
8624
8625 dpb_init_global(&hw->dpb,
8626 DECODE_ID(hw), 0, 0);
8627 p_H264_Dpb->mDPB.size = actual_dpb_size;
8628 p_H264_Dpb->max_reference_size = max_reference_size;
8629 p_H264_Dpb->reorder_pic_num = reorder_pic_num;
8630
8631 p_H264_Dpb->colocated_buf_size = colocated_buf_size;
8632 p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start;
8633 p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end;
8634
8635 p_H264_Dpb->fast_output_enable = fast_output_enable;
8636 hw->has_i_frame = 0;
8637#else
8638 dpb_print(DECODE_ID(hw), 0,
8639 "%s frame count %d to skip %d\n\n",
8640 __func__, hw->decode_pic_count+1,
8641 hw->skip_frame_count);
8642
8643 timeout = jiffies + HZ;
8644 while (kfifo_len(&hw->display_q) > 0) {
8645 if (time_after(jiffies, timeout))
8646 break;
8647 schedule();
8648 }
8649
8650 for (i = 0; i < VF_POOL_SIZE; i++)
8651 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8652
8653 hw->cur_pool++;
8654 if (hw->cur_pool >= VF_POOL_NUM)
8655 hw->cur_pool = 0;
8656
8657 for (i = 0; i < VF_POOL_SIZE; i++)
8658 hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */
8659
8660
8661 vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL);
8662
8663 buf_spec_init(hw);
8664
8665 vh264_local_init(hw);
8666 /*hw->decode_pic_count = 0;
8667 hw->seq_info2 = 0;*/
8668
8669 if (hw->is_used_v4l) {
8670 mutex_lock(&vmh264_mutex);
8671 /* detach relationship with v4l buffs.*/
8672 dealloc_buf_specs(hw, 1);
8673 mutex_unlock(&vmh264_mutex);
8674 }
8675
8676 if (vh264_set_params(hw,
8677 hw->cfg_param1,
8678 hw->cfg_param2,
8679 hw->cfg_param3,
8680 hw->cfg_param4) < 0)
8681 hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8682
8683 /*drop 3 frames after reset bufmgr if bit0 is set 1 */
8684 if (first_i_policy & 0x01)
8685 hw->first_i_policy = (3 << 8) | first_i_policy;
8686
8687 hw->init_flag = 1;
8688 hw->reset_bufmgr_count++;
8689#endif
8690}
8691
8692int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw)
8693{
8694 int ret = -1;
8695 int tvp_flag = vdec_secure(hw_to_vdec(hw)) ?
8696 CODEC_MM_FLAGS_TVP : 0;
8697 int buf_size = 64;
8698
8699 pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n",
8700 tvp_flag, hw->mmu_enable);
8701 hw->need_cache_size = buf_size * SZ_1M;
8702 hw->sc_start_time = get_jiffies_64();
8703 if (hw->mmu_enable && !hw->mmu_box) {
8704 hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8705 hw->id,
8706 MMU_MAX_BUFFERS,
8707 hw->need_cache_size,
8708 tvp_flag);
8709 if (!hw->mmu_box) {
8710 pr_err("h264 4k alloc mmu box failed!!\n");
8711 return -1;
8712 }
8713 ret = 0;
8714 }
8715 if (!hw->bmmu_box) {
8716 hw->bmmu_box = decoder_bmmu_box_alloc_box(
8717 DRIVER_NAME,
8718 hw->id,
8719 BMMU_MAX_BUFFERS,
8720 4 + PAGE_SHIFT,
8721 CODEC_MM_FLAGS_CMA_CLEAR |
8722 CODEC_MM_FLAGS_FOR_VDECODER |
8723 tvp_flag);
8724 if (hw->bmmu_box)
8725 ret = 0;
8726 }
8727 return ret;
8728}
8729int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw)
8730{
8731 if (hw->mmu_box) {
8732 decoder_mmu_box_free(hw->mmu_box);
8733 hw->mmu_box = NULL;
8734 }
8735 if (hw->bmmu_box) {
8736 decoder_bmmu_box_free(hw->bmmu_box);
8737 hw->bmmu_box = NULL;
8738 }
8739 return 0;
8740}
8741
8742static int ammvdec_h264_probe(struct platform_device *pdev)
8743{
8744 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8745 struct vdec_h264_hw_s *hw = NULL;
8746 char *tmpbuf;
8747 int config_val;
8748
8749 if (pdata == NULL) {
8750 pr_info("\nammvdec_h264 memory resource undefined.\n");
8751 return -EFAULT;
8752 }
8753
8754 hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev,
8755 sizeof(struct vdec_h264_hw_s), GFP_KERNEL);
8756 if (hw == NULL) {
8757 pr_info("\nammvdec_h264 device data allocation failed\n");
8758 return -ENOMEM;
8759 }
8760 hw->id = pdev->id;
8761 hw->platform_dev = pdev;
8762
8763 /* the ctx from v4l2 driver. */
8764 hw->v4l2_ctx = pdata->private;
8765
8766 if ((h264_debug_flag & IGNORE_PARAM_FROM_CONFIG) == 0)
8767 hw->canvas_mode = pdata->canvas_mode;
8768 else
8769 hw->canvas_mode = mem_map_mode;
8770
8771 platform_set_drvdata(pdev, pdata);
8772
8773 hw->mmu_enable = 0;
8774 hw->first_head_check_flag = 0;
8775 hw->new_iframe_flag = 0;
8776 hw->ref_err_flush_dpb_flag = 0;
8777
8778 if (pdata->sys_info)
8779 hw->vh264_amstream_dec_info = *pdata->sys_info;
8780
8781 hw->is_used_v4l = (((unsigned long)
8782 hw->vh264_amstream_dec_info.param & 0x80) >> 7);
8783 if (hw->is_used_v4l) {
8784 hw->mmu_enable = (((unsigned long)
8785 hw->vh264_amstream_dec_info.param & 0x100) >> 8);
8786 dpb_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
8787 "%s v4: enable mmu %d.\n",
8788 __func__, hw->mmu_enable);
8789 }
8790
8791 if (force_enable_mmu && pdata->sys_info &&
8792 (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
8793 (get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_GXLX) &&
8794 (pdata->sys_info->height * pdata->sys_info->width
8795 > 1920 * 1088))
8796 hw->mmu_enable = 1;
8797
8798 if (hw->mmu_enable &&
8799 (pdata->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO)) {
8800 hw->mmu_enable = 0;
8801 pr_info("ionvideo needs disable mmu, path= %d \n",
8802 pdata->frame_base_video_path);
8803 }
8804
8805 if (ammvdec_h264_mmu_init(hw)) {
8806 h264_free_hw_stru(&pdev->dev, (void *)hw);
8807 pr_info("\nammvdec_h264 mmu alloc failed!\n");
8808 return -ENOMEM;
8809 }
8810
8811 if (pdata->config_len) {
8812 /*use ptr config for doubel_write_mode, etc*/
8813 if (get_config_int(pdata->config,
8814 "mh264_double_write_mode", &config_val) == 0)
8815 hw->double_write_mode = config_val;
8816 else
8817 hw->double_write_mode = double_write_mode;
8818 } else
8819 hw->double_write_mode = double_write_mode;
8820
8821 if (hw->mmu_enable)
8822 hw->double_write_mode &= 0xffff;
8823
8824 if (pdata->parallel_dec == 1) {
8825 int i;
8826 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
8827 hw->buffer_spec[i].y_canvas_index = -1;
8828 hw->buffer_spec[i].u_canvas_index = -1;
8829 hw->buffer_spec[i].v_canvas_index = -1;
8830#ifdef VDEC_DW
8831 if (IS_VDEC_DW(hw)) {
8832 hw->buffer_spec[i].vdec_dw_y_canvas_index = -1;
8833 hw->buffer_spec[i].vdec_dw_u_canvas_index = -1;
8834 hw->buffer_spec[i].vdec_dw_v_canvas_index = -1;
8835 }
8836#endif
8837 }
8838 }
8839
8840 dpb_print(DECODE_ID(hw), 0,
8841 "%s mmu_enable %d double_write_mode 0x%x\n",
8842 __func__, hw->mmu_enable, hw->double_write_mode);
8843
8844 pdata->private = hw;
8845 pdata->dec_status = dec_status;
8846 pdata->set_trickmode = vmh264_set_trickmode;
8847 pdata->run_ready = run_ready;
8848 pdata->run = run;
8849 pdata->reset = reset;
8850 pdata->irq_handler = vh264_isr;
8851 pdata->threaded_irq_handler = vh264_isr_thread_fn;
8852 pdata->dump_state = vmh264_dump_state;
8853
8854#ifdef MH264_USERDATA_ENABLE
8855 pdata->wakeup_userdata_poll = vmh264_wakeup_userdata_poll;
8856 pdata->user_data_read = vmh264_user_data_read;
8857 pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo;
8858#else
8859 pdata->wakeup_userdata_poll = NULL;
8860 pdata->user_data_read = NULL;
8861 pdata->reset_userdata_fifo = NULL;
8862#endif
8863 if (pdata->use_vfm_path) {
8864 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8865 VFM_DEC_PROVIDER_NAME);
8866 hw->frameinfo_enable = 1;
8867 }
8868#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8869 else if (vdec_dual(pdata)) {
8870 if (dv_toggle_prov_name) /*debug purpose*/
8871 snprintf(pdata->vf_provider_name,
8872 VDEC_PROVIDER_NAME_SIZE,
8873 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
8874 VFM_DEC_DVEL_PROVIDER_NAME);
8875 else
8876 snprintf(pdata->vf_provider_name,
8877 VDEC_PROVIDER_NAME_SIZE,
8878 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
8879 VFM_DEC_DVBL_PROVIDER_NAME);
8880 }
8881#endif
8882 else
8883 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
8884 PROVIDER_NAME ".%02x", pdev->id & 0xff);
8885
8886 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
8887 &vf_provider_ops, pdata);
8888
8889 platform_set_drvdata(pdev, pdata);
8890
8891 buf_spec_init(hw);
8892
8893 hw->platform_dev = pdev;
8894
8895#ifdef DUMP_USERDATA_RECORD
8896 vmh264_init_userdata_dump();
8897 vmh264_reset_user_data_buf();
8898#endif
8899 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX,
8900 V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) {
8901 h264_free_hw_stru(&pdev->dev, (void *)hw);
8902 pdata->dec_status = NULL;
8903 return -ENOMEM;
8904 }
8905
8906 hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR +
8907 DCAC_READ_MARGIN;
8908 if (hw->mmu_enable) {
8909 u32 extif_size = EXTIF_BUF_SIZE;
8910 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
8911 extif_size <<= 1;
8912 if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
8913 extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {
8914 h264_free_hw_stru(&pdev->dev, (void *)hw);
8915 pdata->dec_status = NULL;
8916 return -ENOMEM;
8917 }
8918 }
8919 if (!vdec_secure(pdata)) {
8920#if 1
8921 /*init internal buf*/
8922 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr);
8923 if (tmpbuf) {
8924 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8925 codec_mm_dma_flush(tmpbuf,
8926 V_BUF_ADDR_OFFSET,
8927 DMA_TO_DEVICE);
8928 } else {
8929 tmpbuf = codec_mm_vmap(hw->cma_alloc_addr,
8930 V_BUF_ADDR_OFFSET);
8931 if (tmpbuf) {
8932 memset(tmpbuf, 0, V_BUF_ADDR_OFFSET);
8933 codec_mm_dma_flush(tmpbuf,
8934 V_BUF_ADDR_OFFSET,
8935 DMA_TO_DEVICE);
8936 codec_mm_unmap_phyaddr(tmpbuf);
8937 }
8938 }
8939#else
8940 /*init sps/pps internal buf 64k*/
8941 tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr
8942 + (mem_sps_base - DEF_BUF_START_ADDR));
8943 memset(tmpbuf, 0, 0x10000);
8944 dma_sync_single_for_device(amports_get_dma_device(),
8945 hw->cma_alloc_addr +
8946 (mem_sps_base - DEF_BUF_START_ADDR),
8947 0x10000, DMA_TO_DEVICE);
8948#endif
8949 }
8950 /**/
8951
8952#if 0
8953 if (NULL == hw->sei_data_buffer) {
8954 hw->sei_data_buffer =
8955 dma_alloc_coherent(amports_get_dma_device(),
8956 USER_DATA_SIZE,
8957 &hw->sei_data_buffer_phys, GFP_KERNEL);
8958 if (!hw->sei_data_buffer) {
8959 pr_info("%s: Can not allocate sei_data_buffer\n",
8960 __func__);
8961 ammvdec_h264_mmu_release(hw);
8962 h264_free_hw_stru(&pdev->dev, (void *)hw);
8963 return -ENOMEM;
8964 }
8965 /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n",
8966 sei_data_buffer, sei_data_buffer_phys,
8967 (u32)sei_data_buffer_remap); */
8968 }
8969#endif
8970 dpb_print(DECODE_ID(hw), 0, "ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n",
8971 pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr);
8972
8973 if (vdec_is_support_4k() ||
8974 (clk_adj_frame_count > (VDEC_CLOCK_ADJUST_FRAME - 1)))
8975 vdec_source_changed(VFORMAT_H264, 3840, 2160, 60);
8976 else if (pdata->sys_info->height * pdata->sys_info->width <= 1280 * 720)
8977 {
8978 vdec_source_changed(VFORMAT_H264, 1280, 720, 29);
8979 }else
8980 {
8981 vdec_source_changed(VFORMAT_H264, 1920, 1080, 29);
8982 }
8983
8984 if (vh264_init(hw) < 0) {
8985 pr_info("\nammvdec_h264 init failed.\n");
8986 ammvdec_h264_mmu_release(hw);
8987 h264_free_hw_stru(&pdev->dev, (void *)hw);
8988 pdata->dec_status = NULL;
8989 return -ENODEV;
8990 }
8991#ifdef MH264_USERDATA_ENABLE
8992 vmh264_crate_userdata_manager(hw,
8993 hw->sei_user_data_buffer,
8994 USER_DATA_SIZE);
8995#endif
8996
8997 vdec_set_prepare_level(pdata, start_decode_buf_level);
8998 if (pdata->parallel_dec == 1) {
8999 if (hw->mmu_enable == 0)
9000 vdec_core_request(pdata, CORE_MASK_VDEC_1);
9001 else {
9002 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9003 | CORE_MASK_COMBINE);
9004 }
9005 } else
9006 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9007 | CORE_MASK_COMBINE);
9008
9009 atomic_set(&hw->vh264_active, 1);
9010
9011 return 0;
9012}
9013
9014static int ammvdec_h264_remove(struct platform_device *pdev)
9015{
9016 struct vdec_h264_hw_s *hw =
9017 (struct vdec_h264_hw_s *)
9018 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
9019 int i;
9020
9021 struct vdec_s *vdec = hw_to_vdec(hw);
9022
9023 if (vdec->next_status == VDEC_STATUS_DISCONNECTED
9024 && (vdec->status == VDEC_STATUS_ACTIVE)) {
9025 dpb_print(DECODE_ID(hw), 0,
9026 "%s force exit %d\n", __func__, __LINE__);
9027 hw->dec_result = DEC_RESULT_FORCE_EXIT;
9028 vdec_schedule_work(&hw->work);
9029 wait_event_interruptible_timeout(hw->wait_q,
9030 (vdec->status == VDEC_STATUS_CONNECTED),
9031 msecs_to_jiffies(1000)); /* wait for work done */
9032 }
9033
9034 for (i = 0; i < BUFSPEC_POOL_SIZE; i++)
9035 release_aux_data(hw, i);
9036
9037 atomic_set(&hw->vh264_active, 0);
9038
9039 if (hw->stat & STAT_TIMER_ARM) {
9040 del_timer_sync(&hw->check_timer);
9041 hw->stat &= ~STAT_TIMER_ARM;
9042 }
9043
9044 vh264_stop(hw);
9045#ifdef MH264_USERDATA_ENABLE
9046#ifdef DUMP_USERDATA_RECORD
9047 vmh264_dump_userdata();
9048#endif
9049 vmh264_destroy_userdata_manager(hw);
9050#endif
9051 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
9052
9053 atomic_set(&hw->vh264_active, 0);
9054 if (vdec->parallel_dec == 1) {
9055 if (hw->mmu_enable == 0)
9056 vdec_core_release(vdec, CORE_MASK_VDEC_1);
9057 else
9058 vdec_core_release(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC |
9059 CORE_MASK_COMBINE);
9060 } else
9061 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
9062
9063 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
9064 if (vdec->parallel_dec == 1) {
9065 for (i = 0; i < BUFSPEC_POOL_SIZE; i++) {
9066 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
9067 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
9068 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
9069 if (IS_VDEC_DW(hw)) {
9070 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_y_canvas_index, vdec->id);
9071 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_u_canvas_index, vdec->id);
9072 vdec->free_canvas_ex(hw->buffer_spec[i].vdec_dw_v_canvas_index, vdec->id);
9073 }
9074 }
9075 }
9076
9077 ammvdec_h264_mmu_release(hw);
9078 h264_free_hw_stru(&pdev->dev, (void *)hw);
9079 clk_adj_frame_count = 0;
9080
9081 return 0;
9082}
9083
9084/****************************************/
9085#ifdef CONFIG_PM
9086static int mh264_suspend(struct device *dev)
9087{
9088 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
9089 return 0;
9090}
9091
9092static int mh264_resume(struct device *dev)
9093{
9094 amvdec_resume(to_platform_device(dev));
9095 return 0;
9096}
9097
9098static const struct dev_pm_ops mh264_pm_ops = {
9099 SET_SYSTEM_SLEEP_PM_OPS(mh264_suspend, mh264_resume)
9100};
9101#endif
9102
9103static struct platform_driver ammvdec_h264_driver = {
9104 .probe = ammvdec_h264_probe,
9105 .remove = ammvdec_h264_remove,
9106 .driver = {
9107 .name = DRIVER_NAME,
9108#ifdef CONFIG_PM
9109 .pm = &mh264_pm_ops,
9110#endif
9111 }
9112};
9113
9114static struct codec_profile_t ammvdec_h264_profile = {
9115 .name = "mh264",
9116 .profile = ""
9117};
9118
9119static struct mconfig hm264_configs[] = {
9120 MC_PU32("h264_debug_flag", &h264_debug_flag),
9121 MC_PI32("start_decode_buf_level", &start_decode_buf_level),
9122 MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode),
9123 MC_PU32("decode_timeout_val", &decode_timeout_val),
9124 MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin),
9125 MC_PU32("reference_buf_margin", &reference_buf_margin),
9126 MC_PU32("radr", &radr),
9127 MC_PU32("rval", &rval),
9128 MC_PU32("h264_debug_mask", &h264_debug_mask),
9129 MC_PU32("h264_debug_cmd", &h264_debug_cmd),
9130 MC_PI32("force_rate_streambase", &force_rate_streambase),
9131 MC_PI32("dec_control", &dec_control),
9132 MC_PI32("force_rate_framebase", &force_rate_framebase),
9133 MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num),
9134 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
9135 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
9136#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9137 MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv),
9138 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
9139 MC_PU32("dolby_meta_with_el", &dolby_meta_with_el),
9140#endif
9141 MC_PU32("i_only_flag", &i_only_flag),
9142 MC_PU32("force_rate_streambase", &force_rate_streambase),
9143};
9144static struct mconfig_node hm264_node;
9145
9146
9147static int __init ammvdec_h264_driver_init_module(void)
9148{
9149 pr_info("ammvdec_h264 module init\n");
9150 if (platform_driver_register(&ammvdec_h264_driver)) {
9151 pr_info("failed to register ammvdec_h264 driver\n");
9152 return -ENODEV;
9153 }
9154
9155 if (vdec_is_support_4k()) {
9156 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) {
9157 ammvdec_h264_profile.profile =
9158 "4k, dwrite, compressed";
9159 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) {
9160 ammvdec_h264_profile.profile = "4k";
9161 }
9162 }
9163
9164 vcodec_profile_register(&ammvdec_h264_profile);
9165 INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node,
9166 "mh264", hm264_configs, CONFIG_FOR_RW);
9167 return 0;
9168}
9169
9170static void __exit ammvdec_h264_driver_remove_module(void)
9171{
9172 pr_info("ammvdec_h264 module remove.\n");
9173
9174 platform_driver_unregister(&ammvdec_h264_driver);
9175}
9176
9177/****************************************/
9178module_param(h264_debug_flag, uint, 0664);
9179MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n");
9180
9181module_param(start_decode_buf_level, int, 0664);
9182MODULE_PARM_DESC(start_decode_buf_level,
9183 "\n ammvdec_h264 start_decode_buf_level\n");
9184
9185module_param(pre_decode_buf_level, int, 0664);
9186MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
9187
9188module_param(fixed_frame_rate_mode, uint, 0664);
9189MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n");
9190
9191module_param(decode_timeout_val, uint, 0664);
9192MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n");
9193
9194module_param(errordata_timeout_val, uint, 0664);
9195MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n");
9196
9197module_param(get_data_timeout_val, uint, 0664);
9198MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n");
9199
9200module_param(frame_max_data_packet, uint, 0664);
9201MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n");
9202
9203module_param(reorder_dpb_size_margin, uint, 0664);
9204MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n");
9205
9206#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9207module_param(reorder_dpb_size_margin_dv, uint, 0664);
9208MODULE_PARM_DESC(reorder_dpb_size_margin_dv,
9209 "\n ammvdec_h264 reorder_dpb_size_margin_dv\n");
9210#endif
9211
9212module_param(reference_buf_margin, uint, 0664);
9213MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n");
9214
9215#ifdef CONSTRAIN_MAX_BUF_NUM
9216module_param(run_ready_max_vf_only_num, uint, 0664);
9217MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
9218
9219module_param(run_ready_display_q_num, uint, 0664);
9220MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
9221
9222module_param(run_ready_max_buf_num, uint, 0664);
9223MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
9224#endif
9225
9226module_param(radr, uint, 0664);
9227MODULE_PARM_DESC(radr, "\nradr\n");
9228
9229module_param(rval, uint, 0664);
9230MODULE_PARM_DESC(rval, "\nrval\n");
9231
9232module_param(h264_debug_mask, uint, 0664);
9233MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n");
9234
9235module_param(h264_debug_cmd, uint, 0664);
9236MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n");
9237
9238module_param(force_rate_streambase, int, 0664);
9239MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n");
9240
9241module_param(dec_control, int, 0664);
9242MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n");
9243
9244module_param(force_rate_framebase, int, 0664);
9245MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n");
9246
9247module_param(force_disp_bufspec_num, int, 0664);
9248MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n");
9249
9250module_param(V_BUF_ADDR_OFFSET, int, 0664);
9251MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n");
9252
9253module_param(prefix_aux_buf_size, uint, 0664);
9254MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
9255
9256module_param(suffix_aux_buf_size, uint, 0664);
9257MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
9258
9259#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9260module_param(dv_toggle_prov_name, uint, 0664);
9261MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
9262
9263module_param(dolby_meta_with_el, uint, 0664);
9264MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n");
9265
9266#endif
9267
9268module_param(fast_output_enable, uint, 0664);
9269MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n");
9270
9271module_param(error_proc_policy, uint, 0664);
9272MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n");
9273
9274module_param(error_skip_count, uint, 0664);
9275MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n");
9276
9277module_param(force_sliding_margin, uint, 0664);
9278MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n");
9279
9280module_param(i_only_flag, uint, 0664);
9281MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n");
9282
9283module_param(first_i_policy, uint, 0664);
9284MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n");
9285
9286module_param(frmbase_cont_bitlevel, uint, 0664);
9287MODULE_PARM_DESC(frmbase_cont_bitlevel,
9288 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9289
9290module_param(frmbase_cont_bitlevel2, uint, 0664);
9291MODULE_PARM_DESC(frmbase_cont_bitlevel2,
9292 "\n amvdec_h264 frmbase_cont_bitlevel\n");
9293
9294module_param(udebug_flag, uint, 0664);
9295MODULE_PARM_DESC(udebug_flag, "\n amvdec_mh264 udebug_flag\n");
9296
9297module_param(udebug_pause_pos, uint, 0664);
9298MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
9299
9300module_param(udebug_pause_val, uint, 0664);
9301MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
9302
9303module_param(udebug_pause_decode_idx, uint, 0664);
9304MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
9305
9306module_param(max_alloc_buf_count, uint, 0664);
9307MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n");
9308
9309module_param(enable_itu_t35, uint, 0664);
9310MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n");
9311
9312module_param(endian, uint, 0664);
9313MODULE_PARM_DESC(endian, "\nrval\n");
9314
9315module_param(mmu_enable, uint, 0664);
9316MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
9317
9318module_param(force_enable_mmu, uint, 0664);
9319MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n");
9320
9321module_param(again_threshold, uint, 0664);
9322MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
9323
9324module_param(stream_mode_start_num, uint, 0664);
9325MODULE_PARM_DESC(stream_mode_start_num, "\n stream_mode_start_num\n");
9326
9327/*
9328module_param(trigger_task, uint, 0664);
9329MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n");
9330*/
9331module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664);
9332
9333module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664);
9334
9335module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
9336
9337module_param_array(run_count, uint,
9338 &max_decode_instance_num, 0664);
9339
9340module_param_array(not_run_ready, uint,
9341 &max_decode_instance_num, 0664);
9342
9343module_param_array(input_empty, uint,
9344 &max_decode_instance_num, 0664);
9345
9346module_param_array(max_get_frame_interval, uint,
9347 &max_decode_instance_num, 0664);
9348
9349module_param_array(step, uint, &max_decode_instance_num, 0664);
9350
9351module_param_array(ref_frame_mark_flag, uint, &max_decode_instance_num, 0664);
9352
9353module_param(disp_vframe_valve_level, uint, 0664);
9354MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
9355
9356module_param(double_write_mode, uint, 0664);
9357MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
9358
9359module_param(mem_map_mode, uint, 0664);
9360MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
9361
9362module_param(without_display_mode, uint, 0664);
9363MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
9364
9365
9366module_init(ammvdec_h264_driver_init_module);
9367module_exit(ammvdec_h264_driver_remove_module);
9368
9369MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver");
9370MODULE_LICENSE("GPL");
9371
generated by cgit at 2024-05-17 08:42:49 (GMT)