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path: root/drivers/frame_provider/decoder/h265/vh265.c (plain)
blob: 7e2e2583b3ce714b4c63ae0c20691d6a80f8c2c5
1/*
2 * drivers/amlogic/amports/vh265.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/platform_device.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/utils/amstream.h>
31#include <linux/amlogic/media/utils/vformat.h>
32#include <linux/amlogic/media/frame_sync/ptsserv.h>
33#include <linux/amlogic/media/canvas/canvas.h>
34#include <linux/amlogic/media/vfm/vframe.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/mm.h>
41#include <linux/amlogic/tee.h>
42#include "../../../stream_input/amports/amports_priv.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44#include "../utils/decoder_mmu_box.h"
45#include "../utils/decoder_bmmu_box.h"
46#include "../utils/config_parser.h"
47#include "../utils/firmware.h"
48#include "../../../common/chips/decoder_cpu_ver_info.h"
49#include "../utils/vdec_v4l2_buffer_ops.h"
50
51#define CONSTRAIN_MAX_BUF_NUM
52
53#define SWAP_HEVC_UCODE
54#define DETREFILL_ENABLE
55
56#define AGAIN_HAS_THRESHOLD
57/*#define TEST_NO_BUF*/
58#define HEVC_PIC_STRUCT_SUPPORT
59#define MULTI_INSTANCE_SUPPORT
60#define USE_UNINIT_SEMA
61
62 /* .buf_size = 0x100000*16,
63 //4k2k , 0x100000 per buffer */
64 /* 4096x2304 , 0x120000 per buffer */
65#define MPRED_8K_MV_BUF_SIZE (0x120000*4)
66#define MPRED_4K_MV_BUF_SIZE (0x120000)
67#define MPRED_MV_BUF_SIZE (0x40000)
68
69#define MMU_COMPRESS_HEADER_SIZE 0x48000
70#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
71
72#define MAX_FRAME_4K_NUM 0x1200
73#define MAX_FRAME_8K_NUM (0x1200*4)
74
75//#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
76#define H265_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7
77
78#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
79
80#define HEVC_CM_HEADER_START_ADDR 0x3628
81#define HEVC_SAO_MMU_VH1_ADDR 0x363b
82#define HEVC_SAO_MMU_VH0_ADDR 0x363a
83
84#define HEVC_DBLK_CFGB 0x350b
85#define HEVCD_MPP_DECOMP_AXIURG_CTL 0x34c7
86#define SWAP_HEVC_OFFSET (3 * 0x1000)
87
88#define MEM_NAME "codec_265"
89/* #include <mach/am_regs.h> */
90#include <linux/amlogic/media/utils/vdec_reg.h>
91
92#include "../utils/vdec.h"
93#include "../utils/amvdec.h"
94#include <linux/amlogic/media/video_sink/video.h>
95#include <linux/amlogic/media/codec_mm/configs.h>
96
97#define SEND_LMEM_WITH_RPM
98#define SUPPORT_10BIT
99/* #define ERROR_HANDLE_DEBUG */
100
101#ifndef STAT_KTHREAD
102#define STAT_KTHREAD 0x40
103#endif
104
105#ifdef MULTI_INSTANCE_SUPPORT
106#define MAX_DECODE_INSTANCE_NUM 9
107#define MULTI_DRIVER_NAME "ammvdec_h265"
108#endif
109#define DRIVER_NAME "amvdec_h265"
110#define MODULE_NAME "amvdec_h265"
111#define DRIVER_HEADER_NAME "amvdec_h265_header"
112
113#define PUT_INTERVAL (HZ/100)
114#define ERROR_SYSTEM_RESET_COUNT 200
115
116#define PTS_NORMAL 0
117#define PTS_NONE_REF_USE_DURATION 1
118
119#define PTS_MODE_SWITCHING_THRESHOLD 3
120#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
121
122#define DUR2PTS(x) ((x)*90/96)
123
124#define MAX_SIZE_8K (8192 * 4608)
125#define MAX_SIZE_4K (4096 * 2304)
126
127#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
128#define IS_4K_SIZE(w, h) (((w) * (h)) > (1920*1088))
129
130#define SEI_UserDataITU_T_T35 4
131
132static struct semaphore h265_sema;
133
134struct hevc_state_s;
135static int hevc_print(struct hevc_state_s *hevc,
136 int debug_flag, const char *fmt, ...);
137static int hevc_print_cont(struct hevc_state_s *hevc,
138 int debug_flag, const char *fmt, ...);
139static int vh265_vf_states(struct vframe_states *states, void *);
140static struct vframe_s *vh265_vf_peek(void *);
141static struct vframe_s *vh265_vf_get(void *);
142static void vh265_vf_put(struct vframe_s *, void *);
143static int vh265_event_cb(int type, void *data, void *private_data);
144
145static int vh265_stop(struct hevc_state_s *hevc);
146#ifdef MULTI_INSTANCE_SUPPORT
147static int vmh265_stop(struct hevc_state_s *hevc);
148static s32 vh265_init(struct vdec_s *vdec);
149static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask);
150static void reset_process_time(struct hevc_state_s *hevc);
151static void start_process_time(struct hevc_state_s *hevc);
152static void restart_process_time(struct hevc_state_s *hevc);
153static void timeout_process(struct hevc_state_s *hevc);
154#else
155static s32 vh265_init(struct hevc_state_s *hevc);
156#endif
157static void vh265_prot_init(struct hevc_state_s *hevc);
158static int vh265_local_init(struct hevc_state_s *hevc);
159static void vh265_check_timer_func(unsigned long arg);
160static void config_decode_mode(struct hevc_state_s *hevc);
161
162static const char vh265_dec_id[] = "vh265-dev";
163
164#define PROVIDER_NAME "decoder.h265"
165#define MULTI_INSTANCE_PROVIDER_NAME "vdec.h265"
166
167static const struct vframe_operations_s vh265_vf_provider = {
168 .peek = vh265_vf_peek,
169 .get = vh265_vf_get,
170 .put = vh265_vf_put,
171 .event_cb = vh265_event_cb,
172 .vf_states = vh265_vf_states,
173};
174
175static struct vframe_provider_s vh265_vf_prov;
176
177static u32 bit_depth_luma;
178static u32 bit_depth_chroma;
179static u32 video_signal_type;
180
181static int start_decode_buf_level = 0x8000;
182
183static unsigned int decode_timeout_val = 200;
184
185/*data_resend_policy:
186 bit 0, stream base resend data when decoding buf empty
187*/
188static u32 data_resend_policy = 1;
189
190#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
191/*
192static const char * const video_format_names[] = {
193 "component", "PAL", "NTSC", "SECAM",
194 "MAC", "unspecified", "unspecified", "unspecified"
195};
196
197static const char * const color_primaries_names[] = {
198 "unknown", "bt709", "undef", "unknown",
199 "bt470m", "bt470bg", "smpte170m", "smpte240m",
200 "film", "bt2020"
201};
202
203static const char * const transfer_characteristics_names[] = {
204 "unknown", "bt709", "undef", "unknown",
205 "bt470m", "bt470bg", "smpte170m", "smpte240m",
206 "linear", "log100", "log316", "iec61966-2-4",
207 "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
208 "smpte-st-2084", "smpte-st-428"
209};
210
211static const char * const matrix_coeffs_names[] = {
212 "GBR", "bt709", "undef", "unknown",
213 "fcc", "bt470bg", "smpte170m", "smpte240m",
214 "YCgCo", "bt2020nc", "bt2020c"
215};
216*/
217#ifdef SUPPORT_10BIT
218#define HEVC_CM_BODY_START_ADDR 0x3626
219#define HEVC_CM_BODY_LENGTH 0x3627
220#define HEVC_CM_HEADER_LENGTH 0x3629
221#define HEVC_CM_HEADER_OFFSET 0x362b
222#define HEVC_SAO_CTRL9 0x362d
223#define LOSLESS_COMPRESS_MODE
224/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
225/* double_write_mode:
226 * 0, no double write;
227 * 1, 1:1 ratio;
228 * 2, (1/4):(1/4) ratio;
229 * 3, (1/4):(1/4) ratio, with both compressed frame included
230 * 4, (1/2):(1/2) ratio;
231 * 0x10, double write only
232 * 0x100, if > 1080p,use mode 4,else use mode 1;
233 * 0x200, if > 1080p,use mode 2,else use mode 1;
234 * 0x300, if > 720p, use mode 4, else use mode 1;
235 */
236static u32 double_write_mode;
237
238/*#define DECOMP_HEADR_SURGENT*/
239
240static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
241static u32 enable_mem_saving = 1;
242static u32 workaround_enable;
243static u32 force_w_h;
244#endif
245static u32 force_fps;
246static u32 pts_unstable;
247#define H265_DEBUG_BUFMGR 0x01
248#define H265_DEBUG_BUFMGR_MORE 0x02
249#define H265_DEBUG_DETAIL 0x04
250#define H265_DEBUG_REG 0x08
251#define H265_DEBUG_MAN_SEARCH_NAL 0x10
252#define H265_DEBUG_MAN_SKIP_NAL 0x20
253#define H265_DEBUG_DISPLAY_CUR_FRAME 0x40
254#define H265_DEBUG_FORCE_CLK 0x80
255#define H265_DEBUG_SEND_PARAM_WITH_REG 0x100
256#define H265_DEBUG_NO_DISPLAY 0x200
257#define H265_DEBUG_DISCARD_NAL 0x400
258#define H265_DEBUG_OUT_PTS 0x800
259#define H265_DEBUG_DUMP_PIC_LIST 0x1000
260#define H265_DEBUG_PRINT_SEI 0x2000
261#define H265_DEBUG_PIC_STRUCT 0x4000
262#define H265_DEBUG_HAS_AUX_IN_SLICE 0x8000
263#define H265_DEBUG_DIS_LOC_ERROR_PROC 0x10000
264#define H265_DEBUG_DIS_SYS_ERROR_PROC 0x20000
265#define H265_NO_CHANG_DEBUG_FLAG_IN_CODE 0x40000
266#define H265_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
267#define H265_DEBUG_HW_RESET 0x100000
268#define H265_CFG_CANVAS_IN_DECODE 0x200000
269#define H265_DEBUG_DV 0x400000
270#define H265_DEBUG_NO_EOS_SEARCH_DONE 0x800000
271#define H265_DEBUG_NOT_USE_LAST_DISPBUF 0x1000000
272#define H265_DEBUG_IGNORE_CONFORMANCE_WINDOW 0x2000000
273#define H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP 0x4000000
274#ifdef MULTI_INSTANCE_SUPPORT
275#define PRINT_FLAG_ERROR 0x0
276#define IGNORE_PARAM_FROM_CONFIG 0x08000000
277#define PRINT_FRAMEBASE_DATA 0x10000000
278#define PRINT_FLAG_VDEC_STATUS 0x20000000
279#define PRINT_FLAG_VDEC_DETAIL 0x40000000
280#define PRINT_FLAG_V4L_DETAIL 0x80000000
281#endif
282
283#define BUF_POOL_SIZE 32
284#define MAX_BUF_NUM 24
285#define MAX_REF_PIC_NUM 24
286#define MAX_REF_ACTIVE 16
287
288#ifdef MV_USE_FIXED_BUF
289#define BMMU_MAX_BUFFERS (BUF_POOL_SIZE + 1)
290#define VF_BUFFER_IDX(n) (n)
291#define BMMU_WORKSPACE_ID (BUF_POOL_SIZE)
292#else
293#define BMMU_MAX_BUFFERS (BUF_POOL_SIZE + 1 + MAX_REF_PIC_NUM)
294#define VF_BUFFER_IDX(n) (n)
295#define BMMU_WORKSPACE_ID (BUF_POOL_SIZE)
296#define MV_BUFFER_IDX(n) (BUF_POOL_SIZE + 1 + n)
297#endif
298
299#define HEVC_MV_INFO 0x310d
300#define HEVC_QP_INFO 0x3137
301#define HEVC_SKIP_INFO 0x3136
302
303const u32 h265_version = 201602101;
304static u32 debug_mask = 0xffffffff;
305static u32 log_mask;
306static u32 debug;
307static u32 radr;
308static u32 rval;
309static u32 dbg_cmd;
310static u32 dump_nal;
311static u32 dbg_skip_decode_index;
312static u32 endian = 0xff0;
313#ifdef ERROR_HANDLE_DEBUG
314static u32 dbg_nal_skip_flag;
315 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
316static u32 dbg_nal_skip_count;
317#endif
318/*for debug*/
319/*
320 udebug_flag:
321 bit 0, enable ucode print
322 bit 1, enable ucode detail print
323 bit [31:16] not 0, pos to dump lmem
324 bit 2, pop bits to lmem
325 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
326*/
327static u32 udebug_flag;
328/*
329 when udebug_flag[1:0] is not 0
330 udebug_pause_pos not 0,
331 pause position
332*/
333static u32 udebug_pause_pos;
334/*
335 when udebug_flag[1:0] is not 0
336 and udebug_pause_pos is not 0,
337 pause only when DEBUG_REG2 is equal to this val
338*/
339static u32 udebug_pause_val;
340
341static u32 udebug_pause_decode_idx;
342
343static u32 decode_pic_begin;
344static uint slice_parse_begin;
345static u32 step;
346static bool is_reset;
347
348#ifdef CONSTRAIN_MAX_BUF_NUM
349static u32 run_ready_max_vf_only_num;
350static u32 run_ready_display_q_num;
351 /*0: not check
352 0xff: work_pic_num
353 */
354static u32 run_ready_max_buf_num = 0xff;
355#endif
356
357static u32 dynamic_buf_num_margin = 7;
358static u32 buf_alloc_width;
359static u32 buf_alloc_height;
360
361static u32 max_buf_num = 16;
362static u32 buf_alloc_size;
363/*static u32 re_config_pic_flag;*/
364/*
365 *bit[0]: 0,
366 *bit[1]: 0, always release cma buffer when stop
367 *bit[1]: 1, never release cma buffer when stop
368 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
369 *do not release cma buffer is blackout is not 1
370 *
371 *bit[2]: 0, when start decoding, check current displayed buffer
372 * (only for buffer decoded by h265) if blackout is 0
373 * 1, do not check current displayed buffer
374 *
375 *bit[3]: 1, if blackout is not 1, do not release current
376 * displayed cma buffer always.
377 */
378/* set to 1 for fast play;
379 * set to 8 for other case of "keep last frame"
380 */
381static u32 buffer_mode = 1;
382
383/* buffer_mode_dbg: debug only*/
384static u32 buffer_mode_dbg = 0xffff0000;
385/**/
386/*
387 *bit[1:0]PB_skip_mode: 0, start decoding at begin;
388 *1, start decoding after first I;
389 *2, only decode and display none error picture;
390 *3, start decoding and display after IDR,etc
391 *bit[31:16] PB_skip_count_after_decoding (decoding but not display),
392 *only for mode 0 and 1.
393 */
394static u32 nal_skip_policy = 2;
395
396/*
397 *bit 0, 1: only display I picture;
398 *bit 1, 1: only decode I picture;
399 */
400static u32 i_only_flag;
401
402/*
403bit 0, fast output first I picture
404*/
405static u32 fast_output_enable = 1;
406
407static u32 frmbase_cont_bitlevel = 0x60;
408
409/*
410use_cma: 1, use both reserver memory and cma for buffers
4112, only use cma for buffers
412*/
413static u32 use_cma = 2;
414
415#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
416static u32 prefix_aux_buf_size = (16 * 1024);
417static u32 suffix_aux_buf_size;
418
419static u32 max_decoding_time;
420/*
421 *error handling
422 */
423/*error_handle_policy:
424 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
425 *1, skip error_skip_nal_count nals before error recovery;
426 *bit 1 (valid only when bit0 == 1):
427 *1, wait vps/sps/pps after error recovery;
428 *bit 2 (valid only when bit0 == 0):
429 *0, auto search after error recovery (hevc_recover() called);
430 *1, manual search after error recovery
431 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
432 *
433 *bit 4: 0, set error_mark after reset/recover
434 * 1, do not set error_mark after reset/recover
435 *bit 5: 0, check total lcu for every picture
436 * 1, do not check total lcu
437 *bit 6: 0, do not check head error
438 * 1, check head error
439 *
440 */
441
442static u32 error_handle_policy;
443static u32 error_skip_nal_count = 6;
444static u32 error_handle_threshold = 30;
445static u32 error_handle_nal_skip_threshold = 10;
446static u32 error_handle_system_threshold = 30;
447static u32 interlace_enable = 1;
448static u32 fr_hint_status;
449
450 /*
451 *parser_sei_enable:
452 * bit 0, sei;
453 * bit 1, sei_suffix (fill aux buf)
454 * bit 2, fill sei to aux buf (when bit 0 is 1)
455 * bit 8, debug flag
456 */
457static u32 parser_sei_enable;
458#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
459static u32 parser_dolby_vision_enable = 1;
460static u32 dolby_meta_with_el;
461static u32 dolby_el_flush_th = 2;
462#endif
463/* this is only for h265 mmu enable */
464
465static u32 mmu_enable = 1;
466static u32 mmu_enable_force;
467static u32 work_buf_size;
468static unsigned int force_disp_pic_index;
469static unsigned int disp_vframe_valve_level;
470static int pre_decode_buf_level = 0x1000;
471static unsigned int pic_list_debug;
472
473
474#ifdef MULTI_INSTANCE_SUPPORT
475static unsigned int max_decode_instance_num
476 = MAX_DECODE_INSTANCE_NUM;
477static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
478static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
479static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
480static unsigned int max_get_frame_interval[MAX_DECODE_INSTANCE_NUM];
481static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
482static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
483static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
484static unsigned int ref_frame_mark_flag[MAX_DECODE_INSTANCE_NUM] =
485{1, 1, 1, 1, 1, 1, 1, 1, 1};
486
487#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
488static unsigned char get_idx(struct hevc_state_s *hevc);
489#endif
490
491#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
492static u32 dv_toggle_prov_name;
493
494static u32 dv_debug;
495
496static u32 force_bypass_dvenl;
497#endif
498#endif
499
500
501#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
502#define get_dbg_flag(hevc) ((debug_mask & (1 << hevc->index)) ? debug : 0)
503#define get_dbg_flag2(hevc) ((debug_mask & (1 << get_idx(hevc))) ? debug : 0)
504#define is_log_enable(hevc) ((log_mask & (1 << hevc->index)) ? 1 : 0)
505#else
506#define get_dbg_flag(hevc) debug
507#define get_dbg_flag2(hevc) debug
508#define is_log_enable(hevc) (log_mask ? 1 : 0)
509#define get_valid_double_write_mode(hevc) double_write_mode
510#define get_buf_alloc_width(hevc) buf_alloc_width
511#define get_buf_alloc_height(hevc) buf_alloc_height
512#define get_dynamic_buf_num_margin(hevc) dynamic_buf_num_margin
513#endif
514#define get_buffer_mode(hevc) buffer_mode
515
516
517DEFINE_SPINLOCK(lock);
518struct task_struct *h265_task = NULL;
519#undef DEBUG_REG
520#ifdef DEBUG_REG
521void WRITE_VREG_DBG(unsigned adr, unsigned val)
522{
523 if (debug & H265_DEBUG_REG)
524 pr_info("%s(%x, %x)\n", __func__, adr, val);
525 WRITE_VREG(adr, val);
526}
527
528#undef WRITE_VREG
529#define WRITE_VREG WRITE_VREG_DBG
530#endif
531
532static DEFINE_MUTEX(vh265_mutex);
533
534static DEFINE_MUTEX(vh265_log_mutex);
535
536static struct vdec_info *gvs;
537
538static u32 without_display_mode;
539
540/**************************************************
541 *
542 *h265 buffer management include
543 *
544 ***************************************************
545 */
546enum NalUnitType {
547 NAL_UNIT_CODED_SLICE_TRAIL_N = 0, /* 0 */
548 NAL_UNIT_CODED_SLICE_TRAIL_R, /* 1 */
549
550 NAL_UNIT_CODED_SLICE_TSA_N, /* 2 */
551 /* Current name in the spec: TSA_R */
552 NAL_UNIT_CODED_SLICE_TLA, /* 3 */
553
554 NAL_UNIT_CODED_SLICE_STSA_N, /* 4 */
555 NAL_UNIT_CODED_SLICE_STSA_R, /* 5 */
556
557 NAL_UNIT_CODED_SLICE_RADL_N, /* 6 */
558 /* Current name in the spec: RADL_R */
559 NAL_UNIT_CODED_SLICE_DLP, /* 7 */
560
561 NAL_UNIT_CODED_SLICE_RASL_N, /* 8 */
562 /* Current name in the spec: RASL_R */
563 NAL_UNIT_CODED_SLICE_TFD, /* 9 */
564
565 NAL_UNIT_RESERVED_10,
566 NAL_UNIT_RESERVED_11,
567 NAL_UNIT_RESERVED_12,
568 NAL_UNIT_RESERVED_13,
569 NAL_UNIT_RESERVED_14,
570 NAL_UNIT_RESERVED_15,
571
572 /* Current name in the spec: BLA_W_LP */
573 NAL_UNIT_CODED_SLICE_BLA, /* 16 */
574 /* Current name in the spec: BLA_W_DLP */
575 NAL_UNIT_CODED_SLICE_BLANT, /* 17 */
576 NAL_UNIT_CODED_SLICE_BLA_N_LP, /* 18 */
577 /* Current name in the spec: IDR_W_DLP */
578 NAL_UNIT_CODED_SLICE_IDR, /* 19 */
579 NAL_UNIT_CODED_SLICE_IDR_N_LP, /* 20 */
580 NAL_UNIT_CODED_SLICE_CRA, /* 21 */
581 NAL_UNIT_RESERVED_22,
582 NAL_UNIT_RESERVED_23,
583
584 NAL_UNIT_RESERVED_24,
585 NAL_UNIT_RESERVED_25,
586 NAL_UNIT_RESERVED_26,
587 NAL_UNIT_RESERVED_27,
588 NAL_UNIT_RESERVED_28,
589 NAL_UNIT_RESERVED_29,
590 NAL_UNIT_RESERVED_30,
591 NAL_UNIT_RESERVED_31,
592
593 NAL_UNIT_VPS, /* 32 */
594 NAL_UNIT_SPS, /* 33 */
595 NAL_UNIT_PPS, /* 34 */
596 NAL_UNIT_ACCESS_UNIT_DELIMITER, /* 35 */
597 NAL_UNIT_EOS, /* 36 */
598 NAL_UNIT_EOB, /* 37 */
599 NAL_UNIT_FILLER_DATA, /* 38 */
600 NAL_UNIT_SEI, /* 39 Prefix SEI */
601 NAL_UNIT_SEI_SUFFIX, /* 40 Suffix SEI */
602 NAL_UNIT_RESERVED_41,
603 NAL_UNIT_RESERVED_42,
604 NAL_UNIT_RESERVED_43,
605 NAL_UNIT_RESERVED_44,
606 NAL_UNIT_RESERVED_45,
607 NAL_UNIT_RESERVED_46,
608 NAL_UNIT_RESERVED_47,
609 NAL_UNIT_UNSPECIFIED_48,
610 NAL_UNIT_UNSPECIFIED_49,
611 NAL_UNIT_UNSPECIFIED_50,
612 NAL_UNIT_UNSPECIFIED_51,
613 NAL_UNIT_UNSPECIFIED_52,
614 NAL_UNIT_UNSPECIFIED_53,
615 NAL_UNIT_UNSPECIFIED_54,
616 NAL_UNIT_UNSPECIFIED_55,
617 NAL_UNIT_UNSPECIFIED_56,
618 NAL_UNIT_UNSPECIFIED_57,
619 NAL_UNIT_UNSPECIFIED_58,
620 NAL_UNIT_UNSPECIFIED_59,
621 NAL_UNIT_UNSPECIFIED_60,
622 NAL_UNIT_UNSPECIFIED_61,
623 NAL_UNIT_UNSPECIFIED_62,
624 NAL_UNIT_UNSPECIFIED_63,
625 NAL_UNIT_INVALID,
626};
627
628/* --------------------------------------------------- */
629/* Amrisc Software Interrupt */
630/* --------------------------------------------------- */
631#define AMRISC_STREAM_EMPTY_REQ 0x01
632#define AMRISC_PARSER_REQ 0x02
633#define AMRISC_MAIN_REQ 0x04
634
635/* --------------------------------------------------- */
636/* HEVC_DEC_STATUS define */
637/* --------------------------------------------------- */
638#define HEVC_DEC_IDLE 0x0
639#define HEVC_NAL_UNIT_VPS 0x1
640#define HEVC_NAL_UNIT_SPS 0x2
641#define HEVC_NAL_UNIT_PPS 0x3
642#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT 0x4
643#define HEVC_CODED_SLICE_SEGMENT_DAT 0x5
644#define HEVC_SLICE_DECODING 0x6
645#define HEVC_NAL_UNIT_SEI 0x7
646#define HEVC_SLICE_SEGMENT_DONE 0x8
647#define HEVC_NAL_SEARCH_DONE 0x9
648#define HEVC_DECPIC_DATA_DONE 0xa
649#define HEVC_DECPIC_DATA_ERROR 0xb
650#define HEVC_SEI_DAT 0xc
651#define HEVC_SEI_DAT_DONE 0xd
652#define HEVC_NAL_DECODE_DONE 0xe
653#define HEVC_OVER_DECODE 0xf
654
655#define HEVC_DATA_REQUEST 0x12
656
657#define HEVC_DECODE_BUFEMPTY 0x20
658#define HEVC_DECODE_TIMEOUT 0x21
659#define HEVC_SEARCH_BUFEMPTY 0x22
660#define HEVC_DECODE_OVER_SIZE 0x23
661#define HEVC_DECODE_BUFEMPTY2 0x24
662#define HEVC_FIND_NEXT_PIC_NAL 0x50
663#define HEVC_FIND_NEXT_DVEL_NAL 0x51
664
665#define HEVC_DUMP_LMEM 0x30
666
667#define HEVC_4k2k_60HZ_NOT_SUPPORT 0x80
668#define HEVC_DISCARD_NAL 0xf0
669#define HEVC_ACTION_DEC_CONT 0xfd
670#define HEVC_ACTION_ERROR 0xfe
671#define HEVC_ACTION_DONE 0xff
672
673/* --------------------------------------------------- */
674/* Include "parser_cmd.h" */
675/* --------------------------------------------------- */
676#define PARSER_CMD_SKIP_CFG_0 0x0000090b
677
678#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
679
680#define PARSER_CMD_SKIP_CFG_2 0x001b1910
681
682#define PARSER_CMD_NUMBER 37
683
684/**************************************************
685 *
686 *h265 buffer management
687 *
688 ***************************************************
689 */
690/* #define BUFFER_MGR_ONLY */
691/* #define CONFIG_HEVC_CLK_FORCED_ON */
692/* #define ENABLE_SWAP_TEST */
693#define MCRCC_ENABLE
694#define INVALID_POC 0x80000000
695
696#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
697#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
698#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
699#define HEVC_VPS_BUFFER HEVC_ASSIST_SCRATCH_3
700#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4
701#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
702#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
703#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
704#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
705#define HEVC_sao_mem_unit HEVC_ASSIST_SCRATCH_9
706#define HEVC_SAO_ABV HEVC_ASSIST_SCRATCH_A
707#define HEVC_sao_vb_size HEVC_ASSIST_SCRATCH_B
708#define HEVC_SAO_VB HEVC_ASSIST_SCRATCH_C
709#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
710#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
711#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
712#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
713#ifdef ENABLE_SWAP_TEST
714#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
715#endif
716
717/*#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M*/
718/*#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N*/
719#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
720 /*do not define ENABLE_SWAP_TEST*/
721#define HEVC_AUX_ADR HEVC_ASSIST_SCRATCH_L
722#define HEVC_AUX_DATA_SIZE HEVC_ASSIST_SCRATCH_M
723
724#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
725#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
726/*
727 *ucode parser/search control
728 *bit 0: 0, header auto parse; 1, header manual parse
729 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
730 *bit [3:2]: valid when bit1==0;
731 *0, auto skip nal before first vps/sps/pps/idr;
732 *1, auto skip nal before first vps/sps/pps
733 *2, auto skip nal before first vps/sps/pps,
734 * and not decode until the first I slice (with slice address of 0)
735 *
736 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
737 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
738 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
739 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
740 *bit [17]: for NAL_SEI when bit0 is 0:
741 * 0, do not parse/fetch SEI in ucode;
742 * 1, parse/fetch SEI in ucode
743 *bit [18]: for NAL_SEI_SUFFIX when bit0 is 0:
744 * 0, do not fetch NAL_SEI_SUFFIX to aux buf;
745 * 1, fetch NAL_SEL_SUFFIX data to aux buf
746 *bit [19]:
747 * 0, parse NAL_SEI in ucode
748 * 1, fetch NAL_SEI to aux buf
749 *bit [20]: for DOLBY_VISION_META
750 * 0, do not fetch DOLBY_VISION_META to aux buf
751 * 1, fetch DOLBY_VISION_META to aux buf
752 */
753#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
754 /*read only*/
755#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
756 /*
757 [15 : 8] rps_set_id
758 [7 : 0] start_decoding_flag
759 */
760#define HEVC_DECODE_INFO HEVC_ASSIST_SCRATCH_1
761 /*set before start decoder*/
762#define HEVC_DECODE_MODE HEVC_ASSIST_SCRATCH_J
763#define HEVC_DECODE_MODE2 HEVC_ASSIST_SCRATCH_H
764#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
765
766#define DECODE_MODE_SINGLE 0x0
767#define DECODE_MODE_MULTI_FRAMEBASE 0x1
768#define DECODE_MODE_MULTI_STREAMBASE 0x2
769#define DECODE_MODE_MULTI_DVBAL 0x3
770#define DECODE_MODE_MULTI_DVENL 0x4
771
772#define MAX_INT 0x7FFFFFFF
773
774#define RPM_BEGIN 0x100
775#define modification_list_cur 0x148
776#define RPM_END 0x180
777
778#define RPS_USED_BIT 14
779/* MISC_FLAG0 */
780#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT 0
781#define PCM_ENABLE_FLAG_BIT 1
782#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT 2
783#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 3
784#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT 4
785#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 5
786#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT 6
787#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 7
788#define SLICE_SAO_LUMA_FLAG_BIT 8
789#define SLICE_SAO_CHROMA_FLAG_BIT 9
790#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10
791
792union param_u {
793 struct {
794 unsigned short data[RPM_END - RPM_BEGIN];
795 } l;
796 struct {
797 /* from ucode lmem, do not change this struct */
798 unsigned short CUR_RPS[0x10];
799 unsigned short num_ref_idx_l0_active;
800 unsigned short num_ref_idx_l1_active;
801 unsigned short slice_type;
802 unsigned short slice_temporal_mvp_enable_flag;
803 unsigned short dependent_slice_segment_flag;
804 unsigned short slice_segment_address;
805 unsigned short num_title_rows_minus1;
806 unsigned short pic_width_in_luma_samples;
807 unsigned short pic_height_in_luma_samples;
808 unsigned short log2_min_coding_block_size_minus3;
809 unsigned short log2_diff_max_min_coding_block_size;
810 unsigned short log2_max_pic_order_cnt_lsb_minus4;
811 unsigned short POClsb;
812 unsigned short collocated_from_l0_flag;
813 unsigned short collocated_ref_idx;
814 unsigned short log2_parallel_merge_level;
815 unsigned short five_minus_max_num_merge_cand;
816 unsigned short sps_num_reorder_pics_0;
817 unsigned short modification_flag;
818 unsigned short tiles_enabled_flag;
819 unsigned short num_tile_columns_minus1;
820 unsigned short num_tile_rows_minus1;
821 unsigned short tile_width[8];
822 unsigned short tile_height[8];
823 unsigned short misc_flag0;
824 unsigned short pps_beta_offset_div2;
825 unsigned short pps_tc_offset_div2;
826 unsigned short slice_beta_offset_div2;
827 unsigned short slice_tc_offset_div2;
828 unsigned short pps_cb_qp_offset;
829 unsigned short pps_cr_qp_offset;
830 unsigned short first_slice_segment_in_pic_flag;
831 unsigned short m_temporalId;
832 unsigned short m_nalUnitType;
833
834 unsigned short vui_num_units_in_tick_hi;
835 unsigned short vui_num_units_in_tick_lo;
836 unsigned short vui_time_scale_hi;
837 unsigned short vui_time_scale_lo;
838 unsigned short bit_depth;
839 unsigned short profile_etc;
840 unsigned short sei_frame_field_info;
841 unsigned short video_signal_type;
842 unsigned short modification_list[0x20];
843 unsigned short conformance_window_flag;
844 unsigned short conf_win_left_offset;
845 unsigned short conf_win_right_offset;
846 unsigned short conf_win_top_offset;
847 unsigned short conf_win_bottom_offset;
848 unsigned short chroma_format_idc;
849 unsigned short color_description;
850 unsigned short aspect_ratio_idc;
851 unsigned short sar_width;
852 unsigned short sar_height;
853 unsigned short sps_max_dec_pic_buffering_minus1_0;
854 } p;
855};
856
857#define RPM_BUF_SIZE (0x80*2)
858/* non mmu mode lmem size : 0x400, mmu mode : 0x500*/
859#define LMEM_BUF_SIZE (0x500 * 2)
860
861struct buff_s {
862 u32 buf_start;
863 u32 buf_size;
864 u32 buf_end;
865};
866
867struct BuffInfo_s {
868 u32 max_width;
869 u32 max_height;
870 unsigned int start_adr;
871 unsigned int end_adr;
872 struct buff_s ipp;
873 struct buff_s sao_abv;
874 struct buff_s sao_vb;
875 struct buff_s short_term_rps;
876 struct buff_s vps;
877 struct buff_s sps;
878 struct buff_s pps;
879 struct buff_s sao_up;
880 struct buff_s swap_buf;
881 struct buff_s swap_buf2;
882 struct buff_s scalelut;
883 struct buff_s dblk_para;
884 struct buff_s dblk_data;
885 struct buff_s dblk_data2;
886 struct buff_s mmu_vbh;
887 struct buff_s cm_header;
888 struct buff_s mpred_above;
889#ifdef MV_USE_FIXED_BUF
890 struct buff_s mpred_mv;
891#endif
892 struct buff_s rpm;
893 struct buff_s lmem;
894};
895#define WORK_BUF_SPEC_NUM 3
896static struct BuffInfo_s amvh265_workbuff_spec[WORK_BUF_SPEC_NUM] = {
897 {
898 /* 8M bytes */
899 .max_width = 1920,
900 .max_height = 1088,
901 .ipp = {
902 /* IPP work space calculation :
903 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
904 */
905 .buf_size = 0x4000,
906 },
907 .sao_abv = {
908 .buf_size = 0x30000,
909 },
910 .sao_vb = {
911 .buf_size = 0x30000,
912 },
913 .short_term_rps = {
914 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
915 * total 64x16x2 = 2048 bytes (0x800)
916 */
917 .buf_size = 0x800,
918 },
919 .vps = {
920 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
921 * total 0x0800 bytes
922 */
923 .buf_size = 0x800,
924 },
925 .sps = {
926 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
927 * total 0x0800 bytes
928 */
929 .buf_size = 0x800,
930 },
931 .pps = {
932 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
933 * total 0x2000 bytes
934 */
935 .buf_size = 0x2000,
936 },
937 .sao_up = {
938 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
939 * each has 16 bytes total 0x2800 bytes
940 */
941 .buf_size = 0x2800,
942 },
943 .swap_buf = {
944 /* 256cyclex64bit = 2K bytes 0x800
945 * (only 144 cycles valid)
946 */
947 .buf_size = 0x800,
948 },
949 .swap_buf2 = {
950 .buf_size = 0x800,
951 },
952 .scalelut = {
953 /* support up to 32 SCALELUT 1024x32 =
954 * 32Kbytes (0x8000)
955 */
956 .buf_size = 0x8000,
957 },
958 .dblk_para = {
959#ifdef SUPPORT_10BIT
960 .buf_size = 0x40000,
961#else
962 /* DBLK -> Max 256(4096/16) LCU, each para
963 *512bytes(total:0x20000), data 1024bytes(total:0x40000)
964 */
965 .buf_size = 0x20000,
966#endif
967 },
968 .dblk_data = {
969 .buf_size = 0x40000,
970 },
971 .dblk_data2 = {
972 .buf_size = 0x40000,
973 }, /*dblk data for adapter*/
974 .mmu_vbh = {
975 .buf_size = 0x5000, /*2*16*2304/4, 4K*/
976 },
977#if 0
978 .cm_header = {/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
979 .buf_size = MMU_COMPRESS_HEADER_SIZE *
980 (MAX_REF_PIC_NUM + 1),
981 },
982#endif
983 .mpred_above = {
984 .buf_size = 0x8000,
985 },
986#ifdef MV_USE_FIXED_BUF
987 .mpred_mv = {/* 1080p, 0x40000 per buffer */
988 .buf_size = 0x40000 * MAX_REF_PIC_NUM,
989 },
990#endif
991 .rpm = {
992 .buf_size = RPM_BUF_SIZE,
993 },
994 .lmem = {
995 .buf_size = 0x500 * 2,
996 }
997 },
998 {
999 .max_width = 4096,
1000 .max_height = 2048,
1001 .ipp = {
1002 /* IPP work space calculation :
1003 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
1004 */
1005 .buf_size = 0x4000,
1006 },
1007 .sao_abv = {
1008 .buf_size = 0x30000,
1009 },
1010 .sao_vb = {
1011 .buf_size = 0x30000,
1012 },
1013 .short_term_rps = {
1014 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1015 * total 64x16x2 = 2048 bytes (0x800)
1016 */
1017 .buf_size = 0x800,
1018 },
1019 .vps = {
1020 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
1021 * total 0x0800 bytes
1022 */
1023 .buf_size = 0x800,
1024 },
1025 .sps = {
1026 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1027 * total 0x0800 bytes
1028 */
1029 .buf_size = 0x800,
1030 },
1031 .pps = {
1032 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1033 * total 0x2000 bytes
1034 */
1035 .buf_size = 0x2000,
1036 },
1037 .sao_up = {
1038 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
1039 * each has 16 bytes total 0x2800 bytes
1040 */
1041 .buf_size = 0x2800,
1042 },
1043 .swap_buf = {
1044 /* 256cyclex64bit = 2K bytes 0x800
1045 * (only 144 cycles valid)
1046 */
1047 .buf_size = 0x800,
1048 },
1049 .swap_buf2 = {
1050 .buf_size = 0x800,
1051 },
1052 .scalelut = {
1053 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
1054 * (0x8000)
1055 */
1056 .buf_size = 0x8000,
1057 },
1058 .dblk_para = {
1059 /* DBLK -> Max 256(4096/16) LCU, each para
1060 * 512bytes(total:0x20000),
1061 * data 1024bytes(total:0x40000)
1062 */
1063 .buf_size = 0x20000,
1064 },
1065 .dblk_data = {
1066 .buf_size = 0x80000,
1067 },
1068 .dblk_data2 = {
1069 .buf_size = 0x80000,
1070 }, /*dblk data for adapter*/
1071 .mmu_vbh = {
1072 .buf_size = 0x5000, /*2*16*2304/4, 4K*/
1073 },
1074#if 0
1075 .cm_header = {/*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
1076 .buf_size = MMU_COMPRESS_HEADER_SIZE *
1077 (MAX_REF_PIC_NUM + 1),
1078 },
1079#endif
1080 .mpred_above = {
1081 .buf_size = 0x8000,
1082 },
1083#ifdef MV_USE_FIXED_BUF
1084 .mpred_mv = {
1085 /* .buf_size = 0x100000*16,
1086 //4k2k , 0x100000 per buffer */
1087 /* 4096x2304 , 0x120000 per buffer */
1088 .buf_size = MPRED_4K_MV_BUF_SIZE * MAX_REF_PIC_NUM,
1089 },
1090#endif
1091 .rpm = {
1092 .buf_size = RPM_BUF_SIZE,
1093 },
1094 .lmem = {
1095 .buf_size = 0x500 * 2,
1096 }
1097 },
1098
1099 {
1100 .max_width = 4096*2,
1101 .max_height = 2048*2,
1102 .ipp = {
1103 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
1104 .buf_size = 0x4000*2,
1105 },
1106 .sao_abv = {
1107 .buf_size = 0x30000*2,
1108 },
1109 .sao_vb = {
1110 .buf_size = 0x30000*2,
1111 },
1112 .short_term_rps = {
1113 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
1114 .buf_size = 0x800,
1115 },
1116 .vps = {
1117 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
1118 .buf_size = 0x800,
1119 },
1120 .sps = {
1121 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
1122 .buf_size = 0x800,
1123 },
1124 .pps = {
1125 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
1126 .buf_size = 0x2000,
1127 },
1128 .sao_up = {
1129 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
1130 .buf_size = 0x2800*2,
1131 },
1132 .swap_buf = {
1133 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
1134 .buf_size = 0x800,
1135 },
1136 .swap_buf2 = {
1137 .buf_size = 0x800,
1138 },
1139 .scalelut = {
1140 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
1141 .buf_size = 0x8000*2,
1142 },
1143 .dblk_para = {.buf_size = 0x40000*2, }, // dblk parameter
1144 .dblk_data = {.buf_size = 0x80000*2, }, // dblk data for left/top
1145 .dblk_data2 = {.buf_size = 0x80000*2, }, // dblk data for adapter
1146 .mmu_vbh = {
1147 .buf_size = 0x5000*2, //2*16*2304/4, 4K
1148 },
1149#if 0
1150 .cm_header = {
1151 .buf_size = MMU_COMPRESS_8K_HEADER_SIZE *
1152 MAX_REF_PIC_NUM, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1153 },
1154#endif
1155 .mpred_above = {
1156 .buf_size = 0x8000*2,
1157 },
1158#ifdef MV_USE_FIXED_BUF
1159 .mpred_mv = {
1160 .buf_size = MPRED_8K_MV_BUF_SIZE * MAX_REF_PIC_NUM, //4k2k , 0x120000 per buffer
1161 },
1162#endif
1163 .rpm = {
1164 .buf_size = RPM_BUF_SIZE,
1165 },
1166 .lmem = {
1167 .buf_size = 0x500 * 2,
1168 },
1169 }
1170};
1171
1172static void init_buff_spec(struct hevc_state_s *hevc,
1173 struct BuffInfo_s *buf_spec)
1174{
1175 buf_spec->ipp.buf_start = buf_spec->start_adr;
1176 buf_spec->sao_abv.buf_start =
1177 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
1178
1179 buf_spec->sao_vb.buf_start =
1180 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
1181 buf_spec->short_term_rps.buf_start =
1182 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
1183 buf_spec->vps.buf_start =
1184 buf_spec->short_term_rps.buf_start +
1185 buf_spec->short_term_rps.buf_size;
1186 buf_spec->sps.buf_start =
1187 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
1188 buf_spec->pps.buf_start =
1189 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
1190 buf_spec->sao_up.buf_start =
1191 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
1192 buf_spec->swap_buf.buf_start =
1193 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
1194 buf_spec->swap_buf2.buf_start =
1195 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
1196 buf_spec->scalelut.buf_start =
1197 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
1198 buf_spec->dblk_para.buf_start =
1199 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
1200 buf_spec->dblk_data.buf_start =
1201 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
1202 buf_spec->dblk_data2.buf_start =
1203 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
1204 buf_spec->mmu_vbh.buf_start =
1205 buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1206 buf_spec->mpred_above.buf_start =
1207 buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
1208#ifdef MV_USE_FIXED_BUF
1209 buf_spec->mpred_mv.buf_start =
1210 buf_spec->mpred_above.buf_start +
1211 buf_spec->mpred_above.buf_size;
1212
1213 buf_spec->rpm.buf_start =
1214 buf_spec->mpred_mv.buf_start +
1215 buf_spec->mpred_mv.buf_size;
1216#else
1217 buf_spec->rpm.buf_start =
1218 buf_spec->mpred_above.buf_start +
1219 buf_spec->mpred_above.buf_size;
1220#endif
1221 buf_spec->lmem.buf_start =
1222 buf_spec->rpm.buf_start +
1223 buf_spec->rpm.buf_size;
1224 buf_spec->end_adr =
1225 buf_spec->lmem.buf_start +
1226 buf_spec->lmem.buf_size;
1227
1228 if (hevc && get_dbg_flag2(hevc)) {
1229 hevc_print(hevc, 0,
1230 "%s workspace (%x %x) size = %x\n", __func__,
1231 buf_spec->start_adr, buf_spec->end_adr,
1232 buf_spec->end_adr - buf_spec->start_adr);
1233
1234 hevc_print(hevc, 0,
1235 "ipp.buf_start :%x\n",
1236 buf_spec->ipp.buf_start);
1237 hevc_print(hevc, 0,
1238 "sao_abv.buf_start :%x\n",
1239 buf_spec->sao_abv.buf_start);
1240 hevc_print(hevc, 0,
1241 "sao_vb.buf_start :%x\n",
1242 buf_spec->sao_vb.buf_start);
1243 hevc_print(hevc, 0,
1244 "short_term_rps.buf_start :%x\n",
1245 buf_spec->short_term_rps.buf_start);
1246 hevc_print(hevc, 0,
1247 "vps.buf_start :%x\n",
1248 buf_spec->vps.buf_start);
1249 hevc_print(hevc, 0,
1250 "sps.buf_start :%x\n",
1251 buf_spec->sps.buf_start);
1252 hevc_print(hevc, 0,
1253 "pps.buf_start :%x\n",
1254 buf_spec->pps.buf_start);
1255 hevc_print(hevc, 0,
1256 "sao_up.buf_start :%x\n",
1257 buf_spec->sao_up.buf_start);
1258 hevc_print(hevc, 0,
1259 "swap_buf.buf_start :%x\n",
1260 buf_spec->swap_buf.buf_start);
1261 hevc_print(hevc, 0,
1262 "swap_buf2.buf_start :%x\n",
1263 buf_spec->swap_buf2.buf_start);
1264 hevc_print(hevc, 0,
1265 "scalelut.buf_start :%x\n",
1266 buf_spec->scalelut.buf_start);
1267 hevc_print(hevc, 0,
1268 "dblk_para.buf_start :%x\n",
1269 buf_spec->dblk_para.buf_start);
1270 hevc_print(hevc, 0,
1271 "dblk_data.buf_start :%x\n",
1272 buf_spec->dblk_data.buf_start);
1273 hevc_print(hevc, 0,
1274 "dblk_data2.buf_start :%x\n",
1275 buf_spec->dblk_data2.buf_start);
1276 hevc_print(hevc, 0,
1277 "mpred_above.buf_start :%x\n",
1278 buf_spec->mpred_above.buf_start);
1279#ifdef MV_USE_FIXED_BUF
1280 hevc_print(hevc, 0,
1281 "mpred_mv.buf_start :%x\n",
1282 buf_spec->mpred_mv.buf_start);
1283#endif
1284 if ((get_dbg_flag2(hevc)
1285 &
1286 H265_DEBUG_SEND_PARAM_WITH_REG)
1287 == 0) {
1288 hevc_print(hevc, 0,
1289 "rpm.buf_start :%x\n",
1290 buf_spec->rpm.buf_start);
1291 }
1292 }
1293
1294}
1295
1296enum SliceType {
1297 B_SLICE,
1298 P_SLICE,
1299 I_SLICE
1300};
1301
1302/*USE_BUF_BLOCK*/
1303struct BUF_s {
1304 unsigned long start_adr;
1305 unsigned int size;
1306 int used_flag;
1307 unsigned int y_size;
1308 ulong v4l_ref_buf_addr;
1309} /*BUF_t */;
1310
1311/* level 6, 6.1 maximum slice number is 800; other is 200 */
1312#define MAX_SLICE_NUM 800
1313struct PIC_s {
1314 int index;
1315 int scatter_alloc;
1316 int BUF_index;
1317 int mv_buf_index;
1318 int POC;
1319 int decode_idx;
1320 int slice_type;
1321 int RefNum_L0;
1322 int RefNum_L1;
1323 int num_reorder_pic;
1324 int stream_offset;
1325 unsigned char referenced;
1326 unsigned char output_mark;
1327 unsigned char recon_mark;
1328 unsigned char output_ready;
1329 unsigned char error_mark;
1330 /**/ int slice_idx;
1331 int m_aiRefPOCList0[MAX_SLICE_NUM][16];
1332 int m_aiRefPOCList1[MAX_SLICE_NUM][16];
1333 /*buffer */
1334 unsigned int header_adr;
1335#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
1336 unsigned char dv_enhance_exist;
1337#endif
1338 char *aux_data_buf;
1339 int aux_data_size;
1340 unsigned long cma_alloc_addr;
1341 struct page *alloc_pages;
1342 unsigned int mpred_mv_wr_start_addr;
1343 unsigned int mc_y_adr;
1344 unsigned int mc_u_v_adr;
1345#ifdef SUPPORT_10BIT
1346 /*unsigned int comp_body_size;*/
1347 unsigned int dw_y_adr;
1348 unsigned int dw_u_v_adr;
1349#endif
1350 int mc_canvas_y;
1351 int mc_canvas_u_v;
1352 int width;
1353 int height;
1354
1355 int y_canvas_index;
1356 int uv_canvas_index;
1357#ifdef MULTI_INSTANCE_SUPPORT
1358 struct canvas_config_s canvas_config[2];
1359#endif
1360#ifdef SUPPORT_10BIT
1361 int mem_saving_mode;
1362 u32 bit_depth_luma;
1363 u32 bit_depth_chroma;
1364#endif
1365#ifdef LOSLESS_COMPRESS_MODE
1366 unsigned int losless_comp_body_size;
1367#endif
1368 unsigned char pic_struct;
1369 int vf_ref;
1370
1371 u32 pts;
1372 u64 pts64;
1373 u64 timestamp;
1374
1375 u32 aspect_ratio_idc;
1376 u32 sar_width;
1377 u32 sar_height;
1378 u32 double_write_mode;
1379 u32 video_signal_type;
1380 unsigned short conformance_window_flag;
1381 unsigned short conf_win_left_offset;
1382 unsigned short conf_win_right_offset;
1383 unsigned short conf_win_top_offset;
1384 unsigned short conf_win_bottom_offset;
1385 unsigned short chroma_format_idc;
1386
1387 /* picture qos infomation*/
1388 int max_qp;
1389 int avg_qp;
1390 int min_qp;
1391 int max_skip;
1392 int avg_skip;
1393 int min_skip;
1394 int max_mv;
1395 int min_mv;
1396 int avg_mv;
1397} /*PIC_t */;
1398
1399#define MAX_TILE_COL_NUM 10
1400#define MAX_TILE_ROW_NUM 20
1401struct tile_s {
1402 int width;
1403 int height;
1404 int start_cu_x;
1405 int start_cu_y;
1406
1407 unsigned int sao_vb_start_addr;
1408 unsigned int sao_abv_start_addr;
1409};
1410
1411#define SEI_MASTER_DISPLAY_COLOR_MASK 0x00000001
1412#define SEI_CONTENT_LIGHT_LEVEL_MASK 0x00000002
1413#define SEI_HDR10PLUS_MASK 0x00000004
1414
1415#define VF_POOL_SIZE 32
1416
1417#ifdef MULTI_INSTANCE_SUPPORT
1418#define DEC_RESULT_NONE 0
1419#define DEC_RESULT_DONE 1
1420#define DEC_RESULT_AGAIN 2
1421#define DEC_RESULT_CONFIG_PARAM 3
1422#define DEC_RESULT_ERROR 4
1423#define DEC_INIT_PICLIST 5
1424#define DEC_UNINIT_PICLIST 6
1425#define DEC_RESULT_GET_DATA 7
1426#define DEC_RESULT_GET_DATA_RETRY 8
1427#define DEC_RESULT_EOS 9
1428#define DEC_RESULT_FORCE_EXIT 10
1429#define DEC_RESULT_FREE_CANVAS 11
1430
1431static void vh265_work(struct work_struct *work);
1432static void vh265_timeout_work(struct work_struct *work);
1433static void vh265_notify_work(struct work_struct *work);
1434
1435#endif
1436
1437struct debug_log_s {
1438 struct list_head list;
1439 uint8_t data; /*will alloc more size*/
1440};
1441
1442struct hevc_state_s {
1443#ifdef MULTI_INSTANCE_SUPPORT
1444 struct platform_device *platform_dev;
1445 void (*vdec_cb)(struct vdec_s *, void *);
1446 void *vdec_cb_arg;
1447 struct vframe_chunk_s *chunk;
1448 int dec_result;
1449 struct work_struct work;
1450 struct work_struct timeout_work;
1451 struct work_struct notify_work;
1452 struct work_struct set_clk_work;
1453 /* timeout handle */
1454 unsigned long int start_process_time;
1455 unsigned int last_lcu_idx;
1456 unsigned int decode_timeout_count;
1457 unsigned int timeout_num;
1458#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
1459 unsigned char switch_dvlayer_flag;
1460 unsigned char no_switch_dvlayer_count;
1461 unsigned char bypass_dvenl_enable;
1462 unsigned char bypass_dvenl;
1463#endif
1464 unsigned char start_parser_type;
1465 /*start_decoding_flag:
1466 vps/pps/sps/idr info from ucode*/
1467 unsigned char start_decoding_flag;
1468 unsigned char rps_set_id;
1469 unsigned char eos;
1470 int pic_decoded_lcu_idx;
1471 u8 over_decode;
1472 u8 empty_flag;
1473#endif
1474 struct vframe_s vframe_dummy;
1475 char *provider_name;
1476 int index;
1477 struct device *cma_dev;
1478 unsigned char m_ins_flag;
1479 unsigned char dolby_enhance_flag;
1480 unsigned long buf_start;
1481 u32 buf_size;
1482 u32 mv_buf_size;
1483
1484 struct BuffInfo_s work_space_buf_store;
1485 struct BuffInfo_s *work_space_buf;
1486
1487 u8 aux_data_dirty;
1488 u32 prefix_aux_size;
1489 u32 suffix_aux_size;
1490 void *aux_addr;
1491 void *rpm_addr;
1492 void *lmem_addr;
1493 dma_addr_t aux_phy_addr;
1494 dma_addr_t rpm_phy_addr;
1495 dma_addr_t lmem_phy_addr;
1496
1497 unsigned int pic_list_init_flag;
1498 unsigned int use_cma_flag;
1499
1500 unsigned short *rpm_ptr;
1501 unsigned short *lmem_ptr;
1502 unsigned short *debug_ptr;
1503 int debug_ptr_size;
1504 int pic_w;
1505 int pic_h;
1506 int lcu_x_num;
1507 int lcu_y_num;
1508 int lcu_total;
1509 int lcu_size;
1510 int lcu_size_log2;
1511 int lcu_x_num_pre;
1512 int lcu_y_num_pre;
1513 int first_pic_after_recover;
1514
1515 int num_tile_col;
1516 int num_tile_row;
1517 int tile_enabled;
1518 int tile_x;
1519 int tile_y;
1520 int tile_y_x;
1521 int tile_start_lcu_x;
1522 int tile_start_lcu_y;
1523 int tile_width_lcu;
1524 int tile_height_lcu;
1525
1526 int slice_type;
1527 unsigned int slice_addr;
1528 unsigned int slice_segment_addr;
1529
1530 unsigned char interlace_flag;
1531 unsigned char curr_pic_struct;
1532 unsigned char frame_field_info_present_flag;
1533
1534 unsigned short sps_num_reorder_pics_0;
1535 unsigned short misc_flag0;
1536 int m_temporalId;
1537 int m_nalUnitType;
1538 int TMVPFlag;
1539 int isNextSliceSegment;
1540 int LDCFlag;
1541 int m_pocRandomAccess;
1542 int plevel;
1543 int MaxNumMergeCand;
1544
1545 int new_pic;
1546 int new_tile;
1547 int curr_POC;
1548 int iPrevPOC;
1549#ifdef MULTI_INSTANCE_SUPPORT
1550 int decoded_poc;
1551 struct PIC_s *decoding_pic;
1552#endif
1553 int iPrevTid0POC;
1554 int list_no;
1555 int RefNum_L0;
1556 int RefNum_L1;
1557 int ColFromL0Flag;
1558 int LongTerm_Curr;
1559 int LongTerm_Col;
1560 int Col_POC;
1561 int LongTerm_Ref;
1562#ifdef MULTI_INSTANCE_SUPPORT
1563 int m_pocRandomAccess_bak;
1564 int curr_POC_bak;
1565 int iPrevPOC_bak;
1566 int iPrevTid0POC_bak;
1567 unsigned char start_parser_type_bak;
1568 unsigned char start_decoding_flag_bak;
1569 unsigned char rps_set_id_bak;
1570 int pic_decoded_lcu_idx_bak;
1571 int decode_idx_bak;
1572#endif
1573 struct PIC_s *cur_pic;
1574 struct PIC_s *col_pic;
1575 int skip_flag;
1576 int decode_idx;
1577 int slice_idx;
1578 unsigned char have_vps;
1579 unsigned char have_sps;
1580 unsigned char have_pps;
1581 unsigned char have_valid_start_slice;
1582 unsigned char wait_buf;
1583 unsigned char error_flag;
1584 unsigned int error_skip_nal_count;
1585 long used_4k_num;
1586
1587 unsigned char
1588 ignore_bufmgr_error; /* bit 0, for decoding;
1589 bit 1, for displaying
1590 bit 1 must be set if bit 0 is 1*/
1591 int PB_skip_mode;
1592 int PB_skip_count_after_decoding;
1593#ifdef SUPPORT_10BIT
1594 int mem_saving_mode;
1595#endif
1596#ifdef LOSLESS_COMPRESS_MODE
1597 unsigned int losless_comp_body_size;
1598#endif
1599 int pts_mode;
1600 int last_lookup_pts;
1601 int last_pts;
1602 u64 last_lookup_pts_us64;
1603 u64 last_pts_us64;
1604 u32 shift_byte_count_lo;
1605 u32 shift_byte_count_hi;
1606 int pts_mode_switching_count;
1607 int pts_mode_recovery_count;
1608
1609 int pic_num;
1610
1611 /**/
1612 union param_u param;
1613
1614 struct tile_s m_tile[MAX_TILE_ROW_NUM][MAX_TILE_COL_NUM];
1615
1616 struct timer_list timer;
1617 struct BUF_s m_BUF[BUF_POOL_SIZE];
1618 struct BUF_s m_mv_BUF[MAX_REF_PIC_NUM];
1619 struct PIC_s *m_PIC[MAX_REF_PIC_NUM];
1620
1621 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1622 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1623 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1624 struct vframe_s vfpool[VF_POOL_SIZE];
1625
1626 u32 stat;
1627 u32 frame_width;
1628 u32 frame_height;
1629 u32 frame_dur;
1630 u32 frame_ar;
1631 u32 bit_depth_luma;
1632 u32 bit_depth_chroma;
1633 u32 video_signal_type;
1634 u32 video_signal_type_debug;
1635 u32 saved_resolution;
1636 bool get_frame_dur;
1637 u32 error_watchdog_count;
1638 u32 error_skip_nal_wt_cnt;
1639 u32 error_system_watchdog_count;
1640
1641#ifdef DEBUG_PTS
1642 unsigned long pts_missed;
1643 unsigned long pts_hit;
1644#endif
1645 struct dec_sysinfo vh265_amstream_dec_info;
1646 unsigned char init_flag;
1647 unsigned char first_sc_checked;
1648 unsigned char uninit_list;
1649 u32 start_decoding_time;
1650
1651 int show_frame_num;
1652#ifdef USE_UNINIT_SEMA
1653 struct semaphore h265_uninit_done_sema;
1654#endif
1655 int fatal_error;
1656
1657
1658 u32 sei_present_flag;
1659 void *frame_mmu_map_addr;
1660 dma_addr_t frame_mmu_map_phy_addr;
1661 unsigned int mmu_mc_buf_start;
1662 unsigned int mmu_mc_buf_end;
1663 unsigned int mmu_mc_start_4k_adr;
1664 void *mmu_box;
1665 void *bmmu_box;
1666 int mmu_enable;
1667
1668 unsigned int dec_status;
1669
1670 /* data for SEI_MASTER_DISPLAY_COLOR */
1671 unsigned int primaries[3][2];
1672 unsigned int white_point[2];
1673 unsigned int luminance[2];
1674 /* data for SEI_CONTENT_LIGHT_LEVEL */
1675 unsigned int content_light_level[2];
1676
1677 struct PIC_s *pre_top_pic;
1678 struct PIC_s *pre_bot_pic;
1679
1680#ifdef MULTI_INSTANCE_SUPPORT
1681 int double_write_mode;
1682 int dynamic_buf_num_margin;
1683 int start_action;
1684 int save_buffer_mode;
1685#endif
1686 u32 i_only;
1687 struct list_head log_list;
1688 u32 ucode_pause_pos;
1689 u32 start_shift_bytes;
1690
1691 u32 vf_pre_count;
1692 u32 vf_get_count;
1693 u32 vf_put_count;
1694#ifdef SWAP_HEVC_UCODE
1695 dma_addr_t mc_dma_handle;
1696 void *mc_cpu_addr;
1697 int swap_size;
1698 ulong swap_addr;
1699#endif
1700#ifdef DETREFILL_ENABLE
1701 dma_addr_t detbuf_adr;
1702 u16 *detbuf_adr_virt;
1703 u8 delrefill_check;
1704#endif
1705 u8 head_error_flag;
1706 int valve_count;
1707 struct firmware_s *fw;
1708 int max_pic_w;
1709 int max_pic_h;
1710#ifdef AGAIN_HAS_THRESHOLD
1711 u8 next_again_flag;
1712 u32 pre_parser_wr_ptr;
1713#endif
1714 u32 ratio_control;
1715 u32 first_pic_flag;
1716 u32 decode_size;
1717 struct mutex chunks_mutex;
1718 int need_cache_size;
1719 u64 sc_start_time;
1720 u32 skip_first_nal;
1721 bool is_swap;
1722 bool is_4k;
1723 int frameinfo_enable;
1724 struct vframe_qos_s vframe_qos;
1725 bool is_used_v4l;
1726 void *v4l2_ctx;
1727 bool v4l_params_parsed;
1728} /*hevc_stru_t */;
1729
1730#ifdef AGAIN_HAS_THRESHOLD
1731u32 again_threshold;
1732#endif
1733#ifdef SEND_LMEM_WITH_RPM
1734#define get_lmem_params(hevc, ladr) \
1735 hevc->lmem_ptr[ladr - (ladr & 0x3) + 3 - (ladr & 0x3)]
1736
1737
1738static int get_frame_mmu_map_size(void)
1739{
1740 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1741 return (MAX_FRAME_8K_NUM * 4);
1742
1743 return (MAX_FRAME_4K_NUM * 4);
1744}
1745
1746static int is_oversize(int w, int h)
1747{
1748 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1749 MAX_SIZE_8K : MAX_SIZE_4K;
1750
1751 if (w < 0 || h < 0)
1752 return true;
1753
1754 if (h != 0 && (w > max / h))
1755 return true;
1756
1757 return false;
1758}
1759
1760void check_head_error(struct hevc_state_s *hevc)
1761{
1762#define pcm_enabled_flag 0x040
1763#define pcm_sample_bit_depth_luma 0x041
1764#define pcm_sample_bit_depth_chroma 0x042
1765 hevc->head_error_flag = 0;
1766 if ((error_handle_policy & 0x40) == 0)
1767 return;
1768 if (get_lmem_params(hevc, pcm_enabled_flag)) {
1769 uint16_t pcm_depth_luma = get_lmem_params(
1770 hevc, pcm_sample_bit_depth_luma);
1771 uint16_t pcm_sample_chroma = get_lmem_params(
1772 hevc, pcm_sample_bit_depth_chroma);
1773 if (pcm_depth_luma >
1774 hevc->bit_depth_luma ||
1775 pcm_sample_chroma >
1776 hevc->bit_depth_chroma) {
1777 hevc_print(hevc, 0,
1778 "error, pcm bit depth %d, %d is greater than normal bit depth %d, %d\n",
1779 pcm_depth_luma,
1780 pcm_sample_chroma,
1781 hevc->bit_depth_luma,
1782 hevc->bit_depth_chroma);
1783 hevc->head_error_flag = 1;
1784 }
1785 }
1786}
1787#endif
1788
1789#ifdef SUPPORT_10BIT
1790/* Losless compression body buffer size 4K per 64x32 (jt) */
1791static int compute_losless_comp_body_size(struct hevc_state_s *hevc,
1792 int width, int height, int mem_saving_mode)
1793{
1794 int width_x64;
1795 int height_x32;
1796 int bsize;
1797
1798 width_x64 = width + 63;
1799 width_x64 >>= 6;
1800
1801 height_x32 = height + 31;
1802 height_x32 >>= 5;
1803 if (mem_saving_mode == 1 && hevc->mmu_enable)
1804 bsize = 3200 * width_x64 * height_x32;
1805 else if (mem_saving_mode == 1)
1806 bsize = 3072 * width_x64 * height_x32;
1807 else
1808 bsize = 4096 * width_x64 * height_x32;
1809
1810 return bsize;
1811}
1812
1813/* Losless compression header buffer size 32bytes per 128x64 (jt) */
1814static int compute_losless_comp_header_size(int width, int height)
1815{
1816 int width_x128;
1817 int height_x64;
1818 int hsize;
1819
1820 width_x128 = width + 127;
1821 width_x128 >>= 7;
1822
1823 height_x64 = height + 63;
1824 height_x64 >>= 6;
1825
1826 hsize = 32*width_x128*height_x64;
1827
1828 return hsize;
1829}
1830#endif
1831
1832static int add_log(struct hevc_state_s *hevc,
1833 const char *fmt, ...)
1834{
1835#define HEVC_LOG_BUF 196
1836 struct debug_log_s *log_item;
1837 unsigned char buf[HEVC_LOG_BUF];
1838 int len = 0;
1839 va_list args;
1840 mutex_lock(&vh265_log_mutex);
1841 va_start(args, fmt);
1842 len = sprintf(buf, "<%ld> <%05d> ",
1843 jiffies, hevc->decode_idx);
1844 len += vsnprintf(buf + len,
1845 HEVC_LOG_BUF - len, fmt, args);
1846 va_end(args);
1847 log_item = kmalloc(
1848 sizeof(struct debug_log_s) + len,
1849 GFP_KERNEL);
1850 if (log_item) {
1851 INIT_LIST_HEAD(&log_item->list);
1852 strcpy(&log_item->data, buf);
1853 list_add_tail(&log_item->list,
1854 &hevc->log_list);
1855 }
1856 mutex_unlock(&vh265_log_mutex);
1857 return 0;
1858}
1859
1860static void dump_log(struct hevc_state_s *hevc)
1861{
1862 int i = 0;
1863 struct debug_log_s *log_item, *tmp;
1864 mutex_lock(&vh265_log_mutex);
1865 list_for_each_entry_safe(log_item, tmp, &hevc->log_list, list) {
1866 hevc_print(hevc, 0,
1867 "[LOG%04d]%s\n",
1868 i++,
1869 &log_item->data);
1870 list_del(&log_item->list);
1871 kfree(log_item);
1872 }
1873 mutex_unlock(&vh265_log_mutex);
1874}
1875
1876static unsigned char is_skip_decoding(struct hevc_state_s *hevc,
1877 struct PIC_s *pic)
1878{
1879 if (pic->error_mark
1880 && ((hevc->ignore_bufmgr_error & 0x1) == 0))
1881 return 1;
1882 return 0;
1883}
1884
1885static int get_pic_poc(struct hevc_state_s *hevc,
1886 unsigned int idx)
1887{
1888 if (idx != 0xff
1889 && idx < MAX_REF_PIC_NUM
1890 && hevc->m_PIC[idx])
1891 return hevc->m_PIC[idx]->POC;
1892 return INVALID_POC;
1893}
1894
1895#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1896static int get_valid_double_write_mode(struct hevc_state_s *hevc)
1897{
1898 return (hevc->m_ins_flag &&
1899 ((double_write_mode & 0x80000000) == 0)) ?
1900 hevc->double_write_mode :
1901 (double_write_mode & 0x7fffffff);
1902}
1903
1904static int get_dynamic_buf_num_margin(struct hevc_state_s *hevc)
1905{
1906 return (hevc->m_ins_flag &&
1907 ((dynamic_buf_num_margin & 0x80000000) == 0)) ?
1908 hevc->dynamic_buf_num_margin :
1909 (dynamic_buf_num_margin & 0x7fffffff);
1910}
1911#endif
1912
1913static int get_double_write_mode(struct hevc_state_s *hevc)
1914{
1915 u32 valid_dw_mode = get_valid_double_write_mode(hevc);
1916 int w = hevc->pic_w;
1917 int h = hevc->pic_h;
1918 u32 dw = 0x1; /*1:1*/
1919 switch (valid_dw_mode) {
1920 case 0x100:
1921 if (w > 1920 && h > 1088)
1922 dw = 0x4; /*1:2*/
1923 break;
1924 case 0x200:
1925 if (w > 1920 && h > 1088)
1926 dw = 0x2; /*1:4*/
1927 break;
1928 case 0x300:
1929 if (w > 1280 && h > 720)
1930 dw = 0x4; /*1:2*/
1931 break;
1932 default:
1933 dw = valid_dw_mode;
1934 break;
1935 }
1936 return dw;
1937}
1938
1939static int get_double_write_ratio(struct hevc_state_s *hevc,
1940 int dw_mode)
1941{
1942 int ratio = 1;
1943 if ((dw_mode == 2) ||
1944 (dw_mode == 3))
1945 ratio = 4;
1946 else if (dw_mode == 4)
1947 ratio = 2;
1948 return ratio;
1949}
1950#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1951static unsigned char get_idx(struct hevc_state_s *hevc)
1952{
1953 return hevc->index;
1954}
1955#endif
1956
1957#undef pr_info
1958#define pr_info printk
1959static int hevc_print(struct hevc_state_s *hevc,
1960 int flag, const char *fmt, ...)
1961{
1962#define HEVC_PRINT_BUF 256
1963 unsigned char buf[HEVC_PRINT_BUF];
1964 int len = 0;
1965#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1966 if (hevc == NULL ||
1967 (flag == 0) ||
1968 ((debug_mask &
1969 (1 << hevc->index))
1970 && (debug & flag))) {
1971#endif
1972 va_list args;
1973
1974 va_start(args, fmt);
1975 if (hevc)
1976 len = sprintf(buf, "[%d]", hevc->index);
1977 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1978 pr_debug("%s", buf);
1979 va_end(args);
1980#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1981 }
1982#endif
1983 return 0;
1984}
1985
1986static int hevc_print_cont(struct hevc_state_s *hevc,
1987 int flag, const char *fmt, ...)
1988{
1989 unsigned char buf[HEVC_PRINT_BUF];
1990 int len = 0;
1991#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1992 if (hevc == NULL ||
1993 (flag == 0) ||
1994 ((debug_mask &
1995 (1 << hevc->index))
1996 && (debug & flag))) {
1997#endif
1998 va_list args;
1999
2000 va_start(args, fmt);
2001 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
2002 pr_info("%s", buf);
2003 va_end(args);
2004#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
2005 }
2006#endif
2007 return 0;
2008}
2009
2010static void put_mv_buf(struct hevc_state_s *hevc,
2011 struct PIC_s *pic);
2012
2013static void update_vf_memhandle(struct hevc_state_s *hevc,
2014 struct vframe_s *vf, struct PIC_s *pic);
2015
2016static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic);
2017
2018static void release_aux_data(struct hevc_state_s *hevc,
2019 struct PIC_s *pic);
2020static void release_pic_mmu_buf(struct hevc_state_s *hevc, struct PIC_s *pic);
2021
2022#ifdef MULTI_INSTANCE_SUPPORT
2023static void backup_decode_state(struct hevc_state_s *hevc)
2024{
2025 hevc->m_pocRandomAccess_bak = hevc->m_pocRandomAccess;
2026 hevc->curr_POC_bak = hevc->curr_POC;
2027 hevc->iPrevPOC_bak = hevc->iPrevPOC;
2028 hevc->iPrevTid0POC_bak = hevc->iPrevTid0POC;
2029 hevc->start_parser_type_bak = hevc->start_parser_type;
2030 hevc->start_decoding_flag_bak = hevc->start_decoding_flag;
2031 hevc->rps_set_id_bak = hevc->rps_set_id;
2032 hevc->pic_decoded_lcu_idx_bak = hevc->pic_decoded_lcu_idx;
2033 hevc->decode_idx_bak = hevc->decode_idx;
2034
2035}
2036
2037static void restore_decode_state(struct hevc_state_s *hevc)
2038{
2039 struct vdec_s *vdec = hw_to_vdec(hevc);
2040 if (!vdec_has_more_input(vdec)) {
2041 hevc->pic_decoded_lcu_idx =
2042 READ_VREG(HEVC_PARSER_LCU_START)
2043 & 0xffffff;
2044 return;
2045 }
2046 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
2047 "%s: discard pic index 0x%x\n",
2048 __func__, hevc->decoding_pic ?
2049 hevc->decoding_pic->index : 0xff);
2050 if (hevc->decoding_pic) {
2051 hevc->decoding_pic->error_mark = 0;
2052 hevc->decoding_pic->output_ready = 0;
2053 hevc->decoding_pic->output_mark = 0;
2054 hevc->decoding_pic->referenced = 0;
2055 hevc->decoding_pic->POC = INVALID_POC;
2056 put_mv_buf(hevc, hevc->decoding_pic);
2057 release_pic_mmu_buf(hevc, hevc->decoding_pic);
2058 release_aux_data(hevc, hevc->decoding_pic);
2059 hevc->decoding_pic = NULL;
2060 }
2061 hevc->decode_idx = hevc->decode_idx_bak;
2062 hevc->m_pocRandomAccess = hevc->m_pocRandomAccess_bak;
2063 hevc->curr_POC = hevc->curr_POC_bak;
2064 hevc->iPrevPOC = hevc->iPrevPOC_bak;
2065 hevc->iPrevTid0POC = hevc->iPrevTid0POC_bak;
2066 hevc->start_parser_type = hevc->start_parser_type_bak;
2067 hevc->start_decoding_flag = hevc->start_decoding_flag_bak;
2068 hevc->rps_set_id = hevc->rps_set_id_bak;
2069 hevc->pic_decoded_lcu_idx = hevc->pic_decoded_lcu_idx_bak;
2070
2071 if (hevc->pic_list_init_flag == 1)
2072 hevc->pic_list_init_flag = 0;
2073 /*if (hevc->decode_idx == 0)
2074 hevc->start_decoding_flag = 0;*/
2075
2076 hevc->slice_idx = 0;
2077 hevc->used_4k_num = -1;
2078}
2079#endif
2080
2081static void hevc_init_stru(struct hevc_state_s *hevc,
2082 struct BuffInfo_s *buf_spec_i)
2083{
2084 //int i;
2085 INIT_LIST_HEAD(&hevc->log_list);
2086 hevc->work_space_buf = buf_spec_i;
2087 hevc->prefix_aux_size = 0;
2088 hevc->suffix_aux_size = 0;
2089 hevc->aux_addr = NULL;
2090 hevc->rpm_addr = NULL;
2091 hevc->lmem_addr = NULL;
2092
2093 hevc->curr_POC = INVALID_POC;
2094
2095 hevc->pic_list_init_flag = 0;
2096 hevc->use_cma_flag = 0;
2097 hevc->decode_idx = 0;
2098 hevc->slice_idx = 0;
2099 hevc->new_pic = 0;
2100 hevc->new_tile = 0;
2101 hevc->iPrevPOC = 0;
2102 hevc->list_no = 0;
2103 /* int m_uiMaxCUWidth = 1<<7; */
2104 /* int m_uiMaxCUHeight = 1<<7; */
2105 hevc->m_pocRandomAccess = MAX_INT;
2106 hevc->tile_enabled = 0;
2107 hevc->tile_x = 0;
2108 hevc->tile_y = 0;
2109 hevc->iPrevTid0POC = 0;
2110 hevc->slice_addr = 0;
2111 hevc->slice_segment_addr = 0;
2112 hevc->skip_flag = 0;
2113 hevc->misc_flag0 = 0;
2114
2115 hevc->cur_pic = NULL;
2116 hevc->col_pic = NULL;
2117 hevc->wait_buf = 0;
2118 hevc->error_flag = 0;
2119 hevc->head_error_flag = 0;
2120 hevc->error_skip_nal_count = 0;
2121 hevc->have_vps = 0;
2122 hevc->have_sps = 0;
2123 hevc->have_pps = 0;
2124 hevc->have_valid_start_slice = 0;
2125
2126 hevc->pts_mode = PTS_NORMAL;
2127 hevc->last_pts = 0;
2128 hevc->last_lookup_pts = 0;
2129 hevc->last_pts_us64 = 0;
2130 hevc->last_lookup_pts_us64 = 0;
2131 hevc->pts_mode_switching_count = 0;
2132 hevc->pts_mode_recovery_count = 0;
2133
2134 hevc->PB_skip_mode = nal_skip_policy & 0x3;
2135 hevc->PB_skip_count_after_decoding = (nal_skip_policy >> 16) & 0xffff;
2136 if (hevc->PB_skip_mode == 0)
2137 hevc->ignore_bufmgr_error = 0x1;
2138 else
2139 hevc->ignore_bufmgr_error = 0x0;
2140
2141 hevc->dec_result = DEC_RESULT_FREE_CANVAS;
2142 vdec_schedule_work(&hevc->work);
2143 /*for (i = 0; i < MAX_REF_PIC_NUM; i++)
2144 hevc->m_PIC[i] = NULL;*/
2145
2146 hevc->pic_num = 0;
2147 hevc->lcu_x_num_pre = 0;
2148 hevc->lcu_y_num_pre = 0;
2149 hevc->first_pic_after_recover = 0;
2150
2151 hevc->pre_top_pic = NULL;
2152 hevc->pre_bot_pic = NULL;
2153
2154 hevc->sei_present_flag = 0;
2155 hevc->valve_count = 0;
2156 hevc->first_pic_flag = 0;
2157#ifdef MULTI_INSTANCE_SUPPORT
2158 hevc->decoded_poc = INVALID_POC;
2159 hevc->start_process_time = 0;
2160 hevc->last_lcu_idx = 0;
2161 hevc->decode_timeout_count = 0;
2162 hevc->timeout_num = 0;
2163 hevc->eos = 0;
2164 hevc->pic_decoded_lcu_idx = -1;
2165 hevc->over_decode = 0;
2166 hevc->used_4k_num = -1;
2167 hevc->start_decoding_flag = 0;
2168 hevc->rps_set_id = 0;
2169 backup_decode_state(hevc);
2170#endif
2171#ifdef DETREFILL_ENABLE
2172 hevc->detbuf_adr = 0;
2173 hevc->detbuf_adr_virt = NULL;
2174#endif
2175}
2176
2177static int prepare_display_buf(struct hevc_state_s *hevc, struct PIC_s *pic);
2178static int H265_alloc_mmu(struct hevc_state_s *hevc,
2179 struct PIC_s *new_pic, unsigned short bit_depth,
2180 unsigned int *mmu_index_adr);
2181
2182#ifdef DETREFILL_ENABLE
2183#define DETREFILL_BUF_SIZE (4 * 0x4000)
2184#define HEVC_SAO_DBG_MODE0 0x361e
2185#define HEVC_SAO_DBG_MODE1 0x361f
2186#define HEVC_SAO_CTRL10 0x362e
2187#define HEVC_SAO_CTRL11 0x362f
2188static int init_detrefill_buf(struct hevc_state_s *hevc)
2189{
2190 if (hevc->detbuf_adr_virt)
2191 return 0;
2192
2193 hevc->detbuf_adr_virt =
2194 (void *)dma_alloc_coherent(amports_get_dma_device(),
2195 DETREFILL_BUF_SIZE, &hevc->detbuf_adr,
2196 GFP_KERNEL);
2197
2198 if (hevc->detbuf_adr_virt == NULL) {
2199 pr_err("%s: failed to alloc ETREFILL_BUF\n", __func__);
2200 return -1;
2201 }
2202 return 0;
2203}
2204
2205static void uninit_detrefill_buf(struct hevc_state_s *hevc)
2206{
2207 if (hevc->detbuf_adr_virt) {
2208 dma_free_coherent(amports_get_dma_device(),
2209 DETREFILL_BUF_SIZE, hevc->detbuf_adr_virt,
2210 hevc->detbuf_adr);
2211
2212 hevc->detbuf_adr_virt = NULL;
2213 hevc->detbuf_adr = 0;
2214 }
2215}
2216
2217/*
2218 * convert uncompressed frame buffer data from/to ddr
2219 */
2220static void convUnc8x4blk(uint16_t* blk8x4Luma,
2221 uint16_t* blk8x4Cb, uint16_t* blk8x4Cr, uint16_t* cmBodyBuf, int32_t direction)
2222{
2223 if (direction == 0) {
2224 blk8x4Luma[3 + 0 * 8] = ((cmBodyBuf[0] >> 0)) & 0x3ff;
2225 blk8x4Luma[3 + 1 * 8] = ((cmBodyBuf[1] << 6)
2226 | (cmBodyBuf[0] >> 10)) & 0x3ff;
2227 blk8x4Luma[3 + 2 * 8] = ((cmBodyBuf[1] >> 4)) & 0x3ff;
2228 blk8x4Luma[3 + 3 * 8] = ((cmBodyBuf[2] << 2)
2229 | (cmBodyBuf[1] >> 14)) & 0x3ff;
2230 blk8x4Luma[7 + 0 * 8] = ((cmBodyBuf[3] << 8)
2231 | (cmBodyBuf[2] >> 8)) & 0x3ff;
2232 blk8x4Luma[7 + 1 * 8] = ((cmBodyBuf[3] >> 2)) & 0x3ff;
2233 blk8x4Luma[7 + 2 * 8] = ((cmBodyBuf[4] << 4)
2234 | (cmBodyBuf[3] >> 12)) & 0x3ff;
2235 blk8x4Luma[7 + 3 * 8] = ((cmBodyBuf[4] >> 6)) & 0x3ff;
2236 blk8x4Cb [0 + 0 * 4] = ((cmBodyBuf[5] >> 0)) & 0x3ff;
2237 blk8x4Cr [0 + 0 * 4] = ((cmBodyBuf[6] << 6)
2238 | (cmBodyBuf[5] >> 10)) & 0x3ff;
2239 blk8x4Cb [0 + 1 * 4] = ((cmBodyBuf[6] >> 4)) & 0x3ff;
2240 blk8x4Cr [0 + 1 * 4] = ((cmBodyBuf[7] << 2)
2241 | (cmBodyBuf[6] >> 14)) & 0x3ff;
2242
2243 blk8x4Luma[0 + 0 * 8] = ((cmBodyBuf[0 + 8] >> 0)) & 0x3ff;
2244 blk8x4Luma[1 + 0 * 8] = ((cmBodyBuf[1 + 8] << 6) |
2245 (cmBodyBuf[0 + 8] >> 10)) & 0x3ff;
2246 blk8x4Luma[2 + 0 * 8] = ((cmBodyBuf[1 + 8] >> 4)) & 0x3ff;
2247 blk8x4Luma[0 + 1 * 8] = ((cmBodyBuf[2 + 8] << 2) |
2248 (cmBodyBuf[1 + 8] >> 14)) & 0x3ff;
2249 blk8x4Luma[1 + 1 * 8] = ((cmBodyBuf[3 + 8] << 8) |
2250 (cmBodyBuf[2 + 8] >> 8)) & 0x3ff;
2251 blk8x4Luma[2 + 1 * 8] = ((cmBodyBuf[3 + 8] >> 2)) & 0x3ff;
2252 blk8x4Luma[0 + 2 * 8] = ((cmBodyBuf[4 + 8] << 4) |
2253 (cmBodyBuf[3 + 8] >> 12)) & 0x3ff;
2254 blk8x4Luma[1 + 2 * 8] = ((cmBodyBuf[4 + 8] >> 6)) & 0x3ff;
2255 blk8x4Luma[2 + 2 * 8] = ((cmBodyBuf[5 + 8] >> 0)) & 0x3ff;
2256 blk8x4Luma[0 + 3 * 8] = ((cmBodyBuf[6 + 8] << 6) |
2257 (cmBodyBuf[5 + 8] >> 10)) & 0x3ff;
2258 blk8x4Luma[1 + 3 * 8] = ((cmBodyBuf[6 + 8] >> 4)) & 0x3ff;
2259 blk8x4Luma[2 + 3 * 8] = ((cmBodyBuf[7 + 8] << 2) |
2260 (cmBodyBuf[6 + 8] >> 14)) & 0x3ff;
2261
2262 blk8x4Luma[4 + 0 * 8] = ((cmBodyBuf[0 + 16] >> 0)) & 0x3ff;
2263 blk8x4Luma[5 + 0 * 8] = ((cmBodyBuf[1 + 16] << 6) |
2264 (cmBodyBuf[0 + 16] >> 10)) & 0x3ff;
2265 blk8x4Luma[6 + 0 * 8] = ((cmBodyBuf[1 + 16] >> 4)) & 0x3ff;
2266 blk8x4Luma[4 + 1 * 8] = ((cmBodyBuf[2 + 16] << 2) |
2267 (cmBodyBuf[1 + 16] >> 14)) & 0x3ff;
2268 blk8x4Luma[5 + 1 * 8] = ((cmBodyBuf[3 + 16] << 8) |
2269 (cmBodyBuf[2 + 16] >> 8)) & 0x3ff;
2270 blk8x4Luma[6 + 1 * 8] = ((cmBodyBuf[3 + 16] >> 2)) & 0x3ff;
2271 blk8x4Luma[4 + 2 * 8] = ((cmBodyBuf[4 + 16] << 4) |
2272 (cmBodyBuf[3 + 16] >> 12)) & 0x3ff;
2273 blk8x4Luma[5 + 2 * 8] = ((cmBodyBuf[4 + 16] >> 6)) & 0x3ff;
2274 blk8x4Luma[6 + 2 * 8] = ((cmBodyBuf[5 + 16] >> 0)) & 0x3ff;
2275 blk8x4Luma[4 + 3 * 8] = ((cmBodyBuf[6 + 16] << 6) |
2276 (cmBodyBuf[5 + 16] >> 10)) & 0x3ff;
2277 blk8x4Luma[5 + 3 * 8] = ((cmBodyBuf[6 + 16] >> 4)) & 0x3ff;
2278 blk8x4Luma[6 + 3 * 8] = ((cmBodyBuf[7 + 16] << 2) |
2279 (cmBodyBuf[6 + 16] >> 14)) & 0x3ff;
2280
2281 blk8x4Cb[1 + 0 * 4] = ((cmBodyBuf[0 + 24] >> 0)) & 0x3ff;
2282 blk8x4Cr[1 + 0 * 4] = ((cmBodyBuf[1 + 24] << 6) |
2283 (cmBodyBuf[0 + 24] >> 10)) & 0x3ff;
2284 blk8x4Cb[2 + 0 * 4] = ((cmBodyBuf[1 + 24] >> 4)) & 0x3ff;
2285 blk8x4Cr[2 + 0 * 4] = ((cmBodyBuf[2 + 24] << 2) |
2286 (cmBodyBuf[1 + 24] >> 14)) & 0x3ff;
2287 blk8x4Cb[3 + 0 * 4] = ((cmBodyBuf[3 + 24] << 8) |
2288 (cmBodyBuf[2 + 24] >> 8)) & 0x3ff;
2289 blk8x4Cr[3 + 0 * 4] = ((cmBodyBuf[3 + 24] >> 2)) & 0x3ff;
2290 blk8x4Cb[1 + 1 * 4] = ((cmBodyBuf[4 + 24] << 4) |
2291 (cmBodyBuf[3 + 24] >> 12)) & 0x3ff;
2292 blk8x4Cr[1 + 1 * 4] = ((cmBodyBuf[4 + 24] >> 6)) & 0x3ff;
2293 blk8x4Cb[2 + 1 * 4] = ((cmBodyBuf[5 + 24] >> 0)) & 0x3ff;
2294 blk8x4Cr[2 + 1 * 4] = ((cmBodyBuf[6 + 24] << 6) |
2295 (cmBodyBuf[5 + 24] >> 10)) & 0x3ff;
2296 blk8x4Cb[3 + 1 * 4] = ((cmBodyBuf[6 + 24] >> 4)) & 0x3ff;
2297 blk8x4Cr[3 + 1 * 4] = ((cmBodyBuf[7 + 24] << 2) |
2298 (cmBodyBuf[6 + 24] >> 14)) & 0x3ff;
2299 } else {
2300 cmBodyBuf[0 + 8 * 0] = (blk8x4Luma[3 + 1 * 8] << 10) |
2301 blk8x4Luma[3 + 0 * 8];
2302 cmBodyBuf[1 + 8 * 0] = (blk8x4Luma[3 + 3 * 8] << 14) |
2303 (blk8x4Luma[3 + 2 * 8] << 4) | (blk8x4Luma[3 + 1 * 8] >> 6);
2304 cmBodyBuf[2 + 8 * 0] = (blk8x4Luma[7 + 0 * 8] << 8) |
2305 (blk8x4Luma[3 + 3 * 8] >> 2);
2306 cmBodyBuf[3 + 8 * 0] = (blk8x4Luma[7 + 2 * 8] << 12) |
2307 (blk8x4Luma[7 + 1 * 8] << 2) | (blk8x4Luma[7 + 0 * 8] >>8);
2308 cmBodyBuf[4 + 8 * 0] = (blk8x4Luma[7 + 3 * 8] << 6) |
2309 (blk8x4Luma[7 + 2 * 8] >>4);
2310 cmBodyBuf[5 + 8 * 0] = (blk8x4Cr[0 + 0 * 4] << 10) |
2311 blk8x4Cb[0 + 0 * 4];
2312 cmBodyBuf[6 + 8 * 0] = (blk8x4Cr[0 + 1 * 4] << 14) |
2313 (blk8x4Cb[0 + 1 * 4] << 4) | (blk8x4Cr[0 + 0 * 4] >> 6);
2314 cmBodyBuf[7 + 8 * 0] = (0<< 8) | (blk8x4Cr[0 + 1 * 4] >> 2);
2315
2316 cmBodyBuf[0 + 8 * 1] = (blk8x4Luma[1 + 0 * 8] << 10) |
2317 blk8x4Luma[0 + 0 * 8];
2318 cmBodyBuf[1 + 8 * 1] = (blk8x4Luma[0 + 1 * 8] << 14) |
2319 (blk8x4Luma[2 + 0 * 8] << 4) | (blk8x4Luma[1 + 0 * 8] >> 6);
2320 cmBodyBuf[2 + 8 * 1] = (blk8x4Luma[1 + 1 * 8] << 8) |
2321 (blk8x4Luma[0 + 1 * 8] >> 2);
2322 cmBodyBuf[3 + 8 * 1] = (blk8x4Luma[0 + 2 * 8] << 12) |
2323 (blk8x4Luma[2 + 1 * 8] << 2) | (blk8x4Luma[1 + 1 * 8] >>8);
2324 cmBodyBuf[4 + 8 * 1] = (blk8x4Luma[1 + 2 * 8] << 6) |
2325 (blk8x4Luma[0 + 2 * 8] >>4);
2326 cmBodyBuf[5 + 8 * 1] = (blk8x4Luma[0 + 3 * 8] << 10) |
2327 blk8x4Luma[2 + 2 * 8];
2328 cmBodyBuf[6 + 8 * 1] = (blk8x4Luma[2 + 3 * 8] << 14) |
2329 (blk8x4Luma[1 + 3 * 8] << 4) | (blk8x4Luma[0 + 3 * 8] >> 6);
2330 cmBodyBuf[7 + 8 * 1] = (0<< 8) | (blk8x4Luma[2 + 3 * 8] >> 2);
2331
2332 cmBodyBuf[0 + 8 * 2] = (blk8x4Luma[5 + 0 * 8] << 10) |
2333 blk8x4Luma[4 + 0 * 8];
2334 cmBodyBuf[1 + 8 * 2] = (blk8x4Luma[4 + 1 * 8] << 14) |
2335 (blk8x4Luma[6 + 0 * 8] << 4) | (blk8x4Luma[5 + 0 * 8] >> 6);
2336 cmBodyBuf[2 + 8 * 2] = (blk8x4Luma[5 + 1 * 8] << 8) |
2337 (blk8x4Luma[4 + 1 * 8] >> 2);
2338 cmBodyBuf[3 + 8 * 2] = (blk8x4Luma[4 + 2 * 8] << 12) |
2339 (blk8x4Luma[6 + 1 * 8] << 2) | (blk8x4Luma[5 + 1 * 8] >>8);
2340 cmBodyBuf[4 + 8 * 2] = (blk8x4Luma[5 + 2 * 8] << 6) |
2341 (blk8x4Luma[4 + 2 * 8] >>4);
2342 cmBodyBuf[5 + 8 * 2] = (blk8x4Luma[4 + 3 * 8] << 10) |
2343 blk8x4Luma[6 + 2 * 8];
2344 cmBodyBuf[6 + 8 * 2] = (blk8x4Luma[6 + 3 * 8] << 14) |
2345 (blk8x4Luma[5 + 3 * 8] << 4) | (blk8x4Luma[4 + 3 * 8] >> 6);
2346 cmBodyBuf[7 + 8 * 2] = (0<< 8) | (blk8x4Luma[6 + 3 * 8] >> 2);
2347
2348 cmBodyBuf[0 + 8 * 3] = (blk8x4Cr[1 + 0 * 4] << 10) |
2349 blk8x4Cb[1 + 0 * 4];
2350 cmBodyBuf[1 + 8 * 3] = (blk8x4Cr[2 + 0 * 4] << 14) |
2351 (blk8x4Cb[2 + 0 * 4] << 4) | (blk8x4Cr[1 + 0 * 4] >> 6);
2352 cmBodyBuf[2 + 8 * 3] = (blk8x4Cb[3 + 0 * 4] << 8) |
2353 (blk8x4Cr[2 + 0 * 4] >> 2);
2354 cmBodyBuf[3 + 8 * 3] = (blk8x4Cb[1 + 1 * 4] << 12) |
2355 (blk8x4Cr[3 + 0 * 4] << 2) | (blk8x4Cb[3 + 0 * 4] >>8);
2356 cmBodyBuf[4 + 8 * 3] = (blk8x4Cr[1 + 1 * 4] << 6) |
2357 (blk8x4Cb[1 + 1 * 4] >>4);
2358 cmBodyBuf[5 + 8 * 3] = (blk8x4Cr[2 + 1 * 4] << 10) |
2359 blk8x4Cb[2 + 1 * 4];
2360 cmBodyBuf[6 + 8 * 3] = (blk8x4Cr[3 + 1 * 4] << 14) |
2361 (blk8x4Cb[3 + 1 * 4] << 4) | (blk8x4Cr[2 + 1 * 4] >> 6);
2362 cmBodyBuf[7 + 8 * 3] = (0 << 8) | (blk8x4Cr[3 + 1 * 4] >> 2);
2363 }
2364}
2365
2366static void corrRefillWithAmrisc (
2367 struct hevc_state_s *hevc,
2368 uint32_t cmHeaderBaseAddr,
2369 uint32_t picWidth,
2370 uint32_t ctuPosition)
2371{
2372 int32_t i;
2373 uint16_t ctux = (ctuPosition>>16) & 0xffff;
2374 uint16_t ctuy = (ctuPosition>> 0) & 0xffff;
2375 int32_t aboveCtuAvailable = (ctuy) ? 1 : 0;
2376
2377 uint16_t cmBodyBuf[32 * 18];
2378
2379 uint32_t pic_width_x64_pre = picWidth + 0x3f;
2380 uint32_t pic_width_x64 = pic_width_x64_pre >> 6;
2381 uint32_t stride64x64 = pic_width_x64 * 128;
2382 uint32_t addr_offset64x64_abv = stride64x64 *
2383 (aboveCtuAvailable ? ctuy - 1 : ctuy) + 128 * ctux;
2384 uint32_t addr_offset64x64_cur = stride64x64*ctuy + 128 * ctux;
2385 uint32_t cmHeaderAddrAbv = cmHeaderBaseAddr + addr_offset64x64_abv;
2386 uint32_t cmHeaderAddrCur = cmHeaderBaseAddr + addr_offset64x64_cur;
2387 unsigned int tmpData32;
2388
2389 uint16_t blkBuf0Y[32];
2390 uint16_t blkBuf0Cb[8];
2391 uint16_t blkBuf0Cr[8];
2392 uint16_t blkBuf1Y[32];
2393 uint16_t blkBuf1Cb[8];
2394 uint16_t blkBuf1Cr[8];
2395 int32_t blkBufCnt = 0;
2396
2397 int32_t blkIdx;
2398
2399 WRITE_VREG(HEVC_SAO_CTRL10, cmHeaderAddrAbv);
2400 WRITE_VREG(HEVC_SAO_CTRL11, cmHeaderAddrCur);
2401 WRITE_VREG(HEVC_SAO_DBG_MODE0, hevc->detbuf_adr);
2402 WRITE_VREG(HEVC_SAO_DBG_MODE1, 2);
2403
2404 for (i = 0; i < 32 * 18; i++)
2405 cmBodyBuf[i] = 0;
2406
2407 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2408 "%s, %d\n", __func__, __LINE__);
2409 do {
2410 tmpData32 = READ_VREG(HEVC_SAO_DBG_MODE1);
2411 } while (tmpData32);
2412 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2413 "%s, %d\n", __func__, __LINE__);
2414
2415 hevc_print(hevc, H265_DEBUG_DETAIL,
2416 "cmBodyBuf from detbuf:\n");
2417 for (i = 0; i < 32 * 18; i++) {
2418 cmBodyBuf[i] = hevc->detbuf_adr_virt[i];
2419 if (get_dbg_flag(hevc) &
2420 H265_DEBUG_DETAIL) {
2421 if ((i & 0xf) == 0)
2422 hevc_print_cont(hevc, 0, "\n");
2423 hevc_print_cont(hevc, 0, "%02x ", cmBodyBuf[i]);
2424 }
2425 }
2426 hevc_print_cont(hevc, H265_DEBUG_DETAIL, "\n");
2427
2428 for (i = 0; i < 32; i++)
2429 blkBuf0Y[i] = 0;
2430 for (i = 0; i < 8; i++)
2431 blkBuf0Cb[i] = 0;
2432 for (i = 0; i < 8; i++)
2433 blkBuf0Cr[i] = 0;
2434 for (i = 0; i < 32; i++)
2435 blkBuf1Y[i] = 0;
2436 for (i = 0; i < 8; i++)
2437 blkBuf1Cb[i] = 0;
2438 for (i = 0; i < 8; i++)
2439 blkBuf1Cr[i] = 0;
2440
2441 for (blkIdx = 0; blkIdx < 18; blkIdx++) {
2442 int32_t inAboveCtu = (blkIdx<2) ? 1 : 0;
2443 int32_t restoreEnable = (blkIdx>0) ? 1 : 0;
2444 uint16_t* blkY = (blkBufCnt==0) ? blkBuf0Y : blkBuf1Y ;
2445 uint16_t* blkCb = (blkBufCnt==0) ? blkBuf0Cb : blkBuf1Cb;
2446 uint16_t* blkCr = (blkBufCnt==0) ? blkBuf0Cr : blkBuf1Cr;
2447 uint16_t* cmBodyBufNow = cmBodyBuf + (blkIdx * 32);
2448
2449 if (!aboveCtuAvailable && inAboveCtu)
2450 continue;
2451
2452 /* detRefillBuf --> 8x4block*/
2453 convUnc8x4blk(blkY, blkCb, blkCr, cmBodyBufNow, 0);
2454
2455 if (restoreEnable) {
2456 blkY[3 + 0 * 8] = blkY[2 + 0 * 8] + 2;
2457 blkY[4 + 0 * 8] = blkY[1 + 0 * 8] + 3;
2458 blkY[5 + 0 * 8] = blkY[0 + 0 * 8] + 1;
2459 blkY[6 + 0 * 8] = blkY[0 + 0 * 8] + 2;
2460 blkY[7 + 0 * 8] = blkY[1 + 0 * 8] + 2;
2461 blkY[3 + 1 * 8] = blkY[2 + 1 * 8] + 1;
2462 blkY[4 + 1 * 8] = blkY[1 + 1 * 8] + 2;
2463 blkY[5 + 1 * 8] = blkY[0 + 1 * 8] + 2;
2464 blkY[6 + 1 * 8] = blkY[0 + 1 * 8] + 2;
2465 blkY[7 + 1 * 8] = blkY[1 + 1 * 8] + 3;
2466 blkY[3 + 2 * 8] = blkY[2 + 2 * 8] + 3;
2467 blkY[4 + 2 * 8] = blkY[1 + 2 * 8] + 1;
2468 blkY[5 + 2 * 8] = blkY[0 + 2 * 8] + 3;
2469 blkY[6 + 2 * 8] = blkY[0 + 2 * 8] + 3;
2470 blkY[7 + 2 * 8] = blkY[1 + 2 * 8] + 3;
2471 blkY[3 + 3 * 8] = blkY[2 + 3 * 8] + 0;
2472 blkY[4 + 3 * 8] = blkY[1 + 3 * 8] + 0;
2473 blkY[5 + 3 * 8] = blkY[0 + 3 * 8] + 1;
2474 blkY[6 + 3 * 8] = blkY[0 + 3 * 8] + 2;
2475 blkY[7 + 3 * 8] = blkY[1 + 3 * 8] + 1;
2476 blkCb[1 + 0 * 4] = blkCb[0 + 0 * 4];
2477 blkCb[2 + 0 * 4] = blkCb[0 + 0 * 4];
2478 blkCb[3 + 0 * 4] = blkCb[0 + 0 * 4];
2479 blkCb[1 + 1 * 4] = blkCb[0 + 1 * 4];
2480 blkCb[2 + 1 * 4] = blkCb[0 + 1 * 4];
2481 blkCb[3 + 1 * 4] = blkCb[0 + 1 * 4];
2482 blkCr[1 + 0 * 4] = blkCr[0 + 0 * 4];
2483 blkCr[2 + 0 * 4] = blkCr[0 + 0 * 4];
2484 blkCr[3 + 0 * 4] = blkCr[0 + 0 * 4];
2485 blkCr[1 + 1 * 4] = blkCr[0 + 1 * 4];
2486 blkCr[2 + 1 * 4] = blkCr[0 + 1 * 4];
2487 blkCr[3 + 1 * 4] = blkCr[0 + 1 * 4];
2488
2489 /*Store data back to DDR*/
2490 convUnc8x4blk(blkY, blkCb, blkCr, cmBodyBufNow, 1);
2491 }
2492
2493 blkBufCnt = (blkBufCnt==1) ? 0 : blkBufCnt + 1;
2494 }
2495
2496 hevc_print(hevc, H265_DEBUG_DETAIL,
2497 "cmBodyBuf to detbuf:\n");
2498 for (i = 0; i < 32 * 18; i++) {
2499 hevc->detbuf_adr_virt[i] = cmBodyBuf[i];
2500 if (get_dbg_flag(hevc) &
2501 H265_DEBUG_DETAIL) {
2502 if ((i & 0xf) == 0)
2503 hevc_print_cont(hevc, 0, "\n");
2504 hevc_print_cont(hevc, 0, "%02x ", cmBodyBuf[i]);
2505 }
2506 }
2507 hevc_print_cont(hevc, H265_DEBUG_DETAIL, "\n");
2508
2509 WRITE_VREG(HEVC_SAO_DBG_MODE1, 3);
2510 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2511 "%s, %d\n", __func__, __LINE__);
2512 do {
2513 tmpData32 = READ_VREG(HEVC_SAO_DBG_MODE1);
2514 } while (tmpData32);
2515 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2516 "%s, %d\n", __func__, __LINE__);
2517}
2518
2519static void delrefill(struct hevc_state_s *hevc)
2520{
2521 /*
2522 * corrRefill
2523 */
2524 /*HEVC_SAO_DBG_MODE0: picGlobalVariable
2525 [31:30]error number
2526 [29:20]error2([9:7]tilex[6:0]ctuy)
2527 [19:10]error1 [9:0]error0*/
2528 uint32_t detResult = READ_VREG(HEVC_ASSIST_SCRATCH_3);
2529 uint32_t errorIdx;
2530 uint32_t errorNum = (detResult>>30);
2531
2532 if (detResult) {
2533 hevc_print(hevc, H265_DEBUG_BUFMGR,
2534 "[corrRefillWithAmrisc] detResult=%08x\n", detResult);
2535 for (errorIdx = 0; errorIdx < errorNum; errorIdx++) {
2536 uint32_t errorPos = errorIdx * 10;
2537 uint32_t errorResult = (detResult >> errorPos) & 0x3ff;
2538 uint32_t tilex = (errorResult >> 7) - 1;
2539 uint16_t ctux = hevc->m_tile[0][tilex].start_cu_x
2540 + hevc->m_tile[0][tilex].width - 1;
2541 uint16_t ctuy = (uint16_t)(errorResult & 0x7f);
2542 uint32_t ctuPosition = (ctux<< 16) + ctuy;
2543 hevc_print(hevc, H265_DEBUG_BUFMGR,
2544 "Idx:%d tilex:%d ctu(%d(0x%x), %d(0x%x))\n",
2545 errorIdx,tilex,ctux,ctux, ctuy,ctuy);
2546 corrRefillWithAmrisc(
2547 hevc,
2548 (uint32_t)hevc->cur_pic->header_adr,
2549 hevc->pic_w,
2550 ctuPosition);
2551 }
2552
2553 WRITE_VREG(HEVC_ASSIST_SCRATCH_3, 0); /*clear status*/
2554 WRITE_VREG(HEVC_SAO_DBG_MODE0, 0);
2555 WRITE_VREG(HEVC_SAO_DBG_MODE1, 1);
2556 }
2557}
2558#endif
2559
2560static void get_rpm_param(union param_u *params)
2561{
2562 int i;
2563 unsigned int data32;
2564
2565 for (i = 0; i < 128; i++) {
2566 do {
2567 data32 = READ_VREG(RPM_CMD_REG);
2568 /* hevc_print(hevc, 0, "%x\n", data32); */
2569 } while ((data32 & 0x10000) == 0);
2570 params->l.data[i] = data32 & 0xffff;
2571 /* hevc_print(hevc, 0, "%x\n", data32); */
2572 WRITE_VREG(RPM_CMD_REG, 0);
2573 }
2574}
2575
2576static struct PIC_s *get_pic_by_POC(struct hevc_state_s *hevc, int POC)
2577{
2578 int i;
2579 struct PIC_s *pic;
2580 struct PIC_s *ret_pic = NULL;
2581 if (POC == INVALID_POC)
2582 return NULL;
2583 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2584 pic = hevc->m_PIC[i];
2585 if (pic == NULL || pic->index == -1 ||
2586 pic->BUF_index == -1)
2587 continue;
2588 if (pic->POC == POC) {
2589 if (ret_pic == NULL)
2590 ret_pic = pic;
2591 else {
2592 if (pic->decode_idx > ret_pic->decode_idx)
2593 ret_pic = pic;
2594 }
2595 }
2596 }
2597 return ret_pic;
2598}
2599
2600static struct PIC_s *get_ref_pic_by_POC(struct hevc_state_s *hevc, int POC)
2601{
2602 int i;
2603 struct PIC_s *pic;
2604 struct PIC_s *ret_pic = NULL;
2605
2606 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2607 pic = hevc->m_PIC[i];
2608 if (pic == NULL || pic->index == -1 ||
2609 pic->BUF_index == -1)
2610 continue;
2611 if ((pic->POC == POC) && (pic->referenced)) {
2612 if (ret_pic == NULL)
2613 ret_pic = pic;
2614 else {
2615 if (pic->decode_idx > ret_pic->decode_idx)
2616 ret_pic = pic;
2617 }
2618 }
2619 }
2620
2621 if (ret_pic == NULL) {
2622 if (get_dbg_flag(hevc)) {
2623 hevc_print(hevc, 0,
2624 "Wrong, POC of %d is not in referenced list\n",
2625 POC);
2626 }
2627 ret_pic = get_pic_by_POC(hevc, POC);
2628 }
2629 return ret_pic;
2630}
2631
2632static unsigned int log2i(unsigned int val)
2633{
2634 unsigned int ret = -1;
2635
2636 while (val != 0) {
2637 val >>= 1;
2638 ret++;
2639 }
2640 return ret;
2641}
2642
2643static int init_buf_spec(struct hevc_state_s *hevc);
2644static void uninit_mmu_buffers(struct hevc_state_s *hevc)
2645{
2646 if (hevc->mmu_box)
2647 decoder_mmu_box_free(hevc->mmu_box);
2648 hevc->mmu_box = NULL;
2649
2650 if (hevc->bmmu_box)
2651 decoder_bmmu_box_free(hevc->bmmu_box);
2652 hevc->bmmu_box = NULL;
2653}
2654static int init_mmu_buffers(struct hevc_state_s *hevc)
2655{
2656 int tvp_flag = vdec_secure(hw_to_vdec(hevc)) ?
2657 CODEC_MM_FLAGS_TVP : 0;
2658 int buf_size = 64;
2659
2660 if ((hevc->max_pic_w * hevc->max_pic_h) > 0 &&
2661 (hevc->max_pic_w * hevc->max_pic_h) <= 1920*1088) {
2662 buf_size = 24;
2663 }
2664
2665 if (get_dbg_flag(hevc)) {
2666 hevc_print(hevc, 0, "%s max_w %d max_h %d\n",
2667 __func__, hevc->max_pic_w, hevc->max_pic_h);
2668 }
2669
2670 hevc->need_cache_size = buf_size * SZ_1M;
2671 hevc->sc_start_time = get_jiffies_64();
2672 if (hevc->mmu_enable
2673 && ((get_double_write_mode(hevc) & 0x10) == 0)) {
2674 hevc->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
2675 hevc->index,
2676 MAX_REF_PIC_NUM,
2677 buf_size * SZ_1M,
2678 tvp_flag
2679 );
2680 if (!hevc->mmu_box) {
2681 pr_err("h265 alloc mmu box failed!!\n");
2682 return -1;
2683 }
2684 }
2685
2686 hevc->bmmu_box = decoder_bmmu_box_alloc_box(DRIVER_NAME,
2687 hevc->index,
2688 BMMU_MAX_BUFFERS,
2689 4 + PAGE_SHIFT,
2690 CODEC_MM_FLAGS_CMA_CLEAR |
2691 CODEC_MM_FLAGS_FOR_VDECODER |
2692 tvp_flag);
2693 if (!hevc->bmmu_box) {
2694 if (hevc->mmu_box)
2695 decoder_mmu_box_free(hevc->mmu_box);
2696 hevc->mmu_box = NULL;
2697 pr_err("h265 alloc mmu box failed!!\n");
2698 return -1;
2699 }
2700 return 0;
2701}
2702
2703struct buf_stru_s
2704{
2705 int lcu_total;
2706 int mc_buffer_size_h;
2707 int mc_buffer_size_u_v_h;
2708};
2709
2710#ifndef MV_USE_FIXED_BUF
2711static void dealloc_mv_bufs(struct hevc_state_s *hevc)
2712{
2713 int i;
2714 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2715 if (hevc->m_mv_BUF[i].start_adr) {
2716 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
2717 hevc_print(hevc, 0,
2718 "dealloc mv buf(%d) adr 0x%p size 0x%x used_flag %d\n",
2719 i, hevc->m_mv_BUF[i].start_adr,
2720 hevc->m_mv_BUF[i].size,
2721 hevc->m_mv_BUF[i].used_flag);
2722 decoder_bmmu_box_free_idx(
2723 hevc->bmmu_box,
2724 MV_BUFFER_IDX(i));
2725 hevc->m_mv_BUF[i].start_adr = 0;
2726 hevc->m_mv_BUF[i].size = 0;
2727 hevc->m_mv_BUF[i].used_flag = 0;
2728 }
2729 }
2730 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2731 if (hevc->m_PIC[i] != NULL)
2732 hevc->m_PIC[i]->mv_buf_index = -1;
2733 }
2734
2735}
2736
2737static int alloc_mv_buf(struct hevc_state_s *hevc, int i)
2738{
2739 int ret = 0;
2740 /*get_cma_alloc_ref();*/ /*DEBUG_TMP*/
2741 if (decoder_bmmu_box_alloc_buf_phy
2742 (hevc->bmmu_box,
2743 MV_BUFFER_IDX(i), hevc->mv_buf_size,
2744 DRIVER_NAME,
2745 &hevc->m_mv_BUF[i].start_adr) < 0) {
2746 hevc->m_mv_BUF[i].start_adr = 0;
2747 ret = -1;
2748 } else {
2749 hevc->m_mv_BUF[i].size = hevc->mv_buf_size;
2750 hevc->m_mv_BUF[i].used_flag = 0;
2751 ret = 0;
2752 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
2753 hevc_print(hevc, 0,
2754 "MV Buffer %d: start_adr %p size %x\n",
2755 i,
2756 (void *)hevc->m_mv_BUF[i].start_adr,
2757 hevc->m_mv_BUF[i].size);
2758 }
2759 if (!vdec_secure(hw_to_vdec(hevc)) && (hevc->m_mv_BUF[i].start_adr)) {
2760 void *mem_start_virt;
2761 mem_start_virt =
2762 codec_mm_phys_to_virt(hevc->m_mv_BUF[i].start_adr);
2763 if (mem_start_virt) {
2764 memset(mem_start_virt, 0, hevc->m_mv_BUF[i].size);
2765 codec_mm_dma_flush(mem_start_virt,
2766 hevc->m_mv_BUF[i].size, DMA_TO_DEVICE);
2767 } else {
2768 mem_start_virt = codec_mm_vmap(
2769 hevc->m_mv_BUF[i].start_adr,
2770 hevc->m_mv_BUF[i].size);
2771 if (mem_start_virt) {
2772 memset(mem_start_virt, 0, hevc->m_mv_BUF[i].size);
2773 codec_mm_dma_flush(mem_start_virt,
2774 hevc->m_mv_BUF[i].size,
2775 DMA_TO_DEVICE);
2776 codec_mm_unmap_phyaddr(mem_start_virt);
2777 } else {
2778 /*not virt for tvp playing,
2779 may need clear on ucode.*/
2780 pr_err("ref %s mem_start_virt failed\n", __func__);
2781 }
2782 }
2783 }
2784 }
2785 /*put_cma_alloc_ref();*/ /*DEBUG_TMP*/
2786 return ret;
2787}
2788#endif
2789
2790static int get_mv_buf(struct hevc_state_s *hevc, struct PIC_s *pic)
2791{
2792#ifdef MV_USE_FIXED_BUF
2793 if (pic && pic->index >= 0) {
2794 if (IS_8K_SIZE(pic->width, pic->height)) {
2795 pic->mpred_mv_wr_start_addr =
2796 hevc->work_space_buf->mpred_mv.buf_start
2797 + (pic->index * MPRED_8K_MV_BUF_SIZE);
2798 } else {
2799 pic->mpred_mv_wr_start_addr =
2800 hevc->work_space_buf->mpred_mv.buf_start
2801 + (pic->index * MPRED_4K_MV_BUF_SIZE);
2802 }
2803 }
2804 return 0;
2805#else
2806 int i;
2807 int ret = -1;
2808 int new_size;
2809 if (IS_8K_SIZE(pic->width, pic->height))
2810 new_size = MPRED_8K_MV_BUF_SIZE + 0x10000;
2811 else if (IS_4K_SIZE(pic->width, pic->height))
2812 new_size = MPRED_4K_MV_BUF_SIZE + 0x10000; /*0x120000*/
2813 else
2814 new_size = MPRED_MV_BUF_SIZE + 0x10000;
2815 if (new_size != hevc->mv_buf_size) {
2816 dealloc_mv_bufs(hevc);
2817 hevc->mv_buf_size = new_size;
2818 }
2819 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2820 if (hevc->m_mv_BUF[i].start_adr &&
2821 hevc->m_mv_BUF[i].used_flag == 0) {
2822 hevc->m_mv_BUF[i].used_flag = 1;
2823 ret = i;
2824 break;
2825 }
2826 }
2827 if (ret < 0) {
2828 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2829 if (hevc->m_mv_BUF[i].start_adr == 0) {
2830 if (alloc_mv_buf(hevc, i) >= 0) {
2831 hevc->m_mv_BUF[i].used_flag = 1;
2832 ret = i;
2833 }
2834 break;
2835 }
2836 }
2837 }
2838
2839 if (ret >= 0) {
2840 pic->mv_buf_index = ret;
2841 pic->mpred_mv_wr_start_addr =
2842 (hevc->m_mv_BUF[ret].start_adr + 0xffff) &
2843 (~0xffff);
2844 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2845 "%s => %d (0x%x) size 0x%x\n",
2846 __func__, ret,
2847 pic->mpred_mv_wr_start_addr,
2848 hevc->m_mv_BUF[ret].size);
2849
2850 } else {
2851 hevc_print(hevc, 0,
2852 "%s: Error, mv buf is not enough\n",
2853 __func__);
2854 }
2855 return ret;
2856
2857#endif
2858}
2859
2860static void put_mv_buf(struct hevc_state_s *hevc,
2861 struct PIC_s *pic)
2862{
2863#ifndef MV_USE_FIXED_BUF
2864 int i = pic->mv_buf_index;
2865 if (i < 0 || i >= MAX_REF_PIC_NUM) {
2866 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2867 "%s: index %d beyond range\n",
2868 __func__, i);
2869 return;
2870 }
2871 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2872 "%s(%d): used_flag(%d)\n",
2873 __func__, i,
2874 hevc->m_mv_BUF[i].used_flag);
2875
2876 if (hevc->m_mv_BUF[i].start_adr &&
2877 hevc->m_mv_BUF[i].used_flag)
2878 hevc->m_mv_BUF[i].used_flag = 0;
2879 pic->mv_buf_index = -1;
2880#endif
2881}
2882
2883static int cal_current_buf_size(struct hevc_state_s *hevc,
2884 struct buf_stru_s *buf_stru)
2885{
2886
2887 int buf_size;
2888 int pic_width = hevc->pic_w;
2889 int pic_height = hevc->pic_h;
2890 int lcu_size = hevc->lcu_size;
2891 int pic_width_lcu = (pic_width % lcu_size) ? pic_width / lcu_size +
2892 1 : pic_width / lcu_size;
2893 int pic_height_lcu = (pic_height % lcu_size) ? pic_height / lcu_size +
2894 1 : pic_height / lcu_size;
2895 /*SUPPORT_10BIT*/
2896 int losless_comp_header_size = compute_losless_comp_header_size
2897 (pic_width, pic_height);
2898 /*always alloc buf for 10bit*/
2899 int losless_comp_body_size = compute_losless_comp_body_size
2900 (hevc, pic_width, pic_height, 0);
2901 int mc_buffer_size = losless_comp_header_size
2902 + losless_comp_body_size;
2903 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
2904 int mc_buffer_size_u_v_h = 0;
2905
2906 int dw_mode = get_double_write_mode(hevc);
2907
2908 if (hevc->mmu_enable) {
2909 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
2910 (IS_8K_SIZE(hevc->pic_w, hevc->pic_h)))
2911 buf_size = ((MMU_COMPRESS_8K_HEADER_SIZE + 0xffff) >> 16)
2912 << 16;
2913 else
2914 buf_size = ((MMU_COMPRESS_HEADER_SIZE + 0xffff) >> 16)
2915 << 16;
2916 } else
2917 buf_size = 0;
2918
2919 if (dw_mode) {
2920 int pic_width_dw = pic_width /
2921 get_double_write_ratio(hevc, dw_mode);
2922 int pic_height_dw = pic_height /
2923 get_double_write_ratio(hevc, dw_mode);
2924
2925 int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
2926 pic_width_dw / lcu_size + 1 :
2927 pic_width_dw / lcu_size;
2928 int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
2929 pic_height_dw / lcu_size + 1 :
2930 pic_height_dw / lcu_size;
2931 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
2932
2933 int mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
2934 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
2935 /*64k alignment*/
2936 buf_size += ((mc_buffer_size_u_v_h << 16) * 3);
2937 }
2938
2939 if ((!hevc->mmu_enable) &&
2940 ((dw_mode & 0x10) == 0)) {
2941 /* use compress mode without mmu,
2942 need buf for compress decoding*/
2943 buf_size += (mc_buffer_size_h << 16);
2944 }
2945
2946 /*in case start adr is not 64k alignment*/
2947 if (buf_size > 0)
2948 buf_size += 0x10000;
2949
2950 if (buf_stru) {
2951 buf_stru->lcu_total = pic_width_lcu * pic_height_lcu;
2952 buf_stru->mc_buffer_size_h = mc_buffer_size_h;
2953 buf_stru->mc_buffer_size_u_v_h = mc_buffer_size_u_v_h;
2954 }
2955
2956 hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,"pic width: %d, pic height: %d, headr: %d, body: %d, size h: %d, size uvh: %d, buf size: %x\n",
2957 pic_width, pic_height, losless_comp_header_size,
2958 losless_comp_body_size, mc_buffer_size_h,
2959 mc_buffer_size_u_v_h, buf_size);
2960
2961 return buf_size;
2962}
2963
2964static int alloc_buf(struct hevc_state_s *hevc)
2965{
2966 int i;
2967 int ret = -1;
2968 int buf_size = cal_current_buf_size(hevc, NULL);
2969
2970 if (hevc->is_used_v4l)
2971 return 0;
2972
2973 if (hevc->fatal_error & DECODER_FATAL_ERROR_NO_MEM)
2974 return ret;
2975
2976 for (i = 0; i < BUF_POOL_SIZE; i++) {
2977 if (hevc->m_BUF[i].start_adr == 0)
2978 break;
2979 }
2980 if (i < BUF_POOL_SIZE) {
2981 if (buf_size > 0) {
2982 /*get_cma_alloc_ref();*/ /*DEBUG_TMP*/
2983 /*alloc compress header first*/
2984
2985 ret = decoder_bmmu_box_alloc_buf_phy
2986 (hevc->bmmu_box,
2987 VF_BUFFER_IDX(i), buf_size,
2988 DRIVER_NAME,
2989 &hevc->m_BUF[i].start_adr);
2990 if (ret < 0) {
2991 hevc->m_BUF[i].start_adr = 0;
2992 if (i <= 8) {
2993 hevc->fatal_error |=
2994 DECODER_FATAL_ERROR_NO_MEM;
2995 hevc_print(hevc, PRINT_FLAG_ERROR,
2996 "%s[%d], size: %d, no mem fatal err\n",
2997 __func__, i, buf_size);
2998 }
2999 }
3000
3001 if (ret >= 0) {
3002 hevc->m_BUF[i].size = buf_size;
3003 hevc->m_BUF[i].used_flag = 0;
3004 ret = 0;
3005
3006 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3007 hevc_print(hevc, 0,
3008 "Buffer %d: start_adr %p size %x\n",
3009 i,
3010 (void *)hevc->m_BUF[i].start_adr,
3011 hevc->m_BUF[i].size);
3012 }
3013 /*flush the buffer make sure no cache dirty*/
3014 if (!vdec_secure(hw_to_vdec(hevc)) && (hevc->m_BUF[i].start_adr)) {
3015 void *mem_start_virt;
3016 mem_start_virt =
3017 codec_mm_phys_to_virt(hevc->m_BUF[i].start_adr);
3018 if (mem_start_virt) {
3019 memset(mem_start_virt, 0, hevc->m_BUF[i].size);
3020 codec_mm_dma_flush(mem_start_virt,
3021 hevc->m_BUF[i].size, DMA_TO_DEVICE);
3022 } else {
3023 mem_start_virt = codec_mm_vmap(
3024 hevc->m_BUF[i].start_adr,
3025 hevc->m_BUF[i].size);
3026 if (mem_start_virt) {
3027 memset(mem_start_virt, 0, hevc->m_BUF[i].size);
3028 codec_mm_dma_flush(mem_start_virt,
3029 hevc->m_BUF[i].size,
3030 DMA_TO_DEVICE);
3031 codec_mm_unmap_phyaddr(mem_start_virt);
3032 } else {
3033 /*not virt for tvp playing,
3034 may need clear on ucode.*/
3035 pr_err("ref %s mem_start_virt failed\n", __func__);
3036 }
3037 }
3038 }
3039 }
3040 /*put_cma_alloc_ref();*/ /*DEBUG_TMP*/
3041 } else
3042 ret = 0;
3043 }
3044 if (ret >= 0) {
3045 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3046 hevc_print(hevc, 0,
3047 "alloc buf(%d) for %d/%d size 0x%x) => %p\n",
3048 i, hevc->pic_w, hevc->pic_h,
3049 buf_size,
3050 hevc->m_BUF[i].start_adr);
3051 }
3052 } else {
3053 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3054 hevc_print(hevc, 0,
3055 "alloc buf(%d) for %d/%d size 0x%x) => Fail!!!\n",
3056 i, hevc->pic_w, hevc->pic_h,
3057 buf_size);
3058 }
3059 }
3060 return ret;
3061}
3062
3063static void set_buf_unused(struct hevc_state_s *hevc, int i)
3064{
3065 if (i >= 0 && i < BUF_POOL_SIZE)
3066 hevc->m_BUF[i].used_flag = 0;
3067}
3068
3069static void dealloc_unused_buf(struct hevc_state_s *hevc)
3070{
3071 int i;
3072 for (i = 0; i < BUF_POOL_SIZE; i++) {
3073 if (hevc->m_BUF[i].start_adr &&
3074 hevc->m_BUF[i].used_flag == 0) {
3075 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3076 hevc_print(hevc, 0,
3077 "dealloc buf(%d) adr 0x%p size 0x%x\n",
3078 i, hevc->m_BUF[i].start_adr,
3079 hevc->m_BUF[i].size);
3080 }
3081 if (!hevc->is_used_v4l)
3082 decoder_bmmu_box_free_idx(
3083 hevc->bmmu_box,
3084 VF_BUFFER_IDX(i));
3085 hevc->m_BUF[i].start_adr = 0;
3086 hevc->m_BUF[i].size = 0;
3087 }
3088 }
3089
3090}
3091
3092static void dealloc_pic_buf(struct hevc_state_s *hevc,
3093 struct PIC_s *pic)
3094{
3095 int i = pic->BUF_index;
3096 pic->BUF_index = -1;
3097 if (i >= 0 &&
3098 i < BUF_POOL_SIZE &&
3099 hevc->m_BUF[i].start_adr) {
3100 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3101 hevc_print(hevc, 0,
3102 "dealloc buf(%d) adr 0x%p size 0x%x\n",
3103 i, hevc->m_BUF[i].start_adr,
3104 hevc->m_BUF[i].size);
3105 }
3106
3107 if (!hevc->is_used_v4l)
3108 decoder_bmmu_box_free_idx(
3109 hevc->bmmu_box,
3110 VF_BUFFER_IDX(i));
3111 hevc->m_BUF[i].used_flag = 0;
3112 hevc->m_BUF[i].start_adr = 0;
3113 hevc->m_BUF[i].size = 0;
3114 }
3115}
3116
3117static int get_work_pic_num(struct hevc_state_s *hevc)
3118{
3119 int used_buf_num = 0;
3120 int sps_pic_buf_diff = 0;
3121
3122 if (get_dynamic_buf_num_margin(hevc) > 0) {
3123 if ((!hevc->sps_num_reorder_pics_0) &&
3124 (hevc->param.p.sps_max_dec_pic_buffering_minus1_0)) {
3125 /* the range of sps_num_reorder_pics_0 is in
3126 [0, sps_max_dec_pic_buffering_minus1_0] */
3127 used_buf_num = get_dynamic_buf_num_margin(hevc) +
3128 hevc->param.p.sps_max_dec_pic_buffering_minus1_0;
3129 } else
3130 used_buf_num = hevc->sps_num_reorder_pics_0
3131 + get_dynamic_buf_num_margin(hevc);
3132
3133 sps_pic_buf_diff = hevc->param.p.sps_max_dec_pic_buffering_minus1_0
3134 - hevc->sps_num_reorder_pics_0;
3135#ifdef MULTI_INSTANCE_SUPPORT
3136 /*
3137 need one more for multi instance, as
3138 apply_ref_pic_set() has no chanch to run to
3139 to clear referenced flag in some case
3140 */
3141 if (hevc->m_ins_flag)
3142 used_buf_num++;
3143#endif
3144 } else
3145 used_buf_num = max_buf_num;
3146
3147 if (hevc->save_buffer_mode)
3148 hevc_print(hevc, 0,
3149 "save buf _mode : dynamic_buf_num_margin %d ----> %d \n",
3150 dynamic_buf_num_margin, hevc->dynamic_buf_num_margin);
3151
3152 if (sps_pic_buf_diff >= 4)
3153 {
3154 used_buf_num += 1;
3155 }
3156
3157 if (used_buf_num > MAX_BUF_NUM)
3158 used_buf_num = MAX_BUF_NUM;
3159 return used_buf_num;
3160}
3161
3162static int get_alloc_pic_count(struct hevc_state_s *hevc)
3163{
3164 int alloc_pic_count = 0;
3165 int i;
3166 struct PIC_s *pic;
3167 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3168 pic = hevc->m_PIC[i];
3169 if (pic && pic->index >= 0)
3170 alloc_pic_count++;
3171 }
3172 return alloc_pic_count;
3173}
3174
3175static int config_pic(struct hevc_state_s *hevc, struct PIC_s *pic)
3176{
3177 int ret = -1;
3178 int i;
3179 /*int lcu_size_log2 = hevc->lcu_size_log2;
3180 int MV_MEM_UNIT=lcu_size_log2==
3181 6 ? 0x100 : lcu_size_log2==5 ? 0x40 : 0x10;*/
3182 /*int MV_MEM_UNIT = lcu_size_log2 == 6 ? 0x200 : lcu_size_log2 ==
3183 5 ? 0x80 : 0x20;
3184 int mpred_mv_end = hevc->work_space_buf->mpred_mv.buf_start +
3185 hevc->work_space_buf->mpred_mv.buf_size;*/
3186 unsigned int y_adr = 0;
3187 struct buf_stru_s buf_stru;
3188 int buf_size = cal_current_buf_size(hevc, &buf_stru);
3189 int dw_mode = get_double_write_mode(hevc);
3190 struct vdec_v4l2_buffer *fb = NULL;
3191
3192 if (hevc->is_used_v4l)
3193 buf_size = 0;
3194
3195 for (i = 0; i < BUF_POOL_SIZE; i++) {
3196 if (hevc->is_used_v4l && !hevc->m_BUF[i].start_adr) {
3197 ret = vdec_v4l_get_buffer(hevc->v4l2_ctx, &fb);
3198 if (ret) {
3199 hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,
3200 "[%d] get fb fail.\n",
3201 ((struct aml_vcodec_ctx *)
3202 (hevc->v4l2_ctx))->id);
3203 return ret;
3204 }
3205
3206 hevc->m_BUF[i].used_flag = 0;
3207 hevc->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
3208 if (fb->num_planes == 1) {
3209 hevc->m_BUF[i].start_adr = fb->m.mem[0].addr;
3210 hevc->m_BUF[i].size = fb->m.mem[0].size;
3211 hevc->m_BUF[i].y_size = fb->m.mem[0].offset;
3212 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
3213 } else if (fb->num_planes == 2) {
3214 hevc->m_BUF[i].start_adr = fb->m.mem[0].addr;
3215 hevc->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
3216 hevc->m_BUF[i].y_size = fb->m.mem[0].size;
3217 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
3218 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
3219 }
3220
3221 pic->BUF_index = i;
3222
3223 hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,
3224 "[%d] %s(), v4l ref buf addr: 0x%x\n",
3225 ((struct aml_vcodec_ctx *)
3226 (hevc->v4l2_ctx))->id, __func__, fb);
3227 }
3228
3229 if (hevc->m_BUF[i].start_adr != 0 &&
3230 hevc->m_BUF[i].used_flag == 0 &&
3231 buf_size <= hevc->m_BUF[i].size) {
3232 hevc->m_BUF[i].used_flag = 1;
3233 break;
3234 }
3235 }
3236
3237 if (i >= BUF_POOL_SIZE)
3238 return -1;
3239
3240 if (hevc->mmu_enable) {
3241 pic->header_adr = hevc->m_BUF[i].start_adr;
3242 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
3243 (IS_8K_SIZE(hevc->pic_w, hevc->pic_h)))
3244 y_adr = hevc->m_BUF[i].start_adr +
3245 MMU_COMPRESS_8K_HEADER_SIZE;
3246 else
3247 y_adr = hevc->m_BUF[i].start_adr +
3248 MMU_COMPRESS_HEADER_SIZE;
3249 } else
3250 y_adr = hevc->m_BUF[i].start_adr;
3251
3252 if (!hevc->is_used_v4l)
3253 y_adr = ((y_adr + 0xffff) >> 16) << 16; /*64k alignment*/
3254
3255 pic->POC = INVALID_POC;
3256 /*ensure get_pic_by_POC()
3257 not get the buffer not decoded*/
3258 pic->BUF_index = i;
3259
3260 if ((!hevc->mmu_enable) &&
3261 ((dw_mode & 0x10) == 0)
3262 ) {
3263 pic->mc_y_adr = y_adr;
3264 y_adr += (buf_stru.mc_buffer_size_h << 16);
3265 }
3266 pic->mc_canvas_y = pic->index;
3267 pic->mc_canvas_u_v = pic->index;
3268 if (dw_mode & 0x10) {
3269 if (hevc->is_used_v4l) {
3270 pic->mc_y_adr = y_adr;
3271 pic->mc_u_v_adr = y_adr + hevc->m_BUF[i].y_size;
3272 } else {
3273 pic->mc_y_adr = y_adr;
3274 pic->mc_u_v_adr = y_adr +
3275 ((buf_stru.mc_buffer_size_u_v_h << 16) << 1);
3276 }
3277
3278 pic->mc_canvas_y = (pic->index << 1);
3279 pic->mc_canvas_u_v = (pic->index << 1) + 1;
3280
3281 pic->dw_y_adr = pic->mc_y_adr;
3282 pic->dw_u_v_adr = pic->mc_u_v_adr;
3283 } else if (dw_mode) {
3284 pic->dw_y_adr = y_adr;
3285 pic->dw_u_v_adr = pic->dw_y_adr +
3286 ((buf_stru.mc_buffer_size_u_v_h << 16) << 1);
3287 }
3288
3289
3290 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3291 hevc_print(hevc, 0,
3292 "%s index %d BUF_index %d mc_y_adr %x\n",
3293 __func__, pic->index,
3294 pic->BUF_index, pic->mc_y_adr);
3295 if (hevc->mmu_enable &&
3296 dw_mode)
3297 hevc_print(hevc, 0,
3298 "mmu double write adr %ld\n",
3299 pic->cma_alloc_addr);
3300
3301
3302 }
3303 ret = 0;
3304
3305 return ret;
3306}
3307
3308static void init_pic_list(struct hevc_state_s *hevc)
3309{
3310 int i;
3311 int init_buf_num = get_work_pic_num(hevc);
3312 int dw_mode = get_double_write_mode(hevc);
3313 struct vdec_s *vdec = hw_to_vdec(hevc);
3314 /*alloc decoder buf*/
3315 for (i = 0; i < init_buf_num; i++) {
3316 if (alloc_buf(hevc) < 0) {
3317 if (i <= 8) {
3318 /*if alloced (i+1)>=9
3319 don't send errors.*/
3320 hevc->fatal_error |=
3321 DECODER_FATAL_ERROR_NO_MEM;
3322 }
3323 break;
3324 }
3325 }
3326
3327 for (i = 0; i < init_buf_num; i++) {
3328 struct PIC_s *pic =
3329 vmalloc(sizeof(struct PIC_s));
3330 if (pic == NULL) {
3331 hevc_print(hevc, 0,
3332 "%s: alloc pic %d fail!!!\n",
3333 __func__, i);
3334 break;
3335 }
3336 memset(pic, 0, sizeof(struct PIC_s));
3337 hevc->m_PIC[i] = pic;
3338 pic->index = i;
3339 pic->BUF_index = -1;
3340 pic->mv_buf_index = -1;
3341 if (vdec->parallel_dec == 1) {
3342 pic->y_canvas_index = -1;
3343 pic->uv_canvas_index = -1;
3344 }
3345
3346 pic->width = hevc->pic_w;
3347 pic->height = hevc->pic_h;
3348 pic->double_write_mode = dw_mode;
3349
3350 if (!hevc->is_used_v4l) {
3351 if (config_pic(hevc, pic) < 0) {
3352 if (get_dbg_flag(hevc))
3353 hevc_print(hevc, 0,
3354 "Config_pic %d fail\n", pic->index);
3355 pic->index = -1;
3356 i++;
3357 break;
3358 }
3359
3360 if (pic->double_write_mode)
3361 set_canvas(hevc, pic);
3362 }
3363 }
3364
3365 for (; i < MAX_REF_PIC_NUM; i++) {
3366 struct PIC_s *pic =
3367 vmalloc(sizeof(struct PIC_s));
3368 if (pic == NULL) {
3369 hevc_print(hevc, 0,
3370 "%s: alloc pic %d fail!!!\n",
3371 __func__, i);
3372 break;
3373 }
3374 memset(pic, 0, sizeof(struct PIC_s));
3375 hevc->m_PIC[i] = pic;
3376 pic->index = -1;
3377 pic->BUF_index = -1;
3378 if (vdec->parallel_dec == 1) {
3379 pic->y_canvas_index = -1;
3380 pic->uv_canvas_index = -1;
3381 }
3382 }
3383
3384}
3385
3386static void uninit_pic_list(struct hevc_state_s *hevc)
3387{
3388 struct vdec_s *vdec = hw_to_vdec(hevc);
3389 int i;
3390#ifndef MV_USE_FIXED_BUF
3391 dealloc_mv_bufs(hevc);
3392#endif
3393 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3394 struct PIC_s *pic = hevc->m_PIC[i];
3395
3396 if (pic) {
3397 if (vdec->parallel_dec == 1) {
3398 vdec->free_canvas_ex(pic->y_canvas_index, vdec->id);
3399 vdec->free_canvas_ex(pic->uv_canvas_index, vdec->id);
3400 }
3401 release_aux_data(hevc, pic);
3402 vfree(pic);
3403 hevc->m_PIC[i] = NULL;
3404 }
3405 }
3406}
3407
3408#ifdef LOSLESS_COMPRESS_MODE
3409static void init_decode_head_hw(struct hevc_state_s *hevc)
3410{
3411
3412 struct BuffInfo_s *buf_spec = hevc->work_space_buf;
3413 unsigned int data32;
3414
3415 int losless_comp_header_size =
3416 compute_losless_comp_header_size(hevc->pic_w,
3417 hevc->pic_h);
3418 int losless_comp_body_size = compute_losless_comp_body_size(hevc,
3419 hevc->pic_w, hevc->pic_h, hevc->mem_saving_mode);
3420
3421 hevc->losless_comp_body_size = losless_comp_body_size;
3422
3423
3424 if (hevc->mmu_enable) {
3425 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3426 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
3427 } else {
3428 if (hevc->mem_saving_mode == 1)
3429 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
3430 (1 << 3) | ((workaround_enable & 2) ? 1 : 0));
3431 else
3432 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
3433 ((workaround_enable & 2) ? 1 : 0));
3434 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3435 /*
3436 *WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);
3437 * //8-bit mode
3438 */
3439 }
3440 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3441 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3442 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3443
3444 if (hevc->mmu_enable) {
3445 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
3446 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR,
3447 buf_spec->mmu_vbh.buf_start +
3448 buf_spec->mmu_vbh.buf_size/2);
3449 data32 = READ_VREG(HEVC_SAO_CTRL9);
3450 data32 |= 0x1;
3451 WRITE_VREG(HEVC_SAO_CTRL9, data32);
3452
3453 /* use HEVC_CM_HEADER_START_ADDR */
3454 data32 = READ_VREG(HEVC_SAO_CTRL5);
3455 data32 |= (1<<10);
3456 WRITE_VREG(HEVC_SAO_CTRL5, data32);
3457 }
3458
3459 if (!hevc->m_ins_flag)
3460 hevc_print(hevc, 0,
3461 "%s: (%d, %d) body_size 0x%x header_size 0x%x\n",
3462 __func__, hevc->pic_w, hevc->pic_h,
3463 losless_comp_body_size, losless_comp_header_size);
3464
3465}
3466#endif
3467#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
3468
3469static void init_pic_list_hw(struct hevc_state_s *hevc)
3470{
3471 int i;
3472 int cur_pic_num = MAX_REF_PIC_NUM;
3473 int dw_mode = get_double_write_mode(hevc);
3474 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL)
3475 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
3476 (0x1 << 1) | (0x1 << 2));
3477 else
3478 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);
3479
3480 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3481 if (hevc->m_PIC[i] == NULL ||
3482 hevc->m_PIC[i]->index == -1) {
3483 cur_pic_num = i;
3484 break;
3485 }
3486 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL) {
3487 if (hevc->mmu_enable && ((dw_mode & 0x10) == 0))
3488 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3489 hevc->m_PIC[i]->header_adr>>5);
3490 else
3491 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3492 hevc->m_PIC[i]->mc_y_adr >> 5);
3493 } else
3494 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3495 hevc->m_PIC[i]->mc_y_adr |
3496 (hevc->m_PIC[i]->mc_canvas_y << 8) | 0x1);
3497 if (dw_mode & 0x10) {
3498 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL) {
3499 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3500 hevc->m_PIC[i]->mc_u_v_adr >> 5);
3501 }
3502 else
3503 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3504 hevc->m_PIC[i]->mc_u_v_adr |
3505 (hevc->m_PIC[i]->mc_canvas_u_v << 8)
3506 | 0x1);
3507 }
3508 }
3509 if (cur_pic_num == 0)
3510 return;
3511 for (; i < MAX_REF_PIC_NUM; i++) {
3512 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL) {
3513 if (hevc->mmu_enable && ((dw_mode & 0x10) == 0))
3514 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3515 hevc->m_PIC[cur_pic_num-1]->header_adr>>5);
3516 else
3517 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3518 hevc->m_PIC[cur_pic_num-1]->mc_y_adr >> 5);
3519#ifndef LOSLESS_COMPRESS_MODE
3520 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3521 hevc->m_PIC[cur_pic_num-1]->mc_u_v_adr >> 5);
3522#endif
3523 } else {
3524 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3525 hevc->m_PIC[cur_pic_num-1]->mc_y_adr|
3526 (hevc->m_PIC[cur_pic_num-1]->mc_canvas_y<<8)
3527 | 0x1);
3528#ifndef LOSLESS_COMPRESS_MODE
3529 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3530 hevc->m_PIC[cur_pic_num-1]->mc_u_v_adr|
3531 (hevc->m_PIC[cur_pic_num-1]->mc_canvas_u_v<<8)
3532 | 0x1);
3533#endif
3534 }
3535 }
3536
3537 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
3538
3539 /* Zero out canvas registers in IPP -- avoid simulation X */
3540 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
3541 (0 << 8) | (0 << 1) | 1);
3542 for (i = 0; i < 32; i++)
3543 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
3544
3545#ifdef LOSLESS_COMPRESS_MODE
3546 if ((dw_mode & 0x10) == 0)
3547 init_decode_head_hw(hevc);
3548#endif
3549
3550}
3551
3552
3553static void dump_pic_list(struct hevc_state_s *hevc)
3554{
3555 int i;
3556 struct PIC_s *pic;
3557
3558 hevc_print(hevc, 0,
3559 "pic_list_init_flag is %d\r\n", hevc->pic_list_init_flag);
3560 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3561 pic = hevc->m_PIC[i];
3562 if (pic == NULL || pic->index == -1)
3563 continue;
3564 hevc_print_cont(hevc, 0,
3565 "index %d buf_idx %d mv_idx %d decode_idx:%d, POC:%d, referenced:%d, ",
3566 pic->index, pic->BUF_index,
3567#ifndef MV_USE_FIXED_BUF
3568 pic->mv_buf_index,
3569#else
3570 -1,
3571#endif
3572 pic->decode_idx, pic->POC, pic->referenced);
3573 hevc_print_cont(hevc, 0,
3574 "num_reorder_pic:%d, output_mark:%d, error_mark:%d w/h %d,%d",
3575 pic->num_reorder_pic, pic->output_mark, pic->error_mark,
3576 pic->width, pic->height);
3577 hevc_print_cont(hevc, 0,
3578 "output_ready:%d, mv_wr_start %x vf_ref %d\n",
3579 pic->output_ready, pic->mpred_mv_wr_start_addr,
3580 pic->vf_ref);
3581 }
3582}
3583
3584static void clear_referenced_flag(struct hevc_state_s *hevc)
3585{
3586 int i;
3587 struct PIC_s *pic;
3588 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3589 pic = hevc->m_PIC[i];
3590 if (pic == NULL || pic->index == -1)
3591 continue;
3592 if (pic->referenced) {
3593 pic->referenced = 0;
3594 put_mv_buf(hevc, pic);
3595 }
3596 }
3597}
3598
3599static void clear_poc_flag(struct hevc_state_s *hevc)
3600{
3601 int i;
3602 struct PIC_s *pic;
3603 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3604 pic = hevc->m_PIC[i];
3605 if (pic == NULL || pic->index == -1)
3606 continue;
3607 pic->POC = INVALID_POC;
3608 }
3609}
3610
3611static struct PIC_s *output_pic(struct hevc_state_s *hevc,
3612 unsigned char flush_flag)
3613{
3614 int num_pic_not_yet_display = 0;
3615 int i;
3616 struct PIC_s *pic;
3617 struct PIC_s *pic_display = NULL;
3618 struct vdec_s *vdec = hw_to_vdec(hevc);
3619
3620 if (hevc->i_only & 0x4) {
3621 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3622 pic = hevc->m_PIC[i];
3623 if (pic == NULL ||
3624 (pic->index == -1) ||
3625 (pic->BUF_index == -1) ||
3626 (pic->POC == INVALID_POC))
3627 continue;
3628 if (pic->output_mark) {
3629 if (pic_display) {
3630 if (pic->decode_idx <
3631 pic_display->decode_idx)
3632 pic_display = pic;
3633
3634 } else
3635 pic_display = pic;
3636
3637 }
3638 }
3639 if (pic_display) {
3640 pic_display->output_mark = 0;
3641 pic_display->recon_mark = 0;
3642 pic_display->output_ready = 1;
3643 pic_display->referenced = 0;
3644 put_mv_buf(hevc, pic_display);
3645 }
3646 } else {
3647 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3648 pic = hevc->m_PIC[i];
3649 if (pic == NULL ||
3650 (pic->index == -1) ||
3651 (pic->BUF_index == -1) ||
3652 (pic->POC == INVALID_POC))
3653 continue;
3654 if (pic->output_mark)
3655 num_pic_not_yet_display++;
3656 if (pic->slice_type == 2 &&
3657 hevc->vf_pre_count == 0 &&
3658 fast_output_enable & 0x1) {
3659 /*fast output for first I picture*/
3660 pic->num_reorder_pic = 0;
3661 if (vdec->master || vdec->slave)
3662 pic_display = pic;
3663 hevc_print(hevc, 0, "VH265: output first frame\n");
3664 }
3665 }
3666
3667 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3668 pic = hevc->m_PIC[i];
3669 if (pic == NULL ||
3670 (pic->index == -1) ||
3671 (pic->BUF_index == -1) ||
3672 (pic->POC == INVALID_POC))
3673 continue;
3674 if (pic->output_mark) {
3675 if (pic_display) {
3676 if (pic->POC < pic_display->POC)
3677 pic_display = pic;
3678 else if ((pic->POC == pic_display->POC)
3679 && (pic->decode_idx <
3680 pic_display->
3681 decode_idx))
3682 pic_display
3683 = pic;
3684 } else
3685 pic_display = pic;
3686 }
3687 }
3688 if (pic_display) {
3689 if ((num_pic_not_yet_display >
3690 pic_display->num_reorder_pic)
3691 || flush_flag) {
3692 pic_display->output_mark = 0;
3693 pic_display->recon_mark = 0;
3694 pic_display->output_ready = 1;
3695 } else if (num_pic_not_yet_display >=
3696 (MAX_REF_PIC_NUM - 1)) {
3697 pic_display->output_mark = 0;
3698 pic_display->recon_mark = 0;
3699 pic_display->output_ready = 1;
3700 hevc_print(hevc, 0,
3701 "Warning, num_reorder_pic %d is byeond buf num\n",
3702 pic_display->num_reorder_pic);
3703 } else
3704 pic_display = NULL;
3705 }
3706 }
3707
3708 if (pic_display && (hevc->vf_pre_count == 1) && (hevc->first_pic_flag == 1)) {
3709 pic_display = NULL;
3710 hevc->first_pic_flag = 0;
3711 }
3712 return pic_display;
3713}
3714
3715static int config_mc_buffer(struct hevc_state_s *hevc, struct PIC_s *cur_pic)
3716{
3717 int i;
3718 struct PIC_s *pic;
3719
3720 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3721 hevc_print(hevc, 0,
3722 "config_mc_buffer entered .....\n");
3723 if (cur_pic->slice_type != 2) { /* P and B pic */
3724 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
3725 (0 << 8) | (0 << 1) | 1);
3726 for (i = 0; i < cur_pic->RefNum_L0; i++) {
3727 pic =
3728 get_ref_pic_by_POC(hevc,
3729 cur_pic->
3730 m_aiRefPOCList0[cur_pic->
3731 slice_idx][i]);
3732 if (pic) {
3733 if ((pic->width != hevc->pic_w) ||
3734 (pic->height != hevc->pic_h)) {
3735 hevc_print(hevc, 0,
3736 "%s: Wrong reference pic (poc %d) width/height %d/%d\n",
3737 __func__, pic->POC,
3738 pic->width, pic->height);
3739 cur_pic->error_mark = 1;
3740 }
3741 if (pic->error_mark && (ref_frame_mark_flag[hevc->index]))
3742 cur_pic->error_mark = 1;
3743 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
3744 (pic->mc_canvas_u_v << 16)
3745 | (pic->mc_canvas_u_v
3746 << 8) |
3747 pic->mc_canvas_y);
3748 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3749 hevc_print_cont(hevc, 0,
3750 "refid %x mc_canvas_u_v %x",
3751 i, pic->mc_canvas_u_v);
3752 hevc_print_cont(hevc, 0,
3753 " mc_canvas_y %x\n",
3754 pic->mc_canvas_y);
3755 }
3756 } else
3757 cur_pic->error_mark = 1;
3758
3759 if (pic == NULL || pic->error_mark) {
3760 hevc_print(hevc, 0,
3761 "Error %s, %dth poc (%d) %s",
3762 __func__, i,
3763 cur_pic->m_aiRefPOCList0[cur_pic->
3764 slice_idx][i],
3765 pic ? "has error" :
3766 "not in list0");
3767 }
3768 }
3769 }
3770 if (cur_pic->slice_type == 0) { /* B pic */
3771 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3772 hevc_print(hevc, 0,
3773 "config_mc_buffer RefNum_L1\n");
3774 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
3775 (16 << 8) | (0 << 1) | 1);
3776
3777 for (i = 0; i < cur_pic->RefNum_L1; i++) {
3778 pic =
3779 get_ref_pic_by_POC(hevc,
3780 cur_pic->
3781 m_aiRefPOCList1[cur_pic->
3782 slice_idx][i]);
3783 if (pic) {
3784 if ((pic->width != hevc->pic_w) ||
3785 (pic->height != hevc->pic_h)) {
3786 hevc_print(hevc, 0,
3787 "%s: Wrong reference pic (poc %d) width/height %d/%d\n",
3788 __func__, pic->POC,
3789 pic->width, pic->height);
3790 cur_pic->error_mark = 1;
3791 }
3792
3793 if (pic->error_mark && (ref_frame_mark_flag[hevc->index]))
3794 cur_pic->error_mark = 1;
3795 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
3796 (pic->mc_canvas_u_v << 16)
3797 | (pic->mc_canvas_u_v
3798 << 8) |
3799 pic->mc_canvas_y);
3800 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3801 hevc_print_cont(hevc, 0,
3802 "refid %x mc_canvas_u_v %x",
3803 i, pic->mc_canvas_u_v);
3804 hevc_print_cont(hevc, 0,
3805 " mc_canvas_y %x\n",
3806 pic->mc_canvas_y);
3807 }
3808 } else
3809 cur_pic->error_mark = 1;
3810
3811 if (pic == NULL || pic->error_mark) {
3812 hevc_print(hevc, 0,
3813 "Error %s, %dth poc (%d) %s",
3814 __func__, i,
3815 cur_pic->m_aiRefPOCList1[cur_pic->
3816 slice_idx][i],
3817 pic ? "has error" :
3818 "not in list1");
3819 }
3820 }
3821 }
3822 return 0;
3823}
3824
3825static void apply_ref_pic_set(struct hevc_state_s *hevc, int cur_poc,
3826 union param_u *params)
3827{
3828 int ii, i;
3829 int poc_tmp;
3830 struct PIC_s *pic;
3831 unsigned char is_referenced;
3832 /* hevc_print(hevc, 0,
3833 "%s cur_poc %d\n", __func__, cur_poc); */
3834 if (pic_list_debug & 0x2) {
3835 pr_err("cur poc %d\n", cur_poc);
3836 }
3837 for (ii = 0; ii < MAX_REF_PIC_NUM; ii++) {
3838 pic = hevc->m_PIC[ii];
3839 if (pic == NULL ||
3840 pic->index == -1 ||
3841 pic->BUF_index == -1
3842 )
3843 continue;
3844
3845 if ((pic->referenced == 0 || pic->POC == cur_poc))
3846 continue;
3847 is_referenced = 0;
3848 for (i = 0; i < 16; i++) {
3849 int delt;
3850
3851 if (params->p.CUR_RPS[i] & 0x8000)
3852 break;
3853 delt =
3854 params->p.CUR_RPS[i] &
3855 ((1 << (RPS_USED_BIT - 1)) - 1);
3856 if (params->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
3857 poc_tmp =
3858 cur_poc - ((1 << (RPS_USED_BIT - 1)) -
3859 delt);
3860 } else
3861 poc_tmp = cur_poc + delt;
3862 if (poc_tmp == pic->POC) {
3863 is_referenced = 1;
3864 /* hevc_print(hevc, 0, "i is %d\n", i); */
3865 break;
3866 }
3867 }
3868 if (is_referenced == 0) {
3869 pic->referenced = 0;
3870 put_mv_buf(hevc, pic);
3871 /* hevc_print(hevc, 0,
3872 "set poc %d reference to 0\n", pic->POC); */
3873 if (pic_list_debug & 0x2) {
3874 pr_err("set poc %d reference to 0\n", pic->POC);
3875 }
3876 }
3877 }
3878
3879}
3880
3881static void set_ref_pic_list(struct hevc_state_s *hevc, union param_u *params)
3882{
3883 struct PIC_s *pic = hevc->cur_pic;
3884 int i, rIdx;
3885 int num_neg = 0;
3886 int num_pos = 0;
3887 int total_num;
3888 int num_ref_idx_l0_active =
3889 (params->p.num_ref_idx_l0_active >
3890 MAX_REF_ACTIVE) ? MAX_REF_ACTIVE :
3891 params->p.num_ref_idx_l0_active;
3892 int num_ref_idx_l1_active =
3893 (params->p.num_ref_idx_l1_active >
3894 MAX_REF_ACTIVE) ? MAX_REF_ACTIVE :
3895 params->p.num_ref_idx_l1_active;
3896
3897 int RefPicSetStCurr0[16];
3898 int RefPicSetStCurr1[16];
3899
3900 for (i = 0; i < 16; i++) {
3901 RefPicSetStCurr0[i] = 0;
3902 RefPicSetStCurr1[i] = 0;
3903 pic->m_aiRefPOCList0[pic->slice_idx][i] = 0;
3904 pic->m_aiRefPOCList1[pic->slice_idx][i] = 0;
3905 }
3906 for (i = 0; i < 16; i++) {
3907 if (params->p.CUR_RPS[i] & 0x8000)
3908 break;
3909 if ((params->p.CUR_RPS[i] >> RPS_USED_BIT) & 1) {
3910 int delt =
3911 params->p.CUR_RPS[i] &
3912 ((1 << (RPS_USED_BIT - 1)) - 1);
3913
3914 if ((params->p.CUR_RPS[i] >> (RPS_USED_BIT - 1)) & 1) {
3915 RefPicSetStCurr0[num_neg] =
3916 pic->POC - ((1 << (RPS_USED_BIT - 1)) -
3917 delt);
3918 /* hevc_print(hevc, 0,
3919 * "RefPicSetStCurr0 %x %x %x\n",
3920 * RefPicSetStCurr0[num_neg], pic->POC,
3921 * (0x800-(params[i]&0x7ff)));
3922 */
3923 num_neg++;
3924 } else {
3925 RefPicSetStCurr1[num_pos] = pic->POC + delt;
3926 /* hevc_print(hevc, 0,
3927 * "RefPicSetStCurr1 %d\n",
3928 * RefPicSetStCurr1[num_pos]);
3929 */
3930 num_pos++;
3931 }
3932 }
3933 }
3934 total_num = num_neg + num_pos;
3935 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3936 hevc_print(hevc, 0,
3937 "%s: curpoc %d slice_type %d, total %d ",
3938 __func__, pic->POC, params->p.slice_type, total_num);
3939 hevc_print_cont(hevc, 0,
3940 "num_neg %d num_list0 %d num_list1 %d\n",
3941 num_neg, num_ref_idx_l0_active, num_ref_idx_l1_active);
3942 }
3943
3944 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3945 hevc_print(hevc, 0,
3946 "HEVC Stream buf start ");
3947 hevc_print_cont(hevc, 0,
3948 "%x end %x wr %x rd %x lev %x ctl %x intctl %x\n",
3949 READ_VREG(HEVC_STREAM_START_ADDR),
3950 READ_VREG(HEVC_STREAM_END_ADDR),
3951 READ_VREG(HEVC_STREAM_WR_PTR),
3952 READ_VREG(HEVC_STREAM_RD_PTR),
3953 READ_VREG(HEVC_STREAM_LEVEL),
3954 READ_VREG(HEVC_STREAM_FIFO_CTL),
3955 READ_VREG(HEVC_PARSER_INT_CONTROL));
3956 }
3957
3958 if (total_num > 0) {
3959 if (params->p.modification_flag & 0x1) {
3960 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3961 hevc_print(hevc, 0, "ref0 POC (modification):");
3962 for (rIdx = 0; rIdx < num_ref_idx_l0_active; rIdx++) {
3963 int cIdx = params->p.modification_list[rIdx];
3964
3965 pic->m_aiRefPOCList0[pic->slice_idx][rIdx] =
3966 cIdx >=
3967 num_neg ? RefPicSetStCurr1[cIdx -
3968 num_neg] :
3969 RefPicSetStCurr0[cIdx];
3970 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3971 hevc_print_cont(hevc, 0, "%d ",
3972 pic->m_aiRefPOCList0[pic->
3973 slice_idx]
3974 [rIdx]);
3975 }
3976 }
3977 } else {
3978 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3979 hevc_print(hevc, 0, "ref0 POC:");
3980 for (rIdx = 0; rIdx < num_ref_idx_l0_active; rIdx++) {
3981 int cIdx = rIdx % total_num;
3982
3983 pic->m_aiRefPOCList0[pic->slice_idx][rIdx] =
3984 cIdx >=
3985 num_neg ? RefPicSetStCurr1[cIdx -
3986 num_neg] :
3987 RefPicSetStCurr0[cIdx];
3988 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3989 hevc_print_cont(hevc, 0, "%d ",
3990 pic->m_aiRefPOCList0[pic->
3991 slice_idx]
3992 [rIdx]);
3993 }
3994 }
3995 }
3996 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3997 hevc_print_cont(hevc, 0, "\n");
3998 if (params->p.slice_type == B_SLICE) {
3999 if (params->p.modification_flag & 0x2) {
4000 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4001 hevc_print(hevc, 0,
4002 "ref1 POC (modification):");
4003 for (rIdx = 0; rIdx < num_ref_idx_l1_active;
4004 rIdx++) {
4005 int cIdx;
4006
4007 if (params->p.modification_flag & 0x1) {
4008 cIdx =
4009 params->p.
4010 modification_list
4011 [num_ref_idx_l0_active +
4012 rIdx];
4013 } else {
4014 cIdx =
4015 params->p.
4016 modification_list[rIdx];
4017 }
4018 pic->m_aiRefPOCList1[pic->
4019 slice_idx][rIdx] =
4020 cIdx >=
4021 num_pos ?
4022 RefPicSetStCurr0[cIdx - num_pos]
4023 : RefPicSetStCurr1[cIdx];
4024 if (get_dbg_flag(hevc) &
4025 H265_DEBUG_BUFMGR) {
4026 hevc_print_cont(hevc, 0, "%d ",
4027 pic->
4028 m_aiRefPOCList1[pic->
4029 slice_idx]
4030 [rIdx]);
4031 }
4032 }
4033 } else {
4034 if (get_dbg_flag(hevc) &
4035 H265_DEBUG_BUFMGR)
4036 hevc_print(hevc, 0, "ref1 POC:");
4037 for (rIdx = 0; rIdx < num_ref_idx_l1_active;
4038 rIdx++) {
4039 int cIdx = rIdx % total_num;
4040
4041 pic->m_aiRefPOCList1[pic->
4042 slice_idx][rIdx] =
4043 cIdx >=
4044 num_pos ?
4045 RefPicSetStCurr0[cIdx -
4046 num_pos]
4047 : RefPicSetStCurr1[cIdx];
4048 if (get_dbg_flag(hevc) &
4049 H265_DEBUG_BUFMGR) {
4050 hevc_print_cont(hevc, 0, "%d ",
4051 pic->
4052 m_aiRefPOCList1[pic->
4053 slice_idx]
4054 [rIdx]);
4055 }
4056 }
4057 }
4058 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4059 hevc_print_cont(hevc, 0, "\n");
4060 }
4061 }
4062 /*set m_PIC */
4063 pic->slice_type = (params->p.slice_type == I_SLICE) ? 2 :
4064 (params->p.slice_type == P_SLICE) ? 1 :
4065 (params->p.slice_type == B_SLICE) ? 0 : 3;
4066 pic->RefNum_L0 = num_ref_idx_l0_active;
4067 pic->RefNum_L1 = num_ref_idx_l1_active;
4068}
4069
4070static void update_tile_info(struct hevc_state_s *hevc, int pic_width_cu,
4071 int pic_height_cu, int sao_mem_unit,
4072 union param_u *params)
4073{
4074 int i, j;
4075 int start_cu_x, start_cu_y;
4076 int sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
4077 int sao_abv_size = sao_mem_unit * pic_width_cu;
4078#ifdef DETREFILL_ENABLE
4079 if (hevc->is_swap && get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
4080 int tmpRefillLcuSize = 1 <<
4081 (params->p.log2_min_coding_block_size_minus3 +
4082 3 + params->p.log2_diff_max_min_coding_block_size);
4083 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
4084 "%x, %x, %x, %x\n",
4085 params->p.slice_segment_address,
4086 params->p.bit_depth,
4087 params->p.tiles_enabled_flag,
4088 tmpRefillLcuSize);
4089 if (params->p.slice_segment_address == 0 &&
4090 params->p.bit_depth != 0 &&
4091 (params->p.tiles_enabled_flag & 1) &&
4092 tmpRefillLcuSize == 64)
4093 hevc->delrefill_check = 1;
4094 else
4095 hevc->delrefill_check = 0;
4096 }
4097#endif
4098
4099 hevc->tile_enabled = params->p.tiles_enabled_flag & 1;
4100 if (params->p.tiles_enabled_flag & 1) {
4101 hevc->num_tile_col = params->p.num_tile_columns_minus1 + 1;
4102 hevc->num_tile_row = params->p.num_tile_rows_minus1 + 1;
4103
4104 if (hevc->num_tile_row > MAX_TILE_ROW_NUM
4105 || hevc->num_tile_row <= 0) {
4106 hevc->num_tile_row = 1;
4107 hevc_print(hevc, 0,
4108 "%s: num_tile_rows_minus1 (%d) error!!\n",
4109 __func__, params->p.num_tile_rows_minus1);
4110 }
4111 if (hevc->num_tile_col > MAX_TILE_COL_NUM
4112 || hevc->num_tile_col <= 0) {
4113 hevc->num_tile_col = 1;
4114 hevc_print(hevc, 0,
4115 "%s: num_tile_columns_minus1 (%d) error!!\n",
4116 __func__, params->p.num_tile_columns_minus1);
4117 }
4118 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4119 hevc_print(hevc, 0,
4120 "%s pic_w_cu %d pic_h_cu %d tile_enabled ",
4121 __func__, pic_width_cu, pic_height_cu);
4122 hevc_print_cont(hevc, 0,
4123 "num_tile_col %d num_tile_row %d:\n",
4124 hevc->num_tile_col, hevc->num_tile_row);
4125 }
4126
4127 if (params->p.tiles_enabled_flag & 2) { /* uniform flag */
4128 int w = pic_width_cu / hevc->num_tile_col;
4129 int h = pic_height_cu / hevc->num_tile_row;
4130
4131 start_cu_y = 0;
4132 for (i = 0; i < hevc->num_tile_row; i++) {
4133 start_cu_x = 0;
4134 for (j = 0; j < hevc->num_tile_col; j++) {
4135 if (j == (hevc->num_tile_col - 1)) {
4136 hevc->m_tile[i][j].width =
4137 pic_width_cu -
4138 start_cu_x;
4139 } else
4140 hevc->m_tile[i][j].width = w;
4141 if (i == (hevc->num_tile_row - 1)) {
4142 hevc->m_tile[i][j].height =
4143 pic_height_cu -
4144 start_cu_y;
4145 } else
4146 hevc->m_tile[i][j].height = h;
4147 hevc->m_tile[i][j].start_cu_x
4148 = start_cu_x;
4149 hevc->m_tile[i][j].start_cu_y
4150 = start_cu_y;
4151 hevc->m_tile[i][j].sao_vb_start_addr =
4152 hevc->work_space_buf->sao_vb.
4153 buf_start + j * sao_vb_size;
4154 hevc->m_tile[i][j].sao_abv_start_addr =
4155 hevc->work_space_buf->sao_abv.
4156 buf_start + i * sao_abv_size;
4157 if (get_dbg_flag(hevc) &
4158 H265_DEBUG_BUFMGR) {
4159 hevc_print_cont(hevc, 0,
4160 "{y=%d, x=%d w %d h %d ",
4161 i, j, hevc->m_tile[i][j].width,
4162 hevc->m_tile[i][j].height);
4163 hevc_print_cont(hevc, 0,
4164 "start_x %d start_y %d ",
4165 hevc->m_tile[i][j].start_cu_x,
4166 hevc->m_tile[i][j].start_cu_y);
4167 hevc_print_cont(hevc, 0,
4168 "sao_vb_start 0x%x ",
4169 hevc->m_tile[i][j].
4170 sao_vb_start_addr);
4171 hevc_print_cont(hevc, 0,
4172 "sao_abv_start 0x%x}\n",
4173 hevc->m_tile[i][j].
4174 sao_abv_start_addr);
4175 }
4176 start_cu_x += hevc->m_tile[i][j].width;
4177
4178 }
4179 start_cu_y += hevc->m_tile[i][0].height;
4180 }
4181 } else {
4182 start_cu_y = 0;
4183 for (i = 0; i < hevc->num_tile_row; i++) {
4184 start_cu_x = 0;
4185 for (j = 0; j < hevc->num_tile_col; j++) {
4186 if (j == (hevc->num_tile_col - 1)) {
4187 hevc->m_tile[i][j].width =
4188 pic_width_cu -
4189 start_cu_x;
4190 } else {
4191 hevc->m_tile[i][j].width =
4192 params->p.tile_width[j];
4193 }
4194 if (i == (hevc->num_tile_row - 1)) {
4195 hevc->m_tile[i][j].height =
4196 pic_height_cu -
4197 start_cu_y;
4198 } else {
4199 hevc->m_tile[i][j].height =
4200 params->
4201 p.tile_height[i];
4202 }
4203 hevc->m_tile[i][j].start_cu_x
4204 = start_cu_x;
4205 hevc->m_tile[i][j].start_cu_y
4206 = start_cu_y;
4207 hevc->m_tile[i][j].sao_vb_start_addr =
4208 hevc->work_space_buf->sao_vb.
4209 buf_start + j * sao_vb_size;
4210 hevc->m_tile[i][j].sao_abv_start_addr =
4211 hevc->work_space_buf->sao_abv.
4212 buf_start + i * sao_abv_size;
4213 if (get_dbg_flag(hevc) &
4214 H265_DEBUG_BUFMGR) {
4215 hevc_print_cont(hevc, 0,
4216 "{y=%d, x=%d w %d h %d ",
4217 i, j, hevc->m_tile[i][j].width,
4218 hevc->m_tile[i][j].height);
4219 hevc_print_cont(hevc, 0,
4220 "start_x %d start_y %d ",
4221 hevc->m_tile[i][j].start_cu_x,
4222 hevc->m_tile[i][j].start_cu_y);
4223 hevc_print_cont(hevc, 0,
4224 "sao_vb_start 0x%x ",
4225 hevc->m_tile[i][j].
4226 sao_vb_start_addr);
4227 hevc_print_cont(hevc, 0,
4228 "sao_abv_start 0x%x}\n",
4229 hevc->m_tile[i][j].
4230 sao_abv_start_addr);
4231
4232 }
4233 start_cu_x += hevc->m_tile[i][j].width;
4234 }
4235 start_cu_y += hevc->m_tile[i][0].height;
4236 }
4237 }
4238 } else {
4239 hevc->num_tile_col = 1;
4240 hevc->num_tile_row = 1;
4241 hevc->m_tile[0][0].width = pic_width_cu;
4242 hevc->m_tile[0][0].height = pic_height_cu;
4243 hevc->m_tile[0][0].start_cu_x = 0;
4244 hevc->m_tile[0][0].start_cu_y = 0;
4245 hevc->m_tile[0][0].sao_vb_start_addr =
4246 hevc->work_space_buf->sao_vb.buf_start;
4247 hevc->m_tile[0][0].sao_abv_start_addr =
4248 hevc->work_space_buf->sao_abv.buf_start;
4249 }
4250}
4251
4252static int get_tile_index(struct hevc_state_s *hevc, int cu_adr,
4253 int pic_width_lcu)
4254{
4255 int cu_x;
4256 int cu_y;
4257 int tile_x = 0;
4258 int tile_y = 0;
4259 int i;
4260
4261 if (pic_width_lcu == 0) {
4262 if (get_dbg_flag(hevc)) {
4263 hevc_print(hevc, 0,
4264 "%s Error, pic_width_lcu is 0, pic_w %d, pic_h %d\n",
4265 __func__, hevc->pic_w, hevc->pic_h);
4266 }
4267 return -1;
4268 }
4269 cu_x = cu_adr % pic_width_lcu;
4270 cu_y = cu_adr / pic_width_lcu;
4271 if (hevc->tile_enabled) {
4272 for (i = 0; i < hevc->num_tile_col; i++) {
4273 if (cu_x >= hevc->m_tile[0][i].start_cu_x)
4274 tile_x = i;
4275 else
4276 break;
4277 }
4278 for (i = 0; i < hevc->num_tile_row; i++) {
4279 if (cu_y >= hevc->m_tile[i][0].start_cu_y)
4280 tile_y = i;
4281 else
4282 break;
4283 }
4284 }
4285 return (tile_x) | (tile_y << 8);
4286}
4287
4288static void print_scratch_error(int error_num)
4289{
4290#if 0
4291 if (get_dbg_flag(hevc)) {
4292 hevc_print(hevc, 0,
4293 " ERROR : HEVC_ASSIST_SCRATCH_TEST Error : %d\n",
4294 error_num);
4295 }
4296#endif
4297}
4298
4299static void hevc_config_work_space_hw(struct hevc_state_s *hevc)
4300{
4301 struct BuffInfo_s *buf_spec = hevc->work_space_buf;
4302
4303 if (get_dbg_flag(hevc))
4304 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
4305 "%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
4306 __func__,
4307 buf_spec->ipp.buf_start,
4308 buf_spec->start_adr,
4309 buf_spec->short_term_rps.buf_start,
4310 buf_spec->vps.buf_start,
4311 buf_spec->sps.buf_start,
4312 buf_spec->pps.buf_start,
4313 buf_spec->sao_up.buf_start,
4314 buf_spec->swap_buf.buf_start,
4315 buf_spec->swap_buf2.buf_start,
4316 buf_spec->scalelut.buf_start,
4317 buf_spec->dblk_para.buf_start,
4318 buf_spec->dblk_data.buf_start,
4319 buf_spec->dblk_data2.buf_start);
4320 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start);
4321 if ((get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) == 0)
4322 WRITE_VREG(HEVC_RPM_BUFFER, (u32)hevc->rpm_phy_addr);
4323 WRITE_VREG(HEVC_SHORT_TERM_RPS, buf_spec->short_term_rps.buf_start);
4324 WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);
4325 WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);
4326 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
4327 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
4328 if (hevc->mmu_enable) {
4329 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
4330 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, hevc->frame_mmu_map_phy_addr);
4331 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
4332 "write HEVC_ASSIST_MMU_MAP_ADDR\n");
4333 } else
4334 WRITE_VREG(H265_MMU_MAP_BUFFER, hevc->frame_mmu_map_phy_addr);
4335 } /*else
4336 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
4337 buf_spec->swap_buf.buf_start);
4338 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start);*/
4339 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
4340 /* cfg_p_addr */
4341 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
4342 /* cfg_d_addr */
4343 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
4344
4345 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start);
4346
4347 WRITE_VREG(LMEM_DUMP_ADR, (u32)hevc->lmem_phy_addr);
4348}
4349
4350static void parser_cmd_write(void)
4351{
4352 u32 i;
4353 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
4354 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
4355 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
4356 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
4357 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
4358 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
4359 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
4360 0x7C00
4361 };
4362 for (i = 0; i < PARSER_CMD_NUMBER; i++)
4363 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
4364}
4365
4366static void hevc_init_decoder_hw(struct hevc_state_s *hevc,
4367 int decode_pic_begin, int decode_pic_num)
4368{
4369 unsigned int data32;
4370 int i;
4371#if 0
4372 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
4373 /* Set MCR fetch priorities*/
4374 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
4375 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
4376 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
4377 }
4378#endif
4379#if 1
4380 /* m8baby test1902 */
4381 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4382 hevc_print(hevc, 0,
4383 "%s\n", __func__);
4384 data32 = READ_VREG(HEVC_PARSER_VERSION);
4385 if (data32 != 0x00010001) {
4386 print_scratch_error(25);
4387 return;
4388 }
4389 WRITE_VREG(HEVC_PARSER_VERSION, 0x5a5a55aa);
4390 data32 = READ_VREG(HEVC_PARSER_VERSION);
4391 if (data32 != 0x5a5a55aa) {
4392 print_scratch_error(26);
4393 return;
4394 }
4395#if 0
4396 /* test Parser Reset */
4397 /* reset iqit to start mem init again */
4398 WRITE_VREG(DOS_SW_RESET3, (1 << 14) |
4399 (1 << 3) /* reset_whole parser */
4400 );
4401 WRITE_VREG(DOS_SW_RESET3, 0); /* clear reset_whole parser */
4402 data32 = READ_VREG(HEVC_PARSER_VERSION);
4403 if (data32 != 0x00010001)
4404 hevc_print(hevc, 0,
4405 "Test Parser Fatal Error\n");
4406#endif
4407 /* reset iqit to start mem init again */
4408 WRITE_VREG(DOS_SW_RESET3, (1 << 14)
4409 );
4410 CLEAR_VREG_MASK(HEVC_CABAC_CONTROL, 1);
4411 CLEAR_VREG_MASK(HEVC_PARSER_CORE_CONTROL, 1);
4412
4413#endif
4414 if (!hevc->m_ins_flag) {
4415 data32 = READ_VREG(HEVC_STREAM_CONTROL);
4416 data32 = data32 | (1 << 0); /* stream_fetch_enable */
4417 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
4418 data32 |= (0xf << 25); /*arwlen_axi_max*/
4419 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
4420 }
4421 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4422 if (data32 != 0x00000100) {
4423 print_scratch_error(29);
4424 return;
4425 }
4426 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4427 if (data32 != 0x00000300) {
4428 print_scratch_error(30);
4429 return;
4430 }
4431 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
4432 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
4433 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4434 if (data32 != 0x12345678) {
4435 print_scratch_error(31);
4436 return;
4437 }
4438 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4439 if (data32 != 0x9abcdef0) {
4440 print_scratch_error(32);
4441 return;
4442 }
4443 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
4444 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
4445
4446 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4447 data32 &= 0x03ffffff;
4448 data32 = data32 | (3 << 29) | (2 << 26) | (1 << 24)
4449 | /* stream_buffer_empty_int_amrisc_enable */
4450 (1 << 22) | /* stream_fifo_empty_int_amrisc_enable*/
4451 (1 << 7) | /* dec_done_int_cpu_enable */
4452 (1 << 4) | /* startcode_found_int_cpu_enable */
4453 (0 << 3) | /* startcode_found_int_amrisc_enable */
4454 (1 << 0) /* parser_int_enable */
4455 ;
4456 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
4457
4458 data32 = READ_VREG(HEVC_SHIFT_STATUS);
4459 data32 = data32 | (1 << 1) | /* emulation_check_on */
4460 (1 << 0) /* startcode_check_on */
4461 ;
4462 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
4463
4464 WRITE_VREG(HEVC_SHIFT_CONTROL, (3 << 6) |/* sft_valid_wr_position */
4465 (2 << 4) | /* emulate_code_length_sub_1 */
4466 (2 << 1) | /* start_code_length_sub_1 */
4467 (1 << 0) /* stream_shift_enable */
4468 );
4469
4470 WRITE_VREG(HEVC_CABAC_CONTROL, (1 << 0) /* cabac_enable */
4471 );
4472 /* hevc_parser_core_clk_en */
4473 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, (1 << 0)
4474 );
4475
4476 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
4477
4478 /* Initial IQIT_SCALELUT memory -- just to avoid X in simulation */
4479 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); /* cfg_p_addr */
4480 for (i = 0; i < 1024; i++)
4481 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
4482
4483#ifdef ENABLE_SWAP_TEST
4484 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
4485#endif
4486
4487 /*WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);*/
4488 /*WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0xffffffff);*/
4489 WRITE_VREG(HEVC_DECODE_SIZE, 0);
4490 /*WRITE_VREG(HEVC_DECODE_COUNT, 0);*/
4491 /* Send parser_cmd */
4492 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
4493
4494 parser_cmd_write();
4495
4496 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
4497 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
4498 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
4499
4500 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4501 /* (1 << 8) | // sao_sw_pred_enable */
4502 (1 << 5) | /* parser_sao_if_en */
4503 (1 << 2) | /* parser_mpred_if_en */
4504 (1 << 0) /* parser_scaler_if_en */
4505 );
4506
4507 /* Changed to Start MPRED in microcode */
4508 /*
4509 * hevc_print(hevc, 0, "[test.c] Start MPRED\n");
4510 * WRITE_VREG(HEVC_MPRED_INT_STATUS,
4511 * (1<<31)
4512 * );
4513 */
4514
4515 WRITE_VREG(HEVCD_IPP_TOP_CNTL, (0 << 1) | /* enable ipp */
4516 (1 << 0) /* software reset ipp and mpp */
4517 );
4518 WRITE_VREG(HEVCD_IPP_TOP_CNTL, (1 << 1) | /* enable ipp */
4519 (0 << 0) /* software reset ipp and mpp */
4520 );
4521
4522 if (get_double_write_mode(hevc) & 0x10)
4523 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
4524 0x1 << 31 /*/Enable NV21 reference read mode for MC*/
4525 );
4526
4527}
4528
4529static void decoder_hw_reset(void)
4530{
4531 int i;
4532 unsigned int data32;
4533 /* reset iqit to start mem init again */
4534 WRITE_VREG(DOS_SW_RESET3, (1 << 14)
4535 );
4536 CLEAR_VREG_MASK(HEVC_CABAC_CONTROL, 1);
4537 CLEAR_VREG_MASK(HEVC_PARSER_CORE_CONTROL, 1);
4538
4539 data32 = READ_VREG(HEVC_STREAM_CONTROL);
4540 data32 = data32 | (1 << 0) /* stream_fetch_enable */
4541 ;
4542 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
4543
4544 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4545 if (data32 != 0x00000100) {
4546 print_scratch_error(29);
4547 return;
4548 }
4549 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4550 if (data32 != 0x00000300) {
4551 print_scratch_error(30);
4552 return;
4553 }
4554 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
4555 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
4556 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4557 if (data32 != 0x12345678) {
4558 print_scratch_error(31);
4559 return;
4560 }
4561 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4562 if (data32 != 0x9abcdef0) {
4563 print_scratch_error(32);
4564 return;
4565 }
4566 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
4567 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
4568
4569 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4570 data32 &= 0x03ffffff;
4571 data32 = data32 | (3 << 29) | (2 << 26) | (1 << 24)
4572 | /* stream_buffer_empty_int_amrisc_enable */
4573 (1 << 22) | /*stream_fifo_empty_int_amrisc_enable */
4574 (1 << 7) | /* dec_done_int_cpu_enable */
4575 (1 << 4) | /* startcode_found_int_cpu_enable */
4576 (0 << 3) | /* startcode_found_int_amrisc_enable */
4577 (1 << 0) /* parser_int_enable */
4578 ;
4579 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
4580
4581 data32 = READ_VREG(HEVC_SHIFT_STATUS);
4582 data32 = data32 | (1 << 1) | /* emulation_check_on */
4583 (1 << 0) /* startcode_check_on */
4584 ;
4585 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
4586
4587 WRITE_VREG(HEVC_SHIFT_CONTROL, (3 << 6) |/* sft_valid_wr_position */
4588 (2 << 4) | /* emulate_code_length_sub_1 */
4589 (2 << 1) | /* start_code_length_sub_1 */
4590 (1 << 0) /* stream_shift_enable */
4591 );
4592
4593 WRITE_VREG(HEVC_CABAC_CONTROL, (1 << 0) /* cabac_enable */
4594 );
4595 /* hevc_parser_core_clk_en */
4596 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, (1 << 0)
4597 );
4598
4599 /* Initial IQIT_SCALELUT memory -- just to avoid X in simulation */
4600 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); /* cfg_p_addr */
4601 for (i = 0; i < 1024; i++)
4602 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
4603
4604 /* Send parser_cmd */
4605 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
4606
4607 parser_cmd_write();
4608
4609 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
4610 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
4611 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
4612
4613 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4614 /* (1 << 8) | // sao_sw_pred_enable */
4615 (1 << 5) | /* parser_sao_if_en */
4616 (1 << 2) | /* parser_mpred_if_en */
4617 (1 << 0) /* parser_scaler_if_en */
4618 );
4619
4620 WRITE_VREG(HEVCD_IPP_TOP_CNTL, (0 << 1) | /* enable ipp */
4621 (1 << 0) /* software reset ipp and mpp */
4622 );
4623 WRITE_VREG(HEVCD_IPP_TOP_CNTL, (1 << 1) | /* enable ipp */
4624 (0 << 0) /* software reset ipp and mpp */
4625 );
4626}
4627
4628#ifdef CONFIG_HEVC_CLK_FORCED_ON
4629static void config_hevc_clk_forced_on(void)
4630{
4631 unsigned int rdata32;
4632 /* IQIT */
4633 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
4634 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
4635
4636 /* DBLK */
4637 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
4638 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
4639
4640 /* SAO */
4641 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
4642 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
4643
4644 /* MPRED */
4645 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
4646 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
4647
4648 /* PARSER */
4649 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
4650 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
4651 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
4652 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
4653 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
4654 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
4655 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
4656 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
4657 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4658 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
4659 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
4660 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4661 rdata32 | (0x3 << 5) | (0x3 << 2) | (0x3 << 0));
4662
4663 /* IPP */
4664 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
4665 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
4666
4667 /* MCRCC */
4668 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
4669 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
4670}
4671#endif
4672
4673#ifdef MCRCC_ENABLE
4674static void config_mcrcc_axi_hw(struct hevc_state_s *hevc, int slice_type)
4675{
4676 unsigned int rdata32;
4677 unsigned int rdata32_2;
4678 int l0_cnt = 0;
4679 int l1_cnt = 0x7fff;
4680
4681 if (get_double_write_mode(hevc) & 0x10) {
4682 l0_cnt = hevc->cur_pic->RefNum_L0;
4683 l1_cnt = hevc->cur_pic->RefNum_L1;
4684 }
4685
4686 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
4687
4688 if (slice_type == 2) { /* I-PIC */
4689 /* remove reset -- disables clock */
4690 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
4691 return;
4692 }
4693
4694 if (slice_type == 0) { /* B-PIC */
4695 /* Programme canvas0 */
4696 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4697 (0 << 8) | (0 << 1) | 0);
4698 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4699 rdata32 = rdata32 & 0xffff;
4700 rdata32 = rdata32 | (rdata32 << 16);
4701 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
4702
4703 /* Programme canvas1 */
4704 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4705 (16 << 8) | (1 << 1) | 0);
4706 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4707 rdata32_2 = rdata32_2 & 0xffff;
4708 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
4709 if (rdata32 == rdata32_2 && l1_cnt > 1) {
4710 rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4711 rdata32_2 = rdata32_2 & 0xffff;
4712 rdata32_2 = rdata32_2 | (rdata32_2 << 16);
4713 }
4714 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
4715 } else { /* P-PIC */
4716 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4717 (0 << 8) | (1 << 1) | 0);
4718 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4719 rdata32 = rdata32 & 0xffff;
4720 rdata32 = rdata32 | (rdata32 << 16);
4721 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
4722
4723 if (l0_cnt == 1) {
4724 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
4725 } else {
4726 /* Programme canvas1 */
4727 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4728 rdata32 = rdata32 & 0xffff;
4729 rdata32 = rdata32 | (rdata32 << 16);
4730 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
4731 }
4732 }
4733 /* enable mcrcc progressive-mode */
4734 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
4735}
4736#endif
4737
4738static void config_title_hw(struct hevc_state_s *hevc, int sao_vb_size,
4739 int sao_mem_unit)
4740{
4741 WRITE_VREG(HEVC_sao_mem_unit, sao_mem_unit);
4742 WRITE_VREG(HEVC_SAO_ABV, hevc->work_space_buf->sao_abv.buf_start);
4743 WRITE_VREG(HEVC_sao_vb_size, sao_vb_size);
4744 WRITE_VREG(HEVC_SAO_VB, hevc->work_space_buf->sao_vb.buf_start);
4745}
4746
4747static u32 init_aux_size;
4748static int aux_data_is_avaible(struct hevc_state_s *hevc)
4749{
4750 u32 reg_val;
4751
4752 reg_val = READ_VREG(HEVC_AUX_DATA_SIZE);
4753 if (reg_val != 0 && reg_val != init_aux_size)
4754 return 1;
4755 else
4756 return 0;
4757}
4758
4759static void config_aux_buf(struct hevc_state_s *hevc)
4760{
4761 WRITE_VREG(HEVC_AUX_ADR, hevc->aux_phy_addr);
4762 init_aux_size = ((hevc->prefix_aux_size >> 4) << 16) |
4763 (hevc->suffix_aux_size >> 4);
4764 WRITE_VREG(HEVC_AUX_DATA_SIZE, init_aux_size);
4765}
4766
4767static void config_mpred_hw(struct hevc_state_s *hevc)
4768{
4769 int i;
4770 unsigned int data32;
4771 struct PIC_s *cur_pic = hevc->cur_pic;
4772 struct PIC_s *col_pic = hevc->col_pic;
4773 int AMVP_MAX_NUM_CANDS_MEM = 3;
4774 int AMVP_MAX_NUM_CANDS = 2;
4775 int NUM_CHROMA_MODE = 5;
4776 int DM_CHROMA_IDX = 36;
4777 int above_ptr_ctrl = 0;
4778 int buffer_linear = 1;
4779 int cu_size_log2 = 3;
4780
4781 int mpred_mv_rd_start_addr;
4782 int mpred_curr_lcu_x;
4783 int mpred_curr_lcu_y;
4784 int mpred_above_buf_start;
4785 int mpred_mv_rd_ptr;
4786 int mpred_mv_rd_ptr_p1;
4787 int mpred_mv_rd_end_addr;
4788 int MV_MEM_UNIT;
4789 int mpred_mv_wr_ptr;
4790 int *ref_poc_L0, *ref_poc_L1;
4791
4792 int above_en;
4793 int mv_wr_en;
4794 int mv_rd_en;
4795 int col_isIntra;
4796
4797 if (hevc->slice_type != 2) {
4798 above_en = 1;
4799 mv_wr_en = 1;
4800 mv_rd_en = 1;
4801 col_isIntra = 0;
4802 } else {
4803 above_en = 1;
4804 mv_wr_en = 1;
4805 mv_rd_en = 0;
4806 col_isIntra = 0;
4807 }
4808
4809 mpred_mv_rd_start_addr = col_pic->mpred_mv_wr_start_addr;
4810 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
4811 mpred_curr_lcu_x = data32 & 0xffff;
4812 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
4813
4814 MV_MEM_UNIT =
4815 hevc->lcu_size_log2 == 6 ? 0x200 : hevc->lcu_size_log2 ==
4816 5 ? 0x80 : 0x20;
4817 mpred_mv_rd_ptr =
4818 mpred_mv_rd_start_addr + (hevc->slice_addr * MV_MEM_UNIT);
4819
4820 mpred_mv_rd_ptr_p1 = mpred_mv_rd_ptr + MV_MEM_UNIT;
4821 mpred_mv_rd_end_addr =
4822 mpred_mv_rd_start_addr +
4823 ((hevc->lcu_x_num * hevc->lcu_y_num) * MV_MEM_UNIT);
4824
4825 mpred_above_buf_start = hevc->work_space_buf->mpred_above.buf_start;
4826
4827 mpred_mv_wr_ptr =
4828 cur_pic->mpred_mv_wr_start_addr +
4829 (hevc->slice_addr * MV_MEM_UNIT);
4830
4831 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4832 hevc_print(hevc, 0,
4833 "cur pic index %d col pic index %d\n", cur_pic->index,
4834 col_pic->index);
4835 }
4836
4837 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
4838 cur_pic->mpred_mv_wr_start_addr);
4839 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, mpred_mv_rd_start_addr);
4840
4841 data32 = ((hevc->lcu_x_num - hevc->tile_width_lcu) * MV_MEM_UNIT);
4842 WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP, data32);
4843 WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP, data32);
4844
4845 data32 = READ_VREG(HEVC_MPRED_CTRL0);
4846 data32 = (hevc->slice_type |
4847 hevc->new_pic << 2 |
4848 hevc->new_tile << 3 |
4849 hevc->isNextSliceSegment << 4 |
4850 hevc->TMVPFlag << 5 |
4851 hevc->LDCFlag << 6 |
4852 hevc->ColFromL0Flag << 7 |
4853 above_ptr_ctrl << 8 |
4854 above_en << 9 |
4855 mv_wr_en << 10 |
4856 mv_rd_en << 11 |
4857 col_isIntra << 12 |
4858 buffer_linear << 13 |
4859 hevc->LongTerm_Curr << 14 |
4860 hevc->LongTerm_Col << 15 |
4861 hevc->lcu_size_log2 << 16 |
4862 cu_size_log2 << 20 | hevc->plevel << 24);
4863 WRITE_VREG(HEVC_MPRED_CTRL0, data32);
4864
4865 data32 = READ_VREG(HEVC_MPRED_CTRL1);
4866 data32 = (
4867#if 0
4868 /* no set in m8baby test1902 */
4869 /* Don't override clk_forced_on , */
4870 (data32 & (0x1 << 24)) |
4871#endif
4872 hevc->MaxNumMergeCand |
4873 AMVP_MAX_NUM_CANDS << 4 |
4874 AMVP_MAX_NUM_CANDS_MEM << 8 |
4875 NUM_CHROMA_MODE << 12 | DM_CHROMA_IDX << 16);
4876 WRITE_VREG(HEVC_MPRED_CTRL1, data32);
4877
4878 data32 = (hevc->pic_w | hevc->pic_h << 16);
4879 WRITE_VREG(HEVC_MPRED_PIC_SIZE, data32);
4880
4881 data32 = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
4882 WRITE_VREG(HEVC_MPRED_PIC_SIZE_LCU, data32);
4883
4884 data32 = (hevc->tile_start_lcu_x | hevc->tile_start_lcu_y << 16);
4885 WRITE_VREG(HEVC_MPRED_TILE_START, data32);
4886
4887 data32 = (hevc->tile_width_lcu | hevc->tile_height_lcu << 16);
4888 WRITE_VREG(HEVC_MPRED_TILE_SIZE_LCU, data32);
4889
4890 data32 = (hevc->RefNum_L0 | hevc->RefNum_L1 << 8 | 0
4891 /* col_RefNum_L0<<16| */
4892 /* col_RefNum_L1<<24 */
4893 );
4894 WRITE_VREG(HEVC_MPRED_REF_NUM, data32);
4895
4896 data32 = (hevc->LongTerm_Ref);
4897 WRITE_VREG(HEVC_MPRED_LT_REF, data32);
4898
4899 data32 = 0;
4900 for (i = 0; i < hevc->RefNum_L0; i++)
4901 data32 = data32 | (1 << i);
4902 WRITE_VREG(HEVC_MPRED_REF_EN_L0, data32);
4903
4904 data32 = 0;
4905 for (i = 0; i < hevc->RefNum_L1; i++)
4906 data32 = data32 | (1 << i);
4907 WRITE_VREG(HEVC_MPRED_REF_EN_L1, data32);
4908
4909 WRITE_VREG(HEVC_MPRED_CUR_POC, hevc->curr_POC);
4910 WRITE_VREG(HEVC_MPRED_COL_POC, hevc->Col_POC);
4911
4912 /* below MPRED Ref_POC_xx_Lx registers must follow Ref_POC_xx_L0 ->
4913 * Ref_POC_xx_L1 in pair write order!!!
4914 */
4915 ref_poc_L0 = &(cur_pic->m_aiRefPOCList0[cur_pic->slice_idx][0]);
4916 ref_poc_L1 = &(cur_pic->m_aiRefPOCList1[cur_pic->slice_idx][0]);
4917
4918 WRITE_VREG(HEVC_MPRED_L0_REF00_POC, ref_poc_L0[0]);
4919 WRITE_VREG(HEVC_MPRED_L1_REF00_POC, ref_poc_L1[0]);
4920
4921 WRITE_VREG(HEVC_MPRED_L0_REF01_POC, ref_poc_L0[1]);
4922 WRITE_VREG(HEVC_MPRED_L1_REF01_POC, ref_poc_L1[1]);
4923
4924 WRITE_VREG(HEVC_MPRED_L0_REF02_POC, ref_poc_L0[2]);
4925 WRITE_VREG(HEVC_MPRED_L1_REF02_POC, ref_poc_L1[2]);
4926
4927 WRITE_VREG(HEVC_MPRED_L0_REF03_POC, ref_poc_L0[3]);
4928 WRITE_VREG(HEVC_MPRED_L1_REF03_POC, ref_poc_L1[3]);
4929
4930 WRITE_VREG(HEVC_MPRED_L0_REF04_POC, ref_poc_L0[4]);
4931 WRITE_VREG(HEVC_MPRED_L1_REF04_POC, ref_poc_L1[4]);
4932
4933 WRITE_VREG(HEVC_MPRED_L0_REF05_POC, ref_poc_L0[5]);
4934 WRITE_VREG(HEVC_MPRED_L1_REF05_POC, ref_poc_L1[5]);
4935
4936 WRITE_VREG(HEVC_MPRED_L0_REF06_POC, ref_poc_L0[6]);
4937 WRITE_VREG(HEVC_MPRED_L1_REF06_POC, ref_poc_L1[6]);
4938
4939 WRITE_VREG(HEVC_MPRED_L0_REF07_POC, ref_poc_L0[7]);
4940 WRITE_VREG(HEVC_MPRED_L1_REF07_POC, ref_poc_L1[7]);
4941
4942 WRITE_VREG(HEVC_MPRED_L0_REF08_POC, ref_poc_L0[8]);
4943 WRITE_VREG(HEVC_MPRED_L1_REF08_POC, ref_poc_L1[8]);
4944
4945 WRITE_VREG(HEVC_MPRED_L0_REF09_POC, ref_poc_L0[9]);
4946 WRITE_VREG(HEVC_MPRED_L1_REF09_POC, ref_poc_L1[9]);
4947
4948 WRITE_VREG(HEVC_MPRED_L0_REF10_POC, ref_poc_L0[10]);
4949 WRITE_VREG(HEVC_MPRED_L1_REF10_POC, ref_poc_L1[10]);
4950
4951 WRITE_VREG(HEVC_MPRED_L0_REF11_POC, ref_poc_L0[11]);
4952 WRITE_VREG(HEVC_MPRED_L1_REF11_POC, ref_poc_L1[11]);
4953
4954 WRITE_VREG(HEVC_MPRED_L0_REF12_POC, ref_poc_L0[12]);
4955 WRITE_VREG(HEVC_MPRED_L1_REF12_POC, ref_poc_L1[12]);
4956
4957 WRITE_VREG(HEVC_MPRED_L0_REF13_POC, ref_poc_L0[13]);
4958 WRITE_VREG(HEVC_MPRED_L1_REF13_POC, ref_poc_L1[13]);
4959
4960 WRITE_VREG(HEVC_MPRED_L0_REF14_POC, ref_poc_L0[14]);
4961 WRITE_VREG(HEVC_MPRED_L1_REF14_POC, ref_poc_L1[14]);
4962
4963 WRITE_VREG(HEVC_MPRED_L0_REF15_POC, ref_poc_L0[15]);
4964 WRITE_VREG(HEVC_MPRED_L1_REF15_POC, ref_poc_L1[15]);
4965
4966 if (hevc->new_pic) {
4967 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, mpred_above_buf_start);
4968 WRITE_VREG(HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr);
4969 /* WRITE_VREG(HEVC_MPRED_MV_RPTR,mpred_mv_rd_ptr); */
4970 WRITE_VREG(HEVC_MPRED_MV_RPTR, mpred_mv_rd_start_addr);
4971 } else if (!hevc->isNextSliceSegment) {
4972 /* WRITE_VREG(HEVC_MPRED_MV_RPTR,mpred_mv_rd_ptr_p1); */
4973 WRITE_VREG(HEVC_MPRED_MV_RPTR, mpred_mv_rd_ptr);
4974 }
4975
4976 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
4977}
4978
4979static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
4980{
4981 unsigned int data32, data32_2;
4982 int misc_flag0 = hevc->misc_flag0;
4983 int slice_deblocking_filter_disabled_flag = 0;
4984
4985 int mc_buffer_size_u_v =
4986 hevc->lcu_total * hevc->lcu_size * hevc->lcu_size / 2;
4987 int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4988 struct PIC_s *cur_pic = hevc->cur_pic;
4989 struct aml_vcodec_ctx * v4l2_ctx = hevc->v4l2_ctx;
4990
4991 data32 = READ_VREG(HEVC_SAO_CTRL0);
4992 data32 &= (~0xf);
4993 data32 |= hevc->lcu_size_log2;
4994 WRITE_VREG(HEVC_SAO_CTRL0, data32);
4995
4996 data32 = (hevc->pic_w | hevc->pic_h << 16);
4997 WRITE_VREG(HEVC_SAO_PIC_SIZE, data32);
4998
4999 data32 = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
5000 WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
5001
5002 if (hevc->new_pic)
5003 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5004#ifdef LOSLESS_COMPRESS_MODE
5005/*SUPPORT_10BIT*/
5006 if ((get_double_write_mode(hevc) & 0x10) == 0) {
5007 data32 = READ_VREG(HEVC_SAO_CTRL5);
5008 data32 &= (~(0xff << 16));
5009
5010 if (get_double_write_mode(hevc) == 2 ||
5011 get_double_write_mode(hevc) == 3)
5012 data32 |= (0xff<<16);
5013 else if (get_double_write_mode(hevc) == 4)
5014 data32 |= (0x33<<16);
5015
5016 if (hevc->mem_saving_mode == 1)
5017 data32 |= (1 << 9);
5018 else
5019 data32 &= ~(1 << 9);
5020 if (workaround_enable & 1)
5021 data32 |= (1 << 7);
5022 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5023 }
5024 data32 = cur_pic->mc_y_adr;
5025 if (get_double_write_mode(hevc))
5026 WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr);
5027
5028 if ((get_double_write_mode(hevc) & 0x10) == 0)
5029 WRITE_VREG(HEVC_CM_BODY_START_ADDR, data32);
5030
5031 if (hevc->mmu_enable)
5032 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr);
5033#else
5034 data32 = cur_pic->mc_y_adr;
5035 WRITE_VREG(HEVC_SAO_Y_START_ADDR, data32);
5036#endif
5037 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5038 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5039
5040#ifdef LOSLESS_COMPRESS_MODE
5041/*SUPPORT_10BIT*/
5042 if (get_double_write_mode(hevc))
5043 WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr);
5044#else
5045 data32 = cur_pic->mc_u_v_adr;
5046 WRITE_VREG(HEVC_SAO_C_START_ADDR, data32);
5047#endif
5048 data32 = (mc_buffer_size_u_v_h << 16);
5049 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5050
5051#ifdef LOSLESS_COMPRESS_MODE
5052/*SUPPORT_10BIT*/
5053 if (get_double_write_mode(hevc)) {
5054 WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr);
5055 WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr);
5056 }
5057#else
5058 /* multi tile to do... */
5059 data32 = cur_pic->mc_y_adr;
5060 WRITE_VREG(HEVC_SAO_Y_WPTR, data32);
5061
5062 data32 = cur_pic->mc_u_v_adr;
5063 WRITE_VREG(HEVC_SAO_C_WPTR, data32);
5064#endif
5065 /* DBLK CONFIG HERE */
5066 if (hevc->new_pic) {
5067 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5068 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
5069 data32 = (0xff << 8) | (0x0 << 0);
5070 else
5071 data32 = (0x57 << 8) | /* 1st/2nd write both enable*/
5072 (0x0 << 0); /* h265 video format*/
5073
5074 if (hevc->pic_w >= 1280)
5075 data32 |= (0x1 << 4); /*dblk pipeline mode=1 for performance*/
5076 data32 &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5077 if (get_double_write_mode(hevc) == 0)
5078 data32 |= (0x1 << 8); /*enable first write*/
5079 else if (get_double_write_mode(hevc) == 0x10)
5080 data32 |= (0x1 << 9); /*double write only*/
5081 else
5082 data32 |= ((0x1 << 8) |(0x1 << 9));
5083
5084 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5085 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5086 "[DBLK DEBUG] HEVC1 CFGB : 0x%x\n", data32);
5087 }
5088 data32 = (hevc->pic_w | hevc->pic_h << 16);
5089 WRITE_VREG(HEVC_DBLK_CFG2, data32);
5090
5091 if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1) {
5092 data32 =
5093 ((misc_flag0 >>
5094 PCM_LOOP_FILTER_DISABLED_FLAG_BIT) &
5095 0x1) << 3;
5096 } else
5097 data32 = 0;
5098 data32 |=
5099 (((params->p.pps_cb_qp_offset & 0x1f) << 4) |
5100 ((params->p.pps_cr_qp_offset
5101 & 0x1f) <<
5102 9));
5103 data32 |=
5104 (hevc->lcu_size ==
5105 64) ? 0 : ((hevc->lcu_size == 32) ? 1 : 2);
5106
5107 WRITE_VREG(HEVC_DBLK_CFG1, data32);
5108
5109 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5110 /*if (debug & 0x80) {*/
5111 data32 = 1 << 28; /* Debug only: sts1 chooses dblk_main*/
5112 WRITE_VREG(HEVC_DBLK_STS1 + 4, data32); /* 0x3510 */
5113 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5114 "[DBLK DEBUG] HEVC1 STS1 : 0x%x\n",
5115 data32);
5116 /*}*/
5117 }
5118 }
5119#if 0
5120 data32 = READ_VREG(HEVC_SAO_CTRL1);
5121 data32 &= (~0x3000);
5122 data32 |= (mem_map_mode <<
5123 12);
5124
5125/* [13:12] axi_aformat,
5126 * 0-Linear, 1-32x32, 2-64x32
5127 */
5128 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5129
5130 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5131 data32 &= (~0x30);
5132 data32 |= (mem_map_mode <<
5133 4);
5134
5135/* [5:4] -- address_format
5136 * 00:linear 01:32x32 10:64x32
5137 */
5138 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5139#else
5140 /* m8baby test1902 */
5141 data32 = READ_VREG(HEVC_SAO_CTRL1);
5142 data32 &= (~0x3000);
5143 data32 |= (mem_map_mode <<
5144 12);
5145
5146/* [13:12] axi_aformat, 0-Linear,
5147 * 1-32x32, 2-64x32
5148 */
5149 data32 &= (~0xff0);
5150 /* data32 |= 0x670; // Big-Endian per 64-bit */
5151 data32 |= endian; /* Big-Endian per 64-bit */
5152 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5153 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5154 if (get_double_write_mode(hevc) == 0)
5155 data32 |= 0x2; /*disable double write*/
5156 else if (get_double_write_mode(hevc) & 0x10)
5157 data32 |= 0x1; /*disable cm*/
5158 } else {
5159 unsigned int data;
5160 data = (0x57 << 8) | /* 1st/2nd write both enable*/
5161 (0x0 << 0); /* h265 video format*/
5162 if (hevc->pic_w >= 1280)
5163 data |= (0x1 << 4); /*dblk pipeline mode=1 for performance*/
5164 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5165 if (get_double_write_mode(hevc) == 0)
5166 data |= (0x1 << 8); /*enable first write*/
5167 else if (get_double_write_mode(hevc) & 0x10)
5168 data |= (0x1 << 9); /*double write only*/
5169 else
5170 data |= ((0x1 << 8) |(0x1 << 9));
5171
5172 WRITE_VREG(HEVC_DBLK_CFGB, data);
5173 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5174 "[DBLK DEBUG] HEVC1 CFGB : 0x%x\n", data);
5175 }
5176
5177 /* swap uv */
5178 if (hevc->is_used_v4l) {
5179 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5180 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5181 data32 &= ~(1 << 8); /* NV21 */
5182 else
5183 data32 |= (1 << 8); /* NV12 */
5184 }
5185
5186 /*
5187 * [31:24] ar_fifo1_axi_thred
5188 * [23:16] ar_fifo0_axi_thred
5189 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5190 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5191 * [11:08] axi_lendian_C
5192 * [07:04] axi_lendian_Y
5193 * [3] reserved
5194 * [2] clk_forceon
5195 * [1] dw_disable:disable double write output
5196 * [0] cm_disable:disable compress output
5197 */
5198 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5199 if (get_double_write_mode(hevc) & 0x10) {
5200 /* [23:22] dw_v1_ctrl
5201 *[21:20] dw_v0_ctrl
5202 *[19:18] dw_h1_ctrl
5203 *[17:16] dw_h0_ctrl
5204 */
5205 data32 = READ_VREG(HEVC_SAO_CTRL5);
5206 /*set them all 0 for H265_NV21 (no down-scale)*/
5207 data32 &= ~(0xff << 16);
5208 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5209 }
5210
5211 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5212 data32 &= (~0x30);
5213 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5214 data32 |= (mem_map_mode <<
5215 4);
5216 data32 &= (~0xF);
5217 data32 |= 0xf; /* valid only when double write only */
5218 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5219
5220 /* swap uv */
5221 if (hevc->is_used_v4l) {
5222 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5223 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5224 data32 |= (1 << 12); /* NV21 */
5225 else
5226 data32 &= ~(1 << 12); /* NV12 */
5227 }
5228
5229 /*
5230 * [3:0] little_endian
5231 * [5:4] address_format 00:linear 01:32x32 10:64x32
5232 * [7:6] reserved
5233 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5234 * [11:10] reserved
5235 * [12] CbCr_byte_swap
5236 * [31:13] reserved
5237 */
5238 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5239#endif
5240 data32 = 0;
5241 data32_2 = READ_VREG(HEVC_SAO_CTRL0);
5242 data32_2 &= (~0x300);
5243 /* slice_deblocking_filter_disabled_flag = 0;
5244 * ucode has handle it , so read it from ucode directly
5245 */
5246 if (hevc->tile_enabled) {
5247 data32 |=
5248 ((misc_flag0 >>
5249 LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT) &
5250 0x1) << 0;
5251 data32_2 |=
5252 ((misc_flag0 >>
5253 LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT) &
5254 0x1) << 8;
5255 }
5256 slice_deblocking_filter_disabled_flag = (misc_flag0 >>
5257 SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
5258 0x1; /* ucode has handle it,so read it from ucode directly */
5259 if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT))
5260 && (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) {
5261 /* slice_deblocking_filter_disabled_flag =
5262 * (misc_flag0>>SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT)&0x1;
5263 * //ucode has handle it , so read it from ucode directly
5264 */
5265 data32 |= slice_deblocking_filter_disabled_flag << 2;
5266 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5267 hevc_print_cont(hevc, 0,
5268 "(1,%x)", data32);
5269 if (!slice_deblocking_filter_disabled_flag) {
5270 data32 |= (params->p.slice_beta_offset_div2 & 0xf) << 3;
5271 data32 |= (params->p.slice_tc_offset_div2 & 0xf) << 7;
5272 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5273 hevc_print_cont(hevc, 0,
5274 "(2,%x)", data32);
5275 }
5276 } else {
5277 data32 |=
5278 ((misc_flag0 >>
5279 PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
5280 0x1) << 2;
5281 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5282 hevc_print_cont(hevc, 0,
5283 "(3,%x)", data32);
5284 if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
5285 0x1) == 0) {
5286 data32 |= (params->p.pps_beta_offset_div2 & 0xf) << 3;
5287 data32 |= (params->p.pps_tc_offset_div2 & 0xf) << 7;
5288 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5289 hevc_print_cont(hevc, 0,
5290 "(4,%x)", data32);
5291 }
5292 }
5293 if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT))
5294 && ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT))
5295 || (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT))
5296 || (!slice_deblocking_filter_disabled_flag))) {
5297 data32 |=
5298 ((misc_flag0 >>
5299 SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5300 & 0x1) << 1;
5301 data32_2 |=
5302 ((misc_flag0 >>
5303 SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5304 & 0x1) << 9;
5305 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5306 hevc_print_cont(hevc, 0,
5307 "(5,%x)\n", data32);
5308 } else {
5309 data32 |=
5310 ((misc_flag0 >>
5311 PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5312 & 0x1) << 1;
5313 data32_2 |=
5314 ((misc_flag0 >>
5315 PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5316 & 0x1) << 9;
5317 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5318 hevc_print_cont(hevc, 0,
5319 "(6,%x)\n", data32);
5320 }
5321 WRITE_VREG(HEVC_DBLK_CFG9, data32);
5322 WRITE_VREG(HEVC_SAO_CTRL0, data32_2);
5323}
5324
5325#ifdef TEST_NO_BUF
5326static unsigned char test_flag = 1;
5327#endif
5328
5329static void pic_list_process(struct hevc_state_s *hevc)
5330{
5331 int work_pic_num = get_work_pic_num(hevc);
5332 int alloc_pic_count = 0;
5333 int i;
5334 struct PIC_s *pic;
5335 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5336 pic = hevc->m_PIC[i];
5337 if (pic == NULL || pic->index == -1)
5338 continue;
5339 alloc_pic_count++;
5340 if (pic->output_mark == 0 && pic->referenced == 0
5341 && pic->output_ready == 0
5342 && (pic->width != hevc->pic_w ||
5343 pic->height != hevc->pic_h)
5344 ) {
5345 set_buf_unused(hevc, pic->BUF_index);
5346 pic->BUF_index = -1;
5347 if (alloc_pic_count > work_pic_num) {
5348 pic->width = 0;
5349 pic->height = 0;
5350 pic->index = -1;
5351 } else {
5352 pic->width = hevc->pic_w;
5353 pic->height = hevc->pic_h;
5354 }
5355 }
5356 }
5357 if (alloc_pic_count < work_pic_num) {
5358 int new_count = alloc_pic_count;
5359 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5360 pic = hevc->m_PIC[i];
5361 if (pic && pic->index == -1) {
5362 pic->index = i;
5363 pic->BUF_index = -1;
5364 pic->width = hevc->pic_w;
5365 pic->height = hevc->pic_h;
5366 new_count++;
5367 if (new_count >=
5368 work_pic_num)
5369 break;
5370 }
5371 }
5372
5373 }
5374 dealloc_unused_buf(hevc);
5375 if (get_alloc_pic_count(hevc)
5376 != alloc_pic_count) {
5377 hevc_print_cont(hevc, 0,
5378 "%s: work_pic_num is %d, Change alloc_pic_count from %d to %d\n",
5379 __func__,
5380 work_pic_num,
5381 alloc_pic_count,
5382 get_alloc_pic_count(hevc));
5383 }
5384}
5385
5386static void recycle_mmu_bufs(struct hevc_state_s *hevc)
5387{
5388 int i;
5389 struct PIC_s *pic;
5390 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5391 pic = hevc->m_PIC[i];
5392 if (pic == NULL || pic->index == -1)
5393 continue;
5394
5395 if (pic->output_mark == 0 && pic->referenced == 0
5396 && pic->output_ready == 0
5397 && pic->scatter_alloc
5398 )
5399 release_pic_mmu_buf(hevc, pic);
5400 }
5401
5402}
5403
5404static struct PIC_s *get_new_pic(struct hevc_state_s *hevc,
5405 union param_u *rpm_param)
5406{
5407 struct PIC_s *new_pic = NULL;
5408 struct PIC_s *pic;
5409 int i;
5410 int ret;
5411
5412 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5413 pic = hevc->m_PIC[i];
5414 if (pic == NULL || pic->index == -1)
5415 continue;
5416
5417 if (pic->output_mark == 0 && pic->referenced == 0
5418 && pic->output_ready == 0
5419 && pic->width == hevc->pic_w
5420 && pic->height == hevc->pic_h
5421 ) {
5422 if (new_pic) {
5423 if (new_pic->POC != INVALID_POC) {
5424 if (pic->POC == INVALID_POC ||
5425 pic->POC < new_pic->POC)
5426 new_pic = pic;
5427 }
5428 } else
5429 new_pic = pic;
5430 }
5431 }
5432
5433 if (new_pic == NULL)
5434 return NULL;
5435
5436 if (new_pic->BUF_index < 0) {
5437 if (alloc_buf(hevc) < 0)
5438 return NULL;
5439 else {
5440 if (config_pic(hevc, new_pic) < 0) {
5441 dealloc_pic_buf(hevc, new_pic);
5442 return NULL;
5443 }
5444 }
5445 new_pic->width = hevc->pic_w;
5446 new_pic->height = hevc->pic_h;
5447 set_canvas(hevc, new_pic);
5448
5449 init_pic_list_hw(hevc);
5450 }
5451
5452 if (new_pic) {
5453 new_pic->double_write_mode =
5454 get_double_write_mode(hevc);
5455 if (new_pic->double_write_mode)
5456 set_canvas(hevc, new_pic);
5457
5458#ifdef TEST_NO_BUF
5459 if (test_flag) {
5460 test_flag = 0;
5461 return NULL;
5462 } else
5463 test_flag = 1;
5464#endif
5465 if (get_mv_buf(hevc, new_pic) < 0)
5466 return NULL;
5467
5468 if (hevc->mmu_enable) {
5469 ret = H265_alloc_mmu(hevc, new_pic,
5470 rpm_param->p.bit_depth,
5471 hevc->frame_mmu_map_addr);
5472 if (ret != 0) {
5473 put_mv_buf(hevc, new_pic);
5474 hevc_print(hevc, 0,
5475 "can't alloc need mmu1,idx %d ret =%d\n",
5476 new_pic->decode_idx,
5477 ret);
5478 return NULL;
5479 }
5480 }
5481 new_pic->referenced = 1;
5482 new_pic->decode_idx = hevc->decode_idx;
5483 new_pic->slice_idx = 0;
5484 new_pic->referenced = 1;
5485 new_pic->output_mark = 0;
5486 new_pic->recon_mark = 0;
5487 new_pic->error_mark = 0;
5488 /* new_pic->output_ready = 0; */
5489 new_pic->num_reorder_pic = rpm_param->p.sps_num_reorder_pics_0;
5490 new_pic->losless_comp_body_size = hevc->losless_comp_body_size;
5491 new_pic->POC = hevc->curr_POC;
5492 new_pic->pic_struct = hevc->curr_pic_struct;
5493 if (new_pic->aux_data_buf)
5494 release_aux_data(hevc, new_pic);
5495 new_pic->mem_saving_mode =
5496 hevc->mem_saving_mode;
5497 new_pic->bit_depth_luma =
5498 hevc->bit_depth_luma;
5499 new_pic->bit_depth_chroma =
5500 hevc->bit_depth_chroma;
5501 new_pic->video_signal_type =
5502 hevc->video_signal_type;
5503
5504 new_pic->conformance_window_flag =
5505 hevc->param.p.conformance_window_flag;
5506 new_pic->conf_win_left_offset =
5507 hevc->param.p.conf_win_left_offset;
5508 new_pic->conf_win_right_offset =
5509 hevc->param.p.conf_win_right_offset;
5510 new_pic->conf_win_top_offset =
5511 hevc->param.p.conf_win_top_offset;
5512 new_pic->conf_win_bottom_offset =
5513 hevc->param.p.conf_win_bottom_offset;
5514 new_pic->chroma_format_idc =
5515 hevc->param.p.chroma_format_idc;
5516
5517 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5518 "%s: index %d, buf_idx %d, decode_idx %d, POC %d\n",
5519 __func__, new_pic->index,
5520 new_pic->BUF_index, new_pic->decode_idx,
5521 new_pic->POC);
5522
5523 }
5524 if (pic_list_debug & 0x1) {
5525 dump_pic_list(hevc);
5526 pr_err("\n*******************************************\n");
5527 }
5528
5529 return new_pic;
5530}
5531
5532static int get_display_pic_num(struct hevc_state_s *hevc)
5533{
5534 int i;
5535 struct PIC_s *pic;
5536 int num = 0;
5537
5538 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5539 pic = hevc->m_PIC[i];
5540 if (pic == NULL ||
5541 pic->index == -1)
5542 continue;
5543
5544 if (pic->output_ready == 1)
5545 num++;
5546 }
5547 return num;
5548}
5549
5550static void flush_output(struct hevc_state_s *hevc, struct PIC_s *pic)
5551{
5552 struct PIC_s *pic_display;
5553
5554 if (pic) {
5555 /*PB skip control */
5556 if (pic->error_mark == 0 && hevc->PB_skip_mode == 1) {
5557 /* start decoding after first I */
5558 hevc->ignore_bufmgr_error |= 0x1;
5559 }
5560 if (hevc->ignore_bufmgr_error & 1) {
5561 if (hevc->PB_skip_count_after_decoding > 0)
5562 hevc->PB_skip_count_after_decoding--;
5563 else {
5564 /* start displaying */
5565 hevc->ignore_bufmgr_error |= 0x2;
5566 }
5567 }
5568 /**/
5569 if (pic->POC != INVALID_POC) {
5570 pic->output_mark = 1;
5571 pic->recon_mark = 1;
5572 }
5573 pic->recon_mark = 1;
5574 }
5575 do {
5576 pic_display = output_pic(hevc, 1);
5577
5578 if (pic_display) {
5579 pic_display->referenced = 0;
5580 put_mv_buf(hevc, pic_display);
5581 if ((pic_display->error_mark
5582 && ((hevc->ignore_bufmgr_error & 0x2) == 0))
5583 || (get_dbg_flag(hevc) &
5584 H265_DEBUG_DISPLAY_CUR_FRAME)
5585 || (get_dbg_flag(hevc) &
5586 H265_DEBUG_NO_DISPLAY)) {
5587 pic_display->output_ready = 0;
5588 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
5589 hevc_print(hevc, 0,
5590 "[BM] Display: POC %d, ",
5591 pic_display->POC);
5592 hevc_print_cont(hevc, 0,
5593 "decoding index %d ==> ",
5594 pic_display->decode_idx);
5595 hevc_print_cont(hevc, 0,
5596 "Debug mode or error, recycle it\n");
5597 }
5598 } else {
5599 if (hevc->i_only & 0x1
5600 && pic_display->slice_type != 2) {
5601 pic_display->output_ready = 0;
5602 } else {
5603 prepare_display_buf(hevc, pic_display);
5604 if (get_dbg_flag(hevc)
5605 & H265_DEBUG_BUFMGR) {
5606 hevc_print(hevc, 0,
5607 "[BM] flush Display: POC %d, ",
5608 pic_display->POC);
5609 hevc_print_cont(hevc, 0,
5610 "decoding index %d\n",
5611 pic_display->decode_idx);
5612 }
5613 }
5614 }
5615 }
5616 } while (pic_display);
5617 clear_referenced_flag(hevc);
5618}
5619
5620/*
5621* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
5622*/
5623static void set_aux_data(struct hevc_state_s *hevc,
5624 struct PIC_s *pic, unsigned char suffix_flag,
5625 unsigned char dv_meta_flag)
5626{
5627 int i;
5628 unsigned short *aux_adr;
5629 unsigned int size_reg_val =
5630 READ_VREG(HEVC_AUX_DATA_SIZE);
5631 unsigned int aux_count = 0;
5632 int aux_size = 0;
5633 if (pic == NULL || 0 == aux_data_is_avaible(hevc))
5634 return;
5635
5636 if (hevc->aux_data_dirty ||
5637 hevc->m_ins_flag == 0) {
5638
5639 hevc->aux_data_dirty = 0;
5640 }
5641
5642 if (suffix_flag) {
5643 aux_adr = (unsigned short *)
5644 (hevc->aux_addr +
5645 hevc->prefix_aux_size);
5646 aux_count =
5647 ((size_reg_val & 0xffff) << 4)
5648 >> 1;
5649 aux_size =
5650 hevc->suffix_aux_size;
5651 } else {
5652 aux_adr =
5653 (unsigned short *)hevc->aux_addr;
5654 aux_count =
5655 ((size_reg_val >> 16) << 4)
5656 >> 1;
5657 aux_size =
5658 hevc->prefix_aux_size;
5659 }
5660 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) {
5661 hevc_print(hevc, 0,
5662 "%s:pic 0x%p old size %d count %d,suf %d dv_flag %d\r\n",
5663 __func__, pic, pic->aux_data_size,
5664 aux_count, suffix_flag, dv_meta_flag);
5665 }
5666 if (aux_size > 0 && aux_count > 0) {
5667 int heads_size = 0;
5668 int new_size;
5669 char *new_buf;
5670
5671 for (i = 0; i < aux_count; i++) {
5672 unsigned char tag = aux_adr[i] >> 8;
5673 if (tag != 0 && tag != 0xff) {
5674 if (dv_meta_flag == 0)
5675 heads_size += 8;
5676 else if (dv_meta_flag == 1 && tag == 0x1)
5677 heads_size += 8;
5678 else if (dv_meta_flag == 2 && tag != 0x1)
5679 heads_size += 8;
5680 }
5681 }
5682 new_size = pic->aux_data_size + aux_count + heads_size;
5683 new_buf = vmalloc(new_size);
5684 if (new_buf) {
5685 unsigned char valid_tag = 0;
5686 unsigned char *h =
5687 new_buf +
5688 pic->aux_data_size;
5689 unsigned char *p = h + 8;
5690 int len = 0;
5691 int padding_len = 0;
5692 memcpy(new_buf, pic->aux_data_buf, pic->aux_data_size);
5693 if (pic->aux_data_buf)
5694 vfree(pic->aux_data_buf);
5695 pic->aux_data_buf = new_buf;
5696 for (i = 0; i < aux_count; i += 4) {
5697 int ii;
5698 unsigned char tag = aux_adr[i + 3] >> 8;
5699 if (tag != 0 && tag != 0xff) {
5700 if (dv_meta_flag == 0)
5701 valid_tag = 1;
5702 else if (dv_meta_flag == 1
5703 && tag == 0x1)
5704 valid_tag = 1;
5705 else if (dv_meta_flag == 2
5706 && tag != 0x1)
5707 valid_tag = 1;
5708 else
5709 valid_tag = 0;
5710 if (valid_tag && len > 0) {
5711 pic->aux_data_size +=
5712 (len + 8);
5713 h[0] = (len >> 24)
5714 & 0xff;
5715 h[1] = (len >> 16)
5716 & 0xff;
5717 h[2] = (len >> 8)
5718 & 0xff;
5719 h[3] = (len >> 0)
5720 & 0xff;
5721 h[6] =
5722 (padding_len >> 8)
5723 & 0xff;
5724 h[7] = (padding_len)
5725 & 0xff;
5726 h += (len + 8);
5727 p += 8;
5728 len = 0;
5729 padding_len = 0;
5730 }
5731 if (valid_tag) {
5732 h[4] = tag;
5733 h[5] = 0;
5734 h[6] = 0;
5735 h[7] = 0;
5736 }
5737 }
5738 if (valid_tag) {
5739 for (ii = 0; ii < 4; ii++) {
5740 unsigned short aa =
5741 aux_adr[i + 3
5742 - ii];
5743 *p = aa & 0xff;
5744 p++;
5745 len++;
5746 /*if ((aa >> 8) == 0xff)
5747 padding_len++;*/
5748 }
5749 }
5750 }
5751 if (len > 0) {
5752 pic->aux_data_size += (len + 8);
5753 h[0] = (len >> 24) & 0xff;
5754 h[1] = (len >> 16) & 0xff;
5755 h[2] = (len >> 8) & 0xff;
5756 h[3] = (len >> 0) & 0xff;
5757 h[6] = (padding_len >> 8) & 0xff;
5758 h[7] = (padding_len) & 0xff;
5759 }
5760 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) {
5761 hevc_print(hevc, 0,
5762 "aux: (size %d) suffix_flag %d\n",
5763 pic->aux_data_size, suffix_flag);
5764 for (i = 0; i < pic->aux_data_size; i++) {
5765 hevc_print_cont(hevc, 0,
5766 "%02x ", pic->aux_data_buf[i]);
5767 if (((i + 1) & 0xf) == 0)
5768 hevc_print_cont(hevc, 0, "\n");
5769 }
5770 hevc_print_cont(hevc, 0, "\n");
5771 }
5772
5773 } else {
5774 hevc_print(hevc, 0, "new buf alloc failed\n");
5775 if (pic->aux_data_buf)
5776 vfree(pic->aux_data_buf);
5777 pic->aux_data_buf = NULL;
5778 pic->aux_data_size = 0;
5779 }
5780 }
5781
5782}
5783
5784static void release_aux_data(struct hevc_state_s *hevc,
5785 struct PIC_s *pic)
5786{
5787 if (pic->aux_data_buf)
5788 vfree(pic->aux_data_buf);
5789 pic->aux_data_buf = NULL;
5790 pic->aux_data_size = 0;
5791}
5792
5793static inline void hevc_pre_pic(struct hevc_state_s *hevc,
5794 struct PIC_s *pic)
5795{
5796
5797 /* prev pic */
5798 /*if (hevc->curr_POC != 0) {*/
5799 int decoded_poc = hevc->iPrevPOC;
5800#ifdef MULTI_INSTANCE_SUPPORT
5801 if (hevc->m_ins_flag) {
5802 decoded_poc = hevc->decoded_poc;
5803 hevc->decoded_poc = INVALID_POC;
5804 }
5805#endif
5806 if (hevc->m_nalUnitType != NAL_UNIT_CODED_SLICE_IDR
5807 && hevc->m_nalUnitType !=
5808 NAL_UNIT_CODED_SLICE_IDR_N_LP) {
5809 struct PIC_s *pic_display;
5810
5811 pic = get_pic_by_POC(hevc, decoded_poc);
5812 if (pic && (pic->POC != INVALID_POC)) {
5813 /*PB skip control */
5814 if (pic->error_mark == 0
5815 && hevc->PB_skip_mode == 1) {
5816 /* start decoding after
5817 * first I
5818 */
5819 hevc->ignore_bufmgr_error |= 0x1;
5820 }
5821 if (hevc->ignore_bufmgr_error & 1) {
5822 if (hevc->PB_skip_count_after_decoding > 0) {
5823 hevc->PB_skip_count_after_decoding--;
5824 } else {
5825 /* start displaying */
5826 hevc->ignore_bufmgr_error |= 0x2;
5827 }
5828 }
5829 if (hevc->mmu_enable
5830 && ((hevc->double_write_mode & 0x10) == 0)) {
5831 if (!hevc->m_ins_flag) {
5832 hevc->used_4k_num =
5833 READ_VREG(HEVC_SAO_MMU_STATUS) >> 16;
5834
5835 if ((!is_skip_decoding(hevc, pic)) &&
5836 (hevc->used_4k_num >= 0) &&
5837 (hevc->cur_pic->scatter_alloc
5838 == 1)) {
5839 hevc_print(hevc,
5840 H265_DEBUG_BUFMGR_MORE,
5841 "%s pic index %d scatter_alloc %d page_start %d\n",
5842 "decoder_mmu_box_free_idx_tail",
5843 hevc->cur_pic->index,
5844 hevc->cur_pic->scatter_alloc,
5845 hevc->used_4k_num);
5846 hevc_mmu_dma_check(hw_to_vdec(hevc));
5847 decoder_mmu_box_free_idx_tail(
5848 hevc->mmu_box,
5849 hevc->cur_pic->index,
5850 hevc->used_4k_num);
5851 hevc->cur_pic->scatter_alloc
5852 = 2;
5853 }
5854 hevc->used_4k_num = -1;
5855 }
5856 }
5857
5858 pic->output_mark = 1;
5859 pic->recon_mark = 1;
5860 }
5861 do {
5862 pic_display = output_pic(hevc, 0);
5863
5864 if (pic_display) {
5865 if ((pic_display->error_mark &&
5866 ((hevc->ignore_bufmgr_error &
5867 0x2) == 0))
5868 || (get_dbg_flag(hevc) &
5869 H265_DEBUG_DISPLAY_CUR_FRAME)
5870 || (get_dbg_flag(hevc) &
5871 H265_DEBUG_NO_DISPLAY)) {
5872 pic_display->output_ready = 0;
5873 if (get_dbg_flag(hevc) &
5874 H265_DEBUG_BUFMGR) {
5875 hevc_print(hevc, 0,
5876 "[BM] Display: POC %d, ",
5877 pic_display->POC);
5878 hevc_print_cont(hevc, 0,
5879 "decoding index %d ==> ",
5880 pic_display->
5881 decode_idx);
5882 hevc_print_cont(hevc, 0,
5883 "Debug or err,recycle it\n");
5884 }
5885 } else {
5886 if (hevc->i_only & 0x1
5887 && pic_display->
5888 slice_type != 2) {
5889 pic_display->output_ready = 0;
5890 } else {
5891 prepare_display_buf
5892 (hevc,
5893 pic_display);
5894 if (get_dbg_flag(hevc) &
5895 H265_DEBUG_BUFMGR) {
5896 hevc_print(hevc, 0,
5897 "[BM] Display: POC %d, ",
5898 pic_display->POC);
5899 hevc_print_cont(hevc, 0,
5900 "decoding index %d\n",
5901 pic_display->
5902 decode_idx);
5903 }
5904 }
5905 }
5906 }
5907 } while (pic_display);
5908 } else {
5909 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
5910 hevc_print(hevc, 0,
5911 "[BM] current pic is IDR, ");
5912 hevc_print(hevc, 0,
5913 "clear referenced flag of all buffers\n");
5914 }
5915 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5916 dump_pic_list(hevc);
5917 pic = get_pic_by_POC(hevc, decoded_poc);
5918 flush_output(hevc, pic);
5919 }
5920
5921}
5922
5923static void check_pic_decoded_error_pre(struct hevc_state_s *hevc,
5924 int decoded_lcu)
5925{
5926 int current_lcu_idx = decoded_lcu;
5927 if (decoded_lcu < 0)
5928 return;
5929
5930 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
5931 hevc_print(hevc, 0,
5932 "cur lcu idx = %d, (total %d)\n",
5933 current_lcu_idx, hevc->lcu_total);
5934 }
5935 if ((error_handle_policy & 0x20) == 0 && hevc->cur_pic != NULL) {
5936 if (hevc->first_pic_after_recover) {
5937 if (current_lcu_idx !=
5938 ((hevc->lcu_x_num_pre*hevc->lcu_y_num_pre) - 1))
5939 hevc->cur_pic->error_mark = 1;
5940 } else {
5941 if (hevc->lcu_x_num_pre != 0
5942 && hevc->lcu_y_num_pre != 0
5943 && current_lcu_idx != 0
5944 && current_lcu_idx <
5945 ((hevc->lcu_x_num_pre*hevc->lcu_y_num_pre) - 1))
5946 hevc->cur_pic->error_mark = 1;
5947 }
5948 if (hevc->cur_pic->error_mark) {
5949 hevc_print(hevc, 0,
5950 "cur lcu idx = %d, (total %d), set error_mark\n",
5951 current_lcu_idx,
5952 hevc->lcu_x_num_pre*hevc->lcu_y_num_pre);
5953 if (is_log_enable(hevc))
5954 add_log(hevc,
5955 "cur lcu idx = %d, (total %d), set error_mark",
5956 current_lcu_idx,
5957 hevc->lcu_x_num_pre *
5958 hevc->lcu_y_num_pre);
5959
5960 }
5961
5962 }
5963 if (hevc->cur_pic && hevc->head_error_flag) {
5964 hevc->cur_pic->error_mark = 1;
5965 hevc_print(hevc, 0,
5966 "head has error, set error_mark\n");
5967 }
5968
5969 if ((error_handle_policy & 0x80) == 0) {
5970 if (hevc->over_decode && hevc->cur_pic) {
5971 hevc_print(hevc, 0,
5972 "over decode, set error_mark\n");
5973 hevc->cur_pic->error_mark = 1;
5974 }
5975 }
5976
5977 hevc->lcu_x_num_pre = hevc->lcu_x_num;
5978 hevc->lcu_y_num_pre = hevc->lcu_y_num;
5979}
5980
5981static void check_pic_decoded_error(struct hevc_state_s *hevc,
5982 int decoded_lcu)
5983{
5984 int current_lcu_idx = decoded_lcu;
5985 if (decoded_lcu < 0)
5986 return;
5987
5988 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
5989 hevc_print(hevc, 0,
5990 "cur lcu idx = %d, (total %d)\n",
5991 current_lcu_idx, hevc->lcu_total);
5992 }
5993 if ((error_handle_policy & 0x20) == 0 && hevc->cur_pic != NULL) {
5994 if (hevc->lcu_x_num != 0
5995 && hevc->lcu_y_num != 0
5996 && current_lcu_idx != 0
5997 && current_lcu_idx <
5998 ((hevc->lcu_x_num*hevc->lcu_y_num) - 1))
5999 hevc->cur_pic->error_mark = 1;
6000 if (hevc->cur_pic->error_mark) {
6001 hevc_print(hevc, 0,
6002 "cur lcu idx = %d, (total %d), set error_mark\n",
6003 current_lcu_idx,
6004 hevc->lcu_x_num*hevc->lcu_y_num);
6005 if (((hevc->i_only & 0x4) == 0) && hevc->cur_pic->POC && ( hevc->cur_pic->slice_type == 0)
6006 && ((hevc->cur_pic->POC + MAX_BUF_NUM) < hevc->iPrevPOC)) {
6007 hevc_print(hevc, 0,
6008 "Flush.. num_reorder_pic %d pic->POC %d hevc->iPrevPOC %d\n",
6009 hevc->sps_num_reorder_pics_0,hevc->cur_pic->POC ,hevc->iPrevPOC);
6010 flush_output(hevc, get_pic_by_POC(hevc, hevc->cur_pic->POC ));
6011 }
6012 if (is_log_enable(hevc))
6013 add_log(hevc,
6014 "cur lcu idx = %d, (total %d), set error_mark",
6015 current_lcu_idx,
6016 hevc->lcu_x_num *
6017 hevc->lcu_y_num);
6018
6019 }
6020
6021 }
6022 if (hevc->cur_pic && hevc->head_error_flag) {
6023 hevc->cur_pic->error_mark = 1;
6024 hevc_print(hevc, 0,
6025 "head has error, set error_mark\n");
6026 }
6027
6028 if ((error_handle_policy & 0x80) == 0) {
6029 if (hevc->over_decode && hevc->cur_pic) {
6030 hevc_print(hevc, 0,
6031 "over decode, set error_mark\n");
6032 hevc->cur_pic->error_mark = 1;
6033 }
6034 }
6035}
6036
6037/* only when we decoded one field or one frame,
6038we can call this function to get qos info*/
6039static void get_picture_qos_info(struct hevc_state_s *hevc)
6040{
6041 struct PIC_s *picture = hevc->cur_pic;
6042
6043/*
6044#define DEBUG_QOS
6045*/
6046
6047 if (!hevc->cur_pic)
6048 return;
6049
6050 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
6051 unsigned char a[3];
6052 unsigned char i, j, t;
6053 unsigned long data;
6054
6055 data = READ_VREG(HEVC_MV_INFO);
6056 if (picture->slice_type == I_SLICE)
6057 data = 0;
6058 a[0] = data & 0xff;
6059 a[1] = (data >> 8) & 0xff;
6060 a[2] = (data >> 16) & 0xff;
6061
6062 for (i = 0; i < 3; i++)
6063 for (j = i+1; j < 3; j++) {
6064 if (a[j] < a[i]) {
6065 t = a[j];
6066 a[j] = a[i];
6067 a[i] = t;
6068 } else if (a[j] == a[i]) {
6069 a[i]++;
6070 t = a[j];
6071 a[j] = a[i];
6072 a[i] = t;
6073 }
6074 }
6075 picture->max_mv = a[2];
6076 picture->avg_mv = a[1];
6077 picture->min_mv = a[0];
6078#ifdef DEBUG_QOS
6079 hevc_print(hevc, 0, "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
6080 data, a[0], a[1], a[2]);
6081#endif
6082
6083 data = READ_VREG(HEVC_QP_INFO);
6084 a[0] = data & 0x1f;
6085 a[1] = (data >> 8) & 0x3f;
6086 a[2] = (data >> 16) & 0x7f;
6087
6088 for (i = 0; i < 3; i++)
6089 for (j = i+1; j < 3; j++) {
6090 if (a[j] < a[i]) {
6091 t = a[j];
6092 a[j] = a[i];
6093 a[i] = t;
6094 } else if (a[j] == a[i]) {
6095 a[i]++;
6096 t = a[j];
6097 a[j] = a[i];
6098 a[i] = t;
6099 }
6100 }
6101 picture->max_qp = a[2];
6102 picture->avg_qp = a[1];
6103 picture->min_qp = a[0];
6104#ifdef DEBUG_QOS
6105 hevc_print(hevc, 0, "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
6106 data, a[0], a[1], a[2]);
6107#endif
6108
6109 data = READ_VREG(HEVC_SKIP_INFO);
6110 a[0] = data & 0x1f;
6111 a[1] = (data >> 8) & 0x3f;
6112 a[2] = (data >> 16) & 0x7f;
6113
6114 for (i = 0; i < 3; i++)
6115 for (j = i+1; j < 3; j++) {
6116 if (a[j] < a[i]) {
6117 t = a[j];
6118 a[j] = a[i];
6119 a[i] = t;
6120 } else if (a[j] == a[i]) {
6121 a[i]++;
6122 t = a[j];
6123 a[j] = a[i];
6124 a[i] = t;
6125 }
6126 }
6127 picture->max_skip = a[2];
6128 picture->avg_skip = a[1];
6129 picture->min_skip = a[0];
6130
6131#ifdef DEBUG_QOS
6132 hevc_print(hevc, 0,
6133 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
6134 data, a[0], a[1], a[2]);
6135#endif
6136 } else {
6137 uint32_t blk88_y_count;
6138 uint32_t blk88_c_count;
6139 uint32_t blk22_mv_count;
6140 uint32_t rdata32;
6141 int32_t mv_hi;
6142 int32_t mv_lo;
6143 uint32_t rdata32_l;
6144 uint32_t mvx_L0_hi;
6145 uint32_t mvy_L0_hi;
6146 uint32_t mvx_L1_hi;
6147 uint32_t mvy_L1_hi;
6148 int64_t value;
6149 uint64_t temp_value;
6150#ifdef DEBUG_QOS
6151 int pic_number = picture->POC;
6152#endif
6153
6154 picture->max_mv = 0;
6155 picture->avg_mv = 0;
6156 picture->min_mv = 0;
6157
6158 picture->max_skip = 0;
6159 picture->avg_skip = 0;
6160 picture->min_skip = 0;
6161
6162 picture->max_qp = 0;
6163 picture->avg_qp = 0;
6164 picture->min_qp = 0;
6165
6166
6167
6168#ifdef DEBUG_QOS
6169 hevc_print(hevc, 0, "slice_type:%d, poc:%d\n",
6170 picture->slice_type,
6171 picture->POC);
6172#endif
6173 /* set rd_idx to 0 */
6174 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
6175
6176 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6177 if (blk88_y_count == 0) {
6178#ifdef DEBUG_QOS
6179 hevc_print(hevc, 0,
6180 "[Picture %d Quality] NO Data yet.\n",
6181 pic_number);
6182#endif
6183 /* reset all counts */
6184 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6185 return;
6186 }
6187 /* qp_y_sum */
6188 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6189#ifdef DEBUG_QOS
6190 hevc_print(hevc, 0,
6191 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
6192 pic_number, rdata32/blk88_y_count,
6193 rdata32, blk88_y_count);
6194#endif
6195 picture->avg_qp = rdata32/blk88_y_count;
6196 /* intra_y_count */
6197 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6198#ifdef DEBUG_QOS
6199 hevc_print(hevc, 0,
6200 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
6201 pic_number, rdata32*100/blk88_y_count,
6202 '%', rdata32);
6203#endif
6204 /* skipped_y_count */
6205 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6206#ifdef DEBUG_QOS
6207 hevc_print(hevc, 0,
6208 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
6209 pic_number, rdata32*100/blk88_y_count,
6210 '%', rdata32);
6211#endif
6212 picture->avg_skip = rdata32*100/blk88_y_count;
6213 /* coeff_non_zero_y_count */
6214 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6215#ifdef DEBUG_QOS
6216 hevc_print(hevc, 0,
6217 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
6218 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
6219 '%', rdata32);
6220#endif
6221 /* blk66_c_count */
6222 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6223 if (blk88_c_count == 0) {
6224#ifdef DEBUG_QOS
6225 hevc_print(hevc, 0,
6226 "[Picture %d Quality] NO Data yet.\n",
6227 pic_number);
6228#endif
6229 /* reset all counts */
6230 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6231 return;
6232 }
6233 /* qp_c_sum */
6234 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6235#ifdef DEBUG_QOS
6236 hevc_print(hevc, 0,
6237 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
6238 pic_number, rdata32/blk88_c_count,
6239 rdata32, blk88_c_count);
6240#endif
6241 /* intra_c_count */
6242 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6243#ifdef DEBUG_QOS
6244 hevc_print(hevc, 0,
6245 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
6246 pic_number, rdata32*100/blk88_c_count,
6247 '%', rdata32);
6248#endif
6249 /* skipped_cu_c_count */
6250 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6251#ifdef DEBUG_QOS
6252 hevc_print(hevc, 0,
6253 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
6254 pic_number, rdata32*100/blk88_c_count,
6255 '%', rdata32);
6256#endif
6257 /* coeff_non_zero_c_count */
6258 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6259#ifdef DEBUG_QOS
6260 hevc_print(hevc, 0,
6261 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
6262 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
6263 '%', rdata32);
6264#endif
6265
6266 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
6267 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
6268 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6269#ifdef DEBUG_QOS
6270 hevc_print(hevc, 0, "[Picture %d Quality] Y QP min : %d\n",
6271 pic_number, (rdata32>>0)&0xff);
6272#endif
6273 picture->min_qp = (rdata32>>0)&0xff;
6274
6275#ifdef DEBUG_QOS
6276 hevc_print(hevc, 0, "[Picture %d Quality] Y QP max : %d\n",
6277 pic_number, (rdata32>>8)&0xff);
6278#endif
6279 picture->max_qp = (rdata32>>8)&0xff;
6280
6281#ifdef DEBUG_QOS
6282 hevc_print(hevc, 0, "[Picture %d Quality] C QP min : %d\n",
6283 pic_number, (rdata32>>16)&0xff);
6284 hevc_print(hevc, 0, "[Picture %d Quality] C QP max : %d\n",
6285 pic_number, (rdata32>>24)&0xff);
6286#endif
6287
6288 /* blk22_mv_count */
6289 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6290 if (blk22_mv_count == 0) {
6291#ifdef DEBUG_QOS
6292 hevc_print(hevc, 0,
6293 "[Picture %d Quality] NO MV Data yet.\n",
6294 pic_number);
6295#endif
6296 /* reset all counts */
6297 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6298 return;
6299 }
6300 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
6301 mvy_L0_count[39:32], mvx_L0_count[39:32] */
6302 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6303 /* should all be 0x00 or 0xff */
6304#ifdef DEBUG_QOS
6305 hevc_print(hevc, 0,
6306 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
6307 pic_number, rdata32);
6308#endif
6309 mvx_L0_hi = ((rdata32>>0)&0xff);
6310 mvy_L0_hi = ((rdata32>>8)&0xff);
6311 mvx_L1_hi = ((rdata32>>16)&0xff);
6312 mvy_L1_hi = ((rdata32>>24)&0xff);
6313
6314 /* mvx_L0_count[31:0] */
6315 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6316 temp_value = mvx_L0_hi;
6317 temp_value = (temp_value << 32) | rdata32_l;
6318
6319 if (mvx_L0_hi & 0x80)
6320 value = 0xFFFFFFF000000000 | temp_value;
6321 else
6322 value = temp_value;
6323 value = div_s64(value, blk22_mv_count);
6324#ifdef DEBUG_QOS
6325 hevc_print(hevc, 0,
6326 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
6327 pic_number, (int)value,
6328 value, blk22_mv_count);
6329#endif
6330 picture->avg_mv = value;
6331
6332 /* mvy_L0_count[31:0] */
6333 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6334 temp_value = mvy_L0_hi;
6335 temp_value = (temp_value << 32) | rdata32_l;
6336
6337 if (mvy_L0_hi & 0x80)
6338 value = 0xFFFFFFF000000000 | temp_value;
6339 else
6340 value = temp_value;
6341#ifdef DEBUG_QOS
6342 hevc_print(hevc, 0,
6343 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
6344 pic_number, rdata32_l/blk22_mv_count,
6345 value, blk22_mv_count);
6346#endif
6347
6348 /* mvx_L1_count[31:0] */
6349 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6350 temp_value = mvx_L1_hi;
6351 temp_value = (temp_value << 32) | rdata32_l;
6352 if (mvx_L1_hi & 0x80)
6353 value = 0xFFFFFFF000000000 | temp_value;
6354 else
6355 value = temp_value;
6356#ifdef DEBUG_QOS
6357 hevc_print(hevc, 0,
6358 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
6359 pic_number, rdata32_l/blk22_mv_count,
6360 value, blk22_mv_count);
6361#endif
6362
6363 /* mvy_L1_count[31:0] */
6364 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6365 temp_value = mvy_L1_hi;
6366 temp_value = (temp_value << 32) | rdata32_l;
6367 if (mvy_L1_hi & 0x80)
6368 value = 0xFFFFFFF000000000 | temp_value;
6369 else
6370 value = temp_value;
6371#ifdef DEBUG_QOS
6372 hevc_print(hevc, 0,
6373 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
6374 pic_number, rdata32_l/blk22_mv_count,
6375 value, blk22_mv_count);
6376#endif
6377
6378 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
6379 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6380 mv_hi = (rdata32>>16)&0xffff;
6381 if (mv_hi & 0x8000)
6382 mv_hi = 0x8000 - mv_hi;
6383#ifdef DEBUG_QOS
6384 hevc_print(hevc, 0, "[Picture %d Quality] MVX_L0 MAX : %d\n",
6385 pic_number, mv_hi);
6386#endif
6387 picture->max_mv = mv_hi;
6388
6389 mv_lo = (rdata32>>0)&0xffff;
6390 if (mv_lo & 0x8000)
6391 mv_lo = 0x8000 - mv_lo;
6392#ifdef DEBUG_QOS
6393 hevc_print(hevc, 0, "[Picture %d Quality] MVX_L0 MIN : %d\n",
6394 pic_number, mv_lo);
6395#endif
6396 picture->min_mv = mv_lo;
6397
6398 /* {mvy_L0_max, mvy_L0_min} */
6399 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6400 mv_hi = (rdata32>>16)&0xffff;
6401 if (mv_hi & 0x8000)
6402 mv_hi = 0x8000 - mv_hi;
6403#ifdef DEBUG_QOS
6404 hevc_print(hevc, 0, "[Picture %d Quality] MVY_L0 MAX : %d\n",
6405 pic_number, mv_hi);
6406#endif
6407
6408 mv_lo = (rdata32>>0)&0xffff;
6409 if (mv_lo & 0x8000)
6410 mv_lo = 0x8000 - mv_lo;
6411#ifdef DEBUG_QOS
6412 hevc_print(hevc, 0, "[Picture %d Quality] MVY_L0 MIN : %d\n",
6413 pic_number, mv_lo);
6414#endif
6415
6416 /* {mvx_L1_max, mvx_L1_min} */
6417 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6418 mv_hi = (rdata32>>16)&0xffff;
6419 if (mv_hi & 0x8000)
6420 mv_hi = 0x8000 - mv_hi;
6421#ifdef DEBUG_QOS
6422 hevc_print(hevc, 0, "[Picture %d Quality] MVX_L1 MAX : %d\n",
6423 pic_number, mv_hi);
6424#endif
6425
6426 mv_lo = (rdata32>>0)&0xffff;
6427 if (mv_lo & 0x8000)
6428 mv_lo = 0x8000 - mv_lo;
6429#ifdef DEBUG_QOS
6430 hevc_print(hevc, 0, "[Picture %d Quality] MVX_L1 MIN : %d\n",
6431 pic_number, mv_lo);
6432#endif
6433
6434 /* {mvy_L1_max, mvy_L1_min} */
6435 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6436 mv_hi = (rdata32>>16)&0xffff;
6437 if (mv_hi & 0x8000)
6438 mv_hi = 0x8000 - mv_hi;
6439#ifdef DEBUG_QOS
6440 hevc_print(hevc, 0, "[Picture %d Quality] MVY_L1 MAX : %d\n",
6441 pic_number, mv_hi);
6442#endif
6443 mv_lo = (rdata32>>0)&0xffff;
6444 if (mv_lo & 0x8000)
6445 mv_lo = 0x8000 - mv_lo;
6446#ifdef DEBUG_QOS
6447 hevc_print(hevc, 0, "[Picture %d Quality] MVY_L1 MIN : %d\n",
6448 pic_number, mv_lo);
6449#endif
6450
6451 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
6452#ifdef DEBUG_QOS
6453 hevc_print(hevc, 0,
6454 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
6455 pic_number, rdata32);
6456#endif
6457 /* reset all counts */
6458 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6459 }
6460}
6461
6462static int hevc_slice_segment_header_process(struct hevc_state_s *hevc,
6463 union param_u *rpm_param,
6464 int decode_pic_begin)
6465{
6466#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6467 struct vdec_s *vdec = hw_to_vdec(hevc);
6468#endif
6469 int i;
6470 int lcu_x_num_div;
6471 int lcu_y_num_div;
6472 int Col_ref;
6473 int dbg_skip_flag = 0;
6474
6475 if (hevc->wait_buf == 0) {
6476 hevc->sps_num_reorder_pics_0 =
6477 rpm_param->p.sps_num_reorder_pics_0;
6478 hevc->m_temporalId = rpm_param->p.m_temporalId;
6479 hevc->m_nalUnitType = rpm_param->p.m_nalUnitType;
6480 hevc->interlace_flag =
6481 (rpm_param->p.profile_etc >> 2) & 0x1;
6482 hevc->curr_pic_struct =
6483 (rpm_param->p.sei_frame_field_info >> 3) & 0xf;
6484 if (parser_sei_enable & 0x4) {
6485 hevc->frame_field_info_present_flag =
6486 (rpm_param->p.sei_frame_field_info >> 8) & 0x1;
6487 }
6488
6489 if (interlace_enable == 0 || hevc->m_ins_flag)
6490 hevc->interlace_flag = 0;
6491 if (interlace_enable & 0x100)
6492 hevc->interlace_flag = interlace_enable & 0x1;
6493 if (hevc->interlace_flag == 0)
6494 hevc->curr_pic_struct = 0;
6495 /* if(hevc->m_nalUnitType == NAL_UNIT_EOS){ */
6496 /*
6497 *hevc->m_pocRandomAccess = MAX_INT;
6498 * //add to fix RAP_B_Bossen_1
6499 */
6500 /* } */
6501 hevc->misc_flag0 = rpm_param->p.misc_flag0;
6502 if (rpm_param->p.first_slice_segment_in_pic_flag == 0) {
6503 hevc->slice_segment_addr =
6504 rpm_param->p.slice_segment_address;
6505 if (!rpm_param->p.dependent_slice_segment_flag)
6506 hevc->slice_addr = hevc->slice_segment_addr;
6507 } else {
6508 hevc->slice_segment_addr = 0;
6509 hevc->slice_addr = 0;
6510 }
6511
6512 hevc->iPrevPOC = hevc->curr_POC;
6513 hevc->slice_type = (rpm_param->p.slice_type == I_SLICE) ? 2 :
6514 (rpm_param->p.slice_type == P_SLICE) ? 1 :
6515 (rpm_param->p.slice_type == B_SLICE) ? 0 : 3;
6516 /* hevc->curr_predFlag_L0=(hevc->slice_type==2) ? 0:1; */
6517 /* hevc->curr_predFlag_L1=(hevc->slice_type==0) ? 1:0; */
6518 hevc->TMVPFlag = rpm_param->p.slice_temporal_mvp_enable_flag;
6519 hevc->isNextSliceSegment =
6520 rpm_param->p.dependent_slice_segment_flag ? 1 : 0;
6521 if (hevc->pic_w != rpm_param->p.pic_width_in_luma_samples
6522 || hevc->pic_h !=
6523 rpm_param->p.pic_height_in_luma_samples) {
6524 hevc_print(hevc, 0,
6525 "Pic Width/Height Change (%d,%d)=>(%d,%d), interlace %d\n",
6526 hevc->pic_w, hevc->pic_h,
6527 rpm_param->p.pic_width_in_luma_samples,
6528 rpm_param->p.pic_height_in_luma_samples,
6529 hevc->interlace_flag);
6530
6531 hevc->pic_w = rpm_param->p.pic_width_in_luma_samples;
6532 hevc->pic_h = rpm_param->p.pic_height_in_luma_samples;
6533 hevc->frame_width = hevc->pic_w;
6534 hevc->frame_height = hevc->pic_h;
6535#ifdef LOSLESS_COMPRESS_MODE
6536 if (/*re_config_pic_flag == 0 &&*/
6537 (get_double_write_mode(hevc) & 0x10) == 0)
6538 init_decode_head_hw(hevc);
6539#endif
6540 }
6541
6542 if (is_oversize(hevc->pic_w, hevc->pic_h)) {
6543 hevc_print(hevc, 0, "over size : %u x %u.\n",
6544 hevc->pic_w, hevc->pic_h);
6545 if ((!hevc->m_ins_flag) &&
6546 ((debug &
6547 H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0))
6548 debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC |
6549 H265_DEBUG_DIS_SYS_ERROR_PROC);
6550 hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6551 return 3;
6552 }
6553 if (hevc->bit_depth_chroma > 10 ||
6554 hevc->bit_depth_luma > 10) {
6555 hevc_print(hevc, 0, "unsupport bitdepth : %u,%u\n",
6556 hevc->bit_depth_chroma,
6557 hevc->bit_depth_luma);
6558 if (!hevc->m_ins_flag)
6559 debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC |
6560 H265_DEBUG_DIS_SYS_ERROR_PROC);
6561 hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6562 return 4;
6563 }
6564
6565 /* it will cause divide 0 error */
6566 if (hevc->pic_w == 0 || hevc->pic_h == 0) {
6567 if (get_dbg_flag(hevc)) {
6568 hevc_print(hevc, 0,
6569 "Fatal Error, pic_w = %d, pic_h = %d\n",
6570 hevc->pic_w, hevc->pic_h);
6571 }
6572 return 3;
6573 }
6574 pic_list_process(hevc);
6575
6576 hevc->lcu_size =
6577 1 << (rpm_param->p.log2_min_coding_block_size_minus3 +
6578 3 + rpm_param->
6579 p.log2_diff_max_min_coding_block_size);
6580 if (hevc->lcu_size == 0) {
6581 hevc_print(hevc, 0,
6582 "Error, lcu_size = 0 (%d,%d)\n",
6583 rpm_param->p.
6584 log2_min_coding_block_size_minus3,
6585 rpm_param->p.
6586 log2_diff_max_min_coding_block_size);
6587 return 3;
6588 }
6589 hevc->lcu_size_log2 = log2i(hevc->lcu_size);
6590 lcu_x_num_div = (hevc->pic_w / hevc->lcu_size);
6591 lcu_y_num_div = (hevc->pic_h / hevc->lcu_size);
6592 hevc->lcu_x_num =
6593 ((hevc->pic_w % hevc->lcu_size) ==
6594 0) ? lcu_x_num_div : lcu_x_num_div + 1;
6595 hevc->lcu_y_num =
6596 ((hevc->pic_h % hevc->lcu_size) ==
6597 0) ? lcu_y_num_div : lcu_y_num_div + 1;
6598 hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num;
6599
6600 if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_IDR
6601 || hevc->m_nalUnitType ==
6602 NAL_UNIT_CODED_SLICE_IDR_N_LP) {
6603 hevc->curr_POC = 0;
6604 if ((hevc->m_temporalId - 1) == 0)
6605 hevc->iPrevTid0POC = hevc->curr_POC;
6606 } else {
6607 int iMaxPOClsb =
6608 1 << (rpm_param->p.
6609 log2_max_pic_order_cnt_lsb_minus4 + 4);
6610 int iPrevPOClsb;
6611 int iPrevPOCmsb;
6612 int iPOCmsb;
6613 int iPOClsb = rpm_param->p.POClsb;
6614
6615 if (iMaxPOClsb == 0) {
6616 hevc_print(hevc, 0,
6617 "error iMaxPOClsb is 0\n");
6618 return 3;
6619 }
6620
6621 iPrevPOClsb = hevc->iPrevTid0POC % iMaxPOClsb;
6622 iPrevPOCmsb = hevc->iPrevTid0POC - iPrevPOClsb;
6623
6624 if ((iPOClsb < iPrevPOClsb)
6625 && ((iPrevPOClsb - iPOClsb) >=
6626 (iMaxPOClsb / 2)))
6627 iPOCmsb = iPrevPOCmsb + iMaxPOClsb;
6628 else if ((iPOClsb > iPrevPOClsb)
6629 && ((iPOClsb - iPrevPOClsb) >
6630 (iMaxPOClsb / 2)))
6631 iPOCmsb = iPrevPOCmsb - iMaxPOClsb;
6632 else
6633 iPOCmsb = iPrevPOCmsb;
6634 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6635 hevc_print(hevc, 0,
6636 "iPrePOC%d iMaxPOClsb%d iPOCmsb%d iPOClsb%d\n",
6637 hevc->iPrevTid0POC, iMaxPOClsb, iPOCmsb,
6638 iPOClsb);
6639 }
6640 if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA
6641 || hevc->m_nalUnitType ==
6642 NAL_UNIT_CODED_SLICE_BLANT
6643 || hevc->m_nalUnitType ==
6644 NAL_UNIT_CODED_SLICE_BLA_N_LP) {
6645 /* For BLA picture types, POCmsb is set to 0. */
6646 iPOCmsb = 0;
6647 }
6648 hevc->curr_POC = (iPOCmsb + iPOClsb);
6649 if ((hevc->m_temporalId - 1) == 0)
6650 hevc->iPrevTid0POC = hevc->curr_POC;
6651 else {
6652 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6653 hevc_print(hevc, 0,
6654 "m_temporalID is %d\n",
6655 hevc->m_temporalId);
6656 }
6657 }
6658 }
6659 hevc->RefNum_L0 =
6660 (rpm_param->p.num_ref_idx_l0_active >
6661 MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : rpm_param->p.
6662 num_ref_idx_l0_active;
6663 hevc->RefNum_L1 =
6664 (rpm_param->p.num_ref_idx_l1_active >
6665 MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : rpm_param->p.
6666 num_ref_idx_l1_active;
6667
6668 /* if(curr_POC==0x10) dump_lmem(); */
6669
6670 /* skip RASL pictures after CRA/BLA pictures */
6671 if (hevc->m_pocRandomAccess == MAX_INT) {/* first picture */
6672 if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_CRA ||
6673 hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA
6674 || hevc->m_nalUnitType ==
6675 NAL_UNIT_CODED_SLICE_BLANT
6676 || hevc->m_nalUnitType ==
6677 NAL_UNIT_CODED_SLICE_BLA_N_LP)
6678 hevc->m_pocRandomAccess = hevc->curr_POC;
6679 else
6680 hevc->m_pocRandomAccess = -MAX_INT;
6681 } else if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA
6682 || hevc->m_nalUnitType ==
6683 NAL_UNIT_CODED_SLICE_BLANT
6684 || hevc->m_nalUnitType ==
6685 NAL_UNIT_CODED_SLICE_BLA_N_LP)
6686 hevc->m_pocRandomAccess = hevc->curr_POC;
6687 else if ((hevc->curr_POC < hevc->m_pocRandomAccess) &&
6688 (nal_skip_policy >= 3) &&
6689 (hevc->m_nalUnitType ==
6690 NAL_UNIT_CODED_SLICE_RASL_N ||
6691 hevc->m_nalUnitType ==
6692 NAL_UNIT_CODED_SLICE_TFD)) { /* skip */
6693 if (get_dbg_flag(hevc)) {
6694 hevc_print(hevc, 0,
6695 "RASL picture with POC %d < %d ",
6696 hevc->curr_POC, hevc->m_pocRandomAccess);
6697 hevc_print(hevc, 0,
6698 "RandomAccess point POC), skip it\n");
6699 }
6700 return 1;
6701 }
6702
6703 WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) | 0x2);
6704 hevc->skip_flag = 0;
6705 /**/
6706 /* if((iPrevPOC != curr_POC)){ */
6707 if (rpm_param->p.slice_segment_address == 0) {
6708 struct PIC_s *pic;
6709
6710 hevc->new_pic = 1;
6711#ifdef MULTI_INSTANCE_SUPPORT
6712 if (!hevc->m_ins_flag)
6713#endif
6714 check_pic_decoded_error_pre(hevc,
6715 READ_VREG(HEVC_PARSER_LCU_START)
6716 & 0xffffff);
6717 /**/ if (use_cma == 0) {
6718 if (hevc->pic_list_init_flag == 0) {
6719 init_pic_list(hevc);
6720 init_pic_list_hw(hevc);
6721 init_buf_spec(hevc);
6722 hevc->pic_list_init_flag = 3;
6723 }
6724 }
6725 if (!hevc->m_ins_flag) {
6726 if (hevc->cur_pic)
6727 get_picture_qos_info(hevc);
6728 }
6729 hevc->first_pic_after_recover = 0;
6730 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE)
6731 dump_pic_list(hevc);
6732 /* prev pic */
6733 hevc_pre_pic(hevc, pic);
6734 /*
6735 *update referenced of old pictures
6736 *(cur_pic->referenced is 1 and not updated)
6737 */
6738 apply_ref_pic_set(hevc, hevc->curr_POC,
6739 rpm_param);
6740
6741 if (hevc->mmu_enable)
6742 recycle_mmu_bufs(hevc);
6743
6744#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6745 if (vdec->master) {
6746 struct hevc_state_s *hevc_ba =
6747 (struct hevc_state_s *)
6748 vdec->master->private;
6749 if (hevc_ba->cur_pic != NULL) {
6750 hevc_ba->cur_pic->dv_enhance_exist = 1;
6751 hevc_print(hevc, H265_DEBUG_DV,
6752 "To decode el (poc %d) => set bl (poc %d) dv_enhance_exist flag\n",
6753 hevc->curr_POC, hevc_ba->cur_pic->POC);
6754 }
6755 }
6756 if (vdec->master == NULL &&
6757 vdec->slave == NULL)
6758 set_aux_data(hevc,
6759 hevc->cur_pic, 1, 0); /*suffix*/
6760 if (hevc->bypass_dvenl && !dolby_meta_with_el)
6761 set_aux_data(hevc,
6762 hevc->cur_pic, 0, 1); /*dv meta only*/
6763#else
6764 set_aux_data(hevc, hevc->cur_pic, 1, 0);
6765#endif
6766 /* new pic */
6767 hevc->cur_pic = get_new_pic(hevc, rpm_param);
6768 if (hevc->cur_pic == NULL) {
6769 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
6770 dump_pic_list(hevc);
6771 hevc->wait_buf = 1;
6772 return -1;
6773 }
6774#ifdef MULTI_INSTANCE_SUPPORT
6775 hevc->decoding_pic = hevc->cur_pic;
6776 if (!hevc->m_ins_flag)
6777 hevc->over_decode = 0;
6778#endif
6779#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6780 hevc->cur_pic->dv_enhance_exist = 0;
6781 if (vdec->slave)
6782 hevc_print(hevc, H265_DEBUG_DV,
6783 "Clear bl (poc %d) dv_enhance_exist flag\n",
6784 hevc->curr_POC);
6785 if (vdec->master == NULL &&
6786 vdec->slave == NULL)
6787 set_aux_data(hevc,
6788 hevc->cur_pic, 0, 0); /*prefix*/
6789
6790 if (hevc->bypass_dvenl && !dolby_meta_with_el)
6791 set_aux_data(hevc,
6792 hevc->cur_pic, 0, 2); /*pre sei only*/
6793#else
6794 set_aux_data(hevc, hevc->cur_pic, 0, 0);
6795#endif
6796 if (get_dbg_flag(hevc) & H265_DEBUG_DISPLAY_CUR_FRAME) {
6797 hevc->cur_pic->output_ready = 1;
6798 hevc->cur_pic->stream_offset =
6799 READ_VREG(HEVC_SHIFT_BYTE_COUNT);
6800 prepare_display_buf(hevc, hevc->cur_pic);
6801 hevc->wait_buf = 2;
6802 return -1;
6803 }
6804 } else {
6805 if (get_dbg_flag(hevc) & H265_DEBUG_HAS_AUX_IN_SLICE) {
6806#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6807 if (vdec->master == NULL &&
6808 vdec->slave == NULL) {
6809 set_aux_data(hevc, hevc->cur_pic, 1, 0);
6810 set_aux_data(hevc, hevc->cur_pic, 0, 0);
6811 }
6812#else
6813 set_aux_data(hevc, hevc->cur_pic, 1, 0);
6814 set_aux_data(hevc, hevc->cur_pic, 0, 0);
6815#endif
6816 }
6817 if (hevc->pic_list_init_flag != 3
6818 || hevc->cur_pic == NULL) {
6819 /* make it dec from the first slice segment */
6820 return 3;
6821 }
6822 hevc->cur_pic->slice_idx++;
6823 hevc->new_pic = 0;
6824 }
6825 } else {
6826 if (hevc->wait_buf == 1) {
6827 pic_list_process(hevc);
6828 hevc->cur_pic = get_new_pic(hevc, rpm_param);
6829 if (hevc->cur_pic == NULL)
6830 return -1;
6831
6832 if (!hevc->m_ins_flag)
6833 hevc->over_decode = 0;
6834
6835#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6836 hevc->cur_pic->dv_enhance_exist = 0;
6837 if (vdec->master == NULL &&
6838 vdec->slave == NULL)
6839 set_aux_data(hevc, hevc->cur_pic, 0, 0);
6840#else
6841 set_aux_data(hevc, hevc->cur_pic, 0, 0);
6842#endif
6843 hevc->wait_buf = 0;
6844 } else if (hevc->wait_buf ==
6845 2) {
6846 if (get_display_pic_num(hevc) >
6847 1)
6848 return -1;
6849 hevc->wait_buf = 0;
6850 }
6851 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE)
6852 dump_pic_list(hevc);
6853 }
6854
6855 if (hevc->new_pic) {
6856#if 1
6857 /*SUPPORT_10BIT*/
6858 int sao_mem_unit =
6859 (hevc->lcu_size == 16 ? 9 :
6860 hevc->lcu_size ==
6861 32 ? 14 : 24) << 4;
6862#else
6863 int sao_mem_unit = ((hevc->lcu_size / 8) * 2 + 4) << 4;
6864#endif
6865 int pic_height_cu =
6866 (hevc->pic_h + hevc->lcu_size - 1) / hevc->lcu_size;
6867 int pic_width_cu =
6868 (hevc->pic_w + hevc->lcu_size - 1) / hevc->lcu_size;
6869 int sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
6870
6871 /* int sao_abv_size = sao_mem_unit*pic_width_cu; */
6872 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6873 hevc_print(hevc, 0,
6874 "==>%s dec idx %d, struct %d interlace %d pic idx %d\n",
6875 __func__,
6876 hevc->decode_idx,
6877 hevc->curr_pic_struct,
6878 hevc->interlace_flag,
6879 hevc->cur_pic->index);
6880 }
6881 if (dbg_skip_decode_index != 0 &&
6882 hevc->decode_idx == dbg_skip_decode_index)
6883 dbg_skip_flag = 1;
6884
6885 hevc->decode_idx++;
6886 update_tile_info(hevc, pic_width_cu, pic_height_cu,
6887 sao_mem_unit, rpm_param);
6888
6889 config_title_hw(hevc, sao_vb_size, sao_mem_unit);
6890 }
6891
6892 if (hevc->iPrevPOC != hevc->curr_POC) {
6893 hevc->new_tile = 1;
6894 hevc->tile_x = 0;
6895 hevc->tile_y = 0;
6896 hevc->tile_y_x = 0;
6897 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6898 hevc_print(hevc, 0,
6899 "new_tile (new_pic) tile_x=%d, tile_y=%d\n",
6900 hevc->tile_x, hevc->tile_y);
6901 }
6902 } else if (hevc->tile_enabled) {
6903 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6904 hevc_print(hevc, 0,
6905 "slice_segment_address is %d\n",
6906 rpm_param->p.slice_segment_address);
6907 }
6908 hevc->tile_y_x =
6909 get_tile_index(hevc, rpm_param->p.slice_segment_address,
6910 (hevc->pic_w +
6911 hevc->lcu_size -
6912 1) / hevc->lcu_size);
6913 if ((hevc->tile_y_x != (hevc->tile_x | (hevc->tile_y << 8)))
6914 && (hevc->tile_y_x != -1)) {
6915 hevc->new_tile = 1;
6916 hevc->tile_x = hevc->tile_y_x & 0xff;
6917 hevc->tile_y = (hevc->tile_y_x >> 8) & 0xff;
6918 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6919 hevc_print(hevc, 0,
6920 "new_tile seg adr %d tile_x=%d, tile_y=%d\n",
6921 rpm_param->p.slice_segment_address,
6922 hevc->tile_x, hevc->tile_y);
6923 }
6924 } else
6925 hevc->new_tile = 0;
6926 } else
6927 hevc->new_tile = 0;
6928
6929 if ((hevc->tile_x > (MAX_TILE_COL_NUM - 1))
6930 || (hevc->tile_y > (MAX_TILE_ROW_NUM - 1)))
6931 hevc->new_tile = 0;
6932
6933 if (hevc->new_tile) {
6934 hevc->tile_start_lcu_x =
6935 hevc->m_tile[hevc->tile_y][hevc->tile_x].start_cu_x;
6936 hevc->tile_start_lcu_y =
6937 hevc->m_tile[hevc->tile_y][hevc->tile_x].start_cu_y;
6938 hevc->tile_width_lcu =
6939 hevc->m_tile[hevc->tile_y][hevc->tile_x].width;
6940 hevc->tile_height_lcu =
6941 hevc->m_tile[hevc->tile_y][hevc->tile_x].height;
6942 }
6943
6944 set_ref_pic_list(hevc, rpm_param);
6945
6946 Col_ref = rpm_param->p.collocated_ref_idx;
6947
6948 hevc->LDCFlag = 0;
6949 if (rpm_param->p.slice_type != I_SLICE) {
6950 hevc->LDCFlag = 1;
6951 for (i = 0; (i < hevc->RefNum_L0) && hevc->LDCFlag; i++) {
6952 if (hevc->cur_pic->
6953 m_aiRefPOCList0[hevc->cur_pic->slice_idx][i] >
6954 hevc->curr_POC)
6955 hevc->LDCFlag = 0;
6956 }
6957 if (rpm_param->p.slice_type == B_SLICE) {
6958 for (i = 0; (i < hevc->RefNum_L1)
6959 && hevc->LDCFlag; i++) {
6960 if (hevc->cur_pic->
6961 m_aiRefPOCList1[hevc->cur_pic->
6962 slice_idx][i] >
6963 hevc->curr_POC)
6964 hevc->LDCFlag = 0;
6965 }
6966 }
6967 }
6968
6969 hevc->ColFromL0Flag = rpm_param->p.collocated_from_l0_flag;
6970
6971 hevc->plevel =
6972 rpm_param->p.log2_parallel_merge_level;
6973 hevc->MaxNumMergeCand = 5 - rpm_param->p.five_minus_max_num_merge_cand;
6974
6975 hevc->LongTerm_Curr = 0; /* to do ... */
6976 hevc->LongTerm_Col = 0; /* to do ... */
6977
6978 hevc->list_no = 0;
6979 if (rpm_param->p.slice_type == B_SLICE)
6980 hevc->list_no = 1 - hevc->ColFromL0Flag;
6981 if (hevc->list_no == 0) {
6982 if (Col_ref < hevc->RefNum_L0) {
6983 hevc->Col_POC =
6984 hevc->cur_pic->m_aiRefPOCList0[hevc->cur_pic->
6985 slice_idx][Col_ref];
6986 } else
6987 hevc->Col_POC = INVALID_POC;
6988 } else {
6989 if (Col_ref < hevc->RefNum_L1) {
6990 hevc->Col_POC =
6991 hevc->cur_pic->m_aiRefPOCList1[hevc->cur_pic->
6992 slice_idx][Col_ref];
6993 } else
6994 hevc->Col_POC = INVALID_POC;
6995 }
6996
6997 hevc->LongTerm_Ref = 0; /* to do ... */
6998
6999 if (hevc->slice_type != 2) {
7000 /* if(hevc->i_only==1){ */
7001 /* return 0xf; */
7002 /* } */
7003
7004 if (hevc->Col_POC != INVALID_POC) {
7005 hevc->col_pic = get_ref_pic_by_POC(hevc, hevc->Col_POC);
7006 if (hevc->col_pic == NULL) {
7007 hevc->cur_pic->error_mark = 1;
7008 if (get_dbg_flag(hevc)) {
7009 hevc_print(hevc, 0,
7010 "WRONG,fail to get the pic Col_POC\n");
7011 }
7012 if (is_log_enable(hevc))
7013 add_log(hevc,
7014 "WRONG,fail to get the pic Col_POC");
7015 } else if (hevc->col_pic->error_mark) {
7016 hevc->cur_pic->error_mark = 1;
7017 if (get_dbg_flag(hevc)) {
7018 hevc_print(hevc, 0,
7019 "WRONG, Col_POC error_mark is 1\n");
7020 }
7021 if (is_log_enable(hevc))
7022 add_log(hevc,
7023 "WRONG, Col_POC error_mark is 1");
7024 } else {
7025 if ((hevc->col_pic->width
7026 != hevc->pic_w) ||
7027 (hevc->col_pic->height
7028 != hevc->pic_h)) {
7029 hevc_print(hevc, 0,
7030 "Wrong reference pic (poc %d) width/height %d/%d\n",
7031 hevc->col_pic->POC,
7032 hevc->col_pic->width,
7033 hevc->col_pic->height);
7034 hevc->cur_pic->error_mark = 1;
7035 }
7036
7037 }
7038
7039 if (hevc->cur_pic->error_mark
7040 && ((hevc->ignore_bufmgr_error & 0x1) == 0)) {
7041#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7042 /*count info*/
7043 vdec_count_info(gvs, hevc->cur_pic->error_mark,
7044 hevc->cur_pic->stream_offset);
7045#endif
7046 }
7047
7048 if (is_skip_decoding(hevc,
7049 hevc->cur_pic)) {
7050 return 2;
7051 }
7052 } else
7053 hevc->col_pic = hevc->cur_pic;
7054 } /* */
7055 if (hevc->col_pic == NULL)
7056 hevc->col_pic = hevc->cur_pic;
7057#ifdef BUFFER_MGR_ONLY
7058 return 0xf;
7059#else
7060 if ((decode_pic_begin > 0 && hevc->decode_idx <= decode_pic_begin)
7061 || (dbg_skip_flag))
7062 return 0xf;
7063#endif
7064
7065 config_mc_buffer(hevc, hevc->cur_pic);
7066
7067 if (is_skip_decoding(hevc,
7068 hevc->cur_pic)) {
7069 if (get_dbg_flag(hevc))
7070 hevc_print(hevc, 0,
7071 "Discard this picture index %d\n",
7072 hevc->cur_pic->index);
7073#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7074 /*count info*/
7075 vdec_count_info(gvs, hevc->cur_pic->error_mark,
7076 hevc->cur_pic->stream_offset);
7077#endif
7078 return 2;
7079 }
7080#ifdef MCRCC_ENABLE
7081 config_mcrcc_axi_hw(hevc, hevc->cur_pic->slice_type);
7082#endif
7083 config_mpred_hw(hevc);
7084
7085 config_sao_hw(hevc, rpm_param);
7086
7087 if ((hevc->slice_type != 2) && (hevc->i_only & 0x2))
7088 return 0xf;
7089
7090 return 0;
7091}
7092
7093
7094
7095static int H265_alloc_mmu(struct hevc_state_s *hevc, struct PIC_s *new_pic,
7096 unsigned short bit_depth, unsigned int *mmu_index_adr) {
7097 int cur_buf_idx = new_pic->index;
7098 int bit_depth_10 = (bit_depth != 0x00);
7099 int picture_size;
7100 int cur_mmu_4k_number;
7101 int ret, max_frame_num;
7102 picture_size = compute_losless_comp_body_size(hevc, new_pic->width,
7103 new_pic->height, !bit_depth_10);
7104 cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
7105 if (hevc->double_write_mode & 0x10)
7106 return 0;
7107 /*hevc_print(hevc, 0,
7108 "alloc_mmu cur_idx : %d picture_size : %d mmu_4k_number : %d\r\n",
7109 cur_buf_idx, picture_size, cur_mmu_4k_number);*/
7110 if (new_pic->scatter_alloc) {
7111 decoder_mmu_box_free_idx(hevc->mmu_box, new_pic->index);
7112 new_pic->scatter_alloc = 0;
7113 }
7114 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7115 max_frame_num = MAX_FRAME_8K_NUM;
7116 else
7117 max_frame_num = MAX_FRAME_4K_NUM;
7118 if (cur_mmu_4k_number > max_frame_num) {
7119 hevc_print(hevc, 0, "over max !! 0x%x width %d height %d\n",
7120 cur_mmu_4k_number,
7121 new_pic->width,
7122 new_pic->height);
7123 return -1;
7124 }
7125 ret = decoder_mmu_box_alloc_idx(
7126 hevc->mmu_box,
7127 cur_buf_idx,
7128 cur_mmu_4k_number,
7129 mmu_index_adr);
7130 if (ret == 0)
7131 new_pic->scatter_alloc = 1;
7132 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
7133 "%s pic index %d page count(%d) ret =%d\n",
7134 __func__, cur_buf_idx,
7135 cur_mmu_4k_number,
7136 ret);
7137 return ret;
7138}
7139
7140
7141static void release_pic_mmu_buf(struct hevc_state_s *hevc,
7142 struct PIC_s *pic)
7143{
7144 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
7145 "%s pic index %d scatter_alloc %d\n",
7146 __func__, pic->index,
7147 pic->scatter_alloc);
7148
7149 if (hevc->mmu_enable
7150 && ((hevc->double_write_mode & 0x10) == 0)
7151 && pic->scatter_alloc)
7152 decoder_mmu_box_free_idx(hevc->mmu_box, pic->index);
7153 pic->scatter_alloc = 0;
7154}
7155
7156/*
7157 *************************************************
7158 *
7159 *h265 buffer management end
7160 *
7161 **************************************************
7162 */
7163static struct hevc_state_s *gHevc;
7164
7165static void hevc_local_uninit(struct hevc_state_s *hevc)
7166{
7167 hevc->rpm_ptr = NULL;
7168 hevc->lmem_ptr = NULL;
7169
7170#ifdef SWAP_HEVC_UCODE
7171 if (hevc->is_swap && get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
7172 if (hevc->mc_cpu_addr != NULL) {
7173 dma_free_coherent(amports_get_dma_device(),
7174 hevc->swap_size, hevc->mc_cpu_addr,
7175 hevc->mc_dma_handle);
7176 hevc->mc_cpu_addr = NULL;
7177 }
7178
7179 }
7180#endif
7181#ifdef DETREFILL_ENABLE
7182 if (hevc->is_swap && get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
7183 uninit_detrefill_buf(hevc);
7184#endif
7185 if (hevc->aux_addr) {
7186 dma_free_coherent(amports_get_dma_device(),
7187 hevc->prefix_aux_size + hevc->suffix_aux_size, hevc->aux_addr,
7188 hevc->aux_phy_addr);
7189 hevc->aux_addr = NULL;
7190 }
7191 if (hevc->rpm_addr) {
7192 dma_free_coherent(amports_get_dma_device(),
7193 RPM_BUF_SIZE, hevc->rpm_addr,
7194 hevc->rpm_phy_addr);
7195 hevc->rpm_addr = NULL;
7196 }
7197 if (hevc->lmem_addr) {
7198 dma_free_coherent(amports_get_dma_device(),
7199 RPM_BUF_SIZE, hevc->lmem_addr,
7200 hevc->lmem_phy_addr);
7201 hevc->lmem_addr = NULL;
7202 }
7203
7204 if (hevc->mmu_enable && hevc->frame_mmu_map_addr) {
7205 if (hevc->frame_mmu_map_phy_addr)
7206 dma_free_coherent(amports_get_dma_device(),
7207 get_frame_mmu_map_size(), hevc->frame_mmu_map_addr,
7208 hevc->frame_mmu_map_phy_addr);
7209
7210 hevc->frame_mmu_map_addr = NULL;
7211 }
7212
7213 kfree(gvs);
7214 gvs = NULL;
7215}
7216
7217static int hevc_local_init(struct hevc_state_s *hevc)
7218{
7219 int ret = -1;
7220 struct BuffInfo_s *cur_buf_info = NULL;
7221
7222 memset(&hevc->param, 0, sizeof(union param_u));
7223
7224 cur_buf_info = &hevc->work_space_buf_store;
7225
7226 if (vdec_is_support_4k()) {
7227 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7228 memcpy(cur_buf_info, &amvh265_workbuff_spec[2], /* 4k */
7229 sizeof(struct BuffInfo_s));
7230 else
7231 memcpy(cur_buf_info, &amvh265_workbuff_spec[1], /* 4k */
7232 sizeof(struct BuffInfo_s));
7233 } else
7234 memcpy(cur_buf_info, &amvh265_workbuff_spec[0], /* 1080p */
7235 sizeof(struct BuffInfo_s));
7236
7237 cur_buf_info->start_adr = hevc->buf_start;
7238 init_buff_spec(hevc, cur_buf_info);
7239
7240 hevc_init_stru(hevc, cur_buf_info);
7241
7242 hevc->bit_depth_luma = 8;
7243 hevc->bit_depth_chroma = 8;
7244 hevc->video_signal_type = 0;
7245 hevc->video_signal_type_debug = 0;
7246 bit_depth_luma = hevc->bit_depth_luma;
7247 bit_depth_chroma = hevc->bit_depth_chroma;
7248 video_signal_type = hevc->video_signal_type;
7249
7250 if ((get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) == 0) {
7251 hevc->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
7252 RPM_BUF_SIZE, &hevc->rpm_phy_addr, GFP_KERNEL);
7253 if (hevc->rpm_addr == NULL) {
7254 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7255 return -1;
7256 }
7257 hevc->rpm_ptr = hevc->rpm_addr;
7258 }
7259
7260 if (prefix_aux_buf_size > 0 ||
7261 suffix_aux_buf_size > 0) {
7262 u32 aux_buf_size;
7263
7264 hevc->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7265 hevc->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7266 aux_buf_size = hevc->prefix_aux_size + hevc->suffix_aux_size;
7267 hevc->aux_addr =dma_alloc_coherent(amports_get_dma_device(),
7268 aux_buf_size, &hevc->aux_phy_addr, GFP_KERNEL);
7269 if (hevc->aux_addr == NULL) {
7270 pr_err("%s: failed to alloc rpm buffer\n", __func__);
7271 return -1;
7272 }
7273 }
7274
7275 hevc->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
7276 LMEM_BUF_SIZE, &hevc->lmem_phy_addr, GFP_KERNEL);
7277 if (hevc->lmem_addr == NULL) {
7278 pr_err("%s: failed to alloc lmem buffer\n", __func__);
7279 return -1;
7280 }
7281 hevc->lmem_ptr = hevc->lmem_addr;
7282
7283 if (hevc->mmu_enable) {
7284 hevc->frame_mmu_map_addr =
7285 dma_alloc_coherent(amports_get_dma_device(),
7286 get_frame_mmu_map_size(),
7287 &hevc->frame_mmu_map_phy_addr, GFP_KERNEL);
7288 if (hevc->frame_mmu_map_addr == NULL) {
7289 pr_err("%s: failed to alloc count_buffer\n", __func__);
7290 return -1;
7291 }
7292 memset(hevc->frame_mmu_map_addr, 0, get_frame_mmu_map_size());
7293 }
7294 ret = 0;
7295 return ret;
7296}
7297
7298/*
7299 *******************************************
7300 * Mailbox command
7301 *******************************************
7302 */
7303#define CMD_FINISHED 0
7304#define CMD_ALLOC_VIEW 1
7305#define CMD_FRAME_DISPLAY 3
7306#define CMD_DEBUG 10
7307
7308
7309#define DECODE_BUFFER_NUM_MAX 32
7310#define DISPLAY_BUFFER_NUM 6
7311
7312#define video_domain_addr(adr) (adr&0x7fffffff)
7313#define DECODER_WORK_SPACE_SIZE 0x800000
7314
7315#define spec2canvas(x) \
7316 (((x)->uv_canvas_index << 16) | \
7317 ((x)->uv_canvas_index << 8) | \
7318 ((x)->y_canvas_index << 0))
7319
7320
7321static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic)
7322{
7323 struct vdec_s *vdec = hw_to_vdec(hevc);
7324 int canvas_w = ALIGN(pic->width, 64)/4;
7325 int canvas_h = ALIGN(pic->height, 32)/4;
7326 int blkmode = mem_map_mode;
7327
7328 /*CANVAS_BLKMODE_64X32*/
7329#ifdef SUPPORT_10BIT
7330 if (pic->double_write_mode) {
7331 canvas_w = pic->width /
7332 get_double_write_ratio(hevc, pic->double_write_mode);
7333 canvas_h = pic->height /
7334 get_double_write_ratio(hevc, pic->double_write_mode);
7335
7336 if (mem_map_mode == 0)
7337 canvas_w = ALIGN(canvas_w, 32);
7338 else
7339 canvas_w = ALIGN(canvas_w, 64);
7340 canvas_h = ALIGN(canvas_h, 32);
7341
7342 if (vdec->parallel_dec == 1) {
7343 if (pic->y_canvas_index == -1)
7344 pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7345 if (pic->uv_canvas_index == -1)
7346 pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7347 } else {
7348 pic->y_canvas_index = 128 + pic->index * 2;
7349 pic->uv_canvas_index = 128 + pic->index * 2 + 1;
7350 }
7351
7352 canvas_config_ex(pic->y_canvas_index,
7353 pic->dw_y_adr, canvas_w, canvas_h,
7354 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
7355 canvas_config_ex(pic->uv_canvas_index, pic->dw_u_v_adr,
7356 canvas_w, canvas_h,
7357 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
7358#ifdef MULTI_INSTANCE_SUPPORT
7359 pic->canvas_config[0].phy_addr =
7360 pic->dw_y_adr;
7361 pic->canvas_config[0].width =
7362 canvas_w;
7363 pic->canvas_config[0].height =
7364 canvas_h;
7365 pic->canvas_config[0].block_mode =
7366 blkmode;
7367 pic->canvas_config[0].endian = 7;
7368
7369 pic->canvas_config[1].phy_addr =
7370 pic->dw_u_v_adr;
7371 pic->canvas_config[1].width =
7372 canvas_w;
7373 pic->canvas_config[1].height =
7374 canvas_h;
7375 pic->canvas_config[1].block_mode =
7376 blkmode;
7377 pic->canvas_config[1].endian = 7;
7378#endif
7379 } else {
7380 if (!hevc->mmu_enable) {
7381 /* to change after 10bit VPU is ready ... */
7382 if (vdec->parallel_dec == 1) {
7383 if (pic->y_canvas_index == -1)
7384 pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7385 pic->uv_canvas_index = pic->y_canvas_index;
7386 } else {
7387 pic->y_canvas_index = 128 + pic->index;
7388 pic->uv_canvas_index = 128 + pic->index;
7389 }
7390
7391 canvas_config_ex(pic->y_canvas_index,
7392 pic->mc_y_adr, canvas_w, canvas_h,
7393 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
7394 canvas_config_ex(pic->uv_canvas_index, pic->mc_u_v_adr,
7395 canvas_w, canvas_h,
7396 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
7397 }
7398 }
7399#else
7400 if (vdec->parallel_dec == 1) {
7401 if (pic->y_canvas_index == -1)
7402 pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7403 if (pic->uv_canvas_index == -1)
7404 pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7405 } else {
7406 pic->y_canvas_index = 128 + pic->index * 2;
7407 pic->uv_canvas_index = 128 + pic->index * 2 + 1;
7408 }
7409
7410
7411 canvas_config_ex(pic->y_canvas_index, pic->mc_y_adr, canvas_w, canvas_h,
7412 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
7413 canvas_config_ex(pic->uv_canvas_index, pic->mc_u_v_adr,
7414 canvas_w, canvas_h,
7415 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
7416#endif
7417}
7418
7419static int init_buf_spec(struct hevc_state_s *hevc)
7420{
7421 int pic_width = hevc->pic_w;
7422 int pic_height = hevc->pic_h;
7423
7424 /* hevc_print(hevc, 0,
7425 *"%s1: %d %d\n", __func__, hevc->pic_w, hevc->pic_h);
7426 */
7427 hevc_print(hevc, 0,
7428 "%s2 %d %d\n", __func__, pic_width, pic_height);
7429 /* pic_width = hevc->pic_w; */
7430 /* pic_height = hevc->pic_h; */
7431
7432 if (hevc->frame_width == 0 || hevc->frame_height == 0) {
7433 hevc->frame_width = pic_width;
7434 hevc->frame_height = pic_height;
7435
7436 }
7437
7438 return 0;
7439}
7440
7441static int parse_sei(struct hevc_state_s *hevc,
7442 struct PIC_s *pic, char *sei_buf, uint32_t size)
7443{
7444 char *p = sei_buf;
7445 char *p_sei;
7446 uint16_t header;
7447 uint8_t nal_unit_type;
7448 uint8_t payload_type, payload_size;
7449 int i, j;
7450
7451 if (size < 2)
7452 return 0;
7453 header = *p++;
7454 header <<= 8;
7455 header += *p++;
7456 nal_unit_type = header >> 9;
7457 if ((nal_unit_type != NAL_UNIT_SEI)
7458 && (nal_unit_type != NAL_UNIT_SEI_SUFFIX))
7459 return 0;
7460 while (p+2 <= sei_buf+size) {
7461 payload_type = *p++;
7462 payload_size = *p++;
7463 if (p+payload_size <= sei_buf+size) {
7464 switch (payload_type) {
7465 case SEI_PicTiming:
7466 if ((parser_sei_enable & 0x4) &&
7467 hevc->frame_field_info_present_flag) {
7468 p_sei = p;
7469 hevc->curr_pic_struct = (*p_sei >> 4)&0x0f;
7470 pic->pic_struct = hevc->curr_pic_struct;
7471 if (get_dbg_flag(hevc) &
7472 H265_DEBUG_PIC_STRUCT) {
7473 hevc_print(hevc, 0,
7474 "parse result pic_struct = %d\n",
7475 hevc->curr_pic_struct);
7476 }
7477 }
7478 break;
7479 case SEI_UserDataITU_T_T35:
7480 p_sei = p;
7481 if (p_sei[0] == 0xB5
7482 && p_sei[1] == 0x00
7483 && p_sei[2] == 0x3C
7484 && p_sei[3] == 0x00
7485 && p_sei[4] == 0x01
7486 && p_sei[5] == 0x04)
7487 hevc->sei_present_flag |= SEI_HDR10PLUS_MASK;
7488
7489 break;
7490 case SEI_MasteringDisplayColorVolume:
7491 /*hevc_print(hevc, 0,
7492 "sei type: primary display color volume %d, size %d\n",
7493 payload_type,
7494 payload_size);*/
7495 /* master_display_colour */
7496 p_sei = p;
7497 for (i = 0; i < 3; i++) {
7498 for (j = 0; j < 2; j++) {
7499 hevc->primaries[i][j]
7500 = (*p_sei<<8)
7501 | *(p_sei+1);
7502 p_sei += 2;
7503 }
7504 }
7505 for (i = 0; i < 2; i++) {
7506 hevc->white_point[i]
7507 = (*p_sei<<8)
7508 | *(p_sei+1);
7509 p_sei += 2;
7510 }
7511 for (i = 0; i < 2; i++) {
7512 hevc->luminance[i]
7513 = (*p_sei<<24)
7514 | (*(p_sei+1)<<16)
7515 | (*(p_sei+2)<<8)
7516 | *(p_sei+3);
7517 p_sei += 4;
7518 }
7519 hevc->sei_present_flag |=
7520 SEI_MASTER_DISPLAY_COLOR_MASK;
7521 /*for (i = 0; i < 3; i++)
7522 for (j = 0; j < 2; j++)
7523 hevc_print(hevc, 0,
7524 "\tprimaries[%1d][%1d] = %04x\n",
7525 i, j,
7526 hevc->primaries[i][j]);
7527 hevc_print(hevc, 0,
7528 "\twhite_point = (%04x, %04x)\n",
7529 hevc->white_point[0],
7530 hevc->white_point[1]);
7531 hevc_print(hevc, 0,
7532 "\tmax,min luminance = %08x, %08x\n",
7533 hevc->luminance[0],
7534 hevc->luminance[1]);*/
7535 break;
7536 case SEI_ContentLightLevel:
7537 if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
7538 hevc_print(hevc, 0,
7539 "sei type: max content light level %d, size %d\n",
7540 payload_type, payload_size);
7541 /* content_light_level */
7542 p_sei = p;
7543 hevc->content_light_level[0]
7544 = (*p_sei<<8) | *(p_sei+1);
7545 p_sei += 2;
7546 hevc->content_light_level[1]
7547 = (*p_sei<<8) | *(p_sei+1);
7548 p_sei += 2;
7549 hevc->sei_present_flag |=
7550 SEI_CONTENT_LIGHT_LEVEL_MASK;
7551 if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
7552 hevc_print(hevc, 0,
7553 "\tmax cll = %04x, max_pa_cll = %04x\n",
7554 hevc->content_light_level[0],
7555 hevc->content_light_level[1]);
7556 break;
7557 default:
7558 break;
7559 }
7560 }
7561 p += payload_size;
7562 }
7563 return 0;
7564}
7565
7566static unsigned calc_ar(unsigned idc, unsigned sar_w, unsigned sar_h,
7567 unsigned w, unsigned h)
7568{
7569 unsigned ar;
7570
7571 if (idc == 255) {
7572 ar = div_u64(256ULL * sar_h * h,
7573 sar_w * w);
7574 } else {
7575 switch (idc) {
7576 case 1:
7577 ar = 0x100 * h / w;
7578 break;
7579 case 2:
7580 ar = 0x100 * h * 11 / (w * 12);
7581 break;
7582 case 3:
7583 ar = 0x100 * h * 11 / (w * 10);
7584 break;
7585 case 4:
7586 ar = 0x100 * h * 11 / (w * 16);
7587 break;
7588 case 5:
7589 ar = 0x100 * h * 33 / (w * 40);
7590 break;
7591 case 6:
7592 ar = 0x100 * h * 11 / (w * 24);
7593 break;
7594 case 7:
7595 ar = 0x100 * h * 11 / (w * 20);
7596 break;
7597 case 8:
7598 ar = 0x100 * h * 11 / (w * 32);
7599 break;
7600 case 9:
7601 ar = 0x100 * h * 33 / (w * 80);
7602 break;
7603 case 10:
7604 ar = 0x100 * h * 11 / (w * 18);
7605 break;
7606 case 11:
7607 ar = 0x100 * h * 11 / (w * 15);
7608 break;
7609 case 12:
7610 ar = 0x100 * h * 33 / (w * 64);
7611 break;
7612 case 13:
7613 ar = 0x100 * h * 99 / (w * 160);
7614 break;
7615 case 14:
7616 ar = 0x100 * h * 3 / (w * 4);
7617 break;
7618 case 15:
7619 ar = 0x100 * h * 2 / (w * 3);
7620 break;
7621 case 16:
7622 ar = 0x100 * h * 1 / (w * 2);
7623 break;
7624 default:
7625 ar = h * 0x100 / w;
7626 break;
7627 }
7628 }
7629
7630 return ar;
7631}
7632
7633static void set_frame_info(struct hevc_state_s *hevc, struct vframe_s *vf,
7634 struct PIC_s *pic)
7635{
7636 unsigned int ar;
7637 int i, j;
7638 char *p;
7639 unsigned size = 0;
7640 unsigned type = 0;
7641 struct vframe_master_display_colour_s *vf_dp
7642 = &vf->prop.master_display_colour;
7643
7644 vf->width = pic->width /
7645 get_double_write_ratio(hevc, pic->double_write_mode);
7646 vf->height = pic->height /
7647 get_double_write_ratio(hevc, pic->double_write_mode);
7648
7649 vf->duration = hevc->frame_dur;
7650 vf->duration_pulldown = 0;
7651 vf->flag = 0;
7652
7653 ar = min_t(u32, hevc->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
7654 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
7655
7656
7657 if (((pic->aspect_ratio_idc == 255) &&
7658 pic->sar_width &&
7659 pic->sar_height) ||
7660 ((pic->aspect_ratio_idc != 255) &&
7661 (pic->width))) {
7662 ar = min_t(u32,
7663 calc_ar(pic->aspect_ratio_idc,
7664 pic->sar_width,
7665 pic->sar_height,
7666 pic->width,
7667 pic->height),
7668 DISP_RATIO_ASPECT_RATIO_MAX);
7669 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
7670 }
7671 hevc->ratio_control = vf->ratio_control;
7672 if (pic->aux_data_buf
7673 && pic->aux_data_size) {
7674 /* parser sei */
7675 p = pic->aux_data_buf;
7676 while (p < pic->aux_data_buf
7677 + pic->aux_data_size - 8) {
7678 size = *p++;
7679 size = (size << 8) | *p++;
7680 size = (size << 8) | *p++;
7681 size = (size << 8) | *p++;
7682 type = *p++;
7683 type = (type << 8) | *p++;
7684 type = (type << 8) | *p++;
7685 type = (type << 8) | *p++;
7686 if (type == 0x02000000) {
7687 /* hevc_print(hevc, 0,
7688 "sei(%d)\n", size); */
7689 parse_sei(hevc, pic, p, size);
7690 }
7691 p += size;
7692 }
7693 }
7694 if (hevc->video_signal_type & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
7695 vf->signal_type = pic->video_signal_type;
7696 if (hevc->sei_present_flag & SEI_HDR10PLUS_MASK) {
7697 u32 data;
7698 data = vf->signal_type;
7699 data = data & 0xFFFF00FF;
7700 data = data | (0x30<<8);
7701 vf->signal_type = data;
7702 }
7703 }
7704 else
7705 vf->signal_type = 0;
7706 hevc->video_signal_type_debug = vf->signal_type;
7707
7708 /* master_display_colour */
7709 if (hevc->sei_present_flag & SEI_MASTER_DISPLAY_COLOR_MASK) {
7710 for (i = 0; i < 3; i++)
7711 for (j = 0; j < 2; j++)
7712 vf_dp->primaries[i][j] = hevc->primaries[i][j];
7713 for (i = 0; i < 2; i++) {
7714 vf_dp->white_point[i] = hevc->white_point[i];
7715 vf_dp->luminance[i]
7716 = hevc->luminance[i];
7717 }
7718 vf_dp->present_flag = 1;
7719 } else
7720 vf_dp->present_flag = 0;
7721
7722 /* content_light_level */
7723 if (hevc->sei_present_flag & SEI_CONTENT_LIGHT_LEVEL_MASK) {
7724 vf_dp->content_light_level.max_content
7725 = hevc->content_light_level[0];
7726 vf_dp->content_light_level.max_pic_average
7727 = hevc->content_light_level[1];
7728 vf_dp->content_light_level.present_flag = 1;
7729 } else
7730 vf_dp->content_light_level.present_flag = 0;
7731}
7732
7733static int vh265_vf_states(struct vframe_states *states, void *op_arg)
7734{
7735 unsigned long flags;
7736#ifdef MULTI_INSTANCE_SUPPORT
7737 struct vdec_s *vdec = op_arg;
7738 struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7739#else
7740 struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7741#endif
7742
7743 spin_lock_irqsave(&lock, flags);
7744
7745 states->vf_pool_size = VF_POOL_SIZE;
7746 states->buf_free_num = kfifo_len(&hevc->newframe_q);
7747 states->buf_avail_num = kfifo_len(&hevc->display_q);
7748
7749 if (step == 2)
7750 states->buf_avail_num = 0;
7751 spin_unlock_irqrestore(&lock, flags);
7752 return 0;
7753}
7754
7755static struct vframe_s *vh265_vf_peek(void *op_arg)
7756{
7757 struct vframe_s *vf[2] = {0, 0};
7758#ifdef MULTI_INSTANCE_SUPPORT
7759 struct vdec_s *vdec = op_arg;
7760 struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7761#else
7762 struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7763#endif
7764
7765 if (step == 2)
7766 return NULL;
7767
7768 if (force_disp_pic_index & 0x100) {
7769 if (force_disp_pic_index & 0x200)
7770 return NULL;
7771 return &hevc->vframe_dummy;
7772 }
7773
7774
7775 if (kfifo_out_peek(&hevc->display_q, (void *)&vf, 2)) {
7776 if (vf[1]) {
7777 vf[0]->next_vf_pts_valid = true;
7778 vf[0]->next_vf_pts = vf[1]->pts;
7779 } else
7780 vf[0]->next_vf_pts_valid = false;
7781 return vf[0];
7782 }
7783
7784 return NULL;
7785}
7786
7787static struct vframe_s *vh265_vf_get(void *op_arg)
7788{
7789 struct vframe_s *vf;
7790#ifdef MULTI_INSTANCE_SUPPORT
7791 struct vdec_s *vdec = op_arg;
7792 struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7793#else
7794 struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7795#endif
7796
7797 if (step == 2)
7798 return NULL;
7799 else if (step == 1)
7800 step = 2;
7801
7802#if 0
7803 if (force_disp_pic_index & 0x100) {
7804 int buffer_index = force_disp_pic_index & 0xff;
7805 struct PIC_s *pic = NULL;
7806 if (buffer_index >= 0
7807 && buffer_index < MAX_REF_PIC_NUM)
7808 pic = hevc->m_PIC[buffer_index];
7809 if (pic == NULL)
7810 return NULL;
7811 if (force_disp_pic_index & 0x200)
7812 return NULL;
7813
7814 vf = &hevc->vframe_dummy;
7815 if (get_double_write_mode(hevc)) {
7816 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
7817 VIDTYPE_VIU_NV21;
7818 if (hevc->m_ins_flag) {
7819 vf->canvas0Addr = vf->canvas1Addr = -1;
7820 vf->plane_num = 2;
7821 vf->canvas0_config[0] =
7822 pic->canvas_config[0];
7823 vf->canvas0_config[1] =
7824 pic->canvas_config[1];
7825
7826 vf->canvas1_config[0] =
7827 pic->canvas_config[0];
7828 vf->canvas1_config[1] =
7829 pic->canvas_config[1];
7830 } else {
7831 vf->canvas0Addr = vf->canvas1Addr
7832 = spec2canvas(pic);
7833 }
7834 } else {
7835 vf->canvas0Addr = vf->canvas1Addr = 0;
7836 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7837 if (hevc->mmu_enable)
7838 vf->type |= VIDTYPE_SCATTER;
7839 }
7840 vf->compWidth = pic->width;
7841 vf->compHeight = pic->height;
7842 update_vf_memhandle(hevc, vf, pic);
7843 switch (hevc->bit_depth_luma) {
7844 case 9:
7845 vf->bitdepth = BITDEPTH_Y9 | BITDEPTH_U9 | BITDEPTH_V9;
7846 break;
7847 case 10:
7848 vf->bitdepth = BITDEPTH_Y10 | BITDEPTH_U10
7849 | BITDEPTH_V10;
7850 break;
7851 default:
7852 vf->bitdepth = BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7853 break;
7854 }
7855 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7856 vf->bitdepth =
7857 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7858 if (hevc->mem_saving_mode == 1)
7859 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7860 vf->duration_pulldown = 0;
7861 vf->pts = 0;
7862 vf->pts_us64 = 0;
7863 set_frame_info(hevc, vf);
7864
7865 vf->width = pic->width /
7866 get_double_write_ratio(hevc, pic->double_write_mode);
7867 vf->height = pic->height /
7868 get_double_write_ratio(hevc, pic->double_write_mode);
7869
7870 force_disp_pic_index |= 0x200;
7871 return vf;
7872 }
7873#endif
7874
7875 if (kfifo_get(&hevc->display_q, &vf)) {
7876 struct vframe_s *next_vf;
7877 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
7878 hevc_print(hevc, 0,
7879 "%s(vf 0x%p type %d index 0x%x poc %d/%d) pts(%d,%d) dur %d\n",
7880 __func__, vf, vf->type, vf->index,
7881 get_pic_poc(hevc, vf->index & 0xff),
7882 get_pic_poc(hevc, (vf->index >> 8) & 0xff),
7883 vf->pts, vf->pts_us64,
7884 vf->duration);
7885#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
7886 if (get_dbg_flag(hevc) & H265_DEBUG_DV) {
7887 struct PIC_s *pic = hevc->m_PIC[vf->index & 0xff];
7888 if (pic->aux_data_buf && pic->aux_data_size > 0) {
7889 int i;
7890 struct PIC_s *pic =
7891 hevc->m_PIC[vf->index & 0xff];
7892 hevc_print(hevc, 0,
7893 "pic 0x%p aux size %d:\n",
7894 pic, pic->aux_data_size);
7895 for (i = 0; i < pic->aux_data_size; i++) {
7896 hevc_print_cont(hevc, 0,
7897 "%02x ", pic->aux_data_buf[i]);
7898 if (((i + 1) & 0xf) == 0)
7899 hevc_print_cont(hevc, 0, "\n");
7900 }
7901 hevc_print_cont(hevc, 0, "\n");
7902 }
7903 }
7904#endif
7905 hevc->show_frame_num++;
7906 hevc->vf_get_count++;
7907
7908 if (kfifo_peek(&hevc->display_q, &next_vf)) {
7909 vf->next_vf_pts_valid = true;
7910 vf->next_vf_pts = next_vf->pts;
7911 } else
7912 vf->next_vf_pts_valid = false;
7913
7914 return vf;
7915 }
7916
7917 return NULL;
7918}
7919static bool vf_valid_check(struct vframe_s *vf, struct hevc_state_s *hevc) {
7920 int i;
7921 for (i = 0; i < VF_POOL_SIZE; i++) {
7922 if (vf == &hevc->vfpool[i])
7923 return true;
7924 }
7925 pr_info(" h265 invalid vf been put, vf = %p\n", vf);
7926 for (i = 0; i < VF_POOL_SIZE; i++) {
7927 pr_info("www valid vf[%d]= %p \n", i, &hevc->vfpool[i]);
7928 }
7929 return false;
7930}
7931
7932static void vh265_vf_put(struct vframe_s *vf, void *op_arg)
7933{
7934 unsigned long flags;
7935#ifdef MULTI_INSTANCE_SUPPORT
7936 struct vdec_s *vdec = op_arg;
7937 struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7938#else
7939 struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7940#endif
7941 unsigned char index_top;
7942 unsigned char index_bot;
7943
7944 if (vf && (vf_valid_check(vf, hevc) == false))
7945 return;
7946 if (vf == (&hevc->vframe_dummy))
7947 return;
7948 index_top = vf->index & 0xff;
7949 index_bot = (vf->index >> 8) & 0xff;
7950 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
7951 hevc_print(hevc, 0,
7952 "%s(type %d index 0x%x)\n",
7953 __func__, vf->type, vf->index);
7954 hevc->vf_put_count++;
7955 kfifo_put(&hevc->newframe_q, (const struct vframe_s *)vf);
7956 spin_lock_irqsave(&lock, flags);
7957
7958 if (index_top != 0xff
7959 && index_top < MAX_REF_PIC_NUM
7960 && hevc->m_PIC[index_top]) {
7961 if (hevc->m_PIC[index_top]->vf_ref > 0) {
7962 hevc->m_PIC[index_top]->vf_ref--;
7963
7964 if (hevc->m_PIC[index_top]->vf_ref == 0) {
7965 hevc->m_PIC[index_top]->output_ready = 0;
7966
7967 if (hevc->wait_buf != 0)
7968 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
7969 0x1);
7970 }
7971 }
7972 }
7973
7974 if (index_bot != 0xff
7975 && index_bot < MAX_REF_PIC_NUM
7976 && hevc->m_PIC[index_bot]) {
7977 if (hevc->m_PIC[index_bot]->vf_ref > 0) {
7978 hevc->m_PIC[index_bot]->vf_ref--;
7979
7980 if (hevc->m_PIC[index_bot]->vf_ref == 0) {
7981 hevc->m_PIC[index_bot]->output_ready = 0;
7982 if (hevc->wait_buf != 0)
7983 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
7984 0x1);
7985 }
7986 }
7987 }
7988 spin_unlock_irqrestore(&lock, flags);
7989}
7990
7991static int vh265_event_cb(int type, void *data, void *op_arg)
7992{
7993 unsigned long flags;
7994#ifdef MULTI_INSTANCE_SUPPORT
7995 struct vdec_s *vdec = op_arg;
7996 struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7997#else
7998 struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7999#endif
8000 if (type & VFRAME_EVENT_RECEIVER_RESET) {
8001#if 0
8002 amhevc_stop();
8003#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
8004 vf_light_unreg_provider(&vh265_vf_prov);
8005#endif
8006 spin_lock_irqsave(&hevc->lock, flags);
8007 vh265_local_init();
8008 vh265_prot_init();
8009 spin_unlock_irqrestore(&hevc->lock, flags);
8010#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
8011 vf_reg_provider(&vh265_vf_prov);
8012#endif
8013 amhevc_start();
8014#endif
8015 } else if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
8016 struct provider_aux_req_s *req =
8017 (struct provider_aux_req_s *)data;
8018 unsigned char index;
8019
8020 spin_lock_irqsave(&lock, flags);
8021 index = req->vf->index & 0xff;
8022 req->aux_buf = NULL;
8023 req->aux_size = 0;
8024 if (req->bot_flag)
8025 index = (req->vf->index >> 8) & 0xff;
8026 if (index != 0xff
8027 && index < MAX_REF_PIC_NUM
8028 && hevc->m_PIC[index]) {
8029 req->aux_buf = hevc->m_PIC[index]->aux_data_buf;
8030 req->aux_size = hevc->m_PIC[index]->aux_data_size;
8031#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8032 if (hevc->bypass_dvenl && !dolby_meta_with_el)
8033 req->dv_enhance_exist = false;
8034 else
8035 req->dv_enhance_exist =
8036 hevc->m_PIC[index]->dv_enhance_exist;
8037 hevc_print(hevc, H265_DEBUG_DV,
8038 "query dv_enhance_exist for pic (vf 0x%p, poc %d index %d) flag => %d, aux sizd 0x%x\n",
8039 req->vf,
8040 hevc->m_PIC[index]->POC, index,
8041 req->dv_enhance_exist, req->aux_size);
8042#else
8043 req->dv_enhance_exist = 0;
8044#endif
8045 }
8046 spin_unlock_irqrestore(&lock, flags);
8047
8048 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8049 hevc_print(hevc, 0,
8050 "%s(type 0x%x vf index 0x%x)=>size 0x%x\n",
8051 __func__, type, index, req->aux_size);
8052#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8053 } else if (type & VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL) {
8054 if ((force_bypass_dvenl & 0x80000000) == 0) {
8055 hevc_print(hevc, 0,
8056 "%s: VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL\n",
8057 __func__);
8058 hevc->bypass_dvenl_enable = 1;
8059 }
8060
8061#endif
8062 }
8063 return 0;
8064}
8065
8066#ifdef HEVC_PIC_STRUCT_SUPPORT
8067static int process_pending_vframe(struct hevc_state_s *hevc,
8068 struct PIC_s *pair_pic, unsigned char pair_frame_top_flag)
8069{
8070 struct vframe_s *vf;
8071
8072 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8073 hevc_print(hevc, 0,
8074 "%s: pair_pic index 0x%x %s\n",
8075 __func__, pair_pic->index,
8076 pair_frame_top_flag ?
8077 "top" : "bot");
8078
8079 if (kfifo_len(&hevc->pending_q) > 1) {
8080 /* do not pending more than 1 frame */
8081 if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8082 hevc_print(hevc, 0,
8083 "fatal error, no available buffer slot.");
8084 return -1;
8085 }
8086 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8087 hevc_print(hevc, 0,
8088 "%s warning(1), vf=>display_q: (index 0x%x)\n",
8089 __func__, vf->index);
8090 hevc->vf_pre_count++;
8091 kfifo_put(&hevc->display_q, (const struct vframe_s *)vf);
8092 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8093 }
8094
8095 if (kfifo_peek(&hevc->pending_q, &vf)) {
8096 if (pair_pic == NULL || pair_pic->vf_ref <= 0) {
8097 /*
8098 *if pair_pic is recycled (pair_pic->vf_ref <= 0),
8099 *do not use it
8100 */
8101 if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8102 hevc_print(hevc, 0,
8103 "fatal error, no available buffer slot.");
8104 return -1;
8105 }
8106 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8107 hevc_print(hevc, 0,
8108 "%s warning(2), vf=>display_q: (index 0x%x)\n",
8109 __func__, vf->index);
8110 if (vf) {
8111 hevc->vf_pre_count++;
8112 kfifo_put(&hevc->display_q,
8113 (const struct vframe_s *)vf);
8114 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8115 }
8116 } else if ((!pair_frame_top_flag) &&
8117 (((vf->index >> 8) & 0xff) == 0xff)) {
8118 if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8119 hevc_print(hevc, 0,
8120 "fatal error, no available buffer slot.");
8121 return -1;
8122 }
8123 if (vf) {
8124 vf->type = VIDTYPE_PROGRESSIVE
8125 | VIDTYPE_VIU_NV21;
8126 vf->index &= 0xff;
8127 vf->index |= (pair_pic->index << 8);
8128 vf->canvas1Addr = spec2canvas(pair_pic);
8129 pair_pic->vf_ref++;
8130 kfifo_put(&hevc->display_q,
8131 (const struct vframe_s *)vf);
8132 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8133 hevc->vf_pre_count++;
8134 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8135 hevc_print(hevc, 0,
8136 "%s vf => display_q: (index 0x%x)\n",
8137 __func__, vf->index);
8138 }
8139 } else if (pair_frame_top_flag &&
8140 ((vf->index & 0xff) == 0xff)) {
8141 if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8142 hevc_print(hevc, 0,
8143 "fatal error, no available buffer slot.");
8144 return -1;
8145 }
8146 if (vf) {
8147 vf->type = VIDTYPE_PROGRESSIVE
8148 | VIDTYPE_VIU_NV21;
8149 vf->index &= 0xff00;
8150 vf->index |= pair_pic->index;
8151 vf->canvas0Addr = spec2canvas(pair_pic);
8152 pair_pic->vf_ref++;
8153 kfifo_put(&hevc->display_q,
8154 (const struct vframe_s *)vf);
8155 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8156 hevc->vf_pre_count++;
8157 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8158 hevc_print(hevc, 0,
8159 "%s vf => display_q: (index 0x%x)\n",
8160 __func__, vf->index);
8161 }
8162 }
8163 }
8164 return 0;
8165}
8166#endif
8167static void update_vf_memhandle(struct hevc_state_s *hevc,
8168 struct vframe_s *vf, struct PIC_s *pic)
8169{
8170 if (pic->index < 0) {
8171 vf->mem_handle = NULL;
8172 vf->mem_head_handle = NULL;
8173 } else if (vf->type & VIDTYPE_SCATTER) {
8174 vf->mem_handle =
8175 decoder_mmu_box_get_mem_handle(
8176 hevc->mmu_box, pic->index);
8177 vf->mem_head_handle =
8178 decoder_bmmu_box_get_mem_handle(
8179 hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
8180 } else {
8181 vf->mem_handle =
8182 decoder_bmmu_box_get_mem_handle(
8183 hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
8184 vf->mem_head_handle = NULL;
8185 /*vf->mem_head_handle =
8186 decoder_bmmu_box_get_mem_handle(
8187 hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));*/
8188 }
8189 return;
8190}
8191
8192static void fill_frame_info(struct hevc_state_s *hevc,
8193 struct PIC_s *pic, unsigned int framesize, unsigned int pts)
8194{
8195 struct vframe_qos_s *vframe_qos = &hevc->vframe_qos;
8196 if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_IDR)
8197 vframe_qos->type = 4;
8198 else if (pic->slice_type == I_SLICE)
8199 vframe_qos->type = 1;
8200 else if (pic->slice_type == P_SLICE)
8201 vframe_qos->type = 2;
8202 else if (pic->slice_type == B_SLICE)
8203 vframe_qos->type = 3;
8204/*
8205#define SHOW_QOS_INFO
8206*/
8207 vframe_qos->size = framesize;
8208 vframe_qos->pts = pts;
8209#ifdef SHOW_QOS_INFO
8210 hevc_print(hevc, 0, "slice:%d, poc:%d\n", pic->slice_type, pic->POC);
8211#endif
8212
8213
8214 vframe_qos->max_mv = pic->max_mv;
8215 vframe_qos->avg_mv = pic->avg_mv;
8216 vframe_qos->min_mv = pic->min_mv;
8217#ifdef SHOW_QOS_INFO
8218 hevc_print(hevc, 0, "mv: max:%d, avg:%d, min:%d\n",
8219 vframe_qos->max_mv,
8220 vframe_qos->avg_mv,
8221 vframe_qos->min_mv);
8222#endif
8223
8224 vframe_qos->max_qp = pic->max_qp;
8225 vframe_qos->avg_qp = pic->avg_qp;
8226 vframe_qos->min_qp = pic->min_qp;
8227#ifdef SHOW_QOS_INFO
8228 hevc_print(hevc, 0, "qp: max:%d, avg:%d, min:%d\n",
8229 vframe_qos->max_qp,
8230 vframe_qos->avg_qp,
8231 vframe_qos->min_qp);
8232#endif
8233
8234 vframe_qos->max_skip = pic->max_skip;
8235 vframe_qos->avg_skip = pic->avg_skip;
8236 vframe_qos->min_skip = pic->min_skip;
8237#ifdef SHOW_QOS_INFO
8238 hevc_print(hevc, 0, "skip: max:%d, avg:%d, min:%d\n",
8239 vframe_qos->max_skip,
8240 vframe_qos->avg_skip,
8241 vframe_qos->min_skip);
8242#endif
8243
8244 vframe_qos->num++;
8245
8246 if (hevc->frameinfo_enable)
8247 vdec_fill_frame_info(vframe_qos, 1);
8248}
8249
8250static int prepare_display_buf(struct hevc_state_s *hevc, struct PIC_s *pic)
8251{
8252#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8253 struct vdec_s *vdec = hw_to_vdec(hevc);
8254#endif
8255 struct vframe_s *vf = NULL;
8256 int stream_offset = pic->stream_offset;
8257 unsigned short slice_type = pic->slice_type;
8258 u32 frame_size;
8259
8260 if (force_disp_pic_index & 0x100) {
8261 /*recycle directly*/
8262 pic->output_ready = 0;
8263 return -1;
8264 }
8265 if (kfifo_get(&hevc->newframe_q, &vf) == 0) {
8266 hevc_print(hevc, 0,
8267 "fatal error, no available buffer slot.");
8268 return -1;
8269 }
8270 display_frame_count[hevc->index]++;
8271 if (vf) {
8272 /*hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
8273 "%s: pic index 0x%x\n",
8274 __func__, pic->index);*/
8275
8276 if (hevc->is_used_v4l) {
8277 vf->v4l_mem_handle
8278 = hevc->m_BUF[pic->BUF_index].v4l_ref_buf_addr;
8279 if (hevc->mmu_enable) {
8280 if (vdec_v4l_binding_fd_and_vf(vf->v4l_mem_handle, vf) < 0) {
8281 hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,
8282 "v4l: binding vf fail.\n");
8283 return -1;
8284 }
8285 }
8286 hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,
8287 "[%d] %s(), v4l mem handle: 0x%lx\n",
8288 ((struct aml_vcodec_ctx *)(hevc->v4l2_ctx))->id,
8289 __func__, vf->v4l_mem_handle);
8290 }
8291
8292#ifdef MULTI_INSTANCE_SUPPORT
8293 if (vdec_frame_based(hw_to_vdec(hevc))) {
8294 vf->pts = pic->pts;
8295 vf->pts_us64 = pic->pts64;
8296 vf->timestamp = pic->timestamp;
8297 }
8298 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
8299 stream_offset, &vf->pts, 0) != 0) { */
8300#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8301 else if (vdec->master == NULL) {
8302#else
8303 else {
8304#endif
8305#endif
8306 hevc_print(hevc, H265_DEBUG_OUT_PTS,
8307 "call pts_lookup_offset_us64(0x%x)\n",
8308 stream_offset);
8309 if (pts_lookup_offset_us64
8310 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
8311 &frame_size, 0,
8312 &vf->pts_us64) != 0) {
8313#ifdef DEBUG_PTS
8314 hevc->pts_missed++;
8315#endif
8316 vf->pts = 0;
8317 vf->pts_us64 = 0;
8318 }
8319#ifdef DEBUG_PTS
8320 else
8321 hevc->pts_hit++;
8322#endif
8323#ifdef MULTI_INSTANCE_SUPPORT
8324#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8325 } else {
8326 vf->pts = 0;
8327 vf->pts_us64 = 0;
8328 }
8329#else
8330 }
8331#endif
8332#endif
8333 if (pts_unstable && (hevc->frame_dur > 0))
8334 hevc->pts_mode = PTS_NONE_REF_USE_DURATION;
8335
8336 fill_frame_info(hevc, pic, frame_size, vf->pts);
8337
8338 if ((hevc->pts_mode == PTS_NORMAL) && (vf->pts != 0)
8339 && hevc->get_frame_dur) {
8340 int pts_diff = (int)vf->pts - hevc->last_lookup_pts;
8341
8342 if (pts_diff < 0) {
8343 hevc->pts_mode_switching_count++;
8344 hevc->pts_mode_recovery_count = 0;
8345
8346 if (hevc->pts_mode_switching_count >=
8347 PTS_MODE_SWITCHING_THRESHOLD) {
8348 hevc->pts_mode =
8349 PTS_NONE_REF_USE_DURATION;
8350 hevc_print(hevc, 0,
8351 "HEVC: switch to n_d mode.\n");
8352 }
8353
8354 } else {
8355 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
8356
8357 hevc->pts_mode_recovery_count++;
8358 if (hevc->pts_mode_recovery_count > p) {
8359 hevc->pts_mode_switching_count = 0;
8360 hevc->pts_mode_recovery_count = 0;
8361 }
8362 }
8363 }
8364
8365 if (vf->pts != 0)
8366 hevc->last_lookup_pts = vf->pts;
8367
8368 if ((hevc->pts_mode == PTS_NONE_REF_USE_DURATION)
8369 && (slice_type != 2))
8370 vf->pts = hevc->last_pts + DUR2PTS(hevc->frame_dur);
8371 hevc->last_pts = vf->pts;
8372
8373 if (vf->pts_us64 != 0)
8374 hevc->last_lookup_pts_us64 = vf->pts_us64;
8375
8376 if ((hevc->pts_mode == PTS_NONE_REF_USE_DURATION)
8377 && (slice_type != 2)) {
8378 vf->pts_us64 =
8379 hevc->last_pts_us64 +
8380 (DUR2PTS(hevc->frame_dur) * 100 / 9);
8381 }
8382 hevc->last_pts_us64 = vf->pts_us64;
8383 if ((get_dbg_flag(hevc) & H265_DEBUG_OUT_PTS) != 0) {
8384 hevc_print(hevc, 0,
8385 "H265 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n",
8386 vf->pts, vf->pts_us64);
8387 }
8388
8389 /*
8390 *vf->index:
8391 *(1) vf->type is VIDTYPE_PROGRESSIVE
8392 * and vf->canvas0Addr != vf->canvas1Addr,
8393 * vf->index[7:0] is the index of top pic
8394 * vf->index[15:8] is the index of bot pic
8395 *(2) other cases,
8396 * only vf->index[7:0] is used
8397 * vf->index[15:8] == 0xff
8398 */
8399 vf->index = 0xff00 | pic->index;
8400#if 1
8401/*SUPPORT_10BIT*/
8402 if (pic->double_write_mode & 0x10) {
8403 /* double write only */
8404 vf->compBodyAddr = 0;
8405 vf->compHeadAddr = 0;
8406 } else {
8407
8408 if (hevc->mmu_enable) {
8409 vf->compBodyAddr = 0;
8410 vf->compHeadAddr = pic->header_adr;
8411 } else {
8412 vf->compBodyAddr = pic->mc_y_adr; /*body adr*/
8413 vf->compHeadAddr = pic->mc_y_adr +
8414 pic->losless_comp_body_size;
8415 vf->mem_head_handle = NULL;
8416 }
8417
8418 /*head adr*/
8419 vf->canvas0Addr = vf->canvas1Addr = 0;
8420 }
8421 if (pic->double_write_mode) {
8422 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
8423 vf->type |= VIDTYPE_VIU_NV21;
8424 if ((pic->double_write_mode == 3) &&
8425 (!(IS_8K_SIZE(pic->width, pic->height)))) {
8426 vf->type |= VIDTYPE_COMPRESS;
8427 if (hevc->mmu_enable)
8428 vf->type |= VIDTYPE_SCATTER;
8429 }
8430#ifdef MULTI_INSTANCE_SUPPORT
8431 if (hevc->m_ins_flag &&
8432 (get_dbg_flag(hevc)
8433 & H265_CFG_CANVAS_IN_DECODE) == 0) {
8434 vf->canvas0Addr = vf->canvas1Addr = -1;
8435 vf->plane_num = 2;
8436 vf->canvas0_config[0] =
8437 pic->canvas_config[0];
8438 vf->canvas0_config[1] =
8439 pic->canvas_config[1];
8440
8441 vf->canvas1_config[0] =
8442 pic->canvas_config[0];
8443 vf->canvas1_config[1] =
8444 pic->canvas_config[1];
8445
8446 } else
8447#endif
8448 vf->canvas0Addr = vf->canvas1Addr
8449 = spec2canvas(pic);
8450 } else {
8451 vf->canvas0Addr = vf->canvas1Addr = 0;
8452 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
8453 if (hevc->mmu_enable)
8454 vf->type |= VIDTYPE_SCATTER;
8455 }
8456 vf->compWidth = pic->width;
8457 vf->compHeight = pic->height;
8458 update_vf_memhandle(hevc, vf, pic);
8459 switch (pic->bit_depth_luma) {
8460 case 9:
8461 vf->bitdepth = BITDEPTH_Y9;
8462 break;
8463 case 10:
8464 vf->bitdepth = BITDEPTH_Y10;
8465 break;
8466 default:
8467 vf->bitdepth = BITDEPTH_Y8;
8468 break;
8469 }
8470 switch (pic->bit_depth_chroma) {
8471 case 9:
8472 vf->bitdepth |= (BITDEPTH_U9 | BITDEPTH_V9);
8473 break;
8474 case 10:
8475 vf->bitdepth |= (BITDEPTH_U10 | BITDEPTH_V10);
8476 break;
8477 default:
8478 vf->bitdepth |= (BITDEPTH_U8 | BITDEPTH_V8);
8479 break;
8480 }
8481 if ((vf->type & VIDTYPE_COMPRESS) == 0)
8482 vf->bitdepth =
8483 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
8484 if (pic->mem_saving_mode == 1)
8485 vf->bitdepth |= BITDEPTH_SAVING_MODE;
8486#else
8487 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
8488 vf->type |= VIDTYPE_VIU_NV21;
8489 vf->canvas0Addr = vf->canvas1Addr = spec2canvas(pic);
8490#endif
8491 set_frame_info(hevc, vf, pic);
8492 /* if((vf->width!=pic->width)||(vf->height!=pic->height)) */
8493 /* hevc_print(hevc, 0,
8494 "aaa: %d/%d, %d/%d\n",
8495 vf->width,vf->height, pic->width, pic->height); */
8496 vf->width = pic->width;
8497 vf->height = pic->height;
8498
8499 if (force_w_h != 0) {
8500 vf->width = (force_w_h >> 16) & 0xffff;
8501 vf->height = force_w_h & 0xffff;
8502 }
8503 if (force_fps & 0x100) {
8504 u32 rate = force_fps & 0xff;
8505
8506 if (rate)
8507 vf->duration = 96000/rate;
8508 else
8509 vf->duration = 0;
8510 }
8511 if (force_fps & 0x200) {
8512 vf->pts = 0;
8513 vf->pts_us64 = 0;
8514 }
8515 /*
8516 * !!! to do ...
8517 * need move below code to get_new_pic(),
8518 * hevc->xxx can only be used by current decoded pic
8519 */
8520 if (pic->conformance_window_flag &&
8521 (get_dbg_flag(hevc) &
8522 H265_DEBUG_IGNORE_CONFORMANCE_WINDOW) == 0) {
8523 unsigned int SubWidthC, SubHeightC;
8524
8525 switch (pic->chroma_format_idc) {
8526 case 1:
8527 SubWidthC = 2;
8528 SubHeightC = 2;
8529 break;
8530 case 2:
8531 SubWidthC = 2;
8532 SubHeightC = 1;
8533 break;
8534 default:
8535 SubWidthC = 1;
8536 SubHeightC = 1;
8537 break;
8538 }
8539 vf->width -= SubWidthC *
8540 (pic->conf_win_left_offset +
8541 pic->conf_win_right_offset);
8542 vf->height -= SubHeightC *
8543 (pic->conf_win_top_offset +
8544 pic->conf_win_bottom_offset);
8545
8546 vf->compWidth -= SubWidthC *
8547 (pic->conf_win_left_offset +
8548 pic->conf_win_right_offset);
8549 vf->compHeight -= SubHeightC *
8550 (pic->conf_win_top_offset +
8551 pic->conf_win_bottom_offset);
8552
8553 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
8554 hevc_print(hevc, 0,
8555 "conformance_window %d, %d, %d, %d, %d => cropped width %d, height %d com_w %d com_h %d\n",
8556 pic->chroma_format_idc,
8557 pic->conf_win_left_offset,
8558 pic->conf_win_right_offset,
8559 pic->conf_win_top_offset,
8560 pic->conf_win_bottom_offset,
8561 vf->width, vf->height, vf->compWidth, vf->compHeight);
8562 }
8563
8564 vf->width = vf->width /
8565 get_double_write_ratio(hevc, pic->double_write_mode);
8566 vf->height = vf->height /
8567 get_double_write_ratio(hevc, pic->double_write_mode);
8568#ifdef HEVC_PIC_STRUCT_SUPPORT
8569 if (pic->pic_struct == 3 || pic->pic_struct == 4) {
8570 struct vframe_s *vf2;
8571
8572 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8573 hevc_print(hevc, 0,
8574 "pic_struct = %d index 0x%x\n",
8575 pic->pic_struct,
8576 pic->index);
8577
8578 if (kfifo_get(&hevc->newframe_q, &vf2) == 0) {
8579 hevc_print(hevc, 0,
8580 "fatal error, no available buffer slot.");
8581 return -1;
8582 }
8583 pic->vf_ref = 2;
8584 vf->duration = vf->duration>>1;
8585 memcpy(vf2, vf, sizeof(struct vframe_s));
8586
8587 if (pic->pic_struct == 3) {
8588 vf->type = VIDTYPE_INTERLACE_TOP
8589 | VIDTYPE_VIU_NV21;
8590 vf2->type = VIDTYPE_INTERLACE_BOTTOM
8591 | VIDTYPE_VIU_NV21;
8592 } else {
8593 vf->type = VIDTYPE_INTERLACE_BOTTOM
8594 | VIDTYPE_VIU_NV21;
8595 vf2->type = VIDTYPE_INTERLACE_TOP
8596 | VIDTYPE_VIU_NV21;
8597 }
8598 hevc->vf_pre_count++;
8599 decoder_do_frame_check(hw_to_vdec(hevc), vf);
8600 kfifo_put(&hevc->display_q,
8601 (const struct vframe_s *)vf);
8602 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8603 hevc->vf_pre_count++;
8604 kfifo_put(&hevc->display_q,
8605 (const struct vframe_s *)vf2);
8606 ATRACE_COUNTER(MODULE_NAME, vf2->pts);
8607 } else if (pic->pic_struct == 5
8608 || pic->pic_struct == 6) {
8609 struct vframe_s *vf2, *vf3;
8610
8611 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8612 hevc_print(hevc, 0,
8613 "pic_struct = %d index 0x%x\n",
8614 pic->pic_struct,
8615 pic->index);
8616
8617 if (kfifo_get(&hevc->newframe_q, &vf2) == 0) {
8618 hevc_print(hevc, 0,
8619 "fatal error, no available buffer slot.");
8620 return -1;
8621 }
8622 if (kfifo_get(&hevc->newframe_q, &vf3) == 0) {
8623 hevc_print(hevc, 0,
8624 "fatal error, no available buffer slot.");
8625 return -1;
8626 }
8627 pic->vf_ref = 3;
8628 vf->duration = vf->duration/3;
8629 memcpy(vf2, vf, sizeof(struct vframe_s));
8630 memcpy(vf3, vf, sizeof(struct vframe_s));
8631
8632 if (pic->pic_struct == 5) {
8633 vf->type = VIDTYPE_INTERLACE_TOP
8634 | VIDTYPE_VIU_NV21;
8635 vf2->type = VIDTYPE_INTERLACE_BOTTOM
8636 | VIDTYPE_VIU_NV21;
8637 vf3->type = VIDTYPE_INTERLACE_TOP
8638 | VIDTYPE_VIU_NV21;
8639 } else {
8640 vf->type = VIDTYPE_INTERLACE_BOTTOM
8641 | VIDTYPE_VIU_NV21;
8642 vf2->type = VIDTYPE_INTERLACE_TOP
8643 | VIDTYPE_VIU_NV21;
8644 vf3->type = VIDTYPE_INTERLACE_BOTTOM
8645 | VIDTYPE_VIU_NV21;
8646 }
8647 hevc->vf_pre_count++;
8648 decoder_do_frame_check(hw_to_vdec(hevc), vf);
8649 kfifo_put(&hevc->display_q,
8650 (const struct vframe_s *)vf);
8651 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8652 hevc->vf_pre_count++;
8653 kfifo_put(&hevc->display_q,
8654 (const struct vframe_s *)vf2);
8655 ATRACE_COUNTER(MODULE_NAME, vf2->pts);
8656 hevc->vf_pre_count++;
8657 kfifo_put(&hevc->display_q,
8658 (const struct vframe_s *)vf3);
8659 ATRACE_COUNTER(MODULE_NAME, vf3->pts);
8660
8661 } else if (pic->pic_struct == 9
8662 || pic->pic_struct == 10) {
8663 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8664 hevc_print(hevc, 0,
8665 "pic_struct = %d index 0x%x\n",
8666 pic->pic_struct,
8667 pic->index);
8668
8669 pic->vf_ref = 1;
8670 /* process previous pending vf*/
8671 process_pending_vframe(hevc,
8672 pic, (pic->pic_struct == 9));
8673
8674 decoder_do_frame_check(hw_to_vdec(hevc), vf);
8675 /* process current vf */
8676 kfifo_put(&hevc->pending_q,
8677 (const struct vframe_s *)vf);
8678 vf->height <<= 1;
8679 if (pic->pic_struct == 9) {
8680 vf->type = VIDTYPE_INTERLACE_TOP
8681 | VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8682 process_pending_vframe(hevc,
8683 hevc->pre_bot_pic, 0);
8684 } else {
8685 vf->type = VIDTYPE_INTERLACE_BOTTOM |
8686 VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8687 vf->index = (pic->index << 8) | 0xff;
8688 process_pending_vframe(hevc,
8689 hevc->pre_top_pic, 1);
8690 }
8691
8692 /**/
8693 if (pic->pic_struct == 9)
8694 hevc->pre_top_pic = pic;
8695 else
8696 hevc->pre_bot_pic = pic;
8697
8698 } else if (pic->pic_struct == 11
8699 || pic->pic_struct == 12) {
8700 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8701 hevc_print(hevc, 0,
8702 "pic_struct = %d index 0x%x\n",
8703 pic->pic_struct,
8704 pic->index);
8705 pic->vf_ref = 1;
8706 /* process previous pending vf*/
8707 process_pending_vframe(hevc, pic,
8708 (pic->pic_struct == 11));
8709
8710 /* put current into pending q */
8711 vf->height <<= 1;
8712 if (pic->pic_struct == 11)
8713 vf->type = VIDTYPE_INTERLACE_TOP |
8714 VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8715 else {
8716 vf->type = VIDTYPE_INTERLACE_BOTTOM |
8717 VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8718 vf->index = (pic->index << 8) | 0xff;
8719 }
8720 decoder_do_frame_check(hw_to_vdec(hevc), vf);
8721 kfifo_put(&hevc->pending_q,
8722 (const struct vframe_s *)vf);
8723
8724 /**/
8725 if (pic->pic_struct == 11)
8726 hevc->pre_top_pic = pic;
8727 else
8728 hevc->pre_bot_pic = pic;
8729
8730 } else {
8731 pic->vf_ref = 1;
8732
8733 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8734 hevc_print(hevc, 0,
8735 "pic_struct = %d index 0x%x\n",
8736 pic->pic_struct,
8737 pic->index);
8738
8739 switch (pic->pic_struct) {
8740 case 7:
8741 vf->duration <<= 1;
8742 break;
8743 case 8:
8744 vf->duration = vf->duration * 3;
8745 break;
8746 case 1:
8747 vf->height <<= 1;
8748 vf->type = VIDTYPE_INTERLACE_TOP |
8749 VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8750 process_pending_vframe(hevc, pic, 1);
8751 hevc->pre_top_pic = pic;
8752 break;
8753 case 2:
8754 vf->height <<= 1;
8755 vf->type = VIDTYPE_INTERLACE_BOTTOM
8756 | VIDTYPE_VIU_NV21
8757 | VIDTYPE_VIU_FIELD;
8758 process_pending_vframe(hevc, pic, 0);
8759 hevc->pre_bot_pic = pic;
8760 break;
8761 }
8762 hevc->vf_pre_count++;
8763 decoder_do_frame_check(hw_to_vdec(hevc), vf);
8764 kfifo_put(&hevc->display_q,
8765 (const struct vframe_s *)vf);
8766 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8767 }
8768#else
8769 vf->type_original = vf->type;
8770 pic->vf_ref = 1;
8771 hevc->vf_pre_count++;
8772 decoder_do_frame_check(hw_to_vdec(hevc), vf);
8773 kfifo_put(&hevc->display_q, (const struct vframe_s *)vf);
8774 ATRACE_COUNTER(MODULE_NAME, vf->pts);
8775
8776 if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8777 hevc_print(hevc, 0,
8778 "%s(type %d index 0x%x poc %d/%d) pts(%d,%d) dur %d\n",
8779 __func__, vf->type, vf->index,
8780 get_pic_poc(hevc, vf->index & 0xff),
8781 get_pic_poc(hevc, (vf->index >> 8) & 0xff),
8782 vf->pts, vf->pts_us64,
8783 vf->duration);
8784#endif
8785#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8786 /*count info*/
8787 vdec_count_info(gvs, 0, stream_offset);
8788#endif
8789 hw_to_vdec(hevc)->vdec_fps_detec(hw_to_vdec(hevc)->id);
8790 if (without_display_mode == 0) {
8791 vf_notify_receiver(hevc->provider_name,
8792 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
8793 }
8794 else
8795 vh265_vf_put(vh265_vf_get(vdec), vdec);
8796 }
8797
8798 return 0;
8799}
8800
8801static int notify_v4l_eos(struct vdec_s *vdec)
8802{
8803 struct hevc_state_s *hw = (struct hevc_state_s *)vdec->private;
8804 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
8805 struct vframe_s *vf = NULL;
8806 struct vdec_v4l2_buffer *fb = NULL;
8807
8808 if (hw->is_used_v4l && hw->eos) {
8809 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
8810 hevc_print(hw, 0,
8811 "%s fatal error, no available buffer slot.\n",
8812 __func__);
8813 return -1;
8814 }
8815
8816 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
8817 pr_err("[%d] get fb fail.\n", ctx->id);
8818 return -1;
8819 }
8820
8821 vf->type |= VIDTYPE_V4L_EOS;
8822 vf->timestamp = ULONG_MAX;
8823 vf->v4l_mem_handle = (unsigned long)fb;
8824 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
8825
8826 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
8827 vf_notify_receiver(vdec->vf_provider_name,
8828 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
8829
8830 pr_info("[%d] H265 EOS notify.\n", ctx->id);
8831 }
8832
8833 return 0;
8834}
8835
8836static void process_nal_sei(struct hevc_state_s *hevc,
8837 int payload_type, int payload_size)
8838{
8839 unsigned short data;
8840
8841 if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
8842 hevc_print(hevc, 0,
8843 "\tsei message: payload_type = 0x%02x, payload_size = 0x%02x\n",
8844 payload_type, payload_size);
8845
8846 if (payload_type == 137) {
8847 int i, j;
8848 /* MASTERING_DISPLAY_COLOUR_VOLUME */
8849 if (payload_size >= 24) {
8850 if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
8851 hevc_print(hevc, 0,
8852 "\tsei MASTERING_DISPLAY_COLOUR_VOLUME available\n");
8853 for (i = 0; i < 3; i++) {
8854 for (j = 0; j < 2; j++) {
8855 data =
8856 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8857 hevc->primaries[i][j] = data;
8858 WRITE_HREG(HEVC_SHIFT_COMMAND,
8859 (1<<7)|16);
8860 if (get_dbg_flag(hevc) &
8861 H265_DEBUG_PRINT_SEI)
8862 hevc_print(hevc, 0,
8863 "\t\tprimaries[%1d][%1d] = %04x\n",
8864 i, j, hevc->primaries[i][j]);
8865 }
8866 }
8867 for (i = 0; i < 2; i++) {
8868 data = (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8869 hevc->white_point[i] = data;
8870 WRITE_HREG(HEVC_SHIFT_COMMAND, (1<<7)|16);
8871 if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
8872 hevc_print(hevc, 0,
8873 "\t\twhite_point[%1d] = %04x\n",
8874 i, hevc->white_point[i]);
8875 }
8876 for (i = 0; i < 2; i++) {
8877 data = (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8878 hevc->luminance[i] = data << 16;
8879 WRITE_HREG(HEVC_SHIFT_COMMAND,
8880 (1<<7)|16);
8881 data =
8882 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8883 hevc->luminance[i] |= data;
8884 WRITE_HREG(HEVC_SHIFT_COMMAND,
8885 (1<<7)|16);
8886 if (get_dbg_flag(hevc) &
8887 H265_DEBUG_PRINT_SEI)
8888 hevc_print(hevc, 0,
8889 "\t\tluminance[%1d] = %08x\n",
8890 i, hevc->luminance[i]);
8891 }
8892 hevc->sei_present_flag |= SEI_MASTER_DISPLAY_COLOR_MASK;
8893 }
8894 payload_size -= 24;
8895 while (payload_size > 0) {
8896 data = (READ_HREG(HEVC_SHIFTED_DATA) >> 24);
8897 payload_size--;
8898 WRITE_HREG(HEVC_SHIFT_COMMAND, (1<<7)|8);
8899 hevc_print(hevc, 0, "\t\tskip byte %02x\n", data);
8900 }
8901 }
8902}
8903
8904static int hevc_recover(struct hevc_state_s *hevc)
8905{
8906 int ret = -1;
8907 u32 rem;
8908 u64 shift_byte_count64;
8909 unsigned int hevc_shift_byte_count;
8910 unsigned int hevc_stream_start_addr;
8911 unsigned int hevc_stream_end_addr;
8912 unsigned int hevc_stream_rd_ptr;
8913 unsigned int hevc_stream_wr_ptr;
8914 unsigned int hevc_stream_control;
8915 unsigned int hevc_stream_fifo_ctl;
8916 unsigned int hevc_stream_buf_size;
8917
8918 mutex_lock(&vh265_mutex);
8919#if 0
8920 for (i = 0; i < (hevc->debug_ptr_size / 2); i += 4) {
8921 int ii;
8922
8923 for (ii = 0; ii < 4; ii++)
8924 hevc_print(hevc, 0,
8925 "%04x ", hevc->debug_ptr[i + 3 - ii]);
8926 if (((i + ii) & 0xf) == 0)
8927 hevc_print(hevc, 0, "\n");
8928 }
8929#endif
8930#define ES_VID_MAN_RD_PTR (1<<0)
8931 if (!hevc->init_flag) {
8932 hevc_print(hevc, 0, "h265 has stopped, recover return!\n");
8933 mutex_unlock(&vh265_mutex);
8934 return ret;
8935 }
8936 amhevc_stop();
8937 msleep(20);
8938 ret = 0;
8939 /* reset */
8940 WRITE_PARSER_REG(PARSER_VIDEO_RP, READ_VREG(HEVC_STREAM_RD_PTR));
8941 SET_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
8942
8943 hevc_stream_start_addr = READ_VREG(HEVC_STREAM_START_ADDR);
8944 hevc_stream_end_addr = READ_VREG(HEVC_STREAM_END_ADDR);
8945 hevc_stream_rd_ptr = READ_VREG(HEVC_STREAM_RD_PTR);
8946 hevc_stream_wr_ptr = READ_VREG(HEVC_STREAM_WR_PTR);
8947 hevc_stream_control = READ_VREG(HEVC_STREAM_CONTROL);
8948 hevc_stream_fifo_ctl = READ_VREG(HEVC_STREAM_FIFO_CTL);
8949 hevc_stream_buf_size = hevc_stream_end_addr - hevc_stream_start_addr;
8950
8951 /* HEVC streaming buffer will reset and restart
8952 * from current hevc_stream_rd_ptr position
8953 */
8954 /* calculate HEVC_SHIFT_BYTE_COUNT value with the new position. */
8955 hevc_shift_byte_count = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
8956 if ((hevc->shift_byte_count_lo & (1 << 31))
8957 && ((hevc_shift_byte_count & (1 << 31)) == 0))
8958 hevc->shift_byte_count_hi++;
8959
8960 hevc->shift_byte_count_lo = hevc_shift_byte_count;
8961 shift_byte_count64 = ((u64)(hevc->shift_byte_count_hi) << 32) |
8962 hevc->shift_byte_count_lo;
8963 div_u64_rem(shift_byte_count64, hevc_stream_buf_size, &rem);
8964 shift_byte_count64 -= rem;
8965 shift_byte_count64 += hevc_stream_rd_ptr - hevc_stream_start_addr;
8966
8967 if (rem > (hevc_stream_rd_ptr - hevc_stream_start_addr))
8968 shift_byte_count64 += hevc_stream_buf_size;
8969
8970 hevc->shift_byte_count_lo = (u32)shift_byte_count64;
8971 hevc->shift_byte_count_hi = (u32)(shift_byte_count64 >> 32);
8972
8973 WRITE_VREG(DOS_SW_RESET3,
8974 /* (1<<2)| */
8975 (1 << 3) | (1 << 4) | (1 << 8) |
8976 (1 << 11) | (1 << 12) | (1 << 14)
8977 | (1 << 15) | (1 << 17) | (1 << 18) | (1 << 19));
8978 WRITE_VREG(DOS_SW_RESET3, 0);
8979
8980 WRITE_VREG(HEVC_STREAM_START_ADDR, hevc_stream_start_addr);
8981 WRITE_VREG(HEVC_STREAM_END_ADDR, hevc_stream_end_addr);
8982 WRITE_VREG(HEVC_STREAM_RD_PTR, hevc_stream_rd_ptr);
8983 WRITE_VREG(HEVC_STREAM_WR_PTR, hevc_stream_wr_ptr);
8984 WRITE_VREG(HEVC_STREAM_CONTROL, hevc_stream_control);
8985 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, hevc->shift_byte_count_lo);
8986 WRITE_VREG(HEVC_STREAM_FIFO_CTL, hevc_stream_fifo_ctl);
8987
8988 hevc_config_work_space_hw(hevc);
8989 decoder_hw_reset();
8990
8991 hevc->have_vps = 0;
8992 hevc->have_sps = 0;
8993 hevc->have_pps = 0;
8994
8995 hevc->have_valid_start_slice = 0;
8996
8997 if (get_double_write_mode(hevc) & 0x10)
8998 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
8999 0x1 << 31 /*/Enable NV21 reference read mode for MC*/
9000 );
9001
9002 WRITE_VREG(HEVC_WAIT_FLAG, 1);
9003 /* clear mailbox interrupt */
9004 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
9005 /* enable mailbox interrupt */
9006 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
9007 /* disable PSCALE for hardware sharing */
9008 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
9009
9010 CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
9011
9012 WRITE_VREG(DEBUG_REG1, 0x0);
9013
9014 if ((error_handle_policy & 1) == 0) {
9015 if ((error_handle_policy & 4) == 0) {
9016 /* ucode auto mode, and do not check vps/sps/pps/idr */
9017 WRITE_VREG(NAL_SEARCH_CTL,
9018 0xc);
9019 } else {
9020 WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */
9021 }
9022 } else {
9023 WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */
9024 }
9025
9026 if (get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE)
9027 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x10000);
9028 WRITE_VREG(NAL_SEARCH_CTL,
9029 READ_VREG(NAL_SEARCH_CTL)
9030 | ((parser_sei_enable & 0x7) << 17));
9031#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9032 WRITE_VREG(NAL_SEARCH_CTL,
9033 READ_VREG(NAL_SEARCH_CTL) |
9034 ((parser_dolby_vision_enable & 0x1) << 20));
9035#endif
9036 config_decode_mode(hevc);
9037 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
9038
9039 /* if (amhevc_loadmc(vh265_mc) < 0) { */
9040 /* amhevc_disable(); */
9041 /* return -EBUSY; */
9042 /* } */
9043#if 0
9044 for (i = 0; i < (hevc->debug_ptr_size / 2); i += 4) {
9045 int ii;
9046
9047 for (ii = 0; ii < 4; ii++) {
9048 /* hevc->debug_ptr[i+3-ii]=ttt++; */
9049 hevc_print(hevc, 0,
9050 "%04x ", hevc->debug_ptr[i + 3 - ii]);
9051 }
9052 if (((i + ii) & 0xf) == 0)
9053 hevc_print(hevc, 0, "\n");
9054 }
9055#endif
9056 init_pic_list_hw(hevc);
9057
9058 hevc_print(hevc, 0, "%s HEVC_SHIFT_BYTE_COUNT=0x%x\n", __func__,
9059 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
9060
9061#ifdef SWAP_HEVC_UCODE
9062 if (!tee_enabled() && hevc->is_swap &&
9063 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
9064 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->mc_dma_handle);
9065 /*pr_info("write swap buffer %x\n", (u32)(hevc->mc_dma_handle));*/
9066 }
9067#endif
9068 amhevc_start();
9069
9070 /* skip, search next start code */
9071 WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) & (~0x2));
9072 hevc->skip_flag = 1;
9073#ifdef ERROR_HANDLE_DEBUG
9074 if (dbg_nal_skip_count & 0x20000) {
9075 dbg_nal_skip_count &= ~0x20000;
9076 mutex_unlock(&vh265_mutex);
9077 return ret;
9078 }
9079#endif
9080 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9081 /* Interrupt Amrisc to excute */
9082 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9083#ifdef MULTI_INSTANCE_SUPPORT
9084 if (!hevc->m_ins_flag)
9085#endif
9086 hevc->first_pic_after_recover = 1;
9087 mutex_unlock(&vh265_mutex);
9088 return ret;
9089}
9090
9091static void dump_aux_buf(struct hevc_state_s *hevc)
9092{
9093 int i;
9094 unsigned short *aux_adr =
9095 (unsigned short *)
9096 hevc->aux_addr;
9097 unsigned int aux_size =
9098 (READ_VREG(HEVC_AUX_DATA_SIZE)
9099 >> 16) << 4;
9100
9101 if (hevc->prefix_aux_size > 0) {
9102 hevc_print(hevc, 0,
9103 "prefix aux: (size %d)\n",
9104 aux_size);
9105 for (i = 0; i <
9106 (aux_size >> 1); i++) {
9107 hevc_print_cont(hevc, 0,
9108 "%04x ",
9109 *(aux_adr + i));
9110 if (((i + 1) & 0xf)
9111 == 0)
9112 hevc_print_cont(hevc,
9113 0, "\n");
9114 }
9115 }
9116 if (hevc->suffix_aux_size > 0) {
9117 aux_adr = (unsigned short *)
9118 (hevc->aux_addr +
9119 hevc->prefix_aux_size);
9120 aux_size =
9121 (READ_VREG(HEVC_AUX_DATA_SIZE) & 0xffff)
9122 << 4;
9123 hevc_print(hevc, 0,
9124 "suffix aux: (size %d)\n",
9125 aux_size);
9126 for (i = 0; i <
9127 (aux_size >> 1); i++) {
9128 hevc_print_cont(hevc, 0,
9129 "%04x ", *(aux_adr + i));
9130 if (((i + 1) & 0xf) == 0)
9131 hevc_print_cont(hevc, 0, "\n");
9132 }
9133 }
9134}
9135
9136#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9137static void dolby_get_meta(struct hevc_state_s *hevc)
9138{
9139 struct vdec_s *vdec = hw_to_vdec(hevc);
9140
9141 if (get_dbg_flag(hevc) &
9142 H265_DEBUG_BUFMGR_MORE)
9143 dump_aux_buf(hevc);
9144 if (vdec->dolby_meta_with_el || vdec->slave) {
9145 set_aux_data(hevc,
9146 hevc->cur_pic, 0, 0);
9147 } else if (vdec->master) {
9148 struct hevc_state_s *hevc_ba =
9149 (struct hevc_state_s *)
9150 vdec->master->private;
9151 /*do not use hevc_ba*/
9152 set_aux_data(hevc,
9153 hevc_ba->cur_pic,
9154 0, 1);
9155 set_aux_data(hevc,
9156 hevc->cur_pic, 0, 2);
9157 }
9158}
9159#endif
9160
9161static void read_decode_info(struct hevc_state_s *hevc)
9162{
9163 uint32_t decode_info =
9164 READ_HREG(HEVC_DECODE_INFO);
9165 hevc->start_decoding_flag |=
9166 (decode_info & 0xff);
9167 hevc->rps_set_id = (decode_info >> 8) & 0xff;
9168}
9169
9170static irqreturn_t vh265_isr_thread_fn(int irq, void *data)
9171{
9172 struct hevc_state_s *hevc = (struct hevc_state_s *) data;
9173 unsigned int dec_status = hevc->dec_status;
9174 int i, ret;
9175
9176#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9177 struct vdec_s *vdec = hw_to_vdec(hevc);
9178#endif
9179
9180 if (hevc->eos)
9181 return IRQ_HANDLED;
9182 if (
9183#ifdef MULTI_INSTANCE_SUPPORT
9184 (!hevc->m_ins_flag) &&
9185#endif
9186 hevc->error_flag == 1) {
9187 if ((error_handle_policy & 0x10) == 0) {
9188 if (hevc->cur_pic) {
9189 int current_lcu_idx =
9190 READ_VREG(HEVC_PARSER_LCU_START)
9191 & 0xffffff;
9192 if (current_lcu_idx <
9193 ((hevc->lcu_x_num*hevc->lcu_y_num)-1))
9194 hevc->cur_pic->error_mark = 1;
9195
9196 }
9197 }
9198 if ((error_handle_policy & 1) == 0) {
9199 hevc->error_skip_nal_count = 1;
9200 /* manual search nal, skip error_skip_nal_count
9201 * of nal and trigger the HEVC_NAL_SEARCH_DONE irq
9202 */
9203 WRITE_VREG(NAL_SEARCH_CTL,
9204 (error_skip_nal_count << 4) | 0x1);
9205 } else {
9206 hevc->error_skip_nal_count = error_skip_nal_count;
9207 WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */
9208 }
9209 if ((get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE)
9210#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9211 || vdec->master
9212 || vdec->slave
9213#endif
9214 ) {
9215 WRITE_VREG(NAL_SEARCH_CTL,
9216 READ_VREG(NAL_SEARCH_CTL) | 0x10000);
9217 }
9218 WRITE_VREG(NAL_SEARCH_CTL,
9219 READ_VREG(NAL_SEARCH_CTL)
9220 | ((parser_sei_enable & 0x7) << 17));
9221#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9222 WRITE_VREG(NAL_SEARCH_CTL,
9223 READ_VREG(NAL_SEARCH_CTL) |
9224 ((parser_dolby_vision_enable & 0x1) << 20));
9225#endif
9226 config_decode_mode(hevc);
9227 /* search new nal */
9228 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9229 /* Interrupt Amrisc to excute */
9230 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9231
9232 /* hevc_print(hevc, 0,
9233 *"%s: error handle\n", __func__);
9234 */
9235 hevc->error_flag = 2;
9236 return IRQ_HANDLED;
9237 } else if (
9238#ifdef MULTI_INSTANCE_SUPPORT
9239 (!hevc->m_ins_flag) &&
9240#endif
9241 hevc->error_flag == 3) {
9242 hevc_print(hevc, 0, "error_flag=3, hevc_recover\n");
9243 hevc_recover(hevc);
9244 hevc->error_flag = 0;
9245
9246 if ((error_handle_policy & 0x10) == 0) {
9247 if (hevc->cur_pic) {
9248 int current_lcu_idx =
9249 READ_VREG(HEVC_PARSER_LCU_START)
9250 & 0xffffff;
9251 if (current_lcu_idx <
9252 ((hevc->lcu_x_num*hevc->lcu_y_num)-1))
9253 hevc->cur_pic->error_mark = 1;
9254
9255 }
9256 }
9257 if ((error_handle_policy & 1) == 0) {
9258 /* need skip some data when
9259 * error_flag of 3 is triggered,
9260 */
9261 /* to avoid hevc_recover() being called
9262 * for many times at the same bitstream position
9263 */
9264 hevc->error_skip_nal_count = 1;
9265 /* manual search nal, skip error_skip_nal_count
9266 * of nal and trigger the HEVC_NAL_SEARCH_DONE irq
9267 */
9268 WRITE_VREG(NAL_SEARCH_CTL,
9269 (error_skip_nal_count << 4) | 0x1);
9270 }
9271
9272 if ((error_handle_policy & 0x2) == 0) {
9273 hevc->have_vps = 1;
9274 hevc->have_sps = 1;
9275 hevc->have_pps = 1;
9276 }
9277 return IRQ_HANDLED;
9278 }
9279 if (!hevc->m_ins_flag) {
9280 i = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9281 if ((hevc->shift_byte_count_lo & (1 << 31))
9282 && ((i & (1 << 31)) == 0))
9283 hevc->shift_byte_count_hi++;
9284 hevc->shift_byte_count_lo = i;
9285 }
9286#ifdef MULTI_INSTANCE_SUPPORT
9287 mutex_lock(&hevc->chunks_mutex);
9288 if ((dec_status == HEVC_DECPIC_DATA_DONE ||
9289 dec_status == HEVC_FIND_NEXT_PIC_NAL ||
9290 dec_status == HEVC_FIND_NEXT_DVEL_NAL)
9291 && (hevc->chunk)) {
9292 hevc->cur_pic->pts = hevc->chunk->pts;
9293 hevc->cur_pic->pts64 = hevc->chunk->pts64;
9294 hevc->cur_pic->timestamp = hevc->chunk->timestamp;
9295 }
9296 mutex_unlock(&hevc->chunks_mutex);
9297
9298 if (dec_status == HEVC_DECODE_BUFEMPTY ||
9299 dec_status == HEVC_DECODE_BUFEMPTY2) {
9300 if (hevc->m_ins_flag) {
9301 read_decode_info(hevc);
9302 if (vdec_frame_based(hw_to_vdec(hevc))) {
9303 hevc->empty_flag = 1;
9304 goto pic_done;
9305 } else {
9306 if (
9307#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9308 vdec->master ||
9309 vdec->slave ||
9310#endif
9311 (data_resend_policy & 0x1)) {
9312 hevc->dec_result = DEC_RESULT_AGAIN;
9313 amhevc_stop();
9314 restore_decode_state(hevc);
9315 } else
9316 hevc->dec_result = DEC_RESULT_GET_DATA;
9317 }
9318 reset_process_time(hevc);
9319 vdec_schedule_work(&hevc->work);
9320 }
9321 return IRQ_HANDLED;
9322 } else if ((dec_status == HEVC_SEARCH_BUFEMPTY) ||
9323 (dec_status == HEVC_NAL_DECODE_DONE)
9324 ) {
9325 if (hevc->m_ins_flag) {
9326 read_decode_info(hevc);
9327 if (vdec_frame_based(hw_to_vdec(hevc))) {
9328 /*hevc->dec_result = DEC_RESULT_GET_DATA;*/
9329 hevc->empty_flag = 1;
9330 goto pic_done;
9331 } else {
9332 hevc->dec_result = DEC_RESULT_AGAIN;
9333 amhevc_stop();
9334 restore_decode_state(hevc);
9335 }
9336
9337 reset_process_time(hevc);
9338 vdec_schedule_work(&hevc->work);
9339 }
9340
9341 return IRQ_HANDLED;
9342 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
9343 if (hevc->m_ins_flag) {
9344 struct PIC_s *pic;
9345 struct PIC_s *pic_display;
9346 int decoded_poc;
9347#ifdef DETREFILL_ENABLE
9348 if (hevc->is_swap &&
9349 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
9350 if (hevc->detbuf_adr_virt && hevc->delrefill_check
9351 && READ_VREG(HEVC_SAO_DBG_MODE0))
9352 hevc->delrefill_check = 2;
9353 }
9354#endif
9355 hevc->empty_flag = 0;
9356pic_done:
9357 if (input_frame_based(hw_to_vdec(hevc)) &&
9358 frmbase_cont_bitlevel != 0 &&
9359 (hevc->decode_size > READ_VREG(HEVC_SHIFT_BYTE_COUNT)) &&
9360 (hevc->decode_size - (READ_VREG(HEVC_SHIFT_BYTE_COUNT))
9361 > frmbase_cont_bitlevel)) {
9362 /*handle the case: multi pictures in one packet*/
9363 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
9364 "%s has more data index= %d, size=0x%x shiftcnt=0x%x)\n",
9365 __func__,
9366 hevc->decode_idx, hevc->decode_size,
9367 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
9368 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9369 start_process_time(hevc);
9370 return IRQ_HANDLED;
9371 }
9372
9373 read_decode_info(hevc);
9374 get_picture_qos_info(hevc);
9375#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9376 hevc->start_parser_type = 0;
9377 hevc->switch_dvlayer_flag = 0;
9378#endif
9379 hevc->decoded_poc = hevc->curr_POC;
9380 hevc->decoding_pic = NULL;
9381 hevc->dec_result = DEC_RESULT_DONE;
9382#ifdef DETREFILL_ENABLE
9383 if (hevc->is_swap &&
9384 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
9385 if (hevc->delrefill_check != 2)
9386#endif
9387
9388 amhevc_stop();
9389
9390 reset_process_time(hevc);
9391
9392 if (hevc->vf_pre_count == 0) {
9393 decoded_poc = hevc->curr_POC;
9394 pic = get_pic_by_POC(hevc, decoded_poc);
9395 if (pic && (pic->POC != INVALID_POC)) {
9396 /*PB skip control */
9397 if (pic->error_mark == 0
9398 && hevc->PB_skip_mode == 1) {
9399 /* start decoding after
9400 * first I
9401 */
9402 hevc->ignore_bufmgr_error |= 0x1;
9403 }
9404 if (hevc->ignore_bufmgr_error & 1) {
9405 if (hevc->PB_skip_count_after_decoding > 0) {
9406 hevc->PB_skip_count_after_decoding--;
9407 } else {
9408 /* start displaying */
9409 hevc->ignore_bufmgr_error |= 0x2;
9410 }
9411 }
9412 if (hevc->mmu_enable
9413 && ((hevc->double_write_mode & 0x10) == 0)) {
9414 if (!hevc->m_ins_flag) {
9415 hevc->used_4k_num =
9416 READ_VREG(HEVC_SAO_MMU_STATUS) >> 16;
9417
9418 if ((!is_skip_decoding(hevc, pic)) &&
9419 (hevc->used_4k_num >= 0) &&
9420 (hevc->cur_pic->scatter_alloc
9421 == 1)) {
9422 hevc_print(hevc,
9423 H265_DEBUG_BUFMGR_MORE,
9424 "%s pic index %d scatter_alloc %d page_start %d\n",
9425 "decoder_mmu_box_free_idx_tail",
9426 hevc->cur_pic->index,
9427 hevc->cur_pic->scatter_alloc,
9428 hevc->used_4k_num);
9429 decoder_mmu_box_free_idx_tail(
9430 hevc->mmu_box,
9431 hevc->cur_pic->index,
9432 hevc->used_4k_num);
9433 hevc->cur_pic->scatter_alloc
9434 = 2;
9435 }
9436 hevc->used_4k_num = -1;
9437 }
9438 }
9439
9440 pic->output_mark = 1;
9441 pic->recon_mark = 1;
9442 }
9443force_output:
9444 pic_display = output_pic(hevc, 1);
9445
9446 if (pic_display) {
9447 if ((pic_display->error_mark &&
9448 ((hevc->ignore_bufmgr_error &
9449 0x2) == 0))
9450 || (get_dbg_flag(hevc) &
9451 H265_DEBUG_DISPLAY_CUR_FRAME)
9452 || (get_dbg_flag(hevc) &
9453 H265_DEBUG_NO_DISPLAY)) {
9454 pic_display->output_ready = 0;
9455 if (get_dbg_flag(hevc) &
9456 H265_DEBUG_BUFMGR) {
9457 hevc_print(hevc, 0,
9458 "[BM] Display: POC %d, ",
9459 pic_display->POC);
9460 hevc_print_cont(hevc, 0,
9461 "decoding index %d ==> ",
9462 pic_display->
9463 decode_idx);
9464 hevc_print_cont(hevc, 0,
9465 "Debug or err,recycle it\n");
9466 }
9467 } else {
9468 if (pic_display->
9469 slice_type != 2) {
9470 pic_display->output_ready = 0;
9471 } else {
9472 prepare_display_buf
9473 (hevc,
9474 pic_display);
9475 hevc->first_pic_flag = 1;
9476 }
9477 }
9478 }
9479 }
9480
9481 vdec_schedule_work(&hevc->work);
9482 }
9483
9484 return IRQ_HANDLED;
9485#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9486 } else if (dec_status == HEVC_FIND_NEXT_PIC_NAL ||
9487 dec_status == HEVC_FIND_NEXT_DVEL_NAL) {
9488 if (hevc->m_ins_flag) {
9489 unsigned char next_parser_type =
9490 READ_HREG(CUR_NAL_UNIT_TYPE) & 0xff;
9491 read_decode_info(hevc);
9492
9493 if (vdec->slave &&
9494 dec_status == HEVC_FIND_NEXT_DVEL_NAL) {
9495 /*cur is base, found enhance*/
9496 struct hevc_state_s *hevc_el =
9497 (struct hevc_state_s *)
9498 vdec->slave->private;
9499 hevc->switch_dvlayer_flag = 1;
9500 hevc->no_switch_dvlayer_count = 0;
9501 hevc_el->start_parser_type =
9502 next_parser_type;
9503 hevc_print(hevc, H265_DEBUG_DV,
9504 "switch (poc %d) to el\n",
9505 hevc->cur_pic ?
9506 hevc->cur_pic->POC :
9507 INVALID_POC);
9508 } else if (vdec->master &&
9509 dec_status == HEVC_FIND_NEXT_PIC_NAL) {
9510 /*cur is enhance, found base*/
9511 struct hevc_state_s *hevc_ba =
9512 (struct hevc_state_s *)
9513 vdec->master->private;
9514 hevc->switch_dvlayer_flag = 1;
9515 hevc->no_switch_dvlayer_count = 0;
9516 hevc_ba->start_parser_type =
9517 next_parser_type;
9518 hevc_print(hevc, H265_DEBUG_DV,
9519 "switch (poc %d) to bl\n",
9520 hevc->cur_pic ?
9521 hevc->cur_pic->POC :
9522 INVALID_POC);
9523 } else {
9524 hevc->switch_dvlayer_flag = 0;
9525 hevc->start_parser_type =
9526 next_parser_type;
9527 hevc->no_switch_dvlayer_count++;
9528 hevc_print(hevc, H265_DEBUG_DV,
9529 "%s: no_switch_dvlayer_count = %d\n",
9530 vdec->master ? "el" : "bl",
9531 hevc->no_switch_dvlayer_count);
9532 if (vdec->slave &&
9533 dolby_el_flush_th != 0 &&
9534 hevc->no_switch_dvlayer_count >
9535 dolby_el_flush_th) {
9536 struct hevc_state_s *hevc_el =
9537 (struct hevc_state_s *)
9538 vdec->slave->private;
9539 struct PIC_s *el_pic;
9540 check_pic_decoded_error(hevc_el,
9541 hevc_el->pic_decoded_lcu_idx);
9542 el_pic = get_pic_by_POC(hevc_el,
9543 hevc_el->curr_POC);
9544 hevc_el->curr_POC = INVALID_POC;
9545 hevc_el->m_pocRandomAccess = MAX_INT;
9546 flush_output(hevc_el, el_pic);
9547 hevc_el->decoded_poc = INVALID_POC; /*
9548 already call flush_output*/
9549 hevc_el->decoding_pic = NULL;
9550 hevc->no_switch_dvlayer_count = 0;
9551 if (get_dbg_flag(hevc) & H265_DEBUG_DV)
9552 hevc_print(hevc, 0,
9553 "no el anymore, flush_output el\n");
9554 }
9555 }
9556 hevc->decoded_poc = hevc->curr_POC;
9557 hevc->decoding_pic = NULL;
9558 hevc->dec_result = DEC_RESULT_DONE;
9559 amhevc_stop();
9560 reset_process_time(hevc);
9561 if (aux_data_is_avaible(hevc))
9562 dolby_get_meta(hevc);
9563 if(hevc->cur_pic->slice_type == 2 &&
9564 hevc->vf_pre_count == 0) {
9565 hevc_print(hevc, 0,
9566 "first slice_type %x no_switch_dvlayer_count %x\n",
9567 hevc->cur_pic->slice_type,
9568 hevc->no_switch_dvlayer_count);
9569 goto force_output;
9570 }
9571 vdec_schedule_work(&hevc->work);
9572 }
9573
9574 return IRQ_HANDLED;
9575#endif
9576 }
9577
9578#endif
9579
9580 if (dec_status == HEVC_SEI_DAT) {
9581 if (!hevc->m_ins_flag) {
9582 int payload_type =
9583 READ_HREG(CUR_NAL_UNIT_TYPE) & 0xffff;
9584 int payload_size =
9585 (READ_HREG(CUR_NAL_UNIT_TYPE) >> 16) & 0xffff;
9586 process_nal_sei(hevc,
9587 payload_type, payload_size);
9588 }
9589 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_SEI_DAT_DONE);
9590 } else if (dec_status == HEVC_NAL_SEARCH_DONE) {
9591 int naltype = READ_HREG(CUR_NAL_UNIT_TYPE);
9592 int parse_type = HEVC_DISCARD_NAL;
9593
9594 hevc->error_watchdog_count = 0;
9595 hevc->error_skip_nal_wt_cnt = 0;
9596#ifdef MULTI_INSTANCE_SUPPORT
9597 if (hevc->m_ins_flag)
9598 reset_process_time(hevc);
9599#endif
9600 if (slice_parse_begin > 0 &&
9601 get_dbg_flag(hevc) & H265_DEBUG_DISCARD_NAL) {
9602 hevc_print(hevc, 0,
9603 "nal type %d, discard %d\n", naltype,
9604 slice_parse_begin);
9605 if (naltype <= NAL_UNIT_CODED_SLICE_CRA)
9606 slice_parse_begin--;
9607 }
9608 if (naltype == NAL_UNIT_EOS) {
9609 struct PIC_s *pic;
9610
9611 hevc_print(hevc, 0, "get NAL_UNIT_EOS, flush output\n");
9612#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9613 if ((vdec->master || vdec->slave) &&
9614 aux_data_is_avaible(hevc)) {
9615 if (hevc->decoding_pic)
9616 dolby_get_meta(hevc);
9617 }
9618#endif
9619 check_pic_decoded_error(hevc,
9620 hevc->pic_decoded_lcu_idx);
9621 pic = get_pic_by_POC(hevc, hevc->curr_POC);
9622 hevc->curr_POC = INVALID_POC;
9623 /* add to fix RAP_B_Bossen_1 */
9624 hevc->m_pocRandomAccess = MAX_INT;
9625 flush_output(hevc, pic);
9626 clear_poc_flag(hevc);
9627 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_DISCARD_NAL);
9628 /* Interrupt Amrisc to excute */
9629 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9630#ifdef MULTI_INSTANCE_SUPPORT
9631 if (hevc->m_ins_flag) {
9632 hevc->decoded_poc = INVALID_POC; /*
9633 already call flush_output*/
9634 hevc->decoding_pic = NULL;
9635 hevc->dec_result = DEC_RESULT_DONE;
9636 amhevc_stop();
9637
9638 vdec_schedule_work(&hevc->work);
9639 }
9640#endif
9641 return IRQ_HANDLED;
9642 }
9643
9644 if (
9645#ifdef MULTI_INSTANCE_SUPPORT
9646 (!hevc->m_ins_flag) &&
9647#endif
9648 hevc->error_skip_nal_count > 0) {
9649 hevc_print(hevc, 0,
9650 "nal type %d, discard %d\n", naltype,
9651 hevc->error_skip_nal_count);
9652 hevc->error_skip_nal_count--;
9653 if (hevc->error_skip_nal_count == 0) {
9654 hevc_recover(hevc);
9655 hevc->error_flag = 0;
9656 if ((error_handle_policy & 0x2) == 0) {
9657 hevc->have_vps = 1;
9658 hevc->have_sps = 1;
9659 hevc->have_pps = 1;
9660 }
9661 return IRQ_HANDLED;
9662 }
9663 } else if (naltype == NAL_UNIT_VPS) {
9664 parse_type = HEVC_NAL_UNIT_VPS;
9665 hevc->have_vps = 1;
9666#ifdef ERROR_HANDLE_DEBUG
9667 if (dbg_nal_skip_flag & 1)
9668 parse_type = HEVC_DISCARD_NAL;
9669#endif
9670 } else if (hevc->have_vps) {
9671 if (naltype == NAL_UNIT_SPS) {
9672 parse_type = HEVC_NAL_UNIT_SPS;
9673 hevc->have_sps = 1;
9674#ifdef ERROR_HANDLE_DEBUG
9675 if (dbg_nal_skip_flag & 2)
9676 parse_type = HEVC_DISCARD_NAL;
9677#endif
9678 } else if (naltype == NAL_UNIT_PPS) {
9679 parse_type = HEVC_NAL_UNIT_PPS;
9680 hevc->have_pps = 1;
9681#ifdef ERROR_HANDLE_DEBUG
9682 if (dbg_nal_skip_flag & 4)
9683 parse_type = HEVC_DISCARD_NAL;
9684#endif
9685 } else if (hevc->have_sps && hevc->have_pps) {
9686 int seg = HEVC_NAL_UNIT_CODED_SLICE_SEGMENT;
9687
9688 if ((naltype == NAL_UNIT_CODED_SLICE_IDR) ||
9689 (naltype ==
9690 NAL_UNIT_CODED_SLICE_IDR_N_LP)
9691 || (naltype ==
9692 NAL_UNIT_CODED_SLICE_CRA)
9693 || (naltype ==
9694 NAL_UNIT_CODED_SLICE_BLA)
9695 || (naltype ==
9696 NAL_UNIT_CODED_SLICE_BLANT)
9697 || (naltype ==
9698 NAL_UNIT_CODED_SLICE_BLA_N_LP)
9699 ) {
9700 if (slice_parse_begin > 0) {
9701 hevc_print(hevc, 0,
9702 "discard %d, for debugging\n",
9703 slice_parse_begin);
9704 slice_parse_begin--;
9705 } else {
9706 parse_type = seg;
9707 }
9708 hevc->have_valid_start_slice = 1;
9709 } else if (naltype <=
9710 NAL_UNIT_CODED_SLICE_CRA
9711 && (hevc->have_valid_start_slice
9712 || (hevc->PB_skip_mode != 3))) {
9713 if (slice_parse_begin > 0) {
9714 hevc_print(hevc, 0,
9715 "discard %d, dd\n",
9716 slice_parse_begin);
9717 slice_parse_begin--;
9718 } else
9719 parse_type = seg;
9720
9721 }
9722 }
9723 }
9724 if (hevc->have_vps && hevc->have_sps && hevc->have_pps
9725 && hevc->have_valid_start_slice &&
9726 hevc->error_flag == 0) {
9727 if ((get_dbg_flag(hevc) &
9728 H265_DEBUG_MAN_SEARCH_NAL) == 0
9729 /* && (!hevc->m_ins_flag)*/) {
9730 /* auot parser NAL; do not check
9731 *vps/sps/pps/idr
9732 */
9733 WRITE_VREG(NAL_SEARCH_CTL, 0x2);
9734 }
9735
9736 if ((get_dbg_flag(hevc) &
9737 H265_DEBUG_NO_EOS_SEARCH_DONE)
9738#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9739 || vdec->master
9740 || vdec->slave
9741#endif
9742 ) {
9743 WRITE_VREG(NAL_SEARCH_CTL,
9744 READ_VREG(NAL_SEARCH_CTL) |
9745 0x10000);
9746 }
9747 WRITE_VREG(NAL_SEARCH_CTL,
9748 READ_VREG(NAL_SEARCH_CTL)
9749 | ((parser_sei_enable & 0x7) << 17));
9750#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9751 WRITE_VREG(NAL_SEARCH_CTL,
9752 READ_VREG(NAL_SEARCH_CTL) |
9753 ((parser_dolby_vision_enable & 0x1) << 20));
9754#endif
9755 config_decode_mode(hevc);
9756 }
9757
9758 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
9759 hevc_print(hevc, 0,
9760 "naltype = %d parse_type %d\n %d %d %d %d\n",
9761 naltype, parse_type, hevc->have_vps,
9762 hevc->have_sps, hevc->have_pps,
9763 hevc->have_valid_start_slice);
9764 }
9765
9766 WRITE_VREG(HEVC_DEC_STATUS_REG, parse_type);
9767 /* Interrupt Amrisc to excute */
9768 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9769#ifdef MULTI_INSTANCE_SUPPORT
9770 if (hevc->m_ins_flag)
9771 start_process_time(hevc);
9772#endif
9773 } else if (dec_status == HEVC_SLICE_SEGMENT_DONE) {
9774#ifdef MULTI_INSTANCE_SUPPORT
9775 if (hevc->m_ins_flag) {
9776 reset_process_time(hevc);
9777 read_decode_info(hevc);
9778
9779 }
9780#endif
9781 if (hevc->start_decoding_time > 0) {
9782 u32 process_time = 1000*
9783 (jiffies - hevc->start_decoding_time)/HZ;
9784 if (process_time > max_decoding_time)
9785 max_decoding_time = process_time;
9786 }
9787
9788 hevc->error_watchdog_count = 0;
9789 if (hevc->pic_list_init_flag == 2) {
9790 hevc->pic_list_init_flag = 3;
9791 hevc_print(hevc, 0, "set pic_list_init_flag to 3\n");
9792 } else if (hevc->wait_buf == 0) {
9793 u32 vui_time_scale;
9794 u32 vui_num_units_in_tick;
9795 unsigned char reconfig_flag = 0;
9796
9797 if (get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG)
9798 get_rpm_param(&hevc->param);
9799 else {
9800
9801 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
9802 int ii;
9803
9804 for (ii = 0; ii < 4; ii++) {
9805 hevc->param.l.data[i + ii] =
9806 hevc->rpm_ptr[i + 3
9807 - ii];
9808 }
9809 }
9810#ifdef SEND_LMEM_WITH_RPM
9811 check_head_error(hevc);
9812#endif
9813 }
9814 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) {
9815 hevc_print(hevc, 0,
9816 "rpm_param: (%d)\n", hevc->slice_idx);
9817 hevc->slice_idx++;
9818 for (i = 0; i < (RPM_END - RPM_BEGIN); i++) {
9819 hevc_print_cont(hevc, 0,
9820 "%04x ", hevc->param.l.data[i]);
9821 if (((i + 1) & 0xf) == 0)
9822 hevc_print_cont(hevc, 0, "\n");
9823 }
9824
9825 hevc_print(hevc, 0,
9826 "vui_timing_info: %x, %x, %x, %x\n",
9827 hevc->param.p.vui_num_units_in_tick_hi,
9828 hevc->param.p.vui_num_units_in_tick_lo,
9829 hevc->param.p.vui_time_scale_hi,
9830 hevc->param.p.vui_time_scale_lo);
9831 }
9832
9833 if (hevc->is_used_v4l) {
9834 struct aml_vcodec_ctx *ctx =
9835 (struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
9836
9837 if (ctx->param_sets_from_ucode && !hevc->v4l_params_parsed) {
9838 struct aml_vdec_pic_infos info;
9839
9840 hevc->frame_width = hevc->param.p.pic_width_in_luma_samples;
9841 hevc->frame_height = hevc->param.p.pic_height_in_luma_samples;
9842 info.visible_width = hevc->frame_width;
9843 info.visible_height = hevc->frame_height;
9844 info.coded_width = ALIGN(hevc->frame_width, 32);
9845 info.coded_height = ALIGN(hevc->frame_height, 32);
9846 info.dpb_size = get_work_pic_num(hevc);
9847 hevc->v4l_params_parsed = true;
9848 /*notice the v4l2 codec.*/
9849 vdec_v4l_set_pic_infos(ctx, &info);
9850 }
9851 }
9852
9853 if (
9854#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9855 vdec->master == NULL &&
9856 vdec->slave == NULL &&
9857#endif
9858 aux_data_is_avaible(hevc)
9859 ) {
9860
9861 if (get_dbg_flag(hevc) &
9862 H265_DEBUG_BUFMGR_MORE)
9863 dump_aux_buf(hevc);
9864 }
9865
9866 vui_time_scale =
9867 (u32)(hevc->param.p.vui_time_scale_hi << 16) |
9868 hevc->param.p.vui_time_scale_lo;
9869 vui_num_units_in_tick =
9870 (u32)(hevc->param.
9871 p.vui_num_units_in_tick_hi << 16) |
9872 hevc->param.
9873 p.vui_num_units_in_tick_lo;
9874 if (hevc->bit_depth_luma !=
9875 ((hevc->param.p.bit_depth & 0xf) + 8)) {
9876 reconfig_flag = 1;
9877 hevc_print(hevc, 0, "Bit depth luma = %d\n",
9878 (hevc->param.p.bit_depth & 0xf) + 8);
9879 }
9880 if (hevc->bit_depth_chroma !=
9881 (((hevc->param.p.bit_depth >> 4) & 0xf) + 8)) {
9882 reconfig_flag = 1;
9883 hevc_print(hevc, 0, "Bit depth chroma = %d\n",
9884 ((hevc->param.p.bit_depth >> 4) &
9885 0xf) + 8);
9886 }
9887 hevc->bit_depth_luma =
9888 (hevc->param.p.bit_depth & 0xf) + 8;
9889 hevc->bit_depth_chroma =
9890 ((hevc->param.p.bit_depth >> 4) & 0xf) + 8;
9891 bit_depth_luma = hevc->bit_depth_luma;
9892 bit_depth_chroma = hevc->bit_depth_chroma;
9893#ifdef SUPPORT_10BIT
9894 if (hevc->bit_depth_luma == 8 &&
9895 hevc->bit_depth_chroma == 8 &&
9896 enable_mem_saving)
9897 hevc->mem_saving_mode = 1;
9898 else
9899 hevc->mem_saving_mode = 0;
9900#endif
9901 if (reconfig_flag &&
9902 (get_double_write_mode(hevc) & 0x10) == 0)
9903 init_decode_head_hw(hevc);
9904
9905 if ((vui_time_scale != 0)
9906 && (vui_num_units_in_tick != 0)) {
9907 hevc->frame_dur =
9908 div_u64(96000ULL *
9909 vui_num_units_in_tick,
9910 vui_time_scale);
9911 if (hevc->get_frame_dur != true)
9912 vdec_schedule_work(
9913 &hevc->notify_work);
9914
9915 hevc->get_frame_dur = true;
9916#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
9917 gvs->frame_dur = hevc->frame_dur;
9918#endif
9919 }
9920
9921 if (hevc->video_signal_type !=
9922 ((hevc->param.p.video_signal_type << 16)
9923 | hevc->param.p.color_description)) {
9924 u32 v = hevc->param.p.video_signal_type;
9925 u32 c = hevc->param.p.color_description;
9926#if 0
9927 if (v & 0x2000) {
9928 hevc_print(hevc, 0,
9929 "video_signal_type present:\n");
9930 hevc_print(hevc, 0, " %s %s\n",
9931 video_format_names[(v >> 10) & 7],
9932 ((v >> 9) & 1) ?
9933 "full_range" : "limited");
9934 if (v & 0x100) {
9935 hevc_print(hevc, 0,
9936 " color_description present:\n");
9937 hevc_print(hevc, 0,
9938 " color_primarie = %s\n",
9939 color_primaries_names
9940 [v & 0xff]);
9941 hevc_print(hevc, 0,
9942 " transfer_characteristic = %s\n",
9943 transfer_characteristics_names
9944 [(c >> 8) & 0xff]);
9945 hevc_print(hevc, 0,
9946 " matrix_coefficient = %s\n",
9947 matrix_coeffs_names[c & 0xff]);
9948 }
9949 }
9950#endif
9951 hevc->video_signal_type = (v << 16) | c;
9952 video_signal_type = hevc->video_signal_type;
9953 }
9954
9955 if (use_cma &&
9956 (hevc->param.p.slice_segment_address == 0)
9957 && (hevc->pic_list_init_flag == 0)) {
9958 int log = hevc->param.p.log2_min_coding_block_size_minus3;
9959 int log_s = hevc->param.p.log2_diff_max_min_coding_block_size;
9960
9961 hevc->pic_w = hevc->param.p.pic_width_in_luma_samples;
9962 hevc->pic_h = hevc->param.p.pic_height_in_luma_samples;
9963 hevc->lcu_size = 1 << (log + 3 + log_s);
9964 hevc->lcu_size_log2 = log2i(hevc->lcu_size);
9965 if (hevc->pic_w == 0 || hevc->pic_h == 0
9966 || hevc->lcu_size == 0
9967 || is_oversize(hevc->pic_w, hevc->pic_h)
9968 || (!hevc->skip_first_nal &&
9969 (hevc->pic_h == 96) && (hevc->pic_w == 160))) {
9970 /* skip search next start code */
9971 WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG)
9972 & (~0x2));
9973 if ( !hevc->skip_first_nal &&
9974 (hevc->pic_h == 96) && (hevc->pic_w == 160))
9975 hevc->skip_first_nal = 1;
9976 hevc->skip_flag = 1;
9977 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9978 /* Interrupt Amrisc to excute */
9979 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9980#ifdef MULTI_INSTANCE_SUPPORT
9981 if (hevc->m_ins_flag)
9982 start_process_time(hevc);
9983#endif
9984 } else {
9985 hevc->sps_num_reorder_pics_0 =
9986 hevc->param.p.sps_num_reorder_pics_0;
9987 hevc->pic_list_init_flag = 1;
9988#ifdef MULTI_INSTANCE_SUPPORT
9989 if (hevc->m_ins_flag) {
9990 vdec_schedule_work(&hevc->work);
9991 } else
9992#endif
9993 up(&h265_sema);
9994 hevc_print(hevc, 0, "set pic_list_init_flag 1\n");
9995 }
9996 return IRQ_HANDLED;
9997 }
9998
9999}
10000 ret =
10001 hevc_slice_segment_header_process(hevc,
10002 &hevc->param, decode_pic_begin);
10003 if (ret < 0) {
10004#ifdef MULTI_INSTANCE_SUPPORT
10005 if (hevc->m_ins_flag) {
10006 hevc->wait_buf = 0;
10007 hevc->dec_result = DEC_RESULT_AGAIN;
10008 amhevc_stop();
10009 restore_decode_state(hevc);
10010 reset_process_time(hevc);
10011 vdec_schedule_work(&hevc->work);
10012 return IRQ_HANDLED;
10013 }
10014#else
10015 ;
10016#endif
10017 } else if (ret == 0) {
10018 if ((hevc->new_pic) && (hevc->cur_pic)) {
10019 hevc->cur_pic->stream_offset =
10020 READ_VREG(HEVC_SHIFT_BYTE_COUNT);
10021 hevc_print(hevc, H265_DEBUG_OUT_PTS,
10022 "read stream_offset = 0x%x\n",
10023 hevc->cur_pic->stream_offset);
10024 hevc->cur_pic->aspect_ratio_idc =
10025 hevc->param.p.aspect_ratio_idc;
10026 hevc->cur_pic->sar_width =
10027 hevc->param.p.sar_width;
10028 hevc->cur_pic->sar_height =
10029 hevc->param.p.sar_height;
10030 }
10031
10032 WRITE_VREG(HEVC_DEC_STATUS_REG,
10033 HEVC_CODED_SLICE_SEGMENT_DAT);
10034 /* Interrupt Amrisc to excute */
10035 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
10036
10037 hevc->start_decoding_time = jiffies;
10038#ifdef MULTI_INSTANCE_SUPPORT
10039 if (hevc->m_ins_flag)
10040 start_process_time(hevc);
10041#endif
10042#if 1
10043 /*to do..., copy aux data to hevc->cur_pic*/
10044#endif
10045#ifdef MULTI_INSTANCE_SUPPORT
10046 } else if (hevc->m_ins_flag) {
10047 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
10048 "%s, bufmgr ret %d skip, DEC_RESULT_DONE\n",
10049 __func__, ret);
10050 hevc->decoded_poc = INVALID_POC;
10051 hevc->decoding_pic = NULL;
10052 hevc->dec_result = DEC_RESULT_DONE;
10053 amhevc_stop();
10054 reset_process_time(hevc);
10055 vdec_schedule_work(&hevc->work);
10056#endif
10057 } else {
10058 /* skip, search next start code */
10059#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10060 gvs->drop_frame_count++;
10061#endif
10062 WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) & (~0x2));
10063 hevc->skip_flag = 1;
10064 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10065 /* Interrupt Amrisc to excute */
10066 WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
10067 }
10068
10069 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
10070 hevc_print(hevc, 0 , "hevc decode oversize !!\n");
10071#ifdef MULTI_INSTANCE_SUPPORT
10072 if (!hevc->m_ins_flag)
10073 debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC |
10074 H265_DEBUG_DIS_SYS_ERROR_PROC);
10075#endif
10076 hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
10077 }
10078 return IRQ_HANDLED;
10079}
10080
10081static void wait_hevc_search_done(struct hevc_state_s *hevc)
10082{
10083 int count = 0;
10084 WRITE_VREG(HEVC_SHIFT_STATUS, 0);
10085 while (READ_VREG(HEVC_STREAM_CONTROL) & 0x2) {
10086 msleep(20);
10087 count++;
10088 if (count > 100) {
10089 hevc_print(hevc, 0, "%s timeout\n", __func__);
10090 break;
10091 }
10092 }
10093}
10094static irqreturn_t vh265_isr(int irq, void *data)
10095{
10096 int i, temp;
10097 unsigned int dec_status;
10098 struct hevc_state_s *hevc = (struct hevc_state_s *)data;
10099 u32 debug_tag;
10100 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
10101
10102 if (hevc->init_flag == 0)
10103 return IRQ_HANDLED;
10104 hevc->dec_status = dec_status;
10105 if (is_log_enable(hevc))
10106 add_log(hevc,
10107 "isr: status = 0x%x dec info 0x%x lcu 0x%x shiftbyte 0x%x shiftstatus 0x%x",
10108 dec_status, READ_HREG(HEVC_DECODE_INFO),
10109 READ_VREG(HEVC_MPRED_CURR_LCU),
10110 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
10111 READ_VREG(HEVC_SHIFT_STATUS));
10112
10113 if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
10114 hevc_print(hevc, 0,
10115 "265 isr dec status = 0x%x dec info 0x%x shiftbyte 0x%x shiftstatus 0x%x\n",
10116 dec_status, READ_HREG(HEVC_DECODE_INFO),
10117 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
10118 READ_VREG(HEVC_SHIFT_STATUS));
10119
10120 debug_tag = READ_HREG(DEBUG_REG1);
10121 if (debug_tag & 0x10000) {
10122 hevc_print(hevc, 0,
10123 "LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
10124
10125 if (hevc->mmu_enable)
10126 temp = 0x500;
10127 else
10128 temp = 0x400;
10129 for (i = 0; i < temp; i += 4) {
10130 int ii;
10131 if ((i & 0xf) == 0)
10132 hevc_print_cont(hevc, 0, "%03x: ", i);
10133 for (ii = 0; ii < 4; ii++) {
10134 hevc_print_cont(hevc, 0, "%04x ",
10135 hevc->lmem_ptr[i + 3 - ii]);
10136 }
10137 if (((i + ii) & 0xf) == 0)
10138 hevc_print_cont(hevc, 0, "\n");
10139 }
10140
10141 if (((udebug_pause_pos & 0xffff)
10142 == (debug_tag & 0xffff)) &&
10143 (udebug_pause_decode_idx == 0 ||
10144 udebug_pause_decode_idx == hevc->decode_idx) &&
10145 (udebug_pause_val == 0 ||
10146 udebug_pause_val == READ_HREG(DEBUG_REG2))) {
10147 udebug_pause_pos &= 0xffff;
10148 hevc->ucode_pause_pos = udebug_pause_pos;
10149 }
10150 else if (debug_tag & 0x20000)
10151 hevc->ucode_pause_pos = 0xffffffff;
10152 if (hevc->ucode_pause_pos)
10153 reset_process_time(hevc);
10154 else
10155 WRITE_HREG(DEBUG_REG1, 0);
10156 } else if (debug_tag != 0) {
10157 hevc_print(hevc, 0,
10158 "dbg%x: %x l/w/r %x %x %x\n", READ_HREG(DEBUG_REG1),
10159 READ_HREG(DEBUG_REG2),
10160 READ_VREG(HEVC_STREAM_LEVEL),
10161 READ_VREG(HEVC_STREAM_WR_PTR),
10162 READ_VREG(HEVC_STREAM_RD_PTR));
10163 if (((udebug_pause_pos & 0xffff)
10164 == (debug_tag & 0xffff)) &&
10165 (udebug_pause_decode_idx == 0 ||
10166 udebug_pause_decode_idx == hevc->decode_idx) &&
10167 (udebug_pause_val == 0 ||
10168 udebug_pause_val == READ_HREG(DEBUG_REG2))) {
10169 udebug_pause_pos &= 0xffff;
10170 hevc->ucode_pause_pos = udebug_pause_pos;
10171 }
10172 if (hevc->ucode_pause_pos)
10173 reset_process_time(hevc);
10174 else
10175 WRITE_HREG(DEBUG_REG1, 0);
10176 return IRQ_HANDLED;
10177 }
10178
10179
10180 if (hevc->pic_list_init_flag == 1)
10181 return IRQ_HANDLED;
10182
10183 if (!hevc->m_ins_flag) {
10184 if (dec_status == HEVC_OVER_DECODE) {
10185 hevc->over_decode = 1;
10186 hevc_print(hevc, 0,
10187 "isr: over decode\n"),
10188 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
10189 return IRQ_HANDLED;
10190 }
10191 }
10192
10193 return IRQ_WAKE_THREAD;
10194
10195}
10196
10197static void vh265_set_clk(struct work_struct *work)
10198{
10199 struct hevc_state_s *hevc = container_of(work,
10200 struct hevc_state_s, set_clk_work);
10201
10202 int fps = 96000 / hevc->frame_dur;
10203
10204 if (hevc_source_changed(VFORMAT_HEVC,
10205 hevc->frame_width, hevc->frame_height, fps) > 0)
10206 hevc->saved_resolution = hevc->frame_width *
10207 hevc->frame_height * fps;
10208}
10209
10210static void vh265_check_timer_func(unsigned long arg)
10211{
10212 struct hevc_state_s *hevc = (struct hevc_state_s *)arg;
10213 struct timer_list *timer = &hevc->timer;
10214 unsigned char empty_flag;
10215 unsigned int buf_level;
10216
10217 enum receviver_start_e state = RECEIVER_INACTIVE;
10218
10219 if (hevc->init_flag == 0) {
10220 if (hevc->stat & STAT_TIMER_ARM) {
10221 mod_timer(&hevc->timer, jiffies + PUT_INTERVAL);
10222 }
10223 return;
10224 }
10225#ifdef MULTI_INSTANCE_SUPPORT
10226 if (hevc->m_ins_flag &&
10227 (get_dbg_flag(hevc) &
10228 H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP) == 0 &&
10229 hw_to_vdec(hevc)->next_status ==
10230 VDEC_STATUS_DISCONNECTED) {
10231 hevc->dec_result = DEC_RESULT_FORCE_EXIT;
10232 vdec_schedule_work(&hevc->work);
10233 hevc_print(hevc,
10234 0, "vdec requested to be disconnected\n");
10235 return;
10236 }
10237
10238 if (hevc->m_ins_flag) {
10239 if ((input_frame_based(hw_to_vdec(hevc)) ||
10240 (READ_VREG(HEVC_STREAM_LEVEL) > 0xb0)) &&
10241 ((get_dbg_flag(hevc) &
10242 H265_DEBUG_DIS_LOC_ERROR_PROC) == 0) &&
10243 (decode_timeout_val > 0) &&
10244 (hevc->start_process_time > 0) &&
10245 ((1000 * (jiffies - hevc->start_process_time) / HZ)
10246 > decode_timeout_val)
10247 ) {
10248 u32 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
10249 int current_lcu_idx =
10250 READ_VREG(HEVC_PARSER_LCU_START)&0xffffff;
10251 if (dec_status == HEVC_CODED_SLICE_SEGMENT_DAT) {
10252 if (hevc->last_lcu_idx == current_lcu_idx) {
10253 if (hevc->decode_timeout_count > 0)
10254 hevc->decode_timeout_count--;
10255 if (hevc->decode_timeout_count == 0)
10256 timeout_process(hevc);
10257 } else
10258 restart_process_time(hevc);
10259 hevc->last_lcu_idx = current_lcu_idx;
10260 } else {
10261 hevc->pic_decoded_lcu_idx = current_lcu_idx;
10262 timeout_process(hevc);
10263 }
10264 }
10265 } else {
10266#endif
10267 if (hevc->m_ins_flag == 0 &&
10268 vf_get_receiver(hevc->provider_name)) {
10269 state =
10270 vf_notify_receiver(hevc->provider_name,
10271 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10272 NULL);
10273 if ((state == RECEIVER_STATE_NULL)
10274 || (state == RECEIVER_STATE_NONE))
10275 state = RECEIVER_INACTIVE;
10276 } else
10277 state = RECEIVER_INACTIVE;
10278
10279 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
10280 /* error watchdog */
10281 if (hevc->m_ins_flag == 0 &&
10282 (empty_flag == 0)
10283 && (hevc->pic_list_init_flag == 0
10284 || hevc->pic_list_init_flag
10285 == 3)) {
10286 /* decoder has input */
10287 if ((get_dbg_flag(hevc) &
10288 H265_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
10289
10290 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
10291 /* receiver has no buffer to recycle */
10292 if ((state == RECEIVER_INACTIVE) &&
10293 (kfifo_is_empty(&hevc->display_q) &&
10294 buf_level > 0x200)
10295 ) {
10296 if (hevc->error_flag == 0) {
10297 hevc->error_watchdog_count++;
10298 if (hevc->error_watchdog_count ==
10299 error_handle_threshold) {
10300 hevc_print(hevc, 0,
10301 "H265 dec err local reset.\n");
10302 hevc->error_flag = 1;
10303 hevc->error_watchdog_count = 0;
10304 hevc->error_skip_nal_wt_cnt = 0;
10305 hevc->
10306 error_system_watchdog_count++;
10307 WRITE_VREG
10308 (HEVC_ASSIST_MBOX0_IRQ_REG,
10309 0x1);
10310 }
10311 } else if (hevc->error_flag == 2) {
10312 int th =
10313 error_handle_nal_skip_threshold;
10314 hevc->error_skip_nal_wt_cnt++;
10315 if (hevc->error_skip_nal_wt_cnt
10316 == th) {
10317 hevc->error_flag = 3;
10318 hevc->error_watchdog_count = 0;
10319 hevc->
10320 error_skip_nal_wt_cnt = 0;
10321 WRITE_VREG
10322 (HEVC_ASSIST_MBOX0_IRQ_REG,
10323 0x1);
10324 }
10325 }
10326 }
10327 }
10328
10329 if ((get_dbg_flag(hevc)
10330 & H265_DEBUG_DIS_SYS_ERROR_PROC) == 0)
10331 /* receiver has no buffer to recycle */
10332 if ((state == RECEIVER_INACTIVE) &&
10333 (kfifo_is_empty(&hevc->display_q))
10334 ) { /* no buffer to recycle */
10335 if ((get_dbg_flag(hevc) &
10336 H265_DEBUG_DIS_LOC_ERROR_PROC) !=
10337 0)
10338 hevc->error_system_watchdog_count++;
10339 if (hevc->error_system_watchdog_count ==
10340 error_handle_system_threshold) {
10341 /* and it lasts for a while */
10342 hevc_print(hevc, 0,
10343 "H265 dec fatal error watchdog.\n");
10344 hevc->
10345 error_system_watchdog_count = 0;
10346 hevc->fatal_error |= DECODER_FATAL_ERROR_UNKNOWN;
10347 }
10348 }
10349 } else {
10350 hevc->error_watchdog_count = 0;
10351 hevc->error_system_watchdog_count = 0;
10352 }
10353#ifdef MULTI_INSTANCE_SUPPORT
10354 }
10355#endif
10356 if ((hevc->ucode_pause_pos != 0) &&
10357 (hevc->ucode_pause_pos != 0xffffffff) &&
10358 udebug_pause_pos != hevc->ucode_pause_pos) {
10359 hevc->ucode_pause_pos = 0;
10360 WRITE_HREG(DEBUG_REG1, 0);
10361 }
10362
10363 if (get_dbg_flag(hevc) & H265_DEBUG_DUMP_PIC_LIST) {
10364 dump_pic_list(hevc);
10365 debug &= ~H265_DEBUG_DUMP_PIC_LIST;
10366 }
10367 if (get_dbg_flag(hevc) & H265_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
10368 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10369 debug &= ~H265_DEBUG_TRIG_SLICE_SEGMENT_PROC;
10370 }
10371#ifdef TEST_NO_BUF
10372 if (hevc->wait_buf)
10373 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10374#endif
10375 if (get_dbg_flag(hevc) & H265_DEBUG_HW_RESET) {
10376 hevc->error_skip_nal_count = error_skip_nal_count;
10377 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10378
10379 debug &= ~H265_DEBUG_HW_RESET;
10380 }
10381
10382#ifdef ERROR_HANDLE_DEBUG
10383 if ((dbg_nal_skip_count > 0) && ((dbg_nal_skip_count & 0x10000) != 0)) {
10384 hevc->error_skip_nal_count = dbg_nal_skip_count & 0xffff;
10385 dbg_nal_skip_count &= ~0x10000;
10386 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10387 }
10388#endif
10389
10390 if (radr != 0) {
10391 if (rval != 0) {
10392 WRITE_VREG(radr, rval);
10393 hevc_print(hevc, 0,
10394 "WRITE_VREG(%x,%x)\n", radr, rval);
10395 } else
10396 hevc_print(hevc, 0,
10397 "READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
10398 rval = 0;
10399 radr = 0;
10400 }
10401 if (dbg_cmd != 0) {
10402 if (dbg_cmd == 1) {
10403 u32 disp_laddr;
10404
10405 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
10406 get_double_write_mode(hevc) == 0) {
10407 disp_laddr =
10408 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
10409 } else {
10410 struct canvas_s cur_canvas;
10411
10412 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
10413 & 0xff), &cur_canvas);
10414 disp_laddr = cur_canvas.addr;
10415 }
10416 hevc_print(hevc, 0,
10417 "current displayed buffer address %x\r\n",
10418 disp_laddr);
10419 }
10420 dbg_cmd = 0;
10421 }
10422 /*don't changed at start.*/
10423 if (hevc->m_ins_flag == 0 &&
10424 hevc->get_frame_dur && hevc->show_frame_num > 60 &&
10425 hevc->frame_dur > 0 && hevc->saved_resolution !=
10426 hevc->frame_width * hevc->frame_height *
10427 (96000 / hevc->frame_dur))
10428 vdec_schedule_work(&hevc->set_clk_work);
10429
10430 mod_timer(timer, jiffies + PUT_INTERVAL);
10431}
10432
10433static int h265_task_handle(void *data)
10434{
10435 int ret = 0;
10436 struct hevc_state_s *hevc = (struct hevc_state_s *)data;
10437
10438 set_user_nice(current, -10);
10439 while (1) {
10440 if (use_cma == 0) {
10441 hevc_print(hevc, 0,
10442 "ERROR: use_cma can not be changed dynamically\n");
10443 }
10444 ret = down_interruptible(&h265_sema);
10445 if ((hevc->init_flag != 0) && (hevc->pic_list_init_flag == 1)) {
10446 init_pic_list(hevc);
10447 init_pic_list_hw(hevc);
10448 init_buf_spec(hevc);
10449 hevc->pic_list_init_flag = 2;
10450 hevc_print(hevc, 0, "set pic_list_init_flag to 2\n");
10451
10452 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10453
10454 }
10455
10456 if (hevc->uninit_list) {
10457 /*USE_BUF_BLOCK*/
10458 uninit_pic_list(hevc);
10459 hevc_print(hevc, 0, "uninit list\n");
10460 hevc->uninit_list = 0;
10461#ifdef USE_UNINIT_SEMA
10462 if (use_cma) {
10463 up(&hevc->h265_uninit_done_sema);
10464 while (!kthread_should_stop())
10465 msleep(1);
10466 break;
10467 }
10468#endif
10469 }
10470 }
10471
10472 return 0;
10473}
10474
10475void vh265_free_cmabuf(void)
10476{
10477 struct hevc_state_s *hevc = gHevc;
10478
10479 mutex_lock(&vh265_mutex);
10480
10481 if (hevc->init_flag) {
10482 mutex_unlock(&vh265_mutex);
10483 return;
10484 }
10485
10486 mutex_unlock(&vh265_mutex);
10487}
10488
10489#ifdef MULTI_INSTANCE_SUPPORT
10490int vh265_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
10491#else
10492int vh265_dec_status(struct vdec_info *vstatus)
10493#endif
10494{
10495#ifdef MULTI_INSTANCE_SUPPORT
10496 struct hevc_state_s *hevc =
10497 (struct hevc_state_s *)vdec->private;
10498#else
10499 struct hevc_state_s *hevc = gHevc;
10500#endif
10501 if (!hevc)
10502 return -1;
10503
10504 vstatus->frame_width = hevc->frame_width;
10505 vstatus->frame_height = hevc->frame_height;
10506 if (hevc->frame_dur != 0)
10507 vstatus->frame_rate = 96000 / hevc->frame_dur;
10508 else
10509 vstatus->frame_rate = -1;
10510 vstatus->error_count = 0;
10511 vstatus->status = hevc->stat | hevc->fatal_error;
10512#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10513 vstatus->bit_rate = gvs->bit_rate;
10514 vstatus->frame_dur = hevc->frame_dur;
10515 if (gvs) {
10516 vstatus->bit_rate = gvs->bit_rate;
10517 vstatus->frame_data = gvs->frame_data;
10518 vstatus->total_data = gvs->total_data;
10519 vstatus->frame_count = gvs->frame_count;
10520 vstatus->error_frame_count = gvs->error_frame_count;
10521 vstatus->drop_frame_count = gvs->drop_frame_count;
10522 vstatus->total_data = gvs->total_data;
10523 vstatus->samp_cnt = gvs->samp_cnt;
10524 vstatus->offset = gvs->offset;
10525 }
10526 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
10527 "%s", DRIVER_NAME);
10528#endif
10529 vstatus->ratio_control = hevc->ratio_control;
10530 return 0;
10531}
10532
10533int vh265_set_isreset(struct vdec_s *vdec, int isreset)
10534{
10535 is_reset = isreset;
10536 return 0;
10537}
10538
10539static int vh265_vdec_info_init(void)
10540{
10541 gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL);
10542 if (NULL == gvs) {
10543 pr_info("the struct of vdec status malloc failed.\n");
10544 return -ENOMEM;
10545 }
10546 return 0;
10547}
10548
10549#if 0
10550static void H265_DECODE_INIT(void)
10551{
10552 /* enable hevc clocks */
10553 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
10554 /* *************************************************************** */
10555 /* Power ON HEVC */
10556 /* *************************************************************** */
10557 /* Powerup HEVC */
10558 WRITE_VREG(P_AO_RTI_GEN_PWR_SLEEP0,
10559 READ_VREG(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
10560 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
10561 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
10562 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
10563 /* remove isolations */
10564 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
10565 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
10566
10567}
10568#endif
10569
10570static void config_decode_mode(struct hevc_state_s *hevc)
10571{
10572#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10573 struct vdec_s *vdec = hw_to_vdec(hevc);
10574#endif
10575 unsigned decode_mode;
10576 if (!hevc->m_ins_flag)
10577 decode_mode = DECODE_MODE_SINGLE;
10578 else if (vdec_frame_based(hw_to_vdec(hevc)))
10579 decode_mode =
10580 DECODE_MODE_MULTI_FRAMEBASE;
10581#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10582 else if (vdec->slave) {
10583 if (force_bypass_dvenl & 0x80000000)
10584 hevc->bypass_dvenl = force_bypass_dvenl & 0x1;
10585 else
10586 hevc->bypass_dvenl = hevc->bypass_dvenl_enable;
10587 if (dolby_meta_with_el && hevc->bypass_dvenl) {
10588 hevc->bypass_dvenl = 0;
10589 hevc_print(hevc, 0,
10590 "NOT support bypass_dvenl when meta_with_el\n");
10591 }
10592 if (hevc->bypass_dvenl)
10593 decode_mode =
10594 (hevc->start_parser_type << 8)
10595 | DECODE_MODE_MULTI_STREAMBASE;
10596 else
10597 decode_mode =
10598 (hevc->start_parser_type << 8)
10599 | DECODE_MODE_MULTI_DVBAL;
10600 } else if (vdec->master)
10601 decode_mode =
10602 (hevc->start_parser_type << 8)
10603 | DECODE_MODE_MULTI_DVENL;
10604#endif
10605 else
10606 decode_mode =
10607 DECODE_MODE_MULTI_STREAMBASE;
10608
10609 if (hevc->m_ins_flag)
10610 decode_mode |=
10611 (hevc->start_decoding_flag << 16);
10612 /* set MBX0 interrupt flag */
10613 decode_mode |= (0x80 << 24);
10614 WRITE_VREG(HEVC_DECODE_MODE, decode_mode);
10615 WRITE_VREG(HEVC_DECODE_MODE2,
10616 hevc->rps_set_id);
10617}
10618
10619static void vh265_prot_init(struct hevc_state_s *hevc)
10620{
10621#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10622 struct vdec_s *vdec = hw_to_vdec(hevc);
10623#endif
10624 /* H265_DECODE_INIT(); */
10625
10626 hevc_config_work_space_hw(hevc);
10627
10628 hevc_init_decoder_hw(hevc, 0, 0xffffffff);
10629
10630 WRITE_VREG(HEVC_WAIT_FLAG, 1);
10631
10632 /* WRITE_VREG(P_HEVC_MPSR, 1); */
10633
10634 /* clear mailbox interrupt */
10635 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
10636
10637 /* enable mailbox interrupt */
10638 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
10639
10640 /* disable PSCALE for hardware sharing */
10641 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
10642
10643 WRITE_VREG(DEBUG_REG1, 0x0 | (dump_nal << 8));
10644
10645 if ((get_dbg_flag(hevc) &
10646 (H265_DEBUG_MAN_SKIP_NAL |
10647 H265_DEBUG_MAN_SEARCH_NAL))
10648 /*||hevc->m_ins_flag*/
10649 ) {
10650 WRITE_VREG(NAL_SEARCH_CTL, 0x1); /* manual parser NAL */
10651 } else {
10652 /* check vps/sps/pps/i-slice in ucode */
10653 unsigned ctl_val = 0x8;
10654 if (hevc->PB_skip_mode == 0)
10655 ctl_val = 0x4; /* check vps/sps/pps only in ucode */
10656 else if (hevc->PB_skip_mode == 3)
10657 ctl_val = 0x0; /* check vps/sps/pps/idr in ucode */
10658 WRITE_VREG(NAL_SEARCH_CTL, ctl_val);
10659 }
10660 if ((get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE)
10661#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10662 || vdec->master
10663 || vdec->slave
10664#endif
10665 )
10666 WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x10000);
10667
10668 WRITE_VREG(NAL_SEARCH_CTL,
10669 READ_VREG(NAL_SEARCH_CTL)
10670 | ((parser_sei_enable & 0x7) << 17));
10671#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10672 WRITE_VREG(NAL_SEARCH_CTL,
10673 READ_VREG(NAL_SEARCH_CTL) |
10674 ((parser_dolby_vision_enable & 0x1) << 20));
10675#endif
10676 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
10677
10678 config_decode_mode(hevc);
10679 config_aux_buf(hevc);
10680#ifdef SWAP_HEVC_UCODE
10681 if (!tee_enabled() && hevc->is_swap &&
10682 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
10683 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->mc_dma_handle);
10684 /*pr_info("write swap buffer %x\n", (u32)(hevc->mc_dma_handle));*/
10685 }
10686#endif
10687#ifdef DETREFILL_ENABLE
10688 if (hevc->is_swap &&
10689 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
10690 WRITE_VREG(HEVC_SAO_DBG_MODE0, 0);
10691 WRITE_VREG(HEVC_SAO_DBG_MODE1, 0);
10692 }
10693#endif
10694}
10695
10696static int vh265_local_init(struct hevc_state_s *hevc)
10697{
10698 int i;
10699 int ret = -1;
10700
10701#ifdef DEBUG_PTS
10702 hevc->pts_missed = 0;
10703 hevc->pts_hit = 0;
10704#endif
10705
10706 hevc->saved_resolution = 0;
10707 hevc->get_frame_dur = false;
10708 hevc->frame_width = hevc->vh265_amstream_dec_info.width;
10709 hevc->frame_height = hevc->vh265_amstream_dec_info.height;
10710 if (is_oversize(hevc->frame_width, hevc->frame_height)) {
10711 pr_info("over size : %u x %u.\n",
10712 hevc->frame_width, hevc->frame_height);
10713 hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
10714 return ret;
10715 }
10716
10717 if (hevc->max_pic_w && hevc->max_pic_h) {
10718 hevc->is_4k = !(hevc->max_pic_w && hevc->max_pic_h) ||
10719 ((hevc->max_pic_w * hevc->max_pic_h) >
10720 1920 * 1088) ? true : false;
10721 } else {
10722 hevc->is_4k = !(hevc->frame_width && hevc->frame_height) ||
10723 ((hevc->frame_width * hevc->frame_height) >
10724 1920 * 1088) ? true : false;
10725 }
10726
10727 hevc->frame_dur =
10728 (hevc->vh265_amstream_dec_info.rate ==
10729 0) ? 3600 : hevc->vh265_amstream_dec_info.rate;
10730#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10731 gvs->frame_dur = hevc->frame_dur;
10732#endif
10733 if (hevc->frame_width && hevc->frame_height)
10734 hevc->frame_ar = hevc->frame_height * 0x100 / hevc->frame_width;
10735
10736 if (i_only_flag)
10737 hevc->i_only = i_only_flag & 0xff;
10738 else if ((unsigned long) hevc->vh265_amstream_dec_info.param
10739 & 0x08)
10740 hevc->i_only = 0x7;
10741 else
10742 hevc->i_only = 0x0;
10743 hevc->error_watchdog_count = 0;
10744 hevc->sei_present_flag = 0;
10745 pts_unstable = ((unsigned long)hevc->vh265_amstream_dec_info.param
10746 & 0x40) >> 6;
10747 hevc_print(hevc, 0,
10748 "h265:pts_unstable=%d\n", pts_unstable);
10749/*
10750 *TODO:FOR VERSION
10751 */
10752 hevc_print(hevc, 0,
10753 "h265: ver (%d,%d) decinfo: %dx%d rate=%d\n", h265_version,
10754 0, hevc->frame_width, hevc->frame_height, hevc->frame_dur);
10755
10756 if (hevc->frame_dur == 0)
10757 hevc->frame_dur = 96000 / 24;
10758
10759 INIT_KFIFO(hevc->display_q);
10760 INIT_KFIFO(hevc->newframe_q);
10761
10762
10763 for (i = 0; i < VF_POOL_SIZE; i++) {
10764 const struct vframe_s *vf = &hevc->vfpool[i];
10765
10766 hevc->vfpool[i].index = -1;
10767 kfifo_put(&hevc->newframe_q, vf);
10768 }
10769
10770
10771 ret = hevc_local_init(hevc);
10772
10773 return ret;
10774}
10775#ifdef MULTI_INSTANCE_SUPPORT
10776static s32 vh265_init(struct vdec_s *vdec)
10777{
10778 struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
10779#else
10780static s32 vh265_init(struct hevc_state_s *hevc)
10781{
10782
10783#endif
10784 int ret, size = -1;
10785 int fw_size = 0x1000 * 16;
10786 struct firmware_s *fw = NULL;
10787
10788 init_timer(&hevc->timer);
10789
10790 hevc->stat |= STAT_TIMER_INIT;
10791
10792 if (hevc->m_ins_flag) {
10793#ifdef USE_UNINIT_SEMA
10794 sema_init(&hevc->h265_uninit_done_sema, 0);
10795#endif
10796 INIT_WORK(&hevc->work, vh265_work);
10797 INIT_WORK(&hevc->timeout_work, vh265_timeout_work);
10798 }
10799
10800 if (vh265_local_init(hevc) < 0)
10801 return -EBUSY;
10802
10803 mutex_init(&hevc->chunks_mutex);
10804 INIT_WORK(&hevc->notify_work, vh265_notify_work);
10805 INIT_WORK(&hevc->set_clk_work, vh265_set_clk);
10806
10807 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
10808 if (IS_ERR_OR_NULL(fw))
10809 return -ENOMEM;
10810
10811 if (hevc->mmu_enable)
10812 if (get_cpu_major_id() > AM_MESON_CPU_MAJOR_ID_GXM)
10813 size = get_firmware_data(VIDEO_DEC_HEVC_MMU, fw->data);
10814 else {
10815 if (!hevc->is_4k) {
10816 /* if an older version of the fw was loaded, */
10817 /* needs try to load noswap fw because the */
10818 /* old fw package dose not contain the swap fw.*/
10819 size = get_firmware_data(
10820 VIDEO_DEC_HEVC_MMU_SWAP, fw->data);
10821 if (size < 0)
10822 size = get_firmware_data(
10823 VIDEO_DEC_HEVC_MMU, fw->data);
10824 else if (size)
10825 hevc->is_swap = true;
10826 } else
10827 size = get_firmware_data(VIDEO_DEC_HEVC_MMU,
10828 fw->data);
10829 }
10830 else
10831 size = get_firmware_data(VIDEO_DEC_HEVC, fw->data);
10832
10833 if (size < 0) {
10834 pr_err("get firmware fail.\n");
10835 vfree(fw);
10836 return -1;
10837 }
10838
10839 fw->len = size;
10840
10841#ifdef SWAP_HEVC_UCODE
10842 if (!tee_enabled() && hevc->is_swap &&
10843 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
10844 if (hevc->mmu_enable) {
10845 hevc->swap_size = (4 * (4 * SZ_1K)); /*max 4 swap code, each 0x400*/
10846 hevc->mc_cpu_addr =
10847 dma_alloc_coherent(amports_get_dma_device(),
10848 hevc->swap_size,
10849 &hevc->mc_dma_handle, GFP_KERNEL);
10850 if (!hevc->mc_cpu_addr) {
10851 amhevc_disable();
10852 pr_info("vh265 mmu swap ucode loaded fail.\n");
10853 return -ENOMEM;
10854 }
10855
10856 memcpy((u8 *) hevc->mc_cpu_addr, fw->data + SWAP_HEVC_OFFSET,
10857 hevc->swap_size);
10858
10859 hevc_print(hevc, 0,
10860 "vh265 mmu ucode swap loaded %x\n",
10861 hevc->mc_dma_handle);
10862 }
10863 }
10864#endif
10865
10866#ifdef MULTI_INSTANCE_SUPPORT
10867 if (hevc->m_ins_flag) {
10868 hevc->timer.data = (ulong) hevc;
10869 hevc->timer.function = vh265_check_timer_func;
10870 hevc->timer.expires = jiffies + PUT_INTERVAL;
10871
10872 hevc->fw = fw;
10873
10874 return 0;
10875 }
10876#endif
10877 amhevc_enable();
10878
10879 if (hevc->mmu_enable)
10880 if (get_cpu_major_id() > AM_MESON_CPU_MAJOR_ID_GXM)
10881 ret = amhevc_loadmc_ex(VFORMAT_HEVC, "h265_mmu", fw->data);
10882 else {
10883 if (!hevc->is_4k) {
10884 /* if an older version of the fw was loaded, */
10885 /* needs try to load noswap fw because the */
10886 /* old fw package dose not contain the swap fw. */
10887 ret = amhevc_loadmc_ex(VFORMAT_HEVC,
10888 "hevc_mmu_swap", fw->data);
10889 if (ret < 0)
10890 ret = amhevc_loadmc_ex(VFORMAT_HEVC,
10891 "h265_mmu", fw->data);
10892 else
10893 hevc->is_swap = true;
10894 } else
10895 ret = amhevc_loadmc_ex(VFORMAT_HEVC,
10896 "h265_mmu", fw->data);
10897 }
10898 else
10899 ret = amhevc_loadmc_ex(VFORMAT_HEVC, NULL, fw->data);
10900
10901 if (ret < 0) {
10902 amhevc_disable();
10903 vfree(fw);
10904 pr_err("H265: the %s fw loading failed, err: %x\n",
10905 tee_enabled() ? "TEE" : "local", ret);
10906 return -EBUSY;
10907 }
10908
10909 vfree(fw);
10910
10911 hevc->stat |= STAT_MC_LOAD;
10912
10913#ifdef DETREFILL_ENABLE
10914 if (hevc->is_swap &&
10915 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
10916 init_detrefill_buf(hevc);
10917#endif
10918 /* enable AMRISC side protocol */
10919 vh265_prot_init(hevc);
10920
10921 if (vdec_request_threaded_irq(VDEC_IRQ_0, vh265_isr,
10922 vh265_isr_thread_fn,
10923 IRQF_ONESHOT,/*run thread on this irq disabled*/
10924 "vh265-irq", (void *)hevc)) {
10925 hevc_print(hevc, 0, "vh265 irq register error.\n");
10926 amhevc_disable();
10927 return -ENOENT;
10928 }
10929
10930 hevc->stat |= STAT_ISR_REG;
10931 hevc->provider_name = PROVIDER_NAME;
10932
10933#ifdef MULTI_INSTANCE_SUPPORT
10934 vf_provider_init(&vh265_vf_prov, hevc->provider_name,
10935 &vh265_vf_provider, vdec);
10936 vf_reg_provider(&vh265_vf_prov);
10937 vf_notify_receiver(hevc->provider_name, VFRAME_EVENT_PROVIDER_START,
10938 NULL);
10939 if (hevc->frame_dur != 0) {
10940 if (!is_reset) {
10941 vf_notify_receiver(hevc->provider_name,
10942 VFRAME_EVENT_PROVIDER_FR_HINT,
10943 (void *)
10944 ((unsigned long)hevc->frame_dur));
10945 fr_hint_status = VDEC_HINTED;
10946 }
10947 } else
10948 fr_hint_status = VDEC_NEED_HINT;
10949#else
10950 vf_provider_init(&vh265_vf_prov, PROVIDER_NAME, &vh265_vf_provider,
10951 hevc);
10952 vf_reg_provider(&vh265_vf_prov);
10953 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
10954 if (hevc->frame_dur != 0) {
10955 vf_notify_receiver(PROVIDER_NAME,
10956 VFRAME_EVENT_PROVIDER_FR_HINT,
10957 (void *)
10958 ((unsigned long)hevc->frame_dur));
10959 fr_hint_status = VDEC_HINTED;
10960 } else
10961 fr_hint_status = VDEC_NEED_HINT;
10962#endif
10963 hevc->stat |= STAT_VF_HOOK;
10964
10965 hevc->timer.data = (ulong) hevc;
10966 hevc->timer.function = vh265_check_timer_func;
10967 hevc->timer.expires = jiffies + PUT_INTERVAL;
10968
10969 add_timer(&hevc->timer);
10970
10971 hevc->stat |= STAT_TIMER_ARM;
10972
10973 if (use_cma) {
10974#ifdef USE_UNINIT_SEMA
10975 sema_init(&hevc->h265_uninit_done_sema, 0);
10976#endif
10977 if (h265_task == NULL) {
10978 sema_init(&h265_sema, 1);
10979 h265_task =
10980 kthread_run(h265_task_handle, hevc,
10981 "kthread_h265");
10982 }
10983 }
10984 /* hevc->stat |= STAT_KTHREAD; */
10985#if 0
10986 if (get_dbg_flag(hevc) & H265_DEBUG_FORCE_CLK) {
10987 hevc_print(hevc, 0, "%s force clk\n", __func__);
10988 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL,
10989 READ_VREG(HEVC_IQIT_CLK_RST_CTRL) |
10990 ((1 << 2) | (1 << 1)));
10991 WRITE_VREG(HEVC_DBLK_CFG0,
10992 READ_VREG(HEVC_DBLK_CFG0) | ((1 << 2) |
10993 (1 << 1) | 0x3fff0000));/* 2,29:16 */
10994 WRITE_VREG(HEVC_SAO_CTRL1, READ_VREG(HEVC_SAO_CTRL1) |
10995 (1 << 2)); /* 2 */
10996 WRITE_VREG(HEVC_MPRED_CTRL1, READ_VREG(HEVC_MPRED_CTRL1) |
10997 (1 << 24)); /* 24 */
10998 WRITE_VREG(HEVC_STREAM_CONTROL,
10999 READ_VREG(HEVC_STREAM_CONTROL) |
11000 (1 << 15)); /* 15 */
11001 WRITE_VREG(HEVC_CABAC_CONTROL, READ_VREG(HEVC_CABAC_CONTROL) |
11002 (1 << 13)); /* 13 */
11003 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
11004 READ_VREG(HEVC_PARSER_CORE_CONTROL) |
11005 (1 << 15)); /* 15 */
11006 WRITE_VREG(HEVC_PARSER_INT_CONTROL,
11007 READ_VREG(HEVC_PARSER_INT_CONTROL) |
11008 (1 << 15)); /* 15 */
11009 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
11010 READ_VREG(HEVC_PARSER_IF_CONTROL) | ((1 << 6) |
11011 (1 << 3) | (1 << 1))); /* 6, 3, 1 */
11012 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, 0xffffffff); /* 31:0 */
11013 WRITE_VREG(HEVCD_MCRCC_CTL1, READ_VREG(HEVCD_MCRCC_CTL1) |
11014 (1 << 3)); /* 3 */
11015 }
11016#endif
11017#ifdef SWAP_HEVC_UCODE
11018 if (!tee_enabled() && hevc->is_swap &&
11019 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
11020 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->mc_dma_handle);
11021 /*pr_info("write swap buffer %x\n", (u32)(hevc->mc_dma_handle));*/
11022 }
11023#endif
11024
11025#ifndef MULTI_INSTANCE_SUPPORT
11026 set_vdec_func(&vh265_dec_status);
11027#endif
11028 amhevc_start();
11029 hevc->stat |= STAT_VDEC_RUN;
11030 hevc->init_flag = 1;
11031 error_handle_threshold = 30;
11032 /* pr_info("%d, vh265_init, RP=0x%x\n",
11033 * __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
11034 */
11035
11036 return 0;
11037}
11038
11039static int vh265_stop(struct hevc_state_s *hevc)
11040{
11041 if (get_dbg_flag(hevc) &
11042 H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP) {
11043 int wait_timeout_count = 0;
11044
11045 while (READ_VREG(HEVC_DEC_STATUS_REG) ==
11046 HEVC_CODED_SLICE_SEGMENT_DAT &&
11047 wait_timeout_count < 10){
11048 wait_timeout_count++;
11049 msleep(20);
11050 }
11051 }
11052 if (hevc->stat & STAT_VDEC_RUN) {
11053 amhevc_stop();
11054 hevc->stat &= ~STAT_VDEC_RUN;
11055 }
11056
11057 if (hevc->stat & STAT_ISR_REG) {
11058#ifdef MULTI_INSTANCE_SUPPORT
11059 if (!hevc->m_ins_flag)
11060#endif
11061 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
11062 vdec_free_irq(VDEC_IRQ_0, (void *)hevc);
11063 hevc->stat &= ~STAT_ISR_REG;
11064 }
11065
11066 hevc->stat &= ~STAT_TIMER_INIT;
11067 if (hevc->stat & STAT_TIMER_ARM) {
11068 del_timer_sync(&hevc->timer);
11069 hevc->stat &= ~STAT_TIMER_ARM;
11070 }
11071
11072 if (hevc->stat & STAT_VF_HOOK) {
11073 if (fr_hint_status == VDEC_HINTED) {
11074 vf_notify_receiver(hevc->provider_name,
11075 VFRAME_EVENT_PROVIDER_FR_END_HINT,
11076 NULL);
11077 }
11078 fr_hint_status = VDEC_NO_NEED_HINT;
11079 vf_unreg_provider(&vh265_vf_prov);
11080 hevc->stat &= ~STAT_VF_HOOK;
11081 }
11082
11083 hevc_local_uninit(hevc);
11084
11085 if (use_cma) {
11086 hevc->uninit_list = 1;
11087 up(&h265_sema);
11088#ifdef USE_UNINIT_SEMA
11089 down(&hevc->h265_uninit_done_sema);
11090 if (!IS_ERR(h265_task)) {
11091 kthread_stop(h265_task);
11092 h265_task = NULL;
11093 }
11094#else
11095 while (hevc->uninit_list) /* wait uninit complete */
11096 msleep(20);
11097#endif
11098
11099 }
11100 hevc->init_flag = 0;
11101 hevc->first_sc_checked = 0;
11102 cancel_work_sync(&hevc->notify_work);
11103 cancel_work_sync(&hevc->set_clk_work);
11104 uninit_mmu_buffers(hevc);
11105 amhevc_disable();
11106
11107 kfree(gvs);
11108 gvs = NULL;
11109
11110 return 0;
11111}
11112
11113#ifdef MULTI_INSTANCE_SUPPORT
11114static void reset_process_time(struct hevc_state_s *hevc)
11115{
11116 if (hevc->start_process_time) {
11117 unsigned int process_time =
11118 1000 * (jiffies - hevc->start_process_time) / HZ;
11119 hevc->start_process_time = 0;
11120 if (process_time > max_process_time[hevc->index])
11121 max_process_time[hevc->index] = process_time;
11122 }
11123}
11124
11125static void start_process_time(struct hevc_state_s *hevc)
11126{
11127 hevc->start_process_time = jiffies;
11128 hevc->decode_timeout_count = 2;
11129 hevc->last_lcu_idx = 0;
11130}
11131
11132static void restart_process_time(struct hevc_state_s *hevc)
11133{
11134 hevc->start_process_time = jiffies;
11135 hevc->decode_timeout_count = 2;
11136}
11137
11138static void timeout_process(struct hevc_state_s *hevc)
11139{
11140 /*
11141 * In this very timeout point,the vh265_work arrives,
11142 * let it to handle the scenario.
11143 */
11144 if (work_pending(&hevc->work))
11145 return;
11146
11147 hevc->timeout_num++;
11148 amhevc_stop();
11149 read_decode_info(hevc);
11150
11151 hevc_print(hevc,
11152 0, "%s decoder timeout\n", __func__);
11153 check_pic_decoded_error(hevc,
11154 hevc->pic_decoded_lcu_idx);
11155 hevc->decoded_poc = hevc->curr_POC;
11156 hevc->decoding_pic = NULL;
11157 hevc->dec_result = DEC_RESULT_DONE;
11158 reset_process_time(hevc);
11159
11160 if (work_pending(&hevc->work))
11161 return;
11162 vdec_schedule_work(&hevc->timeout_work);
11163}
11164
11165#ifdef CONSTRAIN_MAX_BUF_NUM
11166static int get_vf_ref_only_buf_count(struct hevc_state_s *hevc)
11167{
11168 struct PIC_s *pic;
11169 int i;
11170 int count = 0;
11171 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11172 pic = hevc->m_PIC[i];
11173 if (pic == NULL || pic->index == -1)
11174 continue;
11175 if (pic->output_mark == 0 && pic->referenced == 0
11176 && pic->output_ready == 1)
11177 count++;
11178 }
11179
11180 return count;
11181}
11182
11183static int get_used_buf_count(struct hevc_state_s *hevc)
11184{
11185 struct PIC_s *pic;
11186 int i;
11187 int count = 0;
11188 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11189 pic = hevc->m_PIC[i];
11190 if (pic == NULL || pic->index == -1)
11191 continue;
11192 if (pic->output_mark != 0 || pic->referenced != 0
11193 || pic->output_ready != 0)
11194 count++;
11195 }
11196
11197 return count;
11198}
11199#endif
11200
11201
11202static unsigned char is_new_pic_available(struct hevc_state_s *hevc)
11203{
11204 struct PIC_s *new_pic = NULL;
11205 struct PIC_s *pic;
11206 /* recycle un-used pic */
11207 int i;
11208 int ref_pic = 0;
11209 struct vdec_s *vdec = hw_to_vdec(hevc);
11210 /*return 1 if pic_list is not initialized yet*/
11211 if (hevc->pic_list_init_flag != 3)
11212 return 1;
11213
11214 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11215 pic = hevc->m_PIC[i];
11216 if (pic == NULL || pic->index == -1)
11217 continue;
11218 if (pic->referenced == 1)
11219 ref_pic++;
11220 if (pic->output_mark == 0 && pic->referenced == 0
11221 && pic->output_ready == 0
11222 ) {
11223 if (new_pic) {
11224 if (pic->POC < new_pic->POC)
11225 new_pic = pic;
11226 } else
11227 new_pic = pic;
11228 }
11229 }
11230
11231 if ((new_pic == NULL) &&
11232 (ref_pic >=
11233 get_work_pic_num(hevc) -
11234 hevc->sps_num_reorder_pics_0 - 1)) {
11235 enum receviver_start_e state = RECEIVER_INACTIVE;
11236 if (vf_get_receiver(vdec->vf_provider_name)) {
11237 state =
11238 vf_notify_receiver(vdec->vf_provider_name,
11239 VFRAME_EVENT_PROVIDER_QUREY_STATE,
11240 NULL);
11241 if ((state == RECEIVER_STATE_NULL)
11242 || (state == RECEIVER_STATE_NONE))
11243 state = RECEIVER_INACTIVE;
11244 }
11245 if (state == RECEIVER_INACTIVE) {
11246 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11247 pic = hevc->m_PIC[i];
11248 if (pic == NULL || pic->index == -1)
11249 continue;
11250
11251 if ((pic->referenced == 1) &&
11252 (pic->error_mark == 1)) {
11253 if (new_pic) {
11254 if (pic->POC < new_pic->POC)
11255 new_pic = pic;
11256 } else
11257 new_pic = pic;
11258 }
11259 }
11260 if (new_pic != NULL) {
11261 new_pic->referenced = 0;
11262 put_mv_buf(hevc, pic);
11263 if (pic_list_debug & 0x2)
11264 pr_err("err ref poc :%d\n", new_pic->POC);
11265 }
11266 }
11267 }
11268
11269 return (new_pic != NULL) ? 1 : 0;
11270}
11271
11272static int vmh265_stop(struct hevc_state_s *hevc)
11273{
11274 if (hevc->stat & STAT_TIMER_ARM) {
11275 del_timer_sync(&hevc->timer);
11276 hevc->stat &= ~STAT_TIMER_ARM;
11277 }
11278 if (hevc->stat & STAT_VDEC_RUN) {
11279 amhevc_stop();
11280 hevc->stat &= ~STAT_VDEC_RUN;
11281 }
11282 if (hevc->stat & STAT_ISR_REG) {
11283 vdec_free_irq(VDEC_IRQ_0, (void *)hevc);
11284 hevc->stat &= ~STAT_ISR_REG;
11285 }
11286
11287 if (hevc->stat & STAT_VF_HOOK) {
11288 if (fr_hint_status == VDEC_HINTED)
11289 vf_notify_receiver(hevc->provider_name,
11290 VFRAME_EVENT_PROVIDER_FR_END_HINT,
11291 NULL);
11292 fr_hint_status = VDEC_NO_NEED_HINT;
11293 vf_unreg_provider(&vh265_vf_prov);
11294 hevc->stat &= ~STAT_VF_HOOK;
11295 }
11296
11297 hevc_local_uninit(hevc);
11298
11299 if (use_cma) {
11300 hevc->uninit_list = 1;
11301 reset_process_time(hevc);
11302 hevc->dec_result = DEC_RESULT_FREE_CANVAS;
11303 vdec_schedule_work(&hevc->work);
11304 flush_work(&hevc->work);
11305#ifdef USE_UNINIT_SEMA
11306 if (hevc->init_flag) {
11307 down(&hevc->h265_uninit_done_sema);
11308 }
11309#else
11310 while (hevc->uninit_list) /* wait uninit complete */
11311 msleep(20);
11312#endif
11313 }
11314 hevc->init_flag = 0;
11315 hevc->first_sc_checked = 0;
11316 cancel_work_sync(&hevc->notify_work);
11317 cancel_work_sync(&hevc->set_clk_work);
11318 cancel_work_sync(&hevc->work);
11319 cancel_work_sync(&hevc->timeout_work);
11320 uninit_mmu_buffers(hevc);
11321
11322 vfree(hevc->fw);
11323 hevc->fw = NULL;
11324
11325 dump_log(hevc);
11326 return 0;
11327}
11328
11329static unsigned char get_data_check_sum
11330 (struct hevc_state_s *hevc, int size)
11331{
11332 int jj;
11333 int sum = 0;
11334 u8 *data = NULL;
11335
11336 if (!hevc->chunk->block->is_mapped)
11337 data = codec_mm_vmap(hevc->chunk->block->start +
11338 hevc->chunk->offset, size);
11339 else
11340 data = ((u8 *)hevc->chunk->block->start_virt) +
11341 hevc->chunk->offset;
11342
11343 for (jj = 0; jj < size; jj++)
11344 sum += data[jj];
11345
11346 if (!hevc->chunk->block->is_mapped)
11347 codec_mm_unmap_phyaddr(data);
11348 return sum;
11349}
11350
11351static void vh265_notify_work(struct work_struct *work)
11352{
11353 struct hevc_state_s *hevc =
11354 container_of(work,
11355 struct hevc_state_s,
11356 notify_work);
11357 struct vdec_s *vdec = hw_to_vdec(hevc);
11358#ifdef MULTI_INSTANCE_SUPPORT
11359 if (vdec->fr_hint_state == VDEC_NEED_HINT) {
11360 vf_notify_receiver(hevc->provider_name,
11361 VFRAME_EVENT_PROVIDER_FR_HINT,
11362 (void *)
11363 ((unsigned long)hevc->frame_dur));
11364 vdec->fr_hint_state = VDEC_HINTED;
11365 } else if (fr_hint_status == VDEC_NEED_HINT) {
11366 vf_notify_receiver(hevc->provider_name,
11367 VFRAME_EVENT_PROVIDER_FR_HINT,
11368 (void *)
11369 ((unsigned long)hevc->frame_dur));
11370 fr_hint_status = VDEC_HINTED;
11371 }
11372#else
11373 if (fr_hint_status == VDEC_NEED_HINT)
11374 vf_notify_receiver(PROVIDER_NAME,
11375 VFRAME_EVENT_PROVIDER_FR_HINT,
11376 (void *)
11377 ((unsigned long)hevc->frame_dur));
11378 fr_hint_status = VDEC_HINTED;
11379 }
11380#endif
11381
11382 return;
11383}
11384
11385static void vh265_work_implement(struct hevc_state_s *hevc,
11386 struct vdec_s *vdec,int from)
11387{
11388 if (hevc->dec_result == DEC_RESULT_FREE_CANVAS) {
11389 /*USE_BUF_BLOCK*/
11390 uninit_pic_list(hevc);
11391 hevc_print(hevc, 0, "uninit list\n");
11392 hevc->uninit_list = 0;
11393#ifdef USE_UNINIT_SEMA
11394 up(&hevc->h265_uninit_done_sema);
11395#endif
11396 return;
11397 }
11398
11399 /* finished decoding one frame or error,
11400 * notify vdec core to switch context
11401 */
11402 if (hevc->pic_list_init_flag == 1
11403 && (hevc->dec_result != DEC_RESULT_FORCE_EXIT)) {
11404 hevc->pic_list_init_flag = 2;
11405 init_pic_list(hevc);
11406 init_pic_list_hw(hevc);
11407 init_buf_spec(hevc);
11408 hevc_print(hevc, 0,
11409 "set pic_list_init_flag to 2\n");
11410
11411 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
11412 return;
11413 }
11414
11415 hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL,
11416 "%s dec_result %d %x %x %x\n",
11417 __func__,
11418 hevc->dec_result,
11419 READ_VREG(HEVC_STREAM_LEVEL),
11420 READ_VREG(HEVC_STREAM_WR_PTR),
11421 READ_VREG(HEVC_STREAM_RD_PTR));
11422
11423 if (((hevc->dec_result == DEC_RESULT_GET_DATA) ||
11424 (hevc->dec_result == DEC_RESULT_GET_DATA_RETRY))
11425 && (hw_to_vdec(hevc)->next_status !=
11426 VDEC_STATUS_DISCONNECTED)) {
11427 if (!vdec_has_more_input(vdec)) {
11428 hevc->dec_result = DEC_RESULT_EOS;
11429 vdec_schedule_work(&hevc->work);
11430 return;
11431 }
11432 if (!input_frame_based(vdec)) {
11433 int r = vdec_sync_input(vdec);
11434 if (r >= 0x200) {
11435 WRITE_VREG(HEVC_DECODE_SIZE,
11436 READ_VREG(HEVC_DECODE_SIZE) + r);
11437
11438 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11439 "%s DEC_RESULT_GET_DATA %x %x %x mpc %x size 0x%x\n",
11440 __func__,
11441 READ_VREG(HEVC_STREAM_LEVEL),
11442 READ_VREG(HEVC_STREAM_WR_PTR),
11443 READ_VREG(HEVC_STREAM_RD_PTR),
11444 READ_VREG(HEVC_MPC_E), r);
11445
11446 start_process_time(hevc);
11447 if (READ_VREG(HEVC_DEC_STATUS_REG)
11448 == HEVC_DECODE_BUFEMPTY2)
11449 WRITE_VREG(HEVC_DEC_STATUS_REG,
11450 HEVC_ACTION_DONE);
11451 else
11452 WRITE_VREG(HEVC_DEC_STATUS_REG,
11453 HEVC_ACTION_DEC_CONT);
11454 } else {
11455 hevc->dec_result = DEC_RESULT_GET_DATA_RETRY;
11456 vdec_schedule_work(&hevc->work);
11457 }
11458 return;
11459 }
11460
11461 /*below for frame_base*/
11462 if (hevc->dec_result == DEC_RESULT_GET_DATA) {
11463 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11464 "%s DEC_RESULT_GET_DATA %x %x %x mpc %x\n",
11465 __func__,
11466 READ_VREG(HEVC_STREAM_LEVEL),
11467 READ_VREG(HEVC_STREAM_WR_PTR),
11468 READ_VREG(HEVC_STREAM_RD_PTR),
11469 READ_VREG(HEVC_MPC_E));
11470 mutex_lock(&hevc->chunks_mutex);
11471 vdec_vframe_dirty(vdec, hevc->chunk);
11472 hevc->chunk = NULL;
11473 mutex_unlock(&hevc->chunks_mutex);
11474 vdec_clean_input(vdec);
11475 }
11476
11477 /*if (is_new_pic_available(hevc)) {*/
11478 if (run_ready(vdec, VDEC_HEVC)) {
11479 int r;
11480 int decode_size;
11481 r = vdec_prepare_input(vdec, &hevc->chunk);
11482 if (r < 0) {
11483 hevc->dec_result = DEC_RESULT_GET_DATA_RETRY;
11484
11485 hevc_print(hevc,
11486 PRINT_FLAG_VDEC_DETAIL,
11487 "amvdec_vh265: Insufficient data\n");
11488
11489 vdec_schedule_work(&hevc->work);
11490 return;
11491 }
11492 hevc->dec_result = DEC_RESULT_NONE;
11493 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11494 "%s: chunk size 0x%x sum 0x%x mpc %x\n",
11495 __func__, r,
11496 (get_dbg_flag(hevc) & PRINT_FLAG_VDEC_STATUS) ?
11497 get_data_check_sum(hevc, r) : 0,
11498 READ_VREG(HEVC_MPC_E));
11499
11500 if (get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) {
11501 int jj;
11502 u8 *data = NULL;
11503
11504 if (!hevc->chunk->block->is_mapped)
11505 data = codec_mm_vmap(
11506 hevc->chunk->block->start +
11507 hevc->chunk->offset, r);
11508 else
11509 data = ((u8 *)
11510 hevc->chunk->block->start_virt)
11511 + hevc->chunk->offset;
11512
11513 for (jj = 0; jj < r; jj++) {
11514 if ((jj & 0xf) == 0)
11515 hevc_print(hevc,
11516 PRINT_FRAMEBASE_DATA,
11517 "%06x:", jj);
11518 hevc_print_cont(hevc,
11519 PRINT_FRAMEBASE_DATA,
11520 "%02x ", data[jj]);
11521 if (((jj + 1) & 0xf) == 0)
11522 hevc_print_cont(hevc,
11523 PRINT_FRAMEBASE_DATA,
11524 "\n");
11525 }
11526
11527 if (!hevc->chunk->block->is_mapped)
11528 codec_mm_unmap_phyaddr(data);
11529 }
11530
11531 decode_size = hevc->chunk->size +
11532 (hevc->chunk->offset & (VDEC_FIFO_ALIGN - 1));
11533 WRITE_VREG(HEVC_DECODE_SIZE,
11534 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
11535
11536 vdec_enable_input(vdec);
11537
11538 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11539 "%s: mpc %x\n",
11540 __func__, READ_VREG(HEVC_MPC_E));
11541
11542 start_process_time(hevc);
11543 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
11544 } else{
11545 hevc->dec_result = DEC_RESULT_GET_DATA_RETRY;
11546
11547 /*hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL,
11548 * "amvdec_vh265: Insufficient data\n");
11549 */
11550
11551 vdec_schedule_work(&hevc->work);
11552 }
11553 return;
11554 } else if (hevc->dec_result == DEC_RESULT_DONE) {
11555 /* if (!hevc->ctx_valid)
11556 hevc->ctx_valid = 1; */
11557 decode_frame_count[hevc->index]++;
11558#ifdef DETREFILL_ENABLE
11559 if (hevc->is_swap &&
11560 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
11561 if (hevc->delrefill_check == 2) {
11562 delrefill(hevc);
11563 amhevc_stop();
11564 }
11565 }
11566#endif
11567 if (hevc->mmu_enable && ((hevc->double_write_mode & 0x10) == 0)) {
11568 hevc->used_4k_num =
11569 READ_VREG(HEVC_SAO_MMU_STATUS) >> 16;
11570 if (hevc->used_4k_num >= 0 &&
11571 hevc->cur_pic &&
11572 hevc->cur_pic->scatter_alloc
11573 == 1) {
11574 hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
11575 "%s pic index %d scatter_alloc %d page_start %d\n",
11576 "decoder_mmu_box_free_idx_tail",
11577 hevc->cur_pic->index,
11578 hevc->cur_pic->scatter_alloc,
11579 hevc->used_4k_num);
11580 if (hevc->m_ins_flag)
11581 hevc_mmu_dma_check(hw_to_vdec(hevc));
11582 decoder_mmu_box_free_idx_tail(
11583 hevc->mmu_box,
11584 hevc->cur_pic->index,
11585 hevc->used_4k_num);
11586 hevc->cur_pic->scatter_alloc = 2;
11587 }
11588 }
11589 hevc->pic_decoded_lcu_idx =
11590 READ_VREG(HEVC_PARSER_LCU_START)
11591 & 0xffffff;
11592
11593 if (vdec->master == NULL && vdec->slave == NULL &&
11594 hevc->empty_flag == 0) {
11595 hevc->over_decode =
11596 (READ_VREG(HEVC_SHIFT_STATUS) >> 15) & 0x1;
11597 if (hevc->over_decode)
11598 hevc_print(hevc, 0,
11599 "!!!Over decode\n");
11600 }
11601
11602 if (is_log_enable(hevc))
11603 add_log(hevc,
11604 "%s dec_result %d lcu %d used_mmu %d shiftbyte 0x%x decbytes 0x%x",
11605 __func__,
11606 hevc->dec_result,
11607 hevc->pic_decoded_lcu_idx,
11608 hevc->used_4k_num,
11609 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
11610 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
11611 hevc->start_shift_bytes
11612 );
11613
11614 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11615 "%s dec_result %d (%x %x %x) lcu %d used_mmu %d shiftbyte 0x%x decbytes 0x%x\n",
11616 __func__,
11617 hevc->dec_result,
11618 READ_VREG(HEVC_STREAM_LEVEL),
11619 READ_VREG(HEVC_STREAM_WR_PTR),
11620 READ_VREG(HEVC_STREAM_RD_PTR),
11621 hevc->pic_decoded_lcu_idx,
11622 hevc->used_4k_num,
11623 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
11624 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
11625 hevc->start_shift_bytes
11626 );
11627
11628 hevc->used_4k_num = -1;
11629
11630 check_pic_decoded_error(hevc,
11631 hevc->pic_decoded_lcu_idx);
11632#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11633#if 1
11634 if (vdec->slave) {
11635 if (dv_debug & 0x1)
11636 vdec_set_flag(vdec->slave,
11637 VDEC_FLAG_SELF_INPUT_CONTEXT);
11638 else
11639 vdec_set_flag(vdec->slave,
11640 VDEC_FLAG_OTHER_INPUT_CONTEXT);
11641 }
11642#else
11643 if (vdec->slave) {
11644 if (no_interleaved_el_slice)
11645 vdec_set_flag(vdec->slave,
11646 VDEC_FLAG_INPUT_KEEP_CONTEXT);
11647 /* this will move real HW pointer for input */
11648 else
11649 vdec_set_flag(vdec->slave, 0);
11650 /* this will not move real HW pointer
11651 *and SL layer decoding
11652 *will start from same stream position
11653 *as current BL decoder
11654 */
11655 }
11656#endif
11657#endif
11658#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11659 hevc->shift_byte_count_lo
11660 = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
11661 if (vdec->slave) {
11662 /*cur is base, found enhance*/
11663 struct hevc_state_s *hevc_el =
11664 (struct hevc_state_s *)
11665 vdec->slave->private;
11666 if (hevc_el)
11667 hevc_el->shift_byte_count_lo =
11668 hevc->shift_byte_count_lo;
11669 } else if (vdec->master) {
11670 /*cur is enhance, found base*/
11671 struct hevc_state_s *hevc_ba =
11672 (struct hevc_state_s *)
11673 vdec->master->private;
11674 if (hevc_ba)
11675 hevc_ba->shift_byte_count_lo =
11676 hevc->shift_byte_count_lo;
11677 }
11678#endif
11679 mutex_lock(&hevc->chunks_mutex);
11680 vdec_vframe_dirty(hw_to_vdec(hevc), hevc->chunk);
11681 hevc->chunk = NULL;
11682 mutex_unlock(&hevc->chunks_mutex);
11683 } else if (hevc->dec_result == DEC_RESULT_AGAIN) {
11684 /*
11685 stream base: stream buf empty or timeout
11686 frame base: vdec_prepare_input fail
11687 */
11688 if (!vdec_has_more_input(vdec)) {
11689 hevc->dec_result = DEC_RESULT_EOS;
11690 vdec_schedule_work(&hevc->work);
11691 return;
11692 }
11693#ifdef AGAIN_HAS_THRESHOLD
11694 hevc->next_again_flag = 1;
11695#endif
11696 } else if (hevc->dec_result == DEC_RESULT_EOS) {
11697 struct PIC_s *pic;
11698 hevc->eos = 1;
11699#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11700 if ((vdec->master || vdec->slave) &&
11701 aux_data_is_avaible(hevc))
11702 dolby_get_meta(hevc);
11703#endif
11704 check_pic_decoded_error(hevc,
11705 hevc->pic_decoded_lcu_idx);
11706 pic = get_pic_by_POC(hevc, hevc->curr_POC);
11707 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11708 "%s: end of stream, last dec poc %d => 0x%pf\n",
11709 __func__, hevc->curr_POC, pic);
11710 flush_output(hevc, pic);
11711
11712 if (hevc->is_used_v4l)
11713 notify_v4l_eos(hw_to_vdec(hevc));
11714#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11715 hevc->shift_byte_count_lo
11716 = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
11717 if (vdec->slave) {
11718 /*cur is base, found enhance*/
11719 struct hevc_state_s *hevc_el =
11720 (struct hevc_state_s *)
11721 vdec->slave->private;
11722 if (hevc_el)
11723 hevc_el->shift_byte_count_lo =
11724 hevc->shift_byte_count_lo;
11725 } else if (vdec->master) {
11726 /*cur is enhance, found base*/
11727 struct hevc_state_s *hevc_ba =
11728 (struct hevc_state_s *)
11729 vdec->master->private;
11730 if (hevc_ba)
11731 hevc_ba->shift_byte_count_lo =
11732 hevc->shift_byte_count_lo;
11733 }
11734#endif
11735 mutex_lock(&hevc->chunks_mutex);
11736 vdec_vframe_dirty(hw_to_vdec(hevc), hevc->chunk);
11737 hevc->chunk = NULL;
11738 mutex_unlock(&hevc->chunks_mutex);
11739 } else if (hevc->dec_result == DEC_RESULT_FORCE_EXIT) {
11740 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11741 "%s: force exit\n",
11742 __func__);
11743 if (hevc->stat & STAT_VDEC_RUN) {
11744 amhevc_stop();
11745 hevc->stat &= ~STAT_VDEC_RUN;
11746 }
11747 if (hevc->stat & STAT_ISR_REG) {
11748 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
11749 vdec_free_irq(VDEC_IRQ_0, (void *)hevc);
11750 hevc->stat &= ~STAT_ISR_REG;
11751 }
11752 hevc_print(hevc, 0, "%s: force exit end\n",
11753 __func__);
11754 }
11755
11756 if (hevc->stat & STAT_VDEC_RUN) {
11757 amhevc_stop();
11758 hevc->stat &= ~STAT_VDEC_RUN;
11759 }
11760
11761 if (hevc->stat & STAT_TIMER_ARM) {
11762 del_timer_sync(&hevc->timer);
11763 hevc->stat &= ~STAT_TIMER_ARM;
11764 }
11765
11766 wait_hevc_search_done(hevc);
11767#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11768 if (hevc->switch_dvlayer_flag) {
11769 if (vdec->slave)
11770 vdec_set_next_sched(vdec, vdec->slave);
11771 else if (vdec->master)
11772 vdec_set_next_sched(vdec, vdec->master);
11773 } else if (vdec->slave || vdec->master)
11774 vdec_set_next_sched(vdec, vdec);
11775#endif
11776
11777 if (from == 1) {
11778 /* This is a timeout work */
11779 if (work_pending(&hevc->work)) {
11780 /*
11781 * The vh265_work arrives at the last second,
11782 * give it a chance to handle the scenario.
11783 */
11784 return;
11785 //cancel_work_sync(&hevc->work);//reserved for future considraion
11786 }
11787 }
11788
11789 /* mark itself has all HW resource released and input released */
11790 if (vdec->parallel_dec == 1)
11791 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
11792 else
11793 vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
11794
11795 if (hevc->is_used_v4l) {
11796 struct aml_vcodec_ctx *ctx =
11797 (struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
11798
11799 if (ctx->param_sets_from_ucode &&
11800 !hevc->v4l_params_parsed)
11801 vdec_v4l_write_frame_sync(ctx);
11802 }
11803
11804 if (hevc->vdec_cb)
11805 hevc->vdec_cb(hw_to_vdec(hevc), hevc->vdec_cb_arg);
11806}
11807
11808static void vh265_work(struct work_struct *work)
11809{
11810 struct hevc_state_s *hevc = container_of(work,
11811 struct hevc_state_s, work);
11812 struct vdec_s *vdec = hw_to_vdec(hevc);
11813
11814 vh265_work_implement(hevc, vdec, 0);
11815}
11816
11817static void vh265_timeout_work(struct work_struct *work)
11818{
11819 struct hevc_state_s *hevc = container_of(work,
11820 struct hevc_state_s, timeout_work);
11821 struct vdec_s *vdec = hw_to_vdec(hevc);
11822
11823 if (work_pending(&hevc->work))
11824 return;
11825 vh265_work_implement(hevc, vdec, 1);
11826}
11827
11828
11829static int vh265_hw_ctx_restore(struct hevc_state_s *hevc)
11830{
11831 /* new to do ... */
11832 vh265_prot_init(hevc);
11833 return 0;
11834}
11835static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
11836{
11837 struct hevc_state_s *hevc =
11838 (struct hevc_state_s *)vdec->private;
11839 int tvp = vdec_secure(hw_to_vdec(hevc)) ?
11840 CODEC_MM_FLAGS_TVP : 0;
11841 bool ret = 0;
11842 if (step == 0x12)
11843 return 0;
11844 else if (step == 0x11)
11845 step = 0x12;
11846
11847 if (hevc->eos)
11848 return 0;
11849 if (!hevc->first_sc_checked && hevc->mmu_enable) {
11850 int size = decoder_mmu_box_sc_check(hevc->mmu_box, tvp);
11851 hevc->first_sc_checked =1;
11852 hevc_print(hevc, 0,
11853 "vh265 cached=%d need_size=%d speed= %d ms\n",
11854 size, (hevc->need_cache_size >> PAGE_SHIFT),
11855 (int)(get_jiffies_64() - hevc->sc_start_time) * 1000/HZ);
11856 }
11857 if (vdec_stream_based(vdec) && (hevc->init_flag == 0)
11858 && pre_decode_buf_level != 0) {
11859 u32 rp, wp, level;
11860
11861 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
11862 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
11863 if (wp < rp)
11864 level = vdec->input.size + wp - rp;
11865 else
11866 level = wp - rp;
11867
11868 if (level < pre_decode_buf_level)
11869 return 0;
11870 }
11871
11872#ifdef AGAIN_HAS_THRESHOLD
11873 if (hevc->next_again_flag &&
11874 (!vdec_frame_based(vdec))) {
11875 u32 parser_wr_ptr =
11876 READ_PARSER_REG(PARSER_VIDEO_WP);
11877 if (parser_wr_ptr >= hevc->pre_parser_wr_ptr &&
11878 (parser_wr_ptr - hevc->pre_parser_wr_ptr) <
11879 again_threshold) {
11880 int r = vdec_sync_input(vdec);
11881 hevc_print(hevc,
11882 PRINT_FLAG_VDEC_DETAIL, "%s buf lelvel:%x\n", __func__, r);
11883 return 0;
11884 }
11885 }
11886#endif
11887
11888 if (disp_vframe_valve_level &&
11889 kfifo_len(&hevc->display_q) >=
11890 disp_vframe_valve_level) {
11891 hevc->valve_count--;
11892 if (hevc->valve_count <= 0)
11893 hevc->valve_count = 2;
11894 else
11895 return 0;
11896 }
11897
11898 ret = is_new_pic_available(hevc);
11899 if (!ret) {
11900 hevc_print(hevc,
11901 PRINT_FLAG_VDEC_DETAIL, "%s=>%d\r\n",
11902 __func__, ret);
11903 }
11904
11905#ifdef CONSTRAIN_MAX_BUF_NUM
11906 if (hevc->pic_list_init_flag == 3) {
11907 if (run_ready_max_vf_only_num > 0 &&
11908 get_vf_ref_only_buf_count(hevc) >=
11909 run_ready_max_vf_only_num
11910 )
11911 ret = 0;
11912 if (run_ready_display_q_num > 0 &&
11913 kfifo_len(&hevc->display_q) >=
11914 run_ready_display_q_num)
11915 ret = 0;
11916
11917 /*avoid more buffers consumed when
11918 switching resolution*/
11919 if (run_ready_max_buf_num == 0xff &&
11920 get_used_buf_count(hevc) >=
11921 get_work_pic_num(hevc))
11922 ret = 0;
11923 else if (run_ready_max_buf_num &&
11924 get_used_buf_count(hevc) >=
11925 run_ready_max_buf_num)
11926 ret = 0;
11927 }
11928#endif
11929
11930 if (hevc->is_used_v4l) {
11931 struct aml_vcodec_ctx *ctx =
11932 (struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
11933
11934 if (ctx->param_sets_from_ucode &&
11935 !ctx->v4l_codec_ready &&
11936 hevc->v4l_params_parsed)
11937 ret = 0; /*the params has parsed.*/
11938 }
11939
11940
11941 if (ret)
11942 not_run_ready[hevc->index] = 0;
11943 else
11944 not_run_ready[hevc->index]++;
11945 if (vdec->parallel_dec == 1)
11946 return ret ? (CORE_MASK_HEVC) : 0;
11947 else
11948 return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
11949}
11950
11951static void run(struct vdec_s *vdec, unsigned long mask,
11952 void (*callback)(struct vdec_s *, void *), void *arg)
11953{
11954 struct hevc_state_s *hevc =
11955 (struct hevc_state_s *)vdec->private;
11956 int r, loadr = 0;
11957 unsigned char check_sum = 0;
11958
11959 run_count[hevc->index]++;
11960 hevc->vdec_cb_arg = arg;
11961 hevc->vdec_cb = callback;
11962 hevc->aux_data_dirty = 1;
11963 hevc_reset_core(vdec);
11964
11965#ifdef AGAIN_HAS_THRESHOLD
11966 hevc->pre_parser_wr_ptr =
11967 READ_PARSER_REG(PARSER_VIDEO_WP);
11968 hevc->next_again_flag = 0;
11969#endif
11970 r = vdec_prepare_input(vdec, &hevc->chunk);
11971 if (r < 0) {
11972 input_empty[hevc->index]++;
11973 hevc->dec_result = DEC_RESULT_AGAIN;
11974 hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL,
11975 "ammvdec_vh265: Insufficient data\n");
11976
11977 vdec_schedule_work(&hevc->work);
11978 return;
11979 }
11980 input_empty[hevc->index] = 0;
11981 hevc->dec_result = DEC_RESULT_NONE;
11982 if (vdec_frame_based(vdec) &&
11983 ((get_dbg_flag(hevc) & PRINT_FLAG_VDEC_STATUS)
11984 || is_log_enable(hevc)))
11985 check_sum = get_data_check_sum(hevc, r);
11986
11987 if (is_log_enable(hevc))
11988 add_log(hevc,
11989 "%s: size 0x%x sum 0x%x shiftbyte 0x%x",
11990 __func__, r,
11991 check_sum,
11992 READ_VREG(HEVC_SHIFT_BYTE_COUNT)
11993 );
11994 hevc->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
11995 hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11996 "%s: size 0x%x sum 0x%x (%x %x %x %x %x) byte count %x\n",
11997 __func__, r,
11998 check_sum,
11999 READ_VREG(HEVC_STREAM_LEVEL),
12000 READ_VREG(HEVC_STREAM_WR_PTR),
12001 READ_VREG(HEVC_STREAM_RD_PTR),
12002 READ_PARSER_REG(PARSER_VIDEO_RP),
12003 READ_PARSER_REG(PARSER_VIDEO_WP),
12004 hevc->start_shift_bytes
12005 );
12006 if ((get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) &&
12007 input_frame_based(vdec)) {
12008 int jj;
12009 u8 *data = NULL;
12010
12011 if (!hevc->chunk->block->is_mapped)
12012 data = codec_mm_vmap(hevc->chunk->block->start +
12013 hevc->chunk->offset, r);
12014 else
12015 data = ((u8 *)hevc->chunk->block->start_virt)
12016 + hevc->chunk->offset;
12017
12018 for (jj = 0; jj < r; jj++) {
12019 if ((jj & 0xf) == 0)
12020 hevc_print(hevc, PRINT_FRAMEBASE_DATA,
12021 "%06x:", jj);
12022 hevc_print_cont(hevc, PRINT_FRAMEBASE_DATA,
12023 "%02x ", data[jj]);
12024 if (((jj + 1) & 0xf) == 0)
12025 hevc_print_cont(hevc, PRINT_FRAMEBASE_DATA,
12026 "\n");
12027 }
12028
12029 if (!hevc->chunk->block->is_mapped)
12030 codec_mm_unmap_phyaddr(data);
12031 }
12032 if (vdec->mc_loaded) {
12033 /*firmware have load before,
12034 and not changes to another.
12035 ignore reload.
12036 */
12037 if (tee_enabled() && hevc->is_swap &&
12038 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
12039 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->swap_addr);
12040 } else {
12041 if (hevc->mmu_enable)
12042 if (get_cpu_major_id() > AM_MESON_CPU_MAJOR_ID_GXM)
12043 loadr = amhevc_vdec_loadmc_ex(VFORMAT_HEVC, vdec,
12044 "h265_mmu", hevc->fw->data);
12045 else {
12046 if (!hevc->is_4k) {
12047 /* if an older version of the fw was loaded, */
12048 /* needs try to load noswap fw because the */
12049 /* old fw package dose not contain the swap fw.*/
12050 loadr = amhevc_vdec_loadmc_ex(
12051 VFORMAT_HEVC, vdec,
12052 "hevc_mmu_swap",
12053 hevc->fw->data);
12054 if (loadr < 0)
12055 loadr = amhevc_vdec_loadmc_ex(
12056 VFORMAT_HEVC, vdec,
12057 "h265_mmu",
12058 hevc->fw->data);
12059 else
12060 hevc->is_swap = true;
12061 } else
12062 loadr = amhevc_vdec_loadmc_ex(
12063 VFORMAT_HEVC, vdec,
12064 "h265_mmu", hevc->fw->data);
12065 }
12066 else
12067 loadr = amhevc_vdec_loadmc_ex(VFORMAT_HEVC, vdec,
12068 NULL, hevc->fw->data);
12069 if (loadr < 0) {
12070 amhevc_disable();
12071 hevc_print(hevc, 0, "H265: the %s fw loading failed, err: %x\n",
12072 tee_enabled() ? "TEE" : "local", loadr);
12073 hevc->dec_result = DEC_RESULT_FORCE_EXIT;
12074 vdec_schedule_work(&hevc->work);
12075 return;
12076 }
12077
12078 if (tee_enabled() && hevc->is_swap &&
12079 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
12080 hevc->swap_addr = READ_VREG(HEVC_STREAM_SWAP_BUFFER2);
12081#ifdef DETREFILL_ENABLE
12082 if (hevc->is_swap &&
12083 get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
12084 init_detrefill_buf(hevc);
12085#endif
12086 vdec->mc_loaded = 1;
12087 vdec->mc_type = VFORMAT_HEVC;
12088 }
12089 if (vh265_hw_ctx_restore(hevc) < 0) {
12090 vdec_schedule_work(&hevc->work);
12091 return;
12092 }
12093 vdec_enable_input(vdec);
12094
12095 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
12096
12097 if (vdec_frame_based(vdec)) {
12098 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
12099 r = hevc->chunk->size +
12100 (hevc->chunk->offset & (VDEC_FIFO_ALIGN - 1));
12101 hevc->decode_size = r;
12102 }
12103#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
12104 else {
12105 if (vdec->master || vdec->slave)
12106 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT,
12107 hevc->shift_byte_count_lo);
12108 }
12109#endif
12110 WRITE_VREG(HEVC_DECODE_SIZE, r);
12111 /*WRITE_VREG(HEVC_DECODE_COUNT, hevc->decode_idx);*/
12112 hevc->init_flag = 1;
12113
12114 if (hevc->pic_list_init_flag == 3)
12115 init_pic_list_hw(hevc);
12116
12117 backup_decode_state(hevc);
12118
12119 start_process_time(hevc);
12120 mod_timer(&hevc->timer, jiffies);
12121 hevc->stat |= STAT_TIMER_ARM;
12122 hevc->stat |= STAT_ISR_REG;
12123 amhevc_start();
12124 hevc->stat |= STAT_VDEC_RUN;
12125}
12126
12127static void reset(struct vdec_s *vdec)
12128{
12129
12130 struct hevc_state_s *hevc =
12131 (struct hevc_state_s *)vdec->private;
12132 int i;
12133
12134 cancel_work_sync(&hevc->work);
12135 cancel_work_sync(&hevc->notify_work);
12136 if (hevc->stat & STAT_VDEC_RUN) {
12137 amhevc_stop();
12138 hevc->stat &= ~STAT_VDEC_RUN;
12139 }
12140
12141 if (hevc->stat & STAT_TIMER_ARM) {
12142 del_timer_sync(&hevc->timer);
12143 hevc->stat &= ~STAT_TIMER_ARM;
12144 }
12145 hevc->dec_result = DEC_RESULT_NONE;
12146 reset_process_time(hevc);
12147 hevc->init_flag = 0;
12148 hevc->pic_list_init_flag = 0;
12149 dealloc_mv_bufs(hevc);
12150 hevc_local_uninit(hevc);
12151 if (vh265_local_init(hevc) < 0)
12152 pr_debug(" %s local init fail\n", __func__);
12153 for (i = 0; i < BUF_POOL_SIZE; i++) {
12154 hevc->m_BUF[i].start_adr = 0;
12155 }
12156
12157 hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
12158}
12159
12160static irqreturn_t vh265_irq_cb(struct vdec_s *vdec, int irq)
12161{
12162 struct hevc_state_s *hevc =
12163 (struct hevc_state_s *)vdec->private;
12164
12165 return vh265_isr(0, hevc);
12166}
12167
12168static irqreturn_t vh265_threaded_irq_cb(struct vdec_s *vdec, int irq)
12169{
12170 struct hevc_state_s *hevc =
12171 (struct hevc_state_s *)vdec->private;
12172
12173 return vh265_isr_thread_fn(0, hevc);
12174}
12175#endif
12176
12177static int amvdec_h265_probe(struct platform_device *pdev)
12178{
12179#ifdef MULTI_INSTANCE_SUPPORT
12180 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
12181#else
12182 struct vdec_dev_reg_s *pdata =
12183 (struct vdec_dev_reg_s *)pdev->dev.platform_data;
12184#endif
12185 char *tmpbuf;
12186 int ret;
12187 struct hevc_state_s *hevc;
12188
12189 hevc = vmalloc(sizeof(struct hevc_state_s));
12190 if (hevc == NULL) {
12191 hevc_print(hevc, 0, "%s vmalloc hevc failed\r\n", __func__);
12192 return -ENOMEM;
12193 }
12194 gHevc = hevc;
12195 if ((debug & H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0)
12196 debug &= (~(H265_DEBUG_DIS_LOC_ERROR_PROC |
12197 H265_DEBUG_DIS_SYS_ERROR_PROC));
12198 memset(hevc, 0, sizeof(struct hevc_state_s));
12199 if (get_dbg_flag(hevc))
12200 hevc_print(hevc, 0, "%s\r\n", __func__);
12201 mutex_lock(&vh265_mutex);
12202
12203 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) &&
12204 (parser_sei_enable & 0x100) == 0)
12205 parser_sei_enable = 7; /*old 1*/
12206 hevc->m_ins_flag = 0;
12207 hevc->init_flag = 0;
12208 hevc->first_sc_checked = 0;
12209 hevc->uninit_list = 0;
12210 hevc->fatal_error = 0;
12211 hevc->show_frame_num = 0;
12212 hevc->frameinfo_enable = 1;
12213#ifdef MULTI_INSTANCE_SUPPORT
12214 hevc->platform_dev = pdev;
12215 platform_set_drvdata(pdev, pdata);
12216#endif
12217
12218 if (pdata == NULL) {
12219 hevc_print(hevc, 0,
12220 "\namvdec_h265 memory resource undefined.\n");
12221 vfree(hevc);
12222 mutex_unlock(&vh265_mutex);
12223 return -EFAULT;
12224 }
12225 if (mmu_enable_force == 0) {
12226 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_GXL
12227 || double_write_mode == 0x10)
12228 hevc->mmu_enable = 0;
12229 else
12230 hevc->mmu_enable = 1;
12231 }
12232 if (init_mmu_buffers(hevc)) {
12233 hevc_print(hevc, 0,
12234 "\n 265 mmu init failed!\n");
12235 vfree(hevc);
12236 mutex_unlock(&vh265_mutex);
12237 return -EFAULT;
12238 }
12239
12240 ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box, BMMU_WORKSPACE_ID,
12241 work_buf_size, DRIVER_NAME, &hevc->buf_start);
12242 if (ret < 0) {
12243 uninit_mmu_buffers(hevc);
12244 vfree(hevc);
12245 mutex_unlock(&vh265_mutex);
12246 return ret;
12247 }
12248 hevc->buf_size = work_buf_size;
12249
12250
12251 if (!vdec_secure(pdata)) {
12252 tmpbuf = (char *)codec_mm_phys_to_virt(hevc->buf_start);
12253 if (tmpbuf) {
12254 memset(tmpbuf, 0, work_buf_size);
12255 dma_sync_single_for_device(amports_get_dma_device(),
12256 hevc->buf_start,
12257 work_buf_size, DMA_TO_DEVICE);
12258 } else {
12259 tmpbuf = codec_mm_vmap(hevc->buf_start,
12260 work_buf_size);
12261 if (tmpbuf) {
12262 memset(tmpbuf, 0, work_buf_size);
12263 dma_sync_single_for_device(
12264 amports_get_dma_device(),
12265 hevc->buf_start,
12266 work_buf_size,
12267 DMA_TO_DEVICE);
12268 codec_mm_unmap_phyaddr(tmpbuf);
12269 }
12270 }
12271 }
12272
12273 if (get_dbg_flag(hevc)) {
12274 hevc_print(hevc, 0,
12275 "===H.265 decoder mem resource 0x%lx size 0x%x\n",
12276 hevc->buf_start, hevc->buf_size);
12277 }
12278
12279 if (pdata->sys_info)
12280 hevc->vh265_amstream_dec_info = *pdata->sys_info;
12281 else {
12282 hevc->vh265_amstream_dec_info.width = 0;
12283 hevc->vh265_amstream_dec_info.height = 0;
12284 hevc->vh265_amstream_dec_info.rate = 30;
12285 }
12286#ifndef MULTI_INSTANCE_SUPPORT
12287 if (pdata->flag & DEC_FLAG_HEVC_WORKAROUND) {
12288 workaround_enable |= 3;
12289 hevc_print(hevc, 0,
12290 "amvdec_h265 HEVC_WORKAROUND flag set.\n");
12291 } else
12292 workaround_enable &= ~3;
12293#endif
12294 hevc->cma_dev = pdata->cma_dev;
12295 vh265_vdec_info_init();
12296
12297#ifdef MULTI_INSTANCE_SUPPORT
12298 pdata->private = hevc;
12299 pdata->dec_status = vh265_dec_status;
12300 pdata->set_isreset = vh265_set_isreset;
12301 is_reset = 0;
12302 if (vh265_init(pdata) < 0) {
12303#else
12304 if (vh265_init(hevc) < 0) {
12305#endif
12306 hevc_print(hevc, 0,
12307 "\namvdec_h265 init failed.\n");
12308 hevc_local_uninit(hevc);
12309 uninit_mmu_buffers(hevc);
12310 vfree(hevc);
12311 pdata->dec_status = NULL;
12312 mutex_unlock(&vh265_mutex);
12313 return -ENODEV;
12314 }
12315 /*set the max clk for smooth playing...*/
12316 hevc_source_changed(VFORMAT_HEVC,
12317 3840, 2160, 60);
12318 mutex_unlock(&vh265_mutex);
12319
12320 return 0;
12321}
12322
12323static int amvdec_h265_remove(struct platform_device *pdev)
12324{
12325 struct hevc_state_s *hevc = gHevc;
12326
12327 if (get_dbg_flag(hevc))
12328 hevc_print(hevc, 0, "%s\r\n", __func__);
12329
12330 mutex_lock(&vh265_mutex);
12331
12332 vh265_stop(hevc);
12333
12334 hevc_source_changed(VFORMAT_HEVC, 0, 0, 0);
12335
12336
12337#ifdef DEBUG_PTS
12338 hevc_print(hevc, 0,
12339 "pts missed %ld, pts hit %ld, duration %d\n",
12340 hevc->pts_missed, hevc->pts_hit, hevc->frame_dur);
12341#endif
12342
12343 vfree(hevc);
12344 hevc = NULL;
12345 gHevc = NULL;
12346
12347 mutex_unlock(&vh265_mutex);
12348
12349 return 0;
12350}
12351/****************************************/
12352#ifdef CONFIG_PM
12353static int h265_suspend(struct device *dev)
12354{
12355 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
12356 return 0;
12357}
12358
12359static int h265_resume(struct device *dev)
12360{
12361 amhevc_resume(to_platform_device(dev));
12362 return 0;
12363}
12364
12365static const struct dev_pm_ops h265_pm_ops = {
12366 SET_SYSTEM_SLEEP_PM_OPS(h265_suspend, h265_resume)
12367};
12368#endif
12369
12370static struct platform_driver amvdec_h265_driver = {
12371 .probe = amvdec_h265_probe,
12372 .remove = amvdec_h265_remove,
12373 .driver = {
12374 .name = DRIVER_NAME,
12375#ifdef CONFIG_PM
12376 .pm = &h265_pm_ops,
12377#endif
12378 }
12379};
12380
12381#ifdef MULTI_INSTANCE_SUPPORT
12382static void vh265_dump_state(struct vdec_s *vdec)
12383{
12384 int i;
12385 struct hevc_state_s *hevc =
12386 (struct hevc_state_s *)vdec->private;
12387 hevc_print(hevc, 0,
12388 "====== %s\n", __func__);
12389
12390 hevc_print(hevc, 0,
12391 "width/height (%d/%d), reorder_pic_num %d buf count(bufspec size) %d, video_signal_type 0x%x, is_swap %d\n",
12392 hevc->frame_width,
12393 hevc->frame_height,
12394 hevc->sps_num_reorder_pics_0,
12395 get_work_pic_num(hevc),
12396 hevc->video_signal_type_debug,
12397 hevc->is_swap
12398 );
12399
12400 hevc_print(hevc, 0,
12401 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
12402 input_frame_based(vdec),
12403 hevc->eos,
12404 hevc->dec_result,
12405 decode_frame_count[hevc->index],
12406 display_frame_count[hevc->index],
12407 run_count[hevc->index],
12408 not_run_ready[hevc->index],
12409 input_empty[hevc->index]
12410 );
12411
12412 if (vf_get_receiver(vdec->vf_provider_name)) {
12413 enum receviver_start_e state =
12414 vf_notify_receiver(vdec->vf_provider_name,
12415 VFRAME_EVENT_PROVIDER_QUREY_STATE,
12416 NULL);
12417 hevc_print(hevc, 0,
12418 "\nreceiver(%s) state %d\n",
12419 vdec->vf_provider_name,
12420 state);
12421 }
12422
12423 hevc_print(hevc, 0,
12424 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), pic_list_init_flag(%d), is_new_pic_available(%d)\n",
12425 __func__,
12426 kfifo_len(&hevc->newframe_q),
12427 VF_POOL_SIZE,
12428 kfifo_len(&hevc->display_q),
12429 VF_POOL_SIZE,
12430 hevc->vf_pre_count,
12431 hevc->vf_get_count,
12432 hevc->vf_put_count,
12433 hevc->pic_list_init_flag,
12434 is_new_pic_available(hevc)
12435 );
12436
12437 dump_pic_list(hevc);
12438
12439 for (i = 0; i < BUF_POOL_SIZE; i++) {
12440 hevc_print(hevc, 0,
12441 "Buf(%d) start_adr 0x%x size 0x%x used %d\n",
12442 i,
12443 hevc->m_BUF[i].start_adr,
12444 hevc->m_BUF[i].size,
12445 hevc->m_BUF[i].used_flag);
12446 }
12447
12448 for (i = 0; i < MAX_REF_PIC_NUM; i++) {
12449 hevc_print(hevc, 0,
12450 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
12451 i,
12452 hevc->m_mv_BUF[i].start_adr,
12453 hevc->m_mv_BUF[i].size,
12454 hevc->m_mv_BUF[i].used_flag);
12455 }
12456
12457 hevc_print(hevc, 0,
12458 "HEVC_DEC_STATUS_REG=0x%x\n",
12459 READ_VREG(HEVC_DEC_STATUS_REG));
12460 hevc_print(hevc, 0,
12461 "HEVC_MPC_E=0x%x\n",
12462 READ_VREG(HEVC_MPC_E));
12463 hevc_print(hevc, 0,
12464 "HEVC_DECODE_MODE=0x%x\n",
12465 READ_VREG(HEVC_DECODE_MODE));
12466 hevc_print(hevc, 0,
12467 "HEVC_DECODE_MODE2=0x%x\n",
12468 READ_VREG(HEVC_DECODE_MODE2));
12469 hevc_print(hevc, 0,
12470 "NAL_SEARCH_CTL=0x%x\n",
12471 READ_VREG(NAL_SEARCH_CTL));
12472 hevc_print(hevc, 0,
12473 "HEVC_PARSER_LCU_START=0x%x\n",
12474 READ_VREG(HEVC_PARSER_LCU_START));
12475 hevc_print(hevc, 0,
12476 "HEVC_DECODE_SIZE=0x%x\n",
12477 READ_VREG(HEVC_DECODE_SIZE));
12478 hevc_print(hevc, 0,
12479 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
12480 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
12481 hevc_print(hevc, 0,
12482 "HEVC_STREAM_START_ADDR=0x%x\n",
12483 READ_VREG(HEVC_STREAM_START_ADDR));
12484 hevc_print(hevc, 0,
12485 "HEVC_STREAM_END_ADDR=0x%x\n",
12486 READ_VREG(HEVC_STREAM_END_ADDR));
12487 hevc_print(hevc, 0,
12488 "HEVC_STREAM_LEVEL=0x%x\n",
12489 READ_VREG(HEVC_STREAM_LEVEL));
12490 hevc_print(hevc, 0,
12491 "HEVC_STREAM_WR_PTR=0x%x\n",
12492 READ_VREG(HEVC_STREAM_WR_PTR));
12493 hevc_print(hevc, 0,
12494 "HEVC_STREAM_RD_PTR=0x%x\n",
12495 READ_VREG(HEVC_STREAM_RD_PTR));
12496 hevc_print(hevc, 0,
12497 "PARSER_VIDEO_RP=0x%x\n",
12498 READ_PARSER_REG(PARSER_VIDEO_RP));
12499 hevc_print(hevc, 0,
12500 "PARSER_VIDEO_WP=0x%x\n",
12501 READ_PARSER_REG(PARSER_VIDEO_WP));
12502
12503 if (input_frame_based(vdec) &&
12504 (get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA)
12505 ) {
12506 int jj;
12507 if (hevc->chunk && hevc->chunk->block &&
12508 hevc->chunk->size > 0) {
12509 u8 *data = NULL;
12510 if (!hevc->chunk->block->is_mapped)
12511 data = codec_mm_vmap(hevc->chunk->block->start +
12512 hevc->chunk->offset, hevc->chunk->size);
12513 else
12514 data = ((u8 *)hevc->chunk->block->start_virt)
12515 + hevc->chunk->offset;
12516 hevc_print(hevc, 0,
12517 "frame data size 0x%x\n",
12518 hevc->chunk->size);
12519 for (jj = 0; jj < hevc->chunk->size; jj++) {
12520 if ((jj & 0xf) == 0)
12521 hevc_print(hevc,
12522 PRINT_FRAMEBASE_DATA,
12523 "%06x:", jj);
12524 hevc_print_cont(hevc,
12525 PRINT_FRAMEBASE_DATA,
12526 "%02x ", data[jj]);
12527 if (((jj + 1) & 0xf) == 0)
12528 hevc_print_cont(hevc,
12529 PRINT_FRAMEBASE_DATA,
12530 "\n");
12531 }
12532
12533 if (!hevc->chunk->block->is_mapped)
12534 codec_mm_unmap_phyaddr(data);
12535 }
12536 }
12537
12538}
12539
12540
12541static int ammvdec_h265_probe(struct platform_device *pdev)
12542{
12543
12544 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
12545 struct hevc_state_s *hevc = NULL;
12546 int ret;
12547#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
12548 int config_val;
12549#endif
12550 if (pdata == NULL) {
12551 pr_info("\nammvdec_h265 memory resource undefined.\n");
12552 return -EFAULT;
12553 }
12554
12555 /* hevc = (struct hevc_state_s *)devm_kzalloc(&pdev->dev,
12556 sizeof(struct hevc_state_s), GFP_KERNEL); */
12557 hevc = vmalloc(sizeof(struct hevc_state_s));
12558 if (hevc == NULL) {
12559 pr_info("\nammvdec_h265 device data allocation failed\n");
12560 return -ENOMEM;
12561 }
12562 memset(hevc, 0, sizeof(struct hevc_state_s));
12563
12564 /* the ctx from v4l2 driver. */
12565 hevc->v4l2_ctx = pdata->private;
12566
12567 pdata->private = hevc;
12568 pdata->dec_status = vh265_dec_status;
12569 /* pdata->set_trickmode = set_trickmode; */
12570 pdata->run_ready = run_ready;
12571 pdata->run = run;
12572 pdata->reset = reset;
12573 pdata->irq_handler = vh265_irq_cb;
12574 pdata->threaded_irq_handler = vh265_threaded_irq_cb;
12575 pdata->dump_state = vh265_dump_state;
12576
12577 hevc->index = pdev->id;
12578 hevc->m_ins_flag = 1;
12579
12580 if (pdata->use_vfm_path) {
12581 snprintf(pdata->vf_provider_name,
12582 VDEC_PROVIDER_NAME_SIZE,
12583 VFM_DEC_PROVIDER_NAME);
12584 hevc->frameinfo_enable = 1;
12585 }
12586#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
12587 else if (vdec_dual(pdata)) {
12588 struct hevc_state_s *hevc_pair = NULL;
12589
12590 if (dv_toggle_prov_name) /*debug purpose*/
12591 snprintf(pdata->vf_provider_name,
12592 VDEC_PROVIDER_NAME_SIZE,
12593 (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
12594 VFM_DEC_DVEL_PROVIDER_NAME);
12595 else
12596 snprintf(pdata->vf_provider_name,
12597 VDEC_PROVIDER_NAME_SIZE,
12598 (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
12599 VFM_DEC_DVBL_PROVIDER_NAME);
12600 hevc->dolby_enhance_flag = pdata->master ? 1 : 0;
12601 if (pdata->master)
12602 hevc_pair = (struct hevc_state_s *)
12603 pdata->master->private;
12604 else if (pdata->slave)
12605 hevc_pair = (struct hevc_state_s *)
12606 pdata->slave->private;
12607 if (hevc_pair)
12608 hevc->shift_byte_count_lo =
12609 hevc_pair->shift_byte_count_lo;
12610 }
12611#endif
12612 else
12613 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
12614 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
12615
12616 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
12617 &vh265_vf_provider, pdata);
12618
12619 hevc->provider_name = pdata->vf_provider_name;
12620 platform_set_drvdata(pdev, pdata);
12621
12622 hevc->platform_dev = pdev;
12623
12624 if (((get_dbg_flag(hevc) & IGNORE_PARAM_FROM_CONFIG) == 0) &&
12625 pdata->config && pdata->config_len) {
12626#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
12627 /*use ptr config for doubel_write_mode, etc*/
12628 hevc_print(hevc, 0, "pdata->config=%s\n", pdata->config);
12629
12630 if (get_config_int(pdata->config, "hevc_double_write_mode",
12631 &config_val) == 0)
12632 hevc->double_write_mode = config_val;
12633 else
12634 hevc->double_write_mode = double_write_mode;
12635
12636 if (get_config_int(pdata->config, "save_buffer_mode",
12637 &config_val) == 0)
12638 hevc->save_buffer_mode = config_val;
12639 else
12640 hevc->save_buffer_mode = 0;
12641
12642 /*use ptr config for max_pic_w, etc*/
12643 if (get_config_int(pdata->config, "hevc_buf_width",
12644 &config_val) == 0) {
12645 hevc->max_pic_w = config_val;
12646 }
12647 if (get_config_int(pdata->config, "hevc_buf_height",
12648 &config_val) == 0) {
12649 hevc->max_pic_h = config_val;
12650 }
12651
12652#endif
12653 } else {
12654 if (pdata->sys_info)
12655 hevc->vh265_amstream_dec_info = *pdata->sys_info;
12656 else {
12657 hevc->vh265_amstream_dec_info.width = 0;
12658 hevc->vh265_amstream_dec_info.height = 0;
12659 hevc->vh265_amstream_dec_info.rate = 30;
12660 }
12661 hevc->double_write_mode = double_write_mode;
12662 }
12663 if (hevc->save_buffer_mode && dynamic_buf_num_margin > 2)
12664 hevc->dynamic_buf_num_margin = dynamic_buf_num_margin -2;
12665 else
12666 hevc->dynamic_buf_num_margin = dynamic_buf_num_margin;
12667
12668 if (mmu_enable_force == 0) {
12669 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_GXL)
12670 hevc->mmu_enable = 0;
12671 else
12672 hevc->mmu_enable = 1;
12673 }
12674
12675 hevc->is_used_v4l = (((unsigned long)
12676 hevc->vh265_amstream_dec_info.param & 0x80) >> 7);
12677 if (hevc->is_used_v4l) {
12678 hevc->mmu_enable = (((unsigned long) // scatter mem
12679 hevc->vh265_amstream_dec_info.param & 0x100) >> 8);
12680 if (!hevc->mmu_enable)
12681 hevc->double_write_mode = 0x10;
12682
12683 hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,
12684 "%s v4: enable mmu %d.\n",
12685 __func__, hevc->mmu_enable);
12686 }
12687
12688 if (init_mmu_buffers(hevc) < 0) {
12689 hevc_print(hevc, 0,
12690 "\n 265 mmu init failed!\n");
12691 mutex_unlock(&vh265_mutex);
12692 /* devm_kfree(&pdev->dev, (void *)hevc);*/
12693 if (hevc)
12694 vfree((void *)hevc);
12695 pdata->dec_status = NULL;
12696 return -EFAULT;
12697 }
12698#if 0
12699 hevc->buf_start = pdata->mem_start;
12700 hevc->buf_size = pdata->mem_end - pdata->mem_start + 1;
12701#else
12702
12703 ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box,
12704 BMMU_WORKSPACE_ID, work_buf_size,
12705 DRIVER_NAME, &hevc->buf_start);
12706 if (ret < 0) {
12707 uninit_mmu_buffers(hevc);
12708 /* devm_kfree(&pdev->dev, (void *)hevc); */
12709 if (hevc)
12710 vfree((void *)hevc);
12711 pdata->dec_status = NULL;
12712 mutex_unlock(&vh265_mutex);
12713 return ret;
12714 }
12715 hevc->buf_size = work_buf_size;
12716#endif
12717 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) &&
12718 (parser_sei_enable & 0x100) == 0)
12719 parser_sei_enable = 7;
12720 hevc->init_flag = 0;
12721 hevc->first_sc_checked = 0;
12722 hevc->uninit_list = 0;
12723 hevc->fatal_error = 0;
12724 hevc->show_frame_num = 0;
12725
12726 /*
12727 *hevc->mc_buf_spec.buf_end = pdata->mem_end + 1;
12728 *for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
12729 * amvh265_workbuff_spec[i].start_adr = pdata->mem_start;
12730 */
12731 if (get_dbg_flag(hevc)) {
12732 hevc_print(hevc, 0,
12733 "===H.265 decoder mem resource 0x%lx size 0x%x\n",
12734 hevc->buf_start, hevc->buf_size);
12735 }
12736
12737 hevc_print(hevc, 0,
12738 "dynamic_buf_num_margin=%d\n",
12739 hevc->dynamic_buf_num_margin);
12740 hevc_print(hevc, 0,
12741 "double_write_mode=%d\n",
12742 hevc->double_write_mode);
12743
12744 hevc->cma_dev = pdata->cma_dev;
12745
12746 if (vh265_init(pdata) < 0) {
12747 hevc_print(hevc, 0,
12748 "\namvdec_h265 init failed.\n");
12749 hevc_local_uninit(hevc);
12750 uninit_mmu_buffers(hevc);
12751 /* devm_kfree(&pdev->dev, (void *)hevc); */
12752 if (hevc)
12753 vfree((void *)hevc);
12754 pdata->dec_status = NULL;
12755 return -ENODEV;
12756 }
12757
12758 vdec_set_prepare_level(pdata, start_decode_buf_level);
12759
12760 /*set the max clk for smooth playing...*/
12761 hevc_source_changed(VFORMAT_HEVC,
12762 3840, 2160, 60);
12763 if (pdata->parallel_dec == 1)
12764 vdec_core_request(pdata, CORE_MASK_HEVC);
12765 else
12766 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
12767 | CORE_MASK_COMBINE);
12768
12769 return 0;
12770}
12771
12772static int ammvdec_h265_remove(struct platform_device *pdev)
12773{
12774 struct hevc_state_s *hevc =
12775 (struct hevc_state_s *)
12776 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
12777 struct vdec_s *vdec = hw_to_vdec(hevc);
12778
12779 if (hevc == NULL)
12780 return 0;
12781
12782 if (get_dbg_flag(hevc))
12783 hevc_print(hevc, 0, "%s\r\n", __func__);
12784
12785 vmh265_stop(hevc);
12786
12787 /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
12788 if (vdec->parallel_dec == 1)
12789 vdec_core_release(hw_to_vdec(hevc), CORE_MASK_HEVC);
12790 else
12791 vdec_core_release(hw_to_vdec(hevc), CORE_MASK_HEVC);
12792
12793 vdec_set_status(hw_to_vdec(hevc), VDEC_STATUS_DISCONNECTED);
12794
12795 vfree((void *)hevc);
12796 return 0;
12797}
12798
12799static struct platform_driver ammvdec_h265_driver = {
12800 .probe = ammvdec_h265_probe,
12801 .remove = ammvdec_h265_remove,
12802 .driver = {
12803 .name = MULTI_DRIVER_NAME,
12804#ifdef CONFIG_PM
12805 .pm = &h265_pm_ops,
12806#endif
12807 }
12808};
12809#endif
12810
12811static struct codec_profile_t amvdec_h265_profile = {
12812 .name = "hevc",
12813 .profile = ""
12814};
12815
12816static struct codec_profile_t amvdec_h265_profile_single,
12817 amvdec_h265_profile_mult;
12818
12819static struct mconfig h265_configs[] = {
12820 MC_PU32("use_cma", &use_cma),
12821 MC_PU32("bit_depth_luma", &bit_depth_luma),
12822 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
12823 MC_PU32("video_signal_type", &video_signal_type),
12824#ifdef ERROR_HANDLE_DEBUG
12825 MC_PU32("dbg_nal_skip_flag", &dbg_nal_skip_flag),
12826 MC_PU32("dbg_nal_skip_count", &dbg_nal_skip_count),
12827#endif
12828 MC_PU32("radr", &radr),
12829 MC_PU32("rval", &rval),
12830 MC_PU32("dbg_cmd", &dbg_cmd),
12831 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
12832 MC_PU32("endian", &endian),
12833 MC_PU32("step", &step),
12834 MC_PU32("udebug_flag", &udebug_flag),
12835 MC_PU32("decode_pic_begin", &decode_pic_begin),
12836 MC_PU32("slice_parse_begin", &slice_parse_begin),
12837 MC_PU32("nal_skip_policy", &nal_skip_policy),
12838 MC_PU32("i_only_flag", &i_only_flag),
12839 MC_PU32("error_handle_policy", &error_handle_policy),
12840 MC_PU32("error_handle_threshold", &error_handle_threshold),
12841 MC_PU32("error_handle_nal_skip_threshold",
12842 &error_handle_nal_skip_threshold),
12843 MC_PU32("error_handle_system_threshold",
12844 &error_handle_system_threshold),
12845 MC_PU32("error_skip_nal_count", &error_skip_nal_count),
12846 MC_PU32("debug", &debug),
12847 MC_PU32("debug_mask", &debug_mask),
12848 MC_PU32("buffer_mode", &buffer_mode),
12849 MC_PU32("double_write_mode", &double_write_mode),
12850 MC_PU32("buf_alloc_width", &buf_alloc_width),
12851 MC_PU32("buf_alloc_height", &buf_alloc_height),
12852 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
12853 MC_PU32("max_buf_num", &max_buf_num),
12854 MC_PU32("buf_alloc_size", &buf_alloc_size),
12855 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
12856 MC_PU32("mem_map_mode", &mem_map_mode),
12857 MC_PU32("enable_mem_saving", &enable_mem_saving),
12858 MC_PU32("force_w_h", &force_w_h),
12859 MC_PU32("force_fps", &force_fps),
12860 MC_PU32("max_decoding_time", &max_decoding_time),
12861 MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
12862 MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
12863 MC_PU32("interlace_enable", &interlace_enable),
12864 MC_PU32("pts_unstable", &pts_unstable),
12865 MC_PU32("parser_sei_enable", &parser_sei_enable),
12866 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
12867 MC_PU32("decode_timeout_val", &decode_timeout_val),
12868#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
12869 MC_PU32("parser_dolby_vision_enable", &parser_dolby_vision_enable),
12870 MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
12871 MC_PU32("dv_debug", &dv_debug),
12872#endif
12873};
12874static struct mconfig_node decoder_265_node;
12875
12876static int __init amvdec_h265_driver_init_module(void)
12877{
12878 struct BuffInfo_s *p_buf_info;
12879
12880 if (vdec_is_support_4k()) {
12881 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
12882 p_buf_info = &amvh265_workbuff_spec[2];
12883 else
12884 p_buf_info = &amvh265_workbuff_spec[1];
12885 } else
12886 p_buf_info = &amvh265_workbuff_spec[0];
12887
12888 init_buff_spec(NULL, p_buf_info);
12889 work_buf_size =
12890 (p_buf_info->end_adr - p_buf_info->start_adr
12891 + 0xffff) & (~0xffff);
12892
12893 pr_debug("amvdec_h265 module init\n");
12894 error_handle_policy = 0;
12895
12896#ifdef ERROR_HANDLE_DEBUG
12897 dbg_nal_skip_flag = 0;
12898 dbg_nal_skip_count = 0;
12899#endif
12900 udebug_flag = 0;
12901 decode_pic_begin = 0;
12902 slice_parse_begin = 0;
12903 step = 0;
12904 buf_alloc_size = 0;
12905
12906#ifdef MULTI_INSTANCE_SUPPORT
12907 if (platform_driver_register(&ammvdec_h265_driver))
12908 pr_err("failed to register ammvdec_h265 driver\n");
12909
12910#endif
12911 if (platform_driver_register(&amvdec_h265_driver)) {
12912 pr_err("failed to register amvdec_h265 driver\n");
12913 return -ENODEV;
12914 }
12915#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/
12916 if (!has_hevc_vdec()) {
12917 /* not support hevc */
12918 amvdec_h265_profile.name = "hevc_unsupport";
12919 }
12920 if (vdec_is_support_4k()) {
12921 if (is_meson_m8m2_cpu()) {
12922 /* m8m2 support 4k */
12923 amvdec_h265_profile.profile = "4k";
12924 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
12925 amvdec_h265_profile.profile =
12926 "8k, 8bit, 10bit, dwrite, compressed";
12927 }else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB) {
12928 amvdec_h265_profile.profile =
12929 "4k, 8bit, 10bit, dwrite, compressed";
12930 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_MG9TV)
12931 amvdec_h265_profile.profile = "4k";
12932 }
12933#endif
12934 if (codec_mm_get_total_size() < 80 * SZ_1M) {
12935 pr_info("amvdec_h265 default mmu enabled.\n");
12936 mmu_enable = 1;
12937 }
12938
12939 vcodec_profile_register(&amvdec_h265_profile);
12940 amvdec_h265_profile_single = amvdec_h265_profile;
12941 amvdec_h265_profile_single.name = "h265";
12942 vcodec_profile_register(&amvdec_h265_profile_single);
12943 amvdec_h265_profile_mult = amvdec_h265_profile;
12944 amvdec_h265_profile_mult.name = "mh265";
12945 vcodec_profile_register(&amvdec_h265_profile_mult);
12946 INIT_REG_NODE_CONFIGS("media.decoder", &decoder_265_node,
12947 "h265", h265_configs, CONFIG_FOR_RW);
12948 return 0;
12949}
12950
12951static void __exit amvdec_h265_driver_remove_module(void)
12952{
12953 pr_debug("amvdec_h265 module remove.\n");
12954
12955#ifdef MULTI_INSTANCE_SUPPORT
12956 platform_driver_unregister(&ammvdec_h265_driver);
12957#endif
12958 platform_driver_unregister(&amvdec_h265_driver);
12959}
12960
12961/****************************************/
12962/*
12963 *module_param(stat, uint, 0664);
12964 *MODULE_PARM_DESC(stat, "\n amvdec_h265 stat\n");
12965 */
12966module_param(use_cma, uint, 0664);
12967MODULE_PARM_DESC(use_cma, "\n amvdec_h265 use_cma\n");
12968
12969module_param(bit_depth_luma, uint, 0664);
12970MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_h265 bit_depth_luma\n");
12971
12972module_param(bit_depth_chroma, uint, 0664);
12973MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_h265 bit_depth_chroma\n");
12974
12975module_param(video_signal_type, uint, 0664);
12976MODULE_PARM_DESC(video_signal_type, "\n amvdec_h265 video_signal_type\n");
12977
12978#ifdef ERROR_HANDLE_DEBUG
12979module_param(dbg_nal_skip_flag, uint, 0664);
12980MODULE_PARM_DESC(dbg_nal_skip_flag, "\n amvdec_h265 dbg_nal_skip_flag\n");
12981
12982module_param(dbg_nal_skip_count, uint, 0664);
12983MODULE_PARM_DESC(dbg_nal_skip_count, "\n amvdec_h265 dbg_nal_skip_count\n");
12984#endif
12985
12986module_param(radr, uint, 0664);
12987MODULE_PARM_DESC(radr, "\n radr\n");
12988
12989module_param(rval, uint, 0664);
12990MODULE_PARM_DESC(rval, "\n rval\n");
12991
12992module_param(dbg_cmd, uint, 0664);
12993MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
12994
12995module_param(dump_nal, uint, 0664);
12996MODULE_PARM_DESC(dump_nal, "\n dump_nal\n");
12997
12998module_param(dbg_skip_decode_index, uint, 0664);
12999MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
13000
13001module_param(endian, uint, 0664);
13002MODULE_PARM_DESC(endian, "\n rval\n");
13003
13004module_param(step, uint, 0664);
13005MODULE_PARM_DESC(step, "\n amvdec_h265 step\n");
13006
13007module_param(decode_pic_begin, uint, 0664);
13008MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_h265 decode_pic_begin\n");
13009
13010module_param(slice_parse_begin, uint, 0664);
13011MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_h265 slice_parse_begin\n");
13012
13013module_param(nal_skip_policy, uint, 0664);
13014MODULE_PARM_DESC(nal_skip_policy, "\n amvdec_h265 nal_skip_policy\n");
13015
13016module_param(i_only_flag, uint, 0664);
13017MODULE_PARM_DESC(i_only_flag, "\n amvdec_h265 i_only_flag\n");
13018
13019module_param(fast_output_enable, uint, 0664);
13020MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h265 fast_output_enable\n");
13021
13022module_param(error_handle_policy, uint, 0664);
13023MODULE_PARM_DESC(error_handle_policy, "\n amvdec_h265 error_handle_policy\n");
13024
13025module_param(error_handle_threshold, uint, 0664);
13026MODULE_PARM_DESC(error_handle_threshold,
13027 "\n amvdec_h265 error_handle_threshold\n");
13028
13029module_param(error_handle_nal_skip_threshold, uint, 0664);
13030MODULE_PARM_DESC(error_handle_nal_skip_threshold,
13031 "\n amvdec_h265 error_handle_nal_skip_threshold\n");
13032
13033module_param(error_handle_system_threshold, uint, 0664);
13034MODULE_PARM_DESC(error_handle_system_threshold,
13035 "\n amvdec_h265 error_handle_system_threshold\n");
13036
13037module_param(error_skip_nal_count, uint, 0664);
13038MODULE_PARM_DESC(error_skip_nal_count,
13039 "\n amvdec_h265 error_skip_nal_count\n");
13040
13041module_param(debug, uint, 0664);
13042MODULE_PARM_DESC(debug, "\n amvdec_h265 debug\n");
13043
13044module_param(debug_mask, uint, 0664);
13045MODULE_PARM_DESC(debug_mask, "\n amvdec_h265 debug mask\n");
13046
13047module_param(log_mask, uint, 0664);
13048MODULE_PARM_DESC(log_mask, "\n amvdec_h265 log_mask\n");
13049
13050module_param(buffer_mode, uint, 0664);
13051MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
13052
13053module_param(double_write_mode, uint, 0664);
13054MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
13055
13056module_param(buf_alloc_width, uint, 0664);
13057MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
13058
13059module_param(buf_alloc_height, uint, 0664);
13060MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
13061
13062module_param(dynamic_buf_num_margin, uint, 0664);
13063MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
13064
13065module_param(max_buf_num, uint, 0664);
13066MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
13067
13068module_param(buf_alloc_size, uint, 0664);
13069MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
13070
13071#ifdef CONSTRAIN_MAX_BUF_NUM
13072module_param(run_ready_max_vf_only_num, uint, 0664);
13073MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
13074
13075module_param(run_ready_display_q_num, uint, 0664);
13076MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
13077
13078module_param(run_ready_max_buf_num, uint, 0664);
13079MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
13080#endif
13081
13082#if 0
13083module_param(re_config_pic_flag, uint, 0664);
13084MODULE_PARM_DESC(re_config_pic_flag, "\n re_config_pic_flag\n");
13085#endif
13086
13087module_param(buffer_mode_dbg, uint, 0664);
13088MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
13089
13090module_param(mem_map_mode, uint, 0664);
13091MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
13092
13093module_param(enable_mem_saving, uint, 0664);
13094MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
13095
13096module_param(force_w_h, uint, 0664);
13097MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
13098
13099module_param(force_fps, uint, 0664);
13100MODULE_PARM_DESC(force_fps, "\n force_fps\n");
13101
13102module_param(max_decoding_time, uint, 0664);
13103MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
13104
13105module_param(prefix_aux_buf_size, uint, 0664);
13106MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
13107
13108module_param(suffix_aux_buf_size, uint, 0664);
13109MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
13110
13111module_param(interlace_enable, uint, 0664);
13112MODULE_PARM_DESC(interlace_enable, "\n interlace_enable\n");
13113module_param(pts_unstable, uint, 0664);
13114MODULE_PARM_DESC(pts_unstable, "\n amvdec_h265 pts_unstable\n");
13115module_param(parser_sei_enable, uint, 0664);
13116MODULE_PARM_DESC(parser_sei_enable, "\n parser_sei_enable\n");
13117
13118#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
13119module_param(parser_dolby_vision_enable, uint, 0664);
13120MODULE_PARM_DESC(parser_dolby_vision_enable,
13121 "\n parser_dolby_vision_enable\n");
13122
13123module_param(dolby_meta_with_el, uint, 0664);
13124MODULE_PARM_DESC(dolby_meta_with_el,
13125 "\n dolby_meta_with_el\n");
13126
13127module_param(dolby_el_flush_th, uint, 0664);
13128MODULE_PARM_DESC(dolby_el_flush_th,
13129 "\n dolby_el_flush_th\n");
13130#endif
13131module_param(mmu_enable, uint, 0664);
13132MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
13133
13134module_param(mmu_enable_force, uint, 0664);
13135MODULE_PARM_DESC(mmu_enable_force, "\n mmu_enable_force\n");
13136
13137#ifdef MULTI_INSTANCE_SUPPORT
13138module_param(start_decode_buf_level, int, 0664);
13139MODULE_PARM_DESC(start_decode_buf_level,
13140 "\n h265 start_decode_buf_level\n");
13141
13142module_param(decode_timeout_val, uint, 0664);
13143MODULE_PARM_DESC(decode_timeout_val,
13144 "\n h265 decode_timeout_val\n");
13145
13146module_param(data_resend_policy, uint, 0664);
13147MODULE_PARM_DESC(data_resend_policy,
13148 "\n h265 data_resend_policy\n");
13149
13150module_param_array(decode_frame_count, uint,
13151 &max_decode_instance_num, 0664);
13152
13153module_param_array(display_frame_count, uint,
13154 &max_decode_instance_num, 0664);
13155
13156module_param_array(max_process_time, uint,
13157 &max_decode_instance_num, 0664);
13158
13159module_param_array(max_get_frame_interval,
13160 uint, &max_decode_instance_num, 0664);
13161
13162module_param_array(run_count, uint,
13163 &max_decode_instance_num, 0664);
13164
13165module_param_array(input_empty, uint,
13166 &max_decode_instance_num, 0664);
13167
13168module_param_array(not_run_ready, uint,
13169 &max_decode_instance_num, 0664);
13170
13171module_param_array(ref_frame_mark_flag, uint,
13172 &max_decode_instance_num, 0664);
13173
13174#endif
13175#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
13176module_param(dv_toggle_prov_name, uint, 0664);
13177MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
13178
13179module_param(dv_debug, uint, 0664);
13180MODULE_PARM_DESC(dv_debug, "\n dv_debug\n");
13181
13182module_param(force_bypass_dvenl, uint, 0664);
13183MODULE_PARM_DESC(force_bypass_dvenl, "\n force_bypass_dvenl\n");
13184#endif
13185
13186#ifdef AGAIN_HAS_THRESHOLD
13187module_param(again_threshold, uint, 0664);
13188MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
13189#endif
13190
13191module_param(force_disp_pic_index, int, 0664);
13192MODULE_PARM_DESC(force_disp_pic_index,
13193 "\n amvdec_h265 force_disp_pic_index\n");
13194
13195module_param(frmbase_cont_bitlevel, uint, 0664);
13196MODULE_PARM_DESC(frmbase_cont_bitlevel, "\n frmbase_cont_bitlevel\n");
13197
13198module_param(udebug_flag, uint, 0664);
13199MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
13200
13201module_param(udebug_pause_pos, uint, 0664);
13202MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
13203
13204module_param(udebug_pause_val, uint, 0664);
13205MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
13206
13207module_param(pre_decode_buf_level, int, 0664);
13208MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
13209
13210module_param(udebug_pause_decode_idx, uint, 0664);
13211MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
13212
13213module_param(disp_vframe_valve_level, uint, 0664);
13214MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
13215
13216module_param(pic_list_debug, uint, 0664);
13217MODULE_PARM_DESC(pic_list_debug, "\n pic_list_debug\n");
13218
13219module_param(without_display_mode, uint, 0664);
13220MODULE_PARM_DESC(without_display_mode, "\n amvdec_h265 without_display_mode\n");
13221
13222module_init(amvdec_h265_driver_init_module);
13223module_exit(amvdec_h265_driver_remove_module);
13224
13225MODULE_DESCRIPTION("AMLOGIC h265 Video Decoder Driver");
13226MODULE_LICENSE("GPL");
13227MODULE_AUTHOR("Tim Yao <tim.yao@amlogic.com>");
13228
generated by cgit at 2024-05-17 10:01:19 (GMT)