path: root/drivers/frame_provider/decoder/h265/vh265.c (plain)
blob: 9189564dabab8eb100d15279d29f1d01d99d527c

1	/*
2	* drivers/amlogic/amports/vh265.c
3	*
4	* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful, but WITHOUT
12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	* more details.
15	*
16	*/
17	#define DEBUG
18	#include <linux/kernel.h>
19	#include <linux/module.h>
20	#include <linux/types.h>
21	#include <linux/errno.h>
22	#include <linux/interrupt.h>
23	#include <linux/semaphore.h>
24	#include <linux/delay.h>
25	#include <linux/timer.h>
26	#include <linux/kfifo.h>
27	#include <linux/kthread.h>
28	#include <linux/platform_device.h>
29	#include <linux/amlogic/media/vfm/vframe.h>
30	#include <linux/amlogic/media/utils/amstream.h>
31	#include <linux/amlogic/media/utils/vformat.h>
32	#include <linux/amlogic/media/frame_sync/ptsserv.h>
33	#include <linux/amlogic/media/canvas/canvas.h>
34	#include <linux/amlogic/media/vfm/vframe.h>
35	#include <linux/amlogic/media/vfm/vframe_provider.h>
36	#include <linux/amlogic/media/vfm/vframe_receiver.h>
37	#include <linux/dma-mapping.h>
38	#include <linux/dma-contiguous.h>
39	#include <linux/slab.h>
40	#include <linux/mm.h>
41	#include <linux/amlogic/tee.h>
42	#include "../../../stream_input/amports/amports_priv.h"
43	#include <linux/amlogic/media/codec_mm/codec_mm.h>
44	#include "../utils/decoder_mmu_box.h"
45	#include "../utils/decoder_bmmu_box.h"
46	#include "../utils/config_parser.h"
47	#include "../utils/firmware.h"
48	#include "../../../common/chips/decoder_cpu_ver_info.h"
49	#include "../utils/vdec_v4l2_buffer_ops.h"
50
51	#define CONSTRAIN_MAX_BUF_NUM
52
53	#define SWAP_HEVC_UCODE
54	#define DETREFILL_ENABLE
55
56	#define AGAIN_HAS_THRESHOLD
57	/*#define TEST_NO_BUF*/
58	#define HEVC_PIC_STRUCT_SUPPORT
59	#define MULTI_INSTANCE_SUPPORT
60	#define USE_UNINIT_SEMA
61
62	/* .buf_size = 0x100000*16,
63	//4k2k , 0x100000 per buffer */
64	/* 4096x2304 , 0x120000 per buffer */
65	#define MPRED_8K_MV_BUF_SIZE (0x120000*4)
66	#define MPRED_4K_MV_BUF_SIZE (0x120000)
67	#define MPRED_MV_BUF_SIZE (0x40000)
68
69	#define MMU_COMPRESS_HEADER_SIZE 0x48000
70	#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
71
72	#define MAX_FRAME_4K_NUM 0x1200
73	#define MAX_FRAME_8K_NUM (0x1200*4)
74
75	//#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
76	#define H265_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7
77
78	#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
79
80	#define HEVC_CM_HEADER_START_ADDR 0x3628
81	#define HEVC_SAO_MMU_VH1_ADDR 0x363b
82	#define HEVC_SAO_MMU_VH0_ADDR 0x363a
83
84	#define HEVC_DBLK_CFGB 0x350b
85	#define HEVCD_MPP_DECOMP_AXIURG_CTL 0x34c7
86	#define SWAP_HEVC_OFFSET (3 * 0x1000)
87
88	#define MEM_NAME "codec_265"
89	/* #include <mach/am_regs.h> */
90	#include <linux/amlogic/media/utils/vdec_reg.h>
91
92	#include "../utils/vdec.h"
93	#include "../utils/amvdec.h"
94	#include <linux/amlogic/media/video_sink/video.h>
95	#include <linux/amlogic/media/codec_mm/configs.h>
96
97	#define SEND_LMEM_WITH_RPM
98	#define SUPPORT_10BIT
99	/* #define ERROR_HANDLE_DEBUG */
100
101	#ifndef STAT_KTHREAD
102	#define STAT_KTHREAD 0x40
103	#endif
104
105	#ifdef MULTI_INSTANCE_SUPPORT
106	#define MAX_DECODE_INSTANCE_NUM 9
107	#define MULTI_DRIVER_NAME "ammvdec_h265"
108	#endif
109	#define DRIVER_NAME "amvdec_h265"
110	#define MODULE_NAME "amvdec_h265"
111	#define DRIVER_HEADER_NAME "amvdec_h265_header"
112
113	#define PUT_INTERVAL (HZ/100)
114	#define ERROR_SYSTEM_RESET_COUNT 200
115
116	#define PTS_NORMAL 0
117	#define PTS_NONE_REF_USE_DURATION 1
118
119	#define PTS_MODE_SWITCHING_THRESHOLD 3
120	#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
121
122	#define DUR2PTS(x) ((x)*90/96)
123
124	#define MAX_SIZE_8K (8192 * 4608)
125	#define MAX_SIZE_4K (4096 * 2304)
126
127	#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
128	#define IS_4K_SIZE(w, h) (((w) * (h)) > (1920*1088))
129
130	#define SEI_UserDataITU_T_T35 4
131	#define INVALID_IDX -1 /* Invalid buffer index.*/
132
133	static struct semaphore h265_sema;
134
135	struct hevc_state_s;
136	static int hevc_print(struct hevc_state_s *hevc,
137	int debug_flag, const char *fmt, ...);
138	static int hevc_print_cont(struct hevc_state_s *hevc,
139	int debug_flag, const char *fmt, ...);
140	static int vh265_vf_states(struct vframe_states *states, void *);
141	static struct vframe_s *vh265_vf_peek(void *);
142	static struct vframe_s *vh265_vf_get(void *);
143	static void vh265_vf_put(struct vframe_s *, void *);
144	static int vh265_event_cb(int type, void *data, void *private_data);
145
146	static int vh265_stop(struct hevc_state_s *hevc);
147	#ifdef MULTI_INSTANCE_SUPPORT
148	static int vmh265_stop(struct hevc_state_s *hevc);
149	static s32 vh265_init(struct vdec_s *vdec);
150	static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask);
151	static void reset_process_time(struct hevc_state_s *hevc);
152	static void start_process_time(struct hevc_state_s *hevc);
153	static void restart_process_time(struct hevc_state_s *hevc);
154	static void timeout_process(struct hevc_state_s *hevc);
155	#else
156	static s32 vh265_init(struct hevc_state_s *hevc);
157	#endif
158	static void vh265_prot_init(struct hevc_state_s *hevc);
159	static int vh265_local_init(struct hevc_state_s *hevc);
160	static void vh265_check_timer_func(unsigned long arg);
161	static void config_decode_mode(struct hevc_state_s *hevc);
162
163	static const char vh265_dec_id[] = "vh265-dev";
164
165	#define PROVIDER_NAME "decoder.h265"
166	#define MULTI_INSTANCE_PROVIDER_NAME "vdec.h265"
167
168	static const struct vframe_operations_s vh265_vf_provider = {
169	.peek = vh265_vf_peek,
170	.get = vh265_vf_get,
171	.put = vh265_vf_put,
172	.event_cb = vh265_event_cb,
173	.vf_states = vh265_vf_states,
174	};
175
176	static struct vframe_provider_s vh265_vf_prov;
177
178	static u32 bit_depth_luma;
179	static u32 bit_depth_chroma;
180	static u32 video_signal_type;
181
182	static int start_decode_buf_level = 0x8000;
183
184	static unsigned int decode_timeout_val = 200;
185
186	/*data_resend_policy:
187	bit 0, stream base resend data when decoding buf empty
188	*/
189	static u32 data_resend_policy = 1;
190
191	#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
192	/*
193	static const char * const video_format_names[] = {
194	"component", "PAL", "NTSC", "SECAM",
195	"MAC", "unspecified", "unspecified", "unspecified"
196	};
197
198	static const char * const color_primaries_names[] = {
199	"unknown", "bt709", "undef", "unknown",
200	"bt470m", "bt470bg", "smpte170m", "smpte240m",
201	"film", "bt2020"
202	};
203
204	static const char * const transfer_characteristics_names[] = {
205	"unknown", "bt709", "undef", "unknown",
206	"bt470m", "bt470bg", "smpte170m", "smpte240m",
207	"linear", "log100", "log316", "iec61966-2-4",
208	"bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12",
209	"smpte-st-2084", "smpte-st-428"
210	};
211
212	static const char * const matrix_coeffs_names[] = {
213	"GBR", "bt709", "undef", "unknown",
214	"fcc", "bt470bg", "smpte170m", "smpte240m",
215	"YCgCo", "bt2020nc", "bt2020c"
216	};
217	*/
218	#ifdef SUPPORT_10BIT
219	#define HEVC_CM_BODY_START_ADDR 0x3626
220	#define HEVC_CM_BODY_LENGTH 0x3627
221	#define HEVC_CM_HEADER_LENGTH 0x3629
222	#define HEVC_CM_HEADER_OFFSET 0x362b
223	#define HEVC_SAO_CTRL9 0x362d
224	#define LOSLESS_COMPRESS_MODE
225	/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
226	/* double_write_mode:
227	* 0, no double write;
228	* 1, 1:1 ratio;
229	* 2, (1/4):(1/4) ratio;
230	* 3, (1/4):(1/4) ratio, with both compressed frame included
231	* 4, (1/2):(1/2) ratio;
232	* 0x10, double write only
233	* 0x100, if > 1080p,use mode 4,else use mode 1;
234	* 0x200, if > 1080p,use mode 2,else use mode 1;
235	* 0x300, if > 720p, use mode 4, else use mode 1;
236	*/
237	static u32 double_write_mode;
238
239	/*#define DECOMP_HEADR_SURGENT*/
240
241	static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
242	static u32 enable_mem_saving = 1;
243	static u32 workaround_enable;
244	static u32 force_w_h;
245	#endif
246	static u32 force_fps;
247	static u32 pts_unstable;
248	#define H265_DEBUG_BUFMGR 0x01
249	#define H265_DEBUG_BUFMGR_MORE 0x02
250	#define H265_DEBUG_DETAIL 0x04
251	#define H265_DEBUG_REG 0x08
252	#define H265_DEBUG_MAN_SEARCH_NAL 0x10
253	#define H265_DEBUG_MAN_SKIP_NAL 0x20
254	#define H265_DEBUG_DISPLAY_CUR_FRAME 0x40
255	#define H265_DEBUG_FORCE_CLK 0x80
256	#define H265_DEBUG_SEND_PARAM_WITH_REG 0x100
257	#define H265_DEBUG_NO_DISPLAY 0x200
258	#define H265_DEBUG_DISCARD_NAL 0x400
259	#define H265_DEBUG_OUT_PTS 0x800
260	#define H265_DEBUG_DUMP_PIC_LIST 0x1000
261	#define H265_DEBUG_PRINT_SEI 0x2000
262	#define H265_DEBUG_PIC_STRUCT 0x4000
263	#define H265_DEBUG_HAS_AUX_IN_SLICE 0x8000
264	#define H265_DEBUG_DIS_LOC_ERROR_PROC 0x10000
265	#define H265_DEBUG_DIS_SYS_ERROR_PROC 0x20000
266	#define H265_NO_CHANG_DEBUG_FLAG_IN_CODE 0x40000
267	#define H265_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
268	#define H265_DEBUG_HW_RESET 0x100000
269	#define H265_CFG_CANVAS_IN_DECODE 0x200000
270	#define H265_DEBUG_DV 0x400000
271	#define H265_DEBUG_NO_EOS_SEARCH_DONE 0x800000
272	#define H265_DEBUG_NOT_USE_LAST_DISPBUF 0x1000000
273	#define H265_DEBUG_IGNORE_CONFORMANCE_WINDOW 0x2000000
274	#define H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP 0x4000000
275	#ifdef MULTI_INSTANCE_SUPPORT
276	#define PRINT_FLAG_ERROR 0x0
277	#define IGNORE_PARAM_FROM_CONFIG 0x08000000
278	#define PRINT_FRAMEBASE_DATA 0x10000000
279	#define PRINT_FLAG_VDEC_STATUS 0x20000000
280	#define PRINT_FLAG_VDEC_DETAIL 0x40000000
281	#define PRINT_FLAG_V4L_DETAIL 0x80000000
282	#endif
283
284	#define BUF_POOL_SIZE 32
285	#define MAX_BUF_NUM 24
286	#define MAX_REF_PIC_NUM 24
287	#define MAX_REF_ACTIVE 16
288
289	#ifdef MV_USE_FIXED_BUF
290	#define BMMU_MAX_BUFFERS (BUF_POOL_SIZE + 1)
291	#define VF_BUFFER_IDX(n) (n)
292	#define BMMU_WORKSPACE_ID (BUF_POOL_SIZE)
293	#else
294	#define BMMU_MAX_BUFFERS (BUF_POOL_SIZE + 1 + MAX_REF_PIC_NUM)
295	#define VF_BUFFER_IDX(n) (n)
296	#define BMMU_WORKSPACE_ID (BUF_POOL_SIZE)
297	#define MV_BUFFER_IDX(n) (BUF_POOL_SIZE + 1 + n)
298	#endif
299
300	#define HEVC_MV_INFO 0x310d
301	#define HEVC_QP_INFO 0x3137
302	#define HEVC_SKIP_INFO 0x3136
303
304	const u32 h265_version = 201602101;
305	static u32 debug_mask = 0xffffffff;
306	static u32 log_mask;
307	static u32 debug;
308	static u32 radr;
309	static u32 rval;
310	static u32 dbg_cmd;
311	static u32 dump_nal;
312	static u32 dbg_skip_decode_index;
313	static u32 endian = 0xff0;
314	#ifdef ERROR_HANDLE_DEBUG
315	static u32 dbg_nal_skip_flag;
316	/* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
317	static u32 dbg_nal_skip_count;
318	#endif
319	/*for debug*/
320	/*
321	udebug_flag:
322	bit 0, enable ucode print
323	bit 1, enable ucode detail print
324	bit [31:16] not 0, pos to dump lmem
325	bit 2, pop bits to lmem
326	bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
327	*/
328	static u32 udebug_flag;
329	/*
330	when udebug_flag[1:0] is not 0
331	udebug_pause_pos not 0,
332	pause position
333	*/
334	static u32 udebug_pause_pos;
335	/*
336	when udebug_flag[1:0] is not 0
337	and udebug_pause_pos is not 0,
338	pause only when DEBUG_REG2 is equal to this val
339	*/
340	static u32 udebug_pause_val;
341
342	static u32 udebug_pause_decode_idx;
343
344	static u32 decode_pic_begin;
345	static uint slice_parse_begin;
346	static u32 step;
347	static bool is_reset;
348
349	#ifdef CONSTRAIN_MAX_BUF_NUM
350	static u32 run_ready_max_vf_only_num;
351	static u32 run_ready_display_q_num;
352	/*0: not check
353	0xff: work_pic_num
354	*/
355	static u32 run_ready_max_buf_num = 0xff;
356	#endif
357
358	static u32 dynamic_buf_num_margin = 7;
359	static u32 buf_alloc_width;
360	static u32 buf_alloc_height;
361
362	static u32 max_buf_num = 16;
363	static u32 buf_alloc_size;
364	/*static u32 re_config_pic_flag;*/
365	/*
366	*bit[0]: 0,
367	*bit[1]: 0, always release cma buffer when stop
368	*bit[1]: 1, never release cma buffer when stop
369	*bit[0]: 1, when stop, release cma buffer if blackout is 1;
370	*do not release cma buffer is blackout is not 1
371	*
372	*bit[2]: 0, when start decoding, check current displayed buffer
373	* (only for buffer decoded by h265) if blackout is 0
374	* 1, do not check current displayed buffer
375	*
376	*bit[3]: 1, if blackout is not 1, do not release current
377	* displayed cma buffer always.
378	*/
379	/* set to 1 for fast play;
380	* set to 8 for other case of "keep last frame"
381	*/
382	static u32 buffer_mode = 1;
383
384	/* buffer_mode_dbg: debug only*/
385	static u32 buffer_mode_dbg = 0xffff0000;
386	/**/
387	/*
388	*bit[1:0]PB_skip_mode: 0, start decoding at begin;
389	*1, start decoding after first I;
390	*2, only decode and display none error picture;
391	*3, start decoding and display after IDR,etc
392	*bit[31:16] PB_skip_count_after_decoding (decoding but not display),
393	*only for mode 0 and 1.
394	*/
395	static u32 nal_skip_policy = 2;
396
397	/*
398	*bit 0, 1: only display I picture;
399	*bit 1, 1: only decode I picture;
400	*/
401	static u32 i_only_flag;
402
403	/*
404	bit 0, fast output first I picture
405	*/
406	static u32 fast_output_enable = 1;
407
408	static u32 frmbase_cont_bitlevel = 0x60;
409
410	/*
411	use_cma: 1, use both reserver memory and cma for buffers
412	2, only use cma for buffers
413	*/
414	static u32 use_cma = 2;
415
416	#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf))
417	static u32 prefix_aux_buf_size = (16 * 1024);
418	static u32 suffix_aux_buf_size;
419
420	static u32 max_decoding_time;
421	/*
422	*error handling
423	*/
424	/*error_handle_policy:
425	*bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
426	*1, skip error_skip_nal_count nals before error recovery;
427	*bit 1 (valid only when bit0 == 1):
428	*1, wait vps/sps/pps after error recovery;
429	*bit 2 (valid only when bit0 == 0):
430	*0, auto search after error recovery (hevc_recover() called);
431	*1, manual search after error recovery
432	*(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
433	*
434	*bit 4: 0, set error_mark after reset/recover
435	* 1, do not set error_mark after reset/recover
436	*bit 5: 0, check total lcu for every picture
437	* 1, do not check total lcu
438	*bit 6: 0, do not check head error
439	* 1, check head error
440	*
441	*/
442
443	static u32 error_handle_policy;
444	static u32 error_skip_nal_count = 6;
445	static u32 error_handle_threshold = 30;
446	static u32 error_handle_nal_skip_threshold = 10;
447	static u32 error_handle_system_threshold = 30;
448	static u32 interlace_enable = 1;
449	static u32 fr_hint_status;
450
451	/*
452	*parser_sei_enable:
453	* bit 0, sei;
454	* bit 1, sei_suffix (fill aux buf)
455	* bit 2, fill sei to aux buf (when bit 0 is 1)
456	* bit 8, debug flag
457	*/
458	static u32 parser_sei_enable;
459	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
460	static u32 parser_dolby_vision_enable = 1;
461	static u32 dolby_meta_with_el;
462	static u32 dolby_el_flush_th = 2;
463	#endif
464	/* this is only for h265 mmu enable */
465
466	static u32 mmu_enable = 1;
467	static u32 mmu_enable_force;
468	static u32 work_buf_size;
469	static unsigned int force_disp_pic_index;
470	static unsigned int disp_vframe_valve_level;
471	static int pre_decode_buf_level = 0x1000;
472	static unsigned int pic_list_debug;
473
474
475	#ifdef MULTI_INSTANCE_SUPPORT
476	static unsigned int max_decode_instance_num
477	= MAX_DECODE_INSTANCE_NUM;
478	static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
479	static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
480	static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
481	static unsigned int max_get_frame_interval[MAX_DECODE_INSTANCE_NUM];
482	static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
483	static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
484	static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
485	static unsigned int ref_frame_mark_flag[MAX_DECODE_INSTANCE_NUM] =
486	{1, 1, 1, 1, 1, 1, 1, 1, 1};
487
488	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
489	static unsigned char get_idx(struct hevc_state_s *hevc);
490	#endif
491
492	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
493	static u32 dv_toggle_prov_name;
494
495	static u32 dv_debug;
496
497	static u32 force_bypass_dvenl;
498	#endif
499	#endif
500
501
502	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
503	#define get_dbg_flag(hevc) ((debug_mask & (1 << hevc->index)) ? debug : 0)
504	#define get_dbg_flag2(hevc) ((debug_mask & (1 << get_idx(hevc))) ? debug : 0)
505	#define is_log_enable(hevc) ((log_mask & (1 << hevc->index)) ? 1 : 0)
506	#else
507	#define get_dbg_flag(hevc) debug
508	#define get_dbg_flag2(hevc) debug
509	#define is_log_enable(hevc) (log_mask ? 1 : 0)
510	#define get_valid_double_write_mode(hevc) double_write_mode
511	#define get_buf_alloc_width(hevc) buf_alloc_width
512	#define get_buf_alloc_height(hevc) buf_alloc_height
513	#define get_dynamic_buf_num_margin(hevc) dynamic_buf_num_margin
514	#endif
515	#define get_buffer_mode(hevc) buffer_mode
516
517
518	DEFINE_SPINLOCK(lock);
519	struct task_struct *h265_task = NULL;
520	#undef DEBUG_REG
521	#ifdef DEBUG_REG
522	void WRITE_VREG_DBG(unsigned adr, unsigned val)
523	{
524	if (debug & H265_DEBUG_REG)
525	pr_info("%s(%x, %x)\n", __func__, adr, val);
526	WRITE_VREG(adr, val);
527	}
528
529	#undef WRITE_VREG
530	#define WRITE_VREG WRITE_VREG_DBG
531	#endif
532
533	static DEFINE_MUTEX(vh265_mutex);
534
535	static DEFINE_MUTEX(vh265_log_mutex);
536
537	static struct vdec_info *gvs;
538
539	static u32 without_display_mode;
540
541	/**************************************************
542	*
543	*h265 buffer management include
544	*
545	***************************************************
546	*/
547	enum NalUnitType {
548	NAL_UNIT_CODED_SLICE_TRAIL_N = 0, /* 0 */
549	NAL_UNIT_CODED_SLICE_TRAIL_R, /* 1 */
550
551	NAL_UNIT_CODED_SLICE_TSA_N, /* 2 */
552	/* Current name in the spec: TSA_R */
553	NAL_UNIT_CODED_SLICE_TLA, /* 3 */
554
555	NAL_UNIT_CODED_SLICE_STSA_N, /* 4 */
556	NAL_UNIT_CODED_SLICE_STSA_R, /* 5 */
557
558	NAL_UNIT_CODED_SLICE_RADL_N, /* 6 */
559	/* Current name in the spec: RADL_R */
560	NAL_UNIT_CODED_SLICE_DLP, /* 7 */
561
562	NAL_UNIT_CODED_SLICE_RASL_N, /* 8 */
563	/* Current name in the spec: RASL_R */
564	NAL_UNIT_CODED_SLICE_TFD, /* 9 */
565
566	NAL_UNIT_RESERVED_10,
567	NAL_UNIT_RESERVED_11,
568	NAL_UNIT_RESERVED_12,
569	NAL_UNIT_RESERVED_13,
570	NAL_UNIT_RESERVED_14,
571	NAL_UNIT_RESERVED_15,
572
573	/* Current name in the spec: BLA_W_LP */
574	NAL_UNIT_CODED_SLICE_BLA, /* 16 */
575	/* Current name in the spec: BLA_W_DLP */
576	NAL_UNIT_CODED_SLICE_BLANT, /* 17 */
577	NAL_UNIT_CODED_SLICE_BLA_N_LP, /* 18 */
578	/* Current name in the spec: IDR_W_DLP */
579	NAL_UNIT_CODED_SLICE_IDR, /* 19 */
580	NAL_UNIT_CODED_SLICE_IDR_N_LP, /* 20 */
581	NAL_UNIT_CODED_SLICE_CRA, /* 21 */
582	NAL_UNIT_RESERVED_22,
583	NAL_UNIT_RESERVED_23,
584
585	NAL_UNIT_RESERVED_24,
586	NAL_UNIT_RESERVED_25,
587	NAL_UNIT_RESERVED_26,
588	NAL_UNIT_RESERVED_27,
589	NAL_UNIT_RESERVED_28,
590	NAL_UNIT_RESERVED_29,
591	NAL_UNIT_RESERVED_30,
592	NAL_UNIT_RESERVED_31,
593
594	NAL_UNIT_VPS, /* 32 */
595	NAL_UNIT_SPS, /* 33 */
596	NAL_UNIT_PPS, /* 34 */
597	NAL_UNIT_ACCESS_UNIT_DELIMITER, /* 35 */
598	NAL_UNIT_EOS, /* 36 */
599	NAL_UNIT_EOB, /* 37 */
600	NAL_UNIT_FILLER_DATA, /* 38 */
601	NAL_UNIT_SEI, /* 39 Prefix SEI */
602	NAL_UNIT_SEI_SUFFIX, /* 40 Suffix SEI */
603	NAL_UNIT_RESERVED_41,
604	NAL_UNIT_RESERVED_42,
605	NAL_UNIT_RESERVED_43,
606	NAL_UNIT_RESERVED_44,
607	NAL_UNIT_RESERVED_45,
608	NAL_UNIT_RESERVED_46,
609	NAL_UNIT_RESERVED_47,
610	NAL_UNIT_UNSPECIFIED_48,
611	NAL_UNIT_UNSPECIFIED_49,
612	NAL_UNIT_UNSPECIFIED_50,
613	NAL_UNIT_UNSPECIFIED_51,
614	NAL_UNIT_UNSPECIFIED_52,
615	NAL_UNIT_UNSPECIFIED_53,
616	NAL_UNIT_UNSPECIFIED_54,
617	NAL_UNIT_UNSPECIFIED_55,
618	NAL_UNIT_UNSPECIFIED_56,
619	NAL_UNIT_UNSPECIFIED_57,
620	NAL_UNIT_UNSPECIFIED_58,
621	NAL_UNIT_UNSPECIFIED_59,
622	NAL_UNIT_UNSPECIFIED_60,
623	NAL_UNIT_UNSPECIFIED_61,
624	NAL_UNIT_UNSPECIFIED_62,
625	NAL_UNIT_UNSPECIFIED_63,
626	NAL_UNIT_INVALID,
627	};
628
629	/* --------------------------------------------------- */
630	/* Amrisc Software Interrupt */
631	/* --------------------------------------------------- */
632	#define AMRISC_STREAM_EMPTY_REQ 0x01
633	#define AMRISC_PARSER_REQ 0x02
634	#define AMRISC_MAIN_REQ 0x04
635
636	/* --------------------------------------------------- */
637	/* HEVC_DEC_STATUS define */
638	/* --------------------------------------------------- */
639	#define HEVC_DEC_IDLE 0x0
640	#define HEVC_NAL_UNIT_VPS 0x1
641	#define HEVC_NAL_UNIT_SPS 0x2
642	#define HEVC_NAL_UNIT_PPS 0x3
643	#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT 0x4
644	#define HEVC_CODED_SLICE_SEGMENT_DAT 0x5
645	#define HEVC_SLICE_DECODING 0x6
646	#define HEVC_NAL_UNIT_SEI 0x7
647	#define HEVC_SLICE_SEGMENT_DONE 0x8
648	#define HEVC_NAL_SEARCH_DONE 0x9
649	#define HEVC_DECPIC_DATA_DONE 0xa
650	#define HEVC_DECPIC_DATA_ERROR 0xb
651	#define HEVC_SEI_DAT 0xc
652	#define HEVC_SEI_DAT_DONE 0xd
653	#define HEVC_NAL_DECODE_DONE 0xe
654	#define HEVC_OVER_DECODE 0xf
655
656	#define HEVC_DATA_REQUEST 0x12
657
658	#define HEVC_DECODE_BUFEMPTY 0x20
659	#define HEVC_DECODE_TIMEOUT 0x21
660	#define HEVC_SEARCH_BUFEMPTY 0x22
661	#define HEVC_DECODE_OVER_SIZE 0x23
662	#define HEVC_DECODE_BUFEMPTY2 0x24
663	#define HEVC_FIND_NEXT_PIC_NAL 0x50
664	#define HEVC_FIND_NEXT_DVEL_NAL 0x51
665
666	#define HEVC_DUMP_LMEM 0x30
667
668	#define HEVC_4k2k_60HZ_NOT_SUPPORT 0x80
669	#define HEVC_DISCARD_NAL 0xf0
670	#define HEVC_ACTION_DEC_CONT 0xfd
671	#define HEVC_ACTION_ERROR 0xfe
672	#define HEVC_ACTION_DONE 0xff
673
674	/* --------------------------------------------------- */
675	/* Include "parser_cmd.h" */
676	/* --------------------------------------------------- */
677	#define PARSER_CMD_SKIP_CFG_0 0x0000090b
678
679	#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
680
681	#define PARSER_CMD_SKIP_CFG_2 0x001b1910
682
683	#define PARSER_CMD_NUMBER 37
684
685	/**************************************************
686	*
687	*h265 buffer management
688	*
689	***************************************************
690	*/
691	/* #define BUFFER_MGR_ONLY */
692	/* #define CONFIG_HEVC_CLK_FORCED_ON */
693	/* #define ENABLE_SWAP_TEST */
694	#define MCRCC_ENABLE
695	#define INVALID_POC 0x80000000
696
697	#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
698	#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
699	#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
700	#define HEVC_VPS_BUFFER HEVC_ASSIST_SCRATCH_3
701	#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4
702	#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
703	#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
704	#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
705	#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
706	#define HEVC_sao_mem_unit HEVC_ASSIST_SCRATCH_9
707	#define HEVC_SAO_ABV HEVC_ASSIST_SCRATCH_A
708	#define HEVC_sao_vb_size HEVC_ASSIST_SCRATCH_B
709	#define HEVC_SAO_VB HEVC_ASSIST_SCRATCH_C
710	#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
711	#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
712	#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
713	#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
714	#ifdef ENABLE_SWAP_TEST
715	#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
716	#endif
717
718	/*#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M*/
719	/*#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N*/
720	#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
721	/*do not define ENABLE_SWAP_TEST*/
722	#define HEVC_AUX_ADR HEVC_ASSIST_SCRATCH_L
723	#define HEVC_AUX_DATA_SIZE HEVC_ASSIST_SCRATCH_M
724
725	#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
726	#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
727	/*
728	*ucode parser/search control
729	*bit 0: 0, header auto parse; 1, header manual parse
730	*bit 1: 0, auto skip for noneseamless stream; 1, no skip
731	*bit [3:2]: valid when bit1==0;
732	*0, auto skip nal before first vps/sps/pps/idr;
733	*1, auto skip nal before first vps/sps/pps
734	*2, auto skip nal before first vps/sps/pps,
735	* and not decode until the first I slice (with slice address of 0)
736	*
737	*3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
738	*bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
739	*bit [16]: for NAL_UNIT_EOS when bit0 is 0:
740	* 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
741	*bit [17]: for NAL_SEI when bit0 is 0:
742	* 0, do not parse/fetch SEI in ucode;
743	* 1, parse/fetch SEI in ucode
744	*bit [18]: for NAL_SEI_SUFFIX when bit0 is 0:
745	* 0, do not fetch NAL_SEI_SUFFIX to aux buf;
746	* 1, fetch NAL_SEL_SUFFIX data to aux buf
747	*bit [19]:
748	* 0, parse NAL_SEI in ucode
749	* 1, fetch NAL_SEI to aux buf
750	*bit [20]: for DOLBY_VISION_META
751	* 0, do not fetch DOLBY_VISION_META to aux buf
752	* 1, fetch DOLBY_VISION_META to aux buf
753	*/
754	#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
755	/*read only*/
756	#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J
757	/*
758	[15 : 8] rps_set_id
759	[7 : 0] start_decoding_flag
760	*/
761	#define HEVC_DECODE_INFO HEVC_ASSIST_SCRATCH_1
762	/*set before start decoder*/
763	#define HEVC_DECODE_MODE HEVC_ASSIST_SCRATCH_J
764	#define HEVC_DECODE_MODE2 HEVC_ASSIST_SCRATCH_H
765	#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
766
767	#define DECODE_MODE_SINGLE 0x0
768	#define DECODE_MODE_MULTI_FRAMEBASE 0x1
769	#define DECODE_MODE_MULTI_STREAMBASE 0x2
770	#define DECODE_MODE_MULTI_DVBAL 0x3
771	#define DECODE_MODE_MULTI_DVENL 0x4
772
773	#define MAX_INT 0x7FFFFFFF
774
775	#define RPM_BEGIN 0x100
776	#define modification_list_cur 0x148
777	#define RPM_END 0x180
778
779	#define RPS_USED_BIT 14
780	/* MISC_FLAG0 */
781	#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT 0
782	#define PCM_ENABLE_FLAG_BIT 1
783	#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT 2
784	#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 3
785	#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT 4
786	#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 5
787	#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT 6
788	#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 7
789	#define SLICE_SAO_LUMA_FLAG_BIT 8
790	#define SLICE_SAO_CHROMA_FLAG_BIT 9
791	#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10
792
793	union param_u {
794	struct {
795	unsigned short data[RPM_END - RPM_BEGIN];
796	} l;
797	struct {
798	/* from ucode lmem, do not change this struct */
799	unsigned short CUR_RPS[0x10];
800	unsigned short num_ref_idx_l0_active;
801	unsigned short num_ref_idx_l1_active;
802	unsigned short slice_type;
803	unsigned short slice_temporal_mvp_enable_flag;
804	unsigned short dependent_slice_segment_flag;
805	unsigned short slice_segment_address;
806	unsigned short num_title_rows_minus1;
807	unsigned short pic_width_in_luma_samples;
808	unsigned short pic_height_in_luma_samples;
809	unsigned short log2_min_coding_block_size_minus3;
810	unsigned short log2_diff_max_min_coding_block_size;
811	unsigned short log2_max_pic_order_cnt_lsb_minus4;
812	unsigned short POClsb;
813	unsigned short collocated_from_l0_flag;
814	unsigned short collocated_ref_idx;
815	unsigned short log2_parallel_merge_level;
816	unsigned short five_minus_max_num_merge_cand;
817	unsigned short sps_num_reorder_pics_0;
818	unsigned short modification_flag;
819	unsigned short tiles_enabled_flag;
820	unsigned short num_tile_columns_minus1;
821	unsigned short num_tile_rows_minus1;
822	unsigned short tile_width[8];
823	unsigned short tile_height[8];
824	unsigned short misc_flag0;
825	unsigned short pps_beta_offset_div2;
826	unsigned short pps_tc_offset_div2;
827	unsigned short slice_beta_offset_div2;
828	unsigned short slice_tc_offset_div2;
829	unsigned short pps_cb_qp_offset;
830	unsigned short pps_cr_qp_offset;
831	unsigned short first_slice_segment_in_pic_flag;
832	unsigned short m_temporalId;
833	unsigned short m_nalUnitType;
834
835	unsigned short vui_num_units_in_tick_hi;
836	unsigned short vui_num_units_in_tick_lo;
837	unsigned short vui_time_scale_hi;
838	unsigned short vui_time_scale_lo;
839	unsigned short bit_depth;
840	unsigned short profile_etc;
841	unsigned short sei_frame_field_info;
842	unsigned short video_signal_type;
843	unsigned short modification_list[0x20];
844	unsigned short conformance_window_flag;
845	unsigned short conf_win_left_offset;
846	unsigned short conf_win_right_offset;
847	unsigned short conf_win_top_offset;
848	unsigned short conf_win_bottom_offset;
849	unsigned short chroma_format_idc;
850	unsigned short color_description;
851	unsigned short aspect_ratio_idc;
852	unsigned short sar_width;
853	unsigned short sar_height;
854	unsigned short sps_max_dec_pic_buffering_minus1_0;
855	} p;
856	};
857
858	#define RPM_BUF_SIZE (0x80*2)
859	/* non mmu mode lmem size : 0x400, mmu mode : 0x500*/
860	#define LMEM_BUF_SIZE (0x500 * 2)
861
862	struct buff_s {
863	u32 buf_start;
864	u32 buf_size;
865	u32 buf_end;
866	};
867
868	struct BuffInfo_s {
869	u32 max_width;
870	u32 max_height;
871	unsigned int start_adr;
872	unsigned int end_adr;
873	struct buff_s ipp;
874	struct buff_s sao_abv;
875	struct buff_s sao_vb;
876	struct buff_s short_term_rps;
877	struct buff_s vps;
878	struct buff_s sps;
879	struct buff_s pps;
880	struct buff_s sao_up;
881	struct buff_s swap_buf;
882	struct buff_s swap_buf2;
883	struct buff_s scalelut;
884	struct buff_s dblk_para;
885	struct buff_s dblk_data;
886	struct buff_s dblk_data2;
887	struct buff_s mmu_vbh;
888	struct buff_s cm_header;
889	struct buff_s mpred_above;
890	#ifdef MV_USE_FIXED_BUF
891	struct buff_s mpred_mv;
892	#endif
893	struct buff_s rpm;
894	struct buff_s lmem;
895	};
896	#define WORK_BUF_SPEC_NUM 3
897	static struct BuffInfo_s amvh265_workbuff_spec[WORK_BUF_SPEC_NUM] = {
898	{
899	/* 8M bytes */
900	.max_width = 1920,
901	.max_height = 1088,
902	.ipp = {
903	/* IPP work space calculation :
904	* 4096 * (Y+CbCr+Flags) = 12k, round to 16k
905	*/
906	.buf_size = 0x4000,
907	},
908	.sao_abv = {
909	.buf_size = 0x30000,
910	},
911	.sao_vb = {
912	.buf_size = 0x30000,
913	},
914	.short_term_rps = {
915	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
916	* total 64x16x2 = 2048 bytes (0x800)
917	*/
918	.buf_size = 0x800,
919	},
920	.vps = {
921	/* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
922	* total 0x0800 bytes
923	*/
924	.buf_size = 0x800,
925	},
926	.sps = {
927	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
928	* total 0x0800 bytes
929	*/
930	.buf_size = 0x800,
931	},
932	.pps = {
933	/* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
934	* total 0x2000 bytes
935	*/
936	.buf_size = 0x2000,
937	},
938	.sao_up = {
939	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
940	* each has 16 bytes total 0x2800 bytes
941	*/
942	.buf_size = 0x2800,
943	},
944	.swap_buf = {
945	/* 256cyclex64bit = 2K bytes 0x800
946	* (only 144 cycles valid)
947	*/
948	.buf_size = 0x800,
949	},
950	.swap_buf2 = {
951	.buf_size = 0x800,
952	},
953	.scalelut = {
954	/* support up to 32 SCALELUT 1024x32 =
955	* 32Kbytes (0x8000)
956	*/
957	.buf_size = 0x8000,
958	},
959	.dblk_para = {
960	#ifdef SUPPORT_10BIT
961	.buf_size = 0x40000,
962	#else
963	/* DBLK -> Max 256(4096/16) LCU, each para
964	*512bytes(total:0x20000), data 1024bytes(total:0x40000)
965	*/
966	.buf_size = 0x20000,
967	#endif
968	},
969	.dblk_data = {
970	.buf_size = 0x40000,
971	},
972	.dblk_data2 = {
973	.buf_size = 0x40000,
974	}, /*dblk data for adapter*/
975	.mmu_vbh = {
976	.buf_size = 0x5000, /*2*16*2304/4, 4K*/
977	},
978	#if 0
979	.cm_header = {/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
980	.buf_size = MMU_COMPRESS_HEADER_SIZE *
981	(MAX_REF_PIC_NUM + 1),
982	},
983	#endif
984	.mpred_above = {
985	.buf_size = 0x8000,
986	},
987	#ifdef MV_USE_FIXED_BUF
988	.mpred_mv = {/* 1080p, 0x40000 per buffer */
989	.buf_size = 0x40000 * MAX_REF_PIC_NUM,
990	},
991	#endif
992	.rpm = {
993	.buf_size = RPM_BUF_SIZE,
994	},
995	.lmem = {
996	.buf_size = 0x500 * 2,
997	}
998	},
999	{
1000	.max_width = 4096,
1001	.max_height = 2048,
1002	.ipp = {
1003	/* IPP work space calculation :
1004	* 4096 * (Y+CbCr+Flags) = 12k, round to 16k
1005	*/
1006	.buf_size = 0x4000,
1007	},
1008	.sao_abv = {
1009	.buf_size = 0x30000,
1010	},
1011	.sao_vb = {
1012	.buf_size = 0x30000,
1013	},
1014	.short_term_rps = {
1015	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
1016	* total 64x16x2 = 2048 bytes (0x800)
1017	*/
1018	.buf_size = 0x800,
1019	},
1020	.vps = {
1021	/* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
1022	* total 0x0800 bytes
1023	*/
1024	.buf_size = 0x800,
1025	},
1026	.sps = {
1027	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
1028	* total 0x0800 bytes
1029	*/
1030	.buf_size = 0x800,
1031	},
1032	.pps = {
1033	/* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
1034	* total 0x2000 bytes
1035	*/
1036	.buf_size = 0x2000,
1037	},
1038	.sao_up = {
1039	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
1040	* each has 16 bytes total 0x2800 bytes
1041	*/
1042	.buf_size = 0x2800,
1043	},
1044	.swap_buf = {
1045	/* 256cyclex64bit = 2K bytes 0x800
1046	* (only 144 cycles valid)
1047	*/
1048	.buf_size = 0x800,
1049	},
1050	.swap_buf2 = {
1051	.buf_size = 0x800,
1052	},
1053	.scalelut = {
1054	/* support up to 32 SCALELUT 1024x32 = 32Kbytes
1055	* (0x8000)
1056	*/
1057	.buf_size = 0x8000,
1058	},
1059	.dblk_para = {
1060	/* DBLK -> Max 256(4096/16) LCU, each para
1061	* 512bytes(total:0x20000),
1062	* data 1024bytes(total:0x40000)
1063	*/
1064	.buf_size = 0x20000,
1065	},
1066	.dblk_data = {
1067	.buf_size = 0x80000,
1068	},
1069	.dblk_data2 = {
1070	.buf_size = 0x80000,
1071	}, /*dblk data for adapter*/
1072	.mmu_vbh = {
1073	.buf_size = 0x5000, /*2*16*2304/4, 4K*/
1074	},
1075	#if 0
1076	.cm_header = {/*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
1077	.buf_size = MMU_COMPRESS_HEADER_SIZE *
1078	(MAX_REF_PIC_NUM + 1),
1079	},
1080	#endif
1081	.mpred_above = {
1082	.buf_size = 0x8000,
1083	},
1084	#ifdef MV_USE_FIXED_BUF
1085	.mpred_mv = {
1086	/* .buf_size = 0x100000*16,
1087	//4k2k , 0x100000 per buffer */
1088	/* 4096x2304 , 0x120000 per buffer */
1089	.buf_size = MPRED_4K_MV_BUF_SIZE * MAX_REF_PIC_NUM,
1090	},
1091	#endif
1092	.rpm = {
1093	.buf_size = RPM_BUF_SIZE,
1094	},
1095	.lmem = {
1096	.buf_size = 0x500 * 2,
1097	}
1098	},
1099
1100	{
1101	.max_width = 4096*2,
1102	.max_height = 2048*2,
1103	.ipp = {
1104	// IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
1105	.buf_size = 0x4000*2,
1106	},
1107	.sao_abv = {
1108	.buf_size = 0x30000*2,
1109	},
1110	.sao_vb = {
1111	.buf_size = 0x30000*2,
1112	},
1113	.short_term_rps = {
1114	// SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
1115	.buf_size = 0x800,
1116	},
1117	.vps = {
1118	// VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
1119	.buf_size = 0x800,
1120	},
1121	.sps = {
1122	// SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
1123	.buf_size = 0x800,
1124	},
1125	.pps = {
1126	// PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
1127	.buf_size = 0x2000,
1128	},
1129	.sao_up = {
1130	// SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
1131	.buf_size = 0x2800*2,
1132	},
1133	.swap_buf = {
1134	// 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
1135	.buf_size = 0x800,
1136	},
1137	.swap_buf2 = {
1138	.buf_size = 0x800,
1139	},
1140	.scalelut = {
1141	// support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
1142	.buf_size = 0x8000*2,
1143	},
1144	.dblk_para = {.buf_size = 0x40000*2, }, // dblk parameter
1145	.dblk_data = {.buf_size = 0x80000*2, }, // dblk data for left/top
1146	.dblk_data2 = {.buf_size = 0x80000*2, }, // dblk data for adapter
1147	.mmu_vbh = {
1148	.buf_size = 0x5000*2, //2*16*2304/4, 4K
1149	},
1150	#if 0
1151	.cm_header = {
1152	.buf_size = MMU_COMPRESS_8K_HEADER_SIZE *
1153	MAX_REF_PIC_NUM, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
1154	},
1155	#endif
1156	.mpred_above = {
1157	.buf_size = 0x8000*2,
1158	},
1159	#ifdef MV_USE_FIXED_BUF
1160	.mpred_mv = {
1161	.buf_size = MPRED_8K_MV_BUF_SIZE * MAX_REF_PIC_NUM, //4k2k , 0x120000 per buffer
1162	},
1163	#endif
1164	.rpm = {
1165	.buf_size = RPM_BUF_SIZE,
1166	},
1167	.lmem = {
1168	.buf_size = 0x500 * 2,
1169	},
1170	}
1171	};
1172
1173	static void init_buff_spec(struct hevc_state_s *hevc,
1174	struct BuffInfo_s *buf_spec)
1175	{
1176	buf_spec->ipp.buf_start = buf_spec->start_adr;
1177	buf_spec->sao_abv.buf_start =
1178	buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
1179
1180	buf_spec->sao_vb.buf_start =
1181	buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
1182	buf_spec->short_term_rps.buf_start =
1183	buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
1184	buf_spec->vps.buf_start =
1185	buf_spec->short_term_rps.buf_start +
1186	buf_spec->short_term_rps.buf_size;
1187	buf_spec->sps.buf_start =
1188	buf_spec->vps.buf_start + buf_spec->vps.buf_size;
1189	buf_spec->pps.buf_start =
1190	buf_spec->sps.buf_start + buf_spec->sps.buf_size;
1191	buf_spec->sao_up.buf_start =
1192	buf_spec->pps.buf_start + buf_spec->pps.buf_size;
1193	buf_spec->swap_buf.buf_start =
1194	buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
1195	buf_spec->swap_buf2.buf_start =
1196	buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
1197	buf_spec->scalelut.buf_start =
1198	buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
1199	buf_spec->dblk_para.buf_start =
1200	buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
1201	buf_spec->dblk_data.buf_start =
1202	buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
1203	buf_spec->dblk_data2.buf_start =
1204	buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
1205	buf_spec->mmu_vbh.buf_start =
1206	buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size;
1207	buf_spec->mpred_above.buf_start =
1208	buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size;
1209	#ifdef MV_USE_FIXED_BUF
1210	buf_spec->mpred_mv.buf_start =
1211	buf_spec->mpred_above.buf_start +
1212	buf_spec->mpred_above.buf_size;
1213
1214	buf_spec->rpm.buf_start =
1215	buf_spec->mpred_mv.buf_start +
1216	buf_spec->mpred_mv.buf_size;
1217	#else
1218	buf_spec->rpm.buf_start =
1219	buf_spec->mpred_above.buf_start +
1220	buf_spec->mpred_above.buf_size;
1221	#endif
1222	buf_spec->lmem.buf_start =
1223	buf_spec->rpm.buf_start +
1224	buf_spec->rpm.buf_size;
1225	buf_spec->end_adr =
1226	buf_spec->lmem.buf_start +
1227	buf_spec->lmem.buf_size;
1228
1229	if (hevc && get_dbg_flag2(hevc)) {
1230	hevc_print(hevc, 0,
1231	"%s workspace (%x %x) size = %x\n", __func__,
1232	buf_spec->start_adr, buf_spec->end_adr,
1233	buf_spec->end_adr - buf_spec->start_adr);
1234
1235	hevc_print(hevc, 0,
1236	"ipp.buf_start :%x\n",
1237	buf_spec->ipp.buf_start);
1238	hevc_print(hevc, 0,
1239	"sao_abv.buf_start :%x\n",
1240	buf_spec->sao_abv.buf_start);
1241	hevc_print(hevc, 0,
1242	"sao_vb.buf_start :%x\n",
1243	buf_spec->sao_vb.buf_start);
1244	hevc_print(hevc, 0,
1245	"short_term_rps.buf_start :%x\n",
1246	buf_spec->short_term_rps.buf_start);
1247	hevc_print(hevc, 0,
1248	"vps.buf_start :%x\n",
1249	buf_spec->vps.buf_start);
1250	hevc_print(hevc, 0,
1251	"sps.buf_start :%x\n",
1252	buf_spec->sps.buf_start);
1253	hevc_print(hevc, 0,
1254	"pps.buf_start :%x\n",
1255	buf_spec->pps.buf_start);
1256	hevc_print(hevc, 0,
1257	"sao_up.buf_start :%x\n",
1258	buf_spec->sao_up.buf_start);
1259	hevc_print(hevc, 0,
1260	"swap_buf.buf_start :%x\n",
1261	buf_spec->swap_buf.buf_start);
1262	hevc_print(hevc, 0,
1263	"swap_buf2.buf_start :%x\n",
1264	buf_spec->swap_buf2.buf_start);
1265	hevc_print(hevc, 0,
1266	"scalelut.buf_start :%x\n",
1267	buf_spec->scalelut.buf_start);
1268	hevc_print(hevc, 0,
1269	"dblk_para.buf_start :%x\n",
1270	buf_spec->dblk_para.buf_start);
1271	hevc_print(hevc, 0,
1272	"dblk_data.buf_start :%x\n",
1273	buf_spec->dblk_data.buf_start);
1274	hevc_print(hevc, 0,
1275	"dblk_data2.buf_start :%x\n",
1276	buf_spec->dblk_data2.buf_start);
1277	hevc_print(hevc, 0,
1278	"mpred_above.buf_start :%x\n",
1279	buf_spec->mpred_above.buf_start);
1280	#ifdef MV_USE_FIXED_BUF
1281	hevc_print(hevc, 0,
1282	"mpred_mv.buf_start :%x\n",
1283	buf_spec->mpred_mv.buf_start);
1284	#endif
1285	if ((get_dbg_flag2(hevc)
1286	&
1287	H265_DEBUG_SEND_PARAM_WITH_REG)
1288	== 0) {
1289	hevc_print(hevc, 0,
1290	"rpm.buf_start :%x\n",
1291	buf_spec->rpm.buf_start);
1292	}
1293	}
1294
1295	}
1296
1297	enum SliceType {
1298	B_SLICE,
1299	P_SLICE,
1300	I_SLICE
1301	};
1302
1303	/*USE_BUF_BLOCK*/
1304	struct BUF_s {
1305	ulong start_adr;
1306	u32 size;
1307	u32 luma_size;
1308	ulong header_addr;
1309	u32 header_size;
1310	int used_flag;
1311	ulong v4l_ref_buf_addr;
1312	} /*BUF_t */;
1313
1314	/* level 6, 6.1 maximum slice number is 800; other is 200 */
1315	#define MAX_SLICE_NUM 800
1316	struct PIC_s {
1317	int index;
1318	int scatter_alloc;
1319	int BUF_index;
1320	int mv_buf_index;
1321	int POC;
1322	int decode_idx;
1323	int slice_type;
1324	int RefNum_L0;
1325	int RefNum_L1;
1326	int num_reorder_pic;
1327	int stream_offset;
1328	unsigned char referenced;
1329	unsigned char output_mark;
1330	unsigned char recon_mark;
1331	unsigned char output_ready;
1332	unsigned char error_mark;
1333	//dis_mark = 0:discard mark,dis_mark = 1:no discard mark
1334	unsigned char dis_mark;
1335	/**/ int slice_idx;
1336	int m_aiRefPOCList0[MAX_SLICE_NUM][16];
1337	int m_aiRefPOCList1[MAX_SLICE_NUM][16];
1338	/*buffer */
1339	unsigned int header_adr;
1340	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
1341	unsigned char dv_enhance_exist;
1342	#endif
1343	char *aux_data_buf;
1344	int aux_data_size;
1345	unsigned long cma_alloc_addr;
1346	struct page *alloc_pages;
1347	unsigned int mpred_mv_wr_start_addr;
1348	unsigned int mc_y_adr;
1349	unsigned int mc_u_v_adr;
1350	#ifdef SUPPORT_10BIT
1351	/*unsigned int comp_body_size;*/
1352	unsigned int dw_y_adr;
1353	unsigned int dw_u_v_adr;
1354	#endif
1355	int mc_canvas_y;
1356	int mc_canvas_u_v;
1357	int width;
1358	int height;
1359
1360	int y_canvas_index;
1361	int uv_canvas_index;
1362	#ifdef MULTI_INSTANCE_SUPPORT
1363	struct canvas_config_s canvas_config[2];
1364	#endif
1365	#ifdef SUPPORT_10BIT
1366	int mem_saving_mode;
1367	u32 bit_depth_luma;
1368	u32 bit_depth_chroma;
1369	#endif
1370	#ifdef LOSLESS_COMPRESS_MODE
1371	unsigned int losless_comp_body_size;
1372	#endif
1373	unsigned char pic_struct;
1374	int vf_ref;
1375
1376	u32 pts;
1377	u64 pts64;
1378	u64 timestamp;
1379
1380	u32 aspect_ratio_idc;
1381	u32 sar_width;
1382	u32 sar_height;
1383	u32 double_write_mode;
1384	u32 video_signal_type;
1385	unsigned short conformance_window_flag;
1386	unsigned short conf_win_left_offset;
1387	unsigned short conf_win_right_offset;
1388	unsigned short conf_win_top_offset;
1389	unsigned short conf_win_bottom_offset;
1390	unsigned short chroma_format_idc;
1391
1392	/* picture qos infomation*/
1393	int max_qp;
1394	int avg_qp;
1395	int min_qp;
1396	int max_skip;
1397	int avg_skip;
1398	int min_skip;
1399	int max_mv;
1400	int min_mv;
1401	int avg_mv;
1402
1403	bool vframe_bound;
1404	} /*PIC_t */;
1405
1406	#define MAX_TILE_COL_NUM 10
1407	#define MAX_TILE_ROW_NUM 20
1408	struct tile_s {
1409	int width;
1410	int height;
1411	int start_cu_x;
1412	int start_cu_y;
1413
1414	unsigned int sao_vb_start_addr;
1415	unsigned int sao_abv_start_addr;
1416	};
1417
1418	#define SEI_MASTER_DISPLAY_COLOR_MASK 0x00000001
1419	#define SEI_CONTENT_LIGHT_LEVEL_MASK 0x00000002
1420	#define SEI_HDR10PLUS_MASK 0x00000004
1421
1422	#define VF_POOL_SIZE 32
1423
1424	#ifdef MULTI_INSTANCE_SUPPORT
1425	#define DEC_RESULT_NONE 0
1426	#define DEC_RESULT_DONE 1
1427	#define DEC_RESULT_AGAIN 2
1428	#define DEC_RESULT_CONFIG_PARAM 3
1429	#define DEC_RESULT_ERROR 4
1430	#define DEC_INIT_PICLIST 5
1431	#define DEC_UNINIT_PICLIST 6
1432	#define DEC_RESULT_GET_DATA 7
1433	#define DEC_RESULT_GET_DATA_RETRY 8
1434	#define DEC_RESULT_EOS 9
1435	#define DEC_RESULT_FORCE_EXIT 10
1436	#define DEC_RESULT_FREE_CANVAS 11
1437
1438	static void vh265_work(struct work_struct *work);
1439	static void vh265_timeout_work(struct work_struct *work);
1440	static void vh265_notify_work(struct work_struct *work);
1441
1442	#endif
1443
1444	struct debug_log_s {
1445	struct list_head list;
1446	uint8_t data; /*will alloc more size*/
1447	};
1448
1449	struct hevc_state_s {
1450	#ifdef MULTI_INSTANCE_SUPPORT
1451	struct platform_device *platform_dev;
1452	void (*vdec_cb)(struct vdec_s *, void *);
1453	void *vdec_cb_arg;
1454	struct vframe_chunk_s *chunk;
1455	int dec_result;
1456	struct work_struct work;
1457	struct work_struct timeout_work;
1458	struct work_struct notify_work;
1459	struct work_struct set_clk_work;
1460	/* timeout handle */
1461	unsigned long int start_process_time;
1462	unsigned int last_lcu_idx;
1463	unsigned int decode_timeout_count;
1464	unsigned int timeout_num;
1465	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
1466	unsigned char switch_dvlayer_flag;
1467	unsigned char no_switch_dvlayer_count;
1468	unsigned char bypass_dvenl_enable;
1469	unsigned char bypass_dvenl;
1470	#endif
1471	unsigned char start_parser_type;
1472	/*start_decoding_flag:
1473	vps/pps/sps/idr info from ucode*/
1474	unsigned char start_decoding_flag;
1475	unsigned char rps_set_id;
1476	unsigned char eos;
1477	int pic_decoded_lcu_idx;
1478	u8 over_decode;
1479	u8 empty_flag;
1480	#endif
1481	struct vframe_s vframe_dummy;
1482	char *provider_name;
1483	int index;
1484	struct device *cma_dev;
1485	unsigned char m_ins_flag;
1486	unsigned char dolby_enhance_flag;
1487	unsigned long buf_start;
1488	u32 buf_size;
1489	u32 mv_buf_size;
1490
1491	struct BuffInfo_s work_space_buf_store;
1492	struct BuffInfo_s *work_space_buf;
1493
1494	u8 aux_data_dirty;
1495	u32 prefix_aux_size;
1496	u32 suffix_aux_size;
1497	void *aux_addr;
1498	void *rpm_addr;
1499	void *lmem_addr;
1500	dma_addr_t aux_phy_addr;
1501	dma_addr_t rpm_phy_addr;
1502	dma_addr_t lmem_phy_addr;
1503
1504	unsigned int pic_list_init_flag;
1505	unsigned int use_cma_flag;
1506
1507	unsigned short *rpm_ptr;
1508	unsigned short *lmem_ptr;
1509	unsigned short *debug_ptr;
1510	int debug_ptr_size;
1511	int pic_w;
1512	int pic_h;
1513	int lcu_x_num;
1514	int lcu_y_num;
1515	int lcu_total;
1516	int lcu_size;
1517	int lcu_size_log2;
1518	int lcu_x_num_pre;
1519	int lcu_y_num_pre;
1520	int first_pic_after_recover;
1521
1522	int num_tile_col;
1523	int num_tile_row;
1524	int tile_enabled;
1525	int tile_x;
1526	int tile_y;
1527	int tile_y_x;
1528	int tile_start_lcu_x;
1529	int tile_start_lcu_y;
1530	int tile_width_lcu;
1531	int tile_height_lcu;
1532
1533	int slice_type;
1534	unsigned int slice_addr;
1535	unsigned int slice_segment_addr;
1536
1537	unsigned char interlace_flag;
1538	unsigned char curr_pic_struct;
1539	unsigned char frame_field_info_present_flag;
1540
1541	unsigned short sps_num_reorder_pics_0;
1542	unsigned short misc_flag0;
1543	int m_temporalId;
1544	int m_nalUnitType;
1545	int TMVPFlag;
1546	int isNextSliceSegment;
1547	int LDCFlag;
1548	int m_pocRandomAccess;
1549	int plevel;
1550	int MaxNumMergeCand;
1551
1552	int new_pic;
1553	int new_tile;
1554	int curr_POC;
1555	int iPrevPOC;
1556	#ifdef MULTI_INSTANCE_SUPPORT
1557	int decoded_poc;
1558	struct PIC_s *decoding_pic;
1559	#endif
1560	int iPrevTid0POC;
1561	int list_no;
1562	int RefNum_L0;
1563	int RefNum_L1;
1564	int ColFromL0Flag;
1565	int LongTerm_Curr;
1566	int LongTerm_Col;
1567	int Col_POC;
1568	int LongTerm_Ref;
1569	#ifdef MULTI_INSTANCE_SUPPORT
1570	int m_pocRandomAccess_bak;
1571	int curr_POC_bak;
1572	int iPrevPOC_bak;
1573	int iPrevTid0POC_bak;
1574	unsigned char start_parser_type_bak;
1575	unsigned char start_decoding_flag_bak;
1576	unsigned char rps_set_id_bak;
1577	int pic_decoded_lcu_idx_bak;
1578	int decode_idx_bak;
1579	#endif
1580	struct PIC_s *cur_pic;
1581	struct PIC_s *col_pic;
1582	int skip_flag;
1583	int decode_idx;
1584	int slice_idx;
1585	unsigned char have_vps;
1586	unsigned char have_sps;
1587	unsigned char have_pps;
1588	unsigned char have_valid_start_slice;
1589	unsigned char wait_buf;
1590	unsigned char error_flag;
1591	unsigned int error_skip_nal_count;
1592	long used_4k_num;
1593
1594	unsigned char
1595	ignore_bufmgr_error; /* bit 0, for decoding;
1596	bit 1, for displaying
1597	bit 1 must be set if bit 0 is 1*/
1598	int PB_skip_mode;
1599	int PB_skip_count_after_decoding;
1600	#ifdef SUPPORT_10BIT
1601	int mem_saving_mode;
1602	#endif
1603	#ifdef LOSLESS_COMPRESS_MODE
1604	unsigned int losless_comp_body_size;
1605	#endif
1606	int pts_mode;
1607	int last_lookup_pts;
1608	int last_pts;
1609	u64 last_lookup_pts_us64;
1610	u64 last_pts_us64;
1611	u32 shift_byte_count_lo;
1612	u32 shift_byte_count_hi;
1613	int pts_mode_switching_count;
1614	int pts_mode_recovery_count;
1615
1616	int pic_num;
1617
1618	/**/
1619	union param_u param;
1620
1621	struct tile_s m_tile[MAX_TILE_ROW_NUM][MAX_TILE_COL_NUM];
1622
1623	struct timer_list timer;
1624	struct BUF_s m_BUF[BUF_POOL_SIZE];
1625	struct BUF_s m_mv_BUF[MAX_REF_PIC_NUM];
1626	struct PIC_s *m_PIC[MAX_REF_PIC_NUM];
1627
1628	DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1629	DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1630	DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1631	struct vframe_s vfpool[VF_POOL_SIZE];
1632
1633	u32 stat;
1634	u32 frame_width;
1635	u32 frame_height;
1636	u32 frame_dur;
1637	u32 frame_ar;
1638	u32 bit_depth_luma;
1639	u32 bit_depth_chroma;
1640	u32 video_signal_type;
1641	u32 video_signal_type_debug;
1642	u32 saved_resolution;
1643	bool get_frame_dur;
1644	u32 error_watchdog_count;
1645	u32 error_skip_nal_wt_cnt;
1646	u32 error_system_watchdog_count;
1647
1648	#ifdef DEBUG_PTS
1649	unsigned long pts_missed;
1650	unsigned long pts_hit;
1651	#endif
1652	struct dec_sysinfo vh265_amstream_dec_info;
1653	unsigned char init_flag;
1654	unsigned char first_sc_checked;
1655	unsigned char uninit_list;
1656	u32 start_decoding_time;
1657
1658	int show_frame_num;
1659	#ifdef USE_UNINIT_SEMA
1660	struct semaphore h265_uninit_done_sema;
1661	#endif
1662	int fatal_error;
1663
1664
1665	u32 sei_present_flag;
1666	void *frame_mmu_map_addr;
1667	dma_addr_t frame_mmu_map_phy_addr;
1668	unsigned int mmu_mc_buf_start;
1669	unsigned int mmu_mc_buf_end;
1670	unsigned int mmu_mc_start_4k_adr;
1671	void *mmu_box;
1672	void *bmmu_box;
1673	int mmu_enable;
1674
1675	unsigned int dec_status;
1676
1677	/* data for SEI_MASTER_DISPLAY_COLOR */
1678	unsigned int primaries[3][2];
1679	unsigned int white_point[2];
1680	unsigned int luminance[2];
1681	/* data for SEI_CONTENT_LIGHT_LEVEL */
1682	unsigned int content_light_level[2];
1683
1684	struct PIC_s *pre_top_pic;
1685	struct PIC_s *pre_bot_pic;
1686
1687	#ifdef MULTI_INSTANCE_SUPPORT
1688	int double_write_mode;
1689	int dynamic_buf_num_margin;
1690	int start_action;
1691	int save_buffer_mode;
1692	#endif
1693	u32 i_only;
1694	struct list_head log_list;
1695	u32 ucode_pause_pos;
1696	u32 start_shift_bytes;
1697
1698	u32 vf_pre_count;
1699	u32 vf_get_count;
1700	u32 vf_put_count;
1701	#ifdef SWAP_HEVC_UCODE
1702	dma_addr_t mc_dma_handle;
1703	void *mc_cpu_addr;
1704	int swap_size;
1705	ulong swap_addr;
1706	#endif
1707	#ifdef DETREFILL_ENABLE
1708	dma_addr_t detbuf_adr;
1709	u16 *detbuf_adr_virt;
1710	u8 delrefill_check;
1711	#endif
1712	u8 head_error_flag;
1713	int valve_count;
1714	struct firmware_s *fw;
1715	int max_pic_w;
1716	int max_pic_h;
1717	#ifdef AGAIN_HAS_THRESHOLD
1718	u8 next_again_flag;
1719	u32 pre_parser_wr_ptr;
1720	#endif
1721	u32 ratio_control;
1722	u32 first_pic_flag;
1723	u32 decode_size;
1724	struct mutex chunks_mutex;
1725	int need_cache_size;
1726	u64 sc_start_time;
1727	u32 skip_first_nal;
1728	bool is_swap;
1729	bool is_4k;
1730	int frameinfo_enable;
1731	struct vframe_qos_s vframe_qos;
1732	bool is_used_v4l;
1733	void *v4l2_ctx;
1734	bool v4l_params_parsed;
1735	} /*hevc_stru_t */;
1736
1737	#ifdef AGAIN_HAS_THRESHOLD
1738	u32 again_threshold;
1739	#endif
1740	#ifdef SEND_LMEM_WITH_RPM
1741	#define get_lmem_params(hevc, ladr) \
1742	hevc->lmem_ptr[ladr - (ladr & 0x3) + 3 - (ladr & 0x3)]
1743
1744
1745	static int get_frame_mmu_map_size(void)
1746	{
1747	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1748	return (MAX_FRAME_8K_NUM * 4);
1749
1750	return (MAX_FRAME_4K_NUM * 4);
1751	}
1752
1753	static int is_oversize(int w, int h)
1754	{
1755	int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1756	MAX_SIZE_8K : MAX_SIZE_4K;
1757
1758	if (w < 0 || h < 0)
1759	return true;
1760
1761	if (h != 0 && (w > max / h))
1762	return true;
1763
1764	return false;
1765	}
1766
1767	void check_head_error(struct hevc_state_s *hevc)
1768	{
1769	#define pcm_enabled_flag 0x040
1770	#define pcm_sample_bit_depth_luma 0x041
1771	#define pcm_sample_bit_depth_chroma 0x042
1772	hevc->head_error_flag = 0;
1773	if ((error_handle_policy & 0x40) == 0)
1774	return;
1775	if (get_lmem_params(hevc, pcm_enabled_flag)) {
1776	uint16_t pcm_depth_luma = get_lmem_params(
1777	hevc, pcm_sample_bit_depth_luma);
1778	uint16_t pcm_sample_chroma = get_lmem_params(
1779	hevc, pcm_sample_bit_depth_chroma);
1780	if (pcm_depth_luma >
1781	hevc->bit_depth_luma ||
1782	pcm_sample_chroma >
1783	hevc->bit_depth_chroma) {
1784	hevc_print(hevc, 0,
1785	"error, pcm bit depth %d, %d is greater than normal bit depth %d, %d\n",
1786	pcm_depth_luma,
1787	pcm_sample_chroma,
1788	hevc->bit_depth_luma,
1789	hevc->bit_depth_chroma);
1790	hevc->head_error_flag = 1;
1791	}
1792	}
1793	}
1794	#endif
1795
1796	#ifdef SUPPORT_10BIT
1797	/* Losless compression body buffer size 4K per 64x32 (jt) */
1798	static int compute_losless_comp_body_size(struct hevc_state_s *hevc,
1799	int width, int height, int mem_saving_mode)
1800	{
1801	int width_x64;
1802	int height_x32;
1803	int bsize;
1804
1805	width_x64 = width + 63;
1806	width_x64 >>= 6;
1807
1808	height_x32 = height + 31;
1809	height_x32 >>= 5;
1810	if (mem_saving_mode == 1 && hevc->mmu_enable)
1811	bsize = 3200 * width_x64 * height_x32;
1812	else if (mem_saving_mode == 1)
1813	bsize = 3072 * width_x64 * height_x32;
1814	else
1815	bsize = 4096 * width_x64 * height_x32;
1816
1817	return bsize;
1818	}
1819
1820	/* Losless compression header buffer size 32bytes per 128x64 (jt) */
1821	static int compute_losless_comp_header_size(int width, int height)
1822	{
1823	int width_x128;
1824	int height_x64;
1825	int hsize;
1826
1827	width_x128 = width + 127;
1828	width_x128 >>= 7;
1829
1830	height_x64 = height + 63;
1831	height_x64 >>= 6;
1832
1833	hsize = 32*width_x128*height_x64;
1834
1835	return hsize;
1836	}
1837	#endif
1838
1839	static int add_log(struct hevc_state_s *hevc,
1840	const char *fmt, ...)
1841	{
1842	#define HEVC_LOG_BUF 196
1843	struct debug_log_s *log_item;
1844	unsigned char buf[HEVC_LOG_BUF];
1845	int len = 0;
1846	va_list args;
1847	mutex_lock(&vh265_log_mutex);
1848	va_start(args, fmt);
1849	len = sprintf(buf, "<%ld> <%05d> ",
1850	jiffies, hevc->decode_idx);
1851	len += vsnprintf(buf + len,
1852	HEVC_LOG_BUF - len, fmt, args);
1853	va_end(args);
1854	log_item = kmalloc(
1855	sizeof(struct debug_log_s) + len,
1856	GFP_KERNEL);
1857	if (log_item) {
1858	INIT_LIST_HEAD(&log_item->list);
1859	strcpy(&log_item->data, buf);
1860	list_add_tail(&log_item->list,
1861	&hevc->log_list);
1862	}
1863	mutex_unlock(&vh265_log_mutex);
1864	return 0;
1865	}
1866
1867	static void dump_log(struct hevc_state_s *hevc)
1868	{
1869	int i = 0;
1870	struct debug_log_s *log_item, *tmp;
1871	mutex_lock(&vh265_log_mutex);
1872	list_for_each_entry_safe(log_item, tmp, &hevc->log_list, list) {
1873	hevc_print(hevc, 0,
1874	"[LOG%04d]%s\n",
1875	i++,
1876	&log_item->data);
1877	list_del(&log_item->list);
1878	kfree(log_item);
1879	}
1880	mutex_unlock(&vh265_log_mutex);
1881	}
1882
1883	static unsigned char is_skip_decoding(struct hevc_state_s *hevc,
1884	struct PIC_s *pic)
1885	{
1886	if (pic->error_mark
1887	&& ((hevc->ignore_bufmgr_error & 0x1) == 0))
1888	return 1;
1889	return 0;
1890	}
1891
1892	static int get_pic_poc(struct hevc_state_s *hevc,
1893	unsigned int idx)
1894	{
1895	if (idx != 0xff
1896	&& idx < MAX_REF_PIC_NUM
1897	&& hevc->m_PIC[idx])
1898	return hevc->m_PIC[idx]->POC;
1899	return INVALID_POC;
1900	}
1901
1902	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1903	static int get_valid_double_write_mode(struct hevc_state_s *hevc)
1904	{
1905	return (hevc->m_ins_flag &&
1906	((double_write_mode & 0x80000000) == 0)) ?
1907	hevc->double_write_mode :
1908	(double_write_mode & 0x7fffffff);
1909	}
1910
1911	static int get_dynamic_buf_num_margin(struct hevc_state_s *hevc)
1912	{
1913	return (hevc->m_ins_flag &&
1914	((dynamic_buf_num_margin & 0x80000000) == 0)) ?
1915	hevc->dynamic_buf_num_margin :
1916	(dynamic_buf_num_margin & 0x7fffffff);
1917	}
1918	#endif
1919
1920	static int get_double_write_mode(struct hevc_state_s *hevc)
1921	{
1922	u32 valid_dw_mode = get_valid_double_write_mode(hevc);
1923	int w = hevc->pic_w;
1924	int h = hevc->pic_h;
1925	u32 dw = 0x1; /*1:1*/
1926	switch (valid_dw_mode) {
1927	case 0x100:
1928	if (w > 1920 && h > 1088)
1929	dw = 0x4; /*1:2*/
1930	break;
1931	case 0x200:
1932	if (w > 1920 && h > 1088)
1933	dw = 0x2; /*1:4*/
1934	break;
1935	case 0x300:
1936	if (w > 1280 && h > 720)
1937	dw = 0x4; /*1:2*/
1938	break;
1939	default:
1940	dw = valid_dw_mode;
1941	break;
1942	}
1943	return dw;
1944	}
1945
1946	static int get_double_write_ratio(struct hevc_state_s *hevc,
1947	int dw_mode)
1948	{
1949	int ratio = 1;
1950	if ((dw_mode == 2) ||
1951	(dw_mode == 3))
1952	ratio = 4;
1953	else if (dw_mode == 4)
1954	ratio = 2;
1955	return ratio;
1956	}
1957	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1958	static unsigned char get_idx(struct hevc_state_s *hevc)
1959	{
1960	return hevc->index;
1961	}
1962	#endif
1963
1964	#undef pr_info
1965	#define pr_info printk
1966	static int hevc_print(struct hevc_state_s *hevc,
1967	int flag, const char *fmt, ...)
1968	{
1969	#define HEVC_PRINT_BUF 256
1970	unsigned char buf[HEVC_PRINT_BUF];
1971	int len = 0;
1972	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1973	if (hevc == NULL ||
1974	(flag == 0) ||
1975	((debug_mask &
1976	(1 << hevc->index))
1977	&& (debug & flag))) {
1978	#endif
1979	va_list args;
1980
1981	va_start(args, fmt);
1982	if (hevc)
1983	len = sprintf(buf, "[%d]", hevc->index);
1984	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1985	pr_debug("%s", buf);
1986	va_end(args);
1987	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1988	}
1989	#endif
1990	return 0;
1991	}
1992
1993	static int hevc_print_cont(struct hevc_state_s *hevc,
1994	int flag, const char *fmt, ...)
1995	{
1996	unsigned char buf[HEVC_PRINT_BUF];
1997	int len = 0;
1998	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
1999	if (hevc == NULL ||
2000	(flag == 0) ||
2001	((debug_mask &
2002	(1 << hevc->index))
2003	&& (debug & flag))) {
2004	#endif
2005	va_list args;
2006
2007	va_start(args, fmt);
2008	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
2009	pr_info("%s", buf);
2010	va_end(args);
2011	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
2012	}
2013	#endif
2014	return 0;
2015	}
2016
2017	static void put_mv_buf(struct hevc_state_s *hevc,
2018	struct PIC_s *pic);
2019
2020	static void update_vf_memhandle(struct hevc_state_s *hevc,
2021	struct vframe_s *vf, struct PIC_s *pic);
2022
2023	static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic);
2024
2025	static void release_aux_data(struct hevc_state_s *hevc,
2026	struct PIC_s *pic);
2027	static void release_pic_mmu_buf(struct hevc_state_s *hevc, struct PIC_s *pic);
2028
2029	#ifdef MULTI_INSTANCE_SUPPORT
2030	static void backup_decode_state(struct hevc_state_s *hevc)
2031	{
2032	hevc->m_pocRandomAccess_bak = hevc->m_pocRandomAccess;
2033	hevc->curr_POC_bak = hevc->curr_POC;
2034	hevc->iPrevPOC_bak = hevc->iPrevPOC;
2035	hevc->iPrevTid0POC_bak = hevc->iPrevTid0POC;
2036	hevc->start_parser_type_bak = hevc->start_parser_type;
2037	hevc->start_decoding_flag_bak = hevc->start_decoding_flag;
2038	hevc->rps_set_id_bak = hevc->rps_set_id;
2039	hevc->pic_decoded_lcu_idx_bak = hevc->pic_decoded_lcu_idx;
2040	hevc->decode_idx_bak = hevc->decode_idx;
2041
2042	}
2043
2044	static void restore_decode_state(struct hevc_state_s *hevc)
2045	{
2046	struct vdec_s *vdec = hw_to_vdec(hevc);
2047	if (!vdec_has_more_input(vdec)) {
2048	hevc->pic_decoded_lcu_idx =
2049	READ_VREG(HEVC_PARSER_LCU_START)
2050	& 0xffffff;
2051	return;
2052	}
2053	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
2054	"%s: discard pic index 0x%x\n",
2055	__func__, hevc->decoding_pic ?
2056	hevc->decoding_pic->index : 0xff);
2057	if (hevc->decoding_pic) {
2058	hevc->decoding_pic->error_mark = 0;
2059	hevc->decoding_pic->output_ready = 0;
2060	hevc->decoding_pic->output_mark = 0;
2061	hevc->decoding_pic->referenced = 0;
2062	hevc->decoding_pic->POC = INVALID_POC;
2063	put_mv_buf(hevc, hevc->decoding_pic);
2064	release_pic_mmu_buf(hevc, hevc->decoding_pic);
2065	release_aux_data(hevc, hevc->decoding_pic);
2066	hevc->decoding_pic = NULL;
2067	}
2068	hevc->decode_idx = hevc->decode_idx_bak;
2069	hevc->m_pocRandomAccess = hevc->m_pocRandomAccess_bak;
2070	hevc->curr_POC = hevc->curr_POC_bak;
2071	hevc->iPrevPOC = hevc->iPrevPOC_bak;
2072	hevc->iPrevTid0POC = hevc->iPrevTid0POC_bak;
2073	hevc->start_parser_type = hevc->start_parser_type_bak;
2074	hevc->start_decoding_flag = hevc->start_decoding_flag_bak;
2075	hevc->rps_set_id = hevc->rps_set_id_bak;
2076	hevc->pic_decoded_lcu_idx = hevc->pic_decoded_lcu_idx_bak;
2077
2078	if (hevc->pic_list_init_flag == 1)
2079	hevc->pic_list_init_flag = 0;
2080	/*if (hevc->decode_idx == 0)
2081	hevc->start_decoding_flag = 0;*/
2082
2083	hevc->slice_idx = 0;
2084	hevc->used_4k_num = -1;
2085	}
2086	#endif
2087
2088	static void hevc_init_stru(struct hevc_state_s *hevc,
2089	struct BuffInfo_s *buf_spec_i)
2090	{
2091	//int i;
2092	INIT_LIST_HEAD(&hevc->log_list);
2093	hevc->work_space_buf = buf_spec_i;
2094	hevc->prefix_aux_size = 0;
2095	hevc->suffix_aux_size = 0;
2096	hevc->aux_addr = NULL;
2097	hevc->rpm_addr = NULL;
2098	hevc->lmem_addr = NULL;
2099
2100	hevc->curr_POC = INVALID_POC;
2101
2102	hevc->pic_list_init_flag = 0;
2103	hevc->use_cma_flag = 0;
2104	hevc->decode_idx = 0;
2105	hevc->slice_idx = 0;
2106	hevc->new_pic = 0;
2107	hevc->new_tile = 0;
2108	hevc->iPrevPOC = 0;
2109	hevc->list_no = 0;
2110	/* int m_uiMaxCUWidth = 1<<7; */
2111	/* int m_uiMaxCUHeight = 1<<7; */
2112	hevc->m_pocRandomAccess = MAX_INT;
2113	hevc->tile_enabled = 0;
2114	hevc->tile_x = 0;
2115	hevc->tile_y = 0;
2116	hevc->iPrevTid0POC = 0;
2117	hevc->slice_addr = 0;
2118	hevc->slice_segment_addr = 0;
2119	hevc->skip_flag = 0;
2120	hevc->misc_flag0 = 0;
2121
2122	hevc->cur_pic = NULL;
2123	hevc->col_pic = NULL;
2124	hevc->wait_buf = 0;
2125	hevc->error_flag = 0;
2126	hevc->head_error_flag = 0;
2127	hevc->error_skip_nal_count = 0;
2128	hevc->have_vps = 0;
2129	hevc->have_sps = 0;
2130	hevc->have_pps = 0;
2131	hevc->have_valid_start_slice = 0;
2132
2133	hevc->pts_mode = PTS_NORMAL;
2134	hevc->last_pts = 0;
2135	hevc->last_lookup_pts = 0;
2136	hevc->last_pts_us64 = 0;
2137	hevc->last_lookup_pts_us64 = 0;
2138	hevc->pts_mode_switching_count = 0;
2139	hevc->pts_mode_recovery_count = 0;
2140
2141	hevc->PB_skip_mode = nal_skip_policy & 0x3;
2142	hevc->PB_skip_count_after_decoding = (nal_skip_policy >> 16) & 0xffff;
2143	if (hevc->PB_skip_mode == 0)
2144	hevc->ignore_bufmgr_error = 0x1;
2145	else
2146	hevc->ignore_bufmgr_error = 0x0;
2147
2148	/*for (i = 0; i < MAX_REF_PIC_NUM; i++)
2149	hevc->m_PIC[i] = NULL;*/
2150
2151	hevc->pic_num = 0;
2152	hevc->lcu_x_num_pre = 0;
2153	hevc->lcu_y_num_pre = 0;
2154	hevc->first_pic_after_recover = 0;
2155
2156	hevc->pre_top_pic = NULL;
2157	hevc->pre_bot_pic = NULL;
2158
2159	hevc->sei_present_flag = 0;
2160	hevc->valve_count = 0;
2161	hevc->first_pic_flag = 0;
2162	#ifdef MULTI_INSTANCE_SUPPORT
2163	hevc->decoded_poc = INVALID_POC;
2164	hevc->start_process_time = 0;
2165	hevc->last_lcu_idx = 0;
2166	hevc->decode_timeout_count = 0;
2167	hevc->timeout_num = 0;
2168	hevc->eos = 0;
2169	hevc->pic_decoded_lcu_idx = -1;
2170	hevc->over_decode = 0;
2171	hevc->used_4k_num = -1;
2172	hevc->start_decoding_flag = 0;
2173	hevc->rps_set_id = 0;
2174	backup_decode_state(hevc);
2175	#endif
2176	#ifdef DETREFILL_ENABLE
2177	hevc->detbuf_adr = 0;
2178	hevc->detbuf_adr_virt = NULL;
2179	#endif
2180	}
2181
2182	static int prepare_display_buf(struct hevc_state_s *hevc, struct PIC_s *pic);
2183	static int H265_alloc_mmu(struct hevc_state_s *hevc,
2184	struct PIC_s *new_pic, unsigned short bit_depth,
2185	unsigned int *mmu_index_adr);
2186
2187	#ifdef DETREFILL_ENABLE
2188	#define DETREFILL_BUF_SIZE (4 * 0x4000)
2189	#define HEVC_SAO_DBG_MODE0 0x361e
2190	#define HEVC_SAO_DBG_MODE1 0x361f
2191	#define HEVC_SAO_CTRL10 0x362e
2192	#define HEVC_SAO_CTRL11 0x362f
2193	static int init_detrefill_buf(struct hevc_state_s *hevc)
2194	{
2195	if (hevc->detbuf_adr_virt)
2196	return 0;
2197
2198	hevc->detbuf_adr_virt =
2199	(void *)dma_alloc_coherent(amports_get_dma_device(),
2200	DETREFILL_BUF_SIZE, &hevc->detbuf_adr,
2201	GFP_KERNEL);
2202
2203	if (hevc->detbuf_adr_virt == NULL) {
2204	pr_err("%s: failed to alloc ETREFILL_BUF\n", __func__);
2205	return -1;
2206	}
2207	return 0;
2208	}
2209
2210	static void uninit_detrefill_buf(struct hevc_state_s *hevc)
2211	{
2212	if (hevc->detbuf_adr_virt) {
2213	dma_free_coherent(amports_get_dma_device(),
2214	DETREFILL_BUF_SIZE, hevc->detbuf_adr_virt,
2215	hevc->detbuf_adr);
2216
2217	hevc->detbuf_adr_virt = NULL;
2218	hevc->detbuf_adr = 0;
2219	}
2220	}
2221
2222	/*
2223	* convert uncompressed frame buffer data from/to ddr
2224	*/
2225	static void convUnc8x4blk(uint16_t* blk8x4Luma,
2226	uint16_t* blk8x4Cb, uint16_t* blk8x4Cr, uint16_t* cmBodyBuf, int32_t direction)
2227	{
2228	if (direction == 0) {
2229	blk8x4Luma[3 + 0 * 8] = ((cmBodyBuf[0] >> 0)) & 0x3ff;
2230	blk8x4Luma[3 + 1 * 8] = ((cmBodyBuf[1] << 6)
2231	| (cmBodyBuf[0] >> 10)) & 0x3ff;
2232	blk8x4Luma[3 + 2 * 8] = ((cmBodyBuf[1] >> 4)) & 0x3ff;
2233	blk8x4Luma[3 + 3 * 8] = ((cmBodyBuf[2] << 2)
2234	| (cmBodyBuf[1] >> 14)) & 0x3ff;
2235	blk8x4Luma[7 + 0 * 8] = ((cmBodyBuf[3] << 8)
2236	| (cmBodyBuf[2] >> 8)) & 0x3ff;
2237	blk8x4Luma[7 + 1 * 8] = ((cmBodyBuf[3] >> 2)) & 0x3ff;
2238	blk8x4Luma[7 + 2 * 8] = ((cmBodyBuf[4] << 4)
2239	| (cmBodyBuf[3] >> 12)) & 0x3ff;
2240	blk8x4Luma[7 + 3 * 8] = ((cmBodyBuf[4] >> 6)) & 0x3ff;
2241	blk8x4Cb [0 + 0 * 4] = ((cmBodyBuf[5] >> 0)) & 0x3ff;
2242	blk8x4Cr [0 + 0 * 4] = ((cmBodyBuf[6] << 6)
2243	| (cmBodyBuf[5] >> 10)) & 0x3ff;
2244	blk8x4Cb [0 + 1 * 4] = ((cmBodyBuf[6] >> 4)) & 0x3ff;
2245	blk8x4Cr [0 + 1 * 4] = ((cmBodyBuf[7] << 2)
2246	| (cmBodyBuf[6] >> 14)) & 0x3ff;
2247
2248	blk8x4Luma[0 + 0 * 8] = ((cmBodyBuf[0 + 8] >> 0)) & 0x3ff;
2249	blk8x4Luma[1 + 0 * 8] = ((cmBodyBuf[1 + 8] << 6) |
2250	(cmBodyBuf[0 + 8] >> 10)) & 0x3ff;
2251	blk8x4Luma[2 + 0 * 8] = ((cmBodyBuf[1 + 8] >> 4)) & 0x3ff;
2252	blk8x4Luma[0 + 1 * 8] = ((cmBodyBuf[2 + 8] << 2) |
2253	(cmBodyBuf[1 + 8] >> 14)) & 0x3ff;
2254	blk8x4Luma[1 + 1 * 8] = ((cmBodyBuf[3 + 8] << 8) |
2255	(cmBodyBuf[2 + 8] >> 8)) & 0x3ff;
2256	blk8x4Luma[2 + 1 * 8] = ((cmBodyBuf[3 + 8] >> 2)) & 0x3ff;
2257	blk8x4Luma[0 + 2 * 8] = ((cmBodyBuf[4 + 8] << 4) |
2258	(cmBodyBuf[3 + 8] >> 12)) & 0x3ff;
2259	blk8x4Luma[1 + 2 * 8] = ((cmBodyBuf[4 + 8] >> 6)) & 0x3ff;
2260	blk8x4Luma[2 + 2 * 8] = ((cmBodyBuf[5 + 8] >> 0)) & 0x3ff;
2261	blk8x4Luma[0 + 3 * 8] = ((cmBodyBuf[6 + 8] << 6) |
2262	(cmBodyBuf[5 + 8] >> 10)) & 0x3ff;
2263	blk8x4Luma[1 + 3 * 8] = ((cmBodyBuf[6 + 8] >> 4)) & 0x3ff;
2264	blk8x4Luma[2 + 3 * 8] = ((cmBodyBuf[7 + 8] << 2) |
2265	(cmBodyBuf[6 + 8] >> 14)) & 0x3ff;
2266
2267	blk8x4Luma[4 + 0 * 8] = ((cmBodyBuf[0 + 16] >> 0)) & 0x3ff;
2268	blk8x4Luma[5 + 0 * 8] = ((cmBodyBuf[1 + 16] << 6) |
2269	(cmBodyBuf[0 + 16] >> 10)) & 0x3ff;
2270	blk8x4Luma[6 + 0 * 8] = ((cmBodyBuf[1 + 16] >> 4)) & 0x3ff;
2271	blk8x4Luma[4 + 1 * 8] = ((cmBodyBuf[2 + 16] << 2) |
2272	(cmBodyBuf[1 + 16] >> 14)) & 0x3ff;
2273	blk8x4Luma[5 + 1 * 8] = ((cmBodyBuf[3 + 16] << 8) |
2274	(cmBodyBuf[2 + 16] >> 8)) & 0x3ff;
2275	blk8x4Luma[6 + 1 * 8] = ((cmBodyBuf[3 + 16] >> 2)) & 0x3ff;
2276	blk8x4Luma[4 + 2 * 8] = ((cmBodyBuf[4 + 16] << 4) |
2277	(cmBodyBuf[3 + 16] >> 12)) & 0x3ff;
2278	blk8x4Luma[5 + 2 * 8] = ((cmBodyBuf[4 + 16] >> 6)) & 0x3ff;
2279	blk8x4Luma[6 + 2 * 8] = ((cmBodyBuf[5 + 16] >> 0)) & 0x3ff;
2280	blk8x4Luma[4 + 3 * 8] = ((cmBodyBuf[6 + 16] << 6) |
2281	(cmBodyBuf[5 + 16] >> 10)) & 0x3ff;
2282	blk8x4Luma[5 + 3 * 8] = ((cmBodyBuf[6 + 16] >> 4)) & 0x3ff;
2283	blk8x4Luma[6 + 3 * 8] = ((cmBodyBuf[7 + 16] << 2) |
2284	(cmBodyBuf[6 + 16] >> 14)) & 0x3ff;
2285
2286	blk8x4Cb[1 + 0 * 4] = ((cmBodyBuf[0 + 24] >> 0)) & 0x3ff;
2287	blk8x4Cr[1 + 0 * 4] = ((cmBodyBuf[1 + 24] << 6) |
2288	(cmBodyBuf[0 + 24] >> 10)) & 0x3ff;
2289	blk8x4Cb[2 + 0 * 4] = ((cmBodyBuf[1 + 24] >> 4)) & 0x3ff;
2290	blk8x4Cr[2 + 0 * 4] = ((cmBodyBuf[2 + 24] << 2) |
2291	(cmBodyBuf[1 + 24] >> 14)) & 0x3ff;
2292	blk8x4Cb[3 + 0 * 4] = ((cmBodyBuf[3 + 24] << 8) |
2293	(cmBodyBuf[2 + 24] >> 8)) & 0x3ff;
2294	blk8x4Cr[3 + 0 * 4] = ((cmBodyBuf[3 + 24] >> 2)) & 0x3ff;
2295	blk8x4Cb[1 + 1 * 4] = ((cmBodyBuf[4 + 24] << 4) |
2296	(cmBodyBuf[3 + 24] >> 12)) & 0x3ff;
2297	blk8x4Cr[1 + 1 * 4] = ((cmBodyBuf[4 + 24] >> 6)) & 0x3ff;
2298	blk8x4Cb[2 + 1 * 4] = ((cmBodyBuf[5 + 24] >> 0)) & 0x3ff;
2299	blk8x4Cr[2 + 1 * 4] = ((cmBodyBuf[6 + 24] << 6) |
2300	(cmBodyBuf[5 + 24] >> 10)) & 0x3ff;
2301	blk8x4Cb[3 + 1 * 4] = ((cmBodyBuf[6 + 24] >> 4)) & 0x3ff;
2302	blk8x4Cr[3 + 1 * 4] = ((cmBodyBuf[7 + 24] << 2) |
2303	(cmBodyBuf[6 + 24] >> 14)) & 0x3ff;
2304	} else {
2305	cmBodyBuf[0 + 8 * 0] = (blk8x4Luma[3 + 1 * 8] << 10) |
2306	blk8x4Luma[3 + 0 * 8];
2307	cmBodyBuf[1 + 8 * 0] = (blk8x4Luma[3 + 3 * 8] << 14) |
2308	(blk8x4Luma[3 + 2 * 8] << 4) | (blk8x4Luma[3 + 1 * 8] >> 6);
2309	cmBodyBuf[2 + 8 * 0] = (blk8x4Luma[7 + 0 * 8] << 8) |
2310	(blk8x4Luma[3 + 3 * 8] >> 2);
2311	cmBodyBuf[3 + 8 * 0] = (blk8x4Luma[7 + 2 * 8] << 12) |
2312	(blk8x4Luma[7 + 1 * 8] << 2) | (blk8x4Luma[7 + 0 * 8] >>8);
2313	cmBodyBuf[4 + 8 * 0] = (blk8x4Luma[7 + 3 * 8] << 6) |
2314	(blk8x4Luma[7 + 2 * 8] >>4);
2315	cmBodyBuf[5 + 8 * 0] = (blk8x4Cr[0 + 0 * 4] << 10) |
2316	blk8x4Cb[0 + 0 * 4];
2317	cmBodyBuf[6 + 8 * 0] = (blk8x4Cr[0 + 1 * 4] << 14) |
2318	(blk8x4Cb[0 + 1 * 4] << 4) | (blk8x4Cr[0 + 0 * 4] >> 6);
2319	cmBodyBuf[7 + 8 * 0] = (0<< 8) | (blk8x4Cr[0 + 1 * 4] >> 2);
2320
2321	cmBodyBuf[0 + 8 * 1] = (blk8x4Luma[1 + 0 * 8] << 10) |
2322	blk8x4Luma[0 + 0 * 8];
2323	cmBodyBuf[1 + 8 * 1] = (blk8x4Luma[0 + 1 * 8] << 14) |
2324	(blk8x4Luma[2 + 0 * 8] << 4) | (blk8x4Luma[1 + 0 * 8] >> 6);
2325	cmBodyBuf[2 + 8 * 1] = (blk8x4Luma[1 + 1 * 8] << 8) |
2326	(blk8x4Luma[0 + 1 * 8] >> 2);
2327	cmBodyBuf[3 + 8 * 1] = (blk8x4Luma[0 + 2 * 8] << 12) |
2328	(blk8x4Luma[2 + 1 * 8] << 2) | (blk8x4Luma[1 + 1 * 8] >>8);
2329	cmBodyBuf[4 + 8 * 1] = (blk8x4Luma[1 + 2 * 8] << 6) |
2330	(blk8x4Luma[0 + 2 * 8] >>4);
2331	cmBodyBuf[5 + 8 * 1] = (blk8x4Luma[0 + 3 * 8] << 10) |
2332	blk8x4Luma[2 + 2 * 8];
2333	cmBodyBuf[6 + 8 * 1] = (blk8x4Luma[2 + 3 * 8] << 14) |
2334	(blk8x4Luma[1 + 3 * 8] << 4) | (blk8x4Luma[0 + 3 * 8] >> 6);
2335	cmBodyBuf[7 + 8 * 1] = (0<< 8) | (blk8x4Luma[2 + 3 * 8] >> 2);
2336
2337	cmBodyBuf[0 + 8 * 2] = (blk8x4Luma[5 + 0 * 8] << 10) |
2338	blk8x4Luma[4 + 0 * 8];
2339	cmBodyBuf[1 + 8 * 2] = (blk8x4Luma[4 + 1 * 8] << 14) |
2340	(blk8x4Luma[6 + 0 * 8] << 4) | (blk8x4Luma[5 + 0 * 8] >> 6);
2341	cmBodyBuf[2 + 8 * 2] = (blk8x4Luma[5 + 1 * 8] << 8) |
2342	(blk8x4Luma[4 + 1 * 8] >> 2);
2343	cmBodyBuf[3 + 8 * 2] = (blk8x4Luma[4 + 2 * 8] << 12) |
2344	(blk8x4Luma[6 + 1 * 8] << 2) | (blk8x4Luma[5 + 1 * 8] >>8);
2345	cmBodyBuf[4 + 8 * 2] = (blk8x4Luma[5 + 2 * 8] << 6) |
2346	(blk8x4Luma[4 + 2 * 8] >>4);
2347	cmBodyBuf[5 + 8 * 2] = (blk8x4Luma[4 + 3 * 8] << 10) |
2348	blk8x4Luma[6 + 2 * 8];
2349	cmBodyBuf[6 + 8 * 2] = (blk8x4Luma[6 + 3 * 8] << 14) |
2350	(blk8x4Luma[5 + 3 * 8] << 4) | (blk8x4Luma[4 + 3 * 8] >> 6);
2351	cmBodyBuf[7 + 8 * 2] = (0<< 8) | (blk8x4Luma[6 + 3 * 8] >> 2);
2352
2353	cmBodyBuf[0 + 8 * 3] = (blk8x4Cr[1 + 0 * 4] << 10) |
2354	blk8x4Cb[1 + 0 * 4];
2355	cmBodyBuf[1 + 8 * 3] = (blk8x4Cr[2 + 0 * 4] << 14) |
2356	(blk8x4Cb[2 + 0 * 4] << 4) | (blk8x4Cr[1 + 0 * 4] >> 6);
2357	cmBodyBuf[2 + 8 * 3] = (blk8x4Cb[3 + 0 * 4] << 8) |
2358	(blk8x4Cr[2 + 0 * 4] >> 2);
2359	cmBodyBuf[3 + 8 * 3] = (blk8x4Cb[1 + 1 * 4] << 12) |
2360	(blk8x4Cr[3 + 0 * 4] << 2) | (blk8x4Cb[3 + 0 * 4] >>8);
2361	cmBodyBuf[4 + 8 * 3] = (blk8x4Cr[1 + 1 * 4] << 6) |
2362	(blk8x4Cb[1 + 1 * 4] >>4);
2363	cmBodyBuf[5 + 8 * 3] = (blk8x4Cr[2 + 1 * 4] << 10) |
2364	blk8x4Cb[2 + 1 * 4];
2365	cmBodyBuf[6 + 8 * 3] = (blk8x4Cr[3 + 1 * 4] << 14) |
2366	(blk8x4Cb[3 + 1 * 4] << 4) | (blk8x4Cr[2 + 1 * 4] >> 6);
2367	cmBodyBuf[7 + 8 * 3] = (0 << 8) | (blk8x4Cr[3 + 1 * 4] >> 2);
2368	}
2369	}
2370
2371	static void corrRefillWithAmrisc (
2372	struct hevc_state_s *hevc,
2373	uint32_t cmHeaderBaseAddr,
2374	uint32_t picWidth,
2375	uint32_t ctuPosition)
2376	{
2377	int32_t i;
2378	uint16_t ctux = (ctuPosition>>16) & 0xffff;
2379	uint16_t ctuy = (ctuPosition>> 0) & 0xffff;
2380	int32_t aboveCtuAvailable = (ctuy) ? 1 : 0;
2381
2382	uint16_t cmBodyBuf[32 * 18];
2383
2384	uint32_t pic_width_x64_pre = picWidth + 0x3f;
2385	uint32_t pic_width_x64 = pic_width_x64_pre >> 6;
2386	uint32_t stride64x64 = pic_width_x64 * 128;
2387	uint32_t addr_offset64x64_abv = stride64x64 *
2388	(aboveCtuAvailable ? ctuy - 1 : ctuy) + 128 * ctux;
2389	uint32_t addr_offset64x64_cur = stride64x64*ctuy + 128 * ctux;
2390	uint32_t cmHeaderAddrAbv = cmHeaderBaseAddr + addr_offset64x64_abv;
2391	uint32_t cmHeaderAddrCur = cmHeaderBaseAddr + addr_offset64x64_cur;
2392	unsigned int tmpData32;
2393
2394	uint16_t blkBuf0Y[32];
2395	uint16_t blkBuf0Cb[8];
2396	uint16_t blkBuf0Cr[8];
2397	uint16_t blkBuf1Y[32];
2398	uint16_t blkBuf1Cb[8];
2399	uint16_t blkBuf1Cr[8];
2400	int32_t blkBufCnt = 0;
2401
2402	int32_t blkIdx;
2403
2404	WRITE_VREG(HEVC_SAO_CTRL10, cmHeaderAddrAbv);
2405	WRITE_VREG(HEVC_SAO_CTRL11, cmHeaderAddrCur);
2406	WRITE_VREG(HEVC_SAO_DBG_MODE0, hevc->detbuf_adr);
2407	WRITE_VREG(HEVC_SAO_DBG_MODE1, 2);
2408
2409	for (i = 0; i < 32 * 18; i++)
2410	cmBodyBuf[i] = 0;
2411
2412	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2413	"%s, %d\n", __func__, __LINE__);
2414	do {
2415	tmpData32 = READ_VREG(HEVC_SAO_DBG_MODE1);
2416	} while (tmpData32);
2417	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2418	"%s, %d\n", __func__, __LINE__);
2419
2420	hevc_print(hevc, H265_DEBUG_DETAIL,
2421	"cmBodyBuf from detbuf:\n");
2422	for (i = 0; i < 32 * 18; i++) {
2423	cmBodyBuf[i] = hevc->detbuf_adr_virt[i];
2424	if (get_dbg_flag(hevc) &
2425	H265_DEBUG_DETAIL) {
2426	if ((i & 0xf) == 0)
2427	hevc_print_cont(hevc, 0, "\n");
2428	hevc_print_cont(hevc, 0, "%02x ", cmBodyBuf[i]);
2429	}
2430	}
2431	hevc_print_cont(hevc, H265_DEBUG_DETAIL, "\n");
2432
2433	for (i = 0; i < 32; i++)
2434	blkBuf0Y[i] = 0;
2435	for (i = 0; i < 8; i++)
2436	blkBuf0Cb[i] = 0;
2437	for (i = 0; i < 8; i++)
2438	blkBuf0Cr[i] = 0;
2439	for (i = 0; i < 32; i++)
2440	blkBuf1Y[i] = 0;
2441	for (i = 0; i < 8; i++)
2442	blkBuf1Cb[i] = 0;
2443	for (i = 0; i < 8; i++)
2444	blkBuf1Cr[i] = 0;
2445
2446	for (blkIdx = 0; blkIdx < 18; blkIdx++) {
2447	int32_t inAboveCtu = (blkIdx<2) ? 1 : 0;
2448	int32_t restoreEnable = (blkIdx>0) ? 1 : 0;
2449	uint16_t* blkY = (blkBufCnt==0) ? blkBuf0Y : blkBuf1Y ;
2450	uint16_t* blkCb = (blkBufCnt==0) ? blkBuf0Cb : blkBuf1Cb;
2451	uint16_t* blkCr = (blkBufCnt==0) ? blkBuf0Cr : blkBuf1Cr;
2452	uint16_t* cmBodyBufNow = cmBodyBuf + (blkIdx * 32);
2453
2454	if (!aboveCtuAvailable && inAboveCtu)
2455	continue;
2456
2457	/* detRefillBuf --> 8x4block*/
2458	convUnc8x4blk(blkY, blkCb, blkCr, cmBodyBufNow, 0);
2459
2460	if (restoreEnable) {
2461	blkY[3 + 0 * 8] = blkY[2 + 0 * 8] + 2;
2462	blkY[4 + 0 * 8] = blkY[1 + 0 * 8] + 3;
2463	blkY[5 + 0 * 8] = blkY[0 + 0 * 8] + 1;
2464	blkY[6 + 0 * 8] = blkY[0 + 0 * 8] + 2;
2465	blkY[7 + 0 * 8] = blkY[1 + 0 * 8] + 2;
2466	blkY[3 + 1 * 8] = blkY[2 + 1 * 8] + 1;
2467	blkY[4 + 1 * 8] = blkY[1 + 1 * 8] + 2;
2468	blkY[5 + 1 * 8] = blkY[0 + 1 * 8] + 2;
2469	blkY[6 + 1 * 8] = blkY[0 + 1 * 8] + 2;
2470	blkY[7 + 1 * 8] = blkY[1 + 1 * 8] + 3;
2471	blkY[3 + 2 * 8] = blkY[2 + 2 * 8] + 3;
2472	blkY[4 + 2 * 8] = blkY[1 + 2 * 8] + 1;
2473	blkY[5 + 2 * 8] = blkY[0 + 2 * 8] + 3;
2474	blkY[6 + 2 * 8] = blkY[0 + 2 * 8] + 3;
2475	blkY[7 + 2 * 8] = blkY[1 + 2 * 8] + 3;
2476	blkY[3 + 3 * 8] = blkY[2 + 3 * 8] + 0;
2477	blkY[4 + 3 * 8] = blkY[1 + 3 * 8] + 0;
2478	blkY[5 + 3 * 8] = blkY[0 + 3 * 8] + 1;
2479	blkY[6 + 3 * 8] = blkY[0 + 3 * 8] + 2;
2480	blkY[7 + 3 * 8] = blkY[1 + 3 * 8] + 1;
2481	blkCb[1 + 0 * 4] = blkCb[0 + 0 * 4];
2482	blkCb[2 + 0 * 4] = blkCb[0 + 0 * 4];
2483	blkCb[3 + 0 * 4] = blkCb[0 + 0 * 4];
2484	blkCb[1 + 1 * 4] = blkCb[0 + 1 * 4];
2485	blkCb[2 + 1 * 4] = blkCb[0 + 1 * 4];
2486	blkCb[3 + 1 * 4] = blkCb[0 + 1 * 4];
2487	blkCr[1 + 0 * 4] = blkCr[0 + 0 * 4];
2488	blkCr[2 + 0 * 4] = blkCr[0 + 0 * 4];
2489	blkCr[3 + 0 * 4] = blkCr[0 + 0 * 4];
2490	blkCr[1 + 1 * 4] = blkCr[0 + 1 * 4];
2491	blkCr[2 + 1 * 4] = blkCr[0 + 1 * 4];
2492	blkCr[3 + 1 * 4] = blkCr[0 + 1 * 4];
2493
2494	/*Store data back to DDR*/
2495	convUnc8x4blk(blkY, blkCb, blkCr, cmBodyBufNow, 1);
2496	}
2497
2498	blkBufCnt = (blkBufCnt==1) ? 0 : blkBufCnt + 1;
2499	}
2500
2501	hevc_print(hevc, H265_DEBUG_DETAIL,
2502	"cmBodyBuf to detbuf:\n");
2503	for (i = 0; i < 32 * 18; i++) {
2504	hevc->detbuf_adr_virt[i] = cmBodyBuf[i];
2505	if (get_dbg_flag(hevc) &
2506	H265_DEBUG_DETAIL) {
2507	if ((i & 0xf) == 0)
2508	hevc_print_cont(hevc, 0, "\n");
2509	hevc_print_cont(hevc, 0, "%02x ", cmBodyBuf[i]);
2510	}
2511	}
2512	hevc_print_cont(hevc, H265_DEBUG_DETAIL, "\n");
2513
2514	WRITE_VREG(HEVC_SAO_DBG_MODE1, 3);
2515	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2516	"%s, %d\n", __func__, __LINE__);
2517	do {
2518	tmpData32 = READ_VREG(HEVC_SAO_DBG_MODE1);
2519	} while (tmpData32);
2520	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2521	"%s, %d\n", __func__, __LINE__);
2522	}
2523
2524	static void delrefill(struct hevc_state_s *hevc)
2525	{
2526	/*
2527	* corrRefill
2528	*/
2529	/*HEVC_SAO_DBG_MODE0: picGlobalVariable
2530	[31:30]error number
2531	[29:20]error2([9:7]tilex[6:0]ctuy)
2532	[19:10]error1 [9:0]error0*/
2533	uint32_t detResult = READ_VREG(HEVC_ASSIST_SCRATCH_3);
2534	uint32_t errorIdx;
2535	uint32_t errorNum = (detResult>>30);
2536
2537	if (detResult) {
2538	hevc_print(hevc, H265_DEBUG_BUFMGR,
2539	"[corrRefillWithAmrisc] detResult=%08x\n", detResult);
2540	for (errorIdx = 0; errorIdx < errorNum; errorIdx++) {
2541	uint32_t errorPos = errorIdx * 10;
2542	uint32_t errorResult = (detResult >> errorPos) & 0x3ff;
2543	uint32_t tilex = (errorResult >> 7) - 1;
2544	uint16_t ctux = hevc->m_tile[0][tilex].start_cu_x
2545	+ hevc->m_tile[0][tilex].width - 1;
2546	uint16_t ctuy = (uint16_t)(errorResult & 0x7f);
2547	uint32_t ctuPosition = (ctux<< 16) + ctuy;
2548	hevc_print(hevc, H265_DEBUG_BUFMGR,
2549	"Idx:%d tilex:%d ctu(%d(0x%x), %d(0x%x))\n",
2550	errorIdx,tilex,ctux,ctux, ctuy,ctuy);
2551	corrRefillWithAmrisc(
2552	hevc,
2553	(uint32_t)hevc->cur_pic->header_adr,
2554	hevc->pic_w,
2555	ctuPosition);
2556	}
2557
2558	WRITE_VREG(HEVC_ASSIST_SCRATCH_3, 0); /*clear status*/
2559	WRITE_VREG(HEVC_SAO_DBG_MODE0, 0);
2560	WRITE_VREG(HEVC_SAO_DBG_MODE1, 1);
2561	}
2562	}
2563	#endif
2564
2565	static void get_rpm_param(union param_u *params)
2566	{
2567	int i;
2568	unsigned int data32;
2569
2570	for (i = 0; i < 128; i++) {
2571	do {
2572	data32 = READ_VREG(RPM_CMD_REG);
2573	/* hevc_print(hevc, 0, "%x\n", data32); */
2574	} while ((data32 & 0x10000) == 0);
2575	params->l.data[i] = data32 & 0xffff;
2576	/* hevc_print(hevc, 0, "%x\n", data32); */
2577	WRITE_VREG(RPM_CMD_REG, 0);
2578	}
2579	}
2580
2581	static int get_free_buf_idx(struct hevc_state_s *hevc)
2582	{
2583	int index = INVALID_IDX;
2584	struct PIC_s *pic;
2585	int i;
2586
2587	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2588	pic = hevc->m_PIC[i];
2589	if (pic == NULL ||
2590	pic->index == -1 ||
2591	pic->BUF_index == -1)
2592	continue;
2593
2594	if (pic->output_mark == 0 &&
2595	pic->referenced == 0 &&
2596	pic->output_ready == 0) {
2597	pic->output_ready = 1;
2598	index = i;
2599	break;
2600	}
2601	}
2602
2603	return index;
2604	}
2605
2606	static struct PIC_s *get_pic_by_POC(struct hevc_state_s *hevc, int POC)
2607	{
2608	int i;
2609	struct PIC_s *pic;
2610	struct PIC_s *ret_pic = NULL;
2611	if (POC == INVALID_POC)
2612	return NULL;
2613	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2614	pic = hevc->m_PIC[i];
2615	if (pic == NULL || pic->index == -1 ||
2616	pic->BUF_index == -1)
2617	continue;
2618	if (pic->POC == POC) {
2619	if (ret_pic == NULL)
2620	ret_pic = pic;
2621	else {
2622	if (pic->decode_idx > ret_pic->decode_idx)
2623	ret_pic = pic;
2624	}
2625	}
2626	}
2627	return ret_pic;
2628	}
2629
2630	static struct PIC_s *get_ref_pic_by_POC(struct hevc_state_s *hevc, int POC)
2631	{
2632	int i;
2633	struct PIC_s *pic;
2634	struct PIC_s *ret_pic = NULL;
2635
2636	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2637	pic = hevc->m_PIC[i];
2638	if (pic == NULL || pic->index == -1 ||
2639	pic->BUF_index == -1)
2640	continue;
2641	if ((pic->POC == POC) && (pic->referenced)) {
2642	if (ret_pic == NULL)
2643	ret_pic = pic;
2644	else {
2645	if (pic->decode_idx > ret_pic->decode_idx)
2646	ret_pic = pic;
2647	}
2648	}
2649	}
2650
2651	if (ret_pic == NULL) {
2652	if (get_dbg_flag(hevc)) {
2653	hevc_print(hevc, 0,
2654	"Wrong, POC of %d is not in referenced list\n",
2655	POC);
2656	}
2657	ret_pic = get_pic_by_POC(hevc, POC);
2658	}
2659	return ret_pic;
2660	}
2661
2662	static unsigned int log2i(unsigned int val)
2663	{
2664	unsigned int ret = -1;
2665
2666	while (val != 0) {
2667	val >>= 1;
2668	ret++;
2669	}
2670	return ret;
2671	}
2672
2673	static int init_buf_spec(struct hevc_state_s *hevc);
2674
2675	static bool v4l_is_there_vframe_bound(struct hevc_state_s *hevc)
2676	{
2677	int i;
2678
2679	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2680	struct PIC_s *pic = hevc->m_PIC[i];
2681
2682	if (pic && pic->vframe_bound)
2683	return true;
2684	}
2685
2686	return false;
2687	}
2688
2689	static void v4l_mmu_buffer_release(struct hevc_state_s *hevc)
2690	{
2691	int i;
2692
2693	/* release workspace */
2694	if (hevc->bmmu_box)
2695	decoder_bmmu_box_free_idx(hevc->bmmu_box,
2696	BMMU_WORKSPACE_ID);
2697	/*
2698	* it's only when vframe get back to driver, right now we can be sure
2699	* that vframe and fd are related. if the playback exits, the capture
2700	* requires the upper app to release when the fd is closed, and others
2701	* buffers drivers are released by driver.
2702	*/
2703	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2704	struct PIC_s *pic = hevc->m_PIC[i];
2705
2706	if (pic && !pic->vframe_bound) {
2707	if (hevc->bmmu_box)
2708	decoder_bmmu_box_free_idx(hevc->bmmu_box,
2709	VF_BUFFER_IDX(i));
2710	if (hevc->mmu_box)
2711	decoder_mmu_box_free_idx(hevc->mmu_box, i);
2712
2713	hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,
2714	"%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
2715	__func__, i, hevc->bmmu_box, hevc->mmu_box);
2716	}
2717	}
2718	}
2719
2720	static void uninit_mmu_buffers(struct hevc_state_s *hevc)
2721	{
2722	if (hevc->is_used_v4l &&
2723	v4l_is_there_vframe_bound(hevc)) {
2724	if (get_double_write_mode(hevc) != 0x10) {
2725	v4l_mmu_buffer_release(hevc);
2726	return;
2727	}
2728	}
2729
2730	if (hevc->mmu_box)
2731	decoder_mmu_box_free(hevc->mmu_box);
2732	hevc->mmu_box = NULL;
2733
2734	if (hevc->bmmu_box)
2735	decoder_bmmu_box_free(hevc->bmmu_box);
2736	hevc->bmmu_box = NULL;
2737	}
2738	static int init_mmu_buffers(struct hevc_state_s *hevc)
2739	{
2740	int tvp_flag = vdec_secure(hw_to_vdec(hevc)) ?
2741	CODEC_MM_FLAGS_TVP : 0;
2742	int buf_size = 64;
2743
2744	if ((hevc->max_pic_w * hevc->max_pic_h) > 0 &&
2745	(hevc->max_pic_w * hevc->max_pic_h) <= 1920*1088) {
2746	buf_size = 24;
2747	}
2748
2749	if (get_dbg_flag(hevc)) {
2750	hevc_print(hevc, 0, "%s max_w %d max_h %d\n",
2751	__func__, hevc->max_pic_w, hevc->max_pic_h);
2752	}
2753
2754	hevc->need_cache_size = buf_size * SZ_1M;
2755	hevc->sc_start_time = get_jiffies_64();
2756	if (hevc->mmu_enable
2757	&& ((get_double_write_mode(hevc) & 0x10) == 0)) {
2758	hevc->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
2759	hevc->index,
2760	MAX_REF_PIC_NUM,
2761	buf_size * SZ_1M,
2762	tvp_flag
2763	);
2764	if (!hevc->mmu_box) {
2765	pr_err("h265 alloc mmu box failed!!\n");
2766	return -1;
2767	}
2768	}
2769
2770	hevc->bmmu_box = decoder_bmmu_box_alloc_box(DRIVER_NAME,
2771	hevc->index,
2772	BMMU_MAX_BUFFERS,
2773	4 + PAGE_SHIFT,
2774	CODEC_MM_FLAGS_CMA_CLEAR |
2775	CODEC_MM_FLAGS_FOR_VDECODER |
2776	tvp_flag);
2777	if (!hevc->bmmu_box) {
2778	if (hevc->mmu_box)
2779	decoder_mmu_box_free(hevc->mmu_box);
2780	hevc->mmu_box = NULL;
2781	pr_err("h265 alloc mmu box failed!!\n");
2782	return -1;
2783	}
2784	return 0;
2785	}
2786
2787	struct buf_stru_s
2788	{
2789	int lcu_total;
2790	int mc_buffer_size_h;
2791	int mc_buffer_size_u_v_h;
2792	};
2793
2794	#ifndef MV_USE_FIXED_BUF
2795	static void dealloc_mv_bufs(struct hevc_state_s *hevc)
2796	{
2797	int i;
2798	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2799	if (hevc->m_mv_BUF[i].start_adr) {
2800	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
2801	hevc_print(hevc, 0,
2802	"dealloc mv buf(%d) adr 0x%p size 0x%x used_flag %d\n",
2803	i, hevc->m_mv_BUF[i].start_adr,
2804	hevc->m_mv_BUF[i].size,
2805	hevc->m_mv_BUF[i].used_flag);
2806	decoder_bmmu_box_free_idx(
2807	hevc->bmmu_box,
2808	MV_BUFFER_IDX(i));
2809	hevc->m_mv_BUF[i].start_adr = 0;
2810	hevc->m_mv_BUF[i].size = 0;
2811	hevc->m_mv_BUF[i].used_flag = 0;
2812	}
2813	}
2814	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2815	if (hevc->m_PIC[i] != NULL)
2816	hevc->m_PIC[i]->mv_buf_index = -1;
2817	}
2818	}
2819
2820	static int alloc_mv_buf(struct hevc_state_s *hevc, int i)
2821	{
2822	int ret = 0;
2823	/*get_cma_alloc_ref();*/ /*DEBUG_TMP*/
2824	if (decoder_bmmu_box_alloc_buf_phy
2825	(hevc->bmmu_box,
2826	MV_BUFFER_IDX(i), hevc->mv_buf_size,
2827	DRIVER_NAME,
2828	&hevc->m_mv_BUF[i].start_adr) < 0) {
2829	hevc->m_mv_BUF[i].start_adr = 0;
2830	ret = -1;
2831	} else {
2832	hevc->m_mv_BUF[i].size = hevc->mv_buf_size;
2833	hevc->m_mv_BUF[i].used_flag = 0;
2834	ret = 0;
2835	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
2836	hevc_print(hevc, 0,
2837	"MV Buffer %d: start_adr %p size %x\n",
2838	i,
2839	(void *)hevc->m_mv_BUF[i].start_adr,
2840	hevc->m_mv_BUF[i].size);
2841	}
2842	if (!vdec_secure(hw_to_vdec(hevc)) && (hevc->m_mv_BUF[i].start_adr)) {
2843	void *mem_start_virt;
2844	mem_start_virt =
2845	codec_mm_phys_to_virt(hevc->m_mv_BUF[i].start_adr);
2846	if (mem_start_virt) {
2847	memset(mem_start_virt, 0, hevc->m_mv_BUF[i].size);
2848	codec_mm_dma_flush(mem_start_virt,
2849	hevc->m_mv_BUF[i].size, DMA_TO_DEVICE);
2850	} else {
2851	mem_start_virt = codec_mm_vmap(
2852	hevc->m_mv_BUF[i].start_adr,
2853	hevc->m_mv_BUF[i].size);
2854	if (mem_start_virt) {
2855	memset(mem_start_virt, 0, hevc->m_mv_BUF[i].size);
2856	codec_mm_dma_flush(mem_start_virt,
2857	hevc->m_mv_BUF[i].size,
2858	DMA_TO_DEVICE);
2859	codec_mm_unmap_phyaddr(mem_start_virt);
2860	} else {
2861	/*not virt for tvp playing,
2862	may need clear on ucode.*/
2863	pr_err("ref %s mem_start_virt failed\n", __func__);
2864	}
2865	}
2866	}
2867	}
2868	/*put_cma_alloc_ref();*/ /*DEBUG_TMP*/
2869	return ret;
2870	}
2871	#endif
2872
2873	static int get_mv_buf(struct hevc_state_s *hevc, struct PIC_s *pic)
2874	{
2875	#ifdef MV_USE_FIXED_BUF
2876	if (pic && pic->index >= 0) {
2877	if (IS_8K_SIZE(pic->width, pic->height)) {
2878	pic->mpred_mv_wr_start_addr =
2879	hevc->work_space_buf->mpred_mv.buf_start
2880	+ (pic->index * MPRED_8K_MV_BUF_SIZE);
2881	} else {
2882	pic->mpred_mv_wr_start_addr =
2883	hevc->work_space_buf->mpred_mv.buf_start
2884	+ (pic->index * MPRED_4K_MV_BUF_SIZE);
2885	}
2886	}
2887	return 0;
2888	#else
2889	int i;
2890	int ret = -1;
2891	int new_size;
2892	if (IS_8K_SIZE(pic->width, pic->height))
2893	new_size = MPRED_8K_MV_BUF_SIZE + 0x10000;
2894	else if (IS_4K_SIZE(pic->width, pic->height))
2895	new_size = MPRED_4K_MV_BUF_SIZE + 0x10000; /*0x120000*/
2896	else
2897	new_size = MPRED_MV_BUF_SIZE + 0x10000;
2898	if (new_size != hevc->mv_buf_size) {
2899	dealloc_mv_bufs(hevc);
2900	hevc->mv_buf_size = new_size;
2901	}
2902	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2903	if (hevc->m_mv_BUF[i].start_adr &&
2904	hevc->m_mv_BUF[i].used_flag == 0) {
2905	hevc->m_mv_BUF[i].used_flag = 1;
2906	ret = i;
2907	break;
2908	}
2909	}
2910	if (ret < 0) {
2911	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
2912	if (hevc->m_mv_BUF[i].start_adr == 0) {
2913	if (alloc_mv_buf(hevc, i) >= 0) {
2914	hevc->m_mv_BUF[i].used_flag = 1;
2915	ret = i;
2916	}
2917	break;
2918	}
2919	}
2920	}
2921
2922	if (ret >= 0) {
2923	pic->mv_buf_index = ret;
2924	pic->mpred_mv_wr_start_addr =
2925	(hevc->m_mv_BUF[ret].start_adr + 0xffff) &
2926	(~0xffff);
2927	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2928	"%s => %d (0x%x) size 0x%x\n",
2929	__func__, ret,
2930	pic->mpred_mv_wr_start_addr,
2931	hevc->m_mv_BUF[ret].size);
2932
2933	} else {
2934	hevc_print(hevc, 0,
2935	"%s: Error, mv buf is not enough\n",
2936	__func__);
2937	}
2938	return ret;
2939
2940	#endif
2941	}
2942
2943	static void put_mv_buf(struct hevc_state_s *hevc,
2944	struct PIC_s *pic)
2945	{
2946	#ifndef MV_USE_FIXED_BUF
2947	int i = pic->mv_buf_index;
2948	if (i < 0 || i >= MAX_REF_PIC_NUM) {
2949	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2950	"%s: index %d beyond range\n",
2951	__func__, i);
2952	return;
2953	}
2954	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
2955	"%s(%d): used_flag(%d)\n",
2956	__func__, i,
2957	hevc->m_mv_BUF[i].used_flag);
2958
2959	if (hevc->m_mv_BUF[i].start_adr &&
2960	hevc->m_mv_BUF[i].used_flag)
2961	hevc->m_mv_BUF[i].used_flag = 0;
2962	pic->mv_buf_index = -1;
2963	#endif
2964	}
2965
2966	static int cal_current_buf_size(struct hevc_state_s *hevc,
2967	struct buf_stru_s *buf_stru)
2968	{
2969
2970	int buf_size;
2971	int pic_width = hevc->pic_w;
2972	int pic_height = hevc->pic_h;
2973	int lcu_size = hevc->lcu_size;
2974	int pic_width_lcu = (pic_width % lcu_size) ? pic_width / lcu_size +
2975	1 : pic_width / lcu_size;
2976	int pic_height_lcu = (pic_height % lcu_size) ? pic_height / lcu_size +
2977	1 : pic_height / lcu_size;
2978	/*SUPPORT_10BIT*/
2979	int losless_comp_header_size = compute_losless_comp_header_size
2980	(pic_width, pic_height);
2981	/*always alloc buf for 10bit*/
2982	int losless_comp_body_size = compute_losless_comp_body_size
2983	(hevc, pic_width, pic_height, 0);
2984	int mc_buffer_size = losless_comp_header_size
2985	+ losless_comp_body_size;
2986	int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
2987	int mc_buffer_size_u_v_h = 0;
2988
2989	int dw_mode = get_double_write_mode(hevc);
2990
2991	if (hevc->mmu_enable) {
2992	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
2993	(IS_8K_SIZE(hevc->pic_w, hevc->pic_h)))
2994	buf_size = ((MMU_COMPRESS_8K_HEADER_SIZE + 0xffff) >> 16)
2995	<< 16;
2996	else
2997	buf_size = ((MMU_COMPRESS_HEADER_SIZE + 0xffff) >> 16)
2998	<< 16;
2999	} else
3000	buf_size = 0;
3001
3002	if (dw_mode) {
3003	int pic_width_dw = pic_width /
3004	get_double_write_ratio(hevc, dw_mode);
3005	int pic_height_dw = pic_height /
3006	get_double_write_ratio(hevc, dw_mode);
3007
3008	int pic_width_lcu_dw = (pic_width_dw % lcu_size) ?
3009	pic_width_dw / lcu_size + 1 :
3010	pic_width_dw / lcu_size;
3011	int pic_height_lcu_dw = (pic_height_dw % lcu_size) ?
3012	pic_height_dw / lcu_size + 1 :
3013	pic_height_dw / lcu_size;
3014	int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
3015
3016	int mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
3017	mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
3018	/*64k alignment*/
3019	buf_size += ((mc_buffer_size_u_v_h << 16) * 3);
3020	}
3021
3022	if ((!hevc->mmu_enable) &&
3023	((dw_mode & 0x10) == 0)) {
3024	/* use compress mode without mmu,
3025	need buf for compress decoding*/
3026	buf_size += (mc_buffer_size_h << 16);
3027	}
3028
3029	/*in case start adr is not 64k alignment*/
3030	if (buf_size > 0)
3031	buf_size += 0x10000;
3032
3033	if (buf_stru) {
3034	buf_stru->lcu_total = pic_width_lcu * pic_height_lcu;
3035	buf_stru->mc_buffer_size_h = mc_buffer_size_h;
3036	buf_stru->mc_buffer_size_u_v_h = mc_buffer_size_u_v_h;
3037	}
3038
3039	hevc_print(hevc, PRINT_FLAG_V4L_DETAIL,"pic width: %d, pic height: %d, headr: %d, body: %d, size h: %d, size uvh: %d, buf size: %x\n",
3040	pic_width, pic_height, losless_comp_header_size,
3041	losless_comp_body_size, mc_buffer_size_h,
3042	mc_buffer_size_u_v_h, buf_size);
3043
3044	return buf_size;
3045	}
3046
3047	static int v4l_alloc_buf(struct hevc_state_s *hevc)
3048	{
3049	int i;
3050	int ret = -1;
3051	struct vdec_v4l2_buffer *fb = NULL;
3052
3053	if (hevc->fatal_error & DECODER_FATAL_ERROR_NO_MEM)
3054	return ret;
3055
3056	ret = vdec_v4l_get_buffer(hevc->v4l2_ctx, &fb);
3057	if (ret < 0) {
3058	hevc_print(hevc, 0, "[%d] H265 get buffer fail.\n",
3059	((struct aml_vcodec_ctx *)(hevc->v4l2_ctx))->id);
3060	return ret;
3061	}
3062
3063	for (i = 0; i < BUF_POOL_SIZE; i++)
3064	if (hevc->m_BUF[i].start_adr == 0)
3065	break;
3066
3067	if (hevc->mmu_enable) {
3068	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
3069	(IS_8K_SIZE(hevc->pic_w, hevc->pic_h)))
3070	hevc->m_BUF[i].header_size =
3071	ALIGN(MMU_COMPRESS_8K_HEADER_SIZE, 0x10000);
3072	else
3073	hevc->m_BUF[i].header_size =
3074	ALIGN(MMU_COMPRESS_HEADER_SIZE, 0x10000);
3075
3076	ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box,
3077	VF_BUFFER_IDX(i), hevc->m_BUF[i].header_size,
3078	DRIVER_NAME, &hevc->m_BUF[i].header_addr);
3079	if (ret < 0) {
3080	hevc_print(hevc, PRINT_FLAG_ERROR,
3081	"%s[%d], header size: %d, no mem fatal err\n",
3082	__func__, i, hevc->m_BUF[i].header_size);
3083	return ret;
3084	}
3085	}
3086
3087	hevc->m_BUF[i].used_flag = 0;
3088	hevc->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
3089	if (fb->num_planes == 1) {
3090	hevc->m_BUF[i].start_adr = fb->m.mem[0].addr;
3091	hevc->m_BUF[i].size = fb->m.mem[0].size;
3092	hevc->m_BUF[i].luma_size = fb->m.mem[0].offset;
3093	fb->m.mem[0].bytes_used = fb->m.mem[0].size;
3094	} else if (fb->num_planes == 2) {
3095	hevc->m_BUF[i].start_adr = fb->m.mem[0].addr;
3096	hevc->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
3097	hevc->m_BUF[i].luma_size = fb->m.mem[0].size;
3098	fb->m.mem[0].bytes_used = fb->m.mem[0].size;
3099	fb->m.mem[1].bytes_used = fb->m.mem[1].size;
3100	}
3101
3102	return ret;
3103	}
3104
3105	static int alloc_buf(struct hevc_state_s *hevc)
3106	{
3107	int i;
3108	int ret = -1;
3109	int buf_size = cal_current_buf_size(hevc, NULL);
3110
3111	if (hevc->fatal_error & DECODER_FATAL_ERROR_NO_MEM)
3112	return ret;
3113
3114	for (i = 0; i < BUF_POOL_SIZE; i++) {
3115	if (hevc->m_BUF[i].start_adr == 0)
3116	break;
3117	}
3118	if (i < BUF_POOL_SIZE) {
3119	if (buf_size > 0) {
3120	ret = decoder_bmmu_box_alloc_buf_phy
3121	(hevc->bmmu_box,
3122	VF_BUFFER_IDX(i), buf_size,
3123	DRIVER_NAME,
3124	&hevc->m_BUF[i].start_adr);
3125	if (ret < 0) {
3126	hevc->m_BUF[i].start_adr = 0;
3127	if (i <= 8) {
3128	hevc->fatal_error |=
3129	DECODER_FATAL_ERROR_NO_MEM;
3130	hevc_print(hevc, PRINT_FLAG_ERROR,
3131	"%s[%d], size: %d, no mem fatal err\n",
3132	__func__, i, buf_size);
3133	}
3134	}
3135
3136	if (ret >= 0) {
3137	hevc->m_BUF[i].size = buf_size;
3138	hevc->m_BUF[i].used_flag = 0;
3139	ret = 0;
3140
3141	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3142	hevc_print(hevc, 0,
3143	"Buffer %d: start_adr %p size %x\n",
3144	i,
3145	(void *)hevc->m_BUF[i].start_adr,
3146	hevc->m_BUF[i].size);
3147	}
3148	/*flush the buffer make sure no cache dirty*/
3149	if (!vdec_secure(hw_to_vdec(hevc)) && (hevc->m_BUF[i].start_adr)) {
3150	void *mem_start_virt;
3151	mem_start_virt =
3152	codec_mm_phys_to_virt(hevc->m_BUF[i].start_adr);
3153	if (mem_start_virt) {
3154	memset(mem_start_virt, 0, hevc->m_BUF[i].size);
3155	codec_mm_dma_flush(mem_start_virt,
3156	hevc->m_BUF[i].size, DMA_TO_DEVICE);
3157	} else {
3158	mem_start_virt = codec_mm_vmap(
3159	hevc->m_BUF[i].start_adr,
3160	hevc->m_BUF[i].size);
3161	if (mem_start_virt) {
3162	memset(mem_start_virt, 0, hevc->m_BUF[i].size);
3163	codec_mm_dma_flush(mem_start_virt,
3164	hevc->m_BUF[i].size,
3165	DMA_TO_DEVICE);
3166	codec_mm_unmap_phyaddr(mem_start_virt);
3167	} else {
3168	/*not virt for tvp playing,
3169	may need clear on ucode.*/
3170	pr_err("ref %s mem_start_virt failed\n", __func__);
3171	}
3172	}
3173	}
3174	}
3175	/*put_cma_alloc_ref();*/ /*DEBUG_TMP*/
3176	} else
3177	ret = 0;
3178	}
3179
3180	if (ret >= 0) {
3181	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3182	hevc_print(hevc, 0,
3183	"alloc buf(%d) for %d/%d size 0x%x) => %p\n",
3184	i, hevc->pic_w, hevc->pic_h,
3185	buf_size,
3186	hevc->m_BUF[i].start_adr);
3187	}
3188	} else {
3189	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3190	hevc_print(hevc, 0,
3191	"alloc buf(%d) for %d/%d size 0x%x) => Fail!!!\n",
3192	i, hevc->pic_w, hevc->pic_h,
3193	buf_size);
3194	}
3195	}
3196	return ret;
3197	}
3198
3199	static void set_buf_unused(struct hevc_state_s *hevc, int i)
3200	{
3201	if (i >= 0 && i < BUF_POOL_SIZE)
3202	hevc->m_BUF[i].used_flag = 0;
3203	}
3204
3205	static void dealloc_unused_buf(struct hevc_state_s *hevc)
3206	{
3207	int i;
3208	for (i = 0; i < BUF_POOL_SIZE; i++) {
3209	if (hevc->m_BUF[i].start_adr &&
3210	hevc->m_BUF[i].used_flag == 0) {
3211	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3212	hevc_print(hevc, 0,
3213	"dealloc buf(%d) adr 0x%p size 0x%x\n",
3214	i, hevc->m_BUF[i].start_adr,
3215	hevc->m_BUF[i].size);
3216	}
3217	if (!hevc->is_used_v4l)
3218	decoder_bmmu_box_free_idx(
3219	hevc->bmmu_box,
3220	VF_BUFFER_IDX(i));
3221	hevc->m_BUF[i].start_adr = 0;
3222	hevc->m_BUF[i].size = 0;
3223	}
3224	}
3225	}
3226
3227	static void dealloc_pic_buf(struct hevc_state_s *hevc,
3228	struct PIC_s *pic)
3229	{
3230	int i = pic->BUF_index;
3231	pic->BUF_index = -1;
3232	if (i >= 0 &&
3233	i < BUF_POOL_SIZE &&
3234	hevc->m_BUF[i].start_adr) {
3235	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3236	hevc_print(hevc, 0,
3237	"dealloc buf(%d) adr 0x%p size 0x%x\n",
3238	i, hevc->m_BUF[i].start_adr,
3239	hevc->m_BUF[i].size);
3240	}
3241
3242	if (!hevc->is_used_v4l)
3243	decoder_bmmu_box_free_idx(
3244	hevc->bmmu_box,
3245	VF_BUFFER_IDX(i));
3246	hevc->m_BUF[i].used_flag = 0;
3247	hevc->m_BUF[i].start_adr = 0;
3248	hevc->m_BUF[i].size = 0;
3249	}
3250	}
3251
3252	static int get_work_pic_num(struct hevc_state_s *hevc)
3253	{
3254	int used_buf_num = 0;
3255	int sps_pic_buf_diff = 0;
3256
3257	if (get_dynamic_buf_num_margin(hevc) > 0) {
3258	if ((!hevc->sps_num_reorder_pics_0) &&
3259	(hevc->param.p.sps_max_dec_pic_buffering_minus1_0)) {
3260	/* the range of sps_num_reorder_pics_0 is in
3261	[0, sps_max_dec_pic_buffering_minus1_0] */
3262	used_buf_num = get_dynamic_buf_num_margin(hevc) +
3263	hevc->param.p.sps_max_dec_pic_buffering_minus1_0;
3264	} else
3265	used_buf_num = hevc->sps_num_reorder_pics_0
3266	+ get_dynamic_buf_num_margin(hevc);
3267
3268	sps_pic_buf_diff = hevc->param.p.sps_max_dec_pic_buffering_minus1_0
3269	- hevc->sps_num_reorder_pics_0;
3270	#ifdef MULTI_INSTANCE_SUPPORT
3271	/*
3272	need one more for multi instance, as
3273	apply_ref_pic_set() has no chanch to run to
3274	to clear referenced flag in some case
3275	*/
3276	if (hevc->m_ins_flag)
3277	used_buf_num++;
3278	#endif
3279	} else
3280	used_buf_num = max_buf_num;
3281
3282	if (hevc->save_buffer_mode)
3283	hevc_print(hevc, 0,
3284	"save buf _mode : dynamic_buf_num_margin %d ----> %d \n",
3285	dynamic_buf_num_margin, hevc->dynamic_buf_num_margin);
3286
3287	if (sps_pic_buf_diff >= 4)
3288	{
3289	used_buf_num += 1;
3290	}
3291
3292	if (used_buf_num > MAX_BUF_NUM)
3293	used_buf_num = MAX_BUF_NUM;
3294	return used_buf_num;
3295	}
3296
3297	static int get_alloc_pic_count(struct hevc_state_s *hevc)
3298	{
3299	int alloc_pic_count = 0;
3300	int i;
3301	struct PIC_s *pic;
3302	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3303	pic = hevc->m_PIC[i];
3304	if (pic && pic->index >= 0)
3305	alloc_pic_count++;
3306	}
3307	return alloc_pic_count;
3308	}
3309
3310	static int v4l_config_pic(struct hevc_state_s *hevc, struct PIC_s *pic)
3311	{
3312	int i;
3313	int dw_mode = get_double_write_mode(hevc);
3314
3315	for (i = 0; i < BUF_POOL_SIZE; i++) {
3316	if (hevc->m_BUF[i].start_adr != 0 &&
3317	hevc->m_BUF[i].used_flag == 0) {
3318	hevc->m_BUF[i].used_flag = 1;
3319	break;
3320	}
3321	}
3322
3323	if (i >= BUF_POOL_SIZE)
3324	return -1;
3325
3326	if (hevc->mmu_enable)
3327	pic->header_adr = hevc->m_BUF[i].header_addr;
3328
3329	pic->BUF_index = i;
3330	pic->POC = INVALID_POC;
3331	pic->mc_canvas_y = pic->index;
3332	pic->mc_canvas_u_v = pic->index;
3333
3334	if (dw_mode & 0x10) {
3335	pic->mc_y_adr = hevc->m_BUF[i].start_adr;
3336	pic->mc_u_v_adr = pic->mc_y_adr + hevc->m_BUF[i].luma_size;
3337	pic->mc_canvas_y = (pic->index << 1);
3338	pic->mc_canvas_u_v = (pic->index << 1) + 1;
3339
3340	pic->dw_y_adr = pic->mc_y_adr;
3341	pic->dw_u_v_adr = pic->mc_u_v_adr;
3342	} else if (dw_mode) {
3343	pic->dw_y_adr = hevc->m_BUF[i].start_adr;
3344	pic->dw_u_v_adr = pic->dw_y_adr + hevc->m_BUF[i].luma_size;
3345	}
3346
3347	return 0;
3348	}
3349
3350	static int config_pic(struct hevc_state_s *hevc, struct PIC_s *pic)
3351	{
3352	int ret = -1;
3353	int i;
3354	/*int lcu_size_log2 = hevc->lcu_size_log2;
3355	int MV_MEM_UNIT=lcu_size_log2==
3356	6 ? 0x100 : lcu_size_log2==5 ? 0x40 : 0x10;*/
3357	/*int MV_MEM_UNIT = lcu_size_log2 == 6 ? 0x200 : lcu_size_log2 ==
3358	5 ? 0x80 : 0x20;
3359	int mpred_mv_end = hevc->work_space_buf->mpred_mv.buf_start +
3360	hevc->work_space_buf->mpred_mv.buf_size;*/
3361	unsigned int y_adr = 0;
3362	struct buf_stru_s buf_stru;
3363	int buf_size = cal_current_buf_size(hevc, &buf_stru);
3364	int dw_mode = get_double_write_mode(hevc);
3365
3366	for (i = 0; i < BUF_POOL_SIZE; i++) {
3367	if (hevc->m_BUF[i].start_adr != 0 &&
3368	hevc->m_BUF[i].used_flag == 0 &&
3369	buf_size <= hevc->m_BUF[i].size) {
3370	hevc->m_BUF[i].used_flag = 1;
3371	break;
3372	}
3373	}
3374
3375	if (i >= BUF_POOL_SIZE)
3376	return -1;
3377
3378	if (hevc->mmu_enable) {
3379	pic->header_adr = hevc->m_BUF[i].start_adr;
3380	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
3381	(IS_8K_SIZE(hevc->pic_w, hevc->pic_h)))
3382	y_adr = hevc->m_BUF[i].start_adr +
3383	MMU_COMPRESS_8K_HEADER_SIZE;
3384	else
3385	y_adr = hevc->m_BUF[i].start_adr +
3386	MMU_COMPRESS_HEADER_SIZE;
3387	} else
3388	y_adr = hevc->m_BUF[i].start_adr;
3389
3390	y_adr = ((y_adr + 0xffff) >> 16) << 16; /*64k alignment*/
3391
3392	pic->POC = INVALID_POC;
3393	/*ensure get_pic_by_POC()
3394	not get the buffer not decoded*/
3395	pic->BUF_index = i;
3396
3397	if ((!hevc->mmu_enable) &&
3398	((dw_mode & 0x10) == 0)
3399	) {
3400	pic->mc_y_adr = y_adr;
3401	y_adr += (buf_stru.mc_buffer_size_h << 16);
3402	}
3403	pic->mc_canvas_y = pic->index;
3404	pic->mc_canvas_u_v = pic->index;
3405	if (dw_mode & 0x10) {
3406	pic->mc_y_adr = y_adr;
3407	pic->mc_u_v_adr = y_adr +
3408	((buf_stru.mc_buffer_size_u_v_h << 16) << 1);
3409	pic->mc_canvas_y = (pic->index << 1);
3410	pic->mc_canvas_u_v = (pic->index << 1) + 1;
3411
3412	pic->dw_y_adr = pic->mc_y_adr;
3413	pic->dw_u_v_adr = pic->mc_u_v_adr;
3414	} else if (dw_mode) {
3415	pic->dw_y_adr = y_adr;
3416	pic->dw_u_v_adr = pic->dw_y_adr +
3417	((buf_stru.mc_buffer_size_u_v_h << 16) << 1);
3418	}
3419
3420	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3421	hevc_print(hevc, 0,
3422	"%s index %d BUF_index %d mc_y_adr %x\n",
3423	__func__, pic->index,
3424	pic->BUF_index, pic->mc_y_adr);
3425	if (hevc->mmu_enable &&
3426	dw_mode)
3427	hevc_print(hevc, 0,
3428	"mmu double write adr %ld\n",
3429	pic->cma_alloc_addr);
3430	}
3431	ret = 0;
3432
3433	return ret;
3434	}
3435
3436	static void init_pic_list(struct hevc_state_s *hevc)
3437	{
3438	int i;
3439	int init_buf_num = get_work_pic_num(hevc);
3440	int dw_mode = get_double_write_mode(hevc);
3441	struct vdec_s *vdec = hw_to_vdec(hevc);
3442	/*alloc decoder buf will be delay if work on v4l. */
3443	if (!hevc->is_used_v4l) {
3444	for (i = 0; i < init_buf_num; i++) {
3445	if (alloc_buf(hevc) < 0) {
3446	if (i <= 8) {
3447	/*if alloced (i+1)>=9
3448	don't send errors.*/
3449	hevc->fatal_error |=
3450	DECODER_FATAL_ERROR_NO_MEM;
3451	}
3452	break;
3453	}
3454	}
3455	}
3456
3457	for (i = 0; i < init_buf_num; i++) {
3458	struct PIC_s *pic = hevc->m_PIC[i];
3459
3460	if (!pic) {
3461	pic = vmalloc(sizeof(struct PIC_s));
3462	if (pic == NULL) {
3463	hevc_print(hevc, 0,
3464	"%s: alloc pic %d fail!!!\n",
3465	__func__, i);
3466	break;
3467	}
3468	hevc->m_PIC[i] = pic;
3469	}
3470	memset(pic, 0, sizeof(struct PIC_s));
3471
3472	pic->index = i;
3473	pic->BUF_index = -1;
3474	pic->mv_buf_index = -1;
3475	if (vdec->parallel_dec == 1) {
3476	pic->y_canvas_index = -1;
3477	pic->uv_canvas_index = -1;
3478	}
3479
3480	pic->width = hevc->pic_w;
3481	pic->height = hevc->pic_h;
3482	pic->double_write_mode = dw_mode;
3483
3484	/*config canvas will be delay if work on v4l. */
3485	if (!hevc->is_used_v4l) {
3486	if (config_pic(hevc, pic) < 0) {
3487	if (get_dbg_flag(hevc))
3488	hevc_print(hevc, 0,
3489	"Config_pic %d fail\n", pic->index);
3490	pic->index = -1;
3491	i++;
3492	break;
3493	}
3494
3495	if (pic->double_write_mode)
3496	set_canvas(hevc, pic);
3497	}
3498	}
3499
3500	for (; i < MAX_REF_PIC_NUM; i++) {
3501	struct PIC_s *pic = hevc->m_PIC[i];
3502
3503	if (!pic) {
3504	pic = vmalloc(sizeof(struct PIC_s));
3505	if (pic == NULL) {
3506	hevc_print(hevc, 0,
3507	"%s: alloc pic %d fail!!!\n",
3508	__func__, i);
3509	break;
3510	}
3511	hevc->m_PIC[i] = pic;
3512	}
3513	memset(pic, 0, sizeof(struct PIC_s));
3514
3515	pic->index = -1;
3516	pic->BUF_index = -1;
3517	if (vdec->parallel_dec == 1) {
3518	pic->y_canvas_index = -1;
3519	pic->uv_canvas_index = -1;
3520	}
3521	}
3522
3523	}
3524
3525	static void uninit_pic_list(struct hevc_state_s *hevc)
3526	{
3527	struct vdec_s *vdec = hw_to_vdec(hevc);
3528	int i;
3529	#ifndef MV_USE_FIXED_BUF
3530	dealloc_mv_bufs(hevc);
3531	#endif
3532	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3533	struct PIC_s *pic = hevc->m_PIC[i];
3534
3535	if (pic) {
3536	if (vdec->parallel_dec == 1) {
3537	vdec->free_canvas_ex(pic->y_canvas_index, vdec->id);
3538	vdec->free_canvas_ex(pic->uv_canvas_index, vdec->id);
3539	}
3540	release_aux_data(hevc, pic);
3541	vfree(pic);
3542	hevc->m_PIC[i] = NULL;
3543	}
3544	}
3545	}
3546
3547	#ifdef LOSLESS_COMPRESS_MODE
3548	static void init_decode_head_hw(struct hevc_state_s *hevc)
3549	{
3550
3551	struct BuffInfo_s *buf_spec = hevc->work_space_buf;
3552	unsigned int data32;
3553
3554	int losless_comp_header_size =
3555	compute_losless_comp_header_size(hevc->pic_w,
3556	hevc->pic_h);
3557	int losless_comp_body_size = compute_losless_comp_body_size(hevc,
3558	hevc->pic_w, hevc->pic_h, hevc->mem_saving_mode);
3559
3560	hevc->losless_comp_body_size = losless_comp_body_size;
3561
3562
3563	if (hevc->mmu_enable) {
3564	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
3565	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0);
3566	} else {
3567	if (hevc->mem_saving_mode == 1)
3568	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
3569	(1 << 3) | ((workaround_enable & 2) ? 1 : 0));
3570	else
3571	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
3572	((workaround_enable & 2) ? 1 : 0));
3573	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
3574	/*
3575	*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);
3576	* //8-bit mode
3577	*/
3578	}
3579	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
3580	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
3581	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
3582
3583	if (hevc->mmu_enable) {
3584	WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
3585	WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR,
3586	buf_spec->mmu_vbh.buf_start +
3587	buf_spec->mmu_vbh.buf_size/2);
3588	data32 = READ_VREG(HEVC_SAO_CTRL9);
3589	data32 |= 0x1;
3590	WRITE_VREG(HEVC_SAO_CTRL9, data32);
3591
3592	/* use HEVC_CM_HEADER_START_ADDR */
3593	data32 = READ_VREG(HEVC_SAO_CTRL5);
3594	data32 |= (1<<10);
3595	WRITE_VREG(HEVC_SAO_CTRL5, data32);
3596	}
3597
3598	if (!hevc->m_ins_flag)
3599	hevc_print(hevc, 0,
3600	"%s: (%d, %d) body_size 0x%x header_size 0x%x\n",
3601	__func__, hevc->pic_w, hevc->pic_h,
3602	losless_comp_body_size, losless_comp_header_size);
3603
3604	}
3605	#endif
3606	#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
3607
3608	static void init_pic_list_hw(struct hevc_state_s *hevc)
3609	{
3610	int i;
3611	int cur_pic_num = MAX_REF_PIC_NUM;
3612	int dw_mode = get_double_write_mode(hevc);
3613	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL)
3614	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
3615	(0x1 << 1) | (0x1 << 2));
3616	else
3617	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);
3618
3619	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3620	if (hevc->m_PIC[i] == NULL ||
3621	hevc->m_PIC[i]->index == -1) {
3622	cur_pic_num = i;
3623	break;
3624	}
3625	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL) {
3626	if (hevc->mmu_enable && ((dw_mode & 0x10) == 0))
3627	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3628	hevc->m_PIC[i]->header_adr>>5);
3629	else
3630	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3631	hevc->m_PIC[i]->mc_y_adr >> 5);
3632	} else
3633	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3634	hevc->m_PIC[i]->mc_y_adr |
3635	(hevc->m_PIC[i]->mc_canvas_y << 8) | 0x1);
3636	if (dw_mode & 0x10) {
3637	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL) {
3638	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3639	hevc->m_PIC[i]->mc_u_v_adr >> 5);
3640	}
3641	else
3642	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3643	hevc->m_PIC[i]->mc_u_v_adr |
3644	(hevc->m_PIC[i]->mc_canvas_u_v << 8)
3645	| 0x1);
3646	}
3647	}
3648	if (cur_pic_num == 0)
3649	return;
3650	for (; i < MAX_REF_PIC_NUM; i++) {
3651	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL) {
3652	if (hevc->mmu_enable && ((dw_mode & 0x10) == 0))
3653	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3654	hevc->m_PIC[cur_pic_num-1]->header_adr>>5);
3655	else
3656	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3657	hevc->m_PIC[cur_pic_num-1]->mc_y_adr >> 5);
3658	#ifndef LOSLESS_COMPRESS_MODE
3659	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
3660	hevc->m_PIC[cur_pic_num-1]->mc_u_v_adr >> 5);
3661	#endif
3662	} else {
3663	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3664	hevc->m_PIC[cur_pic_num-1]->mc_y_adr|
3665	(hevc->m_PIC[cur_pic_num-1]->mc_canvas_y<<8)
3666	| 0x1);
3667	#ifndef LOSLESS_COMPRESS_MODE
3668	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
3669	hevc->m_PIC[cur_pic_num-1]->mc_u_v_adr|
3670	(hevc->m_PIC[cur_pic_num-1]->mc_canvas_u_v<<8)
3671	| 0x1);
3672	#endif
3673	}
3674	}
3675
3676	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
3677
3678	/* Zero out canvas registers in IPP -- avoid simulation X */
3679	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
3680	(0 << 8) | (0 << 1) | 1);
3681	for (i = 0; i < 32; i++)
3682	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
3683
3684	#ifdef LOSLESS_COMPRESS_MODE
3685	if ((dw_mode & 0x10) == 0)
3686	init_decode_head_hw(hevc);
3687	#endif
3688
3689	}
3690
3691
3692	static void dump_pic_list(struct hevc_state_s *hevc)
3693	{
3694	int i;
3695	struct PIC_s *pic;
3696
3697	hevc_print(hevc, 0,
3698	"pic_list_init_flag is %d\r\n", hevc->pic_list_init_flag);
3699	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3700	pic = hevc->m_PIC[i];
3701	if (pic == NULL || pic->index == -1)
3702	continue;
3703	hevc_print_cont(hevc, 0,
3704	"index %d buf_idx %d mv_idx %d decode_idx:%d, POC:%d, referenced:%d, ",
3705	pic->index, pic->BUF_index,
3706	#ifndef MV_USE_FIXED_BUF
3707	pic->mv_buf_index,
3708	#else
3709	-1,
3710	#endif
3711	pic->decode_idx, pic->POC, pic->referenced);
3712	hevc_print_cont(hevc, 0,
3713	"num_reorder_pic:%d, output_mark:%d, error_mark:%d w/h %d,%d",
3714	pic->num_reorder_pic, pic->output_mark, pic->error_mark,
3715	pic->width, pic->height);
3716	hevc_print_cont(hevc, 0,
3717	"output_ready:%d, mv_wr_start %x vf_ref %d\n",
3718	pic->output_ready, pic->mpred_mv_wr_start_addr,
3719	pic->vf_ref);
3720	}
3721	}
3722
3723	static void clear_referenced_flag(struct hevc_state_s *hevc)
3724	{
3725	int i;
3726	struct PIC_s *pic;
3727	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3728	pic = hevc->m_PIC[i];
3729	if (pic == NULL || pic->index == -1)
3730	continue;
3731	if (pic->referenced) {
3732	pic->referenced = 0;
3733	put_mv_buf(hevc, pic);
3734	}
3735	}
3736	}
3737
3738	static void clear_poc_flag(struct hevc_state_s *hevc)
3739	{
3740	int i;
3741	struct PIC_s *pic;
3742	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3743	pic = hevc->m_PIC[i];
3744	if (pic == NULL || pic->index == -1)
3745	continue;
3746	pic->POC = INVALID_POC;
3747	}
3748	}
3749
3750	static struct PIC_s *output_pic(struct hevc_state_s *hevc,
3751	unsigned char flush_flag)
3752	{
3753	int num_pic_not_yet_display = 0;
3754	int i;
3755	struct PIC_s *pic;
3756	struct PIC_s *pic_display = NULL;
3757	struct vdec_s *vdec = hw_to_vdec(hevc);
3758
3759	if (hevc->i_only & 0x4) {
3760	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3761	pic = hevc->m_PIC[i];
3762	if (pic == NULL ||
3763	(pic->index == -1) ||
3764	(pic->BUF_index == -1) ||
3765	(pic->POC == INVALID_POC))
3766	continue;
3767	if (pic->output_mark) {
3768	if (pic_display) {
3769	if (pic->decode_idx <
3770	pic_display->decode_idx)
3771	pic_display = pic;
3772
3773	} else
3774	pic_display = pic;
3775
3776	}
3777	}
3778	if (pic_display) {
3779	pic_display->output_mark = 0;
3780	pic_display->recon_mark = 0;
3781	pic_display->output_ready = 1;
3782	pic_display->referenced = 0;
3783	put_mv_buf(hevc, pic_display);
3784	}
3785	} else {
3786	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3787	pic = hevc->m_PIC[i];
3788	if (pic == NULL ||
3789	(pic->index == -1) ||
3790	(pic->BUF_index == -1) ||
3791	(pic->POC == INVALID_POC))
3792	continue;
3793	if (pic->output_mark)
3794	num_pic_not_yet_display++;
3795	if (pic->slice_type == 2 &&
3796	hevc->vf_pre_count == 0 &&
3797	fast_output_enable & 0x1) {
3798	/*fast output for first I picture*/
3799	pic->num_reorder_pic = 0;
3800	if (vdec->master || vdec->slave)
3801	pic_display = pic;
3802	hevc_print(hevc, 0, "VH265: output first frame\n");
3803	}
3804	}
3805
3806	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
3807	pic = hevc->m_PIC[i];
3808	if (pic == NULL ||
3809	(pic->index == -1) ||
3810	(pic->BUF_index == -1) ||
3811	(pic->POC == INVALID_POC))
3812	continue;
3813	if (pic->output_mark) {
3814	if (pic_display) {
3815	if (pic->POC < pic_display->POC)
3816	pic_display = pic;
3817	else if ((pic->POC == pic_display->POC)
3818	&& (pic->decode_idx <
3819	pic_display->
3820	decode_idx))
3821	pic_display
3822	= pic;
3823	} else
3824	pic_display = pic;
3825	}
3826	}
3827	if (pic_display) {
3828	if ((num_pic_not_yet_display >
3829	pic_display->num_reorder_pic)
3830	|| flush_flag) {
3831	pic_display->output_mark = 0;
3832	pic_display->recon_mark = 0;
3833	pic_display->output_ready = 1;
3834	} else if (num_pic_not_yet_display >=
3835	(MAX_REF_PIC_NUM - 1)) {
3836	pic_display->output_mark = 0;
3837	pic_display->recon_mark = 0;
3838	pic_display->output_ready = 1;
3839	hevc_print(hevc, 0,
3840	"Warning, num_reorder_pic %d is byeond buf num\n",
3841	pic_display->num_reorder_pic);
3842	} else
3843	pic_display = NULL;
3844	}
3845	}
3846
3847	if (pic_display && (hevc->vf_pre_count == 1) && (hevc->first_pic_flag == 1)) {
3848	pic_display = NULL;
3849	hevc->first_pic_flag = 0;
3850	}
3851	return pic_display;
3852	}
3853
3854	static int config_mc_buffer(struct hevc_state_s *hevc, struct PIC_s *cur_pic)
3855	{
3856	int i;
3857	struct PIC_s *pic;
3858
3859	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3860	hevc_print(hevc, 0,
3861	"config_mc_buffer entered .....\n");
3862	if (cur_pic->slice_type != 2) { /* P and B pic */
3863	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
3864	(0 << 8) | (0 << 1) | 1);
3865	for (i = 0; i < cur_pic->RefNum_L0; i++) {
3866	pic =
3867	get_ref_pic_by_POC(hevc,
3868	cur_pic->
3869	m_aiRefPOCList0[cur_pic->
3870	slice_idx][i]);
3871	if (pic) {
3872	if ((pic->width != hevc->pic_w) ||
3873	(pic->height != hevc->pic_h)) {
3874	hevc_print(hevc, 0,
3875	"%s: Wrong reference pic (poc %d) width/height %d/%d\n",
3876	__func__, pic->POC,
3877	pic->width, pic->height);
3878	cur_pic->error_mark = 1;
3879	}
3880	if (pic->error_mark && (ref_frame_mark_flag[hevc->index]))
3881	cur_pic->error_mark = 1;
3882	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
3883	(pic->mc_canvas_u_v << 16)
3884	| (pic->mc_canvas_u_v
3885	<< 8) |
3886	pic->mc_canvas_y);
3887	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3888	hevc_print_cont(hevc, 0,
3889	"refid %x mc_canvas_u_v %x",
3890	i, pic->mc_canvas_u_v);
3891	hevc_print_cont(hevc, 0,
3892	" mc_canvas_y %x\n",
3893	pic->mc_canvas_y);
3894	}
3895	} else
3896	cur_pic->error_mark = 1;
3897
3898	if (pic == NULL || pic->error_mark) {
3899	hevc_print(hevc, 0,
3900	"Error %s, %dth poc (%d) %s",
3901	__func__, i,
3902	cur_pic->m_aiRefPOCList0[cur_pic->
3903	slice_idx][i],
3904	pic ? "has error" :
3905	"not in list0");
3906	}
3907	}
3908	}
3909	if (cur_pic->slice_type == 0) { /* B pic */
3910	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
3911	hevc_print(hevc, 0,
3912	"config_mc_buffer RefNum_L1\n");
3913	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
3914	(16 << 8) | (0 << 1) | 1);
3915
3916	for (i = 0; i < cur_pic->RefNum_L1; i++) {
3917	pic =
3918	get_ref_pic_by_POC(hevc,
3919	cur_pic->
3920	m_aiRefPOCList1[cur_pic->
3921	slice_idx][i]);
3922	if (pic) {
3923	if ((pic->width != hevc->pic_w) ||
3924	(pic->height != hevc->pic_h)) {
3925	hevc_print(hevc, 0,
3926	"%s: Wrong reference pic (poc %d) width/height %d/%d\n",
3927	__func__, pic->POC,
3928	pic->width, pic->height);
3929	cur_pic->error_mark = 1;
3930	}
3931
3932	if (pic->error_mark && (ref_frame_mark_flag[hevc->index]))
3933	cur_pic->error_mark = 1;
3934	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
3935	(pic->mc_canvas_u_v << 16)
3936	| (pic->mc_canvas_u_v
3937	<< 8) |
3938	pic->mc_canvas_y);
3939	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
3940	hevc_print_cont(hevc, 0,
3941	"refid %x mc_canvas_u_v %x",
3942	i, pic->mc_canvas_u_v);
3943	hevc_print_cont(hevc, 0,
3944	" mc_canvas_y %x\n",
3945	pic->mc_canvas_y);
3946	}
3947	} else
3948	cur_pic->error_mark = 1;
3949
3950	if (pic == NULL || pic->error_mark) {
3951	hevc_print(hevc, 0,
3952	"Error %s, %dth poc (%d) %s",
3953	__func__, i,
3954	cur_pic->m_aiRefPOCList1[cur_pic->
3955	slice_idx][i],
3956	pic ? "has error" :
3957	"not in list1");
3958	}
3959	}
3960	}
3961	return 0;
3962	}
3963
3964	static void apply_ref_pic_set(struct hevc_state_s *hevc, int cur_poc,
3965	union param_u *params)
3966	{
3967	int ii, i;
3968	int poc_tmp;
3969	struct PIC_s *pic;
3970	unsigned char is_referenced;
3971	/* hevc_print(hevc, 0,
3972	"%s cur_poc %d\n", __func__, cur_poc); */
3973	if (pic_list_debug & 0x2) {
3974	pr_err("cur poc %d\n", cur_poc);
3975	}
3976	for (ii = 0; ii < MAX_REF_PIC_NUM; ii++) {
3977	pic = hevc->m_PIC[ii];
3978	if (pic == NULL ||
3979	pic->index == -1 ||
3980	pic->BUF_index == -1
3981	)
3982	continue;
3983
3984	if ((pic->referenced == 0 || pic->POC == cur_poc))
3985	continue;
3986	is_referenced = 0;
3987	for (i = 0; i < 16; i++) {
3988	int delt;
3989
3990	if (params->p.CUR_RPS[i] & 0x8000)
3991	break;
3992	delt =
3993	params->p.CUR_RPS[i] &
3994	((1 << (RPS_USED_BIT - 1)) - 1);
3995	if (params->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
3996	poc_tmp =
3997	cur_poc - ((1 << (RPS_USED_BIT - 1)) -
3998	delt);
3999	} else
4000	poc_tmp = cur_poc + delt;
4001	if (poc_tmp == pic->POC) {
4002	is_referenced = 1;
4003	/* hevc_print(hevc, 0, "i is %d\n", i); */
4004	break;
4005	}
4006	}
4007	if (is_referenced == 0) {
4008	pic->referenced = 0;
4009	put_mv_buf(hevc, pic);
4010	/* hevc_print(hevc, 0,
4011	"set poc %d reference to 0\n", pic->POC); */
4012	if (pic_list_debug & 0x2) {
4013	pr_err("set poc %d reference to 0\n", pic->POC);
4014	}
4015	}
4016	}
4017
4018	}
4019
4020	static void set_ref_pic_list(struct hevc_state_s *hevc, union param_u *params)
4021	{
4022	struct PIC_s *pic = hevc->cur_pic;
4023	int i, rIdx;
4024	int num_neg = 0;
4025	int num_pos = 0;
4026	int total_num;
4027	int num_ref_idx_l0_active =
4028	(params->p.num_ref_idx_l0_active >
4029	MAX_REF_ACTIVE) ? MAX_REF_ACTIVE :
4030	params->p.num_ref_idx_l0_active;
4031	int num_ref_idx_l1_active =
4032	(params->p.num_ref_idx_l1_active >
4033	MAX_REF_ACTIVE) ? MAX_REF_ACTIVE :
4034	params->p.num_ref_idx_l1_active;
4035
4036	int RefPicSetStCurr0[16];
4037	int RefPicSetStCurr1[16];
4038
4039	for (i = 0; i < 16; i++) {
4040	RefPicSetStCurr0[i] = 0;
4041	RefPicSetStCurr1[i] = 0;
4042	pic->m_aiRefPOCList0[pic->slice_idx][i] = 0;
4043	pic->m_aiRefPOCList1[pic->slice_idx][i] = 0;
4044	}
4045	for (i = 0; i < 16; i++) {
4046	if (params->p.CUR_RPS[i] & 0x8000)
4047	break;
4048	if ((params->p.CUR_RPS[i] >> RPS_USED_BIT) & 1) {
4049	int delt =
4050	params->p.CUR_RPS[i] &
4051	((1 << (RPS_USED_BIT - 1)) - 1);
4052
4053	if ((params->p.CUR_RPS[i] >> (RPS_USED_BIT - 1)) & 1) {
4054	RefPicSetStCurr0[num_neg] =
4055	pic->POC - ((1 << (RPS_USED_BIT - 1)) -
4056	delt);
4057	/* hevc_print(hevc, 0,
4058	* "RefPicSetStCurr0 %x %x %x\n",
4059	* RefPicSetStCurr0[num_neg], pic->POC,
4060	* (0x800-(params[i]&0x7ff)));
4061	*/
4062	num_neg++;
4063	} else {
4064	RefPicSetStCurr1[num_pos] = pic->POC + delt;
4065	/* hevc_print(hevc, 0,
4066	* "RefPicSetStCurr1 %d\n",
4067	* RefPicSetStCurr1[num_pos]);
4068	*/
4069	num_pos++;
4070	}
4071	}
4072	}
4073	total_num = num_neg + num_pos;
4074	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4075	hevc_print(hevc, 0,
4076	"%s: curpoc %d slice_type %d, total %d ",
4077	__func__, pic->POC, params->p.slice_type, total_num);
4078	hevc_print_cont(hevc, 0,
4079	"num_neg %d num_list0 %d num_list1 %d\n",
4080	num_neg, num_ref_idx_l0_active, num_ref_idx_l1_active);
4081	}
4082
4083	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4084	hevc_print(hevc, 0,
4085	"HEVC Stream buf start ");
4086	hevc_print_cont(hevc, 0,
4087	"%x end %x wr %x rd %x lev %x ctl %x intctl %x\n",
4088	READ_VREG(HEVC_STREAM_START_ADDR),
4089	READ_VREG(HEVC_STREAM_END_ADDR),
4090	READ_VREG(HEVC_STREAM_WR_PTR),
4091	READ_VREG(HEVC_STREAM_RD_PTR),
4092	READ_VREG(HEVC_STREAM_LEVEL),
4093	READ_VREG(HEVC_STREAM_FIFO_CTL),
4094	READ_VREG(HEVC_PARSER_INT_CONTROL));
4095	}
4096
4097	if (total_num > 0) {
4098	if (params->p.modification_flag & 0x1) {
4099	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4100	hevc_print(hevc, 0, "ref0 POC (modification):");
4101	for (rIdx = 0; rIdx < num_ref_idx_l0_active; rIdx++) {
4102	int cIdx = params->p.modification_list[rIdx];
4103
4104	pic->m_aiRefPOCList0[pic->slice_idx][rIdx] =
4105	cIdx >=
4106	num_neg ? RefPicSetStCurr1[cIdx -
4107	num_neg] :
4108	RefPicSetStCurr0[cIdx];
4109	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4110	hevc_print_cont(hevc, 0, "%d ",
4111	pic->m_aiRefPOCList0[pic->
4112	slice_idx]
4113	[rIdx]);
4114	}
4115	}
4116	} else {
4117	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4118	hevc_print(hevc, 0, "ref0 POC:");
4119	for (rIdx = 0; rIdx < num_ref_idx_l0_active; rIdx++) {
4120	int cIdx = rIdx % total_num;
4121
4122	pic->m_aiRefPOCList0[pic->slice_idx][rIdx] =
4123	cIdx >=
4124	num_neg ? RefPicSetStCurr1[cIdx -
4125	num_neg] :
4126	RefPicSetStCurr0[cIdx];
4127	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4128	hevc_print_cont(hevc, 0, "%d ",
4129	pic->m_aiRefPOCList0[pic->
4130	slice_idx]
4131	[rIdx]);
4132	}
4133	}
4134	}
4135	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4136	hevc_print_cont(hevc, 0, "\n");
4137	if (params->p.slice_type == B_SLICE) {
4138	if (params->p.modification_flag & 0x2) {
4139	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4140	hevc_print(hevc, 0,
4141	"ref1 POC (modification):");
4142	for (rIdx = 0; rIdx < num_ref_idx_l1_active;
4143	rIdx++) {
4144	int cIdx;
4145
4146	if (params->p.modification_flag & 0x1) {
4147	cIdx =
4148	params->p.
4149	modification_list
4150	[num_ref_idx_l0_active +
4151	rIdx];
4152	} else {
4153	cIdx =
4154	params->p.
4155	modification_list[rIdx];
4156	}
4157	pic->m_aiRefPOCList1[pic->
4158	slice_idx][rIdx] =
4159	cIdx >=
4160	num_pos ?
4161	RefPicSetStCurr0[cIdx - num_pos]
4162	: RefPicSetStCurr1[cIdx];
4163	if (get_dbg_flag(hevc) &
4164	H265_DEBUG_BUFMGR) {
4165	hevc_print_cont(hevc, 0, "%d ",
4166	pic->
4167	m_aiRefPOCList1[pic->
4168	slice_idx]
4169	[rIdx]);
4170	}
4171	}
4172	} else {
4173	if (get_dbg_flag(hevc) &
4174	H265_DEBUG_BUFMGR)
4175	hevc_print(hevc, 0, "ref1 POC:");
4176	for (rIdx = 0; rIdx < num_ref_idx_l1_active;
4177	rIdx++) {
4178	int cIdx = rIdx % total_num;
4179
4180	pic->m_aiRefPOCList1[pic->
4181	slice_idx][rIdx] =
4182	cIdx >=
4183	num_pos ?
4184	RefPicSetStCurr0[cIdx -
4185	num_pos]
4186	: RefPicSetStCurr1[cIdx];
4187	if (get_dbg_flag(hevc) &
4188	H265_DEBUG_BUFMGR) {
4189	hevc_print_cont(hevc, 0, "%d ",
4190	pic->
4191	m_aiRefPOCList1[pic->
4192	slice_idx]
4193	[rIdx]);
4194	}
4195	}
4196	}
4197	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4198	hevc_print_cont(hevc, 0, "\n");
4199	}
4200	}
4201	/*set m_PIC */
4202	pic->slice_type = (params->p.slice_type == I_SLICE) ? 2 :
4203	(params->p.slice_type == P_SLICE) ? 1 :
4204	(params->p.slice_type == B_SLICE) ? 0 : 3;
4205	pic->RefNum_L0 = num_ref_idx_l0_active;
4206	pic->RefNum_L1 = num_ref_idx_l1_active;
4207	}
4208
4209	static void update_tile_info(struct hevc_state_s *hevc, int pic_width_cu,
4210	int pic_height_cu, int sao_mem_unit,
4211	union param_u *params)
4212	{
4213	int i, j;
4214	int start_cu_x, start_cu_y;
4215	int sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
4216	int sao_abv_size = sao_mem_unit * pic_width_cu;
4217	#ifdef DETREFILL_ENABLE
4218	if (hevc->is_swap && get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
4219	int tmpRefillLcuSize = 1 <<
4220	(params->p.log2_min_coding_block_size_minus3 +
4221	3 + params->p.log2_diff_max_min_coding_block_size);
4222	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
4223	"%x, %x, %x, %x\n",
4224	params->p.slice_segment_address,
4225	params->p.bit_depth,
4226	params->p.tiles_enabled_flag,
4227	tmpRefillLcuSize);
4228	if (params->p.slice_segment_address == 0 &&
4229	params->p.bit_depth != 0 &&
4230	(params->p.tiles_enabled_flag & 1) &&
4231	tmpRefillLcuSize == 64)
4232	hevc->delrefill_check = 1;
4233	else
4234	hevc->delrefill_check = 0;
4235	}
4236	#endif
4237
4238	hevc->tile_enabled = params->p.tiles_enabled_flag & 1;
4239	if (params->p.tiles_enabled_flag & 1) {
4240	hevc->num_tile_col = params->p.num_tile_columns_minus1 + 1;
4241	hevc->num_tile_row = params->p.num_tile_rows_minus1 + 1;
4242
4243	if (hevc->num_tile_row > MAX_TILE_ROW_NUM
4244	|| hevc->num_tile_row <= 0) {
4245	hevc->num_tile_row = 1;
4246	hevc_print(hevc, 0,
4247	"%s: num_tile_rows_minus1 (%d) error!!\n",
4248	__func__, params->p.num_tile_rows_minus1);
4249	}
4250	if (hevc->num_tile_col > MAX_TILE_COL_NUM
4251	|| hevc->num_tile_col <= 0) {
4252	hevc->num_tile_col = 1;
4253	hevc_print(hevc, 0,
4254	"%s: num_tile_columns_minus1 (%d) error!!\n",
4255	__func__, params->p.num_tile_columns_minus1);
4256	}
4257	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4258	hevc_print(hevc, 0,
4259	"%s pic_w_cu %d pic_h_cu %d tile_enabled ",
4260	__func__, pic_width_cu, pic_height_cu);
4261	hevc_print_cont(hevc, 0,
4262	"num_tile_col %d num_tile_row %d:\n",
4263	hevc->num_tile_col, hevc->num_tile_row);
4264	}
4265
4266	if (params->p.tiles_enabled_flag & 2) { /* uniform flag */
4267	int w = pic_width_cu / hevc->num_tile_col;
4268	int h = pic_height_cu / hevc->num_tile_row;
4269
4270	start_cu_y = 0;
4271	for (i = 0; i < hevc->num_tile_row; i++) {
4272	start_cu_x = 0;
4273	for (j = 0; j < hevc->num_tile_col; j++) {
4274	if (j == (hevc->num_tile_col - 1)) {
4275	hevc->m_tile[i][j].width =
4276	pic_width_cu -
4277	start_cu_x;
4278	} else
4279	hevc->m_tile[i][j].width = w;
4280	if (i == (hevc->num_tile_row - 1)) {
4281	hevc->m_tile[i][j].height =
4282	pic_height_cu -
4283	start_cu_y;
4284	} else
4285	hevc->m_tile[i][j].height = h;
4286	hevc->m_tile[i][j].start_cu_x
4287	= start_cu_x;
4288	hevc->m_tile[i][j].start_cu_y
4289	= start_cu_y;
4290	hevc->m_tile[i][j].sao_vb_start_addr =
4291	hevc->work_space_buf->sao_vb.
4292	buf_start + j * sao_vb_size;
4293	hevc->m_tile[i][j].sao_abv_start_addr =
4294	hevc->work_space_buf->sao_abv.
4295	buf_start + i * sao_abv_size;
4296	if (get_dbg_flag(hevc) &
4297	H265_DEBUG_BUFMGR) {
4298	hevc_print_cont(hevc, 0,
4299	"{y=%d, x=%d w %d h %d ",
4300	i, j, hevc->m_tile[i][j].width,
4301	hevc->m_tile[i][j].height);
4302	hevc_print_cont(hevc, 0,
4303	"start_x %d start_y %d ",
4304	hevc->m_tile[i][j].start_cu_x,
4305	hevc->m_tile[i][j].start_cu_y);
4306	hevc_print_cont(hevc, 0,
4307	"sao_vb_start 0x%x ",
4308	hevc->m_tile[i][j].
4309	sao_vb_start_addr);
4310	hevc_print_cont(hevc, 0,
4311	"sao_abv_start 0x%x}\n",
4312	hevc->m_tile[i][j].
4313	sao_abv_start_addr);
4314	}
4315	start_cu_x += hevc->m_tile[i][j].width;
4316
4317	}
4318	start_cu_y += hevc->m_tile[i][0].height;
4319	}
4320	} else {
4321	start_cu_y = 0;
4322	for (i = 0; i < hevc->num_tile_row; i++) {
4323	start_cu_x = 0;
4324	for (j = 0; j < hevc->num_tile_col; j++) {
4325	if (j == (hevc->num_tile_col - 1)) {
4326	hevc->m_tile[i][j].width =
4327	pic_width_cu -
4328	start_cu_x;
4329	} else {
4330	hevc->m_tile[i][j].width =
4331	params->p.tile_width[j];
4332	}
4333	if (i == (hevc->num_tile_row - 1)) {
4334	hevc->m_tile[i][j].height =
4335	pic_height_cu -
4336	start_cu_y;
4337	} else {
4338	hevc->m_tile[i][j].height =
4339	params->
4340	p.tile_height[i];
4341	}
4342	hevc->m_tile[i][j].start_cu_x
4343	= start_cu_x;
4344	hevc->m_tile[i][j].start_cu_y
4345	= start_cu_y;
4346	hevc->m_tile[i][j].sao_vb_start_addr =
4347	hevc->work_space_buf->sao_vb.
4348	buf_start + j * sao_vb_size;
4349	hevc->m_tile[i][j].sao_abv_start_addr =
4350	hevc->work_space_buf->sao_abv.
4351	buf_start + i * sao_abv_size;
4352	if (get_dbg_flag(hevc) &
4353	H265_DEBUG_BUFMGR) {
4354	hevc_print_cont(hevc, 0,
4355	"{y=%d, x=%d w %d h %d ",
4356	i, j, hevc->m_tile[i][j].width,
4357	hevc->m_tile[i][j].height);
4358	hevc_print_cont(hevc, 0,
4359	"start_x %d start_y %d ",
4360	hevc->m_tile[i][j].start_cu_x,
4361	hevc->m_tile[i][j].start_cu_y);
4362	hevc_print_cont(hevc, 0,
4363	"sao_vb_start 0x%x ",
4364	hevc->m_tile[i][j].
4365	sao_vb_start_addr);
4366	hevc_print_cont(hevc, 0,
4367	"sao_abv_start 0x%x}\n",
4368	hevc->m_tile[i][j].
4369	sao_abv_start_addr);
4370
4371	}
4372	start_cu_x += hevc->m_tile[i][j].width;
4373	}
4374	start_cu_y += hevc->m_tile[i][0].height;
4375	}
4376	}
4377	} else {
4378	hevc->num_tile_col = 1;
4379	hevc->num_tile_row = 1;
4380	hevc->m_tile[0][0].width = pic_width_cu;
4381	hevc->m_tile[0][0].height = pic_height_cu;
4382	hevc->m_tile[0][0].start_cu_x = 0;
4383	hevc->m_tile[0][0].start_cu_y = 0;
4384	hevc->m_tile[0][0].sao_vb_start_addr =
4385	hevc->work_space_buf->sao_vb.buf_start;
4386	hevc->m_tile[0][0].sao_abv_start_addr =
4387	hevc->work_space_buf->sao_abv.buf_start;
4388	}
4389	}
4390
4391	static int get_tile_index(struct hevc_state_s *hevc, int cu_adr,
4392	int pic_width_lcu)
4393	{
4394	int cu_x;
4395	int cu_y;
4396	int tile_x = 0;
4397	int tile_y = 0;
4398	int i;
4399
4400	if (pic_width_lcu == 0) {
4401	if (get_dbg_flag(hevc)) {
4402	hevc_print(hevc, 0,
4403	"%s Error, pic_width_lcu is 0, pic_w %d, pic_h %d\n",
4404	__func__, hevc->pic_w, hevc->pic_h);
4405	}
4406	return -1;
4407	}
4408	cu_x = cu_adr % pic_width_lcu;
4409	cu_y = cu_adr / pic_width_lcu;
4410	if (hevc->tile_enabled) {
4411	for (i = 0; i < hevc->num_tile_col; i++) {
4412	if (cu_x >= hevc->m_tile[0][i].start_cu_x)
4413	tile_x = i;
4414	else
4415	break;
4416	}
4417	for (i = 0; i < hevc->num_tile_row; i++) {
4418	if (cu_y >= hevc->m_tile[i][0].start_cu_y)
4419	tile_y = i;
4420	else
4421	break;
4422	}
4423	}
4424	return (tile_x) | (tile_y << 8);
4425	}
4426
4427	static void print_scratch_error(int error_num)
4428	{
4429	#if 0
4430	if (get_dbg_flag(hevc)) {
4431	hevc_print(hevc, 0,
4432	" ERROR : HEVC_ASSIST_SCRATCH_TEST Error : %d\n",
4433	error_num);
4434	}
4435	#endif
4436	}
4437
4438	static void hevc_config_work_space_hw(struct hevc_state_s *hevc)
4439	{
4440	struct BuffInfo_s *buf_spec = hevc->work_space_buf;
4441
4442	if (get_dbg_flag(hevc))
4443	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
4444	"%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
4445	__func__,
4446	buf_spec->ipp.buf_start,
4447	buf_spec->start_adr,
4448	buf_spec->short_term_rps.buf_start,
4449	buf_spec->vps.buf_start,
4450	buf_spec->sps.buf_start,
4451	buf_spec->pps.buf_start,
4452	buf_spec->sao_up.buf_start,
4453	buf_spec->swap_buf.buf_start,
4454	buf_spec->swap_buf2.buf_start,
4455	buf_spec->scalelut.buf_start,
4456	buf_spec->dblk_para.buf_start,
4457	buf_spec->dblk_data.buf_start,
4458	buf_spec->dblk_data2.buf_start);
4459	WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start);
4460	if ((get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) == 0)
4461	WRITE_VREG(HEVC_RPM_BUFFER, (u32)hevc->rpm_phy_addr);
4462	WRITE_VREG(HEVC_SHORT_TERM_RPS, buf_spec->short_term_rps.buf_start);
4463	WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);
4464	WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);
4465	WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
4466	WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
4467	if (hevc->mmu_enable) {
4468	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
4469	WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, hevc->frame_mmu_map_phy_addr);
4470	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
4471	"write HEVC_ASSIST_MMU_MAP_ADDR\n");
4472	} else
4473	WRITE_VREG(H265_MMU_MAP_BUFFER, hevc->frame_mmu_map_phy_addr);
4474	} /*else
4475	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
4476	buf_spec->swap_buf.buf_start);
4477	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start);*/
4478	WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
4479	/* cfg_p_addr */
4480	WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
4481	/* cfg_d_addr */
4482	WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
4483
4484	WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start);
4485
4486	WRITE_VREG(LMEM_DUMP_ADR, (u32)hevc->lmem_phy_addr);
4487	}
4488
4489	static void parser_cmd_write(void)
4490	{
4491	u32 i;
4492	const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
4493	0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
4494	0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
4495	0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
4496	0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
4497	0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
4498	0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
4499	0x7C00
4500	};
4501	for (i = 0; i < PARSER_CMD_NUMBER; i++)
4502	WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
4503	}
4504
4505	static void hevc_init_decoder_hw(struct hevc_state_s *hevc,
4506	int decode_pic_begin, int decode_pic_num)
4507	{
4508	unsigned int data32;
4509	int i;
4510	#if 0
4511	if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
4512	/* Set MCR fetch priorities*/
4513	data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
4514	(24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
4515	WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
4516	}
4517	#endif
4518	#if 1
4519	/* m8baby test1902 */
4520	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
4521	hevc_print(hevc, 0,
4522	"%s\n", __func__);
4523	data32 = READ_VREG(HEVC_PARSER_VERSION);
4524	if (data32 != 0x00010001) {
4525	print_scratch_error(25);
4526	return;
4527	}
4528	WRITE_VREG(HEVC_PARSER_VERSION, 0x5a5a55aa);
4529	data32 = READ_VREG(HEVC_PARSER_VERSION);
4530	if (data32 != 0x5a5a55aa) {
4531	print_scratch_error(26);
4532	return;
4533	}
4534	#if 0
4535	/* test Parser Reset */
4536	/* reset iqit to start mem init again */
4537	WRITE_VREG(DOS_SW_RESET3, (1 << 14) |
4538	(1 << 3) /* reset_whole parser */
4539	);
4540	WRITE_VREG(DOS_SW_RESET3, 0); /* clear reset_whole parser */
4541	data32 = READ_VREG(HEVC_PARSER_VERSION);
4542	if (data32 != 0x00010001)
4543	hevc_print(hevc, 0,
4544	"Test Parser Fatal Error\n");
4545	#endif
4546	/* reset iqit to start mem init again */
4547	WRITE_VREG(DOS_SW_RESET3, (1 << 14)
4548	);
4549	CLEAR_VREG_MASK(HEVC_CABAC_CONTROL, 1);
4550	CLEAR_VREG_MASK(HEVC_PARSER_CORE_CONTROL, 1);
4551
4552	#endif
4553	if (!hevc->m_ins_flag) {
4554	data32 = READ_VREG(HEVC_STREAM_CONTROL);
4555	data32 = data32 | (1 << 0); /* stream_fetch_enable */
4556	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
4557	data32 |= (0xf << 25); /*arwlen_axi_max*/
4558	WRITE_VREG(HEVC_STREAM_CONTROL, data32);
4559	}
4560	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4561	if (data32 != 0x00000100) {
4562	print_scratch_error(29);
4563	return;
4564	}
4565	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4566	if (data32 != 0x00000300) {
4567	print_scratch_error(30);
4568	return;
4569	}
4570	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
4571	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
4572	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4573	if (data32 != 0x12345678) {
4574	print_scratch_error(31);
4575	return;
4576	}
4577	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4578	if (data32 != 0x9abcdef0) {
4579	print_scratch_error(32);
4580	return;
4581	}
4582	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
4583	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
4584
4585	data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4586	data32 &= 0x03ffffff;
4587	data32 = data32 | (3 << 29) | (2 << 26) | (1 << 24)
4588	| /* stream_buffer_empty_int_amrisc_enable */
4589	(1 << 22) | /* stream_fifo_empty_int_amrisc_enable*/
4590	(1 << 7) | /* dec_done_int_cpu_enable */
4591	(1 << 4) | /* startcode_found_int_cpu_enable */
4592	(0 << 3) | /* startcode_found_int_amrisc_enable */
4593	(1 << 0) /* parser_int_enable */
4594	;
4595	WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
4596
4597	data32 = READ_VREG(HEVC_SHIFT_STATUS);
4598	data32 = data32 | (1 << 1) | /* emulation_check_on */
4599	(1 << 0) /* startcode_check_on */
4600	;
4601	WRITE_VREG(HEVC_SHIFT_STATUS, data32);
4602
4603	WRITE_VREG(HEVC_SHIFT_CONTROL, (3 << 6) |/* sft_valid_wr_position */
4604	(2 << 4) | /* emulate_code_length_sub_1 */
4605	(2 << 1) | /* start_code_length_sub_1 */
4606	(1 << 0) /* stream_shift_enable */
4607	);
4608
4609	WRITE_VREG(HEVC_CABAC_CONTROL, (1 << 0) /* cabac_enable */
4610	);
4611	/* hevc_parser_core_clk_en */
4612	WRITE_VREG(HEVC_PARSER_CORE_CONTROL, (1 << 0)
4613	);
4614
4615	WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
4616
4617	/* Initial IQIT_SCALELUT memory -- just to avoid X in simulation */
4618	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); /* cfg_p_addr */
4619	for (i = 0; i < 1024; i++)
4620	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
4621
4622	#ifdef ENABLE_SWAP_TEST
4623	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
4624	#endif
4625
4626	/*WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);*/
4627	/*WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0xffffffff);*/
4628	WRITE_VREG(HEVC_DECODE_SIZE, 0);
4629	/*WRITE_VREG(HEVC_DECODE_COUNT, 0);*/
4630	/* Send parser_cmd */
4631	WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
4632
4633	parser_cmd_write();
4634
4635	WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
4636	WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
4637	WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
4638
4639	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4640	/* (1 << 8) | // sao_sw_pred_enable */
4641	(1 << 5) | /* parser_sao_if_en */
4642	(1 << 2) | /* parser_mpred_if_en */
4643	(1 << 0) /* parser_scaler_if_en */
4644	);
4645
4646	/* Changed to Start MPRED in microcode */
4647	/*
4648	* hevc_print(hevc, 0, "[test.c] Start MPRED\n");
4649	* WRITE_VREG(HEVC_MPRED_INT_STATUS,
4650	* (1<<31)
4651	* );
4652	*/
4653
4654	WRITE_VREG(HEVCD_IPP_TOP_CNTL, (0 << 1) | /* enable ipp */
4655	(1 << 0) /* software reset ipp and mpp */
4656	);
4657	WRITE_VREG(HEVCD_IPP_TOP_CNTL, (1 << 1) | /* enable ipp */
4658	(0 << 0) /* software reset ipp and mpp */
4659	);
4660
4661	if (get_double_write_mode(hevc) & 0x10)
4662	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
4663	0x1 << 31 /*/Enable NV21 reference read mode for MC*/
4664	);
4665
4666	}
4667
4668	static void decoder_hw_reset(void)
4669	{
4670	int i;
4671	unsigned int data32;
4672	/* reset iqit to start mem init again */
4673	WRITE_VREG(DOS_SW_RESET3, (1 << 14)
4674	);
4675	CLEAR_VREG_MASK(HEVC_CABAC_CONTROL, 1);
4676	CLEAR_VREG_MASK(HEVC_PARSER_CORE_CONTROL, 1);
4677
4678	data32 = READ_VREG(HEVC_STREAM_CONTROL);
4679	data32 = data32 | (1 << 0) /* stream_fetch_enable */
4680	;
4681	WRITE_VREG(HEVC_STREAM_CONTROL, data32);
4682
4683	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4684	if (data32 != 0x00000100) {
4685	print_scratch_error(29);
4686	return;
4687	}
4688	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4689	if (data32 != 0x00000300) {
4690	print_scratch_error(30);
4691	return;
4692	}
4693	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
4694	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
4695	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
4696	if (data32 != 0x12345678) {
4697	print_scratch_error(31);
4698	return;
4699	}
4700	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
4701	if (data32 != 0x9abcdef0) {
4702	print_scratch_error(32);
4703	return;
4704	}
4705	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100);
4706	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
4707
4708	data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4709	data32 &= 0x03ffffff;
4710	data32 = data32 | (3 << 29) | (2 << 26) | (1 << 24)
4711	| /* stream_buffer_empty_int_amrisc_enable */
4712	(1 << 22) | /*stream_fifo_empty_int_amrisc_enable */
4713	(1 << 7) | /* dec_done_int_cpu_enable */
4714	(1 << 4) | /* startcode_found_int_cpu_enable */
4715	(0 << 3) | /* startcode_found_int_amrisc_enable */
4716	(1 << 0) /* parser_int_enable */
4717	;
4718	WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
4719
4720	data32 = READ_VREG(HEVC_SHIFT_STATUS);
4721	data32 = data32 | (1 << 1) | /* emulation_check_on */
4722	(1 << 0) /* startcode_check_on */
4723	;
4724	WRITE_VREG(HEVC_SHIFT_STATUS, data32);
4725
4726	WRITE_VREG(HEVC_SHIFT_CONTROL, (3 << 6) |/* sft_valid_wr_position */
4727	(2 << 4) | /* emulate_code_length_sub_1 */
4728	(2 << 1) | /* start_code_length_sub_1 */
4729	(1 << 0) /* stream_shift_enable */
4730	);
4731
4732	WRITE_VREG(HEVC_CABAC_CONTROL, (1 << 0) /* cabac_enable */
4733	);
4734	/* hevc_parser_core_clk_en */
4735	WRITE_VREG(HEVC_PARSER_CORE_CONTROL, (1 << 0)
4736	);
4737
4738	/* Initial IQIT_SCALELUT memory -- just to avoid X in simulation */
4739	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); /* cfg_p_addr */
4740	for (i = 0; i < 1024; i++)
4741	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
4742
4743	/* Send parser_cmd */
4744	WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
4745
4746	parser_cmd_write();
4747
4748	WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
4749	WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
4750	WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
4751
4752	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4753	/* (1 << 8) | // sao_sw_pred_enable */
4754	(1 << 5) | /* parser_sao_if_en */
4755	(1 << 2) | /* parser_mpred_if_en */
4756	(1 << 0) /* parser_scaler_if_en */
4757	);
4758
4759	WRITE_VREG(HEVCD_IPP_TOP_CNTL, (0 << 1) | /* enable ipp */
4760	(1 << 0) /* software reset ipp and mpp */
4761	);
4762	WRITE_VREG(HEVCD_IPP_TOP_CNTL, (1 << 1) | /* enable ipp */
4763	(0 << 0) /* software reset ipp and mpp */
4764	);
4765	}
4766
4767	#ifdef CONFIG_HEVC_CLK_FORCED_ON
4768	static void config_hevc_clk_forced_on(void)
4769	{
4770	unsigned int rdata32;
4771	/* IQIT */
4772	rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
4773	WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
4774
4775	/* DBLK */
4776	rdata32 = READ_VREG(HEVC_DBLK_CFG0);
4777	WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
4778
4779	/* SAO */
4780	rdata32 = READ_VREG(HEVC_SAO_CTRL1);
4781	WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
4782
4783	/* MPRED */
4784	rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
4785	WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
4786
4787	/* PARSER */
4788	rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
4789	WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
4790	rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
4791	WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
4792	rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
4793	WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
4794	rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
4795	WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
4796	rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
4797	WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
4798	rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
4799	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
4800	rdata32 | (0x3 << 5) | (0x3 << 2) | (0x3 << 0));
4801
4802	/* IPP */
4803	rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
4804	WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
4805
4806	/* MCRCC */
4807	rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
4808	WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
4809	}
4810	#endif
4811
4812	#ifdef MCRCC_ENABLE
4813	static void config_mcrcc_axi_hw(struct hevc_state_s *hevc, int slice_type)
4814	{
4815	unsigned int rdata32;
4816	unsigned int rdata32_2;
4817	int l0_cnt = 0;
4818	int l1_cnt = 0x7fff;
4819
4820	if (get_double_write_mode(hevc) & 0x10) {
4821	l0_cnt = hevc->cur_pic->RefNum_L0;
4822	l1_cnt = hevc->cur_pic->RefNum_L1;
4823	}
4824
4825	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
4826
4827	if (slice_type == 2) { /* I-PIC */
4828	/* remove reset -- disables clock */
4829	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
4830	return;
4831	}
4832
4833	if (slice_type == 0) { /* B-PIC */
4834	/* Programme canvas0 */
4835	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4836	(0 << 8) | (0 << 1) | 0);
4837	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4838	rdata32 = rdata32 & 0xffff;
4839	rdata32 = rdata32 | (rdata32 << 16);
4840	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
4841
4842	/* Programme canvas1 */
4843	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4844	(16 << 8) | (1 << 1) | 0);
4845	rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4846	rdata32_2 = rdata32_2 & 0xffff;
4847	rdata32_2 = rdata32_2 | (rdata32_2 << 16);
4848	if (rdata32 == rdata32_2 && l1_cnt > 1) {
4849	rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4850	rdata32_2 = rdata32_2 & 0xffff;
4851	rdata32_2 = rdata32_2 | (rdata32_2 << 16);
4852	}
4853	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2);
4854	} else { /* P-PIC */
4855	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4856	(0 << 8) | (1 << 1) | 0);
4857	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4858	rdata32 = rdata32 & 0xffff;
4859	rdata32 = rdata32 | (rdata32 << 16);
4860	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
4861
4862	if (l0_cnt == 1) {
4863	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
4864	} else {
4865	/* Programme canvas1 */
4866	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
4867	rdata32 = rdata32 & 0xffff;
4868	rdata32 = rdata32 | (rdata32 << 16);
4869	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
4870	}
4871	}
4872	/* enable mcrcc progressive-mode */
4873	WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
4874	}
4875	#endif
4876
4877	static void config_title_hw(struct hevc_state_s *hevc, int sao_vb_size,
4878	int sao_mem_unit)
4879	{
4880	WRITE_VREG(HEVC_sao_mem_unit, sao_mem_unit);
4881	WRITE_VREG(HEVC_SAO_ABV, hevc->work_space_buf->sao_abv.buf_start);
4882	WRITE_VREG(HEVC_sao_vb_size, sao_vb_size);
4883	WRITE_VREG(HEVC_SAO_VB, hevc->work_space_buf->sao_vb.buf_start);
4884	}
4885
4886	static u32 init_aux_size;
4887	static int aux_data_is_avaible(struct hevc_state_s *hevc)
4888	{
4889	u32 reg_val;
4890
4891	reg_val = READ_VREG(HEVC_AUX_DATA_SIZE);
4892	if (reg_val != 0 && reg_val != init_aux_size)
4893	return 1;
4894	else
4895	return 0;
4896	}
4897
4898	static void config_aux_buf(struct hevc_state_s *hevc)
4899	{
4900	WRITE_VREG(HEVC_AUX_ADR, hevc->aux_phy_addr);
4901	init_aux_size = ((hevc->prefix_aux_size >> 4) << 16) |
4902	(hevc->suffix_aux_size >> 4);
4903	WRITE_VREG(HEVC_AUX_DATA_SIZE, init_aux_size);
4904	}
4905
4906	static void config_mpred_hw(struct hevc_state_s *hevc)
4907	{
4908	int i;
4909	unsigned int data32;
4910	struct PIC_s *cur_pic = hevc->cur_pic;
4911	struct PIC_s *col_pic = hevc->col_pic;
4912	int AMVP_MAX_NUM_CANDS_MEM = 3;
4913	int AMVP_MAX_NUM_CANDS = 2;
4914	int NUM_CHROMA_MODE = 5;
4915	int DM_CHROMA_IDX = 36;
4916	int above_ptr_ctrl = 0;
4917	int buffer_linear = 1;
4918	int cu_size_log2 = 3;
4919
4920	int mpred_mv_rd_start_addr;
4921	int mpred_curr_lcu_x;
4922	int mpred_curr_lcu_y;
4923	int mpred_above_buf_start;
4924	int mpred_mv_rd_ptr;
4925	int mpred_mv_rd_ptr_p1;
4926	int mpred_mv_rd_end_addr;
4927	int MV_MEM_UNIT;
4928	int mpred_mv_wr_ptr;
4929	int *ref_poc_L0, *ref_poc_L1;
4930
4931	int above_en;
4932	int mv_wr_en;
4933	int mv_rd_en;
4934	int col_isIntra;
4935
4936	if (hevc->slice_type != 2) {
4937	above_en = 1;
4938	mv_wr_en = 1;
4939	mv_rd_en = 1;
4940	col_isIntra = 0;
4941	} else {
4942	above_en = 1;
4943	mv_wr_en = 1;
4944	mv_rd_en = 0;
4945	col_isIntra = 0;
4946	}
4947
4948	mpred_mv_rd_start_addr = col_pic->mpred_mv_wr_start_addr;
4949	data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
4950	mpred_curr_lcu_x = data32 & 0xffff;
4951	mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
4952
4953	MV_MEM_UNIT =
4954	hevc->lcu_size_log2 == 6 ? 0x200 : hevc->lcu_size_log2 ==
4955	5 ? 0x80 : 0x20;
4956	mpred_mv_rd_ptr =
4957	mpred_mv_rd_start_addr + (hevc->slice_addr * MV_MEM_UNIT);
4958
4959	mpred_mv_rd_ptr_p1 = mpred_mv_rd_ptr + MV_MEM_UNIT;
4960	mpred_mv_rd_end_addr =
4961	mpred_mv_rd_start_addr +
4962	((hevc->lcu_x_num * hevc->lcu_y_num) * MV_MEM_UNIT);
4963
4964	mpred_above_buf_start = hevc->work_space_buf->mpred_above.buf_start;
4965
4966	mpred_mv_wr_ptr =
4967	cur_pic->mpred_mv_wr_start_addr +
4968	(hevc->slice_addr * MV_MEM_UNIT);
4969
4970	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
4971	hevc_print(hevc, 0,
4972	"cur pic index %d col pic index %d\n", cur_pic->index,
4973	col_pic->index);
4974	}
4975
4976	WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
4977	cur_pic->mpred_mv_wr_start_addr);
4978	WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, mpred_mv_rd_start_addr);
4979
4980	data32 = ((hevc->lcu_x_num - hevc->tile_width_lcu) * MV_MEM_UNIT);
4981	WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP, data32);
4982	WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP, data32);
4983
4984	data32 = READ_VREG(HEVC_MPRED_CTRL0);
4985	data32 = (hevc->slice_type |
4986	hevc->new_pic << 2 |
4987	hevc->new_tile << 3 |
4988	hevc->isNextSliceSegment << 4 |
4989	hevc->TMVPFlag << 5 |
4990	hevc->LDCFlag << 6 |
4991	hevc->ColFromL0Flag << 7 |
4992	above_ptr_ctrl << 8 |
4993	above_en << 9 |
4994	mv_wr_en << 10 |
4995	mv_rd_en << 11 |
4996	col_isIntra << 12 |
4997	buffer_linear << 13 |
4998	hevc->LongTerm_Curr << 14 |
4999	hevc->LongTerm_Col << 15 |
5000	hevc->lcu_size_log2 << 16 |
5001	cu_size_log2 << 20 | hevc->plevel << 24);
5002	WRITE_VREG(HEVC_MPRED_CTRL0, data32);
5003
5004	data32 = READ_VREG(HEVC_MPRED_CTRL1);
5005	data32 = (
5006	#if 0
5007	/* no set in m8baby test1902 */
5008	/* Don't override clk_forced_on , */
5009	(data32 & (0x1 << 24)) |
5010	#endif
5011	hevc->MaxNumMergeCand |
5012	AMVP_MAX_NUM_CANDS << 4 |
5013	AMVP_MAX_NUM_CANDS_MEM << 8 |
5014	NUM_CHROMA_MODE << 12 | DM_CHROMA_IDX << 16);
5015	WRITE_VREG(HEVC_MPRED_CTRL1, data32);
5016
5017	data32 = (hevc->pic_w | hevc->pic_h << 16);
5018	WRITE_VREG(HEVC_MPRED_PIC_SIZE, data32);
5019
5020	data32 = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
5021	WRITE_VREG(HEVC_MPRED_PIC_SIZE_LCU, data32);
5022
5023	data32 = (hevc->tile_start_lcu_x | hevc->tile_start_lcu_y << 16);
5024	WRITE_VREG(HEVC_MPRED_TILE_START, data32);
5025
5026	data32 = (hevc->tile_width_lcu | hevc->tile_height_lcu << 16);
5027	WRITE_VREG(HEVC_MPRED_TILE_SIZE_LCU, data32);
5028
5029	data32 = (hevc->RefNum_L0 | hevc->RefNum_L1 << 8 | 0
5030	/* col_RefNum_L0<<16| */
5031	/* col_RefNum_L1<<24 */
5032	);
5033	WRITE_VREG(HEVC_MPRED_REF_NUM, data32);
5034
5035	data32 = (hevc->LongTerm_Ref);
5036	WRITE_VREG(HEVC_MPRED_LT_REF, data32);
5037
5038	data32 = 0;
5039	for (i = 0; i < hevc->RefNum_L0; i++)
5040	data32 = data32 | (1 << i);
5041	WRITE_VREG(HEVC_MPRED_REF_EN_L0, data32);
5042
5043	data32 = 0;
5044	for (i = 0; i < hevc->RefNum_L1; i++)
5045	data32 = data32 | (1 << i);
5046	WRITE_VREG(HEVC_MPRED_REF_EN_L1, data32);
5047
5048	WRITE_VREG(HEVC_MPRED_CUR_POC, hevc->curr_POC);
5049	WRITE_VREG(HEVC_MPRED_COL_POC, hevc->Col_POC);
5050
5051	/* below MPRED Ref_POC_xx_Lx registers must follow Ref_POC_xx_L0 ->
5052	* Ref_POC_xx_L1 in pair write order!!!
5053	*/
5054	ref_poc_L0 = &(cur_pic->m_aiRefPOCList0[cur_pic->slice_idx][0]);
5055	ref_poc_L1 = &(cur_pic->m_aiRefPOCList1[cur_pic->slice_idx][0]);
5056
5057	WRITE_VREG(HEVC_MPRED_L0_REF00_POC, ref_poc_L0[0]);
5058	WRITE_VREG(HEVC_MPRED_L1_REF00_POC, ref_poc_L1[0]);
5059
5060	WRITE_VREG(HEVC_MPRED_L0_REF01_POC, ref_poc_L0[1]);
5061	WRITE_VREG(HEVC_MPRED_L1_REF01_POC, ref_poc_L1[1]);
5062
5063	WRITE_VREG(HEVC_MPRED_L0_REF02_POC, ref_poc_L0[2]);
5064	WRITE_VREG(HEVC_MPRED_L1_REF02_POC, ref_poc_L1[2]);
5065
5066	WRITE_VREG(HEVC_MPRED_L0_REF03_POC, ref_poc_L0[3]);
5067	WRITE_VREG(HEVC_MPRED_L1_REF03_POC, ref_poc_L1[3]);
5068
5069	WRITE_VREG(HEVC_MPRED_L0_REF04_POC, ref_poc_L0[4]);
5070	WRITE_VREG(HEVC_MPRED_L1_REF04_POC, ref_poc_L1[4]);
5071
5072	WRITE_VREG(HEVC_MPRED_L0_REF05_POC, ref_poc_L0[5]);
5073	WRITE_VREG(HEVC_MPRED_L1_REF05_POC, ref_poc_L1[5]);
5074
5075	WRITE_VREG(HEVC_MPRED_L0_REF06_POC, ref_poc_L0[6]);
5076	WRITE_VREG(HEVC_MPRED_L1_REF06_POC, ref_poc_L1[6]);
5077
5078	WRITE_VREG(HEVC_MPRED_L0_REF07_POC, ref_poc_L0[7]);
5079	WRITE_VREG(HEVC_MPRED_L1_REF07_POC, ref_poc_L1[7]);
5080
5081	WRITE_VREG(HEVC_MPRED_L0_REF08_POC, ref_poc_L0[8]);
5082	WRITE_VREG(HEVC_MPRED_L1_REF08_POC, ref_poc_L1[8]);
5083
5084	WRITE_VREG(HEVC_MPRED_L0_REF09_POC, ref_poc_L0[9]);
5085	WRITE_VREG(HEVC_MPRED_L1_REF09_POC, ref_poc_L1[9]);
5086
5087	WRITE_VREG(HEVC_MPRED_L0_REF10_POC, ref_poc_L0[10]);
5088	WRITE_VREG(HEVC_MPRED_L1_REF10_POC, ref_poc_L1[10]);
5089
5090	WRITE_VREG(HEVC_MPRED_L0_REF11_POC, ref_poc_L0[11]);
5091	WRITE_VREG(HEVC_MPRED_L1_REF11_POC, ref_poc_L1[11]);
5092
5093	WRITE_VREG(HEVC_MPRED_L0_REF12_POC, ref_poc_L0[12]);
5094	WRITE_VREG(HEVC_MPRED_L1_REF12_POC, ref_poc_L1[12]);
5095
5096	WRITE_VREG(HEVC_MPRED_L0_REF13_POC, ref_poc_L0[13]);
5097	WRITE_VREG(HEVC_MPRED_L1_REF13_POC, ref_poc_L1[13]);
5098
5099	WRITE_VREG(HEVC_MPRED_L0_REF14_POC, ref_poc_L0[14]);
5100	WRITE_VREG(HEVC_MPRED_L1_REF14_POC, ref_poc_L1[14]);
5101
5102	WRITE_VREG(HEVC_MPRED_L0_REF15_POC, ref_poc_L0[15]);
5103	WRITE_VREG(HEVC_MPRED_L1_REF15_POC, ref_poc_L1[15]);
5104
5105	if (hevc->new_pic) {
5106	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, mpred_above_buf_start);
5107	WRITE_VREG(HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr);
5108	/* WRITE_VREG(HEVC_MPRED_MV_RPTR,mpred_mv_rd_ptr); */
5109	WRITE_VREG(HEVC_MPRED_MV_RPTR, mpred_mv_rd_start_addr);
5110	} else if (!hevc->isNextSliceSegment) {
5111	/* WRITE_VREG(HEVC_MPRED_MV_RPTR,mpred_mv_rd_ptr_p1); */
5112	WRITE_VREG(HEVC_MPRED_MV_RPTR, mpred_mv_rd_ptr);
5113	}
5114
5115	WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5116	}
5117
5118	static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
5119	{
5120	unsigned int data32, data32_2;
5121	int misc_flag0 = hevc->misc_flag0;
5122	int slice_deblocking_filter_disabled_flag = 0;
5123
5124	int mc_buffer_size_u_v =
5125	hevc->lcu_total * hevc->lcu_size * hevc->lcu_size / 2;
5126	int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
5127	struct PIC_s *cur_pic = hevc->cur_pic;
5128	struct aml_vcodec_ctx * v4l2_ctx = hevc->v4l2_ctx;
5129
5130	data32 = READ_VREG(HEVC_SAO_CTRL0);
5131	data32 &= (~0xf);
5132	data32 |= hevc->lcu_size_log2;
5133	WRITE_VREG(HEVC_SAO_CTRL0, data32);
5134
5135	data32 = (hevc->pic_w | hevc->pic_h << 16);
5136	WRITE_VREG(HEVC_SAO_PIC_SIZE, data32);
5137
5138	data32 = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
5139	WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32);
5140
5141	if (hevc->new_pic)
5142	WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5143	#ifdef LOSLESS_COMPRESS_MODE
5144	/*SUPPORT_10BIT*/
5145	if ((get_double_write_mode(hevc) & 0x10) == 0) {
5146	data32 = READ_VREG(HEVC_SAO_CTRL5);
5147	data32 &= (~(0xff << 16));
5148
5149	if (get_double_write_mode(hevc) == 2 ||
5150	get_double_write_mode(hevc) == 3)
5151	data32 |= (0xff<<16);
5152	else if (get_double_write_mode(hevc) == 4)
5153	data32 |= (0x33<<16);
5154
5155	if (hevc->mem_saving_mode == 1)
5156	data32 |= (1 << 9);
5157	else
5158	data32 &= ~(1 << 9);
5159	if (workaround_enable & 1)
5160	data32 |= (1 << 7);
5161	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5162	}
5163	data32 = cur_pic->mc_y_adr;
5164	if (get_double_write_mode(hevc))
5165	WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr);
5166
5167	if ((get_double_write_mode(hevc) & 0x10) == 0)
5168	WRITE_VREG(HEVC_CM_BODY_START_ADDR, data32);
5169
5170	if (hevc->mmu_enable)
5171	WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr);
5172	#else
5173	data32 = cur_pic->mc_y_adr;
5174	WRITE_VREG(HEVC_SAO_Y_START_ADDR, data32);
5175	#endif
5176	data32 = (mc_buffer_size_u_v_h << 16) << 1;
5177	WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5178
5179	#ifdef LOSLESS_COMPRESS_MODE
5180	/*SUPPORT_10BIT*/
5181	if (get_double_write_mode(hevc))
5182	WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr);
5183	#else
5184	data32 = cur_pic->mc_u_v_adr;
5185	WRITE_VREG(HEVC_SAO_C_START_ADDR, data32);
5186	#endif
5187	data32 = (mc_buffer_size_u_v_h << 16);
5188	WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5189
5190	#ifdef LOSLESS_COMPRESS_MODE
5191	/*SUPPORT_10BIT*/
5192	if (get_double_write_mode(hevc)) {
5193	WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr);
5194	WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr);
5195	}
5196	#else
5197	/* multi tile to do... */
5198	data32 = cur_pic->mc_y_adr;
5199	WRITE_VREG(HEVC_SAO_Y_WPTR, data32);
5200
5201	data32 = cur_pic->mc_u_v_adr;
5202	WRITE_VREG(HEVC_SAO_C_WPTR, data32);
5203	#endif
5204	/* DBLK CONFIG HERE */
5205	if (hevc->new_pic) {
5206	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5207	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
5208	data32 = (0xff << 8) | (0x0 << 0);
5209	else
5210	data32 = (0x57 << 8) | /* 1st/2nd write both enable*/
5211	(0x0 << 0); /* h265 video format*/
5212
5213	if (hevc->pic_w >= 1280)
5214	data32 |= (0x1 << 4); /*dblk pipeline mode=1 for performance*/
5215	data32 &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5216	if (get_double_write_mode(hevc) == 0)
5217	data32 |= (0x1 << 8); /*enable first write*/
5218	else if (get_double_write_mode(hevc) == 0x10)
5219	data32 |= (0x1 << 9); /*double write only*/
5220	else
5221	data32 |= ((0x1 << 8) |(0x1 << 9));
5222
5223	WRITE_VREG(HEVC_DBLK_CFGB, data32);
5224	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5225	"[DBLK DEBUG] HEVC1 CFGB : 0x%x\n", data32);
5226	}
5227	data32 = (hevc->pic_w | hevc->pic_h << 16);
5228	WRITE_VREG(HEVC_DBLK_CFG2, data32);
5229
5230	if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1) {
5231	data32 =
5232	((misc_flag0 >>
5233	PCM_LOOP_FILTER_DISABLED_FLAG_BIT) &
5234	0x1) << 3;
5235	} else
5236	data32 = 0;
5237	data32 |=
5238	(((params->p.pps_cb_qp_offset & 0x1f) << 4) |
5239	((params->p.pps_cr_qp_offset
5240	& 0x1f) <<
5241	9));
5242	data32 |=
5243	(hevc->lcu_size ==
5244	64) ? 0 : ((hevc->lcu_size == 32) ? 1 : 2);
5245
5246	WRITE_VREG(HEVC_DBLK_CFG1, data32);
5247
5248	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5249	/*if (debug & 0x80) {*/
5250	data32 = 1 << 28; /* Debug only: sts1 chooses dblk_main*/
5251	WRITE_VREG(HEVC_DBLK_STS1 + 4, data32); /* 0x3510 */
5252	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5253	"[DBLK DEBUG] HEVC1 STS1 : 0x%x\n",
5254	data32);
5255	/*}*/
5256	}
5257	}
5258	#if 0
5259	data32 = READ_VREG(HEVC_SAO_CTRL1);
5260	data32 &= (~0x3000);
5261	data32 |= (mem_map_mode <<
5262	12);
5263
5264	/* [13:12] axi_aformat,
5265	* 0-Linear, 1-32x32, 2-64x32
5266	*/
5267	WRITE_VREG(HEVC_SAO_CTRL1, data32);
5268
5269	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5270	data32 &= (~0x30);
5271	data32 |= (mem_map_mode <<
5272	4);
5273
5274	/* [5:4] -- address_format
5275	* 00:linear 01:32x32 10:64x32
5276	*/
5277	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5278	#else
5279	/* m8baby test1902 */
5280	data32 = READ_VREG(HEVC_SAO_CTRL1);
5281	data32 &= (~0x3000);
5282	data32 |= (mem_map_mode <<
5283	12);
5284
5285	/* [13:12] axi_aformat, 0-Linear,
5286	* 1-32x32, 2-64x32
5287	*/
5288	data32 &= (~0xff0);
5289	/* data32 |= 0x670; // Big-Endian per 64-bit */
5290	data32 |= endian; /* Big-Endian per 64-bit */
5291	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5292	data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5293	if (get_double_write_mode(hevc) == 0)
5294	data32 |= 0x2; /*disable double write*/
5295	else if (get_double_write_mode(hevc) & 0x10)
5296	data32 |= 0x1; /*disable cm*/
5297	} else {
5298	unsigned int data;
5299	data = (0x57 << 8) | /* 1st/2nd write both enable*/
5300	(0x0 << 0); /* h265 video format*/
5301	if (hevc->pic_w >= 1280)
5302	data |= (0x1 << 4); /*dblk pipeline mode=1 for performance*/
5303	data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5304	if (get_double_write_mode(hevc) == 0)
5305	data |= (0x1 << 8); /*enable first write*/
5306	else if (get_double_write_mode(hevc) & 0x10)
5307	data |= (0x1 << 9); /*double write only*/
5308	else
5309	data |= ((0x1 << 8) |(0x1 << 9));
5310
5311	WRITE_VREG(HEVC_DBLK_CFGB, data);
5312	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5313	"[DBLK DEBUG] HEVC1 CFGB : 0x%x\n", data);
5314	}
5315
5316	/* swap uv */
5317	if (hevc->is_used_v4l) {
5318	if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5319	(v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5320	data32 &= ~(1 << 8); /* NV21 */
5321	else
5322	data32 |= (1 << 8); /* NV12 */
5323	}
5324
5325	/*
5326	* [31:24] ar_fifo1_axi_thred
5327	* [23:16] ar_fifo0_axi_thred
5328	* [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5329	* [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5330	* [11:08] axi_lendian_C
5331	* [07:04] axi_lendian_Y
5332	* [3] reserved
5333	* [2] clk_forceon
5334	* [1] dw_disable:disable double write output
5335	* [0] cm_disable:disable compress output
5336	*/
5337	WRITE_VREG(HEVC_SAO_CTRL1, data32);
5338	if (get_double_write_mode(hevc) & 0x10) {
5339	/* [23:22] dw_v1_ctrl
5340	*[21:20] dw_v0_ctrl
5341	*[19:18] dw_h1_ctrl
5342	*[17:16] dw_h0_ctrl
5343	*/
5344	data32 = READ_VREG(HEVC_SAO_CTRL5);
5345	/*set them all 0 for H265_NV21 (no down-scale)*/
5346	data32 &= ~(0xff << 16);
5347	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5348	}
5349
5350	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5351	data32 &= (~0x30);
5352	/* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5353	data32 |= (mem_map_mode <<
5354	4);
5355	data32 &= (~0xF);
5356	data32 |= 0xf; /* valid only when double write only */
5357	/*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5358
5359	/* swap uv */
5360	if (hevc->is_used_v4l) {
5361	if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5362	(v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5363	data32 |= (1 << 12); /* NV21 */
5364	else
5365	data32 &= ~(1 << 12); /* NV12 */
5366	}
5367
5368	/*
5369	* [3:0] little_endian
5370	* [5:4] address_format 00:linear 01:32x32 10:64x32
5371	* [7:6] reserved
5372	* [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5373	* [11:10] reserved
5374	* [12] CbCr_byte_swap
5375	* [31:13] reserved
5376	*/
5377	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5378	#endif
5379	data32 = 0;
5380	data32_2 = READ_VREG(HEVC_SAO_CTRL0);
5381	data32_2 &= (~0x300);
5382	/* slice_deblocking_filter_disabled_flag = 0;
5383	* ucode has handle it , so read it from ucode directly
5384	*/
5385	if (hevc->tile_enabled) {
5386	data32 |=
5387	((misc_flag0 >>
5388	LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT) &
5389	0x1) << 0;
5390	data32_2 |=
5391	((misc_flag0 >>
5392	LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT) &
5393	0x1) << 8;
5394	}
5395	slice_deblocking_filter_disabled_flag = (misc_flag0 >>
5396	SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
5397	0x1; /* ucode has handle it,so read it from ucode directly */
5398	if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT))
5399	&& (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) {
5400	/* slice_deblocking_filter_disabled_flag =
5401	* (misc_flag0>>SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT)&0x1;
5402	* //ucode has handle it , so read it from ucode directly
5403	*/
5404	data32 |= slice_deblocking_filter_disabled_flag << 2;
5405	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5406	hevc_print_cont(hevc, 0,
5407	"(1,%x)", data32);
5408	if (!slice_deblocking_filter_disabled_flag) {
5409	data32 |= (params->p.slice_beta_offset_div2 & 0xf) << 3;
5410	data32 |= (params->p.slice_tc_offset_div2 & 0xf) << 7;
5411	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5412	hevc_print_cont(hevc, 0,
5413	"(2,%x)", data32);
5414	}
5415	} else {
5416	data32 |=
5417	((misc_flag0 >>
5418	PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
5419	0x1) << 2;
5420	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5421	hevc_print_cont(hevc, 0,
5422	"(3,%x)", data32);
5423	if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
5424	0x1) == 0) {
5425	data32 |= (params->p.pps_beta_offset_div2 & 0xf) << 3;
5426	data32 |= (params->p.pps_tc_offset_div2 & 0xf) << 7;
5427	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5428	hevc_print_cont(hevc, 0,
5429	"(4,%x)", data32);
5430	}
5431	}
5432	if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT))
5433	&& ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT))
5434	|| (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT))
5435	|| (!slice_deblocking_filter_disabled_flag))) {
5436	data32 |=
5437	((misc_flag0 >>
5438	SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5439	& 0x1) << 1;
5440	data32_2 |=
5441	((misc_flag0 >>
5442	SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5443	& 0x1) << 9;
5444	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5445	hevc_print_cont(hevc, 0,
5446	"(5,%x)\n", data32);
5447	} else {
5448	data32 |=
5449	((misc_flag0 >>
5450	PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5451	& 0x1) << 1;
5452	data32_2 |=
5453	((misc_flag0 >>
5454	PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
5455	& 0x1) << 9;
5456	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
5457	hevc_print_cont(hevc, 0,
5458	"(6,%x)\n", data32);
5459	}
5460	WRITE_VREG(HEVC_DBLK_CFG9, data32);
5461	WRITE_VREG(HEVC_SAO_CTRL0, data32_2);
5462	}
5463
5464	#ifdef TEST_NO_BUF
5465	static unsigned char test_flag = 1;
5466	#endif
5467
5468	static void pic_list_process(struct hevc_state_s *hevc)
5469	{
5470	int work_pic_num = get_work_pic_num(hevc);
5471	int alloc_pic_count = 0;
5472	int i;
5473	struct PIC_s *pic;
5474	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5475	pic = hevc->m_PIC[i];
5476	if (pic == NULL || pic->index == -1)
5477	continue;
5478	alloc_pic_count++;
5479	if (pic->output_mark == 0 && pic->referenced == 0
5480	&& pic->output_ready == 0
5481	&& (pic->width != hevc->pic_w ||
5482	pic->height != hevc->pic_h)
5483	) {
5484	set_buf_unused(hevc, pic->BUF_index);
5485	pic->BUF_index = -1;
5486	if (alloc_pic_count > work_pic_num) {
5487	pic->width = 0;
5488	pic->height = 0;
5489	pic->index = -1;
5490	} else {
5491	pic->width = hevc->pic_w;
5492	pic->height = hevc->pic_h;
5493	}
5494	}
5495	}
5496	if (alloc_pic_count < work_pic_num) {
5497	int new_count = alloc_pic_count;
5498	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5499	pic = hevc->m_PIC[i];
5500	if (pic && pic->index == -1) {
5501	pic->index = i;
5502	pic->BUF_index = -1;
5503	pic->width = hevc->pic_w;
5504	pic->height = hevc->pic_h;
5505	new_count++;
5506	if (new_count >=
5507	work_pic_num)
5508	break;
5509	}
5510	}
5511
5512	}
5513	dealloc_unused_buf(hevc);
5514	if (get_alloc_pic_count(hevc)
5515	!= alloc_pic_count) {
5516	hevc_print_cont(hevc, 0,
5517	"%s: work_pic_num is %d, Change alloc_pic_count from %d to %d\n",
5518	__func__,
5519	work_pic_num,
5520	alloc_pic_count,
5521	get_alloc_pic_count(hevc));
5522	}
5523	}
5524
5525	static void recycle_mmu_bufs(struct hevc_state_s *hevc)
5526	{
5527	int i;
5528	struct PIC_s *pic;
5529	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5530	pic = hevc->m_PIC[i];
5531	if (pic == NULL || pic->index == -1)
5532	continue;
5533
5534	if (pic->output_mark == 0 && pic->referenced == 0
5535	&& pic->output_ready == 0
5536	&& pic->scatter_alloc
5537	)
5538	release_pic_mmu_buf(hevc, pic);
5539	}
5540
5541	}
5542
5543	static struct PIC_s *get_new_pic(struct hevc_state_s *hevc,
5544	union param_u *rpm_param)
5545	{
5546	struct PIC_s *new_pic = NULL;
5547	struct PIC_s *pic;
5548	int i;
5549	int ret;
5550
5551	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5552	pic = hevc->m_PIC[i];
5553	if (pic == NULL || pic->index == -1)
5554	continue;
5555
5556	if (pic->output_mark == 0 && pic->referenced == 0
5557	&& pic->output_ready == 0
5558	&& pic->width == hevc->pic_w
5559	&& pic->height == hevc->pic_h
5560	) {
5561	if (new_pic) {
5562	if (new_pic->POC != INVALID_POC) {
5563	if (pic->POC == INVALID_POC ||
5564	pic->POC < new_pic->POC)
5565	new_pic = pic;
5566	}
5567	} else
5568	new_pic = pic;
5569	}
5570	}
5571
5572	if (new_pic == NULL)
5573	return NULL;
5574
5575	if (new_pic->BUF_index < 0) {
5576	ret = hevc->is_used_v4l ?
5577	v4l_alloc_buf(hevc) :
5578	alloc_buf(hevc);
5579	if (ret < 0)
5580	return NULL;
5581
5582	ret = hevc->is_used_v4l ?
5583	v4l_config_pic(hevc, new_pic) :
5584	config_pic(hevc, new_pic);
5585	if (ret < 0) {
5586	dealloc_pic_buf(hevc, new_pic);
5587	return NULL;
5588	}
5589
5590	new_pic->width = hevc->pic_w;
5591	new_pic->height = hevc->pic_h;
5592	set_canvas(hevc, new_pic);
5593
5594	init_pic_list_hw(hevc);
5595	}
5596
5597	if (new_pic) {
5598	new_pic->double_write_mode =
5599	get_double_write_mode(hevc);
5600	if (new_pic->double_write_mode)
5601	set_canvas(hevc, new_pic);
5602
5603	#ifdef TEST_NO_BUF
5604	if (test_flag) {
5605	test_flag = 0;
5606	return NULL;
5607	} else
5608	test_flag = 1;
5609	#endif
5610	if (get_mv_buf(hevc, new_pic) < 0)
5611	return NULL;
5612
5613	if (hevc->mmu_enable) {
5614	ret = H265_alloc_mmu(hevc, new_pic,
5615	rpm_param->p.bit_depth,
5616	hevc->frame_mmu_map_addr);
5617	if (ret != 0) {
5618	put_mv_buf(hevc, new_pic);
5619	hevc_print(hevc, 0,
5620	"can't alloc need mmu1,idx %d ret =%d\n",
5621	new_pic->decode_idx,
5622	ret);
5623	return NULL;
5624	}
5625	}
5626	new_pic->referenced = 1;
5627	new_pic->decode_idx = hevc->decode_idx;
5628	new_pic->slice_idx = 0;
5629	new_pic->referenced = 1;
5630	new_pic->output_mark = 0;
5631	new_pic->recon_mark = 0;
5632	new_pic->error_mark = 0;
5633	new_pic->dis_mark = 0;
5634	/* new_pic->output_ready = 0; */
5635	new_pic->num_reorder_pic = rpm_param->p.sps_num_reorder_pics_0;
5636	new_pic->losless_comp_body_size = hevc->losless_comp_body_size;
5637	new_pic->POC = hevc->curr_POC;
5638	new_pic->pic_struct = hevc->curr_pic_struct;
5639	if (new_pic->aux_data_buf)
5640	release_aux_data(hevc, new_pic);
5641	new_pic->mem_saving_mode =
5642	hevc->mem_saving_mode;
5643	new_pic->bit_depth_luma =
5644	hevc->bit_depth_luma;
5645	new_pic->bit_depth_chroma =
5646	hevc->bit_depth_chroma;
5647	new_pic->video_signal_type =
5648	hevc->video_signal_type;
5649
5650	new_pic->conformance_window_flag =
5651	hevc->param.p.conformance_window_flag;
5652	new_pic->conf_win_left_offset =
5653	hevc->param.p.conf_win_left_offset;
5654	new_pic->conf_win_right_offset =
5655	hevc->param.p.conf_win_right_offset;
5656	new_pic->conf_win_top_offset =
5657	hevc->param.p.conf_win_top_offset;
5658	new_pic->conf_win_bottom_offset =
5659	hevc->param.p.conf_win_bottom_offset;
5660	new_pic->chroma_format_idc =
5661	hevc->param.p.chroma_format_idc;
5662
5663	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
5664	"%s: index %d, buf_idx %d, decode_idx %d, POC %d\n",
5665	__func__, new_pic->index,
5666	new_pic->BUF_index, new_pic->decode_idx,
5667	new_pic->POC);
5668
5669	}
5670	if (pic_list_debug & 0x1) {
5671	dump_pic_list(hevc);
5672	pr_err("\n*******************************************\n");
5673	}
5674
5675	return new_pic;
5676	}
5677
5678	static int get_display_pic_num(struct hevc_state_s *hevc)
5679	{
5680	int i;
5681	struct PIC_s *pic;
5682	int num = 0;
5683
5684	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
5685	pic = hevc->m_PIC[i];
5686	if (pic == NULL ||
5687	pic->index == -1)
5688	continue;
5689
5690	if (pic->output_ready == 1)
5691	num++;
5692	}
5693	return num;
5694	}
5695
5696	static void flush_output(struct hevc_state_s *hevc, struct PIC_s *pic)
5697	{
5698	struct PIC_s *pic_display;
5699
5700	if (pic) {
5701	/*PB skip control */
5702	if (pic->error_mark == 0 && hevc->PB_skip_mode == 1) {
5703	/* start decoding after first I */
5704	hevc->ignore_bufmgr_error |= 0x1;
5705	}
5706	if (hevc->ignore_bufmgr_error & 1) {
5707	if (hevc->PB_skip_count_after_decoding > 0)
5708	hevc->PB_skip_count_after_decoding--;
5709	else {
5710	/* start displaying */
5711	hevc->ignore_bufmgr_error |= 0x2;
5712	}
5713	}
5714	/**/
5715	if (pic->POC != INVALID_POC) {
5716	pic->output_mark = 1;
5717	pic->recon_mark = 1;
5718	}
5719	pic->recon_mark = 1;
5720	}
5721	do {
5722	pic_display = output_pic(hevc, 1);
5723
5724	if (pic_display) {
5725	pic_display->referenced = 0;
5726	put_mv_buf(hevc, pic_display);
5727	if ((pic_display->error_mark
5728	&& ((hevc->ignore_bufmgr_error & 0x2) == 0))
5729	|| (get_dbg_flag(hevc) &
5730	H265_DEBUG_DISPLAY_CUR_FRAME)
5731	|| (get_dbg_flag(hevc) &
5732	H265_DEBUG_NO_DISPLAY)) {
5733	pic_display->output_ready = 0;
5734	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
5735	hevc_print(hevc, 0,
5736	"[BM] Display: POC %d, ",
5737	pic_display->POC);
5738	hevc_print_cont(hevc, 0,
5739	"decoding index %d ==> ",
5740	pic_display->decode_idx);
5741	hevc_print_cont(hevc, 0,
5742	"Debug mode or error, recycle it\n");
5743	}
5744	} else {
5745	if (hevc->i_only & 0x1
5746	&& pic_display->slice_type != 2) {
5747	pic_display->output_ready = 0;
5748	} else {
5749	prepare_display_buf(hevc, pic_display);
5750	if (get_dbg_flag(hevc)
5751	& H265_DEBUG_BUFMGR) {
5752	hevc_print(hevc, 0,
5753	"[BM] flush Display: POC %d, ",
5754	pic_display->POC);
5755	hevc_print_cont(hevc, 0,
5756	"decoding index %d\n",
5757	pic_display->decode_idx);
5758	}
5759	}
5760	}
5761	}
5762	} while (pic_display);
5763	clear_referenced_flag(hevc);
5764	}
5765
5766	/*
5767	* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta
5768	*/
5769	static void set_aux_data(struct hevc_state_s *hevc,
5770	struct PIC_s *pic, unsigned char suffix_flag,
5771	unsigned char dv_meta_flag)
5772	{
5773	int i;
5774	unsigned short *aux_adr;
5775	unsigned int size_reg_val =
5776	READ_VREG(HEVC_AUX_DATA_SIZE);
5777	unsigned int aux_count = 0;
5778	int aux_size = 0;
5779	if (pic == NULL || 0 == aux_data_is_avaible(hevc))
5780	return;
5781
5782	if (hevc->aux_data_dirty ||
5783	hevc->m_ins_flag == 0) {
5784
5785	hevc->aux_data_dirty = 0;
5786	}
5787
5788	if (suffix_flag) {
5789	aux_adr = (unsigned short *)
5790	(hevc->aux_addr +
5791	hevc->prefix_aux_size);
5792	aux_count =
5793	((size_reg_val & 0xffff) << 4)
5794	>> 1;
5795	aux_size =
5796	hevc->suffix_aux_size;
5797	} else {
5798	aux_adr =
5799	(unsigned short *)hevc->aux_addr;
5800	aux_count =
5801	((size_reg_val >> 16) << 4)
5802	>> 1;
5803	aux_size =
5804	hevc->prefix_aux_size;
5805	}
5806	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) {
5807	hevc_print(hevc, 0,
5808	"%s:pic 0x%p old size %d count %d,suf %d dv_flag %d\r\n",
5809	__func__, pic, pic->aux_data_size,
5810	aux_count, suffix_flag, dv_meta_flag);
5811	}
5812	if (aux_size > 0 && aux_count > 0) {
5813	int heads_size = 0;
5814	int new_size;
5815	char *new_buf;
5816
5817	for (i = 0; i < aux_count; i++) {
5818	unsigned char tag = aux_adr[i] >> 8;
5819	if (tag != 0 && tag != 0xff) {
5820	if (dv_meta_flag == 0)
5821	heads_size += 8;
5822	else if (dv_meta_flag == 1 && tag == 0x1)
5823	heads_size += 8;
5824	else if (dv_meta_flag == 2 && tag != 0x1)
5825	heads_size += 8;
5826	}
5827	}
5828	new_size = pic->aux_data_size + aux_count + heads_size;
5829	new_buf = vmalloc(new_size);
5830	if (new_buf) {
5831	unsigned char valid_tag = 0;
5832	unsigned char *h =
5833	new_buf +
5834	pic->aux_data_size;
5835	unsigned char *p = h + 8;
5836	int len = 0;
5837	int padding_len = 0;
5838	memcpy(new_buf, pic->aux_data_buf, pic->aux_data_size);
5839	if (pic->aux_data_buf)
5840	vfree(pic->aux_data_buf);
5841	pic->aux_data_buf = new_buf;
5842	for (i = 0; i < aux_count; i += 4) {
5843	int ii;
5844	unsigned char tag = aux_adr[i + 3] >> 8;
5845	if (tag != 0 && tag != 0xff) {
5846	if (dv_meta_flag == 0)
5847	valid_tag = 1;
5848	else if (dv_meta_flag == 1
5849	&& tag == 0x1)
5850	valid_tag = 1;
5851	else if (dv_meta_flag == 2
5852	&& tag != 0x1)
5853	valid_tag = 1;
5854	else
5855	valid_tag = 0;
5856	if (valid_tag && len > 0) {
5857	pic->aux_data_size +=
5858	(len + 8);
5859	h[0] = (len >> 24)
5860	& 0xff;
5861	h[1] = (len >> 16)
5862	& 0xff;
5863	h[2] = (len >> 8)
5864	& 0xff;
5865	h[3] = (len >> 0)
5866	& 0xff;
5867	h[6] =
5868	(padding_len >> 8)
5869	& 0xff;
5870	h[7] = (padding_len)
5871	& 0xff;
5872	h += (len + 8);
5873	p += 8;
5874	len = 0;
5875	padding_len = 0;
5876	}
5877	if (valid_tag) {
5878	h[4] = tag;
5879	h[5] = 0;
5880	h[6] = 0;
5881	h[7] = 0;
5882	}
5883	}
5884	if (valid_tag) {
5885	for (ii = 0; ii < 4; ii++) {
5886	unsigned short aa =
5887	aux_adr[i + 3
5888	- ii];
5889	*p = aa & 0xff;
5890	p++;
5891	len++;
5892	/*if ((aa >> 8) == 0xff)
5893	padding_len++;*/
5894	}
5895	}
5896	}
5897	if (len > 0) {
5898	pic->aux_data_size += (len + 8);
5899	h[0] = (len >> 24) & 0xff;
5900	h[1] = (len >> 16) & 0xff;
5901	h[2] = (len >> 8) & 0xff;
5902	h[3] = (len >> 0) & 0xff;
5903	h[6] = (padding_len >> 8) & 0xff;
5904	h[7] = (padding_len) & 0xff;
5905	}
5906	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) {
5907	hevc_print(hevc, 0,
5908	"aux: (size %d) suffix_flag %d\n",
5909	pic->aux_data_size, suffix_flag);
5910	for (i = 0; i < pic->aux_data_size; i++) {
5911	hevc_print_cont(hevc, 0,
5912	"%02x ", pic->aux_data_buf[i]);
5913	if (((i + 1) & 0xf) == 0)
5914	hevc_print_cont(hevc, 0, "\n");
5915	}
5916	hevc_print_cont(hevc, 0, "\n");
5917	}
5918
5919	} else {
5920	hevc_print(hevc, 0, "new buf alloc failed\n");
5921	if (pic->aux_data_buf)
5922	vfree(pic->aux_data_buf);
5923	pic->aux_data_buf = NULL;
5924	pic->aux_data_size = 0;
5925	}
5926	}
5927
5928	}
5929
5930	static void release_aux_data(struct hevc_state_s *hevc,
5931	struct PIC_s *pic)
5932	{
5933	if (pic->aux_data_buf)
5934	vfree(pic->aux_data_buf);
5935	pic->aux_data_buf = NULL;
5936	pic->aux_data_size = 0;
5937	}
5938
5939	static inline void hevc_pre_pic(struct hevc_state_s *hevc,
5940	struct PIC_s *pic)
5941	{
5942
5943	/* prev pic */
5944	/*if (hevc->curr_POC != 0) {*/
5945	int decoded_poc = hevc->iPrevPOC;
5946	#ifdef MULTI_INSTANCE_SUPPORT
5947	if (hevc->m_ins_flag) {
5948	decoded_poc = hevc->decoded_poc;
5949	hevc->decoded_poc = INVALID_POC;
5950	}
5951	#endif
5952	if (hevc->m_nalUnitType != NAL_UNIT_CODED_SLICE_IDR
5953	&& hevc->m_nalUnitType !=
5954	NAL_UNIT_CODED_SLICE_IDR_N_LP) {
5955	struct PIC_s *pic_display;
5956
5957	pic = get_pic_by_POC(hevc, decoded_poc);
5958	if (pic && (pic->POC != INVALID_POC)) {
5959	/*PB skip control */
5960	if (pic->error_mark == 0
5961	&& hevc->PB_skip_mode == 1) {
5962	/* start decoding after
5963	* first I
5964	*/
5965	hevc->ignore_bufmgr_error |= 0x1;
5966	}
5967	if (hevc->ignore_bufmgr_error & 1) {
5968	if (hevc->PB_skip_count_after_decoding > 0) {
5969	hevc->PB_skip_count_after_decoding--;
5970	} else {
5971	/* start displaying */
5972	hevc->ignore_bufmgr_error |= 0x2;
5973	}
5974	}
5975	if (hevc->mmu_enable
5976	&& ((hevc->double_write_mode & 0x10) == 0)) {
5977	if (!hevc->m_ins_flag) {
5978	hevc->used_4k_num =
5979	READ_VREG(HEVC_SAO_MMU_STATUS) >> 16;
5980
5981	if ((!is_skip_decoding(hevc, pic)) &&
5982	(hevc->used_4k_num >= 0) &&
5983	(hevc->cur_pic->scatter_alloc
5984	== 1)) {
5985	hevc_print(hevc,
5986	H265_DEBUG_BUFMGR_MORE,
5987	"%s pic index %d scatter_alloc %d page_start %d\n",
5988	"decoder_mmu_box_free_idx_tail",
5989	hevc->cur_pic->index,
5990	hevc->cur_pic->scatter_alloc,
5991	hevc->used_4k_num);
5992	hevc_mmu_dma_check(hw_to_vdec(hevc));
5993	decoder_mmu_box_free_idx_tail(
5994	hevc->mmu_box,
5995	hevc->cur_pic->index,
5996	hevc->used_4k_num);
5997	hevc->cur_pic->scatter_alloc
5998	= 2;
5999	}
6000	hevc->used_4k_num = -1;
6001	}
6002	}
6003
6004	pic->output_mark = 1;
6005	pic->recon_mark = 1;
6006	pic->dis_mark = 1;
6007	}
6008	do {
6009	pic_display = output_pic(hevc, 0);
6010
6011	if (pic_display) {
6012	if ((pic_display->error_mark &&
6013	((hevc->ignore_bufmgr_error &
6014	0x2) == 0))
6015	|| (get_dbg_flag(hevc) &
6016	H265_DEBUG_DISPLAY_CUR_FRAME)
6017	|| (get_dbg_flag(hevc) &
6018	H265_DEBUG_NO_DISPLAY)) {
6019	pic_display->output_ready = 0;
6020	if (get_dbg_flag(hevc) &
6021	H265_DEBUG_BUFMGR) {
6022	hevc_print(hevc, 0,
6023	"[BM] Display: POC %d, ",
6024	pic_display->POC);
6025	hevc_print_cont(hevc, 0,
6026	"decoding index %d ==> ",
6027	pic_display->
6028	decode_idx);
6029	hevc_print_cont(hevc, 0,
6030	"Debug or err,recycle it\n");
6031	}
6032	} else {
6033	if (hevc->i_only & 0x1
6034	&& pic_display->
6035	slice_type != 2) {
6036	pic_display->output_ready = 0;
6037	} else {
6038	prepare_display_buf
6039	(hevc,
6040	pic_display);
6041	if (get_dbg_flag(hevc) &
6042	H265_DEBUG_BUFMGR) {
6043	hevc_print(hevc, 0,
6044	"[BM] Display: POC %d, ",
6045	pic_display->POC);
6046	hevc_print_cont(hevc, 0,
6047	"decoding index %d\n",
6048	pic_display->
6049	decode_idx);
6050	}
6051	}
6052	}
6053	}
6054	} while (pic_display);
6055	} else {
6056	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6057	hevc_print(hevc, 0,
6058	"[BM] current pic is IDR, ");
6059	hevc_print(hevc, 0,
6060	"clear referenced flag of all buffers\n");
6061	}
6062	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
6063	dump_pic_list(hevc);
6064	pic = get_pic_by_POC(hevc, decoded_poc);
6065	flush_output(hevc, pic);
6066	}
6067
6068	}
6069
6070	static void check_pic_decoded_error_pre(struct hevc_state_s *hevc,
6071	int decoded_lcu)
6072	{
6073	int current_lcu_idx = decoded_lcu;
6074	if (decoded_lcu < 0)
6075	return;
6076
6077	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6078	hevc_print(hevc, 0,
6079	"cur lcu idx = %d, (total %d)\n",
6080	current_lcu_idx, hevc->lcu_total);
6081	}
6082	if ((error_handle_policy & 0x20) == 0 && hevc->cur_pic != NULL) {
6083	if (hevc->first_pic_after_recover) {
6084	if (current_lcu_idx !=
6085	((hevc->lcu_x_num_pre*hevc->lcu_y_num_pre) - 1))
6086	hevc->cur_pic->error_mark = 1;
6087	} else {
6088	if (hevc->lcu_x_num_pre != 0
6089	&& hevc->lcu_y_num_pre != 0
6090	&& current_lcu_idx != 0
6091	&& current_lcu_idx <
6092	((hevc->lcu_x_num_pre*hevc->lcu_y_num_pre) - 1))
6093	hevc->cur_pic->error_mark = 1;
6094	}
6095	if (hevc->cur_pic->error_mark) {
6096	hevc_print(hevc, 0,
6097	"cur lcu idx = %d, (total %d), set error_mark\n",
6098	current_lcu_idx,
6099	hevc->lcu_x_num_pre*hevc->lcu_y_num_pre);
6100	if (is_log_enable(hevc))
6101	add_log(hevc,
6102	"cur lcu idx = %d, (total %d), set error_mark",
6103	current_lcu_idx,
6104	hevc->lcu_x_num_pre *
6105	hevc->lcu_y_num_pre);
6106
6107	}
6108
6109	}
6110	if (hevc->cur_pic && hevc->head_error_flag) {
6111	hevc->cur_pic->error_mark = 1;
6112	hevc_print(hevc, 0,
6113	"head has error, set error_mark\n");
6114	}
6115
6116	if ((error_handle_policy & 0x80) == 0) {
6117	if (hevc->over_decode && hevc->cur_pic) {
6118	hevc_print(hevc, 0,
6119	"over decode, set error_mark\n");
6120	hevc->cur_pic->error_mark = 1;
6121	}
6122	}
6123
6124	hevc->lcu_x_num_pre = hevc->lcu_x_num;
6125	hevc->lcu_y_num_pre = hevc->lcu_y_num;
6126	}
6127
6128	static void check_pic_decoded_error(struct hevc_state_s *hevc,
6129	int decoded_lcu)
6130	{
6131	int current_lcu_idx = decoded_lcu;
6132	if (decoded_lcu < 0)
6133	return;
6134
6135	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6136	hevc_print(hevc, 0,
6137	"cur lcu idx = %d, (total %d)\n",
6138	current_lcu_idx, hevc->lcu_total);
6139	}
6140	if ((error_handle_policy & 0x20) == 0 && hevc->cur_pic != NULL) {
6141	if (hevc->lcu_x_num != 0
6142	&& hevc->lcu_y_num != 0
6143	&& current_lcu_idx != 0
6144	&& current_lcu_idx <
6145	((hevc->lcu_x_num*hevc->lcu_y_num) - 1))
6146	hevc->cur_pic->error_mark = 1;
6147	if (hevc->cur_pic->error_mark) {
6148	hevc_print(hevc, 0,
6149	"cur lcu idx = %d, (total %d), set error_mark\n",
6150	current_lcu_idx,
6151	hevc->lcu_x_num*hevc->lcu_y_num);
6152	if (((hevc->i_only & 0x4) == 0) && hevc->cur_pic->POC && ( hevc->cur_pic->slice_type == 0)
6153	&& ((hevc->cur_pic->POC + MAX_BUF_NUM) < hevc->iPrevPOC)) {
6154	hevc_print(hevc, 0,
6155	"Flush.. num_reorder_pic %d pic->POC %d hevc->iPrevPOC %d\n",
6156	hevc->sps_num_reorder_pics_0,hevc->cur_pic->POC ,hevc->iPrevPOC);
6157	flush_output(hevc, get_pic_by_POC(hevc, hevc->cur_pic->POC ));
6158	}
6159	if (is_log_enable(hevc))
6160	add_log(hevc,
6161	"cur lcu idx = %d, (total %d), set error_mark",
6162	current_lcu_idx,
6163	hevc->lcu_x_num *
6164	hevc->lcu_y_num);
6165
6166	}
6167
6168	}
6169	if (hevc->cur_pic && hevc->head_error_flag) {
6170	hevc->cur_pic->error_mark = 1;
6171	hevc_print(hevc, 0,
6172	"head has error, set error_mark\n");
6173	}
6174
6175	if ((error_handle_policy & 0x80) == 0) {
6176	if (hevc->over_decode && hevc->cur_pic) {
6177	hevc_print(hevc, 0,
6178	"over decode, set error_mark\n");
6179	hevc->cur_pic->error_mark = 1;
6180	}
6181	}
6182	}
6183
6184	/* only when we decoded one field or one frame,
6185	we can call this function to get qos info*/
6186	static void get_picture_qos_info(struct hevc_state_s *hevc)
6187	{
6188	struct PIC_s *picture = hevc->cur_pic;
6189
6190	/*
6191	#define DEBUG_QOS
6192	*/
6193
6194	if (!hevc->cur_pic)
6195	return;
6196
6197	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
6198	unsigned char a[3];
6199	unsigned char i, j, t;
6200	unsigned long data;
6201
6202	data = READ_VREG(HEVC_MV_INFO);
6203	if (picture->slice_type == I_SLICE)
6204	data = 0;
6205	a[0] = data & 0xff;
6206	a[1] = (data >> 8) & 0xff;
6207	a[2] = (data >> 16) & 0xff;
6208
6209	for (i = 0; i < 3; i++)
6210	for (j = i+1; j < 3; j++) {
6211	if (a[j] < a[i]) {
6212	t = a[j];
6213	a[j] = a[i];
6214	a[i] = t;
6215	} else if (a[j] == a[i]) {
6216	a[i]++;
6217	t = a[j];
6218	a[j] = a[i];
6219	a[i] = t;
6220	}
6221	}
6222	picture->max_mv = a[2];
6223	picture->avg_mv = a[1];
6224	picture->min_mv = a[0];
6225	#ifdef DEBUG_QOS
6226	hevc_print(hevc, 0, "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
6227	data, a[0], a[1], a[2]);
6228	#endif
6229
6230	data = READ_VREG(HEVC_QP_INFO);
6231	a[0] = data & 0x1f;
6232	a[1] = (data >> 8) & 0x3f;
6233	a[2] = (data >> 16) & 0x7f;
6234
6235	for (i = 0; i < 3; i++)
6236	for (j = i+1; j < 3; j++) {
6237	if (a[j] < a[i]) {
6238	t = a[j];
6239	a[j] = a[i];
6240	a[i] = t;
6241	} else if (a[j] == a[i]) {
6242	a[i]++;
6243	t = a[j];
6244	a[j] = a[i];
6245	a[i] = t;
6246	}
6247	}
6248	picture->max_qp = a[2];
6249	picture->avg_qp = a[1];
6250	picture->min_qp = a[0];
6251	#ifdef DEBUG_QOS
6252	hevc_print(hevc, 0, "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
6253	data, a[0], a[1], a[2]);
6254	#endif
6255
6256	data = READ_VREG(HEVC_SKIP_INFO);
6257	a[0] = data & 0x1f;
6258	a[1] = (data >> 8) & 0x3f;
6259	a[2] = (data >> 16) & 0x7f;
6260
6261	for (i = 0; i < 3; i++)
6262	for (j = i+1; j < 3; j++) {
6263	if (a[j] < a[i]) {
6264	t = a[j];
6265	a[j] = a[i];
6266	a[i] = t;
6267	} else if (a[j] == a[i]) {
6268	a[i]++;
6269	t = a[j];
6270	a[j] = a[i];
6271	a[i] = t;
6272	}
6273	}
6274	picture->max_skip = a[2];
6275	picture->avg_skip = a[1];
6276	picture->min_skip = a[0];
6277
6278	#ifdef DEBUG_QOS
6279	hevc_print(hevc, 0,
6280	"skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
6281	data, a[0], a[1], a[2]);
6282	#endif
6283	} else {
6284	uint32_t blk88_y_count;
6285	uint32_t blk88_c_count;
6286	uint32_t blk22_mv_count;
6287	uint32_t rdata32;
6288	int32_t mv_hi;
6289	int32_t mv_lo;
6290	uint32_t rdata32_l;
6291	uint32_t mvx_L0_hi;
6292	uint32_t mvy_L0_hi;
6293	uint32_t mvx_L1_hi;
6294	uint32_t mvy_L1_hi;
6295	int64_t value;
6296	uint64_t temp_value;
6297	#ifdef DEBUG_QOS
6298	int pic_number = picture->POC;
6299	#endif
6300
6301	picture->max_mv = 0;
6302	picture->avg_mv = 0;
6303	picture->min_mv = 0;
6304
6305	picture->max_skip = 0;
6306	picture->avg_skip = 0;
6307	picture->min_skip = 0;
6308
6309	picture->max_qp = 0;
6310	picture->avg_qp = 0;
6311	picture->min_qp = 0;
6312
6313
6314
6315	#ifdef DEBUG_QOS
6316	hevc_print(hevc, 0, "slice_type:%d, poc:%d\n",
6317	picture->slice_type,
6318	picture->POC);
6319	#endif
6320	/* set rd_idx to 0 */
6321	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
6322
6323	blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6324	if (blk88_y_count == 0) {
6325	#ifdef DEBUG_QOS
6326	hevc_print(hevc, 0,
6327	"[Picture %d Quality] NO Data yet.\n",
6328	pic_number);
6329	#endif
6330	/* reset all counts */
6331	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6332	return;
6333	}
6334	/* qp_y_sum */
6335	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6336	#ifdef DEBUG_QOS
6337	hevc_print(hevc, 0,
6338	"[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
6339	pic_number, rdata32/blk88_y_count,
6340	rdata32, blk88_y_count);
6341	#endif
6342	picture->avg_qp = rdata32/blk88_y_count;
6343	/* intra_y_count */
6344	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6345	#ifdef DEBUG_QOS
6346	hevc_print(hevc, 0,
6347	"[Picture %d Quality] Y intra rate : %d%c (%d)\n",
6348	pic_number, rdata32*100/blk88_y_count,
6349	'%', rdata32);
6350	#endif
6351	/* skipped_y_count */
6352	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6353	#ifdef DEBUG_QOS
6354	hevc_print(hevc, 0,
6355	"[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
6356	pic_number, rdata32*100/blk88_y_count,
6357	'%', rdata32);
6358	#endif
6359	picture->avg_skip = rdata32*100/blk88_y_count;
6360	/* coeff_non_zero_y_count */
6361	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6362	#ifdef DEBUG_QOS
6363	hevc_print(hevc, 0,
6364	"[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
6365	pic_number, (100 - rdata32*100/(blk88_y_count*1)),
6366	'%', rdata32);
6367	#endif
6368	/* blk66_c_count */
6369	blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6370	if (blk88_c_count == 0) {
6371	#ifdef DEBUG_QOS
6372	hevc_print(hevc, 0,
6373	"[Picture %d Quality] NO Data yet.\n",
6374	pic_number);
6375	#endif
6376	/* reset all counts */
6377	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6378	return;
6379	}
6380	/* qp_c_sum */
6381	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6382	#ifdef DEBUG_QOS
6383	hevc_print(hevc, 0,
6384	"[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
6385	pic_number, rdata32/blk88_c_count,
6386	rdata32, blk88_c_count);
6387	#endif
6388	/* intra_c_count */
6389	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6390	#ifdef DEBUG_QOS
6391	hevc_print(hevc, 0,
6392	"[Picture %d Quality] C intra rate : %d%c (%d)\n",
6393	pic_number, rdata32*100/blk88_c_count,
6394	'%', rdata32);
6395	#endif
6396	/* skipped_cu_c_count */
6397	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6398	#ifdef DEBUG_QOS
6399	hevc_print(hevc, 0,
6400	"[Picture %d Quality] C skipped rate : %d%c (%d)\n",
6401	pic_number, rdata32*100/blk88_c_count,
6402	'%', rdata32);
6403	#endif
6404	/* coeff_non_zero_c_count */
6405	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6406	#ifdef DEBUG_QOS
6407	hevc_print(hevc, 0,
6408	"[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
6409	pic_number, (100 - rdata32*100/(blk88_c_count*1)),
6410	'%', rdata32);
6411	#endif
6412
6413	/* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
6414	1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
6415	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6416	#ifdef DEBUG_QOS
6417	hevc_print(hevc, 0, "[Picture %d Quality] Y QP min : %d\n",
6418	pic_number, (rdata32>>0)&0xff);
6419	#endif
6420	picture->min_qp = (rdata32>>0)&0xff;
6421
6422	#ifdef DEBUG_QOS
6423	hevc_print(hevc, 0, "[Picture %d Quality] Y QP max : %d\n",
6424	pic_number, (rdata32>>8)&0xff);
6425	#endif
6426	picture->max_qp = (rdata32>>8)&0xff;
6427
6428	#ifdef DEBUG_QOS
6429	hevc_print(hevc, 0, "[Picture %d Quality] C QP min : %d\n",
6430	pic_number, (rdata32>>16)&0xff);
6431	hevc_print(hevc, 0, "[Picture %d Quality] C QP max : %d\n",
6432	pic_number, (rdata32>>24)&0xff);
6433	#endif
6434
6435	/* blk22_mv_count */
6436	blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
6437	if (blk22_mv_count == 0) {
6438	#ifdef DEBUG_QOS
6439	hevc_print(hevc, 0,
6440	"[Picture %d Quality] NO MV Data yet.\n",
6441	pic_number);
6442	#endif
6443	/* reset all counts */
6444	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6445	return;
6446	}
6447	/* mvy_L1_count[39:32], mvx_L1_count[39:32],
6448	mvy_L0_count[39:32], mvx_L0_count[39:32] */
6449	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6450	/* should all be 0x00 or 0xff */
6451	#ifdef DEBUG_QOS
6452	hevc_print(hevc, 0,
6453	"[Picture %d Quality] MV AVG High Bits: 0x%X\n",
6454	pic_number, rdata32);
6455	#endif
6456	mvx_L0_hi = ((rdata32>>0)&0xff);
6457	mvy_L0_hi = ((rdata32>>8)&0xff);
6458	mvx_L1_hi = ((rdata32>>16)&0xff);
6459	mvy_L1_hi = ((rdata32>>24)&0xff);
6460
6461	/* mvx_L0_count[31:0] */
6462	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6463	temp_value = mvx_L0_hi;
6464	temp_value = (temp_value << 32) | rdata32_l;
6465
6466	if (mvx_L0_hi & 0x80)
6467	value = 0xFFFFFFF000000000 | temp_value;
6468	else
6469	value = temp_value;
6470	value = div_s64(value, blk22_mv_count);
6471	#ifdef DEBUG_QOS
6472	hevc_print(hevc, 0,
6473	"[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
6474	pic_number, (int)value,
6475	value, blk22_mv_count);
6476	#endif
6477	picture->avg_mv = value;
6478
6479	/* mvy_L0_count[31:0] */
6480	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6481	temp_value = mvy_L0_hi;
6482	temp_value = (temp_value << 32) | rdata32_l;
6483
6484	if (mvy_L0_hi & 0x80)
6485	value = 0xFFFFFFF000000000 | temp_value;
6486	else
6487	value = temp_value;
6488	#ifdef DEBUG_QOS
6489	hevc_print(hevc, 0,
6490	"[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
6491	pic_number, rdata32_l/blk22_mv_count,
6492	value, blk22_mv_count);
6493	#endif
6494
6495	/* mvx_L1_count[31:0] */
6496	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6497	temp_value = mvx_L1_hi;
6498	temp_value = (temp_value << 32) | rdata32_l;
6499	if (mvx_L1_hi & 0x80)
6500	value = 0xFFFFFFF000000000 | temp_value;
6501	else
6502	value = temp_value;
6503	#ifdef DEBUG_QOS
6504	hevc_print(hevc, 0,
6505	"[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
6506	pic_number, rdata32_l/blk22_mv_count,
6507	value, blk22_mv_count);
6508	#endif
6509
6510	/* mvy_L1_count[31:0] */
6511	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
6512	temp_value = mvy_L1_hi;
6513	temp_value = (temp_value << 32) | rdata32_l;
6514	if (mvy_L1_hi & 0x80)
6515	value = 0xFFFFFFF000000000 | temp_value;
6516	else
6517	value = temp_value;
6518	#ifdef DEBUG_QOS
6519	hevc_print(hevc, 0,
6520	"[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
6521	pic_number, rdata32_l/blk22_mv_count,
6522	value, blk22_mv_count);
6523	#endif
6524
6525	/* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
6526	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6527	mv_hi = (rdata32>>16)&0xffff;
6528	if (mv_hi & 0x8000)
6529	mv_hi = 0x8000 - mv_hi;
6530	#ifdef DEBUG_QOS
6531	hevc_print(hevc, 0, "[Picture %d Quality] MVX_L0 MAX : %d\n",
6532	pic_number, mv_hi);
6533	#endif
6534	picture->max_mv = mv_hi;
6535
6536	mv_lo = (rdata32>>0)&0xffff;
6537	if (mv_lo & 0x8000)
6538	mv_lo = 0x8000 - mv_lo;
6539	#ifdef DEBUG_QOS
6540	hevc_print(hevc, 0, "[Picture %d Quality] MVX_L0 MIN : %d\n",
6541	pic_number, mv_lo);
6542	#endif
6543	picture->min_mv = mv_lo;
6544
6545	/* {mvy_L0_max, mvy_L0_min} */
6546	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6547	mv_hi = (rdata32>>16)&0xffff;
6548	if (mv_hi & 0x8000)
6549	mv_hi = 0x8000 - mv_hi;
6550	#ifdef DEBUG_QOS
6551	hevc_print(hevc, 0, "[Picture %d Quality] MVY_L0 MAX : %d\n",
6552	pic_number, mv_hi);
6553	#endif
6554
6555	mv_lo = (rdata32>>0)&0xffff;
6556	if (mv_lo & 0x8000)
6557	mv_lo = 0x8000 - mv_lo;
6558	#ifdef DEBUG_QOS
6559	hevc_print(hevc, 0, "[Picture %d Quality] MVY_L0 MIN : %d\n",
6560	pic_number, mv_lo);
6561	#endif
6562
6563	/* {mvx_L1_max, mvx_L1_min} */
6564	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6565	mv_hi = (rdata32>>16)&0xffff;
6566	if (mv_hi & 0x8000)
6567	mv_hi = 0x8000 - mv_hi;
6568	#ifdef DEBUG_QOS
6569	hevc_print(hevc, 0, "[Picture %d Quality] MVX_L1 MAX : %d\n",
6570	pic_number, mv_hi);
6571	#endif
6572
6573	mv_lo = (rdata32>>0)&0xffff;
6574	if (mv_lo & 0x8000)
6575	mv_lo = 0x8000 - mv_lo;
6576	#ifdef DEBUG_QOS
6577	hevc_print(hevc, 0, "[Picture %d Quality] MVX_L1 MIN : %d\n",
6578	pic_number, mv_lo);
6579	#endif
6580
6581	/* {mvy_L1_max, mvy_L1_min} */
6582	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
6583	mv_hi = (rdata32>>16)&0xffff;
6584	if (mv_hi & 0x8000)
6585	mv_hi = 0x8000 - mv_hi;
6586	#ifdef DEBUG_QOS
6587	hevc_print(hevc, 0, "[Picture %d Quality] MVY_L1 MAX : %d\n",
6588	pic_number, mv_hi);
6589	#endif
6590	mv_lo = (rdata32>>0)&0xffff;
6591	if (mv_lo & 0x8000)
6592	mv_lo = 0x8000 - mv_lo;
6593	#ifdef DEBUG_QOS
6594	hevc_print(hevc, 0, "[Picture %d Quality] MVY_L1 MIN : %d\n",
6595	pic_number, mv_lo);
6596	#endif
6597
6598	rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
6599	#ifdef DEBUG_QOS
6600	hevc_print(hevc, 0,
6601	"[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
6602	pic_number, rdata32);
6603	#endif
6604	/* reset all counts */
6605	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
6606	}
6607	}
6608
6609	static int hevc_slice_segment_header_process(struct hevc_state_s *hevc,
6610	union param_u *rpm_param,
6611	int decode_pic_begin)
6612	{
6613	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6614	struct vdec_s *vdec = hw_to_vdec(hevc);
6615	#endif
6616	int i;
6617	int lcu_x_num_div;
6618	int lcu_y_num_div;
6619	int Col_ref;
6620	int dbg_skip_flag = 0;
6621
6622	if (hevc->wait_buf == 0) {
6623	hevc->sps_num_reorder_pics_0 =
6624	rpm_param->p.sps_num_reorder_pics_0;
6625	hevc->m_temporalId = rpm_param->p.m_temporalId;
6626	hevc->m_nalUnitType = rpm_param->p.m_nalUnitType;
6627	hevc->interlace_flag =
6628	(rpm_param->p.profile_etc >> 2) & 0x1;
6629	hevc->curr_pic_struct =
6630	(rpm_param->p.sei_frame_field_info >> 3) & 0xf;
6631	if (parser_sei_enable & 0x4) {
6632	hevc->frame_field_info_present_flag =
6633	(rpm_param->p.sei_frame_field_info >> 8) & 0x1;
6634	}
6635
6636	if (interlace_enable == 0 || hevc->m_ins_flag)
6637	hevc->interlace_flag = 0;
6638	if (interlace_enable & 0x100)
6639	hevc->interlace_flag = interlace_enable & 0x1;
6640	if (hevc->interlace_flag == 0)
6641	hevc->curr_pic_struct = 0;
6642	/* if(hevc->m_nalUnitType == NAL_UNIT_EOS){ */
6643	/*
6644	*hevc->m_pocRandomAccess = MAX_INT;
6645	* //add to fix RAP_B_Bossen_1
6646	*/
6647	/* } */
6648	hevc->misc_flag0 = rpm_param->p.misc_flag0;
6649	if (rpm_param->p.first_slice_segment_in_pic_flag == 0) {
6650	hevc->slice_segment_addr =
6651	rpm_param->p.slice_segment_address;
6652	if (!rpm_param->p.dependent_slice_segment_flag)
6653	hevc->slice_addr = hevc->slice_segment_addr;
6654	} else {
6655	hevc->slice_segment_addr = 0;
6656	hevc->slice_addr = 0;
6657	}
6658
6659	hevc->iPrevPOC = hevc->curr_POC;
6660	hevc->slice_type = (rpm_param->p.slice_type == I_SLICE) ? 2 :
6661	(rpm_param->p.slice_type == P_SLICE) ? 1 :
6662	(rpm_param->p.slice_type == B_SLICE) ? 0 : 3;
6663	/* hevc->curr_predFlag_L0=(hevc->slice_type==2) ? 0:1; */
6664	/* hevc->curr_predFlag_L1=(hevc->slice_type==0) ? 1:0; */
6665	hevc->TMVPFlag = rpm_param->p.slice_temporal_mvp_enable_flag;
6666	hevc->isNextSliceSegment =
6667	rpm_param->p.dependent_slice_segment_flag ? 1 : 0;
6668	if (hevc->pic_w != rpm_param->p.pic_width_in_luma_samples
6669	|| hevc->pic_h !=
6670	rpm_param->p.pic_height_in_luma_samples) {
6671	hevc_print(hevc, 0,
6672	"Pic Width/Height Change (%d,%d)=>(%d,%d), interlace %d\n",
6673	hevc->pic_w, hevc->pic_h,
6674	rpm_param->p.pic_width_in_luma_samples,
6675	rpm_param->p.pic_height_in_luma_samples,
6676	hevc->interlace_flag);
6677
6678	hevc->pic_w = rpm_param->p.pic_width_in_luma_samples;
6679	hevc->pic_h = rpm_param->p.pic_height_in_luma_samples;
6680	hevc->frame_width = hevc->pic_w;
6681	hevc->frame_height = hevc->pic_h;
6682	#ifdef LOSLESS_COMPRESS_MODE
6683	if (/*re_config_pic_flag == 0 &&*/
6684	(get_double_write_mode(hevc) & 0x10) == 0)
6685	init_decode_head_hw(hevc);
6686	#endif
6687	}
6688
6689	if (is_oversize(hevc->pic_w, hevc->pic_h)) {
6690	hevc_print(hevc, 0, "over size : %u x %u.\n",
6691	hevc->pic_w, hevc->pic_h);
6692	if ((!hevc->m_ins_flag) &&
6693	((debug &
6694	H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0))
6695	debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC |
6696	H265_DEBUG_DIS_SYS_ERROR_PROC);
6697	hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6698	return 3;
6699	}
6700	if (hevc->bit_depth_chroma > 10 ||
6701	hevc->bit_depth_luma > 10) {
6702	hevc_print(hevc, 0, "unsupport bitdepth : %u,%u\n",
6703	hevc->bit_depth_chroma,
6704	hevc->bit_depth_luma);
6705	if (!hevc->m_ins_flag)
6706	debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC |
6707	H265_DEBUG_DIS_SYS_ERROR_PROC);
6708	hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
6709	return 4;
6710	}
6711
6712	/* it will cause divide 0 error */
6713	if (hevc->pic_w == 0 || hevc->pic_h == 0) {
6714	if (get_dbg_flag(hevc)) {
6715	hevc_print(hevc, 0,
6716	"Fatal Error, pic_w = %d, pic_h = %d\n",
6717	hevc->pic_w, hevc->pic_h);
6718	}
6719	return 3;
6720	}
6721	pic_list_process(hevc);
6722
6723	hevc->lcu_size =
6724	1 << (rpm_param->p.log2_min_coding_block_size_minus3 +
6725	3 + rpm_param->
6726	p.log2_diff_max_min_coding_block_size);
6727	if (hevc->lcu_size == 0) {
6728	hevc_print(hevc, 0,
6729	"Error, lcu_size = 0 (%d,%d)\n",
6730	rpm_param->p.
6731	log2_min_coding_block_size_minus3,
6732	rpm_param->p.
6733	log2_diff_max_min_coding_block_size);
6734	return 3;
6735	}
6736	hevc->lcu_size_log2 = log2i(hevc->lcu_size);
6737	lcu_x_num_div = (hevc->pic_w / hevc->lcu_size);
6738	lcu_y_num_div = (hevc->pic_h / hevc->lcu_size);
6739	hevc->lcu_x_num =
6740	((hevc->pic_w % hevc->lcu_size) ==
6741	0) ? lcu_x_num_div : lcu_x_num_div + 1;
6742	hevc->lcu_y_num =
6743	((hevc->pic_h % hevc->lcu_size) ==
6744	0) ? lcu_y_num_div : lcu_y_num_div + 1;
6745	hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num;
6746
6747	if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_IDR
6748	|| hevc->m_nalUnitType ==
6749	NAL_UNIT_CODED_SLICE_IDR_N_LP) {
6750	hevc->curr_POC = 0;
6751	if ((hevc->m_temporalId - 1) == 0)
6752	hevc->iPrevTid0POC = hevc->curr_POC;
6753	} else {
6754	int iMaxPOClsb =
6755	1 << (rpm_param->p.
6756	log2_max_pic_order_cnt_lsb_minus4 + 4);
6757	int iPrevPOClsb;
6758	int iPrevPOCmsb;
6759	int iPOCmsb;
6760	int iPOClsb = rpm_param->p.POClsb;
6761
6762	if (iMaxPOClsb == 0) {
6763	hevc_print(hevc, 0,
6764	"error iMaxPOClsb is 0\n");
6765	return 3;
6766	}
6767
6768	iPrevPOClsb = hevc->iPrevTid0POC % iMaxPOClsb;
6769	iPrevPOCmsb = hevc->iPrevTid0POC - iPrevPOClsb;
6770
6771	if ((iPOClsb < iPrevPOClsb)
6772	&& ((iPrevPOClsb - iPOClsb) >=
6773	(iMaxPOClsb / 2)))
6774	iPOCmsb = iPrevPOCmsb + iMaxPOClsb;
6775	else if ((iPOClsb > iPrevPOClsb)
6776	&& ((iPOClsb - iPrevPOClsb) >
6777	(iMaxPOClsb / 2)))
6778	iPOCmsb = iPrevPOCmsb - iMaxPOClsb;
6779	else
6780	iPOCmsb = iPrevPOCmsb;
6781	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6782	hevc_print(hevc, 0,
6783	"iPrePOC%d iMaxPOClsb%d iPOCmsb%d iPOClsb%d\n",
6784	hevc->iPrevTid0POC, iMaxPOClsb, iPOCmsb,
6785	iPOClsb);
6786	}
6787	if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA
6788	|| hevc->m_nalUnitType ==
6789	NAL_UNIT_CODED_SLICE_BLANT
6790	|| hevc->m_nalUnitType ==
6791	NAL_UNIT_CODED_SLICE_BLA_N_LP) {
6792	/* For BLA picture types, POCmsb is set to 0. */
6793	iPOCmsb = 0;
6794	}
6795	hevc->curr_POC = (iPOCmsb + iPOClsb);
6796	if ((hevc->m_temporalId - 1) == 0)
6797	hevc->iPrevTid0POC = hevc->curr_POC;
6798	else {
6799	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
6800	hevc_print(hevc, 0,
6801	"m_temporalID is %d\n",
6802	hevc->m_temporalId);
6803	}
6804	}
6805	}
6806	hevc->RefNum_L0 =
6807	(rpm_param->p.num_ref_idx_l0_active >
6808	MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : rpm_param->p.
6809	num_ref_idx_l0_active;
6810	hevc->RefNum_L1 =
6811	(rpm_param->p.num_ref_idx_l1_active >
6812	MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : rpm_param->p.
6813	num_ref_idx_l1_active;
6814
6815	/* if(curr_POC==0x10) dump_lmem(); */
6816
6817	/* skip RASL pictures after CRA/BLA pictures */
6818	if (hevc->m_pocRandomAccess == MAX_INT) {/* first picture */
6819	if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_CRA ||
6820	hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA
6821	|| hevc->m_nalUnitType ==
6822	NAL_UNIT_CODED_SLICE_BLANT
6823	|| hevc->m_nalUnitType ==
6824	NAL_UNIT_CODED_SLICE_BLA_N_LP)
6825	hevc->m_pocRandomAccess = hevc->curr_POC;
6826	else
6827	hevc->m_pocRandomAccess = -MAX_INT;
6828	} else if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA
6829	|| hevc->m_nalUnitType ==
6830	NAL_UNIT_CODED_SLICE_BLANT
6831	|| hevc->m_nalUnitType ==
6832	NAL_UNIT_CODED_SLICE_BLA_N_LP)
6833	hevc->m_pocRandomAccess = hevc->curr_POC;
6834	else if ((hevc->curr_POC < hevc->m_pocRandomAccess) &&
6835	(nal_skip_policy >= 3) &&
6836	(hevc->m_nalUnitType ==
6837	NAL_UNIT_CODED_SLICE_RASL_N ||
6838	hevc->m_nalUnitType ==
6839	NAL_UNIT_CODED_SLICE_TFD)) { /* skip */
6840	if (get_dbg_flag(hevc)) {
6841	hevc_print(hevc, 0,
6842	"RASL picture with POC %d < %d ",
6843	hevc->curr_POC, hevc->m_pocRandomAccess);
6844	hevc_print(hevc, 0,
6845	"RandomAccess point POC), skip it\n");
6846	}
6847	return 1;
6848	}
6849
6850	WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) | 0x2);
6851	hevc->skip_flag = 0;
6852	/**/
6853	/* if((iPrevPOC != curr_POC)){ */
6854	if (rpm_param->p.slice_segment_address == 0) {
6855	struct PIC_s *pic;
6856
6857	hevc->new_pic = 1;
6858	#ifdef MULTI_INSTANCE_SUPPORT
6859	if (!hevc->m_ins_flag)
6860	#endif
6861	check_pic_decoded_error_pre(hevc,
6862	READ_VREG(HEVC_PARSER_LCU_START)
6863	& 0xffffff);
6864	/**/ if (use_cma == 0) {
6865	if (hevc->pic_list_init_flag == 0) {
6866	init_pic_list(hevc);
6867	init_pic_list_hw(hevc);
6868	init_buf_spec(hevc);
6869	hevc->pic_list_init_flag = 3;
6870	}
6871	}
6872	if (!hevc->m_ins_flag) {
6873	if (hevc->cur_pic)
6874	get_picture_qos_info(hevc);
6875	}
6876	hevc->first_pic_after_recover = 0;
6877	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE)
6878	dump_pic_list(hevc);
6879	/* prev pic */
6880	hevc_pre_pic(hevc, pic);
6881	/*
6882	*update referenced of old pictures
6883	*(cur_pic->referenced is 1 and not updated)
6884	*/
6885	apply_ref_pic_set(hevc, hevc->curr_POC,
6886	rpm_param);
6887
6888	if (hevc->mmu_enable)
6889	recycle_mmu_bufs(hevc);
6890
6891	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6892	if (vdec->master) {
6893	struct hevc_state_s *hevc_ba =
6894	(struct hevc_state_s *)
6895	vdec->master->private;
6896	if (hevc_ba->cur_pic != NULL) {
6897	hevc_ba->cur_pic->dv_enhance_exist = 1;
6898	hevc_print(hevc, H265_DEBUG_DV,
6899	"To decode el (poc %d) => set bl (poc %d) dv_enhance_exist flag\n",
6900	hevc->curr_POC, hevc_ba->cur_pic->POC);
6901	}
6902	}
6903	if (vdec->master == NULL &&
6904	vdec->slave == NULL)
6905	set_aux_data(hevc,
6906	hevc->cur_pic, 1, 0); /*suffix*/
6907	if (hevc->bypass_dvenl && !dolby_meta_with_el)
6908	set_aux_data(hevc,
6909	hevc->cur_pic, 0, 1); /*dv meta only*/
6910	#else
6911	set_aux_data(hevc, hevc->cur_pic, 1, 0);
6912	#endif
6913	/* new pic */
6914	hevc->cur_pic = get_new_pic(hevc, rpm_param);
6915	if (hevc->cur_pic == NULL) {
6916	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
6917	dump_pic_list(hevc);
6918	hevc->wait_buf = 1;
6919	return -1;
6920	}
6921	#ifdef MULTI_INSTANCE_SUPPORT
6922	hevc->decoding_pic = hevc->cur_pic;
6923	if (!hevc->m_ins_flag)
6924	hevc->over_decode = 0;
6925	#endif
6926	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6927	hevc->cur_pic->dv_enhance_exist = 0;
6928	if (vdec->slave)
6929	hevc_print(hevc, H265_DEBUG_DV,
6930	"Clear bl (poc %d) dv_enhance_exist flag\n",
6931	hevc->curr_POC);
6932	if (vdec->master == NULL &&
6933	vdec->slave == NULL)
6934	set_aux_data(hevc,
6935	hevc->cur_pic, 0, 0); /*prefix*/
6936
6937	if (hevc->bypass_dvenl && !dolby_meta_with_el)
6938	set_aux_data(hevc,
6939	hevc->cur_pic, 0, 2); /*pre sei only*/
6940	#else
6941	set_aux_data(hevc, hevc->cur_pic, 0, 0);
6942	#endif
6943	if (get_dbg_flag(hevc) & H265_DEBUG_DISPLAY_CUR_FRAME) {
6944	hevc->cur_pic->output_ready = 1;
6945	hevc->cur_pic->stream_offset =
6946	READ_VREG(HEVC_SHIFT_BYTE_COUNT);
6947	prepare_display_buf(hevc, hevc->cur_pic);
6948	hevc->wait_buf = 2;
6949	return -1;
6950	}
6951	} else {
6952	if (get_dbg_flag(hevc) & H265_DEBUG_HAS_AUX_IN_SLICE) {
6953	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6954	if (vdec->master == NULL &&
6955	vdec->slave == NULL) {
6956	set_aux_data(hevc, hevc->cur_pic, 1, 0);
6957	set_aux_data(hevc, hevc->cur_pic, 0, 0);
6958	}
6959	#else
6960	set_aux_data(hevc, hevc->cur_pic, 1, 0);
6961	set_aux_data(hevc, hevc->cur_pic, 0, 0);
6962	#endif
6963	}
6964	if (hevc->pic_list_init_flag != 3
6965	|| hevc->cur_pic == NULL) {
6966	/* make it dec from the first slice segment */
6967	return 3;
6968	}
6969	hevc->cur_pic->slice_idx++;
6970	hevc->new_pic = 0;
6971	}
6972	} else {
6973	if (hevc->wait_buf == 1) {
6974	pic_list_process(hevc);
6975	hevc->cur_pic = get_new_pic(hevc, rpm_param);
6976	if (hevc->cur_pic == NULL)
6977	return -1;
6978
6979	if (!hevc->m_ins_flag)
6980	hevc->over_decode = 0;
6981
6982	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
6983	hevc->cur_pic->dv_enhance_exist = 0;
6984	if (vdec->master == NULL &&
6985	vdec->slave == NULL)
6986	set_aux_data(hevc, hevc->cur_pic, 0, 0);
6987	#else
6988	set_aux_data(hevc, hevc->cur_pic, 0, 0);
6989	#endif
6990	hevc->wait_buf = 0;
6991	} else if (hevc->wait_buf ==
6992	2) {
6993	if (get_display_pic_num(hevc) >
6994	1)
6995	return -1;
6996	hevc->wait_buf = 0;
6997	}
6998	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE)
6999	dump_pic_list(hevc);
7000	}
7001
7002	if (hevc->new_pic) {
7003	#if 1
7004	/*SUPPORT_10BIT*/
7005	int sao_mem_unit =
7006	(hevc->lcu_size == 16 ? 9 :
7007	hevc->lcu_size ==
7008	32 ? 14 : 24) << 4;
7009	#else
7010	int sao_mem_unit = ((hevc->lcu_size / 8) * 2 + 4) << 4;
7011	#endif
7012	int pic_height_cu =
7013	(hevc->pic_h + hevc->lcu_size - 1) / hevc->lcu_size;
7014	int pic_width_cu =
7015	(hevc->pic_w + hevc->lcu_size - 1) / hevc->lcu_size;
7016	int sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
7017
7018	/* int sao_abv_size = sao_mem_unit*pic_width_cu; */
7019	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
7020	hevc_print(hevc, 0,
7021	"==>%s dec idx %d, struct %d interlace %d pic idx %d\n",
7022	__func__,
7023	hevc->decode_idx,
7024	hevc->curr_pic_struct,
7025	hevc->interlace_flag,
7026	hevc->cur_pic->index);
7027	}
7028	if (dbg_skip_decode_index != 0 &&
7029	hevc->decode_idx == dbg_skip_decode_index)
7030	dbg_skip_flag = 1;
7031
7032	hevc->decode_idx++;
7033	update_tile_info(hevc, pic_width_cu, pic_height_cu,
7034	sao_mem_unit, rpm_param);
7035
7036	config_title_hw(hevc, sao_vb_size, sao_mem_unit);
7037	}
7038
7039	if (hevc->iPrevPOC != hevc->curr_POC) {
7040	hevc->new_tile = 1;
7041	hevc->tile_x = 0;
7042	hevc->tile_y = 0;
7043	hevc->tile_y_x = 0;
7044	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
7045	hevc_print(hevc, 0,
7046	"new_tile (new_pic) tile_x=%d, tile_y=%d\n",
7047	hevc->tile_x, hevc->tile_y);
7048	}
7049	} else if (hevc->tile_enabled) {
7050	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
7051	hevc_print(hevc, 0,
7052	"slice_segment_address is %d\n",
7053	rpm_param->p.slice_segment_address);
7054	}
7055	hevc->tile_y_x =
7056	get_tile_index(hevc, rpm_param->p.slice_segment_address,
7057	(hevc->pic_w +
7058	hevc->lcu_size -
7059	1) / hevc->lcu_size);
7060	if ((hevc->tile_y_x != (hevc->tile_x | (hevc->tile_y << 8)))
7061	&& (hevc->tile_y_x != -1)) {
7062	hevc->new_tile = 1;
7063	hevc->tile_x = hevc->tile_y_x & 0xff;
7064	hevc->tile_y = (hevc->tile_y_x >> 8) & 0xff;
7065	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
7066	hevc_print(hevc, 0,
7067	"new_tile seg adr %d tile_x=%d, tile_y=%d\n",
7068	rpm_param->p.slice_segment_address,
7069	hevc->tile_x, hevc->tile_y);
7070	}
7071	} else
7072	hevc->new_tile = 0;
7073	} else
7074	hevc->new_tile = 0;
7075
7076	if ((hevc->tile_x > (MAX_TILE_COL_NUM - 1))
7077	|| (hevc->tile_y > (MAX_TILE_ROW_NUM - 1)))
7078	hevc->new_tile = 0;
7079
7080	if (hevc->new_tile) {
7081	hevc->tile_start_lcu_x =
7082	hevc->m_tile[hevc->tile_y][hevc->tile_x].start_cu_x;
7083	hevc->tile_start_lcu_y =
7084	hevc->m_tile[hevc->tile_y][hevc->tile_x].start_cu_y;
7085	hevc->tile_width_lcu =
7086	hevc->m_tile[hevc->tile_y][hevc->tile_x].width;
7087	hevc->tile_height_lcu =
7088	hevc->m_tile[hevc->tile_y][hevc->tile_x].height;
7089	}
7090
7091	set_ref_pic_list(hevc, rpm_param);
7092
7093	Col_ref = rpm_param->p.collocated_ref_idx;
7094
7095	hevc->LDCFlag = 0;
7096	if (rpm_param->p.slice_type != I_SLICE) {
7097	hevc->LDCFlag = 1;
7098	for (i = 0; (i < hevc->RefNum_L0) && hevc->LDCFlag; i++) {
7099	if (hevc->cur_pic->
7100	m_aiRefPOCList0[hevc->cur_pic->slice_idx][i] >
7101	hevc->curr_POC)
7102	hevc->LDCFlag = 0;
7103	}
7104	if (rpm_param->p.slice_type == B_SLICE) {
7105	for (i = 0; (i < hevc->RefNum_L1)
7106	&& hevc->LDCFlag; i++) {
7107	if (hevc->cur_pic->
7108	m_aiRefPOCList1[hevc->cur_pic->
7109	slice_idx][i] >
7110	hevc->curr_POC)
7111	hevc->LDCFlag = 0;
7112	}
7113	}
7114	}
7115
7116	hevc->ColFromL0Flag = rpm_param->p.collocated_from_l0_flag;
7117
7118	hevc->plevel =
7119	rpm_param->p.log2_parallel_merge_level;
7120	hevc->MaxNumMergeCand = 5 - rpm_param->p.five_minus_max_num_merge_cand;
7121
7122	hevc->LongTerm_Curr = 0; /* to do ... */
7123	hevc->LongTerm_Col = 0; /* to do ... */
7124
7125	hevc->list_no = 0;
7126	if (rpm_param->p.slice_type == B_SLICE)
7127	hevc->list_no = 1 - hevc->ColFromL0Flag;
7128	if (hevc->list_no == 0) {
7129	if (Col_ref < hevc->RefNum_L0) {
7130	hevc->Col_POC =
7131	hevc->cur_pic->m_aiRefPOCList0[hevc->cur_pic->
7132	slice_idx][Col_ref];
7133	} else
7134	hevc->Col_POC = INVALID_POC;
7135	} else {
7136	if (Col_ref < hevc->RefNum_L1) {
7137	hevc->Col_POC =
7138	hevc->cur_pic->m_aiRefPOCList1[hevc->cur_pic->
7139	slice_idx][Col_ref];
7140	} else
7141	hevc->Col_POC = INVALID_POC;
7142	}
7143
7144	hevc->LongTerm_Ref = 0; /* to do ... */
7145
7146	if (hevc->slice_type != 2) {
7147	/* if(hevc->i_only==1){ */
7148	/* return 0xf; */
7149	/* } */
7150
7151	if (hevc->Col_POC != INVALID_POC) {
7152	hevc->col_pic = get_ref_pic_by_POC(hevc, hevc->Col_POC);
7153	if (hevc->col_pic == NULL) {
7154	hevc->cur_pic->error_mark = 1;
7155	if (get_dbg_flag(hevc)) {
7156	hevc_print(hevc, 0,
7157	"WRONG,fail to get the pic Col_POC\n");
7158	}
7159	if (is_log_enable(hevc))
7160	add_log(hevc,
7161	"WRONG,fail to get the pic Col_POC");
7162	} else if (hevc->col_pic->error_mark || hevc->col_pic->dis_mark == 0) {
7163	hevc->cur_pic->error_mark = 1;
7164	if (get_dbg_flag(hevc)) {
7165	hevc_print(hevc, 0,
7166	"WRONG, Col_POC error_mark is 1\n");
7167	}
7168	if (is_log_enable(hevc))
7169	add_log(hevc,
7170	"WRONG, Col_POC error_mark is 1");
7171	} else {
7172	if ((hevc->col_pic->width
7173	!= hevc->pic_w) ||
7174	(hevc->col_pic->height
7175	!= hevc->pic_h)) {
7176	hevc_print(hevc, 0,
7177	"Wrong reference pic (poc %d) width/height %d/%d\n",
7178	hevc->col_pic->POC,
7179	hevc->col_pic->width,
7180	hevc->col_pic->height);
7181	hevc->cur_pic->error_mark = 1;
7182	}
7183
7184	}
7185
7186	if (hevc->cur_pic->error_mark
7187	&& ((hevc->ignore_bufmgr_error & 0x1) == 0)) {
7188	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7189	/*count info*/
7190	vdec_count_info(gvs, hevc->cur_pic->error_mark,
7191	hevc->cur_pic->stream_offset);
7192	#endif
7193	}
7194
7195	if (is_skip_decoding(hevc,
7196	hevc->cur_pic)) {
7197	return 2;
7198	}
7199	} else
7200	hevc->col_pic = hevc->cur_pic;
7201	} /* */
7202	if (hevc->col_pic == NULL)
7203	hevc->col_pic = hevc->cur_pic;
7204	#ifdef BUFFER_MGR_ONLY
7205	return 0xf;
7206	#else
7207	if ((decode_pic_begin > 0 && hevc->decode_idx <= decode_pic_begin)
7208	|| (dbg_skip_flag))
7209	return 0xf;
7210	#endif
7211
7212	config_mc_buffer(hevc, hevc->cur_pic);
7213
7214	if (is_skip_decoding(hevc,
7215	hevc->cur_pic)) {
7216	if (get_dbg_flag(hevc))
7217	hevc_print(hevc, 0,
7218	"Discard this picture index %d\n",
7219	hevc->cur_pic->index);
7220	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7221	/*count info*/
7222	vdec_count_info(gvs, hevc->cur_pic->error_mark,
7223	hevc->cur_pic->stream_offset);
7224	#endif
7225	return 2;
7226	}
7227	#ifdef MCRCC_ENABLE
7228	config_mcrcc_axi_hw(hevc, hevc->cur_pic->slice_type);
7229	#endif
7230	config_mpred_hw(hevc);
7231
7232	config_sao_hw(hevc, rpm_param);
7233
7234	if ((hevc->slice_type != 2) && (hevc->i_only & 0x2))
7235	return 0xf;
7236
7237	return 0;
7238	}
7239
7240
7241
7242	static int H265_alloc_mmu(struct hevc_state_s *hevc, struct PIC_s *new_pic,
7243	unsigned short bit_depth, unsigned int *mmu_index_adr) {
7244	int cur_buf_idx = new_pic->index;
7245	int bit_depth_10 = (bit_depth != 0x00);
7246	int picture_size;
7247	int cur_mmu_4k_number;
7248	int ret, max_frame_num;
7249	picture_size = compute_losless_comp_body_size(hevc, new_pic->width,
7250	new_pic->height, !bit_depth_10);
7251	cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
7252	if (hevc->double_write_mode & 0x10)
7253	return 0;
7254	/*hevc_print(hevc, 0,
7255	"alloc_mmu cur_idx : %d picture_size : %d mmu_4k_number : %d\r\n",
7256	cur_buf_idx, picture_size, cur_mmu_4k_number);*/
7257	if (new_pic->scatter_alloc) {
7258	decoder_mmu_box_free_idx(hevc->mmu_box, new_pic->index);
7259	new_pic->scatter_alloc = 0;
7260	}
7261	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7262	max_frame_num = MAX_FRAME_8K_NUM;
7263	else
7264	max_frame_num = MAX_FRAME_4K_NUM;
7265	if (cur_mmu_4k_number > max_frame_num) {
7266	hevc_print(hevc, 0, "over max !! 0x%x width %d height %d\n",
7267	cur_mmu_4k_number,
7268	new_pic->width,
7269	new_pic->height);
7270	return -1;
7271	}
7272	ret = decoder_mmu_box_alloc_idx(
7273	hevc->mmu_box,
7274	cur_buf_idx,
7275	cur_mmu_4k_number,
7276	mmu_index_adr);
7277	if (ret == 0)
7278	new_pic->scatter_alloc = 1;
7279
7280	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
7281	"%s pic index %d page count(%d) ret =%d\n",
7282	__func__, cur_buf_idx,
7283	cur_mmu_4k_number, ret);
7284	return ret;
7285	}
7286
7287
7288	static void release_pic_mmu_buf(struct hevc_state_s *hevc,
7289	struct PIC_s *pic)
7290	{
7291	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
7292	"%s pic index %d scatter_alloc %d\n",
7293	__func__, pic->index,
7294	pic->scatter_alloc);
7295
7296	if (hevc->mmu_enable
7297	&& ((hevc->double_write_mode & 0x10) == 0)
7298	&& pic->scatter_alloc)
7299	decoder_mmu_box_free_idx(hevc->mmu_box, pic->index);
7300	pic->scatter_alloc = 0;
7301	}
7302
7303	/*
7304	*************************************************
7305	*
7306	*h265 buffer management end
7307	*
7308	**************************************************
7309	*/
7310	static struct hevc_state_s *gHevc;
7311
7312	static void hevc_local_uninit(struct hevc_state_s *hevc)
7313	{
7314	hevc->rpm_ptr = NULL;
7315	hevc->lmem_ptr = NULL;
7316
7317	#ifdef SWAP_HEVC_UCODE
7318	if (hevc->is_swap && get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
7319	if (hevc->mc_cpu_addr != NULL) {
7320	dma_free_coherent(amports_get_dma_device(),
7321	hevc->swap_size, hevc->mc_cpu_addr,
7322	hevc->mc_dma_handle);
7323	hevc->mc_cpu_addr = NULL;
7324	}
7325
7326	}
7327	#endif
7328	#ifdef DETREFILL_ENABLE
7329	if (hevc->is_swap && get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
7330	uninit_detrefill_buf(hevc);
7331	#endif
7332	if (hevc->aux_addr) {
7333	dma_free_coherent(amports_get_dma_device(),
7334	hevc->prefix_aux_size + hevc->suffix_aux_size, hevc->aux_addr,
7335	hevc->aux_phy_addr);
7336	hevc->aux_addr = NULL;
7337	}
7338	if (hevc->rpm_addr) {
7339	dma_free_coherent(amports_get_dma_device(),
7340	RPM_BUF_SIZE, hevc->rpm_addr,
7341	hevc->rpm_phy_addr);
7342	hevc->rpm_addr = NULL;
7343	}
7344	if (hevc->lmem_addr) {
7345	dma_free_coherent(amports_get_dma_device(),
7346	RPM_BUF_SIZE, hevc->lmem_addr,
7347	hevc->lmem_phy_addr);
7348	hevc->lmem_addr = NULL;
7349	}
7350
7351	if (hevc->mmu_enable && hevc->frame_mmu_map_addr) {
7352	if (hevc->frame_mmu_map_phy_addr)
7353	dma_free_coherent(amports_get_dma_device(),
7354	get_frame_mmu_map_size(), hevc->frame_mmu_map_addr,
7355	hevc->frame_mmu_map_phy_addr);
7356
7357	hevc->frame_mmu_map_addr = NULL;
7358	}
7359
7360	kfree(gvs);
7361	gvs = NULL;
7362	}
7363
7364	static int hevc_local_init(struct hevc_state_s *hevc)
7365	{
7366	int ret = -1;
7367	struct BuffInfo_s *cur_buf_info = NULL;
7368
7369	memset(&hevc->param, 0, sizeof(union param_u));
7370
7371	cur_buf_info = &hevc->work_space_buf_store;
7372
7373	if (vdec_is_support_4k()) {
7374	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
7375	memcpy(cur_buf_info, &amvh265_workbuff_spec[2], /* 4k */
7376	sizeof(struct BuffInfo_s));
7377	else
7378	memcpy(cur_buf_info, &amvh265_workbuff_spec[1], /* 4k */
7379	sizeof(struct BuffInfo_s));
7380	} else
7381	memcpy(cur_buf_info, &amvh265_workbuff_spec[0], /* 1080p */
7382	sizeof(struct BuffInfo_s));
7383
7384	cur_buf_info->start_adr = hevc->buf_start;
7385	init_buff_spec(hevc, cur_buf_info);
7386
7387	hevc_init_stru(hevc, cur_buf_info);
7388
7389	hevc->bit_depth_luma = 8;
7390	hevc->bit_depth_chroma = 8;
7391	hevc->video_signal_type = 0;
7392	hevc->video_signal_type_debug = 0;
7393	bit_depth_luma = hevc->bit_depth_luma;
7394	bit_depth_chroma = hevc->bit_depth_chroma;
7395	video_signal_type = hevc->video_signal_type;
7396
7397	if ((get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) == 0) {
7398	hevc->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
7399	RPM_BUF_SIZE, &hevc->rpm_phy_addr, GFP_KERNEL);
7400	if (hevc->rpm_addr == NULL) {
7401	pr_err("%s: failed to alloc rpm buffer\n", __func__);
7402	return -1;
7403	}
7404	hevc->rpm_ptr = hevc->rpm_addr;
7405	}
7406
7407	if (prefix_aux_buf_size > 0 ||
7408	suffix_aux_buf_size > 0) {
7409	u32 aux_buf_size;
7410
7411	hevc->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size);
7412	hevc->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size);
7413	aux_buf_size = hevc->prefix_aux_size + hevc->suffix_aux_size;
7414	hevc->aux_addr =dma_alloc_coherent(amports_get_dma_device(),
7415	aux_buf_size, &hevc->aux_phy_addr, GFP_KERNEL);
7416	if (hevc->aux_addr == NULL) {
7417	pr_err("%s: failed to alloc rpm buffer\n", __func__);
7418	return -1;
7419	}
7420	}
7421
7422	hevc->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
7423	LMEM_BUF_SIZE, &hevc->lmem_phy_addr, GFP_KERNEL);
7424	if (hevc->lmem_addr == NULL) {
7425	pr_err("%s: failed to alloc lmem buffer\n", __func__);
7426	return -1;
7427	}
7428	hevc->lmem_ptr = hevc->lmem_addr;
7429
7430	if (hevc->mmu_enable) {
7431	hevc->frame_mmu_map_addr =
7432	dma_alloc_coherent(amports_get_dma_device(),
7433	get_frame_mmu_map_size(),
7434	&hevc->frame_mmu_map_phy_addr, GFP_KERNEL);
7435	if (hevc->frame_mmu_map_addr == NULL) {
7436	pr_err("%s: failed to alloc count_buffer\n", __func__);
7437	return -1;
7438	}
7439	memset(hevc->frame_mmu_map_addr, 0, get_frame_mmu_map_size());
7440	}
7441	ret = 0;
7442	return ret;
7443	}
7444
7445	/*
7446	*******************************************
7447	* Mailbox command
7448	*******************************************
7449	*/
7450	#define CMD_FINISHED 0
7451	#define CMD_ALLOC_VIEW 1
7452	#define CMD_FRAME_DISPLAY 3
7453	#define CMD_DEBUG 10
7454
7455
7456	#define DECODE_BUFFER_NUM_MAX 32
7457	#define DISPLAY_BUFFER_NUM 6
7458
7459	#define video_domain_addr(adr) (adr&0x7fffffff)
7460	#define DECODER_WORK_SPACE_SIZE 0x800000
7461
7462	#define spec2canvas(x) \
7463	(((x)->uv_canvas_index << 16) | \
7464	((x)->uv_canvas_index << 8) | \
7465	((x)->y_canvas_index << 0))
7466
7467
7468	static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic)
7469	{
7470	struct vdec_s *vdec = hw_to_vdec(hevc);
7471	int canvas_w = ALIGN(pic->width, 64)/4;
7472	int canvas_h = ALIGN(pic->height, 32)/4;
7473	int blkmode = mem_map_mode;
7474
7475	/*CANVAS_BLKMODE_64X32*/
7476	#ifdef SUPPORT_10BIT
7477	if (pic->double_write_mode) {
7478	canvas_w = pic->width /
7479	get_double_write_ratio(hevc, pic->double_write_mode);
7480	canvas_h = pic->height /
7481	get_double_write_ratio(hevc, pic->double_write_mode);
7482
7483	if (mem_map_mode == 0)
7484	canvas_w = ALIGN(canvas_w, 32);
7485	else
7486	canvas_w = ALIGN(canvas_w, 64);
7487	canvas_h = ALIGN(canvas_h, 32);
7488
7489	if (vdec->parallel_dec == 1) {
7490	if (pic->y_canvas_index == -1)
7491	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7492	if (pic->uv_canvas_index == -1)
7493	pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7494	} else {
7495	pic->y_canvas_index = 128 + pic->index * 2;
7496	pic->uv_canvas_index = 128 + pic->index * 2 + 1;
7497	}
7498
7499	canvas_config_ex(pic->y_canvas_index,
7500	pic->dw_y_adr, canvas_w, canvas_h,
7501	CANVAS_ADDR_NOWRAP, blkmode, hevc->is_used_v4l ? 0 : 7);
7502	canvas_config_ex(pic->uv_canvas_index, pic->dw_u_v_adr,
7503	canvas_w, canvas_h,
7504	CANVAS_ADDR_NOWRAP, blkmode, hevc->is_used_v4l ? 0 : 7);
7505	#ifdef MULTI_INSTANCE_SUPPORT
7506	pic->canvas_config[0].phy_addr =
7507	pic->dw_y_adr;
7508	pic->canvas_config[0].width =
7509	canvas_w;
7510	pic->canvas_config[0].height =
7511	canvas_h;
7512	pic->canvas_config[0].block_mode =
7513	blkmode;
7514	pic->canvas_config[0].endian = hevc->is_used_v4l ? 0 : 7;
7515
7516	pic->canvas_config[1].phy_addr =
7517	pic->dw_u_v_adr;
7518	pic->canvas_config[1].width =
7519	canvas_w;
7520	pic->canvas_config[1].height =
7521	canvas_h;
7522	pic->canvas_config[1].block_mode =
7523	blkmode;
7524	pic->canvas_config[1].endian = hevc->is_used_v4l ? 0 : 7;
7525	#endif
7526	} else {
7527	if (!hevc->mmu_enable) {
7528	/* to change after 10bit VPU is ready ... */
7529	if (vdec->parallel_dec == 1) {
7530	if (pic->y_canvas_index == -1)
7531	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7532	pic->uv_canvas_index = pic->y_canvas_index;
7533	} else {
7534	pic->y_canvas_index = 128 + pic->index;
7535	pic->uv_canvas_index = 128 + pic->index;
7536	}
7537
7538	canvas_config_ex(pic->y_canvas_index,
7539	pic->mc_y_adr, canvas_w, canvas_h,
7540	CANVAS_ADDR_NOWRAP, blkmode, hevc->is_used_v4l ? 0 : 7);
7541	canvas_config_ex(pic->uv_canvas_index, pic->mc_u_v_adr,
7542	canvas_w, canvas_h,
7543	CANVAS_ADDR_NOWRAP, blkmode, hevc->is_used_v4l ? 0 : 7);
7544	}
7545	}
7546	#else
7547	if (vdec->parallel_dec == 1) {
7548	if (pic->y_canvas_index == -1)
7549	pic->y_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7550	if (pic->uv_canvas_index == -1)
7551	pic->uv_canvas_index = vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
7552	} else {
7553	pic->y_canvas_index = 128 + pic->index * 2;
7554	pic->uv_canvas_index = 128 + pic->index * 2 + 1;
7555	}
7556
7557
7558	canvas_config_ex(pic->y_canvas_index, pic->mc_y_adr, canvas_w, canvas_h,
7559	CANVAS_ADDR_NOWRAP, blkmode, hevc->is_used_v4l ? 0 : 7);
7560	canvas_config_ex(pic->uv_canvas_index, pic->mc_u_v_adr,
7561	canvas_w, canvas_h,
7562	CANVAS_ADDR_NOWRAP, blkmode, hevc->is_used_v4l ? 0 : 7);
7563	#endif
7564	}
7565
7566	static int init_buf_spec(struct hevc_state_s *hevc)
7567	{
7568	int pic_width = hevc->pic_w;
7569	int pic_height = hevc->pic_h;
7570
7571	/* hevc_print(hevc, 0,
7572	*"%s1: %d %d\n", __func__, hevc->pic_w, hevc->pic_h);
7573	*/
7574	hevc_print(hevc, 0,
7575	"%s2 %d %d\n", __func__, pic_width, pic_height);
7576	/* pic_width = hevc->pic_w; */
7577	/* pic_height = hevc->pic_h; */
7578
7579	if (hevc->frame_width == 0 || hevc->frame_height == 0) {
7580	hevc->frame_width = pic_width;
7581	hevc->frame_height = pic_height;
7582
7583	}
7584
7585	return 0;
7586	}
7587
7588	static int parse_sei(struct hevc_state_s *hevc,
7589	struct PIC_s *pic, char *sei_buf, uint32_t size)
7590	{
7591	char *p = sei_buf;
7592	char *p_sei;
7593	uint16_t header;
7594	uint8_t nal_unit_type;
7595	uint8_t payload_type, payload_size;
7596	int i, j;
7597
7598	if (size < 2)
7599	return 0;
7600	header = *p++;
7601	header <<= 8;
7602	header += *p++;
7603	nal_unit_type = header >> 9;
7604	if ((nal_unit_type != NAL_UNIT_SEI)
7605	&& (nal_unit_type != NAL_UNIT_SEI_SUFFIX))
7606	return 0;
7607	while (p+2 <= sei_buf+size) {
7608	payload_type = *p++;
7609	payload_size = *p++;
7610	if (p+payload_size <= sei_buf+size) {
7611	switch (payload_type) {
7612	case SEI_PicTiming:
7613	if ((parser_sei_enable & 0x4) &&
7614	hevc->frame_field_info_present_flag) {
7615	p_sei = p;
7616	hevc->curr_pic_struct = (*p_sei >> 4)&0x0f;
7617	pic->pic_struct = hevc->curr_pic_struct;
7618	if (get_dbg_flag(hevc) &
7619	H265_DEBUG_PIC_STRUCT) {
7620	hevc_print(hevc, 0,
7621	"parse result pic_struct = %d\n",
7622	hevc->curr_pic_struct);
7623	}
7624	}
7625	break;
7626	case SEI_UserDataITU_T_T35:
7627	p_sei = p;
7628	if (p_sei[0] == 0xB5
7629	&& p_sei[1] == 0x00
7630	&& p_sei[2] == 0x3C
7631	&& p_sei[3] == 0x00
7632	&& p_sei[4] == 0x01
7633	&& p_sei[5] == 0x04)
7634	hevc->sei_present_flag |= SEI_HDR10PLUS_MASK;
7635
7636	break;
7637	case SEI_MasteringDisplayColorVolume:
7638	/*hevc_print(hevc, 0,
7639	"sei type: primary display color volume %d, size %d\n",
7640	payload_type,
7641	payload_size);*/
7642	/* master_display_colour */
7643	p_sei = p;
7644	for (i = 0; i < 3; i++) {
7645	for (j = 0; j < 2; j++) {
7646	hevc->primaries[i][j]
7647	= (*p_sei<<8)
7648	| *(p_sei+1);
7649	p_sei += 2;
7650	}
7651	}
7652	for (i = 0; i < 2; i++) {
7653	hevc->white_point[i]
7654	= (*p_sei<<8)
7655	| *(p_sei+1);
7656	p_sei += 2;
7657	}
7658	for (i = 0; i < 2; i++) {
7659	hevc->luminance[i]
7660	= (*p_sei<<24)
7661	| (*(p_sei+1)<<16)
7662	| (*(p_sei+2)<<8)
7663	| *(p_sei+3);
7664	p_sei += 4;
7665	}
7666	hevc->sei_present_flag |=
7667	SEI_MASTER_DISPLAY_COLOR_MASK;
7668	/*for (i = 0; i < 3; i++)
7669	for (j = 0; j < 2; j++)
7670	hevc_print(hevc, 0,
7671	"\tprimaries[%1d][%1d] = %04x\n",
7672	i, j,
7673	hevc->primaries[i][j]);
7674	hevc_print(hevc, 0,
7675	"\twhite_point = (%04x, %04x)\n",
7676	hevc->white_point[0],
7677	hevc->white_point[1]);
7678	hevc_print(hevc, 0,
7679	"\tmax,min luminance = %08x, %08x\n",
7680	hevc->luminance[0],
7681	hevc->luminance[1]);*/
7682	break;
7683	case SEI_ContentLightLevel:
7684	if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
7685	hevc_print(hevc, 0,
7686	"sei type: max content light level %d, size %d\n",
7687	payload_type, payload_size);
7688	/* content_light_level */
7689	p_sei = p;
7690	hevc->content_light_level[0]
7691	= (*p_sei<<8) | *(p_sei+1);
7692	p_sei += 2;
7693	hevc->content_light_level[1]
7694	= (*p_sei<<8) | *(p_sei+1);
7695	p_sei += 2;
7696	hevc->sei_present_flag |=
7697	SEI_CONTENT_LIGHT_LEVEL_MASK;
7698	if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
7699	hevc_print(hevc, 0,
7700	"\tmax cll = %04x, max_pa_cll = %04x\n",
7701	hevc->content_light_level[0],
7702	hevc->content_light_level[1]);
7703	break;
7704	default:
7705	break;
7706	}
7707	}
7708	p += payload_size;
7709	}
7710	return 0;
7711	}
7712
7713	static unsigned calc_ar(unsigned idc, unsigned sar_w, unsigned sar_h,
7714	unsigned w, unsigned h)
7715	{
7716	unsigned ar;
7717
7718	if (idc == 255) {
7719	ar = div_u64(256ULL * sar_h * h,
7720	sar_w * w);
7721	} else {
7722	switch (idc) {
7723	case 1:
7724	ar = 0x100 * h / w;
7725	break;
7726	case 2:
7727	ar = 0x100 * h * 11 / (w * 12);
7728	break;
7729	case 3:
7730	ar = 0x100 * h * 11 / (w * 10);
7731	break;
7732	case 4:
7733	ar = 0x100 * h * 11 / (w * 16);
7734	break;
7735	case 5:
7736	ar = 0x100 * h * 33 / (w * 40);
7737	break;
7738	case 6:
7739	ar = 0x100 * h * 11 / (w * 24);
7740	break;
7741	case 7:
7742	ar = 0x100 * h * 11 / (w * 20);
7743	break;
7744	case 8:
7745	ar = 0x100 * h * 11 / (w * 32);
7746	break;
7747	case 9:
7748	ar = 0x100 * h * 33 / (w * 80);
7749	break;
7750	case 10:
7751	ar = 0x100 * h * 11 / (w * 18);
7752	break;
7753	case 11:
7754	ar = 0x100 * h * 11 / (w * 15);
7755	break;
7756	case 12:
7757	ar = 0x100 * h * 33 / (w * 64);
7758	break;
7759	case 13:
7760	ar = 0x100 * h * 99 / (w * 160);
7761	break;
7762	case 14:
7763	ar = 0x100 * h * 3 / (w * 4);
7764	break;
7765	case 15:
7766	ar = 0x100 * h * 2 / (w * 3);
7767	break;
7768	case 16:
7769	ar = 0x100 * h * 1 / (w * 2);
7770	break;
7771	default:
7772	ar = h * 0x100 / w;
7773	break;
7774	}
7775	}
7776
7777	return ar;
7778	}
7779
7780	static void set_frame_info(struct hevc_state_s *hevc, struct vframe_s *vf,
7781	struct PIC_s *pic)
7782	{
7783	unsigned int ar;
7784	int i, j;
7785	char *p;
7786	unsigned size = 0;
7787	unsigned type = 0;
7788	struct vframe_master_display_colour_s *vf_dp
7789	= &vf->prop.master_display_colour;
7790
7791	vf->width = pic->width /
7792	get_double_write_ratio(hevc, pic->double_write_mode);
7793	vf->height = pic->height /
7794	get_double_write_ratio(hevc, pic->double_write_mode);
7795
7796	vf->duration = hevc->frame_dur;
7797	vf->duration_pulldown = 0;
7798	vf->flag = 0;
7799
7800	ar = min_t(u32, hevc->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
7801	vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
7802
7803
7804	if (((pic->aspect_ratio_idc == 255) &&
7805	pic->sar_width &&
7806	pic->sar_height) ||
7807	((pic->aspect_ratio_idc != 255) &&
7808	(pic->width))) {
7809	ar = min_t(u32,
7810	calc_ar(pic->aspect_ratio_idc,
7811	pic->sar_width,
7812	pic->sar_height,
7813	pic->width,
7814	pic->height),
7815	DISP_RATIO_ASPECT_RATIO_MAX);
7816	vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
7817	}
7818	hevc->ratio_control = vf->ratio_control;
7819	if (pic->aux_data_buf
7820	&& pic->aux_data_size) {
7821	/* parser sei */
7822	p = pic->aux_data_buf;
7823	while (p < pic->aux_data_buf
7824	+ pic->aux_data_size - 8) {
7825	size = *p++;
7826	size = (size << 8) | *p++;
7827	size = (size << 8) | *p++;
7828	size = (size << 8) | *p++;
7829	type = *p++;
7830	type = (type << 8) | *p++;
7831	type = (type << 8) | *p++;
7832	type = (type << 8) | *p++;
7833	if (type == 0x02000000) {
7834	/* hevc_print(hevc, 0,
7835	"sei(%d)\n", size); */
7836	parse_sei(hevc, pic, p, size);
7837	}
7838	p += size;
7839	}
7840	}
7841	if (hevc->video_signal_type & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) {
7842	vf->signal_type = pic->video_signal_type;
7843	if (hevc->sei_present_flag & SEI_HDR10PLUS_MASK) {
7844	u32 data;
7845	data = vf->signal_type;
7846	data = data & 0xFFFF00FF;
7847	data = data | (0x30<<8);
7848	vf->signal_type = data;
7849	}
7850	}
7851	else
7852	vf->signal_type = 0;
7853	hevc->video_signal_type_debug = vf->signal_type;
7854
7855	/* master_display_colour */
7856	if (hevc->sei_present_flag & SEI_MASTER_DISPLAY_COLOR_MASK) {
7857	for (i = 0; i < 3; i++)
7858	for (j = 0; j < 2; j++)
7859	vf_dp->primaries[i][j] = hevc->primaries[i][j];
7860	for (i = 0; i < 2; i++) {
7861	vf_dp->white_point[i] = hevc->white_point[i];
7862	vf_dp->luminance[i]
7863	= hevc->luminance[i];
7864	}
7865	vf_dp->present_flag = 1;
7866	} else
7867	vf_dp->present_flag = 0;
7868
7869	/* content_light_level */
7870	if (hevc->sei_present_flag & SEI_CONTENT_LIGHT_LEVEL_MASK) {
7871	vf_dp->content_light_level.max_content
7872	= hevc->content_light_level[0];
7873	vf_dp->content_light_level.max_pic_average
7874	= hevc->content_light_level[1];
7875	vf_dp->content_light_level.present_flag = 1;
7876	} else
7877	vf_dp->content_light_level.present_flag = 0;
7878
7879	if (hevc->is_used_v4l &&
7880	((hevc->sei_present_flag & SEI_HDR10PLUS_MASK) ||
7881	(vf_dp->present_flag) ||
7882	(vf_dp->content_light_level.present_flag))) {
7883	struct aml_vdec_hdr_infos hdr;
7884	struct aml_vcodec_ctx *ctx =
7885	(struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
7886
7887	memset(&hdr, 0, sizeof(hdr));
7888	hdr.signal_type = vf->signal_type;
7889	hdr.color_parms = *vf_dp;
7890	vdec_v4l_set_hdr_infos(ctx, &hdr);
7891	}
7892	}
7893
7894	static int vh265_vf_states(struct vframe_states *states, void *op_arg)
7895	{
7896	unsigned long flags;
7897	#ifdef MULTI_INSTANCE_SUPPORT
7898	struct vdec_s *vdec = op_arg;
7899	struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7900	#else
7901	struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7902	#endif
7903
7904	spin_lock_irqsave(&lock, flags);
7905
7906	states->vf_pool_size = VF_POOL_SIZE;
7907	states->buf_free_num = kfifo_len(&hevc->newframe_q);
7908	states->buf_avail_num = kfifo_len(&hevc->display_q);
7909
7910	if (step == 2)
7911	states->buf_avail_num = 0;
7912	spin_unlock_irqrestore(&lock, flags);
7913	return 0;
7914	}
7915
7916	static struct vframe_s *vh265_vf_peek(void *op_arg)
7917	{
7918	struct vframe_s *vf[2] = {0, 0};
7919	#ifdef MULTI_INSTANCE_SUPPORT
7920	struct vdec_s *vdec = op_arg;
7921	struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7922	#else
7923	struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7924	#endif
7925
7926	if (step == 2)
7927	return NULL;
7928
7929	if (force_disp_pic_index & 0x100) {
7930	if (force_disp_pic_index & 0x200)
7931	return NULL;
7932	return &hevc->vframe_dummy;
7933	}
7934
7935
7936	if (kfifo_out_peek(&hevc->display_q, (void *)&vf, 2)) {
7937	if (vf[1]) {
7938	vf[0]->next_vf_pts_valid = true;
7939	vf[0]->next_vf_pts = vf[1]->pts;
7940	} else
7941	vf[0]->next_vf_pts_valid = false;
7942	return vf[0];
7943	}
7944
7945	return NULL;
7946	}
7947
7948	static struct vframe_s *vh265_vf_get(void *op_arg)
7949	{
7950	struct vframe_s *vf;
7951	#ifdef MULTI_INSTANCE_SUPPORT
7952	struct vdec_s *vdec = op_arg;
7953	struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
7954	#else
7955	struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
7956	#endif
7957
7958	if (step == 2)
7959	return NULL;
7960	else if (step == 1)
7961	step = 2;
7962
7963	#if 0
7964	if (force_disp_pic_index & 0x100) {
7965	int buffer_index = force_disp_pic_index & 0xff;
7966	struct PIC_s *pic = NULL;
7967	if (buffer_index >= 0
7968	&& buffer_index < MAX_REF_PIC_NUM)
7969	pic = hevc->m_PIC[buffer_index];
7970	if (pic == NULL)
7971	return NULL;
7972	if (force_disp_pic_index & 0x200)
7973	return NULL;
7974
7975	vf = &hevc->vframe_dummy;
7976	if (get_double_write_mode(hevc)) {
7977	vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD |
7978	VIDTYPE_VIU_NV21;
7979	if (hevc->m_ins_flag) {
7980	vf->canvas0Addr = vf->canvas1Addr = -1;
7981	vf->plane_num = 2;
7982	vf->canvas0_config[0] =
7983	pic->canvas_config[0];
7984	vf->canvas0_config[1] =
7985	pic->canvas_config[1];
7986
7987	vf->canvas1_config[0] =
7988	pic->canvas_config[0];
7989	vf->canvas1_config[1] =
7990	pic->canvas_config[1];
7991	} else {
7992	vf->canvas0Addr = vf->canvas1Addr
7993	= spec2canvas(pic);
7994	}
7995	} else {
7996	vf->canvas0Addr = vf->canvas1Addr = 0;
7997	vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7998	if (hevc->mmu_enable)
7999	vf->type |= VIDTYPE_SCATTER;
8000	}
8001	vf->compWidth = pic->width;
8002	vf->compHeight = pic->height;
8003	update_vf_memhandle(hevc, vf, pic);
8004	switch (hevc->bit_depth_luma) {
8005	case 9:
8006	vf->bitdepth = BITDEPTH_Y9 | BITDEPTH_U9 | BITDEPTH_V9;
8007	break;
8008	case 10:
8009	vf->bitdepth = BITDEPTH_Y10 | BITDEPTH_U10
8010	| BITDEPTH_V10;
8011	break;
8012	default:
8013	vf->bitdepth = BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
8014	break;
8015	}
8016	if ((vf->type & VIDTYPE_COMPRESS) == 0)
8017	vf->bitdepth =
8018	BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
8019	if (hevc->mem_saving_mode == 1)
8020	vf->bitdepth |= BITDEPTH_SAVING_MODE;
8021	vf->duration_pulldown = 0;
8022	vf->pts = 0;
8023	vf->pts_us64 = 0;
8024	set_frame_info(hevc, vf);
8025
8026	vf->width = pic->width /
8027	get_double_write_ratio(hevc, pic->double_write_mode);
8028	vf->height = pic->height /
8029	get_double_write_ratio(hevc, pic->double_write_mode);
8030
8031	force_disp_pic_index |= 0x200;
8032	return vf;
8033	}
8034	#endif
8035
8036	if (kfifo_get(&hevc->display_q, &vf)) {
8037	struct vframe_s *next_vf;
8038	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8039	hevc_print(hevc, 0,
8040	"%s(vf 0x%p type %d index 0x%x poc %d/%d) pts(%d,%d) dur %d\n",
8041	__func__, vf, vf->type, vf->index,
8042	get_pic_poc(hevc, vf->index & 0xff),
8043	get_pic_poc(hevc, (vf->index >> 8) & 0xff),
8044	vf->pts, vf->pts_us64,
8045	vf->duration);
8046	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8047	if (get_dbg_flag(hevc) & H265_DEBUG_DV) {
8048	struct PIC_s *pic = hevc->m_PIC[vf->index & 0xff];
8049	if (pic->aux_data_buf && pic->aux_data_size > 0) {
8050	int i;
8051	struct PIC_s *pic =
8052	hevc->m_PIC[vf->index & 0xff];
8053	hevc_print(hevc, 0,
8054	"pic 0x%p aux size %d:\n",
8055	pic, pic->aux_data_size);
8056	for (i = 0; i < pic->aux_data_size; i++) {
8057	hevc_print_cont(hevc, 0,
8058	"%02x ", pic->aux_data_buf[i]);
8059	if (((i + 1) & 0xf) == 0)
8060	hevc_print_cont(hevc, 0, "\n");
8061	}
8062	hevc_print_cont(hevc, 0, "\n");
8063	}
8064	}
8065	#endif
8066	hevc->show_frame_num++;
8067	hevc->vf_get_count++;
8068
8069	if (kfifo_peek(&hevc->display_q, &next_vf)) {
8070	vf->next_vf_pts_valid = true;
8071	vf->next_vf_pts = next_vf->pts;
8072	} else
8073	vf->next_vf_pts_valid = false;
8074
8075	return vf;
8076	}
8077
8078	return NULL;
8079	}
8080	static bool vf_valid_check(struct vframe_s *vf, struct hevc_state_s *hevc) {
8081	int i;
8082	for (i = 0; i < VF_POOL_SIZE; i++) {
8083	if (vf == &hevc->vfpool[i])
8084	return true;
8085	}
8086	pr_info(" h265 invalid vf been put, vf = %p\n", vf);
8087	for (i = 0; i < VF_POOL_SIZE; i++) {
8088	pr_info("www valid vf[%d]= %p \n", i, &hevc->vfpool[i]);
8089	}
8090	return false;
8091	}
8092
8093	static void vh265_vf_put(struct vframe_s *vf, void *op_arg)
8094	{
8095	unsigned long flags;
8096	#ifdef MULTI_INSTANCE_SUPPORT
8097	struct vdec_s *vdec = op_arg;
8098	struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
8099	#else
8100	struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
8101	#endif
8102	unsigned char index_top;
8103	unsigned char index_bot;
8104
8105	if (vf && (vf_valid_check(vf, hevc) == false))
8106	return;
8107	if (vf == (&hevc->vframe_dummy))
8108	return;
8109	index_top = vf->index & 0xff;
8110	index_bot = (vf->index >> 8) & 0xff;
8111	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8112	hevc_print(hevc, 0,
8113	"%s(type %d index 0x%x)\n",
8114	__func__, vf->type, vf->index);
8115	hevc->vf_put_count++;
8116	kfifo_put(&hevc->newframe_q, (const struct vframe_s *)vf);
8117	spin_lock_irqsave(&lock, flags);
8118
8119	if (index_top != 0xff
8120	&& index_top < MAX_REF_PIC_NUM
8121	&& hevc->m_PIC[index_top]) {
8122	if (hevc->is_used_v4l)
8123	hevc->m_PIC[index_top]->vframe_bound = true;
8124	if (hevc->m_PIC[index_top]->vf_ref > 0) {
8125	hevc->m_PIC[index_top]->vf_ref--;
8126
8127	if (hevc->m_PIC[index_top]->vf_ref == 0) {
8128	hevc->m_PIC[index_top]->output_ready = 0;
8129
8130	if (hevc->wait_buf != 0)
8131	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
8132	0x1);
8133	}
8134	}
8135	}
8136
8137	if (index_bot != 0xff
8138	&& index_bot < MAX_REF_PIC_NUM
8139	&& hevc->m_PIC[index_bot]) {
8140	if (hevc->is_used_v4l)
8141	hevc->m_PIC[index_bot]->vframe_bound = true;
8142	if (hevc->m_PIC[index_bot]->vf_ref > 0) {
8143	hevc->m_PIC[index_bot]->vf_ref--;
8144
8145	if (hevc->m_PIC[index_bot]->vf_ref == 0) {
8146	hevc->m_PIC[index_bot]->output_ready = 0;
8147	if (hevc->wait_buf != 0)
8148	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
8149	0x1);
8150	}
8151	}
8152	}
8153	spin_unlock_irqrestore(&lock, flags);
8154	}
8155
8156	static int vh265_event_cb(int type, void *data, void *op_arg)
8157	{
8158	unsigned long flags;
8159	#ifdef MULTI_INSTANCE_SUPPORT
8160	struct vdec_s *vdec = op_arg;
8161	struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
8162	#else
8163	struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg;
8164	#endif
8165	if (type & VFRAME_EVENT_RECEIVER_RESET) {
8166	#if 0
8167	amhevc_stop();
8168	#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
8169	vf_light_unreg_provider(&vh265_vf_prov);
8170	#endif
8171	spin_lock_irqsave(&hevc->lock, flags);
8172	vh265_local_init();
8173	vh265_prot_init();
8174	spin_unlock_irqrestore(&hevc->lock, flags);
8175	#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
8176	vf_reg_provider(&vh265_vf_prov);
8177	#endif
8178	amhevc_start();
8179	#endif
8180	} else if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) {
8181	struct provider_aux_req_s *req =
8182	(struct provider_aux_req_s *)data;
8183	unsigned char index;
8184
8185	spin_lock_irqsave(&lock, flags);
8186	index = req->vf->index & 0xff;
8187	req->aux_buf = NULL;
8188	req->aux_size = 0;
8189	if (req->bot_flag)
8190	index = (req->vf->index >> 8) & 0xff;
8191	if (index != 0xff
8192	&& index < MAX_REF_PIC_NUM
8193	&& hevc->m_PIC[index]) {
8194	req->aux_buf = hevc->m_PIC[index]->aux_data_buf;
8195	req->aux_size = hevc->m_PIC[index]->aux_data_size;
8196	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8197	if (hevc->bypass_dvenl && !dolby_meta_with_el)
8198	req->dv_enhance_exist = false;
8199	else
8200	req->dv_enhance_exist =
8201	hevc->m_PIC[index]->dv_enhance_exist;
8202	hevc_print(hevc, H265_DEBUG_DV,
8203	"query dv_enhance_exist for pic (vf 0x%p, poc %d index %d) flag => %d, aux sizd 0x%x\n",
8204	req->vf,
8205	hevc->m_PIC[index]->POC, index,
8206	req->dv_enhance_exist, req->aux_size);
8207	#else
8208	req->dv_enhance_exist = 0;
8209	#endif
8210	}
8211	spin_unlock_irqrestore(&lock, flags);
8212
8213	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8214	hevc_print(hevc, 0,
8215	"%s(type 0x%x vf index 0x%x)=>size 0x%x\n",
8216	__func__, type, index, req->aux_size);
8217	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8218	} else if (type & VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL) {
8219	if ((force_bypass_dvenl & 0x80000000) == 0) {
8220	hevc_print(hevc, 0,
8221	"%s: VFRAME_EVENT_RECEIVER_DOLBY_BYPASS_EL\n",
8222	__func__);
8223	hevc->bypass_dvenl_enable = 1;
8224	}
8225
8226	#endif
8227	}
8228	return 0;
8229	}
8230
8231	#ifdef HEVC_PIC_STRUCT_SUPPORT
8232	static int process_pending_vframe(struct hevc_state_s *hevc,
8233	struct PIC_s *pair_pic, unsigned char pair_frame_top_flag)
8234	{
8235	struct vframe_s *vf;
8236
8237	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8238	hevc_print(hevc, 0,
8239	"%s: pair_pic index 0x%x %s\n",
8240	__func__, pair_pic->index,
8241	pair_frame_top_flag ?
8242	"top" : "bot");
8243
8244	if (kfifo_len(&hevc->pending_q) > 1) {
8245	unsigned long flags;
8246	/* do not pending more than 1 frame */
8247	if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8248	hevc_print(hevc, 0,
8249	"fatal error, no available buffer slot.");
8250	return -1;
8251	}
8252	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8253	hevc_print(hevc, 0,
8254	"%s warning(1), vf=>display_q: (index 0x%x)\n",
8255	__func__, vf->index);
8256	if ((hevc->double_write_mode == 3) &&
8257	(!(IS_8K_SIZE(vf->width, vf->height)))) {
8258	vf->type |= VIDTYPE_COMPRESS;
8259	if (hevc->mmu_enable)
8260	vf->type |= VIDTYPE_SCATTER;
8261	}
8262	hevc->vf_pre_count++;
8263	kfifo_put(&hevc->newframe_q, (const struct vframe_s *)vf);
8264	spin_lock_irqsave(&lock, flags);
8265	vf->index &= 0xff;
8266	hevc->m_PIC[vf->index]->output_ready = 0;
8267	if (hevc->wait_buf != 0)
8268	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
8269	0x1);
8270	spin_unlock_irqrestore(&lock, flags);
8271
8272	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8273	}
8274
8275	if (kfifo_peek(&hevc->pending_q, &vf)) {
8276	if (pair_pic == NULL || pair_pic->vf_ref <= 0) {
8277	/*
8278	*if pair_pic is recycled (pair_pic->vf_ref <= 0),
8279	*do not use it
8280	*/
8281	if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8282	hevc_print(hevc, 0,
8283	"fatal error, no available buffer slot.");
8284	return -1;
8285	}
8286	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8287	hevc_print(hevc, 0,
8288	"%s warning(2), vf=>display_q: (index 0x%x)\n",
8289	__func__, vf->index);
8290	if (vf) {
8291	if ((hevc->double_write_mode == 3) &&
8292	(!(IS_8K_SIZE(vf->width, vf->height)))) {
8293	vf->type |= VIDTYPE_COMPRESS;
8294	if (hevc->mmu_enable)
8295	vf->type |= VIDTYPE_SCATTER;
8296	}
8297	hevc->vf_pre_count++;
8298	kfifo_put(&hevc->display_q,
8299	(const struct vframe_s *)vf);
8300	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8301	}
8302	} else if ((!pair_frame_top_flag) &&
8303	(((vf->index >> 8) & 0xff) == 0xff)) {
8304	if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8305	hevc_print(hevc, 0,
8306	"fatal error, no available buffer slot.");
8307	return -1;
8308	}
8309	if (vf) {
8310	if ((hevc->double_write_mode == 3) &&
8311	(!(IS_8K_SIZE(vf->width, vf->height)))) {
8312	vf->type |= VIDTYPE_COMPRESS;
8313	if (hevc->mmu_enable)
8314	vf->type |= VIDTYPE_SCATTER;
8315	}
8316	vf->index &= 0xff;
8317	vf->index |= (pair_pic->index << 8);
8318	vf->canvas1Addr = spec2canvas(pair_pic);
8319	pair_pic->vf_ref++;
8320	kfifo_put(&hevc->display_q,
8321	(const struct vframe_s *)vf);
8322	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8323	hevc->vf_pre_count++;
8324	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8325	hevc_print(hevc, 0,
8326	"%s vf => display_q: (index 0x%x)\n",
8327	__func__, vf->index);
8328	}
8329	} else if (pair_frame_top_flag &&
8330	((vf->index & 0xff) == 0xff)) {
8331	if (kfifo_get(&hevc->pending_q, &vf) == 0) {
8332	hevc_print(hevc, 0,
8333	"fatal error, no available buffer slot.");
8334	return -1;
8335	}
8336	if (vf) {
8337	if ((hevc->double_write_mode == 3) &&
8338	(!(IS_8K_SIZE(vf->width, vf->height)))) {
8339	vf->type |= VIDTYPE_COMPRESS;
8340	if (hevc->mmu_enable)
8341	vf->type |= VIDTYPE_SCATTER;
8342	}
8343	vf->index &= 0xff00;
8344	vf->index |= pair_pic->index;
8345	vf->canvas0Addr = spec2canvas(pair_pic);
8346	pair_pic->vf_ref++;
8347	kfifo_put(&hevc->display_q,
8348	(const struct vframe_s *)vf);
8349	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8350	hevc->vf_pre_count++;
8351	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8352	hevc_print(hevc, 0,
8353	"%s vf => display_q: (index 0x%x)\n",
8354	__func__, vf->index);
8355	}
8356	}
8357	}
8358	return 0;
8359	}
8360	#endif
8361	static void update_vf_memhandle(struct hevc_state_s *hevc,
8362	struct vframe_s *vf, struct PIC_s *pic)
8363	{
8364	if (pic->index < 0) {
8365	vf->mem_handle = NULL;
8366	vf->mem_head_handle = NULL;
8367	} else if (vf->type & VIDTYPE_SCATTER) {
8368	vf->mem_handle =
8369	decoder_mmu_box_get_mem_handle(
8370	hevc->mmu_box, pic->index);
8371	vf->mem_head_handle =
8372	decoder_bmmu_box_get_mem_handle(
8373	hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
8374	} else {
8375	vf->mem_handle =
8376	decoder_bmmu_box_get_mem_handle(
8377	hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
8378	vf->mem_head_handle = NULL;
8379	/*vf->mem_head_handle =
8380	decoder_bmmu_box_get_mem_handle(
8381	hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));*/
8382	}
8383	return;
8384	}
8385
8386	static void fill_frame_info(struct hevc_state_s *hevc,
8387	struct PIC_s *pic, unsigned int framesize, unsigned int pts)
8388	{
8389	struct vframe_qos_s *vframe_qos = &hevc->vframe_qos;
8390	if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_IDR)
8391	vframe_qos->type = 4;
8392	else if (pic->slice_type == I_SLICE)
8393	vframe_qos->type = 1;
8394	else if (pic->slice_type == P_SLICE)
8395	vframe_qos->type = 2;
8396	else if (pic->slice_type == B_SLICE)
8397	vframe_qos->type = 3;
8398	/*
8399	#define SHOW_QOS_INFO
8400	*/
8401	vframe_qos->size = framesize;
8402	vframe_qos->pts = pts;
8403	#ifdef SHOW_QOS_INFO
8404	hevc_print(hevc, 0, "slice:%d, poc:%d\n", pic->slice_type, pic->POC);
8405	#endif
8406
8407
8408	vframe_qos->max_mv = pic->max_mv;
8409	vframe_qos->avg_mv = pic->avg_mv;
8410	vframe_qos->min_mv = pic->min_mv;
8411	#ifdef SHOW_QOS_INFO
8412	hevc_print(hevc, 0, "mv: max:%d, avg:%d, min:%d\n",
8413	vframe_qos->max_mv,
8414	vframe_qos->avg_mv,
8415	vframe_qos->min_mv);
8416	#endif
8417
8418	vframe_qos->max_qp = pic->max_qp;
8419	vframe_qos->avg_qp = pic->avg_qp;
8420	vframe_qos->min_qp = pic->min_qp;
8421	#ifdef SHOW_QOS_INFO
8422	hevc_print(hevc, 0, "qp: max:%d, avg:%d, min:%d\n",
8423	vframe_qos->max_qp,
8424	vframe_qos->avg_qp,
8425	vframe_qos->min_qp);
8426	#endif
8427
8428	vframe_qos->max_skip = pic->max_skip;
8429	vframe_qos->avg_skip = pic->avg_skip;
8430	vframe_qos->min_skip = pic->min_skip;
8431	#ifdef SHOW_QOS_INFO
8432	hevc_print(hevc, 0, "skip: max:%d, avg:%d, min:%d\n",
8433	vframe_qos->max_skip,
8434	vframe_qos->avg_skip,
8435	vframe_qos->min_skip);
8436	#endif
8437
8438	vframe_qos->num++;
8439
8440	if (hevc->frameinfo_enable)
8441	vdec_fill_frame_info(vframe_qos, 1);
8442	}
8443
8444	static int prepare_display_buf(struct hevc_state_s *hevc, struct PIC_s *pic)
8445	{
8446	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8447	struct vdec_s *vdec = hw_to_vdec(hevc);
8448	#endif
8449	struct vframe_s *vf = NULL;
8450	int stream_offset = pic->stream_offset;
8451	unsigned short slice_type = pic->slice_type;
8452	u32 frame_size;
8453
8454	if (force_disp_pic_index & 0x100) {
8455	/*recycle directly*/
8456	pic->output_ready = 0;
8457	return -1;
8458	}
8459	if (kfifo_get(&hevc->newframe_q, &vf) == 0) {
8460	hevc_print(hevc, 0,
8461	"fatal error, no available buffer slot.");
8462	return -1;
8463	}
8464	display_frame_count[hevc->index]++;
8465	if (vf) {
8466	/*hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
8467	"%s: pic index 0x%x\n",
8468	__func__, pic->index);*/
8469
8470	if (hevc->is_used_v4l) {
8471	vf->v4l_mem_handle
8472	= hevc->m_BUF[pic->BUF_index].v4l_ref_buf_addr;
8473	if (hevc->mmu_enable) {
8474	vf->mm_box.bmmu_box = hevc->bmmu_box;
8475	vf->mm_box.bmmu_idx = VF_BUFFER_IDX(pic->BUF_index);
8476	vf->mm_box.mmu_box = hevc->mmu_box;
8477	vf->mm_box.mmu_idx = pic->index;
8478	}
8479	}
8480
8481	#ifdef MULTI_INSTANCE_SUPPORT
8482	if (vdec_frame_based(hw_to_vdec(hevc))) {
8483	vf->pts = pic->pts;
8484	vf->pts_us64 = pic->pts64;
8485	vf->timestamp = pic->timestamp;
8486	}
8487	/* if (pts_lookup_offset(PTS_TYPE_VIDEO,
8488	stream_offset, &vf->pts, 0) != 0) { */
8489	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8490	else if (vdec->master == NULL) {
8491	#else
8492	else {
8493	#endif
8494	#endif
8495	hevc_print(hevc, H265_DEBUG_OUT_PTS,
8496	"call pts_lookup_offset_us64(0x%x)\n",
8497	stream_offset);
8498	if (pts_lookup_offset_us64
8499	(PTS_TYPE_VIDEO, stream_offset, &vf->pts,
8500	&frame_size, 0,
8501	&vf->pts_us64) != 0) {
8502	#ifdef DEBUG_PTS
8503	hevc->pts_missed++;
8504	#endif
8505	vf->pts = 0;
8506	vf->pts_us64 = 0;
8507	}
8508	#ifdef DEBUG_PTS
8509	else
8510	hevc->pts_hit++;
8511	#endif
8512	#ifdef MULTI_INSTANCE_SUPPORT
8513	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
8514	} else {
8515	vf->pts = 0;
8516	vf->pts_us64 = 0;
8517	}
8518	#else
8519	}
8520	#endif
8521	#endif
8522	if (pts_unstable && (hevc->frame_dur > 0))
8523	hevc->pts_mode = PTS_NONE_REF_USE_DURATION;
8524
8525	fill_frame_info(hevc, pic, frame_size, vf->pts);
8526
8527	if ((hevc->pts_mode == PTS_NORMAL) && (vf->pts != 0)
8528	&& hevc->get_frame_dur) {
8529	int pts_diff = (int)vf->pts - hevc->last_lookup_pts;
8530
8531	if (pts_diff < 0) {
8532	hevc->pts_mode_switching_count++;
8533	hevc->pts_mode_recovery_count = 0;
8534
8535	if (hevc->pts_mode_switching_count >=
8536	PTS_MODE_SWITCHING_THRESHOLD) {
8537	hevc->pts_mode =
8538	PTS_NONE_REF_USE_DURATION;
8539	hevc_print(hevc, 0,
8540	"HEVC: switch to n_d mode.\n");
8541	}
8542
8543	} else {
8544	int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
8545
8546	hevc->pts_mode_recovery_count++;
8547	if (hevc->pts_mode_recovery_count > p) {
8548	hevc->pts_mode_switching_count = 0;
8549	hevc->pts_mode_recovery_count = 0;
8550	}
8551	}
8552	}
8553
8554	if (vf->pts != 0)
8555	hevc->last_lookup_pts = vf->pts;
8556
8557	if ((hevc->pts_mode == PTS_NONE_REF_USE_DURATION)
8558	&& (slice_type != 2))
8559	vf->pts = hevc->last_pts + DUR2PTS(hevc->frame_dur);
8560	hevc->last_pts = vf->pts;
8561
8562	if (vf->pts_us64 != 0)
8563	hevc->last_lookup_pts_us64 = vf->pts_us64;
8564
8565	if ((hevc->pts_mode == PTS_NONE_REF_USE_DURATION)
8566	&& (slice_type != 2)) {
8567	vf->pts_us64 =
8568	hevc->last_pts_us64 +
8569	(DUR2PTS(hevc->frame_dur) * 100 / 9);
8570	}
8571	hevc->last_pts_us64 = vf->pts_us64;
8572	if ((get_dbg_flag(hevc) & H265_DEBUG_OUT_PTS) != 0) {
8573	hevc_print(hevc, 0,
8574	"H265 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n",
8575	vf->pts, vf->pts_us64);
8576	}
8577
8578	/*
8579	*vf->index:
8580	*(1) vf->type is VIDTYPE_PROGRESSIVE
8581	* and vf->canvas0Addr != vf->canvas1Addr,
8582	* vf->index[7:0] is the index of top pic
8583	* vf->index[15:8] is the index of bot pic
8584	*(2) other cases,
8585	* only vf->index[7:0] is used
8586	* vf->index[15:8] == 0xff
8587	*/
8588	vf->index = 0xff00 | pic->index;
8589	#if 1
8590	/*SUPPORT_10BIT*/
8591	if (pic->double_write_mode & 0x10) {
8592	/* double write only */
8593	vf->compBodyAddr = 0;
8594	vf->compHeadAddr = 0;
8595	} else {
8596
8597	if (hevc->mmu_enable) {
8598	vf->compBodyAddr = 0;
8599	vf->compHeadAddr = pic->header_adr;
8600	} else {
8601	vf->compBodyAddr = pic->mc_y_adr; /*body adr*/
8602	vf->compHeadAddr = pic->mc_y_adr +
8603	pic->losless_comp_body_size;
8604	vf->mem_head_handle = NULL;
8605	}
8606
8607	/*head adr*/
8608	vf->canvas0Addr = vf->canvas1Addr = 0;
8609	}
8610	if (pic->double_write_mode) {
8611	vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
8612	vf->type |= VIDTYPE_VIU_NV21;
8613
8614	if ((pic->double_write_mode == 3) &&
8615	(!(IS_8K_SIZE(pic->width, pic->height)))) {
8616	vf->type |= VIDTYPE_COMPRESS;
8617	if (hevc->mmu_enable)
8618	vf->type |= VIDTYPE_SCATTER;
8619	}
8620	#ifdef MULTI_INSTANCE_SUPPORT
8621	if (hevc->m_ins_flag &&
8622	(get_dbg_flag(hevc)
8623	& H265_CFG_CANVAS_IN_DECODE) == 0) {
8624	vf->canvas0Addr = vf->canvas1Addr = -1;
8625	vf->plane_num = 2;
8626	vf->canvas0_config[0] =
8627	pic->canvas_config[0];
8628	vf->canvas0_config[1] =
8629	pic->canvas_config[1];
8630
8631	vf->canvas1_config[0] =
8632	pic->canvas_config[0];
8633	vf->canvas1_config[1] =
8634	pic->canvas_config[1];
8635
8636	} else
8637	#endif
8638	vf->canvas0Addr = vf->canvas1Addr
8639	= spec2canvas(pic);
8640	} else {
8641	vf->canvas0Addr = vf->canvas1Addr = 0;
8642	vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
8643	if (hevc->mmu_enable)
8644	vf->type |= VIDTYPE_SCATTER;
8645	}
8646	vf->compWidth = pic->width;
8647	vf->compHeight = pic->height;
8648	update_vf_memhandle(hevc, vf, pic);
8649	switch (pic->bit_depth_luma) {
8650	case 9:
8651	vf->bitdepth = BITDEPTH_Y9;
8652	break;
8653	case 10:
8654	vf->bitdepth = BITDEPTH_Y10;
8655	break;
8656	default:
8657	vf->bitdepth = BITDEPTH_Y8;
8658	break;
8659	}
8660	switch (pic->bit_depth_chroma) {
8661	case 9:
8662	vf->bitdepth |= (BITDEPTH_U9 | BITDEPTH_V9);
8663	break;
8664	case 10:
8665	vf->bitdepth |= (BITDEPTH_U10 | BITDEPTH_V10);
8666	break;
8667	default:
8668	vf->bitdepth |= (BITDEPTH_U8 | BITDEPTH_V8);
8669	break;
8670	}
8671	if ((vf->type & VIDTYPE_COMPRESS) == 0)
8672	vf->bitdepth =
8673	BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
8674	if (pic->mem_saving_mode == 1)
8675	vf->bitdepth |= BITDEPTH_SAVING_MODE;
8676	#else
8677	vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
8678	vf->type |= VIDTYPE_VIU_NV21;
8679	vf->canvas0Addr = vf->canvas1Addr = spec2canvas(pic);
8680	#endif
8681	set_frame_info(hevc, vf, pic);
8682	/* if((vf->width!=pic->width)||(vf->height!=pic->height)) */
8683	/* hevc_print(hevc, 0,
8684	"aaa: %d/%d, %d/%d\n",
8685	vf->width,vf->height, pic->width, pic->height); */
8686	vf->width = pic->width;
8687	vf->height = pic->height;
8688
8689	if (force_w_h != 0) {
8690	vf->width = (force_w_h >> 16) & 0xffff;
8691	vf->height = force_w_h & 0xffff;
8692	}
8693	if (force_fps & 0x100) {
8694	u32 rate = force_fps & 0xff;
8695
8696	if (rate)
8697	vf->duration = 96000/rate;
8698	else
8699	vf->duration = 0;
8700	}
8701	if (force_fps & 0x200) {
8702	vf->pts = 0;
8703	vf->pts_us64 = 0;
8704	}
8705	/*
8706	* !!! to do ...
8707	* need move below code to get_new_pic(),
8708	* hevc->xxx can only be used by current decoded pic
8709	*/
8710	if (pic->conformance_window_flag &&
8711	(get_dbg_flag(hevc) &
8712	H265_DEBUG_IGNORE_CONFORMANCE_WINDOW) == 0) {
8713	unsigned int SubWidthC, SubHeightC;
8714
8715	switch (pic->chroma_format_idc) {
8716	case 1:
8717	SubWidthC = 2;
8718	SubHeightC = 2;
8719	break;
8720	case 2:
8721	SubWidthC = 2;
8722	SubHeightC = 1;
8723	break;
8724	default:
8725	SubWidthC = 1;
8726	SubHeightC = 1;
8727	break;
8728	}
8729	vf->width -= SubWidthC *
8730	(pic->conf_win_left_offset +
8731	pic->conf_win_right_offset);
8732	vf->height -= SubHeightC *
8733	(pic->conf_win_top_offset +
8734	pic->conf_win_bottom_offset);
8735
8736	vf->compWidth -= SubWidthC *
8737	(pic->conf_win_left_offset +
8738	pic->conf_win_right_offset);
8739	vf->compHeight -= SubHeightC *
8740	(pic->conf_win_top_offset +
8741	pic->conf_win_bottom_offset);
8742
8743	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
8744	hevc_print(hevc, 0,
8745	"conformance_window %d, %d, %d, %d, %d => cropped width %d, height %d com_w %d com_h %d\n",
8746	pic->chroma_format_idc,
8747	pic->conf_win_left_offset,
8748	pic->conf_win_right_offset,
8749	pic->conf_win_top_offset,
8750	pic->conf_win_bottom_offset,
8751	vf->width, vf->height, vf->compWidth, vf->compHeight);
8752	}
8753
8754	vf->width = vf->width /
8755	get_double_write_ratio(hevc, pic->double_write_mode);
8756	vf->height = vf->height /
8757	get_double_write_ratio(hevc, pic->double_write_mode);
8758	#ifdef HEVC_PIC_STRUCT_SUPPORT
8759	if (pic->pic_struct == 3 || pic->pic_struct == 4) {
8760	struct vframe_s *vf2;
8761
8762	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8763	hevc_print(hevc, 0,
8764	"pic_struct = %d index 0x%x\n",
8765	pic->pic_struct,
8766	pic->index);
8767
8768	if (kfifo_get(&hevc->newframe_q, &vf2) == 0) {
8769	hevc_print(hevc, 0,
8770	"fatal error, no available buffer slot.");
8771	return -1;
8772	}
8773	pic->vf_ref = 2;
8774	vf->duration = vf->duration>>1;
8775	memcpy(vf2, vf, sizeof(struct vframe_s));
8776
8777	if (pic->pic_struct == 3) {
8778	vf->type = VIDTYPE_INTERLACE_TOP
8779	| VIDTYPE_VIU_NV21;
8780	vf2->type = VIDTYPE_INTERLACE_BOTTOM
8781	| VIDTYPE_VIU_NV21;
8782	} else {
8783	vf->type = VIDTYPE_INTERLACE_BOTTOM
8784	| VIDTYPE_VIU_NV21;
8785	vf2->type = VIDTYPE_INTERLACE_TOP
8786	| VIDTYPE_VIU_NV21;
8787	}
8788	hevc->vf_pre_count++;
8789	decoder_do_frame_check(hw_to_vdec(hevc), vf);
8790	kfifo_put(&hevc->display_q,
8791	(const struct vframe_s *)vf);
8792	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8793	hevc->vf_pre_count++;
8794	kfifo_put(&hevc->display_q,
8795	(const struct vframe_s *)vf2);
8796	ATRACE_COUNTER(MODULE_NAME, vf2->pts);
8797	} else if (pic->pic_struct == 5
8798	|| pic->pic_struct == 6) {
8799	struct vframe_s *vf2, *vf3;
8800
8801	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8802	hevc_print(hevc, 0,
8803	"pic_struct = %d index 0x%x\n",
8804	pic->pic_struct,
8805	pic->index);
8806
8807	if (kfifo_get(&hevc->newframe_q, &vf2) == 0) {
8808	hevc_print(hevc, 0,
8809	"fatal error, no available buffer slot.");
8810	return -1;
8811	}
8812	if (kfifo_get(&hevc->newframe_q, &vf3) == 0) {
8813	hevc_print(hevc, 0,
8814	"fatal error, no available buffer slot.");
8815	return -1;
8816	}
8817	pic->vf_ref = 3;
8818	vf->duration = vf->duration/3;
8819	memcpy(vf2, vf, sizeof(struct vframe_s));
8820	memcpy(vf3, vf, sizeof(struct vframe_s));
8821
8822	if (pic->pic_struct == 5) {
8823	vf->type = VIDTYPE_INTERLACE_TOP
8824	| VIDTYPE_VIU_NV21;
8825	vf2->type = VIDTYPE_INTERLACE_BOTTOM
8826	| VIDTYPE_VIU_NV21;
8827	vf3->type = VIDTYPE_INTERLACE_TOP
8828	| VIDTYPE_VIU_NV21;
8829	} else {
8830	vf->type = VIDTYPE_INTERLACE_BOTTOM
8831	| VIDTYPE_VIU_NV21;
8832	vf2->type = VIDTYPE_INTERLACE_TOP
8833	| VIDTYPE_VIU_NV21;
8834	vf3->type = VIDTYPE_INTERLACE_BOTTOM
8835	| VIDTYPE_VIU_NV21;
8836	}
8837	hevc->vf_pre_count++;
8838	decoder_do_frame_check(hw_to_vdec(hevc), vf);
8839	kfifo_put(&hevc->display_q,
8840	(const struct vframe_s *)vf);
8841	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8842	hevc->vf_pre_count++;
8843	kfifo_put(&hevc->display_q,
8844	(const struct vframe_s *)vf2);
8845	ATRACE_COUNTER(MODULE_NAME, vf2->pts);
8846	hevc->vf_pre_count++;
8847	kfifo_put(&hevc->display_q,
8848	(const struct vframe_s *)vf3);
8849	ATRACE_COUNTER(MODULE_NAME, vf3->pts);
8850
8851	} else if (pic->pic_struct == 9
8852	|| pic->pic_struct == 10) {
8853	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8854	hevc_print(hevc, 0,
8855	"pic_struct = %d index 0x%x\n",
8856	pic->pic_struct,
8857	pic->index);
8858
8859	pic->vf_ref = 1;
8860	/* process previous pending vf*/
8861	process_pending_vframe(hevc,
8862	pic, (pic->pic_struct == 9));
8863
8864	decoder_do_frame_check(hw_to_vdec(hevc), vf);
8865	/* process current vf */
8866	kfifo_put(&hevc->pending_q,
8867	(const struct vframe_s *)vf);
8868	vf->height <<= 1;
8869	if (pic->pic_struct == 9) {
8870	vf->type = VIDTYPE_INTERLACE_TOP
8871	| VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8872	process_pending_vframe(hevc,
8873	hevc->pre_bot_pic, 0);
8874	} else {
8875	vf->type = VIDTYPE_INTERLACE_BOTTOM |
8876	VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8877	vf->index = (pic->index << 8) | 0xff;
8878	process_pending_vframe(hevc,
8879	hevc->pre_top_pic, 1);
8880	}
8881
8882	if (hevc->vf_pre_count == 0)
8883	hevc->vf_pre_count++;
8884
8885	/**/
8886	if (pic->pic_struct == 9)
8887	hevc->pre_top_pic = pic;
8888	else
8889	hevc->pre_bot_pic = pic;
8890
8891	} else if (pic->pic_struct == 11
8892	|| pic->pic_struct == 12) {
8893	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8894	hevc_print(hevc, 0,
8895	"pic_struct = %d index 0x%x\n",
8896	pic->pic_struct,
8897	pic->index);
8898	pic->vf_ref = 1;
8899	/* process previous pending vf*/
8900	process_pending_vframe(hevc, pic,
8901	(pic->pic_struct == 11));
8902
8903	/* put current into pending q */
8904	vf->height <<= 1;
8905	if (pic->pic_struct == 11)
8906	vf->type = VIDTYPE_INTERLACE_TOP |
8907	VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8908	else {
8909	vf->type = VIDTYPE_INTERLACE_BOTTOM |
8910	VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8911	vf->index = (pic->index << 8) | 0xff;
8912	}
8913	decoder_do_frame_check(hw_to_vdec(hevc), vf);
8914	kfifo_put(&hevc->pending_q,
8915	(const struct vframe_s *)vf);
8916	if (hevc->vf_pre_count == 0)
8917	hevc->vf_pre_count++;
8918
8919	/**/
8920	if (pic->pic_struct == 11)
8921	hevc->pre_top_pic = pic;
8922	else
8923	hevc->pre_bot_pic = pic;
8924
8925	} else {
8926	pic->vf_ref = 1;
8927
8928	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8929	hevc_print(hevc, 0,
8930	"pic_struct = %d index 0x%x\n",
8931	pic->pic_struct,
8932	pic->index);
8933
8934	switch (pic->pic_struct) {
8935	case 7:
8936	vf->duration <<= 1;
8937	break;
8938	case 8:
8939	vf->duration = vf->duration * 3;
8940	break;
8941	case 1:
8942	vf->height <<= 1;
8943	vf->type = VIDTYPE_INTERLACE_TOP |
8944	VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD;
8945	process_pending_vframe(hevc, pic, 1);
8946	hevc->pre_top_pic = pic;
8947	break;
8948	case 2:
8949	vf->height <<= 1;
8950	vf->type = VIDTYPE_INTERLACE_BOTTOM
8951	| VIDTYPE_VIU_NV21
8952	| VIDTYPE_VIU_FIELD;
8953	process_pending_vframe(hevc, pic, 0);
8954	hevc->pre_bot_pic = pic;
8955	break;
8956	}
8957	hevc->vf_pre_count++;
8958	decoder_do_frame_check(hw_to_vdec(hevc), vf);
8959	kfifo_put(&hevc->display_q,
8960	(const struct vframe_s *)vf);
8961	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8962	}
8963	#else
8964	vf->type_original = vf->type;
8965	pic->vf_ref = 1;
8966	hevc->vf_pre_count++;
8967	decoder_do_frame_check(hw_to_vdec(hevc), vf);
8968	kfifo_put(&hevc->display_q, (const struct vframe_s *)vf);
8969	ATRACE_COUNTER(MODULE_NAME, vf->pts);
8970
8971	if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT)
8972	hevc_print(hevc, 0,
8973	"%s(type %d index 0x%x poc %d/%d) pts(%d,%d) dur %d\n",
8974	__func__, vf->type, vf->index,
8975	get_pic_poc(hevc, vf->index & 0xff),
8976	get_pic_poc(hevc, (vf->index >> 8) & 0xff),
8977	vf->pts, vf->pts_us64,
8978	vf->duration);
8979	#endif
8980	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8981	/*count info*/
8982	vdec_count_info(gvs, 0, stream_offset);
8983	#endif
8984	hw_to_vdec(hevc)->vdec_fps_detec(hw_to_vdec(hevc)->id);
8985	if (without_display_mode == 0) {
8986	vf_notify_receiver(hevc->provider_name,
8987	VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
8988	}
8989	else
8990	vh265_vf_put(vh265_vf_get(vdec), vdec);
8991	}
8992
8993	return 0;
8994	}
8995
8996	static int notify_v4l_eos(struct vdec_s *vdec)
8997	{
8998	struct hevc_state_s *hw = (struct hevc_state_s *)vdec->private;
8999	struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
9000	struct vframe_s *vf = &hw->vframe_dummy;
9001	struct vdec_v4l2_buffer *fb = NULL;
9002	int index = INVALID_IDX;
9003	ulong expires;
9004
9005	if (hw->is_used_v4l && hw->eos) {
9006	expires = jiffies + msecs_to_jiffies(2000);
9007	while (INVALID_IDX == (index = get_free_buf_idx(hw))) {
9008	if (time_after(jiffies, expires))
9009	break;
9010	}
9011
9012	if (index == INVALID_IDX) {
9013	if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
9014	pr_err("[%d] EOS get free buff fail.\n", ctx->id);
9015	return -1;
9016	}
9017	}
9018
9019	vf->type |= VIDTYPE_V4L_EOS;
9020	vf->timestamp = ULONG_MAX;
9021	vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
9022	vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
9023	hw->m_BUF[index].v4l_ref_buf_addr;
9024	kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
9025	vf_notify_receiver(vdec->vf_provider_name,
9026	VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
9027
9028	pr_info("[%d] H265 EOS notify.\n", ctx->id);
9029	}
9030
9031	return 0;
9032	}
9033
9034	static void process_nal_sei(struct hevc_state_s *hevc,
9035	int payload_type, int payload_size)
9036	{
9037	unsigned short data;
9038
9039	if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
9040	hevc_print(hevc, 0,
9041	"\tsei message: payload_type = 0x%02x, payload_size = 0x%02x\n",
9042	payload_type, payload_size);
9043
9044	if (payload_type == 137) {
9045	int i, j;
9046	/* MASTERING_DISPLAY_COLOUR_VOLUME */
9047	if (payload_size >= 24) {
9048	if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
9049	hevc_print(hevc, 0,
9050	"\tsei MASTERING_DISPLAY_COLOUR_VOLUME available\n");
9051	for (i = 0; i < 3; i++) {
9052	for (j = 0; j < 2; j++) {
9053	data =
9054	(READ_HREG(HEVC_SHIFTED_DATA) >> 16);
9055	hevc->primaries[i][j] = data;
9056	WRITE_HREG(HEVC_SHIFT_COMMAND,
9057	(1<<7)|16);
9058	if (get_dbg_flag(hevc) &
9059	H265_DEBUG_PRINT_SEI)
9060	hevc_print(hevc, 0,
9061	"\t\tprimaries[%1d][%1d] = %04x\n",
9062	i, j, hevc->primaries[i][j]);
9063	}
9064	}
9065	for (i = 0; i < 2; i++) {
9066	data = (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
9067	hevc->white_point[i] = data;
9068	WRITE_HREG(HEVC_SHIFT_COMMAND, (1<<7)|16);
9069	if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI)
9070	hevc_print(hevc, 0,
9071	"\t\twhite_point[%1d] = %04x\n",
9072	i, hevc->white_point[i]);
9073	}
9074	for (i = 0; i < 2; i++) {
9075	data = (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
9076	hevc->luminance[i] = data << 16;
9077	WRITE_HREG(HEVC_SHIFT_COMMAND,
9078	(1<<7)|16);
9079	data =
9080	(READ_HREG(HEVC_SHIFTED_DATA) >> 16);
9081	hevc->luminance[i] |= data;
9082	WRITE_HREG(HEVC_SHIFT_COMMAND,
9083	(1<<7)|16);
9084	if (get_dbg_flag(hevc) &
9085	H265_DEBUG_PRINT_SEI)
9086	hevc_print(hevc, 0,
9087	"\t\tluminance[%1d] = %08x\n",
9088	i, hevc->luminance[i]);
9089	}
9090	hevc->sei_present_flag |= SEI_MASTER_DISPLAY_COLOR_MASK;
9091	}
9092	payload_size -= 24;
9093	while (payload_size > 0) {
9094	data = (READ_HREG(HEVC_SHIFTED_DATA) >> 24);
9095	payload_size--;
9096	WRITE_HREG(HEVC_SHIFT_COMMAND, (1<<7)|8);
9097	hevc_print(hevc, 0, "\t\tskip byte %02x\n", data);
9098	}
9099	}
9100	}
9101
9102	static int hevc_recover(struct hevc_state_s *hevc)
9103	{
9104	int ret = -1;
9105	u32 rem;
9106	u64 shift_byte_count64;
9107	unsigned int hevc_shift_byte_count;
9108	unsigned int hevc_stream_start_addr;
9109	unsigned int hevc_stream_end_addr;
9110	unsigned int hevc_stream_rd_ptr;
9111	unsigned int hevc_stream_wr_ptr;
9112	unsigned int hevc_stream_control;
9113	unsigned int hevc_stream_fifo_ctl;
9114	unsigned int hevc_stream_buf_size;
9115
9116	mutex_lock(&vh265_mutex);
9117	#if 0
9118	for (i = 0; i < (hevc->debug_ptr_size / 2); i += 4) {
9119	int ii;
9120
9121	for (ii = 0; ii < 4; ii++)
9122	hevc_print(hevc, 0,
9123	"%04x ", hevc->debug_ptr[i + 3 - ii]);
9124	if (((i + ii) & 0xf) == 0)
9125	hevc_print(hevc, 0, "\n");
9126	}
9127	#endif
9128	#define ES_VID_MAN_RD_PTR (1<<0)
9129	if (!hevc->init_flag) {
9130	hevc_print(hevc, 0, "h265 has stopped, recover return!\n");
9131	mutex_unlock(&vh265_mutex);
9132	return ret;
9133	}
9134	amhevc_stop();
9135	msleep(20);
9136	ret = 0;
9137	/* reset */
9138	WRITE_PARSER_REG(PARSER_VIDEO_RP, READ_VREG(HEVC_STREAM_RD_PTR));
9139	SET_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
9140
9141	hevc_stream_start_addr = READ_VREG(HEVC_STREAM_START_ADDR);
9142	hevc_stream_end_addr = READ_VREG(HEVC_STREAM_END_ADDR);
9143	hevc_stream_rd_ptr = READ_VREG(HEVC_STREAM_RD_PTR);
9144	hevc_stream_wr_ptr = READ_VREG(HEVC_STREAM_WR_PTR);
9145	hevc_stream_control = READ_VREG(HEVC_STREAM_CONTROL);
9146	hevc_stream_fifo_ctl = READ_VREG(HEVC_STREAM_FIFO_CTL);
9147	hevc_stream_buf_size = hevc_stream_end_addr - hevc_stream_start_addr;
9148
9149	/* HEVC streaming buffer will reset and restart
9150	* from current hevc_stream_rd_ptr position
9151	*/
9152	/* calculate HEVC_SHIFT_BYTE_COUNT value with the new position. */
9153	hevc_shift_byte_count = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9154	if ((hevc->shift_byte_count_lo & (1 << 31))
9155	&& ((hevc_shift_byte_count & (1 << 31)) == 0))
9156	hevc->shift_byte_count_hi++;
9157
9158	hevc->shift_byte_count_lo = hevc_shift_byte_count;
9159	shift_byte_count64 = ((u64)(hevc->shift_byte_count_hi) << 32) |
9160	hevc->shift_byte_count_lo;
9161	div_u64_rem(shift_byte_count64, hevc_stream_buf_size, &rem);
9162	shift_byte_count64 -= rem;
9163	shift_byte_count64 += hevc_stream_rd_ptr - hevc_stream_start_addr;
9164
9165	if (rem > (hevc_stream_rd_ptr - hevc_stream_start_addr))
9166	shift_byte_count64 += hevc_stream_buf_size;
9167
9168	hevc->shift_byte_count_lo = (u32)shift_byte_count64;
9169	hevc->shift_byte_count_hi = (u32)(shift_byte_count64 >> 32);
9170
9171	WRITE_VREG(DOS_SW_RESET3,
9172	/* (1<<2)| */
9173	(1 << 3) | (1 << 4) | (1 << 8) |
9174	(1 << 11) | (1 << 12) | (1 << 14)
9175	| (1 << 15) | (1 << 17) | (1 << 18) | (1 << 19));
9176	WRITE_VREG(DOS_SW_RESET3, 0);
9177
9178	WRITE_VREG(HEVC_STREAM_START_ADDR, hevc_stream_start_addr);
9179	WRITE_VREG(HEVC_STREAM_END_ADDR, hevc_stream_end_addr);
9180	WRITE_VREG(HEVC_STREAM_RD_PTR, hevc_stream_rd_ptr);
9181	WRITE_VREG(HEVC_STREAM_WR_PTR, hevc_stream_wr_ptr);
9182	WRITE_VREG(HEVC_STREAM_CONTROL, hevc_stream_control);
9183	WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, hevc->shift_byte_count_lo);
9184	WRITE_VREG(HEVC_STREAM_FIFO_CTL, hevc_stream_fifo_ctl);
9185
9186	hevc_config_work_space_hw(hevc);
9187	decoder_hw_reset();
9188
9189	hevc->have_vps = 0;
9190	hevc->have_sps = 0;
9191	hevc->have_pps = 0;
9192
9193	hevc->have_valid_start_slice = 0;
9194
9195	if (get_double_write_mode(hevc) & 0x10)
9196	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
9197	0x1 << 31 /*/Enable NV21 reference read mode for MC*/
9198	);
9199
9200	WRITE_VREG(HEVC_WAIT_FLAG, 1);
9201	/* clear mailbox interrupt */
9202	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
9203	/* enable mailbox interrupt */
9204	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
9205	/* disable PSCALE for hardware sharing */
9206	WRITE_VREG(HEVC_PSCALE_CTRL, 0);
9207
9208	CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
9209
9210	WRITE_VREG(DEBUG_REG1, 0x0);
9211
9212	if ((error_handle_policy & 1) == 0) {
9213	if ((error_handle_policy & 4) == 0) {
9214	/* ucode auto mode, and do not check vps/sps/pps/idr */
9215	WRITE_VREG(NAL_SEARCH_CTL,
9216	0xc);
9217	} else {
9218	WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */
9219	}
9220	} else {
9221	WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */
9222	}
9223
9224	if (get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE)
9225	WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x10000);
9226	WRITE_VREG(NAL_SEARCH_CTL,
9227	READ_VREG(NAL_SEARCH_CTL)
9228	| ((parser_sei_enable & 0x7) << 17));
9229	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9230	WRITE_VREG(NAL_SEARCH_CTL,
9231	READ_VREG(NAL_SEARCH_CTL) |
9232	((parser_dolby_vision_enable & 0x1) << 20));
9233	#endif
9234	config_decode_mode(hevc);
9235	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
9236
9237	/* if (amhevc_loadmc(vh265_mc) < 0) { */
9238	/* amhevc_disable(); */
9239	/* return -EBUSY; */
9240	/* } */
9241	#if 0
9242	for (i = 0; i < (hevc->debug_ptr_size / 2); i += 4) {
9243	int ii;
9244
9245	for (ii = 0; ii < 4; ii++) {
9246	/* hevc->debug_ptr[i+3-ii]=ttt++; */
9247	hevc_print(hevc, 0,
9248	"%04x ", hevc->debug_ptr[i + 3 - ii]);
9249	}
9250	if (((i + ii) & 0xf) == 0)
9251	hevc_print(hevc, 0, "\n");
9252	}
9253	#endif
9254	init_pic_list_hw(hevc);
9255
9256	hevc_print(hevc, 0, "%s HEVC_SHIFT_BYTE_COUNT=0x%x\n", __func__,
9257	READ_VREG(HEVC_SHIFT_BYTE_COUNT));
9258
9259	#ifdef SWAP_HEVC_UCODE
9260	if (!tee_enabled() && hevc->is_swap &&
9261	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
9262	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->mc_dma_handle);
9263	/*pr_info("write swap buffer %x\n", (u32)(hevc->mc_dma_handle));*/
9264	}
9265	#endif
9266	amhevc_start();
9267
9268	/* skip, search next start code */
9269	WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) & (~0x2));
9270	hevc->skip_flag = 1;
9271	#ifdef ERROR_HANDLE_DEBUG
9272	if (dbg_nal_skip_count & 0x20000) {
9273	dbg_nal_skip_count &= ~0x20000;
9274	mutex_unlock(&vh265_mutex);
9275	return ret;
9276	}
9277	#endif
9278	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9279	/* Interrupt Amrisc to excute */
9280	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9281	#ifdef MULTI_INSTANCE_SUPPORT
9282	if (!hevc->m_ins_flag)
9283	#endif
9284	hevc->first_pic_after_recover = 1;
9285	mutex_unlock(&vh265_mutex);
9286	return ret;
9287	}
9288
9289	static void dump_aux_buf(struct hevc_state_s *hevc)
9290	{
9291	int i;
9292	unsigned short *aux_adr =
9293	(unsigned short *)
9294	hevc->aux_addr;
9295	unsigned int aux_size =
9296	(READ_VREG(HEVC_AUX_DATA_SIZE)
9297	>> 16) << 4;
9298
9299	if (hevc->prefix_aux_size > 0) {
9300	hevc_print(hevc, 0,
9301	"prefix aux: (size %d)\n",
9302	aux_size);
9303	for (i = 0; i <
9304	(aux_size >> 1); i++) {
9305	hevc_print_cont(hevc, 0,
9306	"%04x ",
9307	*(aux_adr + i));
9308	if (((i + 1) & 0xf)
9309	== 0)
9310	hevc_print_cont(hevc,
9311	0, "\n");
9312	}
9313	}
9314	if (hevc->suffix_aux_size > 0) {
9315	aux_adr = (unsigned short *)
9316	(hevc->aux_addr +
9317	hevc->prefix_aux_size);
9318	aux_size =
9319	(READ_VREG(HEVC_AUX_DATA_SIZE) & 0xffff)
9320	<< 4;
9321	hevc_print(hevc, 0,
9322	"suffix aux: (size %d)\n",
9323	aux_size);
9324	for (i = 0; i <
9325	(aux_size >> 1); i++) {
9326	hevc_print_cont(hevc, 0,
9327	"%04x ", *(aux_adr + i));
9328	if (((i + 1) & 0xf) == 0)
9329	hevc_print_cont(hevc, 0, "\n");
9330	}
9331	}
9332	}
9333
9334	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9335	static void dolby_get_meta(struct hevc_state_s *hevc)
9336	{
9337	struct vdec_s *vdec = hw_to_vdec(hevc);
9338
9339	if (get_dbg_flag(hevc) &
9340	H265_DEBUG_BUFMGR_MORE)
9341	dump_aux_buf(hevc);
9342	if (vdec->dolby_meta_with_el || vdec->slave) {
9343	set_aux_data(hevc,
9344	hevc->cur_pic, 0, 0);
9345	} else if (vdec->master) {
9346	struct hevc_state_s *hevc_ba =
9347	(struct hevc_state_s *)
9348	vdec->master->private;
9349	/*do not use hevc_ba*/
9350	set_aux_data(hevc,
9351	hevc_ba->cur_pic,
9352	0, 1);
9353	set_aux_data(hevc,
9354	hevc->cur_pic, 0, 2);
9355	}
9356	}
9357	#endif
9358
9359	static void read_decode_info(struct hevc_state_s *hevc)
9360	{
9361	uint32_t decode_info =
9362	READ_HREG(HEVC_DECODE_INFO);
9363	hevc->start_decoding_flag |=
9364	(decode_info & 0xff);
9365	hevc->rps_set_id = (decode_info >> 8) & 0xff;
9366	}
9367
9368	static irqreturn_t vh265_isr_thread_fn(int irq, void *data)
9369	{
9370	struct hevc_state_s *hevc = (struct hevc_state_s *) data;
9371	unsigned int dec_status = hevc->dec_status;
9372	int i, ret;
9373
9374	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9375	struct vdec_s *vdec = hw_to_vdec(hevc);
9376	#endif
9377
9378	if (hevc->eos)
9379	return IRQ_HANDLED;
9380	if (
9381	#ifdef MULTI_INSTANCE_SUPPORT
9382	(!hevc->m_ins_flag) &&
9383	#endif
9384	hevc->error_flag == 1) {
9385	if ((error_handle_policy & 0x10) == 0) {
9386	if (hevc->cur_pic) {
9387	int current_lcu_idx =
9388	READ_VREG(HEVC_PARSER_LCU_START)
9389	& 0xffffff;
9390	if (current_lcu_idx <
9391	((hevc->lcu_x_num*hevc->lcu_y_num)-1))
9392	hevc->cur_pic->error_mark = 1;
9393
9394	}
9395	}
9396	if ((error_handle_policy & 1) == 0) {
9397	hevc->error_skip_nal_count = 1;
9398	/* manual search nal, skip error_skip_nal_count
9399	* of nal and trigger the HEVC_NAL_SEARCH_DONE irq
9400	*/
9401	WRITE_VREG(NAL_SEARCH_CTL,
9402	(error_skip_nal_count << 4) | 0x1);
9403	} else {
9404	hevc->error_skip_nal_count = error_skip_nal_count;
9405	WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */
9406	}
9407	if ((get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE)
9408	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9409	|| vdec->master
9410	|| vdec->slave
9411	#endif
9412	) {
9413	WRITE_VREG(NAL_SEARCH_CTL,
9414	READ_VREG(NAL_SEARCH_CTL) | 0x10000);
9415	}
9416	WRITE_VREG(NAL_SEARCH_CTL,
9417	READ_VREG(NAL_SEARCH_CTL)
9418	| ((parser_sei_enable & 0x7) << 17));
9419	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9420	WRITE_VREG(NAL_SEARCH_CTL,
9421	READ_VREG(NAL_SEARCH_CTL) |
9422	((parser_dolby_vision_enable & 0x1) << 20));
9423	#endif
9424	config_decode_mode(hevc);
9425	/* search new nal */
9426	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9427	/* Interrupt Amrisc to excute */
9428	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9429
9430	/* hevc_print(hevc, 0,
9431	*"%s: error handle\n", __func__);
9432	*/
9433	hevc->error_flag = 2;
9434	return IRQ_HANDLED;
9435	} else if (
9436	#ifdef MULTI_INSTANCE_SUPPORT
9437	(!hevc->m_ins_flag) &&
9438	#endif
9439	hevc->error_flag == 3) {
9440	hevc_print(hevc, 0, "error_flag=3, hevc_recover\n");
9441	hevc_recover(hevc);
9442	hevc->error_flag = 0;
9443
9444	if ((error_handle_policy & 0x10) == 0) {
9445	if (hevc->cur_pic) {
9446	int current_lcu_idx =
9447	READ_VREG(HEVC_PARSER_LCU_START)
9448	& 0xffffff;
9449	if (current_lcu_idx <
9450	((hevc->lcu_x_num*hevc->lcu_y_num)-1))
9451	hevc->cur_pic->error_mark = 1;
9452
9453	}
9454	}
9455	if ((error_handle_policy & 1) == 0) {
9456	/* need skip some data when
9457	* error_flag of 3 is triggered,
9458	*/
9459	/* to avoid hevc_recover() being called
9460	* for many times at the same bitstream position
9461	*/
9462	hevc->error_skip_nal_count = 1;
9463	/* manual search nal, skip error_skip_nal_count
9464	* of nal and trigger the HEVC_NAL_SEARCH_DONE irq
9465	*/
9466	WRITE_VREG(NAL_SEARCH_CTL,
9467	(error_skip_nal_count << 4) | 0x1);
9468	}
9469
9470	if ((error_handle_policy & 0x2) == 0) {
9471	hevc->have_vps = 1;
9472	hevc->have_sps = 1;
9473	hevc->have_pps = 1;
9474	}
9475	return IRQ_HANDLED;
9476	}
9477	if (!hevc->m_ins_flag) {
9478	i = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9479	if ((hevc->shift_byte_count_lo & (1 << 31))
9480	&& ((i & (1 << 31)) == 0))
9481	hevc->shift_byte_count_hi++;
9482	hevc->shift_byte_count_lo = i;
9483	}
9484	#ifdef MULTI_INSTANCE_SUPPORT
9485	mutex_lock(&hevc->chunks_mutex);
9486	if ((dec_status == HEVC_DECPIC_DATA_DONE ||
9487	dec_status == HEVC_FIND_NEXT_PIC_NAL ||
9488	dec_status == HEVC_FIND_NEXT_DVEL_NAL)
9489	&& (hevc->chunk)) {
9490	hevc->cur_pic->pts = hevc->chunk->pts;
9491	hevc->cur_pic->pts64 = hevc->chunk->pts64;
9492	hevc->cur_pic->timestamp = hevc->chunk->timestamp;
9493	}
9494	mutex_unlock(&hevc->chunks_mutex);
9495
9496	if (dec_status == HEVC_DECODE_BUFEMPTY ||
9497	dec_status == HEVC_DECODE_BUFEMPTY2) {
9498	if (hevc->m_ins_flag) {
9499	read_decode_info(hevc);
9500	if (vdec_frame_based(hw_to_vdec(hevc))) {
9501	hevc->empty_flag = 1;
9502	goto pic_done;
9503	} else {
9504	if (
9505	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9506	vdec->master ||
9507	vdec->slave ||
9508	#endif
9509	(data_resend_policy & 0x1)) {
9510	hevc->dec_result = DEC_RESULT_AGAIN;
9511	amhevc_stop();
9512	restore_decode_state(hevc);
9513	} else
9514	hevc->dec_result = DEC_RESULT_GET_DATA;
9515	}
9516	reset_process_time(hevc);
9517	vdec_schedule_work(&hevc->work);
9518	}
9519	return IRQ_HANDLED;
9520	} else if ((dec_status == HEVC_SEARCH_BUFEMPTY) ||
9521	(dec_status == HEVC_NAL_DECODE_DONE)
9522	) {
9523	if (hevc->m_ins_flag) {
9524	read_decode_info(hevc);
9525	if (vdec_frame_based(hw_to_vdec(hevc))) {
9526	/*hevc->dec_result = DEC_RESULT_GET_DATA;*/
9527	hevc->empty_flag = 1;
9528	goto pic_done;
9529	} else {
9530	hevc->dec_result = DEC_RESULT_AGAIN;
9531	amhevc_stop();
9532	restore_decode_state(hevc);
9533	}
9534
9535	reset_process_time(hevc);
9536	vdec_schedule_work(&hevc->work);
9537	}
9538
9539	return IRQ_HANDLED;
9540	} else if (dec_status == HEVC_DECPIC_DATA_DONE) {
9541	if (hevc->m_ins_flag) {
9542	struct PIC_s *pic;
9543	struct PIC_s *pic_display;
9544	int decoded_poc;
9545	#ifdef DETREFILL_ENABLE
9546	if (hevc->is_swap &&
9547	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
9548	if (hevc->detbuf_adr_virt && hevc->delrefill_check
9549	&& READ_VREG(HEVC_SAO_DBG_MODE0))
9550	hevc->delrefill_check = 2;
9551	}
9552	#endif
9553	hevc->empty_flag = 0;
9554	pic_done:
9555	if (input_frame_based(hw_to_vdec(hevc)) &&
9556	frmbase_cont_bitlevel != 0 &&
9557	(hevc->decode_size > READ_VREG(HEVC_SHIFT_BYTE_COUNT)) &&
9558	(hevc->decode_size - (READ_VREG(HEVC_SHIFT_BYTE_COUNT))
9559	> frmbase_cont_bitlevel)) {
9560	/*handle the case: multi pictures in one packet*/
9561	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
9562	"%s has more data index= %d, size=0x%x shiftcnt=0x%x)\n",
9563	__func__,
9564	hevc->decode_idx, hevc->decode_size,
9565	READ_VREG(HEVC_SHIFT_BYTE_COUNT));
9566	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9567	start_process_time(hevc);
9568	return IRQ_HANDLED;
9569	}
9570
9571	read_decode_info(hevc);
9572	get_picture_qos_info(hevc);
9573	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9574	hevc->start_parser_type = 0;
9575	hevc->switch_dvlayer_flag = 0;
9576	#endif
9577	hevc->decoded_poc = hevc->curr_POC;
9578	hevc->decoding_pic = NULL;
9579	hevc->dec_result = DEC_RESULT_DONE;
9580	#ifdef DETREFILL_ENABLE
9581	if (hevc->is_swap &&
9582	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
9583	if (hevc->delrefill_check != 2)
9584	#endif
9585
9586	amhevc_stop();
9587
9588	reset_process_time(hevc);
9589
9590	if (hevc->vf_pre_count == 0) {
9591	decoded_poc = hevc->curr_POC;
9592	pic = get_pic_by_POC(hevc, decoded_poc);
9593	if (pic && (pic->POC != INVALID_POC)) {
9594	/*PB skip control */
9595	if (pic->error_mark == 0
9596	&& hevc->PB_skip_mode == 1) {
9597	/* start decoding after
9598	* first I
9599	*/
9600	hevc->ignore_bufmgr_error |= 0x1;
9601	}
9602	if (hevc->ignore_bufmgr_error & 1) {
9603	if (hevc->PB_skip_count_after_decoding > 0) {
9604	hevc->PB_skip_count_after_decoding--;
9605	} else {
9606	/* start displaying */
9607	hevc->ignore_bufmgr_error |= 0x2;
9608	}
9609	}
9610	if (hevc->mmu_enable
9611	&& ((hevc->double_write_mode & 0x10) == 0)) {
9612	if (!hevc->m_ins_flag) {
9613	hevc->used_4k_num =
9614	READ_VREG(HEVC_SAO_MMU_STATUS) >> 16;
9615
9616	if ((!is_skip_decoding(hevc, pic)) &&
9617	(hevc->used_4k_num >= 0) &&
9618	(hevc->cur_pic->scatter_alloc
9619	== 1)) {
9620	hevc_print(hevc,
9621	H265_DEBUG_BUFMGR_MORE,
9622	"%s pic index %d scatter_alloc %d page_start %d\n",
9623	"decoder_mmu_box_free_idx_tail",
9624	hevc->cur_pic->index,
9625	hevc->cur_pic->scatter_alloc,
9626	hevc->used_4k_num);
9627	decoder_mmu_box_free_idx_tail(
9628	hevc->mmu_box,
9629	hevc->cur_pic->index,
9630	hevc->used_4k_num);
9631	hevc->cur_pic->scatter_alloc
9632	= 2;
9633	}
9634	hevc->used_4k_num = -1;
9635	}
9636	}
9637
9638	pic->output_mark = 1;
9639	pic->recon_mark = 1;
9640	}
9641	check_pic_decoded_error(hevc,
9642	READ_VREG(HEVC_PARSER_LCU_START) & 0xffffff);
9643	if (hevc->cur_pic != NULL &&
9644	(READ_VREG(HEVC_PARSER_LCU_START) & 0xffffff) == 0
9645	&& (hevc->lcu_x_num * hevc->lcu_y_num != 1))
9646	hevc->cur_pic->error_mark = 1;
9647	force_output:
9648	pic_display = output_pic(hevc, 1);
9649	if (pic_display) {
9650	if ((pic_display->error_mark &&
9651	((hevc->ignore_bufmgr_error &
9652	0x2) == 0))
9653	|| (get_dbg_flag(hevc) &
9654	H265_DEBUG_DISPLAY_CUR_FRAME)
9655	|| (get_dbg_flag(hevc) &
9656	H265_DEBUG_NO_DISPLAY)) {
9657	pic_display->output_ready = 0;
9658	if (get_dbg_flag(hevc) &
9659	H265_DEBUG_BUFMGR) {
9660	hevc_print(hevc, 0,
9661	"[BM] Display: POC %d, ",
9662	pic_display->POC);
9663	hevc_print_cont(hevc, 0,
9664	"decoding index %d ==> ",
9665	pic_display->
9666	decode_idx);
9667	hevc_print_cont(hevc, 0,
9668	"Debug or err,recycle it\n");
9669	}
9670	} else {
9671	if (pic_display->
9672	slice_type != 2) {
9673	pic_display->output_ready = 0;
9674	} else {
9675	prepare_display_buf
9676	(hevc,
9677	pic_display);
9678	hevc->first_pic_flag = 1;
9679	}
9680	}
9681	}
9682	}
9683
9684	vdec_schedule_work(&hevc->work);
9685	}
9686
9687	return IRQ_HANDLED;
9688	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9689	} else if (dec_status == HEVC_FIND_NEXT_PIC_NAL ||
9690	dec_status == HEVC_FIND_NEXT_DVEL_NAL) {
9691	if (hevc->m_ins_flag) {
9692	unsigned char next_parser_type =
9693	READ_HREG(CUR_NAL_UNIT_TYPE) & 0xff;
9694	read_decode_info(hevc);
9695
9696	if (vdec->slave &&
9697	dec_status == HEVC_FIND_NEXT_DVEL_NAL) {
9698	/*cur is base, found enhance*/
9699	struct hevc_state_s *hevc_el =
9700	(struct hevc_state_s *)
9701	vdec->slave->private;
9702	hevc->switch_dvlayer_flag = 1;
9703	hevc->no_switch_dvlayer_count = 0;
9704	hevc_el->start_parser_type =
9705	next_parser_type;
9706	hevc_print(hevc, H265_DEBUG_DV,
9707	"switch (poc %d) to el\n",
9708	hevc->cur_pic ?
9709	hevc->cur_pic->POC :
9710	INVALID_POC);
9711	} else if (vdec->master &&
9712	dec_status == HEVC_FIND_NEXT_PIC_NAL) {
9713	/*cur is enhance, found base*/
9714	struct hevc_state_s *hevc_ba =
9715	(struct hevc_state_s *)
9716	vdec->master->private;
9717	hevc->switch_dvlayer_flag = 1;
9718	hevc->no_switch_dvlayer_count = 0;
9719	hevc_ba->start_parser_type =
9720	next_parser_type;
9721	hevc_print(hevc, H265_DEBUG_DV,
9722	"switch (poc %d) to bl\n",
9723	hevc->cur_pic ?
9724	hevc->cur_pic->POC :
9725	INVALID_POC);
9726	} else {
9727	hevc->switch_dvlayer_flag = 0;
9728	hevc->start_parser_type =
9729	next_parser_type;
9730	hevc->no_switch_dvlayer_count++;
9731	hevc_print(hevc, H265_DEBUG_DV,
9732	"%s: no_switch_dvlayer_count = %d\n",
9733	vdec->master ? "el" : "bl",
9734	hevc->no_switch_dvlayer_count);
9735	if (vdec->slave &&
9736	dolby_el_flush_th != 0 &&
9737	hevc->no_switch_dvlayer_count >
9738	dolby_el_flush_th) {
9739	struct hevc_state_s *hevc_el =
9740	(struct hevc_state_s *)
9741	vdec->slave->private;
9742	struct PIC_s *el_pic;
9743	check_pic_decoded_error(hevc_el,
9744	hevc_el->pic_decoded_lcu_idx);
9745	el_pic = get_pic_by_POC(hevc_el,
9746	hevc_el->curr_POC);
9747	hevc_el->curr_POC = INVALID_POC;
9748	hevc_el->m_pocRandomAccess = MAX_INT;
9749	flush_output(hevc_el, el_pic);
9750	hevc_el->decoded_poc = INVALID_POC; /*
9751	already call flush_output*/
9752	hevc_el->decoding_pic = NULL;
9753	hevc->no_switch_dvlayer_count = 0;
9754	if (get_dbg_flag(hevc) & H265_DEBUG_DV)
9755	hevc_print(hevc, 0,
9756	"no el anymore, flush_output el\n");
9757	}
9758	}
9759	hevc->decoded_poc = hevc->curr_POC;
9760	hevc->decoding_pic = NULL;
9761	hevc->dec_result = DEC_RESULT_DONE;
9762	amhevc_stop();
9763	reset_process_time(hevc);
9764	if (aux_data_is_avaible(hevc))
9765	dolby_get_meta(hevc);
9766	if(hevc->cur_pic->slice_type == 2 &&
9767	hevc->vf_pre_count == 0) {
9768	hevc_print(hevc, 0,
9769	"first slice_type %x no_switch_dvlayer_count %x\n",
9770	hevc->cur_pic->slice_type,
9771	hevc->no_switch_dvlayer_count);
9772	goto force_output;
9773	}
9774	vdec_schedule_work(&hevc->work);
9775	}
9776
9777	return IRQ_HANDLED;
9778	#endif
9779	}
9780
9781	#endif
9782
9783	if (dec_status == HEVC_SEI_DAT) {
9784	if (!hevc->m_ins_flag) {
9785	int payload_type =
9786	READ_HREG(CUR_NAL_UNIT_TYPE) & 0xffff;
9787	int payload_size =
9788	(READ_HREG(CUR_NAL_UNIT_TYPE) >> 16) & 0xffff;
9789	process_nal_sei(hevc,
9790	payload_type, payload_size);
9791	}
9792	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_SEI_DAT_DONE);
9793	} else if (dec_status == HEVC_NAL_SEARCH_DONE) {
9794	int naltype = READ_HREG(CUR_NAL_UNIT_TYPE);
9795	int parse_type = HEVC_DISCARD_NAL;
9796
9797	hevc->error_watchdog_count = 0;
9798	hevc->error_skip_nal_wt_cnt = 0;
9799	#ifdef MULTI_INSTANCE_SUPPORT
9800	if (hevc->m_ins_flag)
9801	reset_process_time(hevc);
9802	#endif
9803	if (slice_parse_begin > 0 &&
9804	get_dbg_flag(hevc) & H265_DEBUG_DISCARD_NAL) {
9805	hevc_print(hevc, 0,
9806	"nal type %d, discard %d\n", naltype,
9807	slice_parse_begin);
9808	if (naltype <= NAL_UNIT_CODED_SLICE_CRA)
9809	slice_parse_begin--;
9810	}
9811	if (naltype == NAL_UNIT_EOS) {
9812	struct PIC_s *pic;
9813
9814	hevc_print(hevc, 0, "get NAL_UNIT_EOS, flush output\n");
9815	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9816	if ((vdec->master || vdec->slave) &&
9817	aux_data_is_avaible(hevc)) {
9818	if (hevc->decoding_pic)
9819	dolby_get_meta(hevc);
9820	}
9821	#endif
9822	check_pic_decoded_error(hevc,
9823	hevc->pic_decoded_lcu_idx);
9824	pic = get_pic_by_POC(hevc, hevc->curr_POC);
9825	hevc->curr_POC = INVALID_POC;
9826	/* add to fix RAP_B_Bossen_1 */
9827	hevc->m_pocRandomAccess = MAX_INT;
9828	flush_output(hevc, pic);
9829	clear_poc_flag(hevc);
9830	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_DISCARD_NAL);
9831	/* Interrupt Amrisc to excute */
9832	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9833	#ifdef MULTI_INSTANCE_SUPPORT
9834	if (hevc->m_ins_flag) {
9835	hevc->decoded_poc = INVALID_POC; /*
9836	already call flush_output*/
9837	hevc->decoding_pic = NULL;
9838	hevc->dec_result = DEC_RESULT_DONE;
9839	amhevc_stop();
9840
9841	vdec_schedule_work(&hevc->work);
9842	}
9843	#endif
9844	return IRQ_HANDLED;
9845	}
9846
9847	if (
9848	#ifdef MULTI_INSTANCE_SUPPORT
9849	(!hevc->m_ins_flag) &&
9850	#endif
9851	hevc->error_skip_nal_count > 0) {
9852	hevc_print(hevc, 0,
9853	"nal type %d, discard %d\n", naltype,
9854	hevc->error_skip_nal_count);
9855	hevc->error_skip_nal_count--;
9856	if (hevc->error_skip_nal_count == 0) {
9857	hevc_recover(hevc);
9858	hevc->error_flag = 0;
9859	if ((error_handle_policy & 0x2) == 0) {
9860	hevc->have_vps = 1;
9861	hevc->have_sps = 1;
9862	hevc->have_pps = 1;
9863	}
9864	return IRQ_HANDLED;
9865	}
9866	} else if (naltype == NAL_UNIT_VPS) {
9867	parse_type = HEVC_NAL_UNIT_VPS;
9868	hevc->have_vps = 1;
9869	#ifdef ERROR_HANDLE_DEBUG
9870	if (dbg_nal_skip_flag & 1)
9871	parse_type = HEVC_DISCARD_NAL;
9872	#endif
9873	} else if (hevc->have_vps) {
9874	if (naltype == NAL_UNIT_SPS) {
9875	parse_type = HEVC_NAL_UNIT_SPS;
9876	hevc->have_sps = 1;
9877	#ifdef ERROR_HANDLE_DEBUG
9878	if (dbg_nal_skip_flag & 2)
9879	parse_type = HEVC_DISCARD_NAL;
9880	#endif
9881	} else if (naltype == NAL_UNIT_PPS) {
9882	parse_type = HEVC_NAL_UNIT_PPS;
9883	hevc->have_pps = 1;
9884	#ifdef ERROR_HANDLE_DEBUG
9885	if (dbg_nal_skip_flag & 4)
9886	parse_type = HEVC_DISCARD_NAL;
9887	#endif
9888	} else if (hevc->have_sps && hevc->have_pps) {
9889	int seg = HEVC_NAL_UNIT_CODED_SLICE_SEGMENT;
9890
9891	if ((naltype == NAL_UNIT_CODED_SLICE_IDR) ||
9892	(naltype ==
9893	NAL_UNIT_CODED_SLICE_IDR_N_LP)
9894	|| (naltype ==
9895	NAL_UNIT_CODED_SLICE_CRA)
9896	|| (naltype ==
9897	NAL_UNIT_CODED_SLICE_BLA)
9898	|| (naltype ==
9899	NAL_UNIT_CODED_SLICE_BLANT)
9900	|| (naltype ==
9901	NAL_UNIT_CODED_SLICE_BLA_N_LP)
9902	) {
9903	if (slice_parse_begin > 0) {
9904	hevc_print(hevc, 0,
9905	"discard %d, for debugging\n",
9906	slice_parse_begin);
9907	slice_parse_begin--;
9908	} else {
9909	parse_type = seg;
9910	}
9911	hevc->have_valid_start_slice = 1;
9912	} else if (naltype <=
9913	NAL_UNIT_CODED_SLICE_CRA
9914	&& (hevc->have_valid_start_slice
9915	|| (hevc->PB_skip_mode != 3))) {
9916	if (slice_parse_begin > 0) {
9917	hevc_print(hevc, 0,
9918	"discard %d, dd\n",
9919	slice_parse_begin);
9920	slice_parse_begin--;
9921	} else
9922	parse_type = seg;
9923
9924	}
9925	}
9926	}
9927	if (hevc->have_vps && hevc->have_sps && hevc->have_pps
9928	&& hevc->have_valid_start_slice &&
9929	hevc->error_flag == 0) {
9930	if ((get_dbg_flag(hevc) &
9931	H265_DEBUG_MAN_SEARCH_NAL) == 0
9932	/* && (!hevc->m_ins_flag)*/) {
9933	/* auot parser NAL; do not check
9934	*vps/sps/pps/idr
9935	*/
9936	WRITE_VREG(NAL_SEARCH_CTL, 0x2);
9937	}
9938
9939	if ((get_dbg_flag(hevc) &
9940	H265_DEBUG_NO_EOS_SEARCH_DONE)
9941	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9942	|| vdec->master
9943	|| vdec->slave
9944	#endif
9945	) {
9946	WRITE_VREG(NAL_SEARCH_CTL,
9947	READ_VREG(NAL_SEARCH_CTL) |
9948	0x10000);
9949	}
9950	WRITE_VREG(NAL_SEARCH_CTL,
9951	READ_VREG(NAL_SEARCH_CTL)
9952	| ((parser_sei_enable & 0x7) << 17));
9953	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
9954	WRITE_VREG(NAL_SEARCH_CTL,
9955	READ_VREG(NAL_SEARCH_CTL) |
9956	((parser_dolby_vision_enable & 0x1) << 20));
9957	#endif
9958	config_decode_mode(hevc);
9959	}
9960
9961	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) {
9962	hevc_print(hevc, 0,
9963	"naltype = %d parse_type %d\n %d %d %d %d\n",
9964	naltype, parse_type, hevc->have_vps,
9965	hevc->have_sps, hevc->have_pps,
9966	hevc->have_valid_start_slice);
9967	}
9968
9969	WRITE_VREG(HEVC_DEC_STATUS_REG, parse_type);
9970	/* Interrupt Amrisc to excute */
9971	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
9972	#ifdef MULTI_INSTANCE_SUPPORT
9973	if (hevc->m_ins_flag)
9974	start_process_time(hevc);
9975	#endif
9976	} else if (dec_status == HEVC_SLICE_SEGMENT_DONE) {
9977	#ifdef MULTI_INSTANCE_SUPPORT
9978	if (hevc->m_ins_flag) {
9979	reset_process_time(hevc);
9980	read_decode_info(hevc);
9981
9982	}
9983	#endif
9984	if (hevc->start_decoding_time > 0) {
9985	u32 process_time = 1000*
9986	(jiffies - hevc->start_decoding_time)/HZ;
9987	if (process_time > max_decoding_time)
9988	max_decoding_time = process_time;
9989	}
9990
9991	hevc->error_watchdog_count = 0;
9992	if (hevc->pic_list_init_flag == 2) {
9993	hevc->pic_list_init_flag = 3;
9994	hevc_print(hevc, 0, "set pic_list_init_flag to 3\n");
9995	} else if (hevc->wait_buf == 0) {
9996	u32 vui_time_scale;
9997	u32 vui_num_units_in_tick;
9998	unsigned char reconfig_flag = 0;
9999
10000	if (get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG)
10001	get_rpm_param(&hevc->param);
10002	else {
10003
10004	for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10005	int ii;
10006
10007	for (ii = 0; ii < 4; ii++) {
10008	hevc->param.l.data[i + ii] =
10009	hevc->rpm_ptr[i + 3
10010	- ii];
10011	}
10012	}
10013	#ifdef SEND_LMEM_WITH_RPM
10014	check_head_error(hevc);
10015	#endif
10016	}
10017	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) {
10018	hevc_print(hevc, 0,
10019	"rpm_param: (%d)\n", hevc->slice_idx);
10020	hevc->slice_idx++;
10021	for (i = 0; i < (RPM_END - RPM_BEGIN); i++) {
10022	hevc_print_cont(hevc, 0,
10023	"%04x ", hevc->param.l.data[i]);
10024	if (((i + 1) & 0xf) == 0)
10025	hevc_print_cont(hevc, 0, "\n");
10026	}
10027
10028	hevc_print(hevc, 0,
10029	"vui_timing_info: %x, %x, %x, %x\n",
10030	hevc->param.p.vui_num_units_in_tick_hi,
10031	hevc->param.p.vui_num_units_in_tick_lo,
10032	hevc->param.p.vui_time_scale_hi,
10033	hevc->param.p.vui_time_scale_lo);
10034	}
10035
10036	if (hevc->is_used_v4l) {
10037	struct aml_vcodec_ctx *ctx =
10038	(struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
10039
10040	if (ctx->param_sets_from_ucode && !hevc->v4l_params_parsed) {
10041	struct aml_vdec_ps_infos ps;
10042
10043	hevc->frame_width = hevc->param.p.pic_width_in_luma_samples;
10044	hevc->frame_height = hevc->param.p.pic_height_in_luma_samples;
10045	ps.visible_width = hevc->frame_width;
10046	ps.visible_height = hevc->frame_height;
10047	ps.coded_width = ALIGN(hevc->frame_width, 32);
10048	ps.coded_height = ALIGN(hevc->frame_height, 32);
10049	ps.dpb_size = get_work_pic_num(hevc);
10050	hevc->v4l_params_parsed = true;
10051	/*notice the v4l2 codec.*/
10052	vdec_v4l_set_ps_infos(ctx, &ps);
10053	}
10054	}
10055
10056	if (
10057	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10058	vdec->master == NULL &&
10059	vdec->slave == NULL &&
10060	#endif
10061	aux_data_is_avaible(hevc)
10062	) {
10063
10064	if (get_dbg_flag(hevc) &
10065	H265_DEBUG_BUFMGR_MORE)
10066	dump_aux_buf(hevc);
10067	}
10068
10069	vui_time_scale =
10070	(u32)(hevc->param.p.vui_time_scale_hi << 16) |
10071	hevc->param.p.vui_time_scale_lo;
10072	vui_num_units_in_tick =
10073	(u32)(hevc->param.
10074	p.vui_num_units_in_tick_hi << 16) |
10075	hevc->param.
10076	p.vui_num_units_in_tick_lo;
10077	if (hevc->bit_depth_luma !=
10078	((hevc->param.p.bit_depth & 0xf) + 8)) {
10079	reconfig_flag = 1;
10080	hevc_print(hevc, 0, "Bit depth luma = %d\n",
10081	(hevc->param.p.bit_depth & 0xf) + 8);
10082	}
10083	if (hevc->bit_depth_chroma !=
10084	(((hevc->param.p.bit_depth >> 4) & 0xf) + 8)) {
10085	reconfig_flag = 1;
10086	hevc_print(hevc, 0, "Bit depth chroma = %d\n",
10087	((hevc->param.p.bit_depth >> 4) &
10088	0xf) + 8);
10089	}
10090	hevc->bit_depth_luma =
10091	(hevc->param.p.bit_depth & 0xf) + 8;
10092	hevc->bit_depth_chroma =
10093	((hevc->param.p.bit_depth >> 4) & 0xf) + 8;
10094	bit_depth_luma = hevc->bit_depth_luma;
10095	bit_depth_chroma = hevc->bit_depth_chroma;
10096	#ifdef SUPPORT_10BIT
10097	if (hevc->bit_depth_luma == 8 &&
10098	hevc->bit_depth_chroma == 8 &&
10099	enable_mem_saving)
10100	hevc->mem_saving_mode = 1;
10101	else
10102	hevc->mem_saving_mode = 0;
10103	#endif
10104	if (reconfig_flag &&
10105	(get_double_write_mode(hevc) & 0x10) == 0)
10106	init_decode_head_hw(hevc);
10107
10108	if ((vui_time_scale != 0)
10109	&& (vui_num_units_in_tick != 0)) {
10110	hevc->frame_dur =
10111	div_u64(96000ULL *
10112	vui_num_units_in_tick,
10113	vui_time_scale);
10114	if (hevc->get_frame_dur != true)
10115	vdec_schedule_work(
10116	&hevc->notify_work);
10117
10118	hevc->get_frame_dur = true;
10119	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10120	gvs->frame_dur = hevc->frame_dur;
10121	#endif
10122	}
10123
10124	if (hevc->video_signal_type !=
10125	((hevc->param.p.video_signal_type << 16)
10126	| hevc->param.p.color_description)) {
10127	u32 v = hevc->param.p.video_signal_type;
10128	u32 c = hevc->param.p.color_description;
10129	#if 0
10130	if (v & 0x2000) {
10131	hevc_print(hevc, 0,
10132	"video_signal_type present:\n");
10133	hevc_print(hevc, 0, " %s %s\n",
10134	video_format_names[(v >> 10) & 7],
10135	((v >> 9) & 1) ?
10136	"full_range" : "limited");
10137	if (v & 0x100) {
10138	hevc_print(hevc, 0,
10139	" color_description present:\n");
10140	hevc_print(hevc, 0,
10141	" color_primarie = %s\n",
10142	color_primaries_names
10143	[v & 0xff]);
10144	hevc_print(hevc, 0,
10145	" transfer_characteristic = %s\n",
10146	transfer_characteristics_names
10147	[(c >> 8) & 0xff]);
10148	hevc_print(hevc, 0,
10149	" matrix_coefficient = %s\n",
10150	matrix_coeffs_names[c & 0xff]);
10151	}
10152	}
10153	#endif
10154	hevc->video_signal_type = (v << 16) | c;
10155	video_signal_type = hevc->video_signal_type;
10156	}
10157
10158	if (use_cma &&
10159	(hevc->param.p.slice_segment_address == 0)
10160	&& (hevc->pic_list_init_flag == 0)) {
10161	int log = hevc->param.p.log2_min_coding_block_size_minus3;
10162	int log_s = hevc->param.p.log2_diff_max_min_coding_block_size;
10163
10164	hevc->pic_w = hevc->param.p.pic_width_in_luma_samples;
10165	hevc->pic_h = hevc->param.p.pic_height_in_luma_samples;
10166	hevc->lcu_size = 1 << (log + 3 + log_s);
10167	hevc->lcu_size_log2 = log2i(hevc->lcu_size);
10168	if (hevc->pic_w == 0 || hevc->pic_h == 0
10169	|| hevc->lcu_size == 0
10170	|| is_oversize(hevc->pic_w, hevc->pic_h)
10171	|| (!hevc->skip_first_nal &&
10172	(hevc->pic_h == 96) && (hevc->pic_w == 160))) {
10173	/* skip search next start code */
10174	WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG)
10175	& (~0x2));
10176	if ( !hevc->skip_first_nal &&
10177	(hevc->pic_h == 96) && (hevc->pic_w == 160))
10178	hevc->skip_first_nal = 1;
10179	hevc->skip_flag = 1;
10180	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10181	/* Interrupt Amrisc to excute */
10182	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
10183	#ifdef MULTI_INSTANCE_SUPPORT
10184	if (hevc->m_ins_flag)
10185	start_process_time(hevc);
10186	#endif
10187	} else {
10188	hevc->sps_num_reorder_pics_0 =
10189	hevc->param.p.sps_num_reorder_pics_0;
10190	hevc->pic_list_init_flag = 1;
10191	#ifdef MULTI_INSTANCE_SUPPORT
10192	if (hevc->m_ins_flag) {
10193	vdec_schedule_work(&hevc->work);
10194	} else
10195	#endif
10196	up(&h265_sema);
10197	hevc_print(hevc, 0, "set pic_list_init_flag 1\n");
10198	}
10199	return IRQ_HANDLED;
10200	}
10201
10202	}
10203	ret =
10204	hevc_slice_segment_header_process(hevc,
10205	&hevc->param, decode_pic_begin);
10206	if (ret < 0) {
10207	#ifdef MULTI_INSTANCE_SUPPORT
10208	if (hevc->m_ins_flag) {
10209	hevc->wait_buf = 0;
10210	hevc->dec_result = DEC_RESULT_AGAIN;
10211	amhevc_stop();
10212	restore_decode_state(hevc);
10213	reset_process_time(hevc);
10214	vdec_schedule_work(&hevc->work);
10215	return IRQ_HANDLED;
10216	}
10217	#else
10218	;
10219	#endif
10220	} else if (ret == 0) {
10221	if ((hevc->new_pic) && (hevc->cur_pic)) {
10222	hevc->cur_pic->stream_offset =
10223	READ_VREG(HEVC_SHIFT_BYTE_COUNT);
10224	hevc_print(hevc, H265_DEBUG_OUT_PTS,
10225	"read stream_offset = 0x%x\n",
10226	hevc->cur_pic->stream_offset);
10227	hevc->cur_pic->aspect_ratio_idc =
10228	hevc->param.p.aspect_ratio_idc;
10229	hevc->cur_pic->sar_width =
10230	hevc->param.p.sar_width;
10231	hevc->cur_pic->sar_height =
10232	hevc->param.p.sar_height;
10233	}
10234
10235	WRITE_VREG(HEVC_DEC_STATUS_REG,
10236	HEVC_CODED_SLICE_SEGMENT_DAT);
10237	/* Interrupt Amrisc to excute */
10238	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
10239
10240	hevc->start_decoding_time = jiffies;
10241	#ifdef MULTI_INSTANCE_SUPPORT
10242	if (hevc->m_ins_flag)
10243	start_process_time(hevc);
10244	#endif
10245	#if 1
10246	/*to do..., copy aux data to hevc->cur_pic*/
10247	#endif
10248	#ifdef MULTI_INSTANCE_SUPPORT
10249	} else if (hevc->m_ins_flag) {
10250	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
10251	"%s, bufmgr ret %d skip, DEC_RESULT_DONE\n",
10252	__func__, ret);
10253	hevc->decoded_poc = INVALID_POC;
10254	hevc->decoding_pic = NULL;
10255	hevc->dec_result = DEC_RESULT_DONE;
10256	amhevc_stop();
10257	reset_process_time(hevc);
10258	vdec_schedule_work(&hevc->work);
10259	#endif
10260	} else {
10261	/* skip, search next start code */
10262	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10263	gvs->drop_frame_count++;
10264	#endif
10265	WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) & (~0x2));
10266	hevc->skip_flag = 1;
10267	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10268	/* Interrupt Amrisc to excute */
10269	WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
10270	}
10271
10272	} else if (dec_status == HEVC_DECODE_OVER_SIZE) {
10273	hevc_print(hevc, 0 , "hevc decode oversize !!\n");
10274	#ifdef MULTI_INSTANCE_SUPPORT
10275	if (!hevc->m_ins_flag)
10276	debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC |
10277	H265_DEBUG_DIS_SYS_ERROR_PROC);
10278	#endif
10279	hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
10280	}
10281	return IRQ_HANDLED;
10282	}
10283
10284	static void wait_hevc_search_done(struct hevc_state_s *hevc)
10285	{
10286	int count = 0;
10287	WRITE_VREG(HEVC_SHIFT_STATUS, 0);
10288	while (READ_VREG(HEVC_STREAM_CONTROL) & 0x2) {
10289	msleep(20);
10290	count++;
10291	if (count > 100) {
10292	hevc_print(hevc, 0, "%s timeout\n", __func__);
10293	break;
10294	}
10295	}
10296	}
10297	static irqreturn_t vh265_isr(int irq, void *data)
10298	{
10299	int i, temp;
10300	unsigned int dec_status;
10301	struct hevc_state_s *hevc = (struct hevc_state_s *)data;
10302	u32 debug_tag;
10303	dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
10304
10305	if (hevc->init_flag == 0)
10306	return IRQ_HANDLED;
10307	hevc->dec_status = dec_status;
10308	if (is_log_enable(hevc))
10309	add_log(hevc,
10310	"isr: status = 0x%x dec info 0x%x lcu 0x%x shiftbyte 0x%x shiftstatus 0x%x",
10311	dec_status, READ_HREG(HEVC_DECODE_INFO),
10312	READ_VREG(HEVC_MPRED_CURR_LCU),
10313	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
10314	READ_VREG(HEVC_SHIFT_STATUS));
10315
10316	if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR)
10317	hevc_print(hevc, 0,
10318	"265 isr dec status = 0x%x dec info 0x%x shiftbyte 0x%x shiftstatus 0x%x\n",
10319	dec_status, READ_HREG(HEVC_DECODE_INFO),
10320	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
10321	READ_VREG(HEVC_SHIFT_STATUS));
10322
10323	debug_tag = READ_HREG(DEBUG_REG1);
10324	if (debug_tag & 0x10000) {
10325	hevc_print(hevc, 0,
10326	"LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
10327
10328	if (hevc->mmu_enable)
10329	temp = 0x500;
10330	else
10331	temp = 0x400;
10332	for (i = 0; i < temp; i += 4) {
10333	int ii;
10334	if ((i & 0xf) == 0)
10335	hevc_print_cont(hevc, 0, "%03x: ", i);
10336	for (ii = 0; ii < 4; ii++) {
10337	hevc_print_cont(hevc, 0, "%04x ",
10338	hevc->lmem_ptr[i + 3 - ii]);
10339	}
10340	if (((i + ii) & 0xf) == 0)
10341	hevc_print_cont(hevc, 0, "\n");
10342	}
10343
10344	if (((udebug_pause_pos & 0xffff)
10345	== (debug_tag & 0xffff)) &&
10346	(udebug_pause_decode_idx == 0 ||
10347	udebug_pause_decode_idx == hevc->decode_idx) &&
10348	(udebug_pause_val == 0 ||
10349	udebug_pause_val == READ_HREG(DEBUG_REG2))) {
10350	udebug_pause_pos &= 0xffff;
10351	hevc->ucode_pause_pos = udebug_pause_pos;
10352	}
10353	else if (debug_tag & 0x20000)
10354	hevc->ucode_pause_pos = 0xffffffff;
10355	if (hevc->ucode_pause_pos)
10356	reset_process_time(hevc);
10357	else
10358	WRITE_HREG(DEBUG_REG1, 0);
10359	} else if (debug_tag != 0) {
10360	hevc_print(hevc, 0,
10361	"dbg%x: %x l/w/r %x %x %x\n", READ_HREG(DEBUG_REG1),
10362	READ_HREG(DEBUG_REG2),
10363	READ_VREG(HEVC_STREAM_LEVEL),
10364	READ_VREG(HEVC_STREAM_WR_PTR),
10365	READ_VREG(HEVC_STREAM_RD_PTR));
10366	if (((udebug_pause_pos & 0xffff)
10367	== (debug_tag & 0xffff)) &&
10368	(udebug_pause_decode_idx == 0 ||
10369	udebug_pause_decode_idx == hevc->decode_idx) &&
10370	(udebug_pause_val == 0 ||
10371	udebug_pause_val == READ_HREG(DEBUG_REG2))) {
10372	udebug_pause_pos &= 0xffff;
10373	hevc->ucode_pause_pos = udebug_pause_pos;
10374	}
10375	if (hevc->ucode_pause_pos)
10376	reset_process_time(hevc);
10377	else
10378	WRITE_HREG(DEBUG_REG1, 0);
10379	return IRQ_HANDLED;
10380	}
10381
10382
10383	if (hevc->pic_list_init_flag == 1)
10384	return IRQ_HANDLED;
10385
10386	if (!hevc->m_ins_flag) {
10387	if (dec_status == HEVC_OVER_DECODE) {
10388	hevc->over_decode = 1;
10389	hevc_print(hevc, 0,
10390	"isr: over decode\n"),
10391	WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
10392	return IRQ_HANDLED;
10393	}
10394	}
10395
10396	return IRQ_WAKE_THREAD;
10397
10398	}
10399
10400	static void vh265_set_clk(struct work_struct *work)
10401	{
10402	struct hevc_state_s *hevc = container_of(work,
10403	struct hevc_state_s, set_clk_work);
10404
10405	int fps = 96000 / hevc->frame_dur;
10406
10407	if (hevc_source_changed(VFORMAT_HEVC,
10408	hevc->frame_width, hevc->frame_height, fps) > 0)
10409	hevc->saved_resolution = hevc->frame_width *
10410	hevc->frame_height * fps;
10411	}
10412
10413	static void vh265_check_timer_func(unsigned long arg)
10414	{
10415	struct hevc_state_s *hevc = (struct hevc_state_s *)arg;
10416	struct timer_list *timer = &hevc->timer;
10417	unsigned char empty_flag;
10418	unsigned int buf_level;
10419
10420	enum receviver_start_e state = RECEIVER_INACTIVE;
10421
10422	if (hevc->init_flag == 0) {
10423	if (hevc->stat & STAT_TIMER_ARM) {
10424	mod_timer(&hevc->timer, jiffies + PUT_INTERVAL);
10425	}
10426	return;
10427	}
10428	#ifdef MULTI_INSTANCE_SUPPORT
10429	if (hevc->m_ins_flag &&
10430	(get_dbg_flag(hevc) &
10431	H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP) == 0 &&
10432	hw_to_vdec(hevc)->next_status ==
10433	VDEC_STATUS_DISCONNECTED) {
10434	hevc->dec_result = DEC_RESULT_FORCE_EXIT;
10435	vdec_schedule_work(&hevc->work);
10436	hevc_print(hevc,
10437	0, "vdec requested to be disconnected\n");
10438	return;
10439	}
10440
10441	if (hevc->m_ins_flag) {
10442	if ((input_frame_based(hw_to_vdec(hevc)) ||
10443	(READ_VREG(HEVC_STREAM_LEVEL) > 0xb0)) &&
10444	((get_dbg_flag(hevc) &
10445	H265_DEBUG_DIS_LOC_ERROR_PROC) == 0) &&
10446	(decode_timeout_val > 0) &&
10447	(hevc->start_process_time > 0) &&
10448	((1000 * (jiffies - hevc->start_process_time) / HZ)
10449	> decode_timeout_val)
10450	) {
10451	u32 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
10452	int current_lcu_idx =
10453	READ_VREG(HEVC_PARSER_LCU_START)&0xffffff;
10454	if (dec_status == HEVC_CODED_SLICE_SEGMENT_DAT) {
10455	if (hevc->last_lcu_idx == current_lcu_idx) {
10456	if (hevc->decode_timeout_count > 0)
10457	hevc->decode_timeout_count--;
10458	if (hevc->decode_timeout_count == 0)
10459	timeout_process(hevc);
10460	} else
10461	restart_process_time(hevc);
10462	hevc->last_lcu_idx = current_lcu_idx;
10463	} else {
10464	hevc->pic_decoded_lcu_idx = current_lcu_idx;
10465	timeout_process(hevc);
10466	}
10467	}
10468	} else {
10469	#endif
10470	if (hevc->m_ins_flag == 0 &&
10471	vf_get_receiver(hevc->provider_name)) {
10472	state =
10473	vf_notify_receiver(hevc->provider_name,
10474	VFRAME_EVENT_PROVIDER_QUREY_STATE,
10475	NULL);
10476	if ((state == RECEIVER_STATE_NULL)
10477	|| (state == RECEIVER_STATE_NONE))
10478	state = RECEIVER_INACTIVE;
10479	} else
10480	state = RECEIVER_INACTIVE;
10481
10482	empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
10483	/* error watchdog */
10484	if (hevc->m_ins_flag == 0 &&
10485	(empty_flag == 0)
10486	&& (hevc->pic_list_init_flag == 0
10487	|| hevc->pic_list_init_flag
10488	== 3)) {
10489	/* decoder has input */
10490	if ((get_dbg_flag(hevc) &
10491	H265_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
10492
10493	buf_level = READ_VREG(HEVC_STREAM_LEVEL);
10494	/* receiver has no buffer to recycle */
10495	if ((state == RECEIVER_INACTIVE) &&
10496	(kfifo_is_empty(&hevc->display_q) &&
10497	buf_level > 0x200)
10498	) {
10499	if (hevc->error_flag == 0) {
10500	hevc->error_watchdog_count++;
10501	if (hevc->error_watchdog_count ==
10502	error_handle_threshold) {
10503	hevc_print(hevc, 0,
10504	"H265 dec err local reset.\n");
10505	hevc->error_flag = 1;
10506	hevc->error_watchdog_count = 0;
10507	hevc->error_skip_nal_wt_cnt = 0;
10508	hevc->
10509	error_system_watchdog_count++;
10510	WRITE_VREG
10511	(HEVC_ASSIST_MBOX0_IRQ_REG,
10512	0x1);
10513	}
10514	} else if (hevc->error_flag == 2) {
10515	int th =
10516	error_handle_nal_skip_threshold;
10517	hevc->error_skip_nal_wt_cnt++;
10518	if (hevc->error_skip_nal_wt_cnt
10519	== th) {
10520	hevc->error_flag = 3;
10521	hevc->error_watchdog_count = 0;
10522	hevc->
10523	error_skip_nal_wt_cnt = 0;
10524	WRITE_VREG
10525	(HEVC_ASSIST_MBOX0_IRQ_REG,
10526	0x1);
10527	}
10528	}
10529	}
10530	}
10531
10532	if ((get_dbg_flag(hevc)
10533	& H265_DEBUG_DIS_SYS_ERROR_PROC) == 0)
10534	/* receiver has no buffer to recycle */
10535	if ((state == RECEIVER_INACTIVE) &&
10536	(kfifo_is_empty(&hevc->display_q))
10537	) { /* no buffer to recycle */
10538	if ((get_dbg_flag(hevc) &
10539	H265_DEBUG_DIS_LOC_ERROR_PROC) !=
10540	0)
10541	hevc->error_system_watchdog_count++;
10542	if (hevc->error_system_watchdog_count ==
10543	error_handle_system_threshold) {
10544	/* and it lasts for a while */
10545	hevc_print(hevc, 0,
10546	"H265 dec fatal error watchdog.\n");
10547	hevc->
10548	error_system_watchdog_count = 0;
10549	hevc->fatal_error |= DECODER_FATAL_ERROR_UNKNOWN;
10550	}
10551	}
10552	} else {
10553	hevc->error_watchdog_count = 0;
10554	hevc->error_system_watchdog_count = 0;
10555	}
10556	#ifdef MULTI_INSTANCE_SUPPORT
10557	}
10558	#endif
10559	if ((hevc->ucode_pause_pos != 0) &&
10560	(hevc->ucode_pause_pos != 0xffffffff) &&
10561	udebug_pause_pos != hevc->ucode_pause_pos) {
10562	hevc->ucode_pause_pos = 0;
10563	WRITE_HREG(DEBUG_REG1, 0);
10564	}
10565
10566	if (get_dbg_flag(hevc) & H265_DEBUG_DUMP_PIC_LIST) {
10567	dump_pic_list(hevc);
10568	debug &= ~H265_DEBUG_DUMP_PIC_LIST;
10569	}
10570	if (get_dbg_flag(hevc) & H265_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
10571	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10572	debug &= ~H265_DEBUG_TRIG_SLICE_SEGMENT_PROC;
10573	}
10574	#ifdef TEST_NO_BUF
10575	if (hevc->wait_buf)
10576	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10577	#endif
10578	if (get_dbg_flag(hevc) & H265_DEBUG_HW_RESET) {
10579	hevc->error_skip_nal_count = error_skip_nal_count;
10580	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10581
10582	debug &= ~H265_DEBUG_HW_RESET;
10583	}
10584
10585	#ifdef ERROR_HANDLE_DEBUG
10586	if ((dbg_nal_skip_count > 0) && ((dbg_nal_skip_count & 0x10000) != 0)) {
10587	hevc->error_skip_nal_count = dbg_nal_skip_count & 0xffff;
10588	dbg_nal_skip_count &= ~0x10000;
10589	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
10590	}
10591	#endif
10592
10593	if (radr != 0) {
10594	if (rval != 0) {
10595	WRITE_VREG(radr, rval);
10596	hevc_print(hevc, 0,
10597	"WRITE_VREG(%x,%x)\n", radr, rval);
10598	} else
10599	hevc_print(hevc, 0,
10600	"READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
10601	rval = 0;
10602	radr = 0;
10603	}
10604	if (dbg_cmd != 0) {
10605	if (dbg_cmd == 1) {
10606	u32 disp_laddr;
10607
10608	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
10609	get_double_write_mode(hevc) == 0) {
10610	disp_laddr =
10611	READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
10612	} else {
10613	struct canvas_s cur_canvas;
10614
10615	canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
10616	& 0xff), &cur_canvas);
10617	disp_laddr = cur_canvas.addr;
10618	}
10619	hevc_print(hevc, 0,
10620	"current displayed buffer address %x\r\n",
10621	disp_laddr);
10622	}
10623	dbg_cmd = 0;
10624	}
10625	/*don't changed at start.*/
10626	if (hevc->m_ins_flag == 0 &&
10627	hevc->get_frame_dur && hevc->show_frame_num > 60 &&
10628	hevc->frame_dur > 0 && hevc->saved_resolution !=
10629	hevc->frame_width * hevc->frame_height *
10630	(96000 / hevc->frame_dur))
10631	vdec_schedule_work(&hevc->set_clk_work);
10632
10633	mod_timer(timer, jiffies + PUT_INTERVAL);
10634	}
10635
10636	static int h265_task_handle(void *data)
10637	{
10638	int ret = 0;
10639	struct hevc_state_s *hevc = (struct hevc_state_s *)data;
10640
10641	set_user_nice(current, -10);
10642	while (1) {
10643	if (use_cma == 0) {
10644	hevc_print(hevc, 0,
10645	"ERROR: use_cma can not be changed dynamically\n");
10646	}
10647	ret = down_interruptible(&h265_sema);
10648	if ((hevc->init_flag != 0) && (hevc->pic_list_init_flag == 1)) {
10649	init_pic_list(hevc);
10650	init_pic_list_hw(hevc);
10651	init_buf_spec(hevc);
10652	hevc->pic_list_init_flag = 2;
10653	hevc_print(hevc, 0, "set pic_list_init_flag to 2\n");
10654
10655	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10656
10657	}
10658
10659	if (hevc->uninit_list) {
10660	/*USE_BUF_BLOCK*/
10661	uninit_pic_list(hevc);
10662	hevc_print(hevc, 0, "uninit list\n");
10663	hevc->uninit_list = 0;
10664	#ifdef USE_UNINIT_SEMA
10665	if (use_cma) {
10666	up(&hevc->h265_uninit_done_sema);
10667	while (!kthread_should_stop())
10668	msleep(1);
10669	break;
10670	}
10671	#endif
10672	}
10673	}
10674
10675	return 0;
10676	}
10677
10678	void vh265_free_cmabuf(void)
10679	{
10680	struct hevc_state_s *hevc = gHevc;
10681
10682	mutex_lock(&vh265_mutex);
10683
10684	if (hevc->init_flag) {
10685	mutex_unlock(&vh265_mutex);
10686	return;
10687	}
10688
10689	mutex_unlock(&vh265_mutex);
10690	}
10691
10692	#ifdef MULTI_INSTANCE_SUPPORT
10693	int vh265_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
10694	#else
10695	int vh265_dec_status(struct vdec_info *vstatus)
10696	#endif
10697	{
10698	#ifdef MULTI_INSTANCE_SUPPORT
10699	struct hevc_state_s *hevc =
10700	(struct hevc_state_s *)vdec->private;
10701	#else
10702	struct hevc_state_s *hevc = gHevc;
10703	#endif
10704	if (!hevc)
10705	return -1;
10706
10707	vstatus->frame_width = hevc->frame_width;
10708	vstatus->frame_height = hevc->frame_height;
10709	if (hevc->frame_dur != 0)
10710	vstatus->frame_rate = 96000 / hevc->frame_dur;
10711	else
10712	vstatus->frame_rate = -1;
10713	vstatus->error_count = 0;
10714	vstatus->status = hevc->stat | hevc->fatal_error;
10715	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10716	vstatus->bit_rate = gvs->bit_rate;
10717	vstatus->frame_dur = hevc->frame_dur;
10718	if (gvs) {
10719	vstatus->bit_rate = gvs->bit_rate;
10720	vstatus->frame_data = gvs->frame_data;
10721	vstatus->total_data = gvs->total_data;
10722	vstatus->frame_count = gvs->frame_count;
10723	vstatus->error_frame_count = gvs->error_frame_count;
10724	vstatus->drop_frame_count = gvs->drop_frame_count;
10725	vstatus->total_data = gvs->total_data;
10726	vstatus->samp_cnt = gvs->samp_cnt;
10727	vstatus->offset = gvs->offset;
10728	}
10729	snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
10730	"%s", DRIVER_NAME);
10731	#endif
10732	vstatus->ratio_control = hevc->ratio_control;
10733	return 0;
10734	}
10735
10736	int vh265_set_isreset(struct vdec_s *vdec, int isreset)
10737	{
10738	is_reset = isreset;
10739	return 0;
10740	}
10741
10742	static int vh265_vdec_info_init(void)
10743	{
10744	gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL);
10745	if (NULL == gvs) {
10746	pr_info("the struct of vdec status malloc failed.\n");
10747	return -ENOMEM;
10748	}
10749	return 0;
10750	}
10751
10752	#if 0
10753	static void H265_DECODE_INIT(void)
10754	{
10755	/* enable hevc clocks */
10756	WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
10757	/* *************************************************************** */
10758	/* Power ON HEVC */
10759	/* *************************************************************** */
10760	/* Powerup HEVC */
10761	WRITE_VREG(P_AO_RTI_GEN_PWR_SLEEP0,
10762	READ_VREG(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
10763	WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
10764	WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
10765	WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
10766	/* remove isolations */
10767	WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
10768	READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
10769
10770	}
10771	#endif
10772
10773	static void config_decode_mode(struct hevc_state_s *hevc)
10774	{
10775	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10776	struct vdec_s *vdec = hw_to_vdec(hevc);
10777	#endif
10778	unsigned decode_mode;
10779	if (!hevc->m_ins_flag)
10780	decode_mode = DECODE_MODE_SINGLE;
10781	else if (vdec_frame_based(hw_to_vdec(hevc)))
10782	decode_mode =
10783	DECODE_MODE_MULTI_FRAMEBASE;
10784	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10785	else if (vdec->slave) {
10786	if (force_bypass_dvenl & 0x80000000)
10787	hevc->bypass_dvenl = force_bypass_dvenl & 0x1;
10788	else
10789	hevc->bypass_dvenl = hevc->bypass_dvenl_enable;
10790	if (dolby_meta_with_el && hevc->bypass_dvenl) {
10791	hevc->bypass_dvenl = 0;
10792	hevc_print(hevc, 0,
10793	"NOT support bypass_dvenl when meta_with_el\n");
10794	}
10795	if (hevc->bypass_dvenl)
10796	decode_mode =
10797	(hevc->start_parser_type << 8)
10798	| DECODE_MODE_MULTI_STREAMBASE;
10799	else
10800	decode_mode =
10801	(hevc->start_parser_type << 8)
10802	| DECODE_MODE_MULTI_DVBAL;
10803	} else if (vdec->master)
10804	decode_mode =
10805	(hevc->start_parser_type << 8)
10806	| DECODE_MODE_MULTI_DVENL;
10807	#endif
10808	else
10809	decode_mode =
10810	DECODE_MODE_MULTI_STREAMBASE;
10811
10812	if (hevc->m_ins_flag)
10813	decode_mode |=
10814	(hevc->start_decoding_flag << 16);
10815	/* set MBX0 interrupt flag */
10816	decode_mode |= (0x80 << 24);
10817	WRITE_VREG(HEVC_DECODE_MODE, decode_mode);
10818	WRITE_VREG(HEVC_DECODE_MODE2,
10819	hevc->rps_set_id);
10820	}
10821
10822	static void vh265_prot_init(struct hevc_state_s *hevc)
10823	{
10824	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10825	struct vdec_s *vdec = hw_to_vdec(hevc);
10826	#endif
10827	/* H265_DECODE_INIT(); */
10828
10829	hevc_config_work_space_hw(hevc);
10830
10831	hevc_init_decoder_hw(hevc, 0, 0xffffffff);
10832
10833	WRITE_VREG(HEVC_WAIT_FLAG, 1);
10834
10835	/* WRITE_VREG(P_HEVC_MPSR, 1); */
10836
10837	/* clear mailbox interrupt */
10838	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
10839
10840	/* enable mailbox interrupt */
10841	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
10842
10843	/* disable PSCALE for hardware sharing */
10844	WRITE_VREG(HEVC_PSCALE_CTRL, 0);
10845
10846	WRITE_VREG(DEBUG_REG1, 0x0 | (dump_nal << 8));
10847
10848	if ((get_dbg_flag(hevc) &
10849	(H265_DEBUG_MAN_SKIP_NAL |
10850	H265_DEBUG_MAN_SEARCH_NAL))
10851	/*||hevc->m_ins_flag*/
10852	) {
10853	WRITE_VREG(NAL_SEARCH_CTL, 0x1); /* manual parser NAL */
10854	} else {
10855	/* check vps/sps/pps/i-slice in ucode */
10856	unsigned ctl_val = 0x8;
10857	if (hevc->PB_skip_mode == 0)
10858	ctl_val = 0x4; /* check vps/sps/pps only in ucode */
10859	else if (hevc->PB_skip_mode == 3)
10860	ctl_val = 0x0; /* check vps/sps/pps/idr in ucode */
10861	WRITE_VREG(NAL_SEARCH_CTL, ctl_val);
10862	}
10863	if ((get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE)
10864	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10865	|| vdec->master
10866	|| vdec->slave
10867	#endif
10868	)
10869	WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x10000);
10870
10871	WRITE_VREG(NAL_SEARCH_CTL,
10872	READ_VREG(NAL_SEARCH_CTL)
10873	| ((parser_sei_enable & 0x7) << 17));
10874	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
10875	WRITE_VREG(NAL_SEARCH_CTL,
10876	READ_VREG(NAL_SEARCH_CTL) |
10877	((parser_dolby_vision_enable & 0x1) << 20));
10878	#endif
10879	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
10880
10881	config_decode_mode(hevc);
10882	config_aux_buf(hevc);
10883	#ifdef SWAP_HEVC_UCODE
10884	if (!tee_enabled() && hevc->is_swap &&
10885	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
10886	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->mc_dma_handle);
10887	/*pr_info("write swap buffer %x\n", (u32)(hevc->mc_dma_handle));*/
10888	}
10889	#endif
10890	#ifdef DETREFILL_ENABLE
10891	if (hevc->is_swap &&
10892	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
10893	WRITE_VREG(HEVC_SAO_DBG_MODE0, 0);
10894	WRITE_VREG(HEVC_SAO_DBG_MODE1, 0);
10895	}
10896	#endif
10897	}
10898
10899	static int vh265_local_init(struct hevc_state_s *hevc)
10900	{
10901	int i;
10902	int ret = -1;
10903
10904	#ifdef DEBUG_PTS
10905	hevc->pts_missed = 0;
10906	hevc->pts_hit = 0;
10907	#endif
10908
10909	hevc->saved_resolution = 0;
10910	hevc->get_frame_dur = false;
10911	hevc->frame_width = hevc->vh265_amstream_dec_info.width;
10912	hevc->frame_height = hevc->vh265_amstream_dec_info.height;
10913	if (is_oversize(hevc->frame_width, hevc->frame_height)) {
10914	pr_info("over size : %u x %u.\n",
10915	hevc->frame_width, hevc->frame_height);
10916	hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
10917	return ret;
10918	}
10919
10920	if (hevc->max_pic_w && hevc->max_pic_h) {
10921	hevc->is_4k = !(hevc->max_pic_w && hevc->max_pic_h) ||
10922	((hevc->max_pic_w * hevc->max_pic_h) >
10923	1920 * 1088) ? true : false;
10924	} else {
10925	hevc->is_4k = !(hevc->frame_width && hevc->frame_height) ||
10926	((hevc->frame_width * hevc->frame_height) >
10927	1920 * 1088) ? true : false;
10928	}
10929
10930	hevc->frame_dur =
10931	(hevc->vh265_amstream_dec_info.rate ==
10932	0) ? 3600 : hevc->vh265_amstream_dec_info.rate;
10933	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
10934	gvs->frame_dur = hevc->frame_dur;
10935	#endif
10936	if (hevc->frame_width && hevc->frame_height)
10937	hevc->frame_ar = hevc->frame_height * 0x100 / hevc->frame_width;
10938
10939	if (i_only_flag)
10940	hevc->i_only = i_only_flag & 0xff;
10941	else if ((unsigned long) hevc->vh265_amstream_dec_info.param
10942	& 0x08)
10943	hevc->i_only = 0x7;
10944	else
10945	hevc->i_only = 0x0;
10946	hevc->error_watchdog_count = 0;
10947	hevc->sei_present_flag = 0;
10948	pts_unstable = ((unsigned long)hevc->vh265_amstream_dec_info.param
10949	& 0x40) >> 6;
10950	hevc_print(hevc, 0,
10951	"h265:pts_unstable=%d\n", pts_unstable);
10952	/*
10953	*TODO:FOR VERSION
10954	*/
10955	hevc_print(hevc, 0,
10956	"h265: ver (%d,%d) decinfo: %dx%d rate=%d\n", h265_version,
10957	0, hevc->frame_width, hevc->frame_height, hevc->frame_dur);
10958
10959	if (hevc->frame_dur == 0)
10960	hevc->frame_dur = 96000 / 24;
10961
10962	INIT_KFIFO(hevc->display_q);
10963	INIT_KFIFO(hevc->newframe_q);
10964	INIT_KFIFO(hevc->pending_q);
10965
10966	for (i = 0; i < VF_POOL_SIZE; i++) {
10967	const struct vframe_s *vf = &hevc->vfpool[i];
10968
10969	hevc->vfpool[i].index = -1;
10970	kfifo_put(&hevc->newframe_q, vf);
10971	}
10972
10973
10974	ret = hevc_local_init(hevc);
10975
10976	return ret;
10977	}
10978	#ifdef MULTI_INSTANCE_SUPPORT
10979	static s32 vh265_init(struct vdec_s *vdec)
10980	{
10981	struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private;
10982	#else
10983	static s32 vh265_init(struct hevc_state_s *hevc)
10984	{
10985
10986	#endif
10987	int ret, size = -1;
10988	int fw_size = 0x1000 * 16;
10989	struct firmware_s *fw = NULL;
10990
10991	init_timer(&hevc->timer);
10992
10993	hevc->stat |= STAT_TIMER_INIT;
10994
10995	if (hevc->m_ins_flag) {
10996	#ifdef USE_UNINIT_SEMA
10997	sema_init(&hevc->h265_uninit_done_sema, 0);
10998	#endif
10999	INIT_WORK(&hevc->work, vh265_work);
11000	INIT_WORK(&hevc->timeout_work, vh265_timeout_work);
11001	}
11002
11003	if (vh265_local_init(hevc) < 0)
11004	return -EBUSY;
11005
11006	mutex_init(&hevc->chunks_mutex);
11007	INIT_WORK(&hevc->notify_work, vh265_notify_work);
11008	INIT_WORK(&hevc->set_clk_work, vh265_set_clk);
11009
11010	fw = vmalloc(sizeof(struct firmware_s) + fw_size);
11011	if (IS_ERR_OR_NULL(fw))
11012	return -ENOMEM;
11013
11014	if (hevc->mmu_enable)
11015	if (get_cpu_major_id() > AM_MESON_CPU_MAJOR_ID_GXM)
11016	size = get_firmware_data(VIDEO_DEC_HEVC_MMU, fw->data);
11017	else {
11018	if (!hevc->is_4k) {
11019	/* if an older version of the fw was loaded, */
11020	/* needs try to load noswap fw because the */
11021	/* old fw package dose not contain the swap fw.*/
11022	size = get_firmware_data(
11023	VIDEO_DEC_HEVC_MMU_SWAP, fw->data);
11024	if (size < 0)
11025	size = get_firmware_data(
11026	VIDEO_DEC_HEVC_MMU, fw->data);
11027	else if (size)
11028	hevc->is_swap = true;
11029	} else
11030	size = get_firmware_data(VIDEO_DEC_HEVC_MMU,
11031	fw->data);
11032	}
11033	else
11034	size = get_firmware_data(VIDEO_DEC_HEVC, fw->data);
11035
11036	if (size < 0) {
11037	pr_err("get firmware fail.\n");
11038	vfree(fw);
11039	return -1;
11040	}
11041
11042	fw->len = size;
11043
11044	#ifdef SWAP_HEVC_UCODE
11045	if (!tee_enabled() && hevc->is_swap &&
11046	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
11047	if (hevc->mmu_enable) {
11048	hevc->swap_size = (4 * (4 * SZ_1K)); /*max 4 swap code, each 0x400*/
11049	hevc->mc_cpu_addr =
11050	dma_alloc_coherent(amports_get_dma_device(),
11051	hevc->swap_size,
11052	&hevc->mc_dma_handle, GFP_KERNEL);
11053	if (!hevc->mc_cpu_addr) {
11054	amhevc_disable();
11055	pr_info("vh265 mmu swap ucode loaded fail.\n");
11056	return -ENOMEM;
11057	}
11058
11059	memcpy((u8 *) hevc->mc_cpu_addr, fw->data + SWAP_HEVC_OFFSET,
11060	hevc->swap_size);
11061
11062	hevc_print(hevc, 0,
11063	"vh265 mmu ucode swap loaded %x\n",
11064	hevc->mc_dma_handle);
11065	}
11066	}
11067	#endif
11068
11069	#ifdef MULTI_INSTANCE_SUPPORT
11070	if (hevc->m_ins_flag) {
11071	hevc->timer.data = (ulong) hevc;
11072	hevc->timer.function = vh265_check_timer_func;
11073	hevc->timer.expires = jiffies + PUT_INTERVAL;
11074
11075	hevc->fw = fw;
11076
11077	return 0;
11078	}
11079	#endif
11080	amhevc_enable();
11081
11082	if (hevc->mmu_enable)
11083	if (get_cpu_major_id() > AM_MESON_CPU_MAJOR_ID_GXM)
11084	ret = amhevc_loadmc_ex(VFORMAT_HEVC, "h265_mmu", fw->data);
11085	else {
11086	if (!hevc->is_4k) {
11087	/* if an older version of the fw was loaded, */
11088	/* needs try to load noswap fw because the */
11089	/* old fw package dose not contain the swap fw. */
11090	ret = amhevc_loadmc_ex(VFORMAT_HEVC,
11091	"hevc_mmu_swap", fw->data);
11092	if (ret < 0)
11093	ret = amhevc_loadmc_ex(VFORMAT_HEVC,
11094	"h265_mmu", fw->data);
11095	else
11096	hevc->is_swap = true;
11097	} else
11098	ret = amhevc_loadmc_ex(VFORMAT_HEVC,
11099	"h265_mmu", fw->data);
11100	}
11101	else
11102	ret = amhevc_loadmc_ex(VFORMAT_HEVC, NULL, fw->data);
11103
11104	if (ret < 0) {
11105	amhevc_disable();
11106	vfree(fw);
11107	pr_err("H265: the %s fw loading failed, err: %x\n",
11108	tee_enabled() ? "TEE" : "local", ret);
11109	return -EBUSY;
11110	}
11111
11112	vfree(fw);
11113
11114	hevc->stat |= STAT_MC_LOAD;
11115
11116	#ifdef DETREFILL_ENABLE
11117	if (hevc->is_swap &&
11118	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
11119	init_detrefill_buf(hevc);
11120	#endif
11121	/* enable AMRISC side protocol */
11122	vh265_prot_init(hevc);
11123
11124	if (vdec_request_threaded_irq(VDEC_IRQ_0, vh265_isr,
11125	vh265_isr_thread_fn,
11126	IRQF_ONESHOT,/*run thread on this irq disabled*/
11127	"vh265-irq", (void *)hevc)) {
11128	hevc_print(hevc, 0, "vh265 irq register error.\n");
11129	amhevc_disable();
11130	return -ENOENT;
11131	}
11132
11133	hevc->stat |= STAT_ISR_REG;
11134	hevc->provider_name = PROVIDER_NAME;
11135
11136	#ifdef MULTI_INSTANCE_SUPPORT
11137	vf_provider_init(&vh265_vf_prov, hevc->provider_name,
11138	&vh265_vf_provider, vdec);
11139	vf_reg_provider(&vh265_vf_prov);
11140	vf_notify_receiver(hevc->provider_name, VFRAME_EVENT_PROVIDER_START,
11141	NULL);
11142	if (hevc->frame_dur != 0) {
11143	if (!is_reset) {
11144	vf_notify_receiver(hevc->provider_name,
11145	VFRAME_EVENT_PROVIDER_FR_HINT,
11146	(void *)
11147	((unsigned long)hevc->frame_dur));
11148	fr_hint_status = VDEC_HINTED;
11149	}
11150	} else
11151	fr_hint_status = VDEC_NEED_HINT;
11152	#else
11153	vf_provider_init(&vh265_vf_prov, PROVIDER_NAME, &vh265_vf_provider,
11154	hevc);
11155	vf_reg_provider(&vh265_vf_prov);
11156	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
11157	if (hevc->frame_dur != 0) {
11158	vf_notify_receiver(PROVIDER_NAME,
11159	VFRAME_EVENT_PROVIDER_FR_HINT,
11160	(void *)
11161	((unsigned long)hevc->frame_dur));
11162	fr_hint_status = VDEC_HINTED;
11163	} else
11164	fr_hint_status = VDEC_NEED_HINT;
11165	#endif
11166	hevc->stat |= STAT_VF_HOOK;
11167
11168	hevc->timer.data = (ulong) hevc;
11169	hevc->timer.function = vh265_check_timer_func;
11170	hevc->timer.expires = jiffies + PUT_INTERVAL;
11171
11172	add_timer(&hevc->timer);
11173
11174	hevc->stat |= STAT_TIMER_ARM;
11175
11176	if (use_cma) {
11177	#ifdef USE_UNINIT_SEMA
11178	sema_init(&hevc->h265_uninit_done_sema, 0);
11179	#endif
11180	if (h265_task == NULL) {
11181	sema_init(&h265_sema, 1);
11182	h265_task =
11183	kthread_run(h265_task_handle, hevc,
11184	"kthread_h265");
11185	}
11186	}
11187	/* hevc->stat |= STAT_KTHREAD; */
11188	#if 0
11189	if (get_dbg_flag(hevc) & H265_DEBUG_FORCE_CLK) {
11190	hevc_print(hevc, 0, "%s force clk\n", __func__);
11191	WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL,
11192	READ_VREG(HEVC_IQIT_CLK_RST_CTRL) |
11193	((1 << 2) | (1 << 1)));
11194	WRITE_VREG(HEVC_DBLK_CFG0,
11195	READ_VREG(HEVC_DBLK_CFG0) | ((1 << 2) |
11196	(1 << 1) | 0x3fff0000));/* 2,29:16 */
11197	WRITE_VREG(HEVC_SAO_CTRL1, READ_VREG(HEVC_SAO_CTRL1) |
11198	(1 << 2)); /* 2 */
11199	WRITE_VREG(HEVC_MPRED_CTRL1, READ_VREG(HEVC_MPRED_CTRL1) |
11200	(1 << 24)); /* 24 */
11201	WRITE_VREG(HEVC_STREAM_CONTROL,
11202	READ_VREG(HEVC_STREAM_CONTROL) |
11203	(1 << 15)); /* 15 */
11204	WRITE_VREG(HEVC_CABAC_CONTROL, READ_VREG(HEVC_CABAC_CONTROL) |
11205	(1 << 13)); /* 13 */
11206	WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
11207	READ_VREG(HEVC_PARSER_CORE_CONTROL) |
11208	(1 << 15)); /* 15 */
11209	WRITE_VREG(HEVC_PARSER_INT_CONTROL,
11210	READ_VREG(HEVC_PARSER_INT_CONTROL) |
11211	(1 << 15)); /* 15 */
11212	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
11213	READ_VREG(HEVC_PARSER_IF_CONTROL) | ((1 << 6) |
11214	(1 << 3) | (1 << 1))); /* 6, 3, 1 */
11215	WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, 0xffffffff); /* 31:0 */
11216	WRITE_VREG(HEVCD_MCRCC_CTL1, READ_VREG(HEVCD_MCRCC_CTL1) |
11217	(1 << 3)); /* 3 */
11218	}
11219	#endif
11220	#ifdef SWAP_HEVC_UCODE
11221	if (!tee_enabled() && hevc->is_swap &&
11222	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
11223	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->mc_dma_handle);
11224	/*pr_info("write swap buffer %x\n", (u32)(hevc->mc_dma_handle));*/
11225	}
11226	#endif
11227
11228	#ifndef MULTI_INSTANCE_SUPPORT
11229	set_vdec_func(&vh265_dec_status);
11230	#endif
11231	amhevc_start();
11232	hevc->stat |= STAT_VDEC_RUN;
11233	hevc->init_flag = 1;
11234	error_handle_threshold = 30;
11235	/* pr_info("%d, vh265_init, RP=0x%x\n",
11236	* __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
11237	*/
11238
11239	return 0;
11240	}
11241
11242	static int vh265_stop(struct hevc_state_s *hevc)
11243	{
11244	if (get_dbg_flag(hevc) &
11245	H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP) {
11246	int wait_timeout_count = 0;
11247
11248	while (READ_VREG(HEVC_DEC_STATUS_REG) ==
11249	HEVC_CODED_SLICE_SEGMENT_DAT &&
11250	wait_timeout_count < 10){
11251	wait_timeout_count++;
11252	msleep(20);
11253	}
11254	}
11255	if (hevc->stat & STAT_VDEC_RUN) {
11256	amhevc_stop();
11257	hevc->stat &= ~STAT_VDEC_RUN;
11258	}
11259
11260	if (hevc->stat & STAT_ISR_REG) {
11261	#ifdef MULTI_INSTANCE_SUPPORT
11262	if (!hevc->m_ins_flag)
11263	#endif
11264	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
11265	vdec_free_irq(VDEC_IRQ_0, (void *)hevc);
11266	hevc->stat &= ~STAT_ISR_REG;
11267	}
11268
11269	hevc->stat &= ~STAT_TIMER_INIT;
11270	if (hevc->stat & STAT_TIMER_ARM) {
11271	del_timer_sync(&hevc->timer);
11272	hevc->stat &= ~STAT_TIMER_ARM;
11273	}
11274
11275	if (hevc->stat & STAT_VF_HOOK) {
11276	if (fr_hint_status == VDEC_HINTED) {
11277	vf_notify_receiver(hevc->provider_name,
11278	VFRAME_EVENT_PROVIDER_FR_END_HINT,
11279	NULL);
11280	}
11281	fr_hint_status = VDEC_NO_NEED_HINT;
11282	vf_unreg_provider(&vh265_vf_prov);
11283	hevc->stat &= ~STAT_VF_HOOK;
11284	}
11285
11286	hevc_local_uninit(hevc);
11287
11288	if (use_cma) {
11289	hevc->uninit_list = 1;
11290	up(&h265_sema);
11291	#ifdef USE_UNINIT_SEMA
11292	down(&hevc->h265_uninit_done_sema);
11293	if (!IS_ERR(h265_task)) {
11294	kthread_stop(h265_task);
11295	h265_task = NULL;
11296	}
11297	#else
11298	while (hevc->uninit_list) /* wait uninit complete */
11299	msleep(20);
11300	#endif
11301
11302	}
11303	hevc->init_flag = 0;
11304	hevc->first_sc_checked = 0;
11305	cancel_work_sync(&hevc->notify_work);
11306	cancel_work_sync(&hevc->set_clk_work);
11307	uninit_mmu_buffers(hevc);
11308	amhevc_disable();
11309
11310	kfree(gvs);
11311	gvs = NULL;
11312
11313	return 0;
11314	}
11315
11316	#ifdef MULTI_INSTANCE_SUPPORT
11317	static void reset_process_time(struct hevc_state_s *hevc)
11318	{
11319	if (hevc->start_process_time) {
11320	unsigned int process_time =
11321	1000 * (jiffies - hevc->start_process_time) / HZ;
11322	hevc->start_process_time = 0;
11323	if (process_time > max_process_time[hevc->index])
11324	max_process_time[hevc->index] = process_time;
11325	}
11326	}
11327
11328	static void start_process_time(struct hevc_state_s *hevc)
11329	{
11330	hevc->start_process_time = jiffies;
11331	hevc->decode_timeout_count = 2;
11332	hevc->last_lcu_idx = 0;
11333	}
11334
11335	static void restart_process_time(struct hevc_state_s *hevc)
11336	{
11337	hevc->start_process_time = jiffies;
11338	hevc->decode_timeout_count = 2;
11339	}
11340
11341	static void timeout_process(struct hevc_state_s *hevc)
11342	{
11343	/*
11344	* In this very timeout point,the vh265_work arrives,
11345	* let it to handle the scenario.
11346	*/
11347	if (work_pending(&hevc->work))
11348	return;
11349
11350	hevc->timeout_num++;
11351	amhevc_stop();
11352	read_decode_info(hevc);
11353
11354	hevc_print(hevc,
11355	0, "%s decoder timeout\n", __func__);
11356	check_pic_decoded_error(hevc,
11357	hevc->pic_decoded_lcu_idx);
11358	hevc->decoded_poc = hevc->curr_POC;
11359	hevc->decoding_pic = NULL;
11360	hevc->dec_result = DEC_RESULT_DONE;
11361	reset_process_time(hevc);
11362
11363	if (work_pending(&hevc->work))
11364	return;
11365	vdec_schedule_work(&hevc->timeout_work);
11366	}
11367
11368	#ifdef CONSTRAIN_MAX_BUF_NUM
11369	static int get_vf_ref_only_buf_count(struct hevc_state_s *hevc)
11370	{
11371	struct PIC_s *pic;
11372	int i;
11373	int count = 0;
11374	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11375	pic = hevc->m_PIC[i];
11376	if (pic == NULL || pic->index == -1)
11377	continue;
11378	if (pic->output_mark == 0 && pic->referenced == 0
11379	&& pic->output_ready == 1)
11380	count++;
11381	}
11382
11383	return count;
11384	}
11385
11386	static int get_used_buf_count(struct hevc_state_s *hevc)
11387	{
11388	struct PIC_s *pic;
11389	int i;
11390	int count = 0;
11391	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11392	pic = hevc->m_PIC[i];
11393	if (pic == NULL || pic->index == -1)
11394	continue;
11395	if (pic->output_mark != 0 || pic->referenced != 0
11396	|| pic->output_ready != 0)
11397	count++;
11398	}
11399
11400	return count;
11401	}
11402	#endif
11403
11404
11405	static unsigned char is_new_pic_available(struct hevc_state_s *hevc)
11406	{
11407	struct PIC_s *new_pic = NULL;
11408	struct PIC_s *pic;
11409	/* recycle un-used pic */
11410	int i;
11411	int ref_pic = 0;
11412	struct vdec_s *vdec = hw_to_vdec(hevc);
11413	/*return 1 if pic_list is not initialized yet*/
11414	if (hevc->pic_list_init_flag != 3)
11415	return 1;
11416
11417	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11418	pic = hevc->m_PIC[i];
11419	if (pic == NULL || pic->index == -1)
11420	continue;
11421	if (pic->referenced == 1)
11422	ref_pic++;
11423	if (pic->output_mark == 0 && pic->referenced == 0
11424	&& pic->output_ready == 0
11425	) {
11426	if (new_pic) {
11427	if (pic->POC < new_pic->POC)
11428	new_pic = pic;
11429	} else
11430	new_pic = pic;
11431	}
11432	}
11433	/*If the number of reference frames of DPB >= (the DPB buffer size - the number of reorders -3)*/
11434	/*and the back-end state is RECEIVER INACTIVE, it will cause the decoder have no buffer to*/
11435	/*decode. all reference frames are removed and setting error flag.*/
11436	/*3 represents 2 filed are needed for back-end display and 1 filed is needed for decoding*/
11437	/*when file is interlace.*/
11438	if ((!hevc->is_used_v4l) && (new_pic == NULL) &&
11439	(ref_pic >=
11440	get_work_pic_num(hevc) -
11441	hevc->sps_num_reorder_pics_0 - 3)) {
11442	enum receviver_start_e state = RECEIVER_INACTIVE;
11443	if (vf_get_receiver(vdec->vf_provider_name)) {
11444	state =
11445	vf_notify_receiver(vdec->vf_provider_name,
11446	VFRAME_EVENT_PROVIDER_QUREY_STATE,
11447	NULL);
11448	if ((state == RECEIVER_STATE_NULL)
11449	|| (state == RECEIVER_STATE_NONE))
11450	state = RECEIVER_INACTIVE;
11451	}
11452	if (state == RECEIVER_INACTIVE) {
11453	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
11454	pic = hevc->m_PIC[i];
11455	if (pic == NULL || pic->index == -1)
11456	continue;
11457
11458	if ((pic->referenced == 1) &&
11459	(pic->error_mark == 1)) {
11460	pic->referenced = 0;
11461	put_mv_buf(hevc, pic);
11462	}
11463	pic->error_mark = 1;
11464	}
11465	}
11466	}
11467
11468	return (new_pic != NULL) ? 1 : 0;
11469	}
11470
11471	static int vmh265_stop(struct hevc_state_s *hevc)
11472	{
11473	if (hevc->stat & STAT_TIMER_ARM) {
11474	del_timer_sync(&hevc->timer);
11475	hevc->stat &= ~STAT_TIMER_ARM;
11476	}
11477	if (hevc->stat & STAT_VDEC_RUN) {
11478	amhevc_stop();
11479	hevc->stat &= ~STAT_VDEC_RUN;
11480	}
11481	if (hevc->stat & STAT_ISR_REG) {
11482	vdec_free_irq(VDEC_IRQ_0, (void *)hevc);
11483	hevc->stat &= ~STAT_ISR_REG;
11484	}
11485
11486	if (hevc->stat & STAT_VF_HOOK) {
11487	if (fr_hint_status == VDEC_HINTED)
11488	vf_notify_receiver(hevc->provider_name,
11489	VFRAME_EVENT_PROVIDER_FR_END_HINT,
11490	NULL);
11491	fr_hint_status = VDEC_NO_NEED_HINT;
11492	vf_unreg_provider(&vh265_vf_prov);
11493	hevc->stat &= ~STAT_VF_HOOK;
11494	}
11495
11496	hevc_local_uninit(hevc);
11497
11498	hevc->init_flag = 0;
11499	hevc->first_sc_checked = 0;
11500	cancel_work_sync(&hevc->notify_work);
11501	cancel_work_sync(&hevc->set_clk_work);
11502	cancel_work_sync(&hevc->timeout_work);
11503
11504	uninit_mmu_buffers(hevc);
11505
11506	if (use_cma) {
11507	hevc->uninit_list = 1;
11508	reset_process_time(hevc);
11509	hevc->dec_result = DEC_RESULT_FREE_CANVAS;
11510	vdec_schedule_work(&hevc->work);
11511	flush_work(&hevc->work);
11512	#ifdef USE_UNINIT_SEMA
11513	if (hevc->init_flag) {
11514	down(&hevc->h265_uninit_done_sema);
11515	}
11516	#else
11517	while (hevc->uninit_list) /* wait uninit complete */
11518	msleep(20);
11519	#endif
11520	}
11521	cancel_work_sync(&hevc->work);
11522
11523	vfree(hevc->fw);
11524	hevc->fw = NULL;
11525
11526	dump_log(hevc);
11527	return 0;
11528	}
11529
11530	static unsigned char get_data_check_sum
11531	(struct hevc_state_s *hevc, int size)
11532	{
11533	int jj;
11534	int sum = 0;
11535	u8 *data = NULL;
11536
11537	if (!hevc->chunk->block->is_mapped)
11538	data = codec_mm_vmap(hevc->chunk->block->start +
11539	hevc->chunk->offset, size);
11540	else
11541	data = ((u8 *)hevc->chunk->block->start_virt) +
11542	hevc->chunk->offset;
11543
11544	for (jj = 0; jj < size; jj++)
11545	sum += data[jj];
11546
11547	if (!hevc->chunk->block->is_mapped)
11548	codec_mm_unmap_phyaddr(data);
11549	return sum;
11550	}
11551
11552	static void vh265_notify_work(struct work_struct *work)
11553	{
11554	struct hevc_state_s *hevc =
11555	container_of(work,
11556	struct hevc_state_s,
11557	notify_work);
11558	struct vdec_s *vdec = hw_to_vdec(hevc);
11559	#ifdef MULTI_INSTANCE_SUPPORT
11560	if (vdec->fr_hint_state == VDEC_NEED_HINT) {
11561	vf_notify_receiver(hevc->provider_name,
11562	VFRAME_EVENT_PROVIDER_FR_HINT,
11563	(void *)
11564	((unsigned long)hevc->frame_dur));
11565	vdec->fr_hint_state = VDEC_HINTED;
11566	} else if (fr_hint_status == VDEC_NEED_HINT) {
11567	vf_notify_receiver(hevc->provider_name,
11568	VFRAME_EVENT_PROVIDER_FR_HINT,
11569	(void *)
11570	((unsigned long)hevc->frame_dur));
11571	fr_hint_status = VDEC_HINTED;
11572	}
11573	#else
11574	if (fr_hint_status == VDEC_NEED_HINT)
11575	vf_notify_receiver(PROVIDER_NAME,
11576	VFRAME_EVENT_PROVIDER_FR_HINT,
11577	(void *)
11578	((unsigned long)hevc->frame_dur));
11579	fr_hint_status = VDEC_HINTED;
11580	}
11581	#endif
11582
11583	return;
11584	}
11585
11586	static void vh265_work_implement(struct hevc_state_s *hevc,
11587	struct vdec_s *vdec,int from)
11588	{
11589	if (hevc->dec_result == DEC_RESULT_FREE_CANVAS) {
11590	/*USE_BUF_BLOCK*/
11591	uninit_pic_list(hevc);
11592	hevc_print(hevc, 0, "uninit list\n");
11593	hevc->uninit_list = 0;
11594	#ifdef USE_UNINIT_SEMA
11595	up(&hevc->h265_uninit_done_sema);
11596	#endif
11597	return;
11598	}
11599
11600	/* finished decoding one frame or error,
11601	* notify vdec core to switch context
11602	*/
11603	if (hevc->pic_list_init_flag == 1
11604	&& (hevc->dec_result != DEC_RESULT_FORCE_EXIT)) {
11605	hevc->pic_list_init_flag = 2;
11606	init_pic_list(hevc);
11607	init_pic_list_hw(hevc);
11608	init_buf_spec(hevc);
11609	hevc_print(hevc, 0,
11610	"set pic_list_init_flag to 2\n");
11611
11612	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
11613	return;
11614	}
11615
11616	hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL,
11617	"%s dec_result %d %x %x %x\n",
11618	__func__,
11619	hevc->dec_result,
11620	READ_VREG(HEVC_STREAM_LEVEL),
11621	READ_VREG(HEVC_STREAM_WR_PTR),
11622	READ_VREG(HEVC_STREAM_RD_PTR));
11623
11624	if (((hevc->dec_result == DEC_RESULT_GET_DATA) ||
11625	(hevc->dec_result == DEC_RESULT_GET_DATA_RETRY))
11626	&& (hw_to_vdec(hevc)->next_status !=
11627	VDEC_STATUS_DISCONNECTED)) {
11628	if (!vdec_has_more_input(vdec)) {
11629	hevc->dec_result = DEC_RESULT_EOS;
11630	vdec_schedule_work(&hevc->work);
11631	return;
11632	}
11633	if (!input_frame_based(vdec)) {
11634	int r = vdec_sync_input(vdec);
11635	if (r >= 0x200) {
11636	WRITE_VREG(HEVC_DECODE_SIZE,
11637	READ_VREG(HEVC_DECODE_SIZE) + r);
11638
11639	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11640	"%s DEC_RESULT_GET_DATA %x %x %x mpc %x size 0x%x\n",
11641	__func__,
11642	READ_VREG(HEVC_STREAM_LEVEL),
11643	READ_VREG(HEVC_STREAM_WR_PTR),
11644	READ_VREG(HEVC_STREAM_RD_PTR),
11645	READ_VREG(HEVC_MPC_E), r);
11646
11647	start_process_time(hevc);
11648	if (READ_VREG(HEVC_DEC_STATUS_REG)
11649	== HEVC_DECODE_BUFEMPTY2)
11650	WRITE_VREG(HEVC_DEC_STATUS_REG,
11651	HEVC_ACTION_DONE);
11652	else
11653	WRITE_VREG(HEVC_DEC_STATUS_REG,
11654	HEVC_ACTION_DEC_CONT);
11655	} else {
11656	hevc->dec_result = DEC_RESULT_GET_DATA_RETRY;
11657	vdec_schedule_work(&hevc->work);
11658	}
11659	return;
11660	}
11661
11662	/*below for frame_base*/
11663	if (hevc->dec_result == DEC_RESULT_GET_DATA) {
11664	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11665	"%s DEC_RESULT_GET_DATA %x %x %x mpc %x\n",
11666	__func__,
11667	READ_VREG(HEVC_STREAM_LEVEL),
11668	READ_VREG(HEVC_STREAM_WR_PTR),
11669	READ_VREG(HEVC_STREAM_RD_PTR),
11670	READ_VREG(HEVC_MPC_E));
11671	mutex_lock(&hevc->chunks_mutex);
11672	vdec_vframe_dirty(vdec, hevc->chunk);
11673	hevc->chunk = NULL;
11674	mutex_unlock(&hevc->chunks_mutex);
11675	vdec_clean_input(vdec);
11676	}
11677
11678	/*if (is_new_pic_available(hevc)) {*/
11679	if (run_ready(vdec, VDEC_HEVC)) {
11680	int r;
11681	int decode_size;
11682	r = vdec_prepare_input(vdec, &hevc->chunk);
11683	if (r < 0) {
11684	hevc->dec_result = DEC_RESULT_GET_DATA_RETRY;
11685
11686	hevc_print(hevc,
11687	PRINT_FLAG_VDEC_DETAIL,
11688	"amvdec_vh265: Insufficient data\n");
11689
11690	vdec_schedule_work(&hevc->work);
11691	return;
11692	}
11693	hevc->dec_result = DEC_RESULT_NONE;
11694	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11695	"%s: chunk size 0x%x sum 0x%x mpc %x\n",
11696	__func__, r,
11697	(get_dbg_flag(hevc) & PRINT_FLAG_VDEC_STATUS) ?
11698	get_data_check_sum(hevc, r) : 0,
11699	READ_VREG(HEVC_MPC_E));
11700
11701	if (get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) {
11702	int jj;
11703	u8 *data = NULL;
11704
11705	if (!hevc->chunk->block->is_mapped)
11706	data = codec_mm_vmap(
11707	hevc->chunk->block->start +
11708	hevc->chunk->offset, r);
11709	else
11710	data = ((u8 *)
11711	hevc->chunk->block->start_virt)
11712	+ hevc->chunk->offset;
11713
11714	for (jj = 0; jj < r; jj++) {
11715	if ((jj & 0xf) == 0)
11716	hevc_print(hevc,
11717	PRINT_FRAMEBASE_DATA,
11718	"%06x:", jj);
11719	hevc_print_cont(hevc,
11720	PRINT_FRAMEBASE_DATA,
11721	"%02x ", data[jj]);
11722	if (((jj + 1) & 0xf) == 0)
11723	hevc_print_cont(hevc,
11724	PRINT_FRAMEBASE_DATA,
11725	"\n");
11726	}
11727
11728	if (!hevc->chunk->block->is_mapped)
11729	codec_mm_unmap_phyaddr(data);
11730	}
11731
11732	decode_size = hevc->chunk->size +
11733	(hevc->chunk->offset & (VDEC_FIFO_ALIGN - 1));
11734	WRITE_VREG(HEVC_DECODE_SIZE,
11735	READ_VREG(HEVC_DECODE_SIZE) + decode_size);
11736
11737	vdec_enable_input(vdec);
11738
11739	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11740	"%s: mpc %x\n",
11741	__func__, READ_VREG(HEVC_MPC_E));
11742
11743	start_process_time(hevc);
11744	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
11745	} else{
11746	hevc->dec_result = DEC_RESULT_GET_DATA_RETRY;
11747
11748	/*hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL,
11749	* "amvdec_vh265: Insufficient data\n");
11750	*/
11751
11752	vdec_schedule_work(&hevc->work);
11753	}
11754	return;
11755	} else if (hevc->dec_result == DEC_RESULT_DONE) {
11756	/* if (!hevc->ctx_valid)
11757	hevc->ctx_valid = 1; */
11758	decode_frame_count[hevc->index]++;
11759	#ifdef DETREFILL_ENABLE
11760	if (hevc->is_swap &&
11761	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM) {
11762	if (hevc->delrefill_check == 2) {
11763	delrefill(hevc);
11764	amhevc_stop();
11765	}
11766	}
11767	#endif
11768	if (hevc->mmu_enable && ((hevc->double_write_mode & 0x10) == 0)) {
11769	hevc->used_4k_num =
11770	READ_VREG(HEVC_SAO_MMU_STATUS) >> 16;
11771	if (hevc->used_4k_num >= 0 &&
11772	hevc->cur_pic &&
11773	hevc->cur_pic->scatter_alloc
11774	== 1) {
11775	hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
11776	"%s pic index %d scatter_alloc %d page_start %d\n",
11777	"decoder_mmu_box_free_idx_tail",
11778	hevc->cur_pic->index,
11779	hevc->cur_pic->scatter_alloc,
11780	hevc->used_4k_num);
11781	if (hevc->m_ins_flag)
11782	hevc_mmu_dma_check(hw_to_vdec(hevc));
11783	decoder_mmu_box_free_idx_tail(
11784	hevc->mmu_box,
11785	hevc->cur_pic->index,
11786	hevc->used_4k_num);
11787	hevc->cur_pic->scatter_alloc = 2;
11788	}
11789	}
11790	hevc->pic_decoded_lcu_idx =
11791	READ_VREG(HEVC_PARSER_LCU_START)
11792	& 0xffffff;
11793
11794	if (vdec->master == NULL && vdec->slave == NULL &&
11795	hevc->empty_flag == 0) {
11796	hevc->over_decode =
11797	(READ_VREG(HEVC_SHIFT_STATUS) >> 15) & 0x1;
11798	if (hevc->over_decode)
11799	hevc_print(hevc, 0,
11800	"!!!Over decode\n");
11801	}
11802
11803	if (is_log_enable(hevc))
11804	add_log(hevc,
11805	"%s dec_result %d lcu %d used_mmu %d shiftbyte 0x%x decbytes 0x%x",
11806	__func__,
11807	hevc->dec_result,
11808	hevc->pic_decoded_lcu_idx,
11809	hevc->used_4k_num,
11810	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
11811	READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
11812	hevc->start_shift_bytes
11813	);
11814
11815	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11816	"%s dec_result %d (%x %x %x) lcu %d used_mmu %d shiftbyte 0x%x decbytes 0x%x\n",
11817	__func__,
11818	hevc->dec_result,
11819	READ_VREG(HEVC_STREAM_LEVEL),
11820	READ_VREG(HEVC_STREAM_WR_PTR),
11821	READ_VREG(HEVC_STREAM_RD_PTR),
11822	hevc->pic_decoded_lcu_idx,
11823	hevc->used_4k_num,
11824	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
11825	READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
11826	hevc->start_shift_bytes
11827	);
11828
11829	hevc->used_4k_num = -1;
11830
11831	check_pic_decoded_error(hevc,
11832	hevc->pic_decoded_lcu_idx);
11833	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11834	#if 1
11835	if (vdec->slave) {
11836	if (dv_debug & 0x1)
11837	vdec_set_flag(vdec->slave,
11838	VDEC_FLAG_SELF_INPUT_CONTEXT);
11839	else
11840	vdec_set_flag(vdec->slave,
11841	VDEC_FLAG_OTHER_INPUT_CONTEXT);
11842	}
11843	#else
11844	if (vdec->slave) {
11845	if (no_interleaved_el_slice)
11846	vdec_set_flag(vdec->slave,
11847	VDEC_FLAG_INPUT_KEEP_CONTEXT);
11848	/* this will move real HW pointer for input */
11849	else
11850	vdec_set_flag(vdec->slave, 0);
11851	/* this will not move real HW pointer
11852	*and SL layer decoding
11853	*will start from same stream position
11854	*as current BL decoder
11855	*/
11856	}
11857	#endif
11858	#endif
11859	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11860	hevc->shift_byte_count_lo
11861	= READ_VREG(HEVC_SHIFT_BYTE_COUNT);
11862	if (vdec->slave) {
11863	/*cur is base, found enhance*/
11864	struct hevc_state_s *hevc_el =
11865	(struct hevc_state_s *)
11866	vdec->slave->private;
11867	if (hevc_el)
11868	hevc_el->shift_byte_count_lo =
11869	hevc->shift_byte_count_lo;
11870	} else if (vdec->master) {
11871	/*cur is enhance, found base*/
11872	struct hevc_state_s *hevc_ba =
11873	(struct hevc_state_s *)
11874	vdec->master->private;
11875	if (hevc_ba)
11876	hevc_ba->shift_byte_count_lo =
11877	hevc->shift_byte_count_lo;
11878	}
11879	#endif
11880	mutex_lock(&hevc->chunks_mutex);
11881	vdec_vframe_dirty(hw_to_vdec(hevc), hevc->chunk);
11882	hevc->chunk = NULL;
11883	mutex_unlock(&hevc->chunks_mutex);
11884	} else if (hevc->dec_result == DEC_RESULT_AGAIN) {
11885	/*
11886	stream base: stream buf empty or timeout
11887	frame base: vdec_prepare_input fail
11888	*/
11889	if (!vdec_has_more_input(vdec)) {
11890	hevc->dec_result = DEC_RESULT_EOS;
11891	vdec_schedule_work(&hevc->work);
11892	return;
11893	}
11894	#ifdef AGAIN_HAS_THRESHOLD
11895	hevc->next_again_flag = 1;
11896	#endif
11897	} else if (hevc->dec_result == DEC_RESULT_EOS) {
11898	struct PIC_s *pic;
11899	hevc->eos = 1;
11900	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11901	if ((vdec->master || vdec->slave) &&
11902	aux_data_is_avaible(hevc))
11903	dolby_get_meta(hevc);
11904	#endif
11905	check_pic_decoded_error(hevc,
11906	hevc->pic_decoded_lcu_idx);
11907	pic = get_pic_by_POC(hevc, hevc->curr_POC);
11908	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11909	"%s: end of stream, last dec poc %d => 0x%pf\n",
11910	__func__, hevc->curr_POC, pic);
11911	flush_output(hevc, pic);
11912
11913	if (hevc->is_used_v4l)
11914	notify_v4l_eos(hw_to_vdec(hevc));
11915	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11916	hevc->shift_byte_count_lo
11917	= READ_VREG(HEVC_SHIFT_BYTE_COUNT);
11918	if (vdec->slave) {
11919	/*cur is base, found enhance*/
11920	struct hevc_state_s *hevc_el =
11921	(struct hevc_state_s *)
11922	vdec->slave->private;
11923	if (hevc_el)
11924	hevc_el->shift_byte_count_lo =
11925	hevc->shift_byte_count_lo;
11926	} else if (vdec->master) {
11927	/*cur is enhance, found base*/
11928	struct hevc_state_s *hevc_ba =
11929	(struct hevc_state_s *)
11930	vdec->master->private;
11931	if (hevc_ba)
11932	hevc_ba->shift_byte_count_lo =
11933	hevc->shift_byte_count_lo;
11934	}
11935	#endif
11936	mutex_lock(&hevc->chunks_mutex);
11937	vdec_vframe_dirty(hw_to_vdec(hevc), hevc->chunk);
11938	hevc->chunk = NULL;
11939	mutex_unlock(&hevc->chunks_mutex);
11940	} else if (hevc->dec_result == DEC_RESULT_FORCE_EXIT) {
11941	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
11942	"%s: force exit\n",
11943	__func__);
11944	if (hevc->stat & STAT_VDEC_RUN) {
11945	amhevc_stop();
11946	hevc->stat &= ~STAT_VDEC_RUN;
11947	}
11948	if (hevc->stat & STAT_ISR_REG) {
11949	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
11950	vdec_free_irq(VDEC_IRQ_0, (void *)hevc);
11951	hevc->stat &= ~STAT_ISR_REG;
11952	}
11953	hevc_print(hevc, 0, "%s: force exit end\n",
11954	__func__);
11955	}
11956
11957	if (hevc->stat & STAT_VDEC_RUN) {
11958	amhevc_stop();
11959	hevc->stat &= ~STAT_VDEC_RUN;
11960	}
11961
11962	if (hevc->stat & STAT_TIMER_ARM) {
11963	del_timer_sync(&hevc->timer);
11964	hevc->stat &= ~STAT_TIMER_ARM;
11965	}
11966
11967	wait_hevc_search_done(hevc);
11968	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
11969	if (hevc->switch_dvlayer_flag) {
11970	if (vdec->slave)
11971	vdec_set_next_sched(vdec, vdec->slave);
11972	else if (vdec->master)
11973	vdec_set_next_sched(vdec, vdec->master);
11974	} else if (vdec->slave || vdec->master)
11975	vdec_set_next_sched(vdec, vdec);
11976	#endif
11977
11978	if (from == 1) {
11979	/* This is a timeout work */
11980	if (work_pending(&hevc->work)) {
11981	/*
11982	* The vh265_work arrives at the last second,
11983	* give it a chance to handle the scenario.
11984	*/
11985	return;
11986	//cancel_work_sync(&hevc->work);//reserved for future considraion
11987	}
11988	}
11989
11990	/* mark itself has all HW resource released and input released */
11991	if (vdec->parallel_dec == 1)
11992	vdec_core_finish_run(vdec, CORE_MASK_HEVC);
11993	else
11994	vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
11995
11996	if (hevc->is_used_v4l) {
11997	struct aml_vcodec_ctx *ctx =
11998	(struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
11999
12000	if (ctx->param_sets_from_ucode &&
12001	!hevc->v4l_params_parsed)
12002	vdec_v4l_write_frame_sync(ctx);
12003	}
12004
12005	if (hevc->vdec_cb)
12006	hevc->vdec_cb(hw_to_vdec(hevc), hevc->vdec_cb_arg);
12007	}
12008
12009	static void vh265_work(struct work_struct *work)
12010	{
12011	struct hevc_state_s *hevc = container_of(work,
12012	struct hevc_state_s, work);
12013	struct vdec_s *vdec = hw_to_vdec(hevc);
12014
12015	vh265_work_implement(hevc, vdec, 0);
12016	}
12017
12018	static void vh265_timeout_work(struct work_struct *work)
12019	{
12020	struct hevc_state_s *hevc = container_of(work,
12021	struct hevc_state_s, timeout_work);
12022	struct vdec_s *vdec = hw_to_vdec(hevc);
12023
12024	if (work_pending(&hevc->work))
12025	return;
12026	vh265_work_implement(hevc, vdec, 1);
12027	}
12028
12029
12030	static int vh265_hw_ctx_restore(struct hevc_state_s *hevc)
12031	{
12032	/* new to do ... */
12033	vh265_prot_init(hevc);
12034	return 0;
12035	}
12036	static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
12037	{
12038	struct hevc_state_s *hevc =
12039	(struct hevc_state_s *)vdec->private;
12040	int tvp = vdec_secure(hw_to_vdec(hevc)) ?
12041	CODEC_MM_FLAGS_TVP : 0;
12042	bool ret = 0;
12043	if (step == 0x12)
12044	return 0;
12045	else if (step == 0x11)
12046	step = 0x12;
12047
12048	if (hevc->eos)
12049	return 0;
12050	if (!hevc->first_sc_checked && hevc->mmu_enable) {
12051	int size = decoder_mmu_box_sc_check(hevc->mmu_box, tvp);
12052	hevc->first_sc_checked =1;
12053	hevc_print(hevc, 0,
12054	"vh265 cached=%d need_size=%d speed= %d ms\n",
12055	size, (hevc->need_cache_size >> PAGE_SHIFT),
12056	(int)(get_jiffies_64() - hevc->sc_start_time) * 1000/HZ);
12057	}
12058	if (vdec_stream_based(vdec) && (hevc->init_flag == 0)
12059	&& pre_decode_buf_level != 0) {
12060	u32 rp, wp, level;
12061
12062	rp = READ_PARSER_REG(PARSER_VIDEO_RP);
12063	wp = READ_PARSER_REG(PARSER_VIDEO_WP);
12064	if (wp < rp)
12065	level = vdec->input.size + wp - rp;
12066	else
12067	level = wp - rp;
12068
12069	if (level < pre_decode_buf_level)
12070	return 0;
12071	}
12072
12073	#ifdef AGAIN_HAS_THRESHOLD
12074	if (hevc->next_again_flag &&
12075	(!vdec_frame_based(vdec))) {
12076	u32 parser_wr_ptr =
12077	READ_PARSER_REG(PARSER_VIDEO_WP);
12078	if (parser_wr_ptr >= hevc->pre_parser_wr_ptr &&
12079	(parser_wr_ptr - hevc->pre_parser_wr_ptr) <
12080	again_threshold) {
12081	int r = vdec_sync_input(vdec);
12082	hevc_print(hevc,
12083	PRINT_FLAG_VDEC_DETAIL, "%s buf lelvel:%x\n", __func__, r);
12084	return 0;
12085	}
12086	}
12087	#endif
12088
12089	if (disp_vframe_valve_level &&
12090	kfifo_len(&hevc->display_q) >=
12091	disp_vframe_valve_level) {
12092	hevc->valve_count--;
12093	if (hevc->valve_count <= 0)
12094	hevc->valve_count = 2;
12095	else
12096	return 0;
12097	}
12098
12099	ret = is_new_pic_available(hevc);
12100	if (!ret) {
12101	hevc_print(hevc,
12102	PRINT_FLAG_VDEC_DETAIL, "%s=>%d\r\n",
12103	__func__, ret);
12104	}
12105
12106	#ifdef CONSTRAIN_MAX_BUF_NUM
12107	if (hevc->pic_list_init_flag == 3) {
12108	if (run_ready_max_vf_only_num > 0 &&
12109	get_vf_ref_only_buf_count(hevc) >=
12110	run_ready_max_vf_only_num
12111	)
12112	ret = 0;
12113	if (run_ready_display_q_num > 0 &&
12114	kfifo_len(&hevc->display_q) >=
12115	run_ready_display_q_num)
12116	ret = 0;
12117
12118	/*avoid more buffers consumed when
12119	switching resolution*/
12120	if (run_ready_max_buf_num == 0xff &&
12121	get_used_buf_count(hevc) >=
12122	get_work_pic_num(hevc))
12123	ret = 0;
12124	else if (run_ready_max_buf_num &&
12125	get_used_buf_count(hevc) >=
12126	run_ready_max_buf_num)
12127	ret = 0;
12128	}
12129	#endif
12130
12131	if (hevc->is_used_v4l) {
12132	struct aml_vcodec_ctx *ctx =
12133	(struct aml_vcodec_ctx *)(hevc->v4l2_ctx);
12134
12135	if (ctx->param_sets_from_ucode &&
12136	!ctx->v4l_codec_ready &&
12137	hevc->v4l_params_parsed) {
12138	ret = 0; /*the params has parsed.*/
12139	} else if (!ctx->v4l_codec_dpb_ready)
12140	ret = 0;
12141	}
12142
12143	if (ret)
12144	not_run_ready[hevc->index] = 0;
12145	else
12146	not_run_ready[hevc->index]++;
12147	if (vdec->parallel_dec == 1)
12148	return ret ? (CORE_MASK_HEVC) : 0;
12149	else
12150	return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0;
12151	}
12152
12153	static void run(struct vdec_s *vdec, unsigned long mask,
12154	void (*callback)(struct vdec_s *, void *), void *arg)
12155	{
12156	struct hevc_state_s *hevc =
12157	(struct hevc_state_s *)vdec->private;
12158	int r, loadr = 0;
12159	unsigned char check_sum = 0;
12160
12161	run_count[hevc->index]++;
12162	hevc->vdec_cb_arg = arg;
12163	hevc->vdec_cb = callback;
12164	hevc->aux_data_dirty = 1;
12165	hevc_reset_core(vdec);
12166
12167	#ifdef AGAIN_HAS_THRESHOLD
12168	hevc->pre_parser_wr_ptr =
12169	READ_PARSER_REG(PARSER_VIDEO_WP);
12170	hevc->next_again_flag = 0;
12171	#endif
12172	r = vdec_prepare_input(vdec, &hevc->chunk);
12173	if (r < 0) {
12174	input_empty[hevc->index]++;
12175	hevc->dec_result = DEC_RESULT_AGAIN;
12176	hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL,
12177	"ammvdec_vh265: Insufficient data\n");
12178
12179	vdec_schedule_work(&hevc->work);
12180	return;
12181	}
12182	input_empty[hevc->index] = 0;
12183	hevc->dec_result = DEC_RESULT_NONE;
12184	if (vdec_frame_based(vdec) &&
12185	((get_dbg_flag(hevc) & PRINT_FLAG_VDEC_STATUS)
12186	|| is_log_enable(hevc)))
12187	check_sum = get_data_check_sum(hevc, r);
12188
12189	if (is_log_enable(hevc))
12190	add_log(hevc,
12191	"%s: size 0x%x sum 0x%x shiftbyte 0x%x",
12192	__func__, r,
12193	check_sum,
12194	READ_VREG(HEVC_SHIFT_BYTE_COUNT)
12195	);
12196	hevc->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
12197	hevc_print(hevc, PRINT_FLAG_VDEC_STATUS,
12198	"%s: size 0x%x sum 0x%x (%x %x %x %x %x) byte count %x\n",
12199	__func__, r,
12200	check_sum,
12201	READ_VREG(HEVC_STREAM_LEVEL),
12202	READ_VREG(HEVC_STREAM_WR_PTR),
12203	READ_VREG(HEVC_STREAM_RD_PTR),
12204	READ_PARSER_REG(PARSER_VIDEO_RP),
12205	READ_PARSER_REG(PARSER_VIDEO_WP),
12206	hevc->start_shift_bytes
12207	);
12208	if ((get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) &&
12209	input_frame_based(vdec)) {
12210	int jj;
12211	u8 *data = NULL;
12212
12213	if (!hevc->chunk->block->is_mapped)
12214	data = codec_mm_vmap(hevc->chunk->block->start +
12215	hevc->chunk->offset, r);
12216	else
12217	data = ((u8 *)hevc->chunk->block->start_virt)
12218	+ hevc->chunk->offset;
12219
12220	for (jj = 0; jj < r; jj++) {
12221	if ((jj & 0xf) == 0)
12222	hevc_print(hevc, PRINT_FRAMEBASE_DATA,
12223	"%06x:", jj);
12224	hevc_print_cont(hevc, PRINT_FRAMEBASE_DATA,
12225	"%02x ", data[jj]);
12226	if (((jj + 1) & 0xf) == 0)
12227	hevc_print_cont(hevc, PRINT_FRAMEBASE_DATA,
12228	"\n");
12229	}
12230
12231	if (!hevc->chunk->block->is_mapped)
12232	codec_mm_unmap_phyaddr(data);
12233	}
12234	if (vdec->mc_loaded) {
12235	/*firmware have load before,
12236	and not changes to another.
12237	ignore reload.
12238	*/
12239	if (tee_enabled() && hevc->is_swap &&
12240	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
12241	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, hevc->swap_addr);
12242	} else {
12243	if (hevc->mmu_enable)
12244	if (get_cpu_major_id() > AM_MESON_CPU_MAJOR_ID_GXM)
12245	loadr = amhevc_vdec_loadmc_ex(VFORMAT_HEVC, vdec,
12246	"h265_mmu", hevc->fw->data);
12247	else {
12248	if (!hevc->is_4k) {
12249	/* if an older version of the fw was loaded, */
12250	/* needs try to load noswap fw because the */
12251	/* old fw package dose not contain the swap fw.*/
12252	loadr = amhevc_vdec_loadmc_ex(
12253	VFORMAT_HEVC, vdec,
12254	"hevc_mmu_swap",
12255	hevc->fw->data);
12256	if (loadr < 0)
12257	loadr = amhevc_vdec_loadmc_ex(
12258	VFORMAT_HEVC, vdec,
12259	"h265_mmu",
12260	hevc->fw->data);
12261	else
12262	hevc->is_swap = true;
12263	} else
12264	loadr = amhevc_vdec_loadmc_ex(
12265	VFORMAT_HEVC, vdec,
12266	"h265_mmu", hevc->fw->data);
12267	}
12268	else
12269	loadr = amhevc_vdec_loadmc_ex(VFORMAT_HEVC, vdec,
12270	NULL, hevc->fw->data);
12271	if (loadr < 0) {
12272	amhevc_disable();
12273	hevc_print(hevc, 0, "H265: the %s fw loading failed, err: %x\n",
12274	tee_enabled() ? "TEE" : "local", loadr);
12275	hevc->dec_result = DEC_RESULT_FORCE_EXIT;
12276	vdec_schedule_work(&hevc->work);
12277	return;
12278	}
12279
12280	if (tee_enabled() && hevc->is_swap &&
12281	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
12282	hevc->swap_addr = READ_VREG(HEVC_STREAM_SWAP_BUFFER2);
12283	#ifdef DETREFILL_ENABLE
12284	if (hevc->is_swap &&
12285	get_cpu_major_id() <= AM_MESON_CPU_MAJOR_ID_GXM)
12286	init_detrefill_buf(hevc);
12287	#endif
12288	vdec->mc_loaded = 1;
12289	vdec->mc_type = VFORMAT_HEVC;
12290	}
12291	if (vh265_hw_ctx_restore(hevc) < 0) {
12292	vdec_schedule_work(&hevc->work);
12293	return;
12294	}
12295	vdec_enable_input(vdec);
12296
12297	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
12298
12299	if (vdec_frame_based(vdec)) {
12300	WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
12301	r = hevc->chunk->size +
12302	(hevc->chunk->offset & (VDEC_FIFO_ALIGN - 1));
12303	hevc->decode_size = r;
12304	}
12305	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
12306	else {
12307	if (vdec->master || vdec->slave)
12308	WRITE_VREG(HEVC_SHIFT_BYTE_COUNT,
12309	hevc->shift_byte_count_lo);
12310	}
12311	#endif
12312	WRITE_VREG(HEVC_DECODE_SIZE, r);
12313	/*WRITE_VREG(HEVC_DECODE_COUNT, hevc->decode_idx);*/
12314	hevc->init_flag = 1;
12315
12316	if (hevc->pic_list_init_flag == 3)
12317	init_pic_list_hw(hevc);
12318
12319	backup_decode_state(hevc);
12320
12321	start_process_time(hevc);
12322	mod_timer(&hevc->timer, jiffies);
12323	hevc->stat |= STAT_TIMER_ARM;
12324	hevc->stat |= STAT_ISR_REG;
12325	amhevc_start();
12326	hevc->stat |= STAT_VDEC_RUN;
12327	}
12328
12329	static void aml_free_canvas(struct vdec_s *vdec)
12330	{
12331	int i;
12332	struct hevc_state_s *hevc =
12333	(struct hevc_state_s *)vdec->private;
12334
12335	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
12336	struct PIC_s *pic = hevc->m_PIC[i];
12337
12338	if (pic) {
12339	if (vdec->parallel_dec == 1) {
12340	vdec->free_canvas_ex(pic->y_canvas_index, vdec->id);
12341	vdec->free_canvas_ex(pic->uv_canvas_index, vdec->id);
12342	}
12343	}
12344	}
12345	}
12346
12347	static void reset(struct vdec_s *vdec)
12348	{
12349
12350	struct hevc_state_s *hevc =
12351	(struct hevc_state_s *)vdec->private;
12352	int i;
12353
12354	cancel_work_sync(&hevc->work);
12355	cancel_work_sync(&hevc->notify_work);
12356	if (hevc->stat & STAT_VDEC_RUN) {
12357	amhevc_stop();
12358	hevc->stat &= ~STAT_VDEC_RUN;
12359	}
12360
12361	if (hevc->stat & STAT_TIMER_ARM) {
12362	del_timer_sync(&hevc->timer);
12363	hevc->stat &= ~STAT_TIMER_ARM;
12364	}
12365	hevc->dec_result = DEC_RESULT_NONE;
12366	reset_process_time(hevc);
12367	hevc->init_flag = 0;
12368	hevc->pic_list_init_flag = 0;
12369	dealloc_mv_bufs(hevc);
12370	aml_free_canvas(vdec);
12371	hevc_local_uninit(hevc);
12372	if (vh265_local_init(hevc) < 0)
12373	pr_debug(" %s local init fail\n", __func__);
12374	for (i = 0; i < BUF_POOL_SIZE; i++) {
12375	hevc->m_BUF[i].start_adr = 0;
12376	}
12377
12378	hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
12379	}
12380
12381	static irqreturn_t vh265_irq_cb(struct vdec_s *vdec, int irq)
12382	{
12383	struct hevc_state_s *hevc =
12384	(struct hevc_state_s *)vdec->private;
12385
12386	return vh265_isr(0, hevc);
12387	}
12388
12389	static irqreturn_t vh265_threaded_irq_cb(struct vdec_s *vdec, int irq)
12390	{
12391	struct hevc_state_s *hevc =
12392	(struct hevc_state_s *)vdec->private;
12393
12394	return vh265_isr_thread_fn(0, hevc);
12395	}
12396	#endif
12397
12398	static int amvdec_h265_probe(struct platform_device *pdev)
12399	{
12400	#ifdef MULTI_INSTANCE_SUPPORT
12401	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
12402	#else
12403	struct vdec_dev_reg_s *pdata =
12404	(struct vdec_dev_reg_s *)pdev->dev.platform_data;
12405	#endif
12406	char *tmpbuf;
12407	int ret;
12408	struct hevc_state_s *hevc;
12409
12410	hevc = vmalloc(sizeof(struct hevc_state_s));
12411	if (hevc == NULL) {
12412	hevc_print(hevc, 0, "%s vmalloc hevc failed\r\n", __func__);
12413	return -ENOMEM;
12414	}
12415	gHevc = hevc;
12416	if ((debug & H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0)
12417	debug &= (~(H265_DEBUG_DIS_LOC_ERROR_PROC |
12418	H265_DEBUG_DIS_SYS_ERROR_PROC));
12419	memset(hevc, 0, sizeof(struct hevc_state_s));
12420	if (get_dbg_flag(hevc))
12421	hevc_print(hevc, 0, "%s\r\n", __func__);
12422	mutex_lock(&vh265_mutex);
12423
12424	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) &&
12425	(parser_sei_enable & 0x100) == 0)
12426	parser_sei_enable = 7; /*old 1*/
12427	hevc->m_ins_flag = 0;
12428	hevc->init_flag = 0;
12429	hevc->first_sc_checked = 0;
12430	hevc->uninit_list = 0;
12431	hevc->fatal_error = 0;
12432	hevc->show_frame_num = 0;
12433	hevc->frameinfo_enable = 1;
12434	#ifdef MULTI_INSTANCE_SUPPORT
12435	hevc->platform_dev = pdev;
12436	platform_set_drvdata(pdev, pdata);
12437	#endif
12438
12439	if (pdata == NULL) {
12440	hevc_print(hevc, 0,
12441	"\namvdec_h265 memory resource undefined.\n");
12442	vfree(hevc);
12443	mutex_unlock(&vh265_mutex);
12444	return -EFAULT;
12445	}
12446	if (mmu_enable_force == 0) {
12447	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_GXL
12448	|| double_write_mode == 0x10)
12449	hevc->mmu_enable = 0;
12450	else
12451	hevc->mmu_enable = 1;
12452	}
12453	if (init_mmu_buffers(hevc)) {
12454	hevc_print(hevc, 0,
12455	"\n 265 mmu init failed!\n");
12456	vfree(hevc);
12457	mutex_unlock(&vh265_mutex);
12458	return -EFAULT;
12459	}
12460
12461	ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box, BMMU_WORKSPACE_ID,
12462	work_buf_size, DRIVER_NAME, &hevc->buf_start);
12463	if (ret < 0) {
12464	uninit_mmu_buffers(hevc);
12465	vfree(hevc);
12466	mutex_unlock(&vh265_mutex);
12467	return ret;
12468	}
12469	hevc->buf_size = work_buf_size;
12470
12471
12472	if (!vdec_secure(pdata)) {
12473	tmpbuf = (char *)codec_mm_phys_to_virt(hevc->buf_start);
12474	if (tmpbuf) {
12475	memset(tmpbuf, 0, work_buf_size);
12476	dma_sync_single_for_device(amports_get_dma_device(),
12477	hevc->buf_start,
12478	work_buf_size, DMA_TO_DEVICE);
12479	} else {
12480	tmpbuf = codec_mm_vmap(hevc->buf_start,
12481	work_buf_size);
12482	if (tmpbuf) {
12483	memset(tmpbuf, 0, work_buf_size);
12484	dma_sync_single_for_device(
12485	amports_get_dma_device(),
12486	hevc->buf_start,
12487	work_buf_size,
12488	DMA_TO_DEVICE);
12489	codec_mm_unmap_phyaddr(tmpbuf);
12490	}
12491	}
12492	}
12493
12494	if (get_dbg_flag(hevc)) {
12495	hevc_print(hevc, 0,
12496	"===H.265 decoder mem resource 0x%lx size 0x%x\n",
12497	hevc->buf_start, hevc->buf_size);
12498	}
12499
12500	if (pdata->sys_info)
12501	hevc->vh265_amstream_dec_info = *pdata->sys_info;
12502	else {
12503	hevc->vh265_amstream_dec_info.width = 0;
12504	hevc->vh265_amstream_dec_info.height = 0;
12505	hevc->vh265_amstream_dec_info.rate = 30;
12506	}
12507	#ifndef MULTI_INSTANCE_SUPPORT
12508	if (pdata->flag & DEC_FLAG_HEVC_WORKAROUND) {
12509	workaround_enable |= 3;
12510	hevc_print(hevc, 0,
12511	"amvdec_h265 HEVC_WORKAROUND flag set.\n");
12512	} else
12513	workaround_enable &= ~3;
12514	#endif
12515	hevc->cma_dev = pdata->cma_dev;
12516	vh265_vdec_info_init();
12517
12518	#ifdef MULTI_INSTANCE_SUPPORT
12519	pdata->private = hevc;
12520	pdata->dec_status = vh265_dec_status;
12521	pdata->set_isreset = vh265_set_isreset;
12522	is_reset = 0;
12523	if (vh265_init(pdata) < 0) {
12524	#else
12525	if (vh265_init(hevc) < 0) {
12526	#endif
12527	hevc_print(hevc, 0,
12528	"\namvdec_h265 init failed.\n");
12529	hevc_local_uninit(hevc);
12530	uninit_mmu_buffers(hevc);
12531	vfree(hevc);
12532	pdata->dec_status = NULL;
12533	mutex_unlock(&vh265_mutex);
12534	return -ENODEV;
12535	}
12536	/*set the max clk for smooth playing...*/
12537	hevc_source_changed(VFORMAT_HEVC,
12538	3840, 2160, 60);
12539	mutex_unlock(&vh265_mutex);
12540
12541	return 0;
12542	}
12543
12544	static int amvdec_h265_remove(struct platform_device *pdev)
12545	{
12546	struct hevc_state_s *hevc = gHevc;
12547
12548	if (get_dbg_flag(hevc))
12549	hevc_print(hevc, 0, "%s\r\n", __func__);
12550
12551	mutex_lock(&vh265_mutex);
12552
12553	vh265_stop(hevc);
12554
12555	hevc_source_changed(VFORMAT_HEVC, 0, 0, 0);
12556
12557
12558	#ifdef DEBUG_PTS
12559	hevc_print(hevc, 0,
12560	"pts missed %ld, pts hit %ld, duration %d\n",
12561	hevc->pts_missed, hevc->pts_hit, hevc->frame_dur);
12562	#endif
12563
12564	vfree(hevc);
12565	hevc = NULL;
12566	gHevc = NULL;
12567
12568	mutex_unlock(&vh265_mutex);
12569
12570	return 0;
12571	}
12572	/****************************************/
12573	#ifdef CONFIG_PM
12574	static int h265_suspend(struct device *dev)
12575	{
12576	amhevc_suspend(to_platform_device(dev), dev->power.power_state);
12577	return 0;
12578	}
12579
12580	static int h265_resume(struct device *dev)
12581	{
12582	amhevc_resume(to_platform_device(dev));
12583	return 0;
12584	}
12585
12586	static const struct dev_pm_ops h265_pm_ops = {
12587	SET_SYSTEM_SLEEP_PM_OPS(h265_suspend, h265_resume)
12588	};
12589	#endif
12590
12591	static struct platform_driver amvdec_h265_driver = {
12592	.probe = amvdec_h265_probe,
12593	.remove = amvdec_h265_remove,
12594	.driver = {
12595	.name = DRIVER_NAME,
12596	#ifdef CONFIG_PM
12597	.pm = &h265_pm_ops,
12598	#endif
12599	}
12600	};
12601
12602	#ifdef MULTI_INSTANCE_SUPPORT
12603	static void vh265_dump_state(struct vdec_s *vdec)
12604	{
12605	int i;
12606	struct hevc_state_s *hevc =
12607	(struct hevc_state_s *)vdec->private;
12608	hevc_print(hevc, 0,
12609	"====== %s\n", __func__);
12610
12611	hevc_print(hevc, 0,
12612	"width/height (%d/%d), reorder_pic_num %d buf count(bufspec size) %d, video_signal_type 0x%x, is_swap %d\n",
12613	hevc->frame_width,
12614	hevc->frame_height,
12615	hevc->sps_num_reorder_pics_0,
12616	get_work_pic_num(hevc),
12617	hevc->video_signal_type_debug,
12618	hevc->is_swap
12619	);
12620
12621	hevc_print(hevc, 0,
12622	"is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n",
12623	input_frame_based(vdec),
12624	hevc->eos,
12625	hevc->dec_result,
12626	decode_frame_count[hevc->index],
12627	display_frame_count[hevc->index],
12628	run_count[hevc->index],
12629	not_run_ready[hevc->index],
12630	input_empty[hevc->index]
12631	);
12632
12633	if (vf_get_receiver(vdec->vf_provider_name)) {
12634	enum receviver_start_e state =
12635	vf_notify_receiver(vdec->vf_provider_name,
12636	VFRAME_EVENT_PROVIDER_QUREY_STATE,
12637	NULL);
12638	hevc_print(hevc, 0,
12639	"\nreceiver(%s) state %d\n",
12640	vdec->vf_provider_name,
12641	state);
12642	}
12643
12644	hevc_print(hevc, 0,
12645	"%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), pic_list_init_flag(%d), is_new_pic_available(%d)\n",
12646	__func__,
12647	kfifo_len(&hevc->newframe_q),
12648	VF_POOL_SIZE,
12649	kfifo_len(&hevc->display_q),
12650	VF_POOL_SIZE,
12651	hevc->vf_pre_count,
12652	hevc->vf_get_count,
12653	hevc->vf_put_count,
12654	hevc->pic_list_init_flag,
12655	is_new_pic_available(hevc)
12656	);
12657
12658	dump_pic_list(hevc);
12659
12660	for (i = 0; i < BUF_POOL_SIZE; i++) {
12661	hevc_print(hevc, 0,
12662	"Buf(%d) start_adr 0x%x size 0x%x used %d\n",
12663	i,
12664	hevc->m_BUF[i].start_adr,
12665	hevc->m_BUF[i].size,
12666	hevc->m_BUF[i].used_flag);
12667	}
12668
12669	for (i = 0; i < MAX_REF_PIC_NUM; i++) {
12670	hevc_print(hevc, 0,
12671	"mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
12672	i,
12673	hevc->m_mv_BUF[i].start_adr,
12674	hevc->m_mv_BUF[i].size,
12675	hevc->m_mv_BUF[i].used_flag);
12676	}
12677
12678	hevc_print(hevc, 0,
12679	"HEVC_DEC_STATUS_REG=0x%x\n",
12680	READ_VREG(HEVC_DEC_STATUS_REG));
12681	hevc_print(hevc, 0,
12682	"HEVC_MPC_E=0x%x\n",
12683	READ_VREG(HEVC_MPC_E));
12684	hevc_print(hevc, 0,
12685	"HEVC_DECODE_MODE=0x%x\n",
12686	READ_VREG(HEVC_DECODE_MODE));
12687	hevc_print(hevc, 0,
12688	"HEVC_DECODE_MODE2=0x%x\n",
12689	READ_VREG(HEVC_DECODE_MODE2));
12690	hevc_print(hevc, 0,
12691	"NAL_SEARCH_CTL=0x%x\n",
12692	READ_VREG(NAL_SEARCH_CTL));
12693	hevc_print(hevc, 0,
12694	"HEVC_PARSER_LCU_START=0x%x\n",
12695	READ_VREG(HEVC_PARSER_LCU_START));
12696	hevc_print(hevc, 0,
12697	"HEVC_DECODE_SIZE=0x%x\n",
12698	READ_VREG(HEVC_DECODE_SIZE));
12699	hevc_print(hevc, 0,
12700	"HEVC_SHIFT_BYTE_COUNT=0x%x\n",
12701	READ_VREG(HEVC_SHIFT_BYTE_COUNT));
12702	hevc_print(hevc, 0,
12703	"HEVC_STREAM_START_ADDR=0x%x\n",
12704	READ_VREG(HEVC_STREAM_START_ADDR));
12705	hevc_print(hevc, 0,
12706	"HEVC_STREAM_END_ADDR=0x%x\n",
12707	READ_VREG(HEVC_STREAM_END_ADDR));
12708	hevc_print(hevc, 0,
12709	"HEVC_STREAM_LEVEL=0x%x\n",
12710	READ_VREG(HEVC_STREAM_LEVEL));
12711	hevc_print(hevc, 0,
12712	"HEVC_STREAM_WR_PTR=0x%x\n",
12713	READ_VREG(HEVC_STREAM_WR_PTR));
12714	hevc_print(hevc, 0,
12715	"HEVC_STREAM_RD_PTR=0x%x\n",
12716	READ_VREG(HEVC_STREAM_RD_PTR));
12717	hevc_print(hevc, 0,
12718	"PARSER_VIDEO_RP=0x%x\n",
12719	READ_PARSER_REG(PARSER_VIDEO_RP));
12720	hevc_print(hevc, 0,
12721	"PARSER_VIDEO_WP=0x%x\n",
12722	READ_PARSER_REG(PARSER_VIDEO_WP));
12723
12724	if (input_frame_based(vdec) &&
12725	(get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA)
12726	) {
12727	int jj;
12728	if (hevc->chunk && hevc->chunk->block &&
12729	hevc->chunk->size > 0) {
12730	u8 *data = NULL;
12731	if (!hevc->chunk->block->is_mapped)
12732	data = codec_mm_vmap(hevc->chunk->block->start +
12733	hevc->chunk->offset, hevc->chunk->size);
12734	else
12735	data = ((u8 *)hevc->chunk->block->start_virt)
12736	+ hevc->chunk->offset;
12737	hevc_print(hevc, 0,
12738	"frame data size 0x%x\n",
12739	hevc->chunk->size);
12740	for (jj = 0; jj < hevc->chunk->size; jj++) {
12741	if ((jj & 0xf) == 0)
12742	hevc_print(hevc,
12743	PRINT_FRAMEBASE_DATA,
12744	"%06x:", jj);
12745	hevc_print_cont(hevc,
12746	PRINT_FRAMEBASE_DATA,
12747	"%02x ", data[jj]);
12748	if (((jj + 1) & 0xf) == 0)
12749	hevc_print_cont(hevc,
12750	PRINT_FRAMEBASE_DATA,
12751	"\n");
12752	}
12753
12754	if (!hevc->chunk->block->is_mapped)
12755	codec_mm_unmap_phyaddr(data);
12756	}
12757	}
12758
12759	}
12760
12761
12762	static int ammvdec_h265_probe(struct platform_device *pdev)
12763	{
12764
12765	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
12766	struct hevc_state_s *hevc = NULL;
12767	int ret;
12768	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
12769	int config_val;
12770	#endif
12771	if (pdata == NULL) {
12772	pr_info("\nammvdec_h265 memory resource undefined.\n");
12773	return -EFAULT;
12774	}
12775
12776	/* hevc = (struct hevc_state_s *)devm_kzalloc(&pdev->dev,
12777	sizeof(struct hevc_state_s), GFP_KERNEL); */
12778	hevc = vmalloc(sizeof(struct hevc_state_s));
12779	if (hevc == NULL) {
12780	pr_info("\nammvdec_h265 device data allocation failed\n");
12781	return -ENOMEM;
12782	}
12783	memset(hevc, 0, sizeof(struct hevc_state_s));
12784
12785	/* the ctx from v4l2 driver. */
12786	hevc->v4l2_ctx = pdata->private;
12787
12788	pdata->private = hevc;
12789	pdata->dec_status = vh265_dec_status;
12790	/* pdata->set_trickmode = set_trickmode; */
12791	pdata->run_ready = run_ready;
12792	pdata->run = run;
12793	pdata->reset = reset;
12794	pdata->irq_handler = vh265_irq_cb;
12795	pdata->threaded_irq_handler = vh265_threaded_irq_cb;
12796	pdata->dump_state = vh265_dump_state;
12797
12798	hevc->index = pdev->id;
12799	hevc->m_ins_flag = 1;
12800
12801	if (pdata->use_vfm_path) {
12802	snprintf(pdata->vf_provider_name,
12803	VDEC_PROVIDER_NAME_SIZE,
12804	VFM_DEC_PROVIDER_NAME);
12805	hevc->frameinfo_enable = 1;
12806	}
12807	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
12808	else if (vdec_dual(pdata)) {
12809	struct hevc_state_s *hevc_pair = NULL;
12810
12811	if (dv_toggle_prov_name) /*debug purpose*/
12812	snprintf(pdata->vf_provider_name,
12813	VDEC_PROVIDER_NAME_SIZE,
12814	(pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME :
12815	VFM_DEC_DVEL_PROVIDER_NAME);
12816	else
12817	snprintf(pdata->vf_provider_name,
12818	VDEC_PROVIDER_NAME_SIZE,
12819	(pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME :
12820	VFM_DEC_DVBL_PROVIDER_NAME);
12821	hevc->dolby_enhance_flag = pdata->master ? 1 : 0;
12822	if (pdata->master)
12823	hevc_pair = (struct hevc_state_s *)
12824	pdata->master->private;
12825	else if (pdata->slave)
12826	hevc_pair = (struct hevc_state_s *)
12827	pdata->slave->private;
12828	if (hevc_pair)
12829	hevc->shift_byte_count_lo =
12830	hevc_pair->shift_byte_count_lo;
12831	}
12832	#endif
12833	else
12834	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
12835	MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
12836
12837	vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
12838	&vh265_vf_provider, pdata);
12839
12840	hevc->provider_name = pdata->vf_provider_name;
12841	platform_set_drvdata(pdev, pdata);
12842
12843	hevc->platform_dev = pdev;
12844
12845	if (((get_dbg_flag(hevc) & IGNORE_PARAM_FROM_CONFIG) == 0) &&
12846	pdata->config && pdata->config_len) {
12847	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
12848	/*use ptr config for doubel_write_mode, etc*/
12849	hevc_print(hevc, 0, "pdata->config=%s\n", pdata->config);
12850
12851	if (get_config_int(pdata->config, "hevc_double_write_mode",
12852	&config_val) == 0)
12853	hevc->double_write_mode = config_val;
12854	else
12855	hevc->double_write_mode = double_write_mode;
12856
12857	if (get_config_int(pdata->config, "save_buffer_mode",
12858	&config_val) == 0)
12859	hevc->save_buffer_mode = config_val;
12860	else
12861	hevc->save_buffer_mode = 0;
12862
12863	/*use ptr config for max_pic_w, etc*/
12864	if (get_config_int(pdata->config, "hevc_buf_width",
12865	&config_val) == 0) {
12866	hevc->max_pic_w = config_val;
12867	}
12868	if (get_config_int(pdata->config, "hevc_buf_height",
12869	&config_val) == 0) {
12870	hevc->max_pic_h = config_val;
12871	}
12872
12873	if (get_config_int(pdata->config,
12874	"parm_v4l_codec_enable",
12875	&config_val) == 0)
12876	hevc->is_used_v4l = config_val;
12877
12878	if (get_config_int(pdata->config,
12879	"parm_v4l_buffer_margin",
12880	&config_val) == 0)
12881	hevc->dynamic_buf_num_margin = config_val;
12882	#endif
12883	} else {
12884	if (pdata->sys_info)
12885	hevc->vh265_amstream_dec_info = *pdata->sys_info;
12886	else {
12887	hevc->vh265_amstream_dec_info.width = 0;
12888	hevc->vh265_amstream_dec_info.height = 0;
12889	hevc->vh265_amstream_dec_info.rate = 30;
12890	}
12891	hevc->double_write_mode = double_write_mode;
12892	}
12893	if (!hevc->is_used_v4l) {
12894	if (hevc->save_buffer_mode && dynamic_buf_num_margin > 2)
12895	hevc->dynamic_buf_num_margin = dynamic_buf_num_margin -2;
12896	else
12897	hevc->dynamic_buf_num_margin = dynamic_buf_num_margin;
12898	}
12899
12900	if (mmu_enable_force == 0) {
12901	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_GXL)
12902	hevc->mmu_enable = 0;
12903	else
12904	hevc->mmu_enable = 1;
12905	}
12906
12907	if (init_mmu_buffers(hevc) < 0) {
12908	hevc_print(hevc, 0,
12909	"\n 265 mmu init failed!\n");
12910	mutex_unlock(&vh265_mutex);
12911	/* devm_kfree(&pdev->dev, (void *)hevc);*/
12912	if (hevc)
12913	vfree((void *)hevc);
12914	pdata->dec_status = NULL;
12915	return -EFAULT;
12916	}
12917	#if 0
12918	hevc->buf_start = pdata->mem_start;
12919	hevc->buf_size = pdata->mem_end - pdata->mem_start + 1;
12920	#else
12921
12922	ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box,
12923	BMMU_WORKSPACE_ID, work_buf_size,
12924	DRIVER_NAME, &hevc->buf_start);
12925	if (ret < 0) {
12926	uninit_mmu_buffers(hevc);
12927	/* devm_kfree(&pdev->dev, (void *)hevc); */
12928	if (hevc)
12929	vfree((void *)hevc);
12930	pdata->dec_status = NULL;
12931	mutex_unlock(&vh265_mutex);
12932	return ret;
12933	}
12934	hevc->buf_size = work_buf_size;
12935	#endif
12936	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXTVBB) &&
12937	(parser_sei_enable & 0x100) == 0)
12938	parser_sei_enable = 7;
12939	hevc->init_flag = 0;
12940	hevc->first_sc_checked = 0;
12941	hevc->uninit_list = 0;
12942	hevc->fatal_error = 0;
12943	hevc->show_frame_num = 0;
12944
12945	/*
12946	*hevc->mc_buf_spec.buf_end = pdata->mem_end + 1;
12947	*for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
12948	* amvh265_workbuff_spec[i].start_adr = pdata->mem_start;
12949	*/
12950	if (get_dbg_flag(hevc)) {
12951	hevc_print(hevc, 0,
12952	"===H.265 decoder mem resource 0x%lx size 0x%x\n",
12953	hevc->buf_start, hevc->buf_size);
12954	}
12955
12956	hevc_print(hevc, 0,
12957	"dynamic_buf_num_margin=%d\n",
12958	hevc->dynamic_buf_num_margin);
12959	hevc_print(hevc, 0,
12960	"double_write_mode=%d\n",
12961	hevc->double_write_mode);
12962
12963	hevc->cma_dev = pdata->cma_dev;
12964
12965	if (vh265_init(pdata) < 0) {
12966	hevc_print(hevc, 0,
12967	"\namvdec_h265 init failed.\n");
12968	hevc_local_uninit(hevc);
12969	uninit_mmu_buffers(hevc);
12970	/* devm_kfree(&pdev->dev, (void *)hevc); */
12971	if (hevc)
12972	vfree((void *)hevc);
12973	pdata->dec_status = NULL;
12974	return -ENODEV;
12975	}
12976
12977	vdec_set_prepare_level(pdata, start_decode_buf_level);
12978
12979	/*set the max clk for smooth playing...*/
12980	hevc_source_changed(VFORMAT_HEVC,
12981	3840, 2160, 60);
12982	if (pdata->parallel_dec == 1)
12983	vdec_core_request(pdata, CORE_MASK_HEVC);
12984	else
12985	vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
12986	| CORE_MASK_COMBINE);
12987
12988	return 0;
12989	}
12990
12991	static int ammvdec_h265_remove(struct platform_device *pdev)
12992	{
12993	struct hevc_state_s *hevc =
12994	(struct hevc_state_s *)
12995	(((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
12996	struct vdec_s *vdec = hw_to_vdec(hevc);
12997
12998	if (hevc == NULL)
12999	return 0;
13000
13001	if (get_dbg_flag(hevc))
13002	hevc_print(hevc, 0, "%s\r\n", __func__);
13003
13004	vmh265_stop(hevc);
13005
13006	/* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */
13007	if (vdec->parallel_dec == 1)
13008	vdec_core_release(hw_to_vdec(hevc), CORE_MASK_HEVC);
13009	else
13010	vdec_core_release(hw_to_vdec(hevc), CORE_MASK_HEVC);
13011
13012	vdec_set_status(hw_to_vdec(hevc), VDEC_STATUS_DISCONNECTED);
13013
13014	vfree((void *)hevc);
13015	return 0;
13016	}
13017
13018	static struct platform_driver ammvdec_h265_driver = {
13019	.probe = ammvdec_h265_probe,
13020	.remove = ammvdec_h265_remove,
13021	.driver = {
13022	.name = MULTI_DRIVER_NAME,
13023	#ifdef CONFIG_PM
13024	.pm = &h265_pm_ops,
13025	#endif
13026	}
13027	};
13028	#endif
13029
13030	static struct codec_profile_t amvdec_h265_profile = {
13031	.name = "hevc",
13032	.profile = ""
13033	};
13034
13035	static struct codec_profile_t amvdec_h265_profile_single,
13036	amvdec_h265_profile_mult;
13037
13038	static struct mconfig h265_configs[] = {
13039	MC_PU32("use_cma", &use_cma),
13040	MC_PU32("bit_depth_luma", &bit_depth_luma),
13041	MC_PU32("bit_depth_chroma", &bit_depth_chroma),
13042	MC_PU32("video_signal_type", &video_signal_type),
13043	#ifdef ERROR_HANDLE_DEBUG
13044	MC_PU32("dbg_nal_skip_flag", &dbg_nal_skip_flag),
13045	MC_PU32("dbg_nal_skip_count", &dbg_nal_skip_count),
13046	#endif
13047	MC_PU32("radr", &radr),
13048	MC_PU32("rval", &rval),
13049	MC_PU32("dbg_cmd", &dbg_cmd),
13050	MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
13051	MC_PU32("endian", &endian),
13052	MC_PU32("step", &step),
13053	MC_PU32("udebug_flag", &udebug_flag),
13054	MC_PU32("decode_pic_begin", &decode_pic_begin),
13055	MC_PU32("slice_parse_begin", &slice_parse_begin),
13056	MC_PU32("nal_skip_policy", &nal_skip_policy),
13057	MC_PU32("i_only_flag", &i_only_flag),
13058	MC_PU32("error_handle_policy", &error_handle_policy),
13059	MC_PU32("error_handle_threshold", &error_handle_threshold),
13060	MC_PU32("error_handle_nal_skip_threshold",
13061	&error_handle_nal_skip_threshold),
13062	MC_PU32("error_handle_system_threshold",
13063	&error_handle_system_threshold),
13064	MC_PU32("error_skip_nal_count", &error_skip_nal_count),
13065	MC_PU32("debug", &debug),
13066	MC_PU32("debug_mask", &debug_mask),
13067	MC_PU32("buffer_mode", &buffer_mode),
13068	MC_PU32("double_write_mode", &double_write_mode),
13069	MC_PU32("buf_alloc_width", &buf_alloc_width),
13070	MC_PU32("buf_alloc_height", &buf_alloc_height),
13071	MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
13072	MC_PU32("max_buf_num", &max_buf_num),
13073	MC_PU32("buf_alloc_size", &buf_alloc_size),
13074	MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
13075	MC_PU32("mem_map_mode", &mem_map_mode),
13076	MC_PU32("enable_mem_saving", &enable_mem_saving),
13077	MC_PU32("force_w_h", &force_w_h),
13078	MC_PU32("force_fps", &force_fps),
13079	MC_PU32("max_decoding_time", &max_decoding_time),
13080	MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size),
13081	MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size),
13082	MC_PU32("interlace_enable", &interlace_enable),
13083	MC_PU32("pts_unstable", &pts_unstable),
13084	MC_PU32("parser_sei_enable", &parser_sei_enable),
13085	MC_PU32("start_decode_buf_level", &start_decode_buf_level),
13086	MC_PU32("decode_timeout_val", &decode_timeout_val),
13087	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
13088	MC_PU32("parser_dolby_vision_enable", &parser_dolby_vision_enable),
13089	MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name),
13090	MC_PU32("dv_debug", &dv_debug),
13091	#endif
13092	};
13093	static struct mconfig_node decoder_265_node;
13094
13095	static int __init amvdec_h265_driver_init_module(void)
13096	{
13097	struct BuffInfo_s *p_buf_info;
13098
13099	if (vdec_is_support_4k()) {
13100	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
13101	p_buf_info = &amvh265_workbuff_spec[2];
13102	else
13103	p_buf_info = &amvh265_workbuff_spec[1];
13104	} else
13105	p_buf_info = &amvh265_workbuff_spec[0];
13106
13107	init_buff_spec(NULL, p_buf_info);
13108	work_buf_size =
13109	(p_buf_info->end_adr - p_buf_info->start_adr
13110	+ 0xffff) & (~0xffff);
13111
13112	pr_debug("amvdec_h265 module init\n");
13113	error_handle_policy = 0;
13114
13115	#ifdef ERROR_HANDLE_DEBUG
13116	dbg_nal_skip_flag = 0;
13117	dbg_nal_skip_count = 0;
13118	#endif
13119	udebug_flag = 0;
13120	decode_pic_begin = 0;
13121	slice_parse_begin = 0;
13122	step = 0;
13123	buf_alloc_size = 0;
13124
13125	#ifdef MULTI_INSTANCE_SUPPORT
13126	if (platform_driver_register(&ammvdec_h265_driver))
13127	pr_err("failed to register ammvdec_h265 driver\n");
13128
13129	#endif
13130	if (platform_driver_register(&amvdec_h265_driver)) {
13131	pr_err("failed to register amvdec_h265 driver\n");
13132	return -ENODEV;
13133	}
13134	#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/
13135	if (!has_hevc_vdec()) {
13136	/* not support hevc */
13137	amvdec_h265_profile.name = "hevc_unsupport";
13138	}
13139	if (vdec_is_support_4k()) {
13140	if (is_meson_m8m2_cpu()) {
13141	/* m8m2 support 4k */
13142	amvdec_h265_profile.profile = "4k";
13143	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
13144	amvdec_h265_profile.profile =
13145	"8k, 8bit, 10bit, dwrite, compressed";
13146	}else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB) {
13147	amvdec_h265_profile.profile =
13148	"4k, 8bit, 10bit, dwrite, compressed";
13149	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_MG9TV)
13150	amvdec_h265_profile.profile = "4k";
13151	}
13152	#endif
13153	if (codec_mm_get_total_size() < 80 * SZ_1M) {
13154	pr_info("amvdec_h265 default mmu enabled.\n");
13155	mmu_enable = 1;
13156	}
13157
13158	vcodec_profile_register(&amvdec_h265_profile);
13159	amvdec_h265_profile_single = amvdec_h265_profile;
13160	amvdec_h265_profile_single.name = "h265";
13161	vcodec_profile_register(&amvdec_h265_profile_single);
13162	amvdec_h265_profile_mult = amvdec_h265_profile;
13163	amvdec_h265_profile_mult.name = "mh265";
13164	vcodec_profile_register(&amvdec_h265_profile_mult);
13165	INIT_REG_NODE_CONFIGS("media.decoder", &decoder_265_node,
13166	"h265", h265_configs, CONFIG_FOR_RW);
13167	return 0;
13168	}
13169
13170	static void __exit amvdec_h265_driver_remove_module(void)
13171	{
13172	pr_debug("amvdec_h265 module remove.\n");
13173
13174	#ifdef MULTI_INSTANCE_SUPPORT
13175	platform_driver_unregister(&ammvdec_h265_driver);
13176	#endif
13177	platform_driver_unregister(&amvdec_h265_driver);
13178	}
13179
13180	/****************************************/
13181	/*
13182	*module_param(stat, uint, 0664);
13183	*MODULE_PARM_DESC(stat, "\n amvdec_h265 stat\n");
13184	*/
13185	module_param(use_cma, uint, 0664);
13186	MODULE_PARM_DESC(use_cma, "\n amvdec_h265 use_cma\n");
13187
13188	module_param(bit_depth_luma, uint, 0664);
13189	MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_h265 bit_depth_luma\n");
13190
13191	module_param(bit_depth_chroma, uint, 0664);
13192	MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_h265 bit_depth_chroma\n");
13193
13194	module_param(video_signal_type, uint, 0664);
13195	MODULE_PARM_DESC(video_signal_type, "\n amvdec_h265 video_signal_type\n");
13196
13197	#ifdef ERROR_HANDLE_DEBUG
13198	module_param(dbg_nal_skip_flag, uint, 0664);
13199	MODULE_PARM_DESC(dbg_nal_skip_flag, "\n amvdec_h265 dbg_nal_skip_flag\n");
13200
13201	module_param(dbg_nal_skip_count, uint, 0664);
13202	MODULE_PARM_DESC(dbg_nal_skip_count, "\n amvdec_h265 dbg_nal_skip_count\n");
13203	#endif
13204
13205	module_param(radr, uint, 0664);
13206	MODULE_PARM_DESC(radr, "\n radr\n");
13207
13208	module_param(rval, uint, 0664);
13209	MODULE_PARM_DESC(rval, "\n rval\n");
13210
13211	module_param(dbg_cmd, uint, 0664);
13212	MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
13213
13214	module_param(dump_nal, uint, 0664);
13215	MODULE_PARM_DESC(dump_nal, "\n dump_nal\n");
13216
13217	module_param(dbg_skip_decode_index, uint, 0664);
13218	MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
13219
13220	module_param(endian, uint, 0664);
13221	MODULE_PARM_DESC(endian, "\n rval\n");
13222
13223	module_param(step, uint, 0664);
13224	MODULE_PARM_DESC(step, "\n amvdec_h265 step\n");
13225
13226	module_param(decode_pic_begin, uint, 0664);
13227	MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_h265 decode_pic_begin\n");
13228
13229	module_param(slice_parse_begin, uint, 0664);
13230	MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_h265 slice_parse_begin\n");
13231
13232	module_param(nal_skip_policy, uint, 0664);
13233	MODULE_PARM_DESC(nal_skip_policy, "\n amvdec_h265 nal_skip_policy\n");
13234
13235	module_param(i_only_flag, uint, 0664);
13236	MODULE_PARM_DESC(i_only_flag, "\n amvdec_h265 i_only_flag\n");
13237
13238	module_param(fast_output_enable, uint, 0664);
13239	MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h265 fast_output_enable\n");
13240
13241	module_param(error_handle_policy, uint, 0664);
13242	MODULE_PARM_DESC(error_handle_policy, "\n amvdec_h265 error_handle_policy\n");
13243
13244	module_param(error_handle_threshold, uint, 0664);
13245	MODULE_PARM_DESC(error_handle_threshold,
13246	"\n amvdec_h265 error_handle_threshold\n");
13247
13248	module_param(error_handle_nal_skip_threshold, uint, 0664);
13249	MODULE_PARM_DESC(error_handle_nal_skip_threshold,
13250	"\n amvdec_h265 error_handle_nal_skip_threshold\n");
13251
13252	module_param(error_handle_system_threshold, uint, 0664);
13253	MODULE_PARM_DESC(error_handle_system_threshold,
13254	"\n amvdec_h265 error_handle_system_threshold\n");
13255
13256	module_param(error_skip_nal_count, uint, 0664);
13257	MODULE_PARM_DESC(error_skip_nal_count,
13258	"\n amvdec_h265 error_skip_nal_count\n");
13259
13260	module_param(debug, uint, 0664);
13261	MODULE_PARM_DESC(debug, "\n amvdec_h265 debug\n");
13262
13263	module_param(debug_mask, uint, 0664);
13264	MODULE_PARM_DESC(debug_mask, "\n amvdec_h265 debug mask\n");
13265
13266	module_param(log_mask, uint, 0664);
13267	MODULE_PARM_DESC(log_mask, "\n amvdec_h265 log_mask\n");
13268
13269	module_param(buffer_mode, uint, 0664);
13270	MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
13271
13272	module_param(double_write_mode, uint, 0664);
13273	MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
13274
13275	module_param(buf_alloc_width, uint, 0664);
13276	MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
13277
13278	module_param(buf_alloc_height, uint, 0664);
13279	MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
13280
13281	module_param(dynamic_buf_num_margin, uint, 0664);
13282	MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
13283
13284	module_param(max_buf_num, uint, 0664);
13285	MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
13286
13287	module_param(buf_alloc_size, uint, 0664);
13288	MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
13289
13290	#ifdef CONSTRAIN_MAX_BUF_NUM
13291	module_param(run_ready_max_vf_only_num, uint, 0664);
13292	MODULE_PARM_DESC(run_ready_max_vf_only_num, "\n run_ready_max_vf_only_num\n");
13293
13294	module_param(run_ready_display_q_num, uint, 0664);
13295	MODULE_PARM_DESC(run_ready_display_q_num, "\n run_ready_display_q_num\n");
13296
13297	module_param(run_ready_max_buf_num, uint, 0664);
13298	MODULE_PARM_DESC(run_ready_max_buf_num, "\n run_ready_max_buf_num\n");
13299	#endif
13300
13301	#if 0
13302	module_param(re_config_pic_flag, uint, 0664);
13303	MODULE_PARM_DESC(re_config_pic_flag, "\n re_config_pic_flag\n");
13304	#endif
13305
13306	module_param(buffer_mode_dbg, uint, 0664);
13307	MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
13308
13309	module_param(mem_map_mode, uint, 0664);
13310	MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
13311
13312	module_param(enable_mem_saving, uint, 0664);
13313	MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
13314
13315	module_param(force_w_h, uint, 0664);
13316	MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
13317
13318	module_param(force_fps, uint, 0664);
13319	MODULE_PARM_DESC(force_fps, "\n force_fps\n");
13320
13321	module_param(max_decoding_time, uint, 0664);
13322	MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
13323
13324	module_param(prefix_aux_buf_size, uint, 0664);
13325	MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n");
13326
13327	module_param(suffix_aux_buf_size, uint, 0664);
13328	MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n");
13329
13330	module_param(interlace_enable, uint, 0664);
13331	MODULE_PARM_DESC(interlace_enable, "\n interlace_enable\n");
13332	module_param(pts_unstable, uint, 0664);
13333	MODULE_PARM_DESC(pts_unstable, "\n amvdec_h265 pts_unstable\n");
13334	module_param(parser_sei_enable, uint, 0664);
13335	MODULE_PARM_DESC(parser_sei_enable, "\n parser_sei_enable\n");
13336
13337	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
13338	module_param(parser_dolby_vision_enable, uint, 0664);
13339	MODULE_PARM_DESC(parser_dolby_vision_enable,
13340	"\n parser_dolby_vision_enable\n");
13341
13342	module_param(dolby_meta_with_el, uint, 0664);
13343	MODULE_PARM_DESC(dolby_meta_with_el,
13344	"\n dolby_meta_with_el\n");
13345
13346	module_param(dolby_el_flush_th, uint, 0664);
13347	MODULE_PARM_DESC(dolby_el_flush_th,
13348	"\n dolby_el_flush_th\n");
13349	#endif
13350	module_param(mmu_enable, uint, 0664);
13351	MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n");
13352
13353	module_param(mmu_enable_force, uint, 0664);
13354	MODULE_PARM_DESC(mmu_enable_force, "\n mmu_enable_force\n");
13355
13356	#ifdef MULTI_INSTANCE_SUPPORT
13357	module_param(start_decode_buf_level, int, 0664);
13358	MODULE_PARM_DESC(start_decode_buf_level,
13359	"\n h265 start_decode_buf_level\n");
13360
13361	module_param(decode_timeout_val, uint, 0664);
13362	MODULE_PARM_DESC(decode_timeout_val,
13363	"\n h265 decode_timeout_val\n");
13364
13365	module_param(data_resend_policy, uint, 0664);
13366	MODULE_PARM_DESC(data_resend_policy,
13367	"\n h265 data_resend_policy\n");
13368
13369	module_param_array(decode_frame_count, uint,
13370	&max_decode_instance_num, 0664);
13371
13372	module_param_array(display_frame_count, uint,
13373	&max_decode_instance_num, 0664);
13374
13375	module_param_array(max_process_time, uint,
13376	&max_decode_instance_num, 0664);
13377
13378	module_param_array(max_get_frame_interval,
13379	uint, &max_decode_instance_num, 0664);
13380
13381	module_param_array(run_count, uint,
13382	&max_decode_instance_num, 0664);
13383
13384	module_param_array(input_empty, uint,
13385	&max_decode_instance_num, 0664);
13386
13387	module_param_array(not_run_ready, uint,
13388	&max_decode_instance_num, 0664);
13389
13390	module_param_array(ref_frame_mark_flag, uint,
13391	&max_decode_instance_num, 0664);
13392
13393	#endif
13394	#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
13395	module_param(dv_toggle_prov_name, uint, 0664);
13396	MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n");
13397
13398	module_param(dv_debug, uint, 0664);
13399	MODULE_PARM_DESC(dv_debug, "\n dv_debug\n");
13400
13401	module_param(force_bypass_dvenl, uint, 0664);
13402	MODULE_PARM_DESC(force_bypass_dvenl, "\n force_bypass_dvenl\n");
13403	#endif
13404
13405	#ifdef AGAIN_HAS_THRESHOLD
13406	module_param(again_threshold, uint, 0664);
13407	MODULE_PARM_DESC(again_threshold, "\n again_threshold\n");
13408	#endif
13409
13410	module_param(force_disp_pic_index, int, 0664);
13411	MODULE_PARM_DESC(force_disp_pic_index,
13412	"\n amvdec_h265 force_disp_pic_index\n");
13413
13414	module_param(frmbase_cont_bitlevel, uint, 0664);
13415	MODULE_PARM_DESC(frmbase_cont_bitlevel, "\n frmbase_cont_bitlevel\n");
13416
13417	module_param(udebug_flag, uint, 0664);
13418	MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
13419
13420	module_param(udebug_pause_pos, uint, 0664);
13421	MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
13422
13423	module_param(udebug_pause_val, uint, 0664);
13424	MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
13425
13426	module_param(pre_decode_buf_level, int, 0664);
13427	MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n");
13428
13429	module_param(udebug_pause_decode_idx, uint, 0664);
13430	MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
13431
13432	module_param(disp_vframe_valve_level, uint, 0664);
13433	MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n");
13434
13435	module_param(pic_list_debug, uint, 0664);
13436	MODULE_PARM_DESC(pic_list_debug, "\n pic_list_debug\n");
13437
13438	module_param(without_display_mode, uint, 0664);
13439	MODULE_PARM_DESC(without_display_mode, "\n amvdec_h265 without_display_mode\n");
13440
13441	module_init(amvdec_h265_driver_init_module);
13442	module_exit(amvdec_h265_driver_remove_module);
13443
13444	MODULE_DESCRIPTION("AMLOGIC h265 Video Decoder Driver");
13445	MODULE_LICENSE("GPL");
13446	MODULE_AUTHOR("Tim Yao <tim.yao@amlogic.com>");
13447