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path: root/drivers/frame_provider/decoder/mjpeg/vmjpeg_multi.c (plain)
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1/*
2 * drivers/amlogic/amports/vmjpeg.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/amlogic/media/frame_sync/ptsserv.h>
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/tee.h>
33
34#include <linux/amlogic/media/utils/vdec_reg.h>
35#include <linux/amlogic/media/registers/register.h>
36#include "../../../stream_input/amports/amports_priv.h"
37
38#include "../utils/vdec_input.h"
39#include "../utils/vdec.h"
40#include "../utils/amvdec.h"
41#include "../utils/decoder_mmu_box.h"
42#include "../utils/decoder_bmmu_box.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44#include <linux/amlogic/media/codec_mm/configs.h>
45#include "../utils/firmware.h"
46#include "../utils/vdec_v4l2_buffer_ops.h"
47
48#define MEM_NAME "codec_mmjpeg"
49
50#define DRIVER_NAME "ammvdec_mjpeg"
51#define MODULE_NAME "ammvdec_mjpeg"
52#define CHECK_INTERVAL (HZ/100)
53
54/* protocol register usage
55 * AV_SCRATCH_4 : decode buffer spec
56 * AV_SCRATCH_5 : decode buffer index
57 */
58
59#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */
60/* bit 15-4: reference height */
61#define MREG_TO_AMRISC AV_SCRATCH_8
62#define MREG_FROM_AMRISC AV_SCRATCH_9
63#define MREG_FRAME_OFFSET AV_SCRATCH_A
64#define DEC_STATUS_REG AV_SCRATCH_F
65#define MREG_PIC_WIDTH AV_SCRATCH_B
66#define MREG_PIC_HEIGHT AV_SCRATCH_C
67#define DECODE_STOP_POS AV_SCRATCH_K
68
69#define PICINFO_BUF_IDX_MASK 0x0007
70#define PICINFO_AVI1 0x0080
71#define PICINFO_INTERLACE 0x0020
72#define PICINFO_INTERLACE_AVI1_BOT 0x0010
73#define PICINFO_INTERLACE_FIRST 0x0010
74
75#define VF_POOL_SIZE 16
76#define DECODE_BUFFER_NUM_MAX 4
77#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX
78
79#define DEFAULT_MEM_SIZE (32*SZ_1M)
80static int debug_enable;
81static u32 udebug_flag;
82#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
83
84static unsigned int radr;
85static unsigned int rval;
86#define VMJPEG_DEV_NUM 9
87static unsigned int max_decode_instance_num = VMJPEG_DEV_NUM;
88static unsigned int max_process_time[VMJPEG_DEV_NUM];
89static unsigned int decode_timeout_val = 200;
90static struct vframe_s *vmjpeg_vf_peek(void *);
91static struct vframe_s *vmjpeg_vf_get(void *);
92static void vmjpeg_vf_put(struct vframe_s *, void *);
93static int vmjpeg_vf_states(struct vframe_states *states, void *);
94static int vmjpeg_event_cb(int type, void *data, void *private_data);
95static void vmjpeg_work(struct work_struct *work);
96static int pre_decode_buf_level = 0x800;
97static u32 without_display_mode;
98#undef pr_info
99#define pr_info printk
100unsigned int mmjpeg_debug_mask = 0xff;
101#define PRINT_FLAG_ERROR 0x0
102#define PRINT_FLAG_RUN_FLOW 0X0001
103#define PRINT_FLAG_TIMEINFO 0x0002
104#define PRINT_FLAG_UCODE_DETAIL 0x0004
105#define PRINT_FLAG_VLD_DETAIL 0x0008
106#define PRINT_FLAG_DEC_DETAIL 0x0010
107#define PRINT_FLAG_BUFFER_DETAIL 0x0020
108#define PRINT_FLAG_RESTORE 0x0040
109#define PRINT_FRAME_NUM 0x0080
110#define PRINT_FLAG_FORCE_DONE 0x0100
111#define PRINT_FRAMEBASE_DATA 0x0400
112#define PRINT_FLAG_TIMEOUT_STATUS 0x1000
113#define PRINT_FLAG_V4L_DETAIL 0x8000
114
115int mmjpeg_debug_print(int index, int debug_flag, const char *fmt, ...)
116{
117 if (((debug_enable & debug_flag) &&
118 ((1 << index) & mmjpeg_debug_mask))
119 || (debug_flag == PRINT_FLAG_ERROR)) {
120 unsigned char buf[512];
121 int len = 0;
122 va_list args;
123 va_start(args, fmt);
124 len = sprintf(buf, "%d: ", index);
125 vsnprintf(buf + len, 512-len, fmt, args);
126 pr_info("%s", buf);
127 va_end(args);
128 }
129 return 0;
130}
131
132static const char vmjpeg_dec_id[] = "vmmjpeg-dev";
133
134#define PROVIDER_NAME "vdec.mjpeg"
135static const struct vframe_operations_s vf_provider_ops = {
136 .peek = vmjpeg_vf_peek,
137 .get = vmjpeg_vf_get,
138 .put = vmjpeg_vf_put,
139 .event_cb = vmjpeg_event_cb,
140 .vf_states = vmjpeg_vf_states,
141};
142
143#define DEC_RESULT_NONE 0
144#define DEC_RESULT_DONE 1
145#define DEC_RESULT_AGAIN 2
146#define DEC_RESULT_ERROR 3
147#define DEC_RESULT_FORCE_EXIT 4
148#define DEC_RESULT_EOS 5
149#define DEC_DECODE_TIMEOUT 0x21
150
151
152struct buffer_spec_s {
153 unsigned int y_addr;
154 unsigned int u_addr;
155 unsigned int v_addr;
156
157 int y_canvas_index;
158 int u_canvas_index;
159 int v_canvas_index;
160
161 struct canvas_config_s canvas_config[3];
162 unsigned long cma_alloc_addr;
163 int cma_alloc_count;
164 unsigned int buf_adr;
165 ulong v4l_ref_buf_addr;
166};
167
168#define spec2canvas(x) \
169 (((x)->v_canvas_index << 16) | \
170 ((x)->u_canvas_index << 8) | \
171 ((x)->y_canvas_index << 0))
172
173struct vdec_mjpeg_hw_s {
174 spinlock_t lock;
175 struct mutex vmjpeg_mutex;
176
177 struct platform_device *platform_dev;
178 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
179 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
180
181 struct vframe_s vfpool[VF_POOL_SIZE];
182 struct buffer_spec_s buffer_spec[DECODE_BUFFER_NUM_MAX];
183 s32 vfbuf_use[DECODE_BUFFER_NUM_MAX];
184
185 u32 frame_width;
186 u32 frame_height;
187 u32 frame_dur;
188 u32 saved_resolution;
189 u8 init_flag;
190 u32 stat;
191 u32 dec_result;
192 unsigned long buf_start;
193 u32 buf_size;
194 void *mm_blk_handle;
195 struct dec_sysinfo vmjpeg_amstream_dec_info;
196
197 struct vframe_chunk_s *chunk;
198 struct work_struct work;
199 void (*vdec_cb)(struct vdec_s *, void *);
200 void *vdec_cb_arg;
201 struct firmware_s *fw;
202 struct timer_list check_timer;
203 u32 decode_timeout_count;
204 unsigned long int start_process_time;
205 u32 last_vld_level;
206 u8 eos;
207 u32 frame_num;
208 u32 put_num;
209 u32 run_count;
210 u32 not_run_ready;
211 u32 buffer_not_ready;
212 u32 input_empty;
213 u32 peek_num;
214 u32 get_num;
215 bool is_used_v4l;
216 void *v4l2_ctx;
217 bool v4l_params_parsed;
218};
219
220static void reset_process_time(struct vdec_mjpeg_hw_s *hw);
221static void set_frame_info(struct vdec_mjpeg_hw_s *hw, struct vframe_s *vf)
222{
223 u32 temp;
224 temp = READ_VREG(MREG_PIC_WIDTH);
225 if (temp > 1920)
226 vf->width = hw->frame_width = 1920;
227 else if (temp > 0)
228 vf->width = hw->frame_width = temp;
229 temp = READ_VREG(MREG_PIC_HEIGHT);
230 if (temp > 1088)
231 vf->height = hw->frame_height = 1088;
232 else if (temp > 0)
233 vf->height = hw->frame_height = temp;
234 vf->duration = hw->frame_dur;
235 vf->ratio_control = 0;
236 vf->duration_pulldown = 0;
237 vf->flag = 0;
238
239 vf->canvas0Addr = vf->canvas1Addr = -1;
240 vf->plane_num = 3;
241
242 vf->canvas0_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
243 vf->canvas0_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
244 vf->canvas0_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
245
246 vf->canvas1_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
247 vf->canvas1_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
248 vf->canvas1_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
249}
250
251static irqreturn_t vmjpeg_isr(struct vdec_s *vdec, int irq)
252{
253 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)(vdec->private);
254 u32 reg;
255 struct vframe_s *vf = NULL;
256 u32 index, offset = 0, pts;
257 u64 pts_us64;
258 u32 frame_size;
259
260 if (!hw)
261 return IRQ_HANDLED;
262
263 if (hw->eos)
264 return IRQ_HANDLED;
265 reset_process_time(hw);
266 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
267 if (READ_VREG(AV_SCRATCH_D) != 0 &&
268 (debug_enable & PRINT_FLAG_UCODE_DETAIL)) {
269 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_D),
270 READ_VREG(AV_SCRATCH_E));
271 WRITE_VREG(AV_SCRATCH_D, 0);
272 return IRQ_HANDLED;
273 }
274
275 reg = READ_VREG(MREG_FROM_AMRISC);
276 index = READ_VREG(AV_SCRATCH_5);
277
278 if (index >= DECODE_BUFFER_NUM_MAX) {
279 pr_err("fatal error, invalid buffer index.");
280 return IRQ_HANDLED;
281 }
282
283 if (kfifo_get(&hw->newframe_q, &vf) == 0) {
284 pr_info(
285 "fatal error, no available buffer slot.");
286 return IRQ_HANDLED;
287 }
288
289 if (hw->is_used_v4l) {
290 struct aml_vcodec_ctx *ctx =
291 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
292
293 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
294 struct aml_vdec_pic_infos info;
295
296 info.visible_width = hw->frame_width;
297 info.visible_height = hw->frame_height;
298 info.coded_width = ALIGN(hw->frame_width, 64);
299 info.coded_height = ALIGN(hw->frame_height, 64);
300 info.dpb_size = MAX_BMMU_BUFFER_NUM - 1;
301 hw->v4l_params_parsed = true;
302 vdec_v4l_set_pic_infos(ctx, &info);
303 }
304
305 if (!ctx->v4l_codec_ready)
306 return IRQ_HANDLED;
307 }
308
309 if (hw->is_used_v4l) {
310 vf->v4l_mem_handle
311 = hw->buffer_spec[index].v4l_ref_buf_addr;
312 if (vdec_v4l_binding_fd_and_vf(vf->v4l_mem_handle, vf) < 0) {
313 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
314 "v4l: binding vf fail.\n");
315 return -1;
316 }
317 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
318 "[%d] %s(), v4l mem handle: 0x%lx\n",
319 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
320 __func__, vf->v4l_mem_handle);
321 }
322
323 vf->index = index;
324 set_frame_info(hw, vf);
325
326 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
327 /* vf->pts = (pts_valid) ? pts : 0; */
328 /* vf->pts_us64 = (pts_valid) ? pts_us64 : 0; */
329
330 if (hw->chunk) {
331 vf->pts = hw->chunk->pts;
332 vf->pts_us64 = hw->chunk->pts64;
333 } else {
334 offset = READ_VREG(MREG_FRAME_OFFSET);
335 if (pts_lookup_offset_us64
336 (PTS_TYPE_VIDEO, offset, &pts,
337 &frame_size, 3000,
338 &pts_us64) == 0) {
339 vf->pts = pts;
340 vf->pts_us64 = pts_us64;
341 } else {
342 vf->pts = 0;
343 vf->pts_us64 = 0;
344 }
345 }
346 vf->orientation = 0;
347 hw->vfbuf_use[index]++;
348
349 vf->mem_handle =
350 decoder_bmmu_box_get_mem_handle(
351 hw->mm_blk_handle, index);
352 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
353 ATRACE_COUNTER(MODULE_NAME, vf->pts);
354 hw->frame_num++;
355 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
356 "%s:frame num:%d,pts=%d,pts64=%lld. dur=%d\n",
357 __func__, hw->frame_num,
358 vf->pts, vf->pts_us64, vf->duration);
359 vdec->vdec_fps_detec(vdec->id);
360 if (without_display_mode == 0) {
361 vf_notify_receiver(vdec->vf_provider_name,
362 VFRAME_EVENT_PROVIDER_VFRAME_READY,
363 NULL);
364 } else
365 vmjpeg_vf_put(vmjpeg_vf_get(vdec), vdec);
366
367 hw->dec_result = DEC_RESULT_DONE;
368
369 vdec_schedule_work(&hw->work);
370
371 return IRQ_HANDLED;
372}
373
374static struct vframe_s *vmjpeg_vf_peek(void *op_arg)
375{
376 struct vframe_s *vf;
377 struct vdec_s *vdec = op_arg;
378 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
379
380 if (!hw)
381 return NULL;
382 hw->peek_num++;
383 if (kfifo_peek(&hw->display_q, &vf))
384 return vf;
385
386 return NULL;
387}
388
389static struct vframe_s *vmjpeg_vf_get(void *op_arg)
390{
391 struct vframe_s *vf;
392 struct vdec_s *vdec = op_arg;
393 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
394
395 if (!hw)
396 return NULL;
397 hw->get_num++;
398 if (kfifo_get(&hw->display_q, &vf))
399 return vf;
400
401 return NULL;
402}
403
404static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg)
405{
406 struct vdec_s *vdec = op_arg;
407 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
408 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
409 "%s:put_num:%d\n", __func__, hw->put_num);
410 hw->vfbuf_use[vf->index]--;
411 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
412 hw->put_num++;
413}
414
415static int vmjpeg_event_cb(int type, void *data, void *private_data)
416{
417 return 0;
418}
419
420static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg)
421{
422 unsigned long flags;
423 struct vdec_s *vdec = op_arg;
424 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
425
426 spin_lock_irqsave(&hw->lock, flags);
427
428 states->vf_pool_size = VF_POOL_SIZE;
429 states->buf_free_num = kfifo_len(&hw->newframe_q);
430 states->buf_avail_num = kfifo_len(&hw->display_q);
431 states->buf_recycle_num = 0;
432
433 spin_unlock_irqrestore(&hw->lock, flags);
434
435 return 0;
436}
437
438static int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
439{
440 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
441
442 if (!hw)
443 return -1;
444
445 vstatus->frame_width = hw->frame_width;
446 vstatus->frame_height = hw->frame_height;
447 if (0 != hw->frame_dur)
448 vstatus->frame_rate = 96000 / hw->frame_dur;
449 else
450 vstatus->frame_rate = 96000;
451 vstatus->error_count = 0;
452 vstatus->status = hw->stat;
453
454 return 0;
455}
456
457/****************************************/
458static void vmjpeg_canvas_init(struct vdec_mjpeg_hw_s *hw)
459{
460 int i, ret;
461 u32 canvas_width, canvas_height;
462 u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
463 unsigned long buf_start, addr;
464 struct vdec_s *vdec = hw_to_vdec(hw);
465
466 canvas_width = 1920;
467 canvas_height = 1088;
468 decbuf_y_size = 0x200000;
469 decbuf_uv_size = 0x80000;
470 decbuf_size = 0x300000;
471
472 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
473 int canvas;
474
475 if (hw->is_used_v4l) {
476 continue;
477 } else {
478 ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i,
479 decbuf_size, DRIVER_NAME, &buf_start);
480 if (ret < 0) {
481 pr_err("CMA alloc failed! size 0x%d idx %d\n",
482 decbuf_size, i);
483 return;
484 }
485 }
486
487 hw->buffer_spec[i].buf_adr = buf_start;
488 addr = hw->buffer_spec[i].buf_adr;
489
490 hw->buffer_spec[i].y_addr = addr;
491 addr += decbuf_y_size;
492 hw->buffer_spec[i].u_addr = addr;
493 addr += decbuf_uv_size;
494 hw->buffer_spec[i].v_addr = addr;
495
496 if (vdec->parallel_dec == 1) {
497 if (hw->buffer_spec[i].y_canvas_index == -1)
498 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
499 if (hw->buffer_spec[i].u_canvas_index == -1)
500 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
501 if (hw->buffer_spec[i].v_canvas_index == -1)
502 hw->buffer_spec[i].v_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
503 } else {
504 canvas = vdec->get_canvas(i, 3);
505 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
506 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
507 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
508 }
509
510 canvas_config(hw->buffer_spec[i].y_canvas_index,
511 hw->buffer_spec[i].y_addr,
512 canvas_width,
513 canvas_height,
514 CANVAS_ADDR_NOWRAP,
515 CANVAS_BLKMODE_LINEAR);
516 hw->buffer_spec[i].canvas_config[0].phy_addr =
517 hw->buffer_spec[i].y_addr;
518 hw->buffer_spec[i].canvas_config[0].width =
519 canvas_width;
520 hw->buffer_spec[i].canvas_config[0].height =
521 canvas_height;
522 hw->buffer_spec[i].canvas_config[0].block_mode =
523 CANVAS_BLKMODE_LINEAR;
524
525 canvas_config(hw->buffer_spec[i].u_canvas_index,
526 hw->buffer_spec[i].u_addr,
527 canvas_width / 2,
528 canvas_height / 2,
529 CANVAS_ADDR_NOWRAP,
530 CANVAS_BLKMODE_LINEAR);
531 hw->buffer_spec[i].canvas_config[1].phy_addr =
532 hw->buffer_spec[i].u_addr;
533 hw->buffer_spec[i].canvas_config[1].width =
534 canvas_width / 2;
535 hw->buffer_spec[i].canvas_config[1].height =
536 canvas_height / 2;
537 hw->buffer_spec[i].canvas_config[1].block_mode =
538 CANVAS_BLKMODE_LINEAR;
539
540 canvas_config(hw->buffer_spec[i].v_canvas_index,
541 hw->buffer_spec[i].v_addr,
542 canvas_width / 2,
543 canvas_height / 2,
544 CANVAS_ADDR_NOWRAP,
545 CANVAS_BLKMODE_LINEAR);
546 hw->buffer_spec[i].canvas_config[2].phy_addr =
547 hw->buffer_spec[i].v_addr;
548 hw->buffer_spec[i].canvas_config[2].width =
549 canvas_width / 2;
550 hw->buffer_spec[i].canvas_config[2].height =
551 canvas_height / 2;
552 hw->buffer_spec[i].canvas_config[2].block_mode =
553 CANVAS_BLKMODE_LINEAR;
554 }
555}
556
557static void init_scaler(void)
558{
559 /* 4 point triangle */
560 const unsigned int filt_coef[] = {
561 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
562 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
563 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
564 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
565 0x18382808, 0x18382808, 0x17372909, 0x17372909,
566 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
567 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
568 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
569 0x10303010
570 };
571 int i;
572
573 /* pscale enable, PSCALE cbus bmem enable */
574 WRITE_VREG(PSCALE_CTRL, 0xc000);
575
576 /* write filter coefs */
577 WRITE_VREG(PSCALE_BMEM_ADDR, 0);
578 for (i = 0; i < 33; i++) {
579 WRITE_VREG(PSCALE_BMEM_DAT, 0);
580 WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]);
581 }
582
583 /* Y horizontal initial info */
584 WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2);
585 /* [35]: buf repeat pix0,
586 * [34:29] => buf receive num,
587 * [28:16] => buf blk x,
588 * [15:0] => buf phase
589 */
590 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
591 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
592
593 /* C horizontal initial info */
594 WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2);
595 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
596 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
597
598 /* Y vertical initial info */
599 WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2);
600 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
601 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
602
603 /* C vertical initial info */
604 WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2);
605 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
606 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
607
608 /* Y horizontal phase step */
609 WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1);
610 /* [19:0] => Y horizontal phase step */
611 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
612 /* C horizontal phase step */
613 WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1);
614 /* [19:0] => C horizontal phase step */
615 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
616
617 /* Y vertical phase step */
618 WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1);
619 /* [19:0] => Y vertical phase step */
620 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
621 /* C vertical phase step */
622 WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1);
623 /* [19:0] => C horizontal phase step */
624 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
625
626 /* reset pscaler */
627#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
628 WRITE_VREG(DOS_SW_RESET0, (1 << 10));
629 WRITE_VREG(DOS_SW_RESET0, 0);
630#else
631 WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE);
632#endif
633 READ_RESET_REG(RESET2_REGISTER);
634 READ_RESET_REG(RESET2_REGISTER);
635 READ_RESET_REG(RESET2_REGISTER);
636
637 WRITE_VREG(PSCALE_RST, 0x7);
638 WRITE_VREG(PSCALE_RST, 0x0);
639}
640
641static void vmjpeg_dump_state(struct vdec_s *vdec)
642{
643 struct vdec_mjpeg_hw_s *hw =
644 (struct vdec_mjpeg_hw_s *)(vdec->private);
645 mmjpeg_debug_print(DECODE_ID(hw), 0,
646 "====== %s\n", __func__);
647 mmjpeg_debug_print(DECODE_ID(hw), 0,
648 "width/height (%d/%d)\n",
649 hw->frame_width,
650 hw->frame_height
651 );
652 mmjpeg_debug_print(DECODE_ID(hw), 0,
653 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d put_frm %d run %d not_run_ready %d input_empty %d\n",
654 input_frame_based(vdec),
655 hw->eos,
656 hw->stat,
657 hw->dec_result,
658 hw->frame_num,
659 hw->put_num,
660 hw->run_count,
661 hw->not_run_ready,
662 hw->input_empty
663 );
664 if (vf_get_receiver(vdec->vf_provider_name)) {
665 enum receviver_start_e state =
666 vf_notify_receiver(vdec->vf_provider_name,
667 VFRAME_EVENT_PROVIDER_QUREY_STATE,
668 NULL);
669 mmjpeg_debug_print(DECODE_ID(hw), 0,
670 "\nreceiver(%s) state %d\n",
671 vdec->vf_provider_name,
672 state);
673 }
674 mmjpeg_debug_print(DECODE_ID(hw), 0,
675 "%s, newq(%d/%d), dispq(%d/%d) vf peek/get/put (%d/%d/%d)\n",
676 __func__,
677 kfifo_len(&hw->newframe_q),
678 VF_POOL_SIZE,
679 kfifo_len(&hw->display_q),
680 VF_POOL_SIZE,
681 hw->peek_num,
682 hw->get_num,
683 hw->put_num
684 );
685 mmjpeg_debug_print(DECODE_ID(hw), 0,
686 "VIFF_BIT_CNT=0x%x\n",
687 READ_VREG(VIFF_BIT_CNT));
688 mmjpeg_debug_print(DECODE_ID(hw), 0,
689 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
690 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
691 mmjpeg_debug_print(DECODE_ID(hw), 0,
692 "VLD_MEM_VIFIFO_WP=0x%x\n",
693 READ_VREG(VLD_MEM_VIFIFO_WP));
694 mmjpeg_debug_print(DECODE_ID(hw), 0,
695 "VLD_MEM_VIFIFO_RP=0x%x\n",
696 READ_VREG(VLD_MEM_VIFIFO_RP));
697 mmjpeg_debug_print(DECODE_ID(hw), 0,
698 "PARSER_VIDEO_RP=0x%x\n",
699 READ_PARSER_REG(PARSER_VIDEO_RP));
700 mmjpeg_debug_print(DECODE_ID(hw), 0,
701 "PARSER_VIDEO_WP=0x%x\n",
702 READ_PARSER_REG(PARSER_VIDEO_WP));
703 if (input_frame_based(vdec) &&
704 debug_enable & PRINT_FRAMEBASE_DATA
705 ) {
706 int jj;
707 if (hw->chunk && hw->chunk->block &&
708 hw->chunk->size > 0) {
709 u8 *data = NULL;
710
711 if (!hw->chunk->block->is_mapped)
712 data = codec_mm_vmap(hw->chunk->block->start +
713 hw->chunk->offset, hw->chunk->size);
714 else
715 data = ((u8 *)hw->chunk->block->start_virt) +
716 hw->chunk->offset;
717
718 mmjpeg_debug_print(DECODE_ID(hw), 0,
719 "frame data size 0x%x\n",
720 hw->chunk->size);
721 for (jj = 0; jj < hw->chunk->size; jj++) {
722 if ((jj & 0xf) == 0)
723 mmjpeg_debug_print(DECODE_ID(hw),
724 PRINT_FRAMEBASE_DATA,
725 "%06x:", jj);
726 mmjpeg_debug_print(DECODE_ID(hw),
727 PRINT_FRAMEBASE_DATA,
728 "%02x ", data[jj]);
729 if (((jj + 1) & 0xf) == 0)
730 mmjpeg_debug_print(DECODE_ID(hw),
731 PRINT_FRAMEBASE_DATA,
732 "\n");
733 }
734
735 if (!hw->chunk->block->is_mapped)
736 codec_mm_unmap_phyaddr(data);
737 }
738 }
739}
740static void reset_process_time(struct vdec_mjpeg_hw_s *hw)
741{
742 if (hw->start_process_time) {
743 unsigned process_time =
744 1000 * (jiffies - hw->start_process_time) / HZ;
745 hw->start_process_time = 0;
746 if (process_time > max_process_time[DECODE_ID(hw)])
747 max_process_time[DECODE_ID(hw)] = process_time;
748 }
749}
750
751static void start_process_time(struct vdec_mjpeg_hw_s *hw)
752{
753 hw->decode_timeout_count = 2;
754 hw->start_process_time = jiffies;
755}
756
757static void timeout_process(struct vdec_mjpeg_hw_s *hw)
758{
759 amvdec_stop();
760 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
761 "%s decoder timeout\n", __func__);
762 hw->dec_result = DEC_RESULT_DONE;
763 reset_process_time(hw);
764 vdec_schedule_work(&hw->work);
765}
766
767static void check_timer_func(unsigned long arg)
768{
769 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)arg;
770 struct vdec_s *vdec = hw_to_vdec(hw);
771 int timeout_val = decode_timeout_val;
772
773 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
774 "%s: status:nstatus=%d:%d\n",
775 __func__, vdec->status, vdec->next_status);
776 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
777 "%s: %d,buftl=%x:%x:%x:%x\n",
778 __func__, __LINE__,
779 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
780 READ_PARSER_REG(PARSER_VIDEO_WP),
781 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
782 READ_VREG(VLD_MEM_VIFIFO_WP));
783
784 if (radr != 0) {
785 if (rval != 0) {
786 WRITE_VREG(radr, rval);
787 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
788 } else
789 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
790 rval = 0;
791 radr = 0;
792 }
793
794 if (((debug_enable & PRINT_FLAG_TIMEOUT_STATUS) == 0) &&
795 (input_frame_based(vdec) ||
796 ((u32)READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x100)) &&
797 (timeout_val > 0) &&
798 (hw->start_process_time > 0) &&
799 ((1000 * (jiffies - hw->start_process_time) / HZ)
800 > timeout_val)) {
801 if (hw->last_vld_level == READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
802 if (hw->decode_timeout_count > 0)
803 hw->decode_timeout_count--;
804 if (hw->decode_timeout_count == 0)
805 timeout_process(hw);
806 }
807 hw->last_vld_level = READ_VREG(VLD_MEM_VIFIFO_LEVEL);
808 }
809
810 if (READ_VREG(DEC_STATUS_REG) == DEC_DECODE_TIMEOUT) {
811 pr_info("ucode DEC_DECODE_TIMEOUT\n");
812 if (hw->decode_timeout_count > 0)
813 hw->decode_timeout_count--;
814 if (hw->decode_timeout_count == 0)
815 timeout_process(hw);
816 WRITE_VREG(DEC_STATUS_REG, 0);
817 }
818
819 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
820 hw->dec_result = DEC_RESULT_FORCE_EXIT;
821 vdec_schedule_work(&hw->work);
822 pr_info("vdec requested to be disconnected\n");
823 return;
824 }
825 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
826}
827
828static int vmjpeg_v4l_alloc_buff_config_canvas(struct vdec_mjpeg_hw_s *hw, int i)
829{
830 int ret;
831 u32 canvas;
832 ulong decbuf_start = 0, addr;
833 int decbuf_y_size = 0, decbuf_uv_size = 0;
834 u32 canvas_width = 0, canvas_height = 0;
835 struct vdec_s *vdec = hw_to_vdec(hw);
836 struct vdec_v4l2_buffer *fb = NULL;
837
838 if (hw->buffer_spec[i].v4l_ref_buf_addr)
839 return 0;
840
841 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
842 if (ret) {
843 mmjpeg_debug_print(DECODE_ID(hw), 0,
844 "[%d] get fb fail.\n",
845 ((struct aml_vcodec_ctx *)
846 (hw->v4l2_ctx))->id);
847 return ret;
848 }
849
850 hw->buffer_spec[i].v4l_ref_buf_addr = (ulong)fb;
851 if (fb->num_planes == 1) {
852 decbuf_start = fb->m.mem[0].addr;
853 decbuf_y_size = fb->m.mem[0].offset;
854 decbuf_uv_size = fb->m.mem[0].size - fb->m.mem[0].offset;
855 canvas_width = ALIGN(hw->frame_width, 16);
856 canvas_height = ALIGN(hw->frame_height, 16);
857 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
858 } else if (fb->num_planes == 2) {
859 decbuf_start = fb->m.mem[0].addr;
860 decbuf_y_size = fb->m.mem[0].size;
861 decbuf_uv_size = fb->m.mem[1].size << 1;
862 canvas_width = ALIGN(hw->frame_width, 16);
863 canvas_height = ALIGN(hw->frame_height, 16);
864 fb->m.mem[0].bytes_used = decbuf_y_size;
865 fb->m.mem[1].bytes_used = decbuf_uv_size >> 1;
866 }
867
868 hw->buffer_spec[i].buf_adr = decbuf_start;
869 addr = hw->buffer_spec[i].buf_adr;
870 hw->buffer_spec[i].y_addr = addr;
871 addr += decbuf_y_size;
872 hw->buffer_spec[i].u_addr = addr;
873 addr += decbuf_uv_size;
874 hw->buffer_spec[i].v_addr = addr;
875
876 mmjpeg_debug_print(DECODE_ID(hw), 0, "[%d] %s(), v4l ref buf addr: 0x%x\n",
877 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id, __func__, fb);
878
879 if (vdec->parallel_dec == 1) {
880 if (hw->buffer_spec[i].y_canvas_index == -1)
881 hw->buffer_spec[i].y_canvas_index =
882 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
883 if (hw->buffer_spec[i].u_canvas_index == -1)
884 hw->buffer_spec[i].u_canvas_index =
885 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
886 if (hw->buffer_spec[i].v_canvas_index == -1)
887 hw->buffer_spec[i].v_canvas_index =
888 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
889 } else {
890 canvas = vdec->get_canvas(i, 3);
891 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
892 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
893 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
894 }
895
896 canvas_config(hw->buffer_spec[i].y_canvas_index,
897 hw->buffer_spec[i].y_addr,
898 canvas_width,
899 canvas_height,
900 CANVAS_ADDR_NOWRAP,
901 CANVAS_BLKMODE_LINEAR);
902 hw->buffer_spec[i].canvas_config[0].phy_addr =
903 hw->buffer_spec[i].y_addr;
904 hw->buffer_spec[i].canvas_config[0].width =
905 canvas_width;
906 hw->buffer_spec[i].canvas_config[0].height =
907 canvas_height;
908 hw->buffer_spec[i].canvas_config[0].block_mode =
909 CANVAS_BLKMODE_LINEAR;
910
911 canvas_config(hw->buffer_spec[i].u_canvas_index,
912 hw->buffer_spec[i].u_addr,
913 canvas_width / 2,
914 canvas_height / 2,
915 CANVAS_ADDR_NOWRAP,
916 CANVAS_BLKMODE_LINEAR);
917 hw->buffer_spec[i].canvas_config[1].phy_addr =
918 hw->buffer_spec[i].u_addr;
919 hw->buffer_spec[i].canvas_config[1].width =
920 canvas_width / 2;
921 hw->buffer_spec[i].canvas_config[1].height =
922 canvas_height / 2;
923 hw->buffer_spec[i].canvas_config[1].block_mode =
924 CANVAS_BLKMODE_LINEAR;
925
926 canvas_config(hw->buffer_spec[i].v_canvas_index,
927 hw->buffer_spec[i].v_addr,
928 canvas_width / 2,
929 canvas_height / 2,
930 CANVAS_ADDR_NOWRAP,
931 CANVAS_BLKMODE_LINEAR);
932 hw->buffer_spec[i].canvas_config[2].phy_addr =
933 hw->buffer_spec[i].v_addr;
934 hw->buffer_spec[i].canvas_config[2].width =
935 canvas_width / 2;
936 hw->buffer_spec[i].canvas_config[2].height =
937 canvas_height / 2;
938 hw->buffer_spec[i].canvas_config[2].block_mode =
939 CANVAS_BLKMODE_LINEAR;
940
941 return 0;
942}
943
944static bool is_enough_free_buffer(struct vdec_mjpeg_hw_s *hw)
945{
946 int i;
947
948 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
949 if (hw->vfbuf_use[i] == 0)
950 break;
951 }
952
953 return i == DECODE_BUFFER_NUM_MAX ? false : true;
954}
955
956static int find_free_buffer(struct vdec_mjpeg_hw_s *hw)
957{
958 int i;
959
960 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
961 if (hw->vfbuf_use[i] == 0)
962 break;
963 }
964
965 if (i == DECODE_BUFFER_NUM_MAX)
966 return -1;
967
968 if (hw->is_used_v4l)
969 if (vmjpeg_v4l_alloc_buff_config_canvas(hw, i))
970 return -1;
971
972 return i;
973}
974
975static int vmjpeg_hw_ctx_restore(struct vdec_mjpeg_hw_s *hw)
976{
977 struct buffer_spec_s *buff_spec;
978 u32 index, i;
979
980 index = find_free_buffer(hw);
981 if (index < 0)
982 return -1;
983
984 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6));
985 WRITE_VREG(DOS_SW_RESET0, 0);
986
987 if (!hw->init_flag) {
988 vmjpeg_canvas_init(hw);
989 } else {
990 if (!hw->is_used_v4l) {
991 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
992 buff_spec = &hw->buffer_spec[i];
993 canvas_config_config(buff_spec->y_canvas_index,
994 &buff_spec->canvas_config[0]);
995 canvas_config_config(buff_spec->u_canvas_index,
996 &buff_spec->canvas_config[1]);
997 canvas_config_config(buff_spec->v_canvas_index,
998 &buff_spec->canvas_config[2]);
999 }
1000 }
1001 }
1002
1003 /* find next decode buffer index */
1004 WRITE_VREG(AV_SCRATCH_4, spec2canvas(&hw->buffer_spec[index]));
1005 WRITE_VREG(AV_SCRATCH_5, index);
1006
1007 init_scaler();
1008
1009 /* clear buffer IN/OUT registers */
1010 WRITE_VREG(MREG_TO_AMRISC, 0);
1011 WRITE_VREG(MREG_FROM_AMRISC, 0);
1012
1013 WRITE_VREG(MCPU_INTR_MSK, 0xffff);
1014 WRITE_VREG(MREG_DECODE_PARAM, (hw->frame_height << 4) | 0x8000);
1015
1016 /* clear mailbox interrupt */
1017 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1018 /* enable mailbox interrupt */
1019 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1020 /* set interrupt mapping for vld */
1021 WRITE_VREG(ASSIST_AMR1_INT8, 8);
1022#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
1023 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1024#endif
1025 return 0;
1026}
1027
1028static s32 vmjpeg_init(struct vdec_s *vdec)
1029{
1030 int i;
1031 int size = -1, fw_size = 0x1000 * 16;
1032 struct firmware_s *fw = NULL;
1033 struct vdec_mjpeg_hw_s *hw =
1034 (struct vdec_mjpeg_hw_s *)vdec->private;
1035
1036 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
1037 if (IS_ERR_OR_NULL(fw))
1038 return -ENOMEM;
1039
1040 size = get_firmware_data(VIDEO_DEC_MJPEG_MULTI, fw->data);
1041 if (size < 0) {
1042 pr_err("get firmware fail.");
1043 vfree(fw);
1044 return -1;
1045 }
1046
1047 fw->len = size;
1048 hw->fw = fw;
1049
1050 hw->frame_width = hw->vmjpeg_amstream_dec_info.width;
1051 hw->frame_height = hw->vmjpeg_amstream_dec_info.height;
1052 hw->frame_dur = ((hw->vmjpeg_amstream_dec_info.rate) ?
1053 hw->vmjpeg_amstream_dec_info.rate : 3840);
1054 hw->saved_resolution = 0;
1055 hw->eos = 0;
1056 hw->init_flag = 0;
1057 hw->frame_num = 0;
1058 hw->put_num = 0;
1059 hw->run_count = 0;
1060 hw->not_run_ready = 0;
1061 hw->input_empty = 0;
1062 hw->peek_num = 0;
1063 hw->get_num = 0;
1064 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++)
1065 hw->vfbuf_use[i] = 0;
1066
1067 INIT_KFIFO(hw->display_q);
1068 INIT_KFIFO(hw->newframe_q);
1069
1070 for (i = 0; i < VF_POOL_SIZE; i++) {
1071 const struct vframe_s *vf = &hw->vfpool[i];
1072
1073 hw->vfpool[i].index = -1;
1074 kfifo_put(&hw->newframe_q, vf);
1075 }
1076
1077 if (hw->mm_blk_handle) {
1078 decoder_bmmu_box_free(hw->mm_blk_handle);
1079 hw->mm_blk_handle = NULL;
1080 }
1081
1082 hw->mm_blk_handle = decoder_bmmu_box_alloc_box(
1083 DRIVER_NAME,
1084 0,
1085 MAX_BMMU_BUFFER_NUM,
1086 4 + PAGE_SHIFT,
1087 CODEC_MM_FLAGS_CMA_CLEAR |
1088 CODEC_MM_FLAGS_FOR_VDECODER);
1089
1090 init_timer(&hw->check_timer);
1091
1092 hw->check_timer.data = (unsigned long)hw;
1093 hw->check_timer.function = check_timer_func;
1094 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
1095 /*add_timer(&hw->check_timer);*/
1096 hw->stat |= STAT_TIMER_ARM;
1097 hw->stat |= STAT_ISR_REG;
1098
1099 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
1100 INIT_WORK(&hw->work, vmjpeg_work);
1101 pr_info("w:h=%d:%d\n", hw->frame_width, hw->frame_height);
1102 return 0;
1103}
1104
1105static unsigned long run_ready(struct vdec_s *vdec,
1106 unsigned long mask)
1107{
1108 struct vdec_mjpeg_hw_s *hw =
1109 (struct vdec_mjpeg_hw_s *)vdec->private;
1110 hw->not_run_ready++;
1111 if (hw->eos)
1112 return 0;
1113 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
1114 && pre_decode_buf_level != 0) {
1115 u32 rp, wp, level;
1116
1117 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
1118 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
1119 if (wp < rp)
1120 level = vdec->input.size + wp - rp;
1121 else
1122 level = wp - rp;
1123
1124 if (level < pre_decode_buf_level)
1125 return 0;
1126 }
1127
1128 if (!is_enough_free_buffer(hw)) {
1129 hw->buffer_not_ready++;
1130 return 0;
1131 }
1132
1133 hw->not_run_ready = 0;
1134 hw->buffer_not_ready = 0;
1135 if (vdec->parallel_dec == 1)
1136 return CORE_MASK_VDEC_1;
1137 else
1138 return CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
1139}
1140
1141static void run(struct vdec_s *vdec, unsigned long mask,
1142 void (*callback)(struct vdec_s *, void *), void *arg)
1143{
1144 struct vdec_mjpeg_hw_s *hw =
1145 (struct vdec_mjpeg_hw_s *)vdec->private;
1146 int i, ret;
1147
1148 hw->vdec_cb_arg = arg;
1149 hw->vdec_cb = callback;
1150
1151 hw->run_count++;
1152 vdec_reset_core(vdec);
1153 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1154 if (hw->vfbuf_use[i] == 0)
1155 break;
1156 }
1157
1158 if (i == DECODE_BUFFER_NUM_MAX) {
1159 hw->dec_result = DEC_RESULT_AGAIN;
1160 vdec_schedule_work(&hw->work);
1161 return;
1162 }
1163
1164 ret = vdec_prepare_input(vdec, &hw->chunk);
1165 if (ret <= 0) {
1166 hw->input_empty++;
1167 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1168 "%s: %d,r=%d,buftl=%x:%x:%x\n",
1169 __func__, __LINE__, ret,
1170 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1171 READ_PARSER_REG(PARSER_VIDEO_WP),
1172 READ_VREG(VLD_MEM_VIFIFO_WP));
1173
1174 hw->dec_result = DEC_RESULT_AGAIN;
1175 vdec_schedule_work(&hw->work);
1176 return;
1177 }
1178 hw->input_empty = 0;
1179 hw->dec_result = DEC_RESULT_NONE;
1180 if (vdec->mc_loaded) {
1181 /*firmware have load before,
1182 and not changes to another.
1183 ignore reload.
1184 */
1185 } else {
1186 ret = amvdec_vdec_loadmc_ex(VFORMAT_MJPEG, "mmjpeg", vdec, hw->fw->data);
1187 if (ret < 0) {
1188 pr_err("[%d] MMJPEG: the %s fw loading failed, err: %x\n",
1189 vdec->id, tee_enabled() ? "TEE" : "local", ret);
1190 hw->dec_result = DEC_RESULT_FORCE_EXIT;
1191 vdec_schedule_work(&hw->work);
1192 return;
1193 }
1194 vdec->mc_loaded = 1;
1195 vdec->mc_type = VFORMAT_MJPEG;
1196 }
1197/* if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) {
1198 pr_err("%s: Error amvdec_loadmc fail\n", __func__);
1199 return;
1200 }*/
1201
1202 if (vmjpeg_hw_ctx_restore(hw) < 0) {
1203 hw->dec_result = DEC_RESULT_ERROR;
1204 mmjpeg_debug_print(DECODE_ID(hw), 0,
1205 "amvdec_mmjpeg: error HW context restore\n");
1206 vdec_schedule_work(&hw->work);
1207 return;
1208 }
1209#if 0
1210 vdec_enable_input(vdec);
1211 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1212#endif
1213 hw->stat |= STAT_MC_LOAD;
1214 start_process_time(hw);
1215 hw->last_vld_level = 0;
1216 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1217 amvdec_start();
1218 vdec_enable_input(vdec);
1219 hw->stat |= STAT_VDEC_RUN;
1220 hw->init_flag = 1;
1221
1222 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1223 "%s (0x%x 0x%x 0x%x) vldcrl 0x%x bitcnt 0x%x powerctl 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1224 __func__,
1225 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
1226 READ_VREG(VLD_MEM_VIFIFO_WP),
1227 READ_VREG(VLD_MEM_VIFIFO_RP),
1228 READ_VREG(VLD_DECODE_CONTROL),
1229 READ_VREG(VIFF_BIT_CNT),
1230 READ_VREG(POWER_CTL_VLD),
1231 READ_VREG(VLD_MEM_VIFIFO_START_PTR),
1232 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR),
1233 READ_VREG(VLD_MEM_VIFIFO_CONTROL),
1234 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1235 READ_VREG(VLD_MEM_VIFIFO_END_PTR));
1236}
1237static void wait_vmjpeg_search_done(struct vdec_mjpeg_hw_s *hw)
1238{
1239 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1240 int count = 0;
1241
1242 do {
1243 usleep_range(100, 500);
1244 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
1245 break;
1246 if (count > 1000) {
1247 mmjpeg_debug_print(DECODE_ID(hw), 0,
1248 "%s, count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
1249 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
1250 break;
1251 } else
1252 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1253 count++;
1254 } while (1);
1255}
1256
1257static int notify_v4l_eos(struct vdec_s *vdec)
1258{
1259 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
1260 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1261 struct vframe_s *vf = NULL;
1262 struct vdec_v4l2_buffer *fb = NULL;
1263
1264 if (hw->is_used_v4l && hw->eos) {
1265 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
1266 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1267 "%s fatal error, no available buffer slot.\n",
1268 __func__);
1269 return -1;
1270 }
1271
1272 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
1273 pr_err("[%d] get fb fail.\n", ctx->id);
1274 return -1;
1275 }
1276
1277 vf->timestamp = ULONG_MAX;
1278 vf->v4l_mem_handle = (unsigned long)fb;
1279 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
1280
1281 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
1282 vf_notify_receiver(vdec->vf_provider_name,
1283 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
1284
1285 pr_info("[%d] mpeg12 EOS notify.\n", ctx->id);
1286 }
1287
1288 return 0;
1289}
1290
1291static void vmjpeg_work(struct work_struct *work)
1292{
1293 struct vdec_mjpeg_hw_s *hw = container_of(work,
1294 struct vdec_mjpeg_hw_s, work);
1295 struct vdec_s *vdec = hw_to_vdec(hw);
1296
1297 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_BUFFER_DETAIL,
1298 "%s: result=%d,len=%d:%d\n",
1299 __func__, hw->dec_result,
1300 kfifo_len(&hw->newframe_q),
1301 kfifo_len(&hw->display_q));
1302 if (hw->dec_result == DEC_RESULT_DONE) {
1303 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1304 hw->chunk = NULL;
1305 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
1306 /*
1307 stream base: stream buf empty or timeout
1308 frame base: vdec_prepare_input fail
1309 */
1310 if (!vdec_has_more_input(hw_to_vdec(hw))) {
1311 hw->dec_result = DEC_RESULT_EOS;
1312 vdec_schedule_work(&hw->work);
1313 /*pr_info("%s: return\n",
1314 __func__);*/
1315 return;
1316 }
1317 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
1318 pr_info("%s: force exit\n", __func__);
1319 if (hw->stat & STAT_ISR_REG) {
1320 amvdec_stop();
1321 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1322 hw->stat &= ~STAT_ISR_REG;
1323 }
1324 } else if (hw->dec_result == DEC_RESULT_EOS) {
1325 pr_info("%s: end of stream\n", __func__);
1326 if (hw->stat & STAT_VDEC_RUN) {
1327 amvdec_stop();
1328 hw->stat &= ~STAT_VDEC_RUN;
1329 }
1330 hw->eos = 1;
1331 if (hw->is_used_v4l)
1332 notify_v4l_eos(vdec);
1333
1334 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1335 hw->chunk = NULL;
1336 vdec_clean_input(hw_to_vdec(hw));
1337 }
1338 if (hw->stat & STAT_VDEC_RUN) {
1339 amvdec_stop();
1340 hw->stat &= ~STAT_VDEC_RUN;
1341 }
1342 /*disable mbox interrupt */
1343 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
1344 wait_vmjpeg_search_done(hw);
1345 /* mark itself has all HW resource released and input released */
1346 if (vdec->parallel_dec == 1)
1347 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1348 else {
1349 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
1350 | CORE_MASK_HEVC);
1351 }
1352 del_timer_sync(&hw->check_timer);
1353 hw->stat &= ~STAT_TIMER_ARM;
1354
1355 if (hw->vdec_cb)
1356 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
1357}
1358
1359static int vmjpeg_stop(struct vdec_mjpeg_hw_s *hw)
1360{
1361 pr_info("%s ...count = %d\n", __func__, hw->frame_num);
1362
1363 if (hw->stat & STAT_VDEC_RUN) {
1364 amvdec_stop();
1365 pr_info("%s amvdec_stop\n", __func__);
1366 hw->stat &= ~STAT_VDEC_RUN;
1367 }
1368
1369 if (hw->stat & STAT_ISR_REG) {
1370 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1371 hw->stat &= ~STAT_ISR_REG;
1372 }
1373
1374 if (hw->stat & STAT_TIMER_ARM) {
1375 del_timer_sync(&hw->check_timer);
1376 hw->stat &= ~STAT_TIMER_ARM;
1377 }
1378 cancel_work_sync(&hw->work);
1379 hw->init_flag = 0;
1380
1381 if (hw->mm_blk_handle) {
1382 decoder_bmmu_box_free(hw->mm_blk_handle);
1383 hw->mm_blk_handle = NULL;
1384 }
1385
1386 if (hw->fw) {
1387 vfree(hw->fw);
1388 hw->fw = NULL;
1389 }
1390
1391 return 0;
1392}
1393
1394static int ammvdec_mjpeg_probe(struct platform_device *pdev)
1395{
1396 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
1397 struct vdec_mjpeg_hw_s *hw = NULL;
1398
1399 if (pdata == NULL) {
1400 pr_info("ammvdec_mjpeg memory resource undefined.\n");
1401 return -EFAULT;
1402 }
1403
1404 hw = (struct vdec_mjpeg_hw_s *)devm_kzalloc(&pdev->dev,
1405 sizeof(struct vdec_mjpeg_hw_s), GFP_KERNEL);
1406 hw = vzalloc(sizeof(struct vdec_mjpeg_hw_s));
1407 if (hw == NULL) {
1408 pr_info("\nammvdec_mjpeg device data allocation failed\n");
1409 return -ENOMEM;
1410 }
1411
1412 /* the ctx from v4l2 driver. */
1413 hw->v4l2_ctx = pdata->private;
1414
1415 pdata->private = hw;
1416 pdata->dec_status = vmjpeg_dec_status;
1417
1418 pdata->run = run;
1419 pdata->run_ready = run_ready;
1420 pdata->irq_handler = vmjpeg_isr;
1421 pdata->dump_state = vmjpeg_dump_state;
1422
1423 if (pdata->parallel_dec == 1) {
1424 int i;
1425 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1426 hw->buffer_spec[i].y_canvas_index = -1;
1427 hw->buffer_spec[i].u_canvas_index = -1;
1428 hw->buffer_spec[i].v_canvas_index = -1;
1429 }
1430 }
1431
1432 if (pdata->use_vfm_path)
1433 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1434 VFM_DEC_PROVIDER_NAME);
1435 else
1436 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1437 PROVIDER_NAME ".%02x", pdev->id & 0xff);
1438
1439 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
1440 &vf_provider_ops, pdata);
1441
1442 platform_set_drvdata(pdev, pdata);
1443
1444 hw->platform_dev = pdev;
1445
1446 if (pdata->sys_info) {
1447 hw->vmjpeg_amstream_dec_info = *pdata->sys_info;
1448 hw->is_used_v4l = (((unsigned long)
1449 hw->vmjpeg_amstream_dec_info.param & 0x80) >> 7);
1450 }
1451
1452 vdec_source_changed(VFORMAT_MJPEG,
1453 1920, 1080, 60);
1454 if (vmjpeg_init(pdata) < 0) {
1455 pr_info("ammvdec_mjpeg init failed.\n");
1456 if (hw) {
1457 vfree(hw);
1458 hw = NULL;
1459 }
1460 pdata->dec_status = NULL;
1461 return -ENODEV;
1462 }
1463 if (pdata->parallel_dec == 1)
1464 vdec_core_request(pdata, CORE_MASK_VDEC_1);
1465 else {
1466 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
1467 | CORE_MASK_COMBINE);
1468 }
1469
1470 return 0;
1471}
1472
1473static int ammvdec_mjpeg_remove(struct platform_device *pdev)
1474{
1475 struct vdec_mjpeg_hw_s *hw =
1476 (struct vdec_mjpeg_hw_s *)
1477 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
1478 struct vdec_s *vdec = hw_to_vdec(hw);
1479 int i;
1480
1481 vmjpeg_stop(hw);
1482
1483 if (vdec->parallel_dec == 1)
1484 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1485 else
1486 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
1487 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
1488 if (vdec->parallel_dec == 1) {
1489 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1490 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
1491 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
1492 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
1493 }
1494 }
1495 if (hw) {
1496 vfree(hw);
1497 hw = NULL;
1498 }
1499 pr_info("%s\n", __func__);
1500 return 0;
1501}
1502
1503/****************************************/
1504#ifdef CONFIG_PM
1505static int mmjpeg_suspend(struct device *dev)
1506{
1507 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
1508 return 0;
1509}
1510
1511static int mmjpeg_resume(struct device *dev)
1512{
1513 amvdec_resume(to_platform_device(dev));
1514 return 0;
1515}
1516
1517static const struct dev_pm_ops mmjpeg_pm_ops = {
1518 SET_SYSTEM_SLEEP_PM_OPS(mmjpeg_suspend, mmjpeg_resume)
1519};
1520#endif
1521
1522static struct platform_driver ammvdec_mjpeg_driver = {
1523 .probe = ammvdec_mjpeg_probe,
1524 .remove = ammvdec_mjpeg_remove,
1525 .driver = {
1526 .name = DRIVER_NAME,
1527#ifdef CONFIG_PM
1528 .pm = &mmjpeg_pm_ops,
1529#endif
1530 }
1531};
1532
1533static struct codec_profile_t ammvdec_mjpeg_profile = {
1534 .name = "mmjpeg",
1535 .profile = ""
1536};
1537
1538static int __init ammvdec_mjpeg_driver_init_module(void)
1539{
1540 if (platform_driver_register(&ammvdec_mjpeg_driver)) {
1541 pr_err("failed to register ammvdec_mjpeg driver\n");
1542 return -ENODEV;
1543 }
1544 vcodec_profile_register(&ammvdec_mjpeg_profile);
1545 return 0;
1546}
1547
1548static void __exit ammvdec_mjpeg_driver_remove_module(void)
1549{
1550 platform_driver_unregister(&ammvdec_mjpeg_driver);
1551}
1552
1553/****************************************/
1554module_param(debug_enable, uint, 0664);
1555MODULE_PARM_DESC(debug_enable, "\n debug enable\n");
1556module_param(pre_decode_buf_level, int, 0664);
1557MODULE_PARM_DESC(pre_decode_buf_level,
1558 "\n ammvdec_h264 pre_decode_buf_level\n");
1559module_param(udebug_flag, uint, 0664);
1560MODULE_PARM_DESC(udebug_flag, "\n amvdec_mmpeg12 udebug_flag\n");
1561
1562
1563module_param(decode_timeout_val, uint, 0664);
1564MODULE_PARM_DESC(decode_timeout_val, "\n ammvdec_mjpeg decode_timeout_val\n");
1565
1566module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
1567
1568module_param(radr, uint, 0664);
1569MODULE_PARM_DESC(radr, "\nradr\n");
1570
1571module_param(rval, uint, 0664);
1572MODULE_PARM_DESC(rval, "\nrval\n");
1573
1574module_param(without_display_mode, uint, 0664);
1575MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
1576
1577module_init(ammvdec_mjpeg_driver_init_module);
1578module_exit(ammvdec_mjpeg_driver_remove_module);
1579
1580MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver");
1581MODULE_LICENSE("GPL");
1582MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
1583
generated by cgit at 2024-05-17 10:21:21 (GMT)