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path: root/drivers/frame_provider/decoder/mjpeg/vmjpeg_multi.c (plain)
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1/*
2 * drivers/amlogic/amports/vmjpeg.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/amlogic/media/frame_sync/ptsserv.h>
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/tee.h>
33
34#include <linux/amlogic/media/utils/vdec_reg.h>
35#include <linux/amlogic/media/registers/register.h>
36#include "../../../stream_input/amports/amports_priv.h"
37
38#include "../utils/vdec_input.h"
39#include "../utils/vdec.h"
40#include "../utils/amvdec.h"
41#include "../utils/decoder_mmu_box.h"
42#include "../utils/decoder_bmmu_box.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44#include <linux/amlogic/media/codec_mm/configs.h>
45#include "../utils/firmware.h"
46
47
48
49#define MEM_NAME "codec_mmjpeg"
50
51#define DRIVER_NAME "ammvdec_mjpeg"
52#define MODULE_NAME "ammvdec_mjpeg"
53#define CHECK_INTERVAL (HZ/100)
54
55/* protocol register usage
56 * AV_SCRATCH_4 : decode buffer spec
57 * AV_SCRATCH_5 : decode buffer index
58 */
59
60#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */
61/* bit 15-4: reference height */
62#define MREG_TO_AMRISC AV_SCRATCH_8
63#define MREG_FROM_AMRISC AV_SCRATCH_9
64#define MREG_FRAME_OFFSET AV_SCRATCH_A
65#define DEC_STATUS_REG AV_SCRATCH_F
66#define MREG_PIC_WIDTH AV_SCRATCH_B
67#define MREG_PIC_HEIGHT AV_SCRATCH_C
68#define DECODE_STOP_POS AV_SCRATCH_K
69
70#define PICINFO_BUF_IDX_MASK 0x0007
71#define PICINFO_AVI1 0x0080
72#define PICINFO_INTERLACE 0x0020
73#define PICINFO_INTERLACE_AVI1_BOT 0x0010
74#define PICINFO_INTERLACE_FIRST 0x0010
75
76#define VF_POOL_SIZE 16
77#define DECODE_BUFFER_NUM_MAX 4
78#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX
79
80#define DEFAULT_MEM_SIZE (32*SZ_1M)
81static int debug_enable;
82static u32 udebug_flag;
83#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
84
85static unsigned int radr;
86static unsigned int rval;
87#define VMJPEG_DEV_NUM 9
88static unsigned int max_decode_instance_num = VMJPEG_DEV_NUM;
89static unsigned int max_process_time[VMJPEG_DEV_NUM];
90static unsigned int decode_timeout_val = 200;
91static struct vframe_s *vmjpeg_vf_peek(void *);
92static struct vframe_s *vmjpeg_vf_get(void *);
93static void vmjpeg_vf_put(struct vframe_s *, void *);
94static int vmjpeg_vf_states(struct vframe_states *states, void *);
95static int vmjpeg_event_cb(int type, void *data, void *private_data);
96static void vmjpeg_work(struct work_struct *work);
97static int pre_decode_buf_level = 0x800;
98static u32 without_display_mode;
99#undef pr_info
100#define pr_info printk
101unsigned int mmjpeg_debug_mask = 0xff;
102#define PRINT_FLAG_ERROR 0x0
103#define PRINT_FLAG_RUN_FLOW 0X0001
104#define PRINT_FLAG_TIMEINFO 0x0002
105#define PRINT_FLAG_UCODE_DETAIL 0x0004
106#define PRINT_FLAG_VLD_DETAIL 0x0008
107#define PRINT_FLAG_DEC_DETAIL 0x0010
108#define PRINT_FLAG_BUFFER_DETAIL 0x0020
109#define PRINT_FLAG_RESTORE 0x0040
110#define PRINT_FRAME_NUM 0x0080
111#define PRINT_FLAG_FORCE_DONE 0x0100
112#define PRINT_FRAMEBASE_DATA 0x0400
113#define PRINT_FLAG_TIMEOUT_STATUS 0x1000
114
115int mmjpeg_debug_print(int index, int debug_flag, const char *fmt, ...)
116{
117 if (((debug_enable & debug_flag) &&
118 ((1 << index) & mmjpeg_debug_mask))
119 || (debug_flag == PRINT_FLAG_ERROR)) {
120 unsigned char buf[512];
121 int len = 0;
122 va_list args;
123 va_start(args, fmt);
124 len = sprintf(buf, "%d: ", index);
125 vsnprintf(buf + len, 512-len, fmt, args);
126 pr_info("%s", buf);
127 va_end(args);
128 }
129 return 0;
130}
131
132static const char vmjpeg_dec_id[] = "vmmjpeg-dev";
133
134#define PROVIDER_NAME "vdec.mjpeg"
135static const struct vframe_operations_s vf_provider_ops = {
136 .peek = vmjpeg_vf_peek,
137 .get = vmjpeg_vf_get,
138 .put = vmjpeg_vf_put,
139 .event_cb = vmjpeg_event_cb,
140 .vf_states = vmjpeg_vf_states,
141};
142
143#define DEC_RESULT_NONE 0
144#define DEC_RESULT_DONE 1
145#define DEC_RESULT_AGAIN 2
146#define DEC_RESULT_FORCE_EXIT 3
147#define DEC_RESULT_EOS 4
148#define DEC_DECODE_TIMEOUT 0x21
149
150
151struct buffer_spec_s {
152 unsigned int y_addr;
153 unsigned int u_addr;
154 unsigned int v_addr;
155
156 int y_canvas_index;
157 int u_canvas_index;
158 int v_canvas_index;
159
160 struct canvas_config_s canvas_config[3];
161 unsigned long cma_alloc_addr;
162 int cma_alloc_count;
163 unsigned int buf_adr;
164};
165
166#define spec2canvas(x) \
167 (((x)->v_canvas_index << 16) | \
168 ((x)->u_canvas_index << 8) | \
169 ((x)->y_canvas_index << 0))
170
171struct vdec_mjpeg_hw_s {
172 spinlock_t lock;
173 struct mutex vmjpeg_mutex;
174
175 struct platform_device *platform_dev;
176 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
177 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
178
179 struct vframe_s vfpool[VF_POOL_SIZE];
180 struct buffer_spec_s buffer_spec[DECODE_BUFFER_NUM_MAX];
181 s32 vfbuf_use[DECODE_BUFFER_NUM_MAX];
182
183 u32 frame_width;
184 u32 frame_height;
185 u32 frame_dur;
186 u32 saved_resolution;
187 u8 init_flag;
188 u32 stat;
189 u32 dec_result;
190 unsigned long buf_start;
191 u32 buf_size;
192 void *mm_blk_handle;
193 struct dec_sysinfo vmjpeg_amstream_dec_info;
194
195 struct vframe_chunk_s *chunk;
196 struct work_struct work;
197 void (*vdec_cb)(struct vdec_s *, void *);
198 void *vdec_cb_arg;
199 struct firmware_s *fw;
200 struct timer_list check_timer;
201 u32 decode_timeout_count;
202 unsigned long int start_process_time;
203 u32 last_vld_level;
204 u8 eos;
205 u32 frame_num;
206 u32 put_num;
207 u32 run_count;
208 u32 not_run_ready;
209 u32 input_empty;
210 u32 peek_num;
211 u32 get_num;
212};
213
214static void reset_process_time(struct vdec_mjpeg_hw_s *hw);
215static void set_frame_info(struct vdec_mjpeg_hw_s *hw, struct vframe_s *vf)
216{
217 u32 temp;
218 temp = READ_VREG(MREG_PIC_WIDTH);
219 if (temp > 1920)
220 vf->width = hw->frame_width = 1920;
221 else if (temp > 0)
222 vf->width = hw->frame_width = temp;
223 temp = READ_VREG(MREG_PIC_HEIGHT);
224 if (temp > 1088)
225 vf->height = hw->frame_height = 1088;
226 else if (temp > 0)
227 vf->height = hw->frame_height = temp;
228 vf->duration = hw->frame_dur;
229 vf->ratio_control = 0;
230 vf->duration_pulldown = 0;
231 vf->flag = 0;
232
233 vf->canvas0Addr = vf->canvas1Addr = -1;
234 vf->plane_num = 3;
235
236 vf->canvas0_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
237 vf->canvas0_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
238 vf->canvas0_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
239
240 vf->canvas1_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
241 vf->canvas1_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
242 vf->canvas1_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
243}
244
245static irqreturn_t vmjpeg_isr(struct vdec_s *vdec, int irq)
246{
247 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)(vdec->private);
248 u32 reg;
249 struct vframe_s *vf = NULL;
250 u32 index, offset = 0, pts;
251 u64 pts_us64;
252 u32 frame_size;
253
254 if (!hw)
255 return IRQ_HANDLED;
256
257 if (hw->eos)
258 return IRQ_HANDLED;
259 reset_process_time(hw);
260 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
261 if (READ_VREG(AV_SCRATCH_D) != 0 &&
262 (debug_enable & PRINT_FLAG_UCODE_DETAIL)) {
263 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_D),
264 READ_VREG(AV_SCRATCH_E));
265 WRITE_VREG(AV_SCRATCH_D, 0);
266 return IRQ_HANDLED;
267 }
268
269 reg = READ_VREG(MREG_FROM_AMRISC);
270 index = READ_VREG(AV_SCRATCH_5);
271
272 if (index >= DECODE_BUFFER_NUM_MAX) {
273 pr_err("fatal error, invalid buffer index.");
274 return IRQ_HANDLED;
275 }
276
277 if (kfifo_get(&hw->newframe_q, &vf) == 0) {
278 pr_info(
279 "fatal error, no available buffer slot.");
280 return IRQ_HANDLED;
281 }
282
283 vf->index = index;
284 set_frame_info(hw, vf);
285
286 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
287 /* vf->pts = (pts_valid) ? pts : 0; */
288 /* vf->pts_us64 = (pts_valid) ? pts_us64 : 0; */
289
290 if (hw->chunk) {
291 vf->pts = hw->chunk->pts;
292 vf->pts_us64 = hw->chunk->pts64;
293 } else {
294 offset = READ_VREG(MREG_FRAME_OFFSET);
295 if (pts_lookup_offset_us64
296 (PTS_TYPE_VIDEO, offset, &pts,
297 &frame_size, 3000,
298 &pts_us64) == 0) {
299 vf->pts = pts;
300 vf->pts_us64 = pts_us64;
301 } else {
302 vf->pts = 0;
303 vf->pts_us64 = 0;
304 }
305 }
306 vf->orientation = 0;
307 hw->vfbuf_use[index]++;
308
309 vf->mem_handle =
310 decoder_bmmu_box_get_mem_handle(
311 hw->mm_blk_handle, index);
312 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
313 ATRACE_COUNTER(MODULE_NAME, vf->pts);
314 hw->frame_num++;
315 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
316 "%s:frame num:%d,pts=%d,pts64=%lld. dur=%d\n",
317 __func__, hw->frame_num,
318 vf->pts, vf->pts_us64, vf->duration);
319 vdec->vdec_fps_detec(vdec->id);
320 if (without_display_mode == 0) {
321 vf_notify_receiver(vdec->vf_provider_name,
322 VFRAME_EVENT_PROVIDER_VFRAME_READY,
323 NULL);
324 } else
325 vmjpeg_vf_put(vmjpeg_vf_get(vdec), vdec);
326
327 hw->dec_result = DEC_RESULT_DONE;
328
329 vdec_schedule_work(&hw->work);
330
331 return IRQ_HANDLED;
332}
333
334static struct vframe_s *vmjpeg_vf_peek(void *op_arg)
335{
336 struct vframe_s *vf;
337 struct vdec_s *vdec = op_arg;
338 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
339
340 if (!hw)
341 return NULL;
342 hw->peek_num++;
343 if (kfifo_peek(&hw->display_q, &vf))
344 return vf;
345
346 return NULL;
347}
348
349static struct vframe_s *vmjpeg_vf_get(void *op_arg)
350{
351 struct vframe_s *vf;
352 struct vdec_s *vdec = op_arg;
353 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
354
355 if (!hw)
356 return NULL;
357 hw->get_num++;
358 if (kfifo_get(&hw->display_q, &vf))
359 return vf;
360
361 return NULL;
362}
363
364static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg)
365{
366 struct vdec_s *vdec = op_arg;
367 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
368 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
369 "%s:put_num:%d\n", __func__, hw->put_num);
370 hw->vfbuf_use[vf->index]--;
371 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
372 hw->put_num++;
373}
374
375static int vmjpeg_event_cb(int type, void *data, void *private_data)
376{
377 return 0;
378}
379
380static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg)
381{
382 unsigned long flags;
383 struct vdec_s *vdec = op_arg;
384 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
385
386 spin_lock_irqsave(&hw->lock, flags);
387
388 states->vf_pool_size = VF_POOL_SIZE;
389 states->buf_free_num = kfifo_len(&hw->newframe_q);
390 states->buf_avail_num = kfifo_len(&hw->display_q);
391 states->buf_recycle_num = 0;
392
393 spin_unlock_irqrestore(&hw->lock, flags);
394
395 return 0;
396}
397
398static int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
399{
400 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
401
402 if (!hw)
403 return -1;
404
405 vstatus->frame_width = hw->frame_width;
406 vstatus->frame_height = hw->frame_height;
407 if (0 != hw->frame_dur)
408 vstatus->frame_rate = 96000 / hw->frame_dur;
409 else
410 vstatus->frame_rate = 96000;
411 vstatus->error_count = 0;
412 vstatus->status = hw->stat;
413
414 return 0;
415}
416
417/****************************************/
418static void vmjpeg_canvas_init(struct vdec_s *vdec)
419{
420 int i, ret;
421 u32 canvas_width, canvas_height;
422 u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
423 unsigned long buf_start, addr;
424 struct vdec_mjpeg_hw_s *hw =
425 (struct vdec_mjpeg_hw_s *)vdec->private;
426
427 canvas_width = 1920;
428 canvas_height = 1088;
429 decbuf_y_size = 0x200000;
430 decbuf_uv_size = 0x80000;
431 decbuf_size = 0x300000;
432
433 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
434 int canvas;
435
436 ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i,
437 decbuf_size, DRIVER_NAME, &buf_start);
438 if (ret < 0) {
439 pr_err("CMA alloc failed! size 0x%d idx %d\n",
440 decbuf_size, i);
441 return;
442 }
443
444 hw->buffer_spec[i].buf_adr = buf_start;
445 addr = hw->buffer_spec[i].buf_adr;
446
447 hw->buffer_spec[i].y_addr = addr;
448 addr += decbuf_y_size;
449 hw->buffer_spec[i].u_addr = addr;
450 addr += decbuf_uv_size;
451 hw->buffer_spec[i].v_addr = addr;
452
453 if (vdec->parallel_dec == 1) {
454 if (hw->buffer_spec[i].y_canvas_index == -1)
455 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
456 if (hw->buffer_spec[i].u_canvas_index == -1)
457 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
458 if (hw->buffer_spec[i].v_canvas_index == -1)
459 hw->buffer_spec[i].v_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
460 } else {
461 canvas = vdec->get_canvas(i, 3);
462 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
463 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
464 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
465 }
466
467 canvas_config(hw->buffer_spec[i].y_canvas_index,
468 hw->buffer_spec[i].y_addr,
469 canvas_width,
470 canvas_height,
471 CANVAS_ADDR_NOWRAP,
472 CANVAS_BLKMODE_LINEAR);
473 hw->buffer_spec[i].canvas_config[0].phy_addr =
474 hw->buffer_spec[i].y_addr;
475 hw->buffer_spec[i].canvas_config[0].width =
476 canvas_width;
477 hw->buffer_spec[i].canvas_config[0].height =
478 canvas_height;
479 hw->buffer_spec[i].canvas_config[0].block_mode =
480 CANVAS_BLKMODE_LINEAR;
481
482 canvas_config(hw->buffer_spec[i].u_canvas_index,
483 hw->buffer_spec[i].u_addr,
484 canvas_width / 2,
485 canvas_height / 2,
486 CANVAS_ADDR_NOWRAP,
487 CANVAS_BLKMODE_LINEAR);
488 hw->buffer_spec[i].canvas_config[1].phy_addr =
489 hw->buffer_spec[i].u_addr;
490 hw->buffer_spec[i].canvas_config[1].width =
491 canvas_width / 2;
492 hw->buffer_spec[i].canvas_config[1].height =
493 canvas_height / 2;
494 hw->buffer_spec[i].canvas_config[1].block_mode =
495 CANVAS_BLKMODE_LINEAR;
496
497 canvas_config(hw->buffer_spec[i].v_canvas_index,
498 hw->buffer_spec[i].v_addr,
499 canvas_width / 2,
500 canvas_height / 2,
501 CANVAS_ADDR_NOWRAP,
502 CANVAS_BLKMODE_LINEAR);
503 hw->buffer_spec[i].canvas_config[2].phy_addr =
504 hw->buffer_spec[i].v_addr;
505 hw->buffer_spec[i].canvas_config[2].width =
506 canvas_width / 2;
507 hw->buffer_spec[i].canvas_config[2].height =
508 canvas_height / 2;
509 hw->buffer_spec[i].canvas_config[2].block_mode =
510 CANVAS_BLKMODE_LINEAR;
511 }
512}
513
514static void init_scaler(void)
515{
516 /* 4 point triangle */
517 const unsigned int filt_coef[] = {
518 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
519 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
520 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
521 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
522 0x18382808, 0x18382808, 0x17372909, 0x17372909,
523 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
524 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
525 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
526 0x10303010
527 };
528 int i;
529
530 /* pscale enable, PSCALE cbus bmem enable */
531 WRITE_VREG(PSCALE_CTRL, 0xc000);
532
533 /* write filter coefs */
534 WRITE_VREG(PSCALE_BMEM_ADDR, 0);
535 for (i = 0; i < 33; i++) {
536 WRITE_VREG(PSCALE_BMEM_DAT, 0);
537 WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]);
538 }
539
540 /* Y horizontal initial info */
541 WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2);
542 /* [35]: buf repeat pix0,
543 * [34:29] => buf receive num,
544 * [28:16] => buf blk x,
545 * [15:0] => buf phase
546 */
547 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
548 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
549
550 /* C horizontal initial info */
551 WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2);
552 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
553 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
554
555 /* Y vertical initial info */
556 WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2);
557 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
558 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
559
560 /* C vertical initial info */
561 WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2);
562 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
563 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
564
565 /* Y horizontal phase step */
566 WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1);
567 /* [19:0] => Y horizontal phase step */
568 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
569 /* C horizontal phase step */
570 WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1);
571 /* [19:0] => C horizontal phase step */
572 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
573
574 /* Y vertical phase step */
575 WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1);
576 /* [19:0] => Y vertical phase step */
577 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
578 /* C vertical phase step */
579 WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1);
580 /* [19:0] => C horizontal phase step */
581 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
582
583 /* reset pscaler */
584#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
585 WRITE_VREG(DOS_SW_RESET0, (1 << 10));
586 WRITE_VREG(DOS_SW_RESET0, 0);
587#else
588 WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE);
589#endif
590 READ_RESET_REG(RESET2_REGISTER);
591 READ_RESET_REG(RESET2_REGISTER);
592 READ_RESET_REG(RESET2_REGISTER);
593
594 WRITE_VREG(PSCALE_RST, 0x7);
595 WRITE_VREG(PSCALE_RST, 0x0);
596}
597
598static void vmjpeg_dump_state(struct vdec_s *vdec)
599{
600 struct vdec_mjpeg_hw_s *hw =
601 (struct vdec_mjpeg_hw_s *)(vdec->private);
602 mmjpeg_debug_print(DECODE_ID(hw), 0,
603 "====== %s\n", __func__);
604 mmjpeg_debug_print(DECODE_ID(hw), 0,
605 "width/height (%d/%d)\n",
606 hw->frame_width,
607 hw->frame_height
608 );
609 mmjpeg_debug_print(DECODE_ID(hw), 0,
610 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d put_frm %d run %d not_run_ready %d input_empty %d\n",
611 input_frame_based(vdec),
612 hw->eos,
613 hw->stat,
614 hw->dec_result,
615 hw->frame_num,
616 hw->put_num,
617 hw->run_count,
618 hw->not_run_ready,
619 hw->input_empty
620 );
621 if (vf_get_receiver(vdec->vf_provider_name)) {
622 enum receviver_start_e state =
623 vf_notify_receiver(vdec->vf_provider_name,
624 VFRAME_EVENT_PROVIDER_QUREY_STATE,
625 NULL);
626 mmjpeg_debug_print(DECODE_ID(hw), 0,
627 "\nreceiver(%s) state %d\n",
628 vdec->vf_provider_name,
629 state);
630 }
631 mmjpeg_debug_print(DECODE_ID(hw), 0,
632 "%s, newq(%d/%d), dispq(%d/%d) vf peek/get/put (%d/%d/%d)\n",
633 __func__,
634 kfifo_len(&hw->newframe_q),
635 VF_POOL_SIZE,
636 kfifo_len(&hw->display_q),
637 VF_POOL_SIZE,
638 hw->peek_num,
639 hw->get_num,
640 hw->put_num
641 );
642 mmjpeg_debug_print(DECODE_ID(hw), 0,
643 "VIFF_BIT_CNT=0x%x\n",
644 READ_VREG(VIFF_BIT_CNT));
645 mmjpeg_debug_print(DECODE_ID(hw), 0,
646 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
647 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
648 mmjpeg_debug_print(DECODE_ID(hw), 0,
649 "VLD_MEM_VIFIFO_WP=0x%x\n",
650 READ_VREG(VLD_MEM_VIFIFO_WP));
651 mmjpeg_debug_print(DECODE_ID(hw), 0,
652 "VLD_MEM_VIFIFO_RP=0x%x\n",
653 READ_VREG(VLD_MEM_VIFIFO_RP));
654 mmjpeg_debug_print(DECODE_ID(hw), 0,
655 "PARSER_VIDEO_RP=0x%x\n",
656 READ_PARSER_REG(PARSER_VIDEO_RP));
657 mmjpeg_debug_print(DECODE_ID(hw), 0,
658 "PARSER_VIDEO_WP=0x%x\n",
659 READ_PARSER_REG(PARSER_VIDEO_WP));
660 if (input_frame_based(vdec) &&
661 debug_enable & PRINT_FRAMEBASE_DATA
662 ) {
663 int jj;
664 if (hw->chunk && hw->chunk->block &&
665 hw->chunk->size > 0) {
666 u8 *data = NULL;
667
668 if (!hw->chunk->block->is_mapped)
669 data = codec_mm_vmap(hw->chunk->block->start +
670 hw->chunk->offset, hw->chunk->size);
671 else
672 data = ((u8 *)hw->chunk->block->start_virt) +
673 hw->chunk->offset;
674
675 mmjpeg_debug_print(DECODE_ID(hw), 0,
676 "frame data size 0x%x\n",
677 hw->chunk->size);
678 for (jj = 0; jj < hw->chunk->size; jj++) {
679 if ((jj & 0xf) == 0)
680 mmjpeg_debug_print(DECODE_ID(hw),
681 PRINT_FRAMEBASE_DATA,
682 "%06x:", jj);
683 mmjpeg_debug_print(DECODE_ID(hw),
684 PRINT_FRAMEBASE_DATA,
685 "%02x ", data[jj]);
686 if (((jj + 1) & 0xf) == 0)
687 mmjpeg_debug_print(DECODE_ID(hw),
688 PRINT_FRAMEBASE_DATA,
689 "\n");
690 }
691
692 if (!hw->chunk->block->is_mapped)
693 codec_mm_unmap_phyaddr(data);
694 }
695 }
696}
697static void reset_process_time(struct vdec_mjpeg_hw_s *hw)
698{
699 if (hw->start_process_time) {
700 unsigned process_time =
701 1000 * (jiffies - hw->start_process_time) / HZ;
702 hw->start_process_time = 0;
703 if (process_time > max_process_time[DECODE_ID(hw)])
704 max_process_time[DECODE_ID(hw)] = process_time;
705 }
706}
707
708static void start_process_time(struct vdec_mjpeg_hw_s *hw)
709{
710 hw->decode_timeout_count = 2;
711 hw->start_process_time = jiffies;
712}
713
714static void timeout_process(struct vdec_mjpeg_hw_s *hw)
715{
716 amvdec_stop();
717 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
718 "%s decoder timeout\n", __func__);
719 hw->dec_result = DEC_RESULT_DONE;
720 reset_process_time(hw);
721 vdec_schedule_work(&hw->work);
722}
723
724static void check_timer_func(unsigned long arg)
725{
726 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)arg;
727 struct vdec_s *vdec = hw_to_vdec(hw);
728 int timeout_val = decode_timeout_val;
729
730 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
731 "%s: status:nstatus=%d:%d\n",
732 __func__, vdec->status, vdec->next_status);
733 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
734 "%s: %d,buftl=%x:%x:%x:%x\n",
735 __func__, __LINE__,
736 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
737 READ_PARSER_REG(PARSER_VIDEO_WP),
738 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
739 READ_VREG(VLD_MEM_VIFIFO_WP));
740
741 if (radr != 0) {
742 if (rval != 0) {
743 WRITE_VREG(radr, rval);
744 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
745 } else
746 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
747 rval = 0;
748 radr = 0;
749 }
750
751 if (((debug_enable & PRINT_FLAG_TIMEOUT_STATUS) == 0) &&
752 (input_frame_based(vdec) ||
753 ((u32)READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x100)) &&
754 (timeout_val > 0) &&
755 (hw->start_process_time > 0) &&
756 ((1000 * (jiffies - hw->start_process_time) / HZ)
757 > timeout_val)) {
758 if (hw->last_vld_level == READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
759 if (hw->decode_timeout_count > 0)
760 hw->decode_timeout_count--;
761 if (hw->decode_timeout_count == 0)
762 timeout_process(hw);
763 }
764 hw->last_vld_level = READ_VREG(VLD_MEM_VIFIFO_LEVEL);
765 }
766
767 if (READ_VREG(DEC_STATUS_REG) == DEC_DECODE_TIMEOUT) {
768 pr_info("ucode DEC_DECODE_TIMEOUT\n");
769 if (hw->decode_timeout_count > 0)
770 hw->decode_timeout_count--;
771 if (hw->decode_timeout_count == 0)
772 timeout_process(hw);
773 WRITE_VREG(DEC_STATUS_REG, 0);
774 }
775
776 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
777 hw->dec_result = DEC_RESULT_FORCE_EXIT;
778 vdec_schedule_work(&hw->work);
779 pr_info("vdec requested to be disconnected\n");
780 return;
781 }
782 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
783}
784
785static void vmjpeg_hw_ctx_restore(struct vdec_s *vdec, int index)
786{
787 struct vdec_mjpeg_hw_s *hw =
788 (struct vdec_mjpeg_hw_s *)vdec->private;
789 struct buffer_spec_s *buff_spec;
790 u32 i;
791
792 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6));
793 WRITE_VREG(DOS_SW_RESET0, 0);
794
795 if (!hw->init_flag) {
796 vmjpeg_canvas_init(vdec);
797 } else {
798 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
799 buff_spec = &hw->buffer_spec[i];
800 canvas_config_config(buff_spec->y_canvas_index,
801 &buff_spec->canvas_config[0]);
802 canvas_config_config(buff_spec->u_canvas_index,
803 &buff_spec->canvas_config[1]);
804 canvas_config_config(buff_spec->v_canvas_index,
805 &buff_spec->canvas_config[2]);
806 }
807 }
808
809 /* find next decode buffer index */
810 WRITE_VREG(AV_SCRATCH_4, spec2canvas(&hw->buffer_spec[index]));
811 WRITE_VREG(AV_SCRATCH_5, index);
812
813 init_scaler();
814
815 /* clear buffer IN/OUT registers */
816 WRITE_VREG(MREG_TO_AMRISC, 0);
817 WRITE_VREG(MREG_FROM_AMRISC, 0);
818
819 WRITE_VREG(MCPU_INTR_MSK, 0xffff);
820 WRITE_VREG(MREG_DECODE_PARAM, (hw->frame_height << 4) | 0x8000);
821
822 /* clear mailbox interrupt */
823 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
824 /* enable mailbox interrupt */
825 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
826 /* set interrupt mapping for vld */
827 WRITE_VREG(ASSIST_AMR1_INT8, 8);
828#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
829 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
830#endif
831}
832
833static s32 vmjpeg_init(struct vdec_s *vdec)
834{
835 int i;
836 int size = -1, fw_size = 0x1000 * 16;
837 struct firmware_s *fw = NULL;
838 struct vdec_mjpeg_hw_s *hw =
839 (struct vdec_mjpeg_hw_s *)vdec->private;
840
841 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
842 if (IS_ERR_OR_NULL(fw))
843 return -ENOMEM;
844
845 size = get_firmware_data(VIDEO_DEC_MJPEG_MULTI, fw->data);
846 if (size < 0) {
847 pr_err("get firmware fail.");
848 vfree(fw);
849 return -1;
850 }
851
852 fw->len = size;
853 hw->fw = fw;
854
855 hw->frame_width = hw->vmjpeg_amstream_dec_info.width;
856 hw->frame_height = hw->vmjpeg_amstream_dec_info.height;
857 hw->frame_dur = ((hw->vmjpeg_amstream_dec_info.rate) ?
858 hw->vmjpeg_amstream_dec_info.rate : 3840);
859 hw->saved_resolution = 0;
860 hw->eos = 0;
861 hw->init_flag = 0;
862 hw->frame_num = 0;
863 hw->put_num = 0;
864 hw->run_count = 0;
865 hw->not_run_ready = 0;
866 hw->input_empty = 0;
867 hw->peek_num = 0;
868 hw->get_num = 0;
869 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++)
870 hw->vfbuf_use[i] = 0;
871
872 INIT_KFIFO(hw->display_q);
873 INIT_KFIFO(hw->newframe_q);
874
875 for (i = 0; i < VF_POOL_SIZE; i++) {
876 const struct vframe_s *vf = &hw->vfpool[i];
877
878 hw->vfpool[i].index = -1;
879 kfifo_put(&hw->newframe_q, vf);
880 }
881
882 if (hw->mm_blk_handle) {
883 decoder_bmmu_box_free(hw->mm_blk_handle);
884 hw->mm_blk_handle = NULL;
885 }
886
887 hw->mm_blk_handle = decoder_bmmu_box_alloc_box(
888 DRIVER_NAME,
889 0,
890 MAX_BMMU_BUFFER_NUM,
891 4 + PAGE_SHIFT,
892 CODEC_MM_FLAGS_CMA_CLEAR |
893 CODEC_MM_FLAGS_FOR_VDECODER);
894
895 init_timer(&hw->check_timer);
896
897 hw->check_timer.data = (unsigned long)hw;
898 hw->check_timer.function = check_timer_func;
899 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
900 /*add_timer(&hw->check_timer);*/
901 hw->stat |= STAT_TIMER_ARM;
902 hw->stat |= STAT_ISR_REG;
903
904 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
905 INIT_WORK(&hw->work, vmjpeg_work);
906 pr_info("w:h=%d:%d\n", hw->frame_width, hw->frame_height);
907 return 0;
908}
909
910static unsigned long run_ready(struct vdec_s *vdec,
911 unsigned long mask)
912{
913 struct vdec_mjpeg_hw_s *hw =
914 (struct vdec_mjpeg_hw_s *)vdec->private;
915 hw->not_run_ready++;
916 if (hw->eos)
917 return 0;
918 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
919 && pre_decode_buf_level != 0) {
920 u32 rp, wp, level;
921
922 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
923 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
924 if (wp < rp)
925 level = vdec->input.size + wp - rp;
926 else
927 level = wp - rp;
928
929 if (level < pre_decode_buf_level)
930 return 0;
931 }
932 hw->not_run_ready = 0;
933
934 if (vdec->parallel_dec == 1)
935 return CORE_MASK_VDEC_1;
936 else
937 return CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
938}
939
940static void run(struct vdec_s *vdec, unsigned long mask,
941 void (*callback)(struct vdec_s *, void *), void *arg)
942{
943 struct vdec_mjpeg_hw_s *hw =
944 (struct vdec_mjpeg_hw_s *)vdec->private;
945 int i, ret;
946
947 hw->vdec_cb_arg = arg;
948 hw->vdec_cb = callback;
949
950 hw->run_count++;
951 vdec_reset_core(vdec);
952 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
953 if (hw->vfbuf_use[i] == 0)
954 break;
955 }
956
957 if (i == DECODE_BUFFER_NUM_MAX) {
958 hw->dec_result = DEC_RESULT_AGAIN;
959 vdec_schedule_work(&hw->work);
960 return;
961 }
962
963 ret = vdec_prepare_input(vdec, &hw->chunk);
964 if (ret <= 0) {
965 hw->input_empty++;
966 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
967 "%s: %d,r=%d,buftl=%x:%x:%x\n",
968 __func__, __LINE__, ret,
969 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
970 READ_PARSER_REG(PARSER_VIDEO_WP),
971 READ_VREG(VLD_MEM_VIFIFO_WP));
972
973 hw->dec_result = DEC_RESULT_AGAIN;
974 vdec_schedule_work(&hw->work);
975 return;
976 }
977 hw->input_empty = 0;
978 hw->dec_result = DEC_RESULT_NONE;
979 if (vdec->mc_loaded) {
980 /*firmware have load before,
981 and not changes to another.
982 ignore reload.
983 */
984 } else {
985 ret = amvdec_vdec_loadmc_ex(VFORMAT_MJPEG, "mmjpeg", vdec, hw->fw->data);
986 if (ret < 0) {
987 pr_err("[%d] MMJPEG: the %s fw loading failed, err: %x\n",
988 vdec->id, tee_enabled() ? "TEE" : "local", ret);
989 hw->dec_result = DEC_RESULT_FORCE_EXIT;
990 vdec_schedule_work(&hw->work);
991 return;
992 }
993 vdec->mc_loaded = 1;
994 vdec->mc_type = VFORMAT_MJPEG;
995 }
996/* if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) {
997 pr_err("%s: Error amvdec_loadmc fail\n", __func__);
998 return;
999 }*/
1000
1001 vmjpeg_hw_ctx_restore(vdec, i);
1002#if 0
1003 vdec_enable_input(vdec);
1004 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1005#endif
1006 hw->stat |= STAT_MC_LOAD;
1007 start_process_time(hw);
1008 hw->last_vld_level = 0;
1009 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1010 amvdec_start();
1011 vdec_enable_input(vdec);
1012 hw->stat |= STAT_VDEC_RUN;
1013 hw->init_flag = 1;
1014
1015 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1016 "%s (0x%x 0x%x 0x%x) vldcrl 0x%x bitcnt 0x%x powerctl 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1017 __func__,
1018 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
1019 READ_VREG(VLD_MEM_VIFIFO_WP),
1020 READ_VREG(VLD_MEM_VIFIFO_RP),
1021 READ_VREG(VLD_DECODE_CONTROL),
1022 READ_VREG(VIFF_BIT_CNT),
1023 READ_VREG(POWER_CTL_VLD),
1024 READ_VREG(VLD_MEM_VIFIFO_START_PTR),
1025 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR),
1026 READ_VREG(VLD_MEM_VIFIFO_CONTROL),
1027 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1028 READ_VREG(VLD_MEM_VIFIFO_END_PTR));
1029}
1030static void wait_vmjpeg_search_done(struct vdec_mjpeg_hw_s *hw)
1031{
1032 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1033 int count = 0;
1034
1035 do {
1036 usleep_range(100, 500);
1037 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
1038 break;
1039 if (count > 1000) {
1040 mmjpeg_debug_print(DECODE_ID(hw), 0,
1041 "%s, count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
1042 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
1043 break;
1044 } else
1045 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1046 count++;
1047 } while (1);
1048}
1049
1050static void vmjpeg_work(struct work_struct *work)
1051{
1052 struct vdec_mjpeg_hw_s *hw = container_of(work,
1053 struct vdec_mjpeg_hw_s, work);
1054 struct vdec_s *vdec = hw_to_vdec(hw);
1055
1056 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_BUFFER_DETAIL,
1057 "%s: result=%d,len=%d:%d\n",
1058 __func__, hw->dec_result,
1059 kfifo_len(&hw->newframe_q),
1060 kfifo_len(&hw->display_q));
1061 if (hw->dec_result == DEC_RESULT_DONE) {
1062 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1063 hw->chunk = NULL;
1064 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
1065 /*
1066 stream base: stream buf empty or timeout
1067 frame base: vdec_prepare_input fail
1068 */
1069 if (!vdec_has_more_input(hw_to_vdec(hw))) {
1070 hw->dec_result = DEC_RESULT_EOS;
1071 vdec_schedule_work(&hw->work);
1072 /*pr_info("%s: return\n",
1073 __func__);*/
1074 return;
1075 }
1076 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
1077 pr_info("%s: force exit\n", __func__);
1078 if (hw->stat & STAT_ISR_REG) {
1079 amvdec_stop();
1080 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1081 hw->stat &= ~STAT_ISR_REG;
1082 }
1083 } else if (hw->dec_result == DEC_RESULT_EOS) {
1084 pr_info("%s: end of stream\n", __func__);
1085 if (hw->stat & STAT_VDEC_RUN) {
1086 amvdec_stop();
1087 hw->stat &= ~STAT_VDEC_RUN;
1088 }
1089 hw->eos = 1;
1090 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1091 hw->chunk = NULL;
1092 vdec_clean_input(hw_to_vdec(hw));
1093 }
1094 if (hw->stat & STAT_VDEC_RUN) {
1095 amvdec_stop();
1096 hw->stat &= ~STAT_VDEC_RUN;
1097 }
1098 /*disable mbox interrupt */
1099 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
1100 wait_vmjpeg_search_done(hw);
1101 /* mark itself has all HW resource released and input released */
1102 if (vdec->parallel_dec == 1)
1103 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1104 else {
1105 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
1106 | CORE_MASK_HEVC);
1107 }
1108 del_timer_sync(&hw->check_timer);
1109 hw->stat &= ~STAT_TIMER_ARM;
1110
1111 if (hw->vdec_cb)
1112 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
1113}
1114
1115static int vmjpeg_stop(struct vdec_mjpeg_hw_s *hw)
1116{
1117 pr_info("%s ...count = %d\n", __func__, hw->frame_num);
1118
1119 if (hw->stat & STAT_VDEC_RUN) {
1120 amvdec_stop();
1121 pr_info("%s amvdec_stop\n", __func__);
1122 hw->stat &= ~STAT_VDEC_RUN;
1123 }
1124
1125 if (hw->stat & STAT_ISR_REG) {
1126 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1127 hw->stat &= ~STAT_ISR_REG;
1128 }
1129
1130 if (hw->stat & STAT_TIMER_ARM) {
1131 del_timer_sync(&hw->check_timer);
1132 hw->stat &= ~STAT_TIMER_ARM;
1133 }
1134 cancel_work_sync(&hw->work);
1135 hw->init_flag = 0;
1136
1137 if (hw->mm_blk_handle) {
1138 decoder_bmmu_box_free(hw->mm_blk_handle);
1139 hw->mm_blk_handle = NULL;
1140 }
1141
1142 if (hw->fw) {
1143 vfree(hw->fw);
1144 hw->fw = NULL;
1145 }
1146
1147 return 0;
1148}
1149
1150static int ammvdec_mjpeg_probe(struct platform_device *pdev)
1151{
1152 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
1153 struct vdec_mjpeg_hw_s *hw = NULL;
1154
1155 if (pdata == NULL) {
1156 pr_info("ammvdec_mjpeg memory resource undefined.\n");
1157 return -EFAULT;
1158 }
1159
1160 hw = (struct vdec_mjpeg_hw_s *)devm_kzalloc(&pdev->dev,
1161 sizeof(struct vdec_mjpeg_hw_s), GFP_KERNEL);
1162 hw = vzalloc(sizeof(struct vdec_mjpeg_hw_s));
1163 if (hw == NULL) {
1164 pr_info("\nammvdec_mjpeg device data allocation failed\n");
1165 return -ENOMEM;
1166 }
1167
1168 pdata->private = hw;
1169 pdata->dec_status = vmjpeg_dec_status;
1170
1171 pdata->run = run;
1172 pdata->run_ready = run_ready;
1173 pdata->irq_handler = vmjpeg_isr;
1174 pdata->dump_state = vmjpeg_dump_state;
1175
1176 if (pdata->parallel_dec == 1) {
1177 int i;
1178 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1179 hw->buffer_spec[i].y_canvas_index = -1;
1180 hw->buffer_spec[i].u_canvas_index = -1;
1181 hw->buffer_spec[i].v_canvas_index = -1;
1182 }
1183 }
1184
1185 if (pdata->use_vfm_path)
1186 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1187 VFM_DEC_PROVIDER_NAME);
1188 else
1189 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1190 PROVIDER_NAME ".%02x", pdev->id & 0xff);
1191
1192 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
1193 &vf_provider_ops, pdata);
1194
1195 platform_set_drvdata(pdev, pdata);
1196
1197 hw->platform_dev = pdev;
1198
1199 if (pdata->sys_info)
1200 hw->vmjpeg_amstream_dec_info = *pdata->sys_info;
1201
1202 vdec_source_changed(VFORMAT_MJPEG,
1203 1920, 1080, 60);
1204 if (vmjpeg_init(pdata) < 0) {
1205 pr_info("ammvdec_mjpeg init failed.\n");
1206 if (hw) {
1207 vfree(hw);
1208 hw = NULL;
1209 }
1210 pdata->dec_status = NULL;
1211 return -ENODEV;
1212 }
1213 if (pdata->parallel_dec == 1)
1214 vdec_core_request(pdata, CORE_MASK_VDEC_1);
1215 else {
1216 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
1217 | CORE_MASK_COMBINE);
1218 }
1219
1220 return 0;
1221}
1222
1223static int ammvdec_mjpeg_remove(struct platform_device *pdev)
1224{
1225 struct vdec_mjpeg_hw_s *hw =
1226 (struct vdec_mjpeg_hw_s *)
1227 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
1228 struct vdec_s *vdec = hw_to_vdec(hw);
1229 int i;
1230
1231 vmjpeg_stop(hw);
1232
1233 if (vdec->parallel_dec == 1)
1234 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1235 else
1236 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
1237 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
1238 if (vdec->parallel_dec == 1) {
1239 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1240 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
1241 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
1242 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
1243 }
1244 }
1245 if (hw) {
1246 vfree(hw);
1247 hw = NULL;
1248 }
1249 pr_info("%s\n", __func__);
1250 return 0;
1251}
1252
1253/****************************************/
1254#ifdef CONFIG_PM
1255static int mmjpeg_suspend(struct device *dev)
1256{
1257 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
1258 return 0;
1259}
1260
1261static int mmjpeg_resume(struct device *dev)
1262{
1263 amvdec_resume(to_platform_device(dev));
1264 return 0;
1265}
1266
1267static const struct dev_pm_ops mmjpeg_pm_ops = {
1268 SET_SYSTEM_SLEEP_PM_OPS(mmjpeg_suspend, mmjpeg_resume)
1269};
1270#endif
1271
1272static struct platform_driver ammvdec_mjpeg_driver = {
1273 .probe = ammvdec_mjpeg_probe,
1274 .remove = ammvdec_mjpeg_remove,
1275 .driver = {
1276 .name = DRIVER_NAME,
1277#ifdef CONFIG_PM
1278 .pm = &mmjpeg_pm_ops,
1279#endif
1280 }
1281};
1282
1283static struct codec_profile_t ammvdec_mjpeg_profile = {
1284 .name = "mmjpeg",
1285 .profile = ""
1286};
1287
1288static int __init ammvdec_mjpeg_driver_init_module(void)
1289{
1290 if (platform_driver_register(&ammvdec_mjpeg_driver)) {
1291 pr_err("failed to register ammvdec_mjpeg driver\n");
1292 return -ENODEV;
1293 }
1294 vcodec_profile_register(&ammvdec_mjpeg_profile);
1295 return 0;
1296}
1297
1298static void __exit ammvdec_mjpeg_driver_remove_module(void)
1299{
1300 platform_driver_unregister(&ammvdec_mjpeg_driver);
1301}
1302
1303/****************************************/
1304module_param(debug_enable, uint, 0664);
1305MODULE_PARM_DESC(debug_enable, "\n debug enable\n");
1306module_param(pre_decode_buf_level, int, 0664);
1307MODULE_PARM_DESC(pre_decode_buf_level,
1308 "\n ammvdec_h264 pre_decode_buf_level\n");
1309module_param(udebug_flag, uint, 0664);
1310MODULE_PARM_DESC(udebug_flag, "\n amvdec_mmpeg12 udebug_flag\n");
1311
1312
1313module_param(decode_timeout_val, uint, 0664);
1314MODULE_PARM_DESC(decode_timeout_val, "\n ammvdec_mjpeg decode_timeout_val\n");
1315
1316module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
1317
1318module_param(radr, uint, 0664);
1319MODULE_PARM_DESC(radr, "\nradr\n");
1320
1321module_param(rval, uint, 0664);
1322MODULE_PARM_DESC(rval, "\nrval\n");
1323
1324module_param(without_display_mode, uint, 0664);
1325MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
1326
1327module_init(ammvdec_mjpeg_driver_init_module);
1328module_exit(ammvdec_mjpeg_driver_remove_module);
1329
1330MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver");
1331MODULE_LICENSE("GPL");
1332MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
1333
generated by cgit at 2024-05-17 11:58:01 (GMT)