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path: root/drivers/frame_provider/decoder/mjpeg/vmjpeg_multi.c (plain)
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1/*
2 * drivers/amlogic/amports/vmjpeg.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/amlogic/media/frame_sync/ptsserv.h>
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/tee.h>
33
34#include <linux/amlogic/media/utils/vdec_reg.h>
35#include <linux/amlogic/media/registers/register.h>
36#include "../../../stream_input/amports/amports_priv.h"
37
38#include "../utils/vdec_input.h"
39#include "../utils/vdec.h"
40#include "../utils/amvdec.h"
41#include "../utils/decoder_mmu_box.h"
42#include "../utils/decoder_bmmu_box.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44#include <linux/amlogic/media/codec_mm/configs.h>
45#include "../utils/firmware.h"
46#include "../utils/vdec_v4l2_buffer_ops.h"
47
48#define MEM_NAME "codec_mmjpeg"
49
50#define DRIVER_NAME "ammvdec_mjpeg"
51#define MODULE_NAME "ammvdec_mjpeg"
52#define CHECK_INTERVAL (HZ/100)
53
54/* protocol register usage
55 * AV_SCRATCH_4 : decode buffer spec
56 * AV_SCRATCH_5 : decode buffer index
57 */
58
59#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */
60/* bit 15-4: reference height */
61#define MREG_TO_AMRISC AV_SCRATCH_8
62#define MREG_FROM_AMRISC AV_SCRATCH_9
63#define MREG_FRAME_OFFSET AV_SCRATCH_A
64#define DEC_STATUS_REG AV_SCRATCH_F
65#define MREG_PIC_WIDTH AV_SCRATCH_B
66#define MREG_PIC_HEIGHT AV_SCRATCH_C
67#define DECODE_STOP_POS AV_SCRATCH_K
68
69#define PICINFO_BUF_IDX_MASK 0x0007
70#define PICINFO_AVI1 0x0080
71#define PICINFO_INTERLACE 0x0020
72#define PICINFO_INTERLACE_AVI1_BOT 0x0010
73#define PICINFO_INTERLACE_FIRST 0x0010
74
75#define VF_POOL_SIZE 16
76#define DECODE_BUFFER_NUM_MAX 4
77#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX
78
79#define DEFAULT_MEM_SIZE (32*SZ_1M)
80static int debug_enable;
81static u32 udebug_flag;
82#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
83
84static unsigned int radr;
85static unsigned int rval;
86#define VMJPEG_DEV_NUM 9
87static unsigned int max_decode_instance_num = VMJPEG_DEV_NUM;
88static unsigned int max_process_time[VMJPEG_DEV_NUM];
89static unsigned int decode_timeout_val = 200;
90static struct vframe_s *vmjpeg_vf_peek(void *);
91static struct vframe_s *vmjpeg_vf_get(void *);
92static void vmjpeg_vf_put(struct vframe_s *, void *);
93static int vmjpeg_vf_states(struct vframe_states *states, void *);
94static int vmjpeg_event_cb(int type, void *data, void *private_data);
95static void vmjpeg_work(struct work_struct *work);
96static int pre_decode_buf_level = 0x800;
97static int start_decode_buf_level = 0x2000;
98static u32 without_display_mode;
99#undef pr_info
100#define pr_info printk
101unsigned int mmjpeg_debug_mask = 0xff;
102#define PRINT_FLAG_ERROR 0x0
103#define PRINT_FLAG_RUN_FLOW 0X0001
104#define PRINT_FLAG_TIMEINFO 0x0002
105#define PRINT_FLAG_UCODE_DETAIL 0x0004
106#define PRINT_FLAG_VLD_DETAIL 0x0008
107#define PRINT_FLAG_DEC_DETAIL 0x0010
108#define PRINT_FLAG_BUFFER_DETAIL 0x0020
109#define PRINT_FLAG_RESTORE 0x0040
110#define PRINT_FRAME_NUM 0x0080
111#define PRINT_FLAG_FORCE_DONE 0x0100
112#define PRINT_FRAMEBASE_DATA 0x0400
113#define PRINT_FLAG_TIMEOUT_STATUS 0x1000
114#define PRINT_FLAG_V4L_DETAIL 0x8000
115
116int mmjpeg_debug_print(int index, int debug_flag, const char *fmt, ...)
117{
118 if (((debug_enable & debug_flag) &&
119 ((1 << index) & mmjpeg_debug_mask))
120 || (debug_flag == PRINT_FLAG_ERROR)) {
121 unsigned char buf[512];
122 int len = 0;
123 va_list args;
124 va_start(args, fmt);
125 len = sprintf(buf, "%d: ", index);
126 vsnprintf(buf + len, 512-len, fmt, args);
127 pr_info("%s", buf);
128 va_end(args);
129 }
130 return 0;
131}
132
133static const char vmjpeg_dec_id[] = "vmmjpeg-dev";
134
135#define PROVIDER_NAME "vdec.mjpeg"
136static const struct vframe_operations_s vf_provider_ops = {
137 .peek = vmjpeg_vf_peek,
138 .get = vmjpeg_vf_get,
139 .put = vmjpeg_vf_put,
140 .event_cb = vmjpeg_event_cb,
141 .vf_states = vmjpeg_vf_states,
142};
143
144#define DEC_RESULT_NONE 0
145#define DEC_RESULT_DONE 1
146#define DEC_RESULT_AGAIN 2
147#define DEC_RESULT_ERROR 3
148#define DEC_RESULT_FORCE_EXIT 4
149#define DEC_RESULT_EOS 5
150#define DEC_DECODE_TIMEOUT 0x21
151
152
153struct buffer_spec_s {
154 unsigned int y_addr;
155 unsigned int u_addr;
156 unsigned int v_addr;
157
158 int y_canvas_index;
159 int u_canvas_index;
160 int v_canvas_index;
161
162 struct canvas_config_s canvas_config[3];
163 unsigned long cma_alloc_addr;
164 int cma_alloc_count;
165 unsigned int buf_adr;
166 ulong v4l_ref_buf_addr;
167};
168
169#define spec2canvas(x) \
170 (((x)->v_canvas_index << 16) | \
171 ((x)->u_canvas_index << 8) | \
172 ((x)->y_canvas_index << 0))
173
174struct vdec_mjpeg_hw_s {
175 spinlock_t lock;
176 struct mutex vmjpeg_mutex;
177
178 struct platform_device *platform_dev;
179 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
180 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
181
182 struct vframe_s vfpool[VF_POOL_SIZE];
183 struct buffer_spec_s buffer_spec[DECODE_BUFFER_NUM_MAX];
184 s32 vfbuf_use[DECODE_BUFFER_NUM_MAX];
185
186 u32 frame_width;
187 u32 frame_height;
188 u32 frame_dur;
189 u32 saved_resolution;
190 u8 init_flag;
191 u32 stat;
192 u32 dec_result;
193 unsigned long buf_start;
194 u32 buf_size;
195 void *mm_blk_handle;
196 struct dec_sysinfo vmjpeg_amstream_dec_info;
197
198 struct vframe_chunk_s *chunk;
199 struct work_struct work;
200 void (*vdec_cb)(struct vdec_s *, void *);
201 void *vdec_cb_arg;
202 struct firmware_s *fw;
203 struct timer_list check_timer;
204 u32 decode_timeout_count;
205 unsigned long int start_process_time;
206 u32 last_vld_level;
207 u8 eos;
208 u32 frame_num;
209 u32 put_num;
210 u32 run_count;
211 u32 not_run_ready;
212 u32 buffer_not_ready;
213 u32 input_empty;
214 u32 peek_num;
215 u32 get_num;
216 bool is_used_v4l;
217 void *v4l2_ctx;
218 bool v4l_params_parsed;
219};
220
221static void reset_process_time(struct vdec_mjpeg_hw_s *hw);
222static void set_frame_info(struct vdec_mjpeg_hw_s *hw, struct vframe_s *vf)
223{
224 u32 temp;
225 temp = READ_VREG(MREG_PIC_WIDTH);
226 if (temp > 1920)
227 vf->width = hw->frame_width = 1920;
228 else if (temp > 0)
229 vf->width = hw->frame_width = temp;
230 temp = READ_VREG(MREG_PIC_HEIGHT);
231 if (temp > 1088)
232 vf->height = hw->frame_height = 1088;
233 else if (temp > 0)
234 vf->height = hw->frame_height = temp;
235 vf->duration = hw->frame_dur;
236 vf->ratio_control = 0;
237 vf->duration_pulldown = 0;
238 vf->flag = 0;
239
240 vf->canvas0Addr = vf->canvas1Addr = -1;
241 vf->plane_num = 3;
242
243 vf->canvas0_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
244 vf->canvas0_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
245 vf->canvas0_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
246
247 vf->canvas1_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
248 vf->canvas1_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
249 vf->canvas1_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
250}
251
252static irqreturn_t vmjpeg_isr(struct vdec_s *vdec, int irq)
253{
254 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)(vdec->private);
255 u32 reg;
256 struct vframe_s *vf = NULL;
257 u32 index, offset = 0, pts;
258 u64 pts_us64;
259 u32 frame_size;
260
261 if (!hw)
262 return IRQ_HANDLED;
263
264 if (hw->eos)
265 return IRQ_HANDLED;
266 reset_process_time(hw);
267 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
268 if (READ_VREG(AV_SCRATCH_D) != 0 &&
269 (debug_enable & PRINT_FLAG_UCODE_DETAIL)) {
270 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_D),
271 READ_VREG(AV_SCRATCH_E));
272 WRITE_VREG(AV_SCRATCH_D, 0);
273 return IRQ_HANDLED;
274 }
275
276 reg = READ_VREG(MREG_FROM_AMRISC);
277 index = READ_VREG(AV_SCRATCH_5);
278
279 if (index >= DECODE_BUFFER_NUM_MAX) {
280 pr_err("fatal error, invalid buffer index.");
281 return IRQ_HANDLED;
282 }
283
284 if (kfifo_get(&hw->newframe_q, &vf) == 0) {
285 pr_info(
286 "fatal error, no available buffer slot.");
287 return IRQ_HANDLED;
288 }
289
290 if (hw->is_used_v4l) {
291 struct aml_vcodec_ctx *ctx =
292 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
293
294 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
295 struct aml_vdec_ps_infos ps;
296
297 ps.visible_width = hw->frame_width;
298 ps.visible_height = hw->frame_height;
299 ps.coded_width = ALIGN(hw->frame_width, 64);
300 ps.coded_height = ALIGN(hw->frame_height, 64);
301 ps.dpb_size = MAX_BMMU_BUFFER_NUM - 1;
302 hw->v4l_params_parsed = true;
303 vdec_v4l_set_ps_infos(ctx, &ps);
304 }
305
306 if (!ctx->v4l_codec_ready)
307 return IRQ_HANDLED;
308 }
309
310 if (hw->is_used_v4l) {
311 vf->v4l_mem_handle
312 = hw->buffer_spec[index].v4l_ref_buf_addr;
313 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
314 "[%d] %s(), v4l mem handle: 0x%lx\n",
315 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
316 __func__, vf->v4l_mem_handle);
317 }
318
319 vf->index = index;
320 set_frame_info(hw, vf);
321
322 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
323 /* vf->pts = (pts_valid) ? pts : 0; */
324 /* vf->pts_us64 = (pts_valid) ? pts_us64 : 0; */
325
326 if (hw->chunk) {
327 vf->pts = hw->chunk->pts;
328 vf->pts_us64 = hw->chunk->pts64;
329 } else {
330 offset = READ_VREG(MREG_FRAME_OFFSET);
331 if (pts_lookup_offset_us64
332 (PTS_TYPE_VIDEO, offset, &pts,
333 &frame_size, 3000,
334 &pts_us64) == 0) {
335 vf->pts = pts;
336 vf->pts_us64 = pts_us64;
337 } else {
338 vf->pts = 0;
339 vf->pts_us64 = 0;
340 }
341 }
342 vf->orientation = 0;
343 hw->vfbuf_use[index]++;
344
345 vf->mem_handle =
346 decoder_bmmu_box_get_mem_handle(
347 hw->mm_blk_handle, index);
348 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
349 ATRACE_COUNTER(MODULE_NAME, vf->pts);
350 hw->frame_num++;
351 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
352 "%s:frame num:%d,pts=%d,pts64=%lld. dur=%d\n",
353 __func__, hw->frame_num,
354 vf->pts, vf->pts_us64, vf->duration);
355 vdec->vdec_fps_detec(vdec->id);
356 if (without_display_mode == 0) {
357 vf_notify_receiver(vdec->vf_provider_name,
358 VFRAME_EVENT_PROVIDER_VFRAME_READY,
359 NULL);
360 } else
361 vmjpeg_vf_put(vmjpeg_vf_get(vdec), vdec);
362
363 hw->dec_result = DEC_RESULT_DONE;
364
365 vdec_schedule_work(&hw->work);
366
367 return IRQ_HANDLED;
368}
369
370static struct vframe_s *vmjpeg_vf_peek(void *op_arg)
371{
372 struct vframe_s *vf;
373 struct vdec_s *vdec = op_arg;
374 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
375
376 if (!hw)
377 return NULL;
378 hw->peek_num++;
379 if (kfifo_peek(&hw->display_q, &vf))
380 return vf;
381
382 return NULL;
383}
384
385static struct vframe_s *vmjpeg_vf_get(void *op_arg)
386{
387 struct vframe_s *vf;
388 struct vdec_s *vdec = op_arg;
389 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
390
391 if (!hw)
392 return NULL;
393 hw->get_num++;
394 if (kfifo_get(&hw->display_q, &vf))
395 return vf;
396
397 return NULL;
398}
399
400static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg)
401{
402 struct vdec_s *vdec = op_arg;
403 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
404 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
405 "%s:put_num:%d\n", __func__, hw->put_num);
406 hw->vfbuf_use[vf->index]--;
407 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
408 hw->put_num++;
409}
410
411static int vmjpeg_event_cb(int type, void *data, void *private_data)
412{
413 return 0;
414}
415
416static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg)
417{
418 unsigned long flags;
419 struct vdec_s *vdec = op_arg;
420 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
421
422 spin_lock_irqsave(&hw->lock, flags);
423
424 states->vf_pool_size = VF_POOL_SIZE;
425 states->buf_free_num = kfifo_len(&hw->newframe_q);
426 states->buf_avail_num = kfifo_len(&hw->display_q);
427 states->buf_recycle_num = 0;
428
429 spin_unlock_irqrestore(&hw->lock, flags);
430
431 return 0;
432}
433
434static int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
435{
436 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
437
438 if (!hw)
439 return -1;
440
441 vstatus->frame_width = hw->frame_width;
442 vstatus->frame_height = hw->frame_height;
443 if (0 != hw->frame_dur)
444 vstatus->frame_rate = 96000 / hw->frame_dur;
445 else
446 vstatus->frame_rate = 96000;
447 vstatus->error_count = 0;
448 vstatus->status = hw->stat;
449
450 return 0;
451}
452
453/****************************************/
454static void vmjpeg_canvas_init(struct vdec_mjpeg_hw_s *hw)
455{
456 int i, ret;
457 u32 canvas_width, canvas_height;
458 u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
459 unsigned long buf_start, addr;
460 struct vdec_s *vdec = hw_to_vdec(hw);
461
462 canvas_width = 1920;
463 canvas_height = 1088;
464 decbuf_y_size = 0x200000;
465 decbuf_uv_size = 0x80000;
466 decbuf_size = 0x300000;
467
468 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
469 int canvas;
470
471 if (hw->is_used_v4l) {
472 continue;
473 } else {
474 ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i,
475 decbuf_size, DRIVER_NAME, &buf_start);
476 if (ret < 0) {
477 pr_err("CMA alloc failed! size 0x%d idx %d\n",
478 decbuf_size, i);
479 return;
480 }
481 }
482
483 hw->buffer_spec[i].buf_adr = buf_start;
484 addr = hw->buffer_spec[i].buf_adr;
485
486 hw->buffer_spec[i].y_addr = addr;
487 addr += decbuf_y_size;
488 hw->buffer_spec[i].u_addr = addr;
489 addr += decbuf_uv_size;
490 hw->buffer_spec[i].v_addr = addr;
491
492 if (vdec->parallel_dec == 1) {
493 if (hw->buffer_spec[i].y_canvas_index == -1)
494 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
495 if (hw->buffer_spec[i].u_canvas_index == -1)
496 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
497 if (hw->buffer_spec[i].v_canvas_index == -1)
498 hw->buffer_spec[i].v_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
499 } else {
500 canvas = vdec->get_canvas(i, 3);
501 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
502 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
503 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
504 }
505
506 canvas_config(hw->buffer_spec[i].y_canvas_index,
507 hw->buffer_spec[i].y_addr,
508 canvas_width,
509 canvas_height,
510 CANVAS_ADDR_NOWRAP,
511 CANVAS_BLKMODE_LINEAR);
512 hw->buffer_spec[i].canvas_config[0].phy_addr =
513 hw->buffer_spec[i].y_addr;
514 hw->buffer_spec[i].canvas_config[0].width =
515 canvas_width;
516 hw->buffer_spec[i].canvas_config[0].height =
517 canvas_height;
518 hw->buffer_spec[i].canvas_config[0].block_mode =
519 CANVAS_BLKMODE_LINEAR;
520
521 canvas_config(hw->buffer_spec[i].u_canvas_index,
522 hw->buffer_spec[i].u_addr,
523 canvas_width / 2,
524 canvas_height / 2,
525 CANVAS_ADDR_NOWRAP,
526 CANVAS_BLKMODE_LINEAR);
527 hw->buffer_spec[i].canvas_config[1].phy_addr =
528 hw->buffer_spec[i].u_addr;
529 hw->buffer_spec[i].canvas_config[1].width =
530 canvas_width / 2;
531 hw->buffer_spec[i].canvas_config[1].height =
532 canvas_height / 2;
533 hw->buffer_spec[i].canvas_config[1].block_mode =
534 CANVAS_BLKMODE_LINEAR;
535
536 canvas_config(hw->buffer_spec[i].v_canvas_index,
537 hw->buffer_spec[i].v_addr,
538 canvas_width / 2,
539 canvas_height / 2,
540 CANVAS_ADDR_NOWRAP,
541 CANVAS_BLKMODE_LINEAR);
542 hw->buffer_spec[i].canvas_config[2].phy_addr =
543 hw->buffer_spec[i].v_addr;
544 hw->buffer_spec[i].canvas_config[2].width =
545 canvas_width / 2;
546 hw->buffer_spec[i].canvas_config[2].height =
547 canvas_height / 2;
548 hw->buffer_spec[i].canvas_config[2].block_mode =
549 CANVAS_BLKMODE_LINEAR;
550 }
551}
552
553static void init_scaler(void)
554{
555 /* 4 point triangle */
556 const unsigned int filt_coef[] = {
557 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
558 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
559 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
560 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
561 0x18382808, 0x18382808, 0x17372909, 0x17372909,
562 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
563 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
564 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
565 0x10303010
566 };
567 int i;
568
569 /* pscale enable, PSCALE cbus bmem enable */
570 WRITE_VREG(PSCALE_CTRL, 0xc000);
571
572 /* write filter coefs */
573 WRITE_VREG(PSCALE_BMEM_ADDR, 0);
574 for (i = 0; i < 33; i++) {
575 WRITE_VREG(PSCALE_BMEM_DAT, 0);
576 WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]);
577 }
578
579 /* Y horizontal initial info */
580 WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2);
581 /* [35]: buf repeat pix0,
582 * [34:29] => buf receive num,
583 * [28:16] => buf blk x,
584 * [15:0] => buf phase
585 */
586 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
587 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
588
589 /* C horizontal initial info */
590 WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2);
591 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
592 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
593
594 /* Y vertical initial info */
595 WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2);
596 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
597 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
598
599 /* C vertical initial info */
600 WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2);
601 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
602 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
603
604 /* Y horizontal phase step */
605 WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1);
606 /* [19:0] => Y horizontal phase step */
607 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
608 /* C horizontal phase step */
609 WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1);
610 /* [19:0] => C horizontal phase step */
611 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
612
613 /* Y vertical phase step */
614 WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1);
615 /* [19:0] => Y vertical phase step */
616 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
617 /* C vertical phase step */
618 WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1);
619 /* [19:0] => C horizontal phase step */
620 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
621
622 /* reset pscaler */
623#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
624 WRITE_VREG(DOS_SW_RESET0, (1 << 10));
625 WRITE_VREG(DOS_SW_RESET0, 0);
626#else
627 WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE);
628#endif
629 READ_RESET_REG(RESET2_REGISTER);
630 READ_RESET_REG(RESET2_REGISTER);
631 READ_RESET_REG(RESET2_REGISTER);
632
633 WRITE_VREG(PSCALE_RST, 0x7);
634 WRITE_VREG(PSCALE_RST, 0x0);
635}
636
637static void vmjpeg_dump_state(struct vdec_s *vdec)
638{
639 struct vdec_mjpeg_hw_s *hw =
640 (struct vdec_mjpeg_hw_s *)(vdec->private);
641 mmjpeg_debug_print(DECODE_ID(hw), 0,
642 "====== %s\n", __func__);
643 mmjpeg_debug_print(DECODE_ID(hw), 0,
644 "width/height (%d/%d)\n",
645 hw->frame_width,
646 hw->frame_height
647 );
648 mmjpeg_debug_print(DECODE_ID(hw), 0,
649 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d put_frm %d run %d not_run_ready %d input_empty %d\n",
650 input_frame_based(vdec),
651 hw->eos,
652 hw->stat,
653 hw->dec_result,
654 hw->frame_num,
655 hw->put_num,
656 hw->run_count,
657 hw->not_run_ready,
658 hw->input_empty
659 );
660 if (vf_get_receiver(vdec->vf_provider_name)) {
661 enum receviver_start_e state =
662 vf_notify_receiver(vdec->vf_provider_name,
663 VFRAME_EVENT_PROVIDER_QUREY_STATE,
664 NULL);
665 mmjpeg_debug_print(DECODE_ID(hw), 0,
666 "\nreceiver(%s) state %d\n",
667 vdec->vf_provider_name,
668 state);
669 }
670 mmjpeg_debug_print(DECODE_ID(hw), 0,
671 "%s, newq(%d/%d), dispq(%d/%d) vf peek/get/put (%d/%d/%d)\n",
672 __func__,
673 kfifo_len(&hw->newframe_q),
674 VF_POOL_SIZE,
675 kfifo_len(&hw->display_q),
676 VF_POOL_SIZE,
677 hw->peek_num,
678 hw->get_num,
679 hw->put_num
680 );
681 mmjpeg_debug_print(DECODE_ID(hw), 0,
682 "VIFF_BIT_CNT=0x%x\n",
683 READ_VREG(VIFF_BIT_CNT));
684 mmjpeg_debug_print(DECODE_ID(hw), 0,
685 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
686 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
687 mmjpeg_debug_print(DECODE_ID(hw), 0,
688 "VLD_MEM_VIFIFO_WP=0x%x\n",
689 READ_VREG(VLD_MEM_VIFIFO_WP));
690 mmjpeg_debug_print(DECODE_ID(hw), 0,
691 "VLD_MEM_VIFIFO_RP=0x%x\n",
692 READ_VREG(VLD_MEM_VIFIFO_RP));
693 mmjpeg_debug_print(DECODE_ID(hw), 0,
694 "PARSER_VIDEO_RP=0x%x\n",
695 READ_PARSER_REG(PARSER_VIDEO_RP));
696 mmjpeg_debug_print(DECODE_ID(hw), 0,
697 "PARSER_VIDEO_WP=0x%x\n",
698 READ_PARSER_REG(PARSER_VIDEO_WP));
699 if (input_frame_based(vdec) &&
700 debug_enable & PRINT_FRAMEBASE_DATA
701 ) {
702 int jj;
703 if (hw->chunk && hw->chunk->block &&
704 hw->chunk->size > 0) {
705 u8 *data = NULL;
706
707 if (!hw->chunk->block->is_mapped)
708 data = codec_mm_vmap(hw->chunk->block->start +
709 hw->chunk->offset, hw->chunk->size);
710 else
711 data = ((u8 *)hw->chunk->block->start_virt) +
712 hw->chunk->offset;
713
714 mmjpeg_debug_print(DECODE_ID(hw), 0,
715 "frame data size 0x%x\n",
716 hw->chunk->size);
717 for (jj = 0; jj < hw->chunk->size; jj++) {
718 if ((jj & 0xf) == 0)
719 mmjpeg_debug_print(DECODE_ID(hw),
720 PRINT_FRAMEBASE_DATA,
721 "%06x:", jj);
722 mmjpeg_debug_print(DECODE_ID(hw),
723 PRINT_FRAMEBASE_DATA,
724 "%02x ", data[jj]);
725 if (((jj + 1) & 0xf) == 0)
726 mmjpeg_debug_print(DECODE_ID(hw),
727 PRINT_FRAMEBASE_DATA,
728 "\n");
729 }
730
731 if (!hw->chunk->block->is_mapped)
732 codec_mm_unmap_phyaddr(data);
733 }
734 }
735}
736static void reset_process_time(struct vdec_mjpeg_hw_s *hw)
737{
738 if (hw->start_process_time) {
739 unsigned process_time =
740 1000 * (jiffies - hw->start_process_time) / HZ;
741 hw->start_process_time = 0;
742 if (process_time > max_process_time[DECODE_ID(hw)])
743 max_process_time[DECODE_ID(hw)] = process_time;
744 }
745}
746
747static void start_process_time(struct vdec_mjpeg_hw_s *hw)
748{
749 hw->decode_timeout_count = 2;
750 hw->start_process_time = jiffies;
751}
752
753static void timeout_process(struct vdec_mjpeg_hw_s *hw)
754{
755 amvdec_stop();
756 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
757 "%s decoder timeout\n", __func__);
758 hw->dec_result = DEC_RESULT_DONE;
759 reset_process_time(hw);
760 vdec_schedule_work(&hw->work);
761}
762
763static void check_timer_func(unsigned long arg)
764{
765 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)arg;
766 struct vdec_s *vdec = hw_to_vdec(hw);
767 int timeout_val = decode_timeout_val;
768
769 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
770 "%s: status:nstatus=%d:%d\n",
771 __func__, vdec->status, vdec->next_status);
772 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
773 "%s: %d,buftl=%x:%x:%x:%x\n",
774 __func__, __LINE__,
775 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
776 READ_PARSER_REG(PARSER_VIDEO_WP),
777 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
778 READ_VREG(VLD_MEM_VIFIFO_WP));
779
780 if (radr != 0) {
781 if (rval != 0) {
782 WRITE_VREG(radr, rval);
783 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
784 } else
785 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
786 rval = 0;
787 radr = 0;
788 }
789
790 if (((debug_enable & PRINT_FLAG_TIMEOUT_STATUS) == 0) &&
791 (input_frame_based(vdec) ||
792 ((u32)READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x100)) &&
793 (timeout_val > 0) &&
794 (hw->start_process_time > 0) &&
795 ((1000 * (jiffies - hw->start_process_time) / HZ)
796 > timeout_val)) {
797 if (hw->last_vld_level == READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
798 if (hw->decode_timeout_count > 0)
799 hw->decode_timeout_count--;
800 if (hw->decode_timeout_count == 0)
801 timeout_process(hw);
802 }
803 hw->last_vld_level = READ_VREG(VLD_MEM_VIFIFO_LEVEL);
804 }
805
806 if (READ_VREG(DEC_STATUS_REG) == DEC_DECODE_TIMEOUT) {
807 pr_info("ucode DEC_DECODE_TIMEOUT\n");
808 if (hw->decode_timeout_count > 0)
809 hw->decode_timeout_count--;
810 if (hw->decode_timeout_count == 0)
811 timeout_process(hw);
812 WRITE_VREG(DEC_STATUS_REG, 0);
813 }
814
815 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
816 hw->dec_result = DEC_RESULT_FORCE_EXIT;
817 vdec_schedule_work(&hw->work);
818 pr_info("vdec requested to be disconnected\n");
819 return;
820 }
821 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
822}
823
824static int vmjpeg_v4l_alloc_buff_config_canvas(struct vdec_mjpeg_hw_s *hw, int i)
825{
826 int ret;
827 u32 canvas;
828 ulong decbuf_start = 0, addr;
829 int decbuf_y_size = 0, decbuf_uv_size = 0;
830 u32 canvas_width = 0, canvas_height = 0;
831 struct vdec_s *vdec = hw_to_vdec(hw);
832 struct vdec_v4l2_buffer *fb = NULL;
833
834 if (hw->buffer_spec[i].v4l_ref_buf_addr)
835 return 0;
836
837 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
838 if (ret < 0) {
839 mmjpeg_debug_print(DECODE_ID(hw), 0,
840 "[%d] get fb fail.\n",
841 ((struct aml_vcodec_ctx *)
842 (hw->v4l2_ctx))->id);
843 return ret;
844 }
845
846 hw->buffer_spec[i].v4l_ref_buf_addr = (ulong)fb;
847 if (fb->num_planes == 1) {
848 decbuf_start = fb->m.mem[0].addr;
849 decbuf_y_size = fb->m.mem[0].offset;
850 decbuf_uv_size = fb->m.mem[0].size - fb->m.mem[0].offset;
851 canvas_width = ALIGN(hw->frame_width, 16);
852 canvas_height = ALIGN(hw->frame_height, 16);
853 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
854 } else if (fb->num_planes == 2) {
855 decbuf_start = fb->m.mem[0].addr;
856 decbuf_y_size = fb->m.mem[0].size;
857 decbuf_uv_size = fb->m.mem[1].size << 1;
858 canvas_width = ALIGN(hw->frame_width, 16);
859 canvas_height = ALIGN(hw->frame_height, 16);
860 fb->m.mem[0].bytes_used = decbuf_y_size;
861 fb->m.mem[1].bytes_used = decbuf_uv_size >> 1;
862 }
863
864 hw->buffer_spec[i].buf_adr = decbuf_start;
865 addr = hw->buffer_spec[i].buf_adr;
866 hw->buffer_spec[i].y_addr = addr;
867 addr += decbuf_y_size;
868 hw->buffer_spec[i].u_addr = addr;
869 addr += decbuf_uv_size;
870 hw->buffer_spec[i].v_addr = addr;
871
872 mmjpeg_debug_print(DECODE_ID(hw), 0, "[%d] %s(), v4l ref buf addr: 0x%x\n",
873 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id, __func__, fb);
874
875 if (vdec->parallel_dec == 1) {
876 if (hw->buffer_spec[i].y_canvas_index == -1)
877 hw->buffer_spec[i].y_canvas_index =
878 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
879 if (hw->buffer_spec[i].u_canvas_index == -1)
880 hw->buffer_spec[i].u_canvas_index =
881 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
882 if (hw->buffer_spec[i].v_canvas_index == -1)
883 hw->buffer_spec[i].v_canvas_index =
884 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
885 } else {
886 canvas = vdec->get_canvas(i, 3);
887 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
888 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
889 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
890 }
891
892 canvas_config(hw->buffer_spec[i].y_canvas_index,
893 hw->buffer_spec[i].y_addr,
894 canvas_width,
895 canvas_height,
896 CANVAS_ADDR_NOWRAP,
897 CANVAS_BLKMODE_LINEAR);
898 hw->buffer_spec[i].canvas_config[0].phy_addr =
899 hw->buffer_spec[i].y_addr;
900 hw->buffer_spec[i].canvas_config[0].width =
901 canvas_width;
902 hw->buffer_spec[i].canvas_config[0].height =
903 canvas_height;
904 hw->buffer_spec[i].canvas_config[0].block_mode =
905 CANVAS_BLKMODE_LINEAR;
906
907 canvas_config(hw->buffer_spec[i].u_canvas_index,
908 hw->buffer_spec[i].u_addr,
909 canvas_width / 2,
910 canvas_height / 2,
911 CANVAS_ADDR_NOWRAP,
912 CANVAS_BLKMODE_LINEAR);
913 hw->buffer_spec[i].canvas_config[1].phy_addr =
914 hw->buffer_spec[i].u_addr;
915 hw->buffer_spec[i].canvas_config[1].width =
916 canvas_width / 2;
917 hw->buffer_spec[i].canvas_config[1].height =
918 canvas_height / 2;
919 hw->buffer_spec[i].canvas_config[1].block_mode =
920 CANVAS_BLKMODE_LINEAR;
921
922 canvas_config(hw->buffer_spec[i].v_canvas_index,
923 hw->buffer_spec[i].v_addr,
924 canvas_width / 2,
925 canvas_height / 2,
926 CANVAS_ADDR_NOWRAP,
927 CANVAS_BLKMODE_LINEAR);
928 hw->buffer_spec[i].canvas_config[2].phy_addr =
929 hw->buffer_spec[i].v_addr;
930 hw->buffer_spec[i].canvas_config[2].width =
931 canvas_width / 2;
932 hw->buffer_spec[i].canvas_config[2].height =
933 canvas_height / 2;
934 hw->buffer_spec[i].canvas_config[2].block_mode =
935 CANVAS_BLKMODE_LINEAR;
936
937 return 0;
938}
939
940static bool is_enough_free_buffer(struct vdec_mjpeg_hw_s *hw)
941{
942 int i;
943
944 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
945 if (hw->vfbuf_use[i] == 0)
946 break;
947 }
948
949 return i == DECODE_BUFFER_NUM_MAX ? false : true;
950}
951
952static int find_free_buffer(struct vdec_mjpeg_hw_s *hw)
953{
954 int i;
955
956 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
957 if (hw->vfbuf_use[i] == 0)
958 break;
959 }
960
961 if (i == DECODE_BUFFER_NUM_MAX)
962 return -1;
963
964 if (hw->is_used_v4l)
965 if (vmjpeg_v4l_alloc_buff_config_canvas(hw, i))
966 return -1;
967
968 return i;
969}
970
971static int vmjpeg_hw_ctx_restore(struct vdec_mjpeg_hw_s *hw)
972{
973 struct buffer_spec_s *buff_spec;
974 u32 index, i;
975
976 index = find_free_buffer(hw);
977 if (index < 0)
978 return -1;
979
980 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6));
981 WRITE_VREG(DOS_SW_RESET0, 0);
982
983 if (!hw->init_flag) {
984 vmjpeg_canvas_init(hw);
985 } else {
986 if (!hw->is_used_v4l) {
987 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
988 buff_spec = &hw->buffer_spec[i];
989 canvas_config_config(buff_spec->y_canvas_index,
990 &buff_spec->canvas_config[0]);
991 canvas_config_config(buff_spec->u_canvas_index,
992 &buff_spec->canvas_config[1]);
993 canvas_config_config(buff_spec->v_canvas_index,
994 &buff_spec->canvas_config[2]);
995 }
996 }
997 }
998
999 /* find next decode buffer index */
1000 WRITE_VREG(AV_SCRATCH_4, spec2canvas(&hw->buffer_spec[index]));
1001 WRITE_VREG(AV_SCRATCH_5, index);
1002
1003 init_scaler();
1004
1005 /* clear buffer IN/OUT registers */
1006 WRITE_VREG(MREG_TO_AMRISC, 0);
1007 WRITE_VREG(MREG_FROM_AMRISC, 0);
1008
1009 WRITE_VREG(MCPU_INTR_MSK, 0xffff);
1010 WRITE_VREG(MREG_DECODE_PARAM, (hw->frame_height << 4) | 0x8000);
1011
1012 /* clear mailbox interrupt */
1013 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1014 /* enable mailbox interrupt */
1015 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1016 /* set interrupt mapping for vld */
1017 WRITE_VREG(ASSIST_AMR1_INT8, 8);
1018#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
1019 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1020#endif
1021 return 0;
1022}
1023
1024static s32 vmjpeg_init(struct vdec_s *vdec)
1025{
1026 int i;
1027 int size = -1, fw_size = 0x1000 * 16;
1028 struct firmware_s *fw = NULL;
1029 struct vdec_mjpeg_hw_s *hw =
1030 (struct vdec_mjpeg_hw_s *)vdec->private;
1031
1032 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
1033 if (IS_ERR_OR_NULL(fw))
1034 return -ENOMEM;
1035
1036 size = get_firmware_data(VIDEO_DEC_MJPEG_MULTI, fw->data);
1037 if (size < 0) {
1038 pr_err("get firmware fail.");
1039 vfree(fw);
1040 return -1;
1041 }
1042
1043 fw->len = size;
1044 hw->fw = fw;
1045
1046 hw->frame_width = hw->vmjpeg_amstream_dec_info.width;
1047 hw->frame_height = hw->vmjpeg_amstream_dec_info.height;
1048 hw->frame_dur = ((hw->vmjpeg_amstream_dec_info.rate) ?
1049 hw->vmjpeg_amstream_dec_info.rate : 3840);
1050 hw->saved_resolution = 0;
1051 hw->eos = 0;
1052 hw->init_flag = 0;
1053 hw->frame_num = 0;
1054 hw->put_num = 0;
1055 hw->run_count = 0;
1056 hw->not_run_ready = 0;
1057 hw->input_empty = 0;
1058 hw->peek_num = 0;
1059 hw->get_num = 0;
1060 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++)
1061 hw->vfbuf_use[i] = 0;
1062
1063 INIT_KFIFO(hw->display_q);
1064 INIT_KFIFO(hw->newframe_q);
1065
1066 for (i = 0; i < VF_POOL_SIZE; i++) {
1067 const struct vframe_s *vf = &hw->vfpool[i];
1068
1069 hw->vfpool[i].index = -1;
1070 kfifo_put(&hw->newframe_q, vf);
1071 }
1072
1073 if (hw->mm_blk_handle) {
1074 decoder_bmmu_box_free(hw->mm_blk_handle);
1075 hw->mm_blk_handle = NULL;
1076 }
1077
1078 hw->mm_blk_handle = decoder_bmmu_box_alloc_box(
1079 DRIVER_NAME,
1080 0,
1081 MAX_BMMU_BUFFER_NUM,
1082 4 + PAGE_SHIFT,
1083 CODEC_MM_FLAGS_CMA_CLEAR |
1084 CODEC_MM_FLAGS_FOR_VDECODER);
1085
1086 init_timer(&hw->check_timer);
1087
1088 hw->check_timer.data = (unsigned long)hw;
1089 hw->check_timer.function = check_timer_func;
1090 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
1091 /*add_timer(&hw->check_timer);*/
1092 hw->stat |= STAT_TIMER_ARM;
1093 hw->stat |= STAT_ISR_REG;
1094
1095 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
1096 INIT_WORK(&hw->work, vmjpeg_work);
1097 pr_info("w:h=%d:%d\n", hw->frame_width, hw->frame_height);
1098 return 0;
1099}
1100
1101static unsigned long run_ready(struct vdec_s *vdec,
1102 unsigned long mask)
1103{
1104 struct vdec_mjpeg_hw_s *hw =
1105 (struct vdec_mjpeg_hw_s *)vdec->private;
1106 hw->not_run_ready++;
1107 if (hw->eos)
1108 return 0;
1109 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
1110 && pre_decode_buf_level != 0) {
1111 u32 rp, wp, level;
1112
1113 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
1114 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
1115 if (wp < rp)
1116 level = vdec->input.size + wp - rp;
1117 else
1118 level = wp - rp;
1119
1120 if (level < pre_decode_buf_level)
1121 return 0;
1122 }
1123
1124 if (!is_enough_free_buffer(hw)) {
1125 hw->buffer_not_ready++;
1126 return 0;
1127 }
1128
1129 hw->not_run_ready = 0;
1130 hw->buffer_not_ready = 0;
1131 if (vdec->parallel_dec == 1)
1132 return CORE_MASK_VDEC_1;
1133 else
1134 return CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
1135}
1136
1137static void run(struct vdec_s *vdec, unsigned long mask,
1138 void (*callback)(struct vdec_s *, void *), void *arg)
1139{
1140 struct vdec_mjpeg_hw_s *hw =
1141 (struct vdec_mjpeg_hw_s *)vdec->private;
1142 int i, ret;
1143
1144 hw->vdec_cb_arg = arg;
1145 hw->vdec_cb = callback;
1146
1147 hw->run_count++;
1148 vdec_reset_core(vdec);
1149 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1150 if (hw->vfbuf_use[i] == 0)
1151 break;
1152 }
1153
1154 if (i == DECODE_BUFFER_NUM_MAX) {
1155 hw->dec_result = DEC_RESULT_AGAIN;
1156 vdec_schedule_work(&hw->work);
1157 return;
1158 }
1159
1160 ret = vdec_prepare_input(vdec, &hw->chunk);
1161 if (ret <= 0) {
1162 hw->input_empty++;
1163 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1164 "%s: %d,r=%d,buftl=%x:%x:%x\n",
1165 __func__, __LINE__, ret,
1166 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1167 READ_PARSER_REG(PARSER_VIDEO_WP),
1168 READ_VREG(VLD_MEM_VIFIFO_WP));
1169
1170 hw->dec_result = DEC_RESULT_AGAIN;
1171 vdec_schedule_work(&hw->work);
1172 return;
1173 }
1174 hw->input_empty = 0;
1175 hw->dec_result = DEC_RESULT_NONE;
1176 if (vdec->mc_loaded) {
1177 /*firmware have load before,
1178 and not changes to another.
1179 ignore reload.
1180 */
1181 } else {
1182 ret = amvdec_vdec_loadmc_ex(VFORMAT_MJPEG, "mmjpeg", vdec, hw->fw->data);
1183 if (ret < 0) {
1184 pr_err("[%d] MMJPEG: the %s fw loading failed, err: %x\n",
1185 vdec->id, tee_enabled() ? "TEE" : "local", ret);
1186 hw->dec_result = DEC_RESULT_FORCE_EXIT;
1187 vdec_schedule_work(&hw->work);
1188 return;
1189 }
1190 vdec->mc_loaded = 1;
1191 vdec->mc_type = VFORMAT_MJPEG;
1192 }
1193/* if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) {
1194 pr_err("%s: Error amvdec_loadmc fail\n", __func__);
1195 return;
1196 }*/
1197
1198 if (vmjpeg_hw_ctx_restore(hw) < 0) {
1199 hw->dec_result = DEC_RESULT_ERROR;
1200 mmjpeg_debug_print(DECODE_ID(hw), 0,
1201 "amvdec_mmjpeg: error HW context restore\n");
1202 vdec_schedule_work(&hw->work);
1203 return;
1204 }
1205#if 0
1206 vdec_enable_input(vdec);
1207 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1208#endif
1209 hw->stat |= STAT_MC_LOAD;
1210 start_process_time(hw);
1211 hw->last_vld_level = 0;
1212 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1213 amvdec_start();
1214 vdec_enable_input(vdec);
1215 hw->stat |= STAT_VDEC_RUN;
1216 hw->init_flag = 1;
1217
1218 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1219 "%s (0x%x 0x%x 0x%x) vldcrl 0x%x bitcnt 0x%x powerctl 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1220 __func__,
1221 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
1222 READ_VREG(VLD_MEM_VIFIFO_WP),
1223 READ_VREG(VLD_MEM_VIFIFO_RP),
1224 READ_VREG(VLD_DECODE_CONTROL),
1225 READ_VREG(VIFF_BIT_CNT),
1226 READ_VREG(POWER_CTL_VLD),
1227 READ_VREG(VLD_MEM_VIFIFO_START_PTR),
1228 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR),
1229 READ_VREG(VLD_MEM_VIFIFO_CONTROL),
1230 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1231 READ_VREG(VLD_MEM_VIFIFO_END_PTR));
1232}
1233static void wait_vmjpeg_search_done(struct vdec_mjpeg_hw_s *hw)
1234{
1235 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1236 int count = 0;
1237
1238 do {
1239 usleep_range(100, 500);
1240 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
1241 break;
1242 if (count > 1000) {
1243 mmjpeg_debug_print(DECODE_ID(hw), 0,
1244 "%s, count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
1245 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
1246 break;
1247 } else
1248 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1249 count++;
1250 } while (1);
1251}
1252
1253static int notify_v4l_eos(struct vdec_s *vdec)
1254{
1255 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
1256 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1257 struct vframe_s *vf = NULL;
1258 struct vdec_v4l2_buffer *fb = NULL;
1259
1260 if (hw->is_used_v4l && hw->eos) {
1261 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
1262 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1263 "%s fatal error, no available buffer slot.\n",
1264 __func__);
1265 return -1;
1266 }
1267
1268 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
1269 pr_err("[%d] get fb fail.\n", ctx->id);
1270 return -1;
1271 }
1272
1273 vf->timestamp = ULONG_MAX;
1274 vf->v4l_mem_handle = (unsigned long)fb;
1275 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
1276
1277 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
1278 vf_notify_receiver(vdec->vf_provider_name,
1279 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
1280
1281 pr_info("[%d] mpeg12 EOS notify.\n", ctx->id);
1282 }
1283
1284 return 0;
1285}
1286
1287static void vmjpeg_work(struct work_struct *work)
1288{
1289 struct vdec_mjpeg_hw_s *hw = container_of(work,
1290 struct vdec_mjpeg_hw_s, work);
1291 struct vdec_s *vdec = hw_to_vdec(hw);
1292
1293 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_BUFFER_DETAIL,
1294 "%s: result=%d,len=%d:%d\n",
1295 __func__, hw->dec_result,
1296 kfifo_len(&hw->newframe_q),
1297 kfifo_len(&hw->display_q));
1298 if (hw->dec_result == DEC_RESULT_DONE) {
1299 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1300 hw->chunk = NULL;
1301 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
1302 /*
1303 stream base: stream buf empty or timeout
1304 frame base: vdec_prepare_input fail
1305 */
1306 if (!vdec_has_more_input(hw_to_vdec(hw))) {
1307 hw->dec_result = DEC_RESULT_EOS;
1308 vdec_schedule_work(&hw->work);
1309 /*pr_info("%s: return\n",
1310 __func__);*/
1311 return;
1312 }
1313 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
1314 pr_info("%s: force exit\n", __func__);
1315 if (hw->stat & STAT_ISR_REG) {
1316 amvdec_stop();
1317 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1318 hw->stat &= ~STAT_ISR_REG;
1319 }
1320 } else if (hw->dec_result == DEC_RESULT_EOS) {
1321 pr_info("%s: end of stream\n", __func__);
1322 if (hw->stat & STAT_VDEC_RUN) {
1323 amvdec_stop();
1324 hw->stat &= ~STAT_VDEC_RUN;
1325 }
1326 hw->eos = 1;
1327 if (hw->is_used_v4l)
1328 notify_v4l_eos(vdec);
1329
1330 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1331 hw->chunk = NULL;
1332 vdec_clean_input(hw_to_vdec(hw));
1333 }
1334 if (hw->stat & STAT_VDEC_RUN) {
1335 amvdec_stop();
1336 hw->stat &= ~STAT_VDEC_RUN;
1337 }
1338 /*disable mbox interrupt */
1339 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
1340 wait_vmjpeg_search_done(hw);
1341 /* mark itself has all HW resource released and input released */
1342 if (vdec->parallel_dec == 1)
1343 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1344 else {
1345 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
1346 | CORE_MASK_HEVC);
1347 }
1348 del_timer_sync(&hw->check_timer);
1349 hw->stat &= ~STAT_TIMER_ARM;
1350
1351 if (hw->vdec_cb)
1352 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
1353}
1354
1355static int vmjpeg_stop(struct vdec_mjpeg_hw_s *hw)
1356{
1357 pr_info("%s ...count = %d\n", __func__, hw->frame_num);
1358
1359 if (hw->stat & STAT_VDEC_RUN) {
1360 amvdec_stop();
1361 pr_info("%s amvdec_stop\n", __func__);
1362 hw->stat &= ~STAT_VDEC_RUN;
1363 }
1364
1365 if (hw->stat & STAT_ISR_REG) {
1366 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1367 hw->stat &= ~STAT_ISR_REG;
1368 }
1369
1370 if (hw->stat & STAT_TIMER_ARM) {
1371 del_timer_sync(&hw->check_timer);
1372 hw->stat &= ~STAT_TIMER_ARM;
1373 }
1374 cancel_work_sync(&hw->work);
1375 hw->init_flag = 0;
1376
1377 if (hw->mm_blk_handle) {
1378 decoder_bmmu_box_free(hw->mm_blk_handle);
1379 hw->mm_blk_handle = NULL;
1380 }
1381
1382 if (hw->fw) {
1383 vfree(hw->fw);
1384 hw->fw = NULL;
1385 }
1386
1387 return 0;
1388}
1389
1390static int ammvdec_mjpeg_probe(struct platform_device *pdev)
1391{
1392 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
1393 struct vdec_mjpeg_hw_s *hw = NULL;
1394
1395 if (pdata == NULL) {
1396 pr_info("ammvdec_mjpeg memory resource undefined.\n");
1397 return -EFAULT;
1398 }
1399
1400 hw = vzalloc(sizeof(struct vdec_mjpeg_hw_s));
1401 if (hw == NULL) {
1402 pr_info("\nammvdec_mjpeg device data allocation failed\n");
1403 return -ENOMEM;
1404 }
1405
1406 /* the ctx from v4l2 driver. */
1407 hw->v4l2_ctx = pdata->private;
1408
1409 pdata->private = hw;
1410 pdata->dec_status = vmjpeg_dec_status;
1411
1412 pdata->run = run;
1413 pdata->run_ready = run_ready;
1414 pdata->irq_handler = vmjpeg_isr;
1415 pdata->dump_state = vmjpeg_dump_state;
1416
1417 if (pdata->parallel_dec == 1) {
1418 int i;
1419 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1420 hw->buffer_spec[i].y_canvas_index = -1;
1421 hw->buffer_spec[i].u_canvas_index = -1;
1422 hw->buffer_spec[i].v_canvas_index = -1;
1423 }
1424 }
1425
1426 if (pdata->use_vfm_path)
1427 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1428 VFM_DEC_PROVIDER_NAME);
1429 else
1430 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1431 PROVIDER_NAME ".%02x", pdev->id & 0xff);
1432
1433 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
1434 &vf_provider_ops, pdata);
1435
1436 platform_set_drvdata(pdev, pdata);
1437
1438 hw->platform_dev = pdev;
1439
1440 if (pdata->sys_info) {
1441 hw->vmjpeg_amstream_dec_info = *pdata->sys_info;
1442 hw->is_used_v4l = (((unsigned long)
1443 hw->vmjpeg_amstream_dec_info.param & 0x80) >> 7);
1444 }
1445
1446 vdec_source_changed(VFORMAT_MJPEG,
1447 1920, 1080, 60);
1448 if (vmjpeg_init(pdata) < 0) {
1449 pr_info("ammvdec_mjpeg init failed.\n");
1450 if (hw) {
1451 vfree(hw);
1452 hw = NULL;
1453 }
1454 pdata->dec_status = NULL;
1455 return -ENODEV;
1456 }
1457 vdec_set_prepare_level(pdata, start_decode_buf_level);
1458
1459 if (pdata->parallel_dec == 1)
1460 vdec_core_request(pdata, CORE_MASK_VDEC_1);
1461 else {
1462 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
1463 | CORE_MASK_COMBINE);
1464 }
1465
1466 return 0;
1467}
1468
1469static int ammvdec_mjpeg_remove(struct platform_device *pdev)
1470{
1471 struct vdec_mjpeg_hw_s *hw =
1472 (struct vdec_mjpeg_hw_s *)
1473 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
1474 struct vdec_s *vdec = hw_to_vdec(hw);
1475 int i;
1476
1477 vmjpeg_stop(hw);
1478
1479 if (vdec->parallel_dec == 1)
1480 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1481 else
1482 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
1483 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
1484 if (vdec->parallel_dec == 1) {
1485 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1486 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
1487 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
1488 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
1489 }
1490 }
1491 if (hw) {
1492 vfree(hw);
1493 hw = NULL;
1494 }
1495 pr_info("%s\n", __func__);
1496 return 0;
1497}
1498
1499/****************************************/
1500#ifdef CONFIG_PM
1501static int mmjpeg_suspend(struct device *dev)
1502{
1503 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
1504 return 0;
1505}
1506
1507static int mmjpeg_resume(struct device *dev)
1508{
1509 amvdec_resume(to_platform_device(dev));
1510 return 0;
1511}
1512
1513static const struct dev_pm_ops mmjpeg_pm_ops = {
1514 SET_SYSTEM_SLEEP_PM_OPS(mmjpeg_suspend, mmjpeg_resume)
1515};
1516#endif
1517
1518static struct platform_driver ammvdec_mjpeg_driver = {
1519 .probe = ammvdec_mjpeg_probe,
1520 .remove = ammvdec_mjpeg_remove,
1521 .driver = {
1522 .name = DRIVER_NAME,
1523#ifdef CONFIG_PM
1524 .pm = &mmjpeg_pm_ops,
1525#endif
1526 }
1527};
1528
1529static struct codec_profile_t ammvdec_mjpeg_profile = {
1530 .name = "mmjpeg",
1531 .profile = ""
1532};
1533
1534static int __init ammvdec_mjpeg_driver_init_module(void)
1535{
1536 if (platform_driver_register(&ammvdec_mjpeg_driver)) {
1537 pr_err("failed to register ammvdec_mjpeg driver\n");
1538 return -ENODEV;
1539 }
1540 vcodec_profile_register(&ammvdec_mjpeg_profile);
1541 return 0;
1542}
1543
1544static void __exit ammvdec_mjpeg_driver_remove_module(void)
1545{
1546 platform_driver_unregister(&ammvdec_mjpeg_driver);
1547}
1548
1549/****************************************/
1550module_param(debug_enable, uint, 0664);
1551MODULE_PARM_DESC(debug_enable, "\n debug enable\n");
1552module_param(pre_decode_buf_level, int, 0664);
1553MODULE_PARM_DESC(pre_decode_buf_level,
1554 "\n ammvdec_h264 pre_decode_buf_level\n");
1555module_param(udebug_flag, uint, 0664);
1556MODULE_PARM_DESC(udebug_flag, "\n amvdec_mmpeg12 udebug_flag\n");
1557
1558
1559module_param(decode_timeout_val, uint, 0664);
1560MODULE_PARM_DESC(decode_timeout_val, "\n ammvdec_mjpeg decode_timeout_val\n");
1561
1562module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
1563
1564module_param(radr, uint, 0664);
1565MODULE_PARM_DESC(radr, "\nradr\n");
1566
1567module_param(start_decode_buf_level, uint, 0664);
1568MODULE_PARM_DESC(start_decode_buf_level, "\nstart_decode_buf_level\n");
1569
1570module_param(rval, uint, 0664);
1571MODULE_PARM_DESC(rval, "\nrval\n");
1572
1573module_param(without_display_mode, uint, 0664);
1574MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
1575
1576module_init(ammvdec_mjpeg_driver_init_module);
1577module_exit(ammvdec_mjpeg_driver_remove_module);
1578
1579MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver");
1580MODULE_LICENSE("GPL");
1581MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
1582
generated by cgit at 2024-05-17 08:36:52 (GMT)