summaryrefslogtreecommitdiff
path: root/drivers/frame_provider/decoder/mjpeg/vmjpeg_multi.c (plain)
blob: 5ec38245e9cc9994dcc58c07cc066f67fe6c11dd
1/*
2 * drivers/amlogic/amports/vmjpeg.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/timer.h>
23#include <linux/kfifo.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/amlogic/media/frame_sync/ptsserv.h>
27#include <linux/amlogic/media/utils/amstream.h>
28#include <linux/amlogic/media/canvas/canvas.h>
29#include <linux/amlogic/media/vfm/vframe.h>
30#include <linux/amlogic/media/vfm/vframe_provider.h>
31#include <linux/amlogic/media/vfm/vframe_receiver.h>
32#include <linux/amlogic/tee.h>
33
34#include <linux/amlogic/media/utils/vdec_reg.h>
35#include <linux/amlogic/media/registers/register.h>
36#include "../../../stream_input/amports/amports_priv.h"
37
38#include "../utils/vdec_input.h"
39#include "../utils/vdec.h"
40#include "../utils/amvdec.h"
41#include "../utils/decoder_mmu_box.h"
42#include "../utils/decoder_bmmu_box.h"
43#include <linux/amlogic/media/codec_mm/codec_mm.h>
44#include <linux/amlogic/media/codec_mm/configs.h>
45#include "../utils/firmware.h"
46#include "../utils/vdec_v4l2_buffer_ops.h"
47
48#define MEM_NAME "codec_mmjpeg"
49
50#define DRIVER_NAME "ammvdec_mjpeg"
51#define MODULE_NAME "ammvdec_mjpeg"
52#define CHECK_INTERVAL (HZ/100)
53
54/* protocol register usage
55 * AV_SCRATCH_4 : decode buffer spec
56 * AV_SCRATCH_5 : decode buffer index
57 */
58
59#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */
60/* bit 15-4: reference height */
61#define MREG_TO_AMRISC AV_SCRATCH_8
62#define MREG_FROM_AMRISC AV_SCRATCH_9
63#define MREG_FRAME_OFFSET AV_SCRATCH_A
64#define DEC_STATUS_REG AV_SCRATCH_F
65#define MREG_PIC_WIDTH AV_SCRATCH_B
66#define MREG_PIC_HEIGHT AV_SCRATCH_C
67#define DECODE_STOP_POS AV_SCRATCH_K
68
69#define PICINFO_BUF_IDX_MASK 0x0007
70#define PICINFO_AVI1 0x0080
71#define PICINFO_INTERLACE 0x0020
72#define PICINFO_INTERLACE_AVI1_BOT 0x0010
73#define PICINFO_INTERLACE_FIRST 0x0010
74
75#define VF_POOL_SIZE 16
76#define DECODE_BUFFER_NUM_MAX 4
77#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX
78
79#define DEFAULT_MEM_SIZE (32*SZ_1M)
80static int debug_enable;
81static u32 udebug_flag;
82#define DECODE_ID(hw) (hw_to_vdec(hw)->id)
83
84static unsigned int radr;
85static unsigned int rval;
86#define VMJPEG_DEV_NUM 9
87static unsigned int max_decode_instance_num = VMJPEG_DEV_NUM;
88static unsigned int max_process_time[VMJPEG_DEV_NUM];
89static unsigned int decode_timeout_val = 200;
90static struct vframe_s *vmjpeg_vf_peek(void *);
91static struct vframe_s *vmjpeg_vf_get(void *);
92static void vmjpeg_vf_put(struct vframe_s *, void *);
93static int vmjpeg_vf_states(struct vframe_states *states, void *);
94static int vmjpeg_event_cb(int type, void *data, void *private_data);
95static void vmjpeg_work(struct work_struct *work);
96static int pre_decode_buf_level = 0x800;
97static u32 without_display_mode;
98#undef pr_info
99#define pr_info printk
100unsigned int mmjpeg_debug_mask = 0xff;
101#define PRINT_FLAG_ERROR 0x0
102#define PRINT_FLAG_RUN_FLOW 0X0001
103#define PRINT_FLAG_TIMEINFO 0x0002
104#define PRINT_FLAG_UCODE_DETAIL 0x0004
105#define PRINT_FLAG_VLD_DETAIL 0x0008
106#define PRINT_FLAG_DEC_DETAIL 0x0010
107#define PRINT_FLAG_BUFFER_DETAIL 0x0020
108#define PRINT_FLAG_RESTORE 0x0040
109#define PRINT_FRAME_NUM 0x0080
110#define PRINT_FLAG_FORCE_DONE 0x0100
111#define PRINT_FRAMEBASE_DATA 0x0400
112#define PRINT_FLAG_TIMEOUT_STATUS 0x1000
113#define PRINT_FLAG_V4L_DETAIL 0x8000
114
115int mmjpeg_debug_print(int index, int debug_flag, const char *fmt, ...)
116{
117 if (((debug_enable & debug_flag) &&
118 ((1 << index) & mmjpeg_debug_mask))
119 || (debug_flag == PRINT_FLAG_ERROR)) {
120 unsigned char buf[512];
121 int len = 0;
122 va_list args;
123 va_start(args, fmt);
124 len = sprintf(buf, "%d: ", index);
125 vsnprintf(buf + len, 512-len, fmt, args);
126 pr_info("%s", buf);
127 va_end(args);
128 }
129 return 0;
130}
131
132static const char vmjpeg_dec_id[] = "vmmjpeg-dev";
133
134#define PROVIDER_NAME "vdec.mjpeg"
135static const struct vframe_operations_s vf_provider_ops = {
136 .peek = vmjpeg_vf_peek,
137 .get = vmjpeg_vf_get,
138 .put = vmjpeg_vf_put,
139 .event_cb = vmjpeg_event_cb,
140 .vf_states = vmjpeg_vf_states,
141};
142
143#define DEC_RESULT_NONE 0
144#define DEC_RESULT_DONE 1
145#define DEC_RESULT_AGAIN 2
146#define DEC_RESULT_ERROR 3
147#define DEC_RESULT_FORCE_EXIT 4
148#define DEC_RESULT_EOS 5
149#define DEC_DECODE_TIMEOUT 0x21
150
151
152struct buffer_spec_s {
153 unsigned int y_addr;
154 unsigned int u_addr;
155 unsigned int v_addr;
156
157 int y_canvas_index;
158 int u_canvas_index;
159 int v_canvas_index;
160
161 struct canvas_config_s canvas_config[3];
162 unsigned long cma_alloc_addr;
163 int cma_alloc_count;
164 unsigned int buf_adr;
165 ulong v4l_ref_buf_addr;
166};
167
168#define spec2canvas(x) \
169 (((x)->v_canvas_index << 16) | \
170 ((x)->u_canvas_index << 8) | \
171 ((x)->y_canvas_index << 0))
172
173struct vdec_mjpeg_hw_s {
174 spinlock_t lock;
175 struct mutex vmjpeg_mutex;
176
177 struct platform_device *platform_dev;
178 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
179 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
180
181 struct vframe_s vfpool[VF_POOL_SIZE];
182 struct buffer_spec_s buffer_spec[DECODE_BUFFER_NUM_MAX];
183 s32 vfbuf_use[DECODE_BUFFER_NUM_MAX];
184
185 u32 frame_width;
186 u32 frame_height;
187 u32 frame_dur;
188 u32 saved_resolution;
189 u8 init_flag;
190 u32 stat;
191 u32 dec_result;
192 unsigned long buf_start;
193 u32 buf_size;
194 void *mm_blk_handle;
195 struct dec_sysinfo vmjpeg_amstream_dec_info;
196
197 struct vframe_chunk_s *chunk;
198 struct work_struct work;
199 void (*vdec_cb)(struct vdec_s *, void *);
200 void *vdec_cb_arg;
201 struct firmware_s *fw;
202 struct timer_list check_timer;
203 u32 decode_timeout_count;
204 unsigned long int start_process_time;
205 u32 last_vld_level;
206 u8 eos;
207 u32 frame_num;
208 u32 put_num;
209 u32 run_count;
210 u32 not_run_ready;
211 u32 buffer_not_ready;
212 u32 input_empty;
213 u32 peek_num;
214 u32 get_num;
215 bool is_used_v4l;
216 void *v4l2_ctx;
217 bool v4l_params_parsed;
218};
219
220static void reset_process_time(struct vdec_mjpeg_hw_s *hw);
221static void set_frame_info(struct vdec_mjpeg_hw_s *hw, struct vframe_s *vf)
222{
223 u32 temp;
224 temp = READ_VREG(MREG_PIC_WIDTH);
225 if (temp > 1920)
226 vf->width = hw->frame_width = 1920;
227 else if (temp > 0)
228 vf->width = hw->frame_width = temp;
229 temp = READ_VREG(MREG_PIC_HEIGHT);
230 if (temp > 1088)
231 vf->height = hw->frame_height = 1088;
232 else if (temp > 0)
233 vf->height = hw->frame_height = temp;
234 vf->duration = hw->frame_dur;
235 vf->ratio_control = 0;
236 vf->duration_pulldown = 0;
237 vf->flag = 0;
238
239 vf->canvas0Addr = vf->canvas1Addr = -1;
240 vf->plane_num = 3;
241
242 vf->canvas0_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
243 vf->canvas0_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
244 vf->canvas0_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
245
246 vf->canvas1_config[0] = hw->buffer_spec[vf->index].canvas_config[0];
247 vf->canvas1_config[1] = hw->buffer_spec[vf->index].canvas_config[1];
248 vf->canvas1_config[2] = hw->buffer_spec[vf->index].canvas_config[2];
249}
250
251static irqreturn_t vmjpeg_isr(struct vdec_s *vdec, int irq)
252{
253 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)(vdec->private);
254 u32 reg;
255 struct vframe_s *vf = NULL;
256 u32 index, offset = 0, pts;
257 u64 pts_us64;
258 u32 frame_size;
259
260 if (!hw)
261 return IRQ_HANDLED;
262
263 if (hw->eos)
264 return IRQ_HANDLED;
265 reset_process_time(hw);
266 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
267 if (READ_VREG(AV_SCRATCH_D) != 0 &&
268 (debug_enable & PRINT_FLAG_UCODE_DETAIL)) {
269 pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_D),
270 READ_VREG(AV_SCRATCH_E));
271 WRITE_VREG(AV_SCRATCH_D, 0);
272 return IRQ_HANDLED;
273 }
274
275 reg = READ_VREG(MREG_FROM_AMRISC);
276 index = READ_VREG(AV_SCRATCH_5);
277
278 if (index >= DECODE_BUFFER_NUM_MAX) {
279 pr_err("fatal error, invalid buffer index.");
280 return IRQ_HANDLED;
281 }
282
283 if (kfifo_get(&hw->newframe_q, &vf) == 0) {
284 pr_info(
285 "fatal error, no available buffer slot.");
286 return IRQ_HANDLED;
287 }
288
289 if (hw->is_used_v4l) {
290 struct aml_vcodec_ctx *ctx =
291 (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
292
293 if (ctx->param_sets_from_ucode && !hw->v4l_params_parsed) {
294 struct aml_vdec_pic_infos info;
295
296 info.visible_width = hw->frame_width;
297 info.visible_height = hw->frame_height;
298 info.coded_width = ALIGN(hw->frame_width, 64);
299 info.coded_height = ALIGN(hw->frame_height, 64);
300 info.dpb_size = MAX_BMMU_BUFFER_NUM - 1;
301 hw->v4l_params_parsed = true;
302 vdec_v4l_set_pic_infos(ctx, &info);
303 }
304
305 if (!ctx->v4l_codec_ready)
306 return IRQ_HANDLED;
307 }
308
309 if (hw->is_used_v4l) {
310 vf->v4l_mem_handle
311 = hw->buffer_spec[index].v4l_ref_buf_addr;
312 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_V4L_DETAIL,
313 "[%d] %s(), v4l mem handle: 0x%lx\n",
314 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id,
315 __func__, vf->v4l_mem_handle);
316 }
317
318 vf->index = index;
319 set_frame_info(hw, vf);
320
321 vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
322 /* vf->pts = (pts_valid) ? pts : 0; */
323 /* vf->pts_us64 = (pts_valid) ? pts_us64 : 0; */
324
325 if (hw->chunk) {
326 vf->pts = hw->chunk->pts;
327 vf->pts_us64 = hw->chunk->pts64;
328 } else {
329 offset = READ_VREG(MREG_FRAME_OFFSET);
330 if (pts_lookup_offset_us64
331 (PTS_TYPE_VIDEO, offset, &pts,
332 &frame_size, 3000,
333 &pts_us64) == 0) {
334 vf->pts = pts;
335 vf->pts_us64 = pts_us64;
336 } else {
337 vf->pts = 0;
338 vf->pts_us64 = 0;
339 }
340 }
341 vf->orientation = 0;
342 hw->vfbuf_use[index]++;
343
344 vf->mem_handle =
345 decoder_bmmu_box_get_mem_handle(
346 hw->mm_blk_handle, index);
347 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
348 ATRACE_COUNTER(MODULE_NAME, vf->pts);
349 hw->frame_num++;
350 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
351 "%s:frame num:%d,pts=%d,pts64=%lld. dur=%d\n",
352 __func__, hw->frame_num,
353 vf->pts, vf->pts_us64, vf->duration);
354 vdec->vdec_fps_detec(vdec->id);
355 if (without_display_mode == 0) {
356 vf_notify_receiver(vdec->vf_provider_name,
357 VFRAME_EVENT_PROVIDER_VFRAME_READY,
358 NULL);
359 } else
360 vmjpeg_vf_put(vmjpeg_vf_get(vdec), vdec);
361
362 hw->dec_result = DEC_RESULT_DONE;
363
364 vdec_schedule_work(&hw->work);
365
366 return IRQ_HANDLED;
367}
368
369static struct vframe_s *vmjpeg_vf_peek(void *op_arg)
370{
371 struct vframe_s *vf;
372 struct vdec_s *vdec = op_arg;
373 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
374
375 if (!hw)
376 return NULL;
377 hw->peek_num++;
378 if (kfifo_peek(&hw->display_q, &vf))
379 return vf;
380
381 return NULL;
382}
383
384static struct vframe_s *vmjpeg_vf_get(void *op_arg)
385{
386 struct vframe_s *vf;
387 struct vdec_s *vdec = op_arg;
388 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
389
390 if (!hw)
391 return NULL;
392 hw->get_num++;
393 if (kfifo_get(&hw->display_q, &vf))
394 return vf;
395
396 return NULL;
397}
398
399static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg)
400{
401 struct vdec_s *vdec = op_arg;
402 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
403 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FRAME_NUM,
404 "%s:put_num:%d\n", __func__, hw->put_num);
405 hw->vfbuf_use[vf->index]--;
406 kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf);
407 hw->put_num++;
408}
409
410static int vmjpeg_event_cb(int type, void *data, void *private_data)
411{
412 return 0;
413}
414
415static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg)
416{
417 unsigned long flags;
418 struct vdec_s *vdec = op_arg;
419 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
420
421 spin_lock_irqsave(&hw->lock, flags);
422
423 states->vf_pool_size = VF_POOL_SIZE;
424 states->buf_free_num = kfifo_len(&hw->newframe_q);
425 states->buf_avail_num = kfifo_len(&hw->display_q);
426 states->buf_recycle_num = 0;
427
428 spin_unlock_irqrestore(&hw->lock, flags);
429
430 return 0;
431}
432
433static int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
434{
435 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
436
437 if (!hw)
438 return -1;
439
440 vstatus->frame_width = hw->frame_width;
441 vstatus->frame_height = hw->frame_height;
442 if (0 != hw->frame_dur)
443 vstatus->frame_rate = 96000 / hw->frame_dur;
444 else
445 vstatus->frame_rate = 96000;
446 vstatus->error_count = 0;
447 vstatus->status = hw->stat;
448
449 return 0;
450}
451
452/****************************************/
453static void vmjpeg_canvas_init(struct vdec_mjpeg_hw_s *hw)
454{
455 int i, ret;
456 u32 canvas_width, canvas_height;
457 u32 decbuf_size, decbuf_y_size, decbuf_uv_size;
458 unsigned long buf_start, addr;
459 struct vdec_s *vdec = hw_to_vdec(hw);
460
461 canvas_width = 1920;
462 canvas_height = 1088;
463 decbuf_y_size = 0x200000;
464 decbuf_uv_size = 0x80000;
465 decbuf_size = 0x300000;
466
467 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
468 int canvas;
469
470 if (hw->is_used_v4l) {
471 continue;
472 } else {
473 ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i,
474 decbuf_size, DRIVER_NAME, &buf_start);
475 if (ret < 0) {
476 pr_err("CMA alloc failed! size 0x%d idx %d\n",
477 decbuf_size, i);
478 return;
479 }
480 }
481
482 hw->buffer_spec[i].buf_adr = buf_start;
483 addr = hw->buffer_spec[i].buf_adr;
484
485 hw->buffer_spec[i].y_addr = addr;
486 addr += decbuf_y_size;
487 hw->buffer_spec[i].u_addr = addr;
488 addr += decbuf_uv_size;
489 hw->buffer_spec[i].v_addr = addr;
490
491 if (vdec->parallel_dec == 1) {
492 if (hw->buffer_spec[i].y_canvas_index == -1)
493 hw->buffer_spec[i].y_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
494 if (hw->buffer_spec[i].u_canvas_index == -1)
495 hw->buffer_spec[i].u_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
496 if (hw->buffer_spec[i].v_canvas_index == -1)
497 hw->buffer_spec[i].v_canvas_index = vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
498 } else {
499 canvas = vdec->get_canvas(i, 3);
500 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
501 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
502 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
503 }
504
505 canvas_config(hw->buffer_spec[i].y_canvas_index,
506 hw->buffer_spec[i].y_addr,
507 canvas_width,
508 canvas_height,
509 CANVAS_ADDR_NOWRAP,
510 CANVAS_BLKMODE_LINEAR);
511 hw->buffer_spec[i].canvas_config[0].phy_addr =
512 hw->buffer_spec[i].y_addr;
513 hw->buffer_spec[i].canvas_config[0].width =
514 canvas_width;
515 hw->buffer_spec[i].canvas_config[0].height =
516 canvas_height;
517 hw->buffer_spec[i].canvas_config[0].block_mode =
518 CANVAS_BLKMODE_LINEAR;
519
520 canvas_config(hw->buffer_spec[i].u_canvas_index,
521 hw->buffer_spec[i].u_addr,
522 canvas_width / 2,
523 canvas_height / 2,
524 CANVAS_ADDR_NOWRAP,
525 CANVAS_BLKMODE_LINEAR);
526 hw->buffer_spec[i].canvas_config[1].phy_addr =
527 hw->buffer_spec[i].u_addr;
528 hw->buffer_spec[i].canvas_config[1].width =
529 canvas_width / 2;
530 hw->buffer_spec[i].canvas_config[1].height =
531 canvas_height / 2;
532 hw->buffer_spec[i].canvas_config[1].block_mode =
533 CANVAS_BLKMODE_LINEAR;
534
535 canvas_config(hw->buffer_spec[i].v_canvas_index,
536 hw->buffer_spec[i].v_addr,
537 canvas_width / 2,
538 canvas_height / 2,
539 CANVAS_ADDR_NOWRAP,
540 CANVAS_BLKMODE_LINEAR);
541 hw->buffer_spec[i].canvas_config[2].phy_addr =
542 hw->buffer_spec[i].v_addr;
543 hw->buffer_spec[i].canvas_config[2].width =
544 canvas_width / 2;
545 hw->buffer_spec[i].canvas_config[2].height =
546 canvas_height / 2;
547 hw->buffer_spec[i].canvas_config[2].block_mode =
548 CANVAS_BLKMODE_LINEAR;
549 }
550}
551
552static void init_scaler(void)
553{
554 /* 4 point triangle */
555 const unsigned int filt_coef[] = {
556 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
557 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
558 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
559 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
560 0x18382808, 0x18382808, 0x17372909, 0x17372909,
561 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
562 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
563 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
564 0x10303010
565 };
566 int i;
567
568 /* pscale enable, PSCALE cbus bmem enable */
569 WRITE_VREG(PSCALE_CTRL, 0xc000);
570
571 /* write filter coefs */
572 WRITE_VREG(PSCALE_BMEM_ADDR, 0);
573 for (i = 0; i < 33; i++) {
574 WRITE_VREG(PSCALE_BMEM_DAT, 0);
575 WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]);
576 }
577
578 /* Y horizontal initial info */
579 WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2);
580 /* [35]: buf repeat pix0,
581 * [34:29] => buf receive num,
582 * [28:16] => buf blk x,
583 * [15:0] => buf phase
584 */
585 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
586 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
587
588 /* C horizontal initial info */
589 WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2);
590 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
591 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
592
593 /* Y vertical initial info */
594 WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2);
595 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
596 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
597
598 /* C vertical initial info */
599 WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2);
600 WRITE_VREG(PSCALE_BMEM_DAT, 0x0008);
601 WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000);
602
603 /* Y horizontal phase step */
604 WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1);
605 /* [19:0] => Y horizontal phase step */
606 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
607 /* C horizontal phase step */
608 WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1);
609 /* [19:0] => C horizontal phase step */
610 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
611
612 /* Y vertical phase step */
613 WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1);
614 /* [19:0] => Y vertical phase step */
615 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
616 /* C vertical phase step */
617 WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1);
618 /* [19:0] => C horizontal phase step */
619 WRITE_VREG(PSCALE_BMEM_DAT, 0x10000);
620
621 /* reset pscaler */
622#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
623 WRITE_VREG(DOS_SW_RESET0, (1 << 10));
624 WRITE_VREG(DOS_SW_RESET0, 0);
625#else
626 WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE);
627#endif
628 READ_RESET_REG(RESET2_REGISTER);
629 READ_RESET_REG(RESET2_REGISTER);
630 READ_RESET_REG(RESET2_REGISTER);
631
632 WRITE_VREG(PSCALE_RST, 0x7);
633 WRITE_VREG(PSCALE_RST, 0x0);
634}
635
636static void vmjpeg_dump_state(struct vdec_s *vdec)
637{
638 struct vdec_mjpeg_hw_s *hw =
639 (struct vdec_mjpeg_hw_s *)(vdec->private);
640 mmjpeg_debug_print(DECODE_ID(hw), 0,
641 "====== %s\n", __func__);
642 mmjpeg_debug_print(DECODE_ID(hw), 0,
643 "width/height (%d/%d)\n",
644 hw->frame_width,
645 hw->frame_height
646 );
647 mmjpeg_debug_print(DECODE_ID(hw), 0,
648 "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d put_frm %d run %d not_run_ready %d input_empty %d\n",
649 input_frame_based(vdec),
650 hw->eos,
651 hw->stat,
652 hw->dec_result,
653 hw->frame_num,
654 hw->put_num,
655 hw->run_count,
656 hw->not_run_ready,
657 hw->input_empty
658 );
659 if (vf_get_receiver(vdec->vf_provider_name)) {
660 enum receviver_start_e state =
661 vf_notify_receiver(vdec->vf_provider_name,
662 VFRAME_EVENT_PROVIDER_QUREY_STATE,
663 NULL);
664 mmjpeg_debug_print(DECODE_ID(hw), 0,
665 "\nreceiver(%s) state %d\n",
666 vdec->vf_provider_name,
667 state);
668 }
669 mmjpeg_debug_print(DECODE_ID(hw), 0,
670 "%s, newq(%d/%d), dispq(%d/%d) vf peek/get/put (%d/%d/%d)\n",
671 __func__,
672 kfifo_len(&hw->newframe_q),
673 VF_POOL_SIZE,
674 kfifo_len(&hw->display_q),
675 VF_POOL_SIZE,
676 hw->peek_num,
677 hw->get_num,
678 hw->put_num
679 );
680 mmjpeg_debug_print(DECODE_ID(hw), 0,
681 "VIFF_BIT_CNT=0x%x\n",
682 READ_VREG(VIFF_BIT_CNT));
683 mmjpeg_debug_print(DECODE_ID(hw), 0,
684 "VLD_MEM_VIFIFO_LEVEL=0x%x\n",
685 READ_VREG(VLD_MEM_VIFIFO_LEVEL));
686 mmjpeg_debug_print(DECODE_ID(hw), 0,
687 "VLD_MEM_VIFIFO_WP=0x%x\n",
688 READ_VREG(VLD_MEM_VIFIFO_WP));
689 mmjpeg_debug_print(DECODE_ID(hw), 0,
690 "VLD_MEM_VIFIFO_RP=0x%x\n",
691 READ_VREG(VLD_MEM_VIFIFO_RP));
692 mmjpeg_debug_print(DECODE_ID(hw), 0,
693 "PARSER_VIDEO_RP=0x%x\n",
694 READ_PARSER_REG(PARSER_VIDEO_RP));
695 mmjpeg_debug_print(DECODE_ID(hw), 0,
696 "PARSER_VIDEO_WP=0x%x\n",
697 READ_PARSER_REG(PARSER_VIDEO_WP));
698 if (input_frame_based(vdec) &&
699 debug_enable & PRINT_FRAMEBASE_DATA
700 ) {
701 int jj;
702 if (hw->chunk && hw->chunk->block &&
703 hw->chunk->size > 0) {
704 u8 *data = NULL;
705
706 if (!hw->chunk->block->is_mapped)
707 data = codec_mm_vmap(hw->chunk->block->start +
708 hw->chunk->offset, hw->chunk->size);
709 else
710 data = ((u8 *)hw->chunk->block->start_virt) +
711 hw->chunk->offset;
712
713 mmjpeg_debug_print(DECODE_ID(hw), 0,
714 "frame data size 0x%x\n",
715 hw->chunk->size);
716 for (jj = 0; jj < hw->chunk->size; jj++) {
717 if ((jj & 0xf) == 0)
718 mmjpeg_debug_print(DECODE_ID(hw),
719 PRINT_FRAMEBASE_DATA,
720 "%06x:", jj);
721 mmjpeg_debug_print(DECODE_ID(hw),
722 PRINT_FRAMEBASE_DATA,
723 "%02x ", data[jj]);
724 if (((jj + 1) & 0xf) == 0)
725 mmjpeg_debug_print(DECODE_ID(hw),
726 PRINT_FRAMEBASE_DATA,
727 "\n");
728 }
729
730 if (!hw->chunk->block->is_mapped)
731 codec_mm_unmap_phyaddr(data);
732 }
733 }
734}
735static void reset_process_time(struct vdec_mjpeg_hw_s *hw)
736{
737 if (hw->start_process_time) {
738 unsigned process_time =
739 1000 * (jiffies - hw->start_process_time) / HZ;
740 hw->start_process_time = 0;
741 if (process_time > max_process_time[DECODE_ID(hw)])
742 max_process_time[DECODE_ID(hw)] = process_time;
743 }
744}
745
746static void start_process_time(struct vdec_mjpeg_hw_s *hw)
747{
748 hw->decode_timeout_count = 2;
749 hw->start_process_time = jiffies;
750}
751
752static void timeout_process(struct vdec_mjpeg_hw_s *hw)
753{
754 amvdec_stop();
755 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
756 "%s decoder timeout\n", __func__);
757 hw->dec_result = DEC_RESULT_DONE;
758 reset_process_time(hw);
759 vdec_schedule_work(&hw->work);
760}
761
762static void check_timer_func(unsigned long arg)
763{
764 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)arg;
765 struct vdec_s *vdec = hw_to_vdec(hw);
766 int timeout_val = decode_timeout_val;
767
768 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
769 "%s: status:nstatus=%d:%d\n",
770 __func__, vdec->status, vdec->next_status);
771 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_VLD_DETAIL,
772 "%s: %d,buftl=%x:%x:%x:%x\n",
773 __func__, __LINE__,
774 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
775 READ_PARSER_REG(PARSER_VIDEO_WP),
776 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
777 READ_VREG(VLD_MEM_VIFIFO_WP));
778
779 if (radr != 0) {
780 if (rval != 0) {
781 WRITE_VREG(radr, rval);
782 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
783 } else
784 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
785 rval = 0;
786 radr = 0;
787 }
788
789 if (((debug_enable & PRINT_FLAG_TIMEOUT_STATUS) == 0) &&
790 (input_frame_based(vdec) ||
791 ((u32)READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x100)) &&
792 (timeout_val > 0) &&
793 (hw->start_process_time > 0) &&
794 ((1000 * (jiffies - hw->start_process_time) / HZ)
795 > timeout_val)) {
796 if (hw->last_vld_level == READ_VREG(VLD_MEM_VIFIFO_LEVEL)) {
797 if (hw->decode_timeout_count > 0)
798 hw->decode_timeout_count--;
799 if (hw->decode_timeout_count == 0)
800 timeout_process(hw);
801 }
802 hw->last_vld_level = READ_VREG(VLD_MEM_VIFIFO_LEVEL);
803 }
804
805 if (READ_VREG(DEC_STATUS_REG) == DEC_DECODE_TIMEOUT) {
806 pr_info("ucode DEC_DECODE_TIMEOUT\n");
807 if (hw->decode_timeout_count > 0)
808 hw->decode_timeout_count--;
809 if (hw->decode_timeout_count == 0)
810 timeout_process(hw);
811 WRITE_VREG(DEC_STATUS_REG, 0);
812 }
813
814 if (vdec->next_status == VDEC_STATUS_DISCONNECTED) {
815 hw->dec_result = DEC_RESULT_FORCE_EXIT;
816 vdec_schedule_work(&hw->work);
817 pr_info("vdec requested to be disconnected\n");
818 return;
819 }
820 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
821}
822
823static int vmjpeg_v4l_alloc_buff_config_canvas(struct vdec_mjpeg_hw_s *hw, int i)
824{
825 int ret;
826 u32 canvas;
827 ulong decbuf_start = 0, addr;
828 int decbuf_y_size = 0, decbuf_uv_size = 0;
829 u32 canvas_width = 0, canvas_height = 0;
830 struct vdec_s *vdec = hw_to_vdec(hw);
831 struct vdec_v4l2_buffer *fb = NULL;
832
833 if (hw->buffer_spec[i].v4l_ref_buf_addr)
834 return 0;
835
836 ret = vdec_v4l_get_buffer(hw->v4l2_ctx, &fb);
837 if (ret < 0) {
838 mmjpeg_debug_print(DECODE_ID(hw), 0,
839 "[%d] get fb fail.\n",
840 ((struct aml_vcodec_ctx *)
841 (hw->v4l2_ctx))->id);
842 return ret;
843 }
844
845 hw->buffer_spec[i].v4l_ref_buf_addr = (ulong)fb;
846 if (fb->num_planes == 1) {
847 decbuf_start = fb->m.mem[0].addr;
848 decbuf_y_size = fb->m.mem[0].offset;
849 decbuf_uv_size = fb->m.mem[0].size - fb->m.mem[0].offset;
850 canvas_width = ALIGN(hw->frame_width, 16);
851 canvas_height = ALIGN(hw->frame_height, 16);
852 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
853 } else if (fb->num_planes == 2) {
854 decbuf_start = fb->m.mem[0].addr;
855 decbuf_y_size = fb->m.mem[0].size;
856 decbuf_uv_size = fb->m.mem[1].size << 1;
857 canvas_width = ALIGN(hw->frame_width, 16);
858 canvas_height = ALIGN(hw->frame_height, 16);
859 fb->m.mem[0].bytes_used = decbuf_y_size;
860 fb->m.mem[1].bytes_used = decbuf_uv_size >> 1;
861 }
862
863 hw->buffer_spec[i].buf_adr = decbuf_start;
864 addr = hw->buffer_spec[i].buf_adr;
865 hw->buffer_spec[i].y_addr = addr;
866 addr += decbuf_y_size;
867 hw->buffer_spec[i].u_addr = addr;
868 addr += decbuf_uv_size;
869 hw->buffer_spec[i].v_addr = addr;
870
871 mmjpeg_debug_print(DECODE_ID(hw), 0, "[%d] %s(), v4l ref buf addr: 0x%x\n",
872 ((struct aml_vcodec_ctx *)(hw->v4l2_ctx))->id, __func__, fb);
873
874 if (vdec->parallel_dec == 1) {
875 if (hw->buffer_spec[i].y_canvas_index == -1)
876 hw->buffer_spec[i].y_canvas_index =
877 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
878 if (hw->buffer_spec[i].u_canvas_index == -1)
879 hw->buffer_spec[i].u_canvas_index =
880 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
881 if (hw->buffer_spec[i].v_canvas_index == -1)
882 hw->buffer_spec[i].v_canvas_index =
883 vdec->get_canvas_ex(CORE_MASK_VDEC_1, vdec->id);
884 } else {
885 canvas = vdec->get_canvas(i, 3);
886 hw->buffer_spec[i].y_canvas_index = canvas_y(canvas);
887 hw->buffer_spec[i].u_canvas_index = canvas_u(canvas);
888 hw->buffer_spec[i].v_canvas_index = canvas_v(canvas);
889 }
890
891 canvas_config(hw->buffer_spec[i].y_canvas_index,
892 hw->buffer_spec[i].y_addr,
893 canvas_width,
894 canvas_height,
895 CANVAS_ADDR_NOWRAP,
896 CANVAS_BLKMODE_LINEAR);
897 hw->buffer_spec[i].canvas_config[0].phy_addr =
898 hw->buffer_spec[i].y_addr;
899 hw->buffer_spec[i].canvas_config[0].width =
900 canvas_width;
901 hw->buffer_spec[i].canvas_config[0].height =
902 canvas_height;
903 hw->buffer_spec[i].canvas_config[0].block_mode =
904 CANVAS_BLKMODE_LINEAR;
905
906 canvas_config(hw->buffer_spec[i].u_canvas_index,
907 hw->buffer_spec[i].u_addr,
908 canvas_width / 2,
909 canvas_height / 2,
910 CANVAS_ADDR_NOWRAP,
911 CANVAS_BLKMODE_LINEAR);
912 hw->buffer_spec[i].canvas_config[1].phy_addr =
913 hw->buffer_spec[i].u_addr;
914 hw->buffer_spec[i].canvas_config[1].width =
915 canvas_width / 2;
916 hw->buffer_spec[i].canvas_config[1].height =
917 canvas_height / 2;
918 hw->buffer_spec[i].canvas_config[1].block_mode =
919 CANVAS_BLKMODE_LINEAR;
920
921 canvas_config(hw->buffer_spec[i].v_canvas_index,
922 hw->buffer_spec[i].v_addr,
923 canvas_width / 2,
924 canvas_height / 2,
925 CANVAS_ADDR_NOWRAP,
926 CANVAS_BLKMODE_LINEAR);
927 hw->buffer_spec[i].canvas_config[2].phy_addr =
928 hw->buffer_spec[i].v_addr;
929 hw->buffer_spec[i].canvas_config[2].width =
930 canvas_width / 2;
931 hw->buffer_spec[i].canvas_config[2].height =
932 canvas_height / 2;
933 hw->buffer_spec[i].canvas_config[2].block_mode =
934 CANVAS_BLKMODE_LINEAR;
935
936 return 0;
937}
938
939static bool is_enough_free_buffer(struct vdec_mjpeg_hw_s *hw)
940{
941 int i;
942
943 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
944 if (hw->vfbuf_use[i] == 0)
945 break;
946 }
947
948 return i == DECODE_BUFFER_NUM_MAX ? false : true;
949}
950
951static int find_free_buffer(struct vdec_mjpeg_hw_s *hw)
952{
953 int i;
954
955 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
956 if (hw->vfbuf_use[i] == 0)
957 break;
958 }
959
960 if (i == DECODE_BUFFER_NUM_MAX)
961 return -1;
962
963 if (hw->is_used_v4l)
964 if (vmjpeg_v4l_alloc_buff_config_canvas(hw, i))
965 return -1;
966
967 return i;
968}
969
970static int vmjpeg_hw_ctx_restore(struct vdec_mjpeg_hw_s *hw)
971{
972 struct buffer_spec_s *buff_spec;
973 u32 index, i;
974
975 index = find_free_buffer(hw);
976 if (index < 0)
977 return -1;
978
979 WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6));
980 WRITE_VREG(DOS_SW_RESET0, 0);
981
982 if (!hw->init_flag) {
983 vmjpeg_canvas_init(hw);
984 } else {
985 if (!hw->is_used_v4l) {
986 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
987 buff_spec = &hw->buffer_spec[i];
988 canvas_config_config(buff_spec->y_canvas_index,
989 &buff_spec->canvas_config[0]);
990 canvas_config_config(buff_spec->u_canvas_index,
991 &buff_spec->canvas_config[1]);
992 canvas_config_config(buff_spec->v_canvas_index,
993 &buff_spec->canvas_config[2]);
994 }
995 }
996 }
997
998 /* find next decode buffer index */
999 WRITE_VREG(AV_SCRATCH_4, spec2canvas(&hw->buffer_spec[index]));
1000 WRITE_VREG(AV_SCRATCH_5, index);
1001
1002 init_scaler();
1003
1004 /* clear buffer IN/OUT registers */
1005 WRITE_VREG(MREG_TO_AMRISC, 0);
1006 WRITE_VREG(MREG_FROM_AMRISC, 0);
1007
1008 WRITE_VREG(MCPU_INTR_MSK, 0xffff);
1009 WRITE_VREG(MREG_DECODE_PARAM, (hw->frame_height << 4) | 0x8000);
1010
1011 /* clear mailbox interrupt */
1012 WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1);
1013 /* enable mailbox interrupt */
1014 WRITE_VREG(ASSIST_MBOX1_MASK, 1);
1015 /* set interrupt mapping for vld */
1016 WRITE_VREG(ASSIST_AMR1_INT8, 8);
1017#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/
1018 CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17);
1019#endif
1020 return 0;
1021}
1022
1023static s32 vmjpeg_init(struct vdec_s *vdec)
1024{
1025 int i;
1026 int size = -1, fw_size = 0x1000 * 16;
1027 struct firmware_s *fw = NULL;
1028 struct vdec_mjpeg_hw_s *hw =
1029 (struct vdec_mjpeg_hw_s *)vdec->private;
1030
1031 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
1032 if (IS_ERR_OR_NULL(fw))
1033 return -ENOMEM;
1034
1035 size = get_firmware_data(VIDEO_DEC_MJPEG_MULTI, fw->data);
1036 if (size < 0) {
1037 pr_err("get firmware fail.");
1038 vfree(fw);
1039 return -1;
1040 }
1041
1042 fw->len = size;
1043 hw->fw = fw;
1044
1045 hw->frame_width = hw->vmjpeg_amstream_dec_info.width;
1046 hw->frame_height = hw->vmjpeg_amstream_dec_info.height;
1047 hw->frame_dur = ((hw->vmjpeg_amstream_dec_info.rate) ?
1048 hw->vmjpeg_amstream_dec_info.rate : 3840);
1049 hw->saved_resolution = 0;
1050 hw->eos = 0;
1051 hw->init_flag = 0;
1052 hw->frame_num = 0;
1053 hw->put_num = 0;
1054 hw->run_count = 0;
1055 hw->not_run_ready = 0;
1056 hw->input_empty = 0;
1057 hw->peek_num = 0;
1058 hw->get_num = 0;
1059 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++)
1060 hw->vfbuf_use[i] = 0;
1061
1062 INIT_KFIFO(hw->display_q);
1063 INIT_KFIFO(hw->newframe_q);
1064
1065 for (i = 0; i < VF_POOL_SIZE; i++) {
1066 const struct vframe_s *vf = &hw->vfpool[i];
1067
1068 hw->vfpool[i].index = -1;
1069 kfifo_put(&hw->newframe_q, vf);
1070 }
1071
1072 if (hw->mm_blk_handle) {
1073 decoder_bmmu_box_free(hw->mm_blk_handle);
1074 hw->mm_blk_handle = NULL;
1075 }
1076
1077 hw->mm_blk_handle = decoder_bmmu_box_alloc_box(
1078 DRIVER_NAME,
1079 0,
1080 MAX_BMMU_BUFFER_NUM,
1081 4 + PAGE_SHIFT,
1082 CODEC_MM_FLAGS_CMA_CLEAR |
1083 CODEC_MM_FLAGS_FOR_VDECODER);
1084
1085 init_timer(&hw->check_timer);
1086
1087 hw->check_timer.data = (unsigned long)hw;
1088 hw->check_timer.function = check_timer_func;
1089 hw->check_timer.expires = jiffies + CHECK_INTERVAL;
1090 /*add_timer(&hw->check_timer);*/
1091 hw->stat |= STAT_TIMER_ARM;
1092 hw->stat |= STAT_ISR_REG;
1093
1094 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
1095 INIT_WORK(&hw->work, vmjpeg_work);
1096 pr_info("w:h=%d:%d\n", hw->frame_width, hw->frame_height);
1097 return 0;
1098}
1099
1100static unsigned long run_ready(struct vdec_s *vdec,
1101 unsigned long mask)
1102{
1103 struct vdec_mjpeg_hw_s *hw =
1104 (struct vdec_mjpeg_hw_s *)vdec->private;
1105 hw->not_run_ready++;
1106 if (hw->eos)
1107 return 0;
1108 if (vdec_stream_based(vdec) && (hw->init_flag == 0)
1109 && pre_decode_buf_level != 0) {
1110 u32 rp, wp, level;
1111
1112 rp = READ_PARSER_REG(PARSER_VIDEO_RP);
1113 wp = READ_PARSER_REG(PARSER_VIDEO_WP);
1114 if (wp < rp)
1115 level = vdec->input.size + wp - rp;
1116 else
1117 level = wp - rp;
1118
1119 if (level < pre_decode_buf_level)
1120 return 0;
1121 }
1122
1123 if (!is_enough_free_buffer(hw)) {
1124 hw->buffer_not_ready++;
1125 return 0;
1126 }
1127
1128 hw->not_run_ready = 0;
1129 hw->buffer_not_ready = 0;
1130 if (vdec->parallel_dec == 1)
1131 return CORE_MASK_VDEC_1;
1132 else
1133 return CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
1134}
1135
1136static void run(struct vdec_s *vdec, unsigned long mask,
1137 void (*callback)(struct vdec_s *, void *), void *arg)
1138{
1139 struct vdec_mjpeg_hw_s *hw =
1140 (struct vdec_mjpeg_hw_s *)vdec->private;
1141 int i, ret;
1142
1143 hw->vdec_cb_arg = arg;
1144 hw->vdec_cb = callback;
1145
1146 hw->run_count++;
1147 vdec_reset_core(vdec);
1148 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1149 if (hw->vfbuf_use[i] == 0)
1150 break;
1151 }
1152
1153 if (i == DECODE_BUFFER_NUM_MAX) {
1154 hw->dec_result = DEC_RESULT_AGAIN;
1155 vdec_schedule_work(&hw->work);
1156 return;
1157 }
1158
1159 ret = vdec_prepare_input(vdec, &hw->chunk);
1160 if (ret <= 0) {
1161 hw->input_empty++;
1162 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1163 "%s: %d,r=%d,buftl=%x:%x:%x\n",
1164 __func__, __LINE__, ret,
1165 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1166 READ_PARSER_REG(PARSER_VIDEO_WP),
1167 READ_VREG(VLD_MEM_VIFIFO_WP));
1168
1169 hw->dec_result = DEC_RESULT_AGAIN;
1170 vdec_schedule_work(&hw->work);
1171 return;
1172 }
1173 hw->input_empty = 0;
1174 hw->dec_result = DEC_RESULT_NONE;
1175 if (vdec->mc_loaded) {
1176 /*firmware have load before,
1177 and not changes to another.
1178 ignore reload.
1179 */
1180 } else {
1181 ret = amvdec_vdec_loadmc_ex(VFORMAT_MJPEG, "mmjpeg", vdec, hw->fw->data);
1182 if (ret < 0) {
1183 pr_err("[%d] MMJPEG: the %s fw loading failed, err: %x\n",
1184 vdec->id, tee_enabled() ? "TEE" : "local", ret);
1185 hw->dec_result = DEC_RESULT_FORCE_EXIT;
1186 vdec_schedule_work(&hw->work);
1187 return;
1188 }
1189 vdec->mc_loaded = 1;
1190 vdec->mc_type = VFORMAT_MJPEG;
1191 }
1192/* if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) {
1193 pr_err("%s: Error amvdec_loadmc fail\n", __func__);
1194 return;
1195 }*/
1196
1197 if (vmjpeg_hw_ctx_restore(hw) < 0) {
1198 hw->dec_result = DEC_RESULT_ERROR;
1199 mmjpeg_debug_print(DECODE_ID(hw), 0,
1200 "amvdec_mmjpeg: error HW context restore\n");
1201 vdec_schedule_work(&hw->work);
1202 return;
1203 }
1204#if 0
1205 vdec_enable_input(vdec);
1206 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1207#endif
1208 hw->stat |= STAT_MC_LOAD;
1209 start_process_time(hw);
1210 hw->last_vld_level = 0;
1211 mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
1212 amvdec_start();
1213 vdec_enable_input(vdec);
1214 hw->stat |= STAT_VDEC_RUN;
1215 hw->init_flag = 1;
1216
1217 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_RUN_FLOW,
1218 "%s (0x%x 0x%x 0x%x) vldcrl 0x%x bitcnt 0x%x powerctl 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1219 __func__,
1220 READ_VREG(VLD_MEM_VIFIFO_LEVEL),
1221 READ_VREG(VLD_MEM_VIFIFO_WP),
1222 READ_VREG(VLD_MEM_VIFIFO_RP),
1223 READ_VREG(VLD_DECODE_CONTROL),
1224 READ_VREG(VIFF_BIT_CNT),
1225 READ_VREG(POWER_CTL_VLD),
1226 READ_VREG(VLD_MEM_VIFIFO_START_PTR),
1227 READ_VREG(VLD_MEM_VIFIFO_CURR_PTR),
1228 READ_VREG(VLD_MEM_VIFIFO_CONTROL),
1229 READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL),
1230 READ_VREG(VLD_MEM_VIFIFO_END_PTR));
1231}
1232static void wait_vmjpeg_search_done(struct vdec_mjpeg_hw_s *hw)
1233{
1234 u32 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1235 int count = 0;
1236
1237 do {
1238 usleep_range(100, 500);
1239 if (vld_rp == READ_VREG(VLD_MEM_VIFIFO_RP))
1240 break;
1241 if (count > 1000) {
1242 mmjpeg_debug_print(DECODE_ID(hw), 0,
1243 "%s, count %d vld_rp 0x%x VLD_MEM_VIFIFO_RP 0x%x\n",
1244 __func__, count, vld_rp, READ_VREG(VLD_MEM_VIFIFO_RP));
1245 break;
1246 } else
1247 vld_rp = READ_VREG(VLD_MEM_VIFIFO_RP);
1248 count++;
1249 } while (1);
1250}
1251
1252static int notify_v4l_eos(struct vdec_s *vdec)
1253{
1254 struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private;
1255 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
1256 struct vframe_s *vf = NULL;
1257 struct vdec_v4l2_buffer *fb = NULL;
1258
1259 if (hw->is_used_v4l && hw->eos) {
1260 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
1261 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_ERROR,
1262 "%s fatal error, no available buffer slot.\n",
1263 __func__);
1264 return -1;
1265 }
1266
1267 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb)) {
1268 pr_err("[%d] get fb fail.\n", ctx->id);
1269 return -1;
1270 }
1271
1272 vf->timestamp = ULONG_MAX;
1273 vf->v4l_mem_handle = (unsigned long)fb;
1274 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
1275
1276 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
1277 vf_notify_receiver(vdec->vf_provider_name,
1278 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
1279
1280 pr_info("[%d] mpeg12 EOS notify.\n", ctx->id);
1281 }
1282
1283 return 0;
1284}
1285
1286static void vmjpeg_work(struct work_struct *work)
1287{
1288 struct vdec_mjpeg_hw_s *hw = container_of(work,
1289 struct vdec_mjpeg_hw_s, work);
1290 struct vdec_s *vdec = hw_to_vdec(hw);
1291
1292 mmjpeg_debug_print(DECODE_ID(hw), PRINT_FLAG_BUFFER_DETAIL,
1293 "%s: result=%d,len=%d:%d\n",
1294 __func__, hw->dec_result,
1295 kfifo_len(&hw->newframe_q),
1296 kfifo_len(&hw->display_q));
1297 if (hw->dec_result == DEC_RESULT_DONE) {
1298 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1299 hw->chunk = NULL;
1300 } else if (hw->dec_result == DEC_RESULT_AGAIN) {
1301 /*
1302 stream base: stream buf empty or timeout
1303 frame base: vdec_prepare_input fail
1304 */
1305 if (!vdec_has_more_input(hw_to_vdec(hw))) {
1306 hw->dec_result = DEC_RESULT_EOS;
1307 vdec_schedule_work(&hw->work);
1308 /*pr_info("%s: return\n",
1309 __func__);*/
1310 return;
1311 }
1312 } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) {
1313 pr_info("%s: force exit\n", __func__);
1314 if (hw->stat & STAT_ISR_REG) {
1315 amvdec_stop();
1316 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1317 hw->stat &= ~STAT_ISR_REG;
1318 }
1319 } else if (hw->dec_result == DEC_RESULT_EOS) {
1320 pr_info("%s: end of stream\n", __func__);
1321 if (hw->stat & STAT_VDEC_RUN) {
1322 amvdec_stop();
1323 hw->stat &= ~STAT_VDEC_RUN;
1324 }
1325 hw->eos = 1;
1326 if (hw->is_used_v4l)
1327 notify_v4l_eos(vdec);
1328
1329 vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk);
1330 hw->chunk = NULL;
1331 vdec_clean_input(hw_to_vdec(hw));
1332 }
1333 if (hw->stat & STAT_VDEC_RUN) {
1334 amvdec_stop();
1335 hw->stat &= ~STAT_VDEC_RUN;
1336 }
1337 /*disable mbox interrupt */
1338 WRITE_VREG(ASSIST_MBOX1_MASK, 0);
1339 wait_vmjpeg_search_done(hw);
1340 /* mark itself has all HW resource released and input released */
1341 if (vdec->parallel_dec == 1)
1342 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1343 else {
1344 vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1
1345 | CORE_MASK_HEVC);
1346 }
1347 del_timer_sync(&hw->check_timer);
1348 hw->stat &= ~STAT_TIMER_ARM;
1349
1350 if (hw->vdec_cb)
1351 hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg);
1352}
1353
1354static int vmjpeg_stop(struct vdec_mjpeg_hw_s *hw)
1355{
1356 pr_info("%s ...count = %d\n", __func__, hw->frame_num);
1357
1358 if (hw->stat & STAT_VDEC_RUN) {
1359 amvdec_stop();
1360 pr_info("%s amvdec_stop\n", __func__);
1361 hw->stat &= ~STAT_VDEC_RUN;
1362 }
1363
1364 if (hw->stat & STAT_ISR_REG) {
1365 vdec_free_irq(VDEC_IRQ_1, (void *)hw);
1366 hw->stat &= ~STAT_ISR_REG;
1367 }
1368
1369 if (hw->stat & STAT_TIMER_ARM) {
1370 del_timer_sync(&hw->check_timer);
1371 hw->stat &= ~STAT_TIMER_ARM;
1372 }
1373 cancel_work_sync(&hw->work);
1374 hw->init_flag = 0;
1375
1376 if (hw->mm_blk_handle) {
1377 decoder_bmmu_box_free(hw->mm_blk_handle);
1378 hw->mm_blk_handle = NULL;
1379 }
1380
1381 if (hw->fw) {
1382 vfree(hw->fw);
1383 hw->fw = NULL;
1384 }
1385
1386 return 0;
1387}
1388
1389static int ammvdec_mjpeg_probe(struct platform_device *pdev)
1390{
1391 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
1392 struct vdec_mjpeg_hw_s *hw = NULL;
1393
1394 if (pdata == NULL) {
1395 pr_info("ammvdec_mjpeg memory resource undefined.\n");
1396 return -EFAULT;
1397 }
1398
1399 hw = (struct vdec_mjpeg_hw_s *)devm_kzalloc(&pdev->dev,
1400 sizeof(struct vdec_mjpeg_hw_s), GFP_KERNEL);
1401 hw = vzalloc(sizeof(struct vdec_mjpeg_hw_s));
1402 if (hw == NULL) {
1403 pr_info("\nammvdec_mjpeg device data allocation failed\n");
1404 return -ENOMEM;
1405 }
1406
1407 /* the ctx from v4l2 driver. */
1408 hw->v4l2_ctx = pdata->private;
1409
1410 pdata->private = hw;
1411 pdata->dec_status = vmjpeg_dec_status;
1412
1413 pdata->run = run;
1414 pdata->run_ready = run_ready;
1415 pdata->irq_handler = vmjpeg_isr;
1416 pdata->dump_state = vmjpeg_dump_state;
1417
1418 if (pdata->parallel_dec == 1) {
1419 int i;
1420 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1421 hw->buffer_spec[i].y_canvas_index = -1;
1422 hw->buffer_spec[i].u_canvas_index = -1;
1423 hw->buffer_spec[i].v_canvas_index = -1;
1424 }
1425 }
1426
1427 if (pdata->use_vfm_path)
1428 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1429 VFM_DEC_PROVIDER_NAME);
1430 else
1431 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
1432 PROVIDER_NAME ".%02x", pdev->id & 0xff);
1433
1434 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
1435 &vf_provider_ops, pdata);
1436
1437 platform_set_drvdata(pdev, pdata);
1438
1439 hw->platform_dev = pdev;
1440
1441 if (pdata->sys_info) {
1442 hw->vmjpeg_amstream_dec_info = *pdata->sys_info;
1443 hw->is_used_v4l = (((unsigned long)
1444 hw->vmjpeg_amstream_dec_info.param & 0x80) >> 7);
1445 }
1446
1447 vdec_source_changed(VFORMAT_MJPEG,
1448 1920, 1080, 60);
1449 if (vmjpeg_init(pdata) < 0) {
1450 pr_info("ammvdec_mjpeg init failed.\n");
1451 if (hw) {
1452 vfree(hw);
1453 hw = NULL;
1454 }
1455 pdata->dec_status = NULL;
1456 return -ENODEV;
1457 }
1458 if (pdata->parallel_dec == 1)
1459 vdec_core_request(pdata, CORE_MASK_VDEC_1);
1460 else {
1461 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
1462 | CORE_MASK_COMBINE);
1463 }
1464
1465 return 0;
1466}
1467
1468static int ammvdec_mjpeg_remove(struct platform_device *pdev)
1469{
1470 struct vdec_mjpeg_hw_s *hw =
1471 (struct vdec_mjpeg_hw_s *)
1472 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
1473 struct vdec_s *vdec = hw_to_vdec(hw);
1474 int i;
1475
1476 vmjpeg_stop(hw);
1477
1478 if (vdec->parallel_dec == 1)
1479 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1);
1480 else
1481 vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
1482 vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED);
1483 if (vdec->parallel_dec == 1) {
1484 for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) {
1485 vdec->free_canvas_ex(hw->buffer_spec[i].y_canvas_index, vdec->id);
1486 vdec->free_canvas_ex(hw->buffer_spec[i].u_canvas_index, vdec->id);
1487 vdec->free_canvas_ex(hw->buffer_spec[i].v_canvas_index, vdec->id);
1488 }
1489 }
1490 if (hw) {
1491 vfree(hw);
1492 hw = NULL;
1493 }
1494 pr_info("%s\n", __func__);
1495 return 0;
1496}
1497
1498/****************************************/
1499#ifdef CONFIG_PM
1500static int mmjpeg_suspend(struct device *dev)
1501{
1502 amvdec_suspend(to_platform_device(dev), dev->power.power_state);
1503 return 0;
1504}
1505
1506static int mmjpeg_resume(struct device *dev)
1507{
1508 amvdec_resume(to_platform_device(dev));
1509 return 0;
1510}
1511
1512static const struct dev_pm_ops mmjpeg_pm_ops = {
1513 SET_SYSTEM_SLEEP_PM_OPS(mmjpeg_suspend, mmjpeg_resume)
1514};
1515#endif
1516
1517static struct platform_driver ammvdec_mjpeg_driver = {
1518 .probe = ammvdec_mjpeg_probe,
1519 .remove = ammvdec_mjpeg_remove,
1520 .driver = {
1521 .name = DRIVER_NAME,
1522#ifdef CONFIG_PM
1523 .pm = &mmjpeg_pm_ops,
1524#endif
1525 }
1526};
1527
1528static struct codec_profile_t ammvdec_mjpeg_profile = {
1529 .name = "mmjpeg",
1530 .profile = ""
1531};
1532
1533static int __init ammvdec_mjpeg_driver_init_module(void)
1534{
1535 if (platform_driver_register(&ammvdec_mjpeg_driver)) {
1536 pr_err("failed to register ammvdec_mjpeg driver\n");
1537 return -ENODEV;
1538 }
1539 vcodec_profile_register(&ammvdec_mjpeg_profile);
1540 return 0;
1541}
1542
1543static void __exit ammvdec_mjpeg_driver_remove_module(void)
1544{
1545 platform_driver_unregister(&ammvdec_mjpeg_driver);
1546}
1547
1548/****************************************/
1549module_param(debug_enable, uint, 0664);
1550MODULE_PARM_DESC(debug_enable, "\n debug enable\n");
1551module_param(pre_decode_buf_level, int, 0664);
1552MODULE_PARM_DESC(pre_decode_buf_level,
1553 "\n ammvdec_h264 pre_decode_buf_level\n");
1554module_param(udebug_flag, uint, 0664);
1555MODULE_PARM_DESC(udebug_flag, "\n amvdec_mmpeg12 udebug_flag\n");
1556
1557
1558module_param(decode_timeout_val, uint, 0664);
1559MODULE_PARM_DESC(decode_timeout_val, "\n ammvdec_mjpeg decode_timeout_val\n");
1560
1561module_param_array(max_process_time, uint, &max_decode_instance_num, 0664);
1562
1563module_param(radr, uint, 0664);
1564MODULE_PARM_DESC(radr, "\nradr\n");
1565
1566module_param(rval, uint, 0664);
1567MODULE_PARM_DESC(rval, "\nrval\n");
1568
1569module_param(without_display_mode, uint, 0664);
1570MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
1571
1572module_init(ammvdec_mjpeg_driver_init_module);
1573module_exit(ammvdec_mjpeg_driver_remove_module);
1574
1575MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver");
1576MODULE_LICENSE("GPL");
1577MODULE_AUTHOR("Tim Yao <timyao@amlogic.com>");
1578
generated by cgit at 2024-05-17 09:07:34 (GMT)