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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: 79e71d068d1895338cd63f8936318c1818f8d4dd
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../utils/vdec_v4l2_buffer_ops.h"
61
62#define MIX_STREAM_SUPPORT
63
64#include "vvp9.h"
65
66
67/*#define SUPPORT_FB_DECODING*/
68/*#define FB_DECODING_TEST_SCHEDULE*/
69
70
71#define HW_MASK_FRONT 0x1
72#define HW_MASK_BACK 0x2
73
74#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
75#define VP9D_MPP_REFINFO_DATA 0x3443
76#define VP9D_MPP_REF_SCALE_ENBL 0x3441
77#define HEVC_MPRED_CTRL4 0x324c
78#define HEVC_CM_HEADER_START_ADDR 0x3628
79#define HEVC_DBLK_CFGB 0x350b
80#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
81#define HEVC_SAO_MMU_VH1_ADDR 0x363b
82#define HEVC_SAO_MMU_VH0_ADDR 0x363a
83
84#define HEVC_MV_INFO 0x310d
85#define HEVC_QP_INFO 0x3137
86#define HEVC_SKIP_INFO 0x3136
87
88#define VP9_10B_DEC_IDLE 0
89#define VP9_10B_DEC_FRAME_HEADER 1
90#define VP9_10B_DEC_SLICE_SEGMENT 2
91#define VP9_10B_DECODE_SLICE 5
92#define VP9_10B_DISCARD_NAL 6
93#define VP9_DUMP_LMEM 7
94#define HEVC_DECPIC_DATA_DONE 0xa
95#define HEVC_DECPIC_DATA_ERROR 0xb
96#define HEVC_NAL_DECODE_DONE 0xe
97#define HEVC_DECODE_BUFEMPTY 0x20
98#define HEVC_DECODE_TIMEOUT 0x21
99#define HEVC_SEARCH_BUFEMPTY 0x22
100#define HEVC_DECODE_OVER_SIZE 0x23
101#define HEVC_S2_DECODING_DONE 0x50
102#define VP9_HEAD_PARSER_DONE 0xf0
103#define VP9_HEAD_SEARCH_DONE 0xf1
104#define VP9_EOS 0xf2
105#define HEVC_ACTION_DONE 0xff
106
107#define VF_POOL_SIZE 32
108
109#undef pr_info
110#define pr_info printk
111
112#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
113#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
114#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
115#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
116#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
117
118#define VP9_TRIGGER_FRAME_DONE 0x100
119#define VP9_TRIGGER_FRAME_ENABLE 0x200
120
121#define MV_MEM_UNIT 0x240
122/*---------------------------------------------------
123 * Include "parser_cmd.h"
124 *---------------------------------------------------
125 */
126#define PARSER_CMD_SKIP_CFG_0 0x0000090b
127
128#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
129
130#define PARSER_CMD_SKIP_CFG_2 0x001b1910
131
132#define PARSER_CMD_NUMBER 37
133
134/*#define HEVC_PIC_STRUCT_SUPPORT*/
135/* to remove, fix build error */
136
137/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
138
139#define MULTI_INSTANCE_SUPPORT
140#define SUPPORT_10BIT
141/* #define ERROR_HANDLE_DEBUG */
142
143#ifndef STAT_KTHREAD
144#define STAT_KTHREAD 0x40
145#endif
146
147#ifdef MULTI_INSTANCE_SUPPORT
148#define MAX_DECODE_INSTANCE_NUM 9
149#define MULTI_DRIVER_NAME "ammvdec_vp9"
150static unsigned int max_decode_instance_num
151 = MAX_DECODE_INSTANCE_NUM;
152static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
153static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
154static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
155static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
156static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
157static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
158
159static u32 decode_timeout_val = 200;
160static int start_decode_buf_level = 0x8000;
161static u32 work_buf_size;
162
163static u32 mv_buf_margin;
164
165/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
166/* double_write_mode:
167 * 0, no double write;
168 * 1, 1:1 ratio;
169 * 2, (1/4):(1/4) ratio;
170 * 3, (1/4):(1/4) ratio, with both compressed frame included
171 * 4, (1/2):(1/2) ratio;
172 * 0x10, double write only
173 * 0x100, if > 1080p,use mode 4,else use mode 1;
174 * 0x200, if > 1080p,use mode 2,else use mode 1;
175 * 0x300, if > 720p, use mode 4, else use mode 1;
176 */
177static u32 double_write_mode;
178
179#define DRIVER_NAME "amvdec_vp9"
180#define MODULE_NAME "amvdec_vp9"
181#define DRIVER_HEADER_NAME "amvdec_vp9_header"
182
183
184#define PUT_INTERVAL (HZ/100)
185#define ERROR_SYSTEM_RESET_COUNT 200
186
187#define PTS_NORMAL 0
188#define PTS_NONE_REF_USE_DURATION 1
189
190#define PTS_MODE_SWITCHING_THRESHOLD 3
191#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
192
193#define DUR2PTS(x) ((x)*90/96)
194
195struct VP9Decoder_s;
196static int vvp9_vf_states(struct vframe_states *states, void *);
197static struct vframe_s *vvp9_vf_peek(void *);
198static struct vframe_s *vvp9_vf_get(void *);
199static void vvp9_vf_put(struct vframe_s *, void *);
200static int vvp9_event_cb(int type, void *data, void *private_data);
201
202static int vvp9_stop(struct VP9Decoder_s *pbi);
203#ifdef MULTI_INSTANCE_SUPPORT
204static s32 vvp9_init(struct vdec_s *vdec);
205#else
206static s32 vvp9_init(struct VP9Decoder_s *pbi);
207#endif
208static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
209static int vvp9_local_init(struct VP9Decoder_s *pbi);
210static void vvp9_put_timer_func(unsigned long arg);
211static void dump_data(struct VP9Decoder_s *pbi, int size);
212static unsigned char get_data_check_sum
213 (struct VP9Decoder_s *pbi, int size);
214static void dump_pic_list(struct VP9Decoder_s *pbi);
215static int vp9_alloc_mmu(
216 struct VP9Decoder_s *pbi,
217 int cur_buf_idx,
218 int pic_width,
219 int pic_height,
220 unsigned short bit_depth,
221 unsigned int *mmu_index_adr);
222
223
224static const char vvp9_dec_id[] = "vvp9-dev";
225
226#define PROVIDER_NAME "decoder.vp9"
227#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
228
229static const struct vframe_operations_s vvp9_vf_provider = {
230 .peek = vvp9_vf_peek,
231 .get = vvp9_vf_get,
232 .put = vvp9_vf_put,
233 .event_cb = vvp9_event_cb,
234 .vf_states = vvp9_vf_states,
235};
236
237static struct vframe_provider_s vvp9_vf_prov;
238
239static u32 bit_depth_luma;
240static u32 bit_depth_chroma;
241static u32 frame_width;
242static u32 frame_height;
243static u32 video_signal_type;
244
245static u32 on_no_keyframe_skiped;
246
247#define PROB_SIZE (496 * 2 * 4)
248#define PROB_BUF_SIZE (0x5000)
249#define COUNT_BUF_SIZE (0x300 * 4 * 4)
250/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
251#define MAX_FRAME_4K_NUM 0x1200
252#define MAX_FRAME_8K_NUM 0x4800
253
254#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
255
256#ifdef SUPPORT_FB_DECODING
257/* register define */
258#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
259#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
260#define HEVC_ASSIST_HED_FB_ADDR 0x3008
261#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
262#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
263
264
265#define MAX_STAGE_PAGE_NUM 0x1200
266#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
267#endif
268static inline int div_r32(int64_t m, int n)
269{
270/*
271 *return (int)(m/n)
272 */
273#ifndef CONFIG_ARM64
274 int64_t qu = 0;
275 qu = div_s64(m, n);
276 return (int)qu;
277#else
278 return (int)(m/n);
279#endif
280}
281
282/*USE_BUF_BLOCK*/
283struct BUF_s {
284 int index;
285 unsigned int alloc_flag;
286 /*buffer */
287 unsigned int cma_page_count;
288 unsigned long alloc_addr;
289 unsigned long start_adr;
290 unsigned int size;
291
292 unsigned int free_start_adr;
293 ulong v4l_ref_buf_addr;
294 ulong header_addr;
295 u32 header_size;
296 u32 luma_size;
297} /*BUF_t */;
298
299struct MVBUF_s {
300 unsigned long start_adr;
301 unsigned int size;
302 int used_flag;
303} /*MVBUF_t */;
304
305 /* #undef BUFMGR_ONLY to enable hardware configuration */
306
307/*#define TEST_WR_PTR_INC*/
308/*#define WR_PTR_INC_NUM 128*/
309#define WR_PTR_INC_NUM 1
310
311#define SIMULATION
312#define DOS_PROJECT
313#undef MEMORY_MAP_IN_REAL_CHIP
314
315/*#undef DOS_PROJECT*/
316/*#define MEMORY_MAP_IN_REAL_CHIP*/
317
318/*#define BUFFER_MGR_ONLY*/
319/*#define CONFIG_HEVC_CLK_FORCED_ON*/
320/*#define ENABLE_SWAP_TEST*/
321#define MCRCC_ENABLE
322
323#define VP9_LPF_LVL_UPDATE
324/*#define DBG_LF_PRINT*/
325
326#ifdef VP9_10B_NV21
327#else
328#define LOSLESS_COMPRESS_MODE
329#endif
330
331#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
332#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
333
334
335
336typedef unsigned int u32;
337typedef unsigned short u16;
338
339#define VP9_DEBUG_BUFMGR 0x01
340#define VP9_DEBUG_BUFMGR_MORE 0x02
341#define VP9_DEBUG_BUFMGR_DETAIL 0x04
342#define VP9_DEBUG_OUT_PTS 0x10
343#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
344#define VP9_DEBUG_MERGE 0x200
345#define VP9_DEBUG_DBG_LF_PRINT 0x400
346#define VP9_DEBUG_REG 0x800
347#define VP9_DEBUG_2_STAGE 0x1000
348#define VP9_DEBUG_2_STAGE_MORE 0x2000
349#define VP9_DEBUG_QOS_INFO 0x4000
350#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
351#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
352#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
353#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
354#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
355#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
356#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
357#define VP9_DEBUG_DUMP_DATA 0x800000
358#define VP9_DEBUG_CACHE 0x1000000
359#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
360#define IGNORE_PARAM_FROM_CONFIG 0x8000000
361#ifdef MULTI_INSTANCE_SUPPORT
362#define PRINT_FLAG_ERROR 0x0
363#define PRINT_FLAG_V4L_DETAIL 0x10000000
364#define PRINT_FLAG_VDEC_STATUS 0x20000000
365#define PRINT_FLAG_VDEC_DETAIL 0x40000000
366#define PRINT_FLAG_VDEC_DATA 0x80000000
367#endif
368
369static u32 debug;
370static bool is_reset;
371/*for debug*/
372/*
373 udebug_flag:
374 bit 0, enable ucode print
375 bit 1, enable ucode detail print
376 bit [31:16] not 0, pos to dump lmem
377 bit 2, pop bits to lmem
378 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
379*/
380static u32 udebug_flag;
381/*
382 when udebug_flag[1:0] is not 0
383 udebug_pause_pos not 0,
384 pause position
385*/
386static u32 udebug_pause_pos;
387/*
388 when udebug_flag[1:0] is not 0
389 and udebug_pause_pos is not 0,
390 pause only when DEBUG_REG2 is equal to this val
391*/
392static u32 udebug_pause_val;
393
394static u32 udebug_pause_decode_idx;
395
396static u32 without_display_mode;
397
398#define DEBUG_REG
399#ifdef DEBUG_REG
400void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
401{
402 if (debug & VP9_DEBUG_REG)
403 pr_info("%s(%x, %x)\n", __func__, adr, val);
404 if (adr != 0)
405 WRITE_VREG(adr, val);
406}
407
408#undef WRITE_VREG
409#define WRITE_VREG WRITE_VREG_DBG2
410#endif
411
412#define FRAME_CNT_WINDOW_SIZE 59
413#define RATE_CORRECTION_THRESHOLD 5
414/**************************************************
415
416VP9 buffer management start
417
418***************************************************/
419
420#define MMU_COMPRESS_HEADER_SIZE 0x48000
421#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
422#define MAX_SIZE_8K (8192 * 4608)
423#define MAX_SIZE_4K (4096 * 2304)
424#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
425
426#define INVALID_IDX -1 /* Invalid buffer index.*/
427
428#define RPM_BEGIN 0x200
429#define RPM_END 0x280
430
431union param_u {
432 struct {
433 unsigned short data[RPM_END - RPM_BEGIN];
434 } l;
435 struct {
436 /* from ucode lmem, do not change this struct */
437 unsigned short profile;
438 unsigned short show_existing_frame;
439 unsigned short frame_to_show_idx;
440 unsigned short frame_type; /*1 bit*/
441 unsigned short show_frame; /*1 bit*/
442 unsigned short error_resilient_mode; /*1 bit*/
443 unsigned short intra_only; /*1 bit*/
444 unsigned short display_size_present; /*1 bit*/
445 unsigned short reset_frame_context;
446 unsigned short refresh_frame_flags;
447 unsigned short width;
448 unsigned short height;
449 unsigned short display_width;
450 unsigned short display_height;
451 /*
452 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
453 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
454 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
455 */
456 unsigned short ref_info;
457 /*
458 *bit[2]: same_frame_size0
459 *bit[1]: same_frame_size1
460 *bit[0]: same_frame_size2
461 */
462 unsigned short same_frame_size;
463
464 unsigned short mode_ref_delta_enabled;
465 unsigned short ref_deltas[4];
466 unsigned short mode_deltas[2];
467 unsigned short filter_level;
468 unsigned short sharpness_level;
469 unsigned short bit_depth;
470 unsigned short seg_quant_info[8];
471 unsigned short seg_enabled;
472 unsigned short seg_abs_delta;
473 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
474 unsigned short seg_lf_info[8];
475 } p;
476};
477
478
479struct vpx_codec_frame_buffer_s {
480 uint8_t *data; /**< Pointer to the data buffer */
481 size_t size; /**< Size of data in bytes */
482 void *priv; /**< Frame's private data */
483};
484
485enum vpx_color_space_t {
486 VPX_CS_UNKNOWN = 0, /**< Unknown */
487 VPX_CS_BT_601 = 1, /**< BT.601 */
488 VPX_CS_BT_709 = 2, /**< BT.709 */
489 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
490 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
491 VPX_CS_BT_2020 = 5, /**< BT.2020 */
492 VPX_CS_RESERVED = 6, /**< Reserved */
493 VPX_CS_SRGB = 7 /**< sRGB */
494}; /**< alias for enum vpx_color_space */
495
496enum vpx_bit_depth_t {
497 VPX_BITS_8 = 8, /**< 8 bits */
498 VPX_BITS_10 = 10, /**< 10 bits */
499 VPX_BITS_12 = 12, /**< 12 bits */
500};
501
502#define MAX_SLICE_NUM 1024
503struct PIC_BUFFER_CONFIG_s {
504 int index;
505 int BUF_index;
506 int mv_buf_index;
507 int comp_body_size;
508 int buf_size;
509 int vf_ref;
510 int y_canvas_index;
511 int uv_canvas_index;
512#ifdef MULTI_INSTANCE_SUPPORT
513 struct canvas_config_s canvas_config[2];
514#endif
515 int decode_idx;
516 int slice_type;
517 int stream_offset;
518 u32 pts;
519 u64 pts64;
520 u64 timestamp;
521 uint8_t error_mark;
522 /**/
523 int slice_idx;
524 /*buffer*/
525 unsigned long header_adr;
526 unsigned long mpred_mv_wr_start_addr;
527 /*unsigned long mc_y_adr;
528 *unsigned long mc_u_v_adr;
529 */
530 unsigned int dw_y_adr;
531 unsigned int dw_u_v_adr;
532 int mc_canvas_y;
533 int mc_canvas_u_v;
534
535 int lcu_total;
536 /**/
537 int y_width;
538 int y_height;
539 int y_crop_width;
540 int y_crop_height;
541 int y_stride;
542
543 int uv_width;
544 int uv_height;
545 int uv_crop_width;
546 int uv_crop_height;
547 int uv_stride;
548
549 int alpha_width;
550 int alpha_height;
551 int alpha_stride;
552
553 uint8_t *y_buffer;
554 uint8_t *u_buffer;
555 uint8_t *v_buffer;
556 uint8_t *alpha_buffer;
557
558 uint8_t *buffer_alloc;
559 int buffer_alloc_sz;
560 int border;
561 int frame_size;
562 int subsampling_x;
563 int subsampling_y;
564 unsigned int bit_depth;
565 enum vpx_color_space_t color_space;
566
567 int corrupted;
568 int flags;
569 unsigned long cma_alloc_addr;
570
571 int double_write_mode;
572
573 /* picture qos infomation*/
574 int max_qp;
575 int avg_qp;
576 int min_qp;
577 int max_skip;
578 int avg_skip;
579 int min_skip;
580 int max_mv;
581 int min_mv;
582 int avg_mv;
583
584 bool vframe_bound;
585} PIC_BUFFER_CONFIG;
586
587enum BITSTREAM_PROFILE {
588 PROFILE_0,
589 PROFILE_1,
590 PROFILE_2,
591 PROFILE_3,
592 MAX_PROFILES
593};
594
595enum FRAME_TYPE {
596 KEY_FRAME = 0,
597 INTER_FRAME = 1,
598 FRAME_TYPES,
599};
600
601enum REFERENCE_MODE {
602 SINGLE_REFERENCE = 0,
603 COMPOUND_REFERENCE = 1,
604 REFERENCE_MODE_SELECT = 2,
605 REFERENCE_MODES = 3,
606};
607
608#define NONE -1
609#define INTRA_FRAME 0
610#define LAST_FRAME 1
611#define GOLDEN_FRAME 2
612#define ALTREF_FRAME 3
613#define MAX_REF_FRAMES 4
614
615#define REFS_PER_FRAME 3
616
617#define REF_FRAMES_LOG2 3
618#define REF_FRAMES (1 << REF_FRAMES_LOG2)
619#define REF_FRAMES_4K (6)
620
621/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
622 *in parallel, 3 for scaled references on the encoder.
623 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
624 * // of framebuffers.
625 *TODO(jkoleszar): These 3 extra references could probably come from the
626 *normal reference pool.
627 */
628#define FRAME_BUFFERS (REF_FRAMES + 16)
629#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
630#define MAX_BUF_NUM (FRAME_BUFFERS)
631#define MV_BUFFER_NUM FRAME_BUFFERS
632#ifdef SUPPORT_FB_DECODING
633#define STAGE_MAX_BUFFERS 16
634#else
635#define STAGE_MAX_BUFFERS 0
636#endif
637
638#define FRAME_CONTEXTS_LOG2 2
639#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
640/*buffer + header buffer + workspace*/
641#ifdef MV_USE_FIXED_BUF
642#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
643#define VF_BUFFER_IDX(n) (n)
644#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
645#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
646#else
647#define MAX_BMMU_BUFFER_NUM \
648 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
649#define VF_BUFFER_IDX(n) (n)
650#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
651#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
652#define WORK_SPACE_BUF_ID \
653 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
654#endif
655
656struct RefCntBuffer_s {
657 int ref_count;
658 /*MV_REF *mvs;*/
659 int mi_rows;
660 int mi_cols;
661 struct vpx_codec_frame_buffer_s raw_frame_buffer;
662 struct PIC_BUFFER_CONFIG_s buf;
663
664/*The Following variables will only be used in frame parallel decode.
665 *
666 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
667 *that no FrameWorker owns, or is decoding, this buffer.
668 *VP9Worker *frame_worker_owner;
669 *
670 *row and col indicate which position frame has been decoded to in real
671 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
672 *when the frame is fully decoded.
673 */
674 int row;
675 int col;
676} RefCntBuffer;
677
678struct RefBuffer_s {
679/*TODO(dkovalev): idx is not really required and should be removed, now it
680 *is used in vp9_onyxd_if.c
681 */
682 int idx;
683 struct PIC_BUFFER_CONFIG_s *buf;
684 /*struct scale_factors sf;*/
685} RefBuffer;
686
687struct InternalFrameBuffer_s {
688 uint8_t *data;
689 size_t size;
690 int in_use;
691} InternalFrameBuffer;
692
693struct InternalFrameBufferList_s {
694 int num_internal_frame_buffers;
695 struct InternalFrameBuffer_s *int_fb;
696} InternalFrameBufferList;
697
698struct BufferPool_s {
699/*Protect BufferPool from being accessed by several FrameWorkers at
700 *the same time during frame parallel decode.
701 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
702 *
703 *Private data associated with the frame buffer callbacks.
704 *void *cb_priv;
705 *
706 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
707 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
708 */
709
710 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
711
712/*Frame buffers allocated internally by the codec.*/
713 struct InternalFrameBufferList_s int_frame_buffers;
714 unsigned long flags;
715 spinlock_t lock;
716
717} BufferPool;
718
719#define lock_buffer_pool(pool, flags) \
720 spin_lock_irqsave(&pool->lock, flags)
721
722#define unlock_buffer_pool(pool, flags) \
723 spin_unlock_irqrestore(&pool->lock, flags)
724
725struct VP9_Common_s {
726 enum vpx_color_space_t color_space;
727 int width;
728 int height;
729 int display_width;
730 int display_height;
731 int last_width;
732 int last_height;
733
734 int subsampling_x;
735 int subsampling_y;
736
737 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
738
739 struct PIC_BUFFER_CONFIG_s *frame_to_show;
740 struct RefCntBuffer_s *prev_frame;
741
742 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
743 struct RefCntBuffer_s *cur_frame;
744
745 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
746
747 /*Prepare ref_frame_map for the next frame.
748 *Only used in frame parallel decode.
749 */
750 int next_ref_frame_map[REF_FRAMES];
751
752 /* TODO(jkoleszar): could expand active_ref_idx to 4,
753 *with 0 as intra, and roll new_fb_idx into it.
754 */
755
756 /*Each frame can reference REFS_PER_FRAME buffers*/
757 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
758
759 int prev_fb_idx;
760 int new_fb_idx;
761 int cur_fb_idx_mmu;
762 /*last frame's frame type for motion search*/
763 enum FRAME_TYPE last_frame_type;
764 enum FRAME_TYPE frame_type;
765
766 int show_frame;
767 int last_show_frame;
768 int show_existing_frame;
769
770 /*Flag signaling that the frame is encoded using only INTRA modes.*/
771 uint8_t intra_only;
772 uint8_t last_intra_only;
773
774 int allow_high_precision_mv;
775
776 /*Flag signaling that the frame context should be reset to default
777 *values. 0 or 1 implies don't reset, 2 reset just the context
778 *specified in the frame header, 3 reset all contexts.
779 */
780 int reset_frame_context;
781
782 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
783 * MODE_INFO (8-pixel) units.
784 */
785 int MBs;
786 int mb_rows, mi_rows;
787 int mb_cols, mi_cols;
788 int mi_stride;
789
790 /*Whether to use previous frame's motion vectors for prediction.*/
791 int use_prev_frame_mvs;
792
793 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
794
795 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
796
797 /*struct loopfilter lf;*/
798 /*struct segmentation seg;*/
799
800 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
801 /* in pbi.*/
802 int frame_parallel_decode; /* frame-based threading.*/
803
804 /*Context probabilities for reference frame prediction*/
805 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
806 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
807 enum REFERENCE_MODE reference_mode;
808
809 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
810 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
811 /*unsigned int frame_context_idx; *//* Context to use/update */
812 /*FRAME_COUNTS counts;*/
813
814 unsigned int current_video_frame;
815 enum BITSTREAM_PROFILE profile;
816
817 enum vpx_bit_depth_t bit_depth;
818
819 int error_resilient_mode;
820 int frame_parallel_decoding_mode;
821
822 int byte_alignment;
823 int skip_loop_filter;
824
825 /*External BufferPool passed from outside.*/
826 struct BufferPool_s *buffer_pool;
827
828 int above_context_alloc_cols;
829
830};
831
832static void set_canvas(struct VP9Decoder_s *pbi,
833 struct PIC_BUFFER_CONFIG_s *pic_config);
834static int prepare_display_buf(struct VP9Decoder_s *pbi,
835 struct PIC_BUFFER_CONFIG_s *pic_config);
836
837static void fill_frame_info(struct VP9Decoder_s *pbi,
838 struct PIC_BUFFER_CONFIG_s *frame,
839 unsigned int framesize,
840 unsigned int pts);
841
842static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
843{
844 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
845}
846
847static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
848{
849 const int ref_index = *idx;
850
851 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
852 bufs[ref_index].ref_count--;
853 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
854 * ref_index, bufs[ref_index].ref_count);
855 */
856 }
857
858 *idx = new_idx;
859
860 bufs[new_idx].ref_count++;
861 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
862 * new_idx, bufs[new_idx].ref_count);
863 */
864}
865
866int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
867{
868 struct InternalFrameBuffer_s *const int_fb =
869 (struct InternalFrameBuffer_s *)fb->priv;
870 if (int_fb)
871 int_fb->in_use = 0;
872 return 0;
873}
874
875static int compute_losless_comp_body_size(int width, int height,
876 uint8_t is_bit_depth_10);
877
878static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
879 int print_header_info)
880{
881 cm->display_width = cm->width;
882 cm->display_height = cm->height;
883 if (params->p.display_size_present) {
884 if (print_header_info)
885 pr_info(" * 1-bit display_size_present read : 1\n");
886 cm->display_width = params->p.display_width;
887 cm->display_height = params->p.display_height;
888 /*vp9_read_frame_size(rb, &cm->display_width,
889 * &cm->display_height);
890 */
891 } else {
892 if (print_header_info)
893 pr_info(" * 1-bit display_size_present read : 0\n");
894 }
895}
896
897
898uint8_t print_header_info = 0;
899
900struct buff_s {
901 u32 buf_start;
902 u32 buf_size;
903 u32 buf_end;
904} buff_t;
905
906struct BuffInfo_s {
907 u32 max_width;
908 u32 max_height;
909 u32 start_adr;
910 u32 end_adr;
911 struct buff_s ipp;
912 struct buff_s sao_abv;
913 struct buff_s sao_vb;
914 struct buff_s short_term_rps;
915 struct buff_s vps;
916 struct buff_s sps;
917 struct buff_s pps;
918 struct buff_s sao_up;
919 struct buff_s swap_buf;
920 struct buff_s swap_buf2;
921 struct buff_s scalelut;
922 struct buff_s dblk_para;
923 struct buff_s dblk_data;
924 struct buff_s seg_map;
925 struct buff_s mmu_vbh;
926 struct buff_s cm_header;
927 struct buff_s mpred_above;
928#ifdef MV_USE_FIXED_BUF
929 struct buff_s mpred_mv;
930#endif
931 struct buff_s rpm;
932 struct buff_s lmem;
933} BuffInfo_t;
934#ifdef MULTI_INSTANCE_SUPPORT
935#define DEC_RESULT_NONE 0
936#define DEC_RESULT_DONE 1
937#define DEC_RESULT_AGAIN 2
938#define DEC_RESULT_CONFIG_PARAM 3
939#define DEC_RESULT_ERROR 4
940#define DEC_INIT_PICLIST 5
941#define DEC_UNINIT_PICLIST 6
942#define DEC_RESULT_GET_DATA 7
943#define DEC_RESULT_GET_DATA_RETRY 8
944#define DEC_RESULT_EOS 9
945#define DEC_RESULT_FORCE_EXIT 10
946#define DEC_V4L2_CONTINUE_DECODING 18
947
948#define DEC_S1_RESULT_NONE 0
949#define DEC_S1_RESULT_DONE 1
950#define DEC_S1_RESULT_FORCE_EXIT 2
951#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
952
953#ifdef FB_DECODING_TEST_SCHEDULE
954#define TEST_SET_NONE 0
955#define TEST_SET_PIC_DONE 1
956#define TEST_SET_S2_DONE 2
957#endif
958
959static void vp9_work(struct work_struct *work);
960#endif
961struct loop_filter_info_n;
962struct loopfilter;
963struct segmentation;
964
965#ifdef SUPPORT_FB_DECODING
966static void mpred_process(struct VP9Decoder_s *pbi);
967static void vp9_s1_work(struct work_struct *work);
968
969struct stage_buf_s {
970 int index;
971 unsigned short rpm[RPM_END - RPM_BEGIN];
972};
973
974static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
975
976static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
977
978#ifdef FB_DECODING_TEST_SCHEDULE
979u32 stage_buf_num; /* = 16;*/
980#else
981u32 stage_buf_num;
982#endif
983#endif
984
985struct VP9Decoder_s {
986#ifdef MULTI_INSTANCE_SUPPORT
987 unsigned char index;
988
989 struct device *cma_dev;
990 struct platform_device *platform_dev;
991 void (*vdec_cb)(struct vdec_s *, void *);
992 void *vdec_cb_arg;
993 struct vframe_chunk_s *chunk;
994 int dec_result;
995 struct work_struct work;
996 struct work_struct set_clk_work;
997 u32 start_shift_bytes;
998
999 struct BuffInfo_s work_space_buf_store;
1000 unsigned long buf_start;
1001 u32 buf_size;
1002 u32 cma_alloc_count;
1003 unsigned long cma_alloc_addr;
1004 uint8_t eos;
1005 unsigned long int start_process_time;
1006 unsigned last_lcu_idx;
1007 int decode_timeout_count;
1008 unsigned timeout_num;
1009 int save_buffer_mode;
1010
1011 int double_write_mode;
1012#endif
1013 long used_4k_num;
1014
1015 unsigned char m_ins_flag;
1016 char *provider_name;
1017 union param_u param;
1018 int frame_count;
1019 int pic_count;
1020 u32 stat;
1021 struct timer_list timer;
1022 u32 frame_dur;
1023 u32 frame_ar;
1024 int fatal_error;
1025 uint8_t init_flag;
1026 uint8_t first_sc_checked;
1027 uint8_t process_busy;
1028#define PROC_STATE_INIT 0
1029#define PROC_STATE_DECODESLICE 1
1030#define PROC_STATE_SENDAGAIN 2
1031 uint8_t process_state;
1032 u32 ucode_pause_pos;
1033
1034 int show_frame_num;
1035 struct buff_s mc_buf_spec;
1036 struct dec_sysinfo vvp9_amstream_dec_info;
1037 void *rpm_addr;
1038 void *lmem_addr;
1039 dma_addr_t rpm_phy_addr;
1040 dma_addr_t lmem_phy_addr;
1041 unsigned short *lmem_ptr;
1042 unsigned short *debug_ptr;
1043
1044 void *prob_buffer_addr;
1045 void *count_buffer_addr;
1046 dma_addr_t prob_buffer_phy_addr;
1047 dma_addr_t count_buffer_phy_addr;
1048
1049 void *frame_mmu_map_addr;
1050 dma_addr_t frame_mmu_map_phy_addr;
1051
1052 unsigned int use_cma_flag;
1053
1054 struct BUF_s m_BUF[MAX_BUF_NUM];
1055 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1056 u32 used_buf_num;
1057 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1058 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1059 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1060 struct vframe_s vfpool[VF_POOL_SIZE];
1061 u32 vf_pre_count;
1062 u32 vf_get_count;
1063 u32 vf_put_count;
1064 int buf_num;
1065 int pic_num;
1066 int lcu_size_log2;
1067 unsigned int losless_comp_body_size;
1068
1069 u32 video_signal_type;
1070
1071 int pts_mode;
1072 int last_lookup_pts;
1073 int last_pts;
1074 u64 last_lookup_pts_us64;
1075 u64 last_pts_us64;
1076 u64 shift_byte_count;
1077
1078 u32 pts_unstable;
1079 u32 frame_cnt_window;
1080 u32 pts1, pts2;
1081 u32 last_duration;
1082 u32 duration_from_pts_done;
1083 bool vp9_first_pts_ready;
1084
1085 u32 shift_byte_count_lo;
1086 u32 shift_byte_count_hi;
1087 int pts_mode_switching_count;
1088 int pts_mode_recovery_count;
1089
1090 bool get_frame_dur;
1091 u32 saved_resolution;
1092
1093 /**/
1094 struct VP9_Common_s common;
1095 struct RefCntBuffer_s *cur_buf;
1096 int refresh_frame_flags;
1097 uint8_t need_resync;
1098 uint8_t hold_ref_buf;
1099 uint8_t ready_for_new_data;
1100 struct BufferPool_s vp9_buffer_pool;
1101
1102 struct BuffInfo_s *work_space_buf;
1103
1104 struct buff_s *mc_buf;
1105
1106 unsigned int frame_width;
1107 unsigned int frame_height;
1108
1109 unsigned short *rpm_ptr;
1110 int init_pic_w;
1111 int init_pic_h;
1112 int lcu_total;
1113 int lcu_size;
1114
1115 int slice_type;
1116
1117 int skip_flag;
1118 int decode_idx;
1119 int slice_idx;
1120 uint8_t has_keyframe;
1121 uint8_t wait_buf;
1122 uint8_t error_flag;
1123
1124 /* bit 0, for decoding; bit 1, for displaying */
1125 uint8_t ignore_bufmgr_error;
1126 int PB_skip_mode;
1127 int PB_skip_count_after_decoding;
1128 /*hw*/
1129
1130 /*lf*/
1131 int default_filt_lvl;
1132 struct loop_filter_info_n *lfi;
1133 struct loopfilter *lf;
1134 struct segmentation *seg_4lf;
1135 /**/
1136 struct vdec_info *gvs;
1137
1138 u32 pre_stream_offset;
1139
1140 unsigned int dec_status;
1141 u32 last_put_idx;
1142 int new_frame_displayed;
1143 void *mmu_box;
1144 void *bmmu_box;
1145 int mmu_enable;
1146 struct vframe_master_display_colour_s vf_dp;
1147 struct firmware_s *fw;
1148 int max_pic_w;
1149 int max_pic_h;
1150#ifdef SUPPORT_FB_DECODING
1151 int dec_s1_result;
1152 int s1_test_cmd;
1153 struct work_struct s1_work;
1154 int used_stage_buf_num;
1155 int s1_pos;
1156 int s2_pos;
1157 void *stage_mmu_map_addr;
1158 dma_addr_t stage_mmu_map_phy_addr;
1159 struct stage_buf_s *s1_buf;
1160 struct stage_buf_s *s2_buf;
1161 struct stage_buf_s *stage_bufs
1162 [STAGE_MAX_BUFFERS];
1163 unsigned char run2_busy;
1164
1165 int s1_mv_buf_index;
1166 int s1_mv_buf_index_pre;
1167 int s1_mv_buf_index_pre_pre;
1168 unsigned long s1_mpred_mv_wr_start_addr;
1169 unsigned long s1_mpred_mv_wr_start_addr_pre;
1170 unsigned short s1_intra_only;
1171 unsigned short s1_frame_type;
1172 unsigned short s1_width;
1173 unsigned short s1_height;
1174 unsigned short s1_last_show_frame;
1175 union param_u s1_param;
1176 u8 back_not_run_ready;
1177#endif
1178 int need_cache_size;
1179 u64 sc_start_time;
1180 bool postproc_done;
1181 int low_latency_flag;
1182 bool no_head;
1183 bool pic_list_init_done;
1184 bool pic_list_init_done2;
1185 bool is_used_v4l;
1186 void *v4l2_ctx;
1187 bool v4l_params_parsed;
1188 int frameinfo_enable;
1189 struct vframe_qos_s vframe_qos;
1190 u32 mem_map_mode;
1191 u32 dynamic_buf_num_margin;
1192 struct vframe_s vframe_dummy;
1193};
1194
1195static int vp9_print(struct VP9Decoder_s *pbi,
1196 int flag, const char *fmt, ...)
1197{
1198#define HEVC_PRINT_BUF 256
1199 unsigned char buf[HEVC_PRINT_BUF];
1200 int len = 0;
1201
1202 if (pbi == NULL ||
1203 (flag == 0) ||
1204 (debug & flag)) {
1205 va_list args;
1206
1207 va_start(args, fmt);
1208 if (pbi)
1209 len = sprintf(buf, "[%d]", pbi->index);
1210 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1211 pr_debug("%s", buf);
1212 va_end(args);
1213 }
1214 return 0;
1215}
1216
1217static int is_oversize(int w, int h)
1218{
1219 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1220 MAX_SIZE_8K : MAX_SIZE_4K;
1221
1222 if (w <= 0 || h <= 0)
1223 return true;
1224
1225 if (h != 0 && (w > max / h))
1226 return true;
1227
1228 return false;
1229}
1230
1231static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1232 struct PIC_BUFFER_CONFIG_s *pic);
1233
1234static void resize_context_buffers(struct VP9Decoder_s *pbi,
1235 struct VP9_Common_s *cm, int width, int height)
1236{
1237 if (cm->width != width || cm->height != height) {
1238 /* to do ..*/
1239 if (pbi != NULL) {
1240 pbi->vp9_first_pts_ready = 0;
1241 pbi->duration_from_pts_done = 0;
1242 }
1243 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1244 cm->height, width, height);
1245
1246 if (pbi->is_used_v4l) {
1247 struct PIC_BUFFER_CONFIG_s *pic = &cm->cur_frame->buf;
1248
1249 /* resolution change happend need to reconfig buffs if true. */
1250 if (pic->y_crop_width != width || pic->y_crop_height != height) {
1251 int i;
1252 for (i = 0; i < pbi->used_buf_num; i++) {
1253 pic = &cm->buffer_pool->frame_bufs[i].buf;
1254 pic->y_crop_width = width;
1255 pic->y_crop_height = height;
1256 if (!v4l_alloc_and_config_pic(pbi, pic))
1257 set_canvas(pbi, pic);
1258 else
1259 vp9_print(pbi, 0,
1260 "v4l: reconfig buff fail.\n");
1261 }
1262 }
1263 }
1264
1265 cm->width = width;
1266 cm->height = height;
1267 }
1268 /*
1269 *if (cm->cur_frame->mvs == NULL ||
1270 * cm->mi_rows > cm->cur_frame->mi_rows ||
1271 * cm->mi_cols > cm->cur_frame->mi_cols) {
1272 * resize_mv_buffer(cm);
1273 *}
1274 */
1275}
1276
1277static int valid_ref_frame_size(int ref_width, int ref_height,
1278 int this_width, int this_height) {
1279 return 2 * this_width >= ref_width &&
1280 2 * this_height >= ref_height &&
1281 this_width <= 16 * ref_width &&
1282 this_height <= 16 * ref_height;
1283}
1284
1285/*
1286 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1287 * int ref_xss, int ref_yss,
1288 * enum vpx_bit_depth_t this_bit_depth,
1289 * int this_xss, int this_yss) {
1290 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1291 * ref_yss == this_yss;
1292 *}
1293 */
1294
1295
1296static int setup_frame_size(
1297 struct VP9Decoder_s *pbi,
1298 struct VP9_Common_s *cm, union param_u *params,
1299 unsigned int *mmu_index_adr,
1300 int print_header_info) {
1301 int width, height;
1302 struct BufferPool_s * const pool = cm->buffer_pool;
1303 struct PIC_BUFFER_CONFIG_s *ybf;
1304 int ret = 0;
1305
1306 width = params->p.width;
1307 height = params->p.height;
1308 if (is_oversize(width, height)) {
1309 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1310 return -1;
1311 }
1312
1313 /*vp9_read_frame_size(rb, &width, &height);*/
1314 if (print_header_info)
1315 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1316 if (print_header_info)
1317 pr_info
1318 (" * 16-bits h read : %d (height : %d)\n", width, height);
1319
1320 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1321#ifdef VP9_10B_HED_FB
1322 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1323#endif
1324 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1325 ret = vp9_alloc_mmu(pbi,
1326 cm->new_fb_idx,
1327 params->p.width,
1328 params->p.height,
1329 params->p.bit_depth,
1330 mmu_index_adr);
1331 if (ret != 0) {
1332 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1333 cm->new_fb_idx,
1334 ret);
1335 return ret;
1336 }
1337 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1338 }
1339
1340 resize_context_buffers(pbi, cm, width, height);
1341 setup_display_size(cm, params, print_header_info);
1342#if 0
1343 lock_buffer_pool(pool);
1344 if (vp9_realloc_frame_buffer(
1345 get_frame_new_buffer(cm), cm->width, cm->height,
1346 cm->subsampling_x, cm->subsampling_y,
1347#if CONFIG_VP9_HIGHBITDEPTH
1348 cm->use_highbitdepth,
1349#endif
1350 VP9_DEC_BORDER_IN_PIXELS,
1351 cm->byte_alignment,
1352 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1353 pool->get_fb_cb, pool->cb_priv)) {
1354 unlock_buffer_pool(pool);
1355 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1356 "Failed to allocate frame buffer");
1357 }
1358 unlock_buffer_pool(pool);
1359#else
1360 /* porting */
1361 ybf = get_frame_new_buffer(cm);
1362 if (!ybf)
1363 return -1;
1364
1365 ybf->y_crop_width = width;
1366 ybf->y_crop_height = height;
1367 ybf->bit_depth = params->p.bit_depth;
1368#endif
1369 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1370 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1371 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1372 (unsigned int)cm->bit_depth;
1373 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1374 return ret;
1375}
1376
1377static int setup_frame_size_with_refs(
1378 struct VP9Decoder_s *pbi,
1379 struct VP9_Common_s *cm,
1380 union param_u *params,
1381 unsigned int *mmu_index_adr,
1382 int print_header_info) {
1383
1384 int width, height;
1385 int found = 0, i;
1386 int has_valid_ref_frame = 0;
1387 struct PIC_BUFFER_CONFIG_s *ybf;
1388 struct BufferPool_s * const pool = cm->buffer_pool;
1389 int ret = 0;
1390
1391 for (i = 0; i < REFS_PER_FRAME; ++i) {
1392 if ((params->p.same_frame_size >>
1393 (REFS_PER_FRAME - i - 1)) & 0x1) {
1394 struct PIC_BUFFER_CONFIG_s *const buf =
1395 cm->frame_refs[i].buf;
1396 /*if (print_header_info)
1397 * pr_info
1398 * ("1-bit same_frame_size[%d] read : 1\n", i);
1399 */
1400 width = buf->y_crop_width;
1401 height = buf->y_crop_height;
1402 /*if (print_header_info)
1403 * pr_info
1404 * (" - same_frame_size width : %d\n", width);
1405 */
1406 /*if (print_header_info)
1407 * pr_info
1408 * (" - same_frame_size height : %d\n", height);
1409 */
1410 found = 1;
1411 break;
1412 } else {
1413 /*if (print_header_info)
1414 * pr_info
1415 * ("1-bit same_frame_size[%d] read : 0\n", i);
1416 */
1417 }
1418 }
1419
1420 if (!found) {
1421 /*vp9_read_frame_size(rb, &width, &height);*/
1422 width = params->p.width;
1423 height = params->p.height;
1424 /*if (print_header_info)
1425 * pr_info
1426 * (" * 16-bits w read : %d (width : %d)\n",
1427 * width, height);
1428 *if (print_header_info)
1429 * pr_info
1430 * (" * 16-bits h read : %d (height : %d)\n",
1431 * width, height);
1432 */
1433 }
1434
1435 if (is_oversize(width, height)) {
1436 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1437 return -1;
1438 }
1439
1440 params->p.width = width;
1441 params->p.height = height;
1442
1443 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1444 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1445 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1446 *cm->prev_fb_idx = cm->new_fb_idx;
1447 */
1448 /* pr_info
1449 * ("[DEBUG DEBUG]Before alloc_mmu,
1450 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1451 * cm->prev_fb_idx, cm->new_fb_idx);
1452 */
1453 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1454 params->p.width, params->p.height,
1455 params->p.bit_depth, mmu_index_adr);
1456 if (ret != 0) {
1457 pr_err("can't alloc need mmu,idx %d\r\n",
1458 cm->new_fb_idx);
1459 return ret;
1460 }
1461 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1462 }
1463
1464 /*Check to make sure at least one of frames that this frame references
1465 *has valid dimensions.
1466 */
1467 for (i = 0; i < REFS_PER_FRAME; ++i) {
1468 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1469
1470 has_valid_ref_frame |=
1471 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1472 ref_frame->buf->y_crop_height,
1473 width, height);
1474 }
1475 if (!has_valid_ref_frame) {
1476 pr_err("Error: Referenced frame has invalid size\r\n");
1477 return -1;
1478 }
1479#if 0
1480 for (i = 0; i < REFS_PER_FRAME; ++i) {
1481 struct RefBuffer_s * const ref_frame =
1482 &cm->frame_refs[i];
1483 if (!valid_ref_frame_img_fmt(
1484 ref_frame->buf->bit_depth,
1485 ref_frame->buf->subsampling_x,
1486 ref_frame->buf->subsampling_y,
1487 cm->bit_depth,
1488 cm->subsampling_x,
1489 cm->subsampling_y))
1490 pr_err
1491 ("Referenced frame incompatible color fmt\r\n");
1492 return -1;
1493 }
1494#endif
1495 resize_context_buffers(pbi, cm, width, height);
1496 setup_display_size(cm, params, print_header_info);
1497
1498#if 0
1499 lock_buffer_pool(pool);
1500 if (vp9_realloc_frame_buffer(
1501 get_frame_new_buffer(cm), cm->width, cm->height,
1502 cm->subsampling_x, cm->subsampling_y,
1503#if CONFIG_VP9_HIGHBITDEPTH
1504 cm->use_highbitdepth,
1505#endif
1506 VP9_DEC_BORDER_IN_PIXELS,
1507 cm->byte_alignment,
1508 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1509 pool->get_fb_cb,
1510 pool->cb_priv)) {
1511 unlock_buffer_pool(pool);
1512 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1513 "Failed to allocate frame buffer");
1514 }
1515 unlock_buffer_pool(pool);
1516#else
1517 /* porting */
1518 ybf = get_frame_new_buffer(cm);
1519 if (!ybf)
1520 return -1;
1521
1522 ybf->y_crop_width = width;
1523 ybf->y_crop_height = height;
1524 ybf->bit_depth = params->p.bit_depth;
1525#endif
1526 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1527 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1528 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1529 (unsigned int)cm->bit_depth;
1530 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1531 return ret;
1532}
1533
1534static inline bool close_to(int a, int b, int m)
1535{
1536 return (abs(a - b) < m) ? true : false;
1537}
1538
1539#ifdef MULTI_INSTANCE_SUPPORT
1540static int vp9_print_cont(struct VP9Decoder_s *pbi,
1541 int flag, const char *fmt, ...)
1542{
1543 unsigned char buf[HEVC_PRINT_BUF];
1544 int len = 0;
1545
1546 if (pbi == NULL ||
1547 (flag == 0) ||
1548 (debug & flag)) {
1549 va_list args;
1550
1551 va_start(args, fmt);
1552 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1553 pr_debug("%s", buf);
1554 va_end(args);
1555 }
1556 return 0;
1557}
1558
1559static void trigger_schedule(struct VP9Decoder_s *pbi)
1560{
1561 if (pbi->is_used_v4l) {
1562 struct aml_vcodec_ctx *ctx =
1563 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1564
1565 if (ctx->param_sets_from_ucode &&
1566 !pbi->v4l_params_parsed)
1567 vdec_v4l_write_frame_sync(ctx);
1568 }
1569
1570 if (pbi->vdec_cb)
1571 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1572}
1573
1574static void reset_process_time(struct VP9Decoder_s *pbi)
1575{
1576 if (pbi->start_process_time) {
1577 unsigned process_time =
1578 1000 * (jiffies - pbi->start_process_time) / HZ;
1579 pbi->start_process_time = 0;
1580 if (process_time > max_process_time[pbi->index])
1581 max_process_time[pbi->index] = process_time;
1582 }
1583}
1584
1585static void start_process_time(struct VP9Decoder_s *pbi)
1586{
1587 pbi->start_process_time = jiffies;
1588 pbi->decode_timeout_count = 0;
1589 pbi->last_lcu_idx = 0;
1590}
1591
1592static void timeout_process(struct VP9Decoder_s *pbi)
1593{
1594 pbi->timeout_num++;
1595 amhevc_stop();
1596 vp9_print(pbi,
1597 0, "%s decoder timeout\n", __func__);
1598
1599 pbi->dec_result = DEC_RESULT_DONE;
1600 reset_process_time(pbi);
1601 vdec_schedule_work(&pbi->work);
1602}
1603
1604static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1605{
1606 return ((double_write_mode & 0x80000000) == 0) ?
1607 pbi->double_write_mode :
1608 (double_write_mode & 0x7fffffff);
1609}
1610
1611static int get_double_write_mode(struct VP9Decoder_s *pbi)
1612{
1613 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1614 u32 dw;
1615 int w, h;
1616 struct VP9_Common_s *cm = &pbi->common;
1617 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1618
1619 /* mask for supporting double write value bigger than 0x100 */
1620 if (valid_dw_mode & 0xffffff00) {
1621 if (!cm->cur_frame)
1622 return 1;/*no valid frame,*/
1623 cur_pic_config = &cm->cur_frame->buf;
1624 w = cur_pic_config->y_crop_width;
1625 h = cur_pic_config->y_crop_height;
1626
1627 dw = 0x1; /*1:1*/
1628 switch (valid_dw_mode) {
1629 case 0x100:
1630 if (w > 1920 && h > 1088)
1631 dw = 0x4; /*1:2*/
1632 break;
1633 case 0x200:
1634 if (w > 1920 && h > 1088)
1635 dw = 0x2; /*1:4*/
1636 break;
1637 case 0x300:
1638 if (w > 1280 && h > 720)
1639 dw = 0x4; /*1:2*/
1640 break;
1641 default:
1642 break;
1643 }
1644 return dw;
1645 }
1646
1647 return valid_dw_mode;
1648}
1649
1650/* for double write buf alloc */
1651static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1652{
1653 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1654 u32 dw;
1655 int w = pbi->init_pic_w;
1656 int h = pbi->init_pic_h;
1657
1658 dw = 0x1; /*1:1*/
1659 switch (valid_dw_mode) {
1660 case 0x100:
1661 if (w > 1920 && h > 1088)
1662 dw = 0x4; /*1:2*/
1663 break;
1664 case 0x200:
1665 if (w > 1920 && h > 1088)
1666 dw = 0x2; /*1:4*/
1667 break;
1668 case 0x300:
1669 if (w > 1280 && h > 720)
1670 dw = 0x4; /*1:2*/
1671 break;
1672 default:
1673 dw = valid_dw_mode;
1674 break;
1675 }
1676 return dw;
1677}
1678#endif
1679
1680static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1681 int dw_mode)
1682{
1683 int ratio = 1;
1684 if ((dw_mode == 2) ||
1685 (dw_mode == 3))
1686 ratio = 4;
1687 else if (dw_mode == 4)
1688 ratio = 2;
1689 return ratio;
1690}
1691
1692//#define MAX_4K_NUM 0x1200
1693
1694int vp9_alloc_mmu(
1695 struct VP9Decoder_s *pbi,
1696 int cur_buf_idx,
1697 int pic_width,
1698 int pic_height,
1699 unsigned short bit_depth,
1700 unsigned int *mmu_index_adr)
1701{
1702 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1703 int picture_size;
1704 int cur_mmu_4k_number, max_frame_num;
1705 if (!pbi->mmu_box) {
1706 pr_err("error no mmu box!\n");
1707 return -1;
1708 }
1709 if (pbi->double_write_mode & 0x10)
1710 return 0;
1711 if (bit_depth >= VPX_BITS_12) {
1712 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1713 pr_err("fatal_error, un support bit depth 12!\n\n");
1714 return -1;
1715 }
1716 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1717 bit_depth_10);
1718 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1719
1720 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1721 max_frame_num = MAX_FRAME_8K_NUM;
1722 else
1723 max_frame_num = MAX_FRAME_4K_NUM;
1724
1725 if (cur_mmu_4k_number > max_frame_num) {
1726 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1727 cur_mmu_4k_number, pic_width, pic_height);
1728 return -1;
1729 }
1730 return decoder_mmu_box_alloc_idx(
1731 pbi->mmu_box,
1732 cur_buf_idx,
1733 cur_mmu_4k_number,
1734 mmu_index_adr);
1735}
1736
1737
1738#ifndef MV_USE_FIXED_BUF
1739static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1740{
1741 int i;
1742 for (i = 0; i < MV_BUFFER_NUM; i++) {
1743 if (pbi->m_mv_BUF[i].start_adr) {
1744 if (debug)
1745 pr_info(
1746 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1747 i, pbi->m_mv_BUF[i].start_adr,
1748 pbi->m_mv_BUF[i].size,
1749 pbi->m_mv_BUF[i].used_flag);
1750 decoder_bmmu_box_free_idx(
1751 pbi->bmmu_box,
1752 MV_BUFFER_IDX(i));
1753 pbi->m_mv_BUF[i].start_adr = 0;
1754 pbi->m_mv_BUF[i].size = 0;
1755 pbi->m_mv_BUF[i].used_flag = 0;
1756 }
1757 }
1758}
1759
1760static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1761 int i, int size)
1762{
1763 int ret = 0;
1764 if (decoder_bmmu_box_alloc_buf_phy
1765 (pbi->bmmu_box,
1766 MV_BUFFER_IDX(i), size,
1767 DRIVER_NAME,
1768 &pbi->m_mv_BUF[i].start_adr) < 0) {
1769 pbi->m_mv_BUF[i].start_adr = 0;
1770 ret = -1;
1771 } else {
1772 pbi->m_mv_BUF[i].size = size;
1773 pbi->m_mv_BUF[i].used_flag = 0;
1774 ret = 0;
1775 if (debug) {
1776 pr_info(
1777 "MV Buffer %d: start_adr %p size %x\n",
1778 i,
1779 (void *)pbi->m_mv_BUF[i].start_adr,
1780 pbi->m_mv_BUF[i].size);
1781 }
1782 }
1783 return ret;
1784}
1785
1786static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1787{
1788 int i;
1789 int ret = 0;
1790 int count = MV_BUFFER_NUM;
1791 int pic_width = pbi->init_pic_w;
1792 int pic_height = pbi->init_pic_h;
1793 int lcu_size = 64; /*fixed 64*/
1794 int pic_width_64 = (pic_width + 63) & (~0x3f);
1795 int pic_height_32 = (pic_height + 31) & (~0x1f);
1796 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1797 pic_width_64 / lcu_size + 1
1798 : pic_width_64 / lcu_size;
1799 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1800 pic_height_32 / lcu_size + 1
1801 : pic_height_32 / lcu_size;
1802 int lcu_total = pic_width_lcu * pic_height_lcu;
1803 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1804 (~0xffff);
1805 if (mv_buf_margin > 0)
1806 count = REF_FRAMES + mv_buf_margin;
1807
1808 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1809 count = REF_FRAMES_4K + mv_buf_margin;
1810
1811 if (debug) {
1812 pr_info("%s w:%d, h:%d, count: %d\n",
1813 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1814 }
1815
1816 for (i = 0;
1817 i < count && i < MV_BUFFER_NUM; i++) {
1818 if (alloc_mv_buf(pbi, i, size) < 0) {
1819 ret = -1;
1820 break;
1821 }
1822 }
1823 return ret;
1824}
1825
1826static int get_mv_buf(struct VP9Decoder_s *pbi,
1827 int *mv_buf_index,
1828 unsigned long *mpred_mv_wr_start_addr)
1829{
1830 int i;
1831 int ret = -1;
1832 for (i = 0; i < MV_BUFFER_NUM; i++) {
1833 if (pbi->m_mv_BUF[i].start_adr &&
1834 pbi->m_mv_BUF[i].used_flag == 0) {
1835 pbi->m_mv_BUF[i].used_flag = 1;
1836 ret = i;
1837 break;
1838 }
1839 }
1840
1841 if (ret >= 0) {
1842 *mv_buf_index = ret;
1843 *mpred_mv_wr_start_addr =
1844 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1845 (~0xffff);
1846 if (debug & VP9_DEBUG_BUFMGR_MORE)
1847 pr_info(
1848 "%s => %d (%ld) size 0x%x\n",
1849 __func__, ret,
1850 *mpred_mv_wr_start_addr,
1851 pbi->m_mv_BUF[ret].size);
1852 } else {
1853 pr_info(
1854 "%s: Error, mv buf is not enough\n",
1855 __func__);
1856 }
1857 return ret;
1858}
1859
1860static void put_mv_buf(struct VP9Decoder_s *pbi,
1861 int *mv_buf_index)
1862{
1863 int i = *mv_buf_index;
1864 if (i >= MV_BUFFER_NUM) {
1865 if (debug & VP9_DEBUG_BUFMGR_MORE)
1866 pr_info(
1867 "%s: index %d beyond range\n",
1868 __func__, i);
1869 return;
1870 }
1871 if (debug & VP9_DEBUG_BUFMGR_MORE)
1872 pr_info(
1873 "%s(%d): used_flag(%d)\n",
1874 __func__, i,
1875 pbi->m_mv_BUF[i].used_flag);
1876
1877 *mv_buf_index = -1;
1878 if (pbi->m_mv_BUF[i].start_adr &&
1879 pbi->m_mv_BUF[i].used_flag)
1880 pbi->m_mv_BUF[i].used_flag = 0;
1881}
1882
1883static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1884{
1885 struct VP9_Common_s *const cm = &pbi->common;
1886 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1887 int i;
1888 for (i = 0; i < pbi->used_buf_num; ++i) {
1889 if ((frame_bufs[i].ref_count == 0) &&
1890 (frame_bufs[i].buf.index != -1) &&
1891 (frame_bufs[i].buf.mv_buf_index >= 0)
1892 )
1893 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1894 }
1895}
1896
1897#ifdef SUPPORT_FB_DECODING
1898static bool mv_buf_available(struct VP9Decoder_s *pbi)
1899{
1900 int i;
1901 bool ret = 0;
1902 for (i = 0; i < MV_BUFFER_NUM; i++) {
1903 if (pbi->m_mv_BUF[i].start_adr &&
1904 pbi->m_mv_BUF[i].used_flag == 0) {
1905 ret = 1;
1906 break;
1907 }
1908 }
1909 return ret;
1910}
1911#endif
1912#endif
1913
1914#ifdef SUPPORT_FB_DECODING
1915static void init_stage_buf(struct VP9Decoder_s *pbi)
1916{
1917 uint i;
1918 for (i = 0; i < STAGE_MAX_BUFFERS
1919 && i < stage_buf_num; i++) {
1920 pbi->stage_bufs[i] =
1921 vmalloc(sizeof(struct stage_buf_s));
1922 if (pbi->stage_bufs[i] == NULL) {
1923 vp9_print(pbi,
1924 0, "%s vmalloc fail\n", __func__);
1925 break;
1926 }
1927 pbi->stage_bufs[i]->index = i;
1928 }
1929 pbi->used_stage_buf_num = i;
1930 pbi->s1_pos = 0;
1931 pbi->s2_pos = 0;
1932 pbi->s1_buf = NULL;
1933 pbi->s2_buf = NULL;
1934 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1935 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1936 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1937
1938 if (pbi->used_stage_buf_num > 0)
1939 vp9_print(pbi,
1940 0, "%s 2 stage decoding buf %d\n",
1941 __func__,
1942 pbi->used_stage_buf_num);
1943}
1944
1945static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1946{
1947 int i;
1948 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1949 if (pbi->stage_bufs[i])
1950 vfree(pbi->stage_bufs[i]);
1951 pbi->stage_bufs[i] = NULL;
1952 }
1953 pbi->used_stage_buf_num = 0;
1954 pbi->s1_pos = 0;
1955 pbi->s2_pos = 0;
1956 pbi->s1_buf = NULL;
1957 pbi->s2_buf = NULL;
1958}
1959
1960static int get_s1_buf(
1961 struct VP9Decoder_s *pbi)
1962{
1963 struct stage_buf_s *buf = NULL;
1964 int ret = -1;
1965 int buf_page_num = MAX_STAGE_PAGE_NUM;
1966 int next_s1_pos = pbi->s1_pos + 1;
1967
1968 if (next_s1_pos >= pbi->used_stage_buf_num)
1969 next_s1_pos = 0;
1970 if (next_s1_pos == pbi->s2_pos) {
1971 pbi->s1_buf = NULL;
1972 return ret;
1973 }
1974
1975 buf = pbi->stage_bufs[pbi->s1_pos];
1976 ret = decoder_mmu_box_alloc_idx(
1977 pbi->mmu_box,
1978 buf->index,
1979 buf_page_num,
1980 pbi->stage_mmu_map_addr);
1981 if (ret < 0) {
1982 vp9_print(pbi, 0,
1983 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1984 __func__, buf->index,
1985 pbi->s1_pos, pbi->s2_pos);
1986 buf = NULL;
1987 } else {
1988 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1989 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1990 __func__, buf_page_num, buf->index,
1991 pbi->s1_pos, pbi->s2_pos);
1992 }
1993 pbi->s1_buf = buf;
1994 return ret;
1995}
1996
1997static void inc_s1_pos(struct VP9Decoder_s *pbi)
1998{
1999 struct stage_buf_s *buf =
2000 pbi->stage_bufs[pbi->s1_pos];
2001
2002 int used_page_num =
2003#ifdef FB_DECODING_TEST_SCHEDULE
2004 MAX_STAGE_PAGE_NUM/2;
2005#else
2006 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
2007#endif
2008 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2009 FRAME_BUFFERS + buf->index, used_page_num);
2010
2011 pbi->s1_pos++;
2012 if (pbi->s1_pos >= pbi->used_stage_buf_num)
2013 pbi->s1_pos = 0;
2014
2015 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2016 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2017 __func__, used_page_num, buf->index,
2018 pbi->s1_pos, pbi->s2_pos);
2019}
2020
2021#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2022
2023static int get_s2_buf(
2024 struct VP9Decoder_s *pbi)
2025{
2026 int ret = -1;
2027 struct stage_buf_s *buf = NULL;
2028 if (s2_buf_available(pbi)) {
2029 buf = pbi->stage_bufs[pbi->s2_pos];
2030 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2031 "%s for index %d (s1_pos %d s2_pos %d)\n",
2032 __func__, buf->index,
2033 pbi->s1_pos, pbi->s2_pos);
2034 pbi->s2_buf = buf;
2035 ret = 0;
2036 }
2037 return ret;
2038}
2039
2040static void inc_s2_pos(struct VP9Decoder_s *pbi)
2041{
2042 struct stage_buf_s *buf =
2043 pbi->stage_bufs[pbi->s2_pos];
2044 decoder_mmu_box_free_idx(pbi->mmu_box,
2045 FRAME_BUFFERS + buf->index);
2046 pbi->s2_pos++;
2047 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2048 pbi->s2_pos = 0;
2049 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2050 "%s for index %d (s1_pos %d s2_pos %d)\n",
2051 __func__, buf->index,
2052 pbi->s1_pos, pbi->s2_pos);
2053}
2054
2055static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2056{
2057 int num;
2058 if (pbi->s1_pos >= pbi->s2_pos)
2059 num = pbi->used_stage_buf_num -
2060 (pbi->s1_pos - pbi->s2_pos) - 1;
2061 else
2062 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2063 return num;
2064}
2065
2066#ifndef FB_DECODING_TEST_SCHEDULE
2067static DEFINE_SPINLOCK(fb_core_spin_lock);
2068
2069static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2070{
2071 /* to do: VLSI review
2072 completion of last LCU decoding in BACK
2073 */
2074 return 1;
2075}
2076
2077static void start_s1_decoding(struct VP9Decoder_s *pbi)
2078{
2079 /* to do: VLSI review
2080 after parser, how to start LCU decoding in BACK
2081 */
2082}
2083
2084static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2085{
2086 /* to do: VLSI review
2087 1. how to disconnect DMC for FRONT and BACK
2088 2. reset bit 13, 24, FRONT or BACK ??
2089 */
2090
2091 unsigned long flags;
2092 u32 reset_bits = 0;
2093 if (mask & HW_MASK_FRONT)
2094 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2095 spin_lock_irqsave(&fb_core_spin_lock, flags);
2096 codec_dmcbus_write(DMC_REQ_CTRL,
2097 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2098 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2099
2100 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2101 & (1 << 4)))
2102 ;
2103
2104 if ((mask & HW_MASK_FRONT) &&
2105 input_frame_based(vdec))
2106 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2107
2108 /*
2109 * 2: assist
2110 * 3: parser
2111 * 4: parser_state
2112 * 8: dblk
2113 * 11:mcpu
2114 * 12:ccpu
2115 * 13:ddr
2116 * 14:iqit
2117 * 15:ipp
2118 * 17:qdct
2119 * 18:mpred
2120 * 19:sao
2121 * 24:hevc_afifo
2122 */
2123 if (mask & HW_MASK_FRONT) {
2124 reset_bits =
2125 (1<<3)|(1<<4)|(1<<11)|
2126 (1<<12)|(1<<18);
2127 }
2128 if (mask & HW_MASK_BACK) {
2129 reset_bits =
2130 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2131 (1<<17)|(1<<19)|(1<<24);
2132 }
2133 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2134#if 0
2135 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2136 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2137 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2138#endif
2139 WRITE_VREG(DOS_SW_RESET3, 0);
2140
2141
2142 spin_lock_irqsave(&fb_core_spin_lock, flags);
2143 codec_dmcbus_write(DMC_REQ_CTRL,
2144 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2145 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2146
2147}
2148#endif
2149
2150#endif
2151
2152static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2153
2154static int get_free_fb(struct VP9Decoder_s *pbi)
2155{
2156 struct VP9_Common_s *const cm = &pbi->common;
2157 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2158 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2159 int i;
2160 unsigned long flags;
2161
2162 lock_buffer_pool(cm->buffer_pool, flags);
2163 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2164 for (i = 0; i < pbi->used_buf_num; ++i) {
2165 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2166 __func__, i, frame_bufs[i].ref_count,
2167 frame_bufs[i].buf.vf_ref,
2168 frame_bufs[i].buf.index);
2169 }
2170 }
2171 for (i = 0; i < pbi->used_buf_num; ++i) {
2172 pic = &frame_bufs[i].buf;
2173 if ((frame_bufs[i].ref_count == 0) &&
2174 (pic->vf_ref == 0) && (pic->index != -1)) {
2175 if (pbi->is_used_v4l && !pic->cma_alloc_addr) {
2176 pic->y_crop_width = pbi->frame_width;
2177 pic->y_crop_height = pbi->frame_height;
2178 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2179 set_canvas(pbi, pic);
2180 init_pic_list_hw(pbi);
2181 } else
2182 i = pbi->used_buf_num;
2183 }
2184
2185 break;
2186 }
2187 }
2188 if (i != pbi->used_buf_num) {
2189 frame_bufs[i].ref_count = 1;
2190 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2191 i, frame_bufs[i].ref_count);*/
2192 } else {
2193 /* Reset i to be INVALID_IDX to indicate
2194 no free buffer found*/
2195 i = INVALID_IDX;
2196 }
2197
2198 unlock_buffer_pool(cm->buffer_pool, flags);
2199 return i;
2200}
2201
2202static int get_free_buf_count(struct VP9Decoder_s *pbi)
2203{
2204 struct VP9_Common_s *const cm = &pbi->common;
2205 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2206 int i;
2207 int free_buf_count = 0;
2208 for (i = 0; i < pbi->used_buf_num; ++i)
2209 if ((frame_bufs[i].ref_count == 0) &&
2210 (frame_bufs[i].buf.vf_ref == 0) &&
2211 (frame_bufs[i].buf.index != -1)
2212 )
2213 free_buf_count++;
2214 return free_buf_count;
2215}
2216
2217static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2218 struct BufferPool_s *const pool)
2219{
2220 if (idx >= 0) {
2221 --frame_bufs[idx].ref_count;
2222 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2223 * frame_bufs[idx].ref_count);
2224 */
2225 /*A worker may only get a free framebuffer index when
2226 *calling get_free_fb. But the private buffer is not set up
2227 *until finish decoding header. So any error happens during
2228 *decoding header, the frame_bufs will not have valid priv
2229 *buffer.
2230 */
2231
2232 if (frame_bufs[idx].ref_count == 0 &&
2233 frame_bufs[idx].raw_frame_buffer.priv)
2234 vp9_release_frame_buffer
2235 (&frame_bufs[idx].raw_frame_buffer);
2236 }
2237}
2238
2239static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2240{
2241 struct VP9_Common_s *const cm = &pbi->common;
2242 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2243 struct BufferPool_s *const pool = cm->buffer_pool;
2244 int mask, ref_index = 0;
2245 unsigned long flags;
2246
2247 /* Generate next_ref_frame_map.*/
2248 lock_buffer_pool(pool, flags);
2249 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2250 if (mask & 1) {
2251 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2252 ++frame_bufs[cm->new_fb_idx].ref_count;
2253 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2254 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2255 */
2256 } else
2257 cm->next_ref_frame_map[ref_index] =
2258 cm->ref_frame_map[ref_index];
2259 /* Current thread holds the reference frame.*/
2260 if (cm->ref_frame_map[ref_index] >= 0) {
2261 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2262 /*pr_info
2263 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2264 *cm->ref_frame_map[ref_index],
2265 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2266 */
2267 }
2268 ++ref_index;
2269 }
2270
2271 for (; ref_index < REF_FRAMES; ++ref_index) {
2272 cm->next_ref_frame_map[ref_index] =
2273 cm->ref_frame_map[ref_index];
2274 /* Current thread holds the reference frame.*/
2275 if (cm->ref_frame_map[ref_index] >= 0) {
2276 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2277 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2278 *cm->ref_frame_map[ref_index],
2279 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2280 */
2281 }
2282 }
2283 unlock_buffer_pool(pool, flags);
2284 return;
2285}
2286
2287static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2288
2289{
2290 struct VP9_Common_s *const cm = &pbi->common;
2291 struct BufferPool_s *pool = cm->buffer_pool;
2292 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2293 int mask, ref_index = 0;
2294 unsigned long flags;
2295
2296 lock_buffer_pool(pool, flags);
2297 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2298 const int old_idx = cm->ref_frame_map[ref_index];
2299 /*Current thread releases the holding of reference frame.*/
2300 decrease_ref_count(old_idx, frame_bufs, pool);
2301
2302 /*Release the reference frame in reference map.*/
2303 if ((mask & 1) && old_idx >= 0)
2304 decrease_ref_count(old_idx, frame_bufs, pool);
2305 cm->ref_frame_map[ref_index] =
2306 cm->next_ref_frame_map[ref_index];
2307 ++ref_index;
2308 }
2309
2310 /*Current thread releases the holding of reference frame.*/
2311 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2312 ++ref_index) {
2313 const int old_idx = cm->ref_frame_map[ref_index];
2314
2315 decrease_ref_count(old_idx, frame_bufs, pool);
2316 cm->ref_frame_map[ref_index] =
2317 cm->next_ref_frame_map[ref_index];
2318 }
2319 unlock_buffer_pool(pool, flags);
2320 return;
2321}
2322
2323int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2324{
2325 struct VP9_Common_s *const cm = &pbi->common;
2326 struct BufferPool_s *pool = cm->buffer_pool;
2327 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2328 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2329 int i;
2330 int ret;
2331
2332 pbi->ready_for_new_data = 0;
2333
2334 if (pbi->has_keyframe == 0 &&
2335 params->p.frame_type != KEY_FRAME){
2336 on_no_keyframe_skiped++;
2337 return -2;
2338 }
2339 pbi->has_keyframe = 1;
2340 on_no_keyframe_skiped = 0;
2341#if 0
2342 if (pbi->mmu_enable) {
2343 if (!pbi->m_ins_flag)
2344 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2345 if (cm->prev_fb_idx >= 0) {
2346 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2347 cm->prev_fb_idx, pbi->used_4k_num);
2348 }
2349 }
2350#endif
2351 if (cm->new_fb_idx >= 0
2352 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2353 vp9_release_frame_buffer
2354 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2355 }
2356 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2357 cm->prev_fb_idx, cm->new_fb_idx);*/
2358#ifndef MV_USE_FIXED_BUF
2359 put_un_used_mv_bufs(pbi);
2360 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2361 dump_pic_list(pbi);
2362#endif
2363 cm->new_fb_idx = get_free_fb(pbi);
2364 if (cm->new_fb_idx == INVALID_IDX) {
2365 pr_info("get_free_fb error\r\n");
2366 return -1;
2367 }
2368#ifndef MV_USE_FIXED_BUF
2369#ifdef SUPPORT_FB_DECODING
2370 if (pbi->used_stage_buf_num == 0) {
2371#endif
2372 if (get_mv_buf(pbi,
2373 &pool->frame_bufs[cm->new_fb_idx].
2374 buf.mv_buf_index,
2375 &pool->frame_bufs[cm->new_fb_idx].
2376 buf.mpred_mv_wr_start_addr
2377 ) < 0) {
2378 pr_info("get_mv_buf fail\r\n");
2379 return -1;
2380 }
2381 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2382 dump_pic_list(pbi);
2383#ifdef SUPPORT_FB_DECODING
2384 }
2385#endif
2386#endif
2387 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2388 /*if (debug & VP9_DEBUG_BUFMGR)
2389 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2390 cm->new_fb_idx);*/
2391
2392 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2393 if (pbi->mmu_enable) {
2394 /* moved to after picture size ready
2395 *alloc_mmu(cm, params->p.width, params->p.height,
2396 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2397 */
2398 cm->prev_fb_idx = cm->new_fb_idx;
2399 }
2400 /*read_uncompressed_header()*/
2401 cm->last_frame_type = cm->frame_type;
2402 cm->last_intra_only = cm->intra_only;
2403 cm->profile = params->p.profile;
2404 if (cm->profile >= MAX_PROFILES) {
2405 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2406 return -1;
2407 }
2408 cm->show_existing_frame = params->p.show_existing_frame;
2409 if (cm->show_existing_frame) {
2410 /* Show an existing frame directly.*/
2411 int frame_to_show_idx = params->p.frame_to_show_idx;
2412 int frame_to_show;
2413 unsigned long flags;
2414 if (frame_to_show_idx >= REF_FRAMES) {
2415 pr_info("frame_to_show_idx %d exceed max index\r\n",
2416 frame_to_show_idx);
2417 return -1;
2418 }
2419
2420 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2421 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2422 lock_buffer_pool(pool, flags);
2423 if (frame_to_show < 0 ||
2424 frame_bufs[frame_to_show].ref_count < 1) {
2425 unlock_buffer_pool(pool, flags);
2426 pr_err
2427 ("Error:Buffer %d does not contain a decoded frame",
2428 frame_to_show);
2429 return -1;
2430 }
2431
2432 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2433 unlock_buffer_pool(pool, flags);
2434 pbi->refresh_frame_flags = 0;
2435 /*cm->lf.filter_level = 0;*/
2436 cm->show_frame = 1;
2437
2438 /*
2439 *if (pbi->frame_parallel_decode) {
2440 * for (i = 0; i < REF_FRAMES; ++i)
2441 * cm->next_ref_frame_map[i] =
2442 * cm->ref_frame_map[i];
2443 *}
2444 */
2445 /* do not decode, search next start code */
2446 return 1;
2447 }
2448 cm->frame_type = params->p.frame_type;
2449 cm->show_frame = params->p.show_frame;
2450 cm->error_resilient_mode = params->p.error_resilient_mode;
2451
2452
2453 if (cm->frame_type == KEY_FRAME) {
2454 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2455
2456 for (i = 0; i < REFS_PER_FRAME; ++i) {
2457 cm->frame_refs[i].idx = INVALID_IDX;
2458 cm->frame_refs[i].buf = NULL;
2459 }
2460
2461 ret = setup_frame_size(pbi,
2462 cm, params, pbi->frame_mmu_map_addr,
2463 print_header_info);
2464 if (ret)
2465 return -1;
2466 if (pbi->need_resync) {
2467 memset(&cm->ref_frame_map, -1,
2468 sizeof(cm->ref_frame_map));
2469 pbi->need_resync = 0;
2470 }
2471 } else {
2472 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2473 /*if (print_header_info) {
2474 * if (cm->show_frame)
2475 * pr_info
2476 * ("intra_only set to 0 because of show_frame\n");
2477 * else
2478 * pr_info
2479 * ("1-bit intra_only read: %d\n", cm->intra_only);
2480 *}
2481 */
2482
2483
2484 cm->reset_frame_context = cm->error_resilient_mode ?
2485 0 : params->p.reset_frame_context;
2486 if (print_header_info) {
2487 if (cm->error_resilient_mode)
2488 pr_info
2489 ("reset to 0 error_resilient_mode\n");
2490 else
2491 pr_info
2492 (" * 2-bits reset_frame_context read : %d\n",
2493 cm->reset_frame_context);
2494 }
2495
2496 if (cm->intra_only) {
2497 if (cm->profile > PROFILE_0) {
2498 /*read_bitdepth_colorspace_sampling(cm,
2499 * rb, print_header_info);
2500 */
2501 } else {
2502 /*NOTE: The intra-only frame header
2503 *does not include the specification
2504 *of either the color format or
2505 *color sub-sampling
2506 *in profile 0. VP9 specifies that the default
2507 *color format should be YUV 4:2:0 in this
2508 *case (normative).
2509 */
2510 cm->color_space = VPX_CS_BT_601;
2511 cm->subsampling_y = cm->subsampling_x = 1;
2512 cm->bit_depth = VPX_BITS_8;
2513 cm->use_highbitdepth = 0;
2514 }
2515
2516 pbi->refresh_frame_flags =
2517 params->p.refresh_frame_flags;
2518 /*if (print_header_info)
2519 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2520 * REF_FRAMES, pbi->refresh_frame_flags);
2521 */
2522 ret = setup_frame_size(pbi,
2523 cm,
2524 params,
2525 pbi->frame_mmu_map_addr,
2526 print_header_info);
2527 if (ret)
2528 return -1;
2529 if (pbi->need_resync) {
2530 memset(&cm->ref_frame_map, -1,
2531 sizeof(cm->ref_frame_map));
2532 pbi->need_resync = 0;
2533 }
2534 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2535 pbi->refresh_frame_flags =
2536 params->p.refresh_frame_flags;
2537 if (print_header_info)
2538 pr_info
2539 ("*%d-bits refresh_frame read:0x%x\n",
2540 REF_FRAMES, pbi->refresh_frame_flags);
2541 for (i = 0; i < REFS_PER_FRAME; ++i) {
2542 const int ref =
2543 (params->p.ref_info >>
2544 (((REFS_PER_FRAME-i-1)*4)+1))
2545 & 0x7;
2546 const int idx =
2547 cm->ref_frame_map[ref];
2548 struct RefBuffer_s * const ref_frame =
2549 &cm->frame_refs[i];
2550 if (print_header_info)
2551 pr_info("*%d-bits ref[%d]read:%d\n",
2552 REF_FRAMES_LOG2, i, ref);
2553 ref_frame->idx = idx;
2554 ref_frame->buf = &frame_bufs[idx].buf;
2555 cm->ref_frame_sign_bias[LAST_FRAME + i]
2556 = (params->p.ref_info >>
2557 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2558 if (print_header_info)
2559 pr_info("1bit ref_frame_sign_bias");
2560 /*pr_info
2561 *("%dread: %d\n",
2562 *LAST_FRAME+i,
2563 *cm->ref_frame_sign_bias
2564 *[LAST_FRAME + i]);
2565 */
2566 /*pr_info
2567 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2568 *__func__, ref_frame->idx);
2569 */
2570
2571 }
2572
2573 ret = setup_frame_size_with_refs(
2574 pbi,
2575 cm,
2576 params,
2577 pbi->frame_mmu_map_addr,
2578 print_header_info);
2579 if (ret)
2580 return -1;
2581 for (i = 0; i < REFS_PER_FRAME; ++i) {
2582 /*struct RefBuffer_s *const ref_buf =
2583 *&cm->frame_refs[i];
2584 */
2585 /* to do:
2586 *vp9_setup_scale_factors_for_frame
2587 */
2588 }
2589 }
2590 }
2591
2592 pic = get_frame_new_buffer(cm);
2593 if (!pic)
2594 return -1;
2595
2596 pic->bit_depth = cm->bit_depth;
2597 pic->color_space = cm->color_space;
2598 pic->slice_type = cm->frame_type;
2599
2600 if (pbi->need_resync) {
2601 pr_err
2602 ("Error: Keyframe/intra-only frame required to reset\r\n");
2603 return -1;
2604 }
2605 generate_next_ref_frames(pbi);
2606 pbi->hold_ref_buf = 1;
2607
2608#if 0
2609 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2610 vp9_setup_past_independence(cm);
2611 setup_loopfilter(&cm->lf, rb, print_header_info);
2612 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2613 setup_segmentation(&cm->seg, rb, print_header_info);
2614 setup_segmentation_dequant(cm, print_header_info);
2615
2616 setup_tile_info(cm, rb, print_header_info);
2617 sz = vp9_rb_read_literal(rb, 16);
2618 if (print_header_info)
2619 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2620
2621 if (sz == 0)
2622 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2623 "Invalid header size");
2624#endif
2625 /*end read_uncompressed_header()*/
2626 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2627 cm->width == cm->last_width &&
2628 cm->height == cm->last_height &&
2629 !cm->last_intra_only &&
2630 cm->last_show_frame &&
2631 (cm->last_frame_type != KEY_FRAME);
2632
2633 /*pr_info
2634 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2635 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2636 *pr_info
2637 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2638 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2639 */
2640 return 0;
2641}
2642
2643
2644void swap_frame_buffers(struct VP9Decoder_s *pbi)
2645{
2646 int ref_index = 0;
2647 struct VP9_Common_s *const cm = &pbi->common;
2648 struct BufferPool_s *const pool = cm->buffer_pool;
2649 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2650 unsigned long flags;
2651 refresh_ref_frames(pbi);
2652 pbi->hold_ref_buf = 0;
2653 cm->frame_to_show = get_frame_new_buffer(cm);
2654
2655 if (cm->frame_to_show) {
2656 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2657 lock_buffer_pool(pool, flags);
2658 --frame_bufs[cm->new_fb_idx].ref_count;
2659 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2660 * frame_bufs[cm->new_fb_idx].ref_count);
2661 */
2662 unlock_buffer_pool(pool, flags);
2663 /*}*/
2664 }
2665
2666 /*Invalidate these references until the next frame starts.*/
2667 for (ref_index = 0; ref_index < 3; ref_index++)
2668 cm->frame_refs[ref_index].idx = -1;
2669}
2670
2671#if 0
2672static void check_resync(vpx_codec_alg_priv_t *const ctx,
2673 const struct VP9Decoder_s *const pbi)
2674{
2675 /* Clear resync flag if worker got a key frame or intra only frame.*/
2676 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2677 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2678 ctx->need_resync = 0;
2679}
2680#endif
2681
2682int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2683{
2684 struct VP9_Common_s *const cm = &pbi->common;
2685 int ret = -1;
2686
2687 if (pbi->ready_for_new_data == 1)
2688 return ret;
2689
2690 pbi->ready_for_new_data = 1;
2691
2692 /* no raw frame to show!!! */
2693 if (!cm->show_frame)
2694 return ret;
2695
2696 /* may not be get buff in v4l2 */
2697 if (!cm->frame_to_show)
2698 return ret;
2699
2700 pbi->ready_for_new_data = 1;
2701
2702 *sd = *cm->frame_to_show;
2703 ret = 0;
2704
2705 return ret;
2706}
2707
2708int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2709 struct buff_s *mc_buf_i) {
2710 struct VP9_Common_s *cm = &pbi->common;
2711
2712 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2713 pbi->frame_count = 0;
2714 pbi->pic_count = 0;
2715 pbi->pre_stream_offset = 0;
2716 cm->buffer_pool = &pbi->vp9_buffer_pool;
2717 spin_lock_init(&cm->buffer_pool->lock);
2718 cm->prev_fb_idx = INVALID_IDX;
2719 cm->new_fb_idx = INVALID_IDX;
2720 pbi->used_4k_num = -1;
2721 cm->cur_fb_idx_mmu = INVALID_IDX;
2722 pr_debug
2723 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2724 cm->prev_fb_idx, cm->new_fb_idx);
2725 pbi->need_resync = 1;
2726 /* Initialize the references to not point to any frame buffers.*/
2727 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2728 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2729 cm->current_video_frame = 0;
2730 pbi->ready_for_new_data = 1;
2731
2732 /* private init */
2733 pbi->work_space_buf = buf_spec_i;
2734 if (!pbi->mmu_enable)
2735 pbi->mc_buf = mc_buf_i;
2736
2737 pbi->rpm_addr = NULL;
2738 pbi->lmem_addr = NULL;
2739
2740 pbi->use_cma_flag = 0;
2741 pbi->decode_idx = 0;
2742 pbi->slice_idx = 0;
2743 /*int m_uiMaxCUWidth = 1<<7;*/
2744 /*int m_uiMaxCUHeight = 1<<7;*/
2745 pbi->has_keyframe = 0;
2746 pbi->skip_flag = 0;
2747 pbi->wait_buf = 0;
2748 pbi->error_flag = 0;
2749
2750 pbi->pts_mode = PTS_NORMAL;
2751 pbi->last_pts = 0;
2752 pbi->last_lookup_pts = 0;
2753 pbi->last_pts_us64 = 0;
2754 pbi->last_lookup_pts_us64 = 0;
2755 pbi->shift_byte_count = 0;
2756 pbi->shift_byte_count_lo = 0;
2757 pbi->shift_byte_count_hi = 0;
2758 pbi->pts_mode_switching_count = 0;
2759 pbi->pts_mode_recovery_count = 0;
2760
2761 pbi->buf_num = 0;
2762 pbi->pic_num = 0;
2763
2764 return 0;
2765}
2766
2767int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2768{
2769 struct VP9_Common_s *cm = &pbi->common;
2770 struct PIC_BUFFER_CONFIG_s sd;
2771
2772 if (pbi->postproc_done)
2773 return 0;
2774 pbi->postproc_done = 1;
2775 swap_frame_buffers(pbi);
2776 if (!cm->show_existing_frame) {
2777 cm->last_show_frame = cm->show_frame;
2778 cm->prev_frame = cm->cur_frame;
2779#if 0
2780 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2781 vp9_swap_current_and_last_seg_map(cm);
2782#endif
2783 }
2784 cm->last_width = cm->width;
2785 cm->last_height = cm->height;
2786 if (cm->show_frame)
2787 cm->current_video_frame++;
2788
2789 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2790 /*pr_info("Display frame index %d\r\n", sd.index);*/
2791 sd.stream_offset = pbi->pre_stream_offset;
2792 prepare_display_buf(pbi, &sd);
2793 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2794 }
2795
2796/* else
2797 * pr_info
2798 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2799 * pbi->ready_for_new_data, cm->show_frame);
2800 */
2801 return 0;
2802}
2803
2804/*struct VP9Decoder_s vp9_decoder;*/
2805union param_u vp9_param;
2806
2807/**************************************************
2808 *
2809 *VP9 buffer management end
2810 *
2811 ***************************************************
2812 */
2813
2814
2815#define HEVC_CM_BODY_START_ADDR 0x3626
2816#define HEVC_CM_BODY_LENGTH 0x3627
2817#define HEVC_CM_HEADER_LENGTH 0x3629
2818#define HEVC_CM_HEADER_OFFSET 0x362b
2819
2820#define LOSLESS_COMPRESS_MODE
2821
2822/*#define DECOMP_HEADR_SURGENT*/
2823#ifdef VP9_10B_NV21
2824static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2825#else
2826static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2827#endif
2828static u32 enable_mem_saving = 1;
2829static u32 force_w_h;
2830
2831static u32 force_fps;
2832
2833
2834const u32 vp9_version = 201602101;
2835static u32 debug;
2836static u32 radr;
2837static u32 rval;
2838static u32 pop_shorts;
2839static u32 dbg_cmd;
2840static u32 dbg_skip_decode_index;
2841static u32 endian = 0xff0;
2842#ifdef ERROR_HANDLE_DEBUG
2843static u32 dbg_nal_skip_flag;
2844 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2845static u32 dbg_nal_skip_count;
2846#endif
2847/*for debug*/
2848static u32 decode_pic_begin;
2849static uint slice_parse_begin;
2850static u32 step;
2851#ifdef MIX_STREAM_SUPPORT
2852static u32 buf_alloc_width = 4096;
2853static u32 buf_alloc_height = 2304;
2854static u32 vp9_max_pic_w = 4096;
2855static u32 vp9_max_pic_h = 2304;
2856
2857static u32 dynamic_buf_num_margin;
2858#else
2859static u32 buf_alloc_width;
2860static u32 buf_alloc_height;
2861static u32 dynamic_buf_num_margin = 7;
2862#endif
2863static u32 buf_alloc_depth = 10;
2864static u32 buf_alloc_size;
2865/*
2866 *bit[0]: 0,
2867 * bit[1]: 0, always release cma buffer when stop
2868 * bit[1]: 1, never release cma buffer when stop
2869 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2870 *do not release cma buffer is blackout is not 1
2871 *
2872 *bit[2]: 0, when start decoding, check current displayed buffer
2873 * (only for buffer decoded by vp9) if blackout is 0
2874 * 1, do not check current displayed buffer
2875 *
2876 *bit[3]: 1, if blackout is not 1, do not release current
2877 * displayed cma buffer always.
2878 */
2879/* set to 1 for fast play;
2880 * set to 8 for other case of "keep last frame"
2881 */
2882static u32 buffer_mode = 1;
2883/* buffer_mode_dbg: debug only*/
2884static u32 buffer_mode_dbg = 0xffff0000;
2885/**/
2886
2887/*
2888 *bit 0, 1: only display I picture;
2889 *bit 1, 1: only decode I picture;
2890 */
2891static u32 i_only_flag;
2892
2893static u32 low_latency_flag;
2894
2895static u32 no_head;
2896
2897static u32 max_decoding_time;
2898/*
2899 *error handling
2900 */
2901/*error_handle_policy:
2902 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2903 *1, skip error_skip_nal_count nals before error recovery;
2904 *bit 1 (valid only when bit0 == 1):
2905 *1, wait vps/sps/pps after error recovery;
2906 *bit 2 (valid only when bit0 == 0):
2907 *0, auto search after error recovery (vp9_recover() called);
2908 *1, manual search after error recovery
2909 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2910 *
2911 *bit 4: 0, set error_mark after reset/recover
2912 * 1, do not set error_mark after reset/recover
2913 *bit 5: 0, check total lcu for every picture
2914 * 1, do not check total lcu
2915 *
2916 */
2917
2918static u32 error_handle_policy;
2919/*static u32 parser_sei_enable = 1;*/
2920#define MAX_BUF_NUM_NORMAL 12
2921#define MAX_BUF_NUM_LESS 10
2922static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2923#define MAX_BUF_NUM_SAVE_BUF 8
2924
2925static u32 run_ready_min_buf_num = 2;
2926
2927
2928static DEFINE_MUTEX(vvp9_mutex);
2929#ifndef MULTI_INSTANCE_SUPPORT
2930static struct device *cma_dev;
2931#endif
2932
2933#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2934#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2935#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2936#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2937#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2938#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2939#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2940#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2941#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2942#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2943#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2944#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2945#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2946#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2947#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2948#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2949#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2950#ifdef MULTI_INSTANCE_SUPPORT
2951#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2952#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2953#else
2954#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2955#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2956#endif
2957#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2958#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2959
2960
2961/*
2962 *ucode parser/search control
2963 *bit 0: 0, header auto parse; 1, header manual parse
2964 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
2965 *bit [3:2]: valid when bit1==0;
2966 *0, auto skip nal before first vps/sps/pps/idr;
2967 *1, auto skip nal before first vps/sps/pps
2968 *2, auto skip nal before first vps/sps/pps,
2969 * and not decode until the first I slice (with slice address of 0)
2970 *
2971 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
2972 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
2973 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
2974 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
2975 *bit [17]: for NAL_SEI when bit0 is 0:
2976 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
2977 *bit [31:20]: used by ucode for debug purpose
2978 */
2979#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
2980 /*[31:24] chip feature
2981 31: 0, use MBOX1; 1, use MBOX0
2982 */
2983#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
2984#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
2985
2986#ifdef MULTI_INSTANCE_SUPPORT
2987#define RPM_BUF_SIZE (0x400 * 2)
2988#else
2989#define RPM_BUF_SIZE (0x80*2)
2990#endif
2991#define LMEM_BUF_SIZE (0x400 * 2)
2992
2993#define WORK_BUF_SPEC_NUM 3
2994static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
2995 {
2996 /* 8M bytes */
2997 .max_width = 1920,
2998 .max_height = 1088,
2999 .ipp = {
3000 /* IPP work space calculation :
3001 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3002 */
3003 .buf_size = 0x4000,
3004 },
3005 .sao_abv = {
3006 .buf_size = 0x30000,
3007 },
3008 .sao_vb = {
3009 .buf_size = 0x30000,
3010 },
3011 .short_term_rps = {
3012 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3013 * total 64x16x2 = 2048 bytes (0x800)
3014 */
3015 .buf_size = 0x800,
3016 },
3017 .vps = {
3018 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3019 * total 0x0800 bytes
3020 */
3021 .buf_size = 0x800,
3022 },
3023 .sps = {
3024 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3025 * total 0x0800 bytes
3026 */
3027 .buf_size = 0x800,
3028 },
3029 .pps = {
3030 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3031 * total 0x2000 bytes
3032 */
3033 .buf_size = 0x2000,
3034 },
3035 .sao_up = {
3036 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3037 * each has 16 bytes total 0x2800 bytes
3038 */
3039 .buf_size = 0x2800,
3040 },
3041 .swap_buf = {
3042 /* 256cyclex64bit = 2K bytes 0x800
3043 * (only 144 cycles valid)
3044 */
3045 .buf_size = 0x800,
3046 },
3047 .swap_buf2 = {
3048 .buf_size = 0x800,
3049 },
3050 .scalelut = {
3051 /* support up to 32 SCALELUT 1024x32 =
3052 * 32Kbytes (0x8000)
3053 */
3054 .buf_size = 0x8000,
3055 },
3056 .dblk_para = {
3057 /* DBLK -> Max 256(4096/16) LCU,
3058 *each para 1024bytes(total:0x40000),
3059 *data 1024bytes(total:0x40000)
3060 */
3061 .buf_size = 0x80000,
3062 },
3063 .dblk_data = {
3064 .buf_size = 0x80000,
3065 },
3066 .seg_map = {
3067 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3068 .buf_size = 0xd800,
3069 },
3070 .mmu_vbh = {
3071 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3072 },
3073#if 0
3074 .cm_header = {
3075 /*add one for keeper.*/
3076 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3077 (FRAME_BUFFERS + 1),
3078 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3079 },
3080#endif
3081 .mpred_above = {
3082 .buf_size = 0x10000, /* 2 * size of hevc*/
3083 },
3084#ifdef MV_USE_FIXED_BUF
3085 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3086 .buf_size = 0x40000 * FRAME_BUFFERS,
3087 },
3088#endif
3089 .rpm = {
3090 .buf_size = RPM_BUF_SIZE,
3091 },
3092 .lmem = {
3093 .buf_size = 0x400 * 2,
3094 }
3095 },
3096 {
3097 .max_width = 4096,
3098 .max_height = 2304,
3099 .ipp = {
3100 /* IPP work space calculation :
3101 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3102 */
3103 .buf_size = 0x4000,
3104 },
3105 .sao_abv = {
3106 .buf_size = 0x30000,
3107 },
3108 .sao_vb = {
3109 .buf_size = 0x30000,
3110 },
3111 .short_term_rps = {
3112 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3113 * total 64x16x2 = 2048 bytes (0x800)
3114 */
3115 .buf_size = 0x800,
3116 },
3117 .vps = {
3118 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3119 * total 0x0800 bytes
3120 */
3121 .buf_size = 0x800,
3122 },
3123 .sps = {
3124 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3125 * total 0x0800 bytes
3126 */
3127 .buf_size = 0x800,
3128 },
3129 .pps = {
3130 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3131 * total 0x2000 bytes
3132 */
3133 .buf_size = 0x2000,
3134 },
3135 .sao_up = {
3136 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3137 * each has 16 bytes total 0x2800 bytes
3138 */
3139 .buf_size = 0x2800,
3140 },
3141 .swap_buf = {
3142 /* 256cyclex64bit = 2K bytes 0x800
3143 * (only 144 cycles valid)
3144 */
3145 .buf_size = 0x800,
3146 },
3147 .swap_buf2 = {
3148 .buf_size = 0x800,
3149 },
3150 .scalelut = {
3151 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3152 * (0x8000)
3153 */
3154 .buf_size = 0x8000,
3155 },
3156 .dblk_para = {
3157 /* DBLK -> Max 256(4096/16) LCU,
3158 *each para 1024bytes(total:0x40000),
3159 *data 1024bytes(total:0x40000)
3160 */
3161 .buf_size = 0x80000,
3162 },
3163 .dblk_data = {
3164 .buf_size = 0x80000,
3165 },
3166 .seg_map = {
3167 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3168 .buf_size = 0xd800,
3169 },
3170 .mmu_vbh = {
3171 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3172 },
3173#if 0
3174 .cm_header = {
3175 /*add one for keeper.*/
3176 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3177 (FRAME_BUFFERS + 1),
3178 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3179 },
3180#endif
3181 .mpred_above = {
3182 .buf_size = 0x10000, /* 2 * size of hevc*/
3183 },
3184#ifdef MV_USE_FIXED_BUF
3185 .mpred_mv = {
3186 /* .buf_size = 0x100000*16,
3187 * //4k2k , 0x100000 per buffer
3188 */
3189 /* 4096x2304 , 0x120000 per buffer */
3190 .buf_size = 0x120000 * FRAME_BUFFERS,
3191 },
3192#endif
3193 .rpm = {
3194 .buf_size = RPM_BUF_SIZE,
3195 },
3196 .lmem = {
3197 .buf_size = 0x400 * 2,
3198 }
3199 },
3200 {
3201 .max_width = 4096*2,
3202 .max_height = 2304*2,
3203 .ipp = {
3204 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3205 .buf_size = 0x4000*2,
3206 },
3207 .sao_abv = {
3208 .buf_size = 0x30000*2,
3209 },
3210 .sao_vb = {
3211 .buf_size = 0x30000*2,
3212 },
3213 .short_term_rps = {
3214 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3215 .buf_size = 0x800,
3216 },
3217 .vps = {
3218 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3219 .buf_size = 0x800,
3220 },
3221 .sps = {
3222 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3223 .buf_size = 0x800,
3224 },
3225 .pps = {
3226 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3227 .buf_size = 0x2000,
3228 },
3229 .sao_up = {
3230 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3231 .buf_size = 0x2800*2,
3232 },
3233 .swap_buf = {
3234 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3235 .buf_size = 0x800,
3236 },
3237 .swap_buf2 = {
3238 .buf_size = 0x800,
3239 },
3240 .scalelut = {
3241 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3242 .buf_size = 0x8000*2,
3243 },
3244 .dblk_para = {
3245 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3246 .buf_size = 0x80000*2,
3247 },
3248 .dblk_data = {
3249 .buf_size = 0x80000*2,
3250 },
3251 .seg_map = {
3252 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3253 .buf_size = 0xd800*4,
3254 },
3255 .mmu_vbh = {
3256 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3257 },
3258#if 0
3259 .cm_header = {
3260 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3261 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3262 },
3263#endif
3264 .mpred_above = {
3265 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3266 },
3267#ifdef MV_USE_FIXED_BUF
3268 .mpred_mv = {
3269 //4k2k , 0x100000 per buffer */
3270 /* 4096x2304 , 0x120000 per buffer */
3271 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3272 },
3273#endif
3274 .rpm = {
3275 .buf_size = RPM_BUF_SIZE,
3276 },
3277 .lmem = {
3278 .buf_size = 0x400 * 2,
3279 }
3280 }
3281};
3282
3283
3284/*Losless compression body buffer size 4K per 64x32 (jt)*/
3285int compute_losless_comp_body_size(int width, int height,
3286 uint8_t is_bit_depth_10)
3287{
3288 int width_x64;
3289 int height_x32;
3290 int bsize;
3291
3292 width_x64 = width + 63;
3293 width_x64 >>= 6;
3294 height_x32 = height + 31;
3295 height_x32 >>= 5;
3296 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3297 if (debug & VP9_DEBUG_BUFMGR_MORE)
3298 pr_info("%s(%d,%d,%d)=>%d\n",
3299 __func__, width, height,
3300 is_bit_depth_10, bsize);
3301
3302 return bsize;
3303}
3304
3305/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3306static int compute_losless_comp_header_size(int width, int height)
3307{
3308 int width_x128;
3309 int height_x64;
3310 int hsize;
3311
3312 width_x128 = width + 127;
3313 width_x128 >>= 7;
3314 height_x64 = height + 63;
3315 height_x64 >>= 6;
3316
3317 hsize = 32 * width_x128 * height_x64;
3318 if (debug & VP9_DEBUG_BUFMGR_MORE)
3319 pr_info("%s(%d,%d)=>%d\n",
3320 __func__, width, height,
3321 hsize);
3322
3323 return hsize;
3324}
3325
3326static void init_buff_spec(struct VP9Decoder_s *pbi,
3327 struct BuffInfo_s *buf_spec)
3328{
3329 void *mem_start_virt;
3330
3331 buf_spec->ipp.buf_start = buf_spec->start_adr;
3332 buf_spec->sao_abv.buf_start =
3333 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3334
3335 buf_spec->sao_vb.buf_start =
3336 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3337 buf_spec->short_term_rps.buf_start =
3338 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3339 buf_spec->vps.buf_start =
3340 buf_spec->short_term_rps.buf_start +
3341 buf_spec->short_term_rps.buf_size;
3342 buf_spec->sps.buf_start =
3343 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3344 buf_spec->pps.buf_start =
3345 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3346 buf_spec->sao_up.buf_start =
3347 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3348 buf_spec->swap_buf.buf_start =
3349 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3350 buf_spec->swap_buf2.buf_start =
3351 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3352 buf_spec->scalelut.buf_start =
3353 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3354 buf_spec->dblk_para.buf_start =
3355 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3356 buf_spec->dblk_data.buf_start =
3357 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3358 buf_spec->seg_map.buf_start =
3359 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3360 if (pbi == NULL || pbi->mmu_enable) {
3361 buf_spec->mmu_vbh.buf_start =
3362 buf_spec->seg_map.buf_start +
3363 buf_spec->seg_map.buf_size;
3364 buf_spec->mpred_above.buf_start =
3365 buf_spec->mmu_vbh.buf_start +
3366 buf_spec->mmu_vbh.buf_size;
3367 } else {
3368 buf_spec->mpred_above.buf_start =
3369 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3370 }
3371#ifdef MV_USE_FIXED_BUF
3372 buf_spec->mpred_mv.buf_start =
3373 buf_spec->mpred_above.buf_start +
3374 buf_spec->mpred_above.buf_size;
3375
3376 buf_spec->rpm.buf_start =
3377 buf_spec->mpred_mv.buf_start +
3378 buf_spec->mpred_mv.buf_size;
3379#else
3380 buf_spec->rpm.buf_start =
3381 buf_spec->mpred_above.buf_start +
3382 buf_spec->mpred_above.buf_size;
3383
3384#endif
3385 buf_spec->lmem.buf_start =
3386 buf_spec->rpm.buf_start +
3387 buf_spec->rpm.buf_size;
3388 buf_spec->end_adr =
3389 buf_spec->lmem.buf_start +
3390 buf_spec->lmem.buf_size;
3391
3392 if (!pbi)
3393 return;
3394
3395 if (!vdec_secure(hw_to_vdec(pbi))) {
3396 mem_start_virt =
3397 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3398 if (mem_start_virt) {
3399 memset(mem_start_virt, 0,
3400 buf_spec->dblk_para.buf_size);
3401 codec_mm_dma_flush(mem_start_virt,
3402 buf_spec->dblk_para.buf_size,
3403 DMA_TO_DEVICE);
3404 } else {
3405 mem_start_virt = codec_mm_vmap(
3406 buf_spec->dblk_para.buf_start,
3407 buf_spec->dblk_para.buf_size);
3408 if (mem_start_virt) {
3409 memset(mem_start_virt, 0,
3410 buf_spec->dblk_para.buf_size);
3411 codec_mm_dma_flush(mem_start_virt,
3412 buf_spec->dblk_para.buf_size,
3413 DMA_TO_DEVICE);
3414 codec_mm_unmap_phyaddr(mem_start_virt);
3415 } else {
3416 /*not virt for tvp playing,
3417 may need clear on ucode.*/
3418 pr_err("mem_start_virt failed\n");
3419 }
3420 }
3421 }
3422
3423 if (debug) {
3424 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3425 buf_spec->start_adr, buf_spec->end_adr,
3426 buf_spec->end_adr - buf_spec->start_adr);
3427 }
3428
3429 if (debug) {
3430 pr_info("ipp.buf_start :%x\n",
3431 buf_spec->ipp.buf_start);
3432 pr_info("sao_abv.buf_start :%x\n",
3433 buf_spec->sao_abv.buf_start);
3434 pr_info("sao_vb.buf_start :%x\n",
3435 buf_spec->sao_vb.buf_start);
3436 pr_info("short_term_rps.buf_start :%x\n",
3437 buf_spec->short_term_rps.buf_start);
3438 pr_info("vps.buf_start :%x\n",
3439 buf_spec->vps.buf_start);
3440 pr_info("sps.buf_start :%x\n",
3441 buf_spec->sps.buf_start);
3442 pr_info("pps.buf_start :%x\n",
3443 buf_spec->pps.buf_start);
3444 pr_info("sao_up.buf_start :%x\n",
3445 buf_spec->sao_up.buf_start);
3446 pr_info("swap_buf.buf_start :%x\n",
3447 buf_spec->swap_buf.buf_start);
3448 pr_info("swap_buf2.buf_start :%x\n",
3449 buf_spec->swap_buf2.buf_start);
3450 pr_info("scalelut.buf_start :%x\n",
3451 buf_spec->scalelut.buf_start);
3452 pr_info("dblk_para.buf_start :%x\n",
3453 buf_spec->dblk_para.buf_start);
3454 pr_info("dblk_data.buf_start :%x\n",
3455 buf_spec->dblk_data.buf_start);
3456 pr_info("seg_map.buf_start :%x\n",
3457 buf_spec->seg_map.buf_start);
3458 if (pbi->mmu_enable) {
3459 pr_info("mmu_vbh.buf_start :%x\n",
3460 buf_spec->mmu_vbh.buf_start);
3461 }
3462 pr_info("mpred_above.buf_start :%x\n",
3463 buf_spec->mpred_above.buf_start);
3464#ifdef MV_USE_FIXED_BUF
3465 pr_info("mpred_mv.buf_start :%x\n",
3466 buf_spec->mpred_mv.buf_start);
3467#endif
3468 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3469 pr_info("rpm.buf_start :%x\n",
3470 buf_spec->rpm.buf_start);
3471 }
3472 }
3473}
3474
3475/* cache_util.c */
3476#define THODIYIL_MCRCC_CANVAS_ALGX 4
3477
3478static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3479
3480static void mcrcc_perfcount_reset(void)
3481{
3482 if (debug & VP9_DEBUG_CACHE)
3483 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3484 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3485 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3486 return;
3487}
3488
3489static unsigned raw_mcr_cnt_total_prev;
3490static unsigned hit_mcr_0_cnt_total_prev;
3491static unsigned hit_mcr_1_cnt_total_prev;
3492static unsigned byp_mcr_cnt_nchcanv_total_prev;
3493static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3494
3495static void mcrcc_get_hitrate(unsigned reset_pre)
3496{
3497 unsigned delta_hit_mcr_0_cnt;
3498 unsigned delta_hit_mcr_1_cnt;
3499 unsigned delta_raw_mcr_cnt;
3500 unsigned delta_mcr_cnt_nchcanv;
3501 unsigned delta_mcr_cnt_nchoutwin;
3502
3503 unsigned tmp;
3504 unsigned raw_mcr_cnt;
3505 unsigned hit_mcr_cnt;
3506 unsigned byp_mcr_cnt_nchoutwin;
3507 unsigned byp_mcr_cnt_nchcanv;
3508 int hitrate;
3509 if (reset_pre) {
3510 raw_mcr_cnt_total_prev = 0;
3511 hit_mcr_0_cnt_total_prev = 0;
3512 hit_mcr_1_cnt_total_prev = 0;
3513 byp_mcr_cnt_nchcanv_total_prev = 0;
3514 byp_mcr_cnt_nchoutwin_total_prev = 0;
3515 }
3516 if (debug & VP9_DEBUG_CACHE)
3517 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3518 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3519 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3520 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3521 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3522 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3523 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3524 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3525 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3526
3527 if (debug & VP9_DEBUG_CACHE)
3528 pr_info("raw_mcr_cnt_total: %d\n",
3529 raw_mcr_cnt);
3530 if (debug & VP9_DEBUG_CACHE)
3531 pr_info("hit_mcr_cnt_total: %d\n",
3532 hit_mcr_cnt);
3533 if (debug & VP9_DEBUG_CACHE)
3534 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3535 byp_mcr_cnt_nchoutwin);
3536 if (debug & VP9_DEBUG_CACHE)
3537 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3538 byp_mcr_cnt_nchcanv);
3539
3540 delta_raw_mcr_cnt = raw_mcr_cnt -
3541 raw_mcr_cnt_total_prev;
3542 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3543 byp_mcr_cnt_nchcanv_total_prev;
3544 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3545 byp_mcr_cnt_nchoutwin_total_prev;
3546 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3547 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3548 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3549
3550 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3551 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3552 if (debug & VP9_DEBUG_CACHE)
3553 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3554 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3555 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3556 if (debug & VP9_DEBUG_CACHE)
3557 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3558 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3559 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3560 if (debug & VP9_DEBUG_CACHE)
3561 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3562 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3563 hit_mcr_0_cnt_total_prev = tmp;
3564 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3565 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3566 if (debug & VP9_DEBUG_CACHE)
3567 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3568 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3569 hit_mcr_1_cnt_total_prev = tmp;
3570
3571 if (delta_raw_mcr_cnt != 0) {
3572 hitrate = 100 * delta_hit_mcr_0_cnt
3573 / delta_raw_mcr_cnt;
3574 if (debug & VP9_DEBUG_CACHE)
3575 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3576 hitrate = 100 * delta_hit_mcr_1_cnt
3577 / delta_raw_mcr_cnt;
3578 if (debug & VP9_DEBUG_CACHE)
3579 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3580 hitrate = 100 * delta_mcr_cnt_nchcanv
3581 / delta_raw_mcr_cnt;
3582 if (debug & VP9_DEBUG_CACHE)
3583 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3584 hitrate = 100 * delta_mcr_cnt_nchoutwin
3585 / delta_raw_mcr_cnt;
3586 if (debug & VP9_DEBUG_CACHE)
3587 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3588 }
3589
3590
3591 if (raw_mcr_cnt != 0) {
3592 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3593 if (debug & VP9_DEBUG_CACHE)
3594 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3595 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3596 / raw_mcr_cnt;
3597 if (debug & VP9_DEBUG_CACHE)
3598 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3599 } else {
3600 if (debug & VP9_DEBUG_CACHE)
3601 pr_info("MCRCC_HIT_RATE : na\n");
3602 if (debug & VP9_DEBUG_CACHE)
3603 pr_info("MCRCC_BYP_RATE : na\n");
3604 }
3605 return;
3606}
3607
3608
3609static void decomp_perfcount_reset(void)
3610{
3611 if (debug & VP9_DEBUG_CACHE)
3612 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3613 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3614 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3615 return;
3616}
3617
3618static void decomp_get_hitrate(void)
3619{
3620 unsigned raw_mcr_cnt;
3621 unsigned hit_mcr_cnt;
3622 int hitrate;
3623 if (debug & VP9_DEBUG_CACHE)
3624 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3625 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3626 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3627 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3628 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3629
3630 if (debug & VP9_DEBUG_CACHE)
3631 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3632 if (debug & VP9_DEBUG_CACHE)
3633 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3634
3635 if (raw_mcr_cnt != 0) {
3636 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3637 if (debug & VP9_DEBUG_CACHE)
3638 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3639 } else {
3640 if (debug & VP9_DEBUG_CACHE)
3641 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3642 }
3643 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3644 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3645 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3646 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3647
3648 if (debug & VP9_DEBUG_CACHE)
3649 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3650 if (debug & VP9_DEBUG_CACHE)
3651 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3652
3653 if (raw_mcr_cnt != 0) {
3654 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3655 if (debug & VP9_DEBUG_CACHE)
3656 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3657 } else {
3658 if (debug & VP9_DEBUG_CACHE)
3659 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3660 }
3661 return;
3662}
3663
3664static void decomp_get_comprate(void)
3665{
3666 unsigned raw_ucomp_cnt;
3667 unsigned fast_comp_cnt;
3668 unsigned slow_comp_cnt;
3669 int comprate;
3670
3671 if (debug & VP9_DEBUG_CACHE)
3672 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3673 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3674 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3675 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3676 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3677 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3678 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3679
3680 if (debug & VP9_DEBUG_CACHE)
3681 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3682 if (debug & VP9_DEBUG_CACHE)
3683 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3684 if (debug & VP9_DEBUG_CACHE)
3685 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3686
3687 if (raw_ucomp_cnt != 0) {
3688 comprate = (fast_comp_cnt + slow_comp_cnt)
3689 * 100 / raw_ucomp_cnt;
3690 if (debug & VP9_DEBUG_CACHE)
3691 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3692 } else {
3693 if (debug & VP9_DEBUG_CACHE)
3694 pr_info("DECOMP_COMP_RATIO : na\n");
3695 }
3696 return;
3697}
3698/* cache_util.c end */
3699
3700/*====================================================
3701 *========================================================================
3702 *vp9_prob define
3703 *========================================================================
3704 */
3705#define VP9_PARTITION_START 0
3706#define VP9_PARTITION_SIZE_STEP (3 * 4)
3707#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3708#define VP9_PARTITION_KEY_START 0
3709#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3710#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3711#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3712#define VP9_SKIP_SIZE 4 /* only use 3*/
3713#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3714#define VP9_TX_MODE_8_0_OFFSET 0
3715#define VP9_TX_MODE_8_1_OFFSET 1
3716#define VP9_TX_MODE_16_0_OFFSET 2
3717#define VP9_TX_MODE_16_1_OFFSET 4
3718#define VP9_TX_MODE_32_0_OFFSET 6
3719#define VP9_TX_MODE_32_1_OFFSET 9
3720#define VP9_TX_MODE_SIZE 12
3721#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3722#define VP9_COEF_BAND_0_OFFSET 0
3723#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3724#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3725#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3726#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3727#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3728#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3729#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3730#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3731#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3732#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3733#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3734#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3735#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3736#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3737#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3738#define VP9_INTERP_SIZE 8
3739#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3740#define VP9_INTRA_INTER_SIZE 4
3741#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3742#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3743#define VP9_COMP_INTER_START \
3744 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3745#define VP9_COMP_INTER_SIZE 5
3746#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3747#define VP9_COMP_REF_SIZE 5
3748#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3749#define VP9_SINGLE_REF_SIZE 10
3750#define VP9_REF_MODE_START VP9_COMP_INTER_START
3751#define VP9_REF_MODE_SIZE \
3752 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3753#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3754#define VP9_IF_Y_MODE_SIZE 36
3755#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3756#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3757#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3758#define VP9_MV_JOINTS_SIZE 3
3759#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3760#define VP9_MV_SIGN_0_SIZE 1
3761#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3762#define VP9_MV_CLASSES_0_SIZE 10
3763#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3764#define VP9_MV_CLASS0_0_SIZE 1
3765#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3766#define VP9_MV_BITS_0_SIZE 10
3767#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3768#define VP9_MV_SIGN_1_SIZE 1
3769#define VP9_MV_CLASSES_1_START \
3770 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3771#define VP9_MV_CLASSES_1_SIZE 10
3772#define VP9_MV_CLASS0_1_START \
3773 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3774#define VP9_MV_CLASS0_1_SIZE 1
3775#define VP9_MV_BITS_1_START \
3776 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3777#define VP9_MV_BITS_1_SIZE 10
3778#define VP9_MV_CLASS0_FP_0_START \
3779 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3780#define VP9_MV_CLASS0_FP_0_SIZE 9
3781#define VP9_MV_CLASS0_FP_1_START \
3782 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3783#define VP9_MV_CLASS0_FP_1_SIZE 9
3784#define VP9_MV_CLASS0_HP_0_START \
3785 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3786#define VP9_MV_CLASS0_HP_0_SIZE 2
3787#define VP9_MV_CLASS0_HP_1_START \
3788 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3789#define VP9_MV_CLASS0_HP_1_SIZE 2
3790#define VP9_MV_START VP9_MV_JOINTS_START
3791#define VP9_MV_SIZE 72 /*only use 69*/
3792
3793#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3794
3795
3796/*========================================================================
3797 * vp9_count_mem define
3798 *========================================================================
3799 */
3800#define VP9_COEF_COUNT_START 0
3801#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3802#define VP9_COEF_COUNT_BAND_1_OFFSET \
3803 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3804#define VP9_COEF_COUNT_BAND_2_OFFSET \
3805 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3806#define VP9_COEF_COUNT_BAND_3_OFFSET \
3807 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3808#define VP9_COEF_COUNT_BAND_4_OFFSET \
3809 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3810#define VP9_COEF_COUNT_BAND_5_OFFSET \
3811 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3812#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3813#define VP9_COEF_COUNT_4X4_START \
3814 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3815#define VP9_COEF_COUNT_8X8_START \
3816 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3817#define VP9_COEF_COUNT_16X16_START \
3818 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3819#define VP9_COEF_COUNT_32X32_START \
3820 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3821#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3822#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3823
3824#define VP9_INTRA_INTER_COUNT_START \
3825 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3826#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3827#define VP9_COMP_INTER_COUNT_START \
3828 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3829#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3830#define VP9_COMP_REF_COUNT_START \
3831 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3832#define VP9_COMP_REF_COUNT_SIZE (5*2)
3833#define VP9_SINGLE_REF_COUNT_START \
3834 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3835#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3836#define VP9_TX_MODE_COUNT_START \
3837 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3838#define VP9_TX_MODE_COUNT_SIZE (12*2)
3839#define VP9_SKIP_COUNT_START \
3840 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3841#define VP9_SKIP_COUNT_SIZE (3*2)
3842#define VP9_MV_SIGN_0_COUNT_START \
3843 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3844#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3845#define VP9_MV_SIGN_1_COUNT_START \
3846 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3847#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3848#define VP9_MV_BITS_0_COUNT_START \
3849 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3850#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3851#define VP9_MV_BITS_1_COUNT_START \
3852 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3853#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3854#define VP9_MV_CLASS0_HP_0_COUNT_START \
3855 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3856#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3857#define VP9_MV_CLASS0_HP_1_COUNT_START \
3858 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3859#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3860/* Start merge_tree*/
3861#define VP9_INTER_MODE_COUNT_START \
3862 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3863#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3864#define VP9_IF_Y_MODE_COUNT_START \
3865 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3866#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3867#define VP9_IF_UV_MODE_COUNT_START \
3868 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3869#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3870#define VP9_PARTITION_P_COUNT_START \
3871 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3872#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3873#define VP9_INTERP_COUNT_START \
3874 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3875#define VP9_INTERP_COUNT_SIZE (4*3)
3876#define VP9_MV_JOINTS_COUNT_START \
3877 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3878#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3879#define VP9_MV_CLASSES_0_COUNT_START \
3880 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3881#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3882#define VP9_MV_CLASS0_0_COUNT_START \
3883 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3884#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3885#define VP9_MV_CLASSES_1_COUNT_START \
3886 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3887#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3888#define VP9_MV_CLASS0_1_COUNT_START \
3889 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3890#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3891#define VP9_MV_CLASS0_FP_0_COUNT_START \
3892 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3893#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3894#define VP9_MV_CLASS0_FP_1_COUNT_START \
3895 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3896#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3897
3898
3899#define DC_PRED 0 /* Average of above and left pixels*/
3900#define V_PRED 1 /* Vertical*/
3901#define H_PRED 2 /* Horizontal*/
3902#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3903#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3904#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3905#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3906#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3907#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3908#define TM_PRED 9 /*True-motion*/
3909
3910int clip_prob(int p)
3911{
3912 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3913}
3914
3915#define ROUND_POWER_OF_TWO(value, n) \
3916 (((value) + (1 << ((n) - 1))) >> (n))
3917
3918#define MODE_MV_COUNT_SAT 20
3919static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3920 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3921 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3922};
3923
3924void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3925 int coef_node_start, int tree_left, int tree_right, int tree_i,
3926 int node) {
3927
3928 int prob_32, prob_res, prob_shift;
3929 int pre_prob, new_prob;
3930 int den, m_count, get_prob, factor;
3931
3932 prob_32 = prev_prob[coef_node_start / 4 * 2];
3933 prob_res = coef_node_start & 3;
3934 prob_shift = prob_res * 8;
3935 pre_prob = (prob_32 >> prob_shift) & 0xff;
3936
3937 den = tree_left + tree_right;
3938
3939 if (den == 0)
3940 new_prob = pre_prob;
3941 else {
3942 m_count = (den < MODE_MV_COUNT_SAT) ?
3943 den : MODE_MV_COUNT_SAT;
3944 get_prob = clip_prob(
3945 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3946 den));
3947 /*weighted_prob*/
3948 factor = count_to_update_factor[m_count];
3949 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3950 + get_prob * factor, 8);
3951 }
3952 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3953 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
3954
3955 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3956 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3957 *cur_prob[coef_node_start/4*2]);
3958 */
3959}
3960
3961
3962/*void adapt_coef_probs(void)*/
3963void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3964 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3965{
3966 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3967 *unsigned int prev_prob[496*2];
3968 *unsigned int cur_prob[496*2];
3969 *0x300 * 128bits = 0x3000 (32K Bytes)
3970 *unsigned int count[0x300*4];
3971 */
3972
3973 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
3974 int plane, coef_plane_start, coef_count_plane_start;
3975 int type, coef_type_start, coef_count_type_start;
3976 int band, coef_band_start, coef_count_band_start;
3977 int cxt_num;
3978 int cxt, coef_cxt_start, coef_count_cxt_start;
3979 int node, coef_node_start, coef_count_node_start;
3980
3981 int tree_i, tree_left, tree_right;
3982 int mvd_i;
3983
3984 int count_sat = 24;
3985 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
3986 *use 128
3987 */
3988 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
3989 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
3990 int update_factor = cur_kf ? 112 :
3991 prev_kf ? 128 : 112;
3992
3993 int prob_32;
3994 int prob_res;
3995 int prob_shift;
3996 int pre_prob;
3997
3998 int num, den;
3999 int get_prob;
4000 int m_count;
4001 int factor;
4002
4003 int new_prob;
4004
4005 if (debug & VP9_DEBUG_MERGE)
4006 pr_info
4007 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4008 pre_fc, prev_kf, cur_kf);
4009
4010 /*adapt_coef_probs*/
4011 for (tx_size = 0; tx_size < 4; tx_size++) {
4012 coef_tx_size_start = VP9_COEF_START
4013 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4014 coef_count_tx_size_start = VP9_COEF_COUNT_START
4015 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4016 coef_plane_start = coef_tx_size_start;
4017 coef_count_plane_start = coef_count_tx_size_start;
4018 for (plane = 0; plane < 2; plane++) {
4019 coef_type_start = coef_plane_start;
4020 coef_count_type_start = coef_count_plane_start;
4021 for (type = 0; type < 2; type++) {
4022 coef_band_start = coef_type_start;
4023 coef_count_band_start = coef_count_type_start;
4024 for (band = 0; band < 6; band++) {
4025 if (band == 0)
4026 cxt_num = 3;
4027 else
4028 cxt_num = 6;
4029 coef_cxt_start = coef_band_start;
4030 coef_count_cxt_start =
4031 coef_count_band_start;
4032 for (cxt = 0; cxt < cxt_num; cxt++) {
4033 const int n0 =
4034 count[coef_count_cxt_start];
4035 const int n1 =
4036 count[coef_count_cxt_start + 1];
4037 const int n2 =
4038 count[coef_count_cxt_start + 2];
4039 const int neob =
4040 count[coef_count_cxt_start + 3];
4041 const int nneob =
4042 count[coef_count_cxt_start + 4];
4043 const unsigned int
4044 branch_ct[3][2] = {
4045 { neob, nneob },
4046 { n0, n1 + n2 },
4047 { n1, n2 }
4048 };
4049 coef_node_start =
4050 coef_cxt_start;
4051 for
4052 (node = 0; node < 3; node++) {
4053 prob_32 =
4054 prev_prob[
4055 coef_node_start
4056 / 4 * 2];
4057 prob_res =
4058 coef_node_start & 3;
4059 prob_shift =
4060 prob_res * 8;
4061 pre_prob =
4062 (prob_32 >> prob_shift)
4063 & 0xff;
4064
4065 /*get_binary_prob*/
4066 num =
4067 branch_ct[node][0];
4068 den =
4069 branch_ct[node][0] +
4070 branch_ct[node][1];
4071 m_count = (den <
4072 count_sat)
4073 ? den : count_sat;
4074
4075 get_prob =
4076 (den == 0) ? 128u :
4077 clip_prob(
4078 div_r32(((int64_t)
4079 num * 256
4080 + (den >> 1)),
4081 den));
4082
4083 factor =
4084 update_factor * m_count
4085 / count_sat;
4086 new_prob =
4087 ROUND_POWER_OF_TWO
4088 (pre_prob *
4089 (256 - factor) +
4090 get_prob * factor, 8);
4091
4092 cur_prob[coef_node_start
4093 / 4 * 2] =
4094 (cur_prob
4095 [coef_node_start
4096 / 4 * 2] & (~(0xff <<
4097 prob_shift))) |
4098 (new_prob <<
4099 prob_shift);
4100
4101 coef_node_start += 1;
4102 }
4103
4104 coef_cxt_start =
4105 coef_cxt_start + 3;
4106 coef_count_cxt_start =
4107 coef_count_cxt_start
4108 + 5;
4109 }
4110 if (band == 0) {
4111 coef_band_start += 10;
4112 coef_count_band_start += 15;
4113 } else {
4114 coef_band_start += 18;
4115 coef_count_band_start += 30;
4116 }
4117 }
4118 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4119 coef_count_type_start +=
4120 VP9_COEF_COUNT_SIZE_ONE_SET;
4121 }
4122 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4123 coef_count_plane_start +=
4124 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4125 }
4126 }
4127
4128 if (cur_kf == 0) {
4129 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4130 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4131 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4132 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4133
4134 if (coef_count_node_start ==
4135 VP9_INTRA_INTER_COUNT_START) {
4136 if (debug & VP9_DEBUG_MERGE)
4137 pr_info(" # merge_intra_inter_prob\n");
4138 coef_node_start = VP9_INTRA_INTER_START;
4139 } else if (coef_count_node_start ==
4140 VP9_COMP_INTER_COUNT_START) {
4141 if (debug & VP9_DEBUG_MERGE)
4142 pr_info(" # merge_comp_inter_prob\n");
4143 coef_node_start = VP9_COMP_INTER_START;
4144 }
4145 /*
4146 *else if (coef_count_node_start ==
4147 * VP9_COMP_REF_COUNT_START) {
4148 * pr_info(" # merge_comp_inter_prob\n");
4149 * coef_node_start = VP9_COMP_REF_START;
4150 *}
4151 *else if (coef_count_node_start ==
4152 * VP9_SINGLE_REF_COUNT_START) {
4153 * pr_info(" # merge_comp_inter_prob\n");
4154 * coef_node_start = VP9_SINGLE_REF_START;
4155 *}
4156 */
4157 else if (coef_count_node_start ==
4158 VP9_TX_MODE_COUNT_START) {
4159 if (debug & VP9_DEBUG_MERGE)
4160 pr_info(" # merge_tx_mode_probs\n");
4161 coef_node_start = VP9_TX_MODE_START;
4162 } else if (coef_count_node_start ==
4163 VP9_SKIP_COUNT_START) {
4164 if (debug & VP9_DEBUG_MERGE)
4165 pr_info(" # merge_skip_probs\n");
4166 coef_node_start = VP9_SKIP_START;
4167 } else if (coef_count_node_start ==
4168 VP9_MV_SIGN_0_COUNT_START) {
4169 if (debug & VP9_DEBUG_MERGE)
4170 pr_info(" # merge_sign_0\n");
4171 coef_node_start = VP9_MV_SIGN_0_START;
4172 } else if (coef_count_node_start ==
4173 VP9_MV_SIGN_1_COUNT_START) {
4174 if (debug & VP9_DEBUG_MERGE)
4175 pr_info(" # merge_sign_1\n");
4176 coef_node_start = VP9_MV_SIGN_1_START;
4177 } else if (coef_count_node_start ==
4178 VP9_MV_BITS_0_COUNT_START) {
4179 if (debug & VP9_DEBUG_MERGE)
4180 pr_info(" # merge_bits_0\n");
4181 coef_node_start = VP9_MV_BITS_0_START;
4182 } else if (coef_count_node_start ==
4183 VP9_MV_BITS_1_COUNT_START) {
4184 if (debug & VP9_DEBUG_MERGE)
4185 pr_info(" # merge_bits_1\n");
4186 coef_node_start = VP9_MV_BITS_1_START;
4187 } else if (coef_count_node_start ==
4188 VP9_MV_CLASS0_HP_0_COUNT_START) {
4189 if (debug & VP9_DEBUG_MERGE)
4190 pr_info(" # merge_class0_hp\n");
4191 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4192 }
4193
4194
4195 den = count[coef_count_node_start] +
4196 count[coef_count_node_start + 1];
4197
4198 prob_32 = prev_prob[coef_node_start / 4 * 2];
4199 prob_res = coef_node_start & 3;
4200 prob_shift = prob_res * 8;
4201 pre_prob = (prob_32 >> prob_shift) & 0xff;
4202
4203 if (den == 0)
4204 new_prob = pre_prob;
4205 else {
4206 m_count = (den < MODE_MV_COUNT_SAT) ?
4207 den : MODE_MV_COUNT_SAT;
4208 get_prob =
4209 clip_prob(
4210 div_r32(((int64_t)count[coef_count_node_start]
4211 * 256 + (den >> 1)),
4212 den));
4213 /*weighted_prob*/
4214 factor = count_to_update_factor[m_count];
4215 new_prob =
4216 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4217 + get_prob * factor, 8);
4218 }
4219 cur_prob[coef_node_start / 4 * 2] =
4220 (cur_prob[coef_node_start / 4 * 2] &
4221 (~(0xff << prob_shift)))
4222 | (new_prob << prob_shift);
4223
4224 coef_node_start = coef_node_start + 1;
4225 }
4226 if (debug & VP9_DEBUG_MERGE)
4227 pr_info(" # merge_vp9_inter_mode_tree\n");
4228 coef_node_start = VP9_INTER_MODE_START;
4229 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4230 for (tree_i = 0; tree_i < 7; tree_i++) {
4231 for (node = 0; node < 3; node++) {
4232 switch (node) {
4233 case 2:
4234 tree_left =
4235 count[coef_count_node_start + 1];
4236 tree_right =
4237 count[coef_count_node_start + 3];
4238 break;
4239 case 1:
4240 tree_left =
4241 count[coef_count_node_start + 0];
4242 tree_right =
4243 count[coef_count_node_start + 1]
4244 + count[coef_count_node_start + 3];
4245 break;
4246 default:
4247 tree_left =
4248 count[coef_count_node_start + 2];
4249 tree_right =
4250 count[coef_count_node_start + 0]
4251 + count[coef_count_node_start + 1]
4252 + count[coef_count_node_start + 3];
4253 break;
4254
4255 }
4256
4257 vp9_tree_merge_probs(prev_prob, cur_prob,
4258 coef_node_start, tree_left, tree_right,
4259 tree_i, node);
4260
4261 coef_node_start = coef_node_start + 1;
4262 }
4263 coef_count_node_start = coef_count_node_start + 4;
4264 }
4265 if (debug & VP9_DEBUG_MERGE)
4266 pr_info(" # merge_vp9_intra_mode_tree\n");
4267 coef_node_start = VP9_IF_Y_MODE_START;
4268 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4269 for (tree_i = 0; tree_i < 14; tree_i++) {
4270 for (node = 0; node < 9; node++) {
4271 switch (node) {
4272 case 8:
4273 tree_left =
4274 count[coef_count_node_start+D153_PRED];
4275 tree_right =
4276 count[coef_count_node_start+D207_PRED];
4277 break;
4278 case 7:
4279 tree_left =
4280 count[coef_count_node_start+D63_PRED];
4281 tree_right =
4282 count[coef_count_node_start+D207_PRED] +
4283 count[coef_count_node_start+D153_PRED];
4284 break;
4285 case 6:
4286 tree_left =
4287 count[coef_count_node_start + D45_PRED];
4288 tree_right =
4289 count[coef_count_node_start+D207_PRED] +
4290 count[coef_count_node_start+D153_PRED] +
4291 count[coef_count_node_start+D63_PRED];
4292 break;
4293 case 5:
4294 tree_left =
4295 count[coef_count_node_start+D135_PRED];
4296 tree_right =
4297 count[coef_count_node_start+D117_PRED];
4298 break;
4299 case 4:
4300 tree_left =
4301 count[coef_count_node_start+H_PRED];
4302 tree_right =
4303 count[coef_count_node_start+D117_PRED] +
4304 count[coef_count_node_start+D135_PRED];
4305 break;
4306 case 3:
4307 tree_left =
4308 count[coef_count_node_start+H_PRED] +
4309 count[coef_count_node_start+D117_PRED] +
4310 count[coef_count_node_start+D135_PRED];
4311 tree_right =
4312 count[coef_count_node_start+D45_PRED] +
4313 count[coef_count_node_start+D207_PRED] +
4314 count[coef_count_node_start+D153_PRED] +
4315 count[coef_count_node_start+D63_PRED];
4316 break;
4317 case 2:
4318 tree_left =
4319 count[coef_count_node_start+V_PRED];
4320 tree_right =
4321 count[coef_count_node_start+H_PRED] +
4322 count[coef_count_node_start+D117_PRED] +
4323 count[coef_count_node_start+D135_PRED] +
4324 count[coef_count_node_start+D45_PRED] +
4325 count[coef_count_node_start+D207_PRED] +
4326 count[coef_count_node_start+D153_PRED] +
4327 count[coef_count_node_start+D63_PRED];
4328 break;
4329 case 1:
4330 tree_left =
4331 count[coef_count_node_start+TM_PRED];
4332 tree_right =
4333 count[coef_count_node_start+V_PRED] +
4334 count[coef_count_node_start+H_PRED] +
4335 count[coef_count_node_start+D117_PRED] +
4336 count[coef_count_node_start+D135_PRED] +
4337 count[coef_count_node_start+D45_PRED] +
4338 count[coef_count_node_start+D207_PRED] +
4339 count[coef_count_node_start+D153_PRED] +
4340 count[coef_count_node_start+D63_PRED];
4341 break;
4342 default:
4343 tree_left =
4344 count[coef_count_node_start+DC_PRED];
4345 tree_right =
4346 count[coef_count_node_start+TM_PRED] +
4347 count[coef_count_node_start+V_PRED] +
4348 count[coef_count_node_start+H_PRED] +
4349 count[coef_count_node_start+D117_PRED] +
4350 count[coef_count_node_start+D135_PRED] +
4351 count[coef_count_node_start+D45_PRED] +
4352 count[coef_count_node_start+D207_PRED] +
4353 count[coef_count_node_start+D153_PRED] +
4354 count[coef_count_node_start+D63_PRED];
4355 break;
4356
4357 }
4358
4359 vp9_tree_merge_probs(prev_prob, cur_prob,
4360 coef_node_start, tree_left, tree_right,
4361 tree_i, node);
4362
4363 coef_node_start = coef_node_start + 1;
4364 }
4365 coef_count_node_start = coef_count_node_start + 10;
4366 }
4367
4368 if (debug & VP9_DEBUG_MERGE)
4369 pr_info(" # merge_vp9_partition_tree\n");
4370 coef_node_start = VP9_PARTITION_P_START;
4371 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4372 for (tree_i = 0; tree_i < 16; tree_i++) {
4373 for (node = 0; node < 3; node++) {
4374 switch (node) {
4375 case 2:
4376 tree_left =
4377 count[coef_count_node_start + 2];
4378 tree_right =
4379 count[coef_count_node_start + 3];
4380 break;
4381 case 1:
4382 tree_left =
4383 count[coef_count_node_start + 1];
4384 tree_right =
4385 count[coef_count_node_start + 2] +
4386 count[coef_count_node_start + 3];
4387 break;
4388 default:
4389 tree_left =
4390 count[coef_count_node_start + 0];
4391 tree_right =
4392 count[coef_count_node_start + 1] +
4393 count[coef_count_node_start + 2] +
4394 count[coef_count_node_start + 3];
4395 break;
4396
4397 }
4398
4399 vp9_tree_merge_probs(prev_prob, cur_prob,
4400 coef_node_start,
4401 tree_left, tree_right, tree_i, node);
4402
4403 coef_node_start = coef_node_start + 1;
4404 }
4405 coef_count_node_start = coef_count_node_start + 4;
4406 }
4407
4408 if (debug & VP9_DEBUG_MERGE)
4409 pr_info(" # merge_vp9_switchable_interp_tree\n");
4410 coef_node_start = VP9_INTERP_START;
4411 coef_count_node_start = VP9_INTERP_COUNT_START;
4412 for (tree_i = 0; tree_i < 4; tree_i++) {
4413 for (node = 0; node < 2; node++) {
4414 switch (node) {
4415 case 1:
4416 tree_left =
4417 count[coef_count_node_start + 1];
4418 tree_right =
4419 count[coef_count_node_start + 2];
4420 break;
4421 default:
4422 tree_left =
4423 count[coef_count_node_start + 0];
4424 tree_right =
4425 count[coef_count_node_start + 1] +
4426 count[coef_count_node_start + 2];
4427 break;
4428
4429 }
4430
4431 vp9_tree_merge_probs(prev_prob, cur_prob,
4432 coef_node_start,
4433 tree_left, tree_right, tree_i, node);
4434
4435 coef_node_start = coef_node_start + 1;
4436 }
4437 coef_count_node_start = coef_count_node_start + 3;
4438 }
4439
4440 if (debug & VP9_DEBUG_MERGE)
4441 pr_info("# merge_vp9_mv_joint_tree\n");
4442 coef_node_start = VP9_MV_JOINTS_START;
4443 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4444 for (tree_i = 0; tree_i < 1; tree_i++) {
4445 for (node = 0; node < 3; node++) {
4446 switch (node) {
4447 case 2:
4448 tree_left =
4449 count[coef_count_node_start + 2];
4450 tree_right =
4451 count[coef_count_node_start + 3];
4452 break;
4453 case 1:
4454 tree_left =
4455 count[coef_count_node_start + 1];
4456 tree_right =
4457 count[coef_count_node_start + 2] +
4458 count[coef_count_node_start + 3];
4459 break;
4460 default:
4461 tree_left =
4462 count[coef_count_node_start + 0];
4463 tree_right =
4464 count[coef_count_node_start + 1] +
4465 count[coef_count_node_start + 2] +
4466 count[coef_count_node_start + 3];
4467 break;
4468 }
4469
4470 vp9_tree_merge_probs(prev_prob, cur_prob,
4471 coef_node_start,
4472 tree_left, tree_right, tree_i, node);
4473
4474 coef_node_start = coef_node_start + 1;
4475 }
4476 coef_count_node_start = coef_count_node_start + 4;
4477 }
4478
4479 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4480 if (debug & VP9_DEBUG_MERGE)
4481 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4482 coef_node_start =
4483 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4484 coef_count_node_start =
4485 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4486 : VP9_MV_CLASSES_0_COUNT_START;
4487 tree_i = 0;
4488 for (node = 0; node < 10; node++) {
4489 switch (node) {
4490 case 9:
4491 tree_left =
4492 count[coef_count_node_start + 9];
4493 tree_right =
4494 count[coef_count_node_start + 10];
4495 break;
4496 case 8:
4497 tree_left =
4498 count[coef_count_node_start + 7];
4499 tree_right =
4500 count[coef_count_node_start + 8];
4501 break;
4502 case 7:
4503 tree_left =
4504 count[coef_count_node_start + 7] +
4505 count[coef_count_node_start + 8];
4506 tree_right =
4507 count[coef_count_node_start + 9] +
4508 count[coef_count_node_start + 10];
4509 break;
4510 case 6:
4511 tree_left =
4512 count[coef_count_node_start + 6];
4513 tree_right =
4514 count[coef_count_node_start + 7] +
4515 count[coef_count_node_start + 8] +
4516 count[coef_count_node_start + 9] +
4517 count[coef_count_node_start + 10];
4518 break;
4519 case 5:
4520 tree_left =
4521 count[coef_count_node_start + 4];
4522 tree_right =
4523 count[coef_count_node_start + 5];
4524 break;
4525 case 4:
4526 tree_left =
4527 count[coef_count_node_start + 4] +
4528 count[coef_count_node_start + 5];
4529 tree_right =
4530 count[coef_count_node_start + 6] +
4531 count[coef_count_node_start + 7] +
4532 count[coef_count_node_start + 8] +
4533 count[coef_count_node_start + 9] +
4534 count[coef_count_node_start + 10];
4535 break;
4536 case 3:
4537 tree_left =
4538 count[coef_count_node_start + 2];
4539 tree_right =
4540 count[coef_count_node_start + 3];
4541 break;
4542 case 2:
4543 tree_left =
4544 count[coef_count_node_start + 2] +
4545 count[coef_count_node_start + 3];
4546 tree_right =
4547 count[coef_count_node_start + 4] +
4548 count[coef_count_node_start + 5] +
4549 count[coef_count_node_start + 6] +
4550 count[coef_count_node_start + 7] +
4551 count[coef_count_node_start + 8] +
4552 count[coef_count_node_start + 9] +
4553 count[coef_count_node_start + 10];
4554 break;
4555 case 1:
4556 tree_left =
4557 count[coef_count_node_start + 1];
4558 tree_right =
4559 count[coef_count_node_start + 2] +
4560 count[coef_count_node_start + 3] +
4561 count[coef_count_node_start + 4] +
4562 count[coef_count_node_start + 5] +
4563 count[coef_count_node_start + 6] +
4564 count[coef_count_node_start + 7] +
4565 count[coef_count_node_start + 8] +
4566 count[coef_count_node_start + 9] +
4567 count[coef_count_node_start + 10];
4568 break;
4569 default:
4570 tree_left =
4571 count[coef_count_node_start + 0];
4572 tree_right =
4573 count[coef_count_node_start + 1] +
4574 count[coef_count_node_start + 2] +
4575 count[coef_count_node_start + 3] +
4576 count[coef_count_node_start + 4] +
4577 count[coef_count_node_start + 5] +
4578 count[coef_count_node_start + 6] +
4579 count[coef_count_node_start + 7] +
4580 count[coef_count_node_start + 8] +
4581 count[coef_count_node_start + 9] +
4582 count[coef_count_node_start + 10];
4583 break;
4584
4585 }
4586
4587 vp9_tree_merge_probs(prev_prob, cur_prob,
4588 coef_node_start, tree_left, tree_right,
4589 tree_i, node);
4590
4591 coef_node_start = coef_node_start + 1;
4592 }
4593
4594 if (debug & VP9_DEBUG_MERGE)
4595 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4596 coef_node_start =
4597 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4598 coef_count_node_start =
4599 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4600 VP9_MV_CLASS0_0_COUNT_START;
4601 tree_i = 0;
4602 node = 0;
4603 tree_left = count[coef_count_node_start + 0];
4604 tree_right = count[coef_count_node_start + 1];
4605
4606 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4607 tree_left, tree_right, tree_i, node);
4608 if (debug & VP9_DEBUG_MERGE)
4609 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4610 mvd_i);
4611 coef_node_start =
4612 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4613 VP9_MV_CLASS0_FP_0_START;
4614 coef_count_node_start =
4615 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4616 VP9_MV_CLASS0_FP_0_COUNT_START;
4617 for (tree_i = 0; tree_i < 3; tree_i++) {
4618 for (node = 0; node < 3; node++) {
4619 switch (node) {
4620 case 2:
4621 tree_left =
4622 count[coef_count_node_start + 2];
4623 tree_right =
4624 count[coef_count_node_start + 3];
4625 break;
4626 case 1:
4627 tree_left =
4628 count[coef_count_node_start + 1];
4629 tree_right =
4630 count[coef_count_node_start + 2]
4631 + count[coef_count_node_start + 3];
4632 break;
4633 default:
4634 tree_left =
4635 count[coef_count_node_start + 0];
4636 tree_right =
4637 count[coef_count_node_start + 1]
4638 + count[coef_count_node_start + 2]
4639 + count[coef_count_node_start + 3];
4640 break;
4641
4642 }
4643
4644 vp9_tree_merge_probs(prev_prob, cur_prob,
4645 coef_node_start, tree_left, tree_right,
4646 tree_i, node);
4647
4648 coef_node_start = coef_node_start + 1;
4649 }
4650 coef_count_node_start = coef_count_node_start + 4;
4651 }
4652
4653 } /* for mvd_i (mvd_y or mvd_x)*/
4654}
4655
4656}
4657
4658static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4659{
4660 int i;
4661 struct VP9_Common_s *const cm = &pbi->common;
4662 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4663
4664 for (i = 0; i < pbi->used_buf_num; ++i) {
4665 if (frame_bufs[i].buf.vframe_bound)
4666 return true;
4667 }
4668
4669 return false;
4670}
4671
4672static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4673{
4674 struct VP9_Common_s *const cm = &pbi->common;
4675 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4676 int i;
4677
4678 /* release workspace */
4679 if (pbi->bmmu_box)
4680 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4681 WORK_SPACE_BUF_ID);
4682 /*
4683 * it's only when vframe get back to driver, right now we can be sure
4684 * that vframe and fd are related. if the playback exits, the capture
4685 * requires the upper app to release when the fd is closed, and others
4686 * buffers drivers are released by driver.
4687 */
4688 for (i = 0; i < pbi->used_buf_num; ++i) {
4689 if (!frame_bufs[i].buf.vframe_bound) {
4690 if (pbi->bmmu_box)
4691 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4692 HEADER_BUFFER_IDX(i));
4693 if (pbi->mmu_box)
4694 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4695
4696 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4697 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4698 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4699 }
4700 }
4701}
4702
4703static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4704{
4705#ifndef MV_USE_FIXED_BUF
4706 dealloc_mv_bufs(pbi);
4707#endif
4708 if (pbi->is_used_v4l &&
4709 v4l_is_there_vframe_bound(pbi)) {
4710 if (get_double_write_mode(pbi) != 0x10) {
4711 v4l_mmu_buffer_release(pbi);
4712 return;
4713 }
4714 }
4715
4716 if (pbi->mmu_box)
4717 decoder_mmu_box_free(pbi->mmu_box);
4718 pbi->mmu_box = NULL;
4719
4720 if (pbi->bmmu_box)
4721 decoder_bmmu_box_free(pbi->bmmu_box);
4722 pbi->bmmu_box = NULL;
4723}
4724
4725static int calc_luc_quantity(u32 w, u32 h)
4726{
4727 int lcu_size = 64; /*fixed 64*/
4728 int pic_width_64 = (w + 63) & (~0x3f);
4729 int pic_height_32 = (h + 31) & (~0x1f);
4730 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4731 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4732 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4733 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4734
4735 return pic_width_lcu * pic_height_lcu;
4736}
4737
4738static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4739 struct PIC_BUFFER_CONFIG_s *pic)
4740{
4741 int ret = -1;
4742 int i = pic->index;
4743 int dw_mode = get_double_write_mode_init(pbi);
4744 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4745#ifdef MV_USE_FIXED_BUF
4746 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4747 pbi->work_space_buf->mpred_mv.buf_size;
4748#endif
4749 struct vdec_v4l2_buffer *fb = NULL;
4750
4751 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4752 if (ret < 0) {
4753 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4754 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4755 return ret;
4756 }
4757
4758 if (pbi->mmu_enable) {
4759 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4760 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4761 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4762 pr_info("MMU header_adr %d: %ld\n",
4763 i, pbi->m_BUF[i].header_addr);
4764 }
4765 }
4766
4767#ifdef MV_USE_FIXED_BUF
4768 if ((pbi->work_space_buf->mpred_mv.buf_start +
4769 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4770 <= mpred_mv_end) {
4771#endif
4772 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4773 pic->cma_alloc_addr = fb->m.mem[0].addr;
4774 if (fb->num_planes == 1) {
4775 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4776 pbi->m_BUF[i].size = fb->m.mem[0].size;
4777 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4778 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4779 } else if (fb->num_planes == 2) {
4780 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4781 pbi->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
4782 pbi->m_BUF[i].luma_size = fb->m.mem[0].size;
4783 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4784 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4785 }
4786
4787 /* config frame buffer */
4788 if (pbi->mmu_enable)
4789 pic->header_adr = pbi->m_BUF[i].header_addr;
4790
4791 pic->BUF_index = i;
4792 pic->lcu_total = lcu_total;
4793 pic->mc_canvas_y = pic->index;
4794 pic->mc_canvas_u_v = pic->index;
4795
4796 if (dw_mode & 0x10) {
4797 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4798 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4799 pic->mc_canvas_y = (pic->index << 1);
4800 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4801 } else if (dw_mode) {
4802 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4803 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4804 }
4805
4806#ifdef MV_USE_FIXED_BUF
4807 pic->mpred_mv_wr_start_addr =
4808 pbi->work_space_buf->mpred_mv.buf_start +
4809 ((pic->index * lcu_total) * MV_MEM_UNIT);
4810#endif
4811 if (debug) {
4812 pr_info("%s index %d BUF_index %d ",
4813 __func__, pic->index,
4814 pic->BUF_index);
4815 pr_info("comp_body_size %x comp_buf_size %x ",
4816 pic->comp_body_size,
4817 pic->buf_size);
4818 pr_info("mpred_mv_wr_start_adr %ld\n",
4819 pic->mpred_mv_wr_start_addr);
4820 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4821 pic->dw_y_adr,
4822 pic->dw_u_v_adr);
4823 }
4824#ifdef MV_USE_FIXED_BUF
4825 }
4826#endif
4827 return ret;
4828}
4829
4830static int config_pic(struct VP9Decoder_s *pbi,
4831 struct PIC_BUFFER_CONFIG_s *pic_config)
4832{
4833 int ret = -1;
4834 int i;
4835 int pic_width = pbi->init_pic_w;
4836 int pic_height = pbi->init_pic_h;
4837 int lcu_size = 64; /*fixed 64*/
4838 int pic_width_64 = (pic_width + 63) & (~0x3f);
4839 int pic_height_32 = (pic_height + 31) & (~0x1f);
4840 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4841 pic_width_64 / lcu_size + 1
4842 : pic_width_64 / lcu_size;
4843 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4844 pic_height_32 / lcu_size + 1
4845 : pic_height_32 / lcu_size;
4846 int lcu_total = pic_width_lcu * pic_height_lcu;
4847#ifdef MV_USE_FIXED_BUF
4848 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4849 pbi->work_space_buf->mpred_mv.buf_size;
4850#endif
4851 u32 y_adr = 0;
4852 int buf_size = 0;
4853
4854 int losless_comp_header_size =
4855 compute_losless_comp_header_size(pic_width,
4856 pic_height);
4857 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4858 pic_height, buf_alloc_depth == 10);
4859 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4860 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4861 int mc_buffer_size_u_v = 0;
4862 int mc_buffer_size_u_v_h = 0;
4863 int dw_mode = get_double_write_mode_init(pbi);
4864
4865 pbi->lcu_total = lcu_total;
4866
4867 if (dw_mode) {
4868 int pic_width_dw = pic_width /
4869 get_double_write_ratio(pbi, dw_mode);
4870 int pic_height_dw = pic_height /
4871 get_double_write_ratio(pbi, dw_mode);
4872
4873 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4874 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4875 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4876 pic_width_64_dw / lcu_size + 1
4877 : pic_width_64_dw / lcu_size;
4878 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4879 pic_height_32_dw / lcu_size + 1
4880 : pic_height_32_dw / lcu_size;
4881 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4882 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4883 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4884 /*64k alignment*/
4885 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4886 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4887 }
4888
4889 if (mc_buffer_size & 0xffff) /*64k alignment*/
4890 mc_buffer_size_h += 1;
4891 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4892 buf_size += (mc_buffer_size_h << 16);
4893
4894 if (pbi->mmu_enable) {
4895 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4896 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4897
4898 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4899 pr_info("MMU header_adr %d: %ld\n",
4900 pic_config->index, pic_config->header_adr);
4901 }
4902 }
4903
4904 i = pic_config->index;
4905#ifdef MV_USE_FIXED_BUF
4906 if ((pbi->work_space_buf->mpred_mv.buf_start +
4907 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4908 <= mpred_mv_end
4909 ) {
4910#endif
4911 if (buf_size > 0) {
4912 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4913 VF_BUFFER_IDX(i),
4914 buf_size, DRIVER_NAME,
4915 &pic_config->cma_alloc_addr);
4916 if (ret < 0) {
4917 pr_info(
4918 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4919 VF_BUFFER_IDX(i),
4920 buf_size
4921 );
4922 return ret;
4923 }
4924
4925 if (pic_config->cma_alloc_addr)
4926 y_adr = pic_config->cma_alloc_addr;
4927 else {
4928 pr_info(
4929 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4930 VF_BUFFER_IDX(i),
4931 buf_size
4932 );
4933 return -1;
4934 }
4935 }
4936 {
4937 /*ensure get_pic_by_POC()
4938 not get the buffer not decoded*/
4939 pic_config->BUF_index = i;
4940 pic_config->lcu_total = lcu_total;
4941
4942 pic_config->comp_body_size = losless_comp_body_size;
4943 pic_config->buf_size = buf_size;
4944
4945 pic_config->mc_canvas_y = pic_config->index;
4946 pic_config->mc_canvas_u_v = pic_config->index;
4947 if (dw_mode & 0x10) {
4948 pic_config->dw_y_adr = y_adr;
4949 pic_config->dw_u_v_adr = y_adr +
4950 ((mc_buffer_size_u_v_h << 16) << 1);
4951
4952 pic_config->mc_canvas_y =
4953 (pic_config->index << 1);
4954 pic_config->mc_canvas_u_v =
4955 (pic_config->index << 1) + 1;
4956 } else if (dw_mode) {
4957 pic_config->dw_y_adr = y_adr;
4958 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4959 ((mc_buffer_size_u_v_h << 16) << 1);
4960 }
4961#ifdef MV_USE_FIXED_BUF
4962 pic_config->mpred_mv_wr_start_addr =
4963 pbi->work_space_buf->mpred_mv.buf_start +
4964 ((pic_config->index * lcu_total)
4965 * MV_MEM_UNIT);
4966#endif
4967 if (debug) {
4968 pr_info
4969 ("%s index %d BUF_index %d ",
4970 __func__, pic_config->index,
4971 pic_config->BUF_index);
4972 pr_info
4973 ("comp_body_size %x comp_buf_size %x ",
4974 pic_config->comp_body_size,
4975 pic_config->buf_size);
4976 pr_info
4977 ("mpred_mv_wr_start_adr %ld\n",
4978 pic_config->mpred_mv_wr_start_addr);
4979 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4980 pic_config->dw_y_adr,
4981 pic_config->dw_u_v_adr);
4982 }
4983 ret = 0;
4984 }
4985#ifdef MV_USE_FIXED_BUF
4986 }
4987#endif
4988 return ret;
4989}
4990
4991static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
4992{
4993 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
4994 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
4995 return (MMU_COMPRESS_8K_HEADER_SIZE);
4996
4997 return (MMU_COMPRESS_HEADER_SIZE);
4998}
4999
5000/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5001static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5002{
5003 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5004 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5005 return (MAX_FRAME_8K_NUM * 4);
5006
5007 return (MAX_FRAME_4K_NUM * 4);
5008}
5009
5010static void init_pic_list(struct VP9Decoder_s *pbi)
5011{
5012 int i;
5013 struct VP9_Common_s *cm = &pbi->common;
5014 struct PIC_BUFFER_CONFIG_s *pic_config;
5015 u32 header_size;
5016 struct vdec_s *vdec = hw_to_vdec(pbi);
5017
5018 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5019 header_size = vvp9_mmu_compress_header_size(pbi);
5020 /*alloc VP9 compress header first*/
5021 for (i = 0; i < pbi->used_buf_num; i++) {
5022 unsigned long buf_addr;
5023 if (decoder_bmmu_box_alloc_buf_phy
5024 (pbi->bmmu_box,
5025 HEADER_BUFFER_IDX(i), header_size,
5026 DRIVER_HEADER_NAME,
5027 &buf_addr) < 0) {
5028 pr_info("%s malloc compress header failed %d\n",
5029 DRIVER_HEADER_NAME, i);
5030 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5031 return;
5032 }
5033 }
5034 }
5035 for (i = 0; i < pbi->used_buf_num; i++) {
5036 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5037 pic_config->index = i;
5038 pic_config->BUF_index = -1;
5039 pic_config->mv_buf_index = -1;
5040 if (vdec->parallel_dec == 1) {
5041 pic_config->y_canvas_index = -1;
5042 pic_config->uv_canvas_index = -1;
5043 }
5044 pic_config->y_crop_width = pbi->init_pic_w;
5045 pic_config->y_crop_height = pbi->init_pic_h;
5046 pic_config->double_write_mode = get_double_write_mode(pbi);
5047
5048 if (!pbi->is_used_v4l) {
5049 if (config_pic(pbi, pic_config) < 0) {
5050 if (debug)
5051 pr_info("Config_pic %d fail\n",
5052 pic_config->index);
5053 pic_config->index = -1;
5054 break;
5055 }
5056
5057 if (pic_config->double_write_mode) {
5058 set_canvas(pbi, pic_config);
5059 }
5060 }
5061 }
5062 for (; i < pbi->used_buf_num; i++) {
5063 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5064 pic_config->index = -1;
5065 pic_config->BUF_index = -1;
5066 pic_config->mv_buf_index = -1;
5067 if (vdec->parallel_dec == 1) {
5068 pic_config->y_canvas_index = -1;
5069 pic_config->uv_canvas_index = -1;
5070 }
5071 }
5072 pr_info("%s ok, used_buf_num = %d\n",
5073 __func__, pbi->used_buf_num);
5074}
5075
5076static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5077{
5078 int i;
5079 struct VP9_Common_s *cm = &pbi->common;
5080 struct PIC_BUFFER_CONFIG_s *pic_config;
5081 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5082 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5083 (0x1 << 1) | (0x1 << 2));
5084
5085
5086 for (i = 0; i < pbi->used_buf_num; i++) {
5087 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5088 if (pic_config->index < 0)
5089 break;
5090
5091 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5092
5093 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5094 pic_config->header_adr >> 5);
5095 } else {
5096 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5097 * pic_config->mc_y_adr
5098 * | (pic_config->mc_canvas_y << 8) | 0x1);
5099 */
5100 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5101 pic_config->dw_y_adr >> 5);
5102 }
5103#ifndef LOSLESS_COMPRESS_MODE
5104 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5105 * pic_config->mc_u_v_adr
5106 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5107 */
5108 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5109 pic_config->header_adr >> 5);
5110#else
5111 if (pic_config->double_write_mode & 0x10) {
5112 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5113 pic_config->dw_u_v_adr >> 5);
5114 }
5115#endif
5116 }
5117 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5118
5119 /*Zero out canvas registers in IPP -- avoid simulation X*/
5120 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5121 (0 << 8) | (0 << 1) | 1);
5122 for (i = 0; i < 32; i++)
5123 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5124}
5125
5126
5127static void dump_pic_list(struct VP9Decoder_s *pbi)
5128{
5129 struct VP9_Common_s *const cm = &pbi->common;
5130 struct PIC_BUFFER_CONFIG_s *pic_config;
5131 int i;
5132 for (i = 0; i < FRAME_BUFFERS; i++) {
5133 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5134 vp9_print(pbi, 0,
5135 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5136 i,
5137 pic_config->index,
5138#ifndef MV_USE_FIXED_BUF
5139 pic_config->mv_buf_index,
5140#else
5141 -1,
5142#endif
5143 cm->buffer_pool->
5144 frame_bufs[i].ref_count,
5145 pic_config->vf_ref,
5146 pic_config->decode_idx,
5147 pic_config->slice_type,
5148 pic_config->y_crop_width,
5149 pic_config->y_crop_height,
5150 pic_config->cma_alloc_addr
5151 );
5152 }
5153 return;
5154}
5155
5156static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5157{
5158#ifdef LOSLESS_COMPRESS_MODE
5159 unsigned int data32;
5160#endif
5161 int losless_comp_header_size, losless_comp_body_size;
5162 struct VP9_Common_s *cm = &pbi->common;
5163 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5164
5165 frame_width = cur_pic_config->y_crop_width;
5166 frame_height = cur_pic_config->y_crop_height;
5167 cur_pic_config->bit_depth = bit_depth;
5168 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5169 losless_comp_header_size =
5170 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5171 cur_pic_config->y_crop_height);
5172 losless_comp_body_size =
5173 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5174 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5175 cur_pic_config->comp_body_size = losless_comp_body_size;
5176#ifdef LOSLESS_COMPRESS_MODE
5177 data32 = READ_VREG(HEVC_SAO_CTRL5);
5178 if (bit_depth == VPX_BITS_10)
5179 data32 &= ~(1 << 9);
5180 else
5181 data32 |= (1 << 9);
5182
5183 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5184
5185 if (pbi->mmu_enable) {
5186 /*bit[4] : paged_mem_mode*/
5187 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5188 } else {
5189 /*bit[3] smem mdoe*/
5190 if (bit_depth == VPX_BITS_10)
5191 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5192 else
5193 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5194 }
5195 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5196 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5197 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5198 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5199 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5200 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5201 if (get_double_write_mode(pbi) & 0x10)
5202 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5203#else
5204 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5205#endif
5206 return 0;
5207}
5208
5209static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5210{
5211 int i;
5212 struct VP9_Common_s *cm = &pbi->common;
5213 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5214 uint8_t scale_enable = 0;
5215
5216 if (debug&VP9_DEBUG_BUFMGR_MORE)
5217 pr_info("config_mc_buffer entered .....\n");
5218
5219 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5220 (0 << 8) | (0 << 1) | 1);
5221 for (i = 0; i < REFS_PER_FRAME; ++i) {
5222 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5223 if (!pic_config)
5224 continue;
5225 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5226 (pic_config->mc_canvas_u_v << 16)
5227 | (pic_config->mc_canvas_u_v << 8)
5228 | pic_config->mc_canvas_y);
5229 if (debug & VP9_DEBUG_BUFMGR_MORE)
5230 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5231 i, pic_config->mc_canvas_u_v,
5232 pic_config->mc_canvas_y);
5233 }
5234 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5235 (16 << 8) | (0 << 1) | 1);
5236 for (i = 0; i < REFS_PER_FRAME; ++i) {
5237 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5238 if (!pic_config)
5239 continue;
5240 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5241 (pic_config->mc_canvas_u_v << 16)
5242 | (pic_config->mc_canvas_u_v << 8)
5243 | pic_config->mc_canvas_y);
5244 }
5245
5246 /*auto_inc start index:0 field:0*/
5247 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5248 /*index 0:last 1:golden 2:altref*/
5249 for (i = 0; i < REFS_PER_FRAME; i++) {
5250 int ref_pic_body_size;
5251 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5252 if (!pic_config)
5253 continue;
5254 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5255 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5256
5257 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5258 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5259 scale_enable |= (1 << i);
5260 }
5261 ref_pic_body_size =
5262 compute_losless_comp_body_size(pic_config->y_crop_width,
5263 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5264 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5265 (pic_config->y_crop_width << 14)
5266 / cur_pic_config->y_crop_width);
5267 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5268 (pic_config->y_crop_height << 14)
5269 / cur_pic_config->y_crop_height);
5270 if (pbi->mmu_enable)
5271 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5272 else
5273 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5274 }
5275 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5276 return 0;
5277}
5278
5279static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5280{
5281 unsigned int data32;
5282
5283 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5284 data32 &= (~(1 << 6));
5285 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5286}
5287
5288static void config_mpred_hw(struct VP9Decoder_s *pbi)
5289{
5290 struct VP9_Common_s *cm = &pbi->common;
5291 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5292 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5293 &cm->prev_frame->buf;
5294
5295 unsigned int data32;
5296 int mpred_curr_lcu_x;
5297 int mpred_curr_lcu_y;
5298 int mpred_mv_rd_end_addr;
5299
5300
5301 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5302 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5303
5304 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5305 mpred_curr_lcu_x = data32 & 0xffff;
5306 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5307
5308 if (debug & VP9_DEBUG_BUFMGR)
5309 pr_info("cur pic_config index %d col pic_config index %d\n",
5310 cur_pic_config->index, last_frame_pic_config->index);
5311 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5312 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5313 pbi->work_space_buf->mpred_above.buf_start);
5314
5315 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5316
5317 data32 &= (~(1 << 6));
5318 data32 |= (cm->use_prev_frame_mvs << 6);
5319 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5320
5321 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5322 cur_pic_config->mpred_mv_wr_start_addr);
5323 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5324
5325 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5326 last_frame_pic_config->mpred_mv_wr_start_addr);
5327 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5328 last_frame_pic_config->mpred_mv_wr_start_addr);
5329 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5330 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5331 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5332 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5333
5334}
5335
5336static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5337{
5338 struct VP9_Common_s *cm = &pbi->common;
5339 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5340
5341 unsigned int data32;
5342 int lcu_size = 64;
5343 int mc_buffer_size_u_v =
5344 pic_config->lcu_total * lcu_size*lcu_size/2;
5345 int mc_buffer_size_u_v_h =
5346 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5347 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5348
5349 if (get_double_write_mode(pbi)) {
5350 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5351 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5352 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5353 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5354 } else {
5355 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5356 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5357 }
5358 if (pbi->mmu_enable)
5359 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5360
5361 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5362 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5363 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5364 */
5365 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5366
5367 data32 = (mc_buffer_size_u_v_h << 16);
5368 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5369
5370#ifdef VP9_10B_NV21
5371#ifdef DOS_PROJECT
5372 data32 = READ_VREG(HEVC_SAO_CTRL1);
5373 data32 &= (~0x3000);
5374 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5375 data32 |= (pbi->mem_map_mode << 12);
5376 data32 &= (~0x3);
5377 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5378 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5379 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5380 * [17:16] dw_h0_ctrl
5381 */
5382 data32 = READ_VREG(HEVC_SAO_CTRL5);
5383 /*set them all 0 for H265_NV21 (no down-scale)*/
5384 data32 &= ~(0xff << 16);
5385 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5386 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5387 data32 &= (~0x30);
5388 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5389 data32 |= (pbi->mem_map_mode << 4);
5390 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5391#else
5392 /*m8baby test1902*/
5393 data32 = READ_VREG(HEVC_SAO_CTRL1);
5394 data32 &= (~0x3000);
5395 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5396 data32 |= (pbi->mem_map_mode << 12);
5397 data32 &= (~0xff0);
5398 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5399 data32 |= 0x880; /*.Big-Endian per 64-bit */
5400 data32 &= (~0x3);
5401 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5402 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5403 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5404 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5405 */
5406 data32 = READ_VREG(HEVC_SAO_CTRL5);
5407 /* set them all 0 for H265_NV21 (no down-scale)*/
5408 data32 &= ~(0xff << 16);
5409 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5410
5411 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5412 data32 &= (~0x30);
5413 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5414 data32 |= (pbi->mem_map_mode << 4);
5415 data32 &= (~0xF);
5416 data32 |= 0x8; /*Big-Endian per 64-bit*/
5417 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5418#endif
5419#else
5420 data32 = READ_VREG(HEVC_SAO_CTRL1);
5421 data32 &= (~0x3000);
5422 data32 |= (pbi->mem_map_mode <<
5423 12);
5424
5425/* [13:12] axi_aformat, 0-Linear,
5426 * 1-32x32, 2-64x32
5427 */
5428 data32 &= (~0xff0);
5429 /* data32 |= 0x670; // Big-Endian per 64-bit */
5430 data32 |= endian; /* Big-Endian per 64-bit */
5431 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5432 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5433 if (get_double_write_mode(pbi) == 0)
5434 data32 |= 0x2; /*disable double write*/
5435 else if (get_double_write_mode(pbi) & 0x10)
5436 data32 |= 0x1; /*disable cm*/
5437 } else { /* >= G12A dw write control */
5438 unsigned int data;
5439 data = READ_VREG(HEVC_DBLK_CFGB);
5440 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5441 if (get_double_write_mode(pbi) == 0)
5442 data |= (0x1 << 8); /*enable first write*/
5443 else if (get_double_write_mode(pbi) & 0x10)
5444 data |= (0x1 << 9); /*double write only*/
5445 else
5446 data |= ((0x1 << 8) |(0x1 << 9));
5447 WRITE_VREG(HEVC_DBLK_CFGB, data);
5448 }
5449
5450 /* swap uv */
5451 if (pbi->is_used_v4l) {
5452 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5453 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5454 data32 &= ~(1 << 8); /* NV21 */
5455 else
5456 data32 |= (1 << 8); /* NV12 */
5457 }
5458
5459 /*
5460 * [31:24] ar_fifo1_axi_thred
5461 * [23:16] ar_fifo0_axi_thred
5462 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5463 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5464 * [11:08] axi_lendian_C
5465 * [07:04] axi_lendian_Y
5466 * [3] reserved
5467 * [2] clk_forceon
5468 * [1] dw_disable:disable double write output
5469 * [0] cm_disable:disable compress output
5470 */
5471 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5472
5473 if (get_double_write_mode(pbi) & 0x10) {
5474 /* [23:22] dw_v1_ctrl
5475 *[21:20] dw_v0_ctrl
5476 *[19:18] dw_h1_ctrl
5477 *[17:16] dw_h0_ctrl
5478 */
5479 data32 = READ_VREG(HEVC_SAO_CTRL5);
5480 /*set them all 0 for H265_NV21 (no down-scale)*/
5481 data32 &= ~(0xff << 16);
5482 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5483 } else {
5484 data32 = READ_VREG(HEVC_SAO_CTRL5);
5485 data32 &= (~(0xff << 16));
5486 if (get_double_write_mode(pbi) == 2 ||
5487 get_double_write_mode(pbi) == 3)
5488 data32 |= (0xff<<16);
5489 else if (get_double_write_mode(pbi) == 4)
5490 data32 |= (0x33<<16);
5491 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5492 }
5493
5494 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5495 data32 &= (~0x30);
5496 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5497 data32 |= (pbi->mem_map_mode <<
5498 4);
5499 data32 &= (~0xF);
5500 data32 |= 0xf; /* valid only when double write only */
5501 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5502
5503 /* swap uv */
5504 if (pbi->is_used_v4l) {
5505 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5506 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5507 data32 |= (1 << 12); /* NV21 */
5508 else
5509 data32 &= ~(1 << 12); /* NV12 */
5510 }
5511
5512 /*
5513 * [3:0] little_endian
5514 * [5:4] address_format 00:linear 01:32x32 10:64x32
5515 * [7:6] reserved
5516 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5517 * [11:10] reserved
5518 * [12] CbCr_byte_swap
5519 * [31:13] reserved
5520 */
5521 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5522#endif
5523}
5524
5525static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5526{
5527 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5528 unsigned int data32;
5529
5530 if (debug && pbi->init_flag == 0)
5531 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5532 __func__,
5533 buf_spec->ipp.buf_start,
5534 buf_spec->start_adr,
5535 buf_spec->short_term_rps.buf_start,
5536 buf_spec->vps.buf_start,
5537 buf_spec->sps.buf_start,
5538 buf_spec->pps.buf_start,
5539 buf_spec->sao_up.buf_start,
5540 buf_spec->swap_buf.buf_start,
5541 buf_spec->swap_buf2.buf_start,
5542 buf_spec->scalelut.buf_start,
5543 buf_spec->dblk_para.buf_start,
5544 buf_spec->dblk_data.buf_start);
5545
5546 if (mask & HW_MASK_FRONT) {
5547 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5548 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5549
5550 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5551 buf_spec->short_term_rps.buf_start);
5552 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5553 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5554 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5555 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5556 buf_spec->swap_buf.buf_start);
5557 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5558 buf_spec->swap_buf2.buf_start);
5559 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5560
5561 }
5562
5563 if (mask & HW_MASK_BACK) {
5564#ifdef LOSLESS_COMPRESS_MODE
5565 int losless_comp_header_size =
5566 compute_losless_comp_header_size(pbi->init_pic_w,
5567 pbi->init_pic_h);
5568 int losless_comp_body_size =
5569 compute_losless_comp_body_size(pbi->init_pic_w,
5570 pbi->init_pic_h, buf_alloc_depth == 10);
5571#endif
5572 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5573 buf_spec->ipp.buf_start);
5574 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5575 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5576 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5577 /* cfg_addr_adp*/
5578 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5579 if (debug & VP9_DEBUG_BUFMGR_MORE)
5580 pr_info("Write HEVC_DBLK_CFGE\n");
5581 }
5582 /* cfg_p_addr */
5583 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5584 /* cfg_d_addr */
5585 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5586
5587 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5588 /*
5589 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5590 * data32 = data32 * 2;
5591 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5592 * data32 = data32 * 2;
5593 */
5594 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5595 }
5596#ifdef LOSLESS_COMPRESS_MODE
5597 if (pbi->mmu_enable) {
5598 /*bit[4] : paged_mem_mode*/
5599 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5600 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5601 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5602 } else {
5603 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5604 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5605 */
5606 /*bit[3] smem mdoe*/
5607 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5608 /*bit[3] smem mdoe*/
5609 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5610 (losless_comp_body_size >> 5));
5611 }
5612 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5613 (losless_comp_body_size >> 5));*/
5614 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5615 (0xff<<20) | (0xff<<10) | 0xff);*/
5616 /*8-bit mode */
5617 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5618 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5619 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5620 if (get_double_write_mode(pbi) & 0x10)
5621 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5622#else
5623 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5624#endif
5625
5626 if (pbi->mmu_enable) {
5627 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5628 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5629 + buf_spec->mmu_vbh.buf_size/2);
5630 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5631 /*data32 |= 0x1;*/
5632 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5633
5634 /* use HEVC_CM_HEADER_START_ADDR */
5635 data32 = READ_VREG(HEVC_SAO_CTRL5);
5636 data32 |= (1<<10);
5637 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5638 }
5639
5640 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5641
5642 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5643 /**/
5644 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5645 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5646 if (pbi->mmu_enable) {
5647 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5648 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5649 else
5650 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5651 }
5652 }
5653}
5654
5655
5656#ifdef VP9_LPF_LVL_UPDATE
5657/*
5658 * Defines, declarations, sub-functions for vp9 de-block loop
5659 filter Thr/Lvl table update
5660 * - struct segmentation is for loop filter only (removed something)
5661 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5662 be instantiated in C_Entry
5663 * - vp9_loop_filter_init run once before decoding start
5664 * - vp9_loop_filter_frame_init run before every frame decoding start
5665 * - set video format to VP9 is in vp9_loop_filter_init
5666 */
5667#define MAX_LOOP_FILTER 63
5668#define MAX_REF_LF_DELTAS 4
5669#define MAX_MODE_LF_DELTAS 2
5670/*#define INTRA_FRAME 0*/
5671/*#define LAST_FRAME 1*/
5672/*#define MAX_REF_FRAMES 4*/
5673#define SEGMENT_DELTADATA 0
5674#define SEGMENT_ABSDATA 1
5675#define MAX_SEGMENTS 8
5676/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5677/*no use for loop filter, if this struct for common use, pls add it back*/
5678/*#define PREDICTION_PROBS 3*/
5679/* no use for loop filter, if this struct for common use, pls add it back*/
5680
5681enum SEG_LVL_FEATURES {
5682 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5683 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5684 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5685 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5686 SEG_LVL_MAX = 4 /*Number of features supported*/
5687};
5688
5689struct segmentation {
5690 uint8_t enabled;
5691 uint8_t update_map;
5692 uint8_t update_data;
5693 uint8_t abs_delta;
5694 uint8_t temporal_update;
5695
5696 /*no use for loop filter, if this struct
5697 *for common use, pls add it back
5698 */
5699 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5700 /* no use for loop filter, if this struct
5701 * for common use, pls add it back
5702 */
5703 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5704
5705 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5706 unsigned int feature_mask[MAX_SEGMENTS];
5707};
5708
5709struct loop_filter_thresh {
5710 uint8_t mblim;
5711 uint8_t lim;
5712 uint8_t hev_thr;
5713};
5714
5715struct loop_filter_info_n {
5716 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5717 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5718};
5719
5720struct loopfilter {
5721 int filter_level;
5722
5723 int sharpness_level;
5724 int last_sharpness_level;
5725
5726 uint8_t mode_ref_delta_enabled;
5727 uint8_t mode_ref_delta_update;
5728
5729 /*0 = Intra, Last, GF, ARF*/
5730 signed char ref_deltas[MAX_REF_LF_DELTAS];
5731 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5732
5733 /*0 = ZERO_MV, MV*/
5734 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5735 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5736};
5737
5738static int vp9_clamp(int value, int low, int high)
5739{
5740 return value < low ? low : (value > high ? high : value);
5741}
5742
5743int segfeature_active(struct segmentation *seg,
5744 int segment_id,
5745 enum SEG_LVL_FEATURES feature_id) {
5746 return seg->enabled &&
5747 (seg->feature_mask[segment_id] & (1 << feature_id));
5748}
5749
5750int get_segdata(struct segmentation *seg, int segment_id,
5751 enum SEG_LVL_FEATURES feature_id) {
5752 return seg->feature_data[segment_id][feature_id];
5753}
5754
5755static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5756 int sharpness_lvl)
5757{
5758 int lvl;
5759 /*For each possible value for the loop filter fill out limits*/
5760 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5761 /*Set loop filter parameters that control sharpness.*/
5762 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5763 (sharpness_lvl > 4));
5764
5765 if (sharpness_lvl > 0) {
5766 if (block_inside_limit > (9 - sharpness_lvl))
5767 block_inside_limit = (9 - sharpness_lvl);
5768 }
5769
5770 if (block_inside_limit < 1)
5771 block_inside_limit = 1;
5772
5773 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5774 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5775 block_inside_limit);
5776 }
5777}
5778
5779/*instantiate this function once when decode is started*/
5780void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5781{
5782 struct loop_filter_info_n *lfi = pbi->lfi;
5783 struct loopfilter *lf = pbi->lf;
5784 struct segmentation *seg_4lf = pbi->seg_4lf;
5785 int i;
5786 unsigned int data32;
5787
5788 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5789 memset(lf, 0, sizeof(struct loopfilter));
5790 memset(seg_4lf, 0, sizeof(struct segmentation));
5791 lf->sharpness_level = 0; /*init to 0 */
5792 /*init limits for given sharpness*/
5793 vp9_update_sharpness(lfi, lf->sharpness_level);
5794 lf->last_sharpness_level = lf->sharpness_level;
5795 /*init hev threshold const vectors (actually no use)
5796 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5797 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5798 */
5799
5800 /*Write to register*/
5801 for (i = 0; i < 32; i++) {
5802 unsigned int thr;
5803
5804 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5805 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5806 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5807 (lfi->lfthr[i * 2].mblim & 0xff);
5808 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5809 }
5810
5811 /*video format is VP9*/
5812 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5813 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5814 (0x3 << 12) | // (dw fifo thres r or b)
5815 (0x3 << 10) | // (dw fifo thres not r/b)
5816 (0x3 << 8) | // 1st/2nd write both enable
5817 (0x1 << 0); // vp9 video format
5818 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5819 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5820 (0x1 << 0); /*vp9 video format*/
5821 } else
5822 data32 = 0x40400001;
5823
5824 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5825 if (debug & VP9_DEBUG_BUFMGR_MORE)
5826 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5827}
5828 /* perform this function per frame*/
5829void vp9_loop_filter_frame_init(struct segmentation *seg,
5830 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5831 int default_filt_lvl) {
5832 int i;
5833 int seg_id;
5834 /*n_shift is the multiplier for lf_deltas
5835 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5836 *2 when filter_lvl is between 32 and 63
5837 */
5838 const int scale = 1 << (default_filt_lvl >> 5);
5839
5840 /*update limits if sharpness has changed*/
5841 if (lf->last_sharpness_level != lf->sharpness_level) {
5842 vp9_update_sharpness(lfi, lf->sharpness_level);
5843 lf->last_sharpness_level = lf->sharpness_level;
5844
5845 /*Write to register*/
5846 for (i = 0; i < 32; i++) {
5847 unsigned int thr;
5848
5849 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5850 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5851 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5852 | (lfi->lfthr[i * 2].mblim & 0xff);
5853 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5854 }
5855 }
5856
5857 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5858 int lvl_seg = default_filt_lvl;
5859
5860 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5861 const int data = get_segdata(seg, seg_id,
5862 SEG_LVL_ALT_LF);
5863 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5864 data : default_filt_lvl + data,
5865 0, MAX_LOOP_FILTER);
5866#ifdef DBG_LF_PRINT
5867 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5868#endif
5869 }
5870
5871 if (!lf->mode_ref_delta_enabled) {
5872 /*we could get rid of this if we assume that deltas are set to
5873 *zero when not in use; encoder always uses deltas
5874 */
5875 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5876 } else {
5877 int ref, mode;
5878 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5879 * scale;
5880#ifdef DBG_LF_PRINT
5881 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5882 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5883#endif
5884 lfi->lvl[seg_id][INTRA_FRAME][0] =
5885 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5886
5887 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5888 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5889 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5890 /*MAX_MODE_LF_DELTAS = 2*/
5891 const int inter_lvl =
5892 lvl_seg + lf->ref_deltas[ref] * scale
5893 + lf->mode_deltas[mode] * scale;
5894#ifdef DBG_LF_PRINT
5895#endif
5896 lfi->lvl[seg_id][ref][mode] =
5897 vp9_clamp(inter_lvl, 0,
5898 MAX_LOOP_FILTER);
5899 }
5900 }
5901 }
5902 }
5903
5904#ifdef DBG_LF_PRINT
5905 /*print out thr/lvl table per frame*/
5906 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5907 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5908 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5909 lfi->lfthr[i].lim);
5910 }
5911 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5912 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5913 seg_id, lfi->lvl[seg_id][0][0],
5914 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5915 lfi->lvl[seg_id][3][0]);
5916 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5917 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5918 lfi->lvl[seg_id][3][1]);
5919 }
5920#endif
5921
5922 /*Write to register */
5923 for (i = 0; i < 16; i++) {
5924 unsigned int level;
5925
5926 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5927 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5928 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5929 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5930 if (!default_filt_lvl)
5931 level = 0;
5932 WRITE_VREG(HEVC_DBLK_CFGA, level);
5933 }
5934}
5935/* VP9_LPF_LVL_UPDATE */
5936#endif
5937
5938static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5939{
5940 unsigned int data32;
5941 int i;
5942 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5943 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5944 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5945 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5946 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5947 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5948 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5949 0x7C00
5950 };
5951#if 0
5952 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5953 /* Set MCR fetch priorities*/
5954 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5955 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5956 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5957 }
5958#endif
5959 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
5960 pr_info("%s\n", __func__);*/
5961 if (mask & HW_MASK_FRONT) {
5962 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5963#if 1
5964 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5965 data32 &= ~(7 << 29);
5966 data32 |= (3 << 29);
5967#endif
5968 data32 = data32 |
5969 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
5970 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
5971 (1 << 7) |/*dec_done_int_cpu_enable*/
5972 (1 << 4) |/*startcode_found_int_cpu_enable*/
5973 (0 << 3) |/*startcode_found_int_amrisc_enable*/
5974 (1 << 0) /*parser_int_enable*/
5975 ;
5976#ifdef SUPPORT_FB_DECODING
5977#ifndef FB_DECODING_TEST_SCHEDULE
5978 /*fed_fb_slice_done_int_cpu_enable*/
5979 if (pbi->used_stage_buf_num > 0)
5980 data32 |= (1 << 10);
5981#endif
5982#endif
5983 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
5984
5985 data32 = READ_VREG(HEVC_SHIFT_STATUS);
5986 data32 = data32 |
5987 (0 << 1) |/*emulation_check_off VP9
5988 do not have emulation*/
5989 (1 << 0)/*startcode_check_on*/
5990 ;
5991 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
5992 WRITE_VREG(HEVC_SHIFT_CONTROL,
5993 (0 << 14) | /*disable_start_code_protect*/
5994 (1 << 10) | /*length_zero_startcode_en for VP9*/
5995 (1 << 9) | /*length_valid_startcode_en for VP9*/
5996 (3 << 6) | /*sft_valid_wr_position*/
5997 (2 << 4) | /*emulate_code_length_sub_1*/
5998 (3 << 1) | /*start_code_length_sub_1
5999 VP9 use 0x00000001 as startcode (4 Bytes)*/
6000 (1 << 0) /*stream_shift_enable*/
6001 );
6002
6003 WRITE_VREG(HEVC_CABAC_CONTROL,
6004 (1 << 0)/*cabac_enable*/
6005 );
6006
6007 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6008 (1 << 0)/* hevc_parser_core_clk_en*/
6009 );
6010
6011
6012 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6013
6014 }
6015
6016 if (mask & HW_MASK_BACK) {
6017 /*Initial IQIT_SCALELUT memory
6018 -- just to avoid X in simulation*/
6019
6020 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6021 for (i = 0; i < 1024; i++)
6022 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6023 }
6024
6025 if (mask & HW_MASK_FRONT) {
6026 u32 decode_mode;
6027#ifdef ENABLE_SWAP_TEST
6028 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6029#else
6030 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6031#endif
6032#ifdef MULTI_INSTANCE_SUPPORT
6033 if (!pbi->m_ins_flag) {
6034 if (pbi->low_latency_flag)
6035 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6036 else
6037 decode_mode = DECODE_MODE_SINGLE;
6038 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6039 decode_mode = pbi->no_head ?
6040 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6041 DECODE_MODE_MULTI_FRAMEBASE;
6042 else
6043 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6044#ifdef SUPPORT_FB_DECODING
6045#ifndef FB_DECODING_TEST_SCHEDULE
6046 if (pbi->used_stage_buf_num > 0)
6047 decode_mode |= (0x01 << 24);
6048#endif
6049#endif
6050 WRITE_VREG(DECODE_MODE, decode_mode);
6051 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6052 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6053#else
6054 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6055 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6056 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6057#endif
6058 /*Send parser_cmd*/
6059 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6060 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6061 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6062 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6063 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6064 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6065
6066
6067 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6068 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6069 (1 << 5) | /*parser_sao_if_en*/
6070 (1 << 2) | /*parser_mpred_if_en*/
6071 (1 << 0) /*parser_scaler_if_en*/
6072 );
6073 }
6074
6075 if (mask & HW_MASK_BACK) {
6076 /*Changed to Start MPRED in microcode*/
6077 /*
6078 pr_info("[test.c] Start MPRED\n");
6079 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6080 (1<<31)
6081 );
6082 */
6083 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6084 (0 << 1) | /*enable ipp*/
6085 (1 << 0) /*software reset ipp and mpp*/
6086 );
6087 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6088 (1 << 1) | /*enable ipp*/
6089 (0 << 0) /*software reset ipp and mpp*/
6090 );
6091 if (get_double_write_mode(pbi) & 0x10) {
6092 /*Enable NV21 reference read mode for MC*/
6093 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6094 }
6095
6096 /*Initialize mcrcc and decomp perf counters*/
6097 if (mcrcc_cache_alg_flag &&
6098 pbi->init_flag == 0) {
6099 mcrcc_perfcount_reset();
6100 decomp_perfcount_reset();
6101 }
6102 }
6103 return;
6104}
6105
6106
6107#ifdef CONFIG_HEVC_CLK_FORCED_ON
6108static void config_vp9_clk_forced_on(void)
6109{
6110 unsigned int rdata32;
6111 /*IQIT*/
6112 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6113 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6114
6115 /* DBLK*/
6116 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6117 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6118
6119 /* SAO*/
6120 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6121 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6122
6123 /*MPRED*/
6124 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6125 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6126
6127 /* PARSER*/
6128 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6129 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6130 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6131 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6132 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6133 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6134 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6135 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6136 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6137 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6138 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6139 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6140 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6141
6142 /*IPP*/
6143 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6144 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6145
6146 /* MCRCC*/
6147 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6148 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6149}
6150#endif
6151
6152
6153#ifdef MCRCC_ENABLE
6154static void dump_hit_rate(struct VP9Decoder_s *pbi)
6155{
6156 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6157 mcrcc_get_hitrate(pbi->m_ins_flag);
6158 decomp_get_hitrate();
6159 decomp_get_comprate();
6160 }
6161}
6162
6163static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6164{
6165 unsigned int rdata32;
6166 unsigned short is_inter;
6167 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6168 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6169 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6170 (!pbi->common.intra_only)) ? 1 : 0;
6171 if (!is_inter) { /* I-PIC*/
6172 /*remove reset -- disables clock*/
6173 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6174 return;
6175 }
6176
6177 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6178 mcrcc_get_hitrate(pbi->m_ins_flag);
6179 decomp_get_hitrate();
6180 decomp_get_comprate();
6181 }
6182
6183 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6184 (0 << 8) | (1 << 1) | 0);
6185 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6186 rdata32 = rdata32 & 0xffff;
6187 rdata32 = rdata32 | (rdata32 << 16);
6188 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6189 /*Programme canvas1 */
6190 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6191 rdata32 = rdata32 & 0xffff;
6192 rdata32 = rdata32 | (rdata32 << 16);
6193 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6194 /*enable mcrcc progressive-mode*/
6195 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6196}
6197
6198static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6199{
6200 u32 curr_picnum = -1;
6201 u32 lastref_picnum = -1;
6202 u32 goldenref_picnum = -1;
6203 u32 altref_picnum = -1;
6204
6205 u32 lastref_delta_picnum;
6206 u32 goldenref_delta_picnum;
6207 u32 altref_delta_picnum;
6208
6209 u32 rdata32;
6210
6211 u32 lastcanvas;
6212 u32 goldencanvas;
6213 u32 altrefcanvas;
6214
6215 u16 is_inter;
6216 u16 lastref_inref;
6217 u16 goldenref_inref;
6218 u16 altref_inref;
6219
6220 u32 refcanvas_array[3], utmp;
6221 int deltapicnum_array[3], tmp;
6222
6223 struct VP9_Common_s *cm = &pbi->common;
6224 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6225 = &cm->cur_frame->buf;
6226 curr_picnum = cur_pic_config->decode_idx;
6227 if (cm->frame_refs[0].buf)
6228 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6229 if (cm->frame_refs[1].buf)
6230 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6231 if (cm->frame_refs[2].buf)
6232 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6233
6234 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6235 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6236 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6237 (goldenref_picnum - curr_picnum) :
6238 (curr_picnum - goldenref_picnum);
6239 altref_delta_picnum =
6240 (altref_picnum >= curr_picnum) ?
6241 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6242
6243 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6244 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6245 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6246
6247 if (debug & VP9_DEBUG_CACHE)
6248 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6249 __func__, lastref_inref, goldenref_inref, altref_inref);
6250
6251 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6252
6253 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6254 && (!pbi->common.intra_only)) ? 1 : 0;
6255
6256 if (!is_inter) { /* I-PIC */
6257 /* remove reset -- disables clock */
6258 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6259 return;
6260 }
6261
6262 if (!pbi->m_ins_flag)
6263 dump_hit_rate(pbi);
6264
6265 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6266 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6267 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6268 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6269
6270 if (debug & VP9_DEBUG_CACHE)
6271 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6272 lastcanvas, goldencanvas, altrefcanvas);
6273
6274 altref_inref = ((altref_inref == 1) &&
6275 (altrefcanvas != (goldenref_inref
6276 ? goldencanvas : 0xffffffff)) &&
6277 (altrefcanvas != (lastref_inref ?
6278 lastcanvas : 0xffffffff))) ? 1 : 0;
6279 goldenref_inref = ((goldenref_inref == 1) &&
6280 (goldencanvas != (lastref_inref ?
6281 lastcanvas : 0xffffffff))) ? 1 : 0;
6282 if (debug & VP9_DEBUG_CACHE)
6283 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6284 lastref_inref, goldenref_inref, altref_inref);
6285
6286 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6287 goldenref_delta_picnum = goldenref_inref ?
6288 goldenref_delta_picnum : 0x7fffffff;
6289 lastref_delta_picnum = lastref_inref ?
6290 lastref_delta_picnum : 0x7fffffff;
6291 if (debug & VP9_DEBUG_CACHE)
6292 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6293 lastref_delta_picnum, goldenref_delta_picnum,
6294 altref_delta_picnum);
6295 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6296
6297 refcanvas_array[0] = lastcanvas;
6298 refcanvas_array[1] = goldencanvas;
6299 refcanvas_array[2] = altrefcanvas;
6300
6301 deltapicnum_array[0] = lastref_delta_picnum;
6302 deltapicnum_array[1] = goldenref_delta_picnum;
6303 deltapicnum_array[2] = altref_delta_picnum;
6304
6305 /* sort0 : 2-to-1 */
6306 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6307 utmp = refcanvas_array[2];
6308 refcanvas_array[2] = refcanvas_array[1];
6309 refcanvas_array[1] = utmp;
6310 tmp = deltapicnum_array[2];
6311 deltapicnum_array[2] = deltapicnum_array[1];
6312 deltapicnum_array[1] = tmp;
6313 }
6314 /* sort1 : 1-to-0 */
6315 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6316 utmp = refcanvas_array[1];
6317 refcanvas_array[1] = refcanvas_array[0];
6318 refcanvas_array[0] = utmp;
6319 tmp = deltapicnum_array[1];
6320 deltapicnum_array[1] = deltapicnum_array[0];
6321 deltapicnum_array[0] = tmp;
6322 }
6323 /* sort2 : 2-to-1 */
6324 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6325 utmp = refcanvas_array[2]; refcanvas_array[2] =
6326 refcanvas_array[1]; refcanvas_array[1] = utmp;
6327 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6328 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6329 }
6330 if (mcrcc_cache_alg_flag ==
6331 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6332 /* lowest delta_picnum */
6333 rdata32 = refcanvas_array[0];
6334 rdata32 = rdata32 & 0xffff;
6335 rdata32 = rdata32 | (rdata32 << 16);
6336 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6337
6338 /* 2nd-lowest delta_picnum */
6339 rdata32 = refcanvas_array[1];
6340 rdata32 = rdata32 & 0xffff;
6341 rdata32 = rdata32 | (rdata32 << 16);
6342 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6343 } else {
6344 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6345 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6346 (0 << 8) | (1<<1) | 0);
6347 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6348 rdata32 = rdata32 & 0xffff;
6349 rdata32 = rdata32 | (rdata32 << 16);
6350 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6351
6352 /* Programme canvas1 */
6353 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6354 rdata32 = rdata32 & 0xffff;
6355 rdata32 = rdata32 | (rdata32 << 16);
6356 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6357 }
6358
6359 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6360 return;
6361}
6362
6363#endif
6364
6365
6366static void free_lf_buf(struct VP9Decoder_s *pbi)
6367{
6368 if (pbi->lfi)
6369 vfree(pbi->lfi);
6370 if (pbi->lf)
6371 vfree(pbi->lf);
6372 if (pbi->seg_4lf)
6373 vfree(pbi->seg_4lf);
6374 pbi->lfi = NULL;
6375 pbi->lf = NULL;
6376 pbi->seg_4lf = NULL;
6377}
6378
6379static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6380{
6381 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6382 pbi->lf = vmalloc(sizeof(struct loopfilter));
6383 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6384 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6385 free_lf_buf(pbi);
6386 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6387 return -1;
6388 }
6389 return 0;
6390}
6391
6392static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6393{
6394 pbi->rpm_ptr = NULL;
6395 pbi->lmem_ptr = NULL;
6396 if (pbi->rpm_addr) {
6397 dma_free_coherent(amports_get_dma_device(),
6398 RPM_BUF_SIZE,
6399 pbi->rpm_addr,
6400 pbi->rpm_phy_addr);
6401 pbi->rpm_addr = NULL;
6402 }
6403 if (pbi->lmem_addr) {
6404 if (pbi->lmem_phy_addr)
6405 dma_free_coherent(amports_get_dma_device(),
6406 LMEM_BUF_SIZE, pbi->lmem_addr,
6407 pbi->lmem_phy_addr);
6408 pbi->lmem_addr = NULL;
6409 }
6410 if (pbi->prob_buffer_addr) {
6411 if (pbi->prob_buffer_phy_addr)
6412 dma_free_coherent(amports_get_dma_device(),
6413 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6414 pbi->prob_buffer_phy_addr);
6415
6416 pbi->prob_buffer_addr = NULL;
6417 }
6418 if (pbi->count_buffer_addr) {
6419 if (pbi->count_buffer_phy_addr)
6420 dma_free_coherent(amports_get_dma_device(),
6421 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6422 pbi->count_buffer_phy_addr);
6423
6424 pbi->count_buffer_addr = NULL;
6425 }
6426 if (pbi->mmu_enable) {
6427 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6428 if (pbi->frame_mmu_map_addr) {
6429 if (pbi->frame_mmu_map_phy_addr)
6430 dma_free_coherent(amports_get_dma_device(),
6431 mmu_map_size,
6432 pbi->frame_mmu_map_addr,
6433 pbi->frame_mmu_map_phy_addr);
6434 pbi->frame_mmu_map_addr = NULL;
6435 }
6436 }
6437#ifdef SUPPORT_FB_DECODING
6438 if (pbi->stage_mmu_map_addr) {
6439 if (pbi->stage_mmu_map_phy_addr)
6440 dma_free_coherent(amports_get_dma_device(),
6441 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6442 pbi->stage_mmu_map_addr,
6443 pbi->stage_mmu_map_phy_addr);
6444 pbi->stage_mmu_map_addr = NULL;
6445 }
6446
6447 uninit_stage_buf(pbi);
6448#endif
6449
6450#ifdef VP9_LPF_LVL_UPDATE
6451 free_lf_buf(pbi);
6452#endif
6453 if (pbi->gvs)
6454 vfree(pbi->gvs);
6455 pbi->gvs = NULL;
6456}
6457
6458static int vp9_local_init(struct VP9Decoder_s *pbi)
6459{
6460 int ret = -1;
6461 /*int losless_comp_header_size, losless_comp_body_size;*/
6462
6463 struct BuffInfo_s *cur_buf_info = NULL;
6464
6465 memset(&pbi->param, 0, sizeof(union param_u));
6466 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6467#ifdef MULTI_INSTANCE_SUPPORT
6468 cur_buf_info = &pbi->work_space_buf_store;
6469
6470 if (vdec_is_support_4k()) {
6471 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6472 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6473 sizeof(struct BuffInfo_s));
6474 } else
6475 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6476 sizeof(struct BuffInfo_s));
6477 } else
6478 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6479 sizeof(struct BuffInfo_s));
6480
6481 cur_buf_info->start_adr = pbi->buf_start;
6482 if (!pbi->mmu_enable)
6483 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6484
6485#else
6486/*! MULTI_INSTANCE_SUPPORT*/
6487 if (vdec_is_support_4k()) {
6488 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6489 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6490 else
6491 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6492 } else
6493 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6494
6495#endif
6496
6497 init_buff_spec(pbi, cur_buf_info);
6498 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6499
6500 if (!vdec_is_support_4k()
6501 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6502 buf_alloc_width = 1920;
6503 buf_alloc_height = 1088;
6504 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6505 pbi->max_pic_w = 1920;
6506 pbi->max_pic_h = 1088;
6507 }
6508 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6509 buf_alloc_width = 8192;
6510 buf_alloc_height = 4608;
6511 }
6512 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6513 (buf_alloc_width ? buf_alloc_width :
6514 (pbi->vvp9_amstream_dec_info.width ?
6515 pbi->vvp9_amstream_dec_info.width :
6516 pbi->work_space_buf->max_width));
6517 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6518 (buf_alloc_height ? buf_alloc_height :
6519 (pbi->vvp9_amstream_dec_info.height ?
6520 pbi->vvp9_amstream_dec_info.height :
6521 pbi->work_space_buf->max_height));
6522
6523 /* video is not support unaligned with 64 in tl1
6524 ** vdec canvas mode will be linear when dump yuv is set
6525 */
6526 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6527 (pbi->double_write_mode != 0) &&
6528 (((pbi->max_pic_w % 64) != 0) ||
6529 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6530 if (hw_to_vdec(pbi)->canvas_mode !=
6531 CANVAS_BLKMODE_LINEAR)
6532 pbi->mem_map_mode = 2;
6533 else {
6534 pbi->mem_map_mode = 0;
6535 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6536 }
6537 }
6538
6539#ifndef MV_USE_FIXED_BUF
6540 if (init_mv_buf_list(pbi) < 0) {
6541 pr_err("%s: init_mv_buf_list fail\n", __func__);
6542 return -1;
6543 }
6544#endif
6545 if (pbi->save_buffer_mode)
6546 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6547 else {
6548 if (pbi->is_used_v4l)
6549 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6550 else
6551 pbi->used_buf_num = max_buf_num;
6552 }
6553
6554 if (pbi->used_buf_num > MAX_BUF_NUM)
6555 pbi->used_buf_num = MAX_BUF_NUM;
6556 if (pbi->used_buf_num > FRAME_BUFFERS)
6557 pbi->used_buf_num = FRAME_BUFFERS;
6558
6559 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6560 & 0x40) >> 6;
6561
6562 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6563 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6564 RPM_BUF_SIZE,
6565 &pbi->rpm_phy_addr, GFP_KERNEL);
6566 if (pbi->rpm_addr == NULL) {
6567 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6568 return -1;
6569 }
6570
6571 pbi->rpm_ptr = pbi->rpm_addr;
6572 }
6573
6574 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6575 LMEM_BUF_SIZE,
6576 &pbi->lmem_phy_addr, GFP_KERNEL);
6577 if (pbi->lmem_addr == NULL) {
6578 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6579 return -1;
6580 }
6581 pbi->lmem_ptr = pbi->lmem_addr;
6582
6583 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6584 PROB_BUF_SIZE,
6585 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6586 if (pbi->prob_buffer_addr == NULL) {
6587 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6588 return -1;
6589 }
6590 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6591 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6592 COUNT_BUF_SIZE,
6593 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6594 if (pbi->count_buffer_addr == NULL) {
6595 pr_err("%s: failed to alloc count_buffer\n", __func__);
6596 return -1;
6597 }
6598 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6599
6600 if (pbi->mmu_enable) {
6601 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6602 pbi->frame_mmu_map_addr =
6603 dma_alloc_coherent(amports_get_dma_device(),
6604 mmu_map_size,
6605 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6606 if (pbi->frame_mmu_map_addr == NULL) {
6607 pr_err("%s: failed to alloc count_buffer\n", __func__);
6608 return -1;
6609 }
6610 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6611 }
6612#ifdef SUPPORT_FB_DECODING
6613 if (pbi->m_ins_flag && stage_buf_num > 0) {
6614 pbi->stage_mmu_map_addr =
6615 dma_alloc_coherent(amports_get_dma_device(),
6616 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6617 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6618 if (pbi->stage_mmu_map_addr == NULL) {
6619 pr_err("%s: failed to alloc count_buffer\n", __func__);
6620 return -1;
6621 }
6622 memset(pbi->stage_mmu_map_addr,
6623 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6624
6625 init_stage_buf(pbi);
6626 }
6627#endif
6628
6629 ret = 0;
6630 return ret;
6631}
6632
6633/********************************************
6634 * Mailbox command
6635 ********************************************/
6636#define CMD_FINISHED 0
6637#define CMD_ALLOC_VIEW 1
6638#define CMD_FRAME_DISPLAY 3
6639#define CMD_DEBUG 10
6640
6641
6642#define DECODE_BUFFER_NUM_MAX 32
6643#define DISPLAY_BUFFER_NUM 6
6644
6645#define video_domain_addr(adr) (adr&0x7fffffff)
6646#define DECODER_WORK_SPACE_SIZE 0x800000
6647
6648#define spec2canvas(x) \
6649 (((x)->uv_canvas_index << 16) | \
6650 ((x)->uv_canvas_index << 8) | \
6651 ((x)->y_canvas_index << 0))
6652
6653
6654static void set_canvas(struct VP9Decoder_s *pbi,
6655 struct PIC_BUFFER_CONFIG_s *pic_config)
6656{
6657 struct vdec_s *vdec = hw_to_vdec(pbi);
6658 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6659 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6660 int blkmode = pbi->mem_map_mode;
6661 /*CANVAS_BLKMODE_64X32*/
6662 if (pic_config->double_write_mode) {
6663 canvas_w = pic_config->y_crop_width /
6664 get_double_write_ratio(pbi,
6665 pic_config->double_write_mode);
6666 canvas_h = pic_config->y_crop_height /
6667 get_double_write_ratio(pbi,
6668 pic_config->double_write_mode);
6669
6670 if (pbi->mem_map_mode == 0)
6671 canvas_w = ALIGN(canvas_w, 32);
6672 else
6673 canvas_w = ALIGN(canvas_w, 64);
6674 canvas_h = ALIGN(canvas_h, 32);
6675
6676 if (vdec->parallel_dec == 1) {
6677 if (pic_config->y_canvas_index == -1)
6678 pic_config->y_canvas_index =
6679 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6680 if (pic_config->uv_canvas_index == -1)
6681 pic_config->uv_canvas_index =
6682 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6683 } else {
6684 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6685 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6686 }
6687
6688 canvas_config_ex(pic_config->y_canvas_index,
6689 pic_config->dw_y_adr, canvas_w, canvas_h,
6690 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6691 canvas_config_ex(pic_config->uv_canvas_index,
6692 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6693 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6694
6695#ifdef MULTI_INSTANCE_SUPPORT
6696 pic_config->canvas_config[0].phy_addr =
6697 pic_config->dw_y_adr;
6698 pic_config->canvas_config[0].width =
6699 canvas_w;
6700 pic_config->canvas_config[0].height =
6701 canvas_h;
6702 pic_config->canvas_config[0].block_mode =
6703 blkmode;
6704 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6705
6706 pic_config->canvas_config[1].phy_addr =
6707 pic_config->dw_u_v_adr;
6708 pic_config->canvas_config[1].width =
6709 canvas_w;
6710 pic_config->canvas_config[1].height =
6711 canvas_h;
6712 pic_config->canvas_config[1].block_mode =
6713 blkmode;
6714 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6715#endif
6716 }
6717}
6718
6719
6720static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6721{
6722 unsigned int ar;
6723 vf->duration = pbi->frame_dur;
6724 vf->duration_pulldown = 0;
6725 vf->flag = 0;
6726 vf->prop.master_display_colour = pbi->vf_dp;
6727 vf->signal_type = pbi->video_signal_type;
6728 if (vf->compWidth && vf->compHeight)
6729 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6730 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6731 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6732
6733 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6734 struct aml_vdec_hdr_infos hdr;
6735 struct aml_vcodec_ctx *ctx =
6736 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6737
6738 memset(&hdr, 0, sizeof(hdr));
6739 hdr.signal_type = vf->signal_type;
6740 hdr.color_parms = pbi->vf_dp;
6741 vdec_v4l_set_hdr_infos(ctx, &hdr);
6742 }
6743}
6744
6745static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6746{
6747 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6748
6749 states->vf_pool_size = VF_POOL_SIZE;
6750 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6751 states->buf_avail_num = kfifo_len(&pbi->display_q);
6752
6753 if (step == 2)
6754 states->buf_avail_num = 0;
6755 return 0;
6756}
6757
6758static struct vframe_s *vvp9_vf_peek(void *op_arg)
6759{
6760 struct vframe_s *vf[2] = {0, 0};
6761 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6762
6763 if (step == 2)
6764 return NULL;
6765
6766 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6767 if (vf[1]) {
6768 vf[0]->next_vf_pts_valid = true;
6769 vf[0]->next_vf_pts = vf[1]->pts;
6770 } else
6771 vf[0]->next_vf_pts_valid = false;
6772 return vf[0];
6773 }
6774
6775 return NULL;
6776}
6777
6778static struct vframe_s *vvp9_vf_get(void *op_arg)
6779{
6780 struct vframe_s *vf;
6781 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6782
6783 if (step == 2)
6784 return NULL;
6785 else if (step == 1)
6786 step = 2;
6787
6788 if (kfifo_get(&pbi->display_q, &vf)) {
6789 struct vframe_s *next_vf;
6790 uint8_t index = vf->index & 0xff;
6791 if (index < pbi->used_buf_num ||
6792 (vf->type & VIDTYPE_V4L_EOS)) {
6793 pbi->vf_get_count++;
6794 if (debug & VP9_DEBUG_BUFMGR)
6795 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6796 __func__, vf->type,
6797 vf->width, vf->height,
6798 vf->pts,
6799 vf->pts_us64);
6800
6801 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6802 vf->next_vf_pts_valid = true;
6803 vf->next_vf_pts = next_vf->pts;
6804 } else
6805 vf->next_vf_pts_valid = false;
6806
6807 return vf;
6808 }
6809 }
6810 return NULL;
6811}
6812
6813static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6814{
6815 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6816 uint8_t index = vf->index & 0xff;
6817
6818 if (vf == (&pbi->vframe_dummy))
6819 return;
6820
6821 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6822 pbi->vf_put_count++;
6823 if (index < pbi->used_buf_num) {
6824 struct VP9_Common_s *cm = &pbi->common;
6825 struct BufferPool_s *pool = cm->buffer_pool;
6826 unsigned long flags;
6827
6828 lock_buffer_pool(pool, flags);
6829 if (pool->frame_bufs[index].buf.vf_ref > 0)
6830 pool->frame_bufs[index].buf.vf_ref--;
6831
6832 if (pbi->is_used_v4l)
6833 pool->frame_bufs[index].buf.vframe_bound = true;
6834
6835 if (pbi->wait_buf)
6836 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6837 0x1);
6838 pbi->last_put_idx = index;
6839 pbi->new_frame_displayed++;
6840 unlock_buffer_pool(pool, flags);
6841#ifdef SUPPORT_FB_DECODING
6842 if (pbi->used_stage_buf_num > 0 &&
6843 pbi->back_not_run_ready)
6844 trigger_schedule(pbi);
6845#endif
6846 }
6847
6848}
6849
6850static int vvp9_event_cb(int type, void *data, void *private_data)
6851{
6852 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6853#if 0
6854 unsigned long flags;
6855
6856 amhevc_stop();
6857#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6858 vf_light_unreg_provider(&vvp9_vf_prov);
6859#endif
6860 spin_lock_irqsave(&pbi->lock, flags);
6861 vvp9_local_init();
6862 vvp9_prot_init();
6863 spin_unlock_irqrestore(&pbi->lock, flags);
6864#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6865 vf_reg_provider(&vvp9_vf_prov);
6866#endif
6867 amhevc_start();
6868#endif
6869 }
6870
6871 return 0;
6872}
6873
6874void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6875{
6876 struct VP9_Common_s *cm = &pbi->common;
6877
6878 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6879
6880 if (debug & VP9_DEBUG_BUFMGR_MORE)
6881 pr_info("%s index = %d new vf_ref = %d\r\n",
6882 __func__, index,
6883 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6884}
6885
6886static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6887{
6888 u32 old_duration, pts_duration = 0;
6889 u32 pts = vf->pts;
6890
6891 if (pbi->get_frame_dur == true)
6892 return true;
6893
6894 pbi->frame_cnt_window++;
6895 if (!(pbi->vp9_first_pts_ready == 1)) {
6896 if (valid) {
6897 pbi->pts1 = pts;
6898 pbi->frame_cnt_window = 0;
6899 pbi->duration_from_pts_done = 0;
6900 pbi->vp9_first_pts_ready = 1;
6901 } else {
6902 return false;
6903 }
6904 } else {
6905 if (pts < pbi->pts1) {
6906 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6907 pbi->pts1 = pts;
6908 pbi->frame_cnt_window = 0;
6909 }
6910 }
6911
6912 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6913 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6914 old_duration = pbi->frame_dur;
6915 pbi->pts2 = pts;
6916 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6917 (pbi->frame_cnt_window * 15));
6918
6919 if (close_to(pts_duration, old_duration, 2000)) {
6920 pbi->frame_dur = pts_duration;
6921 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6922 pr_info("use calc duration %d\n", pts_duration);
6923 }
6924
6925 if (pbi->duration_from_pts_done == 0) {
6926 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6927 pbi->duration_from_pts_done = 1;
6928 } else {
6929 if (!close_to(pts_duration,
6930 old_duration, 1000) &&
6931 !close_to(pts_duration,
6932 pbi->frame_dur, 1000) &&
6933 close_to(pts_duration,
6934 pbi->last_duration, 200)) {
6935 /* frame_dur must
6936 * wrong,recover it.
6937 */
6938 pbi->frame_dur = pts_duration;
6939 }
6940 pbi->pts1 = pbi->pts2;
6941 pbi->frame_cnt_window = 0;
6942 pbi->duration_from_pts_done = 0;
6943 }
6944 }
6945 pbi->last_duration = pts_duration;
6946 }
6947 }
6948 return true;
6949}
6950
6951static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6952 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6953{
6954 if (pic->index < 0) {
6955 vf->mem_handle = NULL;
6956 vf->mem_head_handle = NULL;
6957 } else if (vf->type & VIDTYPE_SCATTER) {
6958 vf->mem_handle =
6959 decoder_mmu_box_get_mem_handle(
6960 pbi->mmu_box, pic->index);
6961 vf->mem_head_handle =
6962 decoder_bmmu_box_get_mem_handle(
6963 pbi->bmmu_box,
6964 HEADER_BUFFER_IDX(pic->BUF_index));
6965 } else {
6966 vf->mem_handle =
6967 decoder_bmmu_box_get_mem_handle(
6968 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
6969 vf->mem_head_handle = NULL;
6970 /*vf->mem_head_handle =
6971 *decoder_bmmu_box_get_mem_handle(
6972 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
6973 */
6974 }
6975}
6976
6977static int prepare_display_buf(struct VP9Decoder_s *pbi,
6978 struct PIC_BUFFER_CONFIG_s *pic_config)
6979{
6980 struct vframe_s *vf = NULL;
6981 int stream_offset = pic_config->stream_offset;
6982 unsigned short slice_type = pic_config->slice_type;
6983 u32 pts_valid = 0, pts_us64_valid = 0;
6984 u32 pts_save;
6985 u64 pts_us64_save;
6986 u32 frame_size;
6987
6988 if (debug & VP9_DEBUG_BUFMGR)
6989 pr_info("%s index = %d\r\n", __func__, pic_config->index);
6990 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
6991 pr_info("fatal error, no available buffer slot.");
6992 return -1;
6993 }
6994
6995 if (pic_config->double_write_mode)
6996 set_canvas(pbi, pic_config);
6997
6998 display_frame_count[pbi->index]++;
6999 if (vf) {
7000 if (pbi->is_used_v4l) {
7001 vf->v4l_mem_handle
7002 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7003 if (pbi->mmu_enable) {
7004 vf->mm_box.bmmu_box = pbi->bmmu_box;
7005 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7006 vf->mm_box.mmu_box = pbi->mmu_box;
7007 vf->mm_box.mmu_idx = pic_config->index;
7008 }
7009 }
7010
7011#ifdef MULTI_INSTANCE_SUPPORT
7012 if (vdec_frame_based(hw_to_vdec(pbi))) {
7013 vf->pts = pic_config->pts;
7014 vf->pts_us64 = pic_config->pts64;
7015 vf->timestamp = pic_config->timestamp;
7016 if (vf->pts != 0 || vf->pts_us64 != 0) {
7017 pts_valid = 1;
7018 pts_us64_valid = 1;
7019 } else {
7020 pts_valid = 0;
7021 pts_us64_valid = 0;
7022 }
7023 } else
7024#endif
7025 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7026 * stream_offset, &vf->pts, 0) != 0) {
7027 */
7028 if (pts_lookup_offset_us64
7029 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7030 &frame_size, 0,
7031 &vf->pts_us64) != 0) {
7032#ifdef DEBUG_PTS
7033 pbi->pts_missed++;
7034#endif
7035 vf->pts = 0;
7036 vf->pts_us64 = 0;
7037 pts_valid = 0;
7038 pts_us64_valid = 0;
7039 } else {
7040#ifdef DEBUG_PTS
7041 pbi->pts_hit++;
7042#endif
7043 pts_valid = 1;
7044 pts_us64_valid = 1;
7045 }
7046
7047 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7048
7049 pts_save = vf->pts;
7050 pts_us64_save = vf->pts_us64;
7051 if (pbi->pts_unstable) {
7052 frame_duration_adapt(pbi, vf, pts_valid);
7053 if (pbi->duration_from_pts_done) {
7054 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7055 } else {
7056 if (pts_valid || pts_us64_valid)
7057 pbi->pts_mode = PTS_NORMAL;
7058 }
7059 }
7060
7061 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7062 && pbi->get_frame_dur) {
7063 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7064
7065 if (pts_diff < 0) {
7066 pbi->pts_mode_switching_count++;
7067 pbi->pts_mode_recovery_count = 0;
7068
7069 if (pbi->pts_mode_switching_count >=
7070 PTS_MODE_SWITCHING_THRESHOLD) {
7071 pbi->pts_mode =
7072 PTS_NONE_REF_USE_DURATION;
7073 pr_info
7074 ("HEVC: switch to n_d mode.\n");
7075 }
7076
7077 } else {
7078 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7079
7080 pbi->pts_mode_recovery_count++;
7081 if (pbi->pts_mode_recovery_count > p) {
7082 pbi->pts_mode_switching_count = 0;
7083 pbi->pts_mode_recovery_count = 0;
7084 }
7085 }
7086 }
7087
7088 if (vf->pts != 0)
7089 pbi->last_lookup_pts = vf->pts;
7090
7091 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7092 && (slice_type != KEY_FRAME))
7093 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7094 pbi->last_pts = vf->pts;
7095
7096 if (vf->pts_us64 != 0)
7097 pbi->last_lookup_pts_us64 = vf->pts_us64;
7098
7099 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7100 && (slice_type != KEY_FRAME)) {
7101 vf->pts_us64 =
7102 pbi->last_pts_us64 +
7103 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7104 }
7105 pbi->last_pts_us64 = vf->pts_us64;
7106 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7107 pr_info
7108 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7109 pbi->pts_mode, pbi->frame_dur, vf->pts,
7110 vf->pts_us64, pts_save, pts_us64_save);
7111 }
7112
7113 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7114 vf->disp_pts = vf->pts;
7115 vf->disp_pts_us64 = vf->pts_us64;
7116 vf->pts = pts_save;
7117 vf->pts_us64 = pts_us64_save;
7118 } else {
7119 vf->disp_pts = 0;
7120 vf->disp_pts_us64 = 0;
7121 }
7122
7123 vf->index = 0xff00 | pic_config->index;
7124
7125 if (pic_config->double_write_mode & 0x10) {
7126 /* double write only */
7127 vf->compBodyAddr = 0;
7128 vf->compHeadAddr = 0;
7129 } else {
7130 if (pbi->mmu_enable) {
7131 vf->compBodyAddr = 0;
7132 vf->compHeadAddr = pic_config->header_adr;
7133 } else {
7134 /*vf->compBodyAddr = pic_config->mc_y_adr;
7135 *vf->compHeadAddr = pic_config->mc_y_adr +
7136 *pic_config->comp_body_size; */
7137 /*head adr*/
7138 }
7139 vf->canvas0Addr = vf->canvas1Addr = 0;
7140 }
7141 if (pic_config->double_write_mode) {
7142 vf->type = VIDTYPE_PROGRESSIVE |
7143 VIDTYPE_VIU_FIELD;
7144 vf->type |= VIDTYPE_VIU_NV21;
7145 if ((pic_config->double_write_mode == 3) &&
7146 (!IS_8K_SIZE(pic_config->y_crop_width,
7147 pic_config->y_crop_height))) {
7148 vf->type |= VIDTYPE_COMPRESS;
7149 if (pbi->mmu_enable)
7150 vf->type |= VIDTYPE_SCATTER;
7151 }
7152#ifdef MULTI_INSTANCE_SUPPORT
7153 if (pbi->m_ins_flag) {
7154 vf->canvas0Addr = vf->canvas1Addr = -1;
7155 vf->plane_num = 2;
7156 vf->canvas0_config[0] =
7157 pic_config->canvas_config[0];
7158 vf->canvas0_config[1] =
7159 pic_config->canvas_config[1];
7160 vf->canvas1_config[0] =
7161 pic_config->canvas_config[0];
7162 vf->canvas1_config[1] =
7163 pic_config->canvas_config[1];
7164
7165 } else
7166#endif
7167 vf->canvas0Addr = vf->canvas1Addr =
7168 spec2canvas(pic_config);
7169 } else {
7170 vf->canvas0Addr = vf->canvas1Addr = 0;
7171 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7172 if (pbi->mmu_enable)
7173 vf->type |= VIDTYPE_SCATTER;
7174 }
7175
7176 switch (pic_config->bit_depth) {
7177 case VPX_BITS_8:
7178 vf->bitdepth = BITDEPTH_Y8 |
7179 BITDEPTH_U8 | BITDEPTH_V8;
7180 break;
7181 case VPX_BITS_10:
7182 case VPX_BITS_12:
7183 vf->bitdepth = BITDEPTH_Y10 |
7184 BITDEPTH_U10 | BITDEPTH_V10;
7185 break;
7186 default:
7187 vf->bitdepth = BITDEPTH_Y10 |
7188 BITDEPTH_U10 | BITDEPTH_V10;
7189 break;
7190 }
7191 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7192 vf->bitdepth =
7193 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7194 if (pic_config->bit_depth == VPX_BITS_8)
7195 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7196
7197 /* if((vf->width!=pic_config->width)|
7198 * (vf->height!=pic_config->height))
7199 */
7200 /* pr_info("aaa: %d/%d, %d/%d\n",
7201 vf->width,vf->height, pic_config->width,
7202 pic_config->height); */
7203 vf->width = pic_config->y_crop_width /
7204 get_double_write_ratio(pbi,
7205 pic_config->double_write_mode);
7206 vf->height = pic_config->y_crop_height /
7207 get_double_write_ratio(pbi,
7208 pic_config->double_write_mode);
7209 if (force_w_h != 0) {
7210 vf->width = (force_w_h >> 16) & 0xffff;
7211 vf->height = force_w_h & 0xffff;
7212 }
7213 vf->compWidth = pic_config->y_crop_width;
7214 vf->compHeight = pic_config->y_crop_height;
7215 set_frame_info(pbi, vf);
7216 if (force_fps & 0x100) {
7217 u32 rate = force_fps & 0xff;
7218
7219 if (rate)
7220 vf->duration = 96000/rate;
7221 else
7222 vf->duration = 0;
7223 }
7224 update_vf_memhandle(pbi, vf, pic_config);
7225 if (!(pic_config->y_crop_width == 196
7226 && pic_config->y_crop_height == 196
7227 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7228 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7229 inc_vf_ref(pbi, pic_config->index);
7230 decoder_do_frame_check(hw_to_vdec(pbi), vf);
7231 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7232 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7233 pbi->vf_pre_count++;
7234#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7235 /*count info*/
7236 gvs->frame_dur = pbi->frame_dur;
7237 vdec_count_info(gvs, 0, stream_offset);
7238#endif
7239 hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
7240 if (without_display_mode == 0) {
7241 vf_notify_receiver(pbi->provider_name,
7242 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7243 } else
7244 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7245 } else {
7246 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7247 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7248 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7249 __func__, __LINE__, vf->width,
7250 vf->height, pbi->stat);
7251 }
7252 }
7253
7254 return 0;
7255}
7256
7257static int notify_v4l_eos(struct vdec_s *vdec)
7258{
7259 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7260 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7261 struct vframe_s *vf = &hw->vframe_dummy;
7262 struct vdec_v4l2_buffer *fb = NULL;
7263 int index = INVALID_IDX;
7264 ulong expires;
7265
7266 if (hw->is_used_v4l && hw->eos) {
7267 expires = jiffies + msecs_to_jiffies(2000);
7268 while (INVALID_IDX == (index = get_free_fb(hw))) {
7269 if (time_after(jiffies, expires))
7270 break;
7271 }
7272
7273 if (index == INVALID_IDX) {
7274 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7275 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7276 return -1;
7277 }
7278 }
7279
7280 vf->type |= VIDTYPE_V4L_EOS;
7281 vf->timestamp = ULONG_MAX;
7282 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7283 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7284 hw->m_BUF[index].v4l_ref_buf_addr;
7285
7286 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7287 vf_notify_receiver(vdec->vf_provider_name,
7288 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7289
7290 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7291 }
7292
7293 return 0;
7294}
7295
7296static void get_rpm_param(union param_u *params)
7297{
7298 int i;
7299 unsigned int data32;
7300
7301 if (debug & VP9_DEBUG_BUFMGR)
7302 pr_info("enter %s\r\n", __func__);
7303 for (i = 0; i < 128; i++) {
7304 do {
7305 data32 = READ_VREG(RPM_CMD_REG);
7306 /*pr_info("%x\n", data32);*/
7307 } while ((data32 & 0x10000) == 0);
7308 params->l.data[i] = data32&0xffff;
7309 /*pr_info("%x\n", data32);*/
7310 WRITE_VREG(RPM_CMD_REG, 0);
7311 }
7312 if (debug & VP9_DEBUG_BUFMGR)
7313 pr_info("leave %s\r\n", __func__);
7314}
7315static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7316{
7317 int i;
7318
7319 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7320 return;
7321 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7322 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7323 pr_info("%04x ", vp9_param.l.data[i]);
7324 if (((i + 1) & 0xf) == 0)
7325 pr_info("\n");
7326 }
7327 pr_info("=============param==========\r\n");
7328 pr_info("profile %x\r\n", vp9_param.p.profile);
7329 pr_info("show_existing_frame %x\r\n",
7330 vp9_param.p.show_existing_frame);
7331 pr_info("frame_to_show_idx %x\r\n",
7332 vp9_param.p.frame_to_show_idx);
7333 pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7334 pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7335 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7336 vp9_param.p.error_resilient_mode);
7337 pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7338 pr_info("display_size_present %x\r\n",
7339 vp9_param.p.display_size_present);
7340 pr_info("reset_frame_context %x\r\n",
7341 vp9_param.p.reset_frame_context);
7342 pr_info("refresh_frame_flags %x\r\n",
7343 vp9_param.p.refresh_frame_flags);
7344 pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7345 pr_info("width %x\r\n", vp9_param.p.width);
7346 pr_info("height %x\r\n", vp9_param.p.height);
7347 pr_info("display_width %x\r\n", vp9_param.p.display_width);
7348 pr_info("display_height %x\r\n", vp9_param.p.display_height);
7349 pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7350 pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7351 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7352 return;
7353 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7354 vp9_param.p.mode_ref_delta_enabled);
7355 pr_info("sharpness_level: 0x%x\r\n",
7356 vp9_param.p.sharpness_level);
7357 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7358 vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7359 vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7360 pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7361 vp9_param.p.mode_deltas[1]);
7362 pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7363 pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7364 pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7365 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7366 (vp9_param.p.seg_lf_info[0]>>15 & 1),
7367 (vp9_param.p.seg_lf_info[1]>>15 & 1),
7368 (vp9_param.p.seg_lf_info[2]>>15 & 1),
7369 (vp9_param.p.seg_lf_info[3]>>15 & 1),
7370 (vp9_param.p.seg_lf_info[4]>>15 & 1),
7371 (vp9_param.p.seg_lf_info[5]>>15 & 1),
7372 (vp9_param.p.seg_lf_info[6]>>15 & 1),
7373 (vp9_param.p.seg_lf_info[7]>>15 & 1));
7374 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7375 (vp9_param.p.seg_lf_info[0] & 0x13f),
7376 (vp9_param.p.seg_lf_info[1] & 0x13f),
7377 (vp9_param.p.seg_lf_info[2] & 0x13f),
7378 (vp9_param.p.seg_lf_info[3] & 0x13f),
7379 (vp9_param.p.seg_lf_info[4] & 0x13f),
7380 (vp9_param.p.seg_lf_info[5] & 0x13f),
7381 (vp9_param.p.seg_lf_info[6] & 0x13f),
7382 (vp9_param.p.seg_lf_info[7] & 0x13f));
7383
7384}
7385
7386
7387static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7388{
7389 struct VP9_Common_s *const cm = &pbi->common;
7390 if (pbi->double_write_mode & 0x10)
7391 return;
7392 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7393 if (pbi->used_4k_num == -1) {
7394 pbi->used_4k_num =
7395 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7396 if (pbi->m_ins_flag)
7397 hevc_mmu_dma_check(hw_to_vdec(pbi));
7398 }
7399 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7400 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7401 cm->cur_fb_idx_mmu = INVALID_IDX;
7402 pbi->used_4k_num = -1;
7403 }
7404}
7405
7406#ifdef MULTI_INSTANCE_SUPPORT
7407static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7408{
7409 struct VP9_Common_s *const cm = &pbi->common;
7410 if (pbi->double_write_mode & 0x10)
7411 return;
7412 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7413 decoder_mmu_box_free_idx(pbi->mmu_box,
7414 cm->cur_fb_idx_mmu);
7415
7416 cm->cur_fb_idx_mmu = INVALID_IDX;
7417 pbi->used_4k_num = -1;
7418 }
7419}
7420#endif
7421
7422
7423static void dec_again_process(struct VP9Decoder_s *pbi)
7424{
7425 amhevc_stop();
7426 pbi->dec_result = DEC_RESULT_AGAIN;
7427 if (pbi->process_state ==
7428 PROC_STATE_DECODESLICE) {
7429 pbi->process_state =
7430 PROC_STATE_SENDAGAIN;
7431 if (pbi->mmu_enable)
7432 vp9_recycle_mmu_buf(pbi);
7433 }
7434 reset_process_time(pbi);
7435 vdec_schedule_work(&pbi->work);
7436}
7437
7438int continue_decoding(struct VP9Decoder_s *pbi)
7439{
7440 int ret;
7441 int i;
7442 struct VP9_Common_s *const cm = &pbi->common;
7443 debug_buffer_mgr_more(pbi);
7444
7445 bit_depth_luma = vp9_param.p.bit_depth;
7446 bit_depth_chroma = vp9_param.p.bit_depth;
7447
7448 if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7449 (get_double_write_mode(pbi) == 0x10)) {
7450 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7451 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7452 vp9_param.p.bit_depth);
7453 return -1;
7454 }
7455
7456 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7457 ret = vp9_bufmgr_process(pbi, &vp9_param);
7458 if (!pbi->m_ins_flag)
7459 pbi->slice_idx++;
7460 } else {
7461 union param_u *params = &vp9_param;
7462 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7463 ret = vp9_alloc_mmu(pbi,
7464 cm->new_fb_idx,
7465 params->p.width,
7466 params->p.height,
7467 params->p.bit_depth,
7468 pbi->frame_mmu_map_addr);
7469 if (ret >= 0)
7470 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7471 else
7472 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7473 cm->new_fb_idx,
7474 ret);
7475 } else {
7476 ret = 0;
7477 }
7478 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7479 (params->p.height << 16) | params->p.width);
7480 }
7481 if (ret < 0) {
7482 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7483 ret);
7484 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7485 cm->show_frame = 0;
7486 if (pbi->mmu_enable)
7487 vp9_recycle_mmu_buf(pbi);
7488#ifdef MULTI_INSTANCE_SUPPORT
7489 if (pbi->m_ins_flag) {
7490 pbi->dec_result = DEC_RESULT_DONE;
7491#ifdef SUPPORT_FB_DECODING
7492 if (pbi->used_stage_buf_num == 0)
7493#endif
7494 amhevc_stop();
7495 vdec_schedule_work(&pbi->work);
7496 }
7497#endif
7498 return ret;
7499 } else if (ret == 0) {
7500 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7501 = &cm->cur_frame->buf;
7502 cur_pic_config->decode_idx = pbi->frame_count;
7503
7504 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7505 if (!pbi->m_ins_flag) {
7506 pbi->frame_count++;
7507 decode_frame_count[pbi->index]
7508 = pbi->frame_count;
7509 }
7510#ifdef MULTI_INSTANCE_SUPPORT
7511 if (pbi->chunk) {
7512 cur_pic_config->pts = pbi->chunk->pts;
7513 cur_pic_config->pts64 = pbi->chunk->pts64;
7514 cur_pic_config->timestamp = pbi->chunk->timestamp;
7515 }
7516#endif
7517 }
7518 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7519 config_pic_size(pbi, vp9_param.p.bit_depth);
7520
7521 if ((pbi->common.frame_type != KEY_FRAME)
7522 && (!pbi->common.intra_only)) {
7523 config_mc_buffer(pbi, vp9_param.p.bit_depth);
7524#ifdef SUPPORT_FB_DECODING
7525 if (pbi->used_stage_buf_num == 0)
7526#endif
7527 config_mpred_hw(pbi);
7528 } else {
7529#ifdef SUPPORT_FB_DECODING
7530 if (pbi->used_stage_buf_num == 0)
7531#endif
7532 clear_mpred_hw(pbi);
7533 }
7534#ifdef MCRCC_ENABLE
7535 if (mcrcc_cache_alg_flag)
7536 config_mcrcc_axi_hw_new(pbi);
7537 else
7538 config_mcrcc_axi_hw(pbi);
7539#endif
7540 config_sao_hw(pbi, &vp9_param);
7541
7542#ifdef VP9_LPF_LVL_UPDATE
7543 /*
7544 * Get loop filter related picture level parameters from Parser
7545 */
7546 pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7547 pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7548 for (i = 0; i < 4; i++)
7549 pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7550 for (i = 0; i < 2; i++)
7551 pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7552 pbi->default_filt_lvl = vp9_param.p.filter_level;
7553 pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7554 pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7555 for (i = 0; i < MAX_SEGMENTS; i++)
7556 pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7557 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7558 for (i = 0; i < MAX_SEGMENTS; i++)
7559 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7560 = (vp9_param.p.seg_lf_info[i]
7561 & 0x100) ? -(vp9_param.p.seg_lf_info[i]
7562 & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7563 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7564 /*Set pipeline mode*/
7565 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7566 /*dblk pipeline mode=1 for performance*/
7567 if (vp9_param.p.width >= 1280)
7568 lpf_data32 |= (0x1 << 4);
7569 else
7570 lpf_data32 &= ~(0x3 << 4);
7571 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7572 }
7573 /*
7574 * Update loop filter Thr/Lvl table for every frame
7575 */
7576 /*pr_info
7577 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7578 vp9_loop_filter_frame_init(pbi->seg_4lf,
7579 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7580#endif
7581 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7582 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7583 } else {
7584 pr_info("Skip search next start code\n");
7585 cm->prev_fb_idx = INVALID_IDX;
7586 /*skip, search next start code*/
7587 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7588 }
7589 pbi->process_state = PROC_STATE_DECODESLICE;
7590 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7591 if (pbi->last_put_idx < pbi->used_buf_num) {
7592 struct RefCntBuffer_s *frame_bufs =
7593 cm->buffer_pool->frame_bufs;
7594 int i = pbi->last_put_idx;
7595 /*free not used buffers.*/
7596 if ((frame_bufs[i].ref_count == 0) &&
7597 (frame_bufs[i].buf.vf_ref == 0) &&
7598 (frame_bufs[i].buf.index != -1)) {
7599 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7600 }
7601 pbi->last_put_idx = -1;
7602 }
7603 }
7604 return ret;
7605}
7606
7607static void fill_frame_info(struct VP9Decoder_s *pbi,
7608 struct PIC_BUFFER_CONFIG_s *frame,
7609 unsigned int framesize,
7610 unsigned int pts)
7611{
7612 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7613
7614 if (frame->slice_type == KEY_FRAME)
7615 vframe_qos->type = 1;
7616 else if (frame->slice_type == INTER_FRAME)
7617 vframe_qos->type = 2;
7618/*
7619#define SHOW_QOS_INFO
7620*/
7621 vframe_qos->size = framesize;
7622 vframe_qos->pts = pts;
7623#ifdef SHOW_QOS_INFO
7624 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7625#endif
7626 vframe_qos->max_mv = frame->max_mv;
7627 vframe_qos->avg_mv = frame->avg_mv;
7628 vframe_qos->min_mv = frame->min_mv;
7629#ifdef SHOW_QOS_INFO
7630 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7631 vframe_qos->max_mv,
7632 vframe_qos->avg_mv,
7633 vframe_qos->min_mv);
7634#endif
7635 vframe_qos->max_qp = frame->max_qp;
7636 vframe_qos->avg_qp = frame->avg_qp;
7637 vframe_qos->min_qp = frame->min_qp;
7638#ifdef SHOW_QOS_INFO
7639 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7640 vframe_qos->max_qp,
7641 vframe_qos->avg_qp,
7642 vframe_qos->min_qp);
7643#endif
7644 vframe_qos->max_skip = frame->max_skip;
7645 vframe_qos->avg_skip = frame->avg_skip;
7646 vframe_qos->min_skip = frame->min_skip;
7647#ifdef SHOW_QOS_INFO
7648 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7649 vframe_qos->max_skip,
7650 vframe_qos->avg_skip,
7651 vframe_qos->min_skip);
7652#endif
7653 vframe_qos->num++;
7654
7655 if (pbi->frameinfo_enable)
7656 vdec_fill_frame_info(vframe_qos, 1);
7657}
7658
7659/* only when we decoded one field or one frame,
7660we can call this function to get qos info*/
7661static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7662{
7663 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7664
7665 if (!frame)
7666 return;
7667
7668 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7669 unsigned char a[3];
7670 unsigned char i, j, t;
7671 unsigned long data;
7672
7673 data = READ_VREG(HEVC_MV_INFO);
7674 if (frame->slice_type == KEY_FRAME)
7675 data = 0;
7676 a[0] = data & 0xff;
7677 a[1] = (data >> 8) & 0xff;
7678 a[2] = (data >> 16) & 0xff;
7679
7680 for (i = 0; i < 3; i++) {
7681 for (j = i+1; j < 3; j++) {
7682 if (a[j] < a[i]) {
7683 t = a[j];
7684 a[j] = a[i];
7685 a[i] = t;
7686 } else if (a[j] == a[i]) {
7687 a[i]++;
7688 t = a[j];
7689 a[j] = a[i];
7690 a[i] = t;
7691 }
7692 }
7693 }
7694 frame->max_mv = a[2];
7695 frame->avg_mv = a[1];
7696 frame->min_mv = a[0];
7697
7698 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7699 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7700 data, a[0], a[1], a[2]);
7701
7702 data = READ_VREG(HEVC_QP_INFO);
7703 a[0] = data & 0x1f;
7704 a[1] = (data >> 8) & 0x3f;
7705 a[2] = (data >> 16) & 0x7f;
7706
7707 for (i = 0; i < 3; i++) {
7708 for (j = i+1; j < 3; j++) {
7709 if (a[j] < a[i]) {
7710 t = a[j];
7711 a[j] = a[i];
7712 a[i] = t;
7713 } else if (a[j] == a[i]) {
7714 a[i]++;
7715 t = a[j];
7716 a[j] = a[i];
7717 a[i] = t;
7718 }
7719 }
7720 }
7721 frame->max_qp = a[2];
7722 frame->avg_qp = a[1];
7723 frame->min_qp = a[0];
7724
7725 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7726 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7727 data, a[0], a[1], a[2]);
7728
7729 data = READ_VREG(HEVC_SKIP_INFO);
7730 a[0] = data & 0x1f;
7731 a[1] = (data >> 8) & 0x3f;
7732 a[2] = (data >> 16) & 0x7f;
7733
7734 for (i = 0; i < 3; i++) {
7735 for (j = i+1; j < 3; j++) {
7736 if (a[j] < a[i]) {
7737 t = a[j];
7738 a[j] = a[i];
7739 a[i] = t;
7740 } else if (a[j] == a[i]) {
7741 a[i]++;
7742 t = a[j];
7743 a[j] = a[i];
7744 a[i] = t;
7745 }
7746 }
7747 }
7748 frame->max_skip = a[2];
7749 frame->avg_skip = a[1];
7750 frame->min_skip = a[0];
7751
7752 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7753 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7754 data, a[0], a[1], a[2]);
7755 } else {
7756 uint32_t blk88_y_count;
7757 uint32_t blk88_c_count;
7758 uint32_t blk22_mv_count;
7759 uint32_t rdata32;
7760 int32_t mv_hi;
7761 int32_t mv_lo;
7762 uint32_t rdata32_l;
7763 uint32_t mvx_L0_hi;
7764 uint32_t mvy_L0_hi;
7765 uint32_t mvx_L1_hi;
7766 uint32_t mvy_L1_hi;
7767 int64_t value;
7768 uint64_t temp_value;
7769 int pic_number = frame->decode_idx;
7770
7771 frame->max_mv = 0;
7772 frame->avg_mv = 0;
7773 frame->min_mv = 0;
7774
7775 frame->max_skip = 0;
7776 frame->avg_skip = 0;
7777 frame->min_skip = 0;
7778
7779 frame->max_qp = 0;
7780 frame->avg_qp = 0;
7781 frame->min_qp = 0;
7782
7783 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7784 frame->slice_type,
7785 pic_number);
7786
7787 /* set rd_idx to 0 */
7788 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7789
7790 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7791 if (blk88_y_count == 0) {
7792
7793 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7794 "[Picture %d Quality] NO Data yet.\n",
7795 pic_number);
7796
7797 /* reset all counts */
7798 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7799 return;
7800 }
7801 /* qp_y_sum */
7802 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7803
7804 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7805 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7806 pic_number, rdata32/blk88_y_count,
7807 rdata32, blk88_y_count);
7808
7809 frame->avg_qp = rdata32/blk88_y_count;
7810 /* intra_y_count */
7811 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7812
7813 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7814 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7815 pic_number, rdata32*100/blk88_y_count,
7816 '%', rdata32);
7817
7818 /* skipped_y_count */
7819 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7820
7821 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7822 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7823 pic_number, rdata32*100/blk88_y_count,
7824 '%', rdata32);
7825
7826 frame->avg_skip = rdata32*100/blk88_y_count;
7827 /* coeff_non_zero_y_count */
7828 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7829
7830 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7831 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7832 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7833 '%', rdata32);
7834
7835 /* blk66_c_count */
7836 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7837 if (blk88_c_count == 0) {
7838 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7839 "[Picture %d Quality] NO Data yet.\n",
7840 pic_number);
7841 /* reset all counts */
7842 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7843 return;
7844 }
7845 /* qp_c_sum */
7846 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7847
7848 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7849 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7850 pic_number, rdata32/blk88_c_count,
7851 rdata32, blk88_c_count);
7852
7853 /* intra_c_count */
7854 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7855
7856 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7857 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7858 pic_number, rdata32*100/blk88_c_count,
7859 '%', rdata32);
7860
7861 /* skipped_cu_c_count */
7862 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7863
7864 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7865 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7866 pic_number, rdata32*100/blk88_c_count,
7867 '%', rdata32);
7868
7869 /* coeff_non_zero_c_count */
7870 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7871
7872 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7873 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7874 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7875 '%', rdata32);
7876
7877 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7878 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7879 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7880
7881 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7882 "[Picture %d Quality] Y QP min : %d\n",
7883 pic_number, (rdata32>>0)&0xff);
7884
7885 frame->min_qp = (rdata32>>0)&0xff;
7886
7887 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7888 "[Picture %d Quality] Y QP max : %d\n",
7889 pic_number, (rdata32>>8)&0xff);
7890
7891 frame->max_qp = (rdata32>>8)&0xff;
7892
7893 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7894 "[Picture %d Quality] C QP min : %d\n",
7895 pic_number, (rdata32>>16)&0xff);
7896 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7897 "[Picture %d Quality] C QP max : %d\n",
7898 pic_number, (rdata32>>24)&0xff);
7899
7900 /* blk22_mv_count */
7901 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7902 if (blk22_mv_count == 0) {
7903 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7904 "[Picture %d Quality] NO MV Data yet.\n",
7905 pic_number);
7906 /* reset all counts */
7907 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7908 return;
7909 }
7910 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7911 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7912 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7913 /* should all be 0x00 or 0xff */
7914 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7915 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7916 pic_number, rdata32);
7917
7918 mvx_L0_hi = ((rdata32>>0)&0xff);
7919 mvy_L0_hi = ((rdata32>>8)&0xff);
7920 mvx_L1_hi = ((rdata32>>16)&0xff);
7921 mvy_L1_hi = ((rdata32>>24)&0xff);
7922
7923 /* mvx_L0_count[31:0] */
7924 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7925 temp_value = mvx_L0_hi;
7926 temp_value = (temp_value << 32) | rdata32_l;
7927
7928 if (mvx_L0_hi & 0x80)
7929 value = 0xFFFFFFF000000000 | temp_value;
7930 else
7931 value = temp_value;
7932
7933 value = div_s64(value, blk22_mv_count);
7934
7935 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7936 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7937 pic_number, (int)value,
7938 value, blk22_mv_count);
7939
7940 frame->avg_mv = value;
7941
7942 /* mvy_L0_count[31:0] */
7943 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7944 temp_value = mvy_L0_hi;
7945 temp_value = (temp_value << 32) | rdata32_l;
7946
7947 if (mvy_L0_hi & 0x80)
7948 value = 0xFFFFFFF000000000 | temp_value;
7949 else
7950 value = temp_value;
7951
7952 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7953 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7954 pic_number, rdata32_l/blk22_mv_count,
7955 value, blk22_mv_count);
7956
7957 /* mvx_L1_count[31:0] */
7958 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7959 temp_value = mvx_L1_hi;
7960 temp_value = (temp_value << 32) | rdata32_l;
7961 if (mvx_L1_hi & 0x80)
7962 value = 0xFFFFFFF000000000 | temp_value;
7963 else
7964 value = temp_value;
7965
7966 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7967 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
7968 pic_number, rdata32_l/blk22_mv_count,
7969 value, blk22_mv_count);
7970
7971 /* mvy_L1_count[31:0] */
7972 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7973 temp_value = mvy_L1_hi;
7974 temp_value = (temp_value << 32) | rdata32_l;
7975 if (mvy_L1_hi & 0x80)
7976 value = 0xFFFFFFF000000000 | temp_value;
7977 else
7978 value = temp_value;
7979
7980 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7981 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
7982 pic_number, rdata32_l/blk22_mv_count,
7983 value, blk22_mv_count);
7984
7985 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
7986 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7987 mv_hi = (rdata32>>16)&0xffff;
7988 if (mv_hi & 0x8000)
7989 mv_hi = 0x8000 - mv_hi;
7990
7991 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7992 "[Picture %d Quality] MVX_L0 MAX : %d\n",
7993 pic_number, mv_hi);
7994
7995 frame->max_mv = mv_hi;
7996
7997 mv_lo = (rdata32>>0)&0xffff;
7998 if (mv_lo & 0x8000)
7999 mv_lo = 0x8000 - mv_lo;
8000
8001 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8002 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8003 pic_number, mv_lo);
8004
8005 frame->min_mv = mv_lo;
8006
8007 /* {mvy_L0_max, mvy_L0_min} */
8008 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8009 mv_hi = (rdata32>>16)&0xffff;
8010 if (mv_hi & 0x8000)
8011 mv_hi = 0x8000 - mv_hi;
8012
8013 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8014 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8015 pic_number, mv_hi);
8016
8017 mv_lo = (rdata32>>0)&0xffff;
8018 if (mv_lo & 0x8000)
8019 mv_lo = 0x8000 - mv_lo;
8020
8021 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8022 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8023 pic_number, mv_lo);
8024
8025 /* {mvx_L1_max, mvx_L1_min} */
8026 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8027 mv_hi = (rdata32>>16)&0xffff;
8028 if (mv_hi & 0x8000)
8029 mv_hi = 0x8000 - mv_hi;
8030
8031 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8032 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8033 pic_number, mv_hi);
8034
8035 mv_lo = (rdata32>>0)&0xffff;
8036 if (mv_lo & 0x8000)
8037 mv_lo = 0x8000 - mv_lo;
8038
8039 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8040 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8041 pic_number, mv_lo);
8042
8043 /* {mvy_L1_max, mvy_L1_min} */
8044 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8045 mv_hi = (rdata32>>16)&0xffff;
8046 if (mv_hi & 0x8000)
8047 mv_hi = 0x8000 - mv_hi;
8048
8049 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8050 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8051 pic_number, mv_hi);
8052
8053 mv_lo = (rdata32>>0)&0xffff;
8054 if (mv_lo & 0x8000)
8055 mv_lo = 0x8000 - mv_lo;
8056
8057 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8058 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8059 pic_number, mv_lo);
8060
8061 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8062
8063 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8064 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8065 pic_number, rdata32);
8066
8067 /* reset all counts */
8068 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8069 }
8070}
8071
8072static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8073{
8074 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8075 unsigned int dec_status = pbi->dec_status;
8076 int i;
8077
8078 /*if (pbi->wait_buf)
8079 * pr_info("set wait_buf to 0\r\n");
8080 */
8081 if (pbi->eos)
8082 return IRQ_HANDLED;
8083 pbi->wait_buf = 0;
8084#ifdef MULTI_INSTANCE_SUPPORT
8085#ifdef SUPPORT_FB_DECODING
8086#ifdef FB_DECODING_TEST_SCHEDULE
8087 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8088 dec_status = HEVC_DECPIC_DATA_DONE;
8089 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8090 && dec_status == HEVC_DECPIC_DATA_DONE)
8091 dec_status = HEVC_S2_DECODING_DONE;
8092 pbi->s1_test_cmd = TEST_SET_NONE;
8093#else
8094 /*if (irq != VDEC_IRQ_0)
8095 dec_status = HEVC_S2_DECODING_DONE;*/
8096#endif
8097 if (dec_status == HEVC_S2_DECODING_DONE) {
8098 pbi->dec_result = DEC_RESULT_DONE;
8099 vdec_schedule_work(&pbi->work);
8100#ifdef FB_DECODING_TEST_SCHEDULE
8101 amhevc_stop();
8102 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8103 vdec_schedule_work(&pbi->s1_work);
8104#endif
8105 } else
8106#endif
8107 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8108 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8109 (dec_status == HEVC_DECODE_BUFEMPTY)
8110 ) {
8111 if (pbi->m_ins_flag) {
8112 reset_process_time(pbi);
8113 if (!vdec_frame_based(hw_to_vdec(pbi)))
8114 dec_again_process(pbi);
8115 else {
8116 pbi->dec_result = DEC_RESULT_GET_DATA;
8117 vdec_schedule_work(&pbi->work);
8118 }
8119 }
8120 pbi->process_busy = 0;
8121 return IRQ_HANDLED;
8122 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8123 if (pbi->m_ins_flag) {
8124 get_picture_qos_info(pbi);
8125#ifdef SUPPORT_FB_DECODING
8126 if (pbi->used_stage_buf_num > 0) {
8127 reset_process_time(pbi);
8128 inc_s1_pos(pbi);
8129 trigger_schedule(pbi);
8130#ifdef FB_DECODING_TEST_SCHEDULE
8131 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8132#else
8133 amhevc_stop();
8134 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8135 vdec_schedule_work(&pbi->s1_work);
8136#endif
8137 } else
8138#endif
8139 {
8140 reset_process_time(pbi);
8141 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8142 vp9_bufmgr_postproc(pbi);
8143
8144 pbi->dec_result = DEC_RESULT_DONE;
8145 amhevc_stop();
8146 if (mcrcc_cache_alg_flag)
8147 dump_hit_rate(pbi);
8148 vdec_schedule_work(&pbi->work);
8149 }
8150 } else {
8151 if (pbi->low_latency_flag) {
8152 vp9_bufmgr_postproc(pbi);
8153 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8154#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8155 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8156 if (debug & PRINT_FLAG_VDEC_DETAIL)
8157 pr_info("%s VP9 frame done \n", __func__);
8158#endif
8159 }
8160 }
8161
8162 pbi->process_busy = 0;
8163 return IRQ_HANDLED;
8164 }
8165#endif
8166
8167 if (dec_status == VP9_EOS) {
8168#ifdef MULTI_INSTANCE_SUPPORT
8169 if (pbi->m_ins_flag)
8170 reset_process_time(pbi);
8171#endif
8172
8173 pr_info("VP9_EOS, flush buffer\r\n");
8174
8175 vp9_bufmgr_postproc(pbi);
8176
8177 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8178 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8179 pbi->process_busy = 0;
8180#ifdef MULTI_INSTANCE_SUPPORT
8181 if (pbi->m_ins_flag) {
8182 pbi->dec_result = DEC_RESULT_DONE;
8183 amhevc_stop();
8184 vdec_schedule_work(&pbi->work);
8185 }
8186#endif
8187 return IRQ_HANDLED;
8188 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8189 pr_info("vp9 decode oversize !!\n");
8190 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8191 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8192 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8193#ifdef MULTI_INSTANCE_SUPPORT
8194 if (pbi->m_ins_flag)
8195 reset_process_time(pbi);
8196#endif
8197 return IRQ_HANDLED;
8198 }
8199
8200 if (dec_status != VP9_HEAD_PARSER_DONE) {
8201 pbi->process_busy = 0;
8202 return IRQ_HANDLED;
8203 }
8204
8205
8206#ifdef MULTI_INSTANCE_SUPPORT
8207#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8208 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8209 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8210 if (debug & PRINT_FLAG_VDEC_DETAIL)
8211 pr_info("%s VP9 frame header found \n", __func__);
8212 }
8213#endif
8214 if (pbi->m_ins_flag)
8215 reset_process_time(pbi);
8216#endif
8217 if (pbi->process_state != PROC_STATE_SENDAGAIN
8218#ifdef SUPPORT_FB_DECODING
8219 && pbi->used_stage_buf_num == 0
8220#endif
8221 ) {
8222 if (pbi->mmu_enable)
8223 vp9_recycle_mmu_buf_tail(pbi);
8224
8225
8226 if (pbi->frame_count > 0)
8227 vp9_bufmgr_postproc(pbi);
8228 }
8229
8230 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8231 get_rpm_param(&vp9_param);
8232 } else {
8233#ifdef SUPPORT_FB_DECODING
8234 if (pbi->used_stage_buf_num > 0) {
8235 reset_process_time(pbi);
8236 get_s1_buf(pbi);
8237
8238 if (get_mv_buf(pbi,
8239 &pbi->s1_mv_buf_index,
8240 &pbi->s1_mpred_mv_wr_start_addr
8241 ) < 0) {
8242 vp9_print(pbi, 0,
8243 "%s: Error get_mv_buf fail\n",
8244 __func__);
8245 }
8246
8247 if (pbi->s1_buf == NULL) {
8248 vp9_print(pbi, 0,
8249 "%s: Error get_s1_buf fail\n",
8250 __func__);
8251 pbi->process_busy = 0;
8252 return IRQ_HANDLED;
8253 }
8254
8255 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8256 int ii;
8257 for (ii = 0; ii < 4; ii++) {
8258 pbi->s1_buf->rpm[i + 3 - ii] =
8259 pbi->rpm_ptr[i + 3 - ii];
8260 pbi->s1_param.l.data[i + ii] =
8261 pbi->rpm_ptr[i + 3 - ii];
8262 }
8263 }
8264
8265 mpred_process(pbi);
8266#ifdef FB_DECODING_TEST_SCHEDULE
8267 pbi->dec_s1_result =
8268 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8269 vdec_schedule_work(&pbi->s1_work);
8270#else
8271 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8272 pbi->stage_mmu_map_phy_addr +
8273 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8274
8275 start_s1_decoding(pbi);
8276#endif
8277 start_process_time(pbi);
8278 pbi->process_busy = 0;
8279 return IRQ_HANDLED;
8280 } else
8281#endif
8282 {
8283 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8284 int ii;
8285 for (ii = 0; ii < 4; ii++)
8286 vp9_param.l.data[i + ii] =
8287 pbi->rpm_ptr[i + 3 - ii];
8288 }
8289 }
8290 }
8291
8292 if (pbi->is_used_v4l) {
8293 struct aml_vcodec_ctx *ctx =
8294 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8295
8296 pbi->frame_width = vp9_param.p.width;
8297 pbi->frame_height = vp9_param.p.height;
8298 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8299 struct aml_vdec_ps_infos ps;
8300
8301 ps.visible_width = pbi->frame_width;
8302 ps.visible_height = pbi->frame_height;
8303 ps.coded_width = ALIGN(pbi->frame_width, 32);
8304 ps.coded_height = ALIGN(pbi->frame_height, 32);
8305 ps.dpb_size = pbi->used_buf_num;
8306 pbi->v4l_params_parsed = true;
8307 vdec_v4l_set_ps_infos(ctx, &ps);
8308 }
8309 }
8310
8311 if (pbi->is_used_v4l) {
8312 pbi->dec_result = DEC_V4L2_CONTINUE_DECODING;
8313 vdec_schedule_work(&pbi->work);
8314 } else {
8315 continue_decoding(pbi);
8316 pbi->postproc_done = 0;
8317 pbi->process_busy = 0;
8318 }
8319
8320#ifdef MULTI_INSTANCE_SUPPORT
8321 if (pbi->m_ins_flag)
8322 start_process_time(pbi);
8323#endif
8324
8325 return IRQ_HANDLED;
8326}
8327
8328static irqreturn_t vvp9_isr(int irq, void *data)
8329{
8330 int i;
8331 unsigned int dec_status;
8332 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8333 unsigned int adapt_prob_status;
8334 struct VP9_Common_s *const cm = &pbi->common;
8335 uint debug_tag;
8336
8337 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8338
8339 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8340 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8341 if (!pbi)
8342 return IRQ_HANDLED;
8343 if (pbi->init_flag == 0)
8344 return IRQ_HANDLED;
8345 if (pbi->process_busy)/*on process.*/
8346 return IRQ_HANDLED;
8347 pbi->dec_status = dec_status;
8348 pbi->process_busy = 1;
8349 if (debug & VP9_DEBUG_BUFMGR)
8350 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8351 irq,
8352 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8353 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8354 READ_VREG(HEVC_STREAM_START_ADDR),
8355 READ_VREG(HEVC_STREAM_END_ADDR),
8356 READ_VREG(HEVC_STREAM_LEVEL),
8357 READ_VREG(HEVC_STREAM_WR_PTR),
8358 READ_VREG(HEVC_STREAM_RD_PTR)
8359 );
8360#ifdef SUPPORT_FB_DECODING
8361 /*if (irq != VDEC_IRQ_0)
8362 return IRQ_WAKE_THREAD;*/
8363#endif
8364
8365 debug_tag = READ_HREG(DEBUG_REG1);
8366 if (debug_tag & 0x10000) {
8367 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8368 for (i = 0; i < 0x400; i += 4) {
8369 int ii;
8370 if ((i & 0xf) == 0)
8371 pr_info("%03x: ", i);
8372 for (ii = 0; ii < 4; ii++) {
8373 pr_info("%04x ",
8374 pbi->lmem_ptr[i + 3 - ii]);
8375 }
8376 if (((i + ii) & 0xf) == 0)
8377 pr_info("\n");
8378 }
8379
8380 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8381 (udebug_pause_decode_idx == 0 ||
8382 udebug_pause_decode_idx == pbi->slice_idx) &&
8383 (udebug_pause_val == 0 ||
8384 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8385 pbi->ucode_pause_pos = udebug_pause_pos;
8386 else if (debug_tag & 0x20000)
8387 pbi->ucode_pause_pos = 0xffffffff;
8388 if (pbi->ucode_pause_pos)
8389 reset_process_time(pbi);
8390 else
8391 WRITE_HREG(DEBUG_REG1, 0);
8392 } else if (debug_tag != 0) {
8393 pr_info(
8394 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8395 READ_HREG(DEBUG_REG2),
8396 READ_VREG(HEVC_PARSER_LCU_START));
8397 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8398 (udebug_pause_decode_idx == 0 ||
8399 udebug_pause_decode_idx == pbi->slice_idx) &&
8400 (udebug_pause_val == 0 ||
8401 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8402 pbi->ucode_pause_pos = udebug_pause_pos;
8403 if (pbi->ucode_pause_pos)
8404 reset_process_time(pbi);
8405 else
8406 WRITE_HREG(DEBUG_REG1, 0);
8407 pbi->process_busy = 0;
8408 return IRQ_HANDLED;
8409 }
8410
8411#ifdef MULTI_INSTANCE_SUPPORT
8412 if (!pbi->m_ins_flag) {
8413#endif
8414 if (pbi->error_flag == 1) {
8415 pbi->error_flag = 2;
8416 pbi->process_busy = 0;
8417 return IRQ_HANDLED;
8418 } else if (pbi->error_flag == 3) {
8419 pbi->process_busy = 0;
8420 return IRQ_HANDLED;
8421 }
8422
8423 if (get_free_buf_count(pbi) <= 0) {
8424 /*
8425 if (pbi->wait_buf == 0)
8426 pr_info("set wait_buf to 1\r\n");
8427 */
8428 pbi->wait_buf = 1;
8429 pbi->process_busy = 0;
8430 return IRQ_HANDLED;
8431 }
8432#ifdef MULTI_INSTANCE_SUPPORT
8433 }
8434#endif
8435 if ((adapt_prob_status & 0xff) == 0xfd) {
8436 /*VP9_REQ_ADAPT_PROB*/
8437 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8438 uint8_t *prev_prob_b =
8439 ((uint8_t *)pbi->prob_buffer_addr) +
8440 ((adapt_prob_status >> 8) * 0x1000);
8441 uint8_t *cur_prob_b =
8442 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8443 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8444#ifdef MULTI_INSTANCE_SUPPORT
8445 if (pbi->m_ins_flag)
8446 reset_process_time(pbi);
8447#endif
8448 adapt_coef_probs(pbi->pic_count,
8449 (cm->last_frame_type == KEY_FRAME),
8450 pre_fc, (adapt_prob_status >> 8),
8451 (unsigned int *)prev_prob_b,
8452 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8453
8454 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8455 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8456 pbi->pic_count += 1;
8457#ifdef MULTI_INSTANCE_SUPPORT
8458 if (pbi->m_ins_flag)
8459 start_process_time(pbi);
8460#endif
8461
8462 /*return IRQ_HANDLED;*/
8463 }
8464 return IRQ_WAKE_THREAD;
8465}
8466
8467static void vp9_set_clk(struct work_struct *work)
8468{
8469 struct VP9Decoder_s *pbi = container_of(work,
8470 struct VP9Decoder_s, set_clk_work);
8471 int fps = 96000 / pbi->frame_dur;
8472
8473 if (hevc_source_changed(VFORMAT_VP9,
8474 frame_width, frame_height, fps) > 0)
8475 pbi->saved_resolution = frame_width *
8476 frame_height * fps;
8477}
8478
8479static void vvp9_put_timer_func(unsigned long arg)
8480{
8481 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8482 struct timer_list *timer = &pbi->timer;
8483 uint8_t empty_flag;
8484 unsigned int buf_level;
8485
8486 enum receviver_start_e state = RECEIVER_INACTIVE;
8487
8488 if (pbi->m_ins_flag) {
8489 if (hw_to_vdec(pbi)->next_status
8490 == VDEC_STATUS_DISCONNECTED) {
8491#ifdef SUPPORT_FB_DECODING
8492 if (pbi->run2_busy)
8493 return;
8494
8495 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8496 vdec_schedule_work(&pbi->s1_work);
8497#endif
8498 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8499 vdec_schedule_work(&pbi->work);
8500 pr_debug(
8501 "vdec requested to be disconnected\n");
8502 return;
8503 }
8504 }
8505 if (pbi->init_flag == 0) {
8506 if (pbi->stat & STAT_TIMER_ARM) {
8507 timer->expires = jiffies + PUT_INTERVAL;
8508 add_timer(&pbi->timer);
8509 }
8510 return;
8511 }
8512 if (pbi->m_ins_flag == 0) {
8513 if (vf_get_receiver(pbi->provider_name)) {
8514 state =
8515 vf_notify_receiver(pbi->provider_name,
8516 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8517 NULL);
8518 if ((state == RECEIVER_STATE_NULL)
8519 || (state == RECEIVER_STATE_NONE))
8520 state = RECEIVER_INACTIVE;
8521 } else
8522 state = RECEIVER_INACTIVE;
8523
8524 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8525 /* error watchdog */
8526 if (empty_flag == 0) {
8527 /* decoder has input */
8528 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8529
8530 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8531 /* receiver has no buffer to recycle */
8532 if ((state == RECEIVER_INACTIVE) &&
8533 (kfifo_is_empty(&pbi->display_q) &&
8534 buf_level > 0x200)
8535 ) {
8536 WRITE_VREG
8537 (HEVC_ASSIST_MBOX0_IRQ_REG,
8538 0x1);
8539 }
8540 }
8541
8542 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8543 /* receiver has no buffer to recycle */
8544 /*if ((state == RECEIVER_INACTIVE) &&
8545 * (kfifo_is_empty(&pbi->display_q))) {
8546 *pr_info("vp9 something error,need reset\n");
8547 *}
8548 */
8549 }
8550 }
8551 }
8552#ifdef MULTI_INSTANCE_SUPPORT
8553 else {
8554 if (
8555 (decode_timeout_val > 0) &&
8556 (pbi->start_process_time > 0) &&
8557 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8558 > decode_timeout_val)
8559 ) {
8560 int current_lcu_idx =
8561 READ_VREG(HEVC_PARSER_LCU_START)
8562 & 0xffffff;
8563 if (pbi->last_lcu_idx == current_lcu_idx) {
8564 if (pbi->decode_timeout_count > 0)
8565 pbi->decode_timeout_count--;
8566 if (pbi->decode_timeout_count == 0) {
8567 if (input_frame_based(
8568 hw_to_vdec(pbi)) ||
8569 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8570 timeout_process(pbi);
8571 else {
8572 vp9_print(pbi, 0,
8573 "timeout & empty, again\n");
8574 dec_again_process(pbi);
8575 }
8576 }
8577 } else {
8578 start_process_time(pbi);
8579 pbi->last_lcu_idx = current_lcu_idx;
8580 }
8581 }
8582 }
8583#endif
8584
8585 if ((pbi->ucode_pause_pos != 0) &&
8586 (pbi->ucode_pause_pos != 0xffffffff) &&
8587 udebug_pause_pos != pbi->ucode_pause_pos) {
8588 pbi->ucode_pause_pos = 0;
8589 WRITE_HREG(DEBUG_REG1, 0);
8590 }
8591#ifdef MULTI_INSTANCE_SUPPORT
8592 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8593 pr_info(
8594 "Force Send Again\r\n");
8595 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8596 reset_process_time(pbi);
8597 pbi->dec_result = DEC_RESULT_AGAIN;
8598 if (pbi->process_state ==
8599 PROC_STATE_DECODESLICE) {
8600 if (pbi->mmu_enable)
8601 vp9_recycle_mmu_buf(pbi);
8602 pbi->process_state =
8603 PROC_STATE_SENDAGAIN;
8604 }
8605 amhevc_stop();
8606
8607 vdec_schedule_work(&pbi->work);
8608 }
8609
8610 if (debug & VP9_DEBUG_DUMP_DATA) {
8611 debug &= ~VP9_DEBUG_DUMP_DATA;
8612 vp9_print(pbi, 0,
8613 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8614 __func__,
8615 pbi->chunk->size,
8616 pbi->chunk->offset,
8617 get_data_check_sum(pbi, pbi->chunk->size)
8618 );
8619 dump_data(pbi, pbi->chunk->size);
8620 }
8621#endif
8622 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8623 dump_pic_list(pbi);
8624 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8625 }
8626 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8627 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8628 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8629 }
8630 /*if (debug & VP9_DEBUG_HW_RESET) {
8631 }*/
8632
8633 if (radr != 0) {
8634 if (rval != 0) {
8635 WRITE_VREG(radr, rval);
8636 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8637 } else
8638 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8639 rval = 0;
8640 radr = 0;
8641 }
8642 if (pop_shorts != 0) {
8643 int i;
8644 u32 sum = 0;
8645
8646 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8647 for (i = 0; i < pop_shorts; i++) {
8648 u32 data =
8649 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8650 WRITE_HREG(HEVC_SHIFT_COMMAND,
8651 (1<<7)|16);
8652 if ((i & 0xf) == 0)
8653 pr_info("%04x:", i);
8654 pr_info("%04x ", data);
8655 if (((i + 1) & 0xf) == 0)
8656 pr_info("\r\n");
8657 sum += data;
8658 }
8659 pr_info("\r\nsum = %x\r\n", sum);
8660 pop_shorts = 0;
8661 }
8662 if (dbg_cmd != 0) {
8663 if (dbg_cmd == 1) {
8664 u32 disp_laddr;
8665
8666 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8667 get_double_write_mode(pbi) == 0) {
8668 disp_laddr =
8669 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8670 } else {
8671 struct canvas_s cur_canvas;
8672
8673 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8674 & 0xff), &cur_canvas);
8675 disp_laddr = cur_canvas.addr;
8676 }
8677 pr_info("current displayed buffer address %x\r\n",
8678 disp_laddr);
8679 }
8680 dbg_cmd = 0;
8681 }
8682 /*don't changed at start.*/
8683 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8684 pbi->frame_dur > 0 && pbi->saved_resolution !=
8685 frame_width * frame_height *
8686 (96000 / pbi->frame_dur))
8687 vdec_schedule_work(&pbi->set_clk_work);
8688
8689 timer->expires = jiffies + PUT_INTERVAL;
8690 add_timer(timer);
8691}
8692
8693
8694int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8695{
8696 struct VP9Decoder_s *vp9 =
8697 (struct VP9Decoder_s *)vdec->private;
8698
8699 if (!vp9)
8700 return -1;
8701
8702 vstatus->frame_width = frame_width;
8703 vstatus->frame_height = frame_height;
8704 if (vp9->frame_dur != 0)
8705 vstatus->frame_rate = 96000 / vp9->frame_dur;
8706 else
8707 vstatus->frame_rate = -1;
8708 vstatus->error_count = 0;
8709 vstatus->status = vp9->stat | vp9->fatal_error;
8710 vstatus->frame_dur = vp9->frame_dur;
8711#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8712 vstatus->bit_rate = gvs->bit_rate;
8713 vstatus->frame_data = gvs->frame_data;
8714 vstatus->total_data = gvs->total_data;
8715 vstatus->frame_count = gvs->frame_count;
8716 vstatus->error_frame_count = gvs->error_frame_count;
8717 vstatus->drop_frame_count = gvs->drop_frame_count;
8718 vstatus->total_data = gvs->total_data;
8719 vstatus->samp_cnt = gvs->samp_cnt;
8720 vstatus->offset = gvs->offset;
8721 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8722 "%s", DRIVER_NAME);
8723#endif
8724 return 0;
8725}
8726
8727int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8728{
8729 is_reset = isreset;
8730 return 0;
8731}
8732
8733#if 0
8734static void VP9_DECODE_INIT(void)
8735{
8736 /* enable vp9 clocks */
8737 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8738 /* *************************************************************** */
8739 /* Power ON HEVC */
8740 /* *************************************************************** */
8741 /* Powerup HEVC */
8742 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8743 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8744 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8745 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8746 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8747 /* remove isolations */
8748 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8749 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8750
8751}
8752#endif
8753
8754static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8755{
8756 unsigned int data32;
8757 /* VP9_DECODE_INIT(); */
8758 vp9_config_work_space_hw(pbi, mask);
8759 if (mask & HW_MASK_BACK)
8760 init_pic_list_hw(pbi);
8761
8762 vp9_init_decoder_hw(pbi, mask);
8763
8764#ifdef VP9_LPF_LVL_UPDATE
8765 if (mask & HW_MASK_BACK)
8766 vp9_loop_filter_init(pbi);
8767#endif
8768
8769 if ((mask & HW_MASK_FRONT) == 0)
8770 return;
8771#if 1
8772 if (debug & VP9_DEBUG_BUFMGR_MORE)
8773 pr_info("%s\n", __func__);
8774 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8775 data32 = data32 |
8776 (1 << 0)/*stream_fetch_enable*/
8777 ;
8778 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8779
8780 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8781 if (debug & VP9_DEBUG_BUFMGR)
8782 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8783 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8784 data32 = data32 |
8785 (1 << 29) // stream_fifo_hole
8786 ;
8787 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8788 }
8789#if 0
8790 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8791 if (data32 != 0x00000100) {
8792 pr_info("vp9 prot init error %d\n", __LINE__);
8793 return;
8794 }
8795 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8796 if (data32 != 0x00000300) {
8797 pr_info("vp9 prot init error %d\n", __LINE__);
8798 return;
8799 }
8800 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8801 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8802 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8803 if (data32 != 0x12345678) {
8804 pr_info("vp9 prot init error %d\n", __LINE__);
8805 return;
8806 }
8807 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8808 if (data32 != 0x9abcdef0) {
8809 pr_info("vp9 prot init error %d\n", __LINE__);
8810 return;
8811 }
8812#endif
8813 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8814 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8815#endif
8816
8817
8818
8819 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8820
8821 /* WRITE_VREG(HEVC_MPSR, 1); */
8822
8823 /* clear mailbox interrupt */
8824 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8825
8826 /* enable mailbox interrupt */
8827 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8828
8829 /* disable PSCALE for hardware sharing */
8830 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8831
8832 WRITE_VREG(DEBUG_REG1, 0x0);
8833 /*check vps/sps/pps/i-slice in ucode*/
8834 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8835
8836 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8837#ifdef SUPPORT_FB_DECODING
8838#ifndef FB_DECODING_TEST_SCHEDULE
8839 if (pbi->used_stage_buf_num > 0) {
8840 if (mask & HW_MASK_FRONT) {
8841 data32 = READ_VREG(
8842 HEVC_ASSIST_HED_FB_W_CTL);
8843 data32 = data32 |
8844 (1 << 0) /*hed_fb_wr_en*/
8845 ;
8846 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8847 data32);
8848 }
8849 if (mask & HW_MASK_BACK) {
8850 data32 = READ_VREG(
8851 HEVC_ASSIST_HED_FB_R_CTL);
8852 while (data32 & (1 << 7)) {
8853 /*wait finish*/
8854 data32 = READ_VREG(
8855 HEVC_ASSIST_HED_FB_R_CTL);
8856 }
8857 data32 &= (~(0x1 << 0));
8858 /*hed_fb_rd_addr_auto_rd*/
8859 data32 &= (~(0x1 << 1));
8860 /*rd_id = 0, hed_rd_map_auto_halt_num,
8861 after wr 2 ready, then start reading*/
8862 data32 |= (0x2 << 16);
8863 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8864 data32);
8865
8866 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8867 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8868 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8869 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8870 data32);
8871 }
8872
8873 }
8874#endif
8875#endif
8876}
8877
8878static int vvp9_local_init(struct VP9Decoder_s *pbi)
8879{
8880 int i;
8881 int ret;
8882 int width, height;
8883 if (alloc_lf_buf(pbi) < 0)
8884 return -1;
8885
8886 pbi->gvs = vzalloc(sizeof(struct vdec_info));
8887 if (NULL == pbi->gvs) {
8888 pr_info("the struct of vdec status malloc failed.\n");
8889 return -1;
8890 }
8891#ifdef DEBUG_PTS
8892 pbi->pts_missed = 0;
8893 pbi->pts_hit = 0;
8894#endif
8895 pbi->new_frame_displayed = 0;
8896 pbi->last_put_idx = -1;
8897 pbi->saved_resolution = 0;
8898 pbi->get_frame_dur = false;
8899 on_no_keyframe_skiped = 0;
8900 pbi->duration_from_pts_done = 0;
8901 pbi->vp9_first_pts_ready = 0;
8902 pbi->frame_cnt_window = 0;
8903 width = pbi->vvp9_amstream_dec_info.width;
8904 height = pbi->vvp9_amstream_dec_info.height;
8905 pbi->frame_dur =
8906 (pbi->vvp9_amstream_dec_info.rate ==
8907 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8908 if (width && height)
8909 pbi->frame_ar = height * 0x100 / width;
8910/*
8911 *TODO:FOR VERSION
8912 */
8913 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8914 0, width, height, pbi->frame_dur);
8915
8916 if (pbi->frame_dur == 0)
8917 pbi->frame_dur = 96000 / 24;
8918
8919 INIT_KFIFO(pbi->display_q);
8920 INIT_KFIFO(pbi->newframe_q);
8921
8922
8923 for (i = 0; i < VF_POOL_SIZE; i++) {
8924 const struct vframe_s *vf = &pbi->vfpool[i];
8925
8926 pbi->vfpool[i].index = -1;
8927 kfifo_put(&pbi->newframe_q, vf);
8928 }
8929
8930
8931 ret = vp9_local_init(pbi);
8932
8933 if (!pbi->pts_unstable) {
8934 pbi->pts_unstable =
8935 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8936 pr_info("set pts unstable\n");
8937 }
8938
8939 return ret;
8940}
8941
8942
8943#ifdef MULTI_INSTANCE_SUPPORT
8944static s32 vvp9_init(struct vdec_s *vdec)
8945{
8946 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8947#else
8948static s32 vvp9_init(struct VP9Decoder_s *pbi)
8949{
8950#endif
8951 int ret;
8952 int fw_size = 0x1000 * 16;
8953 struct firmware_s *fw = NULL;
8954
8955 pbi->stat |= STAT_TIMER_INIT;
8956
8957 if (vvp9_local_init(pbi) < 0)
8958 return -EBUSY;
8959
8960 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8961 if (IS_ERR_OR_NULL(fw))
8962 return -ENOMEM;
8963
8964 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8965 pr_err("get firmware fail.\n");
8966 vfree(fw);
8967 return -1;
8968 }
8969
8970 fw->len = fw_size;
8971
8972 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
8973 init_timer(&pbi->timer);
8974
8975#ifdef MULTI_INSTANCE_SUPPORT
8976 if (pbi->m_ins_flag) {
8977 pbi->timer.data = (ulong) pbi;
8978 pbi->timer.function = vvp9_put_timer_func;
8979 pbi->timer.expires = jiffies + PUT_INTERVAL;
8980
8981 /*add_timer(&pbi->timer);
8982
8983 pbi->stat |= STAT_TIMER_ARM;
8984 pbi->stat |= STAT_ISR_REG;*/
8985
8986 INIT_WORK(&pbi->work, vp9_work);
8987#ifdef SUPPORT_FB_DECODING
8988 if (pbi->used_stage_buf_num > 0)
8989 INIT_WORK(&pbi->s1_work, vp9_s1_work);
8990#endif
8991 pbi->fw = fw;
8992
8993 /* picture list init.*/
8994 pbi->dec_result = DEC_INIT_PICLIST;
8995 vdec_schedule_work(&pbi->work);
8996
8997 return 0;
8998 }
8999#endif
9000 amhevc_enable();
9001
9002 init_pic_list(pbi);
9003
9004 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9005 if (ret < 0) {
9006 amhevc_disable();
9007 vfree(fw);
9008 pr_err("VP9: the %s fw loading failed, err: %x\n",
9009 tee_enabled() ? "TEE" : "local", ret);
9010 return -EBUSY;
9011 }
9012
9013 vfree(fw);
9014
9015 pbi->stat |= STAT_MC_LOAD;
9016
9017 /* enable AMRISC side protocol */
9018 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9019
9020 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9021 vvp9_isr,
9022 vvp9_isr_thread_fn,
9023 IRQF_ONESHOT,/*run thread on this irq disabled*/
9024 "vvp9-irq", (void *)pbi)) {
9025 pr_info("vvp9 irq register error.\n");
9026 amhevc_disable();
9027 return -ENOENT;
9028 }
9029
9030 pbi->stat |= STAT_ISR_REG;
9031
9032 pbi->provider_name = PROVIDER_NAME;
9033#ifdef MULTI_INSTANCE_SUPPORT
9034 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9035 &vvp9_vf_provider, pbi);
9036 vf_reg_provider(&vvp9_vf_prov);
9037 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9038 if (pbi->frame_dur != 0) {
9039 if (!is_reset)
9040 vf_notify_receiver(pbi->provider_name,
9041 VFRAME_EVENT_PROVIDER_FR_HINT,
9042 (void *)
9043 ((unsigned long)pbi->frame_dur));
9044 }
9045#else
9046 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9047 pbi);
9048 vf_reg_provider(&vvp9_vf_prov);
9049 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9050 if (!is_reset)
9051 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9052 (void *)((unsigned long)pbi->frame_dur));
9053#endif
9054 pbi->stat |= STAT_VF_HOOK;
9055
9056 pbi->timer.data = (ulong)pbi;
9057 pbi->timer.function = vvp9_put_timer_func;
9058 pbi->timer.expires = jiffies + PUT_INTERVAL;
9059
9060 pbi->stat |= STAT_VDEC_RUN;
9061
9062 add_timer(&pbi->timer);
9063
9064 pbi->stat |= STAT_TIMER_ARM;
9065
9066 amhevc_start();
9067
9068 pbi->init_flag = 1;
9069 pbi->process_busy = 0;
9070 pr_info("%d, vvp9_init, RP=0x%x\n",
9071 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9072 return 0;
9073}
9074
9075static int vmvp9_stop(struct VP9Decoder_s *pbi)
9076{
9077 pbi->init_flag = 0;
9078
9079 if (pbi->stat & STAT_VDEC_RUN) {
9080 amhevc_stop();
9081 pbi->stat &= ~STAT_VDEC_RUN;
9082 }
9083 if (pbi->stat & STAT_ISR_REG) {
9084 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9085 pbi->stat &= ~STAT_ISR_REG;
9086 }
9087 if (pbi->stat & STAT_TIMER_ARM) {
9088 del_timer_sync(&pbi->timer);
9089 pbi->stat &= ~STAT_TIMER_ARM;
9090 }
9091
9092 if (pbi->stat & STAT_VF_HOOK) {
9093 if (!is_reset)
9094 vf_notify_receiver(pbi->provider_name,
9095 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9096 NULL);
9097
9098 vf_unreg_provider(&vvp9_vf_prov);
9099 pbi->stat &= ~STAT_VF_HOOK;
9100 }
9101 vp9_local_uninit(pbi);
9102 reset_process_time(pbi);
9103 cancel_work_sync(&pbi->work);
9104#ifdef SUPPORT_FB_DECODING
9105 if (pbi->used_stage_buf_num > 0)
9106 cancel_work_sync(&pbi->s1_work);
9107#endif
9108 cancel_work_sync(&pbi->set_clk_work);
9109 uninit_mmu_buffers(pbi);
9110 if (pbi->fw)
9111 vfree(pbi->fw);
9112 pbi->fw = NULL;
9113 return 0;
9114}
9115
9116static int vvp9_stop(struct VP9Decoder_s *pbi)
9117{
9118
9119 pbi->init_flag = 0;
9120 pbi->first_sc_checked = 0;
9121 if (pbi->stat & STAT_VDEC_RUN) {
9122 amhevc_stop();
9123 pbi->stat &= ~STAT_VDEC_RUN;
9124 }
9125
9126 if (pbi->stat & STAT_ISR_REG) {
9127#ifdef MULTI_INSTANCE_SUPPORT
9128 if (!pbi->m_ins_flag)
9129#endif
9130 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9131 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9132 pbi->stat &= ~STAT_ISR_REG;
9133 }
9134
9135 if (pbi->stat & STAT_TIMER_ARM) {
9136 del_timer_sync(&pbi->timer);
9137 pbi->stat &= ~STAT_TIMER_ARM;
9138 }
9139
9140 if (pbi->stat & STAT_VF_HOOK) {
9141 if (!is_reset)
9142 vf_notify_receiver(pbi->provider_name,
9143 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9144 NULL);
9145
9146 vf_unreg_provider(&vvp9_vf_prov);
9147 pbi->stat &= ~STAT_VF_HOOK;
9148 }
9149 vp9_local_uninit(pbi);
9150
9151 cancel_work_sync(&pbi->set_clk_work);
9152#ifdef MULTI_INSTANCE_SUPPORT
9153 if (pbi->m_ins_flag) {
9154#ifdef SUPPORT_FB_DECODING
9155 if (pbi->used_stage_buf_num > 0)
9156 cancel_work_sync(&pbi->s1_work);
9157#endif
9158 cancel_work_sync(&pbi->work);
9159 } else
9160 amhevc_disable();
9161#else
9162 amhevc_disable();
9163#endif
9164 uninit_mmu_buffers(pbi);
9165
9166 vfree(pbi->fw);
9167 pbi->fw = NULL;
9168 return 0;
9169}
9170static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9171{
9172 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9173 CODEC_MM_FLAGS_TVP : 0;
9174 int buf_size = 48;
9175
9176 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9177 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9178 buf_size = 12;
9179 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9180 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9181 buf_size = 4;
9182 }
9183 pbi->need_cache_size = buf_size * SZ_1M;
9184 pbi->sc_start_time = get_jiffies_64();
9185 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9186 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9187 pbi->index, FRAME_BUFFERS,
9188 pbi->need_cache_size,
9189 tvp_flag
9190 );
9191 if (!pbi->mmu_box) {
9192 pr_err("vp9 alloc mmu box failed!!\n");
9193 return -1;
9194 }
9195 }
9196 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9197 DRIVER_NAME,
9198 pbi->index,
9199 MAX_BMMU_BUFFER_NUM,
9200 4 + PAGE_SHIFT,
9201 CODEC_MM_FLAGS_CMA_CLEAR |
9202 CODEC_MM_FLAGS_FOR_VDECODER |
9203 tvp_flag);
9204 if (!pbi->bmmu_box) {
9205 pr_err("vp9 alloc bmmu box failed!!\n");
9206 return -1;
9207 }
9208 return 0;
9209}
9210
9211static struct VP9Decoder_s *gHevc;
9212
9213static int amvdec_vp9_probe(struct platform_device *pdev)
9214{
9215 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9216 struct BUF_s BUF[MAX_BUF_NUM];
9217 struct VP9Decoder_s *pbi;
9218 int ret;
9219#ifndef MULTI_INSTANCE_SUPPORT
9220 int i;
9221#endif
9222 pr_debug("%s\n", __func__);
9223
9224 mutex_lock(&vvp9_mutex);
9225 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9226 if (pbi == NULL) {
9227 pr_info("\namvdec_vp9 device data allocation failed\n");
9228 mutex_unlock(&vvp9_mutex);
9229 return -ENOMEM;
9230 }
9231
9232 gHevc = pbi;
9233 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9234 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9235 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9236
9237 pbi->init_flag = 0;
9238 pbi->first_sc_checked= 0;
9239 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9240 vp9_max_pic_w = 8192;
9241 vp9_max_pic_h = 4608;
9242 }
9243 pbi->max_pic_w = vp9_max_pic_w;
9244 pbi->max_pic_h = vp9_max_pic_h;
9245
9246#ifdef MULTI_INSTANCE_SUPPORT
9247 pbi->eos = 0;
9248 pbi->start_process_time = 0;
9249 pbi->timeout_num = 0;
9250#endif
9251 pbi->fatal_error = 0;
9252 pbi->show_frame_num = 0;
9253 if (pdata == NULL) {
9254 pr_info("\namvdec_vp9 memory resource undefined.\n");
9255 vfree(pbi);
9256 mutex_unlock(&vvp9_mutex);
9257 return -EFAULT;
9258 }
9259 pbi->m_ins_flag = 0;
9260#ifdef MULTI_INSTANCE_SUPPORT
9261 pbi->platform_dev = pdev;
9262 platform_set_drvdata(pdev, pdata);
9263#endif
9264 pbi->double_write_mode = double_write_mode;
9265 pbi->mmu_enable = 1;
9266 if (amvdec_vp9_mmu_init(pbi) < 0) {
9267 vfree(pbi);
9268 mutex_unlock(&vvp9_mutex);
9269 pr_err("vp9 alloc bmmu box failed!!\n");
9270 return -1;
9271 }
9272
9273 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9274 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9275 if (ret < 0) {
9276 uninit_mmu_buffers(pbi);
9277 vfree(pbi);
9278 mutex_unlock(&vvp9_mutex);
9279 return ret;
9280 }
9281 pbi->buf_size = work_buf_size;
9282
9283#ifdef MULTI_INSTANCE_SUPPORT
9284 pbi->buf_start = pdata->mem_start;
9285#else
9286 if (!pbi->mmu_enable)
9287 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9288
9289 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9290 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9291#endif
9292
9293
9294 if (debug) {
9295 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9296 pdata->mem_start, pbi->buf_size);
9297 }
9298
9299 if (pdata->sys_info)
9300 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9301 else {
9302 pbi->vvp9_amstream_dec_info.width = 0;
9303 pbi->vvp9_amstream_dec_info.height = 0;
9304 pbi->vvp9_amstream_dec_info.rate = 30;
9305 }
9306 pbi->no_head = no_head;
9307#ifdef MULTI_INSTANCE_SUPPORT
9308 pbi->cma_dev = pdata->cma_dev;
9309#else
9310 cma_dev = pdata->cma_dev;
9311#endif
9312
9313#ifdef MULTI_INSTANCE_SUPPORT
9314 pdata->private = pbi;
9315 pdata->dec_status = vvp9_dec_status;
9316 pdata->set_isreset = vvp9_set_isreset;
9317 is_reset = 0;
9318 if (vvp9_init(pdata) < 0) {
9319#else
9320 if (vvp9_init(pbi) < 0) {
9321#endif
9322 pr_info("\namvdec_vp9 init failed.\n");
9323 vp9_local_uninit(pbi);
9324 uninit_mmu_buffers(pbi);
9325 vfree(pbi);
9326 pdata->dec_status = NULL;
9327 mutex_unlock(&vvp9_mutex);
9328 return -ENODEV;
9329 }
9330 /*set the max clk for smooth playing...*/
9331 hevc_source_changed(VFORMAT_VP9,
9332 4096, 2048, 60);
9333 mutex_unlock(&vvp9_mutex);
9334
9335 return 0;
9336}
9337
9338static int amvdec_vp9_remove(struct platform_device *pdev)
9339{
9340 struct VP9Decoder_s *pbi = gHevc;
9341 struct vdec_s *vdec = hw_to_vdec(pbi);
9342 int i;
9343
9344 if (debug)
9345 pr_info("amvdec_vp9_remove\n");
9346
9347 mutex_lock(&vvp9_mutex);
9348
9349 vvp9_stop(pbi);
9350
9351 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9352
9353 if (vdec->parallel_dec == 1) {
9354 for (i = 0; i < FRAME_BUFFERS; i++) {
9355 vdec->free_canvas_ex(pbi->common.buffer_pool->
9356 frame_bufs[i].buf.y_canvas_index, vdec->id);
9357 vdec->free_canvas_ex(pbi->common.buffer_pool->
9358 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9359 }
9360 }
9361
9362#ifdef DEBUG_PTS
9363 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9364 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9365#endif
9366 mem_map_mode = 0;
9367
9368 vfree(pbi);
9369 mutex_unlock(&vvp9_mutex);
9370
9371 return 0;
9372}
9373
9374/****************************************/
9375#ifdef CONFIG_PM
9376static int vp9_suspend(struct device *dev)
9377{
9378 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9379 return 0;
9380}
9381
9382static int vp9_resume(struct device *dev)
9383{
9384 amhevc_resume(to_platform_device(dev));
9385 return 0;
9386}
9387
9388static const struct dev_pm_ops vp9_pm_ops = {
9389 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9390};
9391#endif
9392
9393static struct platform_driver amvdec_vp9_driver = {
9394 .probe = amvdec_vp9_probe,
9395 .remove = amvdec_vp9_remove,
9396 .driver = {
9397 .name = DRIVER_NAME,
9398#ifdef CONFIG_PM
9399 .pm = &vp9_pm_ops,
9400#endif
9401 }
9402};
9403
9404static struct codec_profile_t amvdec_vp9_profile = {
9405 .name = "vp9",
9406 .profile = ""
9407};
9408
9409static struct codec_profile_t amvdec_vp9_profile_mult;
9410
9411static unsigned char get_data_check_sum
9412 (struct VP9Decoder_s *pbi, int size)
9413{
9414 int jj;
9415 int sum = 0;
9416 u8 *data = NULL;
9417
9418 if (!pbi->chunk->block->is_mapped)
9419 data = codec_mm_vmap(pbi->chunk->block->start +
9420 pbi->chunk->offset, size);
9421 else
9422 data = ((u8 *)pbi->chunk->block->start_virt) +
9423 pbi->chunk->offset;
9424
9425 for (jj = 0; jj < size; jj++)
9426 sum += data[jj];
9427
9428 if (!pbi->chunk->block->is_mapped)
9429 codec_mm_unmap_phyaddr(data);
9430 return sum;
9431}
9432
9433static void dump_data(struct VP9Decoder_s *pbi, int size)
9434{
9435 int jj;
9436 u8 *data = NULL;
9437 int padding_size = pbi->chunk->offset &
9438 (VDEC_FIFO_ALIGN - 1);
9439
9440 if (!pbi->chunk->block->is_mapped)
9441 data = codec_mm_vmap(pbi->chunk->block->start +
9442 pbi->chunk->offset, size);
9443 else
9444 data = ((u8 *)pbi->chunk->block->start_virt) +
9445 pbi->chunk->offset;
9446
9447 vp9_print(pbi, 0, "padding: ");
9448 for (jj = padding_size; jj > 0; jj--)
9449 vp9_print_cont(pbi,
9450 0,
9451 "%02x ", *(data - jj));
9452 vp9_print_cont(pbi, 0, "data adr %p\n",
9453 data);
9454
9455 for (jj = 0; jj < size; jj++) {
9456 if ((jj & 0xf) == 0)
9457 vp9_print(pbi,
9458 0,
9459 "%06x:", jj);
9460 vp9_print_cont(pbi,
9461 0,
9462 "%02x ", data[jj]);
9463 if (((jj + 1) & 0xf) == 0)
9464 vp9_print(pbi,
9465 0,
9466 "\n");
9467 }
9468 vp9_print(pbi,
9469 0,
9470 "\n");
9471
9472 if (!pbi->chunk->block->is_mapped)
9473 codec_mm_unmap_phyaddr(data);
9474}
9475
9476static void vp9_work(struct work_struct *work)
9477{
9478 struct VP9Decoder_s *pbi = container_of(work,
9479 struct VP9Decoder_s, work);
9480 struct vdec_s *vdec = hw_to_vdec(pbi);
9481 /* finished decoding one frame or error,
9482 * notify vdec core to switch context
9483 */
9484 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9485 "%s dec_result %d %x %x %x\n",
9486 __func__,
9487 pbi->dec_result,
9488 READ_VREG(HEVC_STREAM_LEVEL),
9489 READ_VREG(HEVC_STREAM_WR_PTR),
9490 READ_VREG(HEVC_STREAM_RD_PTR));
9491
9492 if (pbi->dec_result == DEC_INIT_PICLIST) {
9493 init_pic_list(pbi);
9494 pbi->pic_list_init_done = true;
9495 return;
9496 }
9497
9498 if (pbi->dec_result == DEC_V4L2_CONTINUE_DECODING) {
9499 struct aml_vcodec_ctx *ctx =
9500 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9501
9502 if (ctx->param_sets_from_ucode) {
9503 reset_process_time(pbi);
9504 if (wait_event_interruptible_timeout(ctx->wq,
9505 ctx->v4l_codec_ready,
9506 msecs_to_jiffies(500)) < 0)
9507 return;
9508 }
9509
9510 continue_decoding(pbi);
9511 pbi->postproc_done = 0;
9512 pbi->process_busy = 0;
9513
9514 return;
9515 }
9516
9517 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9518 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9519 && (hw_to_vdec(pbi)->next_status !=
9520 VDEC_STATUS_DISCONNECTED)) {
9521 if (!vdec_has_more_input(vdec)) {
9522 pbi->dec_result = DEC_RESULT_EOS;
9523 vdec_schedule_work(&pbi->work);
9524 return;
9525 }
9526
9527 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9528 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9529 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9530 __func__,
9531 READ_VREG(HEVC_STREAM_LEVEL),
9532 READ_VREG(HEVC_STREAM_WR_PTR),
9533 READ_VREG(HEVC_STREAM_RD_PTR));
9534 vdec_vframe_dirty(vdec, pbi->chunk);
9535 vdec_clean_input(vdec);
9536 }
9537
9538 if (get_free_buf_count(pbi) >=
9539 run_ready_min_buf_num) {
9540 int r;
9541 int decode_size;
9542 r = vdec_prepare_input(vdec, &pbi->chunk);
9543 if (r < 0) {
9544 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9545
9546 vp9_print(pbi,
9547 PRINT_FLAG_VDEC_DETAIL,
9548 "amvdec_vh265: Insufficient data\n");
9549
9550 vdec_schedule_work(&pbi->work);
9551 return;
9552 }
9553 pbi->dec_result = DEC_RESULT_NONE;
9554 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9555 "%s: chunk size 0x%x sum 0x%x\n",
9556 __func__, r,
9557 (debug & PRINT_FLAG_VDEC_STATUS) ?
9558 get_data_check_sum(pbi, r) : 0
9559 );
9560
9561 if (debug & PRINT_FLAG_VDEC_DATA)
9562 dump_data(pbi, pbi->chunk->size);
9563
9564 decode_size = pbi->chunk->size +
9565 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9566
9567 WRITE_VREG(HEVC_DECODE_SIZE,
9568 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9569
9570 vdec_enable_input(vdec);
9571
9572 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9573
9574 start_process_time(pbi);
9575
9576 } else{
9577 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9578
9579 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9580 "amvdec_vh265: Insufficient data\n");
9581
9582 vdec_schedule_work(&pbi->work);
9583 }
9584 return;
9585 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9586#ifdef SUPPORT_FB_DECODING
9587 if (pbi->used_stage_buf_num > 0) {
9588#ifndef FB_DECODING_TEST_SCHEDULE
9589 if (!is_s2_decoding_finished(pbi)) {
9590 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9591 "s2 decoding not done, check again later\n");
9592 vdec_schedule_work(&pbi->work);
9593 }
9594#endif
9595 inc_s2_pos(pbi);
9596 if (mcrcc_cache_alg_flag)
9597 dump_hit_rate(pbi);
9598 }
9599#endif
9600 /* if (!pbi->ctx_valid)
9601 pbi->ctx_valid = 1; */
9602 pbi->slice_idx++;
9603 pbi->frame_count++;
9604 pbi->process_state = PROC_STATE_INIT;
9605 decode_frame_count[pbi->index] = pbi->frame_count;
9606
9607 if (pbi->mmu_enable)
9608 pbi->used_4k_num =
9609 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9610 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9611 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9612 __func__,
9613 pbi->frame_count,
9614 pbi->dec_result,
9615 READ_VREG(HEVC_STREAM_LEVEL),
9616 READ_VREG(HEVC_STREAM_WR_PTR),
9617 READ_VREG(HEVC_STREAM_RD_PTR),
9618 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9619 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9620 pbi->start_shift_bytes
9621 );
9622 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9623 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9624 /*
9625 stream base: stream buf empty or timeout
9626 frame base: vdec_prepare_input fail
9627 */
9628 if (!vdec_has_more_input(vdec)) {
9629 pbi->dec_result = DEC_RESULT_EOS;
9630 vdec_schedule_work(&pbi->work);
9631 return;
9632 }
9633 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9634 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9635 "%s: end of stream\n",
9636 __func__);
9637 pbi->eos = 1;
9638 vp9_bufmgr_postproc(pbi);
9639
9640 if (pbi->is_used_v4l)
9641 notify_v4l_eos(hw_to_vdec(pbi));
9642
9643 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9644 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9645 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9646 "%s: force exit\n",
9647 __func__);
9648 if (pbi->stat & STAT_VDEC_RUN) {
9649 amhevc_stop();
9650 pbi->stat &= ~STAT_VDEC_RUN;
9651 }
9652
9653 if (pbi->stat & STAT_ISR_REG) {
9654#ifdef MULTI_INSTANCE_SUPPORT
9655 if (!pbi->m_ins_flag)
9656#endif
9657 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9658 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9659 pbi->stat &= ~STAT_ISR_REG;
9660 }
9661 }
9662 if (pbi->stat & STAT_VDEC_RUN) {
9663 amhevc_stop();
9664 pbi->stat &= ~STAT_VDEC_RUN;
9665 }
9666
9667 if (pbi->stat & STAT_TIMER_ARM) {
9668 del_timer_sync(&pbi->timer);
9669 pbi->stat &= ~STAT_TIMER_ARM;
9670 }
9671 /* mark itself has all HW resource released and input released */
9672#ifdef SUPPORT_FB_DECODING
9673 if (pbi->used_stage_buf_num > 0)
9674 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9675 else
9676 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9677 | CORE_MASK_HEVC
9678 | CORE_MASK_HEVC_FRONT
9679 | CORE_MASK_HEVC_BACK
9680 );
9681#else
9682 if (vdec->parallel_dec == 1)
9683 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9684 else
9685 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9686 | CORE_MASK_HEVC);
9687#endif
9688 trigger_schedule(pbi);
9689}
9690
9691static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9692{
9693 /* new to do ... */
9694#if (!defined SUPPORT_FB_DECODING)
9695 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9696#elif (defined FB_DECODING_TEST_SCHEDULE)
9697 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9698#else
9699 if (pbi->used_stage_buf_num > 0)
9700 vvp9_prot_init(pbi, HW_MASK_FRONT);
9701 else
9702 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9703#endif
9704 return 0;
9705}
9706static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9707{
9708 struct VP9Decoder_s *pbi =
9709 (struct VP9Decoder_s *)vdec->private;
9710 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9711 CODEC_MM_FLAGS_TVP : 0;
9712 unsigned long ret = 0;
9713
9714 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9715 return ret;
9716 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9717 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9718 pbi->first_sc_checked = 1;
9719 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9720 size, (pbi->need_cache_size >> PAGE_SHIFT),
9721 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9722 }
9723
9724#ifdef SUPPORT_FB_DECODING
9725 if (pbi->used_stage_buf_num > 0) {
9726 if (mask & CORE_MASK_HEVC_FRONT) {
9727 if (get_free_stage_buf_num(pbi) > 0
9728 && mv_buf_available(pbi))
9729 ret |= CORE_MASK_HEVC_FRONT;
9730 }
9731 if (mask & CORE_MASK_HEVC_BACK) {
9732 if (s2_buf_available(pbi) &&
9733 (get_free_buf_count(pbi) >=
9734 run_ready_min_buf_num)) {
9735 ret |= CORE_MASK_HEVC_BACK;
9736 pbi->back_not_run_ready = 0;
9737 } else
9738 pbi->back_not_run_ready = 1;
9739#if 0
9740 if (get_free_buf_count(pbi) <
9741 run_ready_min_buf_num)
9742 dump_pic_list(pbi);
9743#endif
9744 }
9745 } else if (get_free_buf_count(pbi) >=
9746 run_ready_min_buf_num)
9747 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9748 | CORE_MASK_HEVC_FRONT
9749 | CORE_MASK_HEVC_BACK;
9750
9751 if (ret & CORE_MASK_HEVC_FRONT)
9752 not_run_ready[pbi->index] = 0;
9753 else
9754 not_run_ready[pbi->index]++;
9755
9756 if (ret & CORE_MASK_HEVC_BACK)
9757 not_run2_ready[pbi->index] = 0;
9758 else
9759 not_run2_ready[pbi->index]++;
9760
9761 vp9_print(pbi,
9762 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9763 __func__, mask, ret,
9764 get_free_stage_buf_num(pbi),
9765 mv_buf_available(pbi),
9766 s2_buf_available(pbi),
9767 get_free_buf_count(pbi)
9768 );
9769
9770 return ret;
9771
9772#else
9773 if (get_free_buf_count(pbi) >=
9774 run_ready_min_buf_num) {
9775 if (vdec->parallel_dec == 1)
9776 ret = CORE_MASK_HEVC;
9777 else
9778 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9779 }
9780
9781 if (pbi->is_used_v4l) {
9782 struct aml_vcodec_ctx *ctx =
9783 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9784
9785 if (ctx->param_sets_from_ucode &&
9786 !ctx->v4l_codec_ready &&
9787 pbi->v4l_params_parsed) {
9788 ret = 0; /*the params has parsed.*/
9789 } else if (!ctx->v4l_codec_dpb_ready)
9790 ret = 0;
9791 }
9792
9793 if (ret)
9794 not_run_ready[pbi->index] = 0;
9795 else
9796 not_run_ready[pbi->index]++;
9797
9798 vp9_print(pbi,
9799 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9800 __func__, mask, ret);
9801 return ret;
9802#endif
9803}
9804
9805static void run_front(struct vdec_s *vdec)
9806{
9807 struct VP9Decoder_s *pbi =
9808 (struct VP9Decoder_s *)vdec->private;
9809 int ret, size;
9810
9811 run_count[pbi->index]++;
9812 /* pbi->chunk = vdec_prepare_input(vdec); */
9813#if (!defined SUPPORT_FB_DECODING)
9814 hevc_reset_core(vdec);
9815#elif (defined FB_DECODING_TEST_SCHEDULE)
9816 hevc_reset_core(vdec);
9817#else
9818 if (pbi->used_stage_buf_num > 0)
9819 fb_reset_core(vdec, HW_MASK_FRONT);
9820 else
9821 hevc_reset_core(vdec);
9822#endif
9823
9824 size = vdec_prepare_input(vdec, &pbi->chunk);
9825 if (size < 0) {
9826 input_empty[pbi->index]++;
9827
9828 pbi->dec_result = DEC_RESULT_AGAIN;
9829
9830 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9831 "ammvdec_vh265: Insufficient data\n");
9832
9833 vdec_schedule_work(&pbi->work);
9834 return;
9835 }
9836
9837 input_empty[pbi->index] = 0;
9838 pbi->dec_result = DEC_RESULT_NONE;
9839 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9840
9841 if (debug & PRINT_FLAG_VDEC_STATUS) {
9842 int ii;
9843 vp9_print(pbi, 0,
9844 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9845 __func__,
9846 pbi->frame_count, size,
9847 pbi->chunk ? pbi->chunk->size : 0,
9848 pbi->chunk ? pbi->chunk->offset : 0,
9849 pbi->chunk ? ((vdec_frame_based(vdec) &&
9850 (debug & PRINT_FLAG_VDEC_STATUS)) ?
9851 get_data_check_sum(pbi, size) : 0) : 0,
9852 READ_VREG(HEVC_STREAM_START_ADDR),
9853 READ_VREG(HEVC_STREAM_END_ADDR),
9854 READ_VREG(HEVC_STREAM_LEVEL),
9855 READ_VREG(HEVC_STREAM_WR_PTR),
9856 READ_VREG(HEVC_STREAM_RD_PTR),
9857 pbi->start_shift_bytes);
9858 if (vdec_frame_based(vdec) && pbi->chunk) {
9859 u8 *data = NULL;
9860
9861 if (!pbi->chunk->block->is_mapped)
9862 data = codec_mm_vmap(pbi->chunk->block->start +
9863 pbi->chunk->offset, 8);
9864 else
9865 data = ((u8 *)pbi->chunk->block->start_virt) +
9866 pbi->chunk->offset;
9867
9868 vp9_print_cont(pbi, 0, "data adr %p:",
9869 data);
9870 for (ii = 0; ii < 8; ii++)
9871 vp9_print_cont(pbi, 0, "%02x ",
9872 data[ii]);
9873
9874 if (!pbi->chunk->block->is_mapped)
9875 codec_mm_unmap_phyaddr(data);
9876 }
9877 vp9_print_cont(pbi, 0, "\r\n");
9878 }
9879 if (vdec->mc_loaded) {
9880 /*firmware have load before,
9881 and not changes to another.
9882 ignore reload.
9883 */
9884 } else {
9885 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9886 if (ret < 0) {
9887 amhevc_disable();
9888 vp9_print(pbi, PRINT_FLAG_ERROR,
9889 "VP9: the %s fw loading failed, err: %x\n",
9890 tee_enabled() ? "TEE" : "local", ret);
9891 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9892 vdec_schedule_work(&pbi->work);
9893 return;
9894 }
9895 vdec->mc_loaded = 1;
9896 vdec->mc_type = VFORMAT_VP9;
9897 }
9898
9899 if (vp9_hw_ctx_restore(pbi) < 0) {
9900 vdec_schedule_work(&pbi->work);
9901 return;
9902 }
9903
9904 vdec_enable_input(vdec);
9905
9906 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9907
9908 if (vdec_frame_based(vdec)) {
9909 if (debug & PRINT_FLAG_VDEC_DATA)
9910 dump_data(pbi, pbi->chunk->size);
9911
9912 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9913 size = pbi->chunk->size +
9914 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9915 }
9916 WRITE_VREG(HEVC_DECODE_SIZE, size);
9917 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9918 pbi->init_flag = 1;
9919
9920 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9921 "%s: start hevc (%x %x %x)\n",
9922 __func__,
9923 READ_VREG(HEVC_DEC_STATUS_REG),
9924 READ_VREG(HEVC_MPC_E),
9925 READ_VREG(HEVC_MPSR));
9926
9927 start_process_time(pbi);
9928 mod_timer(&pbi->timer, jiffies);
9929 pbi->stat |= STAT_TIMER_ARM;
9930 pbi->stat |= STAT_ISR_REG;
9931 amhevc_start();
9932 pbi->stat |= STAT_VDEC_RUN;
9933}
9934
9935#ifdef SUPPORT_FB_DECODING
9936static void mpred_process(struct VP9Decoder_s *pbi)
9937{
9938 union param_u *params = &pbi->s1_param;
9939 unsigned char use_prev_frame_mvs =
9940 !params->p.error_resilient_mode &&
9941 params->p.width == pbi->s1_width &&
9942 params->p.height == pbi->s1_height &&
9943 !pbi->s1_intra_only &&
9944 pbi->s1_last_show_frame &&
9945 (pbi->s1_frame_type != KEY_FRAME);
9946 pbi->s1_width = params->p.width;
9947 pbi->s1_height = params->p.height;
9948 pbi->s1_frame_type = params->p.frame_type;
9949 pbi->s1_intra_only =
9950 (params->p.show_frame ||
9951 params->p.show_existing_frame)
9952 ? 0 : params->p.intra_only;
9953 if ((pbi->s1_frame_type != KEY_FRAME)
9954 && (!pbi->s1_intra_only)) {
9955 unsigned int data32;
9956 int mpred_mv_rd_end_addr;
9957
9958 mpred_mv_rd_end_addr =
9959 pbi->s1_mpred_mv_wr_start_addr_pre
9960 + (pbi->lcu_total * MV_MEM_UNIT);
9961
9962 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
9963 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
9964 pbi->work_space_buf->
9965 mpred_above.buf_start);
9966
9967 data32 = READ_VREG(HEVC_MPRED_CTRL4);
9968
9969 data32 &= (~(1 << 6));
9970 data32 |= (use_prev_frame_mvs << 6);
9971 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
9972
9973 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
9974 pbi->s1_mpred_mv_wr_start_addr);
9975 WRITE_VREG(HEVC_MPRED_MV_WPTR,
9976 pbi->s1_mpred_mv_wr_start_addr);
9977
9978 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
9979 pbi->s1_mpred_mv_wr_start_addr_pre);
9980 WRITE_VREG(HEVC_MPRED_MV_RPTR,
9981 pbi->s1_mpred_mv_wr_start_addr_pre);
9982
9983 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
9984 mpred_mv_rd_end_addr);
9985
9986 } else
9987 clear_mpred_hw(pbi);
9988
9989 if (!params->p.show_existing_frame) {
9990 pbi->s1_mpred_mv_wr_start_addr_pre =
9991 pbi->s1_mpred_mv_wr_start_addr;
9992 pbi->s1_last_show_frame =
9993 params->p.show_frame;
9994 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
9995 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
9996 pbi->s1_mv_buf_index_pre_pre =
9997 pbi->s1_mv_buf_index_pre;
9998 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
9999 } else
10000 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10001}
10002
10003static void vp9_s1_work(struct work_struct *s1_work)
10004{
10005 struct VP9Decoder_s *pbi = container_of(s1_work,
10006 struct VP9Decoder_s, s1_work);
10007 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10008 "%s dec_s1_result %d\n",
10009 __func__,
10010 pbi->dec_s1_result);
10011
10012#ifdef FB_DECODING_TEST_SCHEDULE
10013 if (pbi->dec_s1_result ==
10014 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10015 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10016 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10017 }
10018#endif
10019 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10020 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10021
10022 vdec_core_finish_run(hw_to_vdec(pbi),
10023 CORE_MASK_HEVC_FRONT);
10024
10025 trigger_schedule(pbi);
10026 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10027 }
10028
10029}
10030
10031static void run_back(struct vdec_s *vdec)
10032{
10033 struct VP9Decoder_s *pbi =
10034 (struct VP9Decoder_s *)vdec->private;
10035 int i;
10036 run2_count[pbi->index]++;
10037 if (debug & PRINT_FLAG_VDEC_STATUS) {
10038 vp9_print(pbi, 0,
10039 "%s", __func__);
10040 }
10041 pbi->run2_busy = 1;
10042#ifndef FB_DECODING_TEST_SCHEDULE
10043 fb_reset_core(vdec, HW_MASK_BACK);
10044
10045 vvp9_prot_init(pbi, HW_MASK_BACK);
10046#endif
10047 vp9_recycle_mmu_buf_tail(pbi);
10048
10049 if (pbi->frame_count > 0)
10050 vp9_bufmgr_postproc(pbi);
10051
10052 if (get_s2_buf(pbi) >= 0) {
10053 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10054 int ii;
10055 for (ii = 0; ii < 4; ii++)
10056 vp9_param.l.data[i + ii] =
10057 pbi->s2_buf->rpm[i + 3 - ii];
10058 }
10059#ifndef FB_DECODING_TEST_SCHEDULE
10060 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10061 pbi->stage_mmu_map_phy_addr +
10062 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10063#endif
10064 continue_decoding(pbi);
10065 }
10066 pbi->run2_busy = 0;
10067}
10068#endif
10069
10070static void run(struct vdec_s *vdec, unsigned long mask,
10071 void (*callback)(struct vdec_s *, void *), void *arg)
10072{
10073 struct VP9Decoder_s *pbi =
10074 (struct VP9Decoder_s *)vdec->private;
10075
10076 vp9_print(pbi,
10077 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10078 __func__, mask);
10079
10080 run_count[pbi->index]++;
10081 pbi->vdec_cb_arg = arg;
10082 pbi->vdec_cb = callback;
10083#ifdef SUPPORT_FB_DECODING
10084 if ((mask & CORE_MASK_HEVC) ||
10085 (mask & CORE_MASK_HEVC_FRONT))
10086 run_front(vdec);
10087
10088 if ((pbi->used_stage_buf_num > 0)
10089 && (mask & CORE_MASK_HEVC_BACK))
10090 run_back(vdec);
10091#else
10092 run_front(vdec);
10093#endif
10094}
10095
10096static void init_frame_bufs(struct VP9Decoder_s *pbi)
10097{
10098 struct vdec_s *vdec = hw_to_vdec(pbi);
10099 struct VP9_Common_s *const cm = &pbi->common;
10100 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10101 int i;
10102
10103 for (i = 0; i < pbi->used_buf_num; ++i) {
10104 frame_bufs[i].ref_count = 0;
10105 frame_bufs[i].buf.vf_ref = 0;
10106 frame_bufs[i].buf.decode_idx = 0;
10107 frame_bufs[i].buf.cma_alloc_addr = 0;
10108 frame_bufs[i].buf.index = i;
10109 }
10110
10111 if (vdec->parallel_dec == 1) {
10112 for (i = 0; i < FRAME_BUFFERS; i++) {
10113 vdec->free_canvas_ex
10114 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10115 vdec->id);
10116 vdec->free_canvas_ex
10117 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10118 vdec->id);
10119 }
10120 }
10121}
10122
10123static void reset(struct vdec_s *vdec)
10124{
10125
10126 struct VP9Decoder_s *pbi =
10127 (struct VP9Decoder_s *)vdec->private;
10128
10129 cancel_work_sync(&pbi->work);
10130 if (pbi->stat & STAT_VDEC_RUN) {
10131 amhevc_stop();
10132 pbi->stat &= ~STAT_VDEC_RUN;
10133 }
10134
10135 if (pbi->stat & STAT_TIMER_ARM) {
10136 del_timer_sync(&pbi->timer);
10137 pbi->stat &= ~STAT_TIMER_ARM;
10138 }
10139 pbi->dec_result = DEC_RESULT_NONE;
10140 reset_process_time(pbi);
10141 dealloc_mv_bufs(pbi);
10142 vp9_local_uninit(pbi);
10143 if (vvp9_local_init(pbi) < 0)
10144 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10145 init_frame_bufs(pbi);
10146
10147 pbi->eos = 0;
10148
10149 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10150}
10151
10152static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10153{
10154 struct VP9Decoder_s *pbi =
10155 (struct VP9Decoder_s *)vdec->private;
10156 return vvp9_isr(0, pbi);
10157}
10158
10159static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10160{
10161 struct VP9Decoder_s *pbi =
10162 (struct VP9Decoder_s *)vdec->private;
10163 return vvp9_isr_thread_fn(0, pbi);
10164}
10165
10166static void vp9_dump_state(struct vdec_s *vdec)
10167{
10168 struct VP9Decoder_s *pbi =
10169 (struct VP9Decoder_s *)vdec->private;
10170 struct VP9_Common_s *const cm = &pbi->common;
10171 int i;
10172 vp9_print(pbi, 0, "====== %s\n", __func__);
10173
10174 vp9_print(pbi, 0,
10175 "width/height (%d/%d), used_buf_num %d\n",
10176 cm->width,
10177 cm->height,
10178 pbi->used_buf_num
10179 );
10180
10181 vp9_print(pbi, 0,
10182 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10183 input_frame_based(vdec),
10184 pbi->eos,
10185 pbi->dec_result,
10186 decode_frame_count[pbi->index],
10187 display_frame_count[pbi->index],
10188 run_count[pbi->index],
10189 not_run_ready[pbi->index],
10190 input_empty[pbi->index],
10191 pbi->low_latency_flag,
10192 pbi->no_head
10193 );
10194
10195 if (vf_get_receiver(vdec->vf_provider_name)) {
10196 enum receviver_start_e state =
10197 vf_notify_receiver(vdec->vf_provider_name,
10198 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10199 NULL);
10200 vp9_print(pbi, 0,
10201 "\nreceiver(%s) state %d\n",
10202 vdec->vf_provider_name,
10203 state);
10204 }
10205
10206 vp9_print(pbi, 0,
10207 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10208 __func__,
10209 kfifo_len(&pbi->newframe_q),
10210 VF_POOL_SIZE,
10211 kfifo_len(&pbi->display_q),
10212 VF_POOL_SIZE,
10213 pbi->vf_pre_count,
10214 pbi->vf_get_count,
10215 pbi->vf_put_count,
10216 get_free_buf_count(pbi),
10217 run_ready_min_buf_num
10218 );
10219
10220 dump_pic_list(pbi);
10221
10222 for (i = 0; i < MAX_BUF_NUM; i++) {
10223 vp9_print(pbi, 0,
10224 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10225 i,
10226 pbi->m_mv_BUF[i].start_adr,
10227 pbi->m_mv_BUF[i].size,
10228 pbi->m_mv_BUF[i].used_flag);
10229 }
10230
10231 vp9_print(pbi, 0,
10232 "HEVC_DEC_STATUS_REG=0x%x\n",
10233 READ_VREG(HEVC_DEC_STATUS_REG));
10234 vp9_print(pbi, 0,
10235 "HEVC_MPC_E=0x%x\n",
10236 READ_VREG(HEVC_MPC_E));
10237 vp9_print(pbi, 0,
10238 "DECODE_MODE=0x%x\n",
10239 READ_VREG(DECODE_MODE));
10240 vp9_print(pbi, 0,
10241 "NAL_SEARCH_CTL=0x%x\n",
10242 READ_VREG(NAL_SEARCH_CTL));
10243 vp9_print(pbi, 0,
10244 "HEVC_PARSER_LCU_START=0x%x\n",
10245 READ_VREG(HEVC_PARSER_LCU_START));
10246 vp9_print(pbi, 0,
10247 "HEVC_DECODE_SIZE=0x%x\n",
10248 READ_VREG(HEVC_DECODE_SIZE));
10249 vp9_print(pbi, 0,
10250 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10251 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10252 vp9_print(pbi, 0,
10253 "HEVC_STREAM_START_ADDR=0x%x\n",
10254 READ_VREG(HEVC_STREAM_START_ADDR));
10255 vp9_print(pbi, 0,
10256 "HEVC_STREAM_END_ADDR=0x%x\n",
10257 READ_VREG(HEVC_STREAM_END_ADDR));
10258 vp9_print(pbi, 0,
10259 "HEVC_STREAM_LEVEL=0x%x\n",
10260 READ_VREG(HEVC_STREAM_LEVEL));
10261 vp9_print(pbi, 0,
10262 "HEVC_STREAM_WR_PTR=0x%x\n",
10263 READ_VREG(HEVC_STREAM_WR_PTR));
10264 vp9_print(pbi, 0,
10265 "HEVC_STREAM_RD_PTR=0x%x\n",
10266 READ_VREG(HEVC_STREAM_RD_PTR));
10267 vp9_print(pbi, 0,
10268 "PARSER_VIDEO_RP=0x%x\n",
10269 READ_PARSER_REG(PARSER_VIDEO_RP));
10270 vp9_print(pbi, 0,
10271 "PARSER_VIDEO_WP=0x%x\n",
10272 READ_PARSER_REG(PARSER_VIDEO_WP));
10273
10274 if (input_frame_based(vdec) &&
10275 (debug & PRINT_FLAG_VDEC_DATA)
10276 ) {
10277 int jj;
10278 if (pbi->chunk && pbi->chunk->block &&
10279 pbi->chunk->size > 0) {
10280 u8 *data = NULL;
10281
10282 if (!pbi->chunk->block->is_mapped)
10283 data = codec_mm_vmap(
10284 pbi->chunk->block->start +
10285 pbi->chunk->offset,
10286 pbi->chunk->size);
10287 else
10288 data = ((u8 *)pbi->chunk->block->start_virt)
10289 + pbi->chunk->offset;
10290 vp9_print(pbi, 0,
10291 "frame data size 0x%x\n",
10292 pbi->chunk->size);
10293 for (jj = 0; jj < pbi->chunk->size; jj++) {
10294 if ((jj & 0xf) == 0)
10295 vp9_print(pbi, 0,
10296 "%06x:", jj);
10297 vp9_print_cont(pbi, 0,
10298 "%02x ", data[jj]);
10299 if (((jj + 1) & 0xf) == 0)
10300 vp9_print_cont(pbi, 0,
10301 "\n");
10302 }
10303
10304 if (!pbi->chunk->block->is_mapped)
10305 codec_mm_unmap_phyaddr(data);
10306 }
10307 }
10308
10309}
10310
10311static int ammvdec_vp9_probe(struct platform_device *pdev)
10312{
10313 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10314 int ret;
10315 int config_val;
10316 struct vframe_content_light_level_s content_light_level;
10317 struct vframe_master_display_colour_s vf_dp;
10318
10319 struct BUF_s BUF[MAX_BUF_NUM];
10320 struct VP9Decoder_s *pbi = NULL;
10321 pr_debug("%s\n", __func__);
10322
10323 if (pdata == NULL) {
10324 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10325 return -EFAULT;
10326 }
10327 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10328 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10329 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10330 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10331 if (pbi == NULL) {
10332 pr_info("\nammvdec_vp9 device data allocation failed\n");
10333 return -ENOMEM;
10334 }
10335 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10336
10337 /* the ctx from v4l2 driver. */
10338 pbi->v4l2_ctx = pdata->private;
10339
10340 pdata->private = pbi;
10341 pdata->dec_status = vvp9_dec_status;
10342 /* pdata->set_trickmode = set_trickmode; */
10343 pdata->run_ready = run_ready;
10344 pdata->run = run;
10345 pdata->reset = reset;
10346 pdata->irq_handler = vp9_irq_cb;
10347 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10348 pdata->dump_state = vp9_dump_state;
10349
10350 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10351 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10352
10353 pbi->index = pdev->id;
10354
10355 if (pdata->use_vfm_path)
10356 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10357 VFM_DEC_PROVIDER_NAME);
10358 else
10359 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10360 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10361
10362 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10363 &vvp9_vf_provider, pbi);
10364
10365 pbi->provider_name = pdata->vf_provider_name;
10366 platform_set_drvdata(pdev, pdata);
10367
10368 pbi->platform_dev = pdev;
10369 pbi->video_signal_type = 0;
10370 pbi->m_ins_flag = 1;
10371 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10372 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10373
10374 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10375 pbi->max_pic_w = 8192;
10376 pbi->max_pic_h = 4608;
10377 } else {
10378 pbi->max_pic_w = 4096;
10379 pbi->max_pic_h = 2304;
10380 }
10381#if 1
10382 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10383 pdata->config_len) {
10384#ifdef MULTI_INSTANCE_SUPPORT
10385 int vp9_buf_width = 0;
10386 int vp9_buf_height = 0;
10387 /*use ptr config for doubel_write_mode, etc*/
10388 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10389 if (get_config_int(pdata->config, "vp9_double_write_mode",
10390 &config_val) == 0)
10391 pbi->double_write_mode = config_val;
10392 else
10393 pbi->double_write_mode = double_write_mode;
10394
10395 if (get_config_int(pdata->config, "save_buffer_mode",
10396 &config_val) == 0)
10397 pbi->save_buffer_mode = config_val;
10398 else
10399 pbi->save_buffer_mode = 0;
10400 if (get_config_int(pdata->config, "vp9_buf_width",
10401 &config_val) == 0) {
10402 vp9_buf_width = config_val;
10403 }
10404 if (get_config_int(pdata->config, "vp9_buf_height",
10405 &config_val) == 0) {
10406 vp9_buf_height = config_val;
10407 }
10408
10409 if (get_config_int(pdata->config, "no_head",
10410 &config_val) == 0)
10411 pbi->no_head = config_val;
10412 else
10413 pbi->no_head = no_head;
10414
10415 /*use ptr config for max_pic_w, etc*/
10416 if (get_config_int(pdata->config, "vp9_max_pic_w",
10417 &config_val) == 0) {
10418 pbi->max_pic_w = config_val;
10419 }
10420 if (get_config_int(pdata->config, "vp9_max_pic_h",
10421 &config_val) == 0) {
10422 pbi->max_pic_h = config_val;
10423 }
10424 if ((pbi->max_pic_w * pbi->max_pic_h)
10425 < (vp9_buf_width * vp9_buf_height)) {
10426 pbi->max_pic_w = vp9_buf_width;
10427 pbi->max_pic_h = vp9_buf_height;
10428 vp9_print(pbi, 0, "use buf resolution\n");
10429 }
10430
10431 if (get_config_int(pdata->config,
10432 "parm_v4l_codec_enable",
10433 &config_val) == 0)
10434 pbi->is_used_v4l = config_val;
10435
10436 if (get_config_int(pdata->config,
10437 "parm_v4l_buffer_margin",
10438 &config_val) == 0)
10439 pbi->dynamic_buf_num_margin = config_val;
10440
10441 if (get_config_int(pdata->config,
10442 "parm_v4l_canvas_mem_mode",
10443 &config_val) == 0)
10444 pbi->mem_map_mode = config_val;
10445#endif
10446 if (get_config_int(pdata->config, "HDRStaticInfo",
10447 &vf_dp.present_flag) == 0
10448 && vf_dp.present_flag == 1) {
10449 get_config_int(pdata->config, "mG.x",
10450 &vf_dp.primaries[0][0]);
10451 get_config_int(pdata->config, "mG.y",
10452 &vf_dp.primaries[0][1]);
10453 get_config_int(pdata->config, "mB.x",
10454 &vf_dp.primaries[1][0]);
10455 get_config_int(pdata->config, "mB.y",
10456 &vf_dp.primaries[1][1]);
10457 get_config_int(pdata->config, "mR.x",
10458 &vf_dp.primaries[2][0]);
10459 get_config_int(pdata->config, "mR.y",
10460 &vf_dp.primaries[2][1]);
10461 get_config_int(pdata->config, "mW.x",
10462 &vf_dp.white_point[0]);
10463 get_config_int(pdata->config, "mW.y",
10464 &vf_dp.white_point[1]);
10465 get_config_int(pdata->config, "mMaxDL",
10466 &vf_dp.luminance[0]);
10467 get_config_int(pdata->config, "mMinDL",
10468 &vf_dp.luminance[1]);
10469 vf_dp.content_light_level.present_flag = 1;
10470 get_config_int(pdata->config, "mMaxCLL",
10471 &content_light_level.max_content);
10472 get_config_int(pdata->config, "mMaxFALL",
10473 &content_light_level.max_pic_average);
10474 vf_dp.content_light_level = content_light_level;
10475 pbi->video_signal_type = (1 << 29)
10476 | (5 << 26) /* unspecified */
10477 | (0 << 25) /* limit */
10478 | (1 << 24) /* color available */
10479 | (9 << 16) /* 2020 */
10480 | (16 << 8) /* 2084 */
10481 | (9 << 0); /* 2020 */
10482 }
10483 pbi->vf_dp = vf_dp;
10484 } else
10485#endif
10486 {
10487 /*pbi->vvp9_amstream_dec_info.width = 0;
10488 pbi->vvp9_amstream_dec_info.height = 0;
10489 pbi->vvp9_amstream_dec_info.rate = 30;*/
10490 pbi->double_write_mode = double_write_mode;
10491 }
10492
10493 if (!pbi->is_used_v4l) {
10494 pbi->mem_map_mode = mem_map_mode;
10495 }
10496
10497 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10498 pr_err("over size: %dx%d, probe failed\n",
10499 pbi->max_pic_w, pbi->max_pic_h);
10500 return -1;
10501 }
10502 pbi->mmu_enable = 1;
10503 video_signal_type = pbi->video_signal_type;
10504
10505 if (pdata->sys_info) {
10506 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10507 } else {
10508 pbi->vvp9_amstream_dec_info.width = 0;
10509 pbi->vvp9_amstream_dec_info.height = 0;
10510 pbi->vvp9_amstream_dec_info.rate = 30;
10511 }
10512 pbi->low_latency_flag = 1;
10513
10514 vp9_print(pbi, 0,
10515 "no_head %d low_latency %d\n",
10516 pbi->no_head, pbi->low_latency_flag);
10517#if 0
10518 pbi->buf_start = pdata->mem_start;
10519 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10520#else
10521 if (amvdec_vp9_mmu_init(pbi) < 0) {
10522 pr_err("vp9 alloc bmmu box failed!!\n");
10523 /* devm_kfree(&pdev->dev, (void *)pbi); */
10524 vfree((void *)pbi);
10525 pdata->dec_status = NULL;
10526 return -1;
10527 }
10528
10529 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10530 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10531 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10532 &pbi->cma_alloc_addr);
10533 if (ret < 0) {
10534 uninit_mmu_buffers(pbi);
10535 /* devm_kfree(&pdev->dev, (void *)pbi); */
10536 vfree((void *)pbi);
10537 pdata->dec_status = NULL;
10538 return ret;
10539 }
10540 pbi->buf_start = pbi->cma_alloc_addr;
10541 pbi->buf_size = work_buf_size;
10542#endif
10543
10544 pbi->init_flag = 0;
10545 pbi->first_sc_checked = 0;
10546 pbi->fatal_error = 0;
10547 pbi->show_frame_num = 0;
10548
10549 if (debug) {
10550 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10551 pbi->buf_start,
10552 pbi->buf_size);
10553 }
10554
10555 pbi->cma_dev = pdata->cma_dev;
10556 if (vvp9_init(pdata) < 0) {
10557 pr_info("\namvdec_vp9 init failed.\n");
10558 vp9_local_uninit(pbi);
10559 uninit_mmu_buffers(pbi);
10560 /* devm_kfree(&pdev->dev, (void *)pbi); */
10561 vfree((void *)pbi);
10562 pdata->dec_status = NULL;
10563 return -ENODEV;
10564 }
10565 vdec_set_prepare_level(pdata, start_decode_buf_level);
10566 hevc_source_changed(VFORMAT_VP9,
10567 4096, 2048, 60);
10568#ifdef SUPPORT_FB_DECODING
10569 if (pbi->used_stage_buf_num > 0)
10570 vdec_core_request(pdata,
10571 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10572 else
10573 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10574 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10575 | CORE_MASK_COMBINE);
10576#else
10577 if (pdata->parallel_dec == 1)
10578 vdec_core_request(pdata, CORE_MASK_HEVC);
10579 else
10580 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10581 | CORE_MASK_COMBINE);
10582#endif
10583 pbi->pic_list_init_done2 = true;
10584 return 0;
10585}
10586
10587static int ammvdec_vp9_remove(struct platform_device *pdev)
10588{
10589 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10590 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10591 struct vdec_s *vdec = hw_to_vdec(pbi);
10592 int i;
10593 if (debug)
10594 pr_info("amvdec_vp9_remove\n");
10595
10596 vmvp9_stop(pbi);
10597
10598#ifdef SUPPORT_FB_DECODING
10599 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10600 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10601 );
10602#else
10603 if (vdec->parallel_dec == 1)
10604 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10605 else
10606 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10607#endif
10608 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10609
10610 if (vdec->parallel_dec == 1) {
10611 for (i = 0; i < FRAME_BUFFERS; i++) {
10612 vdec->free_canvas_ex
10613 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10614 vdec->id);
10615 vdec->free_canvas_ex
10616 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10617 vdec->id);
10618 }
10619 }
10620
10621
10622#ifdef DEBUG_PTS
10623 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10624 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10625#endif
10626 mem_map_mode = 0;
10627
10628 /* devm_kfree(&pdev->dev, (void *)pbi); */
10629 vfree((void *)pbi);
10630 return 0;
10631}
10632
10633static struct platform_driver ammvdec_vp9_driver = {
10634 .probe = ammvdec_vp9_probe,
10635 .remove = ammvdec_vp9_remove,
10636 .driver = {
10637 .name = MULTI_DRIVER_NAME,
10638#ifdef CONFIG_PM
10639 .pm = &vp9_pm_ops,
10640#endif
10641 }
10642};
10643#endif
10644static struct mconfig vp9_configs[] = {
10645 MC_PU32("bit_depth_luma", &bit_depth_luma),
10646 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10647 MC_PU32("frame_width", &frame_width),
10648 MC_PU32("frame_height", &frame_height),
10649 MC_PU32("debug", &debug),
10650 MC_PU32("radr", &radr),
10651 MC_PU32("rval", &rval),
10652 MC_PU32("pop_shorts", &pop_shorts),
10653 MC_PU32("dbg_cmd", &dbg_cmd),
10654 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10655 MC_PU32("endian", &endian),
10656 MC_PU32("step", &step),
10657 MC_PU32("udebug_flag", &udebug_flag),
10658 MC_PU32("decode_pic_begin", &decode_pic_begin),
10659 MC_PU32("slice_parse_begin", &slice_parse_begin),
10660 MC_PU32("i_only_flag", &i_only_flag),
10661 MC_PU32("error_handle_policy", &error_handle_policy),
10662 MC_PU32("buf_alloc_width", &buf_alloc_width),
10663 MC_PU32("buf_alloc_height", &buf_alloc_height),
10664 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10665 MC_PU32("buf_alloc_size", &buf_alloc_size),
10666 MC_PU32("buffer_mode", &buffer_mode),
10667 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10668 MC_PU32("max_buf_num", &max_buf_num),
10669 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10670 MC_PU32("mem_map_mode", &mem_map_mode),
10671 MC_PU32("double_write_mode", &double_write_mode),
10672 MC_PU32("enable_mem_saving", &enable_mem_saving),
10673 MC_PU32("force_w_h", &force_w_h),
10674 MC_PU32("force_fps", &force_fps),
10675 MC_PU32("max_decoding_time", &max_decoding_time),
10676 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10677 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10678 MC_PU32("decode_timeout_val", &decode_timeout_val),
10679 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10680 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10681};
10682static struct mconfig_node vp9_node;
10683
10684static int __init amvdec_vp9_driver_init_module(void)
10685{
10686
10687 struct BuffInfo_s *p_buf_info;
10688
10689 if (vdec_is_support_4k()) {
10690 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10691 p_buf_info = &amvvp9_workbuff_spec[2];
10692 else
10693 p_buf_info = &amvvp9_workbuff_spec[1];
10694 } else
10695 p_buf_info = &amvvp9_workbuff_spec[0];
10696
10697 init_buff_spec(NULL, p_buf_info);
10698 work_buf_size =
10699 (p_buf_info->end_adr - p_buf_info->start_adr
10700 + 0xffff) & (~0xffff);
10701
10702 pr_debug("amvdec_vp9 module init\n");
10703
10704 error_handle_policy = 0;
10705
10706#ifdef ERROR_HANDLE_DEBUG
10707 dbg_nal_skip_flag = 0;
10708 dbg_nal_skip_count = 0;
10709#endif
10710 udebug_flag = 0;
10711 decode_pic_begin = 0;
10712 slice_parse_begin = 0;
10713 step = 0;
10714 buf_alloc_size = 0;
10715#ifdef MULTI_INSTANCE_SUPPORT
10716 if (platform_driver_register(&ammvdec_vp9_driver))
10717 pr_err("failed to register ammvdec_vp9 driver\n");
10718
10719#endif
10720 if (platform_driver_register(&amvdec_vp9_driver)) {
10721 pr_err("failed to register amvdec_vp9 driver\n");
10722 return -ENODEV;
10723 }
10724
10725 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10726 amvdec_vp9_profile.profile =
10727 "8k, 10bit, dwrite, compressed, no_head";
10728 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10729 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10730 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10731 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10732 if (vdec_is_support_4k())
10733 amvdec_vp9_profile.profile =
10734 "4k, 10bit, dwrite, compressed";
10735 else
10736 amvdec_vp9_profile.profile =
10737 "10bit, dwrite, compressed";
10738 } else {
10739 if (vdec_is_support_4k())
10740 amvdec_vp9_profile.profile =
10741 "4k, 10bit, dwrite, compressed, no_head";
10742 else
10743 amvdec_vp9_profile.profile =
10744 "10bit, dwrite, compressed, no_head";
10745 }
10746
10747 } else {
10748 amvdec_vp9_profile.name = "vp9_unsupport";
10749 }
10750
10751 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10752 max_buf_num = MAX_BUF_NUM_LESS;
10753
10754 vcodec_profile_register(&amvdec_vp9_profile);
10755 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10756 amvdec_vp9_profile_mult.name = "mvp9";
10757 vcodec_profile_register(&amvdec_vp9_profile_mult);
10758 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10759 "vp9", vp9_configs, CONFIG_FOR_RW);
10760
10761 return 0;
10762}
10763
10764static void __exit amvdec_vp9_driver_remove_module(void)
10765{
10766 pr_debug("amvdec_vp9 module remove.\n");
10767#ifdef MULTI_INSTANCE_SUPPORT
10768 platform_driver_unregister(&ammvdec_vp9_driver);
10769#endif
10770 platform_driver_unregister(&amvdec_vp9_driver);
10771}
10772
10773/****************************************/
10774
10775module_param(bit_depth_luma, uint, 0664);
10776MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10777
10778module_param(bit_depth_chroma, uint, 0664);
10779MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10780
10781module_param(frame_width, uint, 0664);
10782MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10783
10784module_param(frame_height, uint, 0664);
10785MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10786
10787module_param(debug, uint, 0664);
10788MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10789
10790module_param(radr, uint, 0664);
10791MODULE_PARM_DESC(radr, "\n radr\n");
10792
10793module_param(rval, uint, 0664);
10794MODULE_PARM_DESC(rval, "\n rval\n");
10795
10796module_param(pop_shorts, uint, 0664);
10797MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10798
10799module_param(dbg_cmd, uint, 0664);
10800MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10801
10802module_param(dbg_skip_decode_index, uint, 0664);
10803MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10804
10805module_param(endian, uint, 0664);
10806MODULE_PARM_DESC(endian, "\n rval\n");
10807
10808module_param(step, uint, 0664);
10809MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10810
10811module_param(decode_pic_begin, uint, 0664);
10812MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10813
10814module_param(slice_parse_begin, uint, 0664);
10815MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10816
10817module_param(i_only_flag, uint, 0664);
10818MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10819
10820module_param(low_latency_flag, uint, 0664);
10821MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10822
10823module_param(no_head, uint, 0664);
10824MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10825
10826module_param(error_handle_policy, uint, 0664);
10827MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10828
10829module_param(buf_alloc_width, uint, 0664);
10830MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10831
10832module_param(buf_alloc_height, uint, 0664);
10833MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10834
10835module_param(buf_alloc_depth, uint, 0664);
10836MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10837
10838module_param(buf_alloc_size, uint, 0664);
10839MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10840
10841module_param(buffer_mode, uint, 0664);
10842MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10843
10844module_param(buffer_mode_dbg, uint, 0664);
10845MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10846/*USE_BUF_BLOCK*/
10847module_param(max_buf_num, uint, 0664);
10848MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10849
10850module_param(dynamic_buf_num_margin, uint, 0664);
10851MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10852
10853module_param(mv_buf_margin, uint, 0664);
10854MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10855
10856module_param(run_ready_min_buf_num, uint, 0664);
10857MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10858
10859/**/
10860
10861module_param(mem_map_mode, uint, 0664);
10862MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10863
10864#ifdef SUPPORT_10BIT
10865module_param(double_write_mode, uint, 0664);
10866MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10867
10868module_param(enable_mem_saving, uint, 0664);
10869MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10870
10871module_param(force_w_h, uint, 0664);
10872MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10873#endif
10874
10875module_param(force_fps, uint, 0664);
10876MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10877
10878module_param(max_decoding_time, uint, 0664);
10879MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10880
10881module_param(on_no_keyframe_skiped, uint, 0664);
10882MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10883
10884module_param(mcrcc_cache_alg_flag, uint, 0664);
10885MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10886
10887#ifdef MULTI_INSTANCE_SUPPORT
10888module_param(start_decode_buf_level, int, 0664);
10889MODULE_PARM_DESC(start_decode_buf_level,
10890 "\n vp9 start_decode_buf_level\n");
10891
10892module_param(decode_timeout_val, uint, 0664);
10893MODULE_PARM_DESC(decode_timeout_val,
10894 "\n vp9 decode_timeout_val\n");
10895
10896module_param(vp9_max_pic_w, uint, 0664);
10897MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10898
10899module_param(vp9_max_pic_h, uint, 0664);
10900MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10901
10902module_param_array(decode_frame_count, uint,
10903 &max_decode_instance_num, 0664);
10904
10905module_param_array(display_frame_count, uint,
10906 &max_decode_instance_num, 0664);
10907
10908module_param_array(max_process_time, uint,
10909 &max_decode_instance_num, 0664);
10910
10911module_param_array(run_count, uint,
10912 &max_decode_instance_num, 0664);
10913
10914module_param_array(input_empty, uint,
10915 &max_decode_instance_num, 0664);
10916
10917module_param_array(not_run_ready, uint,
10918 &max_decode_instance_num, 0664);
10919#endif
10920
10921#ifdef SUPPORT_FB_DECODING
10922module_param_array(not_run2_ready, uint,
10923 &max_decode_instance_num, 0664);
10924
10925module_param_array(run2_count, uint,
10926 &max_decode_instance_num, 0664);
10927
10928module_param(stage_buf_num, uint, 0664);
10929MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10930#endif
10931
10932module_param(udebug_flag, uint, 0664);
10933MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10934
10935module_param(udebug_pause_pos, uint, 0664);
10936MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10937
10938module_param(udebug_pause_val, uint, 0664);
10939MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10940
10941module_param(udebug_pause_decode_idx, uint, 0664);
10942MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10943
10944module_param(without_display_mode, uint, 0664);
10945MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10946
10947module_init(amvdec_vp9_driver_init_module);
10948module_exit(amvdec_vp9_driver_remove_module);
10949
10950MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
10951MODULE_LICENSE("GPL");
10952
10953
generated by cgit at 2024-05-17 09:55:14 (GMT)