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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: 6db0aa301564b91a721d5df462ffd25ad875b7b2
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../utils/vdec_v4l2_buffer_ops.h"
61#include <media/v4l2-mem2mem.h>
62
63#define MIX_STREAM_SUPPORT
64
65#include "vvp9.h"
66
67
68/*#define SUPPORT_FB_DECODING*/
69/*#define FB_DECODING_TEST_SCHEDULE*/
70
71
72#define HW_MASK_FRONT 0x1
73#define HW_MASK_BACK 0x2
74
75#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
76#define VP9D_MPP_REFINFO_DATA 0x3443
77#define VP9D_MPP_REF_SCALE_ENBL 0x3441
78#define HEVC_MPRED_CTRL4 0x324c
79#define HEVC_CM_HEADER_START_ADDR 0x3628
80#define HEVC_DBLK_CFGB 0x350b
81#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
82#define HEVC_SAO_MMU_VH1_ADDR 0x363b
83#define HEVC_SAO_MMU_VH0_ADDR 0x363a
84
85#define HEVC_MV_INFO 0x310d
86#define HEVC_QP_INFO 0x3137
87#define HEVC_SKIP_INFO 0x3136
88
89#define VP9_10B_DEC_IDLE 0
90#define VP9_10B_DEC_FRAME_HEADER 1
91#define VP9_10B_DEC_SLICE_SEGMENT 2
92#define VP9_10B_DECODE_SLICE 5
93#define VP9_10B_DISCARD_NAL 6
94#define VP9_DUMP_LMEM 7
95#define HEVC_DECPIC_DATA_DONE 0xa
96#define HEVC_DECPIC_DATA_ERROR 0xb
97#define HEVC_NAL_DECODE_DONE 0xe
98#define HEVC_DECODE_BUFEMPTY 0x20
99#define HEVC_DECODE_TIMEOUT 0x21
100#define HEVC_SEARCH_BUFEMPTY 0x22
101#define HEVC_DECODE_OVER_SIZE 0x23
102#define HEVC_S2_DECODING_DONE 0x50
103#define VP9_HEAD_PARSER_DONE 0xf0
104#define VP9_HEAD_SEARCH_DONE 0xf1
105#define VP9_EOS 0xf2
106#define HEVC_ACTION_DONE 0xff
107
108#define VF_POOL_SIZE 32
109
110#undef pr_info
111#define pr_info printk
112
113#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
114#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
115#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
116#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
117#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
118
119#define VP9_TRIGGER_FRAME_DONE 0x100
120#define VP9_TRIGGER_FRAME_ENABLE 0x200
121
122#define MV_MEM_UNIT 0x240
123/*---------------------------------------------------
124 * Include "parser_cmd.h"
125 *---------------------------------------------------
126 */
127#define PARSER_CMD_SKIP_CFG_0 0x0000090b
128
129#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
130
131#define PARSER_CMD_SKIP_CFG_2 0x001b1910
132
133#define PARSER_CMD_NUMBER 37
134
135/*#define HEVC_PIC_STRUCT_SUPPORT*/
136/* to remove, fix build error */
137
138/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
139
140#define MULTI_INSTANCE_SUPPORT
141#define SUPPORT_10BIT
142/* #define ERROR_HANDLE_DEBUG */
143
144#ifndef STAT_KTHREAD
145#define STAT_KTHREAD 0x40
146#endif
147
148#ifdef MULTI_INSTANCE_SUPPORT
149#define MAX_DECODE_INSTANCE_NUM 9
150#define MULTI_DRIVER_NAME "ammvdec_vp9"
151static unsigned int max_decode_instance_num
152 = MAX_DECODE_INSTANCE_NUM;
153static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
154static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
155static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
156static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
157static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
158static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
159
160static u32 decode_timeout_val = 200;
161static int start_decode_buf_level = 0x8000;
162static u32 work_buf_size;
163
164static u32 mv_buf_margin;
165
166/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
167/* double_write_mode:
168 * 0, no double write;
169 * 1, 1:1 ratio;
170 * 2, (1/4):(1/4) ratio;
171 * 3, (1/4):(1/4) ratio, with both compressed frame included
172 * 4, (1/2):(1/2) ratio;
173 * 0x10, double write only
174 * 0x100, if > 1080p,use mode 4,else use mode 1;
175 * 0x200, if > 1080p,use mode 2,else use mode 1;
176 * 0x300, if > 720p, use mode 4, else use mode 1;
177 */
178static u32 double_write_mode;
179
180#define DRIVER_NAME "amvdec_vp9"
181#define MODULE_NAME "amvdec_vp9"
182#define DRIVER_HEADER_NAME "amvdec_vp9_header"
183
184
185#define PUT_INTERVAL (HZ/100)
186#define ERROR_SYSTEM_RESET_COUNT 200
187
188#define PTS_NORMAL 0
189#define PTS_NONE_REF_USE_DURATION 1
190
191#define PTS_MODE_SWITCHING_THRESHOLD 3
192#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
193
194#define DUR2PTS(x) ((x)*90/96)
195
196struct VP9Decoder_s;
197static int vvp9_vf_states(struct vframe_states *states, void *);
198static struct vframe_s *vvp9_vf_peek(void *);
199static struct vframe_s *vvp9_vf_get(void *);
200static void vvp9_vf_put(struct vframe_s *, void *);
201static int vvp9_event_cb(int type, void *data, void *private_data);
202
203static int vvp9_stop(struct VP9Decoder_s *pbi);
204#ifdef MULTI_INSTANCE_SUPPORT
205static s32 vvp9_init(struct vdec_s *vdec);
206#else
207static s32 vvp9_init(struct VP9Decoder_s *pbi);
208#endif
209static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
210static int vvp9_local_init(struct VP9Decoder_s *pbi);
211static void vvp9_put_timer_func(unsigned long arg);
212static void dump_data(struct VP9Decoder_s *pbi, int size);
213static unsigned char get_data_check_sum
214 (struct VP9Decoder_s *pbi, int size);
215static void dump_pic_list(struct VP9Decoder_s *pbi);
216static int vp9_alloc_mmu(
217 struct VP9Decoder_s *pbi,
218 int cur_buf_idx,
219 int pic_width,
220 int pic_height,
221 unsigned short bit_depth,
222 unsigned int *mmu_index_adr);
223
224
225static const char vvp9_dec_id[] = "vvp9-dev";
226
227#define PROVIDER_NAME "decoder.vp9"
228#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
229
230static const struct vframe_operations_s vvp9_vf_provider = {
231 .peek = vvp9_vf_peek,
232 .get = vvp9_vf_get,
233 .put = vvp9_vf_put,
234 .event_cb = vvp9_event_cb,
235 .vf_states = vvp9_vf_states,
236};
237
238static struct vframe_provider_s vvp9_vf_prov;
239
240static u32 bit_depth_luma;
241static u32 bit_depth_chroma;
242static u32 frame_width;
243static u32 frame_height;
244static u32 video_signal_type;
245
246static u32 on_no_keyframe_skiped;
247
248#define PROB_SIZE (496 * 2 * 4)
249#define PROB_BUF_SIZE (0x5000)
250#define COUNT_BUF_SIZE (0x300 * 4 * 4)
251/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
252#define MAX_FRAME_4K_NUM 0x1200
253#define MAX_FRAME_8K_NUM 0x4800
254
255#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
256
257#ifdef SUPPORT_FB_DECODING
258/* register define */
259#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
260#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
261#define HEVC_ASSIST_HED_FB_ADDR 0x3008
262#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
263#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
264
265
266#define MAX_STAGE_PAGE_NUM 0x1200
267#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
268#endif
269static inline int div_r32(int64_t m, int n)
270{
271/*
272 *return (int)(m/n)
273 */
274#ifndef CONFIG_ARM64
275 int64_t qu = 0;
276 qu = div_s64(m, n);
277 return (int)qu;
278#else
279 return (int)(m/n);
280#endif
281}
282
283/*USE_BUF_BLOCK*/
284struct BUF_s {
285 int index;
286 unsigned int alloc_flag;
287 /*buffer */
288 unsigned int cma_page_count;
289 unsigned long alloc_addr;
290 unsigned long start_adr;
291 unsigned int size;
292
293 unsigned int free_start_adr;
294 ulong v4l_ref_buf_addr;
295 ulong header_addr;
296 u32 header_size;
297 u32 luma_size;
298} /*BUF_t */;
299
300struct MVBUF_s {
301 unsigned long start_adr;
302 unsigned int size;
303 int used_flag;
304} /*MVBUF_t */;
305
306 /* #undef BUFMGR_ONLY to enable hardware configuration */
307
308/*#define TEST_WR_PTR_INC*/
309/*#define WR_PTR_INC_NUM 128*/
310#define WR_PTR_INC_NUM 1
311
312#define SIMULATION
313#define DOS_PROJECT
314#undef MEMORY_MAP_IN_REAL_CHIP
315
316/*#undef DOS_PROJECT*/
317/*#define MEMORY_MAP_IN_REAL_CHIP*/
318
319/*#define BUFFER_MGR_ONLY*/
320/*#define CONFIG_HEVC_CLK_FORCED_ON*/
321/*#define ENABLE_SWAP_TEST*/
322#define MCRCC_ENABLE
323
324#define VP9_LPF_LVL_UPDATE
325/*#define DBG_LF_PRINT*/
326
327#ifdef VP9_10B_NV21
328#else
329#define LOSLESS_COMPRESS_MODE
330#endif
331
332#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
333#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
334
335
336
337typedef unsigned int u32;
338typedef unsigned short u16;
339
340#define VP9_DEBUG_BUFMGR 0x01
341#define VP9_DEBUG_BUFMGR_MORE 0x02
342#define VP9_DEBUG_BUFMGR_DETAIL 0x04
343#define VP9_DEBUG_OUT_PTS 0x10
344#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
345#define VP9_DEBUG_MERGE 0x200
346#define VP9_DEBUG_DBG_LF_PRINT 0x400
347#define VP9_DEBUG_REG 0x800
348#define VP9_DEBUG_2_STAGE 0x1000
349#define VP9_DEBUG_2_STAGE_MORE 0x2000
350#define VP9_DEBUG_QOS_INFO 0x4000
351#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
352#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
353#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
354#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
355#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
356#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
357#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
358#define VP9_DEBUG_DUMP_DATA 0x800000
359#define VP9_DEBUG_CACHE 0x1000000
360#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
361#define IGNORE_PARAM_FROM_CONFIG 0x8000000
362#ifdef MULTI_INSTANCE_SUPPORT
363#define PRINT_FLAG_ERROR 0x0
364#define PRINT_FLAG_V4L_DETAIL 0x10000000
365#define PRINT_FLAG_VDEC_STATUS 0x20000000
366#define PRINT_FLAG_VDEC_DETAIL 0x40000000
367#define PRINT_FLAG_VDEC_DATA 0x80000000
368#endif
369
370static u32 debug;
371static bool is_reset;
372/*for debug*/
373/*
374 udebug_flag:
375 bit 0, enable ucode print
376 bit 1, enable ucode detail print
377 bit [31:16] not 0, pos to dump lmem
378 bit 2, pop bits to lmem
379 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
380*/
381static u32 udebug_flag;
382/*
383 when udebug_flag[1:0] is not 0
384 udebug_pause_pos not 0,
385 pause position
386*/
387static u32 udebug_pause_pos;
388/*
389 when udebug_flag[1:0] is not 0
390 and udebug_pause_pos is not 0,
391 pause only when DEBUG_REG2 is equal to this val
392*/
393static u32 udebug_pause_val;
394
395static u32 udebug_pause_decode_idx;
396
397static u32 without_display_mode;
398
399#define DEBUG_REG
400#ifdef DEBUG_REG
401void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
402{
403 if (debug & VP9_DEBUG_REG)
404 pr_info("%s(%x, %x)\n", __func__, adr, val);
405 if (adr != 0)
406 WRITE_VREG(adr, val);
407}
408
409#undef WRITE_VREG
410#define WRITE_VREG WRITE_VREG_DBG2
411#endif
412
413#define FRAME_CNT_WINDOW_SIZE 59
414#define RATE_CORRECTION_THRESHOLD 5
415/**************************************************
416
417VP9 buffer management start
418
419***************************************************/
420
421#define MMU_COMPRESS_HEADER_SIZE 0x48000
422#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
423#define MAX_SIZE_8K (8192 * 4608)
424#define MAX_SIZE_4K (4096 * 2304)
425#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
426
427#define INVALID_IDX -1 /* Invalid buffer index.*/
428
429#define RPM_BEGIN 0x200
430#define RPM_END 0x280
431
432union param_u {
433 struct {
434 unsigned short data[RPM_END - RPM_BEGIN];
435 } l;
436 struct {
437 /* from ucode lmem, do not change this struct */
438 unsigned short profile;
439 unsigned short show_existing_frame;
440 unsigned short frame_to_show_idx;
441 unsigned short frame_type; /*1 bit*/
442 unsigned short show_frame; /*1 bit*/
443 unsigned short error_resilient_mode; /*1 bit*/
444 unsigned short intra_only; /*1 bit*/
445 unsigned short display_size_present; /*1 bit*/
446 unsigned short reset_frame_context;
447 unsigned short refresh_frame_flags;
448 unsigned short width;
449 unsigned short height;
450 unsigned short display_width;
451 unsigned short display_height;
452 /*
453 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
454 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
455 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
456 */
457 unsigned short ref_info;
458 /*
459 *bit[2]: same_frame_size0
460 *bit[1]: same_frame_size1
461 *bit[0]: same_frame_size2
462 */
463 unsigned short same_frame_size;
464
465 unsigned short mode_ref_delta_enabled;
466 unsigned short ref_deltas[4];
467 unsigned short mode_deltas[2];
468 unsigned short filter_level;
469 unsigned short sharpness_level;
470 unsigned short bit_depth;
471 unsigned short seg_quant_info[8];
472 unsigned short seg_enabled;
473 unsigned short seg_abs_delta;
474 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
475 unsigned short seg_lf_info[8];
476 } p;
477};
478
479
480struct vpx_codec_frame_buffer_s {
481 uint8_t *data; /**< Pointer to the data buffer */
482 size_t size; /**< Size of data in bytes */
483 void *priv; /**< Frame's private data */
484};
485
486enum vpx_color_space_t {
487 VPX_CS_UNKNOWN = 0, /**< Unknown */
488 VPX_CS_BT_601 = 1, /**< BT.601 */
489 VPX_CS_BT_709 = 2, /**< BT.709 */
490 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
491 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
492 VPX_CS_BT_2020 = 5, /**< BT.2020 */
493 VPX_CS_RESERVED = 6, /**< Reserved */
494 VPX_CS_SRGB = 7 /**< sRGB */
495}; /**< alias for enum vpx_color_space */
496
497enum vpx_bit_depth_t {
498 VPX_BITS_8 = 8, /**< 8 bits */
499 VPX_BITS_10 = 10, /**< 10 bits */
500 VPX_BITS_12 = 12, /**< 12 bits */
501};
502
503#define MAX_SLICE_NUM 1024
504struct PIC_BUFFER_CONFIG_s {
505 int index;
506 int BUF_index;
507 int mv_buf_index;
508 int comp_body_size;
509 int buf_size;
510 int vf_ref;
511 int y_canvas_index;
512 int uv_canvas_index;
513#ifdef MULTI_INSTANCE_SUPPORT
514 struct canvas_config_s canvas_config[2];
515#endif
516 int decode_idx;
517 int slice_type;
518 int stream_offset;
519 u32 pts;
520 u64 pts64;
521 u64 timestamp;
522 uint8_t error_mark;
523 /**/
524 int slice_idx;
525 /*buffer*/
526 unsigned long header_adr;
527 unsigned long mpred_mv_wr_start_addr;
528 /*unsigned long mc_y_adr;
529 *unsigned long mc_u_v_adr;
530 */
531 unsigned int dw_y_adr;
532 unsigned int dw_u_v_adr;
533 int mc_canvas_y;
534 int mc_canvas_u_v;
535
536 int lcu_total;
537 /**/
538 int y_width;
539 int y_height;
540 int y_crop_width;
541 int y_crop_height;
542 int y_stride;
543
544 int uv_width;
545 int uv_height;
546 int uv_crop_width;
547 int uv_crop_height;
548 int uv_stride;
549
550 int alpha_width;
551 int alpha_height;
552 int alpha_stride;
553
554 uint8_t *y_buffer;
555 uint8_t *u_buffer;
556 uint8_t *v_buffer;
557 uint8_t *alpha_buffer;
558
559 uint8_t *buffer_alloc;
560 int buffer_alloc_sz;
561 int border;
562 int frame_size;
563 int subsampling_x;
564 int subsampling_y;
565 unsigned int bit_depth;
566 enum vpx_color_space_t color_space;
567
568 int corrupted;
569 int flags;
570 unsigned long cma_alloc_addr;
571
572 int double_write_mode;
573
574 /* picture qos infomation*/
575 int max_qp;
576 int avg_qp;
577 int min_qp;
578 int max_skip;
579 int avg_skip;
580 int min_skip;
581 int max_mv;
582 int min_mv;
583 int avg_mv;
584
585 bool vframe_bound;
586} PIC_BUFFER_CONFIG;
587
588enum BITSTREAM_PROFILE {
589 PROFILE_0,
590 PROFILE_1,
591 PROFILE_2,
592 PROFILE_3,
593 MAX_PROFILES
594};
595
596enum FRAME_TYPE {
597 KEY_FRAME = 0,
598 INTER_FRAME = 1,
599 FRAME_TYPES,
600};
601
602enum REFERENCE_MODE {
603 SINGLE_REFERENCE = 0,
604 COMPOUND_REFERENCE = 1,
605 REFERENCE_MODE_SELECT = 2,
606 REFERENCE_MODES = 3,
607};
608
609#define NONE -1
610#define INTRA_FRAME 0
611#define LAST_FRAME 1
612#define GOLDEN_FRAME 2
613#define ALTREF_FRAME 3
614#define MAX_REF_FRAMES 4
615
616#define REFS_PER_FRAME 3
617
618#define REF_FRAMES_LOG2 3
619#define REF_FRAMES (1 << REF_FRAMES_LOG2)
620#define REF_FRAMES_4K (6)
621
622/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
623 *in parallel, 3 for scaled references on the encoder.
624 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
625 * // of framebuffers.
626 *TODO(jkoleszar): These 3 extra references could probably come from the
627 *normal reference pool.
628 */
629#define FRAME_BUFFERS (REF_FRAMES + 16)
630#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
631#define MAX_BUF_NUM (FRAME_BUFFERS)
632#define MV_BUFFER_NUM FRAME_BUFFERS
633#ifdef SUPPORT_FB_DECODING
634#define STAGE_MAX_BUFFERS 16
635#else
636#define STAGE_MAX_BUFFERS 0
637#endif
638
639#define FRAME_CONTEXTS_LOG2 2
640#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
641/*buffer + header buffer + workspace*/
642#ifdef MV_USE_FIXED_BUF
643#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
644#define VF_BUFFER_IDX(n) (n)
645#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
646#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
647#else
648#define MAX_BMMU_BUFFER_NUM \
649 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
650#define VF_BUFFER_IDX(n) (n)
651#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
652#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
653#define WORK_SPACE_BUF_ID \
654 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
655#endif
656
657struct RefCntBuffer_s {
658 int ref_count;
659 /*MV_REF *mvs;*/
660 int mi_rows;
661 int mi_cols;
662 struct vpx_codec_frame_buffer_s raw_frame_buffer;
663 struct PIC_BUFFER_CONFIG_s buf;
664
665/*The Following variables will only be used in frame parallel decode.
666 *
667 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
668 *that no FrameWorker owns, or is decoding, this buffer.
669 *VP9Worker *frame_worker_owner;
670 *
671 *row and col indicate which position frame has been decoded to in real
672 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
673 *when the frame is fully decoded.
674 */
675 int row;
676 int col;
677} RefCntBuffer;
678
679struct RefBuffer_s {
680/*TODO(dkovalev): idx is not really required and should be removed, now it
681 *is used in vp9_onyxd_if.c
682 */
683 int idx;
684 struct PIC_BUFFER_CONFIG_s *buf;
685 /*struct scale_factors sf;*/
686} RefBuffer;
687
688struct InternalFrameBuffer_s {
689 uint8_t *data;
690 size_t size;
691 int in_use;
692} InternalFrameBuffer;
693
694struct InternalFrameBufferList_s {
695 int num_internal_frame_buffers;
696 struct InternalFrameBuffer_s *int_fb;
697} InternalFrameBufferList;
698
699struct BufferPool_s {
700/*Protect BufferPool from being accessed by several FrameWorkers at
701 *the same time during frame parallel decode.
702 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
703 *
704 *Private data associated with the frame buffer callbacks.
705 *void *cb_priv;
706 *
707 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
708 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
709 */
710
711 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
712
713/*Frame buffers allocated internally by the codec.*/
714 struct InternalFrameBufferList_s int_frame_buffers;
715 unsigned long flags;
716 spinlock_t lock;
717
718} BufferPool;
719
720#define lock_buffer_pool(pool, flags) \
721 spin_lock_irqsave(&pool->lock, flags)
722
723#define unlock_buffer_pool(pool, flags) \
724 spin_unlock_irqrestore(&pool->lock, flags)
725
726struct VP9_Common_s {
727 enum vpx_color_space_t color_space;
728 int width;
729 int height;
730 int display_width;
731 int display_height;
732 int last_width;
733 int last_height;
734
735 int subsampling_x;
736 int subsampling_y;
737
738 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
739
740 struct PIC_BUFFER_CONFIG_s *frame_to_show;
741 struct RefCntBuffer_s *prev_frame;
742
743 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
744 struct RefCntBuffer_s *cur_frame;
745
746 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
747
748 /*Prepare ref_frame_map for the next frame.
749 *Only used in frame parallel decode.
750 */
751 int next_ref_frame_map[REF_FRAMES];
752
753 /* TODO(jkoleszar): could expand active_ref_idx to 4,
754 *with 0 as intra, and roll new_fb_idx into it.
755 */
756
757 /*Each frame can reference REFS_PER_FRAME buffers*/
758 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
759
760 int prev_fb_idx;
761 int new_fb_idx;
762 int cur_fb_idx_mmu;
763 /*last frame's frame type for motion search*/
764 enum FRAME_TYPE last_frame_type;
765 enum FRAME_TYPE frame_type;
766
767 int show_frame;
768 int last_show_frame;
769 int show_existing_frame;
770
771 /*Flag signaling that the frame is encoded using only INTRA modes.*/
772 uint8_t intra_only;
773 uint8_t last_intra_only;
774
775 int allow_high_precision_mv;
776
777 /*Flag signaling that the frame context should be reset to default
778 *values. 0 or 1 implies don't reset, 2 reset just the context
779 *specified in the frame header, 3 reset all contexts.
780 */
781 int reset_frame_context;
782
783 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
784 * MODE_INFO (8-pixel) units.
785 */
786 int MBs;
787 int mb_rows, mi_rows;
788 int mb_cols, mi_cols;
789 int mi_stride;
790
791 /*Whether to use previous frame's motion vectors for prediction.*/
792 int use_prev_frame_mvs;
793
794 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
795
796 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
797
798 /*struct loopfilter lf;*/
799 /*struct segmentation seg;*/
800
801 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
802 /* in pbi.*/
803 int frame_parallel_decode; /* frame-based threading.*/
804
805 /*Context probabilities for reference frame prediction*/
806 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
807 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
808 enum REFERENCE_MODE reference_mode;
809
810 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
811 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
812 /*unsigned int frame_context_idx; *//* Context to use/update */
813 /*FRAME_COUNTS counts;*/
814
815 unsigned int current_video_frame;
816 enum BITSTREAM_PROFILE profile;
817
818 enum vpx_bit_depth_t bit_depth;
819
820 int error_resilient_mode;
821 int frame_parallel_decoding_mode;
822
823 int byte_alignment;
824 int skip_loop_filter;
825
826 /*External BufferPool passed from outside.*/
827 struct BufferPool_s *buffer_pool;
828
829 int above_context_alloc_cols;
830
831};
832
833static void set_canvas(struct VP9Decoder_s *pbi,
834 struct PIC_BUFFER_CONFIG_s *pic_config);
835static int prepare_display_buf(struct VP9Decoder_s *pbi,
836 struct PIC_BUFFER_CONFIG_s *pic_config);
837
838static void fill_frame_info(struct VP9Decoder_s *pbi,
839 struct PIC_BUFFER_CONFIG_s *frame,
840 unsigned int framesize,
841 unsigned int pts);
842
843static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
844{
845 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
846}
847
848static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
849{
850 const int ref_index = *idx;
851
852 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
853 bufs[ref_index].ref_count--;
854 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
855 * ref_index, bufs[ref_index].ref_count);
856 */
857 }
858
859 *idx = new_idx;
860
861 bufs[new_idx].ref_count++;
862 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
863 * new_idx, bufs[new_idx].ref_count);
864 */
865}
866
867int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
868{
869 struct InternalFrameBuffer_s *const int_fb =
870 (struct InternalFrameBuffer_s *)fb->priv;
871 if (int_fb)
872 int_fb->in_use = 0;
873 return 0;
874}
875
876static int compute_losless_comp_body_size(int width, int height,
877 uint8_t is_bit_depth_10);
878
879static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
880 int print_header_info)
881{
882 cm->display_width = cm->width;
883 cm->display_height = cm->height;
884 if (params->p.display_size_present) {
885 if (print_header_info)
886 pr_info(" * 1-bit display_size_present read : 1\n");
887 cm->display_width = params->p.display_width;
888 cm->display_height = params->p.display_height;
889 /*vp9_read_frame_size(rb, &cm->display_width,
890 * &cm->display_height);
891 */
892 } else {
893 if (print_header_info)
894 pr_info(" * 1-bit display_size_present read : 0\n");
895 }
896}
897
898
899uint8_t print_header_info = 0;
900
901struct buff_s {
902 u32 buf_start;
903 u32 buf_size;
904 u32 buf_end;
905} buff_t;
906
907struct BuffInfo_s {
908 u32 max_width;
909 u32 max_height;
910 u32 start_adr;
911 u32 end_adr;
912 struct buff_s ipp;
913 struct buff_s sao_abv;
914 struct buff_s sao_vb;
915 struct buff_s short_term_rps;
916 struct buff_s vps;
917 struct buff_s sps;
918 struct buff_s pps;
919 struct buff_s sao_up;
920 struct buff_s swap_buf;
921 struct buff_s swap_buf2;
922 struct buff_s scalelut;
923 struct buff_s dblk_para;
924 struct buff_s dblk_data;
925 struct buff_s seg_map;
926 struct buff_s mmu_vbh;
927 struct buff_s cm_header;
928 struct buff_s mpred_above;
929#ifdef MV_USE_FIXED_BUF
930 struct buff_s mpred_mv;
931#endif
932 struct buff_s rpm;
933 struct buff_s lmem;
934} BuffInfo_t;
935#ifdef MULTI_INSTANCE_SUPPORT
936#define DEC_RESULT_NONE 0
937#define DEC_RESULT_DONE 1
938#define DEC_RESULT_AGAIN 2
939#define DEC_RESULT_CONFIG_PARAM 3
940#define DEC_RESULT_ERROR 4
941#define DEC_INIT_PICLIST 5
942#define DEC_UNINIT_PICLIST 6
943#define DEC_RESULT_GET_DATA 7
944#define DEC_RESULT_GET_DATA_RETRY 8
945#define DEC_RESULT_EOS 9
946#define DEC_RESULT_FORCE_EXIT 10
947#define DEC_V4L2_CONTINUE_DECODING 18
948
949#define DEC_S1_RESULT_NONE 0
950#define DEC_S1_RESULT_DONE 1
951#define DEC_S1_RESULT_FORCE_EXIT 2
952#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
953
954#ifdef FB_DECODING_TEST_SCHEDULE
955#define TEST_SET_NONE 0
956#define TEST_SET_PIC_DONE 1
957#define TEST_SET_S2_DONE 2
958#endif
959
960static void vp9_work(struct work_struct *work);
961#endif
962struct loop_filter_info_n;
963struct loopfilter;
964struct segmentation;
965
966#ifdef SUPPORT_FB_DECODING
967static void mpred_process(struct VP9Decoder_s *pbi);
968static void vp9_s1_work(struct work_struct *work);
969
970struct stage_buf_s {
971 int index;
972 unsigned short rpm[RPM_END - RPM_BEGIN];
973};
974
975static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
976
977static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
978
979#ifdef FB_DECODING_TEST_SCHEDULE
980u32 stage_buf_num; /* = 16;*/
981#else
982u32 stage_buf_num;
983#endif
984#endif
985
986struct VP9Decoder_s {
987#ifdef MULTI_INSTANCE_SUPPORT
988 unsigned char index;
989
990 struct device *cma_dev;
991 struct platform_device *platform_dev;
992 void (*vdec_cb)(struct vdec_s *, void *);
993 void *vdec_cb_arg;
994 struct vframe_chunk_s *chunk;
995 int dec_result;
996 struct work_struct work;
997 struct work_struct set_clk_work;
998 u32 start_shift_bytes;
999
1000 struct BuffInfo_s work_space_buf_store;
1001 unsigned long buf_start;
1002 u32 buf_size;
1003 u32 cma_alloc_count;
1004 unsigned long cma_alloc_addr;
1005 uint8_t eos;
1006 unsigned long int start_process_time;
1007 unsigned last_lcu_idx;
1008 int decode_timeout_count;
1009 unsigned timeout_num;
1010 int save_buffer_mode;
1011
1012 int double_write_mode;
1013#endif
1014 long used_4k_num;
1015
1016 unsigned char m_ins_flag;
1017 char *provider_name;
1018 union param_u param;
1019 int frame_count;
1020 int pic_count;
1021 u32 stat;
1022 struct timer_list timer;
1023 u32 frame_dur;
1024 u32 frame_ar;
1025 int fatal_error;
1026 uint8_t init_flag;
1027 uint8_t first_sc_checked;
1028 uint8_t process_busy;
1029#define PROC_STATE_INIT 0
1030#define PROC_STATE_DECODESLICE 1
1031#define PROC_STATE_SENDAGAIN 2
1032 uint8_t process_state;
1033 u32 ucode_pause_pos;
1034
1035 int show_frame_num;
1036 struct buff_s mc_buf_spec;
1037 struct dec_sysinfo vvp9_amstream_dec_info;
1038 void *rpm_addr;
1039 void *lmem_addr;
1040 dma_addr_t rpm_phy_addr;
1041 dma_addr_t lmem_phy_addr;
1042 unsigned short *lmem_ptr;
1043 unsigned short *debug_ptr;
1044
1045 void *prob_buffer_addr;
1046 void *count_buffer_addr;
1047 dma_addr_t prob_buffer_phy_addr;
1048 dma_addr_t count_buffer_phy_addr;
1049
1050 void *frame_mmu_map_addr;
1051 dma_addr_t frame_mmu_map_phy_addr;
1052
1053 unsigned int use_cma_flag;
1054
1055 struct BUF_s m_BUF[MAX_BUF_NUM];
1056 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1057 u32 used_buf_num;
1058 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1059 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1060 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1061 struct vframe_s vfpool[VF_POOL_SIZE];
1062 u32 vf_pre_count;
1063 u32 vf_get_count;
1064 u32 vf_put_count;
1065 int buf_num;
1066 int pic_num;
1067 int lcu_size_log2;
1068 unsigned int losless_comp_body_size;
1069
1070 u32 video_signal_type;
1071
1072 int pts_mode;
1073 int last_lookup_pts;
1074 int last_pts;
1075 u64 last_lookup_pts_us64;
1076 u64 last_pts_us64;
1077 u64 shift_byte_count;
1078
1079 u32 pts_unstable;
1080 u32 frame_cnt_window;
1081 u32 pts1, pts2;
1082 u32 last_duration;
1083 u32 duration_from_pts_done;
1084 bool vp9_first_pts_ready;
1085
1086 u32 shift_byte_count_lo;
1087 u32 shift_byte_count_hi;
1088 int pts_mode_switching_count;
1089 int pts_mode_recovery_count;
1090
1091 bool get_frame_dur;
1092 u32 saved_resolution;
1093
1094 /**/
1095 struct VP9_Common_s common;
1096 struct RefCntBuffer_s *cur_buf;
1097 int refresh_frame_flags;
1098 uint8_t need_resync;
1099 uint8_t hold_ref_buf;
1100 uint8_t ready_for_new_data;
1101 struct BufferPool_s vp9_buffer_pool;
1102
1103 struct BuffInfo_s *work_space_buf;
1104
1105 struct buff_s *mc_buf;
1106
1107 unsigned int frame_width;
1108 unsigned int frame_height;
1109
1110 unsigned short *rpm_ptr;
1111 int init_pic_w;
1112 int init_pic_h;
1113 int lcu_total;
1114 int lcu_size;
1115
1116 int slice_type;
1117
1118 int skip_flag;
1119 int decode_idx;
1120 int slice_idx;
1121 uint8_t has_keyframe;
1122 uint8_t wait_buf;
1123 uint8_t error_flag;
1124
1125 /* bit 0, for decoding; bit 1, for displaying */
1126 uint8_t ignore_bufmgr_error;
1127 int PB_skip_mode;
1128 int PB_skip_count_after_decoding;
1129 /*hw*/
1130
1131 /*lf*/
1132 int default_filt_lvl;
1133 struct loop_filter_info_n *lfi;
1134 struct loopfilter *lf;
1135 struct segmentation *seg_4lf;
1136 /**/
1137 struct vdec_info *gvs;
1138
1139 u32 pre_stream_offset;
1140
1141 unsigned int dec_status;
1142 u32 last_put_idx;
1143 int new_frame_displayed;
1144 void *mmu_box;
1145 void *bmmu_box;
1146 int mmu_enable;
1147 struct vframe_master_display_colour_s vf_dp;
1148 struct firmware_s *fw;
1149 int max_pic_w;
1150 int max_pic_h;
1151#ifdef SUPPORT_FB_DECODING
1152 int dec_s1_result;
1153 int s1_test_cmd;
1154 struct work_struct s1_work;
1155 int used_stage_buf_num;
1156 int s1_pos;
1157 int s2_pos;
1158 void *stage_mmu_map_addr;
1159 dma_addr_t stage_mmu_map_phy_addr;
1160 struct stage_buf_s *s1_buf;
1161 struct stage_buf_s *s2_buf;
1162 struct stage_buf_s *stage_bufs
1163 [STAGE_MAX_BUFFERS];
1164 unsigned char run2_busy;
1165
1166 int s1_mv_buf_index;
1167 int s1_mv_buf_index_pre;
1168 int s1_mv_buf_index_pre_pre;
1169 unsigned long s1_mpred_mv_wr_start_addr;
1170 unsigned long s1_mpred_mv_wr_start_addr_pre;
1171 unsigned short s1_intra_only;
1172 unsigned short s1_frame_type;
1173 unsigned short s1_width;
1174 unsigned short s1_height;
1175 unsigned short s1_last_show_frame;
1176 union param_u s1_param;
1177 u8 back_not_run_ready;
1178#endif
1179 int need_cache_size;
1180 u64 sc_start_time;
1181 bool postproc_done;
1182 int low_latency_flag;
1183 bool no_head;
1184 bool pic_list_init_done;
1185 bool pic_list_init_done2;
1186 bool is_used_v4l;
1187 void *v4l2_ctx;
1188 bool v4l_params_parsed;
1189 int frameinfo_enable;
1190 struct vframe_qos_s vframe_qos;
1191 u32 mem_map_mode;
1192 u32 dynamic_buf_num_margin;
1193 struct vframe_s vframe_dummy;
1194};
1195
1196static int vp9_print(struct VP9Decoder_s *pbi,
1197 int flag, const char *fmt, ...)
1198{
1199#define HEVC_PRINT_BUF 256
1200 unsigned char buf[HEVC_PRINT_BUF];
1201 int len = 0;
1202
1203 if (pbi == NULL ||
1204 (flag == 0) ||
1205 (debug & flag)) {
1206 va_list args;
1207
1208 va_start(args, fmt);
1209 if (pbi)
1210 len = sprintf(buf, "[%d]", pbi->index);
1211 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1212 pr_debug("%s", buf);
1213 va_end(args);
1214 }
1215 return 0;
1216}
1217
1218static int is_oversize(int w, int h)
1219{
1220 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1221 MAX_SIZE_8K : MAX_SIZE_4K;
1222
1223 if (w <= 0 || h <= 0)
1224 return true;
1225
1226 if (h != 0 && (w > max / h))
1227 return true;
1228
1229 return false;
1230}
1231
1232static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1233 struct PIC_BUFFER_CONFIG_s *pic);
1234
1235static void resize_context_buffers(struct VP9Decoder_s *pbi,
1236 struct VP9_Common_s *cm, int width, int height)
1237{
1238 if (cm->width != width || cm->height != height) {
1239 /* to do ..*/
1240 if (pbi != NULL) {
1241 pbi->vp9_first_pts_ready = 0;
1242 pbi->duration_from_pts_done = 0;
1243 }
1244 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1245 cm->height, width, height);
1246 cm->width = width;
1247 cm->height = height;
1248 }
1249 /*
1250 *if (cm->cur_frame->mvs == NULL ||
1251 * cm->mi_rows > cm->cur_frame->mi_rows ||
1252 * cm->mi_cols > cm->cur_frame->mi_cols) {
1253 * resize_mv_buffer(cm);
1254 *}
1255 */
1256}
1257
1258static int valid_ref_frame_size(int ref_width, int ref_height,
1259 int this_width, int this_height) {
1260 return 2 * this_width >= ref_width &&
1261 2 * this_height >= ref_height &&
1262 this_width <= 16 * ref_width &&
1263 this_height <= 16 * ref_height;
1264}
1265
1266/*
1267 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1268 * int ref_xss, int ref_yss,
1269 * enum vpx_bit_depth_t this_bit_depth,
1270 * int this_xss, int this_yss) {
1271 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1272 * ref_yss == this_yss;
1273 *}
1274 */
1275
1276
1277static int setup_frame_size(
1278 struct VP9Decoder_s *pbi,
1279 struct VP9_Common_s *cm, union param_u *params,
1280 unsigned int *mmu_index_adr,
1281 int print_header_info) {
1282 int width, height;
1283 struct BufferPool_s * const pool = cm->buffer_pool;
1284 struct PIC_BUFFER_CONFIG_s *ybf;
1285 int ret = 0;
1286
1287 width = params->p.width;
1288 height = params->p.height;
1289 if (is_oversize(width, height)) {
1290 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1291 return -1;
1292 }
1293
1294 /*vp9_read_frame_size(rb, &width, &height);*/
1295 if (print_header_info)
1296 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1297 if (print_header_info)
1298 pr_info
1299 (" * 16-bits h read : %d (height : %d)\n", width, height);
1300
1301 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1302#ifdef VP9_10B_HED_FB
1303 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1304#endif
1305 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1306 ret = vp9_alloc_mmu(pbi,
1307 cm->new_fb_idx,
1308 params->p.width,
1309 params->p.height,
1310 params->p.bit_depth,
1311 mmu_index_adr);
1312 if (ret != 0) {
1313 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1314 cm->new_fb_idx,
1315 ret);
1316 return ret;
1317 }
1318 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1319 }
1320
1321 resize_context_buffers(pbi, cm, width, height);
1322 setup_display_size(cm, params, print_header_info);
1323#if 0
1324 lock_buffer_pool(pool);
1325 if (vp9_realloc_frame_buffer(
1326 get_frame_new_buffer(cm), cm->width, cm->height,
1327 cm->subsampling_x, cm->subsampling_y,
1328#if CONFIG_VP9_HIGHBITDEPTH
1329 cm->use_highbitdepth,
1330#endif
1331 VP9_DEC_BORDER_IN_PIXELS,
1332 cm->byte_alignment,
1333 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1334 pool->get_fb_cb, pool->cb_priv)) {
1335 unlock_buffer_pool(pool);
1336 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1337 "Failed to allocate frame buffer");
1338 }
1339 unlock_buffer_pool(pool);
1340#else
1341 /* porting */
1342 ybf = get_frame_new_buffer(cm);
1343 if (!ybf)
1344 return -1;
1345
1346 ybf->y_crop_width = width;
1347 ybf->y_crop_height = height;
1348 ybf->bit_depth = params->p.bit_depth;
1349#endif
1350 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1351 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1352 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1353 (unsigned int)cm->bit_depth;
1354 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1355 return ret;
1356}
1357
1358static int setup_frame_size_with_refs(
1359 struct VP9Decoder_s *pbi,
1360 struct VP9_Common_s *cm,
1361 union param_u *params,
1362 unsigned int *mmu_index_adr,
1363 int print_header_info) {
1364
1365 int width, height;
1366 int found = 0, i;
1367 int has_valid_ref_frame = 0;
1368 struct PIC_BUFFER_CONFIG_s *ybf;
1369 struct BufferPool_s * const pool = cm->buffer_pool;
1370 int ret = 0;
1371
1372 for (i = 0; i < REFS_PER_FRAME; ++i) {
1373 if ((params->p.same_frame_size >>
1374 (REFS_PER_FRAME - i - 1)) & 0x1) {
1375 struct PIC_BUFFER_CONFIG_s *const buf =
1376 cm->frame_refs[i].buf;
1377 /*if (print_header_info)
1378 * pr_info
1379 * ("1-bit same_frame_size[%d] read : 1\n", i);
1380 */
1381 width = buf->y_crop_width;
1382 height = buf->y_crop_height;
1383 /*if (print_header_info)
1384 * pr_info
1385 * (" - same_frame_size width : %d\n", width);
1386 */
1387 /*if (print_header_info)
1388 * pr_info
1389 * (" - same_frame_size height : %d\n", height);
1390 */
1391 found = 1;
1392 break;
1393 } else {
1394 /*if (print_header_info)
1395 * pr_info
1396 * ("1-bit same_frame_size[%d] read : 0\n", i);
1397 */
1398 }
1399 }
1400
1401 if (!found) {
1402 /*vp9_read_frame_size(rb, &width, &height);*/
1403 width = params->p.width;
1404 height = params->p.height;
1405 /*if (print_header_info)
1406 * pr_info
1407 * (" * 16-bits w read : %d (width : %d)\n",
1408 * width, height);
1409 *if (print_header_info)
1410 * pr_info
1411 * (" * 16-bits h read : %d (height : %d)\n",
1412 * width, height);
1413 */
1414 }
1415
1416 if (is_oversize(width, height)) {
1417 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1418 return -1;
1419 }
1420
1421 params->p.width = width;
1422 params->p.height = height;
1423
1424 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1425 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1426 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1427 *cm->prev_fb_idx = cm->new_fb_idx;
1428 */
1429 /* pr_info
1430 * ("[DEBUG DEBUG]Before alloc_mmu,
1431 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1432 * cm->prev_fb_idx, cm->new_fb_idx);
1433 */
1434 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1435 params->p.width, params->p.height,
1436 params->p.bit_depth, mmu_index_adr);
1437 if (ret != 0) {
1438 pr_err("can't alloc need mmu,idx %d\r\n",
1439 cm->new_fb_idx);
1440 return ret;
1441 }
1442 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1443 }
1444
1445 /*Check to make sure at least one of frames that this frame references
1446 *has valid dimensions.
1447 */
1448 for (i = 0; i < REFS_PER_FRAME; ++i) {
1449 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1450
1451 has_valid_ref_frame |=
1452 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1453 ref_frame->buf->y_crop_height,
1454 width, height);
1455 }
1456 if (!has_valid_ref_frame) {
1457 pr_err("Error: Referenced frame has invalid size\r\n");
1458 return -1;
1459 }
1460#if 0
1461 for (i = 0; i < REFS_PER_FRAME; ++i) {
1462 struct RefBuffer_s * const ref_frame =
1463 &cm->frame_refs[i];
1464 if (!valid_ref_frame_img_fmt(
1465 ref_frame->buf->bit_depth,
1466 ref_frame->buf->subsampling_x,
1467 ref_frame->buf->subsampling_y,
1468 cm->bit_depth,
1469 cm->subsampling_x,
1470 cm->subsampling_y))
1471 pr_err
1472 ("Referenced frame incompatible color fmt\r\n");
1473 return -1;
1474 }
1475#endif
1476 resize_context_buffers(pbi, cm, width, height);
1477 setup_display_size(cm, params, print_header_info);
1478
1479#if 0
1480 lock_buffer_pool(pool);
1481 if (vp9_realloc_frame_buffer(
1482 get_frame_new_buffer(cm), cm->width, cm->height,
1483 cm->subsampling_x, cm->subsampling_y,
1484#if CONFIG_VP9_HIGHBITDEPTH
1485 cm->use_highbitdepth,
1486#endif
1487 VP9_DEC_BORDER_IN_PIXELS,
1488 cm->byte_alignment,
1489 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1490 pool->get_fb_cb,
1491 pool->cb_priv)) {
1492 unlock_buffer_pool(pool);
1493 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1494 "Failed to allocate frame buffer");
1495 }
1496 unlock_buffer_pool(pool);
1497#else
1498 /* porting */
1499 ybf = get_frame_new_buffer(cm);
1500 if (!ybf)
1501 return -1;
1502
1503 ybf->y_crop_width = width;
1504 ybf->y_crop_height = height;
1505 ybf->bit_depth = params->p.bit_depth;
1506#endif
1507 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1508 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1509 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1510 (unsigned int)cm->bit_depth;
1511 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1512 return ret;
1513}
1514
1515static inline bool close_to(int a, int b, int m)
1516{
1517 return (abs(a - b) < m) ? true : false;
1518}
1519
1520#ifdef MULTI_INSTANCE_SUPPORT
1521static int vp9_print_cont(struct VP9Decoder_s *pbi,
1522 int flag, const char *fmt, ...)
1523{
1524 unsigned char buf[HEVC_PRINT_BUF];
1525 int len = 0;
1526
1527 if (pbi == NULL ||
1528 (flag == 0) ||
1529 (debug & flag)) {
1530 va_list args;
1531
1532 va_start(args, fmt);
1533 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1534 pr_debug("%s", buf);
1535 va_end(args);
1536 }
1537 return 0;
1538}
1539
1540static void trigger_schedule(struct VP9Decoder_s *pbi)
1541{
1542 if (pbi->is_used_v4l) {
1543 struct aml_vcodec_ctx *ctx =
1544 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1545
1546 if (ctx->param_sets_from_ucode &&
1547 !pbi->v4l_params_parsed)
1548 vdec_v4l_write_frame_sync(ctx);
1549 }
1550
1551 if (pbi->vdec_cb)
1552 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1553}
1554
1555static void reset_process_time(struct VP9Decoder_s *pbi)
1556{
1557 if (pbi->start_process_time) {
1558 unsigned process_time =
1559 1000 * (jiffies - pbi->start_process_time) / HZ;
1560 pbi->start_process_time = 0;
1561 if (process_time > max_process_time[pbi->index])
1562 max_process_time[pbi->index] = process_time;
1563 }
1564}
1565
1566static void start_process_time(struct VP9Decoder_s *pbi)
1567{
1568 pbi->start_process_time = jiffies;
1569 pbi->decode_timeout_count = 0;
1570 pbi->last_lcu_idx = 0;
1571}
1572
1573static void timeout_process(struct VP9Decoder_s *pbi)
1574{
1575 pbi->timeout_num++;
1576 amhevc_stop();
1577 vp9_print(pbi,
1578 0, "%s decoder timeout\n", __func__);
1579
1580 pbi->dec_result = DEC_RESULT_DONE;
1581 reset_process_time(pbi);
1582 vdec_schedule_work(&pbi->work);
1583}
1584
1585static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1586{
1587 return ((double_write_mode & 0x80000000) == 0) ?
1588 pbi->double_write_mode :
1589 (double_write_mode & 0x7fffffff);
1590}
1591
1592static int get_double_write_mode(struct VP9Decoder_s *pbi)
1593{
1594 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1595 u32 dw;
1596 int w, h;
1597 struct VP9_Common_s *cm = &pbi->common;
1598 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1599
1600 /* mask for supporting double write value bigger than 0x100 */
1601 if (valid_dw_mode & 0xffffff00) {
1602 if (!cm->cur_frame)
1603 return 1;/*no valid frame,*/
1604 cur_pic_config = &cm->cur_frame->buf;
1605 w = cur_pic_config->y_crop_width;
1606 h = cur_pic_config->y_crop_height;
1607
1608 dw = 0x1; /*1:1*/
1609 switch (valid_dw_mode) {
1610 case 0x100:
1611 if (w > 1920 && h > 1088)
1612 dw = 0x4; /*1:2*/
1613 break;
1614 case 0x200:
1615 if (w > 1920 && h > 1088)
1616 dw = 0x2; /*1:4*/
1617 break;
1618 case 0x300:
1619 if (w > 1280 && h > 720)
1620 dw = 0x4; /*1:2*/
1621 break;
1622 default:
1623 break;
1624 }
1625 return dw;
1626 }
1627
1628 return valid_dw_mode;
1629}
1630
1631/* for double write buf alloc */
1632static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1633{
1634 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1635 u32 dw;
1636 int w = pbi->init_pic_w;
1637 int h = pbi->init_pic_h;
1638
1639 dw = 0x1; /*1:1*/
1640 switch (valid_dw_mode) {
1641 case 0x100:
1642 if (w > 1920 && h > 1088)
1643 dw = 0x4; /*1:2*/
1644 break;
1645 case 0x200:
1646 if (w > 1920 && h > 1088)
1647 dw = 0x2; /*1:4*/
1648 break;
1649 case 0x300:
1650 if (w > 1280 && h > 720)
1651 dw = 0x4; /*1:2*/
1652 break;
1653 default:
1654 dw = valid_dw_mode;
1655 break;
1656 }
1657 return dw;
1658}
1659#endif
1660
1661static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1662 int dw_mode)
1663{
1664 int ratio = 1;
1665 if ((dw_mode == 2) ||
1666 (dw_mode == 3))
1667 ratio = 4;
1668 else if (dw_mode == 4)
1669 ratio = 2;
1670 return ratio;
1671}
1672
1673//#define MAX_4K_NUM 0x1200
1674
1675int vp9_alloc_mmu(
1676 struct VP9Decoder_s *pbi,
1677 int cur_buf_idx,
1678 int pic_width,
1679 int pic_height,
1680 unsigned short bit_depth,
1681 unsigned int *mmu_index_adr)
1682{
1683 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1684 int picture_size;
1685 int cur_mmu_4k_number, max_frame_num;
1686 if (!pbi->mmu_box) {
1687 pr_err("error no mmu box!\n");
1688 return -1;
1689 }
1690 if (pbi->double_write_mode & 0x10)
1691 return 0;
1692 if (bit_depth >= VPX_BITS_12) {
1693 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1694 pr_err("fatal_error, un support bit depth 12!\n\n");
1695 return -1;
1696 }
1697 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1698 bit_depth_10);
1699 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1700
1701 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1702 max_frame_num = MAX_FRAME_8K_NUM;
1703 else
1704 max_frame_num = MAX_FRAME_4K_NUM;
1705
1706 if (cur_mmu_4k_number > max_frame_num) {
1707 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1708 cur_mmu_4k_number, pic_width, pic_height);
1709 return -1;
1710 }
1711 return decoder_mmu_box_alloc_idx(
1712 pbi->mmu_box,
1713 cur_buf_idx,
1714 cur_mmu_4k_number,
1715 mmu_index_adr);
1716}
1717
1718
1719#ifndef MV_USE_FIXED_BUF
1720static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1721{
1722 int i;
1723 for (i = 0; i < MV_BUFFER_NUM; i++) {
1724 if (pbi->m_mv_BUF[i].start_adr) {
1725 if (debug)
1726 pr_info(
1727 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1728 i, pbi->m_mv_BUF[i].start_adr,
1729 pbi->m_mv_BUF[i].size,
1730 pbi->m_mv_BUF[i].used_flag);
1731 decoder_bmmu_box_free_idx(
1732 pbi->bmmu_box,
1733 MV_BUFFER_IDX(i));
1734 pbi->m_mv_BUF[i].start_adr = 0;
1735 pbi->m_mv_BUF[i].size = 0;
1736 pbi->m_mv_BUF[i].used_flag = 0;
1737 }
1738 }
1739}
1740
1741static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1742 int i, int size)
1743{
1744 int ret = 0;
1745
1746 if (pbi->m_mv_BUF[i].start_adr &&
1747 size > pbi->m_mv_BUF[i].size) {
1748 dealloc_mv_bufs(pbi);
1749 } else if (pbi->m_mv_BUF[i].start_adr)
1750 return 0;
1751
1752 if (decoder_bmmu_box_alloc_buf_phy
1753 (pbi->bmmu_box,
1754 MV_BUFFER_IDX(i), size,
1755 DRIVER_NAME,
1756 &pbi->m_mv_BUF[i].start_adr) < 0) {
1757 pbi->m_mv_BUF[i].start_adr = 0;
1758 ret = -1;
1759 } else {
1760 pbi->m_mv_BUF[i].size = size;
1761 pbi->m_mv_BUF[i].used_flag = 0;
1762 ret = 0;
1763 if (debug) {
1764 pr_info(
1765 "MV Buffer %d: start_adr %p size %x\n",
1766 i,
1767 (void *)pbi->m_mv_BUF[i].start_adr,
1768 pbi->m_mv_BUF[i].size);
1769 }
1770 }
1771 return ret;
1772}
1773
1774static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1775{
1776 int i;
1777 int ret = 0;
1778 int count = MV_BUFFER_NUM;
1779 int pic_width = pbi->init_pic_w;
1780 int pic_height = pbi->init_pic_h;
1781 int lcu_size = 64; /*fixed 64*/
1782 int pic_width_64 = (pic_width + 63) & (~0x3f);
1783 int pic_height_32 = (pic_height + 31) & (~0x1f);
1784 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1785 pic_width_64 / lcu_size + 1
1786 : pic_width_64 / lcu_size;
1787 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1788 pic_height_32 / lcu_size + 1
1789 : pic_height_32 / lcu_size;
1790 int lcu_total = pic_width_lcu * pic_height_lcu;
1791 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1792 (~0xffff);
1793 if (mv_buf_margin > 0)
1794 count = REF_FRAMES + mv_buf_margin;
1795
1796 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1797 count = REF_FRAMES_4K + mv_buf_margin;
1798
1799 if (debug) {
1800 pr_info("%s w:%d, h:%d, count: %d\n",
1801 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1802 }
1803
1804 for (i = 0;
1805 i < count && i < MV_BUFFER_NUM; i++) {
1806 if (alloc_mv_buf(pbi, i, size) < 0) {
1807 ret = -1;
1808 break;
1809 }
1810 }
1811 return ret;
1812}
1813
1814static int get_mv_buf(struct VP9Decoder_s *pbi,
1815 int *mv_buf_index,
1816 unsigned long *mpred_mv_wr_start_addr)
1817{
1818 int i;
1819 int ret = -1;
1820 for (i = 0; i < MV_BUFFER_NUM; i++) {
1821 if (pbi->m_mv_BUF[i].start_adr &&
1822 pbi->m_mv_BUF[i].used_flag == 0) {
1823 pbi->m_mv_BUF[i].used_flag = 1;
1824 ret = i;
1825 break;
1826 }
1827 }
1828
1829 if (ret >= 0) {
1830 *mv_buf_index = ret;
1831 *mpred_mv_wr_start_addr =
1832 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1833 (~0xffff);
1834 if (debug & VP9_DEBUG_BUFMGR_MORE)
1835 pr_info(
1836 "%s => %d (%ld) size 0x%x\n",
1837 __func__, ret,
1838 *mpred_mv_wr_start_addr,
1839 pbi->m_mv_BUF[ret].size);
1840 } else {
1841 pr_info(
1842 "%s: Error, mv buf is not enough\n",
1843 __func__);
1844 }
1845 return ret;
1846}
1847
1848static void put_mv_buf(struct VP9Decoder_s *pbi,
1849 int *mv_buf_index)
1850{
1851 int i = *mv_buf_index;
1852 if (i >= MV_BUFFER_NUM) {
1853 if (debug & VP9_DEBUG_BUFMGR_MORE)
1854 pr_info(
1855 "%s: index %d beyond range\n",
1856 __func__, i);
1857 return;
1858 }
1859 if (debug & VP9_DEBUG_BUFMGR_MORE)
1860 pr_info(
1861 "%s(%d): used_flag(%d)\n",
1862 __func__, i,
1863 pbi->m_mv_BUF[i].used_flag);
1864
1865 *mv_buf_index = -1;
1866 if (pbi->m_mv_BUF[i].start_adr &&
1867 pbi->m_mv_BUF[i].used_flag)
1868 pbi->m_mv_BUF[i].used_flag = 0;
1869}
1870
1871static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1872{
1873 struct VP9_Common_s *const cm = &pbi->common;
1874 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1875 int i;
1876 for (i = 0; i < pbi->used_buf_num; ++i) {
1877 if ((frame_bufs[i].ref_count == 0) &&
1878 (frame_bufs[i].buf.index != -1) &&
1879 (frame_bufs[i].buf.mv_buf_index >= 0)
1880 )
1881 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1882 }
1883}
1884
1885#ifdef SUPPORT_FB_DECODING
1886static bool mv_buf_available(struct VP9Decoder_s *pbi)
1887{
1888 int i;
1889 bool ret = 0;
1890 for (i = 0; i < MV_BUFFER_NUM; i++) {
1891 if (pbi->m_mv_BUF[i].start_adr &&
1892 pbi->m_mv_BUF[i].used_flag == 0) {
1893 ret = 1;
1894 break;
1895 }
1896 }
1897 return ret;
1898}
1899#endif
1900#endif
1901
1902#ifdef SUPPORT_FB_DECODING
1903static void init_stage_buf(struct VP9Decoder_s *pbi)
1904{
1905 uint i;
1906 for (i = 0; i < STAGE_MAX_BUFFERS
1907 && i < stage_buf_num; i++) {
1908 pbi->stage_bufs[i] =
1909 vmalloc(sizeof(struct stage_buf_s));
1910 if (pbi->stage_bufs[i] == NULL) {
1911 vp9_print(pbi,
1912 0, "%s vmalloc fail\n", __func__);
1913 break;
1914 }
1915 pbi->stage_bufs[i]->index = i;
1916 }
1917 pbi->used_stage_buf_num = i;
1918 pbi->s1_pos = 0;
1919 pbi->s2_pos = 0;
1920 pbi->s1_buf = NULL;
1921 pbi->s2_buf = NULL;
1922 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1923 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1924 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1925
1926 if (pbi->used_stage_buf_num > 0)
1927 vp9_print(pbi,
1928 0, "%s 2 stage decoding buf %d\n",
1929 __func__,
1930 pbi->used_stage_buf_num);
1931}
1932
1933static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1934{
1935 int i;
1936 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1937 if (pbi->stage_bufs[i])
1938 vfree(pbi->stage_bufs[i]);
1939 pbi->stage_bufs[i] = NULL;
1940 }
1941 pbi->used_stage_buf_num = 0;
1942 pbi->s1_pos = 0;
1943 pbi->s2_pos = 0;
1944 pbi->s1_buf = NULL;
1945 pbi->s2_buf = NULL;
1946}
1947
1948static int get_s1_buf(
1949 struct VP9Decoder_s *pbi)
1950{
1951 struct stage_buf_s *buf = NULL;
1952 int ret = -1;
1953 int buf_page_num = MAX_STAGE_PAGE_NUM;
1954 int next_s1_pos = pbi->s1_pos + 1;
1955
1956 if (next_s1_pos >= pbi->used_stage_buf_num)
1957 next_s1_pos = 0;
1958 if (next_s1_pos == pbi->s2_pos) {
1959 pbi->s1_buf = NULL;
1960 return ret;
1961 }
1962
1963 buf = pbi->stage_bufs[pbi->s1_pos];
1964 ret = decoder_mmu_box_alloc_idx(
1965 pbi->mmu_box,
1966 buf->index,
1967 buf_page_num,
1968 pbi->stage_mmu_map_addr);
1969 if (ret < 0) {
1970 vp9_print(pbi, 0,
1971 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1972 __func__, buf->index,
1973 pbi->s1_pos, pbi->s2_pos);
1974 buf = NULL;
1975 } else {
1976 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1977 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1978 __func__, buf_page_num, buf->index,
1979 pbi->s1_pos, pbi->s2_pos);
1980 }
1981 pbi->s1_buf = buf;
1982 return ret;
1983}
1984
1985static void inc_s1_pos(struct VP9Decoder_s *pbi)
1986{
1987 struct stage_buf_s *buf =
1988 pbi->stage_bufs[pbi->s1_pos];
1989
1990 int used_page_num =
1991#ifdef FB_DECODING_TEST_SCHEDULE
1992 MAX_STAGE_PAGE_NUM/2;
1993#else
1994 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
1995#endif
1996 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
1997 FRAME_BUFFERS + buf->index, used_page_num);
1998
1999 pbi->s1_pos++;
2000 if (pbi->s1_pos >= pbi->used_stage_buf_num)
2001 pbi->s1_pos = 0;
2002
2003 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2004 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2005 __func__, used_page_num, buf->index,
2006 pbi->s1_pos, pbi->s2_pos);
2007}
2008
2009#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2010
2011static int get_s2_buf(
2012 struct VP9Decoder_s *pbi)
2013{
2014 int ret = -1;
2015 struct stage_buf_s *buf = NULL;
2016 if (s2_buf_available(pbi)) {
2017 buf = pbi->stage_bufs[pbi->s2_pos];
2018 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2019 "%s for index %d (s1_pos %d s2_pos %d)\n",
2020 __func__, buf->index,
2021 pbi->s1_pos, pbi->s2_pos);
2022 pbi->s2_buf = buf;
2023 ret = 0;
2024 }
2025 return ret;
2026}
2027
2028static void inc_s2_pos(struct VP9Decoder_s *pbi)
2029{
2030 struct stage_buf_s *buf =
2031 pbi->stage_bufs[pbi->s2_pos];
2032 decoder_mmu_box_free_idx(pbi->mmu_box,
2033 FRAME_BUFFERS + buf->index);
2034 pbi->s2_pos++;
2035 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2036 pbi->s2_pos = 0;
2037 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2038 "%s for index %d (s1_pos %d s2_pos %d)\n",
2039 __func__, buf->index,
2040 pbi->s1_pos, pbi->s2_pos);
2041}
2042
2043static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2044{
2045 int num;
2046 if (pbi->s1_pos >= pbi->s2_pos)
2047 num = pbi->used_stage_buf_num -
2048 (pbi->s1_pos - pbi->s2_pos) - 1;
2049 else
2050 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2051 return num;
2052}
2053
2054#ifndef FB_DECODING_TEST_SCHEDULE
2055static DEFINE_SPINLOCK(fb_core_spin_lock);
2056
2057static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2058{
2059 /* to do: VLSI review
2060 completion of last LCU decoding in BACK
2061 */
2062 return 1;
2063}
2064
2065static void start_s1_decoding(struct VP9Decoder_s *pbi)
2066{
2067 /* to do: VLSI review
2068 after parser, how to start LCU decoding in BACK
2069 */
2070}
2071
2072static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2073{
2074 /* to do: VLSI review
2075 1. how to disconnect DMC for FRONT and BACK
2076 2. reset bit 13, 24, FRONT or BACK ??
2077 */
2078
2079 unsigned long flags;
2080 u32 reset_bits = 0;
2081 if (mask & HW_MASK_FRONT)
2082 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2083 spin_lock_irqsave(&fb_core_spin_lock, flags);
2084 codec_dmcbus_write(DMC_REQ_CTRL,
2085 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2086 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2087
2088 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2089 & (1 << 4)))
2090 ;
2091
2092 if ((mask & HW_MASK_FRONT) &&
2093 input_frame_based(vdec))
2094 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2095
2096 /*
2097 * 2: assist
2098 * 3: parser
2099 * 4: parser_state
2100 * 8: dblk
2101 * 11:mcpu
2102 * 12:ccpu
2103 * 13:ddr
2104 * 14:iqit
2105 * 15:ipp
2106 * 17:qdct
2107 * 18:mpred
2108 * 19:sao
2109 * 24:hevc_afifo
2110 */
2111 if (mask & HW_MASK_FRONT) {
2112 reset_bits =
2113 (1<<3)|(1<<4)|(1<<11)|
2114 (1<<12)|(1<<18);
2115 }
2116 if (mask & HW_MASK_BACK) {
2117 reset_bits =
2118 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2119 (1<<17)|(1<<19)|(1<<24);
2120 }
2121 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2122#if 0
2123 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2124 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2125 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2126#endif
2127 WRITE_VREG(DOS_SW_RESET3, 0);
2128
2129
2130 spin_lock_irqsave(&fb_core_spin_lock, flags);
2131 codec_dmcbus_write(DMC_REQ_CTRL,
2132 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2133 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2134
2135}
2136#endif
2137
2138#endif
2139
2140static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2141
2142static int get_free_fb(struct VP9Decoder_s *pbi)
2143{
2144 struct VP9_Common_s *const cm = &pbi->common;
2145 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2146 int i;
2147 unsigned long flags;
2148
2149 lock_buffer_pool(cm->buffer_pool, flags);
2150 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2151 for (i = 0; i < pbi->used_buf_num; ++i) {
2152 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2153 __func__, i, frame_bufs[i].ref_count,
2154 frame_bufs[i].buf.vf_ref,
2155 frame_bufs[i].buf.index);
2156 }
2157 }
2158 for (i = 0; i < pbi->used_buf_num; ++i) {
2159 if ((frame_bufs[i].ref_count == 0) &&
2160 (frame_bufs[i].buf.vf_ref == 0) &&
2161 (frame_bufs[i].buf.index != -1)
2162 )
2163 break;
2164 }
2165 if (i != pbi->used_buf_num) {
2166 frame_bufs[i].ref_count = 1;
2167 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2168 i, frame_bufs[i].ref_count);*/
2169 } else {
2170 /* Reset i to be INVALID_IDX to indicate
2171 no free buffer found*/
2172 i = INVALID_IDX;
2173 }
2174
2175 unlock_buffer_pool(cm->buffer_pool, flags);
2176 return i;
2177}
2178
2179static int v4l_get_free_fb(struct VP9Decoder_s *pbi)
2180{
2181 struct VP9_Common_s *const cm = &pbi->common;
2182 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2183 struct aml_vcodec_ctx * v4l = pbi->v4l2_ctx;
2184 struct v4l_buff_pool *pool = &v4l->cap_pool;
2185 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2186 int i, idx = INVALID_IDX;
2187 ulong flags;
2188
2189 lock_buffer_pool(cm->buffer_pool, flags);
2190
2191 for (i = 0; i < pool->in; ++i) {
2192 u32 state = (pool->seq[i] >> 16);
2193 u32 index = (pool->seq[i] & 0xffff);
2194
2195 switch (state) {
2196 case V4L_CAP_BUFF_IN_DEC:
2197 pic = &frame_bufs[i].buf;
2198 if ((frame_bufs[i].ref_count == 0) &&
2199 (pic->vf_ref == 0) &&
2200 (pic->index != -1) &&
2201 pic->cma_alloc_addr) {
2202 idx = i;
2203 }
2204 break;
2205 case V4L_CAP_BUFF_IN_M2M:
2206 pic = &frame_bufs[index].buf;
2207 pic->y_crop_width = pbi->frame_width;
2208 pic->y_crop_height = pbi->frame_height;
2209 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2210 set_canvas(pbi, pic);
2211 init_pic_list_hw(pbi);
2212 idx = index;
2213 }
2214 break;
2215 default:
2216 pr_err("v4l buffer state err %d.\n", state);
2217 break;
2218 }
2219
2220 if (idx != INVALID_IDX) {
2221 frame_bufs[idx].ref_count = 1;
2222 break;
2223 }
2224 }
2225
2226 unlock_buffer_pool(cm->buffer_pool, flags);
2227
2228 return idx;
2229}
2230
2231static int get_free_buf_count(struct VP9Decoder_s *pbi)
2232{
2233 struct VP9_Common_s *const cm = &pbi->common;
2234 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2235 int i;
2236 int free_buf_count = 0;
2237 for (i = 0; i < pbi->used_buf_num; ++i)
2238 if ((frame_bufs[i].ref_count == 0) &&
2239 (frame_bufs[i].buf.vf_ref == 0) &&
2240 (frame_bufs[i].buf.index != -1)
2241 )
2242 free_buf_count++;
2243 return free_buf_count;
2244}
2245
2246static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2247 struct BufferPool_s *const pool)
2248{
2249 if (idx >= 0) {
2250 --frame_bufs[idx].ref_count;
2251 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2252 * frame_bufs[idx].ref_count);
2253 */
2254 /*A worker may only get a free framebuffer index when
2255 *calling get_free_fb. But the private buffer is not set up
2256 *until finish decoding header. So any error happens during
2257 *decoding header, the frame_bufs will not have valid priv
2258 *buffer.
2259 */
2260
2261 if (frame_bufs[idx].ref_count == 0 &&
2262 frame_bufs[idx].raw_frame_buffer.priv)
2263 vp9_release_frame_buffer
2264 (&frame_bufs[idx].raw_frame_buffer);
2265 }
2266}
2267
2268static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2269{
2270 struct VP9_Common_s *const cm = &pbi->common;
2271 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2272 struct BufferPool_s *const pool = cm->buffer_pool;
2273 int mask, ref_index = 0;
2274 unsigned long flags;
2275
2276 /* Generate next_ref_frame_map.*/
2277 lock_buffer_pool(pool, flags);
2278 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2279 if (mask & 1) {
2280 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2281 ++frame_bufs[cm->new_fb_idx].ref_count;
2282 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2283 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2284 */
2285 } else
2286 cm->next_ref_frame_map[ref_index] =
2287 cm->ref_frame_map[ref_index];
2288 /* Current thread holds the reference frame.*/
2289 if (cm->ref_frame_map[ref_index] >= 0) {
2290 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2291 /*pr_info
2292 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2293 *cm->ref_frame_map[ref_index],
2294 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2295 */
2296 }
2297 ++ref_index;
2298 }
2299
2300 for (; ref_index < REF_FRAMES; ++ref_index) {
2301 cm->next_ref_frame_map[ref_index] =
2302 cm->ref_frame_map[ref_index];
2303 /* Current thread holds the reference frame.*/
2304 if (cm->ref_frame_map[ref_index] >= 0) {
2305 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2306 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2307 *cm->ref_frame_map[ref_index],
2308 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2309 */
2310 }
2311 }
2312 unlock_buffer_pool(pool, flags);
2313 return;
2314}
2315
2316static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2317
2318{
2319 struct VP9_Common_s *const cm = &pbi->common;
2320 struct BufferPool_s *pool = cm->buffer_pool;
2321 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2322 int mask, ref_index = 0;
2323 unsigned long flags;
2324
2325 lock_buffer_pool(pool, flags);
2326 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2327 const int old_idx = cm->ref_frame_map[ref_index];
2328 /*Current thread releases the holding of reference frame.*/
2329 decrease_ref_count(old_idx, frame_bufs, pool);
2330
2331 /*Release the reference frame in reference map.*/
2332 if ((mask & 1) && old_idx >= 0)
2333 decrease_ref_count(old_idx, frame_bufs, pool);
2334 cm->ref_frame_map[ref_index] =
2335 cm->next_ref_frame_map[ref_index];
2336 ++ref_index;
2337 }
2338
2339 /*Current thread releases the holding of reference frame.*/
2340 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2341 ++ref_index) {
2342 const int old_idx = cm->ref_frame_map[ref_index];
2343
2344 decrease_ref_count(old_idx, frame_bufs, pool);
2345 cm->ref_frame_map[ref_index] =
2346 cm->next_ref_frame_map[ref_index];
2347 }
2348 unlock_buffer_pool(pool, flags);
2349 return;
2350}
2351
2352int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2353{
2354 struct VP9_Common_s *const cm = &pbi->common;
2355 struct BufferPool_s *pool = cm->buffer_pool;
2356 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2357 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2358 int i;
2359 int ret;
2360
2361 pbi->ready_for_new_data = 0;
2362
2363 if (pbi->has_keyframe == 0 &&
2364 params->p.frame_type != KEY_FRAME){
2365 on_no_keyframe_skiped++;
2366 return -2;
2367 }
2368 pbi->has_keyframe = 1;
2369 on_no_keyframe_skiped = 0;
2370#if 0
2371 if (pbi->mmu_enable) {
2372 if (!pbi->m_ins_flag)
2373 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2374 if (cm->prev_fb_idx >= 0) {
2375 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2376 cm->prev_fb_idx, pbi->used_4k_num);
2377 }
2378 }
2379#endif
2380 if (cm->new_fb_idx >= 0
2381 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2382 vp9_release_frame_buffer
2383 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2384 }
2385 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2386 cm->prev_fb_idx, cm->new_fb_idx);*/
2387#ifndef MV_USE_FIXED_BUF
2388 put_un_used_mv_bufs(pbi);
2389 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2390 dump_pic_list(pbi);
2391#endif
2392 cm->new_fb_idx = pbi->is_used_v4l ?
2393 v4l_get_free_fb(pbi) :
2394 get_free_fb(pbi);
2395 if (cm->new_fb_idx == INVALID_IDX) {
2396 pr_info("get_free_fb error\r\n");
2397 return -1;
2398 }
2399#ifndef MV_USE_FIXED_BUF
2400#ifdef SUPPORT_FB_DECODING
2401 if (pbi->used_stage_buf_num == 0) {
2402#endif
2403 if (get_mv_buf(pbi,
2404 &pool->frame_bufs[cm->new_fb_idx].
2405 buf.mv_buf_index,
2406 &pool->frame_bufs[cm->new_fb_idx].
2407 buf.mpred_mv_wr_start_addr
2408 ) < 0) {
2409 pr_info("get_mv_buf fail\r\n");
2410 return -1;
2411 }
2412 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2413 dump_pic_list(pbi);
2414#ifdef SUPPORT_FB_DECODING
2415 }
2416#endif
2417#endif
2418 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2419 /*if (debug & VP9_DEBUG_BUFMGR)
2420 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2421 cm->new_fb_idx);*/
2422
2423 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2424 if (pbi->mmu_enable) {
2425 /* moved to after picture size ready
2426 *alloc_mmu(cm, params->p.width, params->p.height,
2427 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2428 */
2429 cm->prev_fb_idx = cm->new_fb_idx;
2430 }
2431 /*read_uncompressed_header()*/
2432 cm->last_frame_type = cm->frame_type;
2433 cm->last_intra_only = cm->intra_only;
2434 cm->profile = params->p.profile;
2435 if (cm->profile >= MAX_PROFILES) {
2436 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2437 return -1;
2438 }
2439 cm->show_existing_frame = params->p.show_existing_frame;
2440 if (cm->show_existing_frame) {
2441 /* Show an existing frame directly.*/
2442 int frame_to_show_idx = params->p.frame_to_show_idx;
2443 int frame_to_show;
2444 unsigned long flags;
2445 if (frame_to_show_idx >= REF_FRAMES) {
2446 pr_info("frame_to_show_idx %d exceed max index\r\n",
2447 frame_to_show_idx);
2448 return -1;
2449 }
2450
2451 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2452 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2453 lock_buffer_pool(pool, flags);
2454 if (frame_to_show < 0 ||
2455 frame_bufs[frame_to_show].ref_count < 1) {
2456 unlock_buffer_pool(pool, flags);
2457 pr_err
2458 ("Error:Buffer %d does not contain a decoded frame",
2459 frame_to_show);
2460 return -1;
2461 }
2462
2463 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2464 unlock_buffer_pool(pool, flags);
2465 pbi->refresh_frame_flags = 0;
2466 /*cm->lf.filter_level = 0;*/
2467 cm->show_frame = 1;
2468
2469 /*
2470 *if (pbi->frame_parallel_decode) {
2471 * for (i = 0; i < REF_FRAMES; ++i)
2472 * cm->next_ref_frame_map[i] =
2473 * cm->ref_frame_map[i];
2474 *}
2475 */
2476 /* do not decode, search next start code */
2477 return 1;
2478 }
2479 cm->frame_type = params->p.frame_type;
2480 cm->show_frame = params->p.show_frame;
2481 cm->error_resilient_mode = params->p.error_resilient_mode;
2482
2483
2484 if (cm->frame_type == KEY_FRAME) {
2485 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2486
2487 for (i = 0; i < REFS_PER_FRAME; ++i) {
2488 cm->frame_refs[i].idx = INVALID_IDX;
2489 cm->frame_refs[i].buf = NULL;
2490 }
2491
2492 ret = setup_frame_size(pbi,
2493 cm, params, pbi->frame_mmu_map_addr,
2494 print_header_info);
2495 if (ret)
2496 return -1;
2497 if (pbi->need_resync) {
2498 memset(&cm->ref_frame_map, -1,
2499 sizeof(cm->ref_frame_map));
2500 pbi->need_resync = 0;
2501 }
2502 } else {
2503 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2504 /*if (print_header_info) {
2505 * if (cm->show_frame)
2506 * pr_info
2507 * ("intra_only set to 0 because of show_frame\n");
2508 * else
2509 * pr_info
2510 * ("1-bit intra_only read: %d\n", cm->intra_only);
2511 *}
2512 */
2513
2514
2515 cm->reset_frame_context = cm->error_resilient_mode ?
2516 0 : params->p.reset_frame_context;
2517 if (print_header_info) {
2518 if (cm->error_resilient_mode)
2519 pr_info
2520 ("reset to 0 error_resilient_mode\n");
2521 else
2522 pr_info
2523 (" * 2-bits reset_frame_context read : %d\n",
2524 cm->reset_frame_context);
2525 }
2526
2527 if (cm->intra_only) {
2528 if (cm->profile > PROFILE_0) {
2529 /*read_bitdepth_colorspace_sampling(cm,
2530 * rb, print_header_info);
2531 */
2532 } else {
2533 /*NOTE: The intra-only frame header
2534 *does not include the specification
2535 *of either the color format or
2536 *color sub-sampling
2537 *in profile 0. VP9 specifies that the default
2538 *color format should be YUV 4:2:0 in this
2539 *case (normative).
2540 */
2541 cm->color_space = VPX_CS_BT_601;
2542 cm->subsampling_y = cm->subsampling_x = 1;
2543 cm->bit_depth = VPX_BITS_8;
2544 cm->use_highbitdepth = 0;
2545 }
2546
2547 pbi->refresh_frame_flags =
2548 params->p.refresh_frame_flags;
2549 /*if (print_header_info)
2550 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2551 * REF_FRAMES, pbi->refresh_frame_flags);
2552 */
2553 ret = setup_frame_size(pbi,
2554 cm,
2555 params,
2556 pbi->frame_mmu_map_addr,
2557 print_header_info);
2558 if (ret)
2559 return -1;
2560 if (pbi->need_resync) {
2561 memset(&cm->ref_frame_map, -1,
2562 sizeof(cm->ref_frame_map));
2563 pbi->need_resync = 0;
2564 }
2565 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2566 pbi->refresh_frame_flags =
2567 params->p.refresh_frame_flags;
2568 if (print_header_info)
2569 pr_info
2570 ("*%d-bits refresh_frame read:0x%x\n",
2571 REF_FRAMES, pbi->refresh_frame_flags);
2572 for (i = 0; i < REFS_PER_FRAME; ++i) {
2573 const int ref =
2574 (params->p.ref_info >>
2575 (((REFS_PER_FRAME-i-1)*4)+1))
2576 & 0x7;
2577 const int idx =
2578 cm->ref_frame_map[ref];
2579 struct RefBuffer_s * const ref_frame =
2580 &cm->frame_refs[i];
2581 if (print_header_info)
2582 pr_info("*%d-bits ref[%d]read:%d\n",
2583 REF_FRAMES_LOG2, i, ref);
2584 ref_frame->idx = idx;
2585 ref_frame->buf = &frame_bufs[idx].buf;
2586 cm->ref_frame_sign_bias[LAST_FRAME + i]
2587 = (params->p.ref_info >>
2588 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2589 if (print_header_info)
2590 pr_info("1bit ref_frame_sign_bias");
2591 /*pr_info
2592 *("%dread: %d\n",
2593 *LAST_FRAME+i,
2594 *cm->ref_frame_sign_bias
2595 *[LAST_FRAME + i]);
2596 */
2597 /*pr_info
2598 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2599 *__func__, ref_frame->idx);
2600 */
2601
2602 }
2603
2604 ret = setup_frame_size_with_refs(
2605 pbi,
2606 cm,
2607 params,
2608 pbi->frame_mmu_map_addr,
2609 print_header_info);
2610 if (ret)
2611 return -1;
2612 for (i = 0; i < REFS_PER_FRAME; ++i) {
2613 /*struct RefBuffer_s *const ref_buf =
2614 *&cm->frame_refs[i];
2615 */
2616 /* to do:
2617 *vp9_setup_scale_factors_for_frame
2618 */
2619 }
2620 }
2621 }
2622
2623 pic = get_frame_new_buffer(cm);
2624 if (!pic)
2625 return -1;
2626
2627 pic->bit_depth = cm->bit_depth;
2628 pic->color_space = cm->color_space;
2629 pic->slice_type = cm->frame_type;
2630
2631 if (pbi->need_resync) {
2632 pr_err
2633 ("Error: Keyframe/intra-only frame required to reset\r\n");
2634 return -1;
2635 }
2636 generate_next_ref_frames(pbi);
2637 pbi->hold_ref_buf = 1;
2638
2639#if 0
2640 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2641 vp9_setup_past_independence(cm);
2642 setup_loopfilter(&cm->lf, rb, print_header_info);
2643 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2644 setup_segmentation(&cm->seg, rb, print_header_info);
2645 setup_segmentation_dequant(cm, print_header_info);
2646
2647 setup_tile_info(cm, rb, print_header_info);
2648 sz = vp9_rb_read_literal(rb, 16);
2649 if (print_header_info)
2650 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2651
2652 if (sz == 0)
2653 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2654 "Invalid header size");
2655#endif
2656 /*end read_uncompressed_header()*/
2657 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2658 cm->width == cm->last_width &&
2659 cm->height == cm->last_height &&
2660 !cm->last_intra_only &&
2661 cm->last_show_frame &&
2662 (cm->last_frame_type != KEY_FRAME);
2663
2664 /*pr_info
2665 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2666 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2667 *pr_info
2668 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2669 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2670 */
2671 return 0;
2672}
2673
2674
2675void swap_frame_buffers(struct VP9Decoder_s *pbi)
2676{
2677 int ref_index = 0;
2678 struct VP9_Common_s *const cm = &pbi->common;
2679 struct BufferPool_s *const pool = cm->buffer_pool;
2680 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2681 unsigned long flags;
2682 refresh_ref_frames(pbi);
2683 pbi->hold_ref_buf = 0;
2684 cm->frame_to_show = get_frame_new_buffer(cm);
2685
2686 if (cm->frame_to_show) {
2687 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2688 lock_buffer_pool(pool, flags);
2689 --frame_bufs[cm->new_fb_idx].ref_count;
2690 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2691 * frame_bufs[cm->new_fb_idx].ref_count);
2692 */
2693 unlock_buffer_pool(pool, flags);
2694 /*}*/
2695 }
2696
2697 /*Invalidate these references until the next frame starts.*/
2698 for (ref_index = 0; ref_index < 3; ref_index++)
2699 cm->frame_refs[ref_index].idx = -1;
2700}
2701
2702#if 0
2703static void check_resync(vpx_codec_alg_priv_t *const ctx,
2704 const struct VP9Decoder_s *const pbi)
2705{
2706 /* Clear resync flag if worker got a key frame or intra only frame.*/
2707 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2708 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2709 ctx->need_resync = 0;
2710}
2711#endif
2712
2713int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2714{
2715 struct VP9_Common_s *const cm = &pbi->common;
2716 int ret = -1;
2717
2718 if (pbi->ready_for_new_data == 1)
2719 return ret;
2720
2721 pbi->ready_for_new_data = 1;
2722
2723 /* no raw frame to show!!! */
2724 if (!cm->show_frame)
2725 return ret;
2726
2727 /* may not be get buff in v4l2 */
2728 if (!cm->frame_to_show)
2729 return ret;
2730
2731 pbi->ready_for_new_data = 1;
2732
2733 *sd = *cm->frame_to_show;
2734 ret = 0;
2735
2736 return ret;
2737}
2738
2739int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2740 struct buff_s *mc_buf_i) {
2741 struct VP9_Common_s *cm = &pbi->common;
2742
2743 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2744 pbi->frame_count = 0;
2745 pbi->pic_count = 0;
2746 pbi->pre_stream_offset = 0;
2747 cm->buffer_pool = &pbi->vp9_buffer_pool;
2748 spin_lock_init(&cm->buffer_pool->lock);
2749 cm->prev_fb_idx = INVALID_IDX;
2750 cm->new_fb_idx = INVALID_IDX;
2751 pbi->used_4k_num = -1;
2752 cm->cur_fb_idx_mmu = INVALID_IDX;
2753 pr_debug
2754 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2755 cm->prev_fb_idx, cm->new_fb_idx);
2756 pbi->need_resync = 1;
2757 /* Initialize the references to not point to any frame buffers.*/
2758 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2759 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2760 cm->current_video_frame = 0;
2761 pbi->ready_for_new_data = 1;
2762
2763 /* private init */
2764 pbi->work_space_buf = buf_spec_i;
2765 if (!pbi->mmu_enable)
2766 pbi->mc_buf = mc_buf_i;
2767
2768 pbi->rpm_addr = NULL;
2769 pbi->lmem_addr = NULL;
2770
2771 pbi->use_cma_flag = 0;
2772 pbi->decode_idx = 0;
2773 pbi->slice_idx = 0;
2774 /*int m_uiMaxCUWidth = 1<<7;*/
2775 /*int m_uiMaxCUHeight = 1<<7;*/
2776 pbi->has_keyframe = 0;
2777 pbi->skip_flag = 0;
2778 pbi->wait_buf = 0;
2779 pbi->error_flag = 0;
2780
2781 pbi->pts_mode = PTS_NORMAL;
2782 pbi->last_pts = 0;
2783 pbi->last_lookup_pts = 0;
2784 pbi->last_pts_us64 = 0;
2785 pbi->last_lookup_pts_us64 = 0;
2786 pbi->shift_byte_count = 0;
2787 pbi->shift_byte_count_lo = 0;
2788 pbi->shift_byte_count_hi = 0;
2789 pbi->pts_mode_switching_count = 0;
2790 pbi->pts_mode_recovery_count = 0;
2791
2792 pbi->buf_num = 0;
2793 pbi->pic_num = 0;
2794
2795 return 0;
2796}
2797
2798int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2799{
2800 struct VP9_Common_s *cm = &pbi->common;
2801 struct PIC_BUFFER_CONFIG_s sd;
2802
2803 if (pbi->postproc_done)
2804 return 0;
2805 pbi->postproc_done = 1;
2806 swap_frame_buffers(pbi);
2807 if (!cm->show_existing_frame) {
2808 cm->last_show_frame = cm->show_frame;
2809 cm->prev_frame = cm->cur_frame;
2810#if 0
2811 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2812 vp9_swap_current_and_last_seg_map(cm);
2813#endif
2814 }
2815 cm->last_width = cm->width;
2816 cm->last_height = cm->height;
2817 if (cm->show_frame)
2818 cm->current_video_frame++;
2819
2820 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2821 /*pr_info("Display frame index %d\r\n", sd.index);*/
2822 sd.stream_offset = pbi->pre_stream_offset;
2823 prepare_display_buf(pbi, &sd);
2824 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2825 }
2826
2827/* else
2828 * pr_info
2829 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2830 * pbi->ready_for_new_data, cm->show_frame);
2831 */
2832 return 0;
2833}
2834
2835/*struct VP9Decoder_s vp9_decoder;*/
2836union param_u vp9_param;
2837
2838/**************************************************
2839 *
2840 *VP9 buffer management end
2841 *
2842 ***************************************************
2843 */
2844
2845
2846#define HEVC_CM_BODY_START_ADDR 0x3626
2847#define HEVC_CM_BODY_LENGTH 0x3627
2848#define HEVC_CM_HEADER_LENGTH 0x3629
2849#define HEVC_CM_HEADER_OFFSET 0x362b
2850
2851#define LOSLESS_COMPRESS_MODE
2852
2853/*#define DECOMP_HEADR_SURGENT*/
2854#ifdef VP9_10B_NV21
2855static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2856#else
2857static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2858#endif
2859static u32 enable_mem_saving = 1;
2860static u32 force_w_h;
2861
2862static u32 force_fps;
2863
2864
2865const u32 vp9_version = 201602101;
2866static u32 debug;
2867static u32 radr;
2868static u32 rval;
2869static u32 pop_shorts;
2870static u32 dbg_cmd;
2871static u32 dbg_skip_decode_index;
2872static u32 endian = 0xff0;
2873#ifdef ERROR_HANDLE_DEBUG
2874static u32 dbg_nal_skip_flag;
2875 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2876static u32 dbg_nal_skip_count;
2877#endif
2878/*for debug*/
2879static u32 decode_pic_begin;
2880static uint slice_parse_begin;
2881static u32 step;
2882#ifdef MIX_STREAM_SUPPORT
2883static u32 buf_alloc_width = 4096;
2884static u32 buf_alloc_height = 2304;
2885static u32 vp9_max_pic_w = 4096;
2886static u32 vp9_max_pic_h = 2304;
2887
2888static u32 dynamic_buf_num_margin;
2889#else
2890static u32 buf_alloc_width;
2891static u32 buf_alloc_height;
2892static u32 dynamic_buf_num_margin = 7;
2893#endif
2894static u32 buf_alloc_depth = 10;
2895static u32 buf_alloc_size;
2896/*
2897 *bit[0]: 0,
2898 * bit[1]: 0, always release cma buffer when stop
2899 * bit[1]: 1, never release cma buffer when stop
2900 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2901 *do not release cma buffer is blackout is not 1
2902 *
2903 *bit[2]: 0, when start decoding, check current displayed buffer
2904 * (only for buffer decoded by vp9) if blackout is 0
2905 * 1, do not check current displayed buffer
2906 *
2907 *bit[3]: 1, if blackout is not 1, do not release current
2908 * displayed cma buffer always.
2909 */
2910/* set to 1 for fast play;
2911 * set to 8 for other case of "keep last frame"
2912 */
2913static u32 buffer_mode = 1;
2914/* buffer_mode_dbg: debug only*/
2915static u32 buffer_mode_dbg = 0xffff0000;
2916/**/
2917
2918/*
2919 *bit 0, 1: only display I picture;
2920 *bit 1, 1: only decode I picture;
2921 */
2922static u32 i_only_flag;
2923
2924static u32 low_latency_flag;
2925
2926static u32 no_head;
2927
2928static u32 max_decoding_time;
2929/*
2930 *error handling
2931 */
2932/*error_handle_policy:
2933 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2934 *1, skip error_skip_nal_count nals before error recovery;
2935 *bit 1 (valid only when bit0 == 1):
2936 *1, wait vps/sps/pps after error recovery;
2937 *bit 2 (valid only when bit0 == 0):
2938 *0, auto search after error recovery (vp9_recover() called);
2939 *1, manual search after error recovery
2940 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2941 *
2942 *bit 4: 0, set error_mark after reset/recover
2943 * 1, do not set error_mark after reset/recover
2944 *bit 5: 0, check total lcu for every picture
2945 * 1, do not check total lcu
2946 *
2947 */
2948
2949static u32 error_handle_policy;
2950/*static u32 parser_sei_enable = 1;*/
2951#define MAX_BUF_NUM_NORMAL 12
2952#define MAX_BUF_NUM_LESS 10
2953static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2954#define MAX_BUF_NUM_SAVE_BUF 8
2955
2956static u32 run_ready_min_buf_num = 2;
2957
2958
2959static DEFINE_MUTEX(vvp9_mutex);
2960#ifndef MULTI_INSTANCE_SUPPORT
2961static struct device *cma_dev;
2962#endif
2963
2964#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2965#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2966#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2967#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2968#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2969#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2970#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2971#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2972#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2973#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2974#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2975#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2976#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2977#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2978#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2979#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2980#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2981#ifdef MULTI_INSTANCE_SUPPORT
2982#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2983#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2984#else
2985#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2986#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2987#endif
2988#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2989#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2990
2991
2992/*
2993 *ucode parser/search control
2994 *bit 0: 0, header auto parse; 1, header manual parse
2995 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
2996 *bit [3:2]: valid when bit1==0;
2997 *0, auto skip nal before first vps/sps/pps/idr;
2998 *1, auto skip nal before first vps/sps/pps
2999 *2, auto skip nal before first vps/sps/pps,
3000 * and not decode until the first I slice (with slice address of 0)
3001 *
3002 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
3003 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
3004 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
3005 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
3006 *bit [17]: for NAL_SEI when bit0 is 0:
3007 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
3008 *bit [31:20]: used by ucode for debug purpose
3009 */
3010#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
3011 /*[31:24] chip feature
3012 31: 0, use MBOX1; 1, use MBOX0
3013 */
3014#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
3015#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
3016
3017#ifdef MULTI_INSTANCE_SUPPORT
3018#define RPM_BUF_SIZE (0x400 * 2)
3019#else
3020#define RPM_BUF_SIZE (0x80*2)
3021#endif
3022#define LMEM_BUF_SIZE (0x400 * 2)
3023
3024#define WORK_BUF_SPEC_NUM 3
3025static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
3026 {
3027 /* 8M bytes */
3028 .max_width = 1920,
3029 .max_height = 1088,
3030 .ipp = {
3031 /* IPP work space calculation :
3032 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3033 */
3034 .buf_size = 0x4000,
3035 },
3036 .sao_abv = {
3037 .buf_size = 0x30000,
3038 },
3039 .sao_vb = {
3040 .buf_size = 0x30000,
3041 },
3042 .short_term_rps = {
3043 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3044 * total 64x16x2 = 2048 bytes (0x800)
3045 */
3046 .buf_size = 0x800,
3047 },
3048 .vps = {
3049 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3050 * total 0x0800 bytes
3051 */
3052 .buf_size = 0x800,
3053 },
3054 .sps = {
3055 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3056 * total 0x0800 bytes
3057 */
3058 .buf_size = 0x800,
3059 },
3060 .pps = {
3061 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3062 * total 0x2000 bytes
3063 */
3064 .buf_size = 0x2000,
3065 },
3066 .sao_up = {
3067 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3068 * each has 16 bytes total 0x2800 bytes
3069 */
3070 .buf_size = 0x2800,
3071 },
3072 .swap_buf = {
3073 /* 256cyclex64bit = 2K bytes 0x800
3074 * (only 144 cycles valid)
3075 */
3076 .buf_size = 0x800,
3077 },
3078 .swap_buf2 = {
3079 .buf_size = 0x800,
3080 },
3081 .scalelut = {
3082 /* support up to 32 SCALELUT 1024x32 =
3083 * 32Kbytes (0x8000)
3084 */
3085 .buf_size = 0x8000,
3086 },
3087 .dblk_para = {
3088 /* DBLK -> Max 256(4096/16) LCU,
3089 *each para 1024bytes(total:0x40000),
3090 *data 1024bytes(total:0x40000)
3091 */
3092 .buf_size = 0x80000,
3093 },
3094 .dblk_data = {
3095 .buf_size = 0x80000,
3096 },
3097 .seg_map = {
3098 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3099 .buf_size = 0xd800,
3100 },
3101 .mmu_vbh = {
3102 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3103 },
3104#if 0
3105 .cm_header = {
3106 /*add one for keeper.*/
3107 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3108 (FRAME_BUFFERS + 1),
3109 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3110 },
3111#endif
3112 .mpred_above = {
3113 .buf_size = 0x10000, /* 2 * size of hevc*/
3114 },
3115#ifdef MV_USE_FIXED_BUF
3116 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3117 .buf_size = 0x40000 * FRAME_BUFFERS,
3118 },
3119#endif
3120 .rpm = {
3121 .buf_size = RPM_BUF_SIZE,
3122 },
3123 .lmem = {
3124 .buf_size = 0x400 * 2,
3125 }
3126 },
3127 {
3128 .max_width = 4096,
3129 .max_height = 2304,
3130 .ipp = {
3131 /* IPP work space calculation :
3132 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3133 */
3134 .buf_size = 0x4000,
3135 },
3136 .sao_abv = {
3137 .buf_size = 0x30000,
3138 },
3139 .sao_vb = {
3140 .buf_size = 0x30000,
3141 },
3142 .short_term_rps = {
3143 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3144 * total 64x16x2 = 2048 bytes (0x800)
3145 */
3146 .buf_size = 0x800,
3147 },
3148 .vps = {
3149 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3150 * total 0x0800 bytes
3151 */
3152 .buf_size = 0x800,
3153 },
3154 .sps = {
3155 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3156 * total 0x0800 bytes
3157 */
3158 .buf_size = 0x800,
3159 },
3160 .pps = {
3161 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3162 * total 0x2000 bytes
3163 */
3164 .buf_size = 0x2000,
3165 },
3166 .sao_up = {
3167 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3168 * each has 16 bytes total 0x2800 bytes
3169 */
3170 .buf_size = 0x2800,
3171 },
3172 .swap_buf = {
3173 /* 256cyclex64bit = 2K bytes 0x800
3174 * (only 144 cycles valid)
3175 */
3176 .buf_size = 0x800,
3177 },
3178 .swap_buf2 = {
3179 .buf_size = 0x800,
3180 },
3181 .scalelut = {
3182 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3183 * (0x8000)
3184 */
3185 .buf_size = 0x8000,
3186 },
3187 .dblk_para = {
3188 /* DBLK -> Max 256(4096/16) LCU,
3189 *each para 1024bytes(total:0x40000),
3190 *data 1024bytes(total:0x40000)
3191 */
3192 .buf_size = 0x80000,
3193 },
3194 .dblk_data = {
3195 .buf_size = 0x80000,
3196 },
3197 .seg_map = {
3198 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3199 .buf_size = 0xd800,
3200 },
3201 .mmu_vbh = {
3202 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3203 },
3204#if 0
3205 .cm_header = {
3206 /*add one for keeper.*/
3207 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3208 (FRAME_BUFFERS + 1),
3209 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3210 },
3211#endif
3212 .mpred_above = {
3213 .buf_size = 0x10000, /* 2 * size of hevc*/
3214 },
3215#ifdef MV_USE_FIXED_BUF
3216 .mpred_mv = {
3217 /* .buf_size = 0x100000*16,
3218 * //4k2k , 0x100000 per buffer
3219 */
3220 /* 4096x2304 , 0x120000 per buffer */
3221 .buf_size = 0x120000 * FRAME_BUFFERS,
3222 },
3223#endif
3224 .rpm = {
3225 .buf_size = RPM_BUF_SIZE,
3226 },
3227 .lmem = {
3228 .buf_size = 0x400 * 2,
3229 }
3230 },
3231 {
3232 .max_width = 4096*2,
3233 .max_height = 2304*2,
3234 .ipp = {
3235 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3236 .buf_size = 0x4000*2,
3237 },
3238 .sao_abv = {
3239 .buf_size = 0x30000*2,
3240 },
3241 .sao_vb = {
3242 .buf_size = 0x30000*2,
3243 },
3244 .short_term_rps = {
3245 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3246 .buf_size = 0x800,
3247 },
3248 .vps = {
3249 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3250 .buf_size = 0x800,
3251 },
3252 .sps = {
3253 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3254 .buf_size = 0x800,
3255 },
3256 .pps = {
3257 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3258 .buf_size = 0x2000,
3259 },
3260 .sao_up = {
3261 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3262 .buf_size = 0x2800*2,
3263 },
3264 .swap_buf = {
3265 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3266 .buf_size = 0x800,
3267 },
3268 .swap_buf2 = {
3269 .buf_size = 0x800,
3270 },
3271 .scalelut = {
3272 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3273 .buf_size = 0x8000*2,
3274 },
3275 .dblk_para = {
3276 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3277 .buf_size = 0x80000*2,
3278 },
3279 .dblk_data = {
3280 .buf_size = 0x80000*2,
3281 },
3282 .seg_map = {
3283 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3284 .buf_size = 0xd800*4,
3285 },
3286 .mmu_vbh = {
3287 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3288 },
3289#if 0
3290 .cm_header = {
3291 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3292 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3293 },
3294#endif
3295 .mpred_above = {
3296 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3297 },
3298#ifdef MV_USE_FIXED_BUF
3299 .mpred_mv = {
3300 //4k2k , 0x100000 per buffer */
3301 /* 4096x2304 , 0x120000 per buffer */
3302 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3303 },
3304#endif
3305 .rpm = {
3306 .buf_size = RPM_BUF_SIZE,
3307 },
3308 .lmem = {
3309 .buf_size = 0x400 * 2,
3310 }
3311 }
3312};
3313
3314
3315/*Losless compression body buffer size 4K per 64x32 (jt)*/
3316int compute_losless_comp_body_size(int width, int height,
3317 uint8_t is_bit_depth_10)
3318{
3319 int width_x64;
3320 int height_x32;
3321 int bsize;
3322
3323 width_x64 = width + 63;
3324 width_x64 >>= 6;
3325 height_x32 = height + 31;
3326 height_x32 >>= 5;
3327 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3328 if (debug & VP9_DEBUG_BUFMGR_MORE)
3329 pr_info("%s(%d,%d,%d)=>%d\n",
3330 __func__, width, height,
3331 is_bit_depth_10, bsize);
3332
3333 return bsize;
3334}
3335
3336/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3337static int compute_losless_comp_header_size(int width, int height)
3338{
3339 int width_x128;
3340 int height_x64;
3341 int hsize;
3342
3343 width_x128 = width + 127;
3344 width_x128 >>= 7;
3345 height_x64 = height + 63;
3346 height_x64 >>= 6;
3347
3348 hsize = 32 * width_x128 * height_x64;
3349 if (debug & VP9_DEBUG_BUFMGR_MORE)
3350 pr_info("%s(%d,%d)=>%d\n",
3351 __func__, width, height,
3352 hsize);
3353
3354 return hsize;
3355}
3356
3357static void init_buff_spec(struct VP9Decoder_s *pbi,
3358 struct BuffInfo_s *buf_spec)
3359{
3360 void *mem_start_virt;
3361
3362 buf_spec->ipp.buf_start = buf_spec->start_adr;
3363 buf_spec->sao_abv.buf_start =
3364 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3365
3366 buf_spec->sao_vb.buf_start =
3367 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3368 buf_spec->short_term_rps.buf_start =
3369 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3370 buf_spec->vps.buf_start =
3371 buf_spec->short_term_rps.buf_start +
3372 buf_spec->short_term_rps.buf_size;
3373 buf_spec->sps.buf_start =
3374 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3375 buf_spec->pps.buf_start =
3376 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3377 buf_spec->sao_up.buf_start =
3378 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3379 buf_spec->swap_buf.buf_start =
3380 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3381 buf_spec->swap_buf2.buf_start =
3382 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3383 buf_spec->scalelut.buf_start =
3384 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3385 buf_spec->dblk_para.buf_start =
3386 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3387 buf_spec->dblk_data.buf_start =
3388 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3389 buf_spec->seg_map.buf_start =
3390 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3391 if (pbi == NULL || pbi->mmu_enable) {
3392 buf_spec->mmu_vbh.buf_start =
3393 buf_spec->seg_map.buf_start +
3394 buf_spec->seg_map.buf_size;
3395 buf_spec->mpred_above.buf_start =
3396 buf_spec->mmu_vbh.buf_start +
3397 buf_spec->mmu_vbh.buf_size;
3398 } else {
3399 buf_spec->mpred_above.buf_start =
3400 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3401 }
3402#ifdef MV_USE_FIXED_BUF
3403 buf_spec->mpred_mv.buf_start =
3404 buf_spec->mpred_above.buf_start +
3405 buf_spec->mpred_above.buf_size;
3406
3407 buf_spec->rpm.buf_start =
3408 buf_spec->mpred_mv.buf_start +
3409 buf_spec->mpred_mv.buf_size;
3410#else
3411 buf_spec->rpm.buf_start =
3412 buf_spec->mpred_above.buf_start +
3413 buf_spec->mpred_above.buf_size;
3414
3415#endif
3416 buf_spec->lmem.buf_start =
3417 buf_spec->rpm.buf_start +
3418 buf_spec->rpm.buf_size;
3419 buf_spec->end_adr =
3420 buf_spec->lmem.buf_start +
3421 buf_spec->lmem.buf_size;
3422
3423 if (!pbi)
3424 return;
3425
3426 if (!vdec_secure(hw_to_vdec(pbi))) {
3427 mem_start_virt =
3428 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3429 if (mem_start_virt) {
3430 memset(mem_start_virt, 0,
3431 buf_spec->dblk_para.buf_size);
3432 codec_mm_dma_flush(mem_start_virt,
3433 buf_spec->dblk_para.buf_size,
3434 DMA_TO_DEVICE);
3435 } else {
3436 mem_start_virt = codec_mm_vmap(
3437 buf_spec->dblk_para.buf_start,
3438 buf_spec->dblk_para.buf_size);
3439 if (mem_start_virt) {
3440 memset(mem_start_virt, 0,
3441 buf_spec->dblk_para.buf_size);
3442 codec_mm_dma_flush(mem_start_virt,
3443 buf_spec->dblk_para.buf_size,
3444 DMA_TO_DEVICE);
3445 codec_mm_unmap_phyaddr(mem_start_virt);
3446 } else {
3447 /*not virt for tvp playing,
3448 may need clear on ucode.*/
3449 pr_err("mem_start_virt failed\n");
3450 }
3451 }
3452 }
3453
3454 if (debug) {
3455 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3456 buf_spec->start_adr, buf_spec->end_adr,
3457 buf_spec->end_adr - buf_spec->start_adr);
3458 }
3459
3460 if (debug) {
3461 pr_info("ipp.buf_start :%x\n",
3462 buf_spec->ipp.buf_start);
3463 pr_info("sao_abv.buf_start :%x\n",
3464 buf_spec->sao_abv.buf_start);
3465 pr_info("sao_vb.buf_start :%x\n",
3466 buf_spec->sao_vb.buf_start);
3467 pr_info("short_term_rps.buf_start :%x\n",
3468 buf_spec->short_term_rps.buf_start);
3469 pr_info("vps.buf_start :%x\n",
3470 buf_spec->vps.buf_start);
3471 pr_info("sps.buf_start :%x\n",
3472 buf_spec->sps.buf_start);
3473 pr_info("pps.buf_start :%x\n",
3474 buf_spec->pps.buf_start);
3475 pr_info("sao_up.buf_start :%x\n",
3476 buf_spec->sao_up.buf_start);
3477 pr_info("swap_buf.buf_start :%x\n",
3478 buf_spec->swap_buf.buf_start);
3479 pr_info("swap_buf2.buf_start :%x\n",
3480 buf_spec->swap_buf2.buf_start);
3481 pr_info("scalelut.buf_start :%x\n",
3482 buf_spec->scalelut.buf_start);
3483 pr_info("dblk_para.buf_start :%x\n",
3484 buf_spec->dblk_para.buf_start);
3485 pr_info("dblk_data.buf_start :%x\n",
3486 buf_spec->dblk_data.buf_start);
3487 pr_info("seg_map.buf_start :%x\n",
3488 buf_spec->seg_map.buf_start);
3489 if (pbi->mmu_enable) {
3490 pr_info("mmu_vbh.buf_start :%x\n",
3491 buf_spec->mmu_vbh.buf_start);
3492 }
3493 pr_info("mpred_above.buf_start :%x\n",
3494 buf_spec->mpred_above.buf_start);
3495#ifdef MV_USE_FIXED_BUF
3496 pr_info("mpred_mv.buf_start :%x\n",
3497 buf_spec->mpred_mv.buf_start);
3498#endif
3499 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3500 pr_info("rpm.buf_start :%x\n",
3501 buf_spec->rpm.buf_start);
3502 }
3503 }
3504}
3505
3506/* cache_util.c */
3507#define THODIYIL_MCRCC_CANVAS_ALGX 4
3508
3509static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3510
3511static void mcrcc_perfcount_reset(void)
3512{
3513 if (debug & VP9_DEBUG_CACHE)
3514 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3515 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3516 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3517 return;
3518}
3519
3520static unsigned raw_mcr_cnt_total_prev;
3521static unsigned hit_mcr_0_cnt_total_prev;
3522static unsigned hit_mcr_1_cnt_total_prev;
3523static unsigned byp_mcr_cnt_nchcanv_total_prev;
3524static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3525
3526static void mcrcc_get_hitrate(unsigned reset_pre)
3527{
3528 unsigned delta_hit_mcr_0_cnt;
3529 unsigned delta_hit_mcr_1_cnt;
3530 unsigned delta_raw_mcr_cnt;
3531 unsigned delta_mcr_cnt_nchcanv;
3532 unsigned delta_mcr_cnt_nchoutwin;
3533
3534 unsigned tmp;
3535 unsigned raw_mcr_cnt;
3536 unsigned hit_mcr_cnt;
3537 unsigned byp_mcr_cnt_nchoutwin;
3538 unsigned byp_mcr_cnt_nchcanv;
3539 int hitrate;
3540 if (reset_pre) {
3541 raw_mcr_cnt_total_prev = 0;
3542 hit_mcr_0_cnt_total_prev = 0;
3543 hit_mcr_1_cnt_total_prev = 0;
3544 byp_mcr_cnt_nchcanv_total_prev = 0;
3545 byp_mcr_cnt_nchoutwin_total_prev = 0;
3546 }
3547 if (debug & VP9_DEBUG_CACHE)
3548 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3549 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3550 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3551 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3552 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3553 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3554 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3555 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3556 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3557
3558 if (debug & VP9_DEBUG_CACHE)
3559 pr_info("raw_mcr_cnt_total: %d\n",
3560 raw_mcr_cnt);
3561 if (debug & VP9_DEBUG_CACHE)
3562 pr_info("hit_mcr_cnt_total: %d\n",
3563 hit_mcr_cnt);
3564 if (debug & VP9_DEBUG_CACHE)
3565 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3566 byp_mcr_cnt_nchoutwin);
3567 if (debug & VP9_DEBUG_CACHE)
3568 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3569 byp_mcr_cnt_nchcanv);
3570
3571 delta_raw_mcr_cnt = raw_mcr_cnt -
3572 raw_mcr_cnt_total_prev;
3573 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3574 byp_mcr_cnt_nchcanv_total_prev;
3575 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3576 byp_mcr_cnt_nchoutwin_total_prev;
3577 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3578 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3579 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3580
3581 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3582 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3583 if (debug & VP9_DEBUG_CACHE)
3584 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3585 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3586 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3587 if (debug & VP9_DEBUG_CACHE)
3588 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3589 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3590 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3591 if (debug & VP9_DEBUG_CACHE)
3592 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3593 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3594 hit_mcr_0_cnt_total_prev = tmp;
3595 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3596 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3597 if (debug & VP9_DEBUG_CACHE)
3598 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3599 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3600 hit_mcr_1_cnt_total_prev = tmp;
3601
3602 if (delta_raw_mcr_cnt != 0) {
3603 hitrate = 100 * delta_hit_mcr_0_cnt
3604 / delta_raw_mcr_cnt;
3605 if (debug & VP9_DEBUG_CACHE)
3606 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3607 hitrate = 100 * delta_hit_mcr_1_cnt
3608 / delta_raw_mcr_cnt;
3609 if (debug & VP9_DEBUG_CACHE)
3610 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3611 hitrate = 100 * delta_mcr_cnt_nchcanv
3612 / delta_raw_mcr_cnt;
3613 if (debug & VP9_DEBUG_CACHE)
3614 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3615 hitrate = 100 * delta_mcr_cnt_nchoutwin
3616 / delta_raw_mcr_cnt;
3617 if (debug & VP9_DEBUG_CACHE)
3618 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3619 }
3620
3621
3622 if (raw_mcr_cnt != 0) {
3623 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3624 if (debug & VP9_DEBUG_CACHE)
3625 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3626 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3627 / raw_mcr_cnt;
3628 if (debug & VP9_DEBUG_CACHE)
3629 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3630 } else {
3631 if (debug & VP9_DEBUG_CACHE)
3632 pr_info("MCRCC_HIT_RATE : na\n");
3633 if (debug & VP9_DEBUG_CACHE)
3634 pr_info("MCRCC_BYP_RATE : na\n");
3635 }
3636 return;
3637}
3638
3639
3640static void decomp_perfcount_reset(void)
3641{
3642 if (debug & VP9_DEBUG_CACHE)
3643 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3644 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3645 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3646 return;
3647}
3648
3649static void decomp_get_hitrate(void)
3650{
3651 unsigned raw_mcr_cnt;
3652 unsigned hit_mcr_cnt;
3653 int hitrate;
3654 if (debug & VP9_DEBUG_CACHE)
3655 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3656 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3657 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3658 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3659 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3660
3661 if (debug & VP9_DEBUG_CACHE)
3662 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3663 if (debug & VP9_DEBUG_CACHE)
3664 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3665
3666 if (raw_mcr_cnt != 0) {
3667 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3668 if (debug & VP9_DEBUG_CACHE)
3669 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3670 } else {
3671 if (debug & VP9_DEBUG_CACHE)
3672 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3673 }
3674 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3675 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3676 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3677 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3678
3679 if (debug & VP9_DEBUG_CACHE)
3680 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3681 if (debug & VP9_DEBUG_CACHE)
3682 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3683
3684 if (raw_mcr_cnt != 0) {
3685 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3686 if (debug & VP9_DEBUG_CACHE)
3687 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3688 } else {
3689 if (debug & VP9_DEBUG_CACHE)
3690 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3691 }
3692 return;
3693}
3694
3695static void decomp_get_comprate(void)
3696{
3697 unsigned raw_ucomp_cnt;
3698 unsigned fast_comp_cnt;
3699 unsigned slow_comp_cnt;
3700 int comprate;
3701
3702 if (debug & VP9_DEBUG_CACHE)
3703 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3704 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3705 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3706 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3707 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3708 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3709 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3710
3711 if (debug & VP9_DEBUG_CACHE)
3712 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3713 if (debug & VP9_DEBUG_CACHE)
3714 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3715 if (debug & VP9_DEBUG_CACHE)
3716 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3717
3718 if (raw_ucomp_cnt != 0) {
3719 comprate = (fast_comp_cnt + slow_comp_cnt)
3720 * 100 / raw_ucomp_cnt;
3721 if (debug & VP9_DEBUG_CACHE)
3722 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3723 } else {
3724 if (debug & VP9_DEBUG_CACHE)
3725 pr_info("DECOMP_COMP_RATIO : na\n");
3726 }
3727 return;
3728}
3729/* cache_util.c end */
3730
3731/*====================================================
3732 *========================================================================
3733 *vp9_prob define
3734 *========================================================================
3735 */
3736#define VP9_PARTITION_START 0
3737#define VP9_PARTITION_SIZE_STEP (3 * 4)
3738#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3739#define VP9_PARTITION_KEY_START 0
3740#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3741#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3742#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3743#define VP9_SKIP_SIZE 4 /* only use 3*/
3744#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3745#define VP9_TX_MODE_8_0_OFFSET 0
3746#define VP9_TX_MODE_8_1_OFFSET 1
3747#define VP9_TX_MODE_16_0_OFFSET 2
3748#define VP9_TX_MODE_16_1_OFFSET 4
3749#define VP9_TX_MODE_32_0_OFFSET 6
3750#define VP9_TX_MODE_32_1_OFFSET 9
3751#define VP9_TX_MODE_SIZE 12
3752#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3753#define VP9_COEF_BAND_0_OFFSET 0
3754#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3755#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3756#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3757#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3758#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3759#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3760#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3761#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3762#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3763#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3764#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3765#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3766#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3767#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3768#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3769#define VP9_INTERP_SIZE 8
3770#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3771#define VP9_INTRA_INTER_SIZE 4
3772#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3773#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3774#define VP9_COMP_INTER_START \
3775 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3776#define VP9_COMP_INTER_SIZE 5
3777#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3778#define VP9_COMP_REF_SIZE 5
3779#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3780#define VP9_SINGLE_REF_SIZE 10
3781#define VP9_REF_MODE_START VP9_COMP_INTER_START
3782#define VP9_REF_MODE_SIZE \
3783 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3784#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3785#define VP9_IF_Y_MODE_SIZE 36
3786#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3787#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3788#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3789#define VP9_MV_JOINTS_SIZE 3
3790#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3791#define VP9_MV_SIGN_0_SIZE 1
3792#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3793#define VP9_MV_CLASSES_0_SIZE 10
3794#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3795#define VP9_MV_CLASS0_0_SIZE 1
3796#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3797#define VP9_MV_BITS_0_SIZE 10
3798#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3799#define VP9_MV_SIGN_1_SIZE 1
3800#define VP9_MV_CLASSES_1_START \
3801 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3802#define VP9_MV_CLASSES_1_SIZE 10
3803#define VP9_MV_CLASS0_1_START \
3804 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3805#define VP9_MV_CLASS0_1_SIZE 1
3806#define VP9_MV_BITS_1_START \
3807 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3808#define VP9_MV_BITS_1_SIZE 10
3809#define VP9_MV_CLASS0_FP_0_START \
3810 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3811#define VP9_MV_CLASS0_FP_0_SIZE 9
3812#define VP9_MV_CLASS0_FP_1_START \
3813 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3814#define VP9_MV_CLASS0_FP_1_SIZE 9
3815#define VP9_MV_CLASS0_HP_0_START \
3816 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3817#define VP9_MV_CLASS0_HP_0_SIZE 2
3818#define VP9_MV_CLASS0_HP_1_START \
3819 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3820#define VP9_MV_CLASS0_HP_1_SIZE 2
3821#define VP9_MV_START VP9_MV_JOINTS_START
3822#define VP9_MV_SIZE 72 /*only use 69*/
3823
3824#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3825
3826
3827/*========================================================================
3828 * vp9_count_mem define
3829 *========================================================================
3830 */
3831#define VP9_COEF_COUNT_START 0
3832#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3833#define VP9_COEF_COUNT_BAND_1_OFFSET \
3834 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3835#define VP9_COEF_COUNT_BAND_2_OFFSET \
3836 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3837#define VP9_COEF_COUNT_BAND_3_OFFSET \
3838 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3839#define VP9_COEF_COUNT_BAND_4_OFFSET \
3840 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3841#define VP9_COEF_COUNT_BAND_5_OFFSET \
3842 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3843#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3844#define VP9_COEF_COUNT_4X4_START \
3845 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3846#define VP9_COEF_COUNT_8X8_START \
3847 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3848#define VP9_COEF_COUNT_16X16_START \
3849 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3850#define VP9_COEF_COUNT_32X32_START \
3851 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3852#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3853#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3854
3855#define VP9_INTRA_INTER_COUNT_START \
3856 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3857#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3858#define VP9_COMP_INTER_COUNT_START \
3859 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3860#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3861#define VP9_COMP_REF_COUNT_START \
3862 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3863#define VP9_COMP_REF_COUNT_SIZE (5*2)
3864#define VP9_SINGLE_REF_COUNT_START \
3865 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3866#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3867#define VP9_TX_MODE_COUNT_START \
3868 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3869#define VP9_TX_MODE_COUNT_SIZE (12*2)
3870#define VP9_SKIP_COUNT_START \
3871 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3872#define VP9_SKIP_COUNT_SIZE (3*2)
3873#define VP9_MV_SIGN_0_COUNT_START \
3874 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3875#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3876#define VP9_MV_SIGN_1_COUNT_START \
3877 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3878#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3879#define VP9_MV_BITS_0_COUNT_START \
3880 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3881#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3882#define VP9_MV_BITS_1_COUNT_START \
3883 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3884#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3885#define VP9_MV_CLASS0_HP_0_COUNT_START \
3886 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3887#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3888#define VP9_MV_CLASS0_HP_1_COUNT_START \
3889 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3890#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3891/* Start merge_tree*/
3892#define VP9_INTER_MODE_COUNT_START \
3893 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3894#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3895#define VP9_IF_Y_MODE_COUNT_START \
3896 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3897#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3898#define VP9_IF_UV_MODE_COUNT_START \
3899 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3900#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3901#define VP9_PARTITION_P_COUNT_START \
3902 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3903#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3904#define VP9_INTERP_COUNT_START \
3905 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3906#define VP9_INTERP_COUNT_SIZE (4*3)
3907#define VP9_MV_JOINTS_COUNT_START \
3908 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3909#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3910#define VP9_MV_CLASSES_0_COUNT_START \
3911 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3912#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3913#define VP9_MV_CLASS0_0_COUNT_START \
3914 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3915#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3916#define VP9_MV_CLASSES_1_COUNT_START \
3917 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3918#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3919#define VP9_MV_CLASS0_1_COUNT_START \
3920 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3921#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3922#define VP9_MV_CLASS0_FP_0_COUNT_START \
3923 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3924#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3925#define VP9_MV_CLASS0_FP_1_COUNT_START \
3926 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3927#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3928
3929
3930#define DC_PRED 0 /* Average of above and left pixels*/
3931#define V_PRED 1 /* Vertical*/
3932#define H_PRED 2 /* Horizontal*/
3933#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3934#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3935#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3936#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3937#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3938#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3939#define TM_PRED 9 /*True-motion*/
3940
3941int clip_prob(int p)
3942{
3943 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3944}
3945
3946#define ROUND_POWER_OF_TWO(value, n) \
3947 (((value) + (1 << ((n) - 1))) >> (n))
3948
3949#define MODE_MV_COUNT_SAT 20
3950static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3951 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3952 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3953};
3954
3955void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3956 int coef_node_start, int tree_left, int tree_right, int tree_i,
3957 int node) {
3958
3959 int prob_32, prob_res, prob_shift;
3960 int pre_prob, new_prob;
3961 int den, m_count, get_prob, factor;
3962
3963 prob_32 = prev_prob[coef_node_start / 4 * 2];
3964 prob_res = coef_node_start & 3;
3965 prob_shift = prob_res * 8;
3966 pre_prob = (prob_32 >> prob_shift) & 0xff;
3967
3968 den = tree_left + tree_right;
3969
3970 if (den == 0)
3971 new_prob = pre_prob;
3972 else {
3973 m_count = (den < MODE_MV_COUNT_SAT) ?
3974 den : MODE_MV_COUNT_SAT;
3975 get_prob = clip_prob(
3976 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3977 den));
3978 /*weighted_prob*/
3979 factor = count_to_update_factor[m_count];
3980 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3981 + get_prob * factor, 8);
3982 }
3983 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3984 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
3985
3986 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3987 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3988 *cur_prob[coef_node_start/4*2]);
3989 */
3990}
3991
3992
3993/*void adapt_coef_probs(void)*/
3994void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3995 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3996{
3997 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3998 *unsigned int prev_prob[496*2];
3999 *unsigned int cur_prob[496*2];
4000 *0x300 * 128bits = 0x3000 (32K Bytes)
4001 *unsigned int count[0x300*4];
4002 */
4003
4004 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
4005 int plane, coef_plane_start, coef_count_plane_start;
4006 int type, coef_type_start, coef_count_type_start;
4007 int band, coef_band_start, coef_count_band_start;
4008 int cxt_num;
4009 int cxt, coef_cxt_start, coef_count_cxt_start;
4010 int node, coef_node_start, coef_count_node_start;
4011
4012 int tree_i, tree_left, tree_right;
4013 int mvd_i;
4014
4015 int count_sat = 24;
4016 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
4017 *use 128
4018 */
4019 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
4020 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
4021 int update_factor = cur_kf ? 112 :
4022 prev_kf ? 128 : 112;
4023
4024 int prob_32;
4025 int prob_res;
4026 int prob_shift;
4027 int pre_prob;
4028
4029 int num, den;
4030 int get_prob;
4031 int m_count;
4032 int factor;
4033
4034 int new_prob;
4035
4036 if (debug & VP9_DEBUG_MERGE)
4037 pr_info
4038 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4039 pre_fc, prev_kf, cur_kf);
4040
4041 /*adapt_coef_probs*/
4042 for (tx_size = 0; tx_size < 4; tx_size++) {
4043 coef_tx_size_start = VP9_COEF_START
4044 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4045 coef_count_tx_size_start = VP9_COEF_COUNT_START
4046 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4047 coef_plane_start = coef_tx_size_start;
4048 coef_count_plane_start = coef_count_tx_size_start;
4049 for (plane = 0; plane < 2; plane++) {
4050 coef_type_start = coef_plane_start;
4051 coef_count_type_start = coef_count_plane_start;
4052 for (type = 0; type < 2; type++) {
4053 coef_band_start = coef_type_start;
4054 coef_count_band_start = coef_count_type_start;
4055 for (band = 0; band < 6; band++) {
4056 if (band == 0)
4057 cxt_num = 3;
4058 else
4059 cxt_num = 6;
4060 coef_cxt_start = coef_band_start;
4061 coef_count_cxt_start =
4062 coef_count_band_start;
4063 for (cxt = 0; cxt < cxt_num; cxt++) {
4064 const int n0 =
4065 count[coef_count_cxt_start];
4066 const int n1 =
4067 count[coef_count_cxt_start + 1];
4068 const int n2 =
4069 count[coef_count_cxt_start + 2];
4070 const int neob =
4071 count[coef_count_cxt_start + 3];
4072 const int nneob =
4073 count[coef_count_cxt_start + 4];
4074 const unsigned int
4075 branch_ct[3][2] = {
4076 { neob, nneob },
4077 { n0, n1 + n2 },
4078 { n1, n2 }
4079 };
4080 coef_node_start =
4081 coef_cxt_start;
4082 for
4083 (node = 0; node < 3; node++) {
4084 prob_32 =
4085 prev_prob[
4086 coef_node_start
4087 / 4 * 2];
4088 prob_res =
4089 coef_node_start & 3;
4090 prob_shift =
4091 prob_res * 8;
4092 pre_prob =
4093 (prob_32 >> prob_shift)
4094 & 0xff;
4095
4096 /*get_binary_prob*/
4097 num =
4098 branch_ct[node][0];
4099 den =
4100 branch_ct[node][0] +
4101 branch_ct[node][1];
4102 m_count = (den <
4103 count_sat)
4104 ? den : count_sat;
4105
4106 get_prob =
4107 (den == 0) ? 128u :
4108 clip_prob(
4109 div_r32(((int64_t)
4110 num * 256
4111 + (den >> 1)),
4112 den));
4113
4114 factor =
4115 update_factor * m_count
4116 / count_sat;
4117 new_prob =
4118 ROUND_POWER_OF_TWO
4119 (pre_prob *
4120 (256 - factor) +
4121 get_prob * factor, 8);
4122
4123 cur_prob[coef_node_start
4124 / 4 * 2] =
4125 (cur_prob
4126 [coef_node_start
4127 / 4 * 2] & (~(0xff <<
4128 prob_shift))) |
4129 (new_prob <<
4130 prob_shift);
4131
4132 coef_node_start += 1;
4133 }
4134
4135 coef_cxt_start =
4136 coef_cxt_start + 3;
4137 coef_count_cxt_start =
4138 coef_count_cxt_start
4139 + 5;
4140 }
4141 if (band == 0) {
4142 coef_band_start += 10;
4143 coef_count_band_start += 15;
4144 } else {
4145 coef_band_start += 18;
4146 coef_count_band_start += 30;
4147 }
4148 }
4149 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4150 coef_count_type_start +=
4151 VP9_COEF_COUNT_SIZE_ONE_SET;
4152 }
4153 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4154 coef_count_plane_start +=
4155 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4156 }
4157 }
4158
4159 if (cur_kf == 0) {
4160 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4161 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4162 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4163 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4164
4165 if (coef_count_node_start ==
4166 VP9_INTRA_INTER_COUNT_START) {
4167 if (debug & VP9_DEBUG_MERGE)
4168 pr_info(" # merge_intra_inter_prob\n");
4169 coef_node_start = VP9_INTRA_INTER_START;
4170 } else if (coef_count_node_start ==
4171 VP9_COMP_INTER_COUNT_START) {
4172 if (debug & VP9_DEBUG_MERGE)
4173 pr_info(" # merge_comp_inter_prob\n");
4174 coef_node_start = VP9_COMP_INTER_START;
4175 }
4176 /*
4177 *else if (coef_count_node_start ==
4178 * VP9_COMP_REF_COUNT_START) {
4179 * pr_info(" # merge_comp_inter_prob\n");
4180 * coef_node_start = VP9_COMP_REF_START;
4181 *}
4182 *else if (coef_count_node_start ==
4183 * VP9_SINGLE_REF_COUNT_START) {
4184 * pr_info(" # merge_comp_inter_prob\n");
4185 * coef_node_start = VP9_SINGLE_REF_START;
4186 *}
4187 */
4188 else if (coef_count_node_start ==
4189 VP9_TX_MODE_COUNT_START) {
4190 if (debug & VP9_DEBUG_MERGE)
4191 pr_info(" # merge_tx_mode_probs\n");
4192 coef_node_start = VP9_TX_MODE_START;
4193 } else if (coef_count_node_start ==
4194 VP9_SKIP_COUNT_START) {
4195 if (debug & VP9_DEBUG_MERGE)
4196 pr_info(" # merge_skip_probs\n");
4197 coef_node_start = VP9_SKIP_START;
4198 } else if (coef_count_node_start ==
4199 VP9_MV_SIGN_0_COUNT_START) {
4200 if (debug & VP9_DEBUG_MERGE)
4201 pr_info(" # merge_sign_0\n");
4202 coef_node_start = VP9_MV_SIGN_0_START;
4203 } else if (coef_count_node_start ==
4204 VP9_MV_SIGN_1_COUNT_START) {
4205 if (debug & VP9_DEBUG_MERGE)
4206 pr_info(" # merge_sign_1\n");
4207 coef_node_start = VP9_MV_SIGN_1_START;
4208 } else if (coef_count_node_start ==
4209 VP9_MV_BITS_0_COUNT_START) {
4210 if (debug & VP9_DEBUG_MERGE)
4211 pr_info(" # merge_bits_0\n");
4212 coef_node_start = VP9_MV_BITS_0_START;
4213 } else if (coef_count_node_start ==
4214 VP9_MV_BITS_1_COUNT_START) {
4215 if (debug & VP9_DEBUG_MERGE)
4216 pr_info(" # merge_bits_1\n");
4217 coef_node_start = VP9_MV_BITS_1_START;
4218 } else if (coef_count_node_start ==
4219 VP9_MV_CLASS0_HP_0_COUNT_START) {
4220 if (debug & VP9_DEBUG_MERGE)
4221 pr_info(" # merge_class0_hp\n");
4222 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4223 }
4224
4225
4226 den = count[coef_count_node_start] +
4227 count[coef_count_node_start + 1];
4228
4229 prob_32 = prev_prob[coef_node_start / 4 * 2];
4230 prob_res = coef_node_start & 3;
4231 prob_shift = prob_res * 8;
4232 pre_prob = (prob_32 >> prob_shift) & 0xff;
4233
4234 if (den == 0)
4235 new_prob = pre_prob;
4236 else {
4237 m_count = (den < MODE_MV_COUNT_SAT) ?
4238 den : MODE_MV_COUNT_SAT;
4239 get_prob =
4240 clip_prob(
4241 div_r32(((int64_t)count[coef_count_node_start]
4242 * 256 + (den >> 1)),
4243 den));
4244 /*weighted_prob*/
4245 factor = count_to_update_factor[m_count];
4246 new_prob =
4247 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4248 + get_prob * factor, 8);
4249 }
4250 cur_prob[coef_node_start / 4 * 2] =
4251 (cur_prob[coef_node_start / 4 * 2] &
4252 (~(0xff << prob_shift)))
4253 | (new_prob << prob_shift);
4254
4255 coef_node_start = coef_node_start + 1;
4256 }
4257 if (debug & VP9_DEBUG_MERGE)
4258 pr_info(" # merge_vp9_inter_mode_tree\n");
4259 coef_node_start = VP9_INTER_MODE_START;
4260 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4261 for (tree_i = 0; tree_i < 7; tree_i++) {
4262 for (node = 0; node < 3; node++) {
4263 switch (node) {
4264 case 2:
4265 tree_left =
4266 count[coef_count_node_start + 1];
4267 tree_right =
4268 count[coef_count_node_start + 3];
4269 break;
4270 case 1:
4271 tree_left =
4272 count[coef_count_node_start + 0];
4273 tree_right =
4274 count[coef_count_node_start + 1]
4275 + count[coef_count_node_start + 3];
4276 break;
4277 default:
4278 tree_left =
4279 count[coef_count_node_start + 2];
4280 tree_right =
4281 count[coef_count_node_start + 0]
4282 + count[coef_count_node_start + 1]
4283 + count[coef_count_node_start + 3];
4284 break;
4285
4286 }
4287
4288 vp9_tree_merge_probs(prev_prob, cur_prob,
4289 coef_node_start, tree_left, tree_right,
4290 tree_i, node);
4291
4292 coef_node_start = coef_node_start + 1;
4293 }
4294 coef_count_node_start = coef_count_node_start + 4;
4295 }
4296 if (debug & VP9_DEBUG_MERGE)
4297 pr_info(" # merge_vp9_intra_mode_tree\n");
4298 coef_node_start = VP9_IF_Y_MODE_START;
4299 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4300 for (tree_i = 0; tree_i < 14; tree_i++) {
4301 for (node = 0; node < 9; node++) {
4302 switch (node) {
4303 case 8:
4304 tree_left =
4305 count[coef_count_node_start+D153_PRED];
4306 tree_right =
4307 count[coef_count_node_start+D207_PRED];
4308 break;
4309 case 7:
4310 tree_left =
4311 count[coef_count_node_start+D63_PRED];
4312 tree_right =
4313 count[coef_count_node_start+D207_PRED] +
4314 count[coef_count_node_start+D153_PRED];
4315 break;
4316 case 6:
4317 tree_left =
4318 count[coef_count_node_start + D45_PRED];
4319 tree_right =
4320 count[coef_count_node_start+D207_PRED] +
4321 count[coef_count_node_start+D153_PRED] +
4322 count[coef_count_node_start+D63_PRED];
4323 break;
4324 case 5:
4325 tree_left =
4326 count[coef_count_node_start+D135_PRED];
4327 tree_right =
4328 count[coef_count_node_start+D117_PRED];
4329 break;
4330 case 4:
4331 tree_left =
4332 count[coef_count_node_start+H_PRED];
4333 tree_right =
4334 count[coef_count_node_start+D117_PRED] +
4335 count[coef_count_node_start+D135_PRED];
4336 break;
4337 case 3:
4338 tree_left =
4339 count[coef_count_node_start+H_PRED] +
4340 count[coef_count_node_start+D117_PRED] +
4341 count[coef_count_node_start+D135_PRED];
4342 tree_right =
4343 count[coef_count_node_start+D45_PRED] +
4344 count[coef_count_node_start+D207_PRED] +
4345 count[coef_count_node_start+D153_PRED] +
4346 count[coef_count_node_start+D63_PRED];
4347 break;
4348 case 2:
4349 tree_left =
4350 count[coef_count_node_start+V_PRED];
4351 tree_right =
4352 count[coef_count_node_start+H_PRED] +
4353 count[coef_count_node_start+D117_PRED] +
4354 count[coef_count_node_start+D135_PRED] +
4355 count[coef_count_node_start+D45_PRED] +
4356 count[coef_count_node_start+D207_PRED] +
4357 count[coef_count_node_start+D153_PRED] +
4358 count[coef_count_node_start+D63_PRED];
4359 break;
4360 case 1:
4361 tree_left =
4362 count[coef_count_node_start+TM_PRED];
4363 tree_right =
4364 count[coef_count_node_start+V_PRED] +
4365 count[coef_count_node_start+H_PRED] +
4366 count[coef_count_node_start+D117_PRED] +
4367 count[coef_count_node_start+D135_PRED] +
4368 count[coef_count_node_start+D45_PRED] +
4369 count[coef_count_node_start+D207_PRED] +
4370 count[coef_count_node_start+D153_PRED] +
4371 count[coef_count_node_start+D63_PRED];
4372 break;
4373 default:
4374 tree_left =
4375 count[coef_count_node_start+DC_PRED];
4376 tree_right =
4377 count[coef_count_node_start+TM_PRED] +
4378 count[coef_count_node_start+V_PRED] +
4379 count[coef_count_node_start+H_PRED] +
4380 count[coef_count_node_start+D117_PRED] +
4381 count[coef_count_node_start+D135_PRED] +
4382 count[coef_count_node_start+D45_PRED] +
4383 count[coef_count_node_start+D207_PRED] +
4384 count[coef_count_node_start+D153_PRED] +
4385 count[coef_count_node_start+D63_PRED];
4386 break;
4387
4388 }
4389
4390 vp9_tree_merge_probs(prev_prob, cur_prob,
4391 coef_node_start, tree_left, tree_right,
4392 tree_i, node);
4393
4394 coef_node_start = coef_node_start + 1;
4395 }
4396 coef_count_node_start = coef_count_node_start + 10;
4397 }
4398
4399 if (debug & VP9_DEBUG_MERGE)
4400 pr_info(" # merge_vp9_partition_tree\n");
4401 coef_node_start = VP9_PARTITION_P_START;
4402 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4403 for (tree_i = 0; tree_i < 16; tree_i++) {
4404 for (node = 0; node < 3; node++) {
4405 switch (node) {
4406 case 2:
4407 tree_left =
4408 count[coef_count_node_start + 2];
4409 tree_right =
4410 count[coef_count_node_start + 3];
4411 break;
4412 case 1:
4413 tree_left =
4414 count[coef_count_node_start + 1];
4415 tree_right =
4416 count[coef_count_node_start + 2] +
4417 count[coef_count_node_start + 3];
4418 break;
4419 default:
4420 tree_left =
4421 count[coef_count_node_start + 0];
4422 tree_right =
4423 count[coef_count_node_start + 1] +
4424 count[coef_count_node_start + 2] +
4425 count[coef_count_node_start + 3];
4426 break;
4427
4428 }
4429
4430 vp9_tree_merge_probs(prev_prob, cur_prob,
4431 coef_node_start,
4432 tree_left, tree_right, tree_i, node);
4433
4434 coef_node_start = coef_node_start + 1;
4435 }
4436 coef_count_node_start = coef_count_node_start + 4;
4437 }
4438
4439 if (debug & VP9_DEBUG_MERGE)
4440 pr_info(" # merge_vp9_switchable_interp_tree\n");
4441 coef_node_start = VP9_INTERP_START;
4442 coef_count_node_start = VP9_INTERP_COUNT_START;
4443 for (tree_i = 0; tree_i < 4; tree_i++) {
4444 for (node = 0; node < 2; node++) {
4445 switch (node) {
4446 case 1:
4447 tree_left =
4448 count[coef_count_node_start + 1];
4449 tree_right =
4450 count[coef_count_node_start + 2];
4451 break;
4452 default:
4453 tree_left =
4454 count[coef_count_node_start + 0];
4455 tree_right =
4456 count[coef_count_node_start + 1] +
4457 count[coef_count_node_start + 2];
4458 break;
4459
4460 }
4461
4462 vp9_tree_merge_probs(prev_prob, cur_prob,
4463 coef_node_start,
4464 tree_left, tree_right, tree_i, node);
4465
4466 coef_node_start = coef_node_start + 1;
4467 }
4468 coef_count_node_start = coef_count_node_start + 3;
4469 }
4470
4471 if (debug & VP9_DEBUG_MERGE)
4472 pr_info("# merge_vp9_mv_joint_tree\n");
4473 coef_node_start = VP9_MV_JOINTS_START;
4474 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4475 for (tree_i = 0; tree_i < 1; tree_i++) {
4476 for (node = 0; node < 3; node++) {
4477 switch (node) {
4478 case 2:
4479 tree_left =
4480 count[coef_count_node_start + 2];
4481 tree_right =
4482 count[coef_count_node_start + 3];
4483 break;
4484 case 1:
4485 tree_left =
4486 count[coef_count_node_start + 1];
4487 tree_right =
4488 count[coef_count_node_start + 2] +
4489 count[coef_count_node_start + 3];
4490 break;
4491 default:
4492 tree_left =
4493 count[coef_count_node_start + 0];
4494 tree_right =
4495 count[coef_count_node_start + 1] +
4496 count[coef_count_node_start + 2] +
4497 count[coef_count_node_start + 3];
4498 break;
4499 }
4500
4501 vp9_tree_merge_probs(prev_prob, cur_prob,
4502 coef_node_start,
4503 tree_left, tree_right, tree_i, node);
4504
4505 coef_node_start = coef_node_start + 1;
4506 }
4507 coef_count_node_start = coef_count_node_start + 4;
4508 }
4509
4510 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4511 if (debug & VP9_DEBUG_MERGE)
4512 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4513 coef_node_start =
4514 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4515 coef_count_node_start =
4516 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4517 : VP9_MV_CLASSES_0_COUNT_START;
4518 tree_i = 0;
4519 for (node = 0; node < 10; node++) {
4520 switch (node) {
4521 case 9:
4522 tree_left =
4523 count[coef_count_node_start + 9];
4524 tree_right =
4525 count[coef_count_node_start + 10];
4526 break;
4527 case 8:
4528 tree_left =
4529 count[coef_count_node_start + 7];
4530 tree_right =
4531 count[coef_count_node_start + 8];
4532 break;
4533 case 7:
4534 tree_left =
4535 count[coef_count_node_start + 7] +
4536 count[coef_count_node_start + 8];
4537 tree_right =
4538 count[coef_count_node_start + 9] +
4539 count[coef_count_node_start + 10];
4540 break;
4541 case 6:
4542 tree_left =
4543 count[coef_count_node_start + 6];
4544 tree_right =
4545 count[coef_count_node_start + 7] +
4546 count[coef_count_node_start + 8] +
4547 count[coef_count_node_start + 9] +
4548 count[coef_count_node_start + 10];
4549 break;
4550 case 5:
4551 tree_left =
4552 count[coef_count_node_start + 4];
4553 tree_right =
4554 count[coef_count_node_start + 5];
4555 break;
4556 case 4:
4557 tree_left =
4558 count[coef_count_node_start + 4] +
4559 count[coef_count_node_start + 5];
4560 tree_right =
4561 count[coef_count_node_start + 6] +
4562 count[coef_count_node_start + 7] +
4563 count[coef_count_node_start + 8] +
4564 count[coef_count_node_start + 9] +
4565 count[coef_count_node_start + 10];
4566 break;
4567 case 3:
4568 tree_left =
4569 count[coef_count_node_start + 2];
4570 tree_right =
4571 count[coef_count_node_start + 3];
4572 break;
4573 case 2:
4574 tree_left =
4575 count[coef_count_node_start + 2] +
4576 count[coef_count_node_start + 3];
4577 tree_right =
4578 count[coef_count_node_start + 4] +
4579 count[coef_count_node_start + 5] +
4580 count[coef_count_node_start + 6] +
4581 count[coef_count_node_start + 7] +
4582 count[coef_count_node_start + 8] +
4583 count[coef_count_node_start + 9] +
4584 count[coef_count_node_start + 10];
4585 break;
4586 case 1:
4587 tree_left =
4588 count[coef_count_node_start + 1];
4589 tree_right =
4590 count[coef_count_node_start + 2] +
4591 count[coef_count_node_start + 3] +
4592 count[coef_count_node_start + 4] +
4593 count[coef_count_node_start + 5] +
4594 count[coef_count_node_start + 6] +
4595 count[coef_count_node_start + 7] +
4596 count[coef_count_node_start + 8] +
4597 count[coef_count_node_start + 9] +
4598 count[coef_count_node_start + 10];
4599 break;
4600 default:
4601 tree_left =
4602 count[coef_count_node_start + 0];
4603 tree_right =
4604 count[coef_count_node_start + 1] +
4605 count[coef_count_node_start + 2] +
4606 count[coef_count_node_start + 3] +
4607 count[coef_count_node_start + 4] +
4608 count[coef_count_node_start + 5] +
4609 count[coef_count_node_start + 6] +
4610 count[coef_count_node_start + 7] +
4611 count[coef_count_node_start + 8] +
4612 count[coef_count_node_start + 9] +
4613 count[coef_count_node_start + 10];
4614 break;
4615
4616 }
4617
4618 vp9_tree_merge_probs(prev_prob, cur_prob,
4619 coef_node_start, tree_left, tree_right,
4620 tree_i, node);
4621
4622 coef_node_start = coef_node_start + 1;
4623 }
4624
4625 if (debug & VP9_DEBUG_MERGE)
4626 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4627 coef_node_start =
4628 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4629 coef_count_node_start =
4630 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4631 VP9_MV_CLASS0_0_COUNT_START;
4632 tree_i = 0;
4633 node = 0;
4634 tree_left = count[coef_count_node_start + 0];
4635 tree_right = count[coef_count_node_start + 1];
4636
4637 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4638 tree_left, tree_right, tree_i, node);
4639 if (debug & VP9_DEBUG_MERGE)
4640 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4641 mvd_i);
4642 coef_node_start =
4643 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4644 VP9_MV_CLASS0_FP_0_START;
4645 coef_count_node_start =
4646 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4647 VP9_MV_CLASS0_FP_0_COUNT_START;
4648 for (tree_i = 0; tree_i < 3; tree_i++) {
4649 for (node = 0; node < 3; node++) {
4650 switch (node) {
4651 case 2:
4652 tree_left =
4653 count[coef_count_node_start + 2];
4654 tree_right =
4655 count[coef_count_node_start + 3];
4656 break;
4657 case 1:
4658 tree_left =
4659 count[coef_count_node_start + 1];
4660 tree_right =
4661 count[coef_count_node_start + 2]
4662 + count[coef_count_node_start + 3];
4663 break;
4664 default:
4665 tree_left =
4666 count[coef_count_node_start + 0];
4667 tree_right =
4668 count[coef_count_node_start + 1]
4669 + count[coef_count_node_start + 2]
4670 + count[coef_count_node_start + 3];
4671 break;
4672
4673 }
4674
4675 vp9_tree_merge_probs(prev_prob, cur_prob,
4676 coef_node_start, tree_left, tree_right,
4677 tree_i, node);
4678
4679 coef_node_start = coef_node_start + 1;
4680 }
4681 coef_count_node_start = coef_count_node_start + 4;
4682 }
4683
4684 } /* for mvd_i (mvd_y or mvd_x)*/
4685}
4686
4687}
4688
4689static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4690{
4691 int i;
4692 struct VP9_Common_s *const cm = &pbi->common;
4693 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4694
4695 for (i = 0; i < pbi->used_buf_num; ++i) {
4696 if (frame_bufs[i].buf.vframe_bound)
4697 return true;
4698 }
4699
4700 return false;
4701}
4702
4703static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4704{
4705 struct VP9_Common_s *const cm = &pbi->common;
4706 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4707 int i;
4708
4709 /* release workspace */
4710 if (pbi->bmmu_box)
4711 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4712 WORK_SPACE_BUF_ID);
4713 /*
4714 * it's only when vframe get back to driver, right now we can be sure
4715 * that vframe and fd are related. if the playback exits, the capture
4716 * requires the upper app to release when the fd is closed, and others
4717 * buffers drivers are released by driver.
4718 */
4719 for (i = 0; i < pbi->used_buf_num; ++i) {
4720 if (!frame_bufs[i].buf.vframe_bound) {
4721 if (pbi->bmmu_box)
4722 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4723 HEADER_BUFFER_IDX(i));
4724 if (pbi->mmu_box)
4725 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4726
4727 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4728 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4729 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4730 }
4731 }
4732}
4733
4734static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4735{
4736#ifndef MV_USE_FIXED_BUF
4737 dealloc_mv_bufs(pbi);
4738#endif
4739 if (pbi->is_used_v4l &&
4740 v4l_is_there_vframe_bound(pbi)) {
4741 if (get_double_write_mode(pbi) != 0x10) {
4742 v4l_mmu_buffer_release(pbi);
4743 return;
4744 }
4745 }
4746
4747 if (pbi->mmu_box)
4748 decoder_mmu_box_free(pbi->mmu_box);
4749 pbi->mmu_box = NULL;
4750
4751 if (pbi->bmmu_box)
4752 decoder_bmmu_box_free(pbi->bmmu_box);
4753 pbi->bmmu_box = NULL;
4754}
4755
4756static int calc_luc_quantity(u32 w, u32 h)
4757{
4758 int lcu_size = 64; /*fixed 64*/
4759 int pic_width_64 = (w + 63) & (~0x3f);
4760 int pic_height_32 = (h + 31) & (~0x1f);
4761 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4762 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4763 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4764 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4765
4766 return pic_width_lcu * pic_height_lcu;
4767}
4768
4769static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4770 struct PIC_BUFFER_CONFIG_s *pic)
4771{
4772 int ret = -1;
4773 int i = pic->index;
4774 int dw_mode = get_double_write_mode_init(pbi);
4775 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4776#ifdef MV_USE_FIXED_BUF
4777 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4778 pbi->work_space_buf->mpred_mv.buf_size;
4779#endif
4780 struct vdec_v4l2_buffer *fb = NULL;
4781
4782 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4783 if (ret < 0) {
4784 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4785 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4786 return ret;
4787 }
4788
4789 if (pbi->mmu_enable) {
4790 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4791 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4792 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4793 pr_info("MMU header_adr %d: %ld\n",
4794 i, pbi->m_BUF[i].header_addr);
4795 }
4796 }
4797
4798#ifdef MV_USE_FIXED_BUF
4799 if ((pbi->work_space_buf->mpred_mv.buf_start +
4800 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4801 <= mpred_mv_end) {
4802#endif
4803 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4804 pic->cma_alloc_addr = fb->m.mem[0].addr;
4805 if (fb->num_planes == 1) {
4806 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4807 pbi->m_BUF[i].size = fb->m.mem[0].size;
4808 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4809 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4810 } else if (fb->num_planes == 2) {
4811 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4812 pbi->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
4813 pbi->m_BUF[i].luma_size = fb->m.mem[0].size;
4814 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4815 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4816 }
4817
4818 /* config frame buffer */
4819 if (pbi->mmu_enable)
4820 pic->header_adr = pbi->m_BUF[i].header_addr;
4821
4822 pic->BUF_index = i;
4823 pic->lcu_total = lcu_total;
4824 pic->mc_canvas_y = pic->index;
4825 pic->mc_canvas_u_v = pic->index;
4826
4827 if (dw_mode & 0x10) {
4828 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4829 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4830 pic->mc_canvas_y = (pic->index << 1);
4831 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4832 } else if (dw_mode) {
4833 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4834 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4835 }
4836
4837#ifdef MV_USE_FIXED_BUF
4838 pic->mpred_mv_wr_start_addr =
4839 pbi->work_space_buf->mpred_mv.buf_start +
4840 ((pic->index * lcu_total) * MV_MEM_UNIT);
4841#endif
4842 if (debug) {
4843 pr_info("%s index %d BUF_index %d ",
4844 __func__, pic->index,
4845 pic->BUF_index);
4846 pr_info("comp_body_size %x comp_buf_size %x ",
4847 pic->comp_body_size,
4848 pic->buf_size);
4849 pr_info("mpred_mv_wr_start_adr %ld\n",
4850 pic->mpred_mv_wr_start_addr);
4851 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4852 pic->dw_y_adr,
4853 pic->dw_u_v_adr);
4854 }
4855#ifdef MV_USE_FIXED_BUF
4856 }
4857#endif
4858 return ret;
4859}
4860
4861static int config_pic(struct VP9Decoder_s *pbi,
4862 struct PIC_BUFFER_CONFIG_s *pic_config)
4863{
4864 int ret = -1;
4865 int i;
4866 int pic_width = pbi->init_pic_w;
4867 int pic_height = pbi->init_pic_h;
4868 int lcu_size = 64; /*fixed 64*/
4869 int pic_width_64 = (pic_width + 63) & (~0x3f);
4870 int pic_height_32 = (pic_height + 31) & (~0x1f);
4871 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4872 pic_width_64 / lcu_size + 1
4873 : pic_width_64 / lcu_size;
4874 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4875 pic_height_32 / lcu_size + 1
4876 : pic_height_32 / lcu_size;
4877 int lcu_total = pic_width_lcu * pic_height_lcu;
4878#ifdef MV_USE_FIXED_BUF
4879 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4880 pbi->work_space_buf->mpred_mv.buf_size;
4881#endif
4882 u32 y_adr = 0;
4883 int buf_size = 0;
4884
4885 int losless_comp_header_size =
4886 compute_losless_comp_header_size(pic_width,
4887 pic_height);
4888 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4889 pic_height, buf_alloc_depth == 10);
4890 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4891 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4892 int mc_buffer_size_u_v = 0;
4893 int mc_buffer_size_u_v_h = 0;
4894 int dw_mode = get_double_write_mode_init(pbi);
4895
4896 pbi->lcu_total = lcu_total;
4897
4898 if (dw_mode) {
4899 int pic_width_dw = pic_width /
4900 get_double_write_ratio(pbi, dw_mode);
4901 int pic_height_dw = pic_height /
4902 get_double_write_ratio(pbi, dw_mode);
4903
4904 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4905 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4906 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4907 pic_width_64_dw / lcu_size + 1
4908 : pic_width_64_dw / lcu_size;
4909 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4910 pic_height_32_dw / lcu_size + 1
4911 : pic_height_32_dw / lcu_size;
4912 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4913 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4914 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4915 /*64k alignment*/
4916 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4917 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4918 }
4919
4920 if (mc_buffer_size & 0xffff) /*64k alignment*/
4921 mc_buffer_size_h += 1;
4922 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4923 buf_size += (mc_buffer_size_h << 16);
4924
4925 if (pbi->mmu_enable) {
4926 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4927 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4928
4929 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4930 pr_info("MMU header_adr %d: %ld\n",
4931 pic_config->index, pic_config->header_adr);
4932 }
4933 }
4934
4935 i = pic_config->index;
4936#ifdef MV_USE_FIXED_BUF
4937 if ((pbi->work_space_buf->mpred_mv.buf_start +
4938 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4939 <= mpred_mv_end
4940 ) {
4941#endif
4942 if (buf_size > 0) {
4943 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4944 VF_BUFFER_IDX(i),
4945 buf_size, DRIVER_NAME,
4946 &pic_config->cma_alloc_addr);
4947 if (ret < 0) {
4948 pr_info(
4949 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4950 VF_BUFFER_IDX(i),
4951 buf_size
4952 );
4953 return ret;
4954 }
4955
4956 if (pic_config->cma_alloc_addr)
4957 y_adr = pic_config->cma_alloc_addr;
4958 else {
4959 pr_info(
4960 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4961 VF_BUFFER_IDX(i),
4962 buf_size
4963 );
4964 return -1;
4965 }
4966 }
4967 {
4968 /*ensure get_pic_by_POC()
4969 not get the buffer not decoded*/
4970 pic_config->BUF_index = i;
4971 pic_config->lcu_total = lcu_total;
4972
4973 pic_config->comp_body_size = losless_comp_body_size;
4974 pic_config->buf_size = buf_size;
4975
4976 pic_config->mc_canvas_y = pic_config->index;
4977 pic_config->mc_canvas_u_v = pic_config->index;
4978 if (dw_mode & 0x10) {
4979 pic_config->dw_y_adr = y_adr;
4980 pic_config->dw_u_v_adr = y_adr +
4981 ((mc_buffer_size_u_v_h << 16) << 1);
4982
4983 pic_config->mc_canvas_y =
4984 (pic_config->index << 1);
4985 pic_config->mc_canvas_u_v =
4986 (pic_config->index << 1) + 1;
4987 } else if (dw_mode) {
4988 pic_config->dw_y_adr = y_adr;
4989 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4990 ((mc_buffer_size_u_v_h << 16) << 1);
4991 }
4992#ifdef MV_USE_FIXED_BUF
4993 pic_config->mpred_mv_wr_start_addr =
4994 pbi->work_space_buf->mpred_mv.buf_start +
4995 ((pic_config->index * lcu_total)
4996 * MV_MEM_UNIT);
4997#endif
4998 if (debug) {
4999 pr_info
5000 ("%s index %d BUF_index %d ",
5001 __func__, pic_config->index,
5002 pic_config->BUF_index);
5003 pr_info
5004 ("comp_body_size %x comp_buf_size %x ",
5005 pic_config->comp_body_size,
5006 pic_config->buf_size);
5007 pr_info
5008 ("mpred_mv_wr_start_adr %ld\n",
5009 pic_config->mpred_mv_wr_start_addr);
5010 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
5011 pic_config->dw_y_adr,
5012 pic_config->dw_u_v_adr);
5013 }
5014 ret = 0;
5015 }
5016#ifdef MV_USE_FIXED_BUF
5017 }
5018#endif
5019 return ret;
5020}
5021
5022static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
5023{
5024 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5025 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5026 return (MMU_COMPRESS_8K_HEADER_SIZE);
5027
5028 return (MMU_COMPRESS_HEADER_SIZE);
5029}
5030
5031/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5032static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5033{
5034 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5035 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5036 return (MAX_FRAME_8K_NUM * 4);
5037
5038 return (MAX_FRAME_4K_NUM * 4);
5039}
5040
5041static void init_pic_list(struct VP9Decoder_s *pbi)
5042{
5043 int i;
5044 struct VP9_Common_s *cm = &pbi->common;
5045 struct PIC_BUFFER_CONFIG_s *pic_config;
5046 u32 header_size;
5047 struct vdec_s *vdec = hw_to_vdec(pbi);
5048
5049 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5050 header_size = vvp9_mmu_compress_header_size(pbi);
5051 /*alloc VP9 compress header first*/
5052 for (i = 0; i < pbi->used_buf_num; i++) {
5053 unsigned long buf_addr;
5054 if (decoder_bmmu_box_alloc_buf_phy
5055 (pbi->bmmu_box,
5056 HEADER_BUFFER_IDX(i), header_size,
5057 DRIVER_HEADER_NAME,
5058 &buf_addr) < 0) {
5059 pr_info("%s malloc compress header failed %d\n",
5060 DRIVER_HEADER_NAME, i);
5061 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5062 return;
5063 }
5064 }
5065 }
5066 for (i = 0; i < pbi->used_buf_num; i++) {
5067 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5068 pic_config->index = i;
5069 pic_config->BUF_index = -1;
5070 pic_config->mv_buf_index = -1;
5071 if (vdec->parallel_dec == 1) {
5072 pic_config->y_canvas_index = -1;
5073 pic_config->uv_canvas_index = -1;
5074 }
5075 pic_config->y_crop_width = pbi->init_pic_w;
5076 pic_config->y_crop_height = pbi->init_pic_h;
5077 pic_config->double_write_mode = get_double_write_mode(pbi);
5078
5079 if (!pbi->is_used_v4l) {
5080 if (config_pic(pbi, pic_config) < 0) {
5081 if (debug)
5082 pr_info("Config_pic %d fail\n",
5083 pic_config->index);
5084 pic_config->index = -1;
5085 break;
5086 }
5087
5088 if (pic_config->double_write_mode) {
5089 set_canvas(pbi, pic_config);
5090 }
5091 }
5092 }
5093 for (; i < pbi->used_buf_num; i++) {
5094 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5095 pic_config->index = -1;
5096 pic_config->BUF_index = -1;
5097 pic_config->mv_buf_index = -1;
5098 if (vdec->parallel_dec == 1) {
5099 pic_config->y_canvas_index = -1;
5100 pic_config->uv_canvas_index = -1;
5101 }
5102 }
5103 pr_info("%s ok, used_buf_num = %d\n",
5104 __func__, pbi->used_buf_num);
5105}
5106
5107static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5108{
5109 int i;
5110 struct VP9_Common_s *cm = &pbi->common;
5111 struct PIC_BUFFER_CONFIG_s *pic_config;
5112 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5113 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5114 (0x1 << 1) | (0x1 << 2));
5115
5116
5117 for (i = 0; i < pbi->used_buf_num; i++) {
5118 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5119 if (pic_config->index < 0)
5120 break;
5121
5122 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5123
5124 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5125 pic_config->header_adr >> 5);
5126 } else {
5127 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5128 * pic_config->mc_y_adr
5129 * | (pic_config->mc_canvas_y << 8) | 0x1);
5130 */
5131 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5132 pic_config->dw_y_adr >> 5);
5133 }
5134#ifndef LOSLESS_COMPRESS_MODE
5135 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5136 * pic_config->mc_u_v_adr
5137 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5138 */
5139 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5140 pic_config->header_adr >> 5);
5141#else
5142 if (pic_config->double_write_mode & 0x10) {
5143 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5144 pic_config->dw_u_v_adr >> 5);
5145 }
5146#endif
5147 }
5148 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5149
5150 /*Zero out canvas registers in IPP -- avoid simulation X*/
5151 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5152 (0 << 8) | (0 << 1) | 1);
5153 for (i = 0; i < 32; i++)
5154 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5155}
5156
5157
5158static void dump_pic_list(struct VP9Decoder_s *pbi)
5159{
5160 struct VP9_Common_s *const cm = &pbi->common;
5161 struct PIC_BUFFER_CONFIG_s *pic_config;
5162 int i;
5163 for (i = 0; i < FRAME_BUFFERS; i++) {
5164 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5165 vp9_print(pbi, 0,
5166 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5167 i,
5168 pic_config->index,
5169#ifndef MV_USE_FIXED_BUF
5170 pic_config->mv_buf_index,
5171#else
5172 -1,
5173#endif
5174 cm->buffer_pool->
5175 frame_bufs[i].ref_count,
5176 pic_config->vf_ref,
5177 pic_config->decode_idx,
5178 pic_config->slice_type,
5179 pic_config->y_crop_width,
5180 pic_config->y_crop_height,
5181 pic_config->cma_alloc_addr
5182 );
5183 }
5184 return;
5185}
5186
5187static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5188{
5189#ifdef LOSLESS_COMPRESS_MODE
5190 unsigned int data32;
5191#endif
5192 int losless_comp_header_size, losless_comp_body_size;
5193 struct VP9_Common_s *cm = &pbi->common;
5194 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5195
5196 frame_width = cur_pic_config->y_crop_width;
5197 frame_height = cur_pic_config->y_crop_height;
5198 cur_pic_config->bit_depth = bit_depth;
5199 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5200 losless_comp_header_size =
5201 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5202 cur_pic_config->y_crop_height);
5203 losless_comp_body_size =
5204 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5205 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5206 cur_pic_config->comp_body_size = losless_comp_body_size;
5207#ifdef LOSLESS_COMPRESS_MODE
5208 data32 = READ_VREG(HEVC_SAO_CTRL5);
5209 if (bit_depth == VPX_BITS_10)
5210 data32 &= ~(1 << 9);
5211 else
5212 data32 |= (1 << 9);
5213
5214 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5215
5216 if (pbi->mmu_enable) {
5217 /*bit[4] : paged_mem_mode*/
5218 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5219 } else {
5220 /*bit[3] smem mdoe*/
5221 if (bit_depth == VPX_BITS_10)
5222 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5223 else
5224 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5225 }
5226 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5227 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5228 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5229 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5230 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5231 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5232 if (get_double_write_mode(pbi) & 0x10)
5233 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5234#else
5235 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5236#endif
5237 return 0;
5238}
5239
5240static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5241{
5242 int i;
5243 struct VP9_Common_s *cm = &pbi->common;
5244 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5245 uint8_t scale_enable = 0;
5246
5247 if (debug&VP9_DEBUG_BUFMGR_MORE)
5248 pr_info("config_mc_buffer entered .....\n");
5249
5250 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5251 (0 << 8) | (0 << 1) | 1);
5252 for (i = 0; i < REFS_PER_FRAME; ++i) {
5253 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5254 if (!pic_config)
5255 continue;
5256 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5257 (pic_config->mc_canvas_u_v << 16)
5258 | (pic_config->mc_canvas_u_v << 8)
5259 | pic_config->mc_canvas_y);
5260 if (debug & VP9_DEBUG_BUFMGR_MORE)
5261 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5262 i, pic_config->mc_canvas_u_v,
5263 pic_config->mc_canvas_y);
5264 }
5265 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5266 (16 << 8) | (0 << 1) | 1);
5267 for (i = 0; i < REFS_PER_FRAME; ++i) {
5268 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5269 if (!pic_config)
5270 continue;
5271 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5272 (pic_config->mc_canvas_u_v << 16)
5273 | (pic_config->mc_canvas_u_v << 8)
5274 | pic_config->mc_canvas_y);
5275 }
5276
5277 /*auto_inc start index:0 field:0*/
5278 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5279 /*index 0:last 1:golden 2:altref*/
5280 for (i = 0; i < REFS_PER_FRAME; i++) {
5281 int ref_pic_body_size;
5282 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5283 if (!pic_config)
5284 continue;
5285 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5286 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5287
5288 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5289 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5290 scale_enable |= (1 << i);
5291 }
5292 ref_pic_body_size =
5293 compute_losless_comp_body_size(pic_config->y_crop_width,
5294 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5295 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5296 (pic_config->y_crop_width << 14)
5297 / cur_pic_config->y_crop_width);
5298 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5299 (pic_config->y_crop_height << 14)
5300 / cur_pic_config->y_crop_height);
5301 if (pbi->mmu_enable)
5302 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5303 else
5304 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5305 }
5306 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5307 return 0;
5308}
5309
5310static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5311{
5312 unsigned int data32;
5313
5314 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5315 data32 &= (~(1 << 6));
5316 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5317}
5318
5319static void config_mpred_hw(struct VP9Decoder_s *pbi)
5320{
5321 struct VP9_Common_s *cm = &pbi->common;
5322 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5323 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5324 &cm->prev_frame->buf;
5325
5326 unsigned int data32;
5327 int mpred_curr_lcu_x;
5328 int mpred_curr_lcu_y;
5329 int mpred_mv_rd_end_addr;
5330
5331
5332 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5333 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5334
5335 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5336 mpred_curr_lcu_x = data32 & 0xffff;
5337 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5338
5339 if (debug & VP9_DEBUG_BUFMGR)
5340 pr_info("cur pic_config index %d col pic_config index %d\n",
5341 cur_pic_config->index, last_frame_pic_config->index);
5342 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5343 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5344 pbi->work_space_buf->mpred_above.buf_start);
5345
5346 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5347
5348 data32 &= (~(1 << 6));
5349 data32 |= (cm->use_prev_frame_mvs << 6);
5350 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5351
5352 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5353 cur_pic_config->mpred_mv_wr_start_addr);
5354 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5355
5356 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5357 last_frame_pic_config->mpred_mv_wr_start_addr);
5358 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5359 last_frame_pic_config->mpred_mv_wr_start_addr);
5360 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5361 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5362 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5363 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5364
5365}
5366
5367static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5368{
5369 struct VP9_Common_s *cm = &pbi->common;
5370 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5371
5372 unsigned int data32;
5373 int lcu_size = 64;
5374 int mc_buffer_size_u_v =
5375 pic_config->lcu_total * lcu_size*lcu_size/2;
5376 int mc_buffer_size_u_v_h =
5377 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5378 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5379
5380 if (get_double_write_mode(pbi)) {
5381 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5382 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5383 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5384 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5385 } else {
5386 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5387 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5388 }
5389 if (pbi->mmu_enable)
5390 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5391
5392 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5393 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5394 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5395 */
5396 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5397
5398 data32 = (mc_buffer_size_u_v_h << 16);
5399 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5400
5401#ifdef VP9_10B_NV21
5402#ifdef DOS_PROJECT
5403 data32 = READ_VREG(HEVC_SAO_CTRL1);
5404 data32 &= (~0x3000);
5405 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5406 data32 |= (pbi->mem_map_mode << 12);
5407 data32 &= (~0x3);
5408 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5409 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5410 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5411 * [17:16] dw_h0_ctrl
5412 */
5413 data32 = READ_VREG(HEVC_SAO_CTRL5);
5414 /*set them all 0 for H265_NV21 (no down-scale)*/
5415 data32 &= ~(0xff << 16);
5416 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5417 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5418 data32 &= (~0x30);
5419 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5420 data32 |= (pbi->mem_map_mode << 4);
5421 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5422#else
5423 /*m8baby test1902*/
5424 data32 = READ_VREG(HEVC_SAO_CTRL1);
5425 data32 &= (~0x3000);
5426 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5427 data32 |= (pbi->mem_map_mode << 12);
5428 data32 &= (~0xff0);
5429 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5430 data32 |= 0x880; /*.Big-Endian per 64-bit */
5431 data32 &= (~0x3);
5432 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5433 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5434 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5435 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5436 */
5437 data32 = READ_VREG(HEVC_SAO_CTRL5);
5438 /* set them all 0 for H265_NV21 (no down-scale)*/
5439 data32 &= ~(0xff << 16);
5440 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5441
5442 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5443 data32 &= (~0x30);
5444 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5445 data32 |= (pbi->mem_map_mode << 4);
5446 data32 &= (~0xF);
5447 data32 |= 0x8; /*Big-Endian per 64-bit*/
5448 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5449#endif
5450#else
5451 data32 = READ_VREG(HEVC_SAO_CTRL1);
5452 data32 &= (~0x3000);
5453 data32 |= (pbi->mem_map_mode <<
5454 12);
5455
5456/* [13:12] axi_aformat, 0-Linear,
5457 * 1-32x32, 2-64x32
5458 */
5459 data32 &= (~0xff0);
5460 /* data32 |= 0x670; // Big-Endian per 64-bit */
5461 data32 |= endian; /* Big-Endian per 64-bit */
5462 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5463 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5464 if (get_double_write_mode(pbi) == 0)
5465 data32 |= 0x2; /*disable double write*/
5466 else if (get_double_write_mode(pbi) & 0x10)
5467 data32 |= 0x1; /*disable cm*/
5468 } else { /* >= G12A dw write control */
5469 unsigned int data;
5470 data = READ_VREG(HEVC_DBLK_CFGB);
5471 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5472 if (get_double_write_mode(pbi) == 0)
5473 data |= (0x1 << 8); /*enable first write*/
5474 else if (get_double_write_mode(pbi) & 0x10)
5475 data |= (0x1 << 9); /*double write only*/
5476 else
5477 data |= ((0x1 << 8) |(0x1 << 9));
5478 WRITE_VREG(HEVC_DBLK_CFGB, data);
5479 }
5480
5481 /* swap uv */
5482 if (pbi->is_used_v4l) {
5483 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5484 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5485 data32 &= ~(1 << 8); /* NV21 */
5486 else
5487 data32 |= (1 << 8); /* NV12 */
5488 }
5489
5490 /*
5491 * [31:24] ar_fifo1_axi_thred
5492 * [23:16] ar_fifo0_axi_thred
5493 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5494 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5495 * [11:08] axi_lendian_C
5496 * [07:04] axi_lendian_Y
5497 * [3] reserved
5498 * [2] clk_forceon
5499 * [1] dw_disable:disable double write output
5500 * [0] cm_disable:disable compress output
5501 */
5502 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5503
5504 if (get_double_write_mode(pbi) & 0x10) {
5505 /* [23:22] dw_v1_ctrl
5506 *[21:20] dw_v0_ctrl
5507 *[19:18] dw_h1_ctrl
5508 *[17:16] dw_h0_ctrl
5509 */
5510 data32 = READ_VREG(HEVC_SAO_CTRL5);
5511 /*set them all 0 for H265_NV21 (no down-scale)*/
5512 data32 &= ~(0xff << 16);
5513 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5514 } else {
5515 data32 = READ_VREG(HEVC_SAO_CTRL5);
5516 data32 &= (~(0xff << 16));
5517 if (get_double_write_mode(pbi) == 2 ||
5518 get_double_write_mode(pbi) == 3)
5519 data32 |= (0xff<<16);
5520 else if (get_double_write_mode(pbi) == 4)
5521 data32 |= (0x33<<16);
5522 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5523 }
5524
5525 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5526 data32 &= (~0x30);
5527 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5528 data32 |= (pbi->mem_map_mode <<
5529 4);
5530 data32 &= (~0xF);
5531 data32 |= 0xf; /* valid only when double write only */
5532 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5533
5534 /* swap uv */
5535 if (pbi->is_used_v4l) {
5536 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5537 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5538 data32 |= (1 << 12); /* NV21 */
5539 else
5540 data32 &= ~(1 << 12); /* NV12 */
5541 }
5542
5543 /*
5544 * [3:0] little_endian
5545 * [5:4] address_format 00:linear 01:32x32 10:64x32
5546 * [7:6] reserved
5547 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5548 * [11:10] reserved
5549 * [12] CbCr_byte_swap
5550 * [31:13] reserved
5551 */
5552 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5553#endif
5554}
5555
5556static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5557{
5558 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5559 unsigned int data32;
5560
5561 if (debug && pbi->init_flag == 0)
5562 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5563 __func__,
5564 buf_spec->ipp.buf_start,
5565 buf_spec->start_adr,
5566 buf_spec->short_term_rps.buf_start,
5567 buf_spec->vps.buf_start,
5568 buf_spec->sps.buf_start,
5569 buf_spec->pps.buf_start,
5570 buf_spec->sao_up.buf_start,
5571 buf_spec->swap_buf.buf_start,
5572 buf_spec->swap_buf2.buf_start,
5573 buf_spec->scalelut.buf_start,
5574 buf_spec->dblk_para.buf_start,
5575 buf_spec->dblk_data.buf_start);
5576
5577 if (mask & HW_MASK_FRONT) {
5578 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5579 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5580
5581 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5582 buf_spec->short_term_rps.buf_start);
5583 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5584 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5585 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5586 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5587 buf_spec->swap_buf.buf_start);
5588 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5589 buf_spec->swap_buf2.buf_start);
5590 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5591
5592 }
5593
5594 if (mask & HW_MASK_BACK) {
5595#ifdef LOSLESS_COMPRESS_MODE
5596 int losless_comp_header_size =
5597 compute_losless_comp_header_size(pbi->init_pic_w,
5598 pbi->init_pic_h);
5599 int losless_comp_body_size =
5600 compute_losless_comp_body_size(pbi->init_pic_w,
5601 pbi->init_pic_h, buf_alloc_depth == 10);
5602#endif
5603 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5604 buf_spec->ipp.buf_start);
5605 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5606 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5607 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5608 /* cfg_addr_adp*/
5609 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5610 if (debug & VP9_DEBUG_BUFMGR_MORE)
5611 pr_info("Write HEVC_DBLK_CFGE\n");
5612 }
5613 /* cfg_p_addr */
5614 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5615 /* cfg_d_addr */
5616 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5617
5618 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5619 /*
5620 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5621 * data32 = data32 * 2;
5622 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5623 * data32 = data32 * 2;
5624 */
5625 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5626 }
5627#ifdef LOSLESS_COMPRESS_MODE
5628 if (pbi->mmu_enable) {
5629 /*bit[4] : paged_mem_mode*/
5630 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5631 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5632 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5633 } else {
5634 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5635 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5636 */
5637 /*bit[3] smem mdoe*/
5638 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5639 /*bit[3] smem mdoe*/
5640 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5641 (losless_comp_body_size >> 5));
5642 }
5643 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5644 (losless_comp_body_size >> 5));*/
5645 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5646 (0xff<<20) | (0xff<<10) | 0xff);*/
5647 /*8-bit mode */
5648 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5649 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5650 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5651 if (get_double_write_mode(pbi) & 0x10)
5652 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5653#else
5654 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5655#endif
5656
5657 if (pbi->mmu_enable) {
5658 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5659 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5660 + buf_spec->mmu_vbh.buf_size/2);
5661 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5662 /*data32 |= 0x1;*/
5663 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5664
5665 /* use HEVC_CM_HEADER_START_ADDR */
5666 data32 = READ_VREG(HEVC_SAO_CTRL5);
5667 data32 |= (1<<10);
5668 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5669 }
5670
5671 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5672
5673 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5674 /**/
5675 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5676 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5677 if (pbi->mmu_enable) {
5678 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5679 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5680 else
5681 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5682 }
5683 }
5684}
5685
5686
5687#ifdef VP9_LPF_LVL_UPDATE
5688/*
5689 * Defines, declarations, sub-functions for vp9 de-block loop
5690 filter Thr/Lvl table update
5691 * - struct segmentation is for loop filter only (removed something)
5692 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5693 be instantiated in C_Entry
5694 * - vp9_loop_filter_init run once before decoding start
5695 * - vp9_loop_filter_frame_init run before every frame decoding start
5696 * - set video format to VP9 is in vp9_loop_filter_init
5697 */
5698#define MAX_LOOP_FILTER 63
5699#define MAX_REF_LF_DELTAS 4
5700#define MAX_MODE_LF_DELTAS 2
5701/*#define INTRA_FRAME 0*/
5702/*#define LAST_FRAME 1*/
5703/*#define MAX_REF_FRAMES 4*/
5704#define SEGMENT_DELTADATA 0
5705#define SEGMENT_ABSDATA 1
5706#define MAX_SEGMENTS 8
5707/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5708/*no use for loop filter, if this struct for common use, pls add it back*/
5709/*#define PREDICTION_PROBS 3*/
5710/* no use for loop filter, if this struct for common use, pls add it back*/
5711
5712enum SEG_LVL_FEATURES {
5713 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5714 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5715 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5716 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5717 SEG_LVL_MAX = 4 /*Number of features supported*/
5718};
5719
5720struct segmentation {
5721 uint8_t enabled;
5722 uint8_t update_map;
5723 uint8_t update_data;
5724 uint8_t abs_delta;
5725 uint8_t temporal_update;
5726
5727 /*no use for loop filter, if this struct
5728 *for common use, pls add it back
5729 */
5730 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5731 /* no use for loop filter, if this struct
5732 * for common use, pls add it back
5733 */
5734 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5735
5736 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5737 unsigned int feature_mask[MAX_SEGMENTS];
5738};
5739
5740struct loop_filter_thresh {
5741 uint8_t mblim;
5742 uint8_t lim;
5743 uint8_t hev_thr;
5744};
5745
5746struct loop_filter_info_n {
5747 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5748 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5749};
5750
5751struct loopfilter {
5752 int filter_level;
5753
5754 int sharpness_level;
5755 int last_sharpness_level;
5756
5757 uint8_t mode_ref_delta_enabled;
5758 uint8_t mode_ref_delta_update;
5759
5760 /*0 = Intra, Last, GF, ARF*/
5761 signed char ref_deltas[MAX_REF_LF_DELTAS];
5762 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5763
5764 /*0 = ZERO_MV, MV*/
5765 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5766 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5767};
5768
5769static int vp9_clamp(int value, int low, int high)
5770{
5771 return value < low ? low : (value > high ? high : value);
5772}
5773
5774int segfeature_active(struct segmentation *seg,
5775 int segment_id,
5776 enum SEG_LVL_FEATURES feature_id) {
5777 return seg->enabled &&
5778 (seg->feature_mask[segment_id] & (1 << feature_id));
5779}
5780
5781int get_segdata(struct segmentation *seg, int segment_id,
5782 enum SEG_LVL_FEATURES feature_id) {
5783 return seg->feature_data[segment_id][feature_id];
5784}
5785
5786static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5787 int sharpness_lvl)
5788{
5789 int lvl;
5790 /*For each possible value for the loop filter fill out limits*/
5791 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5792 /*Set loop filter parameters that control sharpness.*/
5793 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5794 (sharpness_lvl > 4));
5795
5796 if (sharpness_lvl > 0) {
5797 if (block_inside_limit > (9 - sharpness_lvl))
5798 block_inside_limit = (9 - sharpness_lvl);
5799 }
5800
5801 if (block_inside_limit < 1)
5802 block_inside_limit = 1;
5803
5804 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5805 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5806 block_inside_limit);
5807 }
5808}
5809
5810/*instantiate this function once when decode is started*/
5811void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5812{
5813 struct loop_filter_info_n *lfi = pbi->lfi;
5814 struct loopfilter *lf = pbi->lf;
5815 struct segmentation *seg_4lf = pbi->seg_4lf;
5816 int i;
5817 unsigned int data32;
5818
5819 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5820 memset(lf, 0, sizeof(struct loopfilter));
5821 memset(seg_4lf, 0, sizeof(struct segmentation));
5822 lf->sharpness_level = 0; /*init to 0 */
5823 /*init limits for given sharpness*/
5824 vp9_update_sharpness(lfi, lf->sharpness_level);
5825 lf->last_sharpness_level = lf->sharpness_level;
5826 /*init hev threshold const vectors (actually no use)
5827 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5828 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5829 */
5830
5831 /*Write to register*/
5832 for (i = 0; i < 32; i++) {
5833 unsigned int thr;
5834
5835 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5836 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5837 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5838 (lfi->lfthr[i * 2].mblim & 0xff);
5839 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5840 }
5841
5842 /*video format is VP9*/
5843 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5844 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5845 (0x3 << 12) | // (dw fifo thres r or b)
5846 (0x3 << 10) | // (dw fifo thres not r/b)
5847 (0x3 << 8) | // 1st/2nd write both enable
5848 (0x1 << 0); // vp9 video format
5849 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5850 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5851 (0x1 << 0); /*vp9 video format*/
5852 } else
5853 data32 = 0x40400001;
5854
5855 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5856 if (debug & VP9_DEBUG_BUFMGR_MORE)
5857 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5858}
5859 /* perform this function per frame*/
5860void vp9_loop_filter_frame_init(struct segmentation *seg,
5861 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5862 int default_filt_lvl) {
5863 int i;
5864 int seg_id;
5865 /*n_shift is the multiplier for lf_deltas
5866 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5867 *2 when filter_lvl is between 32 and 63
5868 */
5869 const int scale = 1 << (default_filt_lvl >> 5);
5870
5871 /*update limits if sharpness has changed*/
5872 if (lf->last_sharpness_level != lf->sharpness_level) {
5873 vp9_update_sharpness(lfi, lf->sharpness_level);
5874 lf->last_sharpness_level = lf->sharpness_level;
5875
5876 /*Write to register*/
5877 for (i = 0; i < 32; i++) {
5878 unsigned int thr;
5879
5880 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5881 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5882 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5883 | (lfi->lfthr[i * 2].mblim & 0xff);
5884 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5885 }
5886 }
5887
5888 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5889 int lvl_seg = default_filt_lvl;
5890
5891 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5892 const int data = get_segdata(seg, seg_id,
5893 SEG_LVL_ALT_LF);
5894 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5895 data : default_filt_lvl + data,
5896 0, MAX_LOOP_FILTER);
5897#ifdef DBG_LF_PRINT
5898 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5899#endif
5900 }
5901
5902 if (!lf->mode_ref_delta_enabled) {
5903 /*we could get rid of this if we assume that deltas are set to
5904 *zero when not in use; encoder always uses deltas
5905 */
5906 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5907 } else {
5908 int ref, mode;
5909 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5910 * scale;
5911#ifdef DBG_LF_PRINT
5912 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5913 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5914#endif
5915 lfi->lvl[seg_id][INTRA_FRAME][0] =
5916 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5917
5918 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5919 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5920 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5921 /*MAX_MODE_LF_DELTAS = 2*/
5922 const int inter_lvl =
5923 lvl_seg + lf->ref_deltas[ref] * scale
5924 + lf->mode_deltas[mode] * scale;
5925#ifdef DBG_LF_PRINT
5926#endif
5927 lfi->lvl[seg_id][ref][mode] =
5928 vp9_clamp(inter_lvl, 0,
5929 MAX_LOOP_FILTER);
5930 }
5931 }
5932 }
5933 }
5934
5935#ifdef DBG_LF_PRINT
5936 /*print out thr/lvl table per frame*/
5937 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5938 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5939 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5940 lfi->lfthr[i].lim);
5941 }
5942 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5943 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5944 seg_id, lfi->lvl[seg_id][0][0],
5945 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5946 lfi->lvl[seg_id][3][0]);
5947 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5948 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5949 lfi->lvl[seg_id][3][1]);
5950 }
5951#endif
5952
5953 /*Write to register */
5954 for (i = 0; i < 16; i++) {
5955 unsigned int level;
5956
5957 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5958 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5959 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5960 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5961 if (!default_filt_lvl)
5962 level = 0;
5963 WRITE_VREG(HEVC_DBLK_CFGA, level);
5964 }
5965}
5966/* VP9_LPF_LVL_UPDATE */
5967#endif
5968
5969static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5970{
5971 unsigned int data32;
5972 int i;
5973 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5974 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5975 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5976 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5977 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5978 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5979 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5980 0x7C00
5981 };
5982#if 0
5983 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5984 /* Set MCR fetch priorities*/
5985 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5986 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5987 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5988 }
5989#endif
5990 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
5991 pr_info("%s\n", __func__);*/
5992 if (mask & HW_MASK_FRONT) {
5993 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5994#if 1
5995 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5996 data32 &= ~(7 << 29);
5997 data32 |= (3 << 29);
5998#endif
5999 data32 = data32 |
6000 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
6001 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
6002 (1 << 7) |/*dec_done_int_cpu_enable*/
6003 (1 << 4) |/*startcode_found_int_cpu_enable*/
6004 (0 << 3) |/*startcode_found_int_amrisc_enable*/
6005 (1 << 0) /*parser_int_enable*/
6006 ;
6007#ifdef SUPPORT_FB_DECODING
6008#ifndef FB_DECODING_TEST_SCHEDULE
6009 /*fed_fb_slice_done_int_cpu_enable*/
6010 if (pbi->used_stage_buf_num > 0)
6011 data32 |= (1 << 10);
6012#endif
6013#endif
6014 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
6015
6016 data32 = READ_VREG(HEVC_SHIFT_STATUS);
6017 data32 = data32 |
6018 (0 << 1) |/*emulation_check_off VP9
6019 do not have emulation*/
6020 (1 << 0)/*startcode_check_on*/
6021 ;
6022 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
6023 WRITE_VREG(HEVC_SHIFT_CONTROL,
6024 (0 << 14) | /*disable_start_code_protect*/
6025 (1 << 10) | /*length_zero_startcode_en for VP9*/
6026 (1 << 9) | /*length_valid_startcode_en for VP9*/
6027 (3 << 6) | /*sft_valid_wr_position*/
6028 (2 << 4) | /*emulate_code_length_sub_1*/
6029 (3 << 1) | /*start_code_length_sub_1
6030 VP9 use 0x00000001 as startcode (4 Bytes)*/
6031 (1 << 0) /*stream_shift_enable*/
6032 );
6033
6034 WRITE_VREG(HEVC_CABAC_CONTROL,
6035 (1 << 0)/*cabac_enable*/
6036 );
6037
6038 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6039 (1 << 0)/* hevc_parser_core_clk_en*/
6040 );
6041
6042
6043 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6044
6045 }
6046
6047 if (mask & HW_MASK_BACK) {
6048 /*Initial IQIT_SCALELUT memory
6049 -- just to avoid X in simulation*/
6050
6051 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6052 for (i = 0; i < 1024; i++)
6053 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6054 }
6055
6056 if (mask & HW_MASK_FRONT) {
6057 u32 decode_mode;
6058#ifdef ENABLE_SWAP_TEST
6059 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6060#else
6061 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6062#endif
6063#ifdef MULTI_INSTANCE_SUPPORT
6064 if (!pbi->m_ins_flag) {
6065 if (pbi->low_latency_flag)
6066 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6067 else
6068 decode_mode = DECODE_MODE_SINGLE;
6069 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6070 decode_mode = pbi->no_head ?
6071 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6072 DECODE_MODE_MULTI_FRAMEBASE;
6073 else
6074 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6075#ifdef SUPPORT_FB_DECODING
6076#ifndef FB_DECODING_TEST_SCHEDULE
6077 if (pbi->used_stage_buf_num > 0)
6078 decode_mode |= (0x01 << 24);
6079#endif
6080#endif
6081 WRITE_VREG(DECODE_MODE, decode_mode);
6082 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6083 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6084#else
6085 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6086 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6087 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6088#endif
6089 /*Send parser_cmd*/
6090 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6091 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6092 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6093 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6094 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6095 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6096
6097
6098 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6099 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6100 (1 << 5) | /*parser_sao_if_en*/
6101 (1 << 2) | /*parser_mpred_if_en*/
6102 (1 << 0) /*parser_scaler_if_en*/
6103 );
6104 }
6105
6106 if (mask & HW_MASK_BACK) {
6107 /*Changed to Start MPRED in microcode*/
6108 /*
6109 pr_info("[test.c] Start MPRED\n");
6110 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6111 (1<<31)
6112 );
6113 */
6114 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6115 (0 << 1) | /*enable ipp*/
6116 (1 << 0) /*software reset ipp and mpp*/
6117 );
6118 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6119 (1 << 1) | /*enable ipp*/
6120 (0 << 0) /*software reset ipp and mpp*/
6121 );
6122 if (get_double_write_mode(pbi) & 0x10) {
6123 /*Enable NV21 reference read mode for MC*/
6124 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6125 }
6126
6127 /*Initialize mcrcc and decomp perf counters*/
6128 if (mcrcc_cache_alg_flag &&
6129 pbi->init_flag == 0) {
6130 mcrcc_perfcount_reset();
6131 decomp_perfcount_reset();
6132 }
6133 }
6134 return;
6135}
6136
6137
6138#ifdef CONFIG_HEVC_CLK_FORCED_ON
6139static void config_vp9_clk_forced_on(void)
6140{
6141 unsigned int rdata32;
6142 /*IQIT*/
6143 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6144 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6145
6146 /* DBLK*/
6147 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6148 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6149
6150 /* SAO*/
6151 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6152 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6153
6154 /*MPRED*/
6155 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6156 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6157
6158 /* PARSER*/
6159 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6160 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6161 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6162 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6163 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6164 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6165 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6166 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6167 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6168 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6169 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6170 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6171 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6172
6173 /*IPP*/
6174 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6175 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6176
6177 /* MCRCC*/
6178 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6179 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6180}
6181#endif
6182
6183
6184#ifdef MCRCC_ENABLE
6185static void dump_hit_rate(struct VP9Decoder_s *pbi)
6186{
6187 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6188 mcrcc_get_hitrate(pbi->m_ins_flag);
6189 decomp_get_hitrate();
6190 decomp_get_comprate();
6191 }
6192}
6193
6194static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6195{
6196 unsigned int rdata32;
6197 unsigned short is_inter;
6198 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6199 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6200 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6201 (!pbi->common.intra_only)) ? 1 : 0;
6202 if (!is_inter) { /* I-PIC*/
6203 /*remove reset -- disables clock*/
6204 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6205 return;
6206 }
6207
6208 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6209 mcrcc_get_hitrate(pbi->m_ins_flag);
6210 decomp_get_hitrate();
6211 decomp_get_comprate();
6212 }
6213
6214 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6215 (0 << 8) | (1 << 1) | 0);
6216 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6217 rdata32 = rdata32 & 0xffff;
6218 rdata32 = rdata32 | (rdata32 << 16);
6219 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6220 /*Programme canvas1 */
6221 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6222 rdata32 = rdata32 & 0xffff;
6223 rdata32 = rdata32 | (rdata32 << 16);
6224 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6225 /*enable mcrcc progressive-mode*/
6226 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6227}
6228
6229static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6230{
6231 u32 curr_picnum = -1;
6232 u32 lastref_picnum = -1;
6233 u32 goldenref_picnum = -1;
6234 u32 altref_picnum = -1;
6235
6236 u32 lastref_delta_picnum;
6237 u32 goldenref_delta_picnum;
6238 u32 altref_delta_picnum;
6239
6240 u32 rdata32;
6241
6242 u32 lastcanvas;
6243 u32 goldencanvas;
6244 u32 altrefcanvas;
6245
6246 u16 is_inter;
6247 u16 lastref_inref;
6248 u16 goldenref_inref;
6249 u16 altref_inref;
6250
6251 u32 refcanvas_array[3], utmp;
6252 int deltapicnum_array[3], tmp;
6253
6254 struct VP9_Common_s *cm = &pbi->common;
6255 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6256 = &cm->cur_frame->buf;
6257 curr_picnum = cur_pic_config->decode_idx;
6258 if (cm->frame_refs[0].buf)
6259 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6260 if (cm->frame_refs[1].buf)
6261 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6262 if (cm->frame_refs[2].buf)
6263 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6264
6265 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6266 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6267 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6268 (goldenref_picnum - curr_picnum) :
6269 (curr_picnum - goldenref_picnum);
6270 altref_delta_picnum =
6271 (altref_picnum >= curr_picnum) ?
6272 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6273
6274 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6275 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6276 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6277
6278 if (debug & VP9_DEBUG_CACHE)
6279 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6280 __func__, lastref_inref, goldenref_inref, altref_inref);
6281
6282 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6283
6284 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6285 && (!pbi->common.intra_only)) ? 1 : 0;
6286
6287 if (!is_inter) { /* I-PIC */
6288 /* remove reset -- disables clock */
6289 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6290 return;
6291 }
6292
6293 if (!pbi->m_ins_flag)
6294 dump_hit_rate(pbi);
6295
6296 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6297 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6298 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6299 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6300
6301 if (debug & VP9_DEBUG_CACHE)
6302 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6303 lastcanvas, goldencanvas, altrefcanvas);
6304
6305 altref_inref = ((altref_inref == 1) &&
6306 (altrefcanvas != (goldenref_inref
6307 ? goldencanvas : 0xffffffff)) &&
6308 (altrefcanvas != (lastref_inref ?
6309 lastcanvas : 0xffffffff))) ? 1 : 0;
6310 goldenref_inref = ((goldenref_inref == 1) &&
6311 (goldencanvas != (lastref_inref ?
6312 lastcanvas : 0xffffffff))) ? 1 : 0;
6313 if (debug & VP9_DEBUG_CACHE)
6314 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6315 lastref_inref, goldenref_inref, altref_inref);
6316
6317 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6318 goldenref_delta_picnum = goldenref_inref ?
6319 goldenref_delta_picnum : 0x7fffffff;
6320 lastref_delta_picnum = lastref_inref ?
6321 lastref_delta_picnum : 0x7fffffff;
6322 if (debug & VP9_DEBUG_CACHE)
6323 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6324 lastref_delta_picnum, goldenref_delta_picnum,
6325 altref_delta_picnum);
6326 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6327
6328 refcanvas_array[0] = lastcanvas;
6329 refcanvas_array[1] = goldencanvas;
6330 refcanvas_array[2] = altrefcanvas;
6331
6332 deltapicnum_array[0] = lastref_delta_picnum;
6333 deltapicnum_array[1] = goldenref_delta_picnum;
6334 deltapicnum_array[2] = altref_delta_picnum;
6335
6336 /* sort0 : 2-to-1 */
6337 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6338 utmp = refcanvas_array[2];
6339 refcanvas_array[2] = refcanvas_array[1];
6340 refcanvas_array[1] = utmp;
6341 tmp = deltapicnum_array[2];
6342 deltapicnum_array[2] = deltapicnum_array[1];
6343 deltapicnum_array[1] = tmp;
6344 }
6345 /* sort1 : 1-to-0 */
6346 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6347 utmp = refcanvas_array[1];
6348 refcanvas_array[1] = refcanvas_array[0];
6349 refcanvas_array[0] = utmp;
6350 tmp = deltapicnum_array[1];
6351 deltapicnum_array[1] = deltapicnum_array[0];
6352 deltapicnum_array[0] = tmp;
6353 }
6354 /* sort2 : 2-to-1 */
6355 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6356 utmp = refcanvas_array[2]; refcanvas_array[2] =
6357 refcanvas_array[1]; refcanvas_array[1] = utmp;
6358 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6359 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6360 }
6361 if (mcrcc_cache_alg_flag ==
6362 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6363 /* lowest delta_picnum */
6364 rdata32 = refcanvas_array[0];
6365 rdata32 = rdata32 & 0xffff;
6366 rdata32 = rdata32 | (rdata32 << 16);
6367 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6368
6369 /* 2nd-lowest delta_picnum */
6370 rdata32 = refcanvas_array[1];
6371 rdata32 = rdata32 & 0xffff;
6372 rdata32 = rdata32 | (rdata32 << 16);
6373 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6374 } else {
6375 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6376 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6377 (0 << 8) | (1<<1) | 0);
6378 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6379 rdata32 = rdata32 & 0xffff;
6380 rdata32 = rdata32 | (rdata32 << 16);
6381 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6382
6383 /* Programme canvas1 */
6384 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6385 rdata32 = rdata32 & 0xffff;
6386 rdata32 = rdata32 | (rdata32 << 16);
6387 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6388 }
6389
6390 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6391 return;
6392}
6393
6394#endif
6395
6396
6397static void free_lf_buf(struct VP9Decoder_s *pbi)
6398{
6399 if (pbi->lfi)
6400 vfree(pbi->lfi);
6401 if (pbi->lf)
6402 vfree(pbi->lf);
6403 if (pbi->seg_4lf)
6404 vfree(pbi->seg_4lf);
6405 pbi->lfi = NULL;
6406 pbi->lf = NULL;
6407 pbi->seg_4lf = NULL;
6408}
6409
6410static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6411{
6412 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6413 pbi->lf = vmalloc(sizeof(struct loopfilter));
6414 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6415 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6416 free_lf_buf(pbi);
6417 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6418 return -1;
6419 }
6420 return 0;
6421}
6422
6423static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6424{
6425 pbi->rpm_ptr = NULL;
6426 pbi->lmem_ptr = NULL;
6427 if (pbi->rpm_addr) {
6428 dma_free_coherent(amports_get_dma_device(),
6429 RPM_BUF_SIZE,
6430 pbi->rpm_addr,
6431 pbi->rpm_phy_addr);
6432 pbi->rpm_addr = NULL;
6433 }
6434 if (pbi->lmem_addr) {
6435 if (pbi->lmem_phy_addr)
6436 dma_free_coherent(amports_get_dma_device(),
6437 LMEM_BUF_SIZE, pbi->lmem_addr,
6438 pbi->lmem_phy_addr);
6439 pbi->lmem_addr = NULL;
6440 }
6441 if (pbi->prob_buffer_addr) {
6442 if (pbi->prob_buffer_phy_addr)
6443 dma_free_coherent(amports_get_dma_device(),
6444 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6445 pbi->prob_buffer_phy_addr);
6446
6447 pbi->prob_buffer_addr = NULL;
6448 }
6449 if (pbi->count_buffer_addr) {
6450 if (pbi->count_buffer_phy_addr)
6451 dma_free_coherent(amports_get_dma_device(),
6452 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6453 pbi->count_buffer_phy_addr);
6454
6455 pbi->count_buffer_addr = NULL;
6456 }
6457 if (pbi->mmu_enable) {
6458 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6459 if (pbi->frame_mmu_map_addr) {
6460 if (pbi->frame_mmu_map_phy_addr)
6461 dma_free_coherent(amports_get_dma_device(),
6462 mmu_map_size,
6463 pbi->frame_mmu_map_addr,
6464 pbi->frame_mmu_map_phy_addr);
6465 pbi->frame_mmu_map_addr = NULL;
6466 }
6467 }
6468#ifdef SUPPORT_FB_DECODING
6469 if (pbi->stage_mmu_map_addr) {
6470 if (pbi->stage_mmu_map_phy_addr)
6471 dma_free_coherent(amports_get_dma_device(),
6472 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6473 pbi->stage_mmu_map_addr,
6474 pbi->stage_mmu_map_phy_addr);
6475 pbi->stage_mmu_map_addr = NULL;
6476 }
6477
6478 uninit_stage_buf(pbi);
6479#endif
6480
6481#ifdef VP9_LPF_LVL_UPDATE
6482 free_lf_buf(pbi);
6483#endif
6484 if (pbi->gvs)
6485 vfree(pbi->gvs);
6486 pbi->gvs = NULL;
6487}
6488
6489static int vp9_local_init(struct VP9Decoder_s *pbi)
6490{
6491 int ret = -1;
6492 /*int losless_comp_header_size, losless_comp_body_size;*/
6493
6494 struct BuffInfo_s *cur_buf_info = NULL;
6495
6496 memset(&pbi->param, 0, sizeof(union param_u));
6497 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6498#ifdef MULTI_INSTANCE_SUPPORT
6499 cur_buf_info = &pbi->work_space_buf_store;
6500
6501 if (vdec_is_support_4k()) {
6502 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6503 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6504 sizeof(struct BuffInfo_s));
6505 } else
6506 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6507 sizeof(struct BuffInfo_s));
6508 } else
6509 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6510 sizeof(struct BuffInfo_s));
6511
6512 cur_buf_info->start_adr = pbi->buf_start;
6513 if (!pbi->mmu_enable)
6514 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6515
6516#else
6517/*! MULTI_INSTANCE_SUPPORT*/
6518 if (vdec_is_support_4k()) {
6519 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6520 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6521 else
6522 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6523 } else
6524 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6525
6526#endif
6527
6528 init_buff_spec(pbi, cur_buf_info);
6529 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6530
6531 if (!vdec_is_support_4k()
6532 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6533 buf_alloc_width = 1920;
6534 buf_alloc_height = 1088;
6535 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6536 pbi->max_pic_w = 1920;
6537 pbi->max_pic_h = 1088;
6538 }
6539 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6540 buf_alloc_width = 8192;
6541 buf_alloc_height = 4608;
6542 }
6543 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6544 (buf_alloc_width ? buf_alloc_width :
6545 (pbi->vvp9_amstream_dec_info.width ?
6546 pbi->vvp9_amstream_dec_info.width :
6547 pbi->work_space_buf->max_width));
6548 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6549 (buf_alloc_height ? buf_alloc_height :
6550 (pbi->vvp9_amstream_dec_info.height ?
6551 pbi->vvp9_amstream_dec_info.height :
6552 pbi->work_space_buf->max_height));
6553
6554 /* video is not support unaligned with 64 in tl1
6555 ** vdec canvas mode will be linear when dump yuv is set
6556 */
6557 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6558 (pbi->double_write_mode != 0) &&
6559 (((pbi->max_pic_w % 64) != 0) ||
6560 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6561 if (hw_to_vdec(pbi)->canvas_mode !=
6562 CANVAS_BLKMODE_LINEAR)
6563 pbi->mem_map_mode = 2;
6564 else {
6565 pbi->mem_map_mode = 0;
6566 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6567 }
6568 }
6569
6570#ifndef MV_USE_FIXED_BUF
6571 if (init_mv_buf_list(pbi) < 0) {
6572 pr_err("%s: init_mv_buf_list fail\n", __func__);
6573 return -1;
6574 }
6575#endif
6576 if (pbi->save_buffer_mode)
6577 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6578 else {
6579 if (pbi->is_used_v4l)
6580 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6581 else
6582 pbi->used_buf_num = max_buf_num;
6583 }
6584
6585 if (pbi->used_buf_num > MAX_BUF_NUM)
6586 pbi->used_buf_num = MAX_BUF_NUM;
6587 if (pbi->used_buf_num > FRAME_BUFFERS)
6588 pbi->used_buf_num = FRAME_BUFFERS;
6589
6590 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6591 & 0x40) >> 6;
6592
6593 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6594 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6595 RPM_BUF_SIZE,
6596 &pbi->rpm_phy_addr, GFP_KERNEL);
6597 if (pbi->rpm_addr == NULL) {
6598 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6599 return -1;
6600 }
6601
6602 pbi->rpm_ptr = pbi->rpm_addr;
6603 }
6604
6605 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6606 LMEM_BUF_SIZE,
6607 &pbi->lmem_phy_addr, GFP_KERNEL);
6608 if (pbi->lmem_addr == NULL) {
6609 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6610 return -1;
6611 }
6612 pbi->lmem_ptr = pbi->lmem_addr;
6613
6614 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6615 PROB_BUF_SIZE,
6616 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6617 if (pbi->prob_buffer_addr == NULL) {
6618 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6619 return -1;
6620 }
6621 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6622 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6623 COUNT_BUF_SIZE,
6624 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6625 if (pbi->count_buffer_addr == NULL) {
6626 pr_err("%s: failed to alloc count_buffer\n", __func__);
6627 return -1;
6628 }
6629 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6630
6631 if (pbi->mmu_enable) {
6632 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6633 pbi->frame_mmu_map_addr =
6634 dma_alloc_coherent(amports_get_dma_device(),
6635 mmu_map_size,
6636 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6637 if (pbi->frame_mmu_map_addr == NULL) {
6638 pr_err("%s: failed to alloc count_buffer\n", __func__);
6639 return -1;
6640 }
6641 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6642 }
6643#ifdef SUPPORT_FB_DECODING
6644 if (pbi->m_ins_flag && stage_buf_num > 0) {
6645 pbi->stage_mmu_map_addr =
6646 dma_alloc_coherent(amports_get_dma_device(),
6647 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6648 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6649 if (pbi->stage_mmu_map_addr == NULL) {
6650 pr_err("%s: failed to alloc count_buffer\n", __func__);
6651 return -1;
6652 }
6653 memset(pbi->stage_mmu_map_addr,
6654 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6655
6656 init_stage_buf(pbi);
6657 }
6658#endif
6659
6660 ret = 0;
6661 return ret;
6662}
6663
6664/********************************************
6665 * Mailbox command
6666 ********************************************/
6667#define CMD_FINISHED 0
6668#define CMD_ALLOC_VIEW 1
6669#define CMD_FRAME_DISPLAY 3
6670#define CMD_DEBUG 10
6671
6672
6673#define DECODE_BUFFER_NUM_MAX 32
6674#define DISPLAY_BUFFER_NUM 6
6675
6676#define video_domain_addr(adr) (adr&0x7fffffff)
6677#define DECODER_WORK_SPACE_SIZE 0x800000
6678
6679#define spec2canvas(x) \
6680 (((x)->uv_canvas_index << 16) | \
6681 ((x)->uv_canvas_index << 8) | \
6682 ((x)->y_canvas_index << 0))
6683
6684
6685static void set_canvas(struct VP9Decoder_s *pbi,
6686 struct PIC_BUFFER_CONFIG_s *pic_config)
6687{
6688 struct vdec_s *vdec = hw_to_vdec(pbi);
6689 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6690 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6691 int blkmode = pbi->mem_map_mode;
6692 /*CANVAS_BLKMODE_64X32*/
6693 if (pic_config->double_write_mode) {
6694 canvas_w = pic_config->y_crop_width /
6695 get_double_write_ratio(pbi,
6696 pic_config->double_write_mode);
6697 canvas_h = pic_config->y_crop_height /
6698 get_double_write_ratio(pbi,
6699 pic_config->double_write_mode);
6700
6701 if (pbi->mem_map_mode == 0)
6702 canvas_w = ALIGN(canvas_w, 32);
6703 else
6704 canvas_w = ALIGN(canvas_w, 64);
6705 canvas_h = ALIGN(canvas_h, 32);
6706
6707 if (vdec->parallel_dec == 1) {
6708 if (pic_config->y_canvas_index == -1)
6709 pic_config->y_canvas_index =
6710 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6711 if (pic_config->uv_canvas_index == -1)
6712 pic_config->uv_canvas_index =
6713 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6714 } else {
6715 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6716 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6717 }
6718
6719 canvas_config_ex(pic_config->y_canvas_index,
6720 pic_config->dw_y_adr, canvas_w, canvas_h,
6721 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6722 canvas_config_ex(pic_config->uv_canvas_index,
6723 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6724 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6725
6726#ifdef MULTI_INSTANCE_SUPPORT
6727 pic_config->canvas_config[0].phy_addr =
6728 pic_config->dw_y_adr;
6729 pic_config->canvas_config[0].width =
6730 canvas_w;
6731 pic_config->canvas_config[0].height =
6732 canvas_h;
6733 pic_config->canvas_config[0].block_mode =
6734 blkmode;
6735 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6736
6737 pic_config->canvas_config[1].phy_addr =
6738 pic_config->dw_u_v_adr;
6739 pic_config->canvas_config[1].width =
6740 canvas_w;
6741 pic_config->canvas_config[1].height =
6742 canvas_h;
6743 pic_config->canvas_config[1].block_mode =
6744 blkmode;
6745 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6746#endif
6747 }
6748}
6749
6750
6751static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6752{
6753 unsigned int ar;
6754 vf->duration = pbi->frame_dur;
6755 vf->duration_pulldown = 0;
6756 vf->flag = 0;
6757 vf->prop.master_display_colour = pbi->vf_dp;
6758 vf->signal_type = pbi->video_signal_type;
6759 if (vf->compWidth && vf->compHeight)
6760 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6761 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6762 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6763
6764 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6765 struct aml_vdec_hdr_infos hdr;
6766 struct aml_vcodec_ctx *ctx =
6767 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6768
6769 memset(&hdr, 0, sizeof(hdr));
6770 hdr.signal_type = vf->signal_type;
6771 hdr.color_parms = pbi->vf_dp;
6772 vdec_v4l_set_hdr_infos(ctx, &hdr);
6773 }
6774}
6775
6776static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6777{
6778 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6779
6780 states->vf_pool_size = VF_POOL_SIZE;
6781 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6782 states->buf_avail_num = kfifo_len(&pbi->display_q);
6783
6784 if (step == 2)
6785 states->buf_avail_num = 0;
6786 return 0;
6787}
6788
6789static struct vframe_s *vvp9_vf_peek(void *op_arg)
6790{
6791 struct vframe_s *vf[2] = {0, 0};
6792 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6793
6794 if (step == 2)
6795 return NULL;
6796
6797 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6798 if (vf[1]) {
6799 vf[0]->next_vf_pts_valid = true;
6800 vf[0]->next_vf_pts = vf[1]->pts;
6801 } else
6802 vf[0]->next_vf_pts_valid = false;
6803 return vf[0];
6804 }
6805
6806 return NULL;
6807}
6808
6809static struct vframe_s *vvp9_vf_get(void *op_arg)
6810{
6811 struct vframe_s *vf;
6812 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6813
6814 if (step == 2)
6815 return NULL;
6816 else if (step == 1)
6817 step = 2;
6818
6819 if (kfifo_get(&pbi->display_q, &vf)) {
6820 struct vframe_s *next_vf;
6821 uint8_t index = vf->index & 0xff;
6822 if (index < pbi->used_buf_num ||
6823 (vf->type & VIDTYPE_V4L_EOS)) {
6824 vf->index_disp = pbi->vf_get_count;
6825 pbi->vf_get_count++;
6826 if (debug & VP9_DEBUG_BUFMGR)
6827 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6828 __func__, vf->type,
6829 vf->width, vf->height,
6830 vf->pts,
6831 vf->pts_us64);
6832
6833 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6834 vf->next_vf_pts_valid = true;
6835 vf->next_vf_pts = next_vf->pts;
6836 } else
6837 vf->next_vf_pts_valid = false;
6838
6839 return vf;
6840 }
6841 }
6842 return NULL;
6843}
6844
6845static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6846{
6847 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6848 uint8_t index = vf->index & 0xff;
6849
6850 if (vf == (&pbi->vframe_dummy))
6851 return;
6852
6853 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6854 pbi->vf_put_count++;
6855 if (index < pbi->used_buf_num) {
6856 struct VP9_Common_s *cm = &pbi->common;
6857 struct BufferPool_s *pool = cm->buffer_pool;
6858 unsigned long flags;
6859
6860 lock_buffer_pool(pool, flags);
6861 if (pool->frame_bufs[index].buf.vf_ref > 0)
6862 pool->frame_bufs[index].buf.vf_ref--;
6863
6864 if (pbi->is_used_v4l)
6865 pool->frame_bufs[index].buf.vframe_bound = true;
6866
6867 if (pbi->wait_buf)
6868 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6869 0x1);
6870 pbi->last_put_idx = index;
6871 pbi->new_frame_displayed++;
6872 unlock_buffer_pool(pool, flags);
6873#ifdef SUPPORT_FB_DECODING
6874 if (pbi->used_stage_buf_num > 0 &&
6875 pbi->back_not_run_ready)
6876 trigger_schedule(pbi);
6877#endif
6878 }
6879
6880}
6881
6882static int vvp9_event_cb(int type, void *data, void *private_data)
6883{
6884 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6885#if 0
6886 unsigned long flags;
6887
6888 amhevc_stop();
6889#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6890 vf_light_unreg_provider(&vvp9_vf_prov);
6891#endif
6892 spin_lock_irqsave(&pbi->lock, flags);
6893 vvp9_local_init();
6894 vvp9_prot_init();
6895 spin_unlock_irqrestore(&pbi->lock, flags);
6896#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6897 vf_reg_provider(&vvp9_vf_prov);
6898#endif
6899 amhevc_start();
6900#endif
6901 }
6902
6903 return 0;
6904}
6905
6906void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6907{
6908 struct VP9_Common_s *cm = &pbi->common;
6909
6910 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6911
6912 if (debug & VP9_DEBUG_BUFMGR_MORE)
6913 pr_info("%s index = %d new vf_ref = %d\r\n",
6914 __func__, index,
6915 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6916}
6917
6918static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6919{
6920 u32 old_duration, pts_duration = 0;
6921 u32 pts = vf->pts;
6922
6923 if (pbi->get_frame_dur == true)
6924 return true;
6925
6926 pbi->frame_cnt_window++;
6927 if (!(pbi->vp9_first_pts_ready == 1)) {
6928 if (valid) {
6929 pbi->pts1 = pts;
6930 pbi->frame_cnt_window = 0;
6931 pbi->duration_from_pts_done = 0;
6932 pbi->vp9_first_pts_ready = 1;
6933 } else {
6934 return false;
6935 }
6936 } else {
6937 if (pts < pbi->pts1) {
6938 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6939 pbi->pts1 = pts;
6940 pbi->frame_cnt_window = 0;
6941 }
6942 }
6943
6944 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6945 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6946 old_duration = pbi->frame_dur;
6947 pbi->pts2 = pts;
6948 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6949 (pbi->frame_cnt_window * 15));
6950
6951 if (close_to(pts_duration, old_duration, 2000)) {
6952 pbi->frame_dur = pts_duration;
6953 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6954 pr_info("use calc duration %d\n", pts_duration);
6955 }
6956
6957 if (pbi->duration_from_pts_done == 0) {
6958 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6959 pbi->duration_from_pts_done = 1;
6960 } else {
6961 if (!close_to(pts_duration,
6962 old_duration, 1000) &&
6963 !close_to(pts_duration,
6964 pbi->frame_dur, 1000) &&
6965 close_to(pts_duration,
6966 pbi->last_duration, 200)) {
6967 /* frame_dur must
6968 * wrong,recover it.
6969 */
6970 pbi->frame_dur = pts_duration;
6971 }
6972 pbi->pts1 = pbi->pts2;
6973 pbi->frame_cnt_window = 0;
6974 pbi->duration_from_pts_done = 0;
6975 }
6976 }
6977 pbi->last_duration = pts_duration;
6978 }
6979 }
6980 return true;
6981}
6982
6983static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6984 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6985{
6986 if (pic->index < 0) {
6987 vf->mem_handle = NULL;
6988 vf->mem_head_handle = NULL;
6989 } else if (vf->type & VIDTYPE_SCATTER) {
6990 vf->mem_handle =
6991 decoder_mmu_box_get_mem_handle(
6992 pbi->mmu_box, pic->index);
6993 vf->mem_head_handle =
6994 decoder_bmmu_box_get_mem_handle(
6995 pbi->bmmu_box,
6996 HEADER_BUFFER_IDX(pic->BUF_index));
6997 } else {
6998 vf->mem_handle =
6999 decoder_bmmu_box_get_mem_handle(
7000 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
7001 vf->mem_head_handle = NULL;
7002 /*vf->mem_head_handle =
7003 *decoder_bmmu_box_get_mem_handle(
7004 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
7005 */
7006 }
7007}
7008
7009static int prepare_display_buf(struct VP9Decoder_s *pbi,
7010 struct PIC_BUFFER_CONFIG_s *pic_config)
7011{
7012 struct vframe_s *vf = NULL;
7013 int stream_offset = pic_config->stream_offset;
7014 unsigned short slice_type = pic_config->slice_type;
7015 u32 pts_valid = 0, pts_us64_valid = 0;
7016 u32 pts_save;
7017 u64 pts_us64_save;
7018 u32 frame_size;
7019
7020 if (debug & VP9_DEBUG_BUFMGR)
7021 pr_info("%s index = %d\r\n", __func__, pic_config->index);
7022 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
7023 pr_info("fatal error, no available buffer slot.");
7024 return -1;
7025 }
7026
7027 if (pic_config->double_write_mode)
7028 set_canvas(pbi, pic_config);
7029
7030 display_frame_count[pbi->index]++;
7031 if (vf) {
7032 if (pbi->is_used_v4l) {
7033 vf->v4l_mem_handle
7034 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7035 if (pbi->mmu_enable) {
7036 vf->mm_box.bmmu_box = pbi->bmmu_box;
7037 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7038 vf->mm_box.mmu_box = pbi->mmu_box;
7039 vf->mm_box.mmu_idx = pic_config->index;
7040 }
7041 }
7042
7043#ifdef MULTI_INSTANCE_SUPPORT
7044 if (vdec_frame_based(hw_to_vdec(pbi))) {
7045 vf->pts = pic_config->pts;
7046 vf->pts_us64 = pic_config->pts64;
7047 vf->timestamp = pic_config->timestamp;
7048 if (vf->pts != 0 || vf->pts_us64 != 0) {
7049 pts_valid = 1;
7050 pts_us64_valid = 1;
7051 } else {
7052 pts_valid = 0;
7053 pts_us64_valid = 0;
7054 }
7055 } else
7056#endif
7057 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7058 * stream_offset, &vf->pts, 0) != 0) {
7059 */
7060 if (pts_lookup_offset_us64
7061 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7062 &frame_size, 0,
7063 &vf->pts_us64) != 0) {
7064#ifdef DEBUG_PTS
7065 pbi->pts_missed++;
7066#endif
7067 vf->pts = 0;
7068 vf->pts_us64 = 0;
7069 pts_valid = 0;
7070 pts_us64_valid = 0;
7071 } else {
7072#ifdef DEBUG_PTS
7073 pbi->pts_hit++;
7074#endif
7075 pts_valid = 1;
7076 pts_us64_valid = 1;
7077 }
7078
7079 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7080
7081 pts_save = vf->pts;
7082 pts_us64_save = vf->pts_us64;
7083 if (pbi->pts_unstable) {
7084 frame_duration_adapt(pbi, vf, pts_valid);
7085 if (pbi->duration_from_pts_done) {
7086 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7087 } else {
7088 if (pts_valid || pts_us64_valid)
7089 pbi->pts_mode = PTS_NORMAL;
7090 }
7091 }
7092
7093 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7094 && pbi->get_frame_dur) {
7095 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7096
7097 if (pts_diff < 0) {
7098 pbi->pts_mode_switching_count++;
7099 pbi->pts_mode_recovery_count = 0;
7100
7101 if (pbi->pts_mode_switching_count >=
7102 PTS_MODE_SWITCHING_THRESHOLD) {
7103 pbi->pts_mode =
7104 PTS_NONE_REF_USE_DURATION;
7105 pr_info
7106 ("HEVC: switch to n_d mode.\n");
7107 }
7108
7109 } else {
7110 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7111
7112 pbi->pts_mode_recovery_count++;
7113 if (pbi->pts_mode_recovery_count > p) {
7114 pbi->pts_mode_switching_count = 0;
7115 pbi->pts_mode_recovery_count = 0;
7116 }
7117 }
7118 }
7119
7120 if (vf->pts != 0)
7121 pbi->last_lookup_pts = vf->pts;
7122
7123 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7124 && (slice_type != KEY_FRAME))
7125 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7126 pbi->last_pts = vf->pts;
7127
7128 if (vf->pts_us64 != 0)
7129 pbi->last_lookup_pts_us64 = vf->pts_us64;
7130
7131 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7132 && (slice_type != KEY_FRAME)) {
7133 vf->pts_us64 =
7134 pbi->last_pts_us64 +
7135 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7136 }
7137 pbi->last_pts_us64 = vf->pts_us64;
7138 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7139 pr_info
7140 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7141 pbi->pts_mode, pbi->frame_dur, vf->pts,
7142 vf->pts_us64, pts_save, pts_us64_save);
7143 }
7144
7145 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7146 vf->disp_pts = vf->pts;
7147 vf->disp_pts_us64 = vf->pts_us64;
7148 vf->pts = pts_save;
7149 vf->pts_us64 = pts_us64_save;
7150 } else {
7151 vf->disp_pts = 0;
7152 vf->disp_pts_us64 = 0;
7153 }
7154
7155 vf->index = 0xff00 | pic_config->index;
7156
7157 if (pic_config->double_write_mode & 0x10) {
7158 /* double write only */
7159 vf->compBodyAddr = 0;
7160 vf->compHeadAddr = 0;
7161 } else {
7162 if (pbi->mmu_enable) {
7163 vf->compBodyAddr = 0;
7164 vf->compHeadAddr = pic_config->header_adr;
7165 } else {
7166 /*vf->compBodyAddr = pic_config->mc_y_adr;
7167 *vf->compHeadAddr = pic_config->mc_y_adr +
7168 *pic_config->comp_body_size; */
7169 /*head adr*/
7170 }
7171 vf->canvas0Addr = vf->canvas1Addr = 0;
7172 }
7173 if (pic_config->double_write_mode) {
7174 vf->type = VIDTYPE_PROGRESSIVE |
7175 VIDTYPE_VIU_FIELD;
7176 vf->type |= VIDTYPE_VIU_NV21;
7177 if ((pic_config->double_write_mode == 3) &&
7178 (!IS_8K_SIZE(pic_config->y_crop_width,
7179 pic_config->y_crop_height))) {
7180 vf->type |= VIDTYPE_COMPRESS;
7181 if (pbi->mmu_enable)
7182 vf->type |= VIDTYPE_SCATTER;
7183 }
7184#ifdef MULTI_INSTANCE_SUPPORT
7185 if (pbi->m_ins_flag) {
7186 vf->canvas0Addr = vf->canvas1Addr = -1;
7187 vf->plane_num = 2;
7188 vf->canvas0_config[0] =
7189 pic_config->canvas_config[0];
7190 vf->canvas0_config[1] =
7191 pic_config->canvas_config[1];
7192 vf->canvas1_config[0] =
7193 pic_config->canvas_config[0];
7194 vf->canvas1_config[1] =
7195 pic_config->canvas_config[1];
7196
7197 } else
7198#endif
7199 vf->canvas0Addr = vf->canvas1Addr =
7200 spec2canvas(pic_config);
7201 } else {
7202 vf->canvas0Addr = vf->canvas1Addr = 0;
7203 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7204 if (pbi->mmu_enable)
7205 vf->type |= VIDTYPE_SCATTER;
7206 }
7207
7208 switch (pic_config->bit_depth) {
7209 case VPX_BITS_8:
7210 vf->bitdepth = BITDEPTH_Y8 |
7211 BITDEPTH_U8 | BITDEPTH_V8;
7212 break;
7213 case VPX_BITS_10:
7214 case VPX_BITS_12:
7215 vf->bitdepth = BITDEPTH_Y10 |
7216 BITDEPTH_U10 | BITDEPTH_V10;
7217 break;
7218 default:
7219 vf->bitdepth = BITDEPTH_Y10 |
7220 BITDEPTH_U10 | BITDEPTH_V10;
7221 break;
7222 }
7223 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7224 vf->bitdepth =
7225 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7226 if (pic_config->bit_depth == VPX_BITS_8)
7227 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7228
7229 /* if((vf->width!=pic_config->width)|
7230 * (vf->height!=pic_config->height))
7231 */
7232 /* pr_info("aaa: %d/%d, %d/%d\n",
7233 vf->width,vf->height, pic_config->width,
7234 pic_config->height); */
7235 vf->width = pic_config->y_crop_width /
7236 get_double_write_ratio(pbi,
7237 pic_config->double_write_mode);
7238 vf->height = pic_config->y_crop_height /
7239 get_double_write_ratio(pbi,
7240 pic_config->double_write_mode);
7241 if (force_w_h != 0) {
7242 vf->width = (force_w_h >> 16) & 0xffff;
7243 vf->height = force_w_h & 0xffff;
7244 }
7245 vf->compWidth = pic_config->y_crop_width;
7246 vf->compHeight = pic_config->y_crop_height;
7247 set_frame_info(pbi, vf);
7248 if (force_fps & 0x100) {
7249 u32 rate = force_fps & 0xff;
7250
7251 if (rate)
7252 vf->duration = 96000/rate;
7253 else
7254 vf->duration = 0;
7255 }
7256 update_vf_memhandle(pbi, vf, pic_config);
7257 if (!(pic_config->y_crop_width == 196
7258 && pic_config->y_crop_height == 196
7259 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7260 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7261 inc_vf_ref(pbi, pic_config->index);
7262 decoder_do_frame_check(hw_to_vdec(pbi), vf);
7263 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7264 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7265 pbi->vf_pre_count++;
7266#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7267 /*count info*/
7268 gvs->frame_dur = pbi->frame_dur;
7269 vdec_count_info(gvs, 0, stream_offset);
7270#endif
7271 hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
7272 if (without_display_mode == 0) {
7273 vf_notify_receiver(pbi->provider_name,
7274 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7275 } else
7276 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7277 } else {
7278 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7279 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7280 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7281 __func__, __LINE__, vf->width,
7282 vf->height, pbi->stat);
7283 }
7284 }
7285
7286 return 0;
7287}
7288
7289static int notify_v4l_eos(struct vdec_s *vdec)
7290{
7291 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7292 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7293 struct vframe_s *vf = &hw->vframe_dummy;
7294 struct vdec_v4l2_buffer *fb = NULL;
7295 int index = INVALID_IDX;
7296 ulong expires;
7297
7298 if (hw->is_used_v4l && hw->eos) {
7299 expires = jiffies + msecs_to_jiffies(2000);
7300 while (INVALID_IDX == (index = v4l_get_free_fb(hw))) {
7301 if (time_after(jiffies, expires) ||
7302 v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx))
7303 break;
7304 }
7305
7306 if (index == INVALID_IDX) {
7307 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7308 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7309 return -1;
7310 }
7311 }
7312
7313 vf->type |= VIDTYPE_V4L_EOS;
7314 vf->timestamp = ULONG_MAX;
7315 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7316 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7317 hw->m_BUF[index].v4l_ref_buf_addr;
7318
7319 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7320 vf_notify_receiver(vdec->vf_provider_name,
7321 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7322
7323 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7324 }
7325
7326 return 0;
7327}
7328
7329static void get_rpm_param(union param_u *params)
7330{
7331 int i;
7332 unsigned int data32;
7333
7334 if (debug & VP9_DEBUG_BUFMGR)
7335 pr_info("enter %s\r\n", __func__);
7336 for (i = 0; i < 128; i++) {
7337 do {
7338 data32 = READ_VREG(RPM_CMD_REG);
7339 /*pr_info("%x\n", data32);*/
7340 } while ((data32 & 0x10000) == 0);
7341 params->l.data[i] = data32&0xffff;
7342 /*pr_info("%x\n", data32);*/
7343 WRITE_VREG(RPM_CMD_REG, 0);
7344 }
7345 if (debug & VP9_DEBUG_BUFMGR)
7346 pr_info("leave %s\r\n", __func__);
7347}
7348static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7349{
7350 int i;
7351
7352 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7353 return;
7354 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7355 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7356 pr_info("%04x ", vp9_param.l.data[i]);
7357 if (((i + 1) & 0xf) == 0)
7358 pr_info("\n");
7359 }
7360 pr_info("=============param==========\r\n");
7361 pr_info("profile %x\r\n", vp9_param.p.profile);
7362 pr_info("show_existing_frame %x\r\n",
7363 vp9_param.p.show_existing_frame);
7364 pr_info("frame_to_show_idx %x\r\n",
7365 vp9_param.p.frame_to_show_idx);
7366 pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7367 pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7368 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7369 vp9_param.p.error_resilient_mode);
7370 pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7371 pr_info("display_size_present %x\r\n",
7372 vp9_param.p.display_size_present);
7373 pr_info("reset_frame_context %x\r\n",
7374 vp9_param.p.reset_frame_context);
7375 pr_info("refresh_frame_flags %x\r\n",
7376 vp9_param.p.refresh_frame_flags);
7377 pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7378 pr_info("width %x\r\n", vp9_param.p.width);
7379 pr_info("height %x\r\n", vp9_param.p.height);
7380 pr_info("display_width %x\r\n", vp9_param.p.display_width);
7381 pr_info("display_height %x\r\n", vp9_param.p.display_height);
7382 pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7383 pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7384 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7385 return;
7386 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7387 vp9_param.p.mode_ref_delta_enabled);
7388 pr_info("sharpness_level: 0x%x\r\n",
7389 vp9_param.p.sharpness_level);
7390 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7391 vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7392 vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7393 pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7394 vp9_param.p.mode_deltas[1]);
7395 pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7396 pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7397 pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7398 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7399 (vp9_param.p.seg_lf_info[0]>>15 & 1),
7400 (vp9_param.p.seg_lf_info[1]>>15 & 1),
7401 (vp9_param.p.seg_lf_info[2]>>15 & 1),
7402 (vp9_param.p.seg_lf_info[3]>>15 & 1),
7403 (vp9_param.p.seg_lf_info[4]>>15 & 1),
7404 (vp9_param.p.seg_lf_info[5]>>15 & 1),
7405 (vp9_param.p.seg_lf_info[6]>>15 & 1),
7406 (vp9_param.p.seg_lf_info[7]>>15 & 1));
7407 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7408 (vp9_param.p.seg_lf_info[0] & 0x13f),
7409 (vp9_param.p.seg_lf_info[1] & 0x13f),
7410 (vp9_param.p.seg_lf_info[2] & 0x13f),
7411 (vp9_param.p.seg_lf_info[3] & 0x13f),
7412 (vp9_param.p.seg_lf_info[4] & 0x13f),
7413 (vp9_param.p.seg_lf_info[5] & 0x13f),
7414 (vp9_param.p.seg_lf_info[6] & 0x13f),
7415 (vp9_param.p.seg_lf_info[7] & 0x13f));
7416
7417}
7418
7419
7420static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7421{
7422 struct VP9_Common_s *const cm = &pbi->common;
7423 if (pbi->double_write_mode & 0x10)
7424 return;
7425 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7426 if (pbi->used_4k_num == -1) {
7427 pbi->used_4k_num =
7428 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7429 if (pbi->m_ins_flag)
7430 hevc_mmu_dma_check(hw_to_vdec(pbi));
7431 }
7432 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7433 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7434 cm->cur_fb_idx_mmu = INVALID_IDX;
7435 pbi->used_4k_num = -1;
7436 }
7437}
7438
7439#ifdef MULTI_INSTANCE_SUPPORT
7440static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7441{
7442 struct VP9_Common_s *const cm = &pbi->common;
7443 if (pbi->double_write_mode & 0x10)
7444 return;
7445 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7446 decoder_mmu_box_free_idx(pbi->mmu_box,
7447 cm->cur_fb_idx_mmu);
7448
7449 cm->cur_fb_idx_mmu = INVALID_IDX;
7450 pbi->used_4k_num = -1;
7451 }
7452}
7453#endif
7454
7455
7456static void dec_again_process(struct VP9Decoder_s *pbi)
7457{
7458 amhevc_stop();
7459 pbi->dec_result = DEC_RESULT_AGAIN;
7460 if (pbi->process_state ==
7461 PROC_STATE_DECODESLICE) {
7462 pbi->process_state =
7463 PROC_STATE_SENDAGAIN;
7464 if (pbi->mmu_enable)
7465 vp9_recycle_mmu_buf(pbi);
7466 }
7467 reset_process_time(pbi);
7468 vdec_schedule_work(&pbi->work);
7469}
7470
7471int continue_decoding(struct VP9Decoder_s *pbi)
7472{
7473 int ret;
7474 int i;
7475 struct VP9_Common_s *const cm = &pbi->common;
7476 debug_buffer_mgr_more(pbi);
7477
7478 bit_depth_luma = vp9_param.p.bit_depth;
7479 bit_depth_chroma = vp9_param.p.bit_depth;
7480
7481 if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7482 (get_double_write_mode(pbi) == 0x10)) {
7483 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7484 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7485 vp9_param.p.bit_depth);
7486 return -1;
7487 }
7488
7489 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7490 ret = vp9_bufmgr_process(pbi, &vp9_param);
7491 if (!pbi->m_ins_flag)
7492 pbi->slice_idx++;
7493 } else {
7494 union param_u *params = &vp9_param;
7495 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7496 ret = vp9_alloc_mmu(pbi,
7497 cm->new_fb_idx,
7498 params->p.width,
7499 params->p.height,
7500 params->p.bit_depth,
7501 pbi->frame_mmu_map_addr);
7502 if (ret >= 0)
7503 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7504 else
7505 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7506 cm->new_fb_idx,
7507 ret);
7508 } else {
7509 ret = 0;
7510 }
7511 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7512 (params->p.height << 16) | params->p.width);
7513 }
7514 if (ret < 0) {
7515 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7516 ret);
7517 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7518 cm->show_frame = 0;
7519 if (pbi->mmu_enable)
7520 vp9_recycle_mmu_buf(pbi);
7521#ifdef MULTI_INSTANCE_SUPPORT
7522 if (pbi->m_ins_flag) {
7523 pbi->dec_result = DEC_RESULT_DONE;
7524#ifdef SUPPORT_FB_DECODING
7525 if (pbi->used_stage_buf_num == 0)
7526#endif
7527 amhevc_stop();
7528 vdec_schedule_work(&pbi->work);
7529 }
7530#endif
7531 return ret;
7532 } else if (ret == 0) {
7533 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7534 = &cm->cur_frame->buf;
7535 cur_pic_config->decode_idx = pbi->frame_count;
7536
7537 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7538 if (!pbi->m_ins_flag) {
7539 pbi->frame_count++;
7540 decode_frame_count[pbi->index]
7541 = pbi->frame_count;
7542 }
7543#ifdef MULTI_INSTANCE_SUPPORT
7544 if (pbi->chunk) {
7545 cur_pic_config->pts = pbi->chunk->pts;
7546 cur_pic_config->pts64 = pbi->chunk->pts64;
7547 cur_pic_config->timestamp = pbi->chunk->timestamp;
7548 }
7549#endif
7550 }
7551 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7552 config_pic_size(pbi, vp9_param.p.bit_depth);
7553
7554 if ((pbi->common.frame_type != KEY_FRAME)
7555 && (!pbi->common.intra_only)) {
7556 config_mc_buffer(pbi, vp9_param.p.bit_depth);
7557#ifdef SUPPORT_FB_DECODING
7558 if (pbi->used_stage_buf_num == 0)
7559#endif
7560 config_mpred_hw(pbi);
7561 } else {
7562#ifdef SUPPORT_FB_DECODING
7563 if (pbi->used_stage_buf_num == 0)
7564#endif
7565 clear_mpred_hw(pbi);
7566 }
7567#ifdef MCRCC_ENABLE
7568 if (mcrcc_cache_alg_flag)
7569 config_mcrcc_axi_hw_new(pbi);
7570 else
7571 config_mcrcc_axi_hw(pbi);
7572#endif
7573 config_sao_hw(pbi, &vp9_param);
7574
7575#ifdef VP9_LPF_LVL_UPDATE
7576 /*
7577 * Get loop filter related picture level parameters from Parser
7578 */
7579 pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7580 pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7581 for (i = 0; i < 4; i++)
7582 pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7583 for (i = 0; i < 2; i++)
7584 pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7585 pbi->default_filt_lvl = vp9_param.p.filter_level;
7586 pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7587 pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7588 for (i = 0; i < MAX_SEGMENTS; i++)
7589 pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7590 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7591 for (i = 0; i < MAX_SEGMENTS; i++)
7592 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7593 = (vp9_param.p.seg_lf_info[i]
7594 & 0x100) ? -(vp9_param.p.seg_lf_info[i]
7595 & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7596 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7597 /*Set pipeline mode*/
7598 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7599 /*dblk pipeline mode=1 for performance*/
7600 if (vp9_param.p.width >= 1280)
7601 lpf_data32 |= (0x1 << 4);
7602 else
7603 lpf_data32 &= ~(0x3 << 4);
7604 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7605 }
7606 /*
7607 * Update loop filter Thr/Lvl table for every frame
7608 */
7609 /*pr_info
7610 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7611 vp9_loop_filter_frame_init(pbi->seg_4lf,
7612 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7613#endif
7614 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7615 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7616 } else {
7617 pr_info("Skip search next start code\n");
7618 cm->prev_fb_idx = INVALID_IDX;
7619 /*skip, search next start code*/
7620 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7621 }
7622 pbi->process_state = PROC_STATE_DECODESLICE;
7623 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7624 if (pbi->last_put_idx < pbi->used_buf_num) {
7625 struct RefCntBuffer_s *frame_bufs =
7626 cm->buffer_pool->frame_bufs;
7627 int i = pbi->last_put_idx;
7628 /*free not used buffers.*/
7629 if ((frame_bufs[i].ref_count == 0) &&
7630 (frame_bufs[i].buf.vf_ref == 0) &&
7631 (frame_bufs[i].buf.index != -1)) {
7632 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7633 }
7634 pbi->last_put_idx = -1;
7635 }
7636 }
7637 return ret;
7638}
7639
7640static void fill_frame_info(struct VP9Decoder_s *pbi,
7641 struct PIC_BUFFER_CONFIG_s *frame,
7642 unsigned int framesize,
7643 unsigned int pts)
7644{
7645 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7646
7647 if (frame->slice_type == KEY_FRAME)
7648 vframe_qos->type = 1;
7649 else if (frame->slice_type == INTER_FRAME)
7650 vframe_qos->type = 2;
7651/*
7652#define SHOW_QOS_INFO
7653*/
7654 vframe_qos->size = framesize;
7655 vframe_qos->pts = pts;
7656#ifdef SHOW_QOS_INFO
7657 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7658#endif
7659 vframe_qos->max_mv = frame->max_mv;
7660 vframe_qos->avg_mv = frame->avg_mv;
7661 vframe_qos->min_mv = frame->min_mv;
7662#ifdef SHOW_QOS_INFO
7663 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7664 vframe_qos->max_mv,
7665 vframe_qos->avg_mv,
7666 vframe_qos->min_mv);
7667#endif
7668 vframe_qos->max_qp = frame->max_qp;
7669 vframe_qos->avg_qp = frame->avg_qp;
7670 vframe_qos->min_qp = frame->min_qp;
7671#ifdef SHOW_QOS_INFO
7672 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7673 vframe_qos->max_qp,
7674 vframe_qos->avg_qp,
7675 vframe_qos->min_qp);
7676#endif
7677 vframe_qos->max_skip = frame->max_skip;
7678 vframe_qos->avg_skip = frame->avg_skip;
7679 vframe_qos->min_skip = frame->min_skip;
7680#ifdef SHOW_QOS_INFO
7681 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7682 vframe_qos->max_skip,
7683 vframe_qos->avg_skip,
7684 vframe_qos->min_skip);
7685#endif
7686 vframe_qos->num++;
7687
7688 if (pbi->frameinfo_enable)
7689 vdec_fill_frame_info(vframe_qos, 1);
7690}
7691
7692/* only when we decoded one field or one frame,
7693we can call this function to get qos info*/
7694static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7695{
7696 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7697
7698 if (!frame)
7699 return;
7700
7701 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7702 unsigned char a[3];
7703 unsigned char i, j, t;
7704 unsigned long data;
7705
7706 data = READ_VREG(HEVC_MV_INFO);
7707 if (frame->slice_type == KEY_FRAME)
7708 data = 0;
7709 a[0] = data & 0xff;
7710 a[1] = (data >> 8) & 0xff;
7711 a[2] = (data >> 16) & 0xff;
7712
7713 for (i = 0; i < 3; i++) {
7714 for (j = i+1; j < 3; j++) {
7715 if (a[j] < a[i]) {
7716 t = a[j];
7717 a[j] = a[i];
7718 a[i] = t;
7719 } else if (a[j] == a[i]) {
7720 a[i]++;
7721 t = a[j];
7722 a[j] = a[i];
7723 a[i] = t;
7724 }
7725 }
7726 }
7727 frame->max_mv = a[2];
7728 frame->avg_mv = a[1];
7729 frame->min_mv = a[0];
7730
7731 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7732 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7733 data, a[0], a[1], a[2]);
7734
7735 data = READ_VREG(HEVC_QP_INFO);
7736 a[0] = data & 0x1f;
7737 a[1] = (data >> 8) & 0x3f;
7738 a[2] = (data >> 16) & 0x7f;
7739
7740 for (i = 0; i < 3; i++) {
7741 for (j = i+1; j < 3; j++) {
7742 if (a[j] < a[i]) {
7743 t = a[j];
7744 a[j] = a[i];
7745 a[i] = t;
7746 } else if (a[j] == a[i]) {
7747 a[i]++;
7748 t = a[j];
7749 a[j] = a[i];
7750 a[i] = t;
7751 }
7752 }
7753 }
7754 frame->max_qp = a[2];
7755 frame->avg_qp = a[1];
7756 frame->min_qp = a[0];
7757
7758 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7759 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7760 data, a[0], a[1], a[2]);
7761
7762 data = READ_VREG(HEVC_SKIP_INFO);
7763 a[0] = data & 0x1f;
7764 a[1] = (data >> 8) & 0x3f;
7765 a[2] = (data >> 16) & 0x7f;
7766
7767 for (i = 0; i < 3; i++) {
7768 for (j = i+1; j < 3; j++) {
7769 if (a[j] < a[i]) {
7770 t = a[j];
7771 a[j] = a[i];
7772 a[i] = t;
7773 } else if (a[j] == a[i]) {
7774 a[i]++;
7775 t = a[j];
7776 a[j] = a[i];
7777 a[i] = t;
7778 }
7779 }
7780 }
7781 frame->max_skip = a[2];
7782 frame->avg_skip = a[1];
7783 frame->min_skip = a[0];
7784
7785 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7786 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7787 data, a[0], a[1], a[2]);
7788 } else {
7789 uint32_t blk88_y_count;
7790 uint32_t blk88_c_count;
7791 uint32_t blk22_mv_count;
7792 uint32_t rdata32;
7793 int32_t mv_hi;
7794 int32_t mv_lo;
7795 uint32_t rdata32_l;
7796 uint32_t mvx_L0_hi;
7797 uint32_t mvy_L0_hi;
7798 uint32_t mvx_L1_hi;
7799 uint32_t mvy_L1_hi;
7800 int64_t value;
7801 uint64_t temp_value;
7802 int pic_number = frame->decode_idx;
7803
7804 frame->max_mv = 0;
7805 frame->avg_mv = 0;
7806 frame->min_mv = 0;
7807
7808 frame->max_skip = 0;
7809 frame->avg_skip = 0;
7810 frame->min_skip = 0;
7811
7812 frame->max_qp = 0;
7813 frame->avg_qp = 0;
7814 frame->min_qp = 0;
7815
7816 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7817 frame->slice_type,
7818 pic_number);
7819
7820 /* set rd_idx to 0 */
7821 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7822
7823 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7824 if (blk88_y_count == 0) {
7825
7826 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7827 "[Picture %d Quality] NO Data yet.\n",
7828 pic_number);
7829
7830 /* reset all counts */
7831 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7832 return;
7833 }
7834 /* qp_y_sum */
7835 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7836
7837 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7838 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7839 pic_number, rdata32/blk88_y_count,
7840 rdata32, blk88_y_count);
7841
7842 frame->avg_qp = rdata32/blk88_y_count;
7843 /* intra_y_count */
7844 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7845
7846 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7847 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7848 pic_number, rdata32*100/blk88_y_count,
7849 '%', rdata32);
7850
7851 /* skipped_y_count */
7852 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7853
7854 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7855 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7856 pic_number, rdata32*100/blk88_y_count,
7857 '%', rdata32);
7858
7859 frame->avg_skip = rdata32*100/blk88_y_count;
7860 /* coeff_non_zero_y_count */
7861 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7862
7863 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7864 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7865 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7866 '%', rdata32);
7867
7868 /* blk66_c_count */
7869 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7870 if (blk88_c_count == 0) {
7871 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7872 "[Picture %d Quality] NO Data yet.\n",
7873 pic_number);
7874 /* reset all counts */
7875 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7876 return;
7877 }
7878 /* qp_c_sum */
7879 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7880
7881 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7882 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7883 pic_number, rdata32/blk88_c_count,
7884 rdata32, blk88_c_count);
7885
7886 /* intra_c_count */
7887 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7888
7889 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7890 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7891 pic_number, rdata32*100/blk88_c_count,
7892 '%', rdata32);
7893
7894 /* skipped_cu_c_count */
7895 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7896
7897 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7898 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7899 pic_number, rdata32*100/blk88_c_count,
7900 '%', rdata32);
7901
7902 /* coeff_non_zero_c_count */
7903 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7904
7905 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7906 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7907 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7908 '%', rdata32);
7909
7910 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7911 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7912 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7913
7914 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7915 "[Picture %d Quality] Y QP min : %d\n",
7916 pic_number, (rdata32>>0)&0xff);
7917
7918 frame->min_qp = (rdata32>>0)&0xff;
7919
7920 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7921 "[Picture %d Quality] Y QP max : %d\n",
7922 pic_number, (rdata32>>8)&0xff);
7923
7924 frame->max_qp = (rdata32>>8)&0xff;
7925
7926 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7927 "[Picture %d Quality] C QP min : %d\n",
7928 pic_number, (rdata32>>16)&0xff);
7929 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7930 "[Picture %d Quality] C QP max : %d\n",
7931 pic_number, (rdata32>>24)&0xff);
7932
7933 /* blk22_mv_count */
7934 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7935 if (blk22_mv_count == 0) {
7936 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7937 "[Picture %d Quality] NO MV Data yet.\n",
7938 pic_number);
7939 /* reset all counts */
7940 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7941 return;
7942 }
7943 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7944 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7945 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7946 /* should all be 0x00 or 0xff */
7947 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7948 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7949 pic_number, rdata32);
7950
7951 mvx_L0_hi = ((rdata32>>0)&0xff);
7952 mvy_L0_hi = ((rdata32>>8)&0xff);
7953 mvx_L1_hi = ((rdata32>>16)&0xff);
7954 mvy_L1_hi = ((rdata32>>24)&0xff);
7955
7956 /* mvx_L0_count[31:0] */
7957 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7958 temp_value = mvx_L0_hi;
7959 temp_value = (temp_value << 32) | rdata32_l;
7960
7961 if (mvx_L0_hi & 0x80)
7962 value = 0xFFFFFFF000000000 | temp_value;
7963 else
7964 value = temp_value;
7965
7966 value = div_s64(value, blk22_mv_count);
7967
7968 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7969 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7970 pic_number, (int)value,
7971 value, blk22_mv_count);
7972
7973 frame->avg_mv = value;
7974
7975 /* mvy_L0_count[31:0] */
7976 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7977 temp_value = mvy_L0_hi;
7978 temp_value = (temp_value << 32) | rdata32_l;
7979
7980 if (mvy_L0_hi & 0x80)
7981 value = 0xFFFFFFF000000000 | temp_value;
7982 else
7983 value = temp_value;
7984
7985 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7986 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7987 pic_number, rdata32_l/blk22_mv_count,
7988 value, blk22_mv_count);
7989
7990 /* mvx_L1_count[31:0] */
7991 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7992 temp_value = mvx_L1_hi;
7993 temp_value = (temp_value << 32) | rdata32_l;
7994 if (mvx_L1_hi & 0x80)
7995 value = 0xFFFFFFF000000000 | temp_value;
7996 else
7997 value = temp_value;
7998
7999 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8000 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
8001 pic_number, rdata32_l/blk22_mv_count,
8002 value, blk22_mv_count);
8003
8004 /* mvy_L1_count[31:0] */
8005 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
8006 temp_value = mvy_L1_hi;
8007 temp_value = (temp_value << 32) | rdata32_l;
8008 if (mvy_L1_hi & 0x80)
8009 value = 0xFFFFFFF000000000 | temp_value;
8010 else
8011 value = temp_value;
8012
8013 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8014 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
8015 pic_number, rdata32_l/blk22_mv_count,
8016 value, blk22_mv_count);
8017
8018 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
8019 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8020 mv_hi = (rdata32>>16)&0xffff;
8021 if (mv_hi & 0x8000)
8022 mv_hi = 0x8000 - mv_hi;
8023
8024 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8025 "[Picture %d Quality] MVX_L0 MAX : %d\n",
8026 pic_number, mv_hi);
8027
8028 frame->max_mv = mv_hi;
8029
8030 mv_lo = (rdata32>>0)&0xffff;
8031 if (mv_lo & 0x8000)
8032 mv_lo = 0x8000 - mv_lo;
8033
8034 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8035 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8036 pic_number, mv_lo);
8037
8038 frame->min_mv = mv_lo;
8039
8040 /* {mvy_L0_max, mvy_L0_min} */
8041 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8042 mv_hi = (rdata32>>16)&0xffff;
8043 if (mv_hi & 0x8000)
8044 mv_hi = 0x8000 - mv_hi;
8045
8046 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8047 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8048 pic_number, mv_hi);
8049
8050 mv_lo = (rdata32>>0)&0xffff;
8051 if (mv_lo & 0x8000)
8052 mv_lo = 0x8000 - mv_lo;
8053
8054 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8055 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8056 pic_number, mv_lo);
8057
8058 /* {mvx_L1_max, mvx_L1_min} */
8059 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8060 mv_hi = (rdata32>>16)&0xffff;
8061 if (mv_hi & 0x8000)
8062 mv_hi = 0x8000 - mv_hi;
8063
8064 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8065 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8066 pic_number, mv_hi);
8067
8068 mv_lo = (rdata32>>0)&0xffff;
8069 if (mv_lo & 0x8000)
8070 mv_lo = 0x8000 - mv_lo;
8071
8072 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8073 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8074 pic_number, mv_lo);
8075
8076 /* {mvy_L1_max, mvy_L1_min} */
8077 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8078 mv_hi = (rdata32>>16)&0xffff;
8079 if (mv_hi & 0x8000)
8080 mv_hi = 0x8000 - mv_hi;
8081
8082 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8083 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8084 pic_number, mv_hi);
8085
8086 mv_lo = (rdata32>>0)&0xffff;
8087 if (mv_lo & 0x8000)
8088 mv_lo = 0x8000 - mv_lo;
8089
8090 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8091 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8092 pic_number, mv_lo);
8093
8094 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8095
8096 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8097 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8098 pic_number, rdata32);
8099
8100 /* reset all counts */
8101 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8102 }
8103}
8104
8105static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8106{
8107 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8108 unsigned int dec_status = pbi->dec_status;
8109 int i;
8110
8111 /*if (pbi->wait_buf)
8112 * pr_info("set wait_buf to 0\r\n");
8113 */
8114 if (pbi->eos)
8115 return IRQ_HANDLED;
8116 pbi->wait_buf = 0;
8117#ifdef MULTI_INSTANCE_SUPPORT
8118#ifdef SUPPORT_FB_DECODING
8119#ifdef FB_DECODING_TEST_SCHEDULE
8120 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8121 dec_status = HEVC_DECPIC_DATA_DONE;
8122 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8123 && dec_status == HEVC_DECPIC_DATA_DONE)
8124 dec_status = HEVC_S2_DECODING_DONE;
8125 pbi->s1_test_cmd = TEST_SET_NONE;
8126#else
8127 /*if (irq != VDEC_IRQ_0)
8128 dec_status = HEVC_S2_DECODING_DONE;*/
8129#endif
8130 if (dec_status == HEVC_S2_DECODING_DONE) {
8131 pbi->dec_result = DEC_RESULT_DONE;
8132 vdec_schedule_work(&pbi->work);
8133#ifdef FB_DECODING_TEST_SCHEDULE
8134 amhevc_stop();
8135 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8136 vdec_schedule_work(&pbi->s1_work);
8137#endif
8138 } else
8139#endif
8140 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8141 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8142 (dec_status == HEVC_DECODE_BUFEMPTY)
8143 ) {
8144 if (pbi->m_ins_flag) {
8145 reset_process_time(pbi);
8146 if (!vdec_frame_based(hw_to_vdec(pbi)))
8147 dec_again_process(pbi);
8148 else {
8149 pbi->dec_result = DEC_RESULT_GET_DATA;
8150 vdec_schedule_work(&pbi->work);
8151 }
8152 }
8153 pbi->process_busy = 0;
8154 return IRQ_HANDLED;
8155 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8156 if (pbi->m_ins_flag) {
8157 get_picture_qos_info(pbi);
8158#ifdef SUPPORT_FB_DECODING
8159 if (pbi->used_stage_buf_num > 0) {
8160 reset_process_time(pbi);
8161 inc_s1_pos(pbi);
8162 trigger_schedule(pbi);
8163#ifdef FB_DECODING_TEST_SCHEDULE
8164 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8165#else
8166 amhevc_stop();
8167 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8168 vdec_schedule_work(&pbi->s1_work);
8169#endif
8170 } else
8171#endif
8172 {
8173 reset_process_time(pbi);
8174 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8175 vp9_bufmgr_postproc(pbi);
8176
8177 pbi->dec_result = DEC_RESULT_DONE;
8178 amhevc_stop();
8179 if (mcrcc_cache_alg_flag)
8180 dump_hit_rate(pbi);
8181 vdec_schedule_work(&pbi->work);
8182 }
8183 } else {
8184 if (pbi->low_latency_flag) {
8185 vp9_bufmgr_postproc(pbi);
8186 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8187#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8188 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8189 if (debug & PRINT_FLAG_VDEC_DETAIL)
8190 pr_info("%s VP9 frame done \n", __func__);
8191#endif
8192 }
8193 }
8194
8195 pbi->process_busy = 0;
8196 return IRQ_HANDLED;
8197 }
8198#endif
8199
8200 if (dec_status == VP9_EOS) {
8201#ifdef MULTI_INSTANCE_SUPPORT
8202 if (pbi->m_ins_flag)
8203 reset_process_time(pbi);
8204#endif
8205
8206 pr_info("VP9_EOS, flush buffer\r\n");
8207
8208 vp9_bufmgr_postproc(pbi);
8209
8210 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8211 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8212 pbi->process_busy = 0;
8213#ifdef MULTI_INSTANCE_SUPPORT
8214 if (pbi->m_ins_flag) {
8215 pbi->dec_result = DEC_RESULT_DONE;
8216 amhevc_stop();
8217 vdec_schedule_work(&pbi->work);
8218 }
8219#endif
8220 return IRQ_HANDLED;
8221 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8222 pr_info("vp9 decode oversize !!\n");
8223 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8224 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8225 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8226#ifdef MULTI_INSTANCE_SUPPORT
8227 if (pbi->m_ins_flag)
8228 reset_process_time(pbi);
8229#endif
8230 return IRQ_HANDLED;
8231 }
8232
8233 if (dec_status != VP9_HEAD_PARSER_DONE) {
8234 pbi->process_busy = 0;
8235 return IRQ_HANDLED;
8236 }
8237
8238
8239#ifdef MULTI_INSTANCE_SUPPORT
8240#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8241 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8242 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8243 if (debug & PRINT_FLAG_VDEC_DETAIL)
8244 pr_info("%s VP9 frame header found \n", __func__);
8245 }
8246#endif
8247 if (pbi->m_ins_flag)
8248 reset_process_time(pbi);
8249#endif
8250 if (pbi->process_state != PROC_STATE_SENDAGAIN
8251#ifdef SUPPORT_FB_DECODING
8252 && pbi->used_stage_buf_num == 0
8253#endif
8254 ) {
8255 if (pbi->mmu_enable)
8256 vp9_recycle_mmu_buf_tail(pbi);
8257
8258
8259 if (pbi->frame_count > 0)
8260 vp9_bufmgr_postproc(pbi);
8261 }
8262
8263 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8264 get_rpm_param(&vp9_param);
8265 } else {
8266#ifdef SUPPORT_FB_DECODING
8267 if (pbi->used_stage_buf_num > 0) {
8268 reset_process_time(pbi);
8269 get_s1_buf(pbi);
8270
8271 if (get_mv_buf(pbi,
8272 &pbi->s1_mv_buf_index,
8273 &pbi->s1_mpred_mv_wr_start_addr
8274 ) < 0) {
8275 vp9_print(pbi, 0,
8276 "%s: Error get_mv_buf fail\n",
8277 __func__);
8278 }
8279
8280 if (pbi->s1_buf == NULL) {
8281 vp9_print(pbi, 0,
8282 "%s: Error get_s1_buf fail\n",
8283 __func__);
8284 pbi->process_busy = 0;
8285 return IRQ_HANDLED;
8286 }
8287
8288 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8289 int ii;
8290 for (ii = 0; ii < 4; ii++) {
8291 pbi->s1_buf->rpm[i + 3 - ii] =
8292 pbi->rpm_ptr[i + 3 - ii];
8293 pbi->s1_param.l.data[i + ii] =
8294 pbi->rpm_ptr[i + 3 - ii];
8295 }
8296 }
8297
8298 mpred_process(pbi);
8299#ifdef FB_DECODING_TEST_SCHEDULE
8300 pbi->dec_s1_result =
8301 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8302 vdec_schedule_work(&pbi->s1_work);
8303#else
8304 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8305 pbi->stage_mmu_map_phy_addr +
8306 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8307
8308 start_s1_decoding(pbi);
8309#endif
8310 start_process_time(pbi);
8311 pbi->process_busy = 0;
8312 return IRQ_HANDLED;
8313 } else
8314#endif
8315 {
8316 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8317 int ii;
8318 for (ii = 0; ii < 4; ii++)
8319 vp9_param.l.data[i + ii] =
8320 pbi->rpm_ptr[i + 3 - ii];
8321 }
8322 }
8323 }
8324
8325 if (pbi->is_used_v4l) {
8326 struct aml_vcodec_ctx *ctx =
8327 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8328
8329 pbi->frame_width = vp9_param.p.width;
8330 pbi->frame_height = vp9_param.p.height;
8331 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8332 struct aml_vdec_ps_infos ps;
8333
8334 ps.visible_width = pbi->frame_width;
8335 ps.visible_height = pbi->frame_height;
8336 ps.coded_width = ALIGN(pbi->frame_width, 32);
8337 ps.coded_height = ALIGN(pbi->frame_height, 32);
8338 ps.dpb_size = pbi->used_buf_num;
8339 pbi->v4l_params_parsed = true;
8340 vdec_v4l_set_ps_infos(ctx, &ps);
8341 }
8342 }
8343
8344 if (pbi->is_used_v4l) {
8345 pbi->dec_result = DEC_V4L2_CONTINUE_DECODING;
8346 vdec_schedule_work(&pbi->work);
8347 } else {
8348 continue_decoding(pbi);
8349 pbi->postproc_done = 0;
8350 pbi->process_busy = 0;
8351 }
8352
8353#ifdef MULTI_INSTANCE_SUPPORT
8354 if (pbi->m_ins_flag)
8355 start_process_time(pbi);
8356#endif
8357
8358 return IRQ_HANDLED;
8359}
8360
8361static irqreturn_t vvp9_isr(int irq, void *data)
8362{
8363 int i;
8364 unsigned int dec_status;
8365 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8366 unsigned int adapt_prob_status;
8367 struct VP9_Common_s *const cm = &pbi->common;
8368 uint debug_tag;
8369
8370 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8371
8372 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8373 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8374 if (!pbi)
8375 return IRQ_HANDLED;
8376 if (pbi->init_flag == 0)
8377 return IRQ_HANDLED;
8378 if (pbi->process_busy)/*on process.*/
8379 return IRQ_HANDLED;
8380 pbi->dec_status = dec_status;
8381 pbi->process_busy = 1;
8382 if (debug & VP9_DEBUG_BUFMGR)
8383 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8384 irq,
8385 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8386 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8387 READ_VREG(HEVC_STREAM_START_ADDR),
8388 READ_VREG(HEVC_STREAM_END_ADDR),
8389 READ_VREG(HEVC_STREAM_LEVEL),
8390 READ_VREG(HEVC_STREAM_WR_PTR),
8391 READ_VREG(HEVC_STREAM_RD_PTR)
8392 );
8393#ifdef SUPPORT_FB_DECODING
8394 /*if (irq != VDEC_IRQ_0)
8395 return IRQ_WAKE_THREAD;*/
8396#endif
8397
8398 debug_tag = READ_HREG(DEBUG_REG1);
8399 if (debug_tag & 0x10000) {
8400 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8401 for (i = 0; i < 0x400; i += 4) {
8402 int ii;
8403 if ((i & 0xf) == 0)
8404 pr_info("%03x: ", i);
8405 for (ii = 0; ii < 4; ii++) {
8406 pr_info("%04x ",
8407 pbi->lmem_ptr[i + 3 - ii]);
8408 }
8409 if (((i + ii) & 0xf) == 0)
8410 pr_info("\n");
8411 }
8412
8413 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8414 (udebug_pause_decode_idx == 0 ||
8415 udebug_pause_decode_idx == pbi->slice_idx) &&
8416 (udebug_pause_val == 0 ||
8417 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8418 pbi->ucode_pause_pos = udebug_pause_pos;
8419 else if (debug_tag & 0x20000)
8420 pbi->ucode_pause_pos = 0xffffffff;
8421 if (pbi->ucode_pause_pos)
8422 reset_process_time(pbi);
8423 else
8424 WRITE_HREG(DEBUG_REG1, 0);
8425 } else if (debug_tag != 0) {
8426 pr_info(
8427 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8428 READ_HREG(DEBUG_REG2),
8429 READ_VREG(HEVC_PARSER_LCU_START));
8430 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8431 (udebug_pause_decode_idx == 0 ||
8432 udebug_pause_decode_idx == pbi->slice_idx) &&
8433 (udebug_pause_val == 0 ||
8434 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8435 pbi->ucode_pause_pos = udebug_pause_pos;
8436 if (pbi->ucode_pause_pos)
8437 reset_process_time(pbi);
8438 else
8439 WRITE_HREG(DEBUG_REG1, 0);
8440 pbi->process_busy = 0;
8441 return IRQ_HANDLED;
8442 }
8443
8444#ifdef MULTI_INSTANCE_SUPPORT
8445 if (!pbi->m_ins_flag) {
8446#endif
8447 if (pbi->error_flag == 1) {
8448 pbi->error_flag = 2;
8449 pbi->process_busy = 0;
8450 return IRQ_HANDLED;
8451 } else if (pbi->error_flag == 3) {
8452 pbi->process_busy = 0;
8453 return IRQ_HANDLED;
8454 }
8455
8456 if (get_free_buf_count(pbi) <= 0) {
8457 /*
8458 if (pbi->wait_buf == 0)
8459 pr_info("set wait_buf to 1\r\n");
8460 */
8461 pbi->wait_buf = 1;
8462 pbi->process_busy = 0;
8463 return IRQ_HANDLED;
8464 }
8465#ifdef MULTI_INSTANCE_SUPPORT
8466 }
8467#endif
8468 if ((adapt_prob_status & 0xff) == 0xfd) {
8469 /*VP9_REQ_ADAPT_PROB*/
8470 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8471 uint8_t *prev_prob_b =
8472 ((uint8_t *)pbi->prob_buffer_addr) +
8473 ((adapt_prob_status >> 8) * 0x1000);
8474 uint8_t *cur_prob_b =
8475 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8476 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8477#ifdef MULTI_INSTANCE_SUPPORT
8478 if (pbi->m_ins_flag)
8479 reset_process_time(pbi);
8480#endif
8481 adapt_coef_probs(pbi->pic_count,
8482 (cm->last_frame_type == KEY_FRAME),
8483 pre_fc, (adapt_prob_status >> 8),
8484 (unsigned int *)prev_prob_b,
8485 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8486
8487 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8488 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8489 pbi->pic_count += 1;
8490#ifdef MULTI_INSTANCE_SUPPORT
8491 if (pbi->m_ins_flag)
8492 start_process_time(pbi);
8493#endif
8494
8495 /*return IRQ_HANDLED;*/
8496 }
8497 return IRQ_WAKE_THREAD;
8498}
8499
8500static void vp9_set_clk(struct work_struct *work)
8501{
8502 struct VP9Decoder_s *pbi = container_of(work,
8503 struct VP9Decoder_s, set_clk_work);
8504 int fps = 96000 / pbi->frame_dur;
8505
8506 if (hevc_source_changed(VFORMAT_VP9,
8507 frame_width, frame_height, fps) > 0)
8508 pbi->saved_resolution = frame_width *
8509 frame_height * fps;
8510}
8511
8512static void vvp9_put_timer_func(unsigned long arg)
8513{
8514 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8515 struct timer_list *timer = &pbi->timer;
8516 uint8_t empty_flag;
8517 unsigned int buf_level;
8518
8519 enum receviver_start_e state = RECEIVER_INACTIVE;
8520
8521 if (pbi->m_ins_flag) {
8522 if (hw_to_vdec(pbi)->next_status
8523 == VDEC_STATUS_DISCONNECTED) {
8524#ifdef SUPPORT_FB_DECODING
8525 if (pbi->run2_busy)
8526 return;
8527
8528 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8529 vdec_schedule_work(&pbi->s1_work);
8530#endif
8531 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8532 vdec_schedule_work(&pbi->work);
8533 pr_debug(
8534 "vdec requested to be disconnected\n");
8535 return;
8536 }
8537 }
8538 if (pbi->init_flag == 0) {
8539 if (pbi->stat & STAT_TIMER_ARM) {
8540 timer->expires = jiffies + PUT_INTERVAL;
8541 add_timer(&pbi->timer);
8542 }
8543 return;
8544 }
8545 if (pbi->m_ins_flag == 0) {
8546 if (vf_get_receiver(pbi->provider_name)) {
8547 state =
8548 vf_notify_receiver(pbi->provider_name,
8549 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8550 NULL);
8551 if ((state == RECEIVER_STATE_NULL)
8552 || (state == RECEIVER_STATE_NONE))
8553 state = RECEIVER_INACTIVE;
8554 } else
8555 state = RECEIVER_INACTIVE;
8556
8557 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8558 /* error watchdog */
8559 if (empty_flag == 0) {
8560 /* decoder has input */
8561 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8562
8563 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8564 /* receiver has no buffer to recycle */
8565 if ((state == RECEIVER_INACTIVE) &&
8566 (kfifo_is_empty(&pbi->display_q) &&
8567 buf_level > 0x200)
8568 ) {
8569 WRITE_VREG
8570 (HEVC_ASSIST_MBOX0_IRQ_REG,
8571 0x1);
8572 }
8573 }
8574
8575 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8576 /* receiver has no buffer to recycle */
8577 /*if ((state == RECEIVER_INACTIVE) &&
8578 * (kfifo_is_empty(&pbi->display_q))) {
8579 *pr_info("vp9 something error,need reset\n");
8580 *}
8581 */
8582 }
8583 }
8584 }
8585#ifdef MULTI_INSTANCE_SUPPORT
8586 else {
8587 if (
8588 (decode_timeout_val > 0) &&
8589 (pbi->start_process_time > 0) &&
8590 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8591 > decode_timeout_val)
8592 ) {
8593 int current_lcu_idx =
8594 READ_VREG(HEVC_PARSER_LCU_START)
8595 & 0xffffff;
8596 if (pbi->last_lcu_idx == current_lcu_idx) {
8597 if (pbi->decode_timeout_count > 0)
8598 pbi->decode_timeout_count--;
8599 if (pbi->decode_timeout_count == 0) {
8600 if (input_frame_based(
8601 hw_to_vdec(pbi)) ||
8602 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8603 timeout_process(pbi);
8604 else {
8605 vp9_print(pbi, 0,
8606 "timeout & empty, again\n");
8607 dec_again_process(pbi);
8608 }
8609 }
8610 } else {
8611 start_process_time(pbi);
8612 pbi->last_lcu_idx = current_lcu_idx;
8613 }
8614 }
8615 }
8616#endif
8617
8618 if ((pbi->ucode_pause_pos != 0) &&
8619 (pbi->ucode_pause_pos != 0xffffffff) &&
8620 udebug_pause_pos != pbi->ucode_pause_pos) {
8621 pbi->ucode_pause_pos = 0;
8622 WRITE_HREG(DEBUG_REG1, 0);
8623 }
8624#ifdef MULTI_INSTANCE_SUPPORT
8625 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8626 pr_info(
8627 "Force Send Again\r\n");
8628 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8629 reset_process_time(pbi);
8630 pbi->dec_result = DEC_RESULT_AGAIN;
8631 if (pbi->process_state ==
8632 PROC_STATE_DECODESLICE) {
8633 if (pbi->mmu_enable)
8634 vp9_recycle_mmu_buf(pbi);
8635 pbi->process_state =
8636 PROC_STATE_SENDAGAIN;
8637 }
8638 amhevc_stop();
8639
8640 vdec_schedule_work(&pbi->work);
8641 }
8642
8643 if (debug & VP9_DEBUG_DUMP_DATA) {
8644 debug &= ~VP9_DEBUG_DUMP_DATA;
8645 vp9_print(pbi, 0,
8646 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8647 __func__,
8648 pbi->chunk->size,
8649 pbi->chunk->offset,
8650 get_data_check_sum(pbi, pbi->chunk->size)
8651 );
8652 dump_data(pbi, pbi->chunk->size);
8653 }
8654#endif
8655 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8656 dump_pic_list(pbi);
8657 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8658 }
8659 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8660 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8661 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8662 }
8663 /*if (debug & VP9_DEBUG_HW_RESET) {
8664 }*/
8665
8666 if (radr != 0) {
8667 if (rval != 0) {
8668 WRITE_VREG(radr, rval);
8669 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8670 } else
8671 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8672 rval = 0;
8673 radr = 0;
8674 }
8675 if (pop_shorts != 0) {
8676 int i;
8677 u32 sum = 0;
8678
8679 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8680 for (i = 0; i < pop_shorts; i++) {
8681 u32 data =
8682 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8683 WRITE_HREG(HEVC_SHIFT_COMMAND,
8684 (1<<7)|16);
8685 if ((i & 0xf) == 0)
8686 pr_info("%04x:", i);
8687 pr_info("%04x ", data);
8688 if (((i + 1) & 0xf) == 0)
8689 pr_info("\r\n");
8690 sum += data;
8691 }
8692 pr_info("\r\nsum = %x\r\n", sum);
8693 pop_shorts = 0;
8694 }
8695 if (dbg_cmd != 0) {
8696 if (dbg_cmd == 1) {
8697 u32 disp_laddr;
8698
8699 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8700 get_double_write_mode(pbi) == 0) {
8701 disp_laddr =
8702 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8703 } else {
8704 struct canvas_s cur_canvas;
8705
8706 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8707 & 0xff), &cur_canvas);
8708 disp_laddr = cur_canvas.addr;
8709 }
8710 pr_info("current displayed buffer address %x\r\n",
8711 disp_laddr);
8712 }
8713 dbg_cmd = 0;
8714 }
8715 /*don't changed at start.*/
8716 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8717 pbi->frame_dur > 0 && pbi->saved_resolution !=
8718 frame_width * frame_height *
8719 (96000 / pbi->frame_dur))
8720 vdec_schedule_work(&pbi->set_clk_work);
8721
8722 timer->expires = jiffies + PUT_INTERVAL;
8723 add_timer(timer);
8724}
8725
8726
8727int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8728{
8729 struct VP9Decoder_s *vp9 =
8730 (struct VP9Decoder_s *)vdec->private;
8731
8732 if (!vp9)
8733 return -1;
8734
8735 vstatus->frame_width = frame_width;
8736 vstatus->frame_height = frame_height;
8737 if (vp9->frame_dur != 0)
8738 vstatus->frame_rate = 96000 / vp9->frame_dur;
8739 else
8740 vstatus->frame_rate = -1;
8741 vstatus->error_count = 0;
8742 vstatus->status = vp9->stat | vp9->fatal_error;
8743 vstatus->frame_dur = vp9->frame_dur;
8744#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8745 vstatus->bit_rate = gvs->bit_rate;
8746 vstatus->frame_data = gvs->frame_data;
8747 vstatus->total_data = gvs->total_data;
8748 vstatus->frame_count = gvs->frame_count;
8749 vstatus->error_frame_count = gvs->error_frame_count;
8750 vstatus->drop_frame_count = gvs->drop_frame_count;
8751 vstatus->total_data = gvs->total_data;
8752 vstatus->samp_cnt = gvs->samp_cnt;
8753 vstatus->offset = gvs->offset;
8754 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8755 "%s", DRIVER_NAME);
8756#endif
8757 return 0;
8758}
8759
8760int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8761{
8762 is_reset = isreset;
8763 return 0;
8764}
8765
8766#if 0
8767static void VP9_DECODE_INIT(void)
8768{
8769 /* enable vp9 clocks */
8770 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8771 /* *************************************************************** */
8772 /* Power ON HEVC */
8773 /* *************************************************************** */
8774 /* Powerup HEVC */
8775 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8776 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8777 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8778 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8779 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8780 /* remove isolations */
8781 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8782 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8783
8784}
8785#endif
8786
8787static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8788{
8789 unsigned int data32;
8790 /* VP9_DECODE_INIT(); */
8791 vp9_config_work_space_hw(pbi, mask);
8792 if (mask & HW_MASK_BACK)
8793 init_pic_list_hw(pbi);
8794
8795 vp9_init_decoder_hw(pbi, mask);
8796
8797#ifdef VP9_LPF_LVL_UPDATE
8798 if (mask & HW_MASK_BACK)
8799 vp9_loop_filter_init(pbi);
8800#endif
8801
8802 if ((mask & HW_MASK_FRONT) == 0)
8803 return;
8804#if 1
8805 if (debug & VP9_DEBUG_BUFMGR_MORE)
8806 pr_info("%s\n", __func__);
8807 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8808 data32 = data32 |
8809 (1 << 0)/*stream_fetch_enable*/
8810 ;
8811 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8812
8813 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8814 if (debug & VP9_DEBUG_BUFMGR)
8815 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8816 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8817 data32 = data32 |
8818 (1 << 29) // stream_fifo_hole
8819 ;
8820 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8821 }
8822#if 0
8823 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8824 if (data32 != 0x00000100) {
8825 pr_info("vp9 prot init error %d\n", __LINE__);
8826 return;
8827 }
8828 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8829 if (data32 != 0x00000300) {
8830 pr_info("vp9 prot init error %d\n", __LINE__);
8831 return;
8832 }
8833 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8834 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8835 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8836 if (data32 != 0x12345678) {
8837 pr_info("vp9 prot init error %d\n", __LINE__);
8838 return;
8839 }
8840 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8841 if (data32 != 0x9abcdef0) {
8842 pr_info("vp9 prot init error %d\n", __LINE__);
8843 return;
8844 }
8845#endif
8846 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8847 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8848#endif
8849
8850
8851
8852 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8853
8854 /* WRITE_VREG(HEVC_MPSR, 1); */
8855
8856 /* clear mailbox interrupt */
8857 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8858
8859 /* enable mailbox interrupt */
8860 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8861
8862 /* disable PSCALE for hardware sharing */
8863 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8864
8865 WRITE_VREG(DEBUG_REG1, 0x0);
8866 /*check vps/sps/pps/i-slice in ucode*/
8867 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8868
8869 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8870#ifdef SUPPORT_FB_DECODING
8871#ifndef FB_DECODING_TEST_SCHEDULE
8872 if (pbi->used_stage_buf_num > 0) {
8873 if (mask & HW_MASK_FRONT) {
8874 data32 = READ_VREG(
8875 HEVC_ASSIST_HED_FB_W_CTL);
8876 data32 = data32 |
8877 (1 << 0) /*hed_fb_wr_en*/
8878 ;
8879 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8880 data32);
8881 }
8882 if (mask & HW_MASK_BACK) {
8883 data32 = READ_VREG(
8884 HEVC_ASSIST_HED_FB_R_CTL);
8885 while (data32 & (1 << 7)) {
8886 /*wait finish*/
8887 data32 = READ_VREG(
8888 HEVC_ASSIST_HED_FB_R_CTL);
8889 }
8890 data32 &= (~(0x1 << 0));
8891 /*hed_fb_rd_addr_auto_rd*/
8892 data32 &= (~(0x1 << 1));
8893 /*rd_id = 0, hed_rd_map_auto_halt_num,
8894 after wr 2 ready, then start reading*/
8895 data32 |= (0x2 << 16);
8896 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8897 data32);
8898
8899 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8900 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8901 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8902 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8903 data32);
8904 }
8905
8906 }
8907#endif
8908#endif
8909}
8910
8911static int vvp9_local_init(struct VP9Decoder_s *pbi)
8912{
8913 int i;
8914 int ret;
8915 int width, height;
8916 if (alloc_lf_buf(pbi) < 0)
8917 return -1;
8918
8919 pbi->gvs = vzalloc(sizeof(struct vdec_info));
8920 if (NULL == pbi->gvs) {
8921 pr_info("the struct of vdec status malloc failed.\n");
8922 return -1;
8923 }
8924#ifdef DEBUG_PTS
8925 pbi->pts_missed = 0;
8926 pbi->pts_hit = 0;
8927#endif
8928 pbi->new_frame_displayed = 0;
8929 pbi->last_put_idx = -1;
8930 pbi->saved_resolution = 0;
8931 pbi->get_frame_dur = false;
8932 on_no_keyframe_skiped = 0;
8933 pbi->duration_from_pts_done = 0;
8934 pbi->vp9_first_pts_ready = 0;
8935 pbi->frame_cnt_window = 0;
8936 width = pbi->vvp9_amstream_dec_info.width;
8937 height = pbi->vvp9_amstream_dec_info.height;
8938 pbi->frame_dur =
8939 (pbi->vvp9_amstream_dec_info.rate ==
8940 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8941 if (width && height)
8942 pbi->frame_ar = height * 0x100 / width;
8943/*
8944 *TODO:FOR VERSION
8945 */
8946 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8947 0, width, height, pbi->frame_dur);
8948
8949 if (pbi->frame_dur == 0)
8950 pbi->frame_dur = 96000 / 24;
8951
8952 INIT_KFIFO(pbi->display_q);
8953 INIT_KFIFO(pbi->newframe_q);
8954
8955
8956 for (i = 0; i < VF_POOL_SIZE; i++) {
8957 const struct vframe_s *vf = &pbi->vfpool[i];
8958
8959 pbi->vfpool[i].index = -1;
8960 kfifo_put(&pbi->newframe_q, vf);
8961 }
8962
8963
8964 ret = vp9_local_init(pbi);
8965
8966 if (!pbi->pts_unstable) {
8967 pbi->pts_unstable =
8968 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8969 pr_info("set pts unstable\n");
8970 }
8971
8972 return ret;
8973}
8974
8975
8976#ifdef MULTI_INSTANCE_SUPPORT
8977static s32 vvp9_init(struct vdec_s *vdec)
8978{
8979 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8980#else
8981static s32 vvp9_init(struct VP9Decoder_s *pbi)
8982{
8983#endif
8984 int ret;
8985 int fw_size = 0x1000 * 16;
8986 struct firmware_s *fw = NULL;
8987
8988 pbi->stat |= STAT_TIMER_INIT;
8989
8990 if (vvp9_local_init(pbi) < 0)
8991 return -EBUSY;
8992
8993 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8994 if (IS_ERR_OR_NULL(fw))
8995 return -ENOMEM;
8996
8997 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8998 pr_err("get firmware fail.\n");
8999 vfree(fw);
9000 return -1;
9001 }
9002
9003 fw->len = fw_size;
9004
9005 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
9006 init_timer(&pbi->timer);
9007
9008#ifdef MULTI_INSTANCE_SUPPORT
9009 if (pbi->m_ins_flag) {
9010 pbi->timer.data = (ulong) pbi;
9011 pbi->timer.function = vvp9_put_timer_func;
9012 pbi->timer.expires = jiffies + PUT_INTERVAL;
9013
9014 /*add_timer(&pbi->timer);
9015
9016 pbi->stat |= STAT_TIMER_ARM;
9017 pbi->stat |= STAT_ISR_REG;*/
9018
9019 INIT_WORK(&pbi->work, vp9_work);
9020#ifdef SUPPORT_FB_DECODING
9021 if (pbi->used_stage_buf_num > 0)
9022 INIT_WORK(&pbi->s1_work, vp9_s1_work);
9023#endif
9024 pbi->fw = fw;
9025
9026 /* picture list init.*/
9027 pbi->dec_result = DEC_INIT_PICLIST;
9028 vdec_schedule_work(&pbi->work);
9029
9030 return 0;
9031 }
9032#endif
9033 amhevc_enable();
9034
9035 init_pic_list(pbi);
9036
9037 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9038 if (ret < 0) {
9039 amhevc_disable();
9040 vfree(fw);
9041 pr_err("VP9: the %s fw loading failed, err: %x\n",
9042 tee_enabled() ? "TEE" : "local", ret);
9043 return -EBUSY;
9044 }
9045
9046 vfree(fw);
9047
9048 pbi->stat |= STAT_MC_LOAD;
9049
9050 /* enable AMRISC side protocol */
9051 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9052
9053 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9054 vvp9_isr,
9055 vvp9_isr_thread_fn,
9056 IRQF_ONESHOT,/*run thread on this irq disabled*/
9057 "vvp9-irq", (void *)pbi)) {
9058 pr_info("vvp9 irq register error.\n");
9059 amhevc_disable();
9060 return -ENOENT;
9061 }
9062
9063 pbi->stat |= STAT_ISR_REG;
9064
9065 pbi->provider_name = PROVIDER_NAME;
9066#ifdef MULTI_INSTANCE_SUPPORT
9067 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9068 &vvp9_vf_provider, pbi);
9069 vf_reg_provider(&vvp9_vf_prov);
9070 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9071 if (pbi->frame_dur != 0) {
9072 if (!is_reset)
9073 vf_notify_receiver(pbi->provider_name,
9074 VFRAME_EVENT_PROVIDER_FR_HINT,
9075 (void *)
9076 ((unsigned long)pbi->frame_dur));
9077 }
9078#else
9079 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9080 pbi);
9081 vf_reg_provider(&vvp9_vf_prov);
9082 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9083 if (!is_reset)
9084 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9085 (void *)((unsigned long)pbi->frame_dur));
9086#endif
9087 pbi->stat |= STAT_VF_HOOK;
9088
9089 pbi->timer.data = (ulong)pbi;
9090 pbi->timer.function = vvp9_put_timer_func;
9091 pbi->timer.expires = jiffies + PUT_INTERVAL;
9092
9093 pbi->stat |= STAT_VDEC_RUN;
9094
9095 add_timer(&pbi->timer);
9096
9097 pbi->stat |= STAT_TIMER_ARM;
9098
9099 amhevc_start();
9100
9101 pbi->init_flag = 1;
9102 pbi->process_busy = 0;
9103 pr_info("%d, vvp9_init, RP=0x%x\n",
9104 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9105 return 0;
9106}
9107
9108static int vmvp9_stop(struct VP9Decoder_s *pbi)
9109{
9110 pbi->init_flag = 0;
9111
9112 if (pbi->stat & STAT_VDEC_RUN) {
9113 amhevc_stop();
9114 pbi->stat &= ~STAT_VDEC_RUN;
9115 }
9116 if (pbi->stat & STAT_ISR_REG) {
9117 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9118 pbi->stat &= ~STAT_ISR_REG;
9119 }
9120 if (pbi->stat & STAT_TIMER_ARM) {
9121 del_timer_sync(&pbi->timer);
9122 pbi->stat &= ~STAT_TIMER_ARM;
9123 }
9124
9125 if (pbi->stat & STAT_VF_HOOK) {
9126 if (!is_reset)
9127 vf_notify_receiver(pbi->provider_name,
9128 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9129 NULL);
9130
9131 vf_unreg_provider(&vvp9_vf_prov);
9132 pbi->stat &= ~STAT_VF_HOOK;
9133 }
9134 vp9_local_uninit(pbi);
9135 reset_process_time(pbi);
9136 cancel_work_sync(&pbi->work);
9137#ifdef SUPPORT_FB_DECODING
9138 if (pbi->used_stage_buf_num > 0)
9139 cancel_work_sync(&pbi->s1_work);
9140#endif
9141 cancel_work_sync(&pbi->set_clk_work);
9142 uninit_mmu_buffers(pbi);
9143 if (pbi->fw)
9144 vfree(pbi->fw);
9145 pbi->fw = NULL;
9146 return 0;
9147}
9148
9149static int vvp9_stop(struct VP9Decoder_s *pbi)
9150{
9151
9152 pbi->init_flag = 0;
9153 pbi->first_sc_checked = 0;
9154 if (pbi->stat & STAT_VDEC_RUN) {
9155 amhevc_stop();
9156 pbi->stat &= ~STAT_VDEC_RUN;
9157 }
9158
9159 if (pbi->stat & STAT_ISR_REG) {
9160#ifdef MULTI_INSTANCE_SUPPORT
9161 if (!pbi->m_ins_flag)
9162#endif
9163 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9164 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9165 pbi->stat &= ~STAT_ISR_REG;
9166 }
9167
9168 if (pbi->stat & STAT_TIMER_ARM) {
9169 del_timer_sync(&pbi->timer);
9170 pbi->stat &= ~STAT_TIMER_ARM;
9171 }
9172
9173 if (pbi->stat & STAT_VF_HOOK) {
9174 if (!is_reset)
9175 vf_notify_receiver(pbi->provider_name,
9176 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9177 NULL);
9178
9179 vf_unreg_provider(&vvp9_vf_prov);
9180 pbi->stat &= ~STAT_VF_HOOK;
9181 }
9182 vp9_local_uninit(pbi);
9183
9184 cancel_work_sync(&pbi->set_clk_work);
9185#ifdef MULTI_INSTANCE_SUPPORT
9186 if (pbi->m_ins_flag) {
9187#ifdef SUPPORT_FB_DECODING
9188 if (pbi->used_stage_buf_num > 0)
9189 cancel_work_sync(&pbi->s1_work);
9190#endif
9191 cancel_work_sync(&pbi->work);
9192 } else
9193 amhevc_disable();
9194#else
9195 amhevc_disable();
9196#endif
9197 uninit_mmu_buffers(pbi);
9198
9199 vfree(pbi->fw);
9200 pbi->fw = NULL;
9201 return 0;
9202}
9203static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9204{
9205 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9206 CODEC_MM_FLAGS_TVP : 0;
9207 int buf_size = 48;
9208
9209 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9210 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9211 buf_size = 12;
9212 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9213 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9214 buf_size = 4;
9215 }
9216 pbi->need_cache_size = buf_size * SZ_1M;
9217 pbi->sc_start_time = get_jiffies_64();
9218 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9219 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9220 pbi->index, FRAME_BUFFERS,
9221 pbi->need_cache_size,
9222 tvp_flag
9223 );
9224 if (!pbi->mmu_box) {
9225 pr_err("vp9 alloc mmu box failed!!\n");
9226 return -1;
9227 }
9228 }
9229 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9230 DRIVER_NAME,
9231 pbi->index,
9232 MAX_BMMU_BUFFER_NUM,
9233 4 + PAGE_SHIFT,
9234 CODEC_MM_FLAGS_CMA_CLEAR |
9235 CODEC_MM_FLAGS_FOR_VDECODER |
9236 tvp_flag);
9237 if (!pbi->bmmu_box) {
9238 pr_err("vp9 alloc bmmu box failed!!\n");
9239 return -1;
9240 }
9241 return 0;
9242}
9243
9244static struct VP9Decoder_s *gHevc;
9245
9246static int amvdec_vp9_probe(struct platform_device *pdev)
9247{
9248 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9249 struct BUF_s BUF[MAX_BUF_NUM];
9250 struct VP9Decoder_s *pbi;
9251 int ret;
9252#ifndef MULTI_INSTANCE_SUPPORT
9253 int i;
9254#endif
9255 pr_debug("%s\n", __func__);
9256
9257 mutex_lock(&vvp9_mutex);
9258 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9259 if (pbi == NULL) {
9260 pr_info("\namvdec_vp9 device data allocation failed\n");
9261 mutex_unlock(&vvp9_mutex);
9262 return -ENOMEM;
9263 }
9264
9265 gHevc = pbi;
9266 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9267 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9268 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9269
9270 pbi->init_flag = 0;
9271 pbi->first_sc_checked= 0;
9272 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9273 vp9_max_pic_w = 8192;
9274 vp9_max_pic_h = 4608;
9275 }
9276 pbi->max_pic_w = vp9_max_pic_w;
9277 pbi->max_pic_h = vp9_max_pic_h;
9278
9279#ifdef MULTI_INSTANCE_SUPPORT
9280 pbi->eos = 0;
9281 pbi->start_process_time = 0;
9282 pbi->timeout_num = 0;
9283#endif
9284 pbi->fatal_error = 0;
9285 pbi->show_frame_num = 0;
9286 if (pdata == NULL) {
9287 pr_info("\namvdec_vp9 memory resource undefined.\n");
9288 vfree(pbi);
9289 mutex_unlock(&vvp9_mutex);
9290 return -EFAULT;
9291 }
9292 pbi->m_ins_flag = 0;
9293#ifdef MULTI_INSTANCE_SUPPORT
9294 pbi->platform_dev = pdev;
9295 platform_set_drvdata(pdev, pdata);
9296#endif
9297 pbi->double_write_mode = double_write_mode;
9298 pbi->mmu_enable = 1;
9299 if (amvdec_vp9_mmu_init(pbi) < 0) {
9300 vfree(pbi);
9301 mutex_unlock(&vvp9_mutex);
9302 pr_err("vp9 alloc bmmu box failed!!\n");
9303 return -1;
9304 }
9305
9306 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9307 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9308 if (ret < 0) {
9309 uninit_mmu_buffers(pbi);
9310 vfree(pbi);
9311 mutex_unlock(&vvp9_mutex);
9312 return ret;
9313 }
9314 pbi->buf_size = work_buf_size;
9315
9316#ifdef MULTI_INSTANCE_SUPPORT
9317 pbi->buf_start = pdata->mem_start;
9318#else
9319 if (!pbi->mmu_enable)
9320 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9321
9322 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9323 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9324#endif
9325
9326
9327 if (debug) {
9328 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9329 pdata->mem_start, pbi->buf_size);
9330 }
9331
9332 if (pdata->sys_info)
9333 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9334 else {
9335 pbi->vvp9_amstream_dec_info.width = 0;
9336 pbi->vvp9_amstream_dec_info.height = 0;
9337 pbi->vvp9_amstream_dec_info.rate = 30;
9338 }
9339 pbi->no_head = no_head;
9340#ifdef MULTI_INSTANCE_SUPPORT
9341 pbi->cma_dev = pdata->cma_dev;
9342#else
9343 cma_dev = pdata->cma_dev;
9344#endif
9345
9346#ifdef MULTI_INSTANCE_SUPPORT
9347 pdata->private = pbi;
9348 pdata->dec_status = vvp9_dec_status;
9349 pdata->set_isreset = vvp9_set_isreset;
9350 is_reset = 0;
9351 if (vvp9_init(pdata) < 0) {
9352#else
9353 if (vvp9_init(pbi) < 0) {
9354#endif
9355 pr_info("\namvdec_vp9 init failed.\n");
9356 vp9_local_uninit(pbi);
9357 uninit_mmu_buffers(pbi);
9358 vfree(pbi);
9359 pdata->dec_status = NULL;
9360 mutex_unlock(&vvp9_mutex);
9361 return -ENODEV;
9362 }
9363 /*set the max clk for smooth playing...*/
9364 hevc_source_changed(VFORMAT_VP9,
9365 4096, 2048, 60);
9366 mutex_unlock(&vvp9_mutex);
9367
9368 return 0;
9369}
9370
9371static int amvdec_vp9_remove(struct platform_device *pdev)
9372{
9373 struct VP9Decoder_s *pbi = gHevc;
9374 struct vdec_s *vdec = hw_to_vdec(pbi);
9375 int i;
9376
9377 if (debug)
9378 pr_info("amvdec_vp9_remove\n");
9379
9380 mutex_lock(&vvp9_mutex);
9381
9382 vvp9_stop(pbi);
9383
9384 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9385
9386 if (vdec->parallel_dec == 1) {
9387 for (i = 0; i < FRAME_BUFFERS; i++) {
9388 vdec->free_canvas_ex(pbi->common.buffer_pool->
9389 frame_bufs[i].buf.y_canvas_index, vdec->id);
9390 vdec->free_canvas_ex(pbi->common.buffer_pool->
9391 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9392 }
9393 }
9394
9395#ifdef DEBUG_PTS
9396 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9397 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9398#endif
9399 mem_map_mode = 0;
9400
9401 vfree(pbi);
9402 mutex_unlock(&vvp9_mutex);
9403
9404 return 0;
9405}
9406
9407/****************************************/
9408#ifdef CONFIG_PM
9409static int vp9_suspend(struct device *dev)
9410{
9411 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9412 return 0;
9413}
9414
9415static int vp9_resume(struct device *dev)
9416{
9417 amhevc_resume(to_platform_device(dev));
9418 return 0;
9419}
9420
9421static const struct dev_pm_ops vp9_pm_ops = {
9422 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9423};
9424#endif
9425
9426static struct platform_driver amvdec_vp9_driver = {
9427 .probe = amvdec_vp9_probe,
9428 .remove = amvdec_vp9_remove,
9429 .driver = {
9430 .name = DRIVER_NAME,
9431#ifdef CONFIG_PM
9432 .pm = &vp9_pm_ops,
9433#endif
9434 }
9435};
9436
9437static struct codec_profile_t amvdec_vp9_profile = {
9438 .name = "vp9",
9439 .profile = ""
9440};
9441
9442static struct codec_profile_t amvdec_vp9_profile_mult;
9443
9444static unsigned char get_data_check_sum
9445 (struct VP9Decoder_s *pbi, int size)
9446{
9447 int jj;
9448 int sum = 0;
9449 u8 *data = NULL;
9450
9451 if (!pbi->chunk->block->is_mapped)
9452 data = codec_mm_vmap(pbi->chunk->block->start +
9453 pbi->chunk->offset, size);
9454 else
9455 data = ((u8 *)pbi->chunk->block->start_virt) +
9456 pbi->chunk->offset;
9457
9458 for (jj = 0; jj < size; jj++)
9459 sum += data[jj];
9460
9461 if (!pbi->chunk->block->is_mapped)
9462 codec_mm_unmap_phyaddr(data);
9463 return sum;
9464}
9465
9466static void dump_data(struct VP9Decoder_s *pbi, int size)
9467{
9468 int jj;
9469 u8 *data = NULL;
9470 int padding_size = pbi->chunk->offset &
9471 (VDEC_FIFO_ALIGN - 1);
9472
9473 if (!pbi->chunk->block->is_mapped)
9474 data = codec_mm_vmap(pbi->chunk->block->start +
9475 pbi->chunk->offset, size);
9476 else
9477 data = ((u8 *)pbi->chunk->block->start_virt) +
9478 pbi->chunk->offset;
9479
9480 vp9_print(pbi, 0, "padding: ");
9481 for (jj = padding_size; jj > 0; jj--)
9482 vp9_print_cont(pbi,
9483 0,
9484 "%02x ", *(data - jj));
9485 vp9_print_cont(pbi, 0, "data adr %p\n",
9486 data);
9487
9488 for (jj = 0; jj < size; jj++) {
9489 if ((jj & 0xf) == 0)
9490 vp9_print(pbi,
9491 0,
9492 "%06x:", jj);
9493 vp9_print_cont(pbi,
9494 0,
9495 "%02x ", data[jj]);
9496 if (((jj + 1) & 0xf) == 0)
9497 vp9_print(pbi,
9498 0,
9499 "\n");
9500 }
9501 vp9_print(pbi,
9502 0,
9503 "\n");
9504
9505 if (!pbi->chunk->block->is_mapped)
9506 codec_mm_unmap_phyaddr(data);
9507}
9508
9509static void vp9_work(struct work_struct *work)
9510{
9511 struct VP9Decoder_s *pbi = container_of(work,
9512 struct VP9Decoder_s, work);
9513 struct vdec_s *vdec = hw_to_vdec(pbi);
9514 /* finished decoding one frame or error,
9515 * notify vdec core to switch context
9516 */
9517 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9518 "%s dec_result %d %x %x %x\n",
9519 __func__,
9520 pbi->dec_result,
9521 READ_VREG(HEVC_STREAM_LEVEL),
9522 READ_VREG(HEVC_STREAM_WR_PTR),
9523 READ_VREG(HEVC_STREAM_RD_PTR));
9524
9525 if (pbi->dec_result == DEC_INIT_PICLIST) {
9526 init_pic_list(pbi);
9527 pbi->pic_list_init_done = true;
9528 return;
9529 }
9530
9531 if (pbi->dec_result == DEC_V4L2_CONTINUE_DECODING) {
9532 struct aml_vcodec_ctx *ctx =
9533 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9534
9535 if (ctx->param_sets_from_ucode) {
9536 reset_process_time(pbi);
9537 if (wait_event_interruptible_timeout(ctx->wq,
9538 ctx->v4l_codec_ready,
9539 msecs_to_jiffies(500)) < 0)
9540 return;
9541 }
9542
9543 continue_decoding(pbi);
9544 pbi->postproc_done = 0;
9545 pbi->process_busy = 0;
9546
9547 return;
9548 }
9549
9550 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9551 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9552 && (hw_to_vdec(pbi)->next_status !=
9553 VDEC_STATUS_DISCONNECTED)) {
9554 if (!vdec_has_more_input(vdec)) {
9555 pbi->dec_result = DEC_RESULT_EOS;
9556 vdec_schedule_work(&pbi->work);
9557 return;
9558 }
9559
9560 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9561 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9562 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9563 __func__,
9564 READ_VREG(HEVC_STREAM_LEVEL),
9565 READ_VREG(HEVC_STREAM_WR_PTR),
9566 READ_VREG(HEVC_STREAM_RD_PTR));
9567 vdec_vframe_dirty(vdec, pbi->chunk);
9568 vdec_clean_input(vdec);
9569 }
9570
9571 if (get_free_buf_count(pbi) >=
9572 run_ready_min_buf_num) {
9573 int r;
9574 int decode_size;
9575 r = vdec_prepare_input(vdec, &pbi->chunk);
9576 if (r < 0) {
9577 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9578
9579 vp9_print(pbi,
9580 PRINT_FLAG_VDEC_DETAIL,
9581 "amvdec_vh265: Insufficient data\n");
9582
9583 vdec_schedule_work(&pbi->work);
9584 return;
9585 }
9586 pbi->dec_result = DEC_RESULT_NONE;
9587 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9588 "%s: chunk size 0x%x sum 0x%x\n",
9589 __func__, r,
9590 (debug & PRINT_FLAG_VDEC_STATUS) ?
9591 get_data_check_sum(pbi, r) : 0
9592 );
9593
9594 if (debug & PRINT_FLAG_VDEC_DATA)
9595 dump_data(pbi, pbi->chunk->size);
9596
9597 decode_size = pbi->chunk->size +
9598 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9599
9600 WRITE_VREG(HEVC_DECODE_SIZE,
9601 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9602
9603 vdec_enable_input(vdec);
9604
9605 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9606
9607 start_process_time(pbi);
9608
9609 } else{
9610 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9611
9612 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9613 "amvdec_vh265: Insufficient data\n");
9614
9615 vdec_schedule_work(&pbi->work);
9616 }
9617 return;
9618 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9619#ifdef SUPPORT_FB_DECODING
9620 if (pbi->used_stage_buf_num > 0) {
9621#ifndef FB_DECODING_TEST_SCHEDULE
9622 if (!is_s2_decoding_finished(pbi)) {
9623 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9624 "s2 decoding not done, check again later\n");
9625 vdec_schedule_work(&pbi->work);
9626 }
9627#endif
9628 inc_s2_pos(pbi);
9629 if (mcrcc_cache_alg_flag)
9630 dump_hit_rate(pbi);
9631 }
9632#endif
9633 /* if (!pbi->ctx_valid)
9634 pbi->ctx_valid = 1; */
9635 pbi->slice_idx++;
9636 pbi->frame_count++;
9637 pbi->process_state = PROC_STATE_INIT;
9638 decode_frame_count[pbi->index] = pbi->frame_count;
9639
9640 if (pbi->mmu_enable)
9641 pbi->used_4k_num =
9642 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9643 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9644 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9645 __func__,
9646 pbi->frame_count,
9647 pbi->dec_result,
9648 READ_VREG(HEVC_STREAM_LEVEL),
9649 READ_VREG(HEVC_STREAM_WR_PTR),
9650 READ_VREG(HEVC_STREAM_RD_PTR),
9651 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9652 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9653 pbi->start_shift_bytes
9654 );
9655 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9656 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9657 /*
9658 stream base: stream buf empty or timeout
9659 frame base: vdec_prepare_input fail
9660 */
9661 if (!vdec_has_more_input(vdec)) {
9662 pbi->dec_result = DEC_RESULT_EOS;
9663 vdec_schedule_work(&pbi->work);
9664 return;
9665 }
9666 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9667 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9668 "%s: end of stream\n",
9669 __func__);
9670 pbi->eos = 1;
9671 vp9_bufmgr_postproc(pbi);
9672
9673 if (pbi->is_used_v4l)
9674 notify_v4l_eos(hw_to_vdec(pbi));
9675
9676 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9677 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9678 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9679 "%s: force exit\n",
9680 __func__);
9681 if (pbi->stat & STAT_VDEC_RUN) {
9682 amhevc_stop();
9683 pbi->stat &= ~STAT_VDEC_RUN;
9684 }
9685
9686 if (pbi->stat & STAT_ISR_REG) {
9687#ifdef MULTI_INSTANCE_SUPPORT
9688 if (!pbi->m_ins_flag)
9689#endif
9690 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9691 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9692 pbi->stat &= ~STAT_ISR_REG;
9693 }
9694 }
9695 if (pbi->stat & STAT_VDEC_RUN) {
9696 amhevc_stop();
9697 pbi->stat &= ~STAT_VDEC_RUN;
9698 }
9699
9700 if (pbi->stat & STAT_TIMER_ARM) {
9701 del_timer_sync(&pbi->timer);
9702 pbi->stat &= ~STAT_TIMER_ARM;
9703 }
9704 /* mark itself has all HW resource released and input released */
9705#ifdef SUPPORT_FB_DECODING
9706 if (pbi->used_stage_buf_num > 0)
9707 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9708 else
9709 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9710 | CORE_MASK_HEVC
9711 | CORE_MASK_HEVC_FRONT
9712 | CORE_MASK_HEVC_BACK
9713 );
9714#else
9715 if (vdec->parallel_dec == 1)
9716 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9717 else
9718 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9719 | CORE_MASK_HEVC);
9720#endif
9721 trigger_schedule(pbi);
9722}
9723
9724static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9725{
9726 /* new to do ... */
9727#if (!defined SUPPORT_FB_DECODING)
9728 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9729#elif (defined FB_DECODING_TEST_SCHEDULE)
9730 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9731#else
9732 if (pbi->used_stage_buf_num > 0)
9733 vvp9_prot_init(pbi, HW_MASK_FRONT);
9734 else
9735 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9736#endif
9737 return 0;
9738}
9739static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9740{
9741 struct VP9Decoder_s *pbi =
9742 (struct VP9Decoder_s *)vdec->private;
9743 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9744 CODEC_MM_FLAGS_TVP : 0;
9745 unsigned long ret = 0;
9746
9747 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9748 return ret;
9749 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9750 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9751 pbi->first_sc_checked = 1;
9752 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9753 size, (pbi->need_cache_size >> PAGE_SHIFT),
9754 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9755 }
9756
9757#ifdef SUPPORT_FB_DECODING
9758 if (pbi->used_stage_buf_num > 0) {
9759 if (mask & CORE_MASK_HEVC_FRONT) {
9760 if (get_free_stage_buf_num(pbi) > 0
9761 && mv_buf_available(pbi))
9762 ret |= CORE_MASK_HEVC_FRONT;
9763 }
9764 if (mask & CORE_MASK_HEVC_BACK) {
9765 if (s2_buf_available(pbi) &&
9766 (get_free_buf_count(pbi) >=
9767 run_ready_min_buf_num)) {
9768 ret |= CORE_MASK_HEVC_BACK;
9769 pbi->back_not_run_ready = 0;
9770 } else
9771 pbi->back_not_run_ready = 1;
9772#if 0
9773 if (get_free_buf_count(pbi) <
9774 run_ready_min_buf_num)
9775 dump_pic_list(pbi);
9776#endif
9777 }
9778 } else if (get_free_buf_count(pbi) >=
9779 run_ready_min_buf_num)
9780 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9781 | CORE_MASK_HEVC_FRONT
9782 | CORE_MASK_HEVC_BACK;
9783
9784 if (ret & CORE_MASK_HEVC_FRONT)
9785 not_run_ready[pbi->index] = 0;
9786 else
9787 not_run_ready[pbi->index]++;
9788
9789 if (ret & CORE_MASK_HEVC_BACK)
9790 not_run2_ready[pbi->index] = 0;
9791 else
9792 not_run2_ready[pbi->index]++;
9793
9794 vp9_print(pbi,
9795 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9796 __func__, mask, ret,
9797 get_free_stage_buf_num(pbi),
9798 mv_buf_available(pbi),
9799 s2_buf_available(pbi),
9800 get_free_buf_count(pbi)
9801 );
9802
9803 return ret;
9804
9805#else
9806 if (get_free_buf_count(pbi) >=
9807 run_ready_min_buf_num) {
9808 if (vdec->parallel_dec == 1)
9809 ret = CORE_MASK_HEVC;
9810 else
9811 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9812 }
9813
9814 if (pbi->is_used_v4l) {
9815 struct aml_vcodec_ctx *ctx =
9816 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9817
9818 if (ctx->param_sets_from_ucode &&
9819 !ctx->v4l_codec_ready &&
9820 pbi->v4l_params_parsed) {
9821 ret = 0; /*the params has parsed.*/
9822 } else if (!ctx->v4l_codec_dpb_ready) {
9823 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
9824 run_ready_min_buf_num)
9825 ret = 0;
9826 }
9827 }
9828
9829 if (ret)
9830 not_run_ready[pbi->index] = 0;
9831 else
9832 not_run_ready[pbi->index]++;
9833
9834 vp9_print(pbi,
9835 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9836 __func__, mask, ret);
9837 return ret;
9838#endif
9839}
9840
9841static void run_front(struct vdec_s *vdec)
9842{
9843 struct VP9Decoder_s *pbi =
9844 (struct VP9Decoder_s *)vdec->private;
9845 int ret, size;
9846
9847 run_count[pbi->index]++;
9848 /* pbi->chunk = vdec_prepare_input(vdec); */
9849#if (!defined SUPPORT_FB_DECODING)
9850 hevc_reset_core(vdec);
9851#elif (defined FB_DECODING_TEST_SCHEDULE)
9852 hevc_reset_core(vdec);
9853#else
9854 if (pbi->used_stage_buf_num > 0)
9855 fb_reset_core(vdec, HW_MASK_FRONT);
9856 else
9857 hevc_reset_core(vdec);
9858#endif
9859
9860 size = vdec_prepare_input(vdec, &pbi->chunk);
9861 if (size < 0) {
9862 input_empty[pbi->index]++;
9863
9864 pbi->dec_result = DEC_RESULT_AGAIN;
9865
9866 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9867 "ammvdec_vh265: Insufficient data\n");
9868
9869 vdec_schedule_work(&pbi->work);
9870 return;
9871 }
9872
9873 input_empty[pbi->index] = 0;
9874 pbi->dec_result = DEC_RESULT_NONE;
9875 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9876
9877 if (debug & PRINT_FLAG_VDEC_STATUS) {
9878 int ii;
9879 vp9_print(pbi, 0,
9880 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9881 __func__,
9882 pbi->frame_count, size,
9883 pbi->chunk ? pbi->chunk->size : 0,
9884 pbi->chunk ? pbi->chunk->offset : 0,
9885 pbi->chunk ? ((vdec_frame_based(vdec) &&
9886 (debug & PRINT_FLAG_VDEC_STATUS)) ?
9887 get_data_check_sum(pbi, size) : 0) : 0,
9888 READ_VREG(HEVC_STREAM_START_ADDR),
9889 READ_VREG(HEVC_STREAM_END_ADDR),
9890 READ_VREG(HEVC_STREAM_LEVEL),
9891 READ_VREG(HEVC_STREAM_WR_PTR),
9892 READ_VREG(HEVC_STREAM_RD_PTR),
9893 pbi->start_shift_bytes);
9894 if (vdec_frame_based(vdec) && pbi->chunk) {
9895 u8 *data = NULL;
9896
9897 if (!pbi->chunk->block->is_mapped)
9898 data = codec_mm_vmap(pbi->chunk->block->start +
9899 pbi->chunk->offset, 8);
9900 else
9901 data = ((u8 *)pbi->chunk->block->start_virt) +
9902 pbi->chunk->offset;
9903
9904 vp9_print_cont(pbi, 0, "data adr %p:",
9905 data);
9906 for (ii = 0; ii < 8; ii++)
9907 vp9_print_cont(pbi, 0, "%02x ",
9908 data[ii]);
9909
9910 if (!pbi->chunk->block->is_mapped)
9911 codec_mm_unmap_phyaddr(data);
9912 }
9913 vp9_print_cont(pbi, 0, "\r\n");
9914 }
9915 if (vdec->mc_loaded) {
9916 /*firmware have load before,
9917 and not changes to another.
9918 ignore reload.
9919 */
9920 } else {
9921 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9922 if (ret < 0) {
9923 amhevc_disable();
9924 vp9_print(pbi, PRINT_FLAG_ERROR,
9925 "VP9: the %s fw loading failed, err: %x\n",
9926 tee_enabled() ? "TEE" : "local", ret);
9927 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9928 vdec_schedule_work(&pbi->work);
9929 return;
9930 }
9931 vdec->mc_loaded = 1;
9932 vdec->mc_type = VFORMAT_VP9;
9933 }
9934
9935 if (vp9_hw_ctx_restore(pbi) < 0) {
9936 vdec_schedule_work(&pbi->work);
9937 return;
9938 }
9939
9940 vdec_enable_input(vdec);
9941
9942 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9943
9944 if (vdec_frame_based(vdec)) {
9945 if (debug & PRINT_FLAG_VDEC_DATA)
9946 dump_data(pbi, pbi->chunk->size);
9947
9948 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9949 size = pbi->chunk->size +
9950 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9951 }
9952 WRITE_VREG(HEVC_DECODE_SIZE, size);
9953 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9954 pbi->init_flag = 1;
9955
9956 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9957 "%s: start hevc (%x %x %x)\n",
9958 __func__,
9959 READ_VREG(HEVC_DEC_STATUS_REG),
9960 READ_VREG(HEVC_MPC_E),
9961 READ_VREG(HEVC_MPSR));
9962
9963 start_process_time(pbi);
9964 mod_timer(&pbi->timer, jiffies);
9965 pbi->stat |= STAT_TIMER_ARM;
9966 pbi->stat |= STAT_ISR_REG;
9967 amhevc_start();
9968 pbi->stat |= STAT_VDEC_RUN;
9969}
9970
9971#ifdef SUPPORT_FB_DECODING
9972static void mpred_process(struct VP9Decoder_s *pbi)
9973{
9974 union param_u *params = &pbi->s1_param;
9975 unsigned char use_prev_frame_mvs =
9976 !params->p.error_resilient_mode &&
9977 params->p.width == pbi->s1_width &&
9978 params->p.height == pbi->s1_height &&
9979 !pbi->s1_intra_only &&
9980 pbi->s1_last_show_frame &&
9981 (pbi->s1_frame_type != KEY_FRAME);
9982 pbi->s1_width = params->p.width;
9983 pbi->s1_height = params->p.height;
9984 pbi->s1_frame_type = params->p.frame_type;
9985 pbi->s1_intra_only =
9986 (params->p.show_frame ||
9987 params->p.show_existing_frame)
9988 ? 0 : params->p.intra_only;
9989 if ((pbi->s1_frame_type != KEY_FRAME)
9990 && (!pbi->s1_intra_only)) {
9991 unsigned int data32;
9992 int mpred_mv_rd_end_addr;
9993
9994 mpred_mv_rd_end_addr =
9995 pbi->s1_mpred_mv_wr_start_addr_pre
9996 + (pbi->lcu_total * MV_MEM_UNIT);
9997
9998 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
9999 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
10000 pbi->work_space_buf->
10001 mpred_above.buf_start);
10002
10003 data32 = READ_VREG(HEVC_MPRED_CTRL4);
10004
10005 data32 &= (~(1 << 6));
10006 data32 |= (use_prev_frame_mvs << 6);
10007 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
10008
10009 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
10010 pbi->s1_mpred_mv_wr_start_addr);
10011 WRITE_VREG(HEVC_MPRED_MV_WPTR,
10012 pbi->s1_mpred_mv_wr_start_addr);
10013
10014 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
10015 pbi->s1_mpred_mv_wr_start_addr_pre);
10016 WRITE_VREG(HEVC_MPRED_MV_RPTR,
10017 pbi->s1_mpred_mv_wr_start_addr_pre);
10018
10019 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
10020 mpred_mv_rd_end_addr);
10021
10022 } else
10023 clear_mpred_hw(pbi);
10024
10025 if (!params->p.show_existing_frame) {
10026 pbi->s1_mpred_mv_wr_start_addr_pre =
10027 pbi->s1_mpred_mv_wr_start_addr;
10028 pbi->s1_last_show_frame =
10029 params->p.show_frame;
10030 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
10031 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
10032 pbi->s1_mv_buf_index_pre_pre =
10033 pbi->s1_mv_buf_index_pre;
10034 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10035 } else
10036 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10037}
10038
10039static void vp9_s1_work(struct work_struct *s1_work)
10040{
10041 struct VP9Decoder_s *pbi = container_of(s1_work,
10042 struct VP9Decoder_s, s1_work);
10043 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10044 "%s dec_s1_result %d\n",
10045 __func__,
10046 pbi->dec_s1_result);
10047
10048#ifdef FB_DECODING_TEST_SCHEDULE
10049 if (pbi->dec_s1_result ==
10050 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10051 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10052 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10053 }
10054#endif
10055 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10056 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10057
10058 vdec_core_finish_run(hw_to_vdec(pbi),
10059 CORE_MASK_HEVC_FRONT);
10060
10061 trigger_schedule(pbi);
10062 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10063 }
10064
10065}
10066
10067static void run_back(struct vdec_s *vdec)
10068{
10069 struct VP9Decoder_s *pbi =
10070 (struct VP9Decoder_s *)vdec->private;
10071 int i;
10072 run2_count[pbi->index]++;
10073 if (debug & PRINT_FLAG_VDEC_STATUS) {
10074 vp9_print(pbi, 0,
10075 "%s", __func__);
10076 }
10077 pbi->run2_busy = 1;
10078#ifndef FB_DECODING_TEST_SCHEDULE
10079 fb_reset_core(vdec, HW_MASK_BACK);
10080
10081 vvp9_prot_init(pbi, HW_MASK_BACK);
10082#endif
10083 vp9_recycle_mmu_buf_tail(pbi);
10084
10085 if (pbi->frame_count > 0)
10086 vp9_bufmgr_postproc(pbi);
10087
10088 if (get_s2_buf(pbi) >= 0) {
10089 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10090 int ii;
10091 for (ii = 0; ii < 4; ii++)
10092 vp9_param.l.data[i + ii] =
10093 pbi->s2_buf->rpm[i + 3 - ii];
10094 }
10095#ifndef FB_DECODING_TEST_SCHEDULE
10096 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10097 pbi->stage_mmu_map_phy_addr +
10098 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10099#endif
10100 continue_decoding(pbi);
10101 }
10102 pbi->run2_busy = 0;
10103}
10104#endif
10105
10106static void run(struct vdec_s *vdec, unsigned long mask,
10107 void (*callback)(struct vdec_s *, void *), void *arg)
10108{
10109 struct VP9Decoder_s *pbi =
10110 (struct VP9Decoder_s *)vdec->private;
10111
10112 vp9_print(pbi,
10113 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10114 __func__, mask);
10115
10116 run_count[pbi->index]++;
10117 pbi->vdec_cb_arg = arg;
10118 pbi->vdec_cb = callback;
10119#ifdef SUPPORT_FB_DECODING
10120 if ((mask & CORE_MASK_HEVC) ||
10121 (mask & CORE_MASK_HEVC_FRONT))
10122 run_front(vdec);
10123
10124 if ((pbi->used_stage_buf_num > 0)
10125 && (mask & CORE_MASK_HEVC_BACK))
10126 run_back(vdec);
10127#else
10128 run_front(vdec);
10129#endif
10130}
10131
10132static void init_frame_bufs(struct VP9Decoder_s *pbi)
10133{
10134 struct vdec_s *vdec = hw_to_vdec(pbi);
10135 struct VP9_Common_s *const cm = &pbi->common;
10136 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10137 int i;
10138
10139 for (i = 0; i < pbi->used_buf_num; ++i) {
10140 frame_bufs[i].ref_count = 0;
10141 frame_bufs[i].buf.vf_ref = 0;
10142 frame_bufs[i].buf.decode_idx = 0;
10143 frame_bufs[i].buf.cma_alloc_addr = 0;
10144 frame_bufs[i].buf.index = i;
10145 }
10146
10147 if (vdec->parallel_dec == 1) {
10148 for (i = 0; i < FRAME_BUFFERS; i++) {
10149 vdec->free_canvas_ex
10150 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10151 vdec->id);
10152 vdec->free_canvas_ex
10153 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10154 vdec->id);
10155 }
10156 }
10157}
10158
10159static void reset(struct vdec_s *vdec)
10160{
10161 struct VP9Decoder_s *pbi =
10162 (struct VP9Decoder_s *)vdec->private;
10163
10164 cancel_work_sync(&pbi->work);
10165 if (pbi->stat & STAT_VDEC_RUN) {
10166 amhevc_stop();
10167 pbi->stat &= ~STAT_VDEC_RUN;
10168 }
10169
10170 if (pbi->stat & STAT_TIMER_ARM) {
10171 del_timer_sync(&pbi->timer);
10172 pbi->stat &= ~STAT_TIMER_ARM;
10173 }
10174 pbi->dec_result = DEC_RESULT_NONE;
10175 reset_process_time(pbi);
10176 vp9_local_uninit(pbi);
10177 if (vvp9_local_init(pbi) < 0)
10178 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10179 init_frame_bufs(pbi);
10180
10181 pbi->eos = 0;
10182
10183 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10184}
10185
10186static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10187{
10188 struct VP9Decoder_s *pbi =
10189 (struct VP9Decoder_s *)vdec->private;
10190 return vvp9_isr(0, pbi);
10191}
10192
10193static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10194{
10195 struct VP9Decoder_s *pbi =
10196 (struct VP9Decoder_s *)vdec->private;
10197 return vvp9_isr_thread_fn(0, pbi);
10198}
10199
10200static void vp9_dump_state(struct vdec_s *vdec)
10201{
10202 struct VP9Decoder_s *pbi =
10203 (struct VP9Decoder_s *)vdec->private;
10204 struct VP9_Common_s *const cm = &pbi->common;
10205 int i;
10206 vp9_print(pbi, 0, "====== %s\n", __func__);
10207
10208 vp9_print(pbi, 0,
10209 "width/height (%d/%d), used_buf_num %d\n",
10210 cm->width,
10211 cm->height,
10212 pbi->used_buf_num
10213 );
10214
10215 vp9_print(pbi, 0,
10216 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10217 input_frame_based(vdec),
10218 pbi->eos,
10219 pbi->dec_result,
10220 decode_frame_count[pbi->index],
10221 display_frame_count[pbi->index],
10222 run_count[pbi->index],
10223 not_run_ready[pbi->index],
10224 input_empty[pbi->index],
10225 pbi->low_latency_flag,
10226 pbi->no_head
10227 );
10228
10229 if (vf_get_receiver(vdec->vf_provider_name)) {
10230 enum receviver_start_e state =
10231 vf_notify_receiver(vdec->vf_provider_name,
10232 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10233 NULL);
10234 vp9_print(pbi, 0,
10235 "\nreceiver(%s) state %d\n",
10236 vdec->vf_provider_name,
10237 state);
10238 }
10239
10240 vp9_print(pbi, 0,
10241 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10242 __func__,
10243 kfifo_len(&pbi->newframe_q),
10244 VF_POOL_SIZE,
10245 kfifo_len(&pbi->display_q),
10246 VF_POOL_SIZE,
10247 pbi->vf_pre_count,
10248 pbi->vf_get_count,
10249 pbi->vf_put_count,
10250 get_free_buf_count(pbi),
10251 run_ready_min_buf_num
10252 );
10253
10254 dump_pic_list(pbi);
10255
10256 for (i = 0; i < MAX_BUF_NUM; i++) {
10257 vp9_print(pbi, 0,
10258 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10259 i,
10260 pbi->m_mv_BUF[i].start_adr,
10261 pbi->m_mv_BUF[i].size,
10262 pbi->m_mv_BUF[i].used_flag);
10263 }
10264
10265 vp9_print(pbi, 0,
10266 "HEVC_DEC_STATUS_REG=0x%x\n",
10267 READ_VREG(HEVC_DEC_STATUS_REG));
10268 vp9_print(pbi, 0,
10269 "HEVC_MPC_E=0x%x\n",
10270 READ_VREG(HEVC_MPC_E));
10271 vp9_print(pbi, 0,
10272 "DECODE_MODE=0x%x\n",
10273 READ_VREG(DECODE_MODE));
10274 vp9_print(pbi, 0,
10275 "NAL_SEARCH_CTL=0x%x\n",
10276 READ_VREG(NAL_SEARCH_CTL));
10277 vp9_print(pbi, 0,
10278 "HEVC_PARSER_LCU_START=0x%x\n",
10279 READ_VREG(HEVC_PARSER_LCU_START));
10280 vp9_print(pbi, 0,
10281 "HEVC_DECODE_SIZE=0x%x\n",
10282 READ_VREG(HEVC_DECODE_SIZE));
10283 vp9_print(pbi, 0,
10284 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10285 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10286 vp9_print(pbi, 0,
10287 "HEVC_STREAM_START_ADDR=0x%x\n",
10288 READ_VREG(HEVC_STREAM_START_ADDR));
10289 vp9_print(pbi, 0,
10290 "HEVC_STREAM_END_ADDR=0x%x\n",
10291 READ_VREG(HEVC_STREAM_END_ADDR));
10292 vp9_print(pbi, 0,
10293 "HEVC_STREAM_LEVEL=0x%x\n",
10294 READ_VREG(HEVC_STREAM_LEVEL));
10295 vp9_print(pbi, 0,
10296 "HEVC_STREAM_WR_PTR=0x%x\n",
10297 READ_VREG(HEVC_STREAM_WR_PTR));
10298 vp9_print(pbi, 0,
10299 "HEVC_STREAM_RD_PTR=0x%x\n",
10300 READ_VREG(HEVC_STREAM_RD_PTR));
10301 vp9_print(pbi, 0,
10302 "PARSER_VIDEO_RP=0x%x\n",
10303 READ_PARSER_REG(PARSER_VIDEO_RP));
10304 vp9_print(pbi, 0,
10305 "PARSER_VIDEO_WP=0x%x\n",
10306 READ_PARSER_REG(PARSER_VIDEO_WP));
10307
10308 if (input_frame_based(vdec) &&
10309 (debug & PRINT_FLAG_VDEC_DATA)
10310 ) {
10311 int jj;
10312 if (pbi->chunk && pbi->chunk->block &&
10313 pbi->chunk->size > 0) {
10314 u8 *data = NULL;
10315
10316 if (!pbi->chunk->block->is_mapped)
10317 data = codec_mm_vmap(
10318 pbi->chunk->block->start +
10319 pbi->chunk->offset,
10320 pbi->chunk->size);
10321 else
10322 data = ((u8 *)pbi->chunk->block->start_virt)
10323 + pbi->chunk->offset;
10324 vp9_print(pbi, 0,
10325 "frame data size 0x%x\n",
10326 pbi->chunk->size);
10327 for (jj = 0; jj < pbi->chunk->size; jj++) {
10328 if ((jj & 0xf) == 0)
10329 vp9_print(pbi, 0,
10330 "%06x:", jj);
10331 vp9_print_cont(pbi, 0,
10332 "%02x ", data[jj]);
10333 if (((jj + 1) & 0xf) == 0)
10334 vp9_print_cont(pbi, 0,
10335 "\n");
10336 }
10337
10338 if (!pbi->chunk->block->is_mapped)
10339 codec_mm_unmap_phyaddr(data);
10340 }
10341 }
10342
10343}
10344
10345static int ammvdec_vp9_probe(struct platform_device *pdev)
10346{
10347 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10348 int ret;
10349 int config_val;
10350 struct vframe_content_light_level_s content_light_level;
10351 struct vframe_master_display_colour_s vf_dp;
10352
10353 struct BUF_s BUF[MAX_BUF_NUM];
10354 struct VP9Decoder_s *pbi = NULL;
10355 pr_debug("%s\n", __func__);
10356
10357 if (pdata == NULL) {
10358 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10359 return -EFAULT;
10360 }
10361 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10362 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10363 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10364 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10365 if (pbi == NULL) {
10366 pr_info("\nammvdec_vp9 device data allocation failed\n");
10367 return -ENOMEM;
10368 }
10369 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10370
10371 /* the ctx from v4l2 driver. */
10372 pbi->v4l2_ctx = pdata->private;
10373
10374 pdata->private = pbi;
10375 pdata->dec_status = vvp9_dec_status;
10376 /* pdata->set_trickmode = set_trickmode; */
10377 pdata->run_ready = run_ready;
10378 pdata->run = run;
10379 pdata->reset = reset;
10380 pdata->irq_handler = vp9_irq_cb;
10381 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10382 pdata->dump_state = vp9_dump_state;
10383
10384 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10385 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10386
10387 pbi->index = pdev->id;
10388
10389 if (pdata->use_vfm_path)
10390 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10391 VFM_DEC_PROVIDER_NAME);
10392 else
10393 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10394 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10395
10396 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10397 &vvp9_vf_provider, pbi);
10398
10399 pbi->provider_name = pdata->vf_provider_name;
10400 platform_set_drvdata(pdev, pdata);
10401
10402 pbi->platform_dev = pdev;
10403 pbi->video_signal_type = 0;
10404 pbi->m_ins_flag = 1;
10405 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10406 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10407
10408 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10409 pbi->max_pic_w = 8192;
10410 pbi->max_pic_h = 4608;
10411 } else {
10412 pbi->max_pic_w = 4096;
10413 pbi->max_pic_h = 2304;
10414 }
10415#if 1
10416 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10417 pdata->config_len) {
10418#ifdef MULTI_INSTANCE_SUPPORT
10419 int vp9_buf_width = 0;
10420 int vp9_buf_height = 0;
10421 /*use ptr config for doubel_write_mode, etc*/
10422 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10423 if (get_config_int(pdata->config, "vp9_double_write_mode",
10424 &config_val) == 0)
10425 pbi->double_write_mode = config_val;
10426 else
10427 pbi->double_write_mode = double_write_mode;
10428
10429 if (get_config_int(pdata->config, "save_buffer_mode",
10430 &config_val) == 0)
10431 pbi->save_buffer_mode = config_val;
10432 else
10433 pbi->save_buffer_mode = 0;
10434 if (get_config_int(pdata->config, "vp9_buf_width",
10435 &config_val) == 0) {
10436 vp9_buf_width = config_val;
10437 }
10438 if (get_config_int(pdata->config, "vp9_buf_height",
10439 &config_val) == 0) {
10440 vp9_buf_height = config_val;
10441 }
10442
10443 if (get_config_int(pdata->config, "no_head",
10444 &config_val) == 0)
10445 pbi->no_head = config_val;
10446 else
10447 pbi->no_head = no_head;
10448
10449 /*use ptr config for max_pic_w, etc*/
10450 if (get_config_int(pdata->config, "vp9_max_pic_w",
10451 &config_val) == 0) {
10452 pbi->max_pic_w = config_val;
10453 }
10454 if (get_config_int(pdata->config, "vp9_max_pic_h",
10455 &config_val) == 0) {
10456 pbi->max_pic_h = config_val;
10457 }
10458 if ((pbi->max_pic_w * pbi->max_pic_h)
10459 < (vp9_buf_width * vp9_buf_height)) {
10460 pbi->max_pic_w = vp9_buf_width;
10461 pbi->max_pic_h = vp9_buf_height;
10462 vp9_print(pbi, 0, "use buf resolution\n");
10463 }
10464
10465 if (get_config_int(pdata->config,
10466 "parm_v4l_codec_enable",
10467 &config_val) == 0)
10468 pbi->is_used_v4l = config_val;
10469
10470 if (get_config_int(pdata->config,
10471 "parm_v4l_buffer_margin",
10472 &config_val) == 0)
10473 pbi->dynamic_buf_num_margin = config_val;
10474
10475 if (get_config_int(pdata->config,
10476 "parm_v4l_canvas_mem_mode",
10477 &config_val) == 0)
10478 pbi->mem_map_mode = config_val;
10479#endif
10480 if (get_config_int(pdata->config, "HDRStaticInfo",
10481 &vf_dp.present_flag) == 0
10482 && vf_dp.present_flag == 1) {
10483 get_config_int(pdata->config, "mG.x",
10484 &vf_dp.primaries[0][0]);
10485 get_config_int(pdata->config, "mG.y",
10486 &vf_dp.primaries[0][1]);
10487 get_config_int(pdata->config, "mB.x",
10488 &vf_dp.primaries[1][0]);
10489 get_config_int(pdata->config, "mB.y",
10490 &vf_dp.primaries[1][1]);
10491 get_config_int(pdata->config, "mR.x",
10492 &vf_dp.primaries[2][0]);
10493 get_config_int(pdata->config, "mR.y",
10494 &vf_dp.primaries[2][1]);
10495 get_config_int(pdata->config, "mW.x",
10496 &vf_dp.white_point[0]);
10497 get_config_int(pdata->config, "mW.y",
10498 &vf_dp.white_point[1]);
10499 get_config_int(pdata->config, "mMaxDL",
10500 &vf_dp.luminance[0]);
10501 get_config_int(pdata->config, "mMinDL",
10502 &vf_dp.luminance[1]);
10503 vf_dp.content_light_level.present_flag = 1;
10504 get_config_int(pdata->config, "mMaxCLL",
10505 &content_light_level.max_content);
10506 get_config_int(pdata->config, "mMaxFALL",
10507 &content_light_level.max_pic_average);
10508 vf_dp.content_light_level = content_light_level;
10509 pbi->video_signal_type = (1 << 29)
10510 | (5 << 26) /* unspecified */
10511 | (0 << 25) /* limit */
10512 | (1 << 24) /* color available */
10513 | (9 << 16) /* 2020 */
10514 | (16 << 8) /* 2084 */
10515 | (9 << 0); /* 2020 */
10516 }
10517 pbi->vf_dp = vf_dp;
10518 } else
10519#endif
10520 {
10521 /*pbi->vvp9_amstream_dec_info.width = 0;
10522 pbi->vvp9_amstream_dec_info.height = 0;
10523 pbi->vvp9_amstream_dec_info.rate = 30;*/
10524 pbi->double_write_mode = double_write_mode;
10525 }
10526
10527 if (!pbi->is_used_v4l) {
10528 pbi->mem_map_mode = mem_map_mode;
10529 }
10530
10531 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10532 pr_err("over size: %dx%d, probe failed\n",
10533 pbi->max_pic_w, pbi->max_pic_h);
10534 return -1;
10535 }
10536 pbi->mmu_enable = 1;
10537 video_signal_type = pbi->video_signal_type;
10538
10539 if (pdata->sys_info) {
10540 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10541 } else {
10542 pbi->vvp9_amstream_dec_info.width = 0;
10543 pbi->vvp9_amstream_dec_info.height = 0;
10544 pbi->vvp9_amstream_dec_info.rate = 30;
10545 }
10546 pbi->low_latency_flag = 1;
10547
10548 vp9_print(pbi, 0,
10549 "no_head %d low_latency %d\n",
10550 pbi->no_head, pbi->low_latency_flag);
10551#if 0
10552 pbi->buf_start = pdata->mem_start;
10553 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10554#else
10555 if (amvdec_vp9_mmu_init(pbi) < 0) {
10556 pr_err("vp9 alloc bmmu box failed!!\n");
10557 /* devm_kfree(&pdev->dev, (void *)pbi); */
10558 vfree((void *)pbi);
10559 pdata->dec_status = NULL;
10560 return -1;
10561 }
10562
10563 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10564 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10565 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10566 &pbi->cma_alloc_addr);
10567 if (ret < 0) {
10568 uninit_mmu_buffers(pbi);
10569 /* devm_kfree(&pdev->dev, (void *)pbi); */
10570 vfree((void *)pbi);
10571 pdata->dec_status = NULL;
10572 return ret;
10573 }
10574 pbi->buf_start = pbi->cma_alloc_addr;
10575 pbi->buf_size = work_buf_size;
10576#endif
10577
10578 pbi->init_flag = 0;
10579 pbi->first_sc_checked = 0;
10580 pbi->fatal_error = 0;
10581 pbi->show_frame_num = 0;
10582
10583 if (debug) {
10584 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10585 pbi->buf_start,
10586 pbi->buf_size);
10587 }
10588
10589 pbi->cma_dev = pdata->cma_dev;
10590 if (vvp9_init(pdata) < 0) {
10591 pr_info("\namvdec_vp9 init failed.\n");
10592 vp9_local_uninit(pbi);
10593 uninit_mmu_buffers(pbi);
10594 /* devm_kfree(&pdev->dev, (void *)pbi); */
10595 vfree((void *)pbi);
10596 pdata->dec_status = NULL;
10597 return -ENODEV;
10598 }
10599 vdec_set_prepare_level(pdata, start_decode_buf_level);
10600 hevc_source_changed(VFORMAT_VP9,
10601 4096, 2048, 60);
10602#ifdef SUPPORT_FB_DECODING
10603 if (pbi->used_stage_buf_num > 0)
10604 vdec_core_request(pdata,
10605 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10606 else
10607 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10608 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10609 | CORE_MASK_COMBINE);
10610#else
10611 if (pdata->parallel_dec == 1)
10612 vdec_core_request(pdata, CORE_MASK_HEVC);
10613 else
10614 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10615 | CORE_MASK_COMBINE);
10616#endif
10617 pbi->pic_list_init_done2 = true;
10618 return 0;
10619}
10620
10621static int ammvdec_vp9_remove(struct platform_device *pdev)
10622{
10623 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10624 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10625 struct vdec_s *vdec = hw_to_vdec(pbi);
10626 int i;
10627 if (debug)
10628 pr_info("amvdec_vp9_remove\n");
10629
10630 vmvp9_stop(pbi);
10631
10632#ifdef SUPPORT_FB_DECODING
10633 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10634 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10635 );
10636#else
10637 if (vdec->parallel_dec == 1)
10638 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10639 else
10640 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10641#endif
10642 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10643
10644 if (vdec->parallel_dec == 1) {
10645 for (i = 0; i < FRAME_BUFFERS; i++) {
10646 vdec->free_canvas_ex
10647 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10648 vdec->id);
10649 vdec->free_canvas_ex
10650 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10651 vdec->id);
10652 }
10653 }
10654
10655
10656#ifdef DEBUG_PTS
10657 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10658 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10659#endif
10660 mem_map_mode = 0;
10661
10662 /* devm_kfree(&pdev->dev, (void *)pbi); */
10663 vfree((void *)pbi);
10664 return 0;
10665}
10666
10667static struct platform_driver ammvdec_vp9_driver = {
10668 .probe = ammvdec_vp9_probe,
10669 .remove = ammvdec_vp9_remove,
10670 .driver = {
10671 .name = MULTI_DRIVER_NAME,
10672#ifdef CONFIG_PM
10673 .pm = &vp9_pm_ops,
10674#endif
10675 }
10676};
10677#endif
10678static struct mconfig vp9_configs[] = {
10679 MC_PU32("bit_depth_luma", &bit_depth_luma),
10680 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10681 MC_PU32("frame_width", &frame_width),
10682 MC_PU32("frame_height", &frame_height),
10683 MC_PU32("debug", &debug),
10684 MC_PU32("radr", &radr),
10685 MC_PU32("rval", &rval),
10686 MC_PU32("pop_shorts", &pop_shorts),
10687 MC_PU32("dbg_cmd", &dbg_cmd),
10688 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10689 MC_PU32("endian", &endian),
10690 MC_PU32("step", &step),
10691 MC_PU32("udebug_flag", &udebug_flag),
10692 MC_PU32("decode_pic_begin", &decode_pic_begin),
10693 MC_PU32("slice_parse_begin", &slice_parse_begin),
10694 MC_PU32("i_only_flag", &i_only_flag),
10695 MC_PU32("error_handle_policy", &error_handle_policy),
10696 MC_PU32("buf_alloc_width", &buf_alloc_width),
10697 MC_PU32("buf_alloc_height", &buf_alloc_height),
10698 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10699 MC_PU32("buf_alloc_size", &buf_alloc_size),
10700 MC_PU32("buffer_mode", &buffer_mode),
10701 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10702 MC_PU32("max_buf_num", &max_buf_num),
10703 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10704 MC_PU32("mem_map_mode", &mem_map_mode),
10705 MC_PU32("double_write_mode", &double_write_mode),
10706 MC_PU32("enable_mem_saving", &enable_mem_saving),
10707 MC_PU32("force_w_h", &force_w_h),
10708 MC_PU32("force_fps", &force_fps),
10709 MC_PU32("max_decoding_time", &max_decoding_time),
10710 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10711 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10712 MC_PU32("decode_timeout_val", &decode_timeout_val),
10713 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10714 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10715};
10716static struct mconfig_node vp9_node;
10717
10718static int __init amvdec_vp9_driver_init_module(void)
10719{
10720
10721 struct BuffInfo_s *p_buf_info;
10722
10723 if (vdec_is_support_4k()) {
10724 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10725 p_buf_info = &amvvp9_workbuff_spec[2];
10726 else
10727 p_buf_info = &amvvp9_workbuff_spec[1];
10728 } else
10729 p_buf_info = &amvvp9_workbuff_spec[0];
10730
10731 init_buff_spec(NULL, p_buf_info);
10732 work_buf_size =
10733 (p_buf_info->end_adr - p_buf_info->start_adr
10734 + 0xffff) & (~0xffff);
10735
10736 pr_debug("amvdec_vp9 module init\n");
10737
10738 error_handle_policy = 0;
10739
10740#ifdef ERROR_HANDLE_DEBUG
10741 dbg_nal_skip_flag = 0;
10742 dbg_nal_skip_count = 0;
10743#endif
10744 udebug_flag = 0;
10745 decode_pic_begin = 0;
10746 slice_parse_begin = 0;
10747 step = 0;
10748 buf_alloc_size = 0;
10749#ifdef MULTI_INSTANCE_SUPPORT
10750 if (platform_driver_register(&ammvdec_vp9_driver))
10751 pr_err("failed to register ammvdec_vp9 driver\n");
10752
10753#endif
10754 if (platform_driver_register(&amvdec_vp9_driver)) {
10755 pr_err("failed to register amvdec_vp9 driver\n");
10756 return -ENODEV;
10757 }
10758
10759 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10760 amvdec_vp9_profile.profile =
10761 "8k, 10bit, dwrite, compressed, no_head";
10762 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10763 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10764 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10765 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10766 if (vdec_is_support_4k())
10767 amvdec_vp9_profile.profile =
10768 "4k, 10bit, dwrite, compressed";
10769 else
10770 amvdec_vp9_profile.profile =
10771 "10bit, dwrite, compressed";
10772 } else {
10773 if (vdec_is_support_4k())
10774 amvdec_vp9_profile.profile =
10775 "4k, 10bit, dwrite, compressed, no_head";
10776 else
10777 amvdec_vp9_profile.profile =
10778 "10bit, dwrite, compressed, no_head";
10779 }
10780
10781 } else {
10782 amvdec_vp9_profile.name = "vp9_unsupport";
10783 }
10784
10785 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10786 max_buf_num = MAX_BUF_NUM_LESS;
10787
10788 vcodec_profile_register(&amvdec_vp9_profile);
10789 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10790 amvdec_vp9_profile_mult.name = "mvp9";
10791 vcodec_profile_register(&amvdec_vp9_profile_mult);
10792 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10793 "vp9", vp9_configs, CONFIG_FOR_RW);
10794
10795 return 0;
10796}
10797
10798static void __exit amvdec_vp9_driver_remove_module(void)
10799{
10800 pr_debug("amvdec_vp9 module remove.\n");
10801#ifdef MULTI_INSTANCE_SUPPORT
10802 platform_driver_unregister(&ammvdec_vp9_driver);
10803#endif
10804 platform_driver_unregister(&amvdec_vp9_driver);
10805}
10806
10807/****************************************/
10808
10809module_param(bit_depth_luma, uint, 0664);
10810MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10811
10812module_param(bit_depth_chroma, uint, 0664);
10813MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10814
10815module_param(frame_width, uint, 0664);
10816MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10817
10818module_param(frame_height, uint, 0664);
10819MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10820
10821module_param(debug, uint, 0664);
10822MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10823
10824module_param(radr, uint, 0664);
10825MODULE_PARM_DESC(radr, "\n radr\n");
10826
10827module_param(rval, uint, 0664);
10828MODULE_PARM_DESC(rval, "\n rval\n");
10829
10830module_param(pop_shorts, uint, 0664);
10831MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10832
10833module_param(dbg_cmd, uint, 0664);
10834MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10835
10836module_param(dbg_skip_decode_index, uint, 0664);
10837MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10838
10839module_param(endian, uint, 0664);
10840MODULE_PARM_DESC(endian, "\n rval\n");
10841
10842module_param(step, uint, 0664);
10843MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10844
10845module_param(decode_pic_begin, uint, 0664);
10846MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10847
10848module_param(slice_parse_begin, uint, 0664);
10849MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10850
10851module_param(i_only_flag, uint, 0664);
10852MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10853
10854module_param(low_latency_flag, uint, 0664);
10855MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10856
10857module_param(no_head, uint, 0664);
10858MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10859
10860module_param(error_handle_policy, uint, 0664);
10861MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10862
10863module_param(buf_alloc_width, uint, 0664);
10864MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10865
10866module_param(buf_alloc_height, uint, 0664);
10867MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10868
10869module_param(buf_alloc_depth, uint, 0664);
10870MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10871
10872module_param(buf_alloc_size, uint, 0664);
10873MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10874
10875module_param(buffer_mode, uint, 0664);
10876MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10877
10878module_param(buffer_mode_dbg, uint, 0664);
10879MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10880/*USE_BUF_BLOCK*/
10881module_param(max_buf_num, uint, 0664);
10882MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10883
10884module_param(dynamic_buf_num_margin, uint, 0664);
10885MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10886
10887module_param(mv_buf_margin, uint, 0664);
10888MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10889
10890module_param(run_ready_min_buf_num, uint, 0664);
10891MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10892
10893/**/
10894
10895module_param(mem_map_mode, uint, 0664);
10896MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10897
10898#ifdef SUPPORT_10BIT
10899module_param(double_write_mode, uint, 0664);
10900MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10901
10902module_param(enable_mem_saving, uint, 0664);
10903MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10904
10905module_param(force_w_h, uint, 0664);
10906MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10907#endif
10908
10909module_param(force_fps, uint, 0664);
10910MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10911
10912module_param(max_decoding_time, uint, 0664);
10913MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10914
10915module_param(on_no_keyframe_skiped, uint, 0664);
10916MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10917
10918module_param(mcrcc_cache_alg_flag, uint, 0664);
10919MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10920
10921#ifdef MULTI_INSTANCE_SUPPORT
10922module_param(start_decode_buf_level, int, 0664);
10923MODULE_PARM_DESC(start_decode_buf_level,
10924 "\n vp9 start_decode_buf_level\n");
10925
10926module_param(decode_timeout_val, uint, 0664);
10927MODULE_PARM_DESC(decode_timeout_val,
10928 "\n vp9 decode_timeout_val\n");
10929
10930module_param(vp9_max_pic_w, uint, 0664);
10931MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10932
10933module_param(vp9_max_pic_h, uint, 0664);
10934MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10935
10936module_param_array(decode_frame_count, uint,
10937 &max_decode_instance_num, 0664);
10938
10939module_param_array(display_frame_count, uint,
10940 &max_decode_instance_num, 0664);
10941
10942module_param_array(max_process_time, uint,
10943 &max_decode_instance_num, 0664);
10944
10945module_param_array(run_count, uint,
10946 &max_decode_instance_num, 0664);
10947
10948module_param_array(input_empty, uint,
10949 &max_decode_instance_num, 0664);
10950
10951module_param_array(not_run_ready, uint,
10952 &max_decode_instance_num, 0664);
10953#endif
10954
10955#ifdef SUPPORT_FB_DECODING
10956module_param_array(not_run2_ready, uint,
10957 &max_decode_instance_num, 0664);
10958
10959module_param_array(run2_count, uint,
10960 &max_decode_instance_num, 0664);
10961
10962module_param(stage_buf_num, uint, 0664);
10963MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10964#endif
10965
10966module_param(udebug_flag, uint, 0664);
10967MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10968
10969module_param(udebug_pause_pos, uint, 0664);
10970MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10971
10972module_param(udebug_pause_val, uint, 0664);
10973MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10974
10975module_param(udebug_pause_decode_idx, uint, 0664);
10976MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10977
10978module_param(without_display_mode, uint, 0664);
10979MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10980
10981module_init(amvdec_vp9_driver_init_module);
10982module_exit(amvdec_vp9_driver_remove_module);
10983
10984MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
10985MODULE_LICENSE("GPL");
10986
10987
generated by cgit at 2024-05-17 08:38:26 (GMT)