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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: f8eac8a4356c9da080fdeed4d8f209aafcdb0dac
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../../../amvdec_ports/vdec_drv_base.h"
61
62
63
64#define MIX_STREAM_SUPPORT
65
66#include "vvp9.h"
67
68
69/*#define SUPPORT_FB_DECODING*/
70/*#define FB_DECODING_TEST_SCHEDULE*/
71
72
73#define HW_MASK_FRONT 0x1
74#define HW_MASK_BACK 0x2
75
76#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
77#define VP9D_MPP_REFINFO_DATA 0x3443
78#define VP9D_MPP_REF_SCALE_ENBL 0x3441
79#define HEVC_MPRED_CTRL4 0x324c
80#define HEVC_CM_HEADER_START_ADDR 0x3628
81#define HEVC_DBLK_CFGB 0x350b
82#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
83#define HEVC_SAO_MMU_VH1_ADDR 0x363b
84#define HEVC_SAO_MMU_VH0_ADDR 0x363a
85
86#define HEVC_MV_INFO 0x310d
87#define HEVC_QP_INFO 0x3137
88#define HEVC_SKIP_INFO 0x3136
89
90#define VP9_10B_DEC_IDLE 0
91#define VP9_10B_DEC_FRAME_HEADER 1
92#define VP9_10B_DEC_SLICE_SEGMENT 2
93#define VP9_10B_DECODE_SLICE 5
94#define VP9_10B_DISCARD_NAL 6
95#define VP9_DUMP_LMEM 7
96#define HEVC_DECPIC_DATA_DONE 0xa
97#define HEVC_DECPIC_DATA_ERROR 0xb
98#define HEVC_NAL_DECODE_DONE 0xe
99#define HEVC_DECODE_BUFEMPTY 0x20
100#define HEVC_DECODE_TIMEOUT 0x21
101#define HEVC_SEARCH_BUFEMPTY 0x22
102#define HEVC_DECODE_OVER_SIZE 0x23
103#define HEVC_S2_DECODING_DONE 0x50
104#define VP9_HEAD_PARSER_DONE 0xf0
105#define VP9_HEAD_SEARCH_DONE 0xf1
106#define VP9_EOS 0xf2
107#define HEVC_ACTION_DONE 0xff
108
109#define VF_POOL_SIZE 32
110
111#undef pr_info
112#define pr_info printk
113
114#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
115#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
116#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
117#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
118#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
119
120#define VP9_TRIGGER_FRAME_DONE 0x100
121#define VP9_TRIGGER_FRAME_ENABLE 0x200
122
123#define MV_MEM_UNIT 0x240
124/*---------------------------------------------------
125 * Include "parser_cmd.h"
126 *---------------------------------------------------
127 */
128#define PARSER_CMD_SKIP_CFG_0 0x0000090b
129
130#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
131
132#define PARSER_CMD_SKIP_CFG_2 0x001b1910
133
134#define PARSER_CMD_NUMBER 37
135
136/*#define HEVC_PIC_STRUCT_SUPPORT*/
137/* to remove, fix build error */
138
139/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
140
141#define MULTI_INSTANCE_SUPPORT
142#define SUPPORT_10BIT
143/* #define ERROR_HANDLE_DEBUG */
144
145#ifndef STAT_KTHREAD
146#define STAT_KTHREAD 0x40
147#endif
148
149#ifdef MULTI_INSTANCE_SUPPORT
150#define MAX_DECODE_INSTANCE_NUM 9
151#define MULTI_DRIVER_NAME "ammvdec_vp9"
152
153static unsigned int max_decode_instance_num
154 = MAX_DECODE_INSTANCE_NUM;
155static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
156static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
157static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
158static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
159static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
160static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
161
162static u32 decode_timeout_val = 200;
163static int start_decode_buf_level = 0x8000;
164static u32 work_buf_size;
165
166static u32 mv_buf_margin;
167
168/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
169/* double_write_mode:
170 * 0, no double write;
171 * 1, 1:1 ratio;
172 * 2, (1/4):(1/4) ratio;
173 * 3, (1/4):(1/4) ratio, with both compressed frame included
174 * 4, (1/2):(1/2) ratio;
175 * 0x10, double write only
176 * 0x100, if > 1080p,use mode 4,else use mode 1;
177 * 0x200, if > 1080p,use mode 2,else use mode 1;
178 * 0x300, if > 720p, use mode 4, else use mode 1;
179 */
180static u32 double_write_mode;
181
182#define DRIVER_NAME "amvdec_vp9"
183#define MODULE_NAME "amvdec_vp9"
184#define DRIVER_HEADER_NAME "amvdec_vp9_header"
185
186
187#define PUT_INTERVAL (HZ/100)
188#define ERROR_SYSTEM_RESET_COUNT 200
189
190#define PTS_NORMAL 0
191#define PTS_NONE_REF_USE_DURATION 1
192
193#define PTS_MODE_SWITCHING_THRESHOLD 3
194#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
195
196#define DUR2PTS(x) ((x)*90/96)
197
198struct VP9Decoder_s;
199static int vvp9_vf_states(struct vframe_states *states, void *);
200static struct vframe_s *vvp9_vf_peek(void *);
201static struct vframe_s *vvp9_vf_get(void *);
202static void vvp9_vf_put(struct vframe_s *, void *);
203static int vvp9_event_cb(int type, void *data, void *private_data);
204
205static int vvp9_stop(struct VP9Decoder_s *pbi);
206#ifdef MULTI_INSTANCE_SUPPORT
207static s32 vvp9_init(struct vdec_s *vdec);
208#else
209static s32 vvp9_init(struct VP9Decoder_s *pbi);
210#endif
211static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
212static int vvp9_local_init(struct VP9Decoder_s *pbi);
213static void vvp9_put_timer_func(unsigned long arg);
214static void dump_data(struct VP9Decoder_s *pbi, int size);
215static unsigned char get_data_check_sum
216 (struct VP9Decoder_s *pbi, int size);
217static void dump_pic_list(struct VP9Decoder_s *pbi);
218static int vp9_alloc_mmu(
219 struct VP9Decoder_s *pbi,
220 int cur_buf_idx,
221 int pic_width,
222 int pic_height,
223 unsigned short bit_depth,
224 unsigned int *mmu_index_adr);
225
226
227static const char vvp9_dec_id[] = "vvp9-dev";
228
229#define PROVIDER_NAME "decoder.vp9"
230#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
231
232static const struct vframe_operations_s vvp9_vf_provider = {
233 .peek = vvp9_vf_peek,
234 .get = vvp9_vf_get,
235 .put = vvp9_vf_put,
236 .event_cb = vvp9_event_cb,
237 .vf_states = vvp9_vf_states,
238};
239
240static struct vframe_provider_s vvp9_vf_prov;
241
242static u32 bit_depth_luma;
243static u32 bit_depth_chroma;
244static u32 frame_width;
245static u32 frame_height;
246static u32 video_signal_type;
247
248static u32 on_no_keyframe_skiped;
249
250#define PROB_SIZE (496 * 2 * 4)
251#define PROB_BUF_SIZE (0x5000)
252#define COUNT_BUF_SIZE (0x300 * 4 * 4)
253/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
254#define MAX_FRAME_4K_NUM 0x1200
255#define MAX_FRAME_8K_NUM 0x4800
256
257#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
258
259#ifdef SUPPORT_FB_DECODING
260/* register define */
261#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
262#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
263#define HEVC_ASSIST_HED_FB_ADDR 0x3008
264#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
265#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
266
267
268#define MAX_STAGE_PAGE_NUM 0x1200
269#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
270#endif
271static inline int div_r32(int64_t m, int n)
272{
273/*
274 *return (int)(m/n)
275 */
276#ifndef CONFIG_ARM64
277 int64_t qu = 0;
278 qu = div_s64(m, n);
279 return (int)qu;
280#else
281 return (int)(m/n);
282#endif
283}
284
285/*USE_BUF_BLOCK*/
286struct BUF_s {
287 int index;
288 unsigned int alloc_flag;
289 /*buffer */
290 unsigned int cma_page_count;
291 unsigned long alloc_addr;
292 unsigned long start_adr;
293 unsigned int size;
294
295 unsigned int free_start_adr;
296 ulong v4l_ref_buf_addr;
297} /*BUF_t */;
298
299struct MVBUF_s {
300 unsigned long start_adr;
301 unsigned int size;
302 int used_flag;
303} /*MVBUF_t */;
304
305 /* #undef BUFMGR_ONLY to enable hardware configuration */
306
307/*#define TEST_WR_PTR_INC*/
308/*#define WR_PTR_INC_NUM 128*/
309#define WR_PTR_INC_NUM 1
310
311#define SIMULATION
312#define DOS_PROJECT
313#undef MEMORY_MAP_IN_REAL_CHIP
314
315/*#undef DOS_PROJECT*/
316/*#define MEMORY_MAP_IN_REAL_CHIP*/
317
318/*#define BUFFER_MGR_ONLY*/
319/*#define CONFIG_HEVC_CLK_FORCED_ON*/
320/*#define ENABLE_SWAP_TEST*/
321#define MCRCC_ENABLE
322
323#define VP9_LPF_LVL_UPDATE
324/*#define DBG_LF_PRINT*/
325
326#ifdef VP9_10B_NV21
327#else
328#define LOSLESS_COMPRESS_MODE
329#endif
330
331#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
332#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
333
334
335
336typedef unsigned int u32;
337typedef unsigned short u16;
338
339#define VP9_DEBUG_BUFMGR 0x01
340#define VP9_DEBUG_BUFMGR_MORE 0x02
341#define VP9_DEBUG_BUFMGR_DETAIL 0x04
342#define VP9_DEBUG_OUT_PTS 0x10
343#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
344#define VP9_DEBUG_MERGE 0x200
345#define VP9_DEBUG_DBG_LF_PRINT 0x400
346#define VP9_DEBUG_REG 0x800
347#define VP9_DEBUG_2_STAGE 0x1000
348#define VP9_DEBUG_2_STAGE_MORE 0x2000
349#define VP9_DEBUG_QOS_INFO 0x4000
350#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
351#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
352#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
353#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
354#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
355#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
356#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
357#define VP9_DEBUG_DUMP_DATA 0x800000
358#define VP9_DEBUG_CACHE 0x1000000
359#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
360#define IGNORE_PARAM_FROM_CONFIG 0x8000000
361#ifdef MULTI_INSTANCE_SUPPORT
362#define PRINT_FLAG_ERROR 0x0
363#define PRINT_FLAG_V4L_DETAIL 0x10000000
364#define PRINT_FLAG_VDEC_STATUS 0x20000000
365#define PRINT_FLAG_VDEC_DETAIL 0x40000000
366#define PRINT_FLAG_VDEC_DATA 0x80000000
367#endif
368
369static u32 debug;
370static bool is_reset;
371/*for debug*/
372/*
373 udebug_flag:
374 bit 0, enable ucode print
375 bit 1, enable ucode detail print
376 bit [31:16] not 0, pos to dump lmem
377 bit 2, pop bits to lmem
378 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
379*/
380static u32 udebug_flag;
381/*
382 when udebug_flag[1:0] is not 0
383 udebug_pause_pos not 0,
384 pause position
385*/
386static u32 udebug_pause_pos;
387/*
388 when udebug_flag[1:0] is not 0
389 and udebug_pause_pos is not 0,
390 pause only when DEBUG_REG2 is equal to this val
391*/
392static u32 udebug_pause_val;
393
394static u32 udebug_pause_decode_idx;
395
396static u32 without_display_mode;
397
398#define DEBUG_REG
399#ifdef DEBUG_REG
400void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
401{
402 if (debug & VP9_DEBUG_REG)
403 pr_info("%s(%x, %x)\n", __func__, adr, val);
404 if (adr != 0)
405 WRITE_VREG(adr, val);
406}
407
408#undef WRITE_VREG
409#define WRITE_VREG WRITE_VREG_DBG2
410#endif
411
412#define FRAME_CNT_WINDOW_SIZE 59
413#define RATE_CORRECTION_THRESHOLD 5
414/**************************************************
415
416VP9 buffer management start
417
418***************************************************/
419
420#define MMU_COMPRESS_HEADER_SIZE 0x48000
421#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
422#define MAX_SIZE_8K (8192 * 4608)
423#define MAX_SIZE_4K (4096 * 2304)
424#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
425
426#define INVALID_IDX -1 /* Invalid buffer index.*/
427
428#define RPM_BEGIN 0x200
429#define RPM_END 0x280
430
431union param_u {
432 struct {
433 unsigned short data[RPM_END - RPM_BEGIN];
434 } l;
435 struct {
436 /* from ucode lmem, do not change this struct */
437 unsigned short profile;
438 unsigned short show_existing_frame;
439 unsigned short frame_to_show_idx;
440 unsigned short frame_type; /*1 bit*/
441 unsigned short show_frame; /*1 bit*/
442 unsigned short error_resilient_mode; /*1 bit*/
443 unsigned short intra_only; /*1 bit*/
444 unsigned short display_size_present; /*1 bit*/
445 unsigned short reset_frame_context;
446 unsigned short refresh_frame_flags;
447 unsigned short width;
448 unsigned short height;
449 unsigned short display_width;
450 unsigned short display_height;
451 /*
452 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
453 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
454 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
455 */
456 unsigned short ref_info;
457 /*
458 *bit[2]: same_frame_size0
459 *bit[1]: same_frame_size1
460 *bit[0]: same_frame_size2
461 */
462 unsigned short same_frame_size;
463
464 unsigned short mode_ref_delta_enabled;
465 unsigned short ref_deltas[4];
466 unsigned short mode_deltas[2];
467 unsigned short filter_level;
468 unsigned short sharpness_level;
469 unsigned short bit_depth;
470 unsigned short seg_quant_info[8];
471 unsigned short seg_enabled;
472 unsigned short seg_abs_delta;
473 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
474 unsigned short seg_lf_info[8];
475 } p;
476};
477
478
479struct vpx_codec_frame_buffer_s {
480 uint8_t *data; /**< Pointer to the data buffer */
481 size_t size; /**< Size of data in bytes */
482 void *priv; /**< Frame's private data */
483};
484
485enum vpx_color_space_t {
486 VPX_CS_UNKNOWN = 0, /**< Unknown */
487 VPX_CS_BT_601 = 1, /**< BT.601 */
488 VPX_CS_BT_709 = 2, /**< BT.709 */
489 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
490 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
491 VPX_CS_BT_2020 = 5, /**< BT.2020 */
492 VPX_CS_RESERVED = 6, /**< Reserved */
493 VPX_CS_SRGB = 7 /**< sRGB */
494}; /**< alias for enum vpx_color_space */
495
496enum vpx_bit_depth_t {
497 VPX_BITS_8 = 8, /**< 8 bits */
498 VPX_BITS_10 = 10, /**< 10 bits */
499 VPX_BITS_12 = 12, /**< 12 bits */
500};
501
502#define MAX_SLICE_NUM 1024
503struct PIC_BUFFER_CONFIG_s {
504 int index;
505 int BUF_index;
506 int mv_buf_index;
507 int comp_body_size;
508 int buf_size;
509 int vf_ref;
510 int y_canvas_index;
511 int uv_canvas_index;
512#ifdef MULTI_INSTANCE_SUPPORT
513 struct canvas_config_s canvas_config[2];
514#endif
515 int decode_idx;
516 int slice_type;
517 int stream_offset;
518 u32 pts;
519 u64 pts64;
520 uint8_t error_mark;
521 /**/
522 int slice_idx;
523 /*buffer*/
524 unsigned long header_adr;
525 unsigned long mpred_mv_wr_start_addr;
526 /*unsigned long mc_y_adr;
527 *unsigned long mc_u_v_adr;
528 */
529 unsigned int dw_y_adr;
530 unsigned int dw_u_v_adr;
531 int mc_canvas_y;
532 int mc_canvas_u_v;
533
534 int lcu_total;
535 /**/
536 int y_width;
537 int y_height;
538 int y_crop_width;
539 int y_crop_height;
540 int y_stride;
541
542 int uv_width;
543 int uv_height;
544 int uv_crop_width;
545 int uv_crop_height;
546 int uv_stride;
547
548 int alpha_width;
549 int alpha_height;
550 int alpha_stride;
551
552 uint8_t *y_buffer;
553 uint8_t *u_buffer;
554 uint8_t *v_buffer;
555 uint8_t *alpha_buffer;
556
557 uint8_t *buffer_alloc;
558 int buffer_alloc_sz;
559 int border;
560 int frame_size;
561 int subsampling_x;
562 int subsampling_y;
563 unsigned int bit_depth;
564 enum vpx_color_space_t color_space;
565
566 int corrupted;
567 int flags;
568 unsigned long cma_alloc_addr;
569
570 int double_write_mode;
571
572 /* picture qos infomation*/
573 int max_qp;
574 int avg_qp;
575 int min_qp;
576 int max_skip;
577 int avg_skip;
578 int min_skip;
579 int max_mv;
580 int min_mv;
581 int avg_mv;
582} PIC_BUFFER_CONFIG;
583
584enum BITSTREAM_PROFILE {
585 PROFILE_0,
586 PROFILE_1,
587 PROFILE_2,
588 PROFILE_3,
589 MAX_PROFILES
590};
591
592enum FRAME_TYPE {
593 KEY_FRAME = 0,
594 INTER_FRAME = 1,
595 FRAME_TYPES,
596};
597
598enum REFERENCE_MODE {
599 SINGLE_REFERENCE = 0,
600 COMPOUND_REFERENCE = 1,
601 REFERENCE_MODE_SELECT = 2,
602 REFERENCE_MODES = 3,
603};
604
605#define NONE -1
606#define INTRA_FRAME 0
607#define LAST_FRAME 1
608#define GOLDEN_FRAME 2
609#define ALTREF_FRAME 3
610#define MAX_REF_FRAMES 4
611
612#define REFS_PER_FRAME 3
613
614#define REF_FRAMES_LOG2 3
615#define REF_FRAMES (1 << REF_FRAMES_LOG2)
616#define REF_FRAMES_4K (6)
617
618/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
619 *in parallel, 3 for scaled references on the encoder.
620 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
621 * // of framebuffers.
622 *TODO(jkoleszar): These 3 extra references could probably come from the
623 *normal reference pool.
624 */
625#define FRAME_BUFFERS (REF_FRAMES + 16)
626#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
627#define MAX_BUF_NUM (FRAME_BUFFERS)
628#define MV_BUFFER_NUM FRAME_BUFFERS
629#ifdef SUPPORT_FB_DECODING
630#define STAGE_MAX_BUFFERS 16
631#else
632#define STAGE_MAX_BUFFERS 0
633#endif
634
635#define FRAME_CONTEXTS_LOG2 2
636#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
637/*buffer + header buffer + workspace*/
638#ifdef MV_USE_FIXED_BUF
639#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
640#define VF_BUFFER_IDX(n) (n)
641#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
642#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
643#else
644#define MAX_BMMU_BUFFER_NUM \
645 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
646#define VF_BUFFER_IDX(n) (n)
647#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
648#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
649#define WORK_SPACE_BUF_ID \
650 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
651#endif
652
653struct RefCntBuffer_s {
654 int ref_count;
655 /*MV_REF *mvs;*/
656 int mi_rows;
657 int mi_cols;
658 struct vpx_codec_frame_buffer_s raw_frame_buffer;
659 struct PIC_BUFFER_CONFIG_s buf;
660
661/*The Following variables will only be used in frame parallel decode.
662 *
663 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
664 *that no FrameWorker owns, or is decoding, this buffer.
665 *VP9Worker *frame_worker_owner;
666 *
667 *row and col indicate which position frame has been decoded to in real
668 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
669 *when the frame is fully decoded.
670 */
671 int row;
672 int col;
673} RefCntBuffer;
674
675struct RefBuffer_s {
676/*TODO(dkovalev): idx is not really required and should be removed, now it
677 *is used in vp9_onyxd_if.c
678 */
679 int idx;
680 struct PIC_BUFFER_CONFIG_s *buf;
681 /*struct scale_factors sf;*/
682} RefBuffer;
683
684struct InternalFrameBuffer_s {
685 uint8_t *data;
686 size_t size;
687 int in_use;
688} InternalFrameBuffer;
689
690struct InternalFrameBufferList_s {
691 int num_internal_frame_buffers;
692 struct InternalFrameBuffer_s *int_fb;
693} InternalFrameBufferList;
694
695struct BufferPool_s {
696/*Protect BufferPool from being accessed by several FrameWorkers at
697 *the same time during frame parallel decode.
698 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
699 *
700 *Private data associated with the frame buffer callbacks.
701 *void *cb_priv;
702 *
703 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
704 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
705 */
706
707 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
708
709/*Frame buffers allocated internally by the codec.*/
710 struct InternalFrameBufferList_s int_frame_buffers;
711 unsigned long flags;
712 spinlock_t lock;
713
714} BufferPool;
715
716#define lock_buffer_pool(pool, flags) \
717 spin_lock_irqsave(&pool->lock, flags)
718
719#define unlock_buffer_pool(pool, flags) \
720 spin_unlock_irqrestore(&pool->lock, flags)
721
722struct VP9_Common_s {
723 enum vpx_color_space_t color_space;
724 int width;
725 int height;
726 int display_width;
727 int display_height;
728 int last_width;
729 int last_height;
730
731 int subsampling_x;
732 int subsampling_y;
733
734 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
735
736 struct PIC_BUFFER_CONFIG_s *frame_to_show;
737 struct RefCntBuffer_s *prev_frame;
738
739 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
740 struct RefCntBuffer_s *cur_frame;
741
742 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
743
744 /*Prepare ref_frame_map for the next frame.
745 *Only used in frame parallel decode.
746 */
747 int next_ref_frame_map[REF_FRAMES];
748
749 /* TODO(jkoleszar): could expand active_ref_idx to 4,
750 *with 0 as intra, and roll new_fb_idx into it.
751 */
752
753 /*Each frame can reference REFS_PER_FRAME buffers*/
754 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
755
756 int prev_fb_idx;
757 int new_fb_idx;
758 int cur_fb_idx_mmu;
759 /*last frame's frame type for motion search*/
760 enum FRAME_TYPE last_frame_type;
761 enum FRAME_TYPE frame_type;
762
763 int show_frame;
764 int last_show_frame;
765 int show_existing_frame;
766
767 /*Flag signaling that the frame is encoded using only INTRA modes.*/
768 uint8_t intra_only;
769 uint8_t last_intra_only;
770
771 int allow_high_precision_mv;
772
773 /*Flag signaling that the frame context should be reset to default
774 *values. 0 or 1 implies don't reset, 2 reset just the context
775 *specified in the frame header, 3 reset all contexts.
776 */
777 int reset_frame_context;
778
779 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
780 * MODE_INFO (8-pixel) units.
781 */
782 int MBs;
783 int mb_rows, mi_rows;
784 int mb_cols, mi_cols;
785 int mi_stride;
786
787 /*Whether to use previous frame's motion vectors for prediction.*/
788 int use_prev_frame_mvs;
789
790 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
791
792 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
793
794 /*struct loopfilter lf;*/
795 /*struct segmentation seg;*/
796
797 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
798 /* in pbi.*/
799 int frame_parallel_decode; /* frame-based threading.*/
800
801 /*Context probabilities for reference frame prediction*/
802 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
803 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
804 enum REFERENCE_MODE reference_mode;
805
806 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
807 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
808 /*unsigned int frame_context_idx; *//* Context to use/update */
809 /*FRAME_COUNTS counts;*/
810
811 unsigned int current_video_frame;
812 enum BITSTREAM_PROFILE profile;
813
814 enum vpx_bit_depth_t bit_depth;
815
816 int error_resilient_mode;
817 int frame_parallel_decoding_mode;
818
819 int byte_alignment;
820 int skip_loop_filter;
821
822 /*External BufferPool passed from outside.*/
823 struct BufferPool_s *buffer_pool;
824
825 int above_context_alloc_cols;
826
827};
828
829static void set_canvas(struct VP9Decoder_s *pbi,
830 struct PIC_BUFFER_CONFIG_s *pic_config);
831static int prepare_display_buf(struct VP9Decoder_s *pbi,
832 struct PIC_BUFFER_CONFIG_s *pic_config);
833
834static void fill_frame_info(struct VP9Decoder_s *pbi,
835 struct PIC_BUFFER_CONFIG_s *frame,
836 unsigned int framesize,
837 unsigned int pts);
838
839static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
840{
841 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
842}
843
844static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
845{
846 const int ref_index = *idx;
847
848 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
849 bufs[ref_index].ref_count--;
850 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
851 * ref_index, bufs[ref_index].ref_count);
852 */
853 }
854
855 *idx = new_idx;
856
857 bufs[new_idx].ref_count++;
858 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
859 * new_idx, bufs[new_idx].ref_count);
860 */
861}
862
863int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
864{
865 struct InternalFrameBuffer_s *const int_fb =
866 (struct InternalFrameBuffer_s *)fb->priv;
867 if (int_fb)
868 int_fb->in_use = 0;
869 return 0;
870}
871
872static int compute_losless_comp_body_size(int width, int height,
873 uint8_t is_bit_depth_10);
874
875static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
876 int print_header_info)
877{
878 cm->display_width = cm->width;
879 cm->display_height = cm->height;
880 if (params->p.display_size_present) {
881 if (print_header_info)
882 pr_info(" * 1-bit display_size_present read : 1\n");
883 cm->display_width = params->p.display_width;
884 cm->display_height = params->p.display_height;
885 /*vp9_read_frame_size(rb, &cm->display_width,
886 * &cm->display_height);
887 */
888 } else {
889 if (print_header_info)
890 pr_info(" * 1-bit display_size_present read : 0\n");
891 }
892}
893
894
895uint8_t print_header_info = 0;
896
897struct buff_s {
898 u32 buf_start;
899 u32 buf_size;
900 u32 buf_end;
901} buff_t;
902
903struct BuffInfo_s {
904 u32 max_width;
905 u32 max_height;
906 u32 start_adr;
907 u32 end_adr;
908 struct buff_s ipp;
909 struct buff_s sao_abv;
910 struct buff_s sao_vb;
911 struct buff_s short_term_rps;
912 struct buff_s vps;
913 struct buff_s sps;
914 struct buff_s pps;
915 struct buff_s sao_up;
916 struct buff_s swap_buf;
917 struct buff_s swap_buf2;
918 struct buff_s scalelut;
919 struct buff_s dblk_para;
920 struct buff_s dblk_data;
921 struct buff_s seg_map;
922 struct buff_s mmu_vbh;
923 struct buff_s cm_header;
924 struct buff_s mpred_above;
925#ifdef MV_USE_FIXED_BUF
926 struct buff_s mpred_mv;
927#endif
928 struct buff_s rpm;
929 struct buff_s lmem;
930} BuffInfo_t;
931
932#ifdef MULTI_INSTANCE_SUPPORT
933#define DEC_RESULT_NONE 0
934#define DEC_RESULT_DONE 1
935#define DEC_RESULT_AGAIN 2
936#define DEC_RESULT_CONFIG_PARAM 3
937#define DEC_RESULT_ERROR 4
938#define DEC_INIT_PICLIST 5
939#define DEC_UNINIT_PICLIST 6
940#define DEC_RESULT_GET_DATA 7
941#define DEC_RESULT_GET_DATA_RETRY 8
942#define DEC_RESULT_EOS 9
943#define DEC_RESULT_FORCE_EXIT 10
944
945#define DEC_S1_RESULT_NONE 0
946#define DEC_S1_RESULT_DONE 1
947#define DEC_S1_RESULT_FORCE_EXIT 2
948#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
949
950#ifdef FB_DECODING_TEST_SCHEDULE
951#define TEST_SET_NONE 0
952#define TEST_SET_PIC_DONE 1
953#define TEST_SET_S2_DONE 2
954#endif
955
956static void vp9_work(struct work_struct *work);
957#endif
958struct loop_filter_info_n;
959struct loopfilter;
960struct segmentation;
961
962#ifdef SUPPORT_FB_DECODING
963static void mpred_process(struct VP9Decoder_s *pbi);
964static void vp9_s1_work(struct work_struct *work);
965
966struct stage_buf_s {
967 int index;
968 unsigned short rpm[RPM_END - RPM_BEGIN];
969};
970
971static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
972
973static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
974
975#ifdef FB_DECODING_TEST_SCHEDULE
976u32 stage_buf_num; /* = 16;*/
977#else
978u32 stage_buf_num;
979#endif
980#endif
981
982struct VP9Decoder_s {
983#ifdef MULTI_INSTANCE_SUPPORT
984 unsigned char index;
985
986 struct device *cma_dev;
987 struct platform_device *platform_dev;
988 void (*vdec_cb)(struct vdec_s *, void *);
989 void *vdec_cb_arg;
990 struct vframe_chunk_s *chunk;
991 int dec_result;
992 struct work_struct work;
993 struct work_struct set_clk_work;
994 u32 start_shift_bytes;
995
996 struct BuffInfo_s work_space_buf_store;
997 unsigned long buf_start;
998 u32 buf_size;
999 u32 cma_alloc_count;
1000 unsigned long cma_alloc_addr;
1001 uint8_t eos;
1002 unsigned long int start_process_time;
1003 unsigned last_lcu_idx;
1004 int decode_timeout_count;
1005 unsigned timeout_num;
1006 int save_buffer_mode;
1007
1008 int double_write_mode;
1009#endif
1010 long used_4k_num;
1011
1012 unsigned char m_ins_flag;
1013 char *provider_name;
1014 union param_u param;
1015 int frame_count;
1016 int pic_count;
1017 u32 stat;
1018 struct timer_list timer;
1019 u32 frame_dur;
1020 u32 frame_ar;
1021 int fatal_error;
1022 uint8_t init_flag;
1023 uint8_t first_sc_checked;
1024 uint8_t process_busy;
1025#define PROC_STATE_INIT 0
1026#define PROC_STATE_DECODESLICE 1
1027#define PROC_STATE_SENDAGAIN 2
1028 uint8_t process_state;
1029 u32 ucode_pause_pos;
1030
1031 int show_frame_num;
1032 struct buff_s mc_buf_spec;
1033 struct dec_sysinfo vvp9_amstream_dec_info;
1034 void *rpm_addr;
1035 void *lmem_addr;
1036 dma_addr_t rpm_phy_addr;
1037 dma_addr_t lmem_phy_addr;
1038 unsigned short *lmem_ptr;
1039 unsigned short *debug_ptr;
1040
1041 void *prob_buffer_addr;
1042 void *count_buffer_addr;
1043 dma_addr_t prob_buffer_phy_addr;
1044 dma_addr_t count_buffer_phy_addr;
1045
1046 void *frame_mmu_map_addr;
1047 dma_addr_t frame_mmu_map_phy_addr;
1048
1049 unsigned int use_cma_flag;
1050
1051 struct BUF_s m_BUF[MAX_BUF_NUM];
1052 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1053 u32 used_buf_num;
1054 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1055 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1056 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1057 struct vframe_s vfpool[VF_POOL_SIZE];
1058 u32 vf_pre_count;
1059 u32 vf_get_count;
1060 u32 vf_put_count;
1061 int buf_num;
1062 int pic_num;
1063 int lcu_size_log2;
1064 unsigned int losless_comp_body_size;
1065
1066 u32 video_signal_type;
1067
1068 int pts_mode;
1069 int last_lookup_pts;
1070 int last_pts;
1071 u64 last_lookup_pts_us64;
1072 u64 last_pts_us64;
1073 u64 shift_byte_count;
1074
1075 u32 pts_unstable;
1076 u32 frame_cnt_window;
1077 u32 pts1, pts2;
1078 u32 last_duration;
1079 u32 duration_from_pts_done;
1080 bool vp9_first_pts_ready;
1081
1082 u32 shift_byte_count_lo;
1083 u32 shift_byte_count_hi;
1084 int pts_mode_switching_count;
1085 int pts_mode_recovery_count;
1086
1087 bool get_frame_dur;
1088 u32 saved_resolution;
1089
1090 /**/
1091 struct VP9_Common_s common;
1092 struct RefCntBuffer_s *cur_buf;
1093 int refresh_frame_flags;
1094 uint8_t need_resync;
1095 uint8_t hold_ref_buf;
1096 uint8_t ready_for_new_data;
1097 struct BufferPool_s vp9_buffer_pool;
1098
1099 struct BuffInfo_s *work_space_buf;
1100
1101 struct buff_s *mc_buf;
1102
1103 unsigned int frame_width;
1104 unsigned int frame_height;
1105
1106 unsigned short *rpm_ptr;
1107 int init_pic_w;
1108 int init_pic_h;
1109 int lcu_total;
1110 int lcu_size;
1111
1112 int slice_type;
1113
1114 int skip_flag;
1115 int decode_idx;
1116 int slice_idx;
1117 uint8_t has_keyframe;
1118 uint8_t wait_buf;
1119 uint8_t error_flag;
1120
1121 /* bit 0, for decoding; bit 1, for displaying */
1122 uint8_t ignore_bufmgr_error;
1123 int PB_skip_mode;
1124 int PB_skip_count_after_decoding;
1125 /*hw*/
1126
1127 /*lf*/
1128 int default_filt_lvl;
1129 struct loop_filter_info_n *lfi;
1130 struct loopfilter *lf;
1131 struct segmentation *seg_4lf;
1132 /**/
1133 struct vdec_info *gvs;
1134
1135 u32 pre_stream_offset;
1136
1137 unsigned int dec_status;
1138 u32 last_put_idx;
1139 int new_frame_displayed;
1140 void *mmu_box;
1141 void *bmmu_box;
1142 int mmu_enable;
1143 struct vframe_master_display_colour_s vf_dp;
1144 struct firmware_s *fw;
1145 int max_pic_w;
1146 int max_pic_h;
1147#ifdef SUPPORT_FB_DECODING
1148 int dec_s1_result;
1149 int s1_test_cmd;
1150 struct work_struct s1_work;
1151 int used_stage_buf_num;
1152 int s1_pos;
1153 int s2_pos;
1154 void *stage_mmu_map_addr;
1155 dma_addr_t stage_mmu_map_phy_addr;
1156 struct stage_buf_s *s1_buf;
1157 struct stage_buf_s *s2_buf;
1158 struct stage_buf_s *stage_bufs
1159 [STAGE_MAX_BUFFERS];
1160 unsigned char run2_busy;
1161
1162 int s1_mv_buf_index;
1163 int s1_mv_buf_index_pre;
1164 int s1_mv_buf_index_pre_pre;
1165 unsigned long s1_mpred_mv_wr_start_addr;
1166 unsigned long s1_mpred_mv_wr_start_addr_pre;
1167 unsigned short s1_intra_only;
1168 unsigned short s1_frame_type;
1169 unsigned short s1_width;
1170 unsigned short s1_height;
1171 unsigned short s1_last_show_frame;
1172 union param_u s1_param;
1173 u8 back_not_run_ready;
1174#endif
1175 int need_cache_size;
1176 u64 sc_start_time;
1177 bool postproc_done;
1178 int low_latency_flag;
1179 bool no_head;
1180 bool pic_list_init_done;
1181 bool pic_list_init_done2;
1182 bool is_used_v4l;
1183 void *v4l2_ctx;
1184 int frameinfo_enable;
1185 struct vframe_qos_s vframe_qos;
1186};
1187
1188static int vp9_print(struct VP9Decoder_s *pbi,
1189 int flag, const char *fmt, ...)
1190{
1191#define HEVC_PRINT_BUF 256
1192 unsigned char buf[HEVC_PRINT_BUF];
1193 int len = 0;
1194
1195 if (pbi == NULL ||
1196 (flag == 0) ||
1197 (debug & flag)) {
1198 va_list args;
1199
1200 va_start(args, fmt);
1201 if (pbi)
1202 len = sprintf(buf, "[%d]", pbi->index);
1203 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1204 pr_debug("%s", buf);
1205 va_end(args);
1206 }
1207 return 0;
1208}
1209
1210static int is_oversize(int w, int h)
1211{
1212 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1213 MAX_SIZE_8K : MAX_SIZE_4K;
1214
1215 if (w <= 0 || h <= 0)
1216 return true;
1217
1218 if (h != 0 && (w > max / h))
1219 return true;
1220
1221 return false;
1222}
1223
1224static int v4l_get_fb(struct aml_vcodec_ctx *ctx, struct vdec_fb **out)
1225{
1226 int ret = 0;
1227
1228 ret = ctx->dec_if->get_param(ctx->drv_handle,
1229 GET_PARAM_FREE_FRAME_BUFFER, out);
1230
1231 return ret;
1232}
1233
1234static void resize_context_buffers(struct VP9Decoder_s *pbi,
1235 struct VP9_Common_s *cm, int width, int height)
1236{
1237 if (cm->width != width || cm->height != height) {
1238 /* to do ..*/
1239 if (pbi != NULL) {
1240 pbi->vp9_first_pts_ready = 0;
1241 pbi->duration_from_pts_done = 0;
1242 }
1243 cm->width = width;
1244 cm->height = height;
1245 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1246 cm->height, width, height);
1247 }
1248 /*
1249 *if (cm->cur_frame->mvs == NULL ||
1250 * cm->mi_rows > cm->cur_frame->mi_rows ||
1251 * cm->mi_cols > cm->cur_frame->mi_cols) {
1252 * resize_mv_buffer(cm);
1253 *}
1254 */
1255}
1256
1257static int valid_ref_frame_size(int ref_width, int ref_height,
1258 int this_width, int this_height) {
1259 return 2 * this_width >= ref_width &&
1260 2 * this_height >= ref_height &&
1261 this_width <= 16 * ref_width &&
1262 this_height <= 16 * ref_height;
1263}
1264
1265/*
1266 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1267 * int ref_xss, int ref_yss,
1268 * enum vpx_bit_depth_t this_bit_depth,
1269 * int this_xss, int this_yss) {
1270 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1271 * ref_yss == this_yss;
1272 *}
1273 */
1274
1275
1276static int setup_frame_size(
1277 struct VP9Decoder_s *pbi,
1278 struct VP9_Common_s *cm, union param_u *params,
1279 unsigned int *mmu_index_adr,
1280 int print_header_info) {
1281 int width, height;
1282 struct BufferPool_s * const pool = cm->buffer_pool;
1283 struct PIC_BUFFER_CONFIG_s *ybf;
1284 int ret = 0;
1285
1286 width = params->p.width;
1287 height = params->p.height;
1288 if (is_oversize(width, height)) {
1289 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1290 return -1;
1291 }
1292
1293 /*vp9_read_frame_size(rb, &width, &height);*/
1294 if (print_header_info)
1295 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1296 if (print_header_info)
1297 pr_info
1298 (" * 16-bits h read : %d (height : %d)\n", width, height);
1299
1300 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1301#ifdef VP9_10B_HED_FB
1302 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1303#endif
1304 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1305 ret = vp9_alloc_mmu(pbi,
1306 cm->new_fb_idx,
1307 params->p.width,
1308 params->p.height,
1309 params->p.bit_depth,
1310 mmu_index_adr);
1311 if (ret != 0) {
1312 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1313 cm->new_fb_idx,
1314 ret);
1315 return ret;
1316 }
1317 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1318 }
1319
1320 resize_context_buffers(pbi, cm, width, height);
1321 setup_display_size(cm, params, print_header_info);
1322#if 0
1323 lock_buffer_pool(pool);
1324 if (vp9_realloc_frame_buffer(
1325 get_frame_new_buffer(cm), cm->width, cm->height,
1326 cm->subsampling_x, cm->subsampling_y,
1327#if CONFIG_VP9_HIGHBITDEPTH
1328 cm->use_highbitdepth,
1329#endif
1330 VP9_DEC_BORDER_IN_PIXELS,
1331 cm->byte_alignment,
1332 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1333 pool->get_fb_cb, pool->cb_priv)) {
1334 unlock_buffer_pool(pool);
1335 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1336 "Failed to allocate frame buffer");
1337 }
1338 unlock_buffer_pool(pool);
1339#else
1340 /* porting */
1341 ybf = get_frame_new_buffer(cm);
1342 ybf->y_crop_width = width;
1343 ybf->y_crop_height = height;
1344 ybf->bit_depth = params->p.bit_depth;
1345#endif
1346 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1347 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1348 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1349 (unsigned int)cm->bit_depth;
1350 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1351 return ret;
1352}
1353
1354static int setup_frame_size_with_refs(
1355 struct VP9Decoder_s *pbi,
1356 struct VP9_Common_s *cm,
1357 union param_u *params,
1358 unsigned int *mmu_index_adr,
1359 int print_header_info) {
1360
1361 int width, height;
1362 int found = 0, i;
1363 int has_valid_ref_frame = 0;
1364 struct PIC_BUFFER_CONFIG_s *ybf;
1365 struct BufferPool_s * const pool = cm->buffer_pool;
1366 int ret = 0;
1367
1368 for (i = 0; i < REFS_PER_FRAME; ++i) {
1369 if ((params->p.same_frame_size >>
1370 (REFS_PER_FRAME - i - 1)) & 0x1) {
1371 struct PIC_BUFFER_CONFIG_s *const buf =
1372 cm->frame_refs[i].buf;
1373 /*if (print_header_info)
1374 * pr_info
1375 * ("1-bit same_frame_size[%d] read : 1\n", i);
1376 */
1377 width = buf->y_crop_width;
1378 height = buf->y_crop_height;
1379 /*if (print_header_info)
1380 * pr_info
1381 * (" - same_frame_size width : %d\n", width);
1382 */
1383 /*if (print_header_info)
1384 * pr_info
1385 * (" - same_frame_size height : %d\n", height);
1386 */
1387 found = 1;
1388 break;
1389 } else {
1390 /*if (print_header_info)
1391 * pr_info
1392 * ("1-bit same_frame_size[%d] read : 0\n", i);
1393 */
1394 }
1395 }
1396
1397 if (!found) {
1398 /*vp9_read_frame_size(rb, &width, &height);*/
1399 width = params->p.width;
1400 height = params->p.height;
1401 /*if (print_header_info)
1402 * pr_info
1403 * (" * 16-bits w read : %d (width : %d)\n",
1404 * width, height);
1405 *if (print_header_info)
1406 * pr_info
1407 * (" * 16-bits h read : %d (height : %d)\n",
1408 * width, height);
1409 */
1410 }
1411
1412 if (is_oversize(width, height)) {
1413 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1414 return -1;
1415 }
1416
1417 params->p.width = width;
1418 params->p.height = height;
1419
1420 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1421 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1422 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1423 *cm->prev_fb_idx = cm->new_fb_idx;
1424 */
1425 /* pr_info
1426 * ("[DEBUG DEBUG]Before alloc_mmu,
1427 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1428 * cm->prev_fb_idx, cm->new_fb_idx);
1429 */
1430 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1431 params->p.width, params->p.height,
1432 params->p.bit_depth, mmu_index_adr);
1433 if (ret != 0) {
1434 pr_err("can't alloc need mmu,idx %d\r\n",
1435 cm->new_fb_idx);
1436 return ret;
1437 }
1438 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1439 }
1440
1441 /*Check to make sure at least one of frames that this frame references
1442 *has valid dimensions.
1443 */
1444 for (i = 0; i < REFS_PER_FRAME; ++i) {
1445 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1446
1447 has_valid_ref_frame |=
1448 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1449 ref_frame->buf->y_crop_height,
1450 width, height);
1451 }
1452 if (!has_valid_ref_frame) {
1453 pr_err("Error: Referenced frame has invalid size\r\n");
1454 return -1;
1455 }
1456#if 0
1457 for (i = 0; i < REFS_PER_FRAME; ++i) {
1458 struct RefBuffer_s * const ref_frame =
1459 &cm->frame_refs[i];
1460 if (!valid_ref_frame_img_fmt(
1461 ref_frame->buf->bit_depth,
1462 ref_frame->buf->subsampling_x,
1463 ref_frame->buf->subsampling_y,
1464 cm->bit_depth,
1465 cm->subsampling_x,
1466 cm->subsampling_y))
1467 pr_err
1468 ("Referenced frame incompatible color fmt\r\n");
1469 return -1;
1470 }
1471#endif
1472 resize_context_buffers(pbi, cm, width, height);
1473 setup_display_size(cm, params, print_header_info);
1474
1475#if 0
1476 lock_buffer_pool(pool);
1477 if (vp9_realloc_frame_buffer(
1478 get_frame_new_buffer(cm), cm->width, cm->height,
1479 cm->subsampling_x, cm->subsampling_y,
1480#if CONFIG_VP9_HIGHBITDEPTH
1481 cm->use_highbitdepth,
1482#endif
1483 VP9_DEC_BORDER_IN_PIXELS,
1484 cm->byte_alignment,
1485 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1486 pool->get_fb_cb,
1487 pool->cb_priv)) {
1488 unlock_buffer_pool(pool);
1489 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1490 "Failed to allocate frame buffer");
1491 }
1492 unlock_buffer_pool(pool);
1493#else
1494 /* porting */
1495 ybf = get_frame_new_buffer(cm);
1496 ybf->y_crop_width = width;
1497 ybf->y_crop_height = height;
1498 ybf->bit_depth = params->p.bit_depth;
1499#endif
1500 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1501 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1502 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1503 (unsigned int)cm->bit_depth;
1504 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1505 return ret;
1506}
1507
1508static inline bool close_to(int a, int b, int m)
1509{
1510 return (abs(a - b) < m) ? true : false;
1511}
1512
1513#ifdef MULTI_INSTANCE_SUPPORT
1514static int vp9_print_cont(struct VP9Decoder_s *pbi,
1515 int flag, const char *fmt, ...)
1516{
1517 unsigned char buf[HEVC_PRINT_BUF];
1518 int len = 0;
1519
1520 if (pbi == NULL ||
1521 (flag == 0) ||
1522 (debug & flag)) {
1523 va_list args;
1524
1525 va_start(args, fmt);
1526 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1527 pr_debug("%s", buf);
1528 va_end(args);
1529 }
1530 return 0;
1531}
1532
1533static void trigger_schedule(struct VP9Decoder_s *pbi)
1534{
1535 if (pbi->vdec_cb)
1536 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1537}
1538
1539static void reset_process_time(struct VP9Decoder_s *pbi)
1540{
1541 if (pbi->start_process_time) {
1542 unsigned process_time =
1543 1000 * (jiffies - pbi->start_process_time) / HZ;
1544 pbi->start_process_time = 0;
1545 if (process_time > max_process_time[pbi->index])
1546 max_process_time[pbi->index] = process_time;
1547 }
1548}
1549
1550static void start_process_time(struct VP9Decoder_s *pbi)
1551{
1552 pbi->start_process_time = jiffies;
1553 pbi->decode_timeout_count = 0;
1554 pbi->last_lcu_idx = 0;
1555}
1556
1557static void timeout_process(struct VP9Decoder_s *pbi)
1558{
1559 pbi->timeout_num++;
1560 amhevc_stop();
1561 vp9_print(pbi,
1562 0, "%s decoder timeout\n", __func__);
1563
1564 pbi->dec_result = DEC_RESULT_DONE;
1565 reset_process_time(pbi);
1566 vdec_schedule_work(&pbi->work);
1567}
1568
1569static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1570{
1571 return ((double_write_mode & 0x80000000) == 0) ?
1572 pbi->double_write_mode :
1573 (double_write_mode & 0x7fffffff);
1574}
1575
1576static int get_double_write_mode(struct VP9Decoder_s *pbi)
1577{
1578 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1579 u32 dw;
1580 int w, h;
1581 struct VP9_Common_s *cm = &pbi->common;
1582 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1583
1584 /* mask for supporting double write value bigger than 0x100 */
1585 if (valid_dw_mode & 0xffffff00) {
1586 if (!cm->cur_frame)
1587 return 1;/*no valid frame,*/
1588 cur_pic_config = &cm->cur_frame->buf;
1589 w = cur_pic_config->y_crop_width;
1590 h = cur_pic_config->y_crop_height;
1591
1592 dw = 0x1; /*1:1*/
1593 switch (valid_dw_mode) {
1594 case 0x100:
1595 if (w > 1920 && h > 1088)
1596 dw = 0x4; /*1:2*/
1597 break;
1598 case 0x200:
1599 if (w > 1920 && h > 1088)
1600 dw = 0x2; /*1:4*/
1601 break;
1602 case 0x300:
1603 if (w > 1280 && h > 720)
1604 dw = 0x4; /*1:2*/
1605 break;
1606 default:
1607 break;
1608 }
1609 return dw;
1610 }
1611
1612 return valid_dw_mode;
1613}
1614
1615/* for double write buf alloc */
1616static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1617{
1618 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1619 u32 dw;
1620 int w = pbi->init_pic_w;
1621 int h = pbi->init_pic_h;
1622
1623 dw = 0x1; /*1:1*/
1624 switch (valid_dw_mode) {
1625 case 0x100:
1626 if (w > 1920 && h > 1088)
1627 dw = 0x4; /*1:2*/
1628 break;
1629 case 0x200:
1630 if (w > 1920 && h > 1088)
1631 dw = 0x2; /*1:4*/
1632 break;
1633 case 0x300:
1634 if (w > 1280 && h > 720)
1635 dw = 0x4; /*1:2*/
1636 break;
1637 default:
1638 dw = valid_dw_mode;
1639 break;
1640 }
1641 return dw;
1642}
1643#endif
1644
1645static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1646 int dw_mode)
1647{
1648 int ratio = 1;
1649 if ((dw_mode == 2) ||
1650 (dw_mode == 3))
1651 ratio = 4;
1652 else if (dw_mode == 4)
1653 ratio = 2;
1654 return ratio;
1655}
1656
1657//#define MAX_4K_NUM 0x1200
1658
1659int vp9_alloc_mmu(
1660 struct VP9Decoder_s *pbi,
1661 int cur_buf_idx,
1662 int pic_width,
1663 int pic_height,
1664 unsigned short bit_depth,
1665 unsigned int *mmu_index_adr)
1666{
1667 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1668 int picture_size;
1669 int cur_mmu_4k_number, max_frame_num;
1670 if (!pbi->mmu_box) {
1671 pr_err("error no mmu box!\n");
1672 return -1;
1673 }
1674 if (pbi->double_write_mode & 0x10)
1675 return 0;
1676 if (bit_depth >= VPX_BITS_12) {
1677 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1678 pr_err("fatal_error, un support bit depth 12!\n\n");
1679 return -1;
1680 }
1681 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1682 bit_depth_10);
1683 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1684
1685 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1686 max_frame_num = MAX_FRAME_8K_NUM;
1687 else
1688 max_frame_num = MAX_FRAME_4K_NUM;
1689
1690 if (cur_mmu_4k_number > max_frame_num) {
1691 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1692 cur_mmu_4k_number, pic_width, pic_height);
1693 return -1;
1694 }
1695 return decoder_mmu_box_alloc_idx(
1696 pbi->mmu_box,
1697 cur_buf_idx,
1698 cur_mmu_4k_number,
1699 mmu_index_adr);
1700}
1701
1702
1703#ifndef MV_USE_FIXED_BUF
1704static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1705{
1706 int i;
1707 for (i = 0; i < MV_BUFFER_NUM; i++) {
1708 if (pbi->m_mv_BUF[i].start_adr) {
1709 if (debug)
1710 pr_info(
1711 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1712 i, pbi->m_mv_BUF[i].start_adr,
1713 pbi->m_mv_BUF[i].size,
1714 pbi->m_mv_BUF[i].used_flag);
1715 decoder_bmmu_box_free_idx(
1716 pbi->bmmu_box,
1717 MV_BUFFER_IDX(i));
1718 pbi->m_mv_BUF[i].start_adr = 0;
1719 pbi->m_mv_BUF[i].size = 0;
1720 pbi->m_mv_BUF[i].used_flag = 0;
1721 }
1722 }
1723}
1724
1725static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1726 int i, int size)
1727{
1728 int ret = 0;
1729 if (decoder_bmmu_box_alloc_buf_phy
1730 (pbi->bmmu_box,
1731 MV_BUFFER_IDX(i), size,
1732 DRIVER_NAME,
1733 &pbi->m_mv_BUF[i].start_adr) < 0) {
1734 pbi->m_mv_BUF[i].start_adr = 0;
1735 ret = -1;
1736 } else {
1737 pbi->m_mv_BUF[i].size = size;
1738 pbi->m_mv_BUF[i].used_flag = 0;
1739 ret = 0;
1740 if (debug) {
1741 pr_info(
1742 "MV Buffer %d: start_adr %p size %x\n",
1743 i,
1744 (void *)pbi->m_mv_BUF[i].start_adr,
1745 pbi->m_mv_BUF[i].size);
1746 }
1747 }
1748 return ret;
1749}
1750
1751static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1752{
1753 int i;
1754 int ret = 0;
1755 int count = MV_BUFFER_NUM;
1756 int pic_width = pbi->init_pic_w;
1757 int pic_height = pbi->init_pic_h;
1758 int lcu_size = 64; /*fixed 64*/
1759 int pic_width_64 = (pic_width + 63) & (~0x3f);
1760 int pic_height_32 = (pic_height + 31) & (~0x1f);
1761 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1762 pic_width_64 / lcu_size + 1
1763 : pic_width_64 / lcu_size;
1764 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1765 pic_height_32 / lcu_size + 1
1766 : pic_height_32 / lcu_size;
1767 int lcu_total = pic_width_lcu * pic_height_lcu;
1768 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1769 (~0xffff);
1770 if (mv_buf_margin > 0)
1771 count = REF_FRAMES + mv_buf_margin;
1772
1773 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1774 count = REF_FRAMES_4K + mv_buf_margin;
1775
1776 if (debug) {
1777 pr_info("%s w:%d, h:%d, count: %d\n",
1778 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1779 }
1780
1781 for (i = 0;
1782 i < count && i < MV_BUFFER_NUM; i++) {
1783 if (alloc_mv_buf(pbi, i, size) < 0) {
1784 ret = -1;
1785 break;
1786 }
1787 }
1788 return ret;
1789}
1790
1791static int get_mv_buf(struct VP9Decoder_s *pbi,
1792 int *mv_buf_index,
1793 unsigned long *mpred_mv_wr_start_addr)
1794{
1795 int i;
1796 int ret = -1;
1797 for (i = 0; i < MV_BUFFER_NUM; i++) {
1798 if (pbi->m_mv_BUF[i].start_adr &&
1799 pbi->m_mv_BUF[i].used_flag == 0) {
1800 pbi->m_mv_BUF[i].used_flag = 1;
1801 ret = i;
1802 break;
1803 }
1804 }
1805
1806 if (ret >= 0) {
1807 *mv_buf_index = ret;
1808 *mpred_mv_wr_start_addr =
1809 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1810 (~0xffff);
1811 if (debug & VP9_DEBUG_BUFMGR_MORE)
1812 pr_info(
1813 "%s => %d (%ld) size 0x%x\n",
1814 __func__, ret,
1815 *mpred_mv_wr_start_addr,
1816 pbi->m_mv_BUF[ret].size);
1817 } else {
1818 pr_info(
1819 "%s: Error, mv buf is not enough\n",
1820 __func__);
1821 }
1822 return ret;
1823}
1824
1825static void put_mv_buf(struct VP9Decoder_s *pbi,
1826 int *mv_buf_index)
1827{
1828 int i = *mv_buf_index;
1829 if (i >= MV_BUFFER_NUM) {
1830 if (debug & VP9_DEBUG_BUFMGR_MORE)
1831 pr_info(
1832 "%s: index %d beyond range\n",
1833 __func__, i);
1834 return;
1835 }
1836 if (debug & VP9_DEBUG_BUFMGR_MORE)
1837 pr_info(
1838 "%s(%d): used_flag(%d)\n",
1839 __func__, i,
1840 pbi->m_mv_BUF[i].used_flag);
1841
1842 *mv_buf_index = -1;
1843 if (pbi->m_mv_BUF[i].start_adr &&
1844 pbi->m_mv_BUF[i].used_flag)
1845 pbi->m_mv_BUF[i].used_flag = 0;
1846}
1847
1848static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1849{
1850 struct VP9_Common_s *const cm = &pbi->common;
1851 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1852 int i;
1853 for (i = 0; i < pbi->used_buf_num; ++i) {
1854 if ((frame_bufs[i].ref_count == 0) &&
1855 (frame_bufs[i].buf.index != -1) &&
1856 (frame_bufs[i].buf.mv_buf_index >= 0)
1857 )
1858 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1859 }
1860}
1861
1862#ifdef SUPPORT_FB_DECODING
1863static bool mv_buf_available(struct VP9Decoder_s *pbi)
1864{
1865 int i;
1866 bool ret = 0;
1867 for (i = 0; i < MV_BUFFER_NUM; i++) {
1868 if (pbi->m_mv_BUF[i].start_adr &&
1869 pbi->m_mv_BUF[i].used_flag == 0) {
1870 ret = 1;
1871 break;
1872 }
1873 }
1874 return ret;
1875}
1876#endif
1877#endif
1878
1879#ifdef SUPPORT_FB_DECODING
1880static void init_stage_buf(struct VP9Decoder_s *pbi)
1881{
1882 uint i;
1883 for (i = 0; i < STAGE_MAX_BUFFERS
1884 && i < stage_buf_num; i++) {
1885 pbi->stage_bufs[i] =
1886 vmalloc(sizeof(struct stage_buf_s));
1887 if (pbi->stage_bufs[i] == NULL) {
1888 vp9_print(pbi,
1889 0, "%s vmalloc fail\n", __func__);
1890 break;
1891 }
1892 pbi->stage_bufs[i]->index = i;
1893 }
1894 pbi->used_stage_buf_num = i;
1895 pbi->s1_pos = 0;
1896 pbi->s2_pos = 0;
1897 pbi->s1_buf = NULL;
1898 pbi->s2_buf = NULL;
1899 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1900 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1901 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1902
1903 if (pbi->used_stage_buf_num > 0)
1904 vp9_print(pbi,
1905 0, "%s 2 stage decoding buf %d\n",
1906 __func__,
1907 pbi->used_stage_buf_num);
1908}
1909
1910static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1911{
1912 int i;
1913 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1914 if (pbi->stage_bufs[i])
1915 vfree(pbi->stage_bufs[i]);
1916 pbi->stage_bufs[i] = NULL;
1917 }
1918 pbi->used_stage_buf_num = 0;
1919 pbi->s1_pos = 0;
1920 pbi->s2_pos = 0;
1921 pbi->s1_buf = NULL;
1922 pbi->s2_buf = NULL;
1923}
1924
1925static int get_s1_buf(
1926 struct VP9Decoder_s *pbi)
1927{
1928 struct stage_buf_s *buf = NULL;
1929 int ret = -1;
1930 int buf_page_num = MAX_STAGE_PAGE_NUM;
1931 int next_s1_pos = pbi->s1_pos + 1;
1932
1933 if (next_s1_pos >= pbi->used_stage_buf_num)
1934 next_s1_pos = 0;
1935 if (next_s1_pos == pbi->s2_pos) {
1936 pbi->s1_buf = NULL;
1937 return ret;
1938 }
1939
1940 buf = pbi->stage_bufs[pbi->s1_pos];
1941 ret = decoder_mmu_box_alloc_idx(
1942 pbi->mmu_box,
1943 buf->index,
1944 buf_page_num,
1945 pbi->stage_mmu_map_addr);
1946 if (ret < 0) {
1947 vp9_print(pbi, 0,
1948 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1949 __func__, buf->index,
1950 pbi->s1_pos, pbi->s2_pos);
1951 buf = NULL;
1952 } else {
1953 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1954 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1955 __func__, buf_page_num, buf->index,
1956 pbi->s1_pos, pbi->s2_pos);
1957 }
1958 pbi->s1_buf = buf;
1959 return ret;
1960}
1961
1962static void inc_s1_pos(struct VP9Decoder_s *pbi)
1963{
1964 struct stage_buf_s *buf =
1965 pbi->stage_bufs[pbi->s1_pos];
1966
1967 int used_page_num =
1968#ifdef FB_DECODING_TEST_SCHEDULE
1969 MAX_STAGE_PAGE_NUM/2;
1970#else
1971 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
1972#endif
1973 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
1974 FRAME_BUFFERS + buf->index, used_page_num);
1975
1976 pbi->s1_pos++;
1977 if (pbi->s1_pos >= pbi->used_stage_buf_num)
1978 pbi->s1_pos = 0;
1979
1980 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1981 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
1982 __func__, used_page_num, buf->index,
1983 pbi->s1_pos, pbi->s2_pos);
1984}
1985
1986#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
1987
1988static int get_s2_buf(
1989 struct VP9Decoder_s *pbi)
1990{
1991 int ret = -1;
1992 struct stage_buf_s *buf = NULL;
1993 if (s2_buf_available(pbi)) {
1994 buf = pbi->stage_bufs[pbi->s2_pos];
1995 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1996 "%s for index %d (s1_pos %d s2_pos %d)\n",
1997 __func__, buf->index,
1998 pbi->s1_pos, pbi->s2_pos);
1999 pbi->s2_buf = buf;
2000 ret = 0;
2001 }
2002 return ret;
2003}
2004
2005static void inc_s2_pos(struct VP9Decoder_s *pbi)
2006{
2007 struct stage_buf_s *buf =
2008 pbi->stage_bufs[pbi->s2_pos];
2009 decoder_mmu_box_free_idx(pbi->mmu_box,
2010 FRAME_BUFFERS + buf->index);
2011 pbi->s2_pos++;
2012 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2013 pbi->s2_pos = 0;
2014 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2015 "%s for index %d (s1_pos %d s2_pos %d)\n",
2016 __func__, buf->index,
2017 pbi->s1_pos, pbi->s2_pos);
2018}
2019
2020static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2021{
2022 int num;
2023 if (pbi->s1_pos >= pbi->s2_pos)
2024 num = pbi->used_stage_buf_num -
2025 (pbi->s1_pos - pbi->s2_pos) - 1;
2026 else
2027 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2028 return num;
2029}
2030
2031#ifndef FB_DECODING_TEST_SCHEDULE
2032static DEFINE_SPINLOCK(fb_core_spin_lock);
2033
2034static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2035{
2036 /* to do: VLSI review
2037 completion of last LCU decoding in BACK
2038 */
2039 return 1;
2040}
2041
2042static void start_s1_decoding(struct VP9Decoder_s *pbi)
2043{
2044 /* to do: VLSI review
2045 after parser, how to start LCU decoding in BACK
2046 */
2047}
2048
2049static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2050{
2051 /* to do: VLSI review
2052 1. how to disconnect DMC for FRONT and BACK
2053 2. reset bit 13, 24, FRONT or BACK ??
2054 */
2055
2056 unsigned long flags;
2057 u32 reset_bits = 0;
2058 if (mask & HW_MASK_FRONT)
2059 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2060 spin_lock_irqsave(&fb_core_spin_lock, flags);
2061 codec_dmcbus_write(DMC_REQ_CTRL,
2062 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2063 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2064
2065 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2066 & (1 << 4)))
2067 ;
2068
2069 if ((mask & HW_MASK_FRONT) &&
2070 input_frame_based(vdec))
2071 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2072
2073 /*
2074 * 2: assist
2075 * 3: parser
2076 * 4: parser_state
2077 * 8: dblk
2078 * 11:mcpu
2079 * 12:ccpu
2080 * 13:ddr
2081 * 14:iqit
2082 * 15:ipp
2083 * 17:qdct
2084 * 18:mpred
2085 * 19:sao
2086 * 24:hevc_afifo
2087 */
2088 if (mask & HW_MASK_FRONT) {
2089 reset_bits =
2090 (1<<3)|(1<<4)|(1<<11)|
2091 (1<<12)|(1<<18);
2092 }
2093 if (mask & HW_MASK_BACK) {
2094 reset_bits =
2095 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2096 (1<<17)|(1<<19)|(1<<24);
2097 }
2098 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2099#if 0
2100 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2101 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2102 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2103#endif
2104 WRITE_VREG(DOS_SW_RESET3, 0);
2105
2106
2107 spin_lock_irqsave(&fb_core_spin_lock, flags);
2108 codec_dmcbus_write(DMC_REQ_CTRL,
2109 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2110 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2111
2112}
2113#endif
2114
2115#endif
2116
2117
2118static int get_free_fb(struct VP9Decoder_s *pbi)
2119{
2120 struct VP9_Common_s *const cm = &pbi->common;
2121 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2122 int i;
2123 unsigned long flags;
2124
2125 lock_buffer_pool(cm->buffer_pool, flags);
2126 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2127 for (i = 0; i < pbi->used_buf_num; ++i) {
2128 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2129 __func__, i, frame_bufs[i].ref_count,
2130 frame_bufs[i].buf.vf_ref,
2131 frame_bufs[i].buf.index);
2132 }
2133 }
2134 for (i = 0; i < pbi->used_buf_num; ++i) {
2135 if ((frame_bufs[i].ref_count == 0) &&
2136 (frame_bufs[i].buf.vf_ref == 0) &&
2137 (frame_bufs[i].buf.index != -1)
2138 )
2139 break;
2140 }
2141 if (i != pbi->used_buf_num) {
2142 frame_bufs[i].ref_count = 1;
2143 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2144 i, frame_bufs[i].ref_count);*/
2145 } else {
2146 /* Reset i to be INVALID_IDX to indicate
2147 no free buffer found*/
2148 i = INVALID_IDX;
2149 }
2150
2151 unlock_buffer_pool(cm->buffer_pool, flags);
2152 return i;
2153}
2154
2155static int get_free_buf_count(struct VP9Decoder_s *pbi)
2156{
2157 struct VP9_Common_s *const cm = &pbi->common;
2158 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2159 int i;
2160 int free_buf_count = 0;
2161 for (i = 0; i < pbi->used_buf_num; ++i)
2162 if ((frame_bufs[i].ref_count == 0) &&
2163 (frame_bufs[i].buf.vf_ref == 0) &&
2164 (frame_bufs[i].buf.index != -1)
2165 )
2166 free_buf_count++;
2167 return free_buf_count;
2168}
2169
2170static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2171 struct BufferPool_s *const pool)
2172{
2173 if (idx >= 0) {
2174 --frame_bufs[idx].ref_count;
2175 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2176 * frame_bufs[idx].ref_count);
2177 */
2178 /*A worker may only get a free framebuffer index when
2179 *calling get_free_fb. But the private buffer is not set up
2180 *until finish decoding header. So any error happens during
2181 *decoding header, the frame_bufs will not have valid priv
2182 *buffer.
2183 */
2184
2185 if (frame_bufs[idx].ref_count == 0 &&
2186 frame_bufs[idx].raw_frame_buffer.priv)
2187 vp9_release_frame_buffer
2188 (&frame_bufs[idx].raw_frame_buffer);
2189 }
2190}
2191
2192static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2193{
2194 struct VP9_Common_s *const cm = &pbi->common;
2195 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2196 struct BufferPool_s *const pool = cm->buffer_pool;
2197 int mask, ref_index = 0;
2198 unsigned long flags;
2199
2200 /* Generate next_ref_frame_map.*/
2201 lock_buffer_pool(pool, flags);
2202 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2203 if (mask & 1) {
2204 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2205 ++frame_bufs[cm->new_fb_idx].ref_count;
2206 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2207 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2208 */
2209 } else
2210 cm->next_ref_frame_map[ref_index] =
2211 cm->ref_frame_map[ref_index];
2212 /* Current thread holds the reference frame.*/
2213 if (cm->ref_frame_map[ref_index] >= 0) {
2214 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2215 /*pr_info
2216 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2217 *cm->ref_frame_map[ref_index],
2218 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2219 */
2220 }
2221 ++ref_index;
2222 }
2223
2224 for (; ref_index < REF_FRAMES; ++ref_index) {
2225 cm->next_ref_frame_map[ref_index] =
2226 cm->ref_frame_map[ref_index];
2227 /* Current thread holds the reference frame.*/
2228 if (cm->ref_frame_map[ref_index] >= 0) {
2229 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2230 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2231 *cm->ref_frame_map[ref_index],
2232 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2233 */
2234 }
2235 }
2236 unlock_buffer_pool(pool, flags);
2237 return;
2238}
2239
2240static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2241
2242{
2243 struct VP9_Common_s *const cm = &pbi->common;
2244 struct BufferPool_s *pool = cm->buffer_pool;
2245 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2246 int mask, ref_index = 0;
2247 unsigned long flags;
2248
2249 lock_buffer_pool(pool, flags);
2250 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2251 const int old_idx = cm->ref_frame_map[ref_index];
2252 /*Current thread releases the holding of reference frame.*/
2253 decrease_ref_count(old_idx, frame_bufs, pool);
2254
2255 /*Release the reference frame in reference map.*/
2256 if ((mask & 1) && old_idx >= 0)
2257 decrease_ref_count(old_idx, frame_bufs, pool);
2258 cm->ref_frame_map[ref_index] =
2259 cm->next_ref_frame_map[ref_index];
2260 ++ref_index;
2261 }
2262
2263 /*Current thread releases the holding of reference frame.*/
2264 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2265 ++ref_index) {
2266 const int old_idx = cm->ref_frame_map[ref_index];
2267
2268 decrease_ref_count(old_idx, frame_bufs, pool);
2269 cm->ref_frame_map[ref_index] =
2270 cm->next_ref_frame_map[ref_index];
2271 }
2272 unlock_buffer_pool(pool, flags);
2273 return;
2274}
2275
2276int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2277{
2278 struct VP9_Common_s *const cm = &pbi->common;
2279 struct BufferPool_s *pool = cm->buffer_pool;
2280 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2281 int i;
2282 int ret;
2283
2284 pbi->ready_for_new_data = 0;
2285
2286 if (pbi->has_keyframe == 0 &&
2287 params->p.frame_type != KEY_FRAME){
2288 on_no_keyframe_skiped++;
2289 return -2;
2290 }
2291 pbi->has_keyframe = 1;
2292 on_no_keyframe_skiped = 0;
2293#if 0
2294 if (pbi->mmu_enable) {
2295 if (!pbi->m_ins_flag)
2296 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2297 if (cm->prev_fb_idx >= 0) {
2298 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2299 cm->prev_fb_idx, pbi->used_4k_num);
2300 }
2301 }
2302#endif
2303 if (cm->new_fb_idx >= 0
2304 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2305 vp9_release_frame_buffer
2306 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2307 }
2308 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2309 cm->prev_fb_idx, cm->new_fb_idx);*/
2310#ifndef MV_USE_FIXED_BUF
2311 put_un_used_mv_bufs(pbi);
2312 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2313 dump_pic_list(pbi);
2314#endif
2315 cm->new_fb_idx = get_free_fb(pbi);
2316 if (cm->new_fb_idx == INVALID_IDX) {
2317 pr_info("get_free_fb error\r\n");
2318 return -1;
2319 }
2320#ifndef MV_USE_FIXED_BUF
2321#ifdef SUPPORT_FB_DECODING
2322 if (pbi->used_stage_buf_num == 0) {
2323#endif
2324 if (get_mv_buf(pbi,
2325 &pool->frame_bufs[cm->new_fb_idx].
2326 buf.mv_buf_index,
2327 &pool->frame_bufs[cm->new_fb_idx].
2328 buf.mpred_mv_wr_start_addr
2329 ) < 0) {
2330 pr_info("get_mv_buf fail\r\n");
2331 return -1;
2332 }
2333 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2334 dump_pic_list(pbi);
2335#ifdef SUPPORT_FB_DECODING
2336 }
2337#endif
2338#endif
2339 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2340 /*if (debug & VP9_DEBUG_BUFMGR)
2341 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2342 cm->new_fb_idx);*/
2343
2344 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2345 if (pbi->mmu_enable) {
2346 /* moved to after picture size ready
2347 *alloc_mmu(cm, params->p.width, params->p.height,
2348 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2349 */
2350 cm->prev_fb_idx = cm->new_fb_idx;
2351 }
2352 /*read_uncompressed_header()*/
2353 cm->last_frame_type = cm->frame_type;
2354 cm->last_intra_only = cm->intra_only;
2355 cm->profile = params->p.profile;
2356 if (cm->profile >= MAX_PROFILES) {
2357 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2358 return -1;
2359 }
2360 cm->show_existing_frame = params->p.show_existing_frame;
2361 if (cm->show_existing_frame) {
2362 /* Show an existing frame directly.*/
2363 int frame_to_show_idx = params->p.frame_to_show_idx;
2364 int frame_to_show;
2365 unsigned long flags;
2366 if (frame_to_show_idx >= REF_FRAMES) {
2367 pr_info("frame_to_show_idx %d exceed max index\r\n",
2368 frame_to_show_idx);
2369 return -1;
2370 }
2371
2372 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2373 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2374 lock_buffer_pool(pool, flags);
2375 if (frame_to_show < 0 ||
2376 frame_bufs[frame_to_show].ref_count < 1) {
2377 unlock_buffer_pool(pool, flags);
2378 pr_err
2379 ("Error:Buffer %d does not contain a decoded frame",
2380 frame_to_show);
2381 return -1;
2382 }
2383
2384 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2385 unlock_buffer_pool(pool, flags);
2386 pbi->refresh_frame_flags = 0;
2387 /*cm->lf.filter_level = 0;*/
2388 cm->show_frame = 1;
2389
2390 /*
2391 *if (pbi->frame_parallel_decode) {
2392 * for (i = 0; i < REF_FRAMES; ++i)
2393 * cm->next_ref_frame_map[i] =
2394 * cm->ref_frame_map[i];
2395 *}
2396 */
2397 /* do not decode, search next start code */
2398 return 1;
2399 }
2400 cm->frame_type = params->p.frame_type;
2401 cm->show_frame = params->p.show_frame;
2402 cm->error_resilient_mode = params->p.error_resilient_mode;
2403
2404
2405 if (cm->frame_type == KEY_FRAME) {
2406 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2407
2408 for (i = 0; i < REFS_PER_FRAME; ++i) {
2409 cm->frame_refs[i].idx = INVALID_IDX;
2410 cm->frame_refs[i].buf = NULL;
2411 }
2412
2413 ret = setup_frame_size(pbi,
2414 cm, params, pbi->frame_mmu_map_addr,
2415 print_header_info);
2416 if (ret)
2417 return -1;
2418 if (pbi->need_resync) {
2419 memset(&cm->ref_frame_map, -1,
2420 sizeof(cm->ref_frame_map));
2421 pbi->need_resync = 0;
2422 }
2423 } else {
2424 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2425 /*if (print_header_info) {
2426 * if (cm->show_frame)
2427 * pr_info
2428 * ("intra_only set to 0 because of show_frame\n");
2429 * else
2430 * pr_info
2431 * ("1-bit intra_only read: %d\n", cm->intra_only);
2432 *}
2433 */
2434
2435
2436 cm->reset_frame_context = cm->error_resilient_mode ?
2437 0 : params->p.reset_frame_context;
2438 if (print_header_info) {
2439 if (cm->error_resilient_mode)
2440 pr_info
2441 ("reset to 0 error_resilient_mode\n");
2442 else
2443 pr_info
2444 (" * 2-bits reset_frame_context read : %d\n",
2445 cm->reset_frame_context);
2446 }
2447
2448 if (cm->intra_only) {
2449 if (cm->profile > PROFILE_0) {
2450 /*read_bitdepth_colorspace_sampling(cm,
2451 * rb, print_header_info);
2452 */
2453 } else {
2454 /*NOTE: The intra-only frame header
2455 *does not include the specification
2456 *of either the color format or
2457 *color sub-sampling
2458 *in profile 0. VP9 specifies that the default
2459 *color format should be YUV 4:2:0 in this
2460 *case (normative).
2461 */
2462 cm->color_space = VPX_CS_BT_601;
2463 cm->subsampling_y = cm->subsampling_x = 1;
2464 cm->bit_depth = VPX_BITS_8;
2465 cm->use_highbitdepth = 0;
2466 }
2467
2468 pbi->refresh_frame_flags =
2469 params->p.refresh_frame_flags;
2470 /*if (print_header_info)
2471 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2472 * REF_FRAMES, pbi->refresh_frame_flags);
2473 */
2474 ret = setup_frame_size(pbi,
2475 cm,
2476 params,
2477 pbi->frame_mmu_map_addr,
2478 print_header_info);
2479 if (ret)
2480 return -1;
2481 if (pbi->need_resync) {
2482 memset(&cm->ref_frame_map, -1,
2483 sizeof(cm->ref_frame_map));
2484 pbi->need_resync = 0;
2485 }
2486 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2487 pbi->refresh_frame_flags =
2488 params->p.refresh_frame_flags;
2489 if (print_header_info)
2490 pr_info
2491 ("*%d-bits refresh_frame read:0x%x\n",
2492 REF_FRAMES, pbi->refresh_frame_flags);
2493 for (i = 0; i < REFS_PER_FRAME; ++i) {
2494 const int ref =
2495 (params->p.ref_info >>
2496 (((REFS_PER_FRAME-i-1)*4)+1))
2497 & 0x7;
2498 const int idx =
2499 cm->ref_frame_map[ref];
2500 struct RefBuffer_s * const ref_frame =
2501 &cm->frame_refs[i];
2502 if (print_header_info)
2503 pr_info("*%d-bits ref[%d]read:%d\n",
2504 REF_FRAMES_LOG2, i, ref);
2505 ref_frame->idx = idx;
2506 ref_frame->buf = &frame_bufs[idx].buf;
2507 cm->ref_frame_sign_bias[LAST_FRAME + i]
2508 = (params->p.ref_info >>
2509 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2510 if (print_header_info)
2511 pr_info("1bit ref_frame_sign_bias");
2512 /*pr_info
2513 *("%dread: %d\n",
2514 *LAST_FRAME+i,
2515 *cm->ref_frame_sign_bias
2516 *[LAST_FRAME + i]);
2517 */
2518 /*pr_info
2519 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2520 *__func__, ref_frame->idx);
2521 */
2522
2523 }
2524
2525 ret = setup_frame_size_with_refs(
2526 pbi,
2527 cm,
2528 params,
2529 pbi->frame_mmu_map_addr,
2530 print_header_info);
2531 if (ret)
2532 return -1;
2533 for (i = 0; i < REFS_PER_FRAME; ++i) {
2534 /*struct RefBuffer_s *const ref_buf =
2535 *&cm->frame_refs[i];
2536 */
2537 /* to do:
2538 *vp9_setup_scale_factors_for_frame
2539 */
2540 }
2541 }
2542 }
2543
2544 get_frame_new_buffer(cm)->bit_depth = cm->bit_depth;
2545 get_frame_new_buffer(cm)->color_space = cm->color_space;
2546 get_frame_new_buffer(cm)->slice_type = cm->frame_type;
2547
2548 if (pbi->need_resync) {
2549 pr_err
2550 ("Error: Keyframe/intra-only frame required to reset\r\n");
2551 return -1;
2552 }
2553 generate_next_ref_frames(pbi);
2554 pbi->hold_ref_buf = 1;
2555
2556#if 0
2557 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2558 vp9_setup_past_independence(cm);
2559 setup_loopfilter(&cm->lf, rb, print_header_info);
2560 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2561 setup_segmentation(&cm->seg, rb, print_header_info);
2562 setup_segmentation_dequant(cm, print_header_info);
2563
2564 setup_tile_info(cm, rb, print_header_info);
2565 sz = vp9_rb_read_literal(rb, 16);
2566 if (print_header_info)
2567 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2568
2569 if (sz == 0)
2570 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2571 "Invalid header size");
2572#endif
2573 /*end read_uncompressed_header()*/
2574 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2575 cm->width == cm->last_width &&
2576 cm->height == cm->last_height &&
2577 !cm->last_intra_only &&
2578 cm->last_show_frame &&
2579 (cm->last_frame_type != KEY_FRAME);
2580
2581 /*pr_info
2582 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2583 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2584 *pr_info
2585 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2586 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2587 */
2588 return 0;
2589}
2590
2591
2592void swap_frame_buffers(struct VP9Decoder_s *pbi)
2593{
2594 int ref_index = 0;
2595 struct VP9_Common_s *const cm = &pbi->common;
2596 struct BufferPool_s *const pool = cm->buffer_pool;
2597 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2598 unsigned long flags;
2599 refresh_ref_frames(pbi);
2600 pbi->hold_ref_buf = 0;
2601 cm->frame_to_show = get_frame_new_buffer(cm);
2602
2603 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2604 lock_buffer_pool(pool, flags);
2605 --frame_bufs[cm->new_fb_idx].ref_count;
2606 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2607 * frame_bufs[cm->new_fb_idx].ref_count);
2608 */
2609 unlock_buffer_pool(pool, flags);
2610 /*}*/
2611
2612 /*Invalidate these references until the next frame starts.*/
2613 for (ref_index = 0; ref_index < 3; ref_index++)
2614 cm->frame_refs[ref_index].idx = -1;
2615}
2616
2617#if 0
2618static void check_resync(vpx_codec_alg_priv_t *const ctx,
2619 const struct VP9Decoder_s *const pbi)
2620{
2621 /* Clear resync flag if worker got a key frame or intra only frame.*/
2622 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2623 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2624 ctx->need_resync = 0;
2625}
2626#endif
2627
2628int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2629{
2630 struct VP9_Common_s *const cm = &pbi->common;
2631 int ret = -1;
2632
2633 if (pbi->ready_for_new_data == 1)
2634 return ret;
2635
2636 pbi->ready_for_new_data = 1;
2637
2638 /* no raw frame to show!!! */
2639 if (!cm->show_frame)
2640 return ret;
2641
2642 pbi->ready_for_new_data = 1;
2643
2644 *sd = *cm->frame_to_show;
2645 ret = 0;
2646
2647 return ret;
2648}
2649
2650int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2651 struct buff_s *mc_buf_i) {
2652 struct VP9_Common_s *cm = &pbi->common;
2653
2654 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2655 pbi->frame_count = 0;
2656 pbi->pic_count = 0;
2657 pbi->pre_stream_offset = 0;
2658 cm->buffer_pool = &pbi->vp9_buffer_pool;
2659 spin_lock_init(&cm->buffer_pool->lock);
2660 cm->prev_fb_idx = INVALID_IDX;
2661 cm->new_fb_idx = INVALID_IDX;
2662 pbi->used_4k_num = -1;
2663 cm->cur_fb_idx_mmu = INVALID_IDX;
2664 pr_debug
2665 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2666 cm->prev_fb_idx, cm->new_fb_idx);
2667 pbi->need_resync = 1;
2668 /* Initialize the references to not point to any frame buffers.*/
2669 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2670 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2671 cm->current_video_frame = 0;
2672 pbi->ready_for_new_data = 1;
2673
2674 /* private init */
2675 pbi->work_space_buf = buf_spec_i;
2676 if (!pbi->mmu_enable)
2677 pbi->mc_buf = mc_buf_i;
2678
2679 pbi->rpm_addr = NULL;
2680 pbi->lmem_addr = NULL;
2681
2682 pbi->use_cma_flag = 0;
2683 pbi->decode_idx = 0;
2684 pbi->slice_idx = 0;
2685 /*int m_uiMaxCUWidth = 1<<7;*/
2686 /*int m_uiMaxCUHeight = 1<<7;*/
2687 pbi->has_keyframe = 0;
2688 pbi->skip_flag = 0;
2689 pbi->wait_buf = 0;
2690 pbi->error_flag = 0;
2691
2692 pbi->pts_mode = PTS_NORMAL;
2693 pbi->last_pts = 0;
2694 pbi->last_lookup_pts = 0;
2695 pbi->last_pts_us64 = 0;
2696 pbi->last_lookup_pts_us64 = 0;
2697 pbi->shift_byte_count = 0;
2698 pbi->shift_byte_count_lo = 0;
2699 pbi->shift_byte_count_hi = 0;
2700 pbi->pts_mode_switching_count = 0;
2701 pbi->pts_mode_recovery_count = 0;
2702
2703 pbi->buf_num = 0;
2704 pbi->pic_num = 0;
2705
2706 return 0;
2707}
2708
2709
2710int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2711{
2712 struct VP9_Common_s *cm = &pbi->common;
2713 struct PIC_BUFFER_CONFIG_s sd;
2714
2715 if (pbi->postproc_done)
2716 return 0;
2717 pbi->postproc_done = 1;
2718 swap_frame_buffers(pbi);
2719 if (!cm->show_existing_frame) {
2720 cm->last_show_frame = cm->show_frame;
2721 cm->prev_frame = cm->cur_frame;
2722#if 0
2723 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2724 vp9_swap_current_and_last_seg_map(cm);
2725#endif
2726 }
2727 cm->last_width = cm->width;
2728 cm->last_height = cm->height;
2729 if (cm->show_frame)
2730 cm->current_video_frame++;
2731
2732 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2733 /*pr_info("Display frame index %d\r\n", sd.index);*/
2734 sd.stream_offset = pbi->pre_stream_offset;
2735 prepare_display_buf(pbi, &sd);
2736 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2737 }
2738
2739/* else
2740 * pr_info
2741 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2742 * pbi->ready_for_new_data, cm->show_frame);
2743 */
2744 return 0;
2745}
2746
2747/*struct VP9Decoder_s vp9_decoder;*/
2748union param_u vp9_param;
2749
2750/**************************************************
2751 *
2752 *VP9 buffer management end
2753 *
2754 ***************************************************
2755 */
2756
2757
2758#define HEVC_CM_BODY_START_ADDR 0x3626
2759#define HEVC_CM_BODY_LENGTH 0x3627
2760#define HEVC_CM_HEADER_LENGTH 0x3629
2761#define HEVC_CM_HEADER_OFFSET 0x362b
2762
2763#define LOSLESS_COMPRESS_MODE
2764
2765/*#define DECOMP_HEADR_SURGENT*/
2766#ifdef VP9_10B_NV21
2767static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2768#else
2769static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2770#endif
2771static u32 enable_mem_saving = 1;
2772static u32 force_w_h;
2773
2774static u32 force_fps;
2775
2776
2777const u32 vp9_version = 201602101;
2778static u32 debug;
2779static u32 radr;
2780static u32 rval;
2781static u32 pop_shorts;
2782static u32 dbg_cmd;
2783static u32 dbg_skip_decode_index;
2784static u32 endian = 0xff0;
2785#ifdef ERROR_HANDLE_DEBUG
2786static u32 dbg_nal_skip_flag;
2787 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2788static u32 dbg_nal_skip_count;
2789#endif
2790/*for debug*/
2791static u32 decode_pic_begin;
2792static uint slice_parse_begin;
2793static u32 step;
2794#ifdef MIX_STREAM_SUPPORT
2795static u32 buf_alloc_width = 4096;
2796static u32 buf_alloc_height = 2304;
2797static u32 vp9_max_pic_w = 4096;
2798static u32 vp9_max_pic_h = 2304;
2799
2800static u32 dynamic_buf_num_margin;
2801#else
2802static u32 buf_alloc_width;
2803static u32 buf_alloc_height;
2804static u32 dynamic_buf_num_margin = 7;
2805#endif
2806static u32 buf_alloc_depth = 10;
2807static u32 buf_alloc_size;
2808/*
2809 *bit[0]: 0,
2810 * bit[1]: 0, always release cma buffer when stop
2811 * bit[1]: 1, never release cma buffer when stop
2812 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2813 *do not release cma buffer is blackout is not 1
2814 *
2815 *bit[2]: 0, when start decoding, check current displayed buffer
2816 * (only for buffer decoded by vp9) if blackout is 0
2817 * 1, do not check current displayed buffer
2818 *
2819 *bit[3]: 1, if blackout is not 1, do not release current
2820 * displayed cma buffer always.
2821 */
2822/* set to 1 for fast play;
2823 * set to 8 for other case of "keep last frame"
2824 */
2825static u32 buffer_mode = 1;
2826/* buffer_mode_dbg: debug only*/
2827static u32 buffer_mode_dbg = 0xffff0000;
2828/**/
2829
2830/*
2831 *bit 0, 1: only display I picture;
2832 *bit 1, 1: only decode I picture;
2833 */
2834static u32 i_only_flag;
2835
2836static u32 low_latency_flag;
2837
2838static u32 no_head;
2839
2840static u32 max_decoding_time;
2841/*
2842 *error handling
2843 */
2844/*error_handle_policy:
2845 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2846 *1, skip error_skip_nal_count nals before error recovery;
2847 *bit 1 (valid only when bit0 == 1):
2848 *1, wait vps/sps/pps after error recovery;
2849 *bit 2 (valid only when bit0 == 0):
2850 *0, auto search after error recovery (vp9_recover() called);
2851 *1, manual search after error recovery
2852 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2853 *
2854 *bit 4: 0, set error_mark after reset/recover
2855 * 1, do not set error_mark after reset/recover
2856 *bit 5: 0, check total lcu for every picture
2857 * 1, do not check total lcu
2858 *
2859 */
2860
2861static u32 error_handle_policy;
2862/*static u32 parser_sei_enable = 1;*/
2863#define MAX_BUF_NUM_NORMAL 12
2864#define MAX_BUF_NUM_LESS 10
2865static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2866#define MAX_BUF_NUM_SAVE_BUF 8
2867
2868static u32 run_ready_min_buf_num = 2;
2869
2870
2871static DEFINE_MUTEX(vvp9_mutex);
2872#ifndef MULTI_INSTANCE_SUPPORT
2873static struct device *cma_dev;
2874#endif
2875
2876#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2877#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2878#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2879#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2880#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2881#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2882#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2883#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2884#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2885#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2886#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2887#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2888#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2889#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2890#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2891#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2892#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2893#ifdef MULTI_INSTANCE_SUPPORT
2894#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2895#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2896#else
2897#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2898#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2899#endif
2900#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2901#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2902
2903
2904/*
2905 *ucode parser/search control
2906 *bit 0: 0, header auto parse; 1, header manual parse
2907 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
2908 *bit [3:2]: valid when bit1==0;
2909 *0, auto skip nal before first vps/sps/pps/idr;
2910 *1, auto skip nal before first vps/sps/pps
2911 *2, auto skip nal before first vps/sps/pps,
2912 * and not decode until the first I slice (with slice address of 0)
2913 *
2914 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
2915 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
2916 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
2917 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
2918 *bit [17]: for NAL_SEI when bit0 is 0:
2919 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
2920 *bit [31:20]: used by ucode for debug purpose
2921 */
2922#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
2923 /*[31:24] chip feature
2924 31: 0, use MBOX1; 1, use MBOX0
2925 */
2926#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
2927#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
2928
2929#ifdef MULTI_INSTANCE_SUPPORT
2930#define RPM_BUF_SIZE (0x400 * 2)
2931#else
2932#define RPM_BUF_SIZE (0x80*2)
2933#endif
2934#define LMEM_BUF_SIZE (0x400 * 2)
2935
2936#define WORK_BUF_SPEC_NUM 3
2937static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
2938 {
2939 /* 8M bytes */
2940 .max_width = 1920,
2941 .max_height = 1088,
2942 .ipp = {
2943 /* IPP work space calculation :
2944 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
2945 */
2946 .buf_size = 0x4000,
2947 },
2948 .sao_abv = {
2949 .buf_size = 0x30000,
2950 },
2951 .sao_vb = {
2952 .buf_size = 0x30000,
2953 },
2954 .short_term_rps = {
2955 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
2956 * total 64x16x2 = 2048 bytes (0x800)
2957 */
2958 .buf_size = 0x800,
2959 },
2960 .vps = {
2961 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
2962 * total 0x0800 bytes
2963 */
2964 .buf_size = 0x800,
2965 },
2966 .sps = {
2967 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
2968 * total 0x0800 bytes
2969 */
2970 .buf_size = 0x800,
2971 },
2972 .pps = {
2973 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
2974 * total 0x2000 bytes
2975 */
2976 .buf_size = 0x2000,
2977 },
2978 .sao_up = {
2979 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
2980 * each has 16 bytes total 0x2800 bytes
2981 */
2982 .buf_size = 0x2800,
2983 },
2984 .swap_buf = {
2985 /* 256cyclex64bit = 2K bytes 0x800
2986 * (only 144 cycles valid)
2987 */
2988 .buf_size = 0x800,
2989 },
2990 .swap_buf2 = {
2991 .buf_size = 0x800,
2992 },
2993 .scalelut = {
2994 /* support up to 32 SCALELUT 1024x32 =
2995 * 32Kbytes (0x8000)
2996 */
2997 .buf_size = 0x8000,
2998 },
2999 .dblk_para = {
3000 /* DBLK -> Max 256(4096/16) LCU,
3001 *each para 1024bytes(total:0x40000),
3002 *data 1024bytes(total:0x40000)
3003 */
3004 .buf_size = 0x80000,
3005 },
3006 .dblk_data = {
3007 .buf_size = 0x80000,
3008 },
3009 .seg_map = {
3010 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3011 .buf_size = 0xd800,
3012 },
3013 .mmu_vbh = {
3014 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3015 },
3016#if 0
3017 .cm_header = {
3018 /*add one for keeper.*/
3019 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3020 (FRAME_BUFFERS + 1),
3021 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3022 },
3023#endif
3024 .mpred_above = {
3025 .buf_size = 0x10000, /* 2 * size of hevc*/
3026 },
3027#ifdef MV_USE_FIXED_BUF
3028 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3029 .buf_size = 0x40000 * FRAME_BUFFERS,
3030 },
3031#endif
3032 .rpm = {
3033 .buf_size = RPM_BUF_SIZE,
3034 },
3035 .lmem = {
3036 .buf_size = 0x400 * 2,
3037 }
3038 },
3039 {
3040 .max_width = 4096,
3041 .max_height = 2304,
3042 .ipp = {
3043 /* IPP work space calculation :
3044 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3045 */
3046 .buf_size = 0x4000,
3047 },
3048 .sao_abv = {
3049 .buf_size = 0x30000,
3050 },
3051 .sao_vb = {
3052 .buf_size = 0x30000,
3053 },
3054 .short_term_rps = {
3055 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3056 * total 64x16x2 = 2048 bytes (0x800)
3057 */
3058 .buf_size = 0x800,
3059 },
3060 .vps = {
3061 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3062 * total 0x0800 bytes
3063 */
3064 .buf_size = 0x800,
3065 },
3066 .sps = {
3067 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3068 * total 0x0800 bytes
3069 */
3070 .buf_size = 0x800,
3071 },
3072 .pps = {
3073 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3074 * total 0x2000 bytes
3075 */
3076 .buf_size = 0x2000,
3077 },
3078 .sao_up = {
3079 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3080 * each has 16 bytes total 0x2800 bytes
3081 */
3082 .buf_size = 0x2800,
3083 },
3084 .swap_buf = {
3085 /* 256cyclex64bit = 2K bytes 0x800
3086 * (only 144 cycles valid)
3087 */
3088 .buf_size = 0x800,
3089 },
3090 .swap_buf2 = {
3091 .buf_size = 0x800,
3092 },
3093 .scalelut = {
3094 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3095 * (0x8000)
3096 */
3097 .buf_size = 0x8000,
3098 },
3099 .dblk_para = {
3100 /* DBLK -> Max 256(4096/16) LCU,
3101 *each para 1024bytes(total:0x40000),
3102 *data 1024bytes(total:0x40000)
3103 */
3104 .buf_size = 0x80000,
3105 },
3106 .dblk_data = {
3107 .buf_size = 0x80000,
3108 },
3109 .seg_map = {
3110 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3111 .buf_size = 0xd800,
3112 },
3113 .mmu_vbh = {
3114 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3115 },
3116#if 0
3117 .cm_header = {
3118 /*add one for keeper.*/
3119 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3120 (FRAME_BUFFERS + 1),
3121 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3122 },
3123#endif
3124 .mpred_above = {
3125 .buf_size = 0x10000, /* 2 * size of hevc*/
3126 },
3127#ifdef MV_USE_FIXED_BUF
3128 .mpred_mv = {
3129 /* .buf_size = 0x100000*16,
3130 * //4k2k , 0x100000 per buffer
3131 */
3132 /* 4096x2304 , 0x120000 per buffer */
3133 .buf_size = 0x120000 * FRAME_BUFFERS,
3134 },
3135#endif
3136 .rpm = {
3137 .buf_size = RPM_BUF_SIZE,
3138 },
3139 .lmem = {
3140 .buf_size = 0x400 * 2,
3141 }
3142 },
3143 {
3144 .max_width = 4096*2,
3145 .max_height = 2304*2,
3146 .ipp = {
3147 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3148 .buf_size = 0x4000*2,
3149 },
3150 .sao_abv = {
3151 .buf_size = 0x30000*2,
3152 },
3153 .sao_vb = {
3154 .buf_size = 0x30000*2,
3155 },
3156 .short_term_rps = {
3157 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3158 .buf_size = 0x800,
3159 },
3160 .vps = {
3161 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3162 .buf_size = 0x800,
3163 },
3164 .sps = {
3165 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3166 .buf_size = 0x800,
3167 },
3168 .pps = {
3169 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3170 .buf_size = 0x2000,
3171 },
3172 .sao_up = {
3173 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3174 .buf_size = 0x2800*2,
3175 },
3176 .swap_buf = {
3177 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3178 .buf_size = 0x800,
3179 },
3180 .swap_buf2 = {
3181 .buf_size = 0x800,
3182 },
3183 .scalelut = {
3184 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3185 .buf_size = 0x8000*2,
3186 },
3187 .dblk_para = {
3188 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3189 .buf_size = 0x80000*2,
3190 },
3191 .dblk_data = {
3192 .buf_size = 0x80000*2,
3193 },
3194 .seg_map = {
3195 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3196 .buf_size = 0xd800*4,
3197 },
3198 .mmu_vbh = {
3199 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3200 },
3201#if 0
3202 .cm_header = {
3203 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3204 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3205 },
3206#endif
3207 .mpred_above = {
3208 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3209 },
3210#ifdef MV_USE_FIXED_BUF
3211 .mpred_mv = {
3212 //4k2k , 0x100000 per buffer */
3213 /* 4096x2304 , 0x120000 per buffer */
3214 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3215 },
3216#endif
3217 .rpm = {
3218 .buf_size = RPM_BUF_SIZE,
3219 },
3220 .lmem = {
3221 .buf_size = 0x400 * 2,
3222 }
3223 }
3224};
3225
3226
3227/*Losless compression body buffer size 4K per 64x32 (jt)*/
3228int compute_losless_comp_body_size(int width, int height,
3229 uint8_t is_bit_depth_10)
3230{
3231 int width_x64;
3232 int height_x32;
3233 int bsize;
3234
3235 width_x64 = width + 63;
3236 width_x64 >>= 6;
3237 height_x32 = height + 31;
3238 height_x32 >>= 5;
3239 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3240 if (debug & VP9_DEBUG_BUFMGR_MORE)
3241 pr_info("%s(%d,%d,%d)=>%d\n",
3242 __func__, width, height,
3243 is_bit_depth_10, bsize);
3244
3245 return bsize;
3246}
3247
3248/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3249static int compute_losless_comp_header_size(int width, int height)
3250{
3251 int width_x128;
3252 int height_x64;
3253 int hsize;
3254
3255 width_x128 = width + 127;
3256 width_x128 >>= 7;
3257 height_x64 = height + 63;
3258 height_x64 >>= 6;
3259
3260 hsize = 32 * width_x128 * height_x64;
3261 if (debug & VP9_DEBUG_BUFMGR_MORE)
3262 pr_info("%s(%d,%d)=>%d\n",
3263 __func__, width, height,
3264 hsize);
3265
3266 return hsize;
3267}
3268
3269static void init_buff_spec(struct VP9Decoder_s *pbi,
3270 struct BuffInfo_s *buf_spec)
3271{
3272 void *mem_start_virt;
3273
3274 buf_spec->ipp.buf_start = buf_spec->start_adr;
3275 buf_spec->sao_abv.buf_start =
3276 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3277
3278 buf_spec->sao_vb.buf_start =
3279 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3280 buf_spec->short_term_rps.buf_start =
3281 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3282 buf_spec->vps.buf_start =
3283 buf_spec->short_term_rps.buf_start +
3284 buf_spec->short_term_rps.buf_size;
3285 buf_spec->sps.buf_start =
3286 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3287 buf_spec->pps.buf_start =
3288 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3289 buf_spec->sao_up.buf_start =
3290 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3291 buf_spec->swap_buf.buf_start =
3292 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3293 buf_spec->swap_buf2.buf_start =
3294 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3295 buf_spec->scalelut.buf_start =
3296 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3297 buf_spec->dblk_para.buf_start =
3298 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3299 buf_spec->dblk_data.buf_start =
3300 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3301 buf_spec->seg_map.buf_start =
3302 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3303 if (pbi == NULL || pbi->mmu_enable) {
3304 buf_spec->mmu_vbh.buf_start =
3305 buf_spec->seg_map.buf_start +
3306 buf_spec->seg_map.buf_size;
3307 buf_spec->mpred_above.buf_start =
3308 buf_spec->mmu_vbh.buf_start +
3309 buf_spec->mmu_vbh.buf_size;
3310 } else {
3311 buf_spec->mpred_above.buf_start =
3312 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3313 }
3314#ifdef MV_USE_FIXED_BUF
3315 buf_spec->mpred_mv.buf_start =
3316 buf_spec->mpred_above.buf_start +
3317 buf_spec->mpred_above.buf_size;
3318
3319 buf_spec->rpm.buf_start =
3320 buf_spec->mpred_mv.buf_start +
3321 buf_spec->mpred_mv.buf_size;
3322#else
3323 buf_spec->rpm.buf_start =
3324 buf_spec->mpred_above.buf_start +
3325 buf_spec->mpred_above.buf_size;
3326
3327#endif
3328 buf_spec->lmem.buf_start =
3329 buf_spec->rpm.buf_start +
3330 buf_spec->rpm.buf_size;
3331 buf_spec->end_adr =
3332 buf_spec->lmem.buf_start +
3333 buf_spec->lmem.buf_size;
3334
3335 if (!pbi)
3336 return;
3337
3338 if (!vdec_secure(hw_to_vdec(pbi))) {
3339 mem_start_virt =
3340 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3341 if (mem_start_virt) {
3342 memset(mem_start_virt, 0,
3343 buf_spec->dblk_para.buf_size);
3344 codec_mm_dma_flush(mem_start_virt,
3345 buf_spec->dblk_para.buf_size,
3346 DMA_TO_DEVICE);
3347 } else {
3348 mem_start_virt = codec_mm_vmap(
3349 buf_spec->dblk_para.buf_start,
3350 buf_spec->dblk_para.buf_size);
3351 if (mem_start_virt) {
3352 memset(mem_start_virt, 0,
3353 buf_spec->dblk_para.buf_size);
3354 codec_mm_dma_flush(mem_start_virt,
3355 buf_spec->dblk_para.buf_size,
3356 DMA_TO_DEVICE);
3357 codec_mm_unmap_phyaddr(mem_start_virt);
3358 } else {
3359 /*not virt for tvp playing,
3360 may need clear on ucode.*/
3361 pr_err("mem_start_virt failed\n");
3362 }
3363 }
3364 }
3365
3366 if (debug) {
3367 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3368 buf_spec->start_adr, buf_spec->end_adr,
3369 buf_spec->end_adr - buf_spec->start_adr);
3370 }
3371
3372 if (debug) {
3373 pr_info("ipp.buf_start :%x\n",
3374 buf_spec->ipp.buf_start);
3375 pr_info("sao_abv.buf_start :%x\n",
3376 buf_spec->sao_abv.buf_start);
3377 pr_info("sao_vb.buf_start :%x\n",
3378 buf_spec->sao_vb.buf_start);
3379 pr_info("short_term_rps.buf_start :%x\n",
3380 buf_spec->short_term_rps.buf_start);
3381 pr_info("vps.buf_start :%x\n",
3382 buf_spec->vps.buf_start);
3383 pr_info("sps.buf_start :%x\n",
3384 buf_spec->sps.buf_start);
3385 pr_info("pps.buf_start :%x\n",
3386 buf_spec->pps.buf_start);
3387 pr_info("sao_up.buf_start :%x\n",
3388 buf_spec->sao_up.buf_start);
3389 pr_info("swap_buf.buf_start :%x\n",
3390 buf_spec->swap_buf.buf_start);
3391 pr_info("swap_buf2.buf_start :%x\n",
3392 buf_spec->swap_buf2.buf_start);
3393 pr_info("scalelut.buf_start :%x\n",
3394 buf_spec->scalelut.buf_start);
3395 pr_info("dblk_para.buf_start :%x\n",
3396 buf_spec->dblk_para.buf_start);
3397 pr_info("dblk_data.buf_start :%x\n",
3398 buf_spec->dblk_data.buf_start);
3399 pr_info("seg_map.buf_start :%x\n",
3400 buf_spec->seg_map.buf_start);
3401 if (pbi->mmu_enable) {
3402 pr_info("mmu_vbh.buf_start :%x\n",
3403 buf_spec->mmu_vbh.buf_start);
3404 }
3405 pr_info("mpred_above.buf_start :%x\n",
3406 buf_spec->mpred_above.buf_start);
3407#ifdef MV_USE_FIXED_BUF
3408 pr_info("mpred_mv.buf_start :%x\n",
3409 buf_spec->mpred_mv.buf_start);
3410#endif
3411 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3412 pr_info("rpm.buf_start :%x\n",
3413 buf_spec->rpm.buf_start);
3414 }
3415 }
3416}
3417
3418/* cache_util.c */
3419#define THODIYIL_MCRCC_CANVAS_ALGX 4
3420
3421static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3422
3423static void mcrcc_perfcount_reset(void)
3424{
3425 if (debug & VP9_DEBUG_CACHE)
3426 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3427 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3428 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3429 return;
3430}
3431
3432static unsigned raw_mcr_cnt_total_prev;
3433static unsigned hit_mcr_0_cnt_total_prev;
3434static unsigned hit_mcr_1_cnt_total_prev;
3435static unsigned byp_mcr_cnt_nchcanv_total_prev;
3436static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3437
3438static void mcrcc_get_hitrate(unsigned reset_pre)
3439{
3440 unsigned delta_hit_mcr_0_cnt;
3441 unsigned delta_hit_mcr_1_cnt;
3442 unsigned delta_raw_mcr_cnt;
3443 unsigned delta_mcr_cnt_nchcanv;
3444 unsigned delta_mcr_cnt_nchoutwin;
3445
3446 unsigned tmp;
3447 unsigned raw_mcr_cnt;
3448 unsigned hit_mcr_cnt;
3449 unsigned byp_mcr_cnt_nchoutwin;
3450 unsigned byp_mcr_cnt_nchcanv;
3451 int hitrate;
3452 if (reset_pre) {
3453 raw_mcr_cnt_total_prev = 0;
3454 hit_mcr_0_cnt_total_prev = 0;
3455 hit_mcr_1_cnt_total_prev = 0;
3456 byp_mcr_cnt_nchcanv_total_prev = 0;
3457 byp_mcr_cnt_nchoutwin_total_prev = 0;
3458 }
3459 if (debug & VP9_DEBUG_CACHE)
3460 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3461 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3462 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3463 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3464 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3465 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3466 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3467 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3468 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3469
3470 if (debug & VP9_DEBUG_CACHE)
3471 pr_info("raw_mcr_cnt_total: %d\n",
3472 raw_mcr_cnt);
3473 if (debug & VP9_DEBUG_CACHE)
3474 pr_info("hit_mcr_cnt_total: %d\n",
3475 hit_mcr_cnt);
3476 if (debug & VP9_DEBUG_CACHE)
3477 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3478 byp_mcr_cnt_nchoutwin);
3479 if (debug & VP9_DEBUG_CACHE)
3480 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3481 byp_mcr_cnt_nchcanv);
3482
3483 delta_raw_mcr_cnt = raw_mcr_cnt -
3484 raw_mcr_cnt_total_prev;
3485 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3486 byp_mcr_cnt_nchcanv_total_prev;
3487 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3488 byp_mcr_cnt_nchoutwin_total_prev;
3489 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3490 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3491 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3492
3493 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3494 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3495 if (debug & VP9_DEBUG_CACHE)
3496 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3497 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3498 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3499 if (debug & VP9_DEBUG_CACHE)
3500 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3501 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3502 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3503 if (debug & VP9_DEBUG_CACHE)
3504 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3505 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3506 hit_mcr_0_cnt_total_prev = tmp;
3507 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3508 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3509 if (debug & VP9_DEBUG_CACHE)
3510 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3511 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3512 hit_mcr_1_cnt_total_prev = tmp;
3513
3514 if (delta_raw_mcr_cnt != 0) {
3515 hitrate = 100 * delta_hit_mcr_0_cnt
3516 / delta_raw_mcr_cnt;
3517 if (debug & VP9_DEBUG_CACHE)
3518 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3519 hitrate = 100 * delta_hit_mcr_1_cnt
3520 / delta_raw_mcr_cnt;
3521 if (debug & VP9_DEBUG_CACHE)
3522 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3523 hitrate = 100 * delta_mcr_cnt_nchcanv
3524 / delta_raw_mcr_cnt;
3525 if (debug & VP9_DEBUG_CACHE)
3526 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3527 hitrate = 100 * delta_mcr_cnt_nchoutwin
3528 / delta_raw_mcr_cnt;
3529 if (debug & VP9_DEBUG_CACHE)
3530 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3531 }
3532
3533
3534 if (raw_mcr_cnt != 0) {
3535 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3536 if (debug & VP9_DEBUG_CACHE)
3537 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3538 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3539 / raw_mcr_cnt;
3540 if (debug & VP9_DEBUG_CACHE)
3541 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3542 } else {
3543 if (debug & VP9_DEBUG_CACHE)
3544 pr_info("MCRCC_HIT_RATE : na\n");
3545 if (debug & VP9_DEBUG_CACHE)
3546 pr_info("MCRCC_BYP_RATE : na\n");
3547 }
3548 return;
3549}
3550
3551
3552static void decomp_perfcount_reset(void)
3553{
3554 if (debug & VP9_DEBUG_CACHE)
3555 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3556 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3557 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3558 return;
3559}
3560
3561static void decomp_get_hitrate(void)
3562{
3563 unsigned raw_mcr_cnt;
3564 unsigned hit_mcr_cnt;
3565 int hitrate;
3566 if (debug & VP9_DEBUG_CACHE)
3567 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3568 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3569 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3570 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3571 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3572
3573 if (debug & VP9_DEBUG_CACHE)
3574 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3575 if (debug & VP9_DEBUG_CACHE)
3576 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3577
3578 if (raw_mcr_cnt != 0) {
3579 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3580 if (debug & VP9_DEBUG_CACHE)
3581 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3582 } else {
3583 if (debug & VP9_DEBUG_CACHE)
3584 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3585 }
3586 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3587 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3588 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3589 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3590
3591 if (debug & VP9_DEBUG_CACHE)
3592 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3593 if (debug & VP9_DEBUG_CACHE)
3594 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3595
3596 if (raw_mcr_cnt != 0) {
3597 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3598 if (debug & VP9_DEBUG_CACHE)
3599 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3600 } else {
3601 if (debug & VP9_DEBUG_CACHE)
3602 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3603 }
3604 return;
3605}
3606
3607static void decomp_get_comprate(void)
3608{
3609 unsigned raw_ucomp_cnt;
3610 unsigned fast_comp_cnt;
3611 unsigned slow_comp_cnt;
3612 int comprate;
3613
3614 if (debug & VP9_DEBUG_CACHE)
3615 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3616 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3617 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3618 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3619 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3620 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3621 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3622
3623 if (debug & VP9_DEBUG_CACHE)
3624 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3625 if (debug & VP9_DEBUG_CACHE)
3626 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3627 if (debug & VP9_DEBUG_CACHE)
3628 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3629
3630 if (raw_ucomp_cnt != 0) {
3631 comprate = (fast_comp_cnt + slow_comp_cnt)
3632 * 100 / raw_ucomp_cnt;
3633 if (debug & VP9_DEBUG_CACHE)
3634 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3635 } else {
3636 if (debug & VP9_DEBUG_CACHE)
3637 pr_info("DECOMP_COMP_RATIO : na\n");
3638 }
3639 return;
3640}
3641/* cache_util.c end */
3642
3643/*====================================================
3644 *========================================================================
3645 *vp9_prob define
3646 *========================================================================
3647 */
3648#define VP9_PARTITION_START 0
3649#define VP9_PARTITION_SIZE_STEP (3 * 4)
3650#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3651#define VP9_PARTITION_KEY_START 0
3652#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3653#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3654#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3655#define VP9_SKIP_SIZE 4 /* only use 3*/
3656#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3657#define VP9_TX_MODE_8_0_OFFSET 0
3658#define VP9_TX_MODE_8_1_OFFSET 1
3659#define VP9_TX_MODE_16_0_OFFSET 2
3660#define VP9_TX_MODE_16_1_OFFSET 4
3661#define VP9_TX_MODE_32_0_OFFSET 6
3662#define VP9_TX_MODE_32_1_OFFSET 9
3663#define VP9_TX_MODE_SIZE 12
3664#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3665#define VP9_COEF_BAND_0_OFFSET 0
3666#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3667#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3668#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3669#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3670#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3671#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3672#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3673#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3674#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3675#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3676#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3677#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3678#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3679#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3680#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3681#define VP9_INTERP_SIZE 8
3682#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3683#define VP9_INTRA_INTER_SIZE 4
3684#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3685#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3686#define VP9_COMP_INTER_START \
3687 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3688#define VP9_COMP_INTER_SIZE 5
3689#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3690#define VP9_COMP_REF_SIZE 5
3691#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3692#define VP9_SINGLE_REF_SIZE 10
3693#define VP9_REF_MODE_START VP9_COMP_INTER_START
3694#define VP9_REF_MODE_SIZE \
3695 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3696#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3697#define VP9_IF_Y_MODE_SIZE 36
3698#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3699#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3700#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3701#define VP9_MV_JOINTS_SIZE 3
3702#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3703#define VP9_MV_SIGN_0_SIZE 1
3704#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3705#define VP9_MV_CLASSES_0_SIZE 10
3706#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3707#define VP9_MV_CLASS0_0_SIZE 1
3708#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3709#define VP9_MV_BITS_0_SIZE 10
3710#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3711#define VP9_MV_SIGN_1_SIZE 1
3712#define VP9_MV_CLASSES_1_START \
3713 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3714#define VP9_MV_CLASSES_1_SIZE 10
3715#define VP9_MV_CLASS0_1_START \
3716 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3717#define VP9_MV_CLASS0_1_SIZE 1
3718#define VP9_MV_BITS_1_START \
3719 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3720#define VP9_MV_BITS_1_SIZE 10
3721#define VP9_MV_CLASS0_FP_0_START \
3722 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3723#define VP9_MV_CLASS0_FP_0_SIZE 9
3724#define VP9_MV_CLASS0_FP_1_START \
3725 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3726#define VP9_MV_CLASS0_FP_1_SIZE 9
3727#define VP9_MV_CLASS0_HP_0_START \
3728 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3729#define VP9_MV_CLASS0_HP_0_SIZE 2
3730#define VP9_MV_CLASS0_HP_1_START \
3731 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3732#define VP9_MV_CLASS0_HP_1_SIZE 2
3733#define VP9_MV_START VP9_MV_JOINTS_START
3734#define VP9_MV_SIZE 72 /*only use 69*/
3735
3736#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3737
3738
3739/*========================================================================
3740 * vp9_count_mem define
3741 *========================================================================
3742 */
3743#define VP9_COEF_COUNT_START 0
3744#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3745#define VP9_COEF_COUNT_BAND_1_OFFSET \
3746 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3747#define VP9_COEF_COUNT_BAND_2_OFFSET \
3748 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3749#define VP9_COEF_COUNT_BAND_3_OFFSET \
3750 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3751#define VP9_COEF_COUNT_BAND_4_OFFSET \
3752 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3753#define VP9_COEF_COUNT_BAND_5_OFFSET \
3754 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3755#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3756#define VP9_COEF_COUNT_4X4_START \
3757 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3758#define VP9_COEF_COUNT_8X8_START \
3759 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3760#define VP9_COEF_COUNT_16X16_START \
3761 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3762#define VP9_COEF_COUNT_32X32_START \
3763 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3764#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3765#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3766
3767#define VP9_INTRA_INTER_COUNT_START \
3768 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3769#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3770#define VP9_COMP_INTER_COUNT_START \
3771 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3772#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3773#define VP9_COMP_REF_COUNT_START \
3774 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3775#define VP9_COMP_REF_COUNT_SIZE (5*2)
3776#define VP9_SINGLE_REF_COUNT_START \
3777 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3778#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3779#define VP9_TX_MODE_COUNT_START \
3780 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3781#define VP9_TX_MODE_COUNT_SIZE (12*2)
3782#define VP9_SKIP_COUNT_START \
3783 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3784#define VP9_SKIP_COUNT_SIZE (3*2)
3785#define VP9_MV_SIGN_0_COUNT_START \
3786 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3787#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3788#define VP9_MV_SIGN_1_COUNT_START \
3789 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3790#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3791#define VP9_MV_BITS_0_COUNT_START \
3792 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3793#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3794#define VP9_MV_BITS_1_COUNT_START \
3795 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3796#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3797#define VP9_MV_CLASS0_HP_0_COUNT_START \
3798 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3799#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3800#define VP9_MV_CLASS0_HP_1_COUNT_START \
3801 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3802#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3803/* Start merge_tree*/
3804#define VP9_INTER_MODE_COUNT_START \
3805 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3806#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3807#define VP9_IF_Y_MODE_COUNT_START \
3808 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3809#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3810#define VP9_IF_UV_MODE_COUNT_START \
3811 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3812#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3813#define VP9_PARTITION_P_COUNT_START \
3814 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3815#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3816#define VP9_INTERP_COUNT_START \
3817 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3818#define VP9_INTERP_COUNT_SIZE (4*3)
3819#define VP9_MV_JOINTS_COUNT_START \
3820 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3821#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3822#define VP9_MV_CLASSES_0_COUNT_START \
3823 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3824#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3825#define VP9_MV_CLASS0_0_COUNT_START \
3826 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3827#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3828#define VP9_MV_CLASSES_1_COUNT_START \
3829 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3830#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3831#define VP9_MV_CLASS0_1_COUNT_START \
3832 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3833#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3834#define VP9_MV_CLASS0_FP_0_COUNT_START \
3835 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3836#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3837#define VP9_MV_CLASS0_FP_1_COUNT_START \
3838 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3839#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3840
3841
3842#define DC_PRED 0 /* Average of above and left pixels*/
3843#define V_PRED 1 /* Vertical*/
3844#define H_PRED 2 /* Horizontal*/
3845#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3846#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3847#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3848#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3849#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3850#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3851#define TM_PRED 9 /*True-motion*/
3852
3853int clip_prob(int p)
3854{
3855 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3856}
3857
3858#define ROUND_POWER_OF_TWO(value, n) \
3859 (((value) + (1 << ((n) - 1))) >> (n))
3860
3861#define MODE_MV_COUNT_SAT 20
3862static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3863 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3864 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3865};
3866
3867void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3868 int coef_node_start, int tree_left, int tree_right, int tree_i,
3869 int node) {
3870
3871 int prob_32, prob_res, prob_shift;
3872 int pre_prob, new_prob;
3873 int den, m_count, get_prob, factor;
3874
3875 prob_32 = prev_prob[coef_node_start / 4 * 2];
3876 prob_res = coef_node_start & 3;
3877 prob_shift = prob_res * 8;
3878 pre_prob = (prob_32 >> prob_shift) & 0xff;
3879
3880 den = tree_left + tree_right;
3881
3882 if (den == 0)
3883 new_prob = pre_prob;
3884 else {
3885 m_count = (den < MODE_MV_COUNT_SAT) ?
3886 den : MODE_MV_COUNT_SAT;
3887 get_prob = clip_prob(
3888 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3889 den));
3890 /*weighted_prob*/
3891 factor = count_to_update_factor[m_count];
3892 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3893 + get_prob * factor, 8);
3894 }
3895 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3896 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
3897
3898 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3899 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3900 *cur_prob[coef_node_start/4*2]);
3901 */
3902}
3903
3904
3905/*void adapt_coef_probs(void)*/
3906void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3907 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3908{
3909 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3910 *unsigned int prev_prob[496*2];
3911 *unsigned int cur_prob[496*2];
3912 *0x300 * 128bits = 0x3000 (32K Bytes)
3913 *unsigned int count[0x300*4];
3914 */
3915
3916 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
3917 int plane, coef_plane_start, coef_count_plane_start;
3918 int type, coef_type_start, coef_count_type_start;
3919 int band, coef_band_start, coef_count_band_start;
3920 int cxt_num;
3921 int cxt, coef_cxt_start, coef_count_cxt_start;
3922 int node, coef_node_start, coef_count_node_start;
3923
3924 int tree_i, tree_left, tree_right;
3925 int mvd_i;
3926
3927 int count_sat = 24;
3928 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
3929 *use 128
3930 */
3931 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
3932 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
3933 int update_factor = cur_kf ? 112 :
3934 prev_kf ? 128 : 112;
3935
3936 int prob_32;
3937 int prob_res;
3938 int prob_shift;
3939 int pre_prob;
3940
3941 int num, den;
3942 int get_prob;
3943 int m_count;
3944 int factor;
3945
3946 int new_prob;
3947
3948 if (debug & VP9_DEBUG_MERGE)
3949 pr_info
3950 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
3951 pre_fc, prev_kf, cur_kf);
3952
3953 /*adapt_coef_probs*/
3954 for (tx_size = 0; tx_size < 4; tx_size++) {
3955 coef_tx_size_start = VP9_COEF_START
3956 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
3957 coef_count_tx_size_start = VP9_COEF_COUNT_START
3958 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
3959 coef_plane_start = coef_tx_size_start;
3960 coef_count_plane_start = coef_count_tx_size_start;
3961 for (plane = 0; plane < 2; plane++) {
3962 coef_type_start = coef_plane_start;
3963 coef_count_type_start = coef_count_plane_start;
3964 for (type = 0; type < 2; type++) {
3965 coef_band_start = coef_type_start;
3966 coef_count_band_start = coef_count_type_start;
3967 for (band = 0; band < 6; band++) {
3968 if (band == 0)
3969 cxt_num = 3;
3970 else
3971 cxt_num = 6;
3972 coef_cxt_start = coef_band_start;
3973 coef_count_cxt_start =
3974 coef_count_band_start;
3975 for (cxt = 0; cxt < cxt_num; cxt++) {
3976 const int n0 =
3977 count[coef_count_cxt_start];
3978 const int n1 =
3979 count[coef_count_cxt_start + 1];
3980 const int n2 =
3981 count[coef_count_cxt_start + 2];
3982 const int neob =
3983 count[coef_count_cxt_start + 3];
3984 const int nneob =
3985 count[coef_count_cxt_start + 4];
3986 const unsigned int
3987 branch_ct[3][2] = {
3988 { neob, nneob },
3989 { n0, n1 + n2 },
3990 { n1, n2 }
3991 };
3992 coef_node_start =
3993 coef_cxt_start;
3994 for
3995 (node = 0; node < 3; node++) {
3996 prob_32 =
3997 prev_prob[
3998 coef_node_start
3999 / 4 * 2];
4000 prob_res =
4001 coef_node_start & 3;
4002 prob_shift =
4003 prob_res * 8;
4004 pre_prob =
4005 (prob_32 >> prob_shift)
4006 & 0xff;
4007
4008 /*get_binary_prob*/
4009 num =
4010 branch_ct[node][0];
4011 den =
4012 branch_ct[node][0] +
4013 branch_ct[node][1];
4014 m_count = (den <
4015 count_sat)
4016 ? den : count_sat;
4017
4018 get_prob =
4019 (den == 0) ? 128u :
4020 clip_prob(
4021 div_r32(((int64_t)
4022 num * 256
4023 + (den >> 1)),
4024 den));
4025
4026 factor =
4027 update_factor * m_count
4028 / count_sat;
4029 new_prob =
4030 ROUND_POWER_OF_TWO
4031 (pre_prob *
4032 (256 - factor) +
4033 get_prob * factor, 8);
4034
4035 cur_prob[coef_node_start
4036 / 4 * 2] =
4037 (cur_prob
4038 [coef_node_start
4039 / 4 * 2] & (~(0xff <<
4040 prob_shift))) |
4041 (new_prob <<
4042 prob_shift);
4043
4044 coef_node_start += 1;
4045 }
4046
4047 coef_cxt_start =
4048 coef_cxt_start + 3;
4049 coef_count_cxt_start =
4050 coef_count_cxt_start
4051 + 5;
4052 }
4053 if (band == 0) {
4054 coef_band_start += 10;
4055 coef_count_band_start += 15;
4056 } else {
4057 coef_band_start += 18;
4058 coef_count_band_start += 30;
4059 }
4060 }
4061 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4062 coef_count_type_start +=
4063 VP9_COEF_COUNT_SIZE_ONE_SET;
4064 }
4065 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4066 coef_count_plane_start +=
4067 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4068 }
4069 }
4070
4071 if (cur_kf == 0) {
4072 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4073 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4074 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4075 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4076
4077 if (coef_count_node_start ==
4078 VP9_INTRA_INTER_COUNT_START) {
4079 if (debug & VP9_DEBUG_MERGE)
4080 pr_info(" # merge_intra_inter_prob\n");
4081 coef_node_start = VP9_INTRA_INTER_START;
4082 } else if (coef_count_node_start ==
4083 VP9_COMP_INTER_COUNT_START) {
4084 if (debug & VP9_DEBUG_MERGE)
4085 pr_info(" # merge_comp_inter_prob\n");
4086 coef_node_start = VP9_COMP_INTER_START;
4087 }
4088 /*
4089 *else if (coef_count_node_start ==
4090 * VP9_COMP_REF_COUNT_START) {
4091 * pr_info(" # merge_comp_inter_prob\n");
4092 * coef_node_start = VP9_COMP_REF_START;
4093 *}
4094 *else if (coef_count_node_start ==
4095 * VP9_SINGLE_REF_COUNT_START) {
4096 * pr_info(" # merge_comp_inter_prob\n");
4097 * coef_node_start = VP9_SINGLE_REF_START;
4098 *}
4099 */
4100 else if (coef_count_node_start ==
4101 VP9_TX_MODE_COUNT_START) {
4102 if (debug & VP9_DEBUG_MERGE)
4103 pr_info(" # merge_tx_mode_probs\n");
4104 coef_node_start = VP9_TX_MODE_START;
4105 } else if (coef_count_node_start ==
4106 VP9_SKIP_COUNT_START) {
4107 if (debug & VP9_DEBUG_MERGE)
4108 pr_info(" # merge_skip_probs\n");
4109 coef_node_start = VP9_SKIP_START;
4110 } else if (coef_count_node_start ==
4111 VP9_MV_SIGN_0_COUNT_START) {
4112 if (debug & VP9_DEBUG_MERGE)
4113 pr_info(" # merge_sign_0\n");
4114 coef_node_start = VP9_MV_SIGN_0_START;
4115 } else if (coef_count_node_start ==
4116 VP9_MV_SIGN_1_COUNT_START) {
4117 if (debug & VP9_DEBUG_MERGE)
4118 pr_info(" # merge_sign_1\n");
4119 coef_node_start = VP9_MV_SIGN_1_START;
4120 } else if (coef_count_node_start ==
4121 VP9_MV_BITS_0_COUNT_START) {
4122 if (debug & VP9_DEBUG_MERGE)
4123 pr_info(" # merge_bits_0\n");
4124 coef_node_start = VP9_MV_BITS_0_START;
4125 } else if (coef_count_node_start ==
4126 VP9_MV_BITS_1_COUNT_START) {
4127 if (debug & VP9_DEBUG_MERGE)
4128 pr_info(" # merge_bits_1\n");
4129 coef_node_start = VP9_MV_BITS_1_START;
4130 } else if (coef_count_node_start ==
4131 VP9_MV_CLASS0_HP_0_COUNT_START) {
4132 if (debug & VP9_DEBUG_MERGE)
4133 pr_info(" # merge_class0_hp\n");
4134 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4135 }
4136
4137
4138 den = count[coef_count_node_start] +
4139 count[coef_count_node_start + 1];
4140
4141 prob_32 = prev_prob[coef_node_start / 4 * 2];
4142 prob_res = coef_node_start & 3;
4143 prob_shift = prob_res * 8;
4144 pre_prob = (prob_32 >> prob_shift) & 0xff;
4145
4146 if (den == 0)
4147 new_prob = pre_prob;
4148 else {
4149 m_count = (den < MODE_MV_COUNT_SAT) ?
4150 den : MODE_MV_COUNT_SAT;
4151 get_prob =
4152 clip_prob(
4153 div_r32(((int64_t)count[coef_count_node_start]
4154 * 256 + (den >> 1)),
4155 den));
4156 /*weighted_prob*/
4157 factor = count_to_update_factor[m_count];
4158 new_prob =
4159 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4160 + get_prob * factor, 8);
4161 }
4162 cur_prob[coef_node_start / 4 * 2] =
4163 (cur_prob[coef_node_start / 4 * 2] &
4164 (~(0xff << prob_shift)))
4165 | (new_prob << prob_shift);
4166
4167 coef_node_start = coef_node_start + 1;
4168 }
4169 if (debug & VP9_DEBUG_MERGE)
4170 pr_info(" # merge_vp9_inter_mode_tree\n");
4171 coef_node_start = VP9_INTER_MODE_START;
4172 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4173 for (tree_i = 0; tree_i < 7; tree_i++) {
4174 for (node = 0; node < 3; node++) {
4175 switch (node) {
4176 case 2:
4177 tree_left =
4178 count[coef_count_node_start + 1];
4179 tree_right =
4180 count[coef_count_node_start + 3];
4181 break;
4182 case 1:
4183 tree_left =
4184 count[coef_count_node_start + 0];
4185 tree_right =
4186 count[coef_count_node_start + 1]
4187 + count[coef_count_node_start + 3];
4188 break;
4189 default:
4190 tree_left =
4191 count[coef_count_node_start + 2];
4192 tree_right =
4193 count[coef_count_node_start + 0]
4194 + count[coef_count_node_start + 1]
4195 + count[coef_count_node_start + 3];
4196 break;
4197
4198 }
4199
4200 vp9_tree_merge_probs(prev_prob, cur_prob,
4201 coef_node_start, tree_left, tree_right,
4202 tree_i, node);
4203
4204 coef_node_start = coef_node_start + 1;
4205 }
4206 coef_count_node_start = coef_count_node_start + 4;
4207 }
4208 if (debug & VP9_DEBUG_MERGE)
4209 pr_info(" # merge_vp9_intra_mode_tree\n");
4210 coef_node_start = VP9_IF_Y_MODE_START;
4211 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4212 for (tree_i = 0; tree_i < 14; tree_i++) {
4213 for (node = 0; node < 9; node++) {
4214 switch (node) {
4215 case 8:
4216 tree_left =
4217 count[coef_count_node_start+D153_PRED];
4218 tree_right =
4219 count[coef_count_node_start+D207_PRED];
4220 break;
4221 case 7:
4222 tree_left =
4223 count[coef_count_node_start+D63_PRED];
4224 tree_right =
4225 count[coef_count_node_start+D207_PRED] +
4226 count[coef_count_node_start+D153_PRED];
4227 break;
4228 case 6:
4229 tree_left =
4230 count[coef_count_node_start + D45_PRED];
4231 tree_right =
4232 count[coef_count_node_start+D207_PRED] +
4233 count[coef_count_node_start+D153_PRED] +
4234 count[coef_count_node_start+D63_PRED];
4235 break;
4236 case 5:
4237 tree_left =
4238 count[coef_count_node_start+D135_PRED];
4239 tree_right =
4240 count[coef_count_node_start+D117_PRED];
4241 break;
4242 case 4:
4243 tree_left =
4244 count[coef_count_node_start+H_PRED];
4245 tree_right =
4246 count[coef_count_node_start+D117_PRED] +
4247 count[coef_count_node_start+D135_PRED];
4248 break;
4249 case 3:
4250 tree_left =
4251 count[coef_count_node_start+H_PRED] +
4252 count[coef_count_node_start+D117_PRED] +
4253 count[coef_count_node_start+D135_PRED];
4254 tree_right =
4255 count[coef_count_node_start+D45_PRED] +
4256 count[coef_count_node_start+D207_PRED] +
4257 count[coef_count_node_start+D153_PRED] +
4258 count[coef_count_node_start+D63_PRED];
4259 break;
4260 case 2:
4261 tree_left =
4262 count[coef_count_node_start+V_PRED];
4263 tree_right =
4264 count[coef_count_node_start+H_PRED] +
4265 count[coef_count_node_start+D117_PRED] +
4266 count[coef_count_node_start+D135_PRED] +
4267 count[coef_count_node_start+D45_PRED] +
4268 count[coef_count_node_start+D207_PRED] +
4269 count[coef_count_node_start+D153_PRED] +
4270 count[coef_count_node_start+D63_PRED];
4271 break;
4272 case 1:
4273 tree_left =
4274 count[coef_count_node_start+TM_PRED];
4275 tree_right =
4276 count[coef_count_node_start+V_PRED] +
4277 count[coef_count_node_start+H_PRED] +
4278 count[coef_count_node_start+D117_PRED] +
4279 count[coef_count_node_start+D135_PRED] +
4280 count[coef_count_node_start+D45_PRED] +
4281 count[coef_count_node_start+D207_PRED] +
4282 count[coef_count_node_start+D153_PRED] +
4283 count[coef_count_node_start+D63_PRED];
4284 break;
4285 default:
4286 tree_left =
4287 count[coef_count_node_start+DC_PRED];
4288 tree_right =
4289 count[coef_count_node_start+TM_PRED] +
4290 count[coef_count_node_start+V_PRED] +
4291 count[coef_count_node_start+H_PRED] +
4292 count[coef_count_node_start+D117_PRED] +
4293 count[coef_count_node_start+D135_PRED] +
4294 count[coef_count_node_start+D45_PRED] +
4295 count[coef_count_node_start+D207_PRED] +
4296 count[coef_count_node_start+D153_PRED] +
4297 count[coef_count_node_start+D63_PRED];
4298 break;
4299
4300 }
4301
4302 vp9_tree_merge_probs(prev_prob, cur_prob,
4303 coef_node_start, tree_left, tree_right,
4304 tree_i, node);
4305
4306 coef_node_start = coef_node_start + 1;
4307 }
4308 coef_count_node_start = coef_count_node_start + 10;
4309 }
4310
4311 if (debug & VP9_DEBUG_MERGE)
4312 pr_info(" # merge_vp9_partition_tree\n");
4313 coef_node_start = VP9_PARTITION_P_START;
4314 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4315 for (tree_i = 0; tree_i < 16; tree_i++) {
4316 for (node = 0; node < 3; node++) {
4317 switch (node) {
4318 case 2:
4319 tree_left =
4320 count[coef_count_node_start + 2];
4321 tree_right =
4322 count[coef_count_node_start + 3];
4323 break;
4324 case 1:
4325 tree_left =
4326 count[coef_count_node_start + 1];
4327 tree_right =
4328 count[coef_count_node_start + 2] +
4329 count[coef_count_node_start + 3];
4330 break;
4331 default:
4332 tree_left =
4333 count[coef_count_node_start + 0];
4334 tree_right =
4335 count[coef_count_node_start + 1] +
4336 count[coef_count_node_start + 2] +
4337 count[coef_count_node_start + 3];
4338 break;
4339
4340 }
4341
4342 vp9_tree_merge_probs(prev_prob, cur_prob,
4343 coef_node_start,
4344 tree_left, tree_right, tree_i, node);
4345
4346 coef_node_start = coef_node_start + 1;
4347 }
4348 coef_count_node_start = coef_count_node_start + 4;
4349 }
4350
4351 if (debug & VP9_DEBUG_MERGE)
4352 pr_info(" # merge_vp9_switchable_interp_tree\n");
4353 coef_node_start = VP9_INTERP_START;
4354 coef_count_node_start = VP9_INTERP_COUNT_START;
4355 for (tree_i = 0; tree_i < 4; tree_i++) {
4356 for (node = 0; node < 2; node++) {
4357 switch (node) {
4358 case 1:
4359 tree_left =
4360 count[coef_count_node_start + 1];
4361 tree_right =
4362 count[coef_count_node_start + 2];
4363 break;
4364 default:
4365 tree_left =
4366 count[coef_count_node_start + 0];
4367 tree_right =
4368 count[coef_count_node_start + 1] +
4369 count[coef_count_node_start + 2];
4370 break;
4371
4372 }
4373
4374 vp9_tree_merge_probs(prev_prob, cur_prob,
4375 coef_node_start,
4376 tree_left, tree_right, tree_i, node);
4377
4378 coef_node_start = coef_node_start + 1;
4379 }
4380 coef_count_node_start = coef_count_node_start + 3;
4381 }
4382
4383 if (debug & VP9_DEBUG_MERGE)
4384 pr_info("# merge_vp9_mv_joint_tree\n");
4385 coef_node_start = VP9_MV_JOINTS_START;
4386 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4387 for (tree_i = 0; tree_i < 1; tree_i++) {
4388 for (node = 0; node < 3; node++) {
4389 switch (node) {
4390 case 2:
4391 tree_left =
4392 count[coef_count_node_start + 2];
4393 tree_right =
4394 count[coef_count_node_start + 3];
4395 break;
4396 case 1:
4397 tree_left =
4398 count[coef_count_node_start + 1];
4399 tree_right =
4400 count[coef_count_node_start + 2] +
4401 count[coef_count_node_start + 3];
4402 break;
4403 default:
4404 tree_left =
4405 count[coef_count_node_start + 0];
4406 tree_right =
4407 count[coef_count_node_start + 1] +
4408 count[coef_count_node_start + 2] +
4409 count[coef_count_node_start + 3];
4410 break;
4411 }
4412
4413 vp9_tree_merge_probs(prev_prob, cur_prob,
4414 coef_node_start,
4415 tree_left, tree_right, tree_i, node);
4416
4417 coef_node_start = coef_node_start + 1;
4418 }
4419 coef_count_node_start = coef_count_node_start + 4;
4420 }
4421
4422 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4423 if (debug & VP9_DEBUG_MERGE)
4424 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4425 coef_node_start =
4426 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4427 coef_count_node_start =
4428 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4429 : VP9_MV_CLASSES_0_COUNT_START;
4430 tree_i = 0;
4431 for (node = 0; node < 10; node++) {
4432 switch (node) {
4433 case 9:
4434 tree_left =
4435 count[coef_count_node_start + 9];
4436 tree_right =
4437 count[coef_count_node_start + 10];
4438 break;
4439 case 8:
4440 tree_left =
4441 count[coef_count_node_start + 7];
4442 tree_right =
4443 count[coef_count_node_start + 8];
4444 break;
4445 case 7:
4446 tree_left =
4447 count[coef_count_node_start + 7] +
4448 count[coef_count_node_start + 8];
4449 tree_right =
4450 count[coef_count_node_start + 9] +
4451 count[coef_count_node_start + 10];
4452 break;
4453 case 6:
4454 tree_left =
4455 count[coef_count_node_start + 6];
4456 tree_right =
4457 count[coef_count_node_start + 7] +
4458 count[coef_count_node_start + 8] +
4459 count[coef_count_node_start + 9] +
4460 count[coef_count_node_start + 10];
4461 break;
4462 case 5:
4463 tree_left =
4464 count[coef_count_node_start + 4];
4465 tree_right =
4466 count[coef_count_node_start + 5];
4467 break;
4468 case 4:
4469 tree_left =
4470 count[coef_count_node_start + 4] +
4471 count[coef_count_node_start + 5];
4472 tree_right =
4473 count[coef_count_node_start + 6] +
4474 count[coef_count_node_start + 7] +
4475 count[coef_count_node_start + 8] +
4476 count[coef_count_node_start + 9] +
4477 count[coef_count_node_start + 10];
4478 break;
4479 case 3:
4480 tree_left =
4481 count[coef_count_node_start + 2];
4482 tree_right =
4483 count[coef_count_node_start + 3];
4484 break;
4485 case 2:
4486 tree_left =
4487 count[coef_count_node_start + 2] +
4488 count[coef_count_node_start + 3];
4489 tree_right =
4490 count[coef_count_node_start + 4] +
4491 count[coef_count_node_start + 5] +
4492 count[coef_count_node_start + 6] +
4493 count[coef_count_node_start + 7] +
4494 count[coef_count_node_start + 8] +
4495 count[coef_count_node_start + 9] +
4496 count[coef_count_node_start + 10];
4497 break;
4498 case 1:
4499 tree_left =
4500 count[coef_count_node_start + 1];
4501 tree_right =
4502 count[coef_count_node_start + 2] +
4503 count[coef_count_node_start + 3] +
4504 count[coef_count_node_start + 4] +
4505 count[coef_count_node_start + 5] +
4506 count[coef_count_node_start + 6] +
4507 count[coef_count_node_start + 7] +
4508 count[coef_count_node_start + 8] +
4509 count[coef_count_node_start + 9] +
4510 count[coef_count_node_start + 10];
4511 break;
4512 default:
4513 tree_left =
4514 count[coef_count_node_start + 0];
4515 tree_right =
4516 count[coef_count_node_start + 1] +
4517 count[coef_count_node_start + 2] +
4518 count[coef_count_node_start + 3] +
4519 count[coef_count_node_start + 4] +
4520 count[coef_count_node_start + 5] +
4521 count[coef_count_node_start + 6] +
4522 count[coef_count_node_start + 7] +
4523 count[coef_count_node_start + 8] +
4524 count[coef_count_node_start + 9] +
4525 count[coef_count_node_start + 10];
4526 break;
4527
4528 }
4529
4530 vp9_tree_merge_probs(prev_prob, cur_prob,
4531 coef_node_start, tree_left, tree_right,
4532 tree_i, node);
4533
4534 coef_node_start = coef_node_start + 1;
4535 }
4536
4537 if (debug & VP9_DEBUG_MERGE)
4538 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4539 coef_node_start =
4540 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4541 coef_count_node_start =
4542 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4543 VP9_MV_CLASS0_0_COUNT_START;
4544 tree_i = 0;
4545 node = 0;
4546 tree_left = count[coef_count_node_start + 0];
4547 tree_right = count[coef_count_node_start + 1];
4548
4549 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4550 tree_left, tree_right, tree_i, node);
4551 if (debug & VP9_DEBUG_MERGE)
4552 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4553 mvd_i);
4554 coef_node_start =
4555 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4556 VP9_MV_CLASS0_FP_0_START;
4557 coef_count_node_start =
4558 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4559 VP9_MV_CLASS0_FP_0_COUNT_START;
4560 for (tree_i = 0; tree_i < 3; tree_i++) {
4561 for (node = 0; node < 3; node++) {
4562 switch (node) {
4563 case 2:
4564 tree_left =
4565 count[coef_count_node_start + 2];
4566 tree_right =
4567 count[coef_count_node_start + 3];
4568 break;
4569 case 1:
4570 tree_left =
4571 count[coef_count_node_start + 1];
4572 tree_right =
4573 count[coef_count_node_start + 2]
4574 + count[coef_count_node_start + 3];
4575 break;
4576 default:
4577 tree_left =
4578 count[coef_count_node_start + 0];
4579 tree_right =
4580 count[coef_count_node_start + 1]
4581 + count[coef_count_node_start + 2]
4582 + count[coef_count_node_start + 3];
4583 break;
4584
4585 }
4586
4587 vp9_tree_merge_probs(prev_prob, cur_prob,
4588 coef_node_start, tree_left, tree_right,
4589 tree_i, node);
4590
4591 coef_node_start = coef_node_start + 1;
4592 }
4593 coef_count_node_start = coef_count_node_start + 4;
4594 }
4595
4596 } /* for mvd_i (mvd_y or mvd_x)*/
4597}
4598
4599}
4600
4601
4602static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4603{
4604#ifndef MV_USE_FIXED_BUF
4605 dealloc_mv_bufs(pbi);
4606#endif
4607 if (pbi->mmu_box)
4608 decoder_mmu_box_free(pbi->mmu_box);
4609 pbi->mmu_box = NULL;
4610
4611 if (pbi->bmmu_box)
4612 decoder_bmmu_box_free(pbi->bmmu_box);
4613 pbi->bmmu_box = NULL;
4614}
4615
4616
4617static int config_pic(struct VP9Decoder_s *pbi,
4618 struct PIC_BUFFER_CONFIG_s *pic_config)
4619{
4620 int ret = -1;
4621 int i;
4622 int pic_width = pbi->init_pic_w;
4623 int pic_height = pbi->init_pic_h;
4624 int lcu_size = 64; /*fixed 64*/
4625 int pic_width_64 = (pic_width + 63) & (~0x3f);
4626 int pic_height_32 = (pic_height + 31) & (~0x1f);
4627 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4628 pic_width_64 / lcu_size + 1
4629 : pic_width_64 / lcu_size;
4630 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4631 pic_height_32 / lcu_size + 1
4632 : pic_height_32 / lcu_size;
4633 int lcu_total = pic_width_lcu * pic_height_lcu;
4634#ifdef MV_USE_FIXED_BUF
4635 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4636 pbi->work_space_buf->mpred_mv.buf_size;
4637#endif
4638 u32 y_adr = 0;
4639 int buf_size = 0;
4640
4641 int losless_comp_header_size =
4642 compute_losless_comp_header_size(pic_width,
4643 pic_height);
4644 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4645 pic_height, buf_alloc_depth == 10);
4646 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4647 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4648 int mc_buffer_size_u_v = 0;
4649 int mc_buffer_size_u_v_h = 0;
4650 int dw_mode = get_double_write_mode_init(pbi);
4651 struct vdec_fb *fb = NULL;
4652
4653 pbi->lcu_total = lcu_total;
4654
4655 if (dw_mode) {
4656 int pic_width_dw = pic_width /
4657 get_double_write_ratio(pbi, dw_mode);
4658 int pic_height_dw = pic_height /
4659 get_double_write_ratio(pbi, dw_mode);
4660
4661 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4662 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4663 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4664 pic_width_64_dw / lcu_size + 1
4665 : pic_width_64_dw / lcu_size;
4666 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4667 pic_height_32_dw / lcu_size + 1
4668 : pic_height_32_dw / lcu_size;
4669 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4670 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4671 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4672 /*64k alignment*/
4673 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4674 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4675 }
4676
4677 if (mc_buffer_size & 0xffff) /*64k alignment*/
4678 mc_buffer_size_h += 1;
4679 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4680 buf_size += (mc_buffer_size_h << 16);
4681
4682
4683 if (pbi->mmu_enable) {
4684 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4685 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4686
4687 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4688 pr_info("MMU header_adr %d: %ld\n",
4689 pic_config->index, pic_config->header_adr);
4690 }
4691 }
4692
4693 i = pic_config->index;
4694#ifdef MV_USE_FIXED_BUF
4695 if ((pbi->work_space_buf->mpred_mv.buf_start +
4696 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4697 <= mpred_mv_end
4698 ) {
4699#endif
4700 if (buf_size > 0) {
4701 if (pbi->is_used_v4l) {
4702 ret = v4l_get_fb(pbi->v4l2_ctx, &fb);
4703 if (ret) {
4704 vp9_print(pbi, PRINT_FLAG_ERROR,
4705 "[%d] get fb fail.\n",
4706 ((struct aml_vcodec_ctx *)
4707 (pbi->v4l2_ctx))->id);
4708 return ret;
4709 }
4710
4711 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4712 pic_config->cma_alloc_addr =
4713 virt_to_phys(fb->base_y.va);
4714 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4715 "[%d] %s(), v4l ref buf addr: 0x%x\n",
4716 ((struct aml_vcodec_ctx *)
4717 (pbi->v4l2_ctx))->id, __func__, fb);
4718 } else {
4719 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4720 VF_BUFFER_IDX(i),
4721 buf_size, DRIVER_NAME,
4722 &pic_config->cma_alloc_addr);
4723 if (ret < 0) {
4724 pr_info(
4725 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4726 VF_BUFFER_IDX(i),
4727 buf_size
4728 );
4729 return ret;
4730 }
4731 }
4732
4733 if (pic_config->cma_alloc_addr)
4734 y_adr = pic_config->cma_alloc_addr;
4735 else {
4736 pr_info(
4737 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4738 VF_BUFFER_IDX(i),
4739 buf_size
4740 );
4741 return -1;
4742 }
4743 }
4744 {
4745 /*ensure get_pic_by_POC()
4746 not get the buffer not decoded*/
4747 pic_config->BUF_index = i;
4748 pic_config->lcu_total = lcu_total;
4749
4750 pic_config->comp_body_size = losless_comp_body_size;
4751 pic_config->buf_size = buf_size;
4752
4753 pic_config->mc_canvas_y = pic_config->index;
4754 pic_config->mc_canvas_u_v = pic_config->index;
4755 if (dw_mode & 0x10) {
4756 pic_config->dw_y_adr = y_adr;
4757 pic_config->dw_u_v_adr = y_adr +
4758 ((mc_buffer_size_u_v_h << 16) << 1);
4759
4760 pic_config->mc_canvas_y =
4761 (pic_config->index << 1);
4762 pic_config->mc_canvas_u_v =
4763 (pic_config->index << 1) + 1;
4764 } else if (dw_mode) {
4765 pic_config->dw_y_adr = y_adr;
4766 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4767 ((mc_buffer_size_u_v_h << 16) << 1);
4768 }
4769#ifdef MV_USE_FIXED_BUF
4770 pic_config->mpred_mv_wr_start_addr =
4771 pbi->work_space_buf->mpred_mv.buf_start +
4772 ((pic_config->index * lcu_total)
4773 * MV_MEM_UNIT);
4774#endif
4775 if (debug) {
4776 pr_info
4777 ("%s index %d BUF_index %d ",
4778 __func__, pic_config->index,
4779 pic_config->BUF_index);
4780 pr_info
4781 ("comp_body_size %x comp_buf_size %x ",
4782 pic_config->comp_body_size,
4783 pic_config->buf_size);
4784 pr_info
4785 ("mpred_mv_wr_start_adr %ld\n",
4786 pic_config->mpred_mv_wr_start_addr);
4787 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4788 pic_config->dw_y_adr,
4789 pic_config->dw_u_v_adr);
4790 }
4791 ret = 0;
4792 }
4793#ifdef MV_USE_FIXED_BUF
4794 }
4795#endif
4796 return ret;
4797}
4798
4799static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
4800{
4801 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
4802 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
4803 return (MMU_COMPRESS_8K_HEADER_SIZE);
4804
4805 return (MMU_COMPRESS_HEADER_SIZE);
4806}
4807
4808/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
4809static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
4810{
4811 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
4812 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
4813 return (MAX_FRAME_8K_NUM * 4);
4814
4815 return (MAX_FRAME_4K_NUM * 4);
4816}
4817
4818
4819static void init_pic_list(struct VP9Decoder_s *pbi)
4820{
4821 int i;
4822 struct VP9_Common_s *cm = &pbi->common;
4823 struct PIC_BUFFER_CONFIG_s *pic_config;
4824 u32 header_size;
4825 struct vdec_s *vdec = hw_to_vdec(pbi);
4826
4827 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
4828 header_size = vvp9_mmu_compress_header_size(pbi);
4829 /*alloc VP9 compress header first*/
4830 for (i = 0; i < pbi->used_buf_num; i++) {
4831 unsigned long buf_addr;
4832 if (decoder_bmmu_box_alloc_buf_phy
4833 (pbi->bmmu_box,
4834 HEADER_BUFFER_IDX(i), header_size,
4835 DRIVER_HEADER_NAME,
4836 &buf_addr) < 0) {
4837 pr_info("%s malloc compress header failed %d\n",
4838 DRIVER_HEADER_NAME, i);
4839 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
4840 return;
4841 }
4842 }
4843 }
4844 for (i = 0; i < pbi->used_buf_num; i++) {
4845 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
4846 pic_config->index = i;
4847 pic_config->BUF_index = -1;
4848 pic_config->mv_buf_index = -1;
4849 if (vdec->parallel_dec == 1) {
4850 pic_config->y_canvas_index = -1;
4851 pic_config->uv_canvas_index = -1;
4852 }
4853 if (config_pic(pbi, pic_config) < 0) {
4854 if (debug)
4855 pr_info("Config_pic %d fail\n",
4856 pic_config->index);
4857 pic_config->index = -1;
4858 break;
4859 }
4860 pic_config->y_crop_width = pbi->init_pic_w;
4861 pic_config->y_crop_height = pbi->init_pic_h;
4862 pic_config->double_write_mode = get_double_write_mode(pbi);
4863
4864 if (pic_config->double_write_mode) {
4865 set_canvas(pbi, pic_config);
4866 }
4867 }
4868 for (; i < pbi->used_buf_num; i++) {
4869 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
4870 pic_config->index = -1;
4871 pic_config->BUF_index = -1;
4872 pic_config->mv_buf_index = -1;
4873 if (vdec->parallel_dec == 1) {
4874 pic_config->y_canvas_index = -1;
4875 pic_config->uv_canvas_index = -1;
4876 }
4877 }
4878 pr_info("%s ok, used_buf_num = %d\n",
4879 __func__, pbi->used_buf_num);
4880
4881}
4882
4883static void init_pic_list_hw(struct VP9Decoder_s *pbi)
4884{
4885 int i;
4886 struct VP9_Common_s *cm = &pbi->common;
4887 struct PIC_BUFFER_CONFIG_s *pic_config;
4888 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
4889 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
4890 (0x1 << 1) | (0x1 << 2));
4891
4892
4893 for (i = 0; i < pbi->used_buf_num; i++) {
4894 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
4895 if (pic_config->index < 0)
4896 break;
4897
4898 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
4899
4900 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
4901 pic_config->header_adr >> 5);
4902 } else {
4903 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
4904 * pic_config->mc_y_adr
4905 * | (pic_config->mc_canvas_y << 8) | 0x1);
4906 */
4907 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
4908 pic_config->dw_y_adr >> 5);
4909 }
4910#ifndef LOSLESS_COMPRESS_MODE
4911 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
4912 * pic_config->mc_u_v_adr
4913 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
4914 */
4915 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
4916 pic_config->header_adr >> 5);
4917#else
4918 if (pic_config->double_write_mode & 0x10) {
4919 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
4920 pic_config->dw_u_v_adr >> 5);
4921 }
4922#endif
4923 }
4924 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
4925
4926 /*Zero out canvas registers in IPP -- avoid simulation X*/
4927 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
4928 (0 << 8) | (0 << 1) | 1);
4929 for (i = 0; i < 32; i++)
4930 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
4931}
4932
4933
4934static void dump_pic_list(struct VP9Decoder_s *pbi)
4935{
4936 struct VP9_Common_s *const cm = &pbi->common;
4937 struct PIC_BUFFER_CONFIG_s *pic_config;
4938 int i;
4939 for (i = 0; i < FRAME_BUFFERS; i++) {
4940 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
4941 vp9_print(pbi, 0,
4942 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
4943 i,
4944 pic_config->index,
4945#ifndef MV_USE_FIXED_BUF
4946 pic_config->mv_buf_index,
4947#else
4948 -1,
4949#endif
4950 cm->buffer_pool->
4951 frame_bufs[i].ref_count,
4952 pic_config->vf_ref,
4953 pic_config->decode_idx,
4954 pic_config->slice_type,
4955 pic_config->y_crop_width,
4956 pic_config->y_crop_height,
4957 pic_config->cma_alloc_addr
4958 );
4959 }
4960 return;
4961}
4962
4963static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
4964{
4965#ifdef LOSLESS_COMPRESS_MODE
4966 unsigned int data32;
4967#endif
4968 int losless_comp_header_size, losless_comp_body_size;
4969 struct VP9_Common_s *cm = &pbi->common;
4970 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
4971
4972 frame_width = cur_pic_config->y_crop_width;
4973 frame_height = cur_pic_config->y_crop_height;
4974 cur_pic_config->bit_depth = bit_depth;
4975 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
4976 losless_comp_header_size =
4977 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
4978 cur_pic_config->y_crop_height);
4979 losless_comp_body_size =
4980 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
4981 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
4982 cur_pic_config->comp_body_size = losless_comp_body_size;
4983#ifdef LOSLESS_COMPRESS_MODE
4984 data32 = READ_VREG(HEVC_SAO_CTRL5);
4985 if (bit_depth == VPX_BITS_10)
4986 data32 &= ~(1 << 9);
4987 else
4988 data32 |= (1 << 9);
4989
4990 WRITE_VREG(HEVC_SAO_CTRL5, data32);
4991
4992 if (pbi->mmu_enable) {
4993 /*bit[4] : paged_mem_mode*/
4994 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
4995 } else {
4996 /*bit[3] smem mdoe*/
4997 if (bit_depth == VPX_BITS_10)
4998 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
4999 else
5000 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5001 }
5002 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5003 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5004 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5005 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5006 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5007 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5008 if (get_double_write_mode(pbi) & 0x10)
5009 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5010#else
5011 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5012#endif
5013 return 0;
5014}
5015
5016static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5017{
5018 int i;
5019 struct VP9_Common_s *cm = &pbi->common;
5020 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5021 uint8_t scale_enable = 0;
5022
5023 if (debug&VP9_DEBUG_BUFMGR_MORE)
5024 pr_info("config_mc_buffer entered .....\n");
5025
5026 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5027 (0 << 8) | (0 << 1) | 1);
5028 for (i = 0; i < REFS_PER_FRAME; ++i) {
5029 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5030 if (!pic_config)
5031 continue;
5032 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5033 (pic_config->mc_canvas_u_v << 16)
5034 | (pic_config->mc_canvas_u_v << 8)
5035 | pic_config->mc_canvas_y);
5036 if (debug & VP9_DEBUG_BUFMGR_MORE)
5037 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5038 i, pic_config->mc_canvas_u_v,
5039 pic_config->mc_canvas_y);
5040 }
5041 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5042 (16 << 8) | (0 << 1) | 1);
5043 for (i = 0; i < REFS_PER_FRAME; ++i) {
5044 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5045 if (!pic_config)
5046 continue;
5047 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5048 (pic_config->mc_canvas_u_v << 16)
5049 | (pic_config->mc_canvas_u_v << 8)
5050 | pic_config->mc_canvas_y);
5051 }
5052
5053 /*auto_inc start index:0 field:0*/
5054 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5055 /*index 0:last 1:golden 2:altref*/
5056 for (i = 0; i < REFS_PER_FRAME; i++) {
5057 int ref_pic_body_size;
5058 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5059 if (!pic_config)
5060 continue;
5061 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5062 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5063
5064 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5065 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5066 scale_enable |= (1 << i);
5067 }
5068 ref_pic_body_size =
5069 compute_losless_comp_body_size(pic_config->y_crop_width,
5070 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5071 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5072 (pic_config->y_crop_width << 14)
5073 / cur_pic_config->y_crop_width);
5074 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5075 (pic_config->y_crop_height << 14)
5076 / cur_pic_config->y_crop_height);
5077 if (pbi->mmu_enable)
5078 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5079 else
5080 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5081 }
5082 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5083 return 0;
5084}
5085
5086static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5087{
5088 unsigned int data32;
5089
5090 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5091 data32 &= (~(1 << 6));
5092 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5093}
5094
5095static void config_mpred_hw(struct VP9Decoder_s *pbi)
5096{
5097 struct VP9_Common_s *cm = &pbi->common;
5098 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5099 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5100 &cm->prev_frame->buf;
5101
5102 unsigned int data32;
5103 int mpred_curr_lcu_x;
5104 int mpred_curr_lcu_y;
5105 int mpred_mv_rd_end_addr;
5106
5107
5108 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5109 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5110
5111 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5112 mpred_curr_lcu_x = data32 & 0xffff;
5113 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5114
5115 if (debug & VP9_DEBUG_BUFMGR)
5116 pr_info("cur pic_config index %d col pic_config index %d\n",
5117 cur_pic_config->index, last_frame_pic_config->index);
5118 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5119 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5120 pbi->work_space_buf->mpred_above.buf_start);
5121
5122 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5123
5124 data32 &= (~(1 << 6));
5125 data32 |= (cm->use_prev_frame_mvs << 6);
5126 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5127
5128 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5129 cur_pic_config->mpred_mv_wr_start_addr);
5130 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5131
5132 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5133 last_frame_pic_config->mpred_mv_wr_start_addr);
5134 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5135 last_frame_pic_config->mpred_mv_wr_start_addr);
5136 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5137 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5138 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5139 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5140
5141}
5142
5143static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5144{
5145 struct VP9_Common_s *cm = &pbi->common;
5146 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5147
5148 unsigned int data32;
5149 int lcu_size = 64;
5150 int mc_buffer_size_u_v =
5151 pic_config->lcu_total * lcu_size*lcu_size/2;
5152 int mc_buffer_size_u_v_h =
5153 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5154
5155
5156 if (get_double_write_mode(pbi)) {
5157 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5158 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5159 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5160 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5161 } else {
5162 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5163 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5164 }
5165 if (pbi->mmu_enable)
5166 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5167
5168 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5169 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5170 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5171 */
5172 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5173
5174 data32 = (mc_buffer_size_u_v_h << 16);
5175 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5176
5177#ifdef VP9_10B_NV21
5178#ifdef DOS_PROJECT
5179 data32 = READ_VREG(HEVC_SAO_CTRL1);
5180 data32 &= (~0x3000);
5181 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5182 data32 |= (mem_map_mode << 12);
5183 data32 &= (~0x3);
5184 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5185 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5186 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5187 * [17:16] dw_h0_ctrl
5188 */
5189 data32 = READ_VREG(HEVC_SAO_CTRL5);
5190 /*set them all 0 for H265_NV21 (no down-scale)*/
5191 data32 &= ~(0xff << 16);
5192 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5193 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5194 data32 &= (~0x30);
5195 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5196 data32 |= (mem_map_mode << 4);
5197 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5198#else
5199 /*m8baby test1902*/
5200 data32 = READ_VREG(HEVC_SAO_CTRL1);
5201 data32 &= (~0x3000);
5202 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5203 data32 |= (mem_map_mode << 12);
5204 data32 &= (~0xff0);
5205 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5206 data32 |= 0x880; /*.Big-Endian per 64-bit */
5207 data32 &= (~0x3);
5208 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5209 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5210 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5211 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5212 */
5213 data32 = READ_VREG(HEVC_SAO_CTRL5);
5214 /* set them all 0 for H265_NV21 (no down-scale)*/
5215 data32 &= ~(0xff << 16);
5216 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5217
5218 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5219 data32 &= (~0x30);
5220 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5221 data32 |= (mem_map_mode << 4);
5222 data32 &= (~0xF);
5223 data32 |= 0x8; /*Big-Endian per 64-bit*/
5224 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5225#endif
5226#else
5227 data32 = READ_VREG(HEVC_SAO_CTRL1);
5228 data32 &= (~0x3000);
5229 data32 |= (mem_map_mode <<
5230 12);
5231
5232/* [13:12] axi_aformat, 0-Linear,
5233 * 1-32x32, 2-64x32
5234 */
5235 data32 &= (~0xff0);
5236 /* data32 |= 0x670; // Big-Endian per 64-bit */
5237 data32 |= endian; /* Big-Endian per 64-bit */
5238 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5239 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5240 if (get_double_write_mode(pbi) == 0)
5241 data32 |= 0x2; /*disable double write*/
5242 else if (get_double_write_mode(pbi) & 0x10)
5243 data32 |= 0x1; /*disable cm*/
5244 } else { /* >= G12A dw write control */
5245 unsigned int data;
5246 data = READ_VREG(HEVC_DBLK_CFGB);
5247 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5248 if (get_double_write_mode(pbi) == 0)
5249 data |= (0x1 << 8); /*enable first write*/
5250 else if (get_double_write_mode(pbi) & 0x10)
5251 data |= (0x1 << 9); /*double write only*/
5252 else
5253 data |= ((0x1 << 8) |(0x1 << 9));
5254 WRITE_VREG(HEVC_DBLK_CFGB, data);
5255 }
5256 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5257
5258 if (get_double_write_mode(pbi) & 0x10) {
5259 /* [23:22] dw_v1_ctrl
5260 *[21:20] dw_v0_ctrl
5261 *[19:18] dw_h1_ctrl
5262 *[17:16] dw_h0_ctrl
5263 */
5264 data32 = READ_VREG(HEVC_SAO_CTRL5);
5265 /*set them all 0 for H265_NV21 (no down-scale)*/
5266 data32 &= ~(0xff << 16);
5267 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5268 } else {
5269 data32 = READ_VREG(HEVC_SAO_CTRL5);
5270 data32 &= (~(0xff << 16));
5271 if (get_double_write_mode(pbi) == 2 ||
5272 get_double_write_mode(pbi) == 3)
5273 data32 |= (0xff<<16);
5274 else if (get_double_write_mode(pbi) == 4)
5275 data32 |= (0x33<<16);
5276 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5277 }
5278
5279 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5280 data32 &= (~0x30);
5281 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5282 data32 |= (mem_map_mode <<
5283 4);
5284 data32 &= (~0xF);
5285 data32 |= 0xf; /* valid only when double write only */
5286 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5287 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5288#endif
5289}
5290
5291static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5292{
5293 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5294 unsigned int data32;
5295
5296 if (debug && pbi->init_flag == 0)
5297 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5298 __func__,
5299 buf_spec->ipp.buf_start,
5300 buf_spec->start_adr,
5301 buf_spec->short_term_rps.buf_start,
5302 buf_spec->vps.buf_start,
5303 buf_spec->sps.buf_start,
5304 buf_spec->pps.buf_start,
5305 buf_spec->sao_up.buf_start,
5306 buf_spec->swap_buf.buf_start,
5307 buf_spec->swap_buf2.buf_start,
5308 buf_spec->scalelut.buf_start,
5309 buf_spec->dblk_para.buf_start,
5310 buf_spec->dblk_data.buf_start);
5311
5312 if (mask & HW_MASK_FRONT) {
5313 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5314 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5315
5316 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5317 buf_spec->short_term_rps.buf_start);
5318 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5319 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5320 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5321 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5322 buf_spec->swap_buf.buf_start);
5323 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5324 buf_spec->swap_buf2.buf_start);
5325 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5326
5327 }
5328
5329 if (mask & HW_MASK_BACK) {
5330#ifdef LOSLESS_COMPRESS_MODE
5331 int losless_comp_header_size =
5332 compute_losless_comp_header_size(pbi->init_pic_w,
5333 pbi->init_pic_h);
5334 int losless_comp_body_size =
5335 compute_losless_comp_body_size(pbi->init_pic_w,
5336 pbi->init_pic_h, buf_alloc_depth == 10);
5337#endif
5338 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5339 buf_spec->ipp.buf_start);
5340 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5341 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5342 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5343 /* cfg_addr_adp*/
5344 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5345 if (debug & VP9_DEBUG_BUFMGR_MORE)
5346 pr_info("Write HEVC_DBLK_CFGE\n");
5347 }
5348 /* cfg_p_addr */
5349 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5350 /* cfg_d_addr */
5351 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5352
5353 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5354 /*
5355 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5356 * data32 = data32 * 2;
5357 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5358 * data32 = data32 * 2;
5359 */
5360 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5361 }
5362#ifdef LOSLESS_COMPRESS_MODE
5363 if (pbi->mmu_enable) {
5364 /*bit[4] : paged_mem_mode*/
5365 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5366 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5367 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5368 } else {
5369 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5370 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5371 */
5372 /*bit[3] smem mdoe*/
5373 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5374 /*bit[3] smem mdoe*/
5375 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5376 (losless_comp_body_size >> 5));
5377 }
5378 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5379 (losless_comp_body_size >> 5));*/
5380 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5381 (0xff<<20) | (0xff<<10) | 0xff);*/
5382 /*8-bit mode */
5383 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5384 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5385 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5386 if (get_double_write_mode(pbi) & 0x10)
5387 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5388#else
5389 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5390#endif
5391
5392 if (pbi->mmu_enable) {
5393 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5394 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5395 + buf_spec->mmu_vbh.buf_size/2);
5396 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5397 /*data32 |= 0x1;*/
5398 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5399
5400 /* use HEVC_CM_HEADER_START_ADDR */
5401 data32 = READ_VREG(HEVC_SAO_CTRL5);
5402 data32 |= (1<<10);
5403 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5404 }
5405
5406 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5407
5408 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5409 /**/
5410 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5411 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5412 if (pbi->mmu_enable) {
5413 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5414 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5415 else
5416 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5417 }
5418 }
5419}
5420
5421
5422#ifdef VP9_LPF_LVL_UPDATE
5423/*
5424 * Defines, declarations, sub-functions for vp9 de-block loop
5425 filter Thr/Lvl table update
5426 * - struct segmentation is for loop filter only (removed something)
5427 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5428 be instantiated in C_Entry
5429 * - vp9_loop_filter_init run once before decoding start
5430 * - vp9_loop_filter_frame_init run before every frame decoding start
5431 * - set video format to VP9 is in vp9_loop_filter_init
5432 */
5433#define MAX_LOOP_FILTER 63
5434#define MAX_REF_LF_DELTAS 4
5435#define MAX_MODE_LF_DELTAS 2
5436/*#define INTRA_FRAME 0*/
5437/*#define LAST_FRAME 1*/
5438/*#define MAX_REF_FRAMES 4*/
5439#define SEGMENT_DELTADATA 0
5440#define SEGMENT_ABSDATA 1
5441#define MAX_SEGMENTS 8
5442/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5443/*no use for loop filter, if this struct for common use, pls add it back*/
5444/*#define PREDICTION_PROBS 3*/
5445/* no use for loop filter, if this struct for common use, pls add it back*/
5446
5447enum SEG_LVL_FEATURES {
5448 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5449 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5450 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5451 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5452 SEG_LVL_MAX = 4 /*Number of features supported*/
5453};
5454
5455struct segmentation {
5456 uint8_t enabled;
5457 uint8_t update_map;
5458 uint8_t update_data;
5459 uint8_t abs_delta;
5460 uint8_t temporal_update;
5461
5462 /*no use for loop filter, if this struct
5463 *for common use, pls add it back
5464 */
5465 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5466 /* no use for loop filter, if this struct
5467 * for common use, pls add it back
5468 */
5469 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5470
5471 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5472 unsigned int feature_mask[MAX_SEGMENTS];
5473};
5474
5475struct loop_filter_thresh {
5476 uint8_t mblim;
5477 uint8_t lim;
5478 uint8_t hev_thr;
5479};
5480
5481struct loop_filter_info_n {
5482 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5483 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5484};
5485
5486struct loopfilter {
5487 int filter_level;
5488
5489 int sharpness_level;
5490 int last_sharpness_level;
5491
5492 uint8_t mode_ref_delta_enabled;
5493 uint8_t mode_ref_delta_update;
5494
5495 /*0 = Intra, Last, GF, ARF*/
5496 signed char ref_deltas[MAX_REF_LF_DELTAS];
5497 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5498
5499 /*0 = ZERO_MV, MV*/
5500 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5501 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5502};
5503
5504static int vp9_clamp(int value, int low, int high)
5505{
5506 return value < low ? low : (value > high ? high : value);
5507}
5508
5509int segfeature_active(struct segmentation *seg,
5510 int segment_id,
5511 enum SEG_LVL_FEATURES feature_id) {
5512 return seg->enabled &&
5513 (seg->feature_mask[segment_id] & (1 << feature_id));
5514}
5515
5516int get_segdata(struct segmentation *seg, int segment_id,
5517 enum SEG_LVL_FEATURES feature_id) {
5518 return seg->feature_data[segment_id][feature_id];
5519}
5520
5521static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5522 int sharpness_lvl)
5523{
5524 int lvl;
5525 /*For each possible value for the loop filter fill out limits*/
5526 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5527 /*Set loop filter parameters that control sharpness.*/
5528 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5529 (sharpness_lvl > 4));
5530
5531 if (sharpness_lvl > 0) {
5532 if (block_inside_limit > (9 - sharpness_lvl))
5533 block_inside_limit = (9 - sharpness_lvl);
5534 }
5535
5536 if (block_inside_limit < 1)
5537 block_inside_limit = 1;
5538
5539 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5540 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5541 block_inside_limit);
5542 }
5543}
5544
5545/*instantiate this function once when decode is started*/
5546void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5547{
5548 struct loop_filter_info_n *lfi = pbi->lfi;
5549 struct loopfilter *lf = pbi->lf;
5550 struct segmentation *seg_4lf = pbi->seg_4lf;
5551 int i;
5552 unsigned int data32;
5553
5554 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5555 memset(lf, 0, sizeof(struct loopfilter));
5556 memset(seg_4lf, 0, sizeof(struct segmentation));
5557 lf->sharpness_level = 0; /*init to 0 */
5558 /*init limits for given sharpness*/
5559 vp9_update_sharpness(lfi, lf->sharpness_level);
5560 lf->last_sharpness_level = lf->sharpness_level;
5561 /*init hev threshold const vectors (actually no use)
5562 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5563 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5564 */
5565
5566 /*Write to register*/
5567 for (i = 0; i < 32; i++) {
5568 unsigned int thr;
5569
5570 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5571 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5572 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5573 (lfi->lfthr[i * 2].mblim & 0xff);
5574 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5575 }
5576
5577 /*video format is VP9*/
5578 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5579 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5580 (0x3 << 12) | // (dw fifo thres r or b)
5581 (0x3 << 10) | // (dw fifo thres not r/b)
5582 (0x3 << 8) | // 1st/2nd write both enable
5583 (0x1 << 0); // vp9 video format
5584 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5585 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5586 (0x1 << 0); /*vp9 video format*/
5587 } else
5588 data32 = 0x40400001;
5589
5590 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5591 if (debug & VP9_DEBUG_BUFMGR_MORE)
5592 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5593}
5594 /* perform this function per frame*/
5595void vp9_loop_filter_frame_init(struct segmentation *seg,
5596 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5597 int default_filt_lvl) {
5598 int i;
5599 int seg_id;
5600 /*n_shift is the multiplier for lf_deltas
5601 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5602 *2 when filter_lvl is between 32 and 63
5603 */
5604 const int scale = 1 << (default_filt_lvl >> 5);
5605
5606 /*update limits if sharpness has changed*/
5607 if (lf->last_sharpness_level != lf->sharpness_level) {
5608 vp9_update_sharpness(lfi, lf->sharpness_level);
5609 lf->last_sharpness_level = lf->sharpness_level;
5610
5611 /*Write to register*/
5612 for (i = 0; i < 32; i++) {
5613 unsigned int thr;
5614
5615 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5616 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5617 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5618 | (lfi->lfthr[i * 2].mblim & 0xff);
5619 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5620 }
5621 }
5622
5623 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5624 int lvl_seg = default_filt_lvl;
5625
5626 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5627 const int data = get_segdata(seg, seg_id,
5628 SEG_LVL_ALT_LF);
5629 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5630 data : default_filt_lvl + data,
5631 0, MAX_LOOP_FILTER);
5632#ifdef DBG_LF_PRINT
5633 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5634#endif
5635 }
5636
5637 if (!lf->mode_ref_delta_enabled) {
5638 /*we could get rid of this if we assume that deltas are set to
5639 *zero when not in use; encoder always uses deltas
5640 */
5641 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5642 } else {
5643 int ref, mode;
5644 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5645 * scale;
5646#ifdef DBG_LF_PRINT
5647 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5648 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5649#endif
5650 lfi->lvl[seg_id][INTRA_FRAME][0] =
5651 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5652
5653 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5654 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5655 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5656 /*MAX_MODE_LF_DELTAS = 2*/
5657 const int inter_lvl =
5658 lvl_seg + lf->ref_deltas[ref] * scale
5659 + lf->mode_deltas[mode] * scale;
5660#ifdef DBG_LF_PRINT
5661#endif
5662 lfi->lvl[seg_id][ref][mode] =
5663 vp9_clamp(inter_lvl, 0,
5664 MAX_LOOP_FILTER);
5665 }
5666 }
5667 }
5668 }
5669
5670#ifdef DBG_LF_PRINT
5671 /*print out thr/lvl table per frame*/
5672 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5673 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5674 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5675 lfi->lfthr[i].lim);
5676 }
5677 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5678 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5679 seg_id, lfi->lvl[seg_id][0][0],
5680 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5681 lfi->lvl[seg_id][3][0]);
5682 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5683 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5684 lfi->lvl[seg_id][3][1]);
5685 }
5686#endif
5687
5688 /*Write to register */
5689 for (i = 0; i < 16; i++) {
5690 unsigned int level;
5691
5692 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5693 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5694 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5695 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5696 if (!default_filt_lvl)
5697 level = 0;
5698 WRITE_VREG(HEVC_DBLK_CFGA, level);
5699 }
5700}
5701/* VP9_LPF_LVL_UPDATE */
5702#endif
5703
5704static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5705{
5706 unsigned int data32;
5707 int i;
5708 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5709 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5710 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5711 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5712 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5713 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5714 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5715 0x7C00
5716 };
5717#if 0
5718 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5719 /* Set MCR fetch priorities*/
5720 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5721 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5722 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5723 }
5724#endif
5725 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
5726 pr_info("%s\n", __func__);*/
5727 if (mask & HW_MASK_FRONT) {
5728 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5729#if 1
5730 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5731 data32 &= ~(7 << 29);
5732 data32 |= (3 << 29);
5733#endif
5734 data32 = data32 |
5735 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
5736 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
5737 (1 << 7) |/*dec_done_int_cpu_enable*/
5738 (1 << 4) |/*startcode_found_int_cpu_enable*/
5739 (0 << 3) |/*startcode_found_int_amrisc_enable*/
5740 (1 << 0) /*parser_int_enable*/
5741 ;
5742#ifdef SUPPORT_FB_DECODING
5743#ifndef FB_DECODING_TEST_SCHEDULE
5744 /*fed_fb_slice_done_int_cpu_enable*/
5745 if (pbi->used_stage_buf_num > 0)
5746 data32 |= (1 << 10);
5747#endif
5748#endif
5749 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
5750
5751 data32 = READ_VREG(HEVC_SHIFT_STATUS);
5752 data32 = data32 |
5753 (0 << 1) |/*emulation_check_off VP9
5754 do not have emulation*/
5755 (1 << 0)/*startcode_check_on*/
5756 ;
5757 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
5758 WRITE_VREG(HEVC_SHIFT_CONTROL,
5759 (0 << 14) | /*disable_start_code_protect*/
5760 (1 << 10) | /*length_zero_startcode_en for VP9*/
5761 (1 << 9) | /*length_valid_startcode_en for VP9*/
5762 (3 << 6) | /*sft_valid_wr_position*/
5763 (2 << 4) | /*emulate_code_length_sub_1*/
5764 (3 << 1) | /*start_code_length_sub_1
5765 VP9 use 0x00000001 as startcode (4 Bytes)*/
5766 (1 << 0) /*stream_shift_enable*/
5767 );
5768
5769 WRITE_VREG(HEVC_CABAC_CONTROL,
5770 (1 << 0)/*cabac_enable*/
5771 );
5772
5773 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
5774 (1 << 0)/* hevc_parser_core_clk_en*/
5775 );
5776
5777
5778 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
5779
5780 }
5781
5782 if (mask & HW_MASK_BACK) {
5783 /*Initial IQIT_SCALELUT memory
5784 -- just to avoid X in simulation*/
5785
5786 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
5787 for (i = 0; i < 1024; i++)
5788 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
5789 }
5790
5791 if (mask & HW_MASK_FRONT) {
5792 u32 decode_mode;
5793#ifdef ENABLE_SWAP_TEST
5794 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
5795#else
5796 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
5797#endif
5798#ifdef MULTI_INSTANCE_SUPPORT
5799 if (!pbi->m_ins_flag) {
5800 if (pbi->low_latency_flag)
5801 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
5802 else
5803 decode_mode = DECODE_MODE_SINGLE;
5804 } else if (vdec_frame_based(hw_to_vdec(pbi)))
5805 decode_mode = pbi->no_head ?
5806 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
5807 DECODE_MODE_MULTI_FRAMEBASE;
5808 else
5809 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
5810#ifdef SUPPORT_FB_DECODING
5811#ifndef FB_DECODING_TEST_SCHEDULE
5812 if (pbi->used_stage_buf_num > 0)
5813 decode_mode |= (0x01 << 24);
5814#endif
5815#endif
5816 WRITE_VREG(DECODE_MODE, decode_mode);
5817 WRITE_VREG(HEVC_DECODE_SIZE, 0);
5818 WRITE_VREG(HEVC_DECODE_COUNT, 0);
5819#else
5820 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
5821 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
5822 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
5823#endif
5824 /*Send parser_cmd*/
5825 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
5826 for (i = 0; i < PARSER_CMD_NUMBER; i++)
5827 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
5828 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
5829 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
5830 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
5831
5832
5833 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
5834 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
5835 (1 << 5) | /*parser_sao_if_en*/
5836 (1 << 2) | /*parser_mpred_if_en*/
5837 (1 << 0) /*parser_scaler_if_en*/
5838 );
5839 }
5840
5841 if (mask & HW_MASK_BACK) {
5842 /*Changed to Start MPRED in microcode*/
5843 /*
5844 pr_info("[test.c] Start MPRED\n");
5845 WRITE_VREG(HEVC_MPRED_INT_STATUS,
5846 (1<<31)
5847 );
5848 */
5849 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
5850 (0 << 1) | /*enable ipp*/
5851 (1 << 0) /*software reset ipp and mpp*/
5852 );
5853 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
5854 (1 << 1) | /*enable ipp*/
5855 (0 << 0) /*software reset ipp and mpp*/
5856 );
5857 if (get_double_write_mode(pbi) & 0x10) {
5858 /*Enable NV21 reference read mode for MC*/
5859 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5860 }
5861
5862 /*Initialize mcrcc and decomp perf counters*/
5863 if (mcrcc_cache_alg_flag &&
5864 pbi->init_flag == 0) {
5865 mcrcc_perfcount_reset();
5866 decomp_perfcount_reset();
5867 }
5868 }
5869 return;
5870}
5871
5872
5873#ifdef CONFIG_HEVC_CLK_FORCED_ON
5874static void config_vp9_clk_forced_on(void)
5875{
5876 unsigned int rdata32;
5877 /*IQIT*/
5878 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
5879 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
5880
5881 /* DBLK*/
5882 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
5883 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
5884
5885 /* SAO*/
5886 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
5887 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
5888
5889 /*MPRED*/
5890 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
5891 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
5892
5893 /* PARSER*/
5894 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
5895 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
5896 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
5897 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
5898 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
5899 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
5900 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
5901 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
5902 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5903 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
5904 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
5905 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
5906 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
5907
5908 /*IPP*/
5909 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
5910 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
5911
5912 /* MCRCC*/
5913 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
5914 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
5915}
5916#endif
5917
5918
5919#ifdef MCRCC_ENABLE
5920static void dump_hit_rate(struct VP9Decoder_s *pbi)
5921{
5922 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
5923 mcrcc_get_hitrate(pbi->m_ins_flag);
5924 decomp_get_hitrate();
5925 decomp_get_comprate();
5926 }
5927}
5928
5929static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
5930{
5931 unsigned int rdata32;
5932 unsigned short is_inter;
5933 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
5934 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
5935 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
5936 (!pbi->common.intra_only)) ? 1 : 0;
5937 if (!is_inter) { /* I-PIC*/
5938 /*remove reset -- disables clock*/
5939 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
5940 return;
5941 }
5942
5943 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5944 mcrcc_get_hitrate(pbi->m_ins_flag);
5945 decomp_get_hitrate();
5946 decomp_get_comprate();
5947 }
5948
5949 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5950 (0 << 8) | (1 << 1) | 0);
5951 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
5952 rdata32 = rdata32 & 0xffff;
5953 rdata32 = rdata32 | (rdata32 << 16);
5954 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
5955 /*Programme canvas1 */
5956 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
5957 rdata32 = rdata32 & 0xffff;
5958 rdata32 = rdata32 | (rdata32 << 16);
5959 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
5960 /*enable mcrcc progressive-mode*/
5961 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
5962}
5963
5964static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
5965{
5966 u32 curr_picnum = -1;
5967 u32 lastref_picnum = -1;
5968 u32 goldenref_picnum = -1;
5969 u32 altref_picnum = -1;
5970
5971 u32 lastref_delta_picnum;
5972 u32 goldenref_delta_picnum;
5973 u32 altref_delta_picnum;
5974
5975 u32 rdata32;
5976
5977 u32 lastcanvas;
5978 u32 goldencanvas;
5979 u32 altrefcanvas;
5980
5981 u16 is_inter;
5982 u16 lastref_inref;
5983 u16 goldenref_inref;
5984 u16 altref_inref;
5985
5986 u32 refcanvas_array[3], utmp;
5987 int deltapicnum_array[3], tmp;
5988
5989 struct VP9_Common_s *cm = &pbi->common;
5990 struct PIC_BUFFER_CONFIG_s *cur_pic_config
5991 = &cm->cur_frame->buf;
5992 curr_picnum = cur_pic_config->decode_idx;
5993 if (cm->frame_refs[0].buf)
5994 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
5995 if (cm->frame_refs[1].buf)
5996 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
5997 if (cm->frame_refs[2].buf)
5998 altref_picnum = cm->frame_refs[2].buf->decode_idx;
5999
6000 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6001 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6002 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6003 (goldenref_picnum - curr_picnum) :
6004 (curr_picnum - goldenref_picnum);
6005 altref_delta_picnum =
6006 (altref_picnum >= curr_picnum) ?
6007 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6008
6009 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6010 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6011 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6012
6013 if (debug & VP9_DEBUG_CACHE)
6014 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6015 __func__, lastref_inref, goldenref_inref, altref_inref);
6016
6017 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6018
6019 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6020 && (!pbi->common.intra_only)) ? 1 : 0;
6021
6022 if (!is_inter) { /* I-PIC */
6023 /* remove reset -- disables clock */
6024 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6025 return;
6026 }
6027
6028 if (!pbi->m_ins_flag)
6029 dump_hit_rate(pbi);
6030
6031 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6032 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6033 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6034 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6035
6036 if (debug & VP9_DEBUG_CACHE)
6037 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6038 lastcanvas, goldencanvas, altrefcanvas);
6039
6040 altref_inref = ((altref_inref == 1) &&
6041 (altrefcanvas != (goldenref_inref
6042 ? goldencanvas : 0xffffffff)) &&
6043 (altrefcanvas != (lastref_inref ?
6044 lastcanvas : 0xffffffff))) ? 1 : 0;
6045 goldenref_inref = ((goldenref_inref == 1) &&
6046 (goldencanvas != (lastref_inref ?
6047 lastcanvas : 0xffffffff))) ? 1 : 0;
6048 if (debug & VP9_DEBUG_CACHE)
6049 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6050 lastref_inref, goldenref_inref, altref_inref);
6051
6052 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6053 goldenref_delta_picnum = goldenref_inref ?
6054 goldenref_delta_picnum : 0x7fffffff;
6055 lastref_delta_picnum = lastref_inref ?
6056 lastref_delta_picnum : 0x7fffffff;
6057 if (debug & VP9_DEBUG_CACHE)
6058 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6059 lastref_delta_picnum, goldenref_delta_picnum,
6060 altref_delta_picnum);
6061 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6062
6063 refcanvas_array[0] = lastcanvas;
6064 refcanvas_array[1] = goldencanvas;
6065 refcanvas_array[2] = altrefcanvas;
6066
6067 deltapicnum_array[0] = lastref_delta_picnum;
6068 deltapicnum_array[1] = goldenref_delta_picnum;
6069 deltapicnum_array[2] = altref_delta_picnum;
6070
6071 /* sort0 : 2-to-1 */
6072 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6073 utmp = refcanvas_array[2];
6074 refcanvas_array[2] = refcanvas_array[1];
6075 refcanvas_array[1] = utmp;
6076 tmp = deltapicnum_array[2];
6077 deltapicnum_array[2] = deltapicnum_array[1];
6078 deltapicnum_array[1] = tmp;
6079 }
6080 /* sort1 : 1-to-0 */
6081 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6082 utmp = refcanvas_array[1];
6083 refcanvas_array[1] = refcanvas_array[0];
6084 refcanvas_array[0] = utmp;
6085 tmp = deltapicnum_array[1];
6086 deltapicnum_array[1] = deltapicnum_array[0];
6087 deltapicnum_array[0] = tmp;
6088 }
6089 /* sort2 : 2-to-1 */
6090 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6091 utmp = refcanvas_array[2]; refcanvas_array[2] =
6092 refcanvas_array[1]; refcanvas_array[1] = utmp;
6093 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6094 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6095 }
6096 if (mcrcc_cache_alg_flag ==
6097 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6098 /* lowest delta_picnum */
6099 rdata32 = refcanvas_array[0];
6100 rdata32 = rdata32 & 0xffff;
6101 rdata32 = rdata32 | (rdata32 << 16);
6102 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6103
6104 /* 2nd-lowest delta_picnum */
6105 rdata32 = refcanvas_array[1];
6106 rdata32 = rdata32 & 0xffff;
6107 rdata32 = rdata32 | (rdata32 << 16);
6108 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6109 } else {
6110 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6111 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6112 (0 << 8) | (1<<1) | 0);
6113 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6114 rdata32 = rdata32 & 0xffff;
6115 rdata32 = rdata32 | (rdata32 << 16);
6116 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6117
6118 /* Programme canvas1 */
6119 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6120 rdata32 = rdata32 & 0xffff;
6121 rdata32 = rdata32 | (rdata32 << 16);
6122 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6123 }
6124
6125 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6126 return;
6127}
6128
6129#endif
6130
6131
6132static void free_lf_buf(struct VP9Decoder_s *pbi)
6133{
6134 if (pbi->lfi)
6135 vfree(pbi->lfi);
6136 if (pbi->lf)
6137 vfree(pbi->lf);
6138 if (pbi->seg_4lf)
6139 vfree(pbi->seg_4lf);
6140 pbi->lfi = NULL;
6141 pbi->lf = NULL;
6142 pbi->seg_4lf = NULL;
6143}
6144
6145static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6146{
6147 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6148 pbi->lf = vmalloc(sizeof(struct loopfilter));
6149 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6150 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6151 free_lf_buf(pbi);
6152 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6153 return -1;
6154 }
6155 return 0;
6156}
6157
6158static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6159{
6160 pbi->rpm_ptr = NULL;
6161 pbi->lmem_ptr = NULL;
6162 if (pbi->rpm_addr) {
6163 dma_free_coherent(amports_get_dma_device(),
6164 RPM_BUF_SIZE,
6165 pbi->rpm_addr,
6166 pbi->rpm_phy_addr);
6167 pbi->rpm_addr = NULL;
6168 }
6169 if (pbi->lmem_addr) {
6170 if (pbi->lmem_phy_addr)
6171 dma_free_coherent(amports_get_dma_device(),
6172 LMEM_BUF_SIZE, pbi->lmem_addr,
6173 pbi->lmem_phy_addr);
6174 pbi->lmem_addr = NULL;
6175 }
6176 if (pbi->prob_buffer_addr) {
6177 if (pbi->prob_buffer_phy_addr)
6178 dma_free_coherent(amports_get_dma_device(),
6179 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6180 pbi->prob_buffer_phy_addr);
6181
6182 pbi->prob_buffer_addr = NULL;
6183 }
6184 if (pbi->count_buffer_addr) {
6185 if (pbi->count_buffer_phy_addr)
6186 dma_free_coherent(amports_get_dma_device(),
6187 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6188 pbi->count_buffer_phy_addr);
6189
6190 pbi->count_buffer_addr = NULL;
6191 }
6192 if (pbi->mmu_enable) {
6193 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6194 if (pbi->frame_mmu_map_addr) {
6195 if (pbi->frame_mmu_map_phy_addr)
6196 dma_free_coherent(amports_get_dma_device(),
6197 mmu_map_size,
6198 pbi->frame_mmu_map_addr,
6199 pbi->frame_mmu_map_phy_addr);
6200 pbi->frame_mmu_map_addr = NULL;
6201 }
6202 }
6203#ifdef SUPPORT_FB_DECODING
6204 if (pbi->stage_mmu_map_addr) {
6205 if (pbi->stage_mmu_map_phy_addr)
6206 dma_free_coherent(amports_get_dma_device(),
6207 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6208 pbi->stage_mmu_map_addr,
6209 pbi->stage_mmu_map_phy_addr);
6210 pbi->stage_mmu_map_addr = NULL;
6211 }
6212
6213 uninit_stage_buf(pbi);
6214#endif
6215
6216#ifdef VP9_LPF_LVL_UPDATE
6217 free_lf_buf(pbi);
6218#endif
6219 if (pbi->gvs)
6220 vfree(pbi->gvs);
6221 pbi->gvs = NULL;
6222}
6223
6224static int vp9_local_init(struct VP9Decoder_s *pbi)
6225{
6226 int ret = -1;
6227 /*int losless_comp_header_size, losless_comp_body_size;*/
6228
6229 struct BuffInfo_s *cur_buf_info = NULL;
6230
6231 memset(&pbi->param, 0, sizeof(union param_u));
6232 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6233#ifdef MULTI_INSTANCE_SUPPORT
6234 cur_buf_info = &pbi->work_space_buf_store;
6235
6236 if (vdec_is_support_4k()) {
6237 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6238 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6239 sizeof(struct BuffInfo_s));
6240 } else
6241 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6242 sizeof(struct BuffInfo_s));
6243 } else
6244 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6245 sizeof(struct BuffInfo_s));
6246
6247 cur_buf_info->start_adr = pbi->buf_start;
6248 if (!pbi->mmu_enable)
6249 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6250
6251#else
6252/*! MULTI_INSTANCE_SUPPORT*/
6253 if (vdec_is_support_4k()) {
6254 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6255 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6256 else
6257 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6258 } else
6259 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6260
6261#endif
6262
6263 init_buff_spec(pbi, cur_buf_info);
6264 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6265
6266 if (!vdec_is_support_4k()
6267 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6268 buf_alloc_width = 1920;
6269 buf_alloc_height = 1088;
6270 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6271 pbi->max_pic_w = 1920;
6272 pbi->max_pic_h = 1088;
6273 }
6274 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6275 buf_alloc_width = 8192;
6276 buf_alloc_height = 4608;
6277 }
6278 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6279 (buf_alloc_width ? buf_alloc_width :
6280 (pbi->vvp9_amstream_dec_info.width ?
6281 pbi->vvp9_amstream_dec_info.width :
6282 pbi->work_space_buf->max_width));
6283 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6284 (buf_alloc_height ? buf_alloc_height :
6285 (pbi->vvp9_amstream_dec_info.height ?
6286 pbi->vvp9_amstream_dec_info.height :
6287 pbi->work_space_buf->max_height));
6288
6289 /* video is not support unaligned with 64 in tl1
6290 ** vdec canvas mode will be linear when dump yuv is set
6291 */
6292 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6293 (pbi->double_write_mode != 0) &&
6294 (((pbi->max_pic_w % 64) != 0) ||
6295 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6296 if (hw_to_vdec(pbi)->canvas_mode !=
6297 CANVAS_BLKMODE_LINEAR)
6298 mem_map_mode = 2;
6299 else {
6300 mem_map_mode = 0;
6301 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6302 }
6303 }
6304
6305#ifndef MV_USE_FIXED_BUF
6306 if (init_mv_buf_list(pbi) < 0) {
6307 pr_err("%s: init_mv_buf_list fail\n", __func__);
6308 return -1;
6309 }
6310#endif
6311 if (pbi->save_buffer_mode)
6312 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6313 else
6314 pbi->used_buf_num = max_buf_num;
6315
6316 if (pbi->used_buf_num > MAX_BUF_NUM)
6317 pbi->used_buf_num = MAX_BUF_NUM;
6318 if (pbi->used_buf_num > FRAME_BUFFERS)
6319 pbi->used_buf_num = FRAME_BUFFERS;
6320
6321 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6322 & 0x40) >> 6;
6323
6324 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6325 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6326 RPM_BUF_SIZE,
6327 &pbi->rpm_phy_addr, GFP_KERNEL);
6328 if (pbi->rpm_addr == NULL) {
6329 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6330 return -1;
6331 }
6332
6333 pbi->rpm_ptr = pbi->rpm_addr;
6334 }
6335
6336 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6337 LMEM_BUF_SIZE,
6338 &pbi->lmem_phy_addr, GFP_KERNEL);
6339 if (pbi->lmem_addr == NULL) {
6340 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6341 return -1;
6342 }
6343 pbi->lmem_ptr = pbi->lmem_addr;
6344
6345 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6346 PROB_BUF_SIZE,
6347 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6348 if (pbi->prob_buffer_addr == NULL) {
6349 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6350 return -1;
6351 }
6352 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6353 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6354 COUNT_BUF_SIZE,
6355 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6356 if (pbi->count_buffer_addr == NULL) {
6357 pr_err("%s: failed to alloc count_buffer\n", __func__);
6358 return -1;
6359 }
6360 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6361
6362 if (pbi->mmu_enable) {
6363 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6364 pbi->frame_mmu_map_addr =
6365 dma_alloc_coherent(amports_get_dma_device(),
6366 mmu_map_size,
6367 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6368 if (pbi->frame_mmu_map_addr == NULL) {
6369 pr_err("%s: failed to alloc count_buffer\n", __func__);
6370 return -1;
6371 }
6372 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6373 }
6374#ifdef SUPPORT_FB_DECODING
6375 if (pbi->m_ins_flag && stage_buf_num > 0) {
6376 pbi->stage_mmu_map_addr =
6377 dma_alloc_coherent(amports_get_dma_device(),
6378 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6379 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6380 if (pbi->stage_mmu_map_addr == NULL) {
6381 pr_err("%s: failed to alloc count_buffer\n", __func__);
6382 return -1;
6383 }
6384 memset(pbi->stage_mmu_map_addr,
6385 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6386
6387 init_stage_buf(pbi);
6388 }
6389#endif
6390
6391 ret = 0;
6392 return ret;
6393}
6394
6395/********************************************
6396 * Mailbox command
6397 ********************************************/
6398#define CMD_FINISHED 0
6399#define CMD_ALLOC_VIEW 1
6400#define CMD_FRAME_DISPLAY 3
6401#define CMD_DEBUG 10
6402
6403
6404#define DECODE_BUFFER_NUM_MAX 32
6405#define DISPLAY_BUFFER_NUM 6
6406
6407#define video_domain_addr(adr) (adr&0x7fffffff)
6408#define DECODER_WORK_SPACE_SIZE 0x800000
6409
6410#define spec2canvas(x) \
6411 (((x)->uv_canvas_index << 16) | \
6412 ((x)->uv_canvas_index << 8) | \
6413 ((x)->y_canvas_index << 0))
6414
6415
6416static void set_canvas(struct VP9Decoder_s *pbi,
6417 struct PIC_BUFFER_CONFIG_s *pic_config)
6418{
6419 struct vdec_s *vdec = hw_to_vdec(pbi);
6420 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6421 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6422 int blkmode = mem_map_mode;
6423 /*CANVAS_BLKMODE_64X32*/
6424 if (pic_config->double_write_mode) {
6425 canvas_w = pic_config->y_crop_width /
6426 get_double_write_ratio(pbi,
6427 pic_config->double_write_mode);
6428 canvas_h = pic_config->y_crop_height /
6429 get_double_write_ratio(pbi,
6430 pic_config->double_write_mode);
6431
6432 if (mem_map_mode == 0)
6433 canvas_w = ALIGN(canvas_w, 32);
6434 else
6435 canvas_w = ALIGN(canvas_w, 64);
6436 canvas_h = ALIGN(canvas_h, 32);
6437
6438 if (vdec->parallel_dec == 1) {
6439 if (pic_config->y_canvas_index == -1)
6440 pic_config->y_canvas_index =
6441 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6442 if (pic_config->uv_canvas_index == -1)
6443 pic_config->uv_canvas_index =
6444 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6445 } else {
6446 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6447 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6448 }
6449
6450 canvas_config_ex(pic_config->y_canvas_index,
6451 pic_config->dw_y_adr, canvas_w, canvas_h,
6452 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
6453 canvas_config_ex(pic_config->uv_canvas_index,
6454 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6455 CANVAS_ADDR_NOWRAP, blkmode, 0x7);
6456
6457#ifdef MULTI_INSTANCE_SUPPORT
6458 pic_config->canvas_config[0].phy_addr =
6459 pic_config->dw_y_adr;
6460 pic_config->canvas_config[0].width =
6461 canvas_w;
6462 pic_config->canvas_config[0].height =
6463 canvas_h;
6464 pic_config->canvas_config[0].block_mode =
6465 blkmode;
6466 pic_config->canvas_config[0].endian = 7;
6467
6468 pic_config->canvas_config[1].phy_addr =
6469 pic_config->dw_u_v_adr;
6470 pic_config->canvas_config[1].width =
6471 canvas_w;
6472 pic_config->canvas_config[1].height =
6473 canvas_h;
6474 pic_config->canvas_config[1].block_mode =
6475 blkmode;
6476 pic_config->canvas_config[1].endian = 7;
6477#endif
6478 }
6479}
6480
6481
6482static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6483{
6484 unsigned int ar;
6485 vf->duration = pbi->frame_dur;
6486 vf->duration_pulldown = 0;
6487 vf->flag = 0;
6488 vf->prop.master_display_colour = pbi->vf_dp;
6489 vf->signal_type = pbi->video_signal_type;
6490 if (vf->compWidth && vf->compHeight)
6491 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6492 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6493 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6494
6495}
6496
6497static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6498{
6499 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6500
6501 states->vf_pool_size = VF_POOL_SIZE;
6502 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6503 states->buf_avail_num = kfifo_len(&pbi->display_q);
6504
6505 if (step == 2)
6506 states->buf_avail_num = 0;
6507 return 0;
6508}
6509
6510static struct vframe_s *vvp9_vf_peek(void *op_arg)
6511{
6512 struct vframe_s *vf[2] = {0, 0};
6513 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6514
6515 if (step == 2)
6516 return NULL;
6517
6518 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6519 if (vf[1]) {
6520 vf[0]->next_vf_pts_valid = true;
6521 vf[0]->next_vf_pts = vf[1]->pts;
6522 } else
6523 vf[0]->next_vf_pts_valid = false;
6524 return vf[0];
6525 }
6526
6527 return NULL;
6528}
6529
6530static struct vframe_s *vvp9_vf_get(void *op_arg)
6531{
6532 struct vframe_s *vf;
6533 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6534
6535 if (step == 2)
6536 return NULL;
6537 else if (step == 1)
6538 step = 2;
6539
6540 if (kfifo_get(&pbi->display_q, &vf)) {
6541 struct vframe_s *next_vf;
6542 uint8_t index = vf->index & 0xff;
6543 if (index < pbi->used_buf_num) {
6544 pbi->vf_get_count++;
6545 if (debug & VP9_DEBUG_BUFMGR)
6546 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6547 __func__, vf->type,
6548 vf->width, vf->height,
6549 vf->pts,
6550 vf->pts_us64);
6551
6552 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6553 vf->next_vf_pts_valid = true;
6554 vf->next_vf_pts = next_vf->pts;
6555 } else
6556 vf->next_vf_pts_valid = false;
6557
6558 return vf;
6559 }
6560 }
6561 return NULL;
6562}
6563
6564static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6565{
6566 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6567 uint8_t index = vf->index & 0xff;
6568
6569 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6570 pbi->vf_put_count++;
6571 if (index < pbi->used_buf_num) {
6572 struct VP9_Common_s *cm = &pbi->common;
6573 struct BufferPool_s *pool = cm->buffer_pool;
6574 unsigned long flags;
6575
6576 lock_buffer_pool(pool, flags);
6577 if (pool->frame_bufs[index].buf.vf_ref > 0)
6578 pool->frame_bufs[index].buf.vf_ref--;
6579
6580 if (pbi->wait_buf)
6581 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6582 0x1);
6583 pbi->last_put_idx = index;
6584 pbi->new_frame_displayed++;
6585 unlock_buffer_pool(pool, flags);
6586#ifdef SUPPORT_FB_DECODING
6587 if (pbi->used_stage_buf_num > 0 &&
6588 pbi->back_not_run_ready)
6589 trigger_schedule(pbi);
6590#endif
6591 }
6592
6593}
6594
6595static int vvp9_event_cb(int type, void *data, void *private_data)
6596{
6597 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6598#if 0
6599 unsigned long flags;
6600
6601 amhevc_stop();
6602#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6603 vf_light_unreg_provider(&vvp9_vf_prov);
6604#endif
6605 spin_lock_irqsave(&pbi->lock, flags);
6606 vvp9_local_init();
6607 vvp9_prot_init();
6608 spin_unlock_irqrestore(&pbi->lock, flags);
6609#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6610 vf_reg_provider(&vvp9_vf_prov);
6611#endif
6612 amhevc_start();
6613#endif
6614 }
6615
6616 return 0;
6617}
6618
6619void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6620{
6621 struct VP9_Common_s *cm = &pbi->common;
6622
6623 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6624
6625 if (debug & VP9_DEBUG_BUFMGR_MORE)
6626 pr_info("%s index = %d new vf_ref = %d\r\n",
6627 __func__, index,
6628 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6629}
6630
6631static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6632{
6633 u32 old_duration, pts_duration = 0;
6634 u32 pts = vf->pts;
6635
6636 if (pbi->get_frame_dur == true)
6637 return true;
6638
6639 pbi->frame_cnt_window++;
6640 if (!(pbi->vp9_first_pts_ready == 1)) {
6641 if (valid) {
6642 pbi->pts1 = pts;
6643 pbi->frame_cnt_window = 0;
6644 pbi->duration_from_pts_done = 0;
6645 pbi->vp9_first_pts_ready = 1;
6646 } else {
6647 return false;
6648 }
6649 } else {
6650 if (pts < pbi->pts1) {
6651 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6652 pbi->pts1 = pts;
6653 pbi->frame_cnt_window = 0;
6654 }
6655 }
6656
6657 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6658 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6659 old_duration = pbi->frame_dur;
6660 pbi->pts2 = pts;
6661 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6662 (pbi->frame_cnt_window * 15));
6663
6664 if (close_to(pts_duration, old_duration, 2000)) {
6665 pbi->frame_dur = pts_duration;
6666 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6667 pr_info("use calc duration %d\n", pts_duration);
6668 }
6669
6670 if (pbi->duration_from_pts_done == 0) {
6671 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6672 pbi->duration_from_pts_done = 1;
6673 } else {
6674 if (!close_to(pts_duration,
6675 old_duration, 1000) &&
6676 !close_to(pts_duration,
6677 pbi->frame_dur, 1000) &&
6678 close_to(pts_duration,
6679 pbi->last_duration, 200)) {
6680 /* frame_dur must
6681 * wrong,recover it.
6682 */
6683 pbi->frame_dur = pts_duration;
6684 }
6685 pbi->pts1 = pbi->pts2;
6686 pbi->frame_cnt_window = 0;
6687 pbi->duration_from_pts_done = 0;
6688 }
6689 }
6690 pbi->last_duration = pts_duration;
6691 }
6692 }
6693 return true;
6694}
6695
6696static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6697 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6698{
6699 if (pic->index < 0) {
6700 vf->mem_handle = NULL;
6701 vf->mem_head_handle = NULL;
6702 } else if (vf->type & VIDTYPE_SCATTER) {
6703 vf->mem_handle =
6704 decoder_mmu_box_get_mem_handle(
6705 pbi->mmu_box, pic->index);
6706 vf->mem_head_handle =
6707 decoder_bmmu_box_get_mem_handle(
6708 pbi->bmmu_box,
6709 HEADER_BUFFER_IDX(pic->BUF_index));
6710 } else {
6711 vf->mem_handle =
6712 decoder_bmmu_box_get_mem_handle(
6713 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
6714 vf->mem_head_handle = NULL;
6715 /*vf->mem_head_handle =
6716 *decoder_bmmu_box_get_mem_handle(
6717 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
6718 */
6719 }
6720}
6721
6722static int prepare_display_buf(struct VP9Decoder_s *pbi,
6723 struct PIC_BUFFER_CONFIG_s *pic_config)
6724{
6725 struct vframe_s *vf = NULL;
6726 int stream_offset = pic_config->stream_offset;
6727 unsigned short slice_type = pic_config->slice_type;
6728 u32 pts_valid = 0, pts_us64_valid = 0;
6729 u32 pts_save;
6730 u64 pts_us64_save;
6731 u32 frame_size;
6732
6733 if (debug & VP9_DEBUG_BUFMGR)
6734 pr_info("%s index = %d\r\n", __func__, pic_config->index);
6735 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
6736 pr_info("fatal error, no available buffer slot.");
6737 return -1;
6738 }
6739
6740 if (pic_config->double_write_mode)
6741 set_canvas(pbi, pic_config);
6742
6743 display_frame_count[pbi->index]++;
6744 if (vf) {
6745 if (pbi->is_used_v4l) {
6746 vf->v4l_mem_handle
6747 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
6748 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
6749 "[%d] %s(), v4l mem handle: 0x%lx\n",
6750 ((struct aml_vcodec_ctx *)(pbi->v4l2_ctx))->id,
6751 __func__, vf->v4l_mem_handle);
6752 }
6753
6754#ifdef MULTI_INSTANCE_SUPPORT
6755 if (vdec_frame_based(hw_to_vdec(pbi))) {
6756 vf->pts = pic_config->pts;
6757 vf->pts_us64 = pic_config->pts64;
6758 if (vf->pts != 0 || vf->pts_us64 != 0) {
6759 pts_valid = 1;
6760 pts_us64_valid = 1;
6761 } else {
6762 pts_valid = 0;
6763 pts_us64_valid = 0;
6764 }
6765 } else
6766#endif
6767 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
6768 * stream_offset, &vf->pts, 0) != 0) {
6769 */
6770 if (pts_lookup_offset_us64
6771 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
6772 &frame_size, 0,
6773 &vf->pts_us64) != 0) {
6774#ifdef DEBUG_PTS
6775 pbi->pts_missed++;
6776#endif
6777 vf->pts = 0;
6778 vf->pts_us64 = 0;
6779 pts_valid = 0;
6780 pts_us64_valid = 0;
6781 } else {
6782#ifdef DEBUG_PTS
6783 pbi->pts_hit++;
6784#endif
6785 pts_valid = 1;
6786 pts_us64_valid = 1;
6787 }
6788
6789 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
6790
6791 pts_save = vf->pts;
6792 pts_us64_save = vf->pts_us64;
6793 if (pbi->pts_unstable) {
6794 frame_duration_adapt(pbi, vf, pts_valid);
6795 if (pbi->duration_from_pts_done) {
6796 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
6797 } else {
6798 if (pts_valid || pts_us64_valid)
6799 pbi->pts_mode = PTS_NORMAL;
6800 }
6801 }
6802
6803 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
6804 && pbi->get_frame_dur) {
6805 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
6806
6807 if (pts_diff < 0) {
6808 pbi->pts_mode_switching_count++;
6809 pbi->pts_mode_recovery_count = 0;
6810
6811 if (pbi->pts_mode_switching_count >=
6812 PTS_MODE_SWITCHING_THRESHOLD) {
6813 pbi->pts_mode =
6814 PTS_NONE_REF_USE_DURATION;
6815 pr_info
6816 ("HEVC: switch to n_d mode.\n");
6817 }
6818
6819 } else {
6820 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
6821
6822 pbi->pts_mode_recovery_count++;
6823 if (pbi->pts_mode_recovery_count > p) {
6824 pbi->pts_mode_switching_count = 0;
6825 pbi->pts_mode_recovery_count = 0;
6826 }
6827 }
6828 }
6829
6830 if (vf->pts != 0)
6831 pbi->last_lookup_pts = vf->pts;
6832
6833 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
6834 && (slice_type != KEY_FRAME))
6835 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
6836 pbi->last_pts = vf->pts;
6837
6838 if (vf->pts_us64 != 0)
6839 pbi->last_lookup_pts_us64 = vf->pts_us64;
6840
6841 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
6842 && (slice_type != KEY_FRAME)) {
6843 vf->pts_us64 =
6844 pbi->last_pts_us64 +
6845 (DUR2PTS(pbi->frame_dur) * 100 / 9);
6846 }
6847 pbi->last_pts_us64 = vf->pts_us64;
6848 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
6849 pr_info
6850 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
6851 pbi->pts_mode, pbi->frame_dur, vf->pts,
6852 vf->pts_us64, pts_save, pts_us64_save);
6853 }
6854
6855 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
6856 vf->disp_pts = vf->pts;
6857 vf->disp_pts_us64 = vf->pts_us64;
6858 vf->pts = pts_save;
6859 vf->pts_us64 = pts_us64_save;
6860 } else {
6861 vf->disp_pts = 0;
6862 vf->disp_pts_us64 = 0;
6863 }
6864
6865 vf->index = 0xff00 | pic_config->index;
6866
6867 if (pic_config->double_write_mode & 0x10) {
6868 /* double write only */
6869 vf->compBodyAddr = 0;
6870 vf->compHeadAddr = 0;
6871 } else {
6872 if (pbi->mmu_enable) {
6873 vf->compBodyAddr = 0;
6874 vf->compHeadAddr = pic_config->header_adr;
6875 } else {
6876 /*vf->compBodyAddr = pic_config->mc_y_adr;
6877 *vf->compHeadAddr = pic_config->mc_y_adr +
6878 *pic_config->comp_body_size; */
6879 /*head adr*/
6880 }
6881 vf->canvas0Addr = vf->canvas1Addr = 0;
6882 }
6883 if (pic_config->double_write_mode) {
6884 vf->type = VIDTYPE_PROGRESSIVE |
6885 VIDTYPE_VIU_FIELD;
6886 vf->type |= VIDTYPE_VIU_NV21;
6887 if ((pic_config->double_write_mode == 3) &&
6888 (!IS_8K_SIZE(pic_config->y_crop_width,
6889 pic_config->y_crop_height))) {
6890 vf->type |= VIDTYPE_COMPRESS;
6891 if (pbi->mmu_enable)
6892 vf->type |= VIDTYPE_SCATTER;
6893 }
6894#ifdef MULTI_INSTANCE_SUPPORT
6895 if (pbi->m_ins_flag) {
6896 vf->canvas0Addr = vf->canvas1Addr = -1;
6897 vf->plane_num = 2;
6898 vf->canvas0_config[0] =
6899 pic_config->canvas_config[0];
6900 vf->canvas0_config[1] =
6901 pic_config->canvas_config[1];
6902 vf->canvas1_config[0] =
6903 pic_config->canvas_config[0];
6904 vf->canvas1_config[1] =
6905 pic_config->canvas_config[1];
6906
6907 } else
6908#endif
6909 vf->canvas0Addr = vf->canvas1Addr =
6910 spec2canvas(pic_config);
6911 } else {
6912 vf->canvas0Addr = vf->canvas1Addr = 0;
6913 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
6914 if (pbi->mmu_enable)
6915 vf->type |= VIDTYPE_SCATTER;
6916 }
6917
6918 switch (pic_config->bit_depth) {
6919 case VPX_BITS_8:
6920 vf->bitdepth = BITDEPTH_Y8 |
6921 BITDEPTH_U8 | BITDEPTH_V8;
6922 break;
6923 case VPX_BITS_10:
6924 case VPX_BITS_12:
6925 vf->bitdepth = BITDEPTH_Y10 |
6926 BITDEPTH_U10 | BITDEPTH_V10;
6927 break;
6928 default:
6929 vf->bitdepth = BITDEPTH_Y10 |
6930 BITDEPTH_U10 | BITDEPTH_V10;
6931 break;
6932 }
6933 if ((vf->type & VIDTYPE_COMPRESS) == 0)
6934 vf->bitdepth =
6935 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
6936 if (pic_config->bit_depth == VPX_BITS_8)
6937 vf->bitdepth |= BITDEPTH_SAVING_MODE;
6938
6939 /* if((vf->width!=pic_config->width)|
6940 * (vf->height!=pic_config->height))
6941 */
6942 /* pr_info("aaa: %d/%d, %d/%d\n",
6943 vf->width,vf->height, pic_config->width,
6944 pic_config->height); */
6945 vf->width = pic_config->y_crop_width /
6946 get_double_write_ratio(pbi,
6947 pic_config->double_write_mode);
6948 vf->height = pic_config->y_crop_height /
6949 get_double_write_ratio(pbi,
6950 pic_config->double_write_mode);
6951 if (force_w_h != 0) {
6952 vf->width = (force_w_h >> 16) & 0xffff;
6953 vf->height = force_w_h & 0xffff;
6954 }
6955 vf->compWidth = pic_config->y_crop_width;
6956 vf->compHeight = pic_config->y_crop_height;
6957 set_frame_info(pbi, vf);
6958 if (force_fps & 0x100) {
6959 u32 rate = force_fps & 0xff;
6960
6961 if (rate)
6962 vf->duration = 96000/rate;
6963 else
6964 vf->duration = 0;
6965 }
6966 update_vf_memhandle(pbi, vf, pic_config);
6967 if (!(pic_config->y_crop_width == 196
6968 && pic_config->y_crop_height == 196
6969 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
6970 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
6971 inc_vf_ref(pbi, pic_config->index);
6972 decoder_do_frame_check(hw_to_vdec(pbi), vf);
6973 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
6974 ATRACE_COUNTER(MODULE_NAME, vf->pts);
6975 pbi->vf_pre_count++;
6976#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
6977 /*count info*/
6978 gvs->frame_dur = pbi->frame_dur;
6979 vdec_count_info(gvs, 0, stream_offset);
6980#endif
6981 hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
6982 if (without_display_mode == 0) {
6983 vf_notify_receiver(pbi->provider_name,
6984 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
6985 } else
6986 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
6987 } else {
6988 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
6989 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
6990 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
6991 __func__, __LINE__, vf->width,
6992 vf->height, pbi->stat);
6993 }
6994 }
6995
6996 return 0;
6997}
6998
6999static int notify_v4l_eos(struct vdec_s *vdec)
7000{
7001 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7002 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7003 struct vframe_s *vf = NULL;
7004 struct vdec_fb *fb = NULL;
7005
7006 if (hw->is_used_v4l && hw->eos) {
7007 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
7008 vp9_print(hw, 0,
7009 "%s fatal error, no available buffer slot.\n",
7010 __func__);
7011 return -1;
7012 }
7013
7014 if (v4l_get_fb(hw->v4l2_ctx, &fb)) {
7015 pr_err("[%d] get fb fail.\n", ctx->id);
7016 return -1;
7017 }
7018
7019 vf->timestamp = ULONG_MAX;
7020 vf->v4l_mem_handle = (unsigned long)fb;
7021 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7022
7023 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7024 vf_notify_receiver(vdec->vf_provider_name,
7025 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7026
7027 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7028 }
7029
7030 return 0;
7031}
7032
7033static void get_rpm_param(union param_u *params)
7034{
7035 int i;
7036 unsigned int data32;
7037
7038 if (debug & VP9_DEBUG_BUFMGR)
7039 pr_info("enter %s\r\n", __func__);
7040 for (i = 0; i < 128; i++) {
7041 do {
7042 data32 = READ_VREG(RPM_CMD_REG);
7043 /*pr_info("%x\n", data32);*/
7044 } while ((data32 & 0x10000) == 0);
7045 params->l.data[i] = data32&0xffff;
7046 /*pr_info("%x\n", data32);*/
7047 WRITE_VREG(RPM_CMD_REG, 0);
7048 }
7049 if (debug & VP9_DEBUG_BUFMGR)
7050 pr_info("leave %s\r\n", __func__);
7051}
7052static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7053{
7054 int i;
7055
7056 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7057 return;
7058 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7059 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7060 pr_info("%04x ", vp9_param.l.data[i]);
7061 if (((i + 1) & 0xf) == 0)
7062 pr_info("\n");
7063 }
7064 pr_info("=============param==========\r\n");
7065 pr_info("profile %x\r\n", vp9_param.p.profile);
7066 pr_info("show_existing_frame %x\r\n",
7067 vp9_param.p.show_existing_frame);
7068 pr_info("frame_to_show_idx %x\r\n",
7069 vp9_param.p.frame_to_show_idx);
7070 pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7071 pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7072 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7073 vp9_param.p.error_resilient_mode);
7074 pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7075 pr_info("display_size_present %x\r\n",
7076 vp9_param.p.display_size_present);
7077 pr_info("reset_frame_context %x\r\n",
7078 vp9_param.p.reset_frame_context);
7079 pr_info("refresh_frame_flags %x\r\n",
7080 vp9_param.p.refresh_frame_flags);
7081 pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7082 pr_info("width %x\r\n", vp9_param.p.width);
7083 pr_info("height %x\r\n", vp9_param.p.height);
7084 pr_info("display_width %x\r\n", vp9_param.p.display_width);
7085 pr_info("display_height %x\r\n", vp9_param.p.display_height);
7086 pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7087 pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7088 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7089 return;
7090 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7091 vp9_param.p.mode_ref_delta_enabled);
7092 pr_info("sharpness_level: 0x%x\r\n",
7093 vp9_param.p.sharpness_level);
7094 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7095 vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7096 vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7097 pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7098 vp9_param.p.mode_deltas[1]);
7099 pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7100 pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7101 pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7102 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7103 (vp9_param.p.seg_lf_info[0]>>15 & 1),
7104 (vp9_param.p.seg_lf_info[1]>>15 & 1),
7105 (vp9_param.p.seg_lf_info[2]>>15 & 1),
7106 (vp9_param.p.seg_lf_info[3]>>15 & 1),
7107 (vp9_param.p.seg_lf_info[4]>>15 & 1),
7108 (vp9_param.p.seg_lf_info[5]>>15 & 1),
7109 (vp9_param.p.seg_lf_info[6]>>15 & 1),
7110 (vp9_param.p.seg_lf_info[7]>>15 & 1));
7111 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7112 (vp9_param.p.seg_lf_info[0] & 0x13f),
7113 (vp9_param.p.seg_lf_info[1] & 0x13f),
7114 (vp9_param.p.seg_lf_info[2] & 0x13f),
7115 (vp9_param.p.seg_lf_info[3] & 0x13f),
7116 (vp9_param.p.seg_lf_info[4] & 0x13f),
7117 (vp9_param.p.seg_lf_info[5] & 0x13f),
7118 (vp9_param.p.seg_lf_info[6] & 0x13f),
7119 (vp9_param.p.seg_lf_info[7] & 0x13f));
7120
7121}
7122
7123
7124static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7125{
7126 struct VP9_Common_s *const cm = &pbi->common;
7127 if (pbi->double_write_mode & 0x10)
7128 return;
7129 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7130 if (pbi->used_4k_num == -1) {
7131 pbi->used_4k_num =
7132 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7133 if (pbi->m_ins_flag)
7134 hevc_mmu_dma_check(hw_to_vdec(pbi));
7135 }
7136 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7137 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7138 cm->cur_fb_idx_mmu = INVALID_IDX;
7139 pbi->used_4k_num = -1;
7140 }
7141}
7142
7143#ifdef MULTI_INSTANCE_SUPPORT
7144static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7145{
7146 struct VP9_Common_s *const cm = &pbi->common;
7147 if (pbi->double_write_mode & 0x10)
7148 return;
7149 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7150 decoder_mmu_box_free_idx(pbi->mmu_box,
7151 cm->cur_fb_idx_mmu);
7152
7153 cm->cur_fb_idx_mmu = INVALID_IDX;
7154 pbi->used_4k_num = -1;
7155 }
7156}
7157#endif
7158
7159
7160static void dec_again_process(struct VP9Decoder_s *pbi)
7161{
7162 amhevc_stop();
7163 pbi->dec_result = DEC_RESULT_AGAIN;
7164 if (pbi->process_state ==
7165 PROC_STATE_DECODESLICE) {
7166 pbi->process_state =
7167 PROC_STATE_SENDAGAIN;
7168 if (pbi->mmu_enable)
7169 vp9_recycle_mmu_buf(pbi);
7170 }
7171 reset_process_time(pbi);
7172 vdec_schedule_work(&pbi->work);
7173}
7174
7175int continue_decoding(struct VP9Decoder_s *pbi)
7176{
7177 int ret;
7178 int i;
7179 struct VP9_Common_s *const cm = &pbi->common;
7180 debug_buffer_mgr_more(pbi);
7181
7182 bit_depth_luma = vp9_param.p.bit_depth;
7183 bit_depth_chroma = vp9_param.p.bit_depth;
7184
7185 if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7186 (get_double_write_mode(pbi) == 0x10)) {
7187 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7188 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7189 vp9_param.p.bit_depth);
7190 return -1;
7191 }
7192
7193 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7194 ret = vp9_bufmgr_process(pbi, &vp9_param);
7195 if (!pbi->m_ins_flag)
7196 pbi->slice_idx++;
7197 } else {
7198 union param_u *params = &vp9_param;
7199 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7200 ret = vp9_alloc_mmu(pbi,
7201 cm->new_fb_idx,
7202 params->p.width,
7203 params->p.height,
7204 params->p.bit_depth,
7205 pbi->frame_mmu_map_addr);
7206 if (ret >= 0)
7207 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7208 else
7209 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7210 cm->new_fb_idx,
7211 ret);
7212 } else {
7213 ret = 0;
7214 }
7215 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7216 (params->p.height << 16) | params->p.width);
7217 }
7218 if (ret < 0) {
7219 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7220 ret);
7221 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7222 cm->show_frame = 0;
7223 if (pbi->mmu_enable)
7224 vp9_recycle_mmu_buf(pbi);
7225#ifdef MULTI_INSTANCE_SUPPORT
7226 if (pbi->m_ins_flag) {
7227 pbi->dec_result = DEC_RESULT_DONE;
7228#ifdef SUPPORT_FB_DECODING
7229 if (pbi->used_stage_buf_num == 0)
7230#endif
7231 amhevc_stop();
7232 vdec_schedule_work(&pbi->work);
7233 }
7234#endif
7235 return ret;
7236 } else if (ret == 0) {
7237 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7238 = &cm->cur_frame->buf;
7239 cur_pic_config->decode_idx = pbi->frame_count;
7240
7241 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7242 if (!pbi->m_ins_flag) {
7243 pbi->frame_count++;
7244 decode_frame_count[pbi->index]
7245 = pbi->frame_count;
7246 }
7247#ifdef MULTI_INSTANCE_SUPPORT
7248 if (pbi->chunk) {
7249 cur_pic_config->pts = pbi->chunk->pts;
7250 cur_pic_config->pts64 = pbi->chunk->pts64;
7251 }
7252#endif
7253 }
7254 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7255 config_pic_size(pbi, vp9_param.p.bit_depth);
7256
7257 if ((pbi->common.frame_type != KEY_FRAME)
7258 && (!pbi->common.intra_only)) {
7259 config_mc_buffer(pbi, vp9_param.p.bit_depth);
7260#ifdef SUPPORT_FB_DECODING
7261 if (pbi->used_stage_buf_num == 0)
7262#endif
7263 config_mpred_hw(pbi);
7264 } else {
7265#ifdef SUPPORT_FB_DECODING
7266 if (pbi->used_stage_buf_num == 0)
7267#endif
7268 clear_mpred_hw(pbi);
7269 }
7270#ifdef MCRCC_ENABLE
7271 if (mcrcc_cache_alg_flag)
7272 config_mcrcc_axi_hw_new(pbi);
7273 else
7274 config_mcrcc_axi_hw(pbi);
7275#endif
7276 config_sao_hw(pbi, &vp9_param);
7277
7278#ifdef VP9_LPF_LVL_UPDATE
7279 /*
7280 * Get loop filter related picture level parameters from Parser
7281 */
7282 pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7283 pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7284 for (i = 0; i < 4; i++)
7285 pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7286 for (i = 0; i < 2; i++)
7287 pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7288 pbi->default_filt_lvl = vp9_param.p.filter_level;
7289 pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7290 pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7291 for (i = 0; i < MAX_SEGMENTS; i++)
7292 pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7293 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7294 for (i = 0; i < MAX_SEGMENTS; i++)
7295 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7296 = (vp9_param.p.seg_lf_info[i]
7297 & 0x100) ? -(vp9_param.p.seg_lf_info[i]
7298 & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7299 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7300 /*Set pipeline mode*/
7301 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7302 /*dblk pipeline mode=1 for performance*/
7303 if (vp9_param.p.width >= 1280)
7304 lpf_data32 |= (0x1 << 4);
7305 else
7306 lpf_data32 &= ~(0x3 << 4);
7307 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7308 }
7309 /*
7310 * Update loop filter Thr/Lvl table for every frame
7311 */
7312 /*pr_info
7313 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7314 vp9_loop_filter_frame_init(pbi->seg_4lf,
7315 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7316#endif
7317 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7318 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7319 } else {
7320 pr_info("Skip search next start code\n");
7321 cm->prev_fb_idx = INVALID_IDX;
7322 /*skip, search next start code*/
7323 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7324 }
7325 pbi->process_state = PROC_STATE_DECODESLICE;
7326 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7327 if (pbi->last_put_idx < pbi->used_buf_num) {
7328 struct RefCntBuffer_s *frame_bufs =
7329 cm->buffer_pool->frame_bufs;
7330 int i = pbi->last_put_idx;
7331 /*free not used buffers.*/
7332 if ((frame_bufs[i].ref_count == 0) &&
7333 (frame_bufs[i].buf.vf_ref == 0) &&
7334 (frame_bufs[i].buf.index != -1)) {
7335 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7336 }
7337 pbi->last_put_idx = -1;
7338 }
7339 }
7340 return ret;
7341}
7342
7343static void fill_frame_info(struct VP9Decoder_s *pbi,
7344 struct PIC_BUFFER_CONFIG_s *frame,
7345 unsigned int framesize,
7346 unsigned int pts)
7347{
7348 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7349
7350 if (frame->slice_type == KEY_FRAME)
7351 vframe_qos->type = 1;
7352 else if (frame->slice_type == INTER_FRAME)
7353 vframe_qos->type = 2;
7354/*
7355#define SHOW_QOS_INFO
7356*/
7357 vframe_qos->size = framesize;
7358 vframe_qos->pts = pts;
7359#ifdef SHOW_QOS_INFO
7360 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7361#endif
7362 vframe_qos->max_mv = frame->max_mv;
7363 vframe_qos->avg_mv = frame->avg_mv;
7364 vframe_qos->min_mv = frame->min_mv;
7365#ifdef SHOW_QOS_INFO
7366 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7367 vframe_qos->max_mv,
7368 vframe_qos->avg_mv,
7369 vframe_qos->min_mv);
7370#endif
7371 vframe_qos->max_qp = frame->max_qp;
7372 vframe_qos->avg_qp = frame->avg_qp;
7373 vframe_qos->min_qp = frame->min_qp;
7374#ifdef SHOW_QOS_INFO
7375 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7376 vframe_qos->max_qp,
7377 vframe_qos->avg_qp,
7378 vframe_qos->min_qp);
7379#endif
7380 vframe_qos->max_skip = frame->max_skip;
7381 vframe_qos->avg_skip = frame->avg_skip;
7382 vframe_qos->min_skip = frame->min_skip;
7383#ifdef SHOW_QOS_INFO
7384 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7385 vframe_qos->max_skip,
7386 vframe_qos->avg_skip,
7387 vframe_qos->min_skip);
7388#endif
7389 vframe_qos->num++;
7390
7391 if (pbi->frameinfo_enable)
7392 vdec_fill_frame_info(vframe_qos, 1);
7393}
7394
7395/* only when we decoded one field or one frame,
7396we can call this function to get qos info*/
7397static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7398{
7399 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7400
7401 if (!frame)
7402 return;
7403
7404 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7405 unsigned char a[3];
7406 unsigned char i, j, t;
7407 unsigned long data;
7408
7409 data = READ_VREG(HEVC_MV_INFO);
7410 if (frame->slice_type == KEY_FRAME)
7411 data = 0;
7412 a[0] = data & 0xff;
7413 a[1] = (data >> 8) & 0xff;
7414 a[2] = (data >> 16) & 0xff;
7415
7416 for (i = 0; i < 3; i++) {
7417 for (j = i+1; j < 3; j++) {
7418 if (a[j] < a[i]) {
7419 t = a[j];
7420 a[j] = a[i];
7421 a[i] = t;
7422 } else if (a[j] == a[i]) {
7423 a[i]++;
7424 t = a[j];
7425 a[j] = a[i];
7426 a[i] = t;
7427 }
7428 }
7429 }
7430 frame->max_mv = a[2];
7431 frame->avg_mv = a[1];
7432 frame->min_mv = a[0];
7433
7434 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7435 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7436 data, a[0], a[1], a[2]);
7437
7438 data = READ_VREG(HEVC_QP_INFO);
7439 a[0] = data & 0x1f;
7440 a[1] = (data >> 8) & 0x3f;
7441 a[2] = (data >> 16) & 0x7f;
7442
7443 for (i = 0; i < 3; i++) {
7444 for (j = i+1; j < 3; j++) {
7445 if (a[j] < a[i]) {
7446 t = a[j];
7447 a[j] = a[i];
7448 a[i] = t;
7449 } else if (a[j] == a[i]) {
7450 a[i]++;
7451 t = a[j];
7452 a[j] = a[i];
7453 a[i] = t;
7454 }
7455 }
7456 }
7457 frame->max_qp = a[2];
7458 frame->avg_qp = a[1];
7459 frame->min_qp = a[0];
7460
7461 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7462 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7463 data, a[0], a[1], a[2]);
7464
7465 data = READ_VREG(HEVC_SKIP_INFO);
7466 a[0] = data & 0x1f;
7467 a[1] = (data >> 8) & 0x3f;
7468 a[2] = (data >> 16) & 0x7f;
7469
7470 for (i = 0; i < 3; i++) {
7471 for (j = i+1; j < 3; j++) {
7472 if (a[j] < a[i]) {
7473 t = a[j];
7474 a[j] = a[i];
7475 a[i] = t;
7476 } else if (a[j] == a[i]) {
7477 a[i]++;
7478 t = a[j];
7479 a[j] = a[i];
7480 a[i] = t;
7481 }
7482 }
7483 }
7484 frame->max_skip = a[2];
7485 frame->avg_skip = a[1];
7486 frame->min_skip = a[0];
7487
7488 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7489 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7490 data, a[0], a[1], a[2]);
7491 } else {
7492 uint32_t blk88_y_count;
7493 uint32_t blk88_c_count;
7494 uint32_t blk22_mv_count;
7495 uint32_t rdata32;
7496 int32_t mv_hi;
7497 int32_t mv_lo;
7498 uint32_t rdata32_l;
7499 uint32_t mvx_L0_hi;
7500 uint32_t mvy_L0_hi;
7501 uint32_t mvx_L1_hi;
7502 uint32_t mvy_L1_hi;
7503 int64_t value;
7504 uint64_t temp_value;
7505 int pic_number = frame->decode_idx;
7506
7507 frame->max_mv = 0;
7508 frame->avg_mv = 0;
7509 frame->min_mv = 0;
7510
7511 frame->max_skip = 0;
7512 frame->avg_skip = 0;
7513 frame->min_skip = 0;
7514
7515 frame->max_qp = 0;
7516 frame->avg_qp = 0;
7517 frame->min_qp = 0;
7518
7519 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7520 frame->slice_type,
7521 pic_number);
7522
7523 /* set rd_idx to 0 */
7524 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7525
7526 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7527 if (blk88_y_count == 0) {
7528
7529 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7530 "[Picture %d Quality] NO Data yet.\n",
7531 pic_number);
7532
7533 /* reset all counts */
7534 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7535 return;
7536 }
7537 /* qp_y_sum */
7538 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7539
7540 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7541 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7542 pic_number, rdata32/blk88_y_count,
7543 rdata32, blk88_y_count);
7544
7545 frame->avg_qp = rdata32/blk88_y_count;
7546 /* intra_y_count */
7547 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7548
7549 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7550 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7551 pic_number, rdata32*100/blk88_y_count,
7552 '%', rdata32);
7553
7554 /* skipped_y_count */
7555 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7556
7557 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7558 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7559 pic_number, rdata32*100/blk88_y_count,
7560 '%', rdata32);
7561
7562 frame->avg_skip = rdata32*100/blk88_y_count;
7563 /* coeff_non_zero_y_count */
7564 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7565
7566 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7567 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7568 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7569 '%', rdata32);
7570
7571 /* blk66_c_count */
7572 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7573 if (blk88_c_count == 0) {
7574 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7575 "[Picture %d Quality] NO Data yet.\n",
7576 pic_number);
7577 /* reset all counts */
7578 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7579 return;
7580 }
7581 /* qp_c_sum */
7582 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7583
7584 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7585 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7586 pic_number, rdata32/blk88_c_count,
7587 rdata32, blk88_c_count);
7588
7589 /* intra_c_count */
7590 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7591
7592 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7593 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7594 pic_number, rdata32*100/blk88_c_count,
7595 '%', rdata32);
7596
7597 /* skipped_cu_c_count */
7598 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7599
7600 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7601 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7602 pic_number, rdata32*100/blk88_c_count,
7603 '%', rdata32);
7604
7605 /* coeff_non_zero_c_count */
7606 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7607
7608 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7609 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7610 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7611 '%', rdata32);
7612
7613 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7614 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7615 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7616
7617 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7618 "[Picture %d Quality] Y QP min : %d\n",
7619 pic_number, (rdata32>>0)&0xff);
7620
7621 frame->min_qp = (rdata32>>0)&0xff;
7622
7623 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7624 "[Picture %d Quality] Y QP max : %d\n",
7625 pic_number, (rdata32>>8)&0xff);
7626
7627 frame->max_qp = (rdata32>>8)&0xff;
7628
7629 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7630 "[Picture %d Quality] C QP min : %d\n",
7631 pic_number, (rdata32>>16)&0xff);
7632 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7633 "[Picture %d Quality] C QP max : %d\n",
7634 pic_number, (rdata32>>24)&0xff);
7635
7636 /* blk22_mv_count */
7637 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7638 if (blk22_mv_count == 0) {
7639 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7640 "[Picture %d Quality] NO MV Data yet.\n",
7641 pic_number);
7642 /* reset all counts */
7643 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7644 return;
7645 }
7646 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7647 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7648 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7649 /* should all be 0x00 or 0xff */
7650 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7651 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7652 pic_number, rdata32);
7653
7654 mvx_L0_hi = ((rdata32>>0)&0xff);
7655 mvy_L0_hi = ((rdata32>>8)&0xff);
7656 mvx_L1_hi = ((rdata32>>16)&0xff);
7657 mvy_L1_hi = ((rdata32>>24)&0xff);
7658
7659 /* mvx_L0_count[31:0] */
7660 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7661 temp_value = mvx_L0_hi;
7662 temp_value = (temp_value << 32) | rdata32_l;
7663
7664 if (mvx_L0_hi & 0x80)
7665 value = 0xFFFFFFF000000000 | temp_value;
7666 else
7667 value = temp_value;
7668
7669 value = div_s64(value, blk22_mv_count);
7670
7671 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7672 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7673 pic_number, (int)value,
7674 value, blk22_mv_count);
7675
7676 frame->avg_mv = value;
7677
7678 /* mvy_L0_count[31:0] */
7679 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7680 temp_value = mvy_L0_hi;
7681 temp_value = (temp_value << 32) | rdata32_l;
7682
7683 if (mvy_L0_hi & 0x80)
7684 value = 0xFFFFFFF000000000 | temp_value;
7685 else
7686 value = temp_value;
7687
7688 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7689 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7690 pic_number, rdata32_l/blk22_mv_count,
7691 value, blk22_mv_count);
7692
7693 /* mvx_L1_count[31:0] */
7694 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7695 temp_value = mvx_L1_hi;
7696 temp_value = (temp_value << 32) | rdata32_l;
7697 if (mvx_L1_hi & 0x80)
7698 value = 0xFFFFFFF000000000 | temp_value;
7699 else
7700 value = temp_value;
7701
7702 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7703 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
7704 pic_number, rdata32_l/blk22_mv_count,
7705 value, blk22_mv_count);
7706
7707 /* mvy_L1_count[31:0] */
7708 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7709 temp_value = mvy_L1_hi;
7710 temp_value = (temp_value << 32) | rdata32_l;
7711 if (mvy_L1_hi & 0x80)
7712 value = 0xFFFFFFF000000000 | temp_value;
7713 else
7714 value = temp_value;
7715
7716 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7717 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
7718 pic_number, rdata32_l/blk22_mv_count,
7719 value, blk22_mv_count);
7720
7721 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
7722 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7723 mv_hi = (rdata32>>16)&0xffff;
7724 if (mv_hi & 0x8000)
7725 mv_hi = 0x8000 - mv_hi;
7726
7727 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7728 "[Picture %d Quality] MVX_L0 MAX : %d\n",
7729 pic_number, mv_hi);
7730
7731 frame->max_mv = mv_hi;
7732
7733 mv_lo = (rdata32>>0)&0xffff;
7734 if (mv_lo & 0x8000)
7735 mv_lo = 0x8000 - mv_lo;
7736
7737 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7738 "[Picture %d Quality] MVX_L0 MIN : %d\n",
7739 pic_number, mv_lo);
7740
7741 frame->min_mv = mv_lo;
7742
7743 /* {mvy_L0_max, mvy_L0_min} */
7744 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7745 mv_hi = (rdata32>>16)&0xffff;
7746 if (mv_hi & 0x8000)
7747 mv_hi = 0x8000 - mv_hi;
7748
7749 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7750 "[Picture %d Quality] MVY_L0 MAX : %d\n",
7751 pic_number, mv_hi);
7752
7753 mv_lo = (rdata32>>0)&0xffff;
7754 if (mv_lo & 0x8000)
7755 mv_lo = 0x8000 - mv_lo;
7756
7757 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7758 "[Picture %d Quality] MVY_L0 MIN : %d\n",
7759 pic_number, mv_lo);
7760
7761 /* {mvx_L1_max, mvx_L1_min} */
7762 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7763 mv_hi = (rdata32>>16)&0xffff;
7764 if (mv_hi & 0x8000)
7765 mv_hi = 0x8000 - mv_hi;
7766
7767 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7768 "[Picture %d Quality] MVX_L1 MAX : %d\n",
7769 pic_number, mv_hi);
7770
7771 mv_lo = (rdata32>>0)&0xffff;
7772 if (mv_lo & 0x8000)
7773 mv_lo = 0x8000 - mv_lo;
7774
7775 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7776 "[Picture %d Quality] MVX_L1 MIN : %d\n",
7777 pic_number, mv_lo);
7778
7779 /* {mvy_L1_max, mvy_L1_min} */
7780 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7781 mv_hi = (rdata32>>16)&0xffff;
7782 if (mv_hi & 0x8000)
7783 mv_hi = 0x8000 - mv_hi;
7784
7785 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7786 "[Picture %d Quality] MVY_L1 MAX : %d\n",
7787 pic_number, mv_hi);
7788
7789 mv_lo = (rdata32>>0)&0xffff;
7790 if (mv_lo & 0x8000)
7791 mv_lo = 0x8000 - mv_lo;
7792
7793 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7794 "[Picture %d Quality] MVY_L1 MIN : %d\n",
7795 pic_number, mv_lo);
7796
7797 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
7798
7799 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7800 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
7801 pic_number, rdata32);
7802
7803 /* reset all counts */
7804 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7805 }
7806}
7807
7808static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
7809{
7810 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
7811 unsigned int dec_status = pbi->dec_status;
7812 int i;
7813
7814 /*if (pbi->wait_buf)
7815 * pr_info("set wait_buf to 0\r\n");
7816 */
7817 if (pbi->eos)
7818 return IRQ_HANDLED;
7819 pbi->wait_buf = 0;
7820#ifdef MULTI_INSTANCE_SUPPORT
7821#ifdef SUPPORT_FB_DECODING
7822#ifdef FB_DECODING_TEST_SCHEDULE
7823 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
7824 dec_status = HEVC_DECPIC_DATA_DONE;
7825 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
7826 && dec_status == HEVC_DECPIC_DATA_DONE)
7827 dec_status = HEVC_S2_DECODING_DONE;
7828 pbi->s1_test_cmd = TEST_SET_NONE;
7829#else
7830 /*if (irq != VDEC_IRQ_0)
7831 dec_status = HEVC_S2_DECODING_DONE;*/
7832#endif
7833 if (dec_status == HEVC_S2_DECODING_DONE) {
7834 pbi->dec_result = DEC_RESULT_DONE;
7835 vdec_schedule_work(&pbi->work);
7836#ifdef FB_DECODING_TEST_SCHEDULE
7837 amhevc_stop();
7838 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
7839 vdec_schedule_work(&pbi->s1_work);
7840#endif
7841 } else
7842#endif
7843 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
7844 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
7845 (dec_status == HEVC_DECODE_BUFEMPTY)
7846 ) {
7847 if (pbi->m_ins_flag) {
7848 reset_process_time(pbi);
7849 if (!vdec_frame_based(hw_to_vdec(pbi)))
7850 dec_again_process(pbi);
7851 else {
7852 pbi->dec_result = DEC_RESULT_GET_DATA;
7853 vdec_schedule_work(&pbi->work);
7854 }
7855 }
7856 pbi->process_busy = 0;
7857 return IRQ_HANDLED;
7858 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
7859 if (pbi->m_ins_flag) {
7860 get_picture_qos_info(pbi);
7861#ifdef SUPPORT_FB_DECODING
7862 if (pbi->used_stage_buf_num > 0) {
7863 reset_process_time(pbi);
7864 inc_s1_pos(pbi);
7865 trigger_schedule(pbi);
7866#ifdef FB_DECODING_TEST_SCHEDULE
7867 pbi->s1_test_cmd = TEST_SET_S2_DONE;
7868#else
7869 amhevc_stop();
7870 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
7871 vdec_schedule_work(&pbi->s1_work);
7872#endif
7873 } else
7874#endif
7875 {
7876 reset_process_time(pbi);
7877 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
7878 vp9_bufmgr_postproc(pbi);
7879
7880 pbi->dec_result = DEC_RESULT_DONE;
7881 amhevc_stop();
7882 if (mcrcc_cache_alg_flag)
7883 dump_hit_rate(pbi);
7884 vdec_schedule_work(&pbi->work);
7885 }
7886 } else {
7887 if (pbi->low_latency_flag) {
7888 vp9_bufmgr_postproc(pbi);
7889 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
7890#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7891 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
7892 if (debug & PRINT_FLAG_VDEC_DETAIL)
7893 pr_info("%s VP9 frame done \n", __func__);
7894#endif
7895 }
7896 }
7897
7898 pbi->process_busy = 0;
7899 return IRQ_HANDLED;
7900 }
7901#endif
7902
7903 if (dec_status == VP9_EOS) {
7904#ifdef MULTI_INSTANCE_SUPPORT
7905 if (pbi->m_ins_flag)
7906 reset_process_time(pbi);
7907#endif
7908
7909 pr_info("VP9_EOS, flush buffer\r\n");
7910
7911 vp9_bufmgr_postproc(pbi);
7912
7913 pr_info("send VP9_10B_DISCARD_NAL\r\n");
7914 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7915 pbi->process_busy = 0;
7916#ifdef MULTI_INSTANCE_SUPPORT
7917 if (pbi->m_ins_flag) {
7918 pbi->dec_result = DEC_RESULT_DONE;
7919 amhevc_stop();
7920 vdec_schedule_work(&pbi->work);
7921 }
7922#endif
7923 return IRQ_HANDLED;
7924 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
7925 pr_info("vp9 decode oversize !!\n");
7926 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
7927 VP9_DEBUG_DIS_SYS_ERROR_PROC);
7928 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7929#ifdef MULTI_INSTANCE_SUPPORT
7930 if (pbi->m_ins_flag)
7931 reset_process_time(pbi);
7932#endif
7933 return IRQ_HANDLED;
7934 }
7935
7936 if (dec_status != VP9_HEAD_PARSER_DONE) {
7937 pbi->process_busy = 0;
7938 return IRQ_HANDLED;
7939 }
7940
7941
7942#ifdef MULTI_INSTANCE_SUPPORT
7943#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7944 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
7945 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
7946 if (debug & PRINT_FLAG_VDEC_DETAIL)
7947 pr_info("%s VP9 frame header found \n", __func__);
7948 }
7949#endif
7950 if (pbi->m_ins_flag)
7951 reset_process_time(pbi);
7952#endif
7953 if (pbi->process_state != PROC_STATE_SENDAGAIN
7954#ifdef SUPPORT_FB_DECODING
7955 && pbi->used_stage_buf_num == 0
7956#endif
7957 ) {
7958 if (pbi->mmu_enable)
7959 vp9_recycle_mmu_buf_tail(pbi);
7960
7961
7962 if (pbi->frame_count > 0)
7963 vp9_bufmgr_postproc(pbi);
7964 }
7965
7966 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
7967 get_rpm_param(&vp9_param);
7968 } else {
7969#ifdef SUPPORT_FB_DECODING
7970 if (pbi->used_stage_buf_num > 0) {
7971 reset_process_time(pbi);
7972 get_s1_buf(pbi);
7973
7974 if (get_mv_buf(pbi,
7975 &pbi->s1_mv_buf_index,
7976 &pbi->s1_mpred_mv_wr_start_addr
7977 ) < 0) {
7978 vp9_print(pbi, 0,
7979 "%s: Error get_mv_buf fail\n",
7980 __func__);
7981 }
7982
7983 if (pbi->s1_buf == NULL) {
7984 vp9_print(pbi, 0,
7985 "%s: Error get_s1_buf fail\n",
7986 __func__);
7987 pbi->process_busy = 0;
7988 return IRQ_HANDLED;
7989 }
7990
7991 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
7992 int ii;
7993 for (ii = 0; ii < 4; ii++) {
7994 pbi->s1_buf->rpm[i + 3 - ii] =
7995 pbi->rpm_ptr[i + 3 - ii];
7996 pbi->s1_param.l.data[i + ii] =
7997 pbi->rpm_ptr[i + 3 - ii];
7998 }
7999 }
8000
8001 mpred_process(pbi);
8002#ifdef FB_DECODING_TEST_SCHEDULE
8003 pbi->dec_s1_result =
8004 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8005 vdec_schedule_work(&pbi->s1_work);
8006#else
8007 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8008 pbi->stage_mmu_map_phy_addr +
8009 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8010
8011 start_s1_decoding(pbi);
8012#endif
8013 start_process_time(pbi);
8014 pbi->process_busy = 0;
8015 return IRQ_HANDLED;
8016 } else
8017#endif
8018 {
8019 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8020 int ii;
8021 for (ii = 0; ii < 4; ii++)
8022 vp9_param.l.data[i + ii] =
8023 pbi->rpm_ptr[i + 3 - ii];
8024 }
8025 }
8026 }
8027
8028 continue_decoding(pbi);
8029 pbi->postproc_done = 0;
8030 pbi->process_busy = 0;
8031
8032#ifdef MULTI_INSTANCE_SUPPORT
8033 if (pbi->m_ins_flag)
8034 start_process_time(pbi);
8035#endif
8036
8037 return IRQ_HANDLED;
8038}
8039
8040static irqreturn_t vvp9_isr(int irq, void *data)
8041{
8042 int i;
8043 unsigned int dec_status;
8044 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8045 unsigned int adapt_prob_status;
8046 struct VP9_Common_s *const cm = &pbi->common;
8047 uint debug_tag;
8048
8049 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8050
8051 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8052 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8053 if (!pbi)
8054 return IRQ_HANDLED;
8055 if (pbi->init_flag == 0)
8056 return IRQ_HANDLED;
8057 if (pbi->process_busy)/*on process.*/
8058 return IRQ_HANDLED;
8059 pbi->dec_status = dec_status;
8060 pbi->process_busy = 1;
8061 if (debug & VP9_DEBUG_BUFMGR)
8062 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8063 irq,
8064 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8065 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8066 READ_VREG(HEVC_STREAM_START_ADDR),
8067 READ_VREG(HEVC_STREAM_END_ADDR),
8068 READ_VREG(HEVC_STREAM_LEVEL),
8069 READ_VREG(HEVC_STREAM_WR_PTR),
8070 READ_VREG(HEVC_STREAM_RD_PTR)
8071 );
8072#ifdef SUPPORT_FB_DECODING
8073 /*if (irq != VDEC_IRQ_0)
8074 return IRQ_WAKE_THREAD;*/
8075#endif
8076
8077 debug_tag = READ_HREG(DEBUG_REG1);
8078 if (debug_tag & 0x10000) {
8079 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8080 for (i = 0; i < 0x400; i += 4) {
8081 int ii;
8082 if ((i & 0xf) == 0)
8083 pr_info("%03x: ", i);
8084 for (ii = 0; ii < 4; ii++) {
8085 pr_info("%04x ",
8086 pbi->lmem_ptr[i + 3 - ii]);
8087 }
8088 if (((i + ii) & 0xf) == 0)
8089 pr_info("\n");
8090 }
8091
8092 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8093 (udebug_pause_decode_idx == 0 ||
8094 udebug_pause_decode_idx == pbi->slice_idx) &&
8095 (udebug_pause_val == 0 ||
8096 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8097 pbi->ucode_pause_pos = udebug_pause_pos;
8098 else if (debug_tag & 0x20000)
8099 pbi->ucode_pause_pos = 0xffffffff;
8100 if (pbi->ucode_pause_pos)
8101 reset_process_time(pbi);
8102 else
8103 WRITE_HREG(DEBUG_REG1, 0);
8104 } else if (debug_tag != 0) {
8105 pr_info(
8106 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8107 READ_HREG(DEBUG_REG2),
8108 READ_VREG(HEVC_PARSER_LCU_START));
8109 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8110 (udebug_pause_decode_idx == 0 ||
8111 udebug_pause_decode_idx == pbi->slice_idx) &&
8112 (udebug_pause_val == 0 ||
8113 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8114 pbi->ucode_pause_pos = udebug_pause_pos;
8115 if (pbi->ucode_pause_pos)
8116 reset_process_time(pbi);
8117 else
8118 WRITE_HREG(DEBUG_REG1, 0);
8119 pbi->process_busy = 0;
8120 return IRQ_HANDLED;
8121 }
8122
8123#ifdef MULTI_INSTANCE_SUPPORT
8124 if (!pbi->m_ins_flag) {
8125#endif
8126 if (pbi->error_flag == 1) {
8127 pbi->error_flag = 2;
8128 pbi->process_busy = 0;
8129 return IRQ_HANDLED;
8130 } else if (pbi->error_flag == 3) {
8131 pbi->process_busy = 0;
8132 return IRQ_HANDLED;
8133 }
8134
8135 if (get_free_buf_count(pbi) <= 0) {
8136 /*
8137 if (pbi->wait_buf == 0)
8138 pr_info("set wait_buf to 1\r\n");
8139 */
8140 pbi->wait_buf = 1;
8141 pbi->process_busy = 0;
8142 return IRQ_HANDLED;
8143 }
8144#ifdef MULTI_INSTANCE_SUPPORT
8145 }
8146#endif
8147 if ((adapt_prob_status & 0xff) == 0xfd) {
8148 /*VP9_REQ_ADAPT_PROB*/
8149 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8150 uint8_t *prev_prob_b =
8151 ((uint8_t *)pbi->prob_buffer_addr) +
8152 ((adapt_prob_status >> 8) * 0x1000);
8153 uint8_t *cur_prob_b =
8154 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8155 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8156#ifdef MULTI_INSTANCE_SUPPORT
8157 if (pbi->m_ins_flag)
8158 reset_process_time(pbi);
8159#endif
8160 adapt_coef_probs(pbi->pic_count,
8161 (cm->last_frame_type == KEY_FRAME),
8162 pre_fc, (adapt_prob_status >> 8),
8163 (unsigned int *)prev_prob_b,
8164 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8165
8166 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8167 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8168 pbi->pic_count += 1;
8169#ifdef MULTI_INSTANCE_SUPPORT
8170 if (pbi->m_ins_flag)
8171 start_process_time(pbi);
8172#endif
8173
8174 /*return IRQ_HANDLED;*/
8175 }
8176 return IRQ_WAKE_THREAD;
8177}
8178
8179static void vp9_set_clk(struct work_struct *work)
8180{
8181 struct VP9Decoder_s *pbi = container_of(work,
8182 struct VP9Decoder_s, set_clk_work);
8183 int fps = 96000 / pbi->frame_dur;
8184
8185 if (hevc_source_changed(VFORMAT_VP9,
8186 frame_width, frame_height, fps) > 0)
8187 pbi->saved_resolution = frame_width *
8188 frame_height * fps;
8189}
8190
8191static void vvp9_put_timer_func(unsigned long arg)
8192{
8193 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8194 struct timer_list *timer = &pbi->timer;
8195 uint8_t empty_flag;
8196 unsigned int buf_level;
8197
8198 enum receviver_start_e state = RECEIVER_INACTIVE;
8199
8200 if (pbi->m_ins_flag) {
8201 if (hw_to_vdec(pbi)->next_status
8202 == VDEC_STATUS_DISCONNECTED) {
8203#ifdef SUPPORT_FB_DECODING
8204 if (pbi->run2_busy)
8205 return;
8206
8207 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8208 vdec_schedule_work(&pbi->s1_work);
8209#endif
8210 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8211 vdec_schedule_work(&pbi->work);
8212 pr_debug(
8213 "vdec requested to be disconnected\n");
8214 return;
8215 }
8216 }
8217 if (pbi->init_flag == 0) {
8218 if (pbi->stat & STAT_TIMER_ARM) {
8219 timer->expires = jiffies + PUT_INTERVAL;
8220 add_timer(&pbi->timer);
8221 }
8222 return;
8223 }
8224 if (pbi->m_ins_flag == 0) {
8225 if (vf_get_receiver(pbi->provider_name)) {
8226 state =
8227 vf_notify_receiver(pbi->provider_name,
8228 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8229 NULL);
8230 if ((state == RECEIVER_STATE_NULL)
8231 || (state == RECEIVER_STATE_NONE))
8232 state = RECEIVER_INACTIVE;
8233 } else
8234 state = RECEIVER_INACTIVE;
8235
8236 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8237 /* error watchdog */
8238 if (empty_flag == 0) {
8239 /* decoder has input */
8240 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8241
8242 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8243 /* receiver has no buffer to recycle */
8244 if ((state == RECEIVER_INACTIVE) &&
8245 (kfifo_is_empty(&pbi->display_q) &&
8246 buf_level > 0x200)
8247 ) {
8248 WRITE_VREG
8249 (HEVC_ASSIST_MBOX0_IRQ_REG,
8250 0x1);
8251 }
8252 }
8253
8254 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8255 /* receiver has no buffer to recycle */
8256 /*if ((state == RECEIVER_INACTIVE) &&
8257 * (kfifo_is_empty(&pbi->display_q))) {
8258 *pr_info("vp9 something error,need reset\n");
8259 *}
8260 */
8261 }
8262 }
8263 }
8264#ifdef MULTI_INSTANCE_SUPPORT
8265 else {
8266 if (
8267 (decode_timeout_val > 0) &&
8268 (pbi->start_process_time > 0) &&
8269 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8270 > decode_timeout_val)
8271 ) {
8272 int current_lcu_idx =
8273 READ_VREG(HEVC_PARSER_LCU_START)
8274 & 0xffffff;
8275 if (pbi->last_lcu_idx == current_lcu_idx) {
8276 if (pbi->decode_timeout_count > 0)
8277 pbi->decode_timeout_count--;
8278 if (pbi->decode_timeout_count == 0) {
8279 if (input_frame_based(
8280 hw_to_vdec(pbi)) ||
8281 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8282 timeout_process(pbi);
8283 else {
8284 vp9_print(pbi, 0,
8285 "timeout & empty, again\n");
8286 dec_again_process(pbi);
8287 }
8288 }
8289 } else {
8290 start_process_time(pbi);
8291 pbi->last_lcu_idx = current_lcu_idx;
8292 }
8293 }
8294 }
8295#endif
8296
8297 if ((pbi->ucode_pause_pos != 0) &&
8298 (pbi->ucode_pause_pos != 0xffffffff) &&
8299 udebug_pause_pos != pbi->ucode_pause_pos) {
8300 pbi->ucode_pause_pos = 0;
8301 WRITE_HREG(DEBUG_REG1, 0);
8302 }
8303#ifdef MULTI_INSTANCE_SUPPORT
8304 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8305 pr_info(
8306 "Force Send Again\r\n");
8307 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8308 reset_process_time(pbi);
8309 pbi->dec_result = DEC_RESULT_AGAIN;
8310 if (pbi->process_state ==
8311 PROC_STATE_DECODESLICE) {
8312 if (pbi->mmu_enable)
8313 vp9_recycle_mmu_buf(pbi);
8314 pbi->process_state =
8315 PROC_STATE_SENDAGAIN;
8316 }
8317 amhevc_stop();
8318
8319 vdec_schedule_work(&pbi->work);
8320 }
8321
8322 if (debug & VP9_DEBUG_DUMP_DATA) {
8323 debug &= ~VP9_DEBUG_DUMP_DATA;
8324 vp9_print(pbi, 0,
8325 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8326 __func__,
8327 pbi->chunk->size,
8328 pbi->chunk->offset,
8329 get_data_check_sum(pbi, pbi->chunk->size)
8330 );
8331 dump_data(pbi, pbi->chunk->size);
8332 }
8333#endif
8334 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8335 dump_pic_list(pbi);
8336 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8337 }
8338 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8339 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8340 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8341 }
8342 /*if (debug & VP9_DEBUG_HW_RESET) {
8343 }*/
8344
8345 if (radr != 0) {
8346 if (rval != 0) {
8347 WRITE_VREG(radr, rval);
8348 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8349 } else
8350 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8351 rval = 0;
8352 radr = 0;
8353 }
8354 if (pop_shorts != 0) {
8355 int i;
8356 u32 sum = 0;
8357
8358 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8359 for (i = 0; i < pop_shorts; i++) {
8360 u32 data =
8361 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8362 WRITE_HREG(HEVC_SHIFT_COMMAND,
8363 (1<<7)|16);
8364 if ((i & 0xf) == 0)
8365 pr_info("%04x:", i);
8366 pr_info("%04x ", data);
8367 if (((i + 1) & 0xf) == 0)
8368 pr_info("\r\n");
8369 sum += data;
8370 }
8371 pr_info("\r\nsum = %x\r\n", sum);
8372 pop_shorts = 0;
8373 }
8374 if (dbg_cmd != 0) {
8375 if (dbg_cmd == 1) {
8376 u32 disp_laddr;
8377
8378 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8379 get_double_write_mode(pbi) == 0) {
8380 disp_laddr =
8381 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8382 } else {
8383 struct canvas_s cur_canvas;
8384
8385 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8386 & 0xff), &cur_canvas);
8387 disp_laddr = cur_canvas.addr;
8388 }
8389 pr_info("current displayed buffer address %x\r\n",
8390 disp_laddr);
8391 }
8392 dbg_cmd = 0;
8393 }
8394 /*don't changed at start.*/
8395 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8396 pbi->frame_dur > 0 && pbi->saved_resolution !=
8397 frame_width * frame_height *
8398 (96000 / pbi->frame_dur))
8399 vdec_schedule_work(&pbi->set_clk_work);
8400
8401 timer->expires = jiffies + PUT_INTERVAL;
8402 add_timer(timer);
8403}
8404
8405
8406int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8407{
8408 struct VP9Decoder_s *vp9 =
8409 (struct VP9Decoder_s *)vdec->private;
8410
8411 if (!vp9)
8412 return -1;
8413
8414 vstatus->frame_width = frame_width;
8415 vstatus->frame_height = frame_height;
8416 if (vp9->frame_dur != 0)
8417 vstatus->frame_rate = 96000 / vp9->frame_dur;
8418 else
8419 vstatus->frame_rate = -1;
8420 vstatus->error_count = 0;
8421 vstatus->status = vp9->stat | vp9->fatal_error;
8422 vstatus->frame_dur = vp9->frame_dur;
8423#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8424 vstatus->bit_rate = gvs->bit_rate;
8425 vstatus->frame_data = gvs->frame_data;
8426 vstatus->total_data = gvs->total_data;
8427 vstatus->frame_count = gvs->frame_count;
8428 vstatus->error_frame_count = gvs->error_frame_count;
8429 vstatus->drop_frame_count = gvs->drop_frame_count;
8430 vstatus->total_data = gvs->total_data;
8431 vstatus->samp_cnt = gvs->samp_cnt;
8432 vstatus->offset = gvs->offset;
8433 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8434 "%s", DRIVER_NAME);
8435#endif
8436 return 0;
8437}
8438
8439int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8440{
8441 is_reset = isreset;
8442 return 0;
8443}
8444
8445#if 0
8446static void VP9_DECODE_INIT(void)
8447{
8448 /* enable vp9 clocks */
8449 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8450 /* *************************************************************** */
8451 /* Power ON HEVC */
8452 /* *************************************************************** */
8453 /* Powerup HEVC */
8454 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8455 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8456 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8457 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8458 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8459 /* remove isolations */
8460 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8461 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8462
8463}
8464#endif
8465
8466static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8467{
8468 unsigned int data32;
8469 /* VP9_DECODE_INIT(); */
8470 vp9_config_work_space_hw(pbi, mask);
8471 if (mask & HW_MASK_BACK)
8472 init_pic_list_hw(pbi);
8473
8474 vp9_init_decoder_hw(pbi, mask);
8475
8476#ifdef VP9_LPF_LVL_UPDATE
8477 if (mask & HW_MASK_BACK)
8478 vp9_loop_filter_init(pbi);
8479#endif
8480
8481 if ((mask & HW_MASK_FRONT) == 0)
8482 return;
8483#if 1
8484 if (debug & VP9_DEBUG_BUFMGR_MORE)
8485 pr_info("%s\n", __func__);
8486 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8487 data32 = data32 |
8488 (1 << 0)/*stream_fetch_enable*/
8489 ;
8490 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8491
8492 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8493 if (debug & VP9_DEBUG_BUFMGR)
8494 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8495 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8496 data32 = data32 |
8497 (1 << 29) // stream_fifo_hole
8498 ;
8499 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8500 }
8501#if 0
8502 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8503 if (data32 != 0x00000100) {
8504 pr_info("vp9 prot init error %d\n", __LINE__);
8505 return;
8506 }
8507 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8508 if (data32 != 0x00000300) {
8509 pr_info("vp9 prot init error %d\n", __LINE__);
8510 return;
8511 }
8512 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8513 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8514 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8515 if (data32 != 0x12345678) {
8516 pr_info("vp9 prot init error %d\n", __LINE__);
8517 return;
8518 }
8519 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8520 if (data32 != 0x9abcdef0) {
8521 pr_info("vp9 prot init error %d\n", __LINE__);
8522 return;
8523 }
8524#endif
8525 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8526 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8527#endif
8528
8529
8530
8531 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8532
8533 /* WRITE_VREG(HEVC_MPSR, 1); */
8534
8535 /* clear mailbox interrupt */
8536 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8537
8538 /* enable mailbox interrupt */
8539 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8540
8541 /* disable PSCALE for hardware sharing */
8542 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8543
8544 WRITE_VREG(DEBUG_REG1, 0x0);
8545 /*check vps/sps/pps/i-slice in ucode*/
8546 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8547
8548 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8549#ifdef SUPPORT_FB_DECODING
8550#ifndef FB_DECODING_TEST_SCHEDULE
8551 if (pbi->used_stage_buf_num > 0) {
8552 if (mask & HW_MASK_FRONT) {
8553 data32 = READ_VREG(
8554 HEVC_ASSIST_HED_FB_W_CTL);
8555 data32 = data32 |
8556 (1 << 0) /*hed_fb_wr_en*/
8557 ;
8558 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8559 data32);
8560 }
8561 if (mask & HW_MASK_BACK) {
8562 data32 = READ_VREG(
8563 HEVC_ASSIST_HED_FB_R_CTL);
8564 while (data32 & (1 << 7)) {
8565 /*wait finish*/
8566 data32 = READ_VREG(
8567 HEVC_ASSIST_HED_FB_R_CTL);
8568 }
8569 data32 &= (~(0x1 << 0));
8570 /*hed_fb_rd_addr_auto_rd*/
8571 data32 &= (~(0x1 << 1));
8572 /*rd_id = 0, hed_rd_map_auto_halt_num,
8573 after wr 2 ready, then start reading*/
8574 data32 |= (0x2 << 16);
8575 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8576 data32);
8577
8578 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8579 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8580 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8581 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8582 data32);
8583 }
8584
8585 }
8586#endif
8587#endif
8588}
8589
8590static int vvp9_local_init(struct VP9Decoder_s *pbi)
8591{
8592 int i;
8593 int ret;
8594 int width, height;
8595 if (alloc_lf_buf(pbi) < 0)
8596 return -1;
8597
8598 pbi->gvs = vzalloc(sizeof(struct vdec_info));
8599 if (NULL == pbi->gvs) {
8600 pr_info("the struct of vdec status malloc failed.\n");
8601 return -1;
8602 }
8603#ifdef DEBUG_PTS
8604 pbi->pts_missed = 0;
8605 pbi->pts_hit = 0;
8606#endif
8607 pbi->new_frame_displayed = 0;
8608 pbi->last_put_idx = -1;
8609 pbi->saved_resolution = 0;
8610 pbi->get_frame_dur = false;
8611 on_no_keyframe_skiped = 0;
8612 pbi->duration_from_pts_done = 0;
8613 pbi->vp9_first_pts_ready = 0;
8614 pbi->frame_cnt_window = 0;
8615 width = pbi->vvp9_amstream_dec_info.width;
8616 height = pbi->vvp9_amstream_dec_info.height;
8617 pbi->frame_dur =
8618 (pbi->vvp9_amstream_dec_info.rate ==
8619 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8620 if (width && height)
8621 pbi->frame_ar = height * 0x100 / width;
8622/*
8623 *TODO:FOR VERSION
8624 */
8625 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8626 0, width, height, pbi->frame_dur);
8627
8628 if (pbi->frame_dur == 0)
8629 pbi->frame_dur = 96000 / 24;
8630
8631 INIT_KFIFO(pbi->display_q);
8632 INIT_KFIFO(pbi->newframe_q);
8633
8634
8635 for (i = 0; i < VF_POOL_SIZE; i++) {
8636 const struct vframe_s *vf = &pbi->vfpool[i];
8637
8638 pbi->vfpool[i].index = -1;
8639 kfifo_put(&pbi->newframe_q, vf);
8640 }
8641
8642
8643 ret = vp9_local_init(pbi);
8644
8645 if (!pbi->pts_unstable) {
8646 pbi->pts_unstable =
8647 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8648 pr_info("set pts unstable\n");
8649 }
8650
8651 return ret;
8652}
8653
8654
8655#ifdef MULTI_INSTANCE_SUPPORT
8656static s32 vvp9_init(struct vdec_s *vdec)
8657{
8658 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8659#else
8660static s32 vvp9_init(struct VP9Decoder_s *pbi)
8661{
8662#endif
8663 int ret;
8664 int fw_size = 0x1000 * 16;
8665 struct firmware_s *fw = NULL;
8666
8667 pbi->stat |= STAT_TIMER_INIT;
8668
8669 if (vvp9_local_init(pbi) < 0)
8670 return -EBUSY;
8671
8672 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8673 if (IS_ERR_OR_NULL(fw))
8674 return -ENOMEM;
8675
8676 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8677 pr_err("get firmware fail.\n");
8678 vfree(fw);
8679 return -1;
8680 }
8681
8682 fw->len = fw_size;
8683
8684 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
8685 init_timer(&pbi->timer);
8686
8687#ifdef MULTI_INSTANCE_SUPPORT
8688 if (pbi->m_ins_flag) {
8689 pbi->timer.data = (ulong) pbi;
8690 pbi->timer.function = vvp9_put_timer_func;
8691 pbi->timer.expires = jiffies + PUT_INTERVAL;
8692
8693 /*add_timer(&pbi->timer);
8694
8695 pbi->stat |= STAT_TIMER_ARM;
8696 pbi->stat |= STAT_ISR_REG;*/
8697
8698 INIT_WORK(&pbi->work, vp9_work);
8699#ifdef SUPPORT_FB_DECODING
8700 if (pbi->used_stage_buf_num > 0)
8701 INIT_WORK(&pbi->s1_work, vp9_s1_work);
8702#endif
8703 pbi->fw = fw;
8704
8705 /* picture list init.*/
8706 pbi->dec_result = DEC_INIT_PICLIST;
8707 vdec_schedule_work(&pbi->work);
8708
8709 return 0;
8710 }
8711#endif
8712 amhevc_enable();
8713
8714 init_pic_list(pbi);
8715
8716 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
8717 if (ret < 0) {
8718 amhevc_disable();
8719 vfree(fw);
8720 pr_err("VP9: the %s fw loading failed, err: %x\n",
8721 tee_enabled() ? "TEE" : "local", ret);
8722 return -EBUSY;
8723 }
8724
8725 vfree(fw);
8726
8727 pbi->stat |= STAT_MC_LOAD;
8728
8729 /* enable AMRISC side protocol */
8730 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
8731
8732 if (vdec_request_threaded_irq(VDEC_IRQ_0,
8733 vvp9_isr,
8734 vvp9_isr_thread_fn,
8735 IRQF_ONESHOT,/*run thread on this irq disabled*/
8736 "vvp9-irq", (void *)pbi)) {
8737 pr_info("vvp9 irq register error.\n");
8738 amhevc_disable();
8739 return -ENOENT;
8740 }
8741
8742 pbi->stat |= STAT_ISR_REG;
8743
8744 pbi->provider_name = PROVIDER_NAME;
8745#ifdef MULTI_INSTANCE_SUPPORT
8746 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
8747 &vvp9_vf_provider, pbi);
8748 vf_reg_provider(&vvp9_vf_prov);
8749 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
8750 if (pbi->frame_dur != 0) {
8751 if (!is_reset)
8752 vf_notify_receiver(pbi->provider_name,
8753 VFRAME_EVENT_PROVIDER_FR_HINT,
8754 (void *)
8755 ((unsigned long)pbi->frame_dur));
8756 }
8757#else
8758 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
8759 pbi);
8760 vf_reg_provider(&vvp9_vf_prov);
8761 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
8762 if (!is_reset)
8763 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
8764 (void *)((unsigned long)pbi->frame_dur));
8765#endif
8766 pbi->stat |= STAT_VF_HOOK;
8767
8768 pbi->timer.data = (ulong)pbi;
8769 pbi->timer.function = vvp9_put_timer_func;
8770 pbi->timer.expires = jiffies + PUT_INTERVAL;
8771
8772 pbi->stat |= STAT_VDEC_RUN;
8773
8774 add_timer(&pbi->timer);
8775
8776 pbi->stat |= STAT_TIMER_ARM;
8777
8778 amhevc_start();
8779
8780 pbi->init_flag = 1;
8781 pbi->process_busy = 0;
8782 pr_info("%d, vvp9_init, RP=0x%x\n",
8783 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
8784 return 0;
8785}
8786
8787static int vmvp9_stop(struct VP9Decoder_s *pbi)
8788{
8789 pbi->init_flag = 0;
8790
8791 if (pbi->stat & STAT_VDEC_RUN) {
8792 amhevc_stop();
8793 pbi->stat &= ~STAT_VDEC_RUN;
8794 }
8795 if (pbi->stat & STAT_ISR_REG) {
8796 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
8797 pbi->stat &= ~STAT_ISR_REG;
8798 }
8799 if (pbi->stat & STAT_TIMER_ARM) {
8800 del_timer_sync(&pbi->timer);
8801 pbi->stat &= ~STAT_TIMER_ARM;
8802 }
8803
8804 if (pbi->stat & STAT_VF_HOOK) {
8805 if (!is_reset)
8806 vf_notify_receiver(pbi->provider_name,
8807 VFRAME_EVENT_PROVIDER_FR_END_HINT,
8808 NULL);
8809
8810 vf_unreg_provider(&vvp9_vf_prov);
8811 pbi->stat &= ~STAT_VF_HOOK;
8812 }
8813 vp9_local_uninit(pbi);
8814 reset_process_time(pbi);
8815 cancel_work_sync(&pbi->work);
8816#ifdef SUPPORT_FB_DECODING
8817 if (pbi->used_stage_buf_num > 0)
8818 cancel_work_sync(&pbi->s1_work);
8819#endif
8820 cancel_work_sync(&pbi->set_clk_work);
8821 uninit_mmu_buffers(pbi);
8822 if (pbi->fw)
8823 vfree(pbi->fw);
8824 pbi->fw = NULL;
8825 return 0;
8826}
8827
8828static int vvp9_stop(struct VP9Decoder_s *pbi)
8829{
8830
8831 pbi->init_flag = 0;
8832 pbi->first_sc_checked = 0;
8833 if (pbi->stat & STAT_VDEC_RUN) {
8834 amhevc_stop();
8835 pbi->stat &= ~STAT_VDEC_RUN;
8836 }
8837
8838 if (pbi->stat & STAT_ISR_REG) {
8839#ifdef MULTI_INSTANCE_SUPPORT
8840 if (!pbi->m_ins_flag)
8841#endif
8842 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
8843 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
8844 pbi->stat &= ~STAT_ISR_REG;
8845 }
8846
8847 if (pbi->stat & STAT_TIMER_ARM) {
8848 del_timer_sync(&pbi->timer);
8849 pbi->stat &= ~STAT_TIMER_ARM;
8850 }
8851
8852 if (pbi->stat & STAT_VF_HOOK) {
8853 if (!is_reset)
8854 vf_notify_receiver(pbi->provider_name,
8855 VFRAME_EVENT_PROVIDER_FR_END_HINT,
8856 NULL);
8857
8858 vf_unreg_provider(&vvp9_vf_prov);
8859 pbi->stat &= ~STAT_VF_HOOK;
8860 }
8861 vp9_local_uninit(pbi);
8862
8863 cancel_work_sync(&pbi->set_clk_work);
8864#ifdef MULTI_INSTANCE_SUPPORT
8865 if (pbi->m_ins_flag) {
8866#ifdef SUPPORT_FB_DECODING
8867 if (pbi->used_stage_buf_num > 0)
8868 cancel_work_sync(&pbi->s1_work);
8869#endif
8870 cancel_work_sync(&pbi->work);
8871 } else
8872 amhevc_disable();
8873#else
8874 amhevc_disable();
8875#endif
8876 uninit_mmu_buffers(pbi);
8877
8878 vfree(pbi->fw);
8879 pbi->fw = NULL;
8880 return 0;
8881}
8882static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
8883{
8884 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
8885 CODEC_MM_FLAGS_TVP : 0;
8886 int buf_size = 48;
8887
8888 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
8889 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
8890 buf_size = 12;
8891 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
8892 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
8893 buf_size = 4;
8894 }
8895 pbi->need_cache_size = buf_size * SZ_1M;
8896 pbi->sc_start_time = get_jiffies_64();
8897 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
8898 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
8899 pbi->index, FRAME_BUFFERS,
8900 pbi->need_cache_size,
8901 tvp_flag
8902 );
8903 if (!pbi->mmu_box) {
8904 pr_err("vp9 alloc mmu box failed!!\n");
8905 return -1;
8906 }
8907 }
8908 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
8909 DRIVER_NAME,
8910 pbi->index,
8911 MAX_BMMU_BUFFER_NUM,
8912 4 + PAGE_SHIFT,
8913 CODEC_MM_FLAGS_CMA_CLEAR |
8914 CODEC_MM_FLAGS_FOR_VDECODER |
8915 tvp_flag);
8916 if (!pbi->bmmu_box) {
8917 pr_err("vp9 alloc bmmu box failed!!\n");
8918 return -1;
8919 }
8920 return 0;
8921}
8922
8923static struct VP9Decoder_s *gHevc;
8924
8925static int amvdec_vp9_probe(struct platform_device *pdev)
8926{
8927 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
8928 struct BUF_s BUF[MAX_BUF_NUM];
8929 struct VP9Decoder_s *pbi;
8930 int ret;
8931#ifndef MULTI_INSTANCE_SUPPORT
8932 int i;
8933#endif
8934 pr_debug("%s\n", __func__);
8935
8936 mutex_lock(&vvp9_mutex);
8937 pbi = vmalloc(sizeof(struct VP9Decoder_s));
8938 if (pbi == NULL) {
8939 pr_info("\namvdec_vp9 device data allocation failed\n");
8940 mutex_unlock(&vvp9_mutex);
8941 return -ENOMEM;
8942 }
8943
8944 gHevc = pbi;
8945 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
8946 memset(pbi, 0, sizeof(struct VP9Decoder_s));
8947 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
8948
8949 pbi->init_flag = 0;
8950 pbi->first_sc_checked= 0;
8951 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
8952 vp9_max_pic_w = 8192;
8953 vp9_max_pic_h = 4608;
8954 }
8955 pbi->max_pic_w = vp9_max_pic_w;
8956 pbi->max_pic_h = vp9_max_pic_h;
8957
8958#ifdef MULTI_INSTANCE_SUPPORT
8959 pbi->eos = 0;
8960 pbi->start_process_time = 0;
8961 pbi->timeout_num = 0;
8962#endif
8963 pbi->fatal_error = 0;
8964 pbi->show_frame_num = 0;
8965 if (pdata == NULL) {
8966 pr_info("\namvdec_vp9 memory resource undefined.\n");
8967 vfree(pbi);
8968 mutex_unlock(&vvp9_mutex);
8969 return -EFAULT;
8970 }
8971 pbi->m_ins_flag = 0;
8972#ifdef MULTI_INSTANCE_SUPPORT
8973 pbi->platform_dev = pdev;
8974 platform_set_drvdata(pdev, pdata);
8975#endif
8976 pbi->double_write_mode = double_write_mode;
8977 pbi->mmu_enable = 1;
8978 if (amvdec_vp9_mmu_init(pbi) < 0) {
8979 vfree(pbi);
8980 mutex_unlock(&vvp9_mutex);
8981 pr_err("vp9 alloc bmmu box failed!!\n");
8982 return -1;
8983 }
8984
8985 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
8986 work_buf_size, DRIVER_NAME, &pdata->mem_start);
8987 if (ret < 0) {
8988 uninit_mmu_buffers(pbi);
8989 vfree(pbi);
8990 mutex_unlock(&vvp9_mutex);
8991 return ret;
8992 }
8993 pbi->buf_size = work_buf_size;
8994
8995#ifdef MULTI_INSTANCE_SUPPORT
8996 pbi->buf_start = pdata->mem_start;
8997#else
8998 if (!pbi->mmu_enable)
8999 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9000
9001 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9002 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9003#endif
9004
9005
9006 if (debug) {
9007 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9008 pdata->mem_start, pbi->buf_size);
9009 }
9010
9011 if (pdata->sys_info)
9012 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9013 else {
9014 pbi->vvp9_amstream_dec_info.width = 0;
9015 pbi->vvp9_amstream_dec_info.height = 0;
9016 pbi->vvp9_amstream_dec_info.rate = 30;
9017 }
9018 pbi->no_head = no_head;
9019#ifdef MULTI_INSTANCE_SUPPORT
9020 pbi->cma_dev = pdata->cma_dev;
9021#else
9022 cma_dev = pdata->cma_dev;
9023#endif
9024
9025#ifdef MULTI_INSTANCE_SUPPORT
9026 pdata->private = pbi;
9027 pdata->dec_status = vvp9_dec_status;
9028 pdata->set_isreset = vvp9_set_isreset;
9029 is_reset = 0;
9030 if (vvp9_init(pdata) < 0) {
9031#else
9032 if (vvp9_init(pbi) < 0) {
9033#endif
9034 pr_info("\namvdec_vp9 init failed.\n");
9035 vp9_local_uninit(pbi);
9036 uninit_mmu_buffers(pbi);
9037 vfree(pbi);
9038 pdata->dec_status = NULL;
9039 mutex_unlock(&vvp9_mutex);
9040 return -ENODEV;
9041 }
9042 /*set the max clk for smooth playing...*/
9043 hevc_source_changed(VFORMAT_VP9,
9044 4096, 2048, 60);
9045 mutex_unlock(&vvp9_mutex);
9046
9047 return 0;
9048}
9049
9050static int amvdec_vp9_remove(struct platform_device *pdev)
9051{
9052 struct VP9Decoder_s *pbi = gHevc;
9053 struct vdec_s *vdec = hw_to_vdec(pbi);
9054 int i;
9055
9056 if (debug)
9057 pr_info("amvdec_vp9_remove\n");
9058
9059 mutex_lock(&vvp9_mutex);
9060
9061 vvp9_stop(pbi);
9062
9063 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9064
9065 if (vdec->parallel_dec == 1) {
9066 for (i = 0; i < FRAME_BUFFERS; i++) {
9067 vdec->free_canvas_ex(pbi->common.buffer_pool->
9068 frame_bufs[i].buf.y_canvas_index, vdec->id);
9069 vdec->free_canvas_ex(pbi->common.buffer_pool->
9070 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9071 }
9072 }
9073
9074#ifdef DEBUG_PTS
9075 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9076 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9077#endif
9078 vfree(pbi);
9079 mutex_unlock(&vvp9_mutex);
9080
9081 return 0;
9082}
9083
9084/****************************************/
9085#ifdef CONFIG_PM
9086static int vp9_suspend(struct device *dev)
9087{
9088 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9089 return 0;
9090}
9091
9092static int vp9_resume(struct device *dev)
9093{
9094 amhevc_resume(to_platform_device(dev));
9095 return 0;
9096}
9097
9098static const struct dev_pm_ops vp9_pm_ops = {
9099 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9100};
9101#endif
9102
9103static struct platform_driver amvdec_vp9_driver = {
9104 .probe = amvdec_vp9_probe,
9105 .remove = amvdec_vp9_remove,
9106 .driver = {
9107 .name = DRIVER_NAME,
9108#ifdef CONFIG_PM
9109 .pm = &vp9_pm_ops,
9110#endif
9111 }
9112};
9113
9114static struct codec_profile_t amvdec_vp9_profile = {
9115 .name = "vp9",
9116 .profile = ""
9117};
9118
9119static struct codec_profile_t amvdec_vp9_profile_mult;
9120
9121static unsigned char get_data_check_sum
9122 (struct VP9Decoder_s *pbi, int size)
9123{
9124 int jj;
9125 int sum = 0;
9126 u8 *data = NULL;
9127
9128 if (!pbi->chunk->block->is_mapped)
9129 data = codec_mm_vmap(pbi->chunk->block->start +
9130 pbi->chunk->offset, size);
9131 else
9132 data = ((u8 *)pbi->chunk->block->start_virt) +
9133 pbi->chunk->offset;
9134
9135 for (jj = 0; jj < size; jj++)
9136 sum += data[jj];
9137
9138 if (!pbi->chunk->block->is_mapped)
9139 codec_mm_unmap_phyaddr(data);
9140 return sum;
9141}
9142
9143static void dump_data(struct VP9Decoder_s *pbi, int size)
9144{
9145 int jj;
9146 u8 *data = NULL;
9147 int padding_size = pbi->chunk->offset &
9148 (VDEC_FIFO_ALIGN - 1);
9149
9150 if (!pbi->chunk->block->is_mapped)
9151 data = codec_mm_vmap(pbi->chunk->block->start +
9152 pbi->chunk->offset, size);
9153 else
9154 data = ((u8 *)pbi->chunk->block->start_virt) +
9155 pbi->chunk->offset;
9156
9157 vp9_print(pbi, 0, "padding: ");
9158 for (jj = padding_size; jj > 0; jj--)
9159 vp9_print_cont(pbi,
9160 0,
9161 "%02x ", *(data - jj));
9162 vp9_print_cont(pbi, 0, "data adr %p\n",
9163 data);
9164
9165 for (jj = 0; jj < size; jj++) {
9166 if ((jj & 0xf) == 0)
9167 vp9_print(pbi,
9168 0,
9169 "%06x:", jj);
9170 vp9_print_cont(pbi,
9171 0,
9172 "%02x ", data[jj]);
9173 if (((jj + 1) & 0xf) == 0)
9174 vp9_print(pbi,
9175 0,
9176 "\n");
9177 }
9178 vp9_print(pbi,
9179 0,
9180 "\n");
9181
9182 if (!pbi->chunk->block->is_mapped)
9183 codec_mm_unmap_phyaddr(data);
9184}
9185
9186static void vp9_work(struct work_struct *work)
9187{
9188 struct VP9Decoder_s *pbi = container_of(work,
9189 struct VP9Decoder_s, work);
9190 struct vdec_s *vdec = hw_to_vdec(pbi);
9191 /* finished decoding one frame or error,
9192 * notify vdec core to switch context
9193 */
9194 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9195 "%s dec_result %d %x %x %x\n",
9196 __func__,
9197 pbi->dec_result,
9198 READ_VREG(HEVC_STREAM_LEVEL),
9199 READ_VREG(HEVC_STREAM_WR_PTR),
9200 READ_VREG(HEVC_STREAM_RD_PTR));
9201
9202 if (pbi->dec_result == DEC_INIT_PICLIST) {
9203 init_pic_list(pbi);
9204 pbi->pic_list_init_done = true;
9205 return;
9206 }
9207
9208 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9209 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9210 && (hw_to_vdec(pbi)->next_status !=
9211 VDEC_STATUS_DISCONNECTED)) {
9212 if (!vdec_has_more_input(vdec)) {
9213 pbi->dec_result = DEC_RESULT_EOS;
9214 vdec_schedule_work(&pbi->work);
9215 return;
9216 }
9217
9218 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9219 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9220 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9221 __func__,
9222 READ_VREG(HEVC_STREAM_LEVEL),
9223 READ_VREG(HEVC_STREAM_WR_PTR),
9224 READ_VREG(HEVC_STREAM_RD_PTR));
9225 vdec_vframe_dirty(vdec, pbi->chunk);
9226 vdec_clean_input(vdec);
9227 }
9228
9229 if (get_free_buf_count(pbi) >=
9230 run_ready_min_buf_num) {
9231 int r;
9232 int decode_size;
9233 r = vdec_prepare_input(vdec, &pbi->chunk);
9234 if (r < 0) {
9235 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9236
9237 vp9_print(pbi,
9238 PRINT_FLAG_VDEC_DETAIL,
9239 "amvdec_vh265: Insufficient data\n");
9240
9241 vdec_schedule_work(&pbi->work);
9242 return;
9243 }
9244 pbi->dec_result = DEC_RESULT_NONE;
9245 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9246 "%s: chunk size 0x%x sum 0x%x\n",
9247 __func__, r,
9248 (debug & PRINT_FLAG_VDEC_STATUS) ?
9249 get_data_check_sum(pbi, r) : 0
9250 );
9251
9252 if (debug & PRINT_FLAG_VDEC_DATA)
9253 dump_data(pbi, pbi->chunk->size);
9254
9255 decode_size = pbi->chunk->size +
9256 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9257
9258 WRITE_VREG(HEVC_DECODE_SIZE,
9259 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9260
9261 vdec_enable_input(vdec);
9262
9263 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9264
9265 start_process_time(pbi);
9266
9267 } else{
9268 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9269
9270 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9271 "amvdec_vh265: Insufficient data\n");
9272
9273 vdec_schedule_work(&pbi->work);
9274 }
9275 return;
9276 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9277#ifdef SUPPORT_FB_DECODING
9278 if (pbi->used_stage_buf_num > 0) {
9279#ifndef FB_DECODING_TEST_SCHEDULE
9280 if (!is_s2_decoding_finished(pbi)) {
9281 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9282 "s2 decoding not done, check again later\n");
9283 vdec_schedule_work(&pbi->work);
9284 }
9285#endif
9286 inc_s2_pos(pbi);
9287 if (mcrcc_cache_alg_flag)
9288 dump_hit_rate(pbi);
9289 }
9290#endif
9291 /* if (!pbi->ctx_valid)
9292 pbi->ctx_valid = 1; */
9293 pbi->slice_idx++;
9294 pbi->frame_count++;
9295 pbi->process_state = PROC_STATE_INIT;
9296 decode_frame_count[pbi->index] = pbi->frame_count;
9297
9298 if (pbi->mmu_enable)
9299 pbi->used_4k_num =
9300 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9301 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9302 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9303 __func__,
9304 pbi->frame_count,
9305 pbi->dec_result,
9306 READ_VREG(HEVC_STREAM_LEVEL),
9307 READ_VREG(HEVC_STREAM_WR_PTR),
9308 READ_VREG(HEVC_STREAM_RD_PTR),
9309 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9310 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9311 pbi->start_shift_bytes
9312 );
9313 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9314 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9315 /*
9316 stream base: stream buf empty or timeout
9317 frame base: vdec_prepare_input fail
9318 */
9319 if (!vdec_has_more_input(vdec)) {
9320 pbi->dec_result = DEC_RESULT_EOS;
9321 vdec_schedule_work(&pbi->work);
9322 return;
9323 }
9324 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9325 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9326 "%s: end of stream\n",
9327 __func__);
9328 pbi->eos = 1;
9329 vp9_bufmgr_postproc(pbi);
9330
9331 if (pbi->is_used_v4l)
9332 notify_v4l_eos(hw_to_vdec(pbi));
9333
9334 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9335 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9336 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9337 "%s: force exit\n",
9338 __func__);
9339 if (pbi->stat & STAT_VDEC_RUN) {
9340 amhevc_stop();
9341 pbi->stat &= ~STAT_VDEC_RUN;
9342 }
9343
9344 if (pbi->stat & STAT_ISR_REG) {
9345#ifdef MULTI_INSTANCE_SUPPORT
9346 if (!pbi->m_ins_flag)
9347#endif
9348 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9349 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9350 pbi->stat &= ~STAT_ISR_REG;
9351 }
9352 }
9353 if (pbi->stat & STAT_VDEC_RUN) {
9354 amhevc_stop();
9355 pbi->stat &= ~STAT_VDEC_RUN;
9356 }
9357
9358 if (pbi->stat & STAT_TIMER_ARM) {
9359 del_timer_sync(&pbi->timer);
9360 pbi->stat &= ~STAT_TIMER_ARM;
9361 }
9362 /* mark itself has all HW resource released and input released */
9363#ifdef SUPPORT_FB_DECODING
9364 if (pbi->used_stage_buf_num > 0)
9365 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9366 else
9367 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9368 | CORE_MASK_HEVC
9369 | CORE_MASK_HEVC_FRONT
9370 | CORE_MASK_HEVC_BACK
9371 );
9372#else
9373 if (vdec->parallel_dec == 1)
9374 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9375 else
9376 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9377 | CORE_MASK_HEVC);
9378#endif
9379 trigger_schedule(pbi);
9380}
9381
9382static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9383{
9384 /* new to do ... */
9385#if (!defined SUPPORT_FB_DECODING)
9386 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9387#elif (defined FB_DECODING_TEST_SCHEDULE)
9388 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9389#else
9390 if (pbi->used_stage_buf_num > 0)
9391 vvp9_prot_init(pbi, HW_MASK_FRONT);
9392 else
9393 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9394#endif
9395 return 0;
9396}
9397static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9398{
9399 struct VP9Decoder_s *pbi =
9400 (struct VP9Decoder_s *)vdec->private;
9401 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9402 CODEC_MM_FLAGS_TVP : 0;
9403 unsigned long ret = 0;
9404
9405 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9406 return ret;
9407 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9408 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9409 pbi->first_sc_checked = 1;
9410 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9411 size, (pbi->need_cache_size >> PAGE_SHIFT),
9412 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9413 }
9414#ifdef SUPPORT_FB_DECODING
9415 if (pbi->used_stage_buf_num > 0) {
9416 if (mask & CORE_MASK_HEVC_FRONT) {
9417 if (get_free_stage_buf_num(pbi) > 0
9418 && mv_buf_available(pbi))
9419 ret |= CORE_MASK_HEVC_FRONT;
9420 }
9421 if (mask & CORE_MASK_HEVC_BACK) {
9422 if (s2_buf_available(pbi) &&
9423 (get_free_buf_count(pbi) >=
9424 run_ready_min_buf_num)) {
9425 ret |= CORE_MASK_HEVC_BACK;
9426 pbi->back_not_run_ready = 0;
9427 } else
9428 pbi->back_not_run_ready = 1;
9429#if 0
9430 if (get_free_buf_count(pbi) <
9431 run_ready_min_buf_num)
9432 dump_pic_list(pbi);
9433#endif
9434 }
9435 } else if (get_free_buf_count(pbi) >=
9436 run_ready_min_buf_num)
9437 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9438 | CORE_MASK_HEVC_FRONT
9439 | CORE_MASK_HEVC_BACK;
9440
9441 if (ret & CORE_MASK_HEVC_FRONT)
9442 not_run_ready[pbi->index] = 0;
9443 else
9444 not_run_ready[pbi->index]++;
9445
9446 if (ret & CORE_MASK_HEVC_BACK)
9447 not_run2_ready[pbi->index] = 0;
9448 else
9449 not_run2_ready[pbi->index]++;
9450
9451 vp9_print(pbi,
9452 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9453 __func__, mask, ret,
9454 get_free_stage_buf_num(pbi),
9455 mv_buf_available(pbi),
9456 s2_buf_available(pbi),
9457 get_free_buf_count(pbi)
9458 );
9459
9460 return ret;
9461
9462#else
9463 if (get_free_buf_count(pbi) >=
9464 run_ready_min_buf_num) {
9465 if (vdec->parallel_dec == 1)
9466 ret = CORE_MASK_HEVC;
9467 else
9468 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9469 }
9470 if (ret)
9471 not_run_ready[pbi->index] = 0;
9472 else
9473 not_run_ready[pbi->index]++;
9474
9475 vp9_print(pbi,
9476 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9477 __func__, mask, ret);
9478 return ret;
9479#endif
9480}
9481
9482static void run_front(struct vdec_s *vdec)
9483{
9484 struct VP9Decoder_s *pbi =
9485 (struct VP9Decoder_s *)vdec->private;
9486 int ret, size;
9487
9488 run_count[pbi->index]++;
9489 /* pbi->chunk = vdec_prepare_input(vdec); */
9490#if (!defined SUPPORT_FB_DECODING)
9491 hevc_reset_core(vdec);
9492#elif (defined FB_DECODING_TEST_SCHEDULE)
9493 hevc_reset_core(vdec);
9494#else
9495 if (pbi->used_stage_buf_num > 0)
9496 fb_reset_core(vdec, HW_MASK_FRONT);
9497 else
9498 hevc_reset_core(vdec);
9499#endif
9500
9501 size = vdec_prepare_input(vdec, &pbi->chunk);
9502 if (size < 0) {
9503 input_empty[pbi->index]++;
9504
9505 pbi->dec_result = DEC_RESULT_AGAIN;
9506
9507 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9508 "ammvdec_vh265: Insufficient data\n");
9509
9510 vdec_schedule_work(&pbi->work);
9511 return;
9512 }
9513 input_empty[pbi->index] = 0;
9514 pbi->dec_result = DEC_RESULT_NONE;
9515 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9516
9517 if (debug & PRINT_FLAG_VDEC_STATUS) {
9518 int ii;
9519 vp9_print(pbi, 0,
9520 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9521 __func__,
9522 pbi->frame_count, size,
9523 pbi->chunk ? pbi->chunk->size : 0,
9524 pbi->chunk ? pbi->chunk->offset : 0,
9525 pbi->chunk ? ((vdec_frame_based(vdec) &&
9526 (debug & PRINT_FLAG_VDEC_STATUS)) ?
9527 get_data_check_sum(pbi, size) : 0) : 0,
9528 READ_VREG(HEVC_STREAM_START_ADDR),
9529 READ_VREG(HEVC_STREAM_END_ADDR),
9530 READ_VREG(HEVC_STREAM_LEVEL),
9531 READ_VREG(HEVC_STREAM_WR_PTR),
9532 READ_VREG(HEVC_STREAM_RD_PTR),
9533 pbi->start_shift_bytes);
9534 if (vdec_frame_based(vdec) && pbi->chunk) {
9535 u8 *data = NULL;
9536
9537 if (!pbi->chunk->block->is_mapped)
9538 data = codec_mm_vmap(pbi->chunk->block->start +
9539 pbi->chunk->offset, 8);
9540 else
9541 data = ((u8 *)pbi->chunk->block->start_virt) +
9542 pbi->chunk->offset;
9543
9544 vp9_print_cont(pbi, 0, "data adr %p:",
9545 data);
9546 for (ii = 0; ii < 8; ii++)
9547 vp9_print_cont(pbi, 0, "%02x ",
9548 data[ii]);
9549
9550 if (!pbi->chunk->block->is_mapped)
9551 codec_mm_unmap_phyaddr(data);
9552 }
9553 vp9_print_cont(pbi, 0, "\r\n");
9554 }
9555 if (vdec->mc_loaded) {
9556 /*firmware have load before,
9557 and not changes to another.
9558 ignore reload.
9559 */
9560 } else {
9561 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9562 if (ret < 0) {
9563 amhevc_disable();
9564 vp9_print(pbi, PRINT_FLAG_ERROR,
9565 "VP9: the %s fw loading failed, err: %x\n",
9566 tee_enabled() ? "TEE" : "local", ret);
9567 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9568 vdec_schedule_work(&pbi->work);
9569 return;
9570 }
9571 vdec->mc_loaded = 1;
9572 vdec->mc_type = VFORMAT_VP9;
9573 }
9574
9575 if (vp9_hw_ctx_restore(pbi) < 0) {
9576 vdec_schedule_work(&pbi->work);
9577 return;
9578 }
9579
9580 vdec_enable_input(vdec);
9581
9582 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9583
9584 if (vdec_frame_based(vdec)) {
9585 if (debug & PRINT_FLAG_VDEC_DATA)
9586 dump_data(pbi, pbi->chunk->size);
9587
9588 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9589 size = pbi->chunk->size +
9590 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9591 }
9592 WRITE_VREG(HEVC_DECODE_SIZE, size);
9593 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9594 pbi->init_flag = 1;
9595
9596 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9597 "%s: start hevc (%x %x %x)\n",
9598 __func__,
9599 READ_VREG(HEVC_DEC_STATUS_REG),
9600 READ_VREG(HEVC_MPC_E),
9601 READ_VREG(HEVC_MPSR));
9602
9603 start_process_time(pbi);
9604 mod_timer(&pbi->timer, jiffies);
9605 pbi->stat |= STAT_TIMER_ARM;
9606 pbi->stat |= STAT_ISR_REG;
9607 amhevc_start();
9608 pbi->stat |= STAT_VDEC_RUN;
9609}
9610
9611#ifdef SUPPORT_FB_DECODING
9612static void mpred_process(struct VP9Decoder_s *pbi)
9613{
9614 union param_u *params = &pbi->s1_param;
9615 unsigned char use_prev_frame_mvs =
9616 !params->p.error_resilient_mode &&
9617 params->p.width == pbi->s1_width &&
9618 params->p.height == pbi->s1_height &&
9619 !pbi->s1_intra_only &&
9620 pbi->s1_last_show_frame &&
9621 (pbi->s1_frame_type != KEY_FRAME);
9622 pbi->s1_width = params->p.width;
9623 pbi->s1_height = params->p.height;
9624 pbi->s1_frame_type = params->p.frame_type;
9625 pbi->s1_intra_only =
9626 (params->p.show_frame ||
9627 params->p.show_existing_frame)
9628 ? 0 : params->p.intra_only;
9629 if ((pbi->s1_frame_type != KEY_FRAME)
9630 && (!pbi->s1_intra_only)) {
9631 unsigned int data32;
9632 int mpred_mv_rd_end_addr;
9633
9634 mpred_mv_rd_end_addr =
9635 pbi->s1_mpred_mv_wr_start_addr_pre
9636 + (pbi->lcu_total * MV_MEM_UNIT);
9637
9638 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
9639 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
9640 pbi->work_space_buf->
9641 mpred_above.buf_start);
9642
9643 data32 = READ_VREG(HEVC_MPRED_CTRL4);
9644
9645 data32 &= (~(1 << 6));
9646 data32 |= (use_prev_frame_mvs << 6);
9647 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
9648
9649 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
9650 pbi->s1_mpred_mv_wr_start_addr);
9651 WRITE_VREG(HEVC_MPRED_MV_WPTR,
9652 pbi->s1_mpred_mv_wr_start_addr);
9653
9654 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
9655 pbi->s1_mpred_mv_wr_start_addr_pre);
9656 WRITE_VREG(HEVC_MPRED_MV_RPTR,
9657 pbi->s1_mpred_mv_wr_start_addr_pre);
9658
9659 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
9660 mpred_mv_rd_end_addr);
9661
9662 } else
9663 clear_mpred_hw(pbi);
9664
9665 if (!params->p.show_existing_frame) {
9666 pbi->s1_mpred_mv_wr_start_addr_pre =
9667 pbi->s1_mpred_mv_wr_start_addr;
9668 pbi->s1_last_show_frame =
9669 params->p.show_frame;
9670 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
9671 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
9672 pbi->s1_mv_buf_index_pre_pre =
9673 pbi->s1_mv_buf_index_pre;
9674 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
9675 } else
9676 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
9677}
9678
9679static void vp9_s1_work(struct work_struct *s1_work)
9680{
9681 struct VP9Decoder_s *pbi = container_of(s1_work,
9682 struct VP9Decoder_s, s1_work);
9683 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9684 "%s dec_s1_result %d\n",
9685 __func__,
9686 pbi->dec_s1_result);
9687
9688#ifdef FB_DECODING_TEST_SCHEDULE
9689 if (pbi->dec_s1_result ==
9690 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
9691 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
9692 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
9693 }
9694#endif
9695 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
9696 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
9697
9698 vdec_core_finish_run(hw_to_vdec(pbi),
9699 CORE_MASK_HEVC_FRONT);
9700
9701 trigger_schedule(pbi);
9702 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
9703 }
9704
9705}
9706
9707static void run_back(struct vdec_s *vdec)
9708{
9709 struct VP9Decoder_s *pbi =
9710 (struct VP9Decoder_s *)vdec->private;
9711 int i;
9712 run2_count[pbi->index]++;
9713 if (debug & PRINT_FLAG_VDEC_STATUS) {
9714 vp9_print(pbi, 0,
9715 "%s", __func__);
9716 }
9717 pbi->run2_busy = 1;
9718#ifndef FB_DECODING_TEST_SCHEDULE
9719 fb_reset_core(vdec, HW_MASK_BACK);
9720
9721 vvp9_prot_init(pbi, HW_MASK_BACK);
9722#endif
9723 vp9_recycle_mmu_buf_tail(pbi);
9724
9725 if (pbi->frame_count > 0)
9726 vp9_bufmgr_postproc(pbi);
9727
9728 if (get_s2_buf(pbi) >= 0) {
9729 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
9730 int ii;
9731 for (ii = 0; ii < 4; ii++)
9732 vp9_param.l.data[i + ii] =
9733 pbi->s2_buf->rpm[i + 3 - ii];
9734 }
9735#ifndef FB_DECODING_TEST_SCHEDULE
9736 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
9737 pbi->stage_mmu_map_phy_addr +
9738 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
9739#endif
9740 continue_decoding(pbi);
9741 }
9742 pbi->run2_busy = 0;
9743}
9744#endif
9745
9746static void run(struct vdec_s *vdec, unsigned long mask,
9747 void (*callback)(struct vdec_s *, void *), void *arg)
9748{
9749 struct VP9Decoder_s *pbi =
9750 (struct VP9Decoder_s *)vdec->private;
9751
9752 vp9_print(pbi,
9753 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
9754 __func__, mask);
9755
9756 run_count[pbi->index]++;
9757 pbi->vdec_cb_arg = arg;
9758 pbi->vdec_cb = callback;
9759#ifdef SUPPORT_FB_DECODING
9760 if ((mask & CORE_MASK_HEVC) ||
9761 (mask & CORE_MASK_HEVC_FRONT))
9762 run_front(vdec);
9763
9764 if ((pbi->used_stage_buf_num > 0)
9765 && (mask & CORE_MASK_HEVC_BACK))
9766 run_back(vdec);
9767#else
9768 run_front(vdec);
9769#endif
9770}
9771
9772static void reset(struct vdec_s *vdec)
9773{
9774
9775 struct VP9Decoder_s *pbi =
9776 (struct VP9Decoder_s *)vdec->private;
9777
9778 vp9_print(pbi,
9779 PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
9780
9781}
9782
9783static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
9784{
9785 struct VP9Decoder_s *pbi =
9786 (struct VP9Decoder_s *)vdec->private;
9787 return vvp9_isr(0, pbi);
9788}
9789
9790static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
9791{
9792 struct VP9Decoder_s *pbi =
9793 (struct VP9Decoder_s *)vdec->private;
9794 return vvp9_isr_thread_fn(0, pbi);
9795}
9796
9797static void vp9_dump_state(struct vdec_s *vdec)
9798{
9799 struct VP9Decoder_s *pbi =
9800 (struct VP9Decoder_s *)vdec->private;
9801 struct VP9_Common_s *const cm = &pbi->common;
9802 int i;
9803 vp9_print(pbi, 0, "====== %s\n", __func__);
9804
9805 vp9_print(pbi, 0,
9806 "width/height (%d/%d), used_buf_num %d\n",
9807 cm->width,
9808 cm->height,
9809 pbi->used_buf_num
9810 );
9811
9812 vp9_print(pbi, 0,
9813 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
9814 input_frame_based(vdec),
9815 pbi->eos,
9816 pbi->dec_result,
9817 decode_frame_count[pbi->index],
9818 display_frame_count[pbi->index],
9819 run_count[pbi->index],
9820 not_run_ready[pbi->index],
9821 input_empty[pbi->index],
9822 pbi->low_latency_flag,
9823 pbi->no_head
9824 );
9825
9826 if (vf_get_receiver(vdec->vf_provider_name)) {
9827 enum receviver_start_e state =
9828 vf_notify_receiver(vdec->vf_provider_name,
9829 VFRAME_EVENT_PROVIDER_QUREY_STATE,
9830 NULL);
9831 vp9_print(pbi, 0,
9832 "\nreceiver(%s) state %d\n",
9833 vdec->vf_provider_name,
9834 state);
9835 }
9836
9837 vp9_print(pbi, 0,
9838 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
9839 __func__,
9840 kfifo_len(&pbi->newframe_q),
9841 VF_POOL_SIZE,
9842 kfifo_len(&pbi->display_q),
9843 VF_POOL_SIZE,
9844 pbi->vf_pre_count,
9845 pbi->vf_get_count,
9846 pbi->vf_put_count,
9847 get_free_buf_count(pbi),
9848 run_ready_min_buf_num
9849 );
9850
9851 dump_pic_list(pbi);
9852
9853 for (i = 0; i < MAX_BUF_NUM; i++) {
9854 vp9_print(pbi, 0,
9855 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
9856 i,
9857 pbi->m_mv_BUF[i].start_adr,
9858 pbi->m_mv_BUF[i].size,
9859 pbi->m_mv_BUF[i].used_flag);
9860 }
9861
9862 vp9_print(pbi, 0,
9863 "HEVC_DEC_STATUS_REG=0x%x\n",
9864 READ_VREG(HEVC_DEC_STATUS_REG));
9865 vp9_print(pbi, 0,
9866 "HEVC_MPC_E=0x%x\n",
9867 READ_VREG(HEVC_MPC_E));
9868 vp9_print(pbi, 0,
9869 "DECODE_MODE=0x%x\n",
9870 READ_VREG(DECODE_MODE));
9871 vp9_print(pbi, 0,
9872 "NAL_SEARCH_CTL=0x%x\n",
9873 READ_VREG(NAL_SEARCH_CTL));
9874 vp9_print(pbi, 0,
9875 "HEVC_PARSER_LCU_START=0x%x\n",
9876 READ_VREG(HEVC_PARSER_LCU_START));
9877 vp9_print(pbi, 0,
9878 "HEVC_DECODE_SIZE=0x%x\n",
9879 READ_VREG(HEVC_DECODE_SIZE));
9880 vp9_print(pbi, 0,
9881 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
9882 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
9883 vp9_print(pbi, 0,
9884 "HEVC_STREAM_START_ADDR=0x%x\n",
9885 READ_VREG(HEVC_STREAM_START_ADDR));
9886 vp9_print(pbi, 0,
9887 "HEVC_STREAM_END_ADDR=0x%x\n",
9888 READ_VREG(HEVC_STREAM_END_ADDR));
9889 vp9_print(pbi, 0,
9890 "HEVC_STREAM_LEVEL=0x%x\n",
9891 READ_VREG(HEVC_STREAM_LEVEL));
9892 vp9_print(pbi, 0,
9893 "HEVC_STREAM_WR_PTR=0x%x\n",
9894 READ_VREG(HEVC_STREAM_WR_PTR));
9895 vp9_print(pbi, 0,
9896 "HEVC_STREAM_RD_PTR=0x%x\n",
9897 READ_VREG(HEVC_STREAM_RD_PTR));
9898 vp9_print(pbi, 0,
9899 "PARSER_VIDEO_RP=0x%x\n",
9900 READ_PARSER_REG(PARSER_VIDEO_RP));
9901 vp9_print(pbi, 0,
9902 "PARSER_VIDEO_WP=0x%x\n",
9903 READ_PARSER_REG(PARSER_VIDEO_WP));
9904
9905 if (input_frame_based(vdec) &&
9906 (debug & PRINT_FLAG_VDEC_DATA)
9907 ) {
9908 int jj;
9909 if (pbi->chunk && pbi->chunk->block &&
9910 pbi->chunk->size > 0) {
9911 u8 *data = NULL;
9912
9913 if (!pbi->chunk->block->is_mapped)
9914 data = codec_mm_vmap(
9915 pbi->chunk->block->start +
9916 pbi->chunk->offset,
9917 pbi->chunk->size);
9918 else
9919 data = ((u8 *)pbi->chunk->block->start_virt)
9920 + pbi->chunk->offset;
9921 vp9_print(pbi, 0,
9922 "frame data size 0x%x\n",
9923 pbi->chunk->size);
9924 for (jj = 0; jj < pbi->chunk->size; jj++) {
9925 if ((jj & 0xf) == 0)
9926 vp9_print(pbi, 0,
9927 "%06x:", jj);
9928 vp9_print_cont(pbi, 0,
9929 "%02x ", data[jj]);
9930 if (((jj + 1) & 0xf) == 0)
9931 vp9_print_cont(pbi, 0,
9932 "\n");
9933 }
9934
9935 if (!pbi->chunk->block->is_mapped)
9936 codec_mm_unmap_phyaddr(data);
9937 }
9938 }
9939
9940}
9941
9942static int ammvdec_vp9_probe(struct platform_device *pdev)
9943{
9944 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9945 int ret;
9946 int config_val;
9947 struct vframe_content_light_level_s content_light_level;
9948 struct vframe_master_display_colour_s vf_dp;
9949
9950 struct BUF_s BUF[MAX_BUF_NUM];
9951 struct VP9Decoder_s *pbi = NULL;
9952 pr_debug("%s\n", __func__);
9953
9954 if (pdata == NULL) {
9955 pr_info("\nammvdec_vp9 memory resource undefined.\n");
9956 return -EFAULT;
9957 }
9958 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
9959 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
9960 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
9961 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9962 if (pbi == NULL) {
9963 pr_info("\nammvdec_vp9 device data allocation failed\n");
9964 return -ENOMEM;
9965 }
9966 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9967
9968 /* the ctx from v4l2 driver. */
9969 pbi->v4l2_ctx = pdata->private;
9970
9971 pdata->private = pbi;
9972 pdata->dec_status = vvp9_dec_status;
9973 /* pdata->set_trickmode = set_trickmode; */
9974 pdata->run_ready = run_ready;
9975 pdata->run = run;
9976 pdata->reset = reset;
9977 pdata->irq_handler = vp9_irq_cb;
9978 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
9979 pdata->dump_state = vp9_dump_state;
9980
9981 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9982 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9983
9984 pbi->index = pdev->id;
9985
9986 if (pdata->use_vfm_path)
9987 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9988 VFM_DEC_PROVIDER_NAME);
9989 else
9990 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
9991 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
9992
9993 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
9994 &vvp9_vf_provider, pbi);
9995
9996 pbi->provider_name = pdata->vf_provider_name;
9997 platform_set_drvdata(pdev, pdata);
9998
9999 pbi->platform_dev = pdev;
10000 pbi->video_signal_type = 0;
10001 pbi->m_ins_flag = 1;
10002 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10003 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10004
10005 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10006 pbi->max_pic_w = 8192;
10007 pbi->max_pic_h = 4608;
10008 } else {
10009 pbi->max_pic_w = 4096;
10010 pbi->max_pic_h = 2304;
10011 }
10012#if 1
10013 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10014 pdata->config_len) {
10015#ifdef MULTI_INSTANCE_SUPPORT
10016 int vp9_buf_width = 0;
10017 int vp9_buf_height = 0;
10018 /*use ptr config for doubel_write_mode, etc*/
10019 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10020 if (get_config_int(pdata->config, "vp9_double_write_mode",
10021 &config_val) == 0)
10022 pbi->double_write_mode = config_val;
10023 else
10024 pbi->double_write_mode = double_write_mode;
10025
10026 if (get_config_int(pdata->config, "save_buffer_mode",
10027 &config_val) == 0)
10028 pbi->save_buffer_mode = config_val;
10029 else
10030 pbi->save_buffer_mode = 0;
10031 if (get_config_int(pdata->config, "vp9_buf_width",
10032 &config_val) == 0) {
10033 vp9_buf_width = config_val;
10034 }
10035 if (get_config_int(pdata->config, "vp9_buf_height",
10036 &config_val) == 0) {
10037 vp9_buf_height = config_val;
10038 }
10039
10040 if (get_config_int(pdata->config, "no_head",
10041 &config_val) == 0)
10042 pbi->no_head = config_val;
10043 else
10044 pbi->no_head = no_head;
10045
10046 /*use ptr config for max_pic_w, etc*/
10047 if (get_config_int(pdata->config, "vp9_max_pic_w",
10048 &config_val) == 0) {
10049 pbi->max_pic_w = config_val;
10050 }
10051 if (get_config_int(pdata->config, "vp9_max_pic_h",
10052 &config_val) == 0) {
10053 pbi->max_pic_h = config_val;
10054 }
10055 if ((pbi->max_pic_w * pbi->max_pic_h)
10056 < (vp9_buf_width * vp9_buf_height)) {
10057 pbi->max_pic_w = vp9_buf_width;
10058 pbi->max_pic_h = vp9_buf_height;
10059 vp9_print(pbi, 0, "use buf resolution\n");
10060 }
10061#endif
10062 if (get_config_int(pdata->config, "HDRStaticInfo",
10063 &vf_dp.present_flag) == 0
10064 && vf_dp.present_flag == 1) {
10065 get_config_int(pdata->config, "mG.x",
10066 &vf_dp.primaries[0][0]);
10067 get_config_int(pdata->config, "mG.y",
10068 &vf_dp.primaries[0][1]);
10069 get_config_int(pdata->config, "mB.x",
10070 &vf_dp.primaries[1][0]);
10071 get_config_int(pdata->config, "mB.y",
10072 &vf_dp.primaries[1][1]);
10073 get_config_int(pdata->config, "mR.x",
10074 &vf_dp.primaries[2][0]);
10075 get_config_int(pdata->config, "mR.y",
10076 &vf_dp.primaries[2][1]);
10077 get_config_int(pdata->config, "mW.x",
10078 &vf_dp.white_point[0]);
10079 get_config_int(pdata->config, "mW.y",
10080 &vf_dp.white_point[1]);
10081 get_config_int(pdata->config, "mMaxDL",
10082 &vf_dp.luminance[0]);
10083 get_config_int(pdata->config, "mMinDL",
10084 &vf_dp.luminance[1]);
10085 vf_dp.content_light_level.present_flag = 1;
10086 get_config_int(pdata->config, "mMaxCLL",
10087 &content_light_level.max_content);
10088 get_config_int(pdata->config, "mMaxFALL",
10089 &content_light_level.max_pic_average);
10090 vf_dp.content_light_level = content_light_level;
10091 pbi->video_signal_type = (1 << 29)
10092 | (5 << 26) /* unspecified */
10093 | (0 << 25) /* limit */
10094 | (1 << 24) /* color available */
10095 | (9 << 16) /* 2020 */
10096 | (16 << 8) /* 2084 */
10097 | (9 << 0); /* 2020 */
10098 }
10099 pbi->vf_dp = vf_dp;
10100 } else
10101#endif
10102 {
10103 /*pbi->vvp9_amstream_dec_info.width = 0;
10104 pbi->vvp9_amstream_dec_info.height = 0;
10105 pbi->vvp9_amstream_dec_info.rate = 30;*/
10106 pbi->double_write_mode = double_write_mode;
10107 }
10108 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10109 pr_err("over size: %dx%d, probe failed\n",
10110 pbi->max_pic_w, pbi->max_pic_h);
10111 return -1;
10112 }
10113 pbi->mmu_enable = 1;
10114 video_signal_type = pbi->video_signal_type;
10115
10116 if (pdata->sys_info) {
10117 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10118 } else {
10119 pbi->vvp9_amstream_dec_info.width = 0;
10120 pbi->vvp9_amstream_dec_info.height = 0;
10121 pbi->vvp9_amstream_dec_info.rate = 30;
10122 }
10123 pbi->low_latency_flag = 1;
10124 pbi->is_used_v4l = (((unsigned long)
10125 pbi->vvp9_amstream_dec_info.param & 0x80) >> 7);
10126 if (pbi->is_used_v4l) {
10127 pbi->double_write_mode = 0x10;
10128 pbi->mmu_enable = 0;
10129 pbi->max_pic_w = 1920;
10130 pbi->max_pic_h = 1080;
10131 }
10132
10133 vp9_print(pbi, 0,
10134 "no_head %d low_latency %d\n",
10135 pbi->no_head, pbi->low_latency_flag);
10136#if 0
10137 pbi->buf_start = pdata->mem_start;
10138 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10139#else
10140 if (amvdec_vp9_mmu_init(pbi) < 0) {
10141 pr_err("vp9 alloc bmmu box failed!!\n");
10142 /* devm_kfree(&pdev->dev, (void *)pbi); */
10143 vfree((void *)pbi);
10144 pdata->dec_status = NULL;
10145 return -1;
10146 }
10147
10148 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10149 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10150 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10151 &pbi->cma_alloc_addr);
10152 if (ret < 0) {
10153 uninit_mmu_buffers(pbi);
10154 /* devm_kfree(&pdev->dev, (void *)pbi); */
10155 vfree((void *)pbi);
10156 pdata->dec_status = NULL;
10157 return ret;
10158 }
10159 pbi->buf_start = pbi->cma_alloc_addr;
10160 pbi->buf_size = work_buf_size;
10161#endif
10162
10163 pbi->init_flag = 0;
10164 pbi->first_sc_checked = 0;
10165 pbi->fatal_error = 0;
10166 pbi->show_frame_num = 0;
10167
10168 if (debug) {
10169 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10170 pbi->buf_start,
10171 pbi->buf_size);
10172 }
10173
10174 pbi->cma_dev = pdata->cma_dev;
10175 if (vvp9_init(pdata) < 0) {
10176 pr_info("\namvdec_vp9 init failed.\n");
10177 vp9_local_uninit(pbi);
10178 uninit_mmu_buffers(pbi);
10179 /* devm_kfree(&pdev->dev, (void *)pbi); */
10180 vfree((void *)pbi);
10181 pdata->dec_status = NULL;
10182 return -ENODEV;
10183 }
10184 vdec_set_prepare_level(pdata, start_decode_buf_level);
10185 hevc_source_changed(VFORMAT_VP9,
10186 4096, 2048, 60);
10187#ifdef SUPPORT_FB_DECODING
10188 if (pbi->used_stage_buf_num > 0)
10189 vdec_core_request(pdata,
10190 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10191 else
10192 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10193 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10194 | CORE_MASK_COMBINE);
10195#else
10196 if (pdata->parallel_dec == 1)
10197 vdec_core_request(pdata, CORE_MASK_HEVC);
10198 else
10199 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10200 | CORE_MASK_COMBINE);
10201#endif
10202 pbi->pic_list_init_done2 = true;
10203 return 0;
10204}
10205
10206static int ammvdec_vp9_remove(struct platform_device *pdev)
10207{
10208 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10209 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10210 struct vdec_s *vdec = hw_to_vdec(pbi);
10211 int i;
10212 if (debug)
10213 pr_info("amvdec_vp9_remove\n");
10214
10215 vmvp9_stop(pbi);
10216
10217#ifdef SUPPORT_FB_DECODING
10218 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10219 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10220 );
10221#else
10222 if (vdec->parallel_dec == 1)
10223 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10224 else
10225 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10226#endif
10227 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10228
10229 if (vdec->parallel_dec == 1) {
10230 for (i = 0; i < FRAME_BUFFERS; i++) {
10231 vdec->free_canvas_ex
10232 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10233 vdec->id);
10234 vdec->free_canvas_ex
10235 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10236 vdec->id);
10237 }
10238 }
10239
10240
10241#ifdef DEBUG_PTS
10242 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10243 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10244#endif
10245 /* devm_kfree(&pdev->dev, (void *)pbi); */
10246 vfree((void *)pbi);
10247 return 0;
10248}
10249
10250static struct platform_driver ammvdec_vp9_driver = {
10251 .probe = ammvdec_vp9_probe,
10252 .remove = ammvdec_vp9_remove,
10253 .driver = {
10254 .name = MULTI_DRIVER_NAME,
10255#ifdef CONFIG_PM
10256 .pm = &vp9_pm_ops,
10257#endif
10258 }
10259};
10260#endif
10261static struct mconfig vp9_configs[] = {
10262 MC_PU32("bit_depth_luma", &bit_depth_luma),
10263 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10264 MC_PU32("frame_width", &frame_width),
10265 MC_PU32("frame_height", &frame_height),
10266 MC_PU32("debug", &debug),
10267 MC_PU32("radr", &radr),
10268 MC_PU32("rval", &rval),
10269 MC_PU32("pop_shorts", &pop_shorts),
10270 MC_PU32("dbg_cmd", &dbg_cmd),
10271 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10272 MC_PU32("endian", &endian),
10273 MC_PU32("step", &step),
10274 MC_PU32("udebug_flag", &udebug_flag),
10275 MC_PU32("decode_pic_begin", &decode_pic_begin),
10276 MC_PU32("slice_parse_begin", &slice_parse_begin),
10277 MC_PU32("i_only_flag", &i_only_flag),
10278 MC_PU32("error_handle_policy", &error_handle_policy),
10279 MC_PU32("buf_alloc_width", &buf_alloc_width),
10280 MC_PU32("buf_alloc_height", &buf_alloc_height),
10281 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10282 MC_PU32("buf_alloc_size", &buf_alloc_size),
10283 MC_PU32("buffer_mode", &buffer_mode),
10284 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10285 MC_PU32("max_buf_num", &max_buf_num),
10286 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10287 MC_PU32("mem_map_mode", &mem_map_mode),
10288 MC_PU32("double_write_mode", &double_write_mode),
10289 MC_PU32("enable_mem_saving", &enable_mem_saving),
10290 MC_PU32("force_w_h", &force_w_h),
10291 MC_PU32("force_fps", &force_fps),
10292 MC_PU32("max_decoding_time", &max_decoding_time),
10293 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10294 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10295 MC_PU32("decode_timeout_val", &decode_timeout_val),
10296 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10297 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10298};
10299static struct mconfig_node vp9_node;
10300
10301static int __init amvdec_vp9_driver_init_module(void)
10302{
10303
10304 struct BuffInfo_s *p_buf_info;
10305
10306 if (vdec_is_support_4k()) {
10307 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10308 p_buf_info = &amvvp9_workbuff_spec[2];
10309 else
10310 p_buf_info = &amvvp9_workbuff_spec[1];
10311 } else
10312 p_buf_info = &amvvp9_workbuff_spec[0];
10313
10314 init_buff_spec(NULL, p_buf_info);
10315 work_buf_size =
10316 (p_buf_info->end_adr - p_buf_info->start_adr
10317 + 0xffff) & (~0xffff);
10318
10319 pr_debug("amvdec_vp9 module init\n");
10320
10321 error_handle_policy = 0;
10322
10323#ifdef ERROR_HANDLE_DEBUG
10324 dbg_nal_skip_flag = 0;
10325 dbg_nal_skip_count = 0;
10326#endif
10327 udebug_flag = 0;
10328 decode_pic_begin = 0;
10329 slice_parse_begin = 0;
10330 step = 0;
10331 buf_alloc_size = 0;
10332#ifdef MULTI_INSTANCE_SUPPORT
10333 if (platform_driver_register(&ammvdec_vp9_driver))
10334 pr_err("failed to register ammvdec_vp9 driver\n");
10335
10336#endif
10337 if (platform_driver_register(&amvdec_vp9_driver)) {
10338 pr_err("failed to register amvdec_vp9 driver\n");
10339 return -ENODEV;
10340 }
10341
10342 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10343 amvdec_vp9_profile.profile =
10344 "8k, 10bit, dwrite, compressed, no_head";
10345 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10346 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10347 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10348 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10349 if (vdec_is_support_4k())
10350 amvdec_vp9_profile.profile =
10351 "4k, 10bit, dwrite, compressed";
10352 else
10353 amvdec_vp9_profile.profile =
10354 "10bit, dwrite, compressed";
10355 } else {
10356 if (vdec_is_support_4k())
10357 amvdec_vp9_profile.profile =
10358 "4k, 10bit, dwrite, compressed, no_head";
10359 else
10360 amvdec_vp9_profile.profile =
10361 "10bit, dwrite, compressed, no_head";
10362 }
10363
10364 } else {
10365 amvdec_vp9_profile.name = "vp9_unsupport";
10366 }
10367
10368 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10369 max_buf_num = MAX_BUF_NUM_LESS;
10370
10371 vcodec_profile_register(&amvdec_vp9_profile);
10372 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10373 amvdec_vp9_profile_mult.name = "mvp9";
10374 vcodec_profile_register(&amvdec_vp9_profile_mult);
10375 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10376 "vp9", vp9_configs, CONFIG_FOR_RW);
10377
10378 return 0;
10379}
10380
10381static void __exit amvdec_vp9_driver_remove_module(void)
10382{
10383 pr_debug("amvdec_vp9 module remove.\n");
10384#ifdef MULTI_INSTANCE_SUPPORT
10385 platform_driver_unregister(&ammvdec_vp9_driver);
10386#endif
10387 platform_driver_unregister(&amvdec_vp9_driver);
10388}
10389
10390/****************************************/
10391
10392module_param(bit_depth_luma, uint, 0664);
10393MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10394
10395module_param(bit_depth_chroma, uint, 0664);
10396MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10397
10398module_param(frame_width, uint, 0664);
10399MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10400
10401module_param(frame_height, uint, 0664);
10402MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10403
10404module_param(debug, uint, 0664);
10405MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10406
10407module_param(radr, uint, 0664);
10408MODULE_PARM_DESC(radr, "\n radr\n");
10409
10410module_param(rval, uint, 0664);
10411MODULE_PARM_DESC(rval, "\n rval\n");
10412
10413module_param(pop_shorts, uint, 0664);
10414MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10415
10416module_param(dbg_cmd, uint, 0664);
10417MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10418
10419module_param(dbg_skip_decode_index, uint, 0664);
10420MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10421
10422module_param(endian, uint, 0664);
10423MODULE_PARM_DESC(endian, "\n rval\n");
10424
10425module_param(step, uint, 0664);
10426MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10427
10428module_param(decode_pic_begin, uint, 0664);
10429MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10430
10431module_param(slice_parse_begin, uint, 0664);
10432MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10433
10434module_param(i_only_flag, uint, 0664);
10435MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10436
10437module_param(low_latency_flag, uint, 0664);
10438MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10439
10440module_param(no_head, uint, 0664);
10441MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10442
10443module_param(error_handle_policy, uint, 0664);
10444MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10445
10446module_param(buf_alloc_width, uint, 0664);
10447MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10448
10449module_param(buf_alloc_height, uint, 0664);
10450MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10451
10452module_param(buf_alloc_depth, uint, 0664);
10453MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10454
10455module_param(buf_alloc_size, uint, 0664);
10456MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10457
10458module_param(buffer_mode, uint, 0664);
10459MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10460
10461module_param(buffer_mode_dbg, uint, 0664);
10462MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10463/*USE_BUF_BLOCK*/
10464module_param(max_buf_num, uint, 0664);
10465MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10466
10467module_param(dynamic_buf_num_margin, uint, 0664);
10468MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10469
10470module_param(mv_buf_margin, uint, 0664);
10471MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10472
10473module_param(run_ready_min_buf_num, uint, 0664);
10474MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10475
10476/**/
10477
10478module_param(mem_map_mode, uint, 0664);
10479MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10480
10481#ifdef SUPPORT_10BIT
10482module_param(double_write_mode, uint, 0664);
10483MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10484
10485module_param(enable_mem_saving, uint, 0664);
10486MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10487
10488module_param(force_w_h, uint, 0664);
10489MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10490#endif
10491
10492module_param(force_fps, uint, 0664);
10493MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10494
10495module_param(max_decoding_time, uint, 0664);
10496MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10497
10498module_param(on_no_keyframe_skiped, uint, 0664);
10499MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10500
10501module_param(mcrcc_cache_alg_flag, uint, 0664);
10502MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10503
10504#ifdef MULTI_INSTANCE_SUPPORT
10505module_param(start_decode_buf_level, int, 0664);
10506MODULE_PARM_DESC(start_decode_buf_level,
10507 "\n vp9 start_decode_buf_level\n");
10508
10509module_param(decode_timeout_val, uint, 0664);
10510MODULE_PARM_DESC(decode_timeout_val,
10511 "\n vp9 decode_timeout_val\n");
10512
10513module_param(vp9_max_pic_w, uint, 0664);
10514MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10515
10516module_param(vp9_max_pic_h, uint, 0664);
10517MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10518
10519module_param_array(decode_frame_count, uint,
10520 &max_decode_instance_num, 0664);
10521
10522module_param_array(display_frame_count, uint,
10523 &max_decode_instance_num, 0664);
10524
10525module_param_array(max_process_time, uint,
10526 &max_decode_instance_num, 0664);
10527
10528module_param_array(run_count, uint,
10529 &max_decode_instance_num, 0664);
10530
10531module_param_array(input_empty, uint,
10532 &max_decode_instance_num, 0664);
10533
10534module_param_array(not_run_ready, uint,
10535 &max_decode_instance_num, 0664);
10536#endif
10537
10538#ifdef SUPPORT_FB_DECODING
10539module_param_array(not_run2_ready, uint,
10540 &max_decode_instance_num, 0664);
10541
10542module_param_array(run2_count, uint,
10543 &max_decode_instance_num, 0664);
10544
10545module_param(stage_buf_num, uint, 0664);
10546MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10547#endif
10548
10549module_param(udebug_flag, uint, 0664);
10550MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10551
10552module_param(udebug_pause_pos, uint, 0664);
10553MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10554
10555module_param(udebug_pause_val, uint, 0664);
10556MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10557
10558module_param(udebug_pause_decode_idx, uint, 0664);
10559MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10560
10561module_param(without_display_mode, uint, 0664);
10562MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10563
10564module_init(amvdec_vp9_driver_init_module);
10565module_exit(amvdec_vp9_driver_remove_module);
10566
10567MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
10568MODULE_LICENSE("GPL");
10569
10570
generated by cgit at 2024-05-17 08:47:08 (GMT)