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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
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1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../utils/vdec_v4l2_buffer_ops.h"
61
62#define MIX_STREAM_SUPPORT
63
64#include "vvp9.h"
65
66
67/*#define SUPPORT_FB_DECODING*/
68/*#define FB_DECODING_TEST_SCHEDULE*/
69
70
71#define HW_MASK_FRONT 0x1
72#define HW_MASK_BACK 0x2
73
74#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
75#define VP9D_MPP_REFINFO_DATA 0x3443
76#define VP9D_MPP_REF_SCALE_ENBL 0x3441
77#define HEVC_MPRED_CTRL4 0x324c
78#define HEVC_CM_HEADER_START_ADDR 0x3628
79#define HEVC_DBLK_CFGB 0x350b
80#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
81#define HEVC_SAO_MMU_VH1_ADDR 0x363b
82#define HEVC_SAO_MMU_VH0_ADDR 0x363a
83
84#define HEVC_MV_INFO 0x310d
85#define HEVC_QP_INFO 0x3137
86#define HEVC_SKIP_INFO 0x3136
87
88#define VP9_10B_DEC_IDLE 0
89#define VP9_10B_DEC_FRAME_HEADER 1
90#define VP9_10B_DEC_SLICE_SEGMENT 2
91#define VP9_10B_DECODE_SLICE 5
92#define VP9_10B_DISCARD_NAL 6
93#define VP9_DUMP_LMEM 7
94#define HEVC_DECPIC_DATA_DONE 0xa
95#define HEVC_DECPIC_DATA_ERROR 0xb
96#define HEVC_NAL_DECODE_DONE 0xe
97#define HEVC_DECODE_BUFEMPTY 0x20
98#define HEVC_DECODE_TIMEOUT 0x21
99#define HEVC_SEARCH_BUFEMPTY 0x22
100#define HEVC_DECODE_OVER_SIZE 0x23
101#define HEVC_S2_DECODING_DONE 0x50
102#define VP9_HEAD_PARSER_DONE 0xf0
103#define VP9_HEAD_SEARCH_DONE 0xf1
104#define VP9_EOS 0xf2
105#define HEVC_ACTION_DONE 0xff
106
107#define VF_POOL_SIZE 32
108
109#undef pr_info
110#define pr_info printk
111
112#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
113#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
114#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
115#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
116#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
117
118#define VP9_TRIGGER_FRAME_DONE 0x100
119#define VP9_TRIGGER_FRAME_ENABLE 0x200
120
121#define MV_MEM_UNIT 0x240
122/*---------------------------------------------------
123 * Include "parser_cmd.h"
124 *---------------------------------------------------
125 */
126#define PARSER_CMD_SKIP_CFG_0 0x0000090b
127
128#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
129
130#define PARSER_CMD_SKIP_CFG_2 0x001b1910
131
132#define PARSER_CMD_NUMBER 37
133
134/*#define HEVC_PIC_STRUCT_SUPPORT*/
135/* to remove, fix build error */
136
137/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
138
139#define MULTI_INSTANCE_SUPPORT
140#define SUPPORT_10BIT
141/* #define ERROR_HANDLE_DEBUG */
142
143#ifndef STAT_KTHREAD
144#define STAT_KTHREAD 0x40
145#endif
146
147#ifdef MULTI_INSTANCE_SUPPORT
148#define MAX_DECODE_INSTANCE_NUM 9
149#define MULTI_DRIVER_NAME "ammvdec_vp9"
150static unsigned int max_decode_instance_num
151 = MAX_DECODE_INSTANCE_NUM;
152static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
153static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
154static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
155static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
156static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
157static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
158
159static u32 decode_timeout_val = 200;
160static int start_decode_buf_level = 0x8000;
161static u32 work_buf_size;
162
163static u32 mv_buf_margin;
164
165/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
166/* double_write_mode:
167 * 0, no double write;
168 * 1, 1:1 ratio;
169 * 2, (1/4):(1/4) ratio;
170 * 3, (1/4):(1/4) ratio, with both compressed frame included
171 * 4, (1/2):(1/2) ratio;
172 * 0x10, double write only
173 * 0x100, if > 1080p,use mode 4,else use mode 1;
174 * 0x200, if > 1080p,use mode 2,else use mode 1;
175 * 0x300, if > 720p, use mode 4, else use mode 1;
176 */
177static u32 double_write_mode;
178
179#define DRIVER_NAME "amvdec_vp9"
180#define MODULE_NAME "amvdec_vp9"
181#define DRIVER_HEADER_NAME "amvdec_vp9_header"
182
183
184#define PUT_INTERVAL (HZ/100)
185#define ERROR_SYSTEM_RESET_COUNT 200
186
187#define PTS_NORMAL 0
188#define PTS_NONE_REF_USE_DURATION 1
189
190#define PTS_MODE_SWITCHING_THRESHOLD 3
191#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
192
193#define DUR2PTS(x) ((x)*90/96)
194
195struct VP9Decoder_s;
196static int vvp9_vf_states(struct vframe_states *states, void *);
197static struct vframe_s *vvp9_vf_peek(void *);
198static struct vframe_s *vvp9_vf_get(void *);
199static void vvp9_vf_put(struct vframe_s *, void *);
200static int vvp9_event_cb(int type, void *data, void *private_data);
201
202static int vvp9_stop(struct VP9Decoder_s *pbi);
203#ifdef MULTI_INSTANCE_SUPPORT
204static s32 vvp9_init(struct vdec_s *vdec);
205#else
206static s32 vvp9_init(struct VP9Decoder_s *pbi);
207#endif
208static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
209static int vvp9_local_init(struct VP9Decoder_s *pbi);
210static void vvp9_put_timer_func(unsigned long arg);
211static void dump_data(struct VP9Decoder_s *pbi, int size);
212static unsigned char get_data_check_sum
213 (struct VP9Decoder_s *pbi, int size);
214static void dump_pic_list(struct VP9Decoder_s *pbi);
215static int vp9_alloc_mmu(
216 struct VP9Decoder_s *pbi,
217 int cur_buf_idx,
218 int pic_width,
219 int pic_height,
220 unsigned short bit_depth,
221 unsigned int *mmu_index_adr);
222
223
224static const char vvp9_dec_id[] = "vvp9-dev";
225
226#define PROVIDER_NAME "decoder.vp9"
227#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
228
229static const struct vframe_operations_s vvp9_vf_provider = {
230 .peek = vvp9_vf_peek,
231 .get = vvp9_vf_get,
232 .put = vvp9_vf_put,
233 .event_cb = vvp9_event_cb,
234 .vf_states = vvp9_vf_states,
235};
236
237static struct vframe_provider_s vvp9_vf_prov;
238
239static u32 bit_depth_luma;
240static u32 bit_depth_chroma;
241static u32 frame_width;
242static u32 frame_height;
243static u32 video_signal_type;
244
245static u32 on_no_keyframe_skiped;
246
247#define PROB_SIZE (496 * 2 * 4)
248#define PROB_BUF_SIZE (0x5000)
249#define COUNT_BUF_SIZE (0x300 * 4 * 4)
250/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
251#define MAX_FRAME_4K_NUM 0x1200
252#define MAX_FRAME_8K_NUM 0x4800
253
254#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
255
256#ifdef SUPPORT_FB_DECODING
257/* register define */
258#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
259#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
260#define HEVC_ASSIST_HED_FB_ADDR 0x3008
261#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
262#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
263
264
265#define MAX_STAGE_PAGE_NUM 0x1200
266#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
267#endif
268static inline int div_r32(int64_t m, int n)
269{
270/*
271 *return (int)(m/n)
272 */
273#ifndef CONFIG_ARM64
274 int64_t qu = 0;
275 qu = div_s64(m, n);
276 return (int)qu;
277#else
278 return (int)(m/n);
279#endif
280}
281
282/*USE_BUF_BLOCK*/
283struct BUF_s {
284 int index;
285 unsigned int alloc_flag;
286 /*buffer */
287 unsigned int cma_page_count;
288 unsigned long alloc_addr;
289 unsigned long start_adr;
290 unsigned int size;
291
292 unsigned int free_start_adr;
293 ulong v4l_ref_buf_addr;
294 ulong header_addr;
295 u32 header_size;
296 u32 luma_size;
297} /*BUF_t */;
298
299struct MVBUF_s {
300 unsigned long start_adr;
301 unsigned int size;
302 int used_flag;
303} /*MVBUF_t */;
304
305 /* #undef BUFMGR_ONLY to enable hardware configuration */
306
307/*#define TEST_WR_PTR_INC*/
308/*#define WR_PTR_INC_NUM 128*/
309#define WR_PTR_INC_NUM 1
310
311#define SIMULATION
312#define DOS_PROJECT
313#undef MEMORY_MAP_IN_REAL_CHIP
314
315/*#undef DOS_PROJECT*/
316/*#define MEMORY_MAP_IN_REAL_CHIP*/
317
318/*#define BUFFER_MGR_ONLY*/
319/*#define CONFIG_HEVC_CLK_FORCED_ON*/
320/*#define ENABLE_SWAP_TEST*/
321#define MCRCC_ENABLE
322
323#define VP9_LPF_LVL_UPDATE
324/*#define DBG_LF_PRINT*/
325
326#ifdef VP9_10B_NV21
327#else
328#define LOSLESS_COMPRESS_MODE
329#endif
330
331#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
332#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
333
334
335
336typedef unsigned int u32;
337typedef unsigned short u16;
338
339#define VP9_DEBUG_BUFMGR 0x01
340#define VP9_DEBUG_BUFMGR_MORE 0x02
341#define VP9_DEBUG_BUFMGR_DETAIL 0x04
342#define VP9_DEBUG_OUT_PTS 0x10
343#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
344#define VP9_DEBUG_MERGE 0x200
345#define VP9_DEBUG_DBG_LF_PRINT 0x400
346#define VP9_DEBUG_REG 0x800
347#define VP9_DEBUG_2_STAGE 0x1000
348#define VP9_DEBUG_2_STAGE_MORE 0x2000
349#define VP9_DEBUG_QOS_INFO 0x4000
350#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
351#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
352#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
353#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
354#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
355#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
356#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
357#define VP9_DEBUG_DUMP_DATA 0x800000
358#define VP9_DEBUG_CACHE 0x1000000
359#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
360#define IGNORE_PARAM_FROM_CONFIG 0x8000000
361#ifdef MULTI_INSTANCE_SUPPORT
362#define PRINT_FLAG_ERROR 0x0
363#define PRINT_FLAG_V4L_DETAIL 0x10000000
364#define PRINT_FLAG_VDEC_STATUS 0x20000000
365#define PRINT_FLAG_VDEC_DETAIL 0x40000000
366#define PRINT_FLAG_VDEC_DATA 0x80000000
367#endif
368
369static u32 debug;
370static bool is_reset;
371/*for debug*/
372/*
373 udebug_flag:
374 bit 0, enable ucode print
375 bit 1, enable ucode detail print
376 bit [31:16] not 0, pos to dump lmem
377 bit 2, pop bits to lmem
378 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
379*/
380static u32 udebug_flag;
381/*
382 when udebug_flag[1:0] is not 0
383 udebug_pause_pos not 0,
384 pause position
385*/
386static u32 udebug_pause_pos;
387/*
388 when udebug_flag[1:0] is not 0
389 and udebug_pause_pos is not 0,
390 pause only when DEBUG_REG2 is equal to this val
391*/
392static u32 udebug_pause_val;
393
394static u32 udebug_pause_decode_idx;
395
396static u32 without_display_mode;
397
398#define DEBUG_REG
399#ifdef DEBUG_REG
400void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
401{
402 if (debug & VP9_DEBUG_REG)
403 pr_info("%s(%x, %x)\n", __func__, adr, val);
404 if (adr != 0)
405 WRITE_VREG(adr, val);
406}
407
408#undef WRITE_VREG
409#define WRITE_VREG WRITE_VREG_DBG2
410#endif
411
412#define FRAME_CNT_WINDOW_SIZE 59
413#define RATE_CORRECTION_THRESHOLD 5
414/**************************************************
415
416VP9 buffer management start
417
418***************************************************/
419
420#define MMU_COMPRESS_HEADER_SIZE 0x48000
421#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
422#define MAX_SIZE_8K (8192 * 4608)
423#define MAX_SIZE_4K (4096 * 2304)
424#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
425
426#define INVALID_IDX -1 /* Invalid buffer index.*/
427
428#define RPM_BEGIN 0x200
429#define RPM_END 0x280
430
431union param_u {
432 struct {
433 unsigned short data[RPM_END - RPM_BEGIN];
434 } l;
435 struct {
436 /* from ucode lmem, do not change this struct */
437 unsigned short profile;
438 unsigned short show_existing_frame;
439 unsigned short frame_to_show_idx;
440 unsigned short frame_type; /*1 bit*/
441 unsigned short show_frame; /*1 bit*/
442 unsigned short error_resilient_mode; /*1 bit*/
443 unsigned short intra_only; /*1 bit*/
444 unsigned short display_size_present; /*1 bit*/
445 unsigned short reset_frame_context;
446 unsigned short refresh_frame_flags;
447 unsigned short width;
448 unsigned short height;
449 unsigned short display_width;
450 unsigned short display_height;
451 /*
452 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
453 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
454 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
455 */
456 unsigned short ref_info;
457 /*
458 *bit[2]: same_frame_size0
459 *bit[1]: same_frame_size1
460 *bit[0]: same_frame_size2
461 */
462 unsigned short same_frame_size;
463
464 unsigned short mode_ref_delta_enabled;
465 unsigned short ref_deltas[4];
466 unsigned short mode_deltas[2];
467 unsigned short filter_level;
468 unsigned short sharpness_level;
469 unsigned short bit_depth;
470 unsigned short seg_quant_info[8];
471 unsigned short seg_enabled;
472 unsigned short seg_abs_delta;
473 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
474 unsigned short seg_lf_info[8];
475 } p;
476};
477
478
479struct vpx_codec_frame_buffer_s {
480 uint8_t *data; /**< Pointer to the data buffer */
481 size_t size; /**< Size of data in bytes */
482 void *priv; /**< Frame's private data */
483};
484
485enum vpx_color_space_t {
486 VPX_CS_UNKNOWN = 0, /**< Unknown */
487 VPX_CS_BT_601 = 1, /**< BT.601 */
488 VPX_CS_BT_709 = 2, /**< BT.709 */
489 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
490 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
491 VPX_CS_BT_2020 = 5, /**< BT.2020 */
492 VPX_CS_RESERVED = 6, /**< Reserved */
493 VPX_CS_SRGB = 7 /**< sRGB */
494}; /**< alias for enum vpx_color_space */
495
496enum vpx_bit_depth_t {
497 VPX_BITS_8 = 8, /**< 8 bits */
498 VPX_BITS_10 = 10, /**< 10 bits */
499 VPX_BITS_12 = 12, /**< 12 bits */
500};
501
502#define MAX_SLICE_NUM 1024
503struct PIC_BUFFER_CONFIG_s {
504 int index;
505 int BUF_index;
506 int mv_buf_index;
507 int comp_body_size;
508 int buf_size;
509 int vf_ref;
510 int y_canvas_index;
511 int uv_canvas_index;
512#ifdef MULTI_INSTANCE_SUPPORT
513 struct canvas_config_s canvas_config[2];
514#endif
515 int decode_idx;
516 int slice_type;
517 int stream_offset;
518 u32 pts;
519 u64 pts64;
520 u64 timestamp;
521 uint8_t error_mark;
522 /**/
523 int slice_idx;
524 /*buffer*/
525 unsigned long header_adr;
526 unsigned long mpred_mv_wr_start_addr;
527 /*unsigned long mc_y_adr;
528 *unsigned long mc_u_v_adr;
529 */
530 unsigned int dw_y_adr;
531 unsigned int dw_u_v_adr;
532 int mc_canvas_y;
533 int mc_canvas_u_v;
534
535 int lcu_total;
536 /**/
537 int y_width;
538 int y_height;
539 int y_crop_width;
540 int y_crop_height;
541 int y_stride;
542
543 int uv_width;
544 int uv_height;
545 int uv_crop_width;
546 int uv_crop_height;
547 int uv_stride;
548
549 int alpha_width;
550 int alpha_height;
551 int alpha_stride;
552
553 uint8_t *y_buffer;
554 uint8_t *u_buffer;
555 uint8_t *v_buffer;
556 uint8_t *alpha_buffer;
557
558 uint8_t *buffer_alloc;
559 int buffer_alloc_sz;
560 int border;
561 int frame_size;
562 int subsampling_x;
563 int subsampling_y;
564 unsigned int bit_depth;
565 enum vpx_color_space_t color_space;
566
567 int corrupted;
568 int flags;
569 unsigned long cma_alloc_addr;
570
571 int double_write_mode;
572
573 /* picture qos infomation*/
574 int max_qp;
575 int avg_qp;
576 int min_qp;
577 int max_skip;
578 int avg_skip;
579 int min_skip;
580 int max_mv;
581 int min_mv;
582 int avg_mv;
583
584 bool vframe_bound;
585} PIC_BUFFER_CONFIG;
586
587enum BITSTREAM_PROFILE {
588 PROFILE_0,
589 PROFILE_1,
590 PROFILE_2,
591 PROFILE_3,
592 MAX_PROFILES
593};
594
595enum FRAME_TYPE {
596 KEY_FRAME = 0,
597 INTER_FRAME = 1,
598 FRAME_TYPES,
599};
600
601enum REFERENCE_MODE {
602 SINGLE_REFERENCE = 0,
603 COMPOUND_REFERENCE = 1,
604 REFERENCE_MODE_SELECT = 2,
605 REFERENCE_MODES = 3,
606};
607
608#define NONE -1
609#define INTRA_FRAME 0
610#define LAST_FRAME 1
611#define GOLDEN_FRAME 2
612#define ALTREF_FRAME 3
613#define MAX_REF_FRAMES 4
614
615#define REFS_PER_FRAME 3
616
617#define REF_FRAMES_LOG2 3
618#define REF_FRAMES (1 << REF_FRAMES_LOG2)
619#define REF_FRAMES_4K (6)
620
621/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
622 *in parallel, 3 for scaled references on the encoder.
623 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
624 * // of framebuffers.
625 *TODO(jkoleszar): These 3 extra references could probably come from the
626 *normal reference pool.
627 */
628#define FRAME_BUFFERS (REF_FRAMES + 16)
629#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
630#define MAX_BUF_NUM (FRAME_BUFFERS)
631#define MV_BUFFER_NUM FRAME_BUFFERS
632#ifdef SUPPORT_FB_DECODING
633#define STAGE_MAX_BUFFERS 16
634#else
635#define STAGE_MAX_BUFFERS 0
636#endif
637
638#define FRAME_CONTEXTS_LOG2 2
639#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
640/*buffer + header buffer + workspace*/
641#ifdef MV_USE_FIXED_BUF
642#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
643#define VF_BUFFER_IDX(n) (n)
644#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
645#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
646#else
647#define MAX_BMMU_BUFFER_NUM \
648 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
649#define VF_BUFFER_IDX(n) (n)
650#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
651#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
652#define WORK_SPACE_BUF_ID \
653 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
654#endif
655
656struct RefCntBuffer_s {
657 int ref_count;
658 /*MV_REF *mvs;*/
659 int mi_rows;
660 int mi_cols;
661 struct vpx_codec_frame_buffer_s raw_frame_buffer;
662 struct PIC_BUFFER_CONFIG_s buf;
663
664/*The Following variables will only be used in frame parallel decode.
665 *
666 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
667 *that no FrameWorker owns, or is decoding, this buffer.
668 *VP9Worker *frame_worker_owner;
669 *
670 *row and col indicate which position frame has been decoded to in real
671 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
672 *when the frame is fully decoded.
673 */
674 int row;
675 int col;
676} RefCntBuffer;
677
678struct RefBuffer_s {
679/*TODO(dkovalev): idx is not really required and should be removed, now it
680 *is used in vp9_onyxd_if.c
681 */
682 int idx;
683 struct PIC_BUFFER_CONFIG_s *buf;
684 /*struct scale_factors sf;*/
685} RefBuffer;
686
687struct InternalFrameBuffer_s {
688 uint8_t *data;
689 size_t size;
690 int in_use;
691} InternalFrameBuffer;
692
693struct InternalFrameBufferList_s {
694 int num_internal_frame_buffers;
695 struct InternalFrameBuffer_s *int_fb;
696} InternalFrameBufferList;
697
698struct BufferPool_s {
699/*Protect BufferPool from being accessed by several FrameWorkers at
700 *the same time during frame parallel decode.
701 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
702 *
703 *Private data associated with the frame buffer callbacks.
704 *void *cb_priv;
705 *
706 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
707 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
708 */
709
710 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
711
712/*Frame buffers allocated internally by the codec.*/
713 struct InternalFrameBufferList_s int_frame_buffers;
714 unsigned long flags;
715 spinlock_t lock;
716
717} BufferPool;
718
719#define lock_buffer_pool(pool, flags) \
720 spin_lock_irqsave(&pool->lock, flags)
721
722#define unlock_buffer_pool(pool, flags) \
723 spin_unlock_irqrestore(&pool->lock, flags)
724
725struct VP9_Common_s {
726 enum vpx_color_space_t color_space;
727 int width;
728 int height;
729 int display_width;
730 int display_height;
731 int last_width;
732 int last_height;
733
734 int subsampling_x;
735 int subsampling_y;
736
737 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
738
739 struct PIC_BUFFER_CONFIG_s *frame_to_show;
740 struct RefCntBuffer_s *prev_frame;
741
742 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
743 struct RefCntBuffer_s *cur_frame;
744
745 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
746
747 /*Prepare ref_frame_map for the next frame.
748 *Only used in frame parallel decode.
749 */
750 int next_ref_frame_map[REF_FRAMES];
751
752 /* TODO(jkoleszar): could expand active_ref_idx to 4,
753 *with 0 as intra, and roll new_fb_idx into it.
754 */
755
756 /*Each frame can reference REFS_PER_FRAME buffers*/
757 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
758
759 int prev_fb_idx;
760 int new_fb_idx;
761 int cur_fb_idx_mmu;
762 /*last frame's frame type for motion search*/
763 enum FRAME_TYPE last_frame_type;
764 enum FRAME_TYPE frame_type;
765
766 int show_frame;
767 int last_show_frame;
768 int show_existing_frame;
769
770 /*Flag signaling that the frame is encoded using only INTRA modes.*/
771 uint8_t intra_only;
772 uint8_t last_intra_only;
773
774 int allow_high_precision_mv;
775
776 /*Flag signaling that the frame context should be reset to default
777 *values. 0 or 1 implies don't reset, 2 reset just the context
778 *specified in the frame header, 3 reset all contexts.
779 */
780 int reset_frame_context;
781
782 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
783 * MODE_INFO (8-pixel) units.
784 */
785 int MBs;
786 int mb_rows, mi_rows;
787 int mb_cols, mi_cols;
788 int mi_stride;
789
790 /*Whether to use previous frame's motion vectors for prediction.*/
791 int use_prev_frame_mvs;
792
793 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
794
795 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
796
797 /*struct loopfilter lf;*/
798 /*struct segmentation seg;*/
799
800 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
801 /* in pbi.*/
802 int frame_parallel_decode; /* frame-based threading.*/
803
804 /*Context probabilities for reference frame prediction*/
805 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
806 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
807 enum REFERENCE_MODE reference_mode;
808
809 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
810 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
811 /*unsigned int frame_context_idx; *//* Context to use/update */
812 /*FRAME_COUNTS counts;*/
813
814 unsigned int current_video_frame;
815 enum BITSTREAM_PROFILE profile;
816
817 enum vpx_bit_depth_t bit_depth;
818
819 int error_resilient_mode;
820 int frame_parallel_decoding_mode;
821
822 int byte_alignment;
823 int skip_loop_filter;
824
825 /*External BufferPool passed from outside.*/
826 struct BufferPool_s *buffer_pool;
827
828 int above_context_alloc_cols;
829
830};
831
832static void set_canvas(struct VP9Decoder_s *pbi,
833 struct PIC_BUFFER_CONFIG_s *pic_config);
834static int prepare_display_buf(struct VP9Decoder_s *pbi,
835 struct PIC_BUFFER_CONFIG_s *pic_config);
836
837static void fill_frame_info(struct VP9Decoder_s *pbi,
838 struct PIC_BUFFER_CONFIG_s *frame,
839 unsigned int framesize,
840 unsigned int pts);
841
842static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
843{
844 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
845}
846
847static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
848{
849 const int ref_index = *idx;
850
851 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
852 bufs[ref_index].ref_count--;
853 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
854 * ref_index, bufs[ref_index].ref_count);
855 */
856 }
857
858 *idx = new_idx;
859
860 bufs[new_idx].ref_count++;
861 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
862 * new_idx, bufs[new_idx].ref_count);
863 */
864}
865
866int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
867{
868 struct InternalFrameBuffer_s *const int_fb =
869 (struct InternalFrameBuffer_s *)fb->priv;
870 if (int_fb)
871 int_fb->in_use = 0;
872 return 0;
873}
874
875static int compute_losless_comp_body_size(int width, int height,
876 uint8_t is_bit_depth_10);
877
878static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
879 int print_header_info)
880{
881 cm->display_width = cm->width;
882 cm->display_height = cm->height;
883 if (params->p.display_size_present) {
884 if (print_header_info)
885 pr_info(" * 1-bit display_size_present read : 1\n");
886 cm->display_width = params->p.display_width;
887 cm->display_height = params->p.display_height;
888 /*vp9_read_frame_size(rb, &cm->display_width,
889 * &cm->display_height);
890 */
891 } else {
892 if (print_header_info)
893 pr_info(" * 1-bit display_size_present read : 0\n");
894 }
895}
896
897
898uint8_t print_header_info = 0;
899
900struct buff_s {
901 u32 buf_start;
902 u32 buf_size;
903 u32 buf_end;
904} buff_t;
905
906struct BuffInfo_s {
907 u32 max_width;
908 u32 max_height;
909 u32 start_adr;
910 u32 end_adr;
911 struct buff_s ipp;
912 struct buff_s sao_abv;
913 struct buff_s sao_vb;
914 struct buff_s short_term_rps;
915 struct buff_s vps;
916 struct buff_s sps;
917 struct buff_s pps;
918 struct buff_s sao_up;
919 struct buff_s swap_buf;
920 struct buff_s swap_buf2;
921 struct buff_s scalelut;
922 struct buff_s dblk_para;
923 struct buff_s dblk_data;
924 struct buff_s seg_map;
925 struct buff_s mmu_vbh;
926 struct buff_s cm_header;
927 struct buff_s mpred_above;
928#ifdef MV_USE_FIXED_BUF
929 struct buff_s mpred_mv;
930#endif
931 struct buff_s rpm;
932 struct buff_s lmem;
933} BuffInfo_t;
934#ifdef MULTI_INSTANCE_SUPPORT
935#define DEC_RESULT_NONE 0
936#define DEC_RESULT_DONE 1
937#define DEC_RESULT_AGAIN 2
938#define DEC_RESULT_CONFIG_PARAM 3
939#define DEC_RESULT_ERROR 4
940#define DEC_INIT_PICLIST 5
941#define DEC_UNINIT_PICLIST 6
942#define DEC_RESULT_GET_DATA 7
943#define DEC_RESULT_GET_DATA_RETRY 8
944#define DEC_RESULT_EOS 9
945#define DEC_RESULT_FORCE_EXIT 10
946#define DEC_V4L2_CONTINUE_DECODING 18
947
948#define DEC_S1_RESULT_NONE 0
949#define DEC_S1_RESULT_DONE 1
950#define DEC_S1_RESULT_FORCE_EXIT 2
951#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
952
953#ifdef FB_DECODING_TEST_SCHEDULE
954#define TEST_SET_NONE 0
955#define TEST_SET_PIC_DONE 1
956#define TEST_SET_S2_DONE 2
957#endif
958
959static void vp9_work(struct work_struct *work);
960#endif
961struct loop_filter_info_n;
962struct loopfilter;
963struct segmentation;
964
965#ifdef SUPPORT_FB_DECODING
966static void mpred_process(struct VP9Decoder_s *pbi);
967static void vp9_s1_work(struct work_struct *work);
968
969struct stage_buf_s {
970 int index;
971 unsigned short rpm[RPM_END - RPM_BEGIN];
972};
973
974static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
975
976static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
977
978#ifdef FB_DECODING_TEST_SCHEDULE
979u32 stage_buf_num; /* = 16;*/
980#else
981u32 stage_buf_num;
982#endif
983#endif
984
985struct VP9Decoder_s {
986#ifdef MULTI_INSTANCE_SUPPORT
987 unsigned char index;
988
989 struct device *cma_dev;
990 struct platform_device *platform_dev;
991 void (*vdec_cb)(struct vdec_s *, void *);
992 void *vdec_cb_arg;
993 struct vframe_chunk_s *chunk;
994 int dec_result;
995 struct work_struct work;
996 struct work_struct set_clk_work;
997 u32 start_shift_bytes;
998
999 struct BuffInfo_s work_space_buf_store;
1000 unsigned long buf_start;
1001 u32 buf_size;
1002 u32 cma_alloc_count;
1003 unsigned long cma_alloc_addr;
1004 uint8_t eos;
1005 unsigned long int start_process_time;
1006 unsigned last_lcu_idx;
1007 int decode_timeout_count;
1008 unsigned timeout_num;
1009 int save_buffer_mode;
1010
1011 int double_write_mode;
1012#endif
1013 long used_4k_num;
1014
1015 unsigned char m_ins_flag;
1016 char *provider_name;
1017 union param_u param;
1018 int frame_count;
1019 int pic_count;
1020 u32 stat;
1021 struct timer_list timer;
1022 u32 frame_dur;
1023 u32 frame_ar;
1024 int fatal_error;
1025 uint8_t init_flag;
1026 uint8_t first_sc_checked;
1027 uint8_t process_busy;
1028#define PROC_STATE_INIT 0
1029#define PROC_STATE_DECODESLICE 1
1030#define PROC_STATE_SENDAGAIN 2
1031 uint8_t process_state;
1032 u32 ucode_pause_pos;
1033
1034 int show_frame_num;
1035 struct buff_s mc_buf_spec;
1036 struct dec_sysinfo vvp9_amstream_dec_info;
1037 void *rpm_addr;
1038 void *lmem_addr;
1039 dma_addr_t rpm_phy_addr;
1040 dma_addr_t lmem_phy_addr;
1041 unsigned short *lmem_ptr;
1042 unsigned short *debug_ptr;
1043
1044 void *prob_buffer_addr;
1045 void *count_buffer_addr;
1046 dma_addr_t prob_buffer_phy_addr;
1047 dma_addr_t count_buffer_phy_addr;
1048
1049 void *frame_mmu_map_addr;
1050 dma_addr_t frame_mmu_map_phy_addr;
1051
1052 unsigned int use_cma_flag;
1053
1054 struct BUF_s m_BUF[MAX_BUF_NUM];
1055 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1056 u32 used_buf_num;
1057 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1058 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1059 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1060 struct vframe_s vfpool[VF_POOL_SIZE];
1061 u32 vf_pre_count;
1062 u32 vf_get_count;
1063 u32 vf_put_count;
1064 int buf_num;
1065 int pic_num;
1066 int lcu_size_log2;
1067 unsigned int losless_comp_body_size;
1068
1069 u32 video_signal_type;
1070
1071 int pts_mode;
1072 int last_lookup_pts;
1073 int last_pts;
1074 u64 last_lookup_pts_us64;
1075 u64 last_pts_us64;
1076 u64 shift_byte_count;
1077
1078 u32 pts_unstable;
1079 u32 frame_cnt_window;
1080 u32 pts1, pts2;
1081 u32 last_duration;
1082 u32 duration_from_pts_done;
1083 bool vp9_first_pts_ready;
1084
1085 u32 shift_byte_count_lo;
1086 u32 shift_byte_count_hi;
1087 int pts_mode_switching_count;
1088 int pts_mode_recovery_count;
1089
1090 bool get_frame_dur;
1091 u32 saved_resolution;
1092
1093 /**/
1094 struct VP9_Common_s common;
1095 struct RefCntBuffer_s *cur_buf;
1096 int refresh_frame_flags;
1097 uint8_t need_resync;
1098 uint8_t hold_ref_buf;
1099 uint8_t ready_for_new_data;
1100 struct BufferPool_s vp9_buffer_pool;
1101
1102 struct BuffInfo_s *work_space_buf;
1103
1104 struct buff_s *mc_buf;
1105
1106 unsigned int frame_width;
1107 unsigned int frame_height;
1108
1109 unsigned short *rpm_ptr;
1110 int init_pic_w;
1111 int init_pic_h;
1112 int lcu_total;
1113 int lcu_size;
1114
1115 int slice_type;
1116
1117 int skip_flag;
1118 int decode_idx;
1119 int slice_idx;
1120 uint8_t has_keyframe;
1121 uint8_t wait_buf;
1122 uint8_t error_flag;
1123
1124 /* bit 0, for decoding; bit 1, for displaying */
1125 uint8_t ignore_bufmgr_error;
1126 int PB_skip_mode;
1127 int PB_skip_count_after_decoding;
1128 /*hw*/
1129
1130 /*lf*/
1131 int default_filt_lvl;
1132 struct loop_filter_info_n *lfi;
1133 struct loopfilter *lf;
1134 struct segmentation *seg_4lf;
1135 /**/
1136 struct vdec_info *gvs;
1137
1138 u32 pre_stream_offset;
1139
1140 unsigned int dec_status;
1141 u32 last_put_idx;
1142 int new_frame_displayed;
1143 void *mmu_box;
1144 void *bmmu_box;
1145 int mmu_enable;
1146 struct vframe_master_display_colour_s vf_dp;
1147 struct firmware_s *fw;
1148 int max_pic_w;
1149 int max_pic_h;
1150#ifdef SUPPORT_FB_DECODING
1151 int dec_s1_result;
1152 int s1_test_cmd;
1153 struct work_struct s1_work;
1154 int used_stage_buf_num;
1155 int s1_pos;
1156 int s2_pos;
1157 void *stage_mmu_map_addr;
1158 dma_addr_t stage_mmu_map_phy_addr;
1159 struct stage_buf_s *s1_buf;
1160 struct stage_buf_s *s2_buf;
1161 struct stage_buf_s *stage_bufs
1162 [STAGE_MAX_BUFFERS];
1163 unsigned char run2_busy;
1164
1165 int s1_mv_buf_index;
1166 int s1_mv_buf_index_pre;
1167 int s1_mv_buf_index_pre_pre;
1168 unsigned long s1_mpred_mv_wr_start_addr;
1169 unsigned long s1_mpred_mv_wr_start_addr_pre;
1170 unsigned short s1_intra_only;
1171 unsigned short s1_frame_type;
1172 unsigned short s1_width;
1173 unsigned short s1_height;
1174 unsigned short s1_last_show_frame;
1175 union param_u s1_param;
1176 u8 back_not_run_ready;
1177#endif
1178 int need_cache_size;
1179 u64 sc_start_time;
1180 bool postproc_done;
1181 int low_latency_flag;
1182 bool no_head;
1183 bool pic_list_init_done;
1184 bool pic_list_init_done2;
1185 bool is_used_v4l;
1186 void *v4l2_ctx;
1187 bool v4l_params_parsed;
1188 int frameinfo_enable;
1189 struct vframe_qos_s vframe_qos;
1190 u32 mem_map_mode;
1191 u32 dynamic_buf_num_margin;
1192};
1193
1194static int vp9_print(struct VP9Decoder_s *pbi,
1195 int flag, const char *fmt, ...)
1196{
1197#define HEVC_PRINT_BUF 256
1198 unsigned char buf[HEVC_PRINT_BUF];
1199 int len = 0;
1200
1201 if (pbi == NULL ||
1202 (flag == 0) ||
1203 (debug & flag)) {
1204 va_list args;
1205
1206 va_start(args, fmt);
1207 if (pbi)
1208 len = sprintf(buf, "[%d]", pbi->index);
1209 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1210 pr_debug("%s", buf);
1211 va_end(args);
1212 }
1213 return 0;
1214}
1215
1216static int is_oversize(int w, int h)
1217{
1218 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1219 MAX_SIZE_8K : MAX_SIZE_4K;
1220
1221 if (w <= 0 || h <= 0)
1222 return true;
1223
1224 if (h != 0 && (w > max / h))
1225 return true;
1226
1227 return false;
1228}
1229
1230static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1231 struct PIC_BUFFER_CONFIG_s *pic);
1232
1233static void resize_context_buffers(struct VP9Decoder_s *pbi,
1234 struct VP9_Common_s *cm, int width, int height)
1235{
1236 if (cm->width != width || cm->height != height) {
1237 /* to do ..*/
1238 if (pbi != NULL) {
1239 pbi->vp9_first_pts_ready = 0;
1240 pbi->duration_from_pts_done = 0;
1241 }
1242 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1243 cm->height, width, height);
1244
1245 if (pbi->is_used_v4l) {
1246 struct PIC_BUFFER_CONFIG_s *pic = &cm->cur_frame->buf;
1247
1248 /* resolution change happend need to reconfig buffs if true. */
1249 if (pic->y_crop_width != width || pic->y_crop_height != height) {
1250 int i;
1251 for (i = 0; i < pbi->used_buf_num; i++) {
1252 pic = &cm->buffer_pool->frame_bufs[i].buf;
1253 pic->y_crop_width = width;
1254 pic->y_crop_height = height;
1255 if (!v4l_alloc_and_config_pic(pbi, pic))
1256 set_canvas(pbi, pic);
1257 else
1258 vp9_print(pbi, 0,
1259 "v4l: reconfig buff fail.\n");
1260 }
1261 }
1262 }
1263
1264 cm->width = width;
1265 cm->height = height;
1266 }
1267 /*
1268 *if (cm->cur_frame->mvs == NULL ||
1269 * cm->mi_rows > cm->cur_frame->mi_rows ||
1270 * cm->mi_cols > cm->cur_frame->mi_cols) {
1271 * resize_mv_buffer(cm);
1272 *}
1273 */
1274}
1275
1276static int valid_ref_frame_size(int ref_width, int ref_height,
1277 int this_width, int this_height) {
1278 return 2 * this_width >= ref_width &&
1279 2 * this_height >= ref_height &&
1280 this_width <= 16 * ref_width &&
1281 this_height <= 16 * ref_height;
1282}
1283
1284/*
1285 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1286 * int ref_xss, int ref_yss,
1287 * enum vpx_bit_depth_t this_bit_depth,
1288 * int this_xss, int this_yss) {
1289 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1290 * ref_yss == this_yss;
1291 *}
1292 */
1293
1294
1295static int setup_frame_size(
1296 struct VP9Decoder_s *pbi,
1297 struct VP9_Common_s *cm, union param_u *params,
1298 unsigned int *mmu_index_adr,
1299 int print_header_info) {
1300 int width, height;
1301 struct BufferPool_s * const pool = cm->buffer_pool;
1302 struct PIC_BUFFER_CONFIG_s *ybf;
1303 int ret = 0;
1304
1305 width = params->p.width;
1306 height = params->p.height;
1307 if (is_oversize(width, height)) {
1308 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1309 return -1;
1310 }
1311
1312 /*vp9_read_frame_size(rb, &width, &height);*/
1313 if (print_header_info)
1314 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1315 if (print_header_info)
1316 pr_info
1317 (" * 16-bits h read : %d (height : %d)\n", width, height);
1318
1319 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1320#ifdef VP9_10B_HED_FB
1321 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1322#endif
1323 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1324 ret = vp9_alloc_mmu(pbi,
1325 cm->new_fb_idx,
1326 params->p.width,
1327 params->p.height,
1328 params->p.bit_depth,
1329 mmu_index_adr);
1330 if (ret != 0) {
1331 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1332 cm->new_fb_idx,
1333 ret);
1334 return ret;
1335 }
1336 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1337 }
1338
1339 resize_context_buffers(pbi, cm, width, height);
1340 setup_display_size(cm, params, print_header_info);
1341#if 0
1342 lock_buffer_pool(pool);
1343 if (vp9_realloc_frame_buffer(
1344 get_frame_new_buffer(cm), cm->width, cm->height,
1345 cm->subsampling_x, cm->subsampling_y,
1346#if CONFIG_VP9_HIGHBITDEPTH
1347 cm->use_highbitdepth,
1348#endif
1349 VP9_DEC_BORDER_IN_PIXELS,
1350 cm->byte_alignment,
1351 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1352 pool->get_fb_cb, pool->cb_priv)) {
1353 unlock_buffer_pool(pool);
1354 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1355 "Failed to allocate frame buffer");
1356 }
1357 unlock_buffer_pool(pool);
1358#else
1359 /* porting */
1360 ybf = get_frame_new_buffer(cm);
1361 if (!ybf)
1362 return -1;
1363
1364 ybf->y_crop_width = width;
1365 ybf->y_crop_height = height;
1366 ybf->bit_depth = params->p.bit_depth;
1367#endif
1368 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1369 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1370 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1371 (unsigned int)cm->bit_depth;
1372 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1373 return ret;
1374}
1375
1376static int setup_frame_size_with_refs(
1377 struct VP9Decoder_s *pbi,
1378 struct VP9_Common_s *cm,
1379 union param_u *params,
1380 unsigned int *mmu_index_adr,
1381 int print_header_info) {
1382
1383 int width, height;
1384 int found = 0, i;
1385 int has_valid_ref_frame = 0;
1386 struct PIC_BUFFER_CONFIG_s *ybf;
1387 struct BufferPool_s * const pool = cm->buffer_pool;
1388 int ret = 0;
1389
1390 for (i = 0; i < REFS_PER_FRAME; ++i) {
1391 if ((params->p.same_frame_size >>
1392 (REFS_PER_FRAME - i - 1)) & 0x1) {
1393 struct PIC_BUFFER_CONFIG_s *const buf =
1394 cm->frame_refs[i].buf;
1395 /*if (print_header_info)
1396 * pr_info
1397 * ("1-bit same_frame_size[%d] read : 1\n", i);
1398 */
1399 width = buf->y_crop_width;
1400 height = buf->y_crop_height;
1401 /*if (print_header_info)
1402 * pr_info
1403 * (" - same_frame_size width : %d\n", width);
1404 */
1405 /*if (print_header_info)
1406 * pr_info
1407 * (" - same_frame_size height : %d\n", height);
1408 */
1409 found = 1;
1410 break;
1411 } else {
1412 /*if (print_header_info)
1413 * pr_info
1414 * ("1-bit same_frame_size[%d] read : 0\n", i);
1415 */
1416 }
1417 }
1418
1419 if (!found) {
1420 /*vp9_read_frame_size(rb, &width, &height);*/
1421 width = params->p.width;
1422 height = params->p.height;
1423 /*if (print_header_info)
1424 * pr_info
1425 * (" * 16-bits w read : %d (width : %d)\n",
1426 * width, height);
1427 *if (print_header_info)
1428 * pr_info
1429 * (" * 16-bits h read : %d (height : %d)\n",
1430 * width, height);
1431 */
1432 }
1433
1434 if (is_oversize(width, height)) {
1435 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1436 return -1;
1437 }
1438
1439 params->p.width = width;
1440 params->p.height = height;
1441
1442 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1443 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1444 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1445 *cm->prev_fb_idx = cm->new_fb_idx;
1446 */
1447 /* pr_info
1448 * ("[DEBUG DEBUG]Before alloc_mmu,
1449 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1450 * cm->prev_fb_idx, cm->new_fb_idx);
1451 */
1452 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1453 params->p.width, params->p.height,
1454 params->p.bit_depth, mmu_index_adr);
1455 if (ret != 0) {
1456 pr_err("can't alloc need mmu,idx %d\r\n",
1457 cm->new_fb_idx);
1458 return ret;
1459 }
1460 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1461 }
1462
1463 /*Check to make sure at least one of frames that this frame references
1464 *has valid dimensions.
1465 */
1466 for (i = 0; i < REFS_PER_FRAME; ++i) {
1467 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1468
1469 has_valid_ref_frame |=
1470 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1471 ref_frame->buf->y_crop_height,
1472 width, height);
1473 }
1474 if (!has_valid_ref_frame) {
1475 pr_err("Error: Referenced frame has invalid size\r\n");
1476 return -1;
1477 }
1478#if 0
1479 for (i = 0; i < REFS_PER_FRAME; ++i) {
1480 struct RefBuffer_s * const ref_frame =
1481 &cm->frame_refs[i];
1482 if (!valid_ref_frame_img_fmt(
1483 ref_frame->buf->bit_depth,
1484 ref_frame->buf->subsampling_x,
1485 ref_frame->buf->subsampling_y,
1486 cm->bit_depth,
1487 cm->subsampling_x,
1488 cm->subsampling_y))
1489 pr_err
1490 ("Referenced frame incompatible color fmt\r\n");
1491 return -1;
1492 }
1493#endif
1494 resize_context_buffers(pbi, cm, width, height);
1495 setup_display_size(cm, params, print_header_info);
1496
1497#if 0
1498 lock_buffer_pool(pool);
1499 if (vp9_realloc_frame_buffer(
1500 get_frame_new_buffer(cm), cm->width, cm->height,
1501 cm->subsampling_x, cm->subsampling_y,
1502#if CONFIG_VP9_HIGHBITDEPTH
1503 cm->use_highbitdepth,
1504#endif
1505 VP9_DEC_BORDER_IN_PIXELS,
1506 cm->byte_alignment,
1507 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1508 pool->get_fb_cb,
1509 pool->cb_priv)) {
1510 unlock_buffer_pool(pool);
1511 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1512 "Failed to allocate frame buffer");
1513 }
1514 unlock_buffer_pool(pool);
1515#else
1516 /* porting */
1517 ybf = get_frame_new_buffer(cm);
1518 if (!ybf)
1519 return -1;
1520
1521 ybf->y_crop_width = width;
1522 ybf->y_crop_height = height;
1523 ybf->bit_depth = params->p.bit_depth;
1524#endif
1525 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1526 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1527 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1528 (unsigned int)cm->bit_depth;
1529 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1530 return ret;
1531}
1532
1533static inline bool close_to(int a, int b, int m)
1534{
1535 return (abs(a - b) < m) ? true : false;
1536}
1537
1538#ifdef MULTI_INSTANCE_SUPPORT
1539static int vp9_print_cont(struct VP9Decoder_s *pbi,
1540 int flag, const char *fmt, ...)
1541{
1542 unsigned char buf[HEVC_PRINT_BUF];
1543 int len = 0;
1544
1545 if (pbi == NULL ||
1546 (flag == 0) ||
1547 (debug & flag)) {
1548 va_list args;
1549
1550 va_start(args, fmt);
1551 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1552 pr_debug("%s", buf);
1553 va_end(args);
1554 }
1555 return 0;
1556}
1557
1558static void trigger_schedule(struct VP9Decoder_s *pbi)
1559{
1560 if (pbi->is_used_v4l) {
1561 struct aml_vcodec_ctx *ctx =
1562 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1563
1564 if (ctx->param_sets_from_ucode &&
1565 !pbi->v4l_params_parsed)
1566 vdec_v4l_write_frame_sync(ctx);
1567 }
1568
1569 if (pbi->vdec_cb)
1570 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1571}
1572
1573static void reset_process_time(struct VP9Decoder_s *pbi)
1574{
1575 if (pbi->start_process_time) {
1576 unsigned process_time =
1577 1000 * (jiffies - pbi->start_process_time) / HZ;
1578 pbi->start_process_time = 0;
1579 if (process_time > max_process_time[pbi->index])
1580 max_process_time[pbi->index] = process_time;
1581 }
1582}
1583
1584static void start_process_time(struct VP9Decoder_s *pbi)
1585{
1586 pbi->start_process_time = jiffies;
1587 pbi->decode_timeout_count = 0;
1588 pbi->last_lcu_idx = 0;
1589}
1590
1591static void timeout_process(struct VP9Decoder_s *pbi)
1592{
1593 pbi->timeout_num++;
1594 amhevc_stop();
1595 vp9_print(pbi,
1596 0, "%s decoder timeout\n", __func__);
1597
1598 pbi->dec_result = DEC_RESULT_DONE;
1599 reset_process_time(pbi);
1600 vdec_schedule_work(&pbi->work);
1601}
1602
1603static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1604{
1605 return ((double_write_mode & 0x80000000) == 0) ?
1606 pbi->double_write_mode :
1607 (double_write_mode & 0x7fffffff);
1608}
1609
1610static int get_double_write_mode(struct VP9Decoder_s *pbi)
1611{
1612 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1613 u32 dw;
1614 int w, h;
1615 struct VP9_Common_s *cm = &pbi->common;
1616 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1617
1618 /* mask for supporting double write value bigger than 0x100 */
1619 if (valid_dw_mode & 0xffffff00) {
1620 if (!cm->cur_frame)
1621 return 1;/*no valid frame,*/
1622 cur_pic_config = &cm->cur_frame->buf;
1623 w = cur_pic_config->y_crop_width;
1624 h = cur_pic_config->y_crop_height;
1625
1626 dw = 0x1; /*1:1*/
1627 switch (valid_dw_mode) {
1628 case 0x100:
1629 if (w > 1920 && h > 1088)
1630 dw = 0x4; /*1:2*/
1631 break;
1632 case 0x200:
1633 if (w > 1920 && h > 1088)
1634 dw = 0x2; /*1:4*/
1635 break;
1636 case 0x300:
1637 if (w > 1280 && h > 720)
1638 dw = 0x4; /*1:2*/
1639 break;
1640 default:
1641 break;
1642 }
1643 return dw;
1644 }
1645
1646 return valid_dw_mode;
1647}
1648
1649/* for double write buf alloc */
1650static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1651{
1652 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1653 u32 dw;
1654 int w = pbi->init_pic_w;
1655 int h = pbi->init_pic_h;
1656
1657 dw = 0x1; /*1:1*/
1658 switch (valid_dw_mode) {
1659 case 0x100:
1660 if (w > 1920 && h > 1088)
1661 dw = 0x4; /*1:2*/
1662 break;
1663 case 0x200:
1664 if (w > 1920 && h > 1088)
1665 dw = 0x2; /*1:4*/
1666 break;
1667 case 0x300:
1668 if (w > 1280 && h > 720)
1669 dw = 0x4; /*1:2*/
1670 break;
1671 default:
1672 dw = valid_dw_mode;
1673 break;
1674 }
1675 return dw;
1676}
1677#endif
1678
1679static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1680 int dw_mode)
1681{
1682 int ratio = 1;
1683 if ((dw_mode == 2) ||
1684 (dw_mode == 3))
1685 ratio = 4;
1686 else if (dw_mode == 4)
1687 ratio = 2;
1688 return ratio;
1689}
1690
1691//#define MAX_4K_NUM 0x1200
1692
1693int vp9_alloc_mmu(
1694 struct VP9Decoder_s *pbi,
1695 int cur_buf_idx,
1696 int pic_width,
1697 int pic_height,
1698 unsigned short bit_depth,
1699 unsigned int *mmu_index_adr)
1700{
1701 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1702 int picture_size;
1703 int cur_mmu_4k_number, max_frame_num;
1704 if (!pbi->mmu_box) {
1705 pr_err("error no mmu box!\n");
1706 return -1;
1707 }
1708 if (pbi->double_write_mode & 0x10)
1709 return 0;
1710 if (bit_depth >= VPX_BITS_12) {
1711 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1712 pr_err("fatal_error, un support bit depth 12!\n\n");
1713 return -1;
1714 }
1715 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1716 bit_depth_10);
1717 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1718
1719 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1720 max_frame_num = MAX_FRAME_8K_NUM;
1721 else
1722 max_frame_num = MAX_FRAME_4K_NUM;
1723
1724 if (cur_mmu_4k_number > max_frame_num) {
1725 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1726 cur_mmu_4k_number, pic_width, pic_height);
1727 return -1;
1728 }
1729 return decoder_mmu_box_alloc_idx(
1730 pbi->mmu_box,
1731 cur_buf_idx,
1732 cur_mmu_4k_number,
1733 mmu_index_adr);
1734}
1735
1736
1737#ifndef MV_USE_FIXED_BUF
1738static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1739{
1740 int i;
1741 for (i = 0; i < MV_BUFFER_NUM; i++) {
1742 if (pbi->m_mv_BUF[i].start_adr) {
1743 if (debug)
1744 pr_info(
1745 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1746 i, pbi->m_mv_BUF[i].start_adr,
1747 pbi->m_mv_BUF[i].size,
1748 pbi->m_mv_BUF[i].used_flag);
1749 decoder_bmmu_box_free_idx(
1750 pbi->bmmu_box,
1751 MV_BUFFER_IDX(i));
1752 pbi->m_mv_BUF[i].start_adr = 0;
1753 pbi->m_mv_BUF[i].size = 0;
1754 pbi->m_mv_BUF[i].used_flag = 0;
1755 }
1756 }
1757}
1758
1759static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1760 int i, int size)
1761{
1762 int ret = 0;
1763 if (decoder_bmmu_box_alloc_buf_phy
1764 (pbi->bmmu_box,
1765 MV_BUFFER_IDX(i), size,
1766 DRIVER_NAME,
1767 &pbi->m_mv_BUF[i].start_adr) < 0) {
1768 pbi->m_mv_BUF[i].start_adr = 0;
1769 ret = -1;
1770 } else {
1771 pbi->m_mv_BUF[i].size = size;
1772 pbi->m_mv_BUF[i].used_flag = 0;
1773 ret = 0;
1774 if (debug) {
1775 pr_info(
1776 "MV Buffer %d: start_adr %p size %x\n",
1777 i,
1778 (void *)pbi->m_mv_BUF[i].start_adr,
1779 pbi->m_mv_BUF[i].size);
1780 }
1781 }
1782 return ret;
1783}
1784
1785static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1786{
1787 int i;
1788 int ret = 0;
1789 int count = MV_BUFFER_NUM;
1790 int pic_width = pbi->init_pic_w;
1791 int pic_height = pbi->init_pic_h;
1792 int lcu_size = 64; /*fixed 64*/
1793 int pic_width_64 = (pic_width + 63) & (~0x3f);
1794 int pic_height_32 = (pic_height + 31) & (~0x1f);
1795 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1796 pic_width_64 / lcu_size + 1
1797 : pic_width_64 / lcu_size;
1798 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1799 pic_height_32 / lcu_size + 1
1800 : pic_height_32 / lcu_size;
1801 int lcu_total = pic_width_lcu * pic_height_lcu;
1802 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1803 (~0xffff);
1804 if (mv_buf_margin > 0)
1805 count = REF_FRAMES + mv_buf_margin;
1806
1807 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1808 count = REF_FRAMES_4K + mv_buf_margin;
1809
1810 if (debug) {
1811 pr_info("%s w:%d, h:%d, count: %d\n",
1812 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1813 }
1814
1815 for (i = 0;
1816 i < count && i < MV_BUFFER_NUM; i++) {
1817 if (alloc_mv_buf(pbi, i, size) < 0) {
1818 ret = -1;
1819 break;
1820 }
1821 }
1822 return ret;
1823}
1824
1825static int get_mv_buf(struct VP9Decoder_s *pbi,
1826 int *mv_buf_index,
1827 unsigned long *mpred_mv_wr_start_addr)
1828{
1829 int i;
1830 int ret = -1;
1831 for (i = 0; i < MV_BUFFER_NUM; i++) {
1832 if (pbi->m_mv_BUF[i].start_adr &&
1833 pbi->m_mv_BUF[i].used_flag == 0) {
1834 pbi->m_mv_BUF[i].used_flag = 1;
1835 ret = i;
1836 break;
1837 }
1838 }
1839
1840 if (ret >= 0) {
1841 *mv_buf_index = ret;
1842 *mpred_mv_wr_start_addr =
1843 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1844 (~0xffff);
1845 if (debug & VP9_DEBUG_BUFMGR_MORE)
1846 pr_info(
1847 "%s => %d (%ld) size 0x%x\n",
1848 __func__, ret,
1849 *mpred_mv_wr_start_addr,
1850 pbi->m_mv_BUF[ret].size);
1851 } else {
1852 pr_info(
1853 "%s: Error, mv buf is not enough\n",
1854 __func__);
1855 }
1856 return ret;
1857}
1858
1859static void put_mv_buf(struct VP9Decoder_s *pbi,
1860 int *mv_buf_index)
1861{
1862 int i = *mv_buf_index;
1863 if (i >= MV_BUFFER_NUM) {
1864 if (debug & VP9_DEBUG_BUFMGR_MORE)
1865 pr_info(
1866 "%s: index %d beyond range\n",
1867 __func__, i);
1868 return;
1869 }
1870 if (debug & VP9_DEBUG_BUFMGR_MORE)
1871 pr_info(
1872 "%s(%d): used_flag(%d)\n",
1873 __func__, i,
1874 pbi->m_mv_BUF[i].used_flag);
1875
1876 *mv_buf_index = -1;
1877 if (pbi->m_mv_BUF[i].start_adr &&
1878 pbi->m_mv_BUF[i].used_flag)
1879 pbi->m_mv_BUF[i].used_flag = 0;
1880}
1881
1882static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1883{
1884 struct VP9_Common_s *const cm = &pbi->common;
1885 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1886 int i;
1887 for (i = 0; i < pbi->used_buf_num; ++i) {
1888 if ((frame_bufs[i].ref_count == 0) &&
1889 (frame_bufs[i].buf.index != -1) &&
1890 (frame_bufs[i].buf.mv_buf_index >= 0)
1891 )
1892 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1893 }
1894}
1895
1896#ifdef SUPPORT_FB_DECODING
1897static bool mv_buf_available(struct VP9Decoder_s *pbi)
1898{
1899 int i;
1900 bool ret = 0;
1901 for (i = 0; i < MV_BUFFER_NUM; i++) {
1902 if (pbi->m_mv_BUF[i].start_adr &&
1903 pbi->m_mv_BUF[i].used_flag == 0) {
1904 ret = 1;
1905 break;
1906 }
1907 }
1908 return ret;
1909}
1910#endif
1911#endif
1912
1913#ifdef SUPPORT_FB_DECODING
1914static void init_stage_buf(struct VP9Decoder_s *pbi)
1915{
1916 uint i;
1917 for (i = 0; i < STAGE_MAX_BUFFERS
1918 && i < stage_buf_num; i++) {
1919 pbi->stage_bufs[i] =
1920 vmalloc(sizeof(struct stage_buf_s));
1921 if (pbi->stage_bufs[i] == NULL) {
1922 vp9_print(pbi,
1923 0, "%s vmalloc fail\n", __func__);
1924 break;
1925 }
1926 pbi->stage_bufs[i]->index = i;
1927 }
1928 pbi->used_stage_buf_num = i;
1929 pbi->s1_pos = 0;
1930 pbi->s2_pos = 0;
1931 pbi->s1_buf = NULL;
1932 pbi->s2_buf = NULL;
1933 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1934 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1935 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1936
1937 if (pbi->used_stage_buf_num > 0)
1938 vp9_print(pbi,
1939 0, "%s 2 stage decoding buf %d\n",
1940 __func__,
1941 pbi->used_stage_buf_num);
1942}
1943
1944static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1945{
1946 int i;
1947 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1948 if (pbi->stage_bufs[i])
1949 vfree(pbi->stage_bufs[i]);
1950 pbi->stage_bufs[i] = NULL;
1951 }
1952 pbi->used_stage_buf_num = 0;
1953 pbi->s1_pos = 0;
1954 pbi->s2_pos = 0;
1955 pbi->s1_buf = NULL;
1956 pbi->s2_buf = NULL;
1957}
1958
1959static int get_s1_buf(
1960 struct VP9Decoder_s *pbi)
1961{
1962 struct stage_buf_s *buf = NULL;
1963 int ret = -1;
1964 int buf_page_num = MAX_STAGE_PAGE_NUM;
1965 int next_s1_pos = pbi->s1_pos + 1;
1966
1967 if (next_s1_pos >= pbi->used_stage_buf_num)
1968 next_s1_pos = 0;
1969 if (next_s1_pos == pbi->s2_pos) {
1970 pbi->s1_buf = NULL;
1971 return ret;
1972 }
1973
1974 buf = pbi->stage_bufs[pbi->s1_pos];
1975 ret = decoder_mmu_box_alloc_idx(
1976 pbi->mmu_box,
1977 buf->index,
1978 buf_page_num,
1979 pbi->stage_mmu_map_addr);
1980 if (ret < 0) {
1981 vp9_print(pbi, 0,
1982 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1983 __func__, buf->index,
1984 pbi->s1_pos, pbi->s2_pos);
1985 buf = NULL;
1986 } else {
1987 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1988 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1989 __func__, buf_page_num, buf->index,
1990 pbi->s1_pos, pbi->s2_pos);
1991 }
1992 pbi->s1_buf = buf;
1993 return ret;
1994}
1995
1996static void inc_s1_pos(struct VP9Decoder_s *pbi)
1997{
1998 struct stage_buf_s *buf =
1999 pbi->stage_bufs[pbi->s1_pos];
2000
2001 int used_page_num =
2002#ifdef FB_DECODING_TEST_SCHEDULE
2003 MAX_STAGE_PAGE_NUM/2;
2004#else
2005 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
2006#endif
2007 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2008 FRAME_BUFFERS + buf->index, used_page_num);
2009
2010 pbi->s1_pos++;
2011 if (pbi->s1_pos >= pbi->used_stage_buf_num)
2012 pbi->s1_pos = 0;
2013
2014 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2015 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2016 __func__, used_page_num, buf->index,
2017 pbi->s1_pos, pbi->s2_pos);
2018}
2019
2020#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2021
2022static int get_s2_buf(
2023 struct VP9Decoder_s *pbi)
2024{
2025 int ret = -1;
2026 struct stage_buf_s *buf = NULL;
2027 if (s2_buf_available(pbi)) {
2028 buf = pbi->stage_bufs[pbi->s2_pos];
2029 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2030 "%s for index %d (s1_pos %d s2_pos %d)\n",
2031 __func__, buf->index,
2032 pbi->s1_pos, pbi->s2_pos);
2033 pbi->s2_buf = buf;
2034 ret = 0;
2035 }
2036 return ret;
2037}
2038
2039static void inc_s2_pos(struct VP9Decoder_s *pbi)
2040{
2041 struct stage_buf_s *buf =
2042 pbi->stage_bufs[pbi->s2_pos];
2043 decoder_mmu_box_free_idx(pbi->mmu_box,
2044 FRAME_BUFFERS + buf->index);
2045 pbi->s2_pos++;
2046 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2047 pbi->s2_pos = 0;
2048 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2049 "%s for index %d (s1_pos %d s2_pos %d)\n",
2050 __func__, buf->index,
2051 pbi->s1_pos, pbi->s2_pos);
2052}
2053
2054static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2055{
2056 int num;
2057 if (pbi->s1_pos >= pbi->s2_pos)
2058 num = pbi->used_stage_buf_num -
2059 (pbi->s1_pos - pbi->s2_pos) - 1;
2060 else
2061 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2062 return num;
2063}
2064
2065#ifndef FB_DECODING_TEST_SCHEDULE
2066static DEFINE_SPINLOCK(fb_core_spin_lock);
2067
2068static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2069{
2070 /* to do: VLSI review
2071 completion of last LCU decoding in BACK
2072 */
2073 return 1;
2074}
2075
2076static void start_s1_decoding(struct VP9Decoder_s *pbi)
2077{
2078 /* to do: VLSI review
2079 after parser, how to start LCU decoding in BACK
2080 */
2081}
2082
2083static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2084{
2085 /* to do: VLSI review
2086 1. how to disconnect DMC for FRONT and BACK
2087 2. reset bit 13, 24, FRONT or BACK ??
2088 */
2089
2090 unsigned long flags;
2091 u32 reset_bits = 0;
2092 if (mask & HW_MASK_FRONT)
2093 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2094 spin_lock_irqsave(&fb_core_spin_lock, flags);
2095 codec_dmcbus_write(DMC_REQ_CTRL,
2096 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2097 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2098
2099 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2100 & (1 << 4)))
2101 ;
2102
2103 if ((mask & HW_MASK_FRONT) &&
2104 input_frame_based(vdec))
2105 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2106
2107 /*
2108 * 2: assist
2109 * 3: parser
2110 * 4: parser_state
2111 * 8: dblk
2112 * 11:mcpu
2113 * 12:ccpu
2114 * 13:ddr
2115 * 14:iqit
2116 * 15:ipp
2117 * 17:qdct
2118 * 18:mpred
2119 * 19:sao
2120 * 24:hevc_afifo
2121 */
2122 if (mask & HW_MASK_FRONT) {
2123 reset_bits =
2124 (1<<3)|(1<<4)|(1<<11)|
2125 (1<<12)|(1<<18);
2126 }
2127 if (mask & HW_MASK_BACK) {
2128 reset_bits =
2129 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2130 (1<<17)|(1<<19)|(1<<24);
2131 }
2132 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2133#if 0
2134 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2135 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2136 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2137#endif
2138 WRITE_VREG(DOS_SW_RESET3, 0);
2139
2140
2141 spin_lock_irqsave(&fb_core_spin_lock, flags);
2142 codec_dmcbus_write(DMC_REQ_CTRL,
2143 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2144 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2145
2146}
2147#endif
2148
2149#endif
2150
2151static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2152
2153static int get_free_fb(struct VP9Decoder_s *pbi)
2154{
2155 struct VP9_Common_s *const cm = &pbi->common;
2156 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2157 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2158 int i;
2159 unsigned long flags;
2160
2161 lock_buffer_pool(cm->buffer_pool, flags);
2162 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2163 for (i = 0; i < pbi->used_buf_num; ++i) {
2164 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2165 __func__, i, frame_bufs[i].ref_count,
2166 frame_bufs[i].buf.vf_ref,
2167 frame_bufs[i].buf.index);
2168 }
2169 }
2170 for (i = 0; i < pbi->used_buf_num; ++i) {
2171 pic = &frame_bufs[i].buf;
2172 if ((frame_bufs[i].ref_count == 0) &&
2173 (pic->vf_ref == 0) && (pic->index != -1)) {
2174 if (pbi->is_used_v4l && !pic->cma_alloc_addr) {
2175 pic->y_crop_width = pbi->frame_width;
2176 pic->y_crop_height = pbi->frame_height;
2177 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2178 set_canvas(pbi, pic);
2179 init_pic_list_hw(pbi);
2180 } else
2181 i = pbi->used_buf_num;
2182 }
2183
2184 break;
2185 }
2186 }
2187 if (i != pbi->used_buf_num) {
2188 frame_bufs[i].ref_count = 1;
2189 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2190 i, frame_bufs[i].ref_count);*/
2191 } else {
2192 /* Reset i to be INVALID_IDX to indicate
2193 no free buffer found*/
2194 i = INVALID_IDX;
2195 }
2196
2197 unlock_buffer_pool(cm->buffer_pool, flags);
2198 return i;
2199}
2200
2201static int get_free_buf_count(struct VP9Decoder_s *pbi)
2202{
2203 struct VP9_Common_s *const cm = &pbi->common;
2204 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2205 int i;
2206 int free_buf_count = 0;
2207 for (i = 0; i < pbi->used_buf_num; ++i)
2208 if ((frame_bufs[i].ref_count == 0) &&
2209 (frame_bufs[i].buf.vf_ref == 0) &&
2210 (frame_bufs[i].buf.index != -1)
2211 )
2212 free_buf_count++;
2213 return free_buf_count;
2214}
2215
2216static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2217 struct BufferPool_s *const pool)
2218{
2219 if (idx >= 0) {
2220 --frame_bufs[idx].ref_count;
2221 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2222 * frame_bufs[idx].ref_count);
2223 */
2224 /*A worker may only get a free framebuffer index when
2225 *calling get_free_fb. But the private buffer is not set up
2226 *until finish decoding header. So any error happens during
2227 *decoding header, the frame_bufs will not have valid priv
2228 *buffer.
2229 */
2230
2231 if (frame_bufs[idx].ref_count == 0 &&
2232 frame_bufs[idx].raw_frame_buffer.priv)
2233 vp9_release_frame_buffer
2234 (&frame_bufs[idx].raw_frame_buffer);
2235 }
2236}
2237
2238static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2239{
2240 struct VP9_Common_s *const cm = &pbi->common;
2241 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2242 struct BufferPool_s *const pool = cm->buffer_pool;
2243 int mask, ref_index = 0;
2244 unsigned long flags;
2245
2246 /* Generate next_ref_frame_map.*/
2247 lock_buffer_pool(pool, flags);
2248 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2249 if (mask & 1) {
2250 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2251 ++frame_bufs[cm->new_fb_idx].ref_count;
2252 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2253 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2254 */
2255 } else
2256 cm->next_ref_frame_map[ref_index] =
2257 cm->ref_frame_map[ref_index];
2258 /* Current thread holds the reference frame.*/
2259 if (cm->ref_frame_map[ref_index] >= 0) {
2260 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2261 /*pr_info
2262 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2263 *cm->ref_frame_map[ref_index],
2264 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2265 */
2266 }
2267 ++ref_index;
2268 }
2269
2270 for (; ref_index < REF_FRAMES; ++ref_index) {
2271 cm->next_ref_frame_map[ref_index] =
2272 cm->ref_frame_map[ref_index];
2273 /* Current thread holds the reference frame.*/
2274 if (cm->ref_frame_map[ref_index] >= 0) {
2275 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2276 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2277 *cm->ref_frame_map[ref_index],
2278 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2279 */
2280 }
2281 }
2282 unlock_buffer_pool(pool, flags);
2283 return;
2284}
2285
2286static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2287
2288{
2289 struct VP9_Common_s *const cm = &pbi->common;
2290 struct BufferPool_s *pool = cm->buffer_pool;
2291 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2292 int mask, ref_index = 0;
2293 unsigned long flags;
2294
2295 lock_buffer_pool(pool, flags);
2296 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2297 const int old_idx = cm->ref_frame_map[ref_index];
2298 /*Current thread releases the holding of reference frame.*/
2299 decrease_ref_count(old_idx, frame_bufs, pool);
2300
2301 /*Release the reference frame in reference map.*/
2302 if ((mask & 1) && old_idx >= 0)
2303 decrease_ref_count(old_idx, frame_bufs, pool);
2304 cm->ref_frame_map[ref_index] =
2305 cm->next_ref_frame_map[ref_index];
2306 ++ref_index;
2307 }
2308
2309 /*Current thread releases the holding of reference frame.*/
2310 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2311 ++ref_index) {
2312 const int old_idx = cm->ref_frame_map[ref_index];
2313
2314 decrease_ref_count(old_idx, frame_bufs, pool);
2315 cm->ref_frame_map[ref_index] =
2316 cm->next_ref_frame_map[ref_index];
2317 }
2318 unlock_buffer_pool(pool, flags);
2319 return;
2320}
2321
2322int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2323{
2324 struct VP9_Common_s *const cm = &pbi->common;
2325 struct BufferPool_s *pool = cm->buffer_pool;
2326 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2327 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2328 int i;
2329 int ret;
2330
2331 pbi->ready_for_new_data = 0;
2332
2333 if (pbi->has_keyframe == 0 &&
2334 params->p.frame_type != KEY_FRAME){
2335 on_no_keyframe_skiped++;
2336 return -2;
2337 }
2338 pbi->has_keyframe = 1;
2339 on_no_keyframe_skiped = 0;
2340#if 0
2341 if (pbi->mmu_enable) {
2342 if (!pbi->m_ins_flag)
2343 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2344 if (cm->prev_fb_idx >= 0) {
2345 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2346 cm->prev_fb_idx, pbi->used_4k_num);
2347 }
2348 }
2349#endif
2350 if (cm->new_fb_idx >= 0
2351 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2352 vp9_release_frame_buffer
2353 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2354 }
2355 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2356 cm->prev_fb_idx, cm->new_fb_idx);*/
2357#ifndef MV_USE_FIXED_BUF
2358 put_un_used_mv_bufs(pbi);
2359 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2360 dump_pic_list(pbi);
2361#endif
2362 cm->new_fb_idx = get_free_fb(pbi);
2363 if (cm->new_fb_idx == INVALID_IDX) {
2364 pr_info("get_free_fb error\r\n");
2365 return -1;
2366 }
2367#ifndef MV_USE_FIXED_BUF
2368#ifdef SUPPORT_FB_DECODING
2369 if (pbi->used_stage_buf_num == 0) {
2370#endif
2371 if (get_mv_buf(pbi,
2372 &pool->frame_bufs[cm->new_fb_idx].
2373 buf.mv_buf_index,
2374 &pool->frame_bufs[cm->new_fb_idx].
2375 buf.mpred_mv_wr_start_addr
2376 ) < 0) {
2377 pr_info("get_mv_buf fail\r\n");
2378 return -1;
2379 }
2380 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2381 dump_pic_list(pbi);
2382#ifdef SUPPORT_FB_DECODING
2383 }
2384#endif
2385#endif
2386 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2387 /*if (debug & VP9_DEBUG_BUFMGR)
2388 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2389 cm->new_fb_idx);*/
2390
2391 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2392 if (pbi->mmu_enable) {
2393 /* moved to after picture size ready
2394 *alloc_mmu(cm, params->p.width, params->p.height,
2395 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2396 */
2397 cm->prev_fb_idx = cm->new_fb_idx;
2398 }
2399 /*read_uncompressed_header()*/
2400 cm->last_frame_type = cm->frame_type;
2401 cm->last_intra_only = cm->intra_only;
2402 cm->profile = params->p.profile;
2403 if (cm->profile >= MAX_PROFILES) {
2404 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2405 return -1;
2406 }
2407 cm->show_existing_frame = params->p.show_existing_frame;
2408 if (cm->show_existing_frame) {
2409 /* Show an existing frame directly.*/
2410 int frame_to_show_idx = params->p.frame_to_show_idx;
2411 int frame_to_show;
2412 unsigned long flags;
2413 if (frame_to_show_idx >= REF_FRAMES) {
2414 pr_info("frame_to_show_idx %d exceed max index\r\n",
2415 frame_to_show_idx);
2416 return -1;
2417 }
2418
2419 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2420 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2421 lock_buffer_pool(pool, flags);
2422 if (frame_to_show < 0 ||
2423 frame_bufs[frame_to_show].ref_count < 1) {
2424 unlock_buffer_pool(pool, flags);
2425 pr_err
2426 ("Error:Buffer %d does not contain a decoded frame",
2427 frame_to_show);
2428 return -1;
2429 }
2430
2431 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2432 unlock_buffer_pool(pool, flags);
2433 pbi->refresh_frame_flags = 0;
2434 /*cm->lf.filter_level = 0;*/
2435 cm->show_frame = 1;
2436
2437 /*
2438 *if (pbi->frame_parallel_decode) {
2439 * for (i = 0; i < REF_FRAMES; ++i)
2440 * cm->next_ref_frame_map[i] =
2441 * cm->ref_frame_map[i];
2442 *}
2443 */
2444 /* do not decode, search next start code */
2445 return 1;
2446 }
2447 cm->frame_type = params->p.frame_type;
2448 cm->show_frame = params->p.show_frame;
2449 cm->error_resilient_mode = params->p.error_resilient_mode;
2450
2451
2452 if (cm->frame_type == KEY_FRAME) {
2453 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2454
2455 for (i = 0; i < REFS_PER_FRAME; ++i) {
2456 cm->frame_refs[i].idx = INVALID_IDX;
2457 cm->frame_refs[i].buf = NULL;
2458 }
2459
2460 ret = setup_frame_size(pbi,
2461 cm, params, pbi->frame_mmu_map_addr,
2462 print_header_info);
2463 if (ret)
2464 return -1;
2465 if (pbi->need_resync) {
2466 memset(&cm->ref_frame_map, -1,
2467 sizeof(cm->ref_frame_map));
2468 pbi->need_resync = 0;
2469 }
2470 } else {
2471 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2472 /*if (print_header_info) {
2473 * if (cm->show_frame)
2474 * pr_info
2475 * ("intra_only set to 0 because of show_frame\n");
2476 * else
2477 * pr_info
2478 * ("1-bit intra_only read: %d\n", cm->intra_only);
2479 *}
2480 */
2481
2482
2483 cm->reset_frame_context = cm->error_resilient_mode ?
2484 0 : params->p.reset_frame_context;
2485 if (print_header_info) {
2486 if (cm->error_resilient_mode)
2487 pr_info
2488 ("reset to 0 error_resilient_mode\n");
2489 else
2490 pr_info
2491 (" * 2-bits reset_frame_context read : %d\n",
2492 cm->reset_frame_context);
2493 }
2494
2495 if (cm->intra_only) {
2496 if (cm->profile > PROFILE_0) {
2497 /*read_bitdepth_colorspace_sampling(cm,
2498 * rb, print_header_info);
2499 */
2500 } else {
2501 /*NOTE: The intra-only frame header
2502 *does not include the specification
2503 *of either the color format or
2504 *color sub-sampling
2505 *in profile 0. VP9 specifies that the default
2506 *color format should be YUV 4:2:0 in this
2507 *case (normative).
2508 */
2509 cm->color_space = VPX_CS_BT_601;
2510 cm->subsampling_y = cm->subsampling_x = 1;
2511 cm->bit_depth = VPX_BITS_8;
2512 cm->use_highbitdepth = 0;
2513 }
2514
2515 pbi->refresh_frame_flags =
2516 params->p.refresh_frame_flags;
2517 /*if (print_header_info)
2518 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2519 * REF_FRAMES, pbi->refresh_frame_flags);
2520 */
2521 ret = setup_frame_size(pbi,
2522 cm,
2523 params,
2524 pbi->frame_mmu_map_addr,
2525 print_header_info);
2526 if (ret)
2527 return -1;
2528 if (pbi->need_resync) {
2529 memset(&cm->ref_frame_map, -1,
2530 sizeof(cm->ref_frame_map));
2531 pbi->need_resync = 0;
2532 }
2533 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2534 pbi->refresh_frame_flags =
2535 params->p.refresh_frame_flags;
2536 if (print_header_info)
2537 pr_info
2538 ("*%d-bits refresh_frame read:0x%x\n",
2539 REF_FRAMES, pbi->refresh_frame_flags);
2540 for (i = 0; i < REFS_PER_FRAME; ++i) {
2541 const int ref =
2542 (params->p.ref_info >>
2543 (((REFS_PER_FRAME-i-1)*4)+1))
2544 & 0x7;
2545 const int idx =
2546 cm->ref_frame_map[ref];
2547 struct RefBuffer_s * const ref_frame =
2548 &cm->frame_refs[i];
2549 if (print_header_info)
2550 pr_info("*%d-bits ref[%d]read:%d\n",
2551 REF_FRAMES_LOG2, i, ref);
2552 ref_frame->idx = idx;
2553 ref_frame->buf = &frame_bufs[idx].buf;
2554 cm->ref_frame_sign_bias[LAST_FRAME + i]
2555 = (params->p.ref_info >>
2556 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2557 if (print_header_info)
2558 pr_info("1bit ref_frame_sign_bias");
2559 /*pr_info
2560 *("%dread: %d\n",
2561 *LAST_FRAME+i,
2562 *cm->ref_frame_sign_bias
2563 *[LAST_FRAME + i]);
2564 */
2565 /*pr_info
2566 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2567 *__func__, ref_frame->idx);
2568 */
2569
2570 }
2571
2572 ret = setup_frame_size_with_refs(
2573 pbi,
2574 cm,
2575 params,
2576 pbi->frame_mmu_map_addr,
2577 print_header_info);
2578 if (ret)
2579 return -1;
2580 for (i = 0; i < REFS_PER_FRAME; ++i) {
2581 /*struct RefBuffer_s *const ref_buf =
2582 *&cm->frame_refs[i];
2583 */
2584 /* to do:
2585 *vp9_setup_scale_factors_for_frame
2586 */
2587 }
2588 }
2589 }
2590
2591 pic = get_frame_new_buffer(cm);
2592 if (!pic)
2593 return -1;
2594
2595 pic->bit_depth = cm->bit_depth;
2596 pic->color_space = cm->color_space;
2597 pic->slice_type = cm->frame_type;
2598
2599 if (pbi->need_resync) {
2600 pr_err
2601 ("Error: Keyframe/intra-only frame required to reset\r\n");
2602 return -1;
2603 }
2604 generate_next_ref_frames(pbi);
2605 pbi->hold_ref_buf = 1;
2606
2607#if 0
2608 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2609 vp9_setup_past_independence(cm);
2610 setup_loopfilter(&cm->lf, rb, print_header_info);
2611 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2612 setup_segmentation(&cm->seg, rb, print_header_info);
2613 setup_segmentation_dequant(cm, print_header_info);
2614
2615 setup_tile_info(cm, rb, print_header_info);
2616 sz = vp9_rb_read_literal(rb, 16);
2617 if (print_header_info)
2618 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2619
2620 if (sz == 0)
2621 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2622 "Invalid header size");
2623#endif
2624 /*end read_uncompressed_header()*/
2625 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2626 cm->width == cm->last_width &&
2627 cm->height == cm->last_height &&
2628 !cm->last_intra_only &&
2629 cm->last_show_frame &&
2630 (cm->last_frame_type != KEY_FRAME);
2631
2632 /*pr_info
2633 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2634 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2635 *pr_info
2636 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2637 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2638 */
2639 return 0;
2640}
2641
2642
2643void swap_frame_buffers(struct VP9Decoder_s *pbi)
2644{
2645 int ref_index = 0;
2646 struct VP9_Common_s *const cm = &pbi->common;
2647 struct BufferPool_s *const pool = cm->buffer_pool;
2648 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2649 unsigned long flags;
2650 refresh_ref_frames(pbi);
2651 pbi->hold_ref_buf = 0;
2652 cm->frame_to_show = get_frame_new_buffer(cm);
2653
2654 if (cm->frame_to_show) {
2655 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2656 lock_buffer_pool(pool, flags);
2657 --frame_bufs[cm->new_fb_idx].ref_count;
2658 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2659 * frame_bufs[cm->new_fb_idx].ref_count);
2660 */
2661 unlock_buffer_pool(pool, flags);
2662 /*}*/
2663 }
2664
2665 /*Invalidate these references until the next frame starts.*/
2666 for (ref_index = 0; ref_index < 3; ref_index++)
2667 cm->frame_refs[ref_index].idx = -1;
2668}
2669
2670#if 0
2671static void check_resync(vpx_codec_alg_priv_t *const ctx,
2672 const struct VP9Decoder_s *const pbi)
2673{
2674 /* Clear resync flag if worker got a key frame or intra only frame.*/
2675 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2676 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2677 ctx->need_resync = 0;
2678}
2679#endif
2680
2681int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2682{
2683 struct VP9_Common_s *const cm = &pbi->common;
2684 int ret = -1;
2685
2686 if (pbi->ready_for_new_data == 1)
2687 return ret;
2688
2689 pbi->ready_for_new_data = 1;
2690
2691 /* no raw frame to show!!! */
2692 if (!cm->show_frame)
2693 return ret;
2694
2695 /* may not be get buff in v4l2 */
2696 if (!cm->frame_to_show)
2697 return ret;
2698
2699 pbi->ready_for_new_data = 1;
2700
2701 *sd = *cm->frame_to_show;
2702 ret = 0;
2703
2704 return ret;
2705}
2706
2707int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2708 struct buff_s *mc_buf_i) {
2709 struct VP9_Common_s *cm = &pbi->common;
2710
2711 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2712 pbi->frame_count = 0;
2713 pbi->pic_count = 0;
2714 pbi->pre_stream_offset = 0;
2715 cm->buffer_pool = &pbi->vp9_buffer_pool;
2716 spin_lock_init(&cm->buffer_pool->lock);
2717 cm->prev_fb_idx = INVALID_IDX;
2718 cm->new_fb_idx = INVALID_IDX;
2719 pbi->used_4k_num = -1;
2720 cm->cur_fb_idx_mmu = INVALID_IDX;
2721 pr_debug
2722 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2723 cm->prev_fb_idx, cm->new_fb_idx);
2724 pbi->need_resync = 1;
2725 /* Initialize the references to not point to any frame buffers.*/
2726 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2727 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2728 cm->current_video_frame = 0;
2729 pbi->ready_for_new_data = 1;
2730
2731 /* private init */
2732 pbi->work_space_buf = buf_spec_i;
2733 if (!pbi->mmu_enable)
2734 pbi->mc_buf = mc_buf_i;
2735
2736 pbi->rpm_addr = NULL;
2737 pbi->lmem_addr = NULL;
2738
2739 pbi->use_cma_flag = 0;
2740 pbi->decode_idx = 0;
2741 pbi->slice_idx = 0;
2742 /*int m_uiMaxCUWidth = 1<<7;*/
2743 /*int m_uiMaxCUHeight = 1<<7;*/
2744 pbi->has_keyframe = 0;
2745 pbi->skip_flag = 0;
2746 pbi->wait_buf = 0;
2747 pbi->error_flag = 0;
2748
2749 pbi->pts_mode = PTS_NORMAL;
2750 pbi->last_pts = 0;
2751 pbi->last_lookup_pts = 0;
2752 pbi->last_pts_us64 = 0;
2753 pbi->last_lookup_pts_us64 = 0;
2754 pbi->shift_byte_count = 0;
2755 pbi->shift_byte_count_lo = 0;
2756 pbi->shift_byte_count_hi = 0;
2757 pbi->pts_mode_switching_count = 0;
2758 pbi->pts_mode_recovery_count = 0;
2759
2760 pbi->buf_num = 0;
2761 pbi->pic_num = 0;
2762
2763 return 0;
2764}
2765
2766int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2767{
2768 struct VP9_Common_s *cm = &pbi->common;
2769 struct PIC_BUFFER_CONFIG_s sd;
2770
2771 if (pbi->postproc_done)
2772 return 0;
2773 pbi->postproc_done = 1;
2774 swap_frame_buffers(pbi);
2775 if (!cm->show_existing_frame) {
2776 cm->last_show_frame = cm->show_frame;
2777 cm->prev_frame = cm->cur_frame;
2778#if 0
2779 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2780 vp9_swap_current_and_last_seg_map(cm);
2781#endif
2782 }
2783 cm->last_width = cm->width;
2784 cm->last_height = cm->height;
2785 if (cm->show_frame)
2786 cm->current_video_frame++;
2787
2788 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2789 /*pr_info("Display frame index %d\r\n", sd.index);*/
2790 sd.stream_offset = pbi->pre_stream_offset;
2791 prepare_display_buf(pbi, &sd);
2792 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2793 }
2794
2795/* else
2796 * pr_info
2797 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2798 * pbi->ready_for_new_data, cm->show_frame);
2799 */
2800 return 0;
2801}
2802
2803/*struct VP9Decoder_s vp9_decoder;*/
2804union param_u vp9_param;
2805
2806/**************************************************
2807 *
2808 *VP9 buffer management end
2809 *
2810 ***************************************************
2811 */
2812
2813
2814#define HEVC_CM_BODY_START_ADDR 0x3626
2815#define HEVC_CM_BODY_LENGTH 0x3627
2816#define HEVC_CM_HEADER_LENGTH 0x3629
2817#define HEVC_CM_HEADER_OFFSET 0x362b
2818
2819#define LOSLESS_COMPRESS_MODE
2820
2821/*#define DECOMP_HEADR_SURGENT*/
2822#ifdef VP9_10B_NV21
2823static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2824#else
2825static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2826#endif
2827static u32 enable_mem_saving = 1;
2828static u32 force_w_h;
2829
2830static u32 force_fps;
2831
2832
2833const u32 vp9_version = 201602101;
2834static u32 debug;
2835static u32 radr;
2836static u32 rval;
2837static u32 pop_shorts;
2838static u32 dbg_cmd;
2839static u32 dbg_skip_decode_index;
2840static u32 endian = 0xff0;
2841#ifdef ERROR_HANDLE_DEBUG
2842static u32 dbg_nal_skip_flag;
2843 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2844static u32 dbg_nal_skip_count;
2845#endif
2846/*for debug*/
2847static u32 decode_pic_begin;
2848static uint slice_parse_begin;
2849static u32 step;
2850#ifdef MIX_STREAM_SUPPORT
2851static u32 buf_alloc_width = 4096;
2852static u32 buf_alloc_height = 2304;
2853static u32 vp9_max_pic_w = 4096;
2854static u32 vp9_max_pic_h = 2304;
2855
2856static u32 dynamic_buf_num_margin;
2857#else
2858static u32 buf_alloc_width;
2859static u32 buf_alloc_height;
2860static u32 dynamic_buf_num_margin = 7;
2861#endif
2862static u32 buf_alloc_depth = 10;
2863static u32 buf_alloc_size;
2864/*
2865 *bit[0]: 0,
2866 * bit[1]: 0, always release cma buffer when stop
2867 * bit[1]: 1, never release cma buffer when stop
2868 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2869 *do not release cma buffer is blackout is not 1
2870 *
2871 *bit[2]: 0, when start decoding, check current displayed buffer
2872 * (only for buffer decoded by vp9) if blackout is 0
2873 * 1, do not check current displayed buffer
2874 *
2875 *bit[3]: 1, if blackout is not 1, do not release current
2876 * displayed cma buffer always.
2877 */
2878/* set to 1 for fast play;
2879 * set to 8 for other case of "keep last frame"
2880 */
2881static u32 buffer_mode = 1;
2882/* buffer_mode_dbg: debug only*/
2883static u32 buffer_mode_dbg = 0xffff0000;
2884/**/
2885
2886/*
2887 *bit 0, 1: only display I picture;
2888 *bit 1, 1: only decode I picture;
2889 */
2890static u32 i_only_flag;
2891
2892static u32 low_latency_flag;
2893
2894static u32 no_head;
2895
2896static u32 max_decoding_time;
2897/*
2898 *error handling
2899 */
2900/*error_handle_policy:
2901 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2902 *1, skip error_skip_nal_count nals before error recovery;
2903 *bit 1 (valid only when bit0 == 1):
2904 *1, wait vps/sps/pps after error recovery;
2905 *bit 2 (valid only when bit0 == 0):
2906 *0, auto search after error recovery (vp9_recover() called);
2907 *1, manual search after error recovery
2908 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2909 *
2910 *bit 4: 0, set error_mark after reset/recover
2911 * 1, do not set error_mark after reset/recover
2912 *bit 5: 0, check total lcu for every picture
2913 * 1, do not check total lcu
2914 *
2915 */
2916
2917static u32 error_handle_policy;
2918/*static u32 parser_sei_enable = 1;*/
2919#define MAX_BUF_NUM_NORMAL 12
2920#define MAX_BUF_NUM_LESS 10
2921static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2922#define MAX_BUF_NUM_SAVE_BUF 8
2923
2924static u32 run_ready_min_buf_num = 2;
2925
2926
2927static DEFINE_MUTEX(vvp9_mutex);
2928#ifndef MULTI_INSTANCE_SUPPORT
2929static struct device *cma_dev;
2930#endif
2931
2932#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2933#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2934#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2935#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2936#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2937#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2938#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2939#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2940#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2941#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2942#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2943#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2944#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2945#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2946#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2947#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2948#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2949#ifdef MULTI_INSTANCE_SUPPORT
2950#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2951#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2952#else
2953#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2954#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2955#endif
2956#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2957#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2958
2959
2960/*
2961 *ucode parser/search control
2962 *bit 0: 0, header auto parse; 1, header manual parse
2963 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
2964 *bit [3:2]: valid when bit1==0;
2965 *0, auto skip nal before first vps/sps/pps/idr;
2966 *1, auto skip nal before first vps/sps/pps
2967 *2, auto skip nal before first vps/sps/pps,
2968 * and not decode until the first I slice (with slice address of 0)
2969 *
2970 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
2971 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
2972 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
2973 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
2974 *bit [17]: for NAL_SEI when bit0 is 0:
2975 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
2976 *bit [31:20]: used by ucode for debug purpose
2977 */
2978#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
2979 /*[31:24] chip feature
2980 31: 0, use MBOX1; 1, use MBOX0
2981 */
2982#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
2983#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
2984
2985#ifdef MULTI_INSTANCE_SUPPORT
2986#define RPM_BUF_SIZE (0x400 * 2)
2987#else
2988#define RPM_BUF_SIZE (0x80*2)
2989#endif
2990#define LMEM_BUF_SIZE (0x400 * 2)
2991
2992#define WORK_BUF_SPEC_NUM 3
2993static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
2994 {
2995 /* 8M bytes */
2996 .max_width = 1920,
2997 .max_height = 1088,
2998 .ipp = {
2999 /* IPP work space calculation :
3000 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3001 */
3002 .buf_size = 0x4000,
3003 },
3004 .sao_abv = {
3005 .buf_size = 0x30000,
3006 },
3007 .sao_vb = {
3008 .buf_size = 0x30000,
3009 },
3010 .short_term_rps = {
3011 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3012 * total 64x16x2 = 2048 bytes (0x800)
3013 */
3014 .buf_size = 0x800,
3015 },
3016 .vps = {
3017 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3018 * total 0x0800 bytes
3019 */
3020 .buf_size = 0x800,
3021 },
3022 .sps = {
3023 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3024 * total 0x0800 bytes
3025 */
3026 .buf_size = 0x800,
3027 },
3028 .pps = {
3029 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3030 * total 0x2000 bytes
3031 */
3032 .buf_size = 0x2000,
3033 },
3034 .sao_up = {
3035 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3036 * each has 16 bytes total 0x2800 bytes
3037 */
3038 .buf_size = 0x2800,
3039 },
3040 .swap_buf = {
3041 /* 256cyclex64bit = 2K bytes 0x800
3042 * (only 144 cycles valid)
3043 */
3044 .buf_size = 0x800,
3045 },
3046 .swap_buf2 = {
3047 .buf_size = 0x800,
3048 },
3049 .scalelut = {
3050 /* support up to 32 SCALELUT 1024x32 =
3051 * 32Kbytes (0x8000)
3052 */
3053 .buf_size = 0x8000,
3054 },
3055 .dblk_para = {
3056 /* DBLK -> Max 256(4096/16) LCU,
3057 *each para 1024bytes(total:0x40000),
3058 *data 1024bytes(total:0x40000)
3059 */
3060 .buf_size = 0x80000,
3061 },
3062 .dblk_data = {
3063 .buf_size = 0x80000,
3064 },
3065 .seg_map = {
3066 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3067 .buf_size = 0xd800,
3068 },
3069 .mmu_vbh = {
3070 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3071 },
3072#if 0
3073 .cm_header = {
3074 /*add one for keeper.*/
3075 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3076 (FRAME_BUFFERS + 1),
3077 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3078 },
3079#endif
3080 .mpred_above = {
3081 .buf_size = 0x10000, /* 2 * size of hevc*/
3082 },
3083#ifdef MV_USE_FIXED_BUF
3084 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3085 .buf_size = 0x40000 * FRAME_BUFFERS,
3086 },
3087#endif
3088 .rpm = {
3089 .buf_size = RPM_BUF_SIZE,
3090 },
3091 .lmem = {
3092 .buf_size = 0x400 * 2,
3093 }
3094 },
3095 {
3096 .max_width = 4096,
3097 .max_height = 2304,
3098 .ipp = {
3099 /* IPP work space calculation :
3100 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3101 */
3102 .buf_size = 0x4000,
3103 },
3104 .sao_abv = {
3105 .buf_size = 0x30000,
3106 },
3107 .sao_vb = {
3108 .buf_size = 0x30000,
3109 },
3110 .short_term_rps = {
3111 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3112 * total 64x16x2 = 2048 bytes (0x800)
3113 */
3114 .buf_size = 0x800,
3115 },
3116 .vps = {
3117 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3118 * total 0x0800 bytes
3119 */
3120 .buf_size = 0x800,
3121 },
3122 .sps = {
3123 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3124 * total 0x0800 bytes
3125 */
3126 .buf_size = 0x800,
3127 },
3128 .pps = {
3129 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3130 * total 0x2000 bytes
3131 */
3132 .buf_size = 0x2000,
3133 },
3134 .sao_up = {
3135 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3136 * each has 16 bytes total 0x2800 bytes
3137 */
3138 .buf_size = 0x2800,
3139 },
3140 .swap_buf = {
3141 /* 256cyclex64bit = 2K bytes 0x800
3142 * (only 144 cycles valid)
3143 */
3144 .buf_size = 0x800,
3145 },
3146 .swap_buf2 = {
3147 .buf_size = 0x800,
3148 },
3149 .scalelut = {
3150 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3151 * (0x8000)
3152 */
3153 .buf_size = 0x8000,
3154 },
3155 .dblk_para = {
3156 /* DBLK -> Max 256(4096/16) LCU,
3157 *each para 1024bytes(total:0x40000),
3158 *data 1024bytes(total:0x40000)
3159 */
3160 .buf_size = 0x80000,
3161 },
3162 .dblk_data = {
3163 .buf_size = 0x80000,
3164 },
3165 .seg_map = {
3166 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3167 .buf_size = 0xd800,
3168 },
3169 .mmu_vbh = {
3170 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3171 },
3172#if 0
3173 .cm_header = {
3174 /*add one for keeper.*/
3175 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3176 (FRAME_BUFFERS + 1),
3177 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3178 },
3179#endif
3180 .mpred_above = {
3181 .buf_size = 0x10000, /* 2 * size of hevc*/
3182 },
3183#ifdef MV_USE_FIXED_BUF
3184 .mpred_mv = {
3185 /* .buf_size = 0x100000*16,
3186 * //4k2k , 0x100000 per buffer
3187 */
3188 /* 4096x2304 , 0x120000 per buffer */
3189 .buf_size = 0x120000 * FRAME_BUFFERS,
3190 },
3191#endif
3192 .rpm = {
3193 .buf_size = RPM_BUF_SIZE,
3194 },
3195 .lmem = {
3196 .buf_size = 0x400 * 2,
3197 }
3198 },
3199 {
3200 .max_width = 4096*2,
3201 .max_height = 2304*2,
3202 .ipp = {
3203 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3204 .buf_size = 0x4000*2,
3205 },
3206 .sao_abv = {
3207 .buf_size = 0x30000*2,
3208 },
3209 .sao_vb = {
3210 .buf_size = 0x30000*2,
3211 },
3212 .short_term_rps = {
3213 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3214 .buf_size = 0x800,
3215 },
3216 .vps = {
3217 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3218 .buf_size = 0x800,
3219 },
3220 .sps = {
3221 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3222 .buf_size = 0x800,
3223 },
3224 .pps = {
3225 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3226 .buf_size = 0x2000,
3227 },
3228 .sao_up = {
3229 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3230 .buf_size = 0x2800*2,
3231 },
3232 .swap_buf = {
3233 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3234 .buf_size = 0x800,
3235 },
3236 .swap_buf2 = {
3237 .buf_size = 0x800,
3238 },
3239 .scalelut = {
3240 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3241 .buf_size = 0x8000*2,
3242 },
3243 .dblk_para = {
3244 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3245 .buf_size = 0x80000*2,
3246 },
3247 .dblk_data = {
3248 .buf_size = 0x80000*2,
3249 },
3250 .seg_map = {
3251 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3252 .buf_size = 0xd800*4,
3253 },
3254 .mmu_vbh = {
3255 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3256 },
3257#if 0
3258 .cm_header = {
3259 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3260 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3261 },
3262#endif
3263 .mpred_above = {
3264 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3265 },
3266#ifdef MV_USE_FIXED_BUF
3267 .mpred_mv = {
3268 //4k2k , 0x100000 per buffer */
3269 /* 4096x2304 , 0x120000 per buffer */
3270 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3271 },
3272#endif
3273 .rpm = {
3274 .buf_size = RPM_BUF_SIZE,
3275 },
3276 .lmem = {
3277 .buf_size = 0x400 * 2,
3278 }
3279 }
3280};
3281
3282
3283/*Losless compression body buffer size 4K per 64x32 (jt)*/
3284int compute_losless_comp_body_size(int width, int height,
3285 uint8_t is_bit_depth_10)
3286{
3287 int width_x64;
3288 int height_x32;
3289 int bsize;
3290
3291 width_x64 = width + 63;
3292 width_x64 >>= 6;
3293 height_x32 = height + 31;
3294 height_x32 >>= 5;
3295 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3296 if (debug & VP9_DEBUG_BUFMGR_MORE)
3297 pr_info("%s(%d,%d,%d)=>%d\n",
3298 __func__, width, height,
3299 is_bit_depth_10, bsize);
3300
3301 return bsize;
3302}
3303
3304/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3305static int compute_losless_comp_header_size(int width, int height)
3306{
3307 int width_x128;
3308 int height_x64;
3309 int hsize;
3310
3311 width_x128 = width + 127;
3312 width_x128 >>= 7;
3313 height_x64 = height + 63;
3314 height_x64 >>= 6;
3315
3316 hsize = 32 * width_x128 * height_x64;
3317 if (debug & VP9_DEBUG_BUFMGR_MORE)
3318 pr_info("%s(%d,%d)=>%d\n",
3319 __func__, width, height,
3320 hsize);
3321
3322 return hsize;
3323}
3324
3325static void init_buff_spec(struct VP9Decoder_s *pbi,
3326 struct BuffInfo_s *buf_spec)
3327{
3328 void *mem_start_virt;
3329
3330 buf_spec->ipp.buf_start = buf_spec->start_adr;
3331 buf_spec->sao_abv.buf_start =
3332 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3333
3334 buf_spec->sao_vb.buf_start =
3335 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3336 buf_spec->short_term_rps.buf_start =
3337 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3338 buf_spec->vps.buf_start =
3339 buf_spec->short_term_rps.buf_start +
3340 buf_spec->short_term_rps.buf_size;
3341 buf_spec->sps.buf_start =
3342 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3343 buf_spec->pps.buf_start =
3344 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3345 buf_spec->sao_up.buf_start =
3346 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3347 buf_spec->swap_buf.buf_start =
3348 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3349 buf_spec->swap_buf2.buf_start =
3350 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3351 buf_spec->scalelut.buf_start =
3352 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3353 buf_spec->dblk_para.buf_start =
3354 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3355 buf_spec->dblk_data.buf_start =
3356 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3357 buf_spec->seg_map.buf_start =
3358 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3359 if (pbi == NULL || pbi->mmu_enable) {
3360 buf_spec->mmu_vbh.buf_start =
3361 buf_spec->seg_map.buf_start +
3362 buf_spec->seg_map.buf_size;
3363 buf_spec->mpred_above.buf_start =
3364 buf_spec->mmu_vbh.buf_start +
3365 buf_spec->mmu_vbh.buf_size;
3366 } else {
3367 buf_spec->mpred_above.buf_start =
3368 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3369 }
3370#ifdef MV_USE_FIXED_BUF
3371 buf_spec->mpred_mv.buf_start =
3372 buf_spec->mpred_above.buf_start +
3373 buf_spec->mpred_above.buf_size;
3374
3375 buf_spec->rpm.buf_start =
3376 buf_spec->mpred_mv.buf_start +
3377 buf_spec->mpred_mv.buf_size;
3378#else
3379 buf_spec->rpm.buf_start =
3380 buf_spec->mpred_above.buf_start +
3381 buf_spec->mpred_above.buf_size;
3382
3383#endif
3384 buf_spec->lmem.buf_start =
3385 buf_spec->rpm.buf_start +
3386 buf_spec->rpm.buf_size;
3387 buf_spec->end_adr =
3388 buf_spec->lmem.buf_start +
3389 buf_spec->lmem.buf_size;
3390
3391 if (!pbi)
3392 return;
3393
3394 if (!vdec_secure(hw_to_vdec(pbi))) {
3395 mem_start_virt =
3396 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3397 if (mem_start_virt) {
3398 memset(mem_start_virt, 0,
3399 buf_spec->dblk_para.buf_size);
3400 codec_mm_dma_flush(mem_start_virt,
3401 buf_spec->dblk_para.buf_size,
3402 DMA_TO_DEVICE);
3403 } else {
3404 mem_start_virt = codec_mm_vmap(
3405 buf_spec->dblk_para.buf_start,
3406 buf_spec->dblk_para.buf_size);
3407 if (mem_start_virt) {
3408 memset(mem_start_virt, 0,
3409 buf_spec->dblk_para.buf_size);
3410 codec_mm_dma_flush(mem_start_virt,
3411 buf_spec->dblk_para.buf_size,
3412 DMA_TO_DEVICE);
3413 codec_mm_unmap_phyaddr(mem_start_virt);
3414 } else {
3415 /*not virt for tvp playing,
3416 may need clear on ucode.*/
3417 pr_err("mem_start_virt failed\n");
3418 }
3419 }
3420 }
3421
3422 if (debug) {
3423 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3424 buf_spec->start_adr, buf_spec->end_adr,
3425 buf_spec->end_adr - buf_spec->start_adr);
3426 }
3427
3428 if (debug) {
3429 pr_info("ipp.buf_start :%x\n",
3430 buf_spec->ipp.buf_start);
3431 pr_info("sao_abv.buf_start :%x\n",
3432 buf_spec->sao_abv.buf_start);
3433 pr_info("sao_vb.buf_start :%x\n",
3434 buf_spec->sao_vb.buf_start);
3435 pr_info("short_term_rps.buf_start :%x\n",
3436 buf_spec->short_term_rps.buf_start);
3437 pr_info("vps.buf_start :%x\n",
3438 buf_spec->vps.buf_start);
3439 pr_info("sps.buf_start :%x\n",
3440 buf_spec->sps.buf_start);
3441 pr_info("pps.buf_start :%x\n",
3442 buf_spec->pps.buf_start);
3443 pr_info("sao_up.buf_start :%x\n",
3444 buf_spec->sao_up.buf_start);
3445 pr_info("swap_buf.buf_start :%x\n",
3446 buf_spec->swap_buf.buf_start);
3447 pr_info("swap_buf2.buf_start :%x\n",
3448 buf_spec->swap_buf2.buf_start);
3449 pr_info("scalelut.buf_start :%x\n",
3450 buf_spec->scalelut.buf_start);
3451 pr_info("dblk_para.buf_start :%x\n",
3452 buf_spec->dblk_para.buf_start);
3453 pr_info("dblk_data.buf_start :%x\n",
3454 buf_spec->dblk_data.buf_start);
3455 pr_info("seg_map.buf_start :%x\n",
3456 buf_spec->seg_map.buf_start);
3457 if (pbi->mmu_enable) {
3458 pr_info("mmu_vbh.buf_start :%x\n",
3459 buf_spec->mmu_vbh.buf_start);
3460 }
3461 pr_info("mpred_above.buf_start :%x\n",
3462 buf_spec->mpred_above.buf_start);
3463#ifdef MV_USE_FIXED_BUF
3464 pr_info("mpred_mv.buf_start :%x\n",
3465 buf_spec->mpred_mv.buf_start);
3466#endif
3467 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3468 pr_info("rpm.buf_start :%x\n",
3469 buf_spec->rpm.buf_start);
3470 }
3471 }
3472}
3473
3474/* cache_util.c */
3475#define THODIYIL_MCRCC_CANVAS_ALGX 4
3476
3477static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3478
3479static void mcrcc_perfcount_reset(void)
3480{
3481 if (debug & VP9_DEBUG_CACHE)
3482 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3483 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3484 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3485 return;
3486}
3487
3488static unsigned raw_mcr_cnt_total_prev;
3489static unsigned hit_mcr_0_cnt_total_prev;
3490static unsigned hit_mcr_1_cnt_total_prev;
3491static unsigned byp_mcr_cnt_nchcanv_total_prev;
3492static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3493
3494static void mcrcc_get_hitrate(unsigned reset_pre)
3495{
3496 unsigned delta_hit_mcr_0_cnt;
3497 unsigned delta_hit_mcr_1_cnt;
3498 unsigned delta_raw_mcr_cnt;
3499 unsigned delta_mcr_cnt_nchcanv;
3500 unsigned delta_mcr_cnt_nchoutwin;
3501
3502 unsigned tmp;
3503 unsigned raw_mcr_cnt;
3504 unsigned hit_mcr_cnt;
3505 unsigned byp_mcr_cnt_nchoutwin;
3506 unsigned byp_mcr_cnt_nchcanv;
3507 int hitrate;
3508 if (reset_pre) {
3509 raw_mcr_cnt_total_prev = 0;
3510 hit_mcr_0_cnt_total_prev = 0;
3511 hit_mcr_1_cnt_total_prev = 0;
3512 byp_mcr_cnt_nchcanv_total_prev = 0;
3513 byp_mcr_cnt_nchoutwin_total_prev = 0;
3514 }
3515 if (debug & VP9_DEBUG_CACHE)
3516 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3517 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3518 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3519 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3520 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3521 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3522 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3523 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3524 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3525
3526 if (debug & VP9_DEBUG_CACHE)
3527 pr_info("raw_mcr_cnt_total: %d\n",
3528 raw_mcr_cnt);
3529 if (debug & VP9_DEBUG_CACHE)
3530 pr_info("hit_mcr_cnt_total: %d\n",
3531 hit_mcr_cnt);
3532 if (debug & VP9_DEBUG_CACHE)
3533 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3534 byp_mcr_cnt_nchoutwin);
3535 if (debug & VP9_DEBUG_CACHE)
3536 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3537 byp_mcr_cnt_nchcanv);
3538
3539 delta_raw_mcr_cnt = raw_mcr_cnt -
3540 raw_mcr_cnt_total_prev;
3541 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3542 byp_mcr_cnt_nchcanv_total_prev;
3543 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3544 byp_mcr_cnt_nchoutwin_total_prev;
3545 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3546 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3547 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3548
3549 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3550 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3551 if (debug & VP9_DEBUG_CACHE)
3552 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3553 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3554 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3555 if (debug & VP9_DEBUG_CACHE)
3556 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3557 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3558 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3559 if (debug & VP9_DEBUG_CACHE)
3560 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3561 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3562 hit_mcr_0_cnt_total_prev = tmp;
3563 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3564 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3565 if (debug & VP9_DEBUG_CACHE)
3566 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3567 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3568 hit_mcr_1_cnt_total_prev = tmp;
3569
3570 if (delta_raw_mcr_cnt != 0) {
3571 hitrate = 100 * delta_hit_mcr_0_cnt
3572 / delta_raw_mcr_cnt;
3573 if (debug & VP9_DEBUG_CACHE)
3574 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3575 hitrate = 100 * delta_hit_mcr_1_cnt
3576 / delta_raw_mcr_cnt;
3577 if (debug & VP9_DEBUG_CACHE)
3578 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3579 hitrate = 100 * delta_mcr_cnt_nchcanv
3580 / delta_raw_mcr_cnt;
3581 if (debug & VP9_DEBUG_CACHE)
3582 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3583 hitrate = 100 * delta_mcr_cnt_nchoutwin
3584 / delta_raw_mcr_cnt;
3585 if (debug & VP9_DEBUG_CACHE)
3586 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3587 }
3588
3589
3590 if (raw_mcr_cnt != 0) {
3591 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3592 if (debug & VP9_DEBUG_CACHE)
3593 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3594 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3595 / raw_mcr_cnt;
3596 if (debug & VP9_DEBUG_CACHE)
3597 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3598 } else {
3599 if (debug & VP9_DEBUG_CACHE)
3600 pr_info("MCRCC_HIT_RATE : na\n");
3601 if (debug & VP9_DEBUG_CACHE)
3602 pr_info("MCRCC_BYP_RATE : na\n");
3603 }
3604 return;
3605}
3606
3607
3608static void decomp_perfcount_reset(void)
3609{
3610 if (debug & VP9_DEBUG_CACHE)
3611 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3612 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3613 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3614 return;
3615}
3616
3617static void decomp_get_hitrate(void)
3618{
3619 unsigned raw_mcr_cnt;
3620 unsigned hit_mcr_cnt;
3621 int hitrate;
3622 if (debug & VP9_DEBUG_CACHE)
3623 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3624 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3625 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3626 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3627 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3628
3629 if (debug & VP9_DEBUG_CACHE)
3630 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3631 if (debug & VP9_DEBUG_CACHE)
3632 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3633
3634 if (raw_mcr_cnt != 0) {
3635 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3636 if (debug & VP9_DEBUG_CACHE)
3637 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3638 } else {
3639 if (debug & VP9_DEBUG_CACHE)
3640 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3641 }
3642 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3643 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3644 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3645 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3646
3647 if (debug & VP9_DEBUG_CACHE)
3648 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3649 if (debug & VP9_DEBUG_CACHE)
3650 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3651
3652 if (raw_mcr_cnt != 0) {
3653 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3654 if (debug & VP9_DEBUG_CACHE)
3655 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3656 } else {
3657 if (debug & VP9_DEBUG_CACHE)
3658 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3659 }
3660 return;
3661}
3662
3663static void decomp_get_comprate(void)
3664{
3665 unsigned raw_ucomp_cnt;
3666 unsigned fast_comp_cnt;
3667 unsigned slow_comp_cnt;
3668 int comprate;
3669
3670 if (debug & VP9_DEBUG_CACHE)
3671 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3672 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3673 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3674 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3675 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3676 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3677 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3678
3679 if (debug & VP9_DEBUG_CACHE)
3680 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3681 if (debug & VP9_DEBUG_CACHE)
3682 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3683 if (debug & VP9_DEBUG_CACHE)
3684 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3685
3686 if (raw_ucomp_cnt != 0) {
3687 comprate = (fast_comp_cnt + slow_comp_cnt)
3688 * 100 / raw_ucomp_cnt;
3689 if (debug & VP9_DEBUG_CACHE)
3690 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3691 } else {
3692 if (debug & VP9_DEBUG_CACHE)
3693 pr_info("DECOMP_COMP_RATIO : na\n");
3694 }
3695 return;
3696}
3697/* cache_util.c end */
3698
3699/*====================================================
3700 *========================================================================
3701 *vp9_prob define
3702 *========================================================================
3703 */
3704#define VP9_PARTITION_START 0
3705#define VP9_PARTITION_SIZE_STEP (3 * 4)
3706#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3707#define VP9_PARTITION_KEY_START 0
3708#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3709#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3710#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3711#define VP9_SKIP_SIZE 4 /* only use 3*/
3712#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3713#define VP9_TX_MODE_8_0_OFFSET 0
3714#define VP9_TX_MODE_8_1_OFFSET 1
3715#define VP9_TX_MODE_16_0_OFFSET 2
3716#define VP9_TX_MODE_16_1_OFFSET 4
3717#define VP9_TX_MODE_32_0_OFFSET 6
3718#define VP9_TX_MODE_32_1_OFFSET 9
3719#define VP9_TX_MODE_SIZE 12
3720#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3721#define VP9_COEF_BAND_0_OFFSET 0
3722#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3723#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3724#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3725#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3726#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3727#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3728#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3729#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3730#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3731#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3732#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3733#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3734#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3735#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3736#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3737#define VP9_INTERP_SIZE 8
3738#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3739#define VP9_INTRA_INTER_SIZE 4
3740#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3741#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3742#define VP9_COMP_INTER_START \
3743 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3744#define VP9_COMP_INTER_SIZE 5
3745#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3746#define VP9_COMP_REF_SIZE 5
3747#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3748#define VP9_SINGLE_REF_SIZE 10
3749#define VP9_REF_MODE_START VP9_COMP_INTER_START
3750#define VP9_REF_MODE_SIZE \
3751 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3752#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3753#define VP9_IF_Y_MODE_SIZE 36
3754#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3755#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3756#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3757#define VP9_MV_JOINTS_SIZE 3
3758#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3759#define VP9_MV_SIGN_0_SIZE 1
3760#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3761#define VP9_MV_CLASSES_0_SIZE 10
3762#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3763#define VP9_MV_CLASS0_0_SIZE 1
3764#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3765#define VP9_MV_BITS_0_SIZE 10
3766#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3767#define VP9_MV_SIGN_1_SIZE 1
3768#define VP9_MV_CLASSES_1_START \
3769 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3770#define VP9_MV_CLASSES_1_SIZE 10
3771#define VP9_MV_CLASS0_1_START \
3772 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3773#define VP9_MV_CLASS0_1_SIZE 1
3774#define VP9_MV_BITS_1_START \
3775 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3776#define VP9_MV_BITS_1_SIZE 10
3777#define VP9_MV_CLASS0_FP_0_START \
3778 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3779#define VP9_MV_CLASS0_FP_0_SIZE 9
3780#define VP9_MV_CLASS0_FP_1_START \
3781 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3782#define VP9_MV_CLASS0_FP_1_SIZE 9
3783#define VP9_MV_CLASS0_HP_0_START \
3784 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3785#define VP9_MV_CLASS0_HP_0_SIZE 2
3786#define VP9_MV_CLASS0_HP_1_START \
3787 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3788#define VP9_MV_CLASS0_HP_1_SIZE 2
3789#define VP9_MV_START VP9_MV_JOINTS_START
3790#define VP9_MV_SIZE 72 /*only use 69*/
3791
3792#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3793
3794
3795/*========================================================================
3796 * vp9_count_mem define
3797 *========================================================================
3798 */
3799#define VP9_COEF_COUNT_START 0
3800#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3801#define VP9_COEF_COUNT_BAND_1_OFFSET \
3802 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3803#define VP9_COEF_COUNT_BAND_2_OFFSET \
3804 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3805#define VP9_COEF_COUNT_BAND_3_OFFSET \
3806 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3807#define VP9_COEF_COUNT_BAND_4_OFFSET \
3808 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3809#define VP9_COEF_COUNT_BAND_5_OFFSET \
3810 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3811#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3812#define VP9_COEF_COUNT_4X4_START \
3813 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3814#define VP9_COEF_COUNT_8X8_START \
3815 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3816#define VP9_COEF_COUNT_16X16_START \
3817 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3818#define VP9_COEF_COUNT_32X32_START \
3819 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3820#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3821#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3822
3823#define VP9_INTRA_INTER_COUNT_START \
3824 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3825#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3826#define VP9_COMP_INTER_COUNT_START \
3827 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3828#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3829#define VP9_COMP_REF_COUNT_START \
3830 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3831#define VP9_COMP_REF_COUNT_SIZE (5*2)
3832#define VP9_SINGLE_REF_COUNT_START \
3833 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3834#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3835#define VP9_TX_MODE_COUNT_START \
3836 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3837#define VP9_TX_MODE_COUNT_SIZE (12*2)
3838#define VP9_SKIP_COUNT_START \
3839 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3840#define VP9_SKIP_COUNT_SIZE (3*2)
3841#define VP9_MV_SIGN_0_COUNT_START \
3842 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3843#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3844#define VP9_MV_SIGN_1_COUNT_START \
3845 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3846#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3847#define VP9_MV_BITS_0_COUNT_START \
3848 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3849#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3850#define VP9_MV_BITS_1_COUNT_START \
3851 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3852#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3853#define VP9_MV_CLASS0_HP_0_COUNT_START \
3854 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3855#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3856#define VP9_MV_CLASS0_HP_1_COUNT_START \
3857 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3858#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3859/* Start merge_tree*/
3860#define VP9_INTER_MODE_COUNT_START \
3861 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3862#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3863#define VP9_IF_Y_MODE_COUNT_START \
3864 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3865#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3866#define VP9_IF_UV_MODE_COUNT_START \
3867 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3868#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3869#define VP9_PARTITION_P_COUNT_START \
3870 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3871#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3872#define VP9_INTERP_COUNT_START \
3873 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3874#define VP9_INTERP_COUNT_SIZE (4*3)
3875#define VP9_MV_JOINTS_COUNT_START \
3876 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3877#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3878#define VP9_MV_CLASSES_0_COUNT_START \
3879 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3880#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3881#define VP9_MV_CLASS0_0_COUNT_START \
3882 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3883#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3884#define VP9_MV_CLASSES_1_COUNT_START \
3885 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3886#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3887#define VP9_MV_CLASS0_1_COUNT_START \
3888 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3889#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3890#define VP9_MV_CLASS0_FP_0_COUNT_START \
3891 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3892#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3893#define VP9_MV_CLASS0_FP_1_COUNT_START \
3894 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3895#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3896
3897
3898#define DC_PRED 0 /* Average of above and left pixels*/
3899#define V_PRED 1 /* Vertical*/
3900#define H_PRED 2 /* Horizontal*/
3901#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3902#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3903#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3904#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3905#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3906#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3907#define TM_PRED 9 /*True-motion*/
3908
3909int clip_prob(int p)
3910{
3911 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3912}
3913
3914#define ROUND_POWER_OF_TWO(value, n) \
3915 (((value) + (1 << ((n) - 1))) >> (n))
3916
3917#define MODE_MV_COUNT_SAT 20
3918static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3919 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3920 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3921};
3922
3923void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3924 int coef_node_start, int tree_left, int tree_right, int tree_i,
3925 int node) {
3926
3927 int prob_32, prob_res, prob_shift;
3928 int pre_prob, new_prob;
3929 int den, m_count, get_prob, factor;
3930
3931 prob_32 = prev_prob[coef_node_start / 4 * 2];
3932 prob_res = coef_node_start & 3;
3933 prob_shift = prob_res * 8;
3934 pre_prob = (prob_32 >> prob_shift) & 0xff;
3935
3936 den = tree_left + tree_right;
3937
3938 if (den == 0)
3939 new_prob = pre_prob;
3940 else {
3941 m_count = (den < MODE_MV_COUNT_SAT) ?
3942 den : MODE_MV_COUNT_SAT;
3943 get_prob = clip_prob(
3944 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3945 den));
3946 /*weighted_prob*/
3947 factor = count_to_update_factor[m_count];
3948 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3949 + get_prob * factor, 8);
3950 }
3951 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3952 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
3953
3954 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3955 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3956 *cur_prob[coef_node_start/4*2]);
3957 */
3958}
3959
3960
3961/*void adapt_coef_probs(void)*/
3962void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3963 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3964{
3965 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3966 *unsigned int prev_prob[496*2];
3967 *unsigned int cur_prob[496*2];
3968 *0x300 * 128bits = 0x3000 (32K Bytes)
3969 *unsigned int count[0x300*4];
3970 */
3971
3972 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
3973 int plane, coef_plane_start, coef_count_plane_start;
3974 int type, coef_type_start, coef_count_type_start;
3975 int band, coef_band_start, coef_count_band_start;
3976 int cxt_num;
3977 int cxt, coef_cxt_start, coef_count_cxt_start;
3978 int node, coef_node_start, coef_count_node_start;
3979
3980 int tree_i, tree_left, tree_right;
3981 int mvd_i;
3982
3983 int count_sat = 24;
3984 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
3985 *use 128
3986 */
3987 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
3988 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
3989 int update_factor = cur_kf ? 112 :
3990 prev_kf ? 128 : 112;
3991
3992 int prob_32;
3993 int prob_res;
3994 int prob_shift;
3995 int pre_prob;
3996
3997 int num, den;
3998 int get_prob;
3999 int m_count;
4000 int factor;
4001
4002 int new_prob;
4003
4004 if (debug & VP9_DEBUG_MERGE)
4005 pr_info
4006 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4007 pre_fc, prev_kf, cur_kf);
4008
4009 /*adapt_coef_probs*/
4010 for (tx_size = 0; tx_size < 4; tx_size++) {
4011 coef_tx_size_start = VP9_COEF_START
4012 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4013 coef_count_tx_size_start = VP9_COEF_COUNT_START
4014 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4015 coef_plane_start = coef_tx_size_start;
4016 coef_count_plane_start = coef_count_tx_size_start;
4017 for (plane = 0; plane < 2; plane++) {
4018 coef_type_start = coef_plane_start;
4019 coef_count_type_start = coef_count_plane_start;
4020 for (type = 0; type < 2; type++) {
4021 coef_band_start = coef_type_start;
4022 coef_count_band_start = coef_count_type_start;
4023 for (band = 0; band < 6; band++) {
4024 if (band == 0)
4025 cxt_num = 3;
4026 else
4027 cxt_num = 6;
4028 coef_cxt_start = coef_band_start;
4029 coef_count_cxt_start =
4030 coef_count_band_start;
4031 for (cxt = 0; cxt < cxt_num; cxt++) {
4032 const int n0 =
4033 count[coef_count_cxt_start];
4034 const int n1 =
4035 count[coef_count_cxt_start + 1];
4036 const int n2 =
4037 count[coef_count_cxt_start + 2];
4038 const int neob =
4039 count[coef_count_cxt_start + 3];
4040 const int nneob =
4041 count[coef_count_cxt_start + 4];
4042 const unsigned int
4043 branch_ct[3][2] = {
4044 { neob, nneob },
4045 { n0, n1 + n2 },
4046 { n1, n2 }
4047 };
4048 coef_node_start =
4049 coef_cxt_start;
4050 for
4051 (node = 0; node < 3; node++) {
4052 prob_32 =
4053 prev_prob[
4054 coef_node_start
4055 / 4 * 2];
4056 prob_res =
4057 coef_node_start & 3;
4058 prob_shift =
4059 prob_res * 8;
4060 pre_prob =
4061 (prob_32 >> prob_shift)
4062 & 0xff;
4063
4064 /*get_binary_prob*/
4065 num =
4066 branch_ct[node][0];
4067 den =
4068 branch_ct[node][0] +
4069 branch_ct[node][1];
4070 m_count = (den <
4071 count_sat)
4072 ? den : count_sat;
4073
4074 get_prob =
4075 (den == 0) ? 128u :
4076 clip_prob(
4077 div_r32(((int64_t)
4078 num * 256
4079 + (den >> 1)),
4080 den));
4081
4082 factor =
4083 update_factor * m_count
4084 / count_sat;
4085 new_prob =
4086 ROUND_POWER_OF_TWO
4087 (pre_prob *
4088 (256 - factor) +
4089 get_prob * factor, 8);
4090
4091 cur_prob[coef_node_start
4092 / 4 * 2] =
4093 (cur_prob
4094 [coef_node_start
4095 / 4 * 2] & (~(0xff <<
4096 prob_shift))) |
4097 (new_prob <<
4098 prob_shift);
4099
4100 coef_node_start += 1;
4101 }
4102
4103 coef_cxt_start =
4104 coef_cxt_start + 3;
4105 coef_count_cxt_start =
4106 coef_count_cxt_start
4107 + 5;
4108 }
4109 if (band == 0) {
4110 coef_band_start += 10;
4111 coef_count_band_start += 15;
4112 } else {
4113 coef_band_start += 18;
4114 coef_count_band_start += 30;
4115 }
4116 }
4117 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4118 coef_count_type_start +=
4119 VP9_COEF_COUNT_SIZE_ONE_SET;
4120 }
4121 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4122 coef_count_plane_start +=
4123 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4124 }
4125 }
4126
4127 if (cur_kf == 0) {
4128 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4129 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4130 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4131 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4132
4133 if (coef_count_node_start ==
4134 VP9_INTRA_INTER_COUNT_START) {
4135 if (debug & VP9_DEBUG_MERGE)
4136 pr_info(" # merge_intra_inter_prob\n");
4137 coef_node_start = VP9_INTRA_INTER_START;
4138 } else if (coef_count_node_start ==
4139 VP9_COMP_INTER_COUNT_START) {
4140 if (debug & VP9_DEBUG_MERGE)
4141 pr_info(" # merge_comp_inter_prob\n");
4142 coef_node_start = VP9_COMP_INTER_START;
4143 }
4144 /*
4145 *else if (coef_count_node_start ==
4146 * VP9_COMP_REF_COUNT_START) {
4147 * pr_info(" # merge_comp_inter_prob\n");
4148 * coef_node_start = VP9_COMP_REF_START;
4149 *}
4150 *else if (coef_count_node_start ==
4151 * VP9_SINGLE_REF_COUNT_START) {
4152 * pr_info(" # merge_comp_inter_prob\n");
4153 * coef_node_start = VP9_SINGLE_REF_START;
4154 *}
4155 */
4156 else if (coef_count_node_start ==
4157 VP9_TX_MODE_COUNT_START) {
4158 if (debug & VP9_DEBUG_MERGE)
4159 pr_info(" # merge_tx_mode_probs\n");
4160 coef_node_start = VP9_TX_MODE_START;
4161 } else if (coef_count_node_start ==
4162 VP9_SKIP_COUNT_START) {
4163 if (debug & VP9_DEBUG_MERGE)
4164 pr_info(" # merge_skip_probs\n");
4165 coef_node_start = VP9_SKIP_START;
4166 } else if (coef_count_node_start ==
4167 VP9_MV_SIGN_0_COUNT_START) {
4168 if (debug & VP9_DEBUG_MERGE)
4169 pr_info(" # merge_sign_0\n");
4170 coef_node_start = VP9_MV_SIGN_0_START;
4171 } else if (coef_count_node_start ==
4172 VP9_MV_SIGN_1_COUNT_START) {
4173 if (debug & VP9_DEBUG_MERGE)
4174 pr_info(" # merge_sign_1\n");
4175 coef_node_start = VP9_MV_SIGN_1_START;
4176 } else if (coef_count_node_start ==
4177 VP9_MV_BITS_0_COUNT_START) {
4178 if (debug & VP9_DEBUG_MERGE)
4179 pr_info(" # merge_bits_0\n");
4180 coef_node_start = VP9_MV_BITS_0_START;
4181 } else if (coef_count_node_start ==
4182 VP9_MV_BITS_1_COUNT_START) {
4183 if (debug & VP9_DEBUG_MERGE)
4184 pr_info(" # merge_bits_1\n");
4185 coef_node_start = VP9_MV_BITS_1_START;
4186 } else if (coef_count_node_start ==
4187 VP9_MV_CLASS0_HP_0_COUNT_START) {
4188 if (debug & VP9_DEBUG_MERGE)
4189 pr_info(" # merge_class0_hp\n");
4190 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4191 }
4192
4193
4194 den = count[coef_count_node_start] +
4195 count[coef_count_node_start + 1];
4196
4197 prob_32 = prev_prob[coef_node_start / 4 * 2];
4198 prob_res = coef_node_start & 3;
4199 prob_shift = prob_res * 8;
4200 pre_prob = (prob_32 >> prob_shift) & 0xff;
4201
4202 if (den == 0)
4203 new_prob = pre_prob;
4204 else {
4205 m_count = (den < MODE_MV_COUNT_SAT) ?
4206 den : MODE_MV_COUNT_SAT;
4207 get_prob =
4208 clip_prob(
4209 div_r32(((int64_t)count[coef_count_node_start]
4210 * 256 + (den >> 1)),
4211 den));
4212 /*weighted_prob*/
4213 factor = count_to_update_factor[m_count];
4214 new_prob =
4215 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4216 + get_prob * factor, 8);
4217 }
4218 cur_prob[coef_node_start / 4 * 2] =
4219 (cur_prob[coef_node_start / 4 * 2] &
4220 (~(0xff << prob_shift)))
4221 | (new_prob << prob_shift);
4222
4223 coef_node_start = coef_node_start + 1;
4224 }
4225 if (debug & VP9_DEBUG_MERGE)
4226 pr_info(" # merge_vp9_inter_mode_tree\n");
4227 coef_node_start = VP9_INTER_MODE_START;
4228 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4229 for (tree_i = 0; tree_i < 7; tree_i++) {
4230 for (node = 0; node < 3; node++) {
4231 switch (node) {
4232 case 2:
4233 tree_left =
4234 count[coef_count_node_start + 1];
4235 tree_right =
4236 count[coef_count_node_start + 3];
4237 break;
4238 case 1:
4239 tree_left =
4240 count[coef_count_node_start + 0];
4241 tree_right =
4242 count[coef_count_node_start + 1]
4243 + count[coef_count_node_start + 3];
4244 break;
4245 default:
4246 tree_left =
4247 count[coef_count_node_start + 2];
4248 tree_right =
4249 count[coef_count_node_start + 0]
4250 + count[coef_count_node_start + 1]
4251 + count[coef_count_node_start + 3];
4252 break;
4253
4254 }
4255
4256 vp9_tree_merge_probs(prev_prob, cur_prob,
4257 coef_node_start, tree_left, tree_right,
4258 tree_i, node);
4259
4260 coef_node_start = coef_node_start + 1;
4261 }
4262 coef_count_node_start = coef_count_node_start + 4;
4263 }
4264 if (debug & VP9_DEBUG_MERGE)
4265 pr_info(" # merge_vp9_intra_mode_tree\n");
4266 coef_node_start = VP9_IF_Y_MODE_START;
4267 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4268 for (tree_i = 0; tree_i < 14; tree_i++) {
4269 for (node = 0; node < 9; node++) {
4270 switch (node) {
4271 case 8:
4272 tree_left =
4273 count[coef_count_node_start+D153_PRED];
4274 tree_right =
4275 count[coef_count_node_start+D207_PRED];
4276 break;
4277 case 7:
4278 tree_left =
4279 count[coef_count_node_start+D63_PRED];
4280 tree_right =
4281 count[coef_count_node_start+D207_PRED] +
4282 count[coef_count_node_start+D153_PRED];
4283 break;
4284 case 6:
4285 tree_left =
4286 count[coef_count_node_start + D45_PRED];
4287 tree_right =
4288 count[coef_count_node_start+D207_PRED] +
4289 count[coef_count_node_start+D153_PRED] +
4290 count[coef_count_node_start+D63_PRED];
4291 break;
4292 case 5:
4293 tree_left =
4294 count[coef_count_node_start+D135_PRED];
4295 tree_right =
4296 count[coef_count_node_start+D117_PRED];
4297 break;
4298 case 4:
4299 tree_left =
4300 count[coef_count_node_start+H_PRED];
4301 tree_right =
4302 count[coef_count_node_start+D117_PRED] +
4303 count[coef_count_node_start+D135_PRED];
4304 break;
4305 case 3:
4306 tree_left =
4307 count[coef_count_node_start+H_PRED] +
4308 count[coef_count_node_start+D117_PRED] +
4309 count[coef_count_node_start+D135_PRED];
4310 tree_right =
4311 count[coef_count_node_start+D45_PRED] +
4312 count[coef_count_node_start+D207_PRED] +
4313 count[coef_count_node_start+D153_PRED] +
4314 count[coef_count_node_start+D63_PRED];
4315 break;
4316 case 2:
4317 tree_left =
4318 count[coef_count_node_start+V_PRED];
4319 tree_right =
4320 count[coef_count_node_start+H_PRED] +
4321 count[coef_count_node_start+D117_PRED] +
4322 count[coef_count_node_start+D135_PRED] +
4323 count[coef_count_node_start+D45_PRED] +
4324 count[coef_count_node_start+D207_PRED] +
4325 count[coef_count_node_start+D153_PRED] +
4326 count[coef_count_node_start+D63_PRED];
4327 break;
4328 case 1:
4329 tree_left =
4330 count[coef_count_node_start+TM_PRED];
4331 tree_right =
4332 count[coef_count_node_start+V_PRED] +
4333 count[coef_count_node_start+H_PRED] +
4334 count[coef_count_node_start+D117_PRED] +
4335 count[coef_count_node_start+D135_PRED] +
4336 count[coef_count_node_start+D45_PRED] +
4337 count[coef_count_node_start+D207_PRED] +
4338 count[coef_count_node_start+D153_PRED] +
4339 count[coef_count_node_start+D63_PRED];
4340 break;
4341 default:
4342 tree_left =
4343 count[coef_count_node_start+DC_PRED];
4344 tree_right =
4345 count[coef_count_node_start+TM_PRED] +
4346 count[coef_count_node_start+V_PRED] +
4347 count[coef_count_node_start+H_PRED] +
4348 count[coef_count_node_start+D117_PRED] +
4349 count[coef_count_node_start+D135_PRED] +
4350 count[coef_count_node_start+D45_PRED] +
4351 count[coef_count_node_start+D207_PRED] +
4352 count[coef_count_node_start+D153_PRED] +
4353 count[coef_count_node_start+D63_PRED];
4354 break;
4355
4356 }
4357
4358 vp9_tree_merge_probs(prev_prob, cur_prob,
4359 coef_node_start, tree_left, tree_right,
4360 tree_i, node);
4361
4362 coef_node_start = coef_node_start + 1;
4363 }
4364 coef_count_node_start = coef_count_node_start + 10;
4365 }
4366
4367 if (debug & VP9_DEBUG_MERGE)
4368 pr_info(" # merge_vp9_partition_tree\n");
4369 coef_node_start = VP9_PARTITION_P_START;
4370 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4371 for (tree_i = 0; tree_i < 16; tree_i++) {
4372 for (node = 0; node < 3; node++) {
4373 switch (node) {
4374 case 2:
4375 tree_left =
4376 count[coef_count_node_start + 2];
4377 tree_right =
4378 count[coef_count_node_start + 3];
4379 break;
4380 case 1:
4381 tree_left =
4382 count[coef_count_node_start + 1];
4383 tree_right =
4384 count[coef_count_node_start + 2] +
4385 count[coef_count_node_start + 3];
4386 break;
4387 default:
4388 tree_left =
4389 count[coef_count_node_start + 0];
4390 tree_right =
4391 count[coef_count_node_start + 1] +
4392 count[coef_count_node_start + 2] +
4393 count[coef_count_node_start + 3];
4394 break;
4395
4396 }
4397
4398 vp9_tree_merge_probs(prev_prob, cur_prob,
4399 coef_node_start,
4400 tree_left, tree_right, tree_i, node);
4401
4402 coef_node_start = coef_node_start + 1;
4403 }
4404 coef_count_node_start = coef_count_node_start + 4;
4405 }
4406
4407 if (debug & VP9_DEBUG_MERGE)
4408 pr_info(" # merge_vp9_switchable_interp_tree\n");
4409 coef_node_start = VP9_INTERP_START;
4410 coef_count_node_start = VP9_INTERP_COUNT_START;
4411 for (tree_i = 0; tree_i < 4; tree_i++) {
4412 for (node = 0; node < 2; node++) {
4413 switch (node) {
4414 case 1:
4415 tree_left =
4416 count[coef_count_node_start + 1];
4417 tree_right =
4418 count[coef_count_node_start + 2];
4419 break;
4420 default:
4421 tree_left =
4422 count[coef_count_node_start + 0];
4423 tree_right =
4424 count[coef_count_node_start + 1] +
4425 count[coef_count_node_start + 2];
4426 break;
4427
4428 }
4429
4430 vp9_tree_merge_probs(prev_prob, cur_prob,
4431 coef_node_start,
4432 tree_left, tree_right, tree_i, node);
4433
4434 coef_node_start = coef_node_start + 1;
4435 }
4436 coef_count_node_start = coef_count_node_start + 3;
4437 }
4438
4439 if (debug & VP9_DEBUG_MERGE)
4440 pr_info("# merge_vp9_mv_joint_tree\n");
4441 coef_node_start = VP9_MV_JOINTS_START;
4442 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4443 for (tree_i = 0; tree_i < 1; tree_i++) {
4444 for (node = 0; node < 3; node++) {
4445 switch (node) {
4446 case 2:
4447 tree_left =
4448 count[coef_count_node_start + 2];
4449 tree_right =
4450 count[coef_count_node_start + 3];
4451 break;
4452 case 1:
4453 tree_left =
4454 count[coef_count_node_start + 1];
4455 tree_right =
4456 count[coef_count_node_start + 2] +
4457 count[coef_count_node_start + 3];
4458 break;
4459 default:
4460 tree_left =
4461 count[coef_count_node_start + 0];
4462 tree_right =
4463 count[coef_count_node_start + 1] +
4464 count[coef_count_node_start + 2] +
4465 count[coef_count_node_start + 3];
4466 break;
4467 }
4468
4469 vp9_tree_merge_probs(prev_prob, cur_prob,
4470 coef_node_start,
4471 tree_left, tree_right, tree_i, node);
4472
4473 coef_node_start = coef_node_start + 1;
4474 }
4475 coef_count_node_start = coef_count_node_start + 4;
4476 }
4477
4478 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4479 if (debug & VP9_DEBUG_MERGE)
4480 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4481 coef_node_start =
4482 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4483 coef_count_node_start =
4484 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4485 : VP9_MV_CLASSES_0_COUNT_START;
4486 tree_i = 0;
4487 for (node = 0; node < 10; node++) {
4488 switch (node) {
4489 case 9:
4490 tree_left =
4491 count[coef_count_node_start + 9];
4492 tree_right =
4493 count[coef_count_node_start + 10];
4494 break;
4495 case 8:
4496 tree_left =
4497 count[coef_count_node_start + 7];
4498 tree_right =
4499 count[coef_count_node_start + 8];
4500 break;
4501 case 7:
4502 tree_left =
4503 count[coef_count_node_start + 7] +
4504 count[coef_count_node_start + 8];
4505 tree_right =
4506 count[coef_count_node_start + 9] +
4507 count[coef_count_node_start + 10];
4508 break;
4509 case 6:
4510 tree_left =
4511 count[coef_count_node_start + 6];
4512 tree_right =
4513 count[coef_count_node_start + 7] +
4514 count[coef_count_node_start + 8] +
4515 count[coef_count_node_start + 9] +
4516 count[coef_count_node_start + 10];
4517 break;
4518 case 5:
4519 tree_left =
4520 count[coef_count_node_start + 4];
4521 tree_right =
4522 count[coef_count_node_start + 5];
4523 break;
4524 case 4:
4525 tree_left =
4526 count[coef_count_node_start + 4] +
4527 count[coef_count_node_start + 5];
4528 tree_right =
4529 count[coef_count_node_start + 6] +
4530 count[coef_count_node_start + 7] +
4531 count[coef_count_node_start + 8] +
4532 count[coef_count_node_start + 9] +
4533 count[coef_count_node_start + 10];
4534 break;
4535 case 3:
4536 tree_left =
4537 count[coef_count_node_start + 2];
4538 tree_right =
4539 count[coef_count_node_start + 3];
4540 break;
4541 case 2:
4542 tree_left =
4543 count[coef_count_node_start + 2] +
4544 count[coef_count_node_start + 3];
4545 tree_right =
4546 count[coef_count_node_start + 4] +
4547 count[coef_count_node_start + 5] +
4548 count[coef_count_node_start + 6] +
4549 count[coef_count_node_start + 7] +
4550 count[coef_count_node_start + 8] +
4551 count[coef_count_node_start + 9] +
4552 count[coef_count_node_start + 10];
4553 break;
4554 case 1:
4555 tree_left =
4556 count[coef_count_node_start + 1];
4557 tree_right =
4558 count[coef_count_node_start + 2] +
4559 count[coef_count_node_start + 3] +
4560 count[coef_count_node_start + 4] +
4561 count[coef_count_node_start + 5] +
4562 count[coef_count_node_start + 6] +
4563 count[coef_count_node_start + 7] +
4564 count[coef_count_node_start + 8] +
4565 count[coef_count_node_start + 9] +
4566 count[coef_count_node_start + 10];
4567 break;
4568 default:
4569 tree_left =
4570 count[coef_count_node_start + 0];
4571 tree_right =
4572 count[coef_count_node_start + 1] +
4573 count[coef_count_node_start + 2] +
4574 count[coef_count_node_start + 3] +
4575 count[coef_count_node_start + 4] +
4576 count[coef_count_node_start + 5] +
4577 count[coef_count_node_start + 6] +
4578 count[coef_count_node_start + 7] +
4579 count[coef_count_node_start + 8] +
4580 count[coef_count_node_start + 9] +
4581 count[coef_count_node_start + 10];
4582 break;
4583
4584 }
4585
4586 vp9_tree_merge_probs(prev_prob, cur_prob,
4587 coef_node_start, tree_left, tree_right,
4588 tree_i, node);
4589
4590 coef_node_start = coef_node_start + 1;
4591 }
4592
4593 if (debug & VP9_DEBUG_MERGE)
4594 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4595 coef_node_start =
4596 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4597 coef_count_node_start =
4598 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4599 VP9_MV_CLASS0_0_COUNT_START;
4600 tree_i = 0;
4601 node = 0;
4602 tree_left = count[coef_count_node_start + 0];
4603 tree_right = count[coef_count_node_start + 1];
4604
4605 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4606 tree_left, tree_right, tree_i, node);
4607 if (debug & VP9_DEBUG_MERGE)
4608 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4609 mvd_i);
4610 coef_node_start =
4611 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4612 VP9_MV_CLASS0_FP_0_START;
4613 coef_count_node_start =
4614 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4615 VP9_MV_CLASS0_FP_0_COUNT_START;
4616 for (tree_i = 0; tree_i < 3; tree_i++) {
4617 for (node = 0; node < 3; node++) {
4618 switch (node) {
4619 case 2:
4620 tree_left =
4621 count[coef_count_node_start + 2];
4622 tree_right =
4623 count[coef_count_node_start + 3];
4624 break;
4625 case 1:
4626 tree_left =
4627 count[coef_count_node_start + 1];
4628 tree_right =
4629 count[coef_count_node_start + 2]
4630 + count[coef_count_node_start + 3];
4631 break;
4632 default:
4633 tree_left =
4634 count[coef_count_node_start + 0];
4635 tree_right =
4636 count[coef_count_node_start + 1]
4637 + count[coef_count_node_start + 2]
4638 + count[coef_count_node_start + 3];
4639 break;
4640
4641 }
4642
4643 vp9_tree_merge_probs(prev_prob, cur_prob,
4644 coef_node_start, tree_left, tree_right,
4645 tree_i, node);
4646
4647 coef_node_start = coef_node_start + 1;
4648 }
4649 coef_count_node_start = coef_count_node_start + 4;
4650 }
4651
4652 } /* for mvd_i (mvd_y or mvd_x)*/
4653}
4654
4655}
4656
4657static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4658{
4659 int i;
4660 struct VP9_Common_s *const cm = &pbi->common;
4661 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4662
4663 for (i = 0; i < pbi->used_buf_num; ++i) {
4664 if (frame_bufs[i].buf.vframe_bound)
4665 return true;
4666 }
4667
4668 return false;
4669}
4670
4671static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4672{
4673 struct VP9_Common_s *const cm = &pbi->common;
4674 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4675 int i;
4676
4677 /* release workspace */
4678 if (pbi->bmmu_box)
4679 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4680 WORK_SPACE_BUF_ID);
4681 /*
4682 * it's only when vframe get back to driver, right now we can be sure
4683 * that vframe and fd are related. if the playback exits, the capture
4684 * requires the upper app to release when the fd is closed, and others
4685 * buffers drivers are released by driver.
4686 */
4687 for (i = 0; i < pbi->used_buf_num; ++i) {
4688 if (!frame_bufs[i].buf.vframe_bound) {
4689 if (pbi->bmmu_box)
4690 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4691 HEADER_BUFFER_IDX(i));
4692 if (pbi->mmu_box)
4693 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4694
4695 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4696 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4697 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4698 }
4699 }
4700}
4701
4702static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4703{
4704#ifndef MV_USE_FIXED_BUF
4705 dealloc_mv_bufs(pbi);
4706#endif
4707 if (pbi->is_used_v4l &&
4708 v4l_is_there_vframe_bound(pbi)) {
4709 if (get_double_write_mode(pbi) != 0x10) {
4710 v4l_mmu_buffer_release(pbi);
4711 return;
4712 }
4713 }
4714
4715 if (pbi->mmu_box)
4716 decoder_mmu_box_free(pbi->mmu_box);
4717 pbi->mmu_box = NULL;
4718
4719 if (pbi->bmmu_box)
4720 decoder_bmmu_box_free(pbi->bmmu_box);
4721 pbi->bmmu_box = NULL;
4722}
4723
4724static int calc_luc_quantity(u32 w, u32 h)
4725{
4726 int lcu_size = 64; /*fixed 64*/
4727 int pic_width_64 = (w + 63) & (~0x3f);
4728 int pic_height_32 = (h + 31) & (~0x1f);
4729 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4730 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4731 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4732 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4733
4734 return pic_width_lcu * pic_height_lcu;
4735}
4736
4737static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4738 struct PIC_BUFFER_CONFIG_s *pic)
4739{
4740 int ret = -1;
4741 int i = pic->index;
4742 int dw_mode = get_double_write_mode_init(pbi);
4743 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4744#ifdef MV_USE_FIXED_BUF
4745 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4746 pbi->work_space_buf->mpred_mv.buf_size;
4747#endif
4748 struct vdec_v4l2_buffer *fb = NULL;
4749
4750 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4751 if (ret < 0) {
4752 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4753 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4754 return ret;
4755 }
4756
4757 if (pbi->mmu_enable) {
4758 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4759 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4760 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4761 pr_info("MMU header_adr %d: %ld\n",
4762 i, pbi->m_BUF[i].header_addr);
4763 }
4764 }
4765
4766#ifdef MV_USE_FIXED_BUF
4767 if ((pbi->work_space_buf->mpred_mv.buf_start +
4768 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4769 <= mpred_mv_end) {
4770#endif
4771 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4772 pic->cma_alloc_addr = fb->m.mem[0].addr;
4773 if (fb->num_planes == 1) {
4774 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4775 pbi->m_BUF[i].size = fb->m.mem[0].size;
4776 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4777 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4778 } else if (fb->num_planes == 2) {
4779 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4780 pbi->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
4781 pbi->m_BUF[i].luma_size = fb->m.mem[0].size;
4782 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4783 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4784 }
4785
4786 /* config frame buffer */
4787 if (pbi->mmu_enable)
4788 pic->header_adr = pbi->m_BUF[i].header_addr;
4789
4790 pic->BUF_index = i;
4791 pic->lcu_total = lcu_total;
4792 pic->mc_canvas_y = pic->index;
4793 pic->mc_canvas_u_v = pic->index;
4794
4795 if (dw_mode & 0x10) {
4796 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4797 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4798 pic->mc_canvas_y = (pic->index << 1);
4799 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4800 } else if (dw_mode) {
4801 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4802 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4803 }
4804
4805#ifdef MV_USE_FIXED_BUF
4806 pic->mpred_mv_wr_start_addr =
4807 pbi->work_space_buf->mpred_mv.buf_start +
4808 ((pic->index * lcu_total) * MV_MEM_UNIT);
4809#endif
4810 if (debug) {
4811 pr_info("%s index %d BUF_index %d ",
4812 __func__, pic->index,
4813 pic->BUF_index);
4814 pr_info("comp_body_size %x comp_buf_size %x ",
4815 pic->comp_body_size,
4816 pic->buf_size);
4817 pr_info("mpred_mv_wr_start_adr %ld\n",
4818 pic->mpred_mv_wr_start_addr);
4819 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4820 pic->dw_y_adr,
4821 pic->dw_u_v_adr);
4822 }
4823#ifdef MV_USE_FIXED_BUF
4824 }
4825#endif
4826 return ret;
4827}
4828
4829static int config_pic(struct VP9Decoder_s *pbi,
4830 struct PIC_BUFFER_CONFIG_s *pic_config)
4831{
4832 int ret = -1;
4833 int i;
4834 int pic_width = pbi->init_pic_w;
4835 int pic_height = pbi->init_pic_h;
4836 int lcu_size = 64; /*fixed 64*/
4837 int pic_width_64 = (pic_width + 63) & (~0x3f);
4838 int pic_height_32 = (pic_height + 31) & (~0x1f);
4839 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4840 pic_width_64 / lcu_size + 1
4841 : pic_width_64 / lcu_size;
4842 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4843 pic_height_32 / lcu_size + 1
4844 : pic_height_32 / lcu_size;
4845 int lcu_total = pic_width_lcu * pic_height_lcu;
4846#ifdef MV_USE_FIXED_BUF
4847 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4848 pbi->work_space_buf->mpred_mv.buf_size;
4849#endif
4850 u32 y_adr = 0;
4851 int buf_size = 0;
4852
4853 int losless_comp_header_size =
4854 compute_losless_comp_header_size(pic_width,
4855 pic_height);
4856 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4857 pic_height, buf_alloc_depth == 10);
4858 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4859 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4860 int mc_buffer_size_u_v = 0;
4861 int mc_buffer_size_u_v_h = 0;
4862 int dw_mode = get_double_write_mode_init(pbi);
4863
4864 pbi->lcu_total = lcu_total;
4865
4866 if (dw_mode) {
4867 int pic_width_dw = pic_width /
4868 get_double_write_ratio(pbi, dw_mode);
4869 int pic_height_dw = pic_height /
4870 get_double_write_ratio(pbi, dw_mode);
4871
4872 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4873 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4874 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4875 pic_width_64_dw / lcu_size + 1
4876 : pic_width_64_dw / lcu_size;
4877 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4878 pic_height_32_dw / lcu_size + 1
4879 : pic_height_32_dw / lcu_size;
4880 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4881 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4882 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4883 /*64k alignment*/
4884 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4885 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4886 }
4887
4888 if (mc_buffer_size & 0xffff) /*64k alignment*/
4889 mc_buffer_size_h += 1;
4890 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4891 buf_size += (mc_buffer_size_h << 16);
4892
4893 if (pbi->mmu_enable) {
4894 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4895 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4896
4897 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4898 pr_info("MMU header_adr %d: %ld\n",
4899 pic_config->index, pic_config->header_adr);
4900 }
4901 }
4902
4903 i = pic_config->index;
4904#ifdef MV_USE_FIXED_BUF
4905 if ((pbi->work_space_buf->mpred_mv.buf_start +
4906 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4907 <= mpred_mv_end
4908 ) {
4909#endif
4910 if (buf_size > 0) {
4911 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4912 VF_BUFFER_IDX(i),
4913 buf_size, DRIVER_NAME,
4914 &pic_config->cma_alloc_addr);
4915 if (ret < 0) {
4916 pr_info(
4917 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4918 VF_BUFFER_IDX(i),
4919 buf_size
4920 );
4921 return ret;
4922 }
4923
4924 if (pic_config->cma_alloc_addr)
4925 y_adr = pic_config->cma_alloc_addr;
4926 else {
4927 pr_info(
4928 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4929 VF_BUFFER_IDX(i),
4930 buf_size
4931 );
4932 return -1;
4933 }
4934 }
4935 {
4936 /*ensure get_pic_by_POC()
4937 not get the buffer not decoded*/
4938 pic_config->BUF_index = i;
4939 pic_config->lcu_total = lcu_total;
4940
4941 pic_config->comp_body_size = losless_comp_body_size;
4942 pic_config->buf_size = buf_size;
4943
4944 pic_config->mc_canvas_y = pic_config->index;
4945 pic_config->mc_canvas_u_v = pic_config->index;
4946 if (dw_mode & 0x10) {
4947 pic_config->dw_y_adr = y_adr;
4948 pic_config->dw_u_v_adr = y_adr +
4949 ((mc_buffer_size_u_v_h << 16) << 1);
4950
4951 pic_config->mc_canvas_y =
4952 (pic_config->index << 1);
4953 pic_config->mc_canvas_u_v =
4954 (pic_config->index << 1) + 1;
4955 } else if (dw_mode) {
4956 pic_config->dw_y_adr = y_adr;
4957 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4958 ((mc_buffer_size_u_v_h << 16) << 1);
4959 }
4960#ifdef MV_USE_FIXED_BUF
4961 pic_config->mpred_mv_wr_start_addr =
4962 pbi->work_space_buf->mpred_mv.buf_start +
4963 ((pic_config->index * lcu_total)
4964 * MV_MEM_UNIT);
4965#endif
4966 if (debug) {
4967 pr_info
4968 ("%s index %d BUF_index %d ",
4969 __func__, pic_config->index,
4970 pic_config->BUF_index);
4971 pr_info
4972 ("comp_body_size %x comp_buf_size %x ",
4973 pic_config->comp_body_size,
4974 pic_config->buf_size);
4975 pr_info
4976 ("mpred_mv_wr_start_adr %ld\n",
4977 pic_config->mpred_mv_wr_start_addr);
4978 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4979 pic_config->dw_y_adr,
4980 pic_config->dw_u_v_adr);
4981 }
4982 ret = 0;
4983 }
4984#ifdef MV_USE_FIXED_BUF
4985 }
4986#endif
4987 return ret;
4988}
4989
4990static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
4991{
4992 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
4993 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
4994 return (MMU_COMPRESS_8K_HEADER_SIZE);
4995
4996 return (MMU_COMPRESS_HEADER_SIZE);
4997}
4998
4999/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5000static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5001{
5002 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5003 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5004 return (MAX_FRAME_8K_NUM * 4);
5005
5006 return (MAX_FRAME_4K_NUM * 4);
5007}
5008
5009static void init_pic_list(struct VP9Decoder_s *pbi)
5010{
5011 int i;
5012 struct VP9_Common_s *cm = &pbi->common;
5013 struct PIC_BUFFER_CONFIG_s *pic_config;
5014 u32 header_size;
5015 struct vdec_s *vdec = hw_to_vdec(pbi);
5016
5017 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5018 header_size = vvp9_mmu_compress_header_size(pbi);
5019 /*alloc VP9 compress header first*/
5020 for (i = 0; i < pbi->used_buf_num; i++) {
5021 unsigned long buf_addr;
5022 if (decoder_bmmu_box_alloc_buf_phy
5023 (pbi->bmmu_box,
5024 HEADER_BUFFER_IDX(i), header_size,
5025 DRIVER_HEADER_NAME,
5026 &buf_addr) < 0) {
5027 pr_info("%s malloc compress header failed %d\n",
5028 DRIVER_HEADER_NAME, i);
5029 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5030 return;
5031 }
5032 }
5033 }
5034 for (i = 0; i < pbi->used_buf_num; i++) {
5035 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5036 pic_config->index = i;
5037 pic_config->BUF_index = -1;
5038 pic_config->mv_buf_index = -1;
5039 if (vdec->parallel_dec == 1) {
5040 pic_config->y_canvas_index = -1;
5041 pic_config->uv_canvas_index = -1;
5042 }
5043 pic_config->y_crop_width = pbi->init_pic_w;
5044 pic_config->y_crop_height = pbi->init_pic_h;
5045 pic_config->double_write_mode = get_double_write_mode(pbi);
5046
5047 if (!pbi->is_used_v4l) {
5048 if (config_pic(pbi, pic_config) < 0) {
5049 if (debug)
5050 pr_info("Config_pic %d fail\n",
5051 pic_config->index);
5052 pic_config->index = -1;
5053 break;
5054 }
5055
5056 if (pic_config->double_write_mode) {
5057 set_canvas(pbi, pic_config);
5058 }
5059 }
5060 }
5061 for (; i < pbi->used_buf_num; i++) {
5062 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5063 pic_config->index = -1;
5064 pic_config->BUF_index = -1;
5065 pic_config->mv_buf_index = -1;
5066 if (vdec->parallel_dec == 1) {
5067 pic_config->y_canvas_index = -1;
5068 pic_config->uv_canvas_index = -1;
5069 }
5070 }
5071 pr_info("%s ok, used_buf_num = %d\n",
5072 __func__, pbi->used_buf_num);
5073}
5074
5075static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5076{
5077 int i;
5078 struct VP9_Common_s *cm = &pbi->common;
5079 struct PIC_BUFFER_CONFIG_s *pic_config;
5080 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5081 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5082 (0x1 << 1) | (0x1 << 2));
5083
5084
5085 for (i = 0; i < pbi->used_buf_num; i++) {
5086 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5087 if (pic_config->index < 0)
5088 break;
5089
5090 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5091
5092 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5093 pic_config->header_adr >> 5);
5094 } else {
5095 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5096 * pic_config->mc_y_adr
5097 * | (pic_config->mc_canvas_y << 8) | 0x1);
5098 */
5099 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5100 pic_config->dw_y_adr >> 5);
5101 }
5102#ifndef LOSLESS_COMPRESS_MODE
5103 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5104 * pic_config->mc_u_v_adr
5105 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5106 */
5107 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5108 pic_config->header_adr >> 5);
5109#else
5110 if (pic_config->double_write_mode & 0x10) {
5111 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5112 pic_config->dw_u_v_adr >> 5);
5113 }
5114#endif
5115 }
5116 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5117
5118 /*Zero out canvas registers in IPP -- avoid simulation X*/
5119 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5120 (0 << 8) | (0 << 1) | 1);
5121 for (i = 0; i < 32; i++)
5122 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5123}
5124
5125
5126static void dump_pic_list(struct VP9Decoder_s *pbi)
5127{
5128 struct VP9_Common_s *const cm = &pbi->common;
5129 struct PIC_BUFFER_CONFIG_s *pic_config;
5130 int i;
5131 for (i = 0; i < FRAME_BUFFERS; i++) {
5132 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5133 vp9_print(pbi, 0,
5134 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5135 i,
5136 pic_config->index,
5137#ifndef MV_USE_FIXED_BUF
5138 pic_config->mv_buf_index,
5139#else
5140 -1,
5141#endif
5142 cm->buffer_pool->
5143 frame_bufs[i].ref_count,
5144 pic_config->vf_ref,
5145 pic_config->decode_idx,
5146 pic_config->slice_type,
5147 pic_config->y_crop_width,
5148 pic_config->y_crop_height,
5149 pic_config->cma_alloc_addr
5150 );
5151 }
5152 return;
5153}
5154
5155static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5156{
5157#ifdef LOSLESS_COMPRESS_MODE
5158 unsigned int data32;
5159#endif
5160 int losless_comp_header_size, losless_comp_body_size;
5161 struct VP9_Common_s *cm = &pbi->common;
5162 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5163
5164 frame_width = cur_pic_config->y_crop_width;
5165 frame_height = cur_pic_config->y_crop_height;
5166 cur_pic_config->bit_depth = bit_depth;
5167 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5168 losless_comp_header_size =
5169 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5170 cur_pic_config->y_crop_height);
5171 losless_comp_body_size =
5172 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5173 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5174 cur_pic_config->comp_body_size = losless_comp_body_size;
5175#ifdef LOSLESS_COMPRESS_MODE
5176 data32 = READ_VREG(HEVC_SAO_CTRL5);
5177 if (bit_depth == VPX_BITS_10)
5178 data32 &= ~(1 << 9);
5179 else
5180 data32 |= (1 << 9);
5181
5182 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5183
5184 if (pbi->mmu_enable) {
5185 /*bit[4] : paged_mem_mode*/
5186 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5187 } else {
5188 /*bit[3] smem mdoe*/
5189 if (bit_depth == VPX_BITS_10)
5190 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5191 else
5192 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5193 }
5194 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5195 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5196 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5197 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5198 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5199 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5200 if (get_double_write_mode(pbi) & 0x10)
5201 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5202#else
5203 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5204#endif
5205 return 0;
5206}
5207
5208static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5209{
5210 int i;
5211 struct VP9_Common_s *cm = &pbi->common;
5212 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5213 uint8_t scale_enable = 0;
5214
5215 if (debug&VP9_DEBUG_BUFMGR_MORE)
5216 pr_info("config_mc_buffer entered .....\n");
5217
5218 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5219 (0 << 8) | (0 << 1) | 1);
5220 for (i = 0; i < REFS_PER_FRAME; ++i) {
5221 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5222 if (!pic_config)
5223 continue;
5224 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5225 (pic_config->mc_canvas_u_v << 16)
5226 | (pic_config->mc_canvas_u_v << 8)
5227 | pic_config->mc_canvas_y);
5228 if (debug & VP9_DEBUG_BUFMGR_MORE)
5229 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5230 i, pic_config->mc_canvas_u_v,
5231 pic_config->mc_canvas_y);
5232 }
5233 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5234 (16 << 8) | (0 << 1) | 1);
5235 for (i = 0; i < REFS_PER_FRAME; ++i) {
5236 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5237 if (!pic_config)
5238 continue;
5239 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5240 (pic_config->mc_canvas_u_v << 16)
5241 | (pic_config->mc_canvas_u_v << 8)
5242 | pic_config->mc_canvas_y);
5243 }
5244
5245 /*auto_inc start index:0 field:0*/
5246 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5247 /*index 0:last 1:golden 2:altref*/
5248 for (i = 0; i < REFS_PER_FRAME; i++) {
5249 int ref_pic_body_size;
5250 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5251 if (!pic_config)
5252 continue;
5253 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5254 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5255
5256 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5257 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5258 scale_enable |= (1 << i);
5259 }
5260 ref_pic_body_size =
5261 compute_losless_comp_body_size(pic_config->y_crop_width,
5262 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5263 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5264 (pic_config->y_crop_width << 14)
5265 / cur_pic_config->y_crop_width);
5266 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5267 (pic_config->y_crop_height << 14)
5268 / cur_pic_config->y_crop_height);
5269 if (pbi->mmu_enable)
5270 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5271 else
5272 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5273 }
5274 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5275 return 0;
5276}
5277
5278static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5279{
5280 unsigned int data32;
5281
5282 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5283 data32 &= (~(1 << 6));
5284 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5285}
5286
5287static void config_mpred_hw(struct VP9Decoder_s *pbi)
5288{
5289 struct VP9_Common_s *cm = &pbi->common;
5290 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5291 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5292 &cm->prev_frame->buf;
5293
5294 unsigned int data32;
5295 int mpred_curr_lcu_x;
5296 int mpred_curr_lcu_y;
5297 int mpred_mv_rd_end_addr;
5298
5299
5300 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5301 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5302
5303 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5304 mpred_curr_lcu_x = data32 & 0xffff;
5305 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5306
5307 if (debug & VP9_DEBUG_BUFMGR)
5308 pr_info("cur pic_config index %d col pic_config index %d\n",
5309 cur_pic_config->index, last_frame_pic_config->index);
5310 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5311 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5312 pbi->work_space_buf->mpred_above.buf_start);
5313
5314 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5315
5316 data32 &= (~(1 << 6));
5317 data32 |= (cm->use_prev_frame_mvs << 6);
5318 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5319
5320 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5321 cur_pic_config->mpred_mv_wr_start_addr);
5322 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5323
5324 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5325 last_frame_pic_config->mpred_mv_wr_start_addr);
5326 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5327 last_frame_pic_config->mpred_mv_wr_start_addr);
5328 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5329 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5330 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5331 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5332
5333}
5334
5335static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5336{
5337 struct VP9_Common_s *cm = &pbi->common;
5338 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5339
5340 unsigned int data32;
5341 int lcu_size = 64;
5342 int mc_buffer_size_u_v =
5343 pic_config->lcu_total * lcu_size*lcu_size/2;
5344 int mc_buffer_size_u_v_h =
5345 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5346 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5347
5348 if (get_double_write_mode(pbi)) {
5349 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5350 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5351 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5352 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5353 } else {
5354 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5355 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5356 }
5357 if (pbi->mmu_enable)
5358 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5359
5360 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5361 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5362 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5363 */
5364 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5365
5366 data32 = (mc_buffer_size_u_v_h << 16);
5367 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5368
5369#ifdef VP9_10B_NV21
5370#ifdef DOS_PROJECT
5371 data32 = READ_VREG(HEVC_SAO_CTRL1);
5372 data32 &= (~0x3000);
5373 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5374 data32 |= (pbi->mem_map_mode << 12);
5375 data32 &= (~0x3);
5376 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5377 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5378 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5379 * [17:16] dw_h0_ctrl
5380 */
5381 data32 = READ_VREG(HEVC_SAO_CTRL5);
5382 /*set them all 0 for H265_NV21 (no down-scale)*/
5383 data32 &= ~(0xff << 16);
5384 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5385 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5386 data32 &= (~0x30);
5387 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5388 data32 |= (pbi->mem_map_mode << 4);
5389 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5390#else
5391 /*m8baby test1902*/
5392 data32 = READ_VREG(HEVC_SAO_CTRL1);
5393 data32 &= (~0x3000);
5394 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5395 data32 |= (pbi->mem_map_mode << 12);
5396 data32 &= (~0xff0);
5397 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5398 data32 |= 0x880; /*.Big-Endian per 64-bit */
5399 data32 &= (~0x3);
5400 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5401 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5402 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5403 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5404 */
5405 data32 = READ_VREG(HEVC_SAO_CTRL5);
5406 /* set them all 0 for H265_NV21 (no down-scale)*/
5407 data32 &= ~(0xff << 16);
5408 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5409
5410 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5411 data32 &= (~0x30);
5412 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5413 data32 |= (pbi->mem_map_mode << 4);
5414 data32 &= (~0xF);
5415 data32 |= 0x8; /*Big-Endian per 64-bit*/
5416 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5417#endif
5418#else
5419 data32 = READ_VREG(HEVC_SAO_CTRL1);
5420 data32 &= (~0x3000);
5421 data32 |= (pbi->mem_map_mode <<
5422 12);
5423
5424/* [13:12] axi_aformat, 0-Linear,
5425 * 1-32x32, 2-64x32
5426 */
5427 data32 &= (~0xff0);
5428 /* data32 |= 0x670; // Big-Endian per 64-bit */
5429 data32 |= endian; /* Big-Endian per 64-bit */
5430 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5431 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5432 if (get_double_write_mode(pbi) == 0)
5433 data32 |= 0x2; /*disable double write*/
5434 else if (get_double_write_mode(pbi) & 0x10)
5435 data32 |= 0x1; /*disable cm*/
5436 } else { /* >= G12A dw write control */
5437 unsigned int data;
5438 data = READ_VREG(HEVC_DBLK_CFGB);
5439 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5440 if (get_double_write_mode(pbi) == 0)
5441 data |= (0x1 << 8); /*enable first write*/
5442 else if (get_double_write_mode(pbi) & 0x10)
5443 data |= (0x1 << 9); /*double write only*/
5444 else
5445 data |= ((0x1 << 8) |(0x1 << 9));
5446 WRITE_VREG(HEVC_DBLK_CFGB, data);
5447 }
5448
5449 /* swap uv */
5450 if (pbi->is_used_v4l) {
5451 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5452 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5453 data32 &= ~(1 << 8); /* NV21 */
5454 else
5455 data32 |= (1 << 8); /* NV12 */
5456 }
5457
5458 /*
5459 * [31:24] ar_fifo1_axi_thred
5460 * [23:16] ar_fifo0_axi_thred
5461 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5462 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5463 * [11:08] axi_lendian_C
5464 * [07:04] axi_lendian_Y
5465 * [3] reserved
5466 * [2] clk_forceon
5467 * [1] dw_disable:disable double write output
5468 * [0] cm_disable:disable compress output
5469 */
5470 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5471
5472 if (get_double_write_mode(pbi) & 0x10) {
5473 /* [23:22] dw_v1_ctrl
5474 *[21:20] dw_v0_ctrl
5475 *[19:18] dw_h1_ctrl
5476 *[17:16] dw_h0_ctrl
5477 */
5478 data32 = READ_VREG(HEVC_SAO_CTRL5);
5479 /*set them all 0 for H265_NV21 (no down-scale)*/
5480 data32 &= ~(0xff << 16);
5481 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5482 } else {
5483 data32 = READ_VREG(HEVC_SAO_CTRL5);
5484 data32 &= (~(0xff << 16));
5485 if (get_double_write_mode(pbi) == 2 ||
5486 get_double_write_mode(pbi) == 3)
5487 data32 |= (0xff<<16);
5488 else if (get_double_write_mode(pbi) == 4)
5489 data32 |= (0x33<<16);
5490 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5491 }
5492
5493 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5494 data32 &= (~0x30);
5495 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5496 data32 |= (pbi->mem_map_mode <<
5497 4);
5498 data32 &= (~0xF);
5499 data32 |= 0xf; /* valid only when double write only */
5500 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5501
5502 /* swap uv */
5503 if (pbi->is_used_v4l) {
5504 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5505 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5506 data32 |= (1 << 12); /* NV21 */
5507 else
5508 data32 &= ~(1 << 12); /* NV12 */
5509 }
5510
5511 /*
5512 * [3:0] little_endian
5513 * [5:4] address_format 00:linear 01:32x32 10:64x32
5514 * [7:6] reserved
5515 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5516 * [11:10] reserved
5517 * [12] CbCr_byte_swap
5518 * [31:13] reserved
5519 */
5520 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5521#endif
5522}
5523
5524static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5525{
5526 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5527 unsigned int data32;
5528
5529 if (debug && pbi->init_flag == 0)
5530 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5531 __func__,
5532 buf_spec->ipp.buf_start,
5533 buf_spec->start_adr,
5534 buf_spec->short_term_rps.buf_start,
5535 buf_spec->vps.buf_start,
5536 buf_spec->sps.buf_start,
5537 buf_spec->pps.buf_start,
5538 buf_spec->sao_up.buf_start,
5539 buf_spec->swap_buf.buf_start,
5540 buf_spec->swap_buf2.buf_start,
5541 buf_spec->scalelut.buf_start,
5542 buf_spec->dblk_para.buf_start,
5543 buf_spec->dblk_data.buf_start);
5544
5545 if (mask & HW_MASK_FRONT) {
5546 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5547 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5548
5549 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5550 buf_spec->short_term_rps.buf_start);
5551 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5552 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5553 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5554 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5555 buf_spec->swap_buf.buf_start);
5556 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5557 buf_spec->swap_buf2.buf_start);
5558 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5559
5560 }
5561
5562 if (mask & HW_MASK_BACK) {
5563#ifdef LOSLESS_COMPRESS_MODE
5564 int losless_comp_header_size =
5565 compute_losless_comp_header_size(pbi->init_pic_w,
5566 pbi->init_pic_h);
5567 int losless_comp_body_size =
5568 compute_losless_comp_body_size(pbi->init_pic_w,
5569 pbi->init_pic_h, buf_alloc_depth == 10);
5570#endif
5571 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5572 buf_spec->ipp.buf_start);
5573 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5574 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5575 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5576 /* cfg_addr_adp*/
5577 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5578 if (debug & VP9_DEBUG_BUFMGR_MORE)
5579 pr_info("Write HEVC_DBLK_CFGE\n");
5580 }
5581 /* cfg_p_addr */
5582 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5583 /* cfg_d_addr */
5584 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5585
5586 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5587 /*
5588 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5589 * data32 = data32 * 2;
5590 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5591 * data32 = data32 * 2;
5592 */
5593 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5594 }
5595#ifdef LOSLESS_COMPRESS_MODE
5596 if (pbi->mmu_enable) {
5597 /*bit[4] : paged_mem_mode*/
5598 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5599 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5600 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5601 } else {
5602 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5603 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5604 */
5605 /*bit[3] smem mdoe*/
5606 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5607 /*bit[3] smem mdoe*/
5608 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5609 (losless_comp_body_size >> 5));
5610 }
5611 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5612 (losless_comp_body_size >> 5));*/
5613 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5614 (0xff<<20) | (0xff<<10) | 0xff);*/
5615 /*8-bit mode */
5616 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5617 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5618 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5619 if (get_double_write_mode(pbi) & 0x10)
5620 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5621#else
5622 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5623#endif
5624
5625 if (pbi->mmu_enable) {
5626 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5627 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5628 + buf_spec->mmu_vbh.buf_size/2);
5629 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5630 /*data32 |= 0x1;*/
5631 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5632
5633 /* use HEVC_CM_HEADER_START_ADDR */
5634 data32 = READ_VREG(HEVC_SAO_CTRL5);
5635 data32 |= (1<<10);
5636 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5637 }
5638
5639 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5640
5641 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5642 /**/
5643 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5644 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5645 if (pbi->mmu_enable) {
5646 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5647 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5648 else
5649 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5650 }
5651 }
5652}
5653
5654
5655#ifdef VP9_LPF_LVL_UPDATE
5656/*
5657 * Defines, declarations, sub-functions for vp9 de-block loop
5658 filter Thr/Lvl table update
5659 * - struct segmentation is for loop filter only (removed something)
5660 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5661 be instantiated in C_Entry
5662 * - vp9_loop_filter_init run once before decoding start
5663 * - vp9_loop_filter_frame_init run before every frame decoding start
5664 * - set video format to VP9 is in vp9_loop_filter_init
5665 */
5666#define MAX_LOOP_FILTER 63
5667#define MAX_REF_LF_DELTAS 4
5668#define MAX_MODE_LF_DELTAS 2
5669/*#define INTRA_FRAME 0*/
5670/*#define LAST_FRAME 1*/
5671/*#define MAX_REF_FRAMES 4*/
5672#define SEGMENT_DELTADATA 0
5673#define SEGMENT_ABSDATA 1
5674#define MAX_SEGMENTS 8
5675/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5676/*no use for loop filter, if this struct for common use, pls add it back*/
5677/*#define PREDICTION_PROBS 3*/
5678/* no use for loop filter, if this struct for common use, pls add it back*/
5679
5680enum SEG_LVL_FEATURES {
5681 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5682 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5683 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5684 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5685 SEG_LVL_MAX = 4 /*Number of features supported*/
5686};
5687
5688struct segmentation {
5689 uint8_t enabled;
5690 uint8_t update_map;
5691 uint8_t update_data;
5692 uint8_t abs_delta;
5693 uint8_t temporal_update;
5694
5695 /*no use for loop filter, if this struct
5696 *for common use, pls add it back
5697 */
5698 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5699 /* no use for loop filter, if this struct
5700 * for common use, pls add it back
5701 */
5702 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5703
5704 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5705 unsigned int feature_mask[MAX_SEGMENTS];
5706};
5707
5708struct loop_filter_thresh {
5709 uint8_t mblim;
5710 uint8_t lim;
5711 uint8_t hev_thr;
5712};
5713
5714struct loop_filter_info_n {
5715 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5716 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5717};
5718
5719struct loopfilter {
5720 int filter_level;
5721
5722 int sharpness_level;
5723 int last_sharpness_level;
5724
5725 uint8_t mode_ref_delta_enabled;
5726 uint8_t mode_ref_delta_update;
5727
5728 /*0 = Intra, Last, GF, ARF*/
5729 signed char ref_deltas[MAX_REF_LF_DELTAS];
5730 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5731
5732 /*0 = ZERO_MV, MV*/
5733 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5734 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5735};
5736
5737static int vp9_clamp(int value, int low, int high)
5738{
5739 return value < low ? low : (value > high ? high : value);
5740}
5741
5742int segfeature_active(struct segmentation *seg,
5743 int segment_id,
5744 enum SEG_LVL_FEATURES feature_id) {
5745 return seg->enabled &&
5746 (seg->feature_mask[segment_id] & (1 << feature_id));
5747}
5748
5749int get_segdata(struct segmentation *seg, int segment_id,
5750 enum SEG_LVL_FEATURES feature_id) {
5751 return seg->feature_data[segment_id][feature_id];
5752}
5753
5754static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5755 int sharpness_lvl)
5756{
5757 int lvl;
5758 /*For each possible value for the loop filter fill out limits*/
5759 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5760 /*Set loop filter parameters that control sharpness.*/
5761 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5762 (sharpness_lvl > 4));
5763
5764 if (sharpness_lvl > 0) {
5765 if (block_inside_limit > (9 - sharpness_lvl))
5766 block_inside_limit = (9 - sharpness_lvl);
5767 }
5768
5769 if (block_inside_limit < 1)
5770 block_inside_limit = 1;
5771
5772 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5773 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5774 block_inside_limit);
5775 }
5776}
5777
5778/*instantiate this function once when decode is started*/
5779void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5780{
5781 struct loop_filter_info_n *lfi = pbi->lfi;
5782 struct loopfilter *lf = pbi->lf;
5783 struct segmentation *seg_4lf = pbi->seg_4lf;
5784 int i;
5785 unsigned int data32;
5786
5787 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5788 memset(lf, 0, sizeof(struct loopfilter));
5789 memset(seg_4lf, 0, sizeof(struct segmentation));
5790 lf->sharpness_level = 0; /*init to 0 */
5791 /*init limits for given sharpness*/
5792 vp9_update_sharpness(lfi, lf->sharpness_level);
5793 lf->last_sharpness_level = lf->sharpness_level;
5794 /*init hev threshold const vectors (actually no use)
5795 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5796 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5797 */
5798
5799 /*Write to register*/
5800 for (i = 0; i < 32; i++) {
5801 unsigned int thr;
5802
5803 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5804 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5805 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5806 (lfi->lfthr[i * 2].mblim & 0xff);
5807 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5808 }
5809
5810 /*video format is VP9*/
5811 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5812 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5813 (0x3 << 12) | // (dw fifo thres r or b)
5814 (0x3 << 10) | // (dw fifo thres not r/b)
5815 (0x3 << 8) | // 1st/2nd write both enable
5816 (0x1 << 0); // vp9 video format
5817 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5818 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5819 (0x1 << 0); /*vp9 video format*/
5820 } else
5821 data32 = 0x40400001;
5822
5823 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5824 if (debug & VP9_DEBUG_BUFMGR_MORE)
5825 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5826}
5827 /* perform this function per frame*/
5828void vp9_loop_filter_frame_init(struct segmentation *seg,
5829 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5830 int default_filt_lvl) {
5831 int i;
5832 int seg_id;
5833 /*n_shift is the multiplier for lf_deltas
5834 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5835 *2 when filter_lvl is between 32 and 63
5836 */
5837 const int scale = 1 << (default_filt_lvl >> 5);
5838
5839 /*update limits if sharpness has changed*/
5840 if (lf->last_sharpness_level != lf->sharpness_level) {
5841 vp9_update_sharpness(lfi, lf->sharpness_level);
5842 lf->last_sharpness_level = lf->sharpness_level;
5843
5844 /*Write to register*/
5845 for (i = 0; i < 32; i++) {
5846 unsigned int thr;
5847
5848 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5849 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5850 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5851 | (lfi->lfthr[i * 2].mblim & 0xff);
5852 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5853 }
5854 }
5855
5856 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5857 int lvl_seg = default_filt_lvl;
5858
5859 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5860 const int data = get_segdata(seg, seg_id,
5861 SEG_LVL_ALT_LF);
5862 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5863 data : default_filt_lvl + data,
5864 0, MAX_LOOP_FILTER);
5865#ifdef DBG_LF_PRINT
5866 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5867#endif
5868 }
5869
5870 if (!lf->mode_ref_delta_enabled) {
5871 /*we could get rid of this if we assume that deltas are set to
5872 *zero when not in use; encoder always uses deltas
5873 */
5874 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5875 } else {
5876 int ref, mode;
5877 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5878 * scale;
5879#ifdef DBG_LF_PRINT
5880 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5881 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5882#endif
5883 lfi->lvl[seg_id][INTRA_FRAME][0] =
5884 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5885
5886 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5887 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5888 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5889 /*MAX_MODE_LF_DELTAS = 2*/
5890 const int inter_lvl =
5891 lvl_seg + lf->ref_deltas[ref] * scale
5892 + lf->mode_deltas[mode] * scale;
5893#ifdef DBG_LF_PRINT
5894#endif
5895 lfi->lvl[seg_id][ref][mode] =
5896 vp9_clamp(inter_lvl, 0,
5897 MAX_LOOP_FILTER);
5898 }
5899 }
5900 }
5901 }
5902
5903#ifdef DBG_LF_PRINT
5904 /*print out thr/lvl table per frame*/
5905 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5906 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5907 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5908 lfi->lfthr[i].lim);
5909 }
5910 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5911 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5912 seg_id, lfi->lvl[seg_id][0][0],
5913 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5914 lfi->lvl[seg_id][3][0]);
5915 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5916 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5917 lfi->lvl[seg_id][3][1]);
5918 }
5919#endif
5920
5921 /*Write to register */
5922 for (i = 0; i < 16; i++) {
5923 unsigned int level;
5924
5925 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5926 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5927 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5928 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5929 if (!default_filt_lvl)
5930 level = 0;
5931 WRITE_VREG(HEVC_DBLK_CFGA, level);
5932 }
5933}
5934/* VP9_LPF_LVL_UPDATE */
5935#endif
5936
5937static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5938{
5939 unsigned int data32;
5940 int i;
5941 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5942 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5943 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5944 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5945 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5946 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5947 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5948 0x7C00
5949 };
5950#if 0
5951 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5952 /* Set MCR fetch priorities*/
5953 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5954 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5955 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5956 }
5957#endif
5958 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
5959 pr_info("%s\n", __func__);*/
5960 if (mask & HW_MASK_FRONT) {
5961 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5962#if 1
5963 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5964 data32 &= ~(7 << 29);
5965 data32 |= (3 << 29);
5966#endif
5967 data32 = data32 |
5968 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
5969 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
5970 (1 << 7) |/*dec_done_int_cpu_enable*/
5971 (1 << 4) |/*startcode_found_int_cpu_enable*/
5972 (0 << 3) |/*startcode_found_int_amrisc_enable*/
5973 (1 << 0) /*parser_int_enable*/
5974 ;
5975#ifdef SUPPORT_FB_DECODING
5976#ifndef FB_DECODING_TEST_SCHEDULE
5977 /*fed_fb_slice_done_int_cpu_enable*/
5978 if (pbi->used_stage_buf_num > 0)
5979 data32 |= (1 << 10);
5980#endif
5981#endif
5982 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
5983
5984 data32 = READ_VREG(HEVC_SHIFT_STATUS);
5985 data32 = data32 |
5986 (0 << 1) |/*emulation_check_off VP9
5987 do not have emulation*/
5988 (1 << 0)/*startcode_check_on*/
5989 ;
5990 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
5991 WRITE_VREG(HEVC_SHIFT_CONTROL,
5992 (0 << 14) | /*disable_start_code_protect*/
5993 (1 << 10) | /*length_zero_startcode_en for VP9*/
5994 (1 << 9) | /*length_valid_startcode_en for VP9*/
5995 (3 << 6) | /*sft_valid_wr_position*/
5996 (2 << 4) | /*emulate_code_length_sub_1*/
5997 (3 << 1) | /*start_code_length_sub_1
5998 VP9 use 0x00000001 as startcode (4 Bytes)*/
5999 (1 << 0) /*stream_shift_enable*/
6000 );
6001
6002 WRITE_VREG(HEVC_CABAC_CONTROL,
6003 (1 << 0)/*cabac_enable*/
6004 );
6005
6006 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6007 (1 << 0)/* hevc_parser_core_clk_en*/
6008 );
6009
6010
6011 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6012
6013 }
6014
6015 if (mask & HW_MASK_BACK) {
6016 /*Initial IQIT_SCALELUT memory
6017 -- just to avoid X in simulation*/
6018
6019 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6020 for (i = 0; i < 1024; i++)
6021 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6022 }
6023
6024 if (mask & HW_MASK_FRONT) {
6025 u32 decode_mode;
6026#ifdef ENABLE_SWAP_TEST
6027 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6028#else
6029 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6030#endif
6031#ifdef MULTI_INSTANCE_SUPPORT
6032 if (!pbi->m_ins_flag) {
6033 if (pbi->low_latency_flag)
6034 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6035 else
6036 decode_mode = DECODE_MODE_SINGLE;
6037 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6038 decode_mode = pbi->no_head ?
6039 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6040 DECODE_MODE_MULTI_FRAMEBASE;
6041 else
6042 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6043#ifdef SUPPORT_FB_DECODING
6044#ifndef FB_DECODING_TEST_SCHEDULE
6045 if (pbi->used_stage_buf_num > 0)
6046 decode_mode |= (0x01 << 24);
6047#endif
6048#endif
6049 WRITE_VREG(DECODE_MODE, decode_mode);
6050 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6051 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6052#else
6053 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6054 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6055 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6056#endif
6057 /*Send parser_cmd*/
6058 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6059 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6060 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6061 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6062 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6063 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6064
6065
6066 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6067 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6068 (1 << 5) | /*parser_sao_if_en*/
6069 (1 << 2) | /*parser_mpred_if_en*/
6070 (1 << 0) /*parser_scaler_if_en*/
6071 );
6072 }
6073
6074 if (mask & HW_MASK_BACK) {
6075 /*Changed to Start MPRED in microcode*/
6076 /*
6077 pr_info("[test.c] Start MPRED\n");
6078 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6079 (1<<31)
6080 );
6081 */
6082 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6083 (0 << 1) | /*enable ipp*/
6084 (1 << 0) /*software reset ipp and mpp*/
6085 );
6086 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6087 (1 << 1) | /*enable ipp*/
6088 (0 << 0) /*software reset ipp and mpp*/
6089 );
6090 if (get_double_write_mode(pbi) & 0x10) {
6091 /*Enable NV21 reference read mode for MC*/
6092 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6093 }
6094
6095 /*Initialize mcrcc and decomp perf counters*/
6096 if (mcrcc_cache_alg_flag &&
6097 pbi->init_flag == 0) {
6098 mcrcc_perfcount_reset();
6099 decomp_perfcount_reset();
6100 }
6101 }
6102 return;
6103}
6104
6105
6106#ifdef CONFIG_HEVC_CLK_FORCED_ON
6107static void config_vp9_clk_forced_on(void)
6108{
6109 unsigned int rdata32;
6110 /*IQIT*/
6111 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6112 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6113
6114 /* DBLK*/
6115 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6116 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6117
6118 /* SAO*/
6119 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6120 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6121
6122 /*MPRED*/
6123 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6124 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6125
6126 /* PARSER*/
6127 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6128 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6129 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6130 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6131 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6132 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6133 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6134 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6135 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6136 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6137 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6138 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6139 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6140
6141 /*IPP*/
6142 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6143 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6144
6145 /* MCRCC*/
6146 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6147 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6148}
6149#endif
6150
6151
6152#ifdef MCRCC_ENABLE
6153static void dump_hit_rate(struct VP9Decoder_s *pbi)
6154{
6155 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6156 mcrcc_get_hitrate(pbi->m_ins_flag);
6157 decomp_get_hitrate();
6158 decomp_get_comprate();
6159 }
6160}
6161
6162static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6163{
6164 unsigned int rdata32;
6165 unsigned short is_inter;
6166 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6167 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6168 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6169 (!pbi->common.intra_only)) ? 1 : 0;
6170 if (!is_inter) { /* I-PIC*/
6171 /*remove reset -- disables clock*/
6172 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6173 return;
6174 }
6175
6176 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6177 mcrcc_get_hitrate(pbi->m_ins_flag);
6178 decomp_get_hitrate();
6179 decomp_get_comprate();
6180 }
6181
6182 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6183 (0 << 8) | (1 << 1) | 0);
6184 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6185 rdata32 = rdata32 & 0xffff;
6186 rdata32 = rdata32 | (rdata32 << 16);
6187 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6188 /*Programme canvas1 */
6189 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6190 rdata32 = rdata32 & 0xffff;
6191 rdata32 = rdata32 | (rdata32 << 16);
6192 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6193 /*enable mcrcc progressive-mode*/
6194 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6195}
6196
6197static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6198{
6199 u32 curr_picnum = -1;
6200 u32 lastref_picnum = -1;
6201 u32 goldenref_picnum = -1;
6202 u32 altref_picnum = -1;
6203
6204 u32 lastref_delta_picnum;
6205 u32 goldenref_delta_picnum;
6206 u32 altref_delta_picnum;
6207
6208 u32 rdata32;
6209
6210 u32 lastcanvas;
6211 u32 goldencanvas;
6212 u32 altrefcanvas;
6213
6214 u16 is_inter;
6215 u16 lastref_inref;
6216 u16 goldenref_inref;
6217 u16 altref_inref;
6218
6219 u32 refcanvas_array[3], utmp;
6220 int deltapicnum_array[3], tmp;
6221
6222 struct VP9_Common_s *cm = &pbi->common;
6223 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6224 = &cm->cur_frame->buf;
6225 curr_picnum = cur_pic_config->decode_idx;
6226 if (cm->frame_refs[0].buf)
6227 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6228 if (cm->frame_refs[1].buf)
6229 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6230 if (cm->frame_refs[2].buf)
6231 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6232
6233 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6234 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6235 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6236 (goldenref_picnum - curr_picnum) :
6237 (curr_picnum - goldenref_picnum);
6238 altref_delta_picnum =
6239 (altref_picnum >= curr_picnum) ?
6240 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6241
6242 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6243 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6244 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6245
6246 if (debug & VP9_DEBUG_CACHE)
6247 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6248 __func__, lastref_inref, goldenref_inref, altref_inref);
6249
6250 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6251
6252 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6253 && (!pbi->common.intra_only)) ? 1 : 0;
6254
6255 if (!is_inter) { /* I-PIC */
6256 /* remove reset -- disables clock */
6257 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6258 return;
6259 }
6260
6261 if (!pbi->m_ins_flag)
6262 dump_hit_rate(pbi);
6263
6264 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6265 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6266 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6267 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6268
6269 if (debug & VP9_DEBUG_CACHE)
6270 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6271 lastcanvas, goldencanvas, altrefcanvas);
6272
6273 altref_inref = ((altref_inref == 1) &&
6274 (altrefcanvas != (goldenref_inref
6275 ? goldencanvas : 0xffffffff)) &&
6276 (altrefcanvas != (lastref_inref ?
6277 lastcanvas : 0xffffffff))) ? 1 : 0;
6278 goldenref_inref = ((goldenref_inref == 1) &&
6279 (goldencanvas != (lastref_inref ?
6280 lastcanvas : 0xffffffff))) ? 1 : 0;
6281 if (debug & VP9_DEBUG_CACHE)
6282 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6283 lastref_inref, goldenref_inref, altref_inref);
6284
6285 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6286 goldenref_delta_picnum = goldenref_inref ?
6287 goldenref_delta_picnum : 0x7fffffff;
6288 lastref_delta_picnum = lastref_inref ?
6289 lastref_delta_picnum : 0x7fffffff;
6290 if (debug & VP9_DEBUG_CACHE)
6291 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6292 lastref_delta_picnum, goldenref_delta_picnum,
6293 altref_delta_picnum);
6294 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6295
6296 refcanvas_array[0] = lastcanvas;
6297 refcanvas_array[1] = goldencanvas;
6298 refcanvas_array[2] = altrefcanvas;
6299
6300 deltapicnum_array[0] = lastref_delta_picnum;
6301 deltapicnum_array[1] = goldenref_delta_picnum;
6302 deltapicnum_array[2] = altref_delta_picnum;
6303
6304 /* sort0 : 2-to-1 */
6305 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6306 utmp = refcanvas_array[2];
6307 refcanvas_array[2] = refcanvas_array[1];
6308 refcanvas_array[1] = utmp;
6309 tmp = deltapicnum_array[2];
6310 deltapicnum_array[2] = deltapicnum_array[1];
6311 deltapicnum_array[1] = tmp;
6312 }
6313 /* sort1 : 1-to-0 */
6314 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6315 utmp = refcanvas_array[1];
6316 refcanvas_array[1] = refcanvas_array[0];
6317 refcanvas_array[0] = utmp;
6318 tmp = deltapicnum_array[1];
6319 deltapicnum_array[1] = deltapicnum_array[0];
6320 deltapicnum_array[0] = tmp;
6321 }
6322 /* sort2 : 2-to-1 */
6323 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6324 utmp = refcanvas_array[2]; refcanvas_array[2] =
6325 refcanvas_array[1]; refcanvas_array[1] = utmp;
6326 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6327 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6328 }
6329 if (mcrcc_cache_alg_flag ==
6330 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6331 /* lowest delta_picnum */
6332 rdata32 = refcanvas_array[0];
6333 rdata32 = rdata32 & 0xffff;
6334 rdata32 = rdata32 | (rdata32 << 16);
6335 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6336
6337 /* 2nd-lowest delta_picnum */
6338 rdata32 = refcanvas_array[1];
6339 rdata32 = rdata32 & 0xffff;
6340 rdata32 = rdata32 | (rdata32 << 16);
6341 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6342 } else {
6343 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6344 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6345 (0 << 8) | (1<<1) | 0);
6346 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6347 rdata32 = rdata32 & 0xffff;
6348 rdata32 = rdata32 | (rdata32 << 16);
6349 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6350
6351 /* Programme canvas1 */
6352 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6353 rdata32 = rdata32 & 0xffff;
6354 rdata32 = rdata32 | (rdata32 << 16);
6355 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6356 }
6357
6358 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6359 return;
6360}
6361
6362#endif
6363
6364
6365static void free_lf_buf(struct VP9Decoder_s *pbi)
6366{
6367 if (pbi->lfi)
6368 vfree(pbi->lfi);
6369 if (pbi->lf)
6370 vfree(pbi->lf);
6371 if (pbi->seg_4lf)
6372 vfree(pbi->seg_4lf);
6373 pbi->lfi = NULL;
6374 pbi->lf = NULL;
6375 pbi->seg_4lf = NULL;
6376}
6377
6378static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6379{
6380 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6381 pbi->lf = vmalloc(sizeof(struct loopfilter));
6382 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6383 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6384 free_lf_buf(pbi);
6385 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6386 return -1;
6387 }
6388 return 0;
6389}
6390
6391static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6392{
6393 pbi->rpm_ptr = NULL;
6394 pbi->lmem_ptr = NULL;
6395 if (pbi->rpm_addr) {
6396 dma_free_coherent(amports_get_dma_device(),
6397 RPM_BUF_SIZE,
6398 pbi->rpm_addr,
6399 pbi->rpm_phy_addr);
6400 pbi->rpm_addr = NULL;
6401 }
6402 if (pbi->lmem_addr) {
6403 if (pbi->lmem_phy_addr)
6404 dma_free_coherent(amports_get_dma_device(),
6405 LMEM_BUF_SIZE, pbi->lmem_addr,
6406 pbi->lmem_phy_addr);
6407 pbi->lmem_addr = NULL;
6408 }
6409 if (pbi->prob_buffer_addr) {
6410 if (pbi->prob_buffer_phy_addr)
6411 dma_free_coherent(amports_get_dma_device(),
6412 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6413 pbi->prob_buffer_phy_addr);
6414
6415 pbi->prob_buffer_addr = NULL;
6416 }
6417 if (pbi->count_buffer_addr) {
6418 if (pbi->count_buffer_phy_addr)
6419 dma_free_coherent(amports_get_dma_device(),
6420 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6421 pbi->count_buffer_phy_addr);
6422
6423 pbi->count_buffer_addr = NULL;
6424 }
6425 if (pbi->mmu_enable) {
6426 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6427 if (pbi->frame_mmu_map_addr) {
6428 if (pbi->frame_mmu_map_phy_addr)
6429 dma_free_coherent(amports_get_dma_device(),
6430 mmu_map_size,
6431 pbi->frame_mmu_map_addr,
6432 pbi->frame_mmu_map_phy_addr);
6433 pbi->frame_mmu_map_addr = NULL;
6434 }
6435 }
6436#ifdef SUPPORT_FB_DECODING
6437 if (pbi->stage_mmu_map_addr) {
6438 if (pbi->stage_mmu_map_phy_addr)
6439 dma_free_coherent(amports_get_dma_device(),
6440 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6441 pbi->stage_mmu_map_addr,
6442 pbi->stage_mmu_map_phy_addr);
6443 pbi->stage_mmu_map_addr = NULL;
6444 }
6445
6446 uninit_stage_buf(pbi);
6447#endif
6448
6449#ifdef VP9_LPF_LVL_UPDATE
6450 free_lf_buf(pbi);
6451#endif
6452 if (pbi->gvs)
6453 vfree(pbi->gvs);
6454 pbi->gvs = NULL;
6455}
6456
6457static int vp9_local_init(struct VP9Decoder_s *pbi)
6458{
6459 int ret = -1;
6460 /*int losless_comp_header_size, losless_comp_body_size;*/
6461
6462 struct BuffInfo_s *cur_buf_info = NULL;
6463
6464 memset(&pbi->param, 0, sizeof(union param_u));
6465 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6466#ifdef MULTI_INSTANCE_SUPPORT
6467 cur_buf_info = &pbi->work_space_buf_store;
6468
6469 if (vdec_is_support_4k()) {
6470 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6471 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6472 sizeof(struct BuffInfo_s));
6473 } else
6474 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6475 sizeof(struct BuffInfo_s));
6476 } else
6477 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6478 sizeof(struct BuffInfo_s));
6479
6480 cur_buf_info->start_adr = pbi->buf_start;
6481 if (!pbi->mmu_enable)
6482 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6483
6484#else
6485/*! MULTI_INSTANCE_SUPPORT*/
6486 if (vdec_is_support_4k()) {
6487 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6488 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6489 else
6490 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6491 } else
6492 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6493
6494#endif
6495
6496 init_buff_spec(pbi, cur_buf_info);
6497 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6498
6499 if (!vdec_is_support_4k()
6500 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6501 buf_alloc_width = 1920;
6502 buf_alloc_height = 1088;
6503 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6504 pbi->max_pic_w = 1920;
6505 pbi->max_pic_h = 1088;
6506 }
6507 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6508 buf_alloc_width = 8192;
6509 buf_alloc_height = 4608;
6510 }
6511 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6512 (buf_alloc_width ? buf_alloc_width :
6513 (pbi->vvp9_amstream_dec_info.width ?
6514 pbi->vvp9_amstream_dec_info.width :
6515 pbi->work_space_buf->max_width));
6516 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6517 (buf_alloc_height ? buf_alloc_height :
6518 (pbi->vvp9_amstream_dec_info.height ?
6519 pbi->vvp9_amstream_dec_info.height :
6520 pbi->work_space_buf->max_height));
6521
6522 pbi->mem_map_mode = mem_map_mode ? mem_map_mode : 0;
6523
6524 /* video is not support unaligned with 64 in tl1
6525 ** vdec canvas mode will be linear when dump yuv is set
6526 */
6527 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6528 (pbi->double_write_mode != 0) &&
6529 (((pbi->max_pic_w % 64) != 0) ||
6530 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6531 if (hw_to_vdec(pbi)->canvas_mode !=
6532 CANVAS_BLKMODE_LINEAR)
6533 pbi->mem_map_mode = 2;
6534 else {
6535 pbi->mem_map_mode = 0;
6536 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6537 }
6538 }
6539
6540#ifndef MV_USE_FIXED_BUF
6541 if (init_mv_buf_list(pbi) < 0) {
6542 pr_err("%s: init_mv_buf_list fail\n", __func__);
6543 return -1;
6544 }
6545#endif
6546 if (pbi->save_buffer_mode)
6547 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6548 else {
6549 if (pbi->is_used_v4l)
6550 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6551 else
6552 pbi->used_buf_num = max_buf_num;
6553 }
6554
6555 if (pbi->used_buf_num > MAX_BUF_NUM)
6556 pbi->used_buf_num = MAX_BUF_NUM;
6557 if (pbi->used_buf_num > FRAME_BUFFERS)
6558 pbi->used_buf_num = FRAME_BUFFERS;
6559
6560 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6561 & 0x40) >> 6;
6562
6563 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6564 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6565 RPM_BUF_SIZE,
6566 &pbi->rpm_phy_addr, GFP_KERNEL);
6567 if (pbi->rpm_addr == NULL) {
6568 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6569 return -1;
6570 }
6571
6572 pbi->rpm_ptr = pbi->rpm_addr;
6573 }
6574
6575 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6576 LMEM_BUF_SIZE,
6577 &pbi->lmem_phy_addr, GFP_KERNEL);
6578 if (pbi->lmem_addr == NULL) {
6579 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6580 return -1;
6581 }
6582 pbi->lmem_ptr = pbi->lmem_addr;
6583
6584 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6585 PROB_BUF_SIZE,
6586 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6587 if (pbi->prob_buffer_addr == NULL) {
6588 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6589 return -1;
6590 }
6591 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6592 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6593 COUNT_BUF_SIZE,
6594 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6595 if (pbi->count_buffer_addr == NULL) {
6596 pr_err("%s: failed to alloc count_buffer\n", __func__);
6597 return -1;
6598 }
6599 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6600
6601 if (pbi->mmu_enable) {
6602 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6603 pbi->frame_mmu_map_addr =
6604 dma_alloc_coherent(amports_get_dma_device(),
6605 mmu_map_size,
6606 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6607 if (pbi->frame_mmu_map_addr == NULL) {
6608 pr_err("%s: failed to alloc count_buffer\n", __func__);
6609 return -1;
6610 }
6611 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6612 }
6613#ifdef SUPPORT_FB_DECODING
6614 if (pbi->m_ins_flag && stage_buf_num > 0) {
6615 pbi->stage_mmu_map_addr =
6616 dma_alloc_coherent(amports_get_dma_device(),
6617 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6618 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6619 if (pbi->stage_mmu_map_addr == NULL) {
6620 pr_err("%s: failed to alloc count_buffer\n", __func__);
6621 return -1;
6622 }
6623 memset(pbi->stage_mmu_map_addr,
6624 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6625
6626 init_stage_buf(pbi);
6627 }
6628#endif
6629
6630 ret = 0;
6631 return ret;
6632}
6633
6634/********************************************
6635 * Mailbox command
6636 ********************************************/
6637#define CMD_FINISHED 0
6638#define CMD_ALLOC_VIEW 1
6639#define CMD_FRAME_DISPLAY 3
6640#define CMD_DEBUG 10
6641
6642
6643#define DECODE_BUFFER_NUM_MAX 32
6644#define DISPLAY_BUFFER_NUM 6
6645
6646#define video_domain_addr(adr) (adr&0x7fffffff)
6647#define DECODER_WORK_SPACE_SIZE 0x800000
6648
6649#define spec2canvas(x) \
6650 (((x)->uv_canvas_index << 16) | \
6651 ((x)->uv_canvas_index << 8) | \
6652 ((x)->y_canvas_index << 0))
6653
6654
6655static void set_canvas(struct VP9Decoder_s *pbi,
6656 struct PIC_BUFFER_CONFIG_s *pic_config)
6657{
6658 struct vdec_s *vdec = hw_to_vdec(pbi);
6659 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6660 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6661 int blkmode = pbi->mem_map_mode;
6662 /*CANVAS_BLKMODE_64X32*/
6663 if (pic_config->double_write_mode) {
6664 canvas_w = pic_config->y_crop_width /
6665 get_double_write_ratio(pbi,
6666 pic_config->double_write_mode);
6667 canvas_h = pic_config->y_crop_height /
6668 get_double_write_ratio(pbi,
6669 pic_config->double_write_mode);
6670
6671 if (pbi->mem_map_mode == 0)
6672 canvas_w = ALIGN(canvas_w, 32);
6673 else
6674 canvas_w = ALIGN(canvas_w, 64);
6675 canvas_h = ALIGN(canvas_h, 32);
6676
6677 if (vdec->parallel_dec == 1) {
6678 if (pic_config->y_canvas_index == -1)
6679 pic_config->y_canvas_index =
6680 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6681 if (pic_config->uv_canvas_index == -1)
6682 pic_config->uv_canvas_index =
6683 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6684 } else {
6685 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6686 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6687 }
6688
6689 canvas_config_ex(pic_config->y_canvas_index,
6690 pic_config->dw_y_adr, canvas_w, canvas_h,
6691 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6692 canvas_config_ex(pic_config->uv_canvas_index,
6693 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6694 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6695
6696#ifdef MULTI_INSTANCE_SUPPORT
6697 pic_config->canvas_config[0].phy_addr =
6698 pic_config->dw_y_adr;
6699 pic_config->canvas_config[0].width =
6700 canvas_w;
6701 pic_config->canvas_config[0].height =
6702 canvas_h;
6703 pic_config->canvas_config[0].block_mode =
6704 blkmode;
6705 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6706
6707 pic_config->canvas_config[1].phy_addr =
6708 pic_config->dw_u_v_adr;
6709 pic_config->canvas_config[1].width =
6710 canvas_w;
6711 pic_config->canvas_config[1].height =
6712 canvas_h;
6713 pic_config->canvas_config[1].block_mode =
6714 blkmode;
6715 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6716#endif
6717 }
6718}
6719
6720
6721static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6722{
6723 unsigned int ar;
6724 vf->duration = pbi->frame_dur;
6725 vf->duration_pulldown = 0;
6726 vf->flag = 0;
6727 vf->prop.master_display_colour = pbi->vf_dp;
6728 vf->signal_type = pbi->video_signal_type;
6729 if (vf->compWidth && vf->compHeight)
6730 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6731 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6732 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6733
6734 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6735 struct aml_vdec_hdr_infos hdr;
6736 struct aml_vcodec_ctx *ctx =
6737 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6738
6739 memset(&hdr, 0, sizeof(hdr));
6740 hdr.signal_type = vf->signal_type;
6741 hdr.color_parms = pbi->vf_dp;
6742 vdec_v4l_set_hdr_infos(ctx, &hdr);
6743 }
6744}
6745
6746static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6747{
6748 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6749
6750 states->vf_pool_size = VF_POOL_SIZE;
6751 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6752 states->buf_avail_num = kfifo_len(&pbi->display_q);
6753
6754 if (step == 2)
6755 states->buf_avail_num = 0;
6756 return 0;
6757}
6758
6759static struct vframe_s *vvp9_vf_peek(void *op_arg)
6760{
6761 struct vframe_s *vf[2] = {0, 0};
6762 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6763
6764 if (step == 2)
6765 return NULL;
6766
6767 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6768 if (vf[1]) {
6769 vf[0]->next_vf_pts_valid = true;
6770 vf[0]->next_vf_pts = vf[1]->pts;
6771 } else
6772 vf[0]->next_vf_pts_valid = false;
6773 return vf[0];
6774 }
6775
6776 return NULL;
6777}
6778
6779static struct vframe_s *vvp9_vf_get(void *op_arg)
6780{
6781 struct vframe_s *vf;
6782 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6783
6784 if (step == 2)
6785 return NULL;
6786 else if (step == 1)
6787 step = 2;
6788
6789 if (kfifo_get(&pbi->display_q, &vf)) {
6790 struct vframe_s *next_vf;
6791 uint8_t index = vf->index & 0xff;
6792 if (index < pbi->used_buf_num ||
6793 (vf->type & VIDTYPE_V4L_EOS)) {
6794 pbi->vf_get_count++;
6795 if (debug & VP9_DEBUG_BUFMGR)
6796 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6797 __func__, vf->type,
6798 vf->width, vf->height,
6799 vf->pts,
6800 vf->pts_us64);
6801
6802 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6803 vf->next_vf_pts_valid = true;
6804 vf->next_vf_pts = next_vf->pts;
6805 } else
6806 vf->next_vf_pts_valid = false;
6807
6808 return vf;
6809 }
6810 }
6811 return NULL;
6812}
6813
6814static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6815{
6816 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6817 uint8_t index = vf->index & 0xff;
6818
6819 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6820 pbi->vf_put_count++;
6821 if (index < pbi->used_buf_num) {
6822 struct VP9_Common_s *cm = &pbi->common;
6823 struct BufferPool_s *pool = cm->buffer_pool;
6824 unsigned long flags;
6825
6826 lock_buffer_pool(pool, flags);
6827 if (pool->frame_bufs[index].buf.vf_ref > 0)
6828 pool->frame_bufs[index].buf.vf_ref--;
6829
6830 if (pbi->is_used_v4l)
6831 pool->frame_bufs[index].buf.vframe_bound = true;
6832
6833 if (pbi->wait_buf)
6834 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6835 0x1);
6836 pbi->last_put_idx = index;
6837 pbi->new_frame_displayed++;
6838 unlock_buffer_pool(pool, flags);
6839#ifdef SUPPORT_FB_DECODING
6840 if (pbi->used_stage_buf_num > 0 &&
6841 pbi->back_not_run_ready)
6842 trigger_schedule(pbi);
6843#endif
6844 }
6845
6846}
6847
6848static int vvp9_event_cb(int type, void *data, void *private_data)
6849{
6850 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6851#if 0
6852 unsigned long flags;
6853
6854 amhevc_stop();
6855#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6856 vf_light_unreg_provider(&vvp9_vf_prov);
6857#endif
6858 spin_lock_irqsave(&pbi->lock, flags);
6859 vvp9_local_init();
6860 vvp9_prot_init();
6861 spin_unlock_irqrestore(&pbi->lock, flags);
6862#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6863 vf_reg_provider(&vvp9_vf_prov);
6864#endif
6865 amhevc_start();
6866#endif
6867 }
6868
6869 return 0;
6870}
6871
6872void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6873{
6874 struct VP9_Common_s *cm = &pbi->common;
6875
6876 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6877
6878 if (debug & VP9_DEBUG_BUFMGR_MORE)
6879 pr_info("%s index = %d new vf_ref = %d\r\n",
6880 __func__, index,
6881 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6882}
6883
6884static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6885{
6886 u32 old_duration, pts_duration = 0;
6887 u32 pts = vf->pts;
6888
6889 if (pbi->get_frame_dur == true)
6890 return true;
6891
6892 pbi->frame_cnt_window++;
6893 if (!(pbi->vp9_first_pts_ready == 1)) {
6894 if (valid) {
6895 pbi->pts1 = pts;
6896 pbi->frame_cnt_window = 0;
6897 pbi->duration_from_pts_done = 0;
6898 pbi->vp9_first_pts_ready = 1;
6899 } else {
6900 return false;
6901 }
6902 } else {
6903 if (pts < pbi->pts1) {
6904 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6905 pbi->pts1 = pts;
6906 pbi->frame_cnt_window = 0;
6907 }
6908 }
6909
6910 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6911 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6912 old_duration = pbi->frame_dur;
6913 pbi->pts2 = pts;
6914 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6915 (pbi->frame_cnt_window * 15));
6916
6917 if (close_to(pts_duration, old_duration, 2000)) {
6918 pbi->frame_dur = pts_duration;
6919 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6920 pr_info("use calc duration %d\n", pts_duration);
6921 }
6922
6923 if (pbi->duration_from_pts_done == 0) {
6924 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6925 pbi->duration_from_pts_done = 1;
6926 } else {
6927 if (!close_to(pts_duration,
6928 old_duration, 1000) &&
6929 !close_to(pts_duration,
6930 pbi->frame_dur, 1000) &&
6931 close_to(pts_duration,
6932 pbi->last_duration, 200)) {
6933 /* frame_dur must
6934 * wrong,recover it.
6935 */
6936 pbi->frame_dur = pts_duration;
6937 }
6938 pbi->pts1 = pbi->pts2;
6939 pbi->frame_cnt_window = 0;
6940 pbi->duration_from_pts_done = 0;
6941 }
6942 }
6943 pbi->last_duration = pts_duration;
6944 }
6945 }
6946 return true;
6947}
6948
6949static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6950 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6951{
6952 if (pic->index < 0) {
6953 vf->mem_handle = NULL;
6954 vf->mem_head_handle = NULL;
6955 } else if (vf->type & VIDTYPE_SCATTER) {
6956 vf->mem_handle =
6957 decoder_mmu_box_get_mem_handle(
6958 pbi->mmu_box, pic->index);
6959 vf->mem_head_handle =
6960 decoder_bmmu_box_get_mem_handle(
6961 pbi->bmmu_box,
6962 HEADER_BUFFER_IDX(pic->BUF_index));
6963 } else {
6964 vf->mem_handle =
6965 decoder_bmmu_box_get_mem_handle(
6966 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
6967 vf->mem_head_handle = NULL;
6968 /*vf->mem_head_handle =
6969 *decoder_bmmu_box_get_mem_handle(
6970 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
6971 */
6972 }
6973}
6974
6975static int prepare_display_buf(struct VP9Decoder_s *pbi,
6976 struct PIC_BUFFER_CONFIG_s *pic_config)
6977{
6978 struct vframe_s *vf = NULL;
6979 int stream_offset = pic_config->stream_offset;
6980 unsigned short slice_type = pic_config->slice_type;
6981 u32 pts_valid = 0, pts_us64_valid = 0;
6982 u32 pts_save;
6983 u64 pts_us64_save;
6984 u32 frame_size;
6985
6986 if (debug & VP9_DEBUG_BUFMGR)
6987 pr_info("%s index = %d\r\n", __func__, pic_config->index);
6988 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
6989 pr_info("fatal error, no available buffer slot.");
6990 return -1;
6991 }
6992
6993 if (pic_config->double_write_mode)
6994 set_canvas(pbi, pic_config);
6995
6996 display_frame_count[pbi->index]++;
6997 if (vf) {
6998 if (pbi->is_used_v4l) {
6999 vf->v4l_mem_handle
7000 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7001 if (pbi->mmu_enable) {
7002 vf->mm_box.bmmu_box = pbi->bmmu_box;
7003 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7004 vf->mm_box.mmu_box = pbi->mmu_box;
7005 vf->mm_box.mmu_idx = pic_config->index;
7006 }
7007 }
7008
7009#ifdef MULTI_INSTANCE_SUPPORT
7010 if (vdec_frame_based(hw_to_vdec(pbi))) {
7011 vf->pts = pic_config->pts;
7012 vf->pts_us64 = pic_config->pts64;
7013 vf->timestamp = pic_config->timestamp;
7014 if (vf->pts != 0 || vf->pts_us64 != 0) {
7015 pts_valid = 1;
7016 pts_us64_valid = 1;
7017 } else {
7018 pts_valid = 0;
7019 pts_us64_valid = 0;
7020 }
7021 } else
7022#endif
7023 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7024 * stream_offset, &vf->pts, 0) != 0) {
7025 */
7026 if (pts_lookup_offset_us64
7027 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7028 &frame_size, 0,
7029 &vf->pts_us64) != 0) {
7030#ifdef DEBUG_PTS
7031 pbi->pts_missed++;
7032#endif
7033 vf->pts = 0;
7034 vf->pts_us64 = 0;
7035 pts_valid = 0;
7036 pts_us64_valid = 0;
7037 } else {
7038#ifdef DEBUG_PTS
7039 pbi->pts_hit++;
7040#endif
7041 pts_valid = 1;
7042 pts_us64_valid = 1;
7043 }
7044
7045 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7046
7047 pts_save = vf->pts;
7048 pts_us64_save = vf->pts_us64;
7049 if (pbi->pts_unstable) {
7050 frame_duration_adapt(pbi, vf, pts_valid);
7051 if (pbi->duration_from_pts_done) {
7052 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7053 } else {
7054 if (pts_valid || pts_us64_valid)
7055 pbi->pts_mode = PTS_NORMAL;
7056 }
7057 }
7058
7059 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7060 && pbi->get_frame_dur) {
7061 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7062
7063 if (pts_diff < 0) {
7064 pbi->pts_mode_switching_count++;
7065 pbi->pts_mode_recovery_count = 0;
7066
7067 if (pbi->pts_mode_switching_count >=
7068 PTS_MODE_SWITCHING_THRESHOLD) {
7069 pbi->pts_mode =
7070 PTS_NONE_REF_USE_DURATION;
7071 pr_info
7072 ("HEVC: switch to n_d mode.\n");
7073 }
7074
7075 } else {
7076 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7077
7078 pbi->pts_mode_recovery_count++;
7079 if (pbi->pts_mode_recovery_count > p) {
7080 pbi->pts_mode_switching_count = 0;
7081 pbi->pts_mode_recovery_count = 0;
7082 }
7083 }
7084 }
7085
7086 if (vf->pts != 0)
7087 pbi->last_lookup_pts = vf->pts;
7088
7089 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7090 && (slice_type != KEY_FRAME))
7091 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7092 pbi->last_pts = vf->pts;
7093
7094 if (vf->pts_us64 != 0)
7095 pbi->last_lookup_pts_us64 = vf->pts_us64;
7096
7097 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7098 && (slice_type != KEY_FRAME)) {
7099 vf->pts_us64 =
7100 pbi->last_pts_us64 +
7101 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7102 }
7103 pbi->last_pts_us64 = vf->pts_us64;
7104 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7105 pr_info
7106 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7107 pbi->pts_mode, pbi->frame_dur, vf->pts,
7108 vf->pts_us64, pts_save, pts_us64_save);
7109 }
7110
7111 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7112 vf->disp_pts = vf->pts;
7113 vf->disp_pts_us64 = vf->pts_us64;
7114 vf->pts = pts_save;
7115 vf->pts_us64 = pts_us64_save;
7116 } else {
7117 vf->disp_pts = 0;
7118 vf->disp_pts_us64 = 0;
7119 }
7120
7121 vf->index = 0xff00 | pic_config->index;
7122
7123 if (pic_config->double_write_mode & 0x10) {
7124 /* double write only */
7125 vf->compBodyAddr = 0;
7126 vf->compHeadAddr = 0;
7127 } else {
7128 if (pbi->mmu_enable) {
7129 vf->compBodyAddr = 0;
7130 vf->compHeadAddr = pic_config->header_adr;
7131 } else {
7132 /*vf->compBodyAddr = pic_config->mc_y_adr;
7133 *vf->compHeadAddr = pic_config->mc_y_adr +
7134 *pic_config->comp_body_size; */
7135 /*head adr*/
7136 }
7137 vf->canvas0Addr = vf->canvas1Addr = 0;
7138 }
7139 if (pic_config->double_write_mode) {
7140 vf->type = VIDTYPE_PROGRESSIVE |
7141 VIDTYPE_VIU_FIELD;
7142 vf->type |= VIDTYPE_VIU_NV21;
7143 if ((pic_config->double_write_mode == 3) &&
7144 (!IS_8K_SIZE(pic_config->y_crop_width,
7145 pic_config->y_crop_height))) {
7146 vf->type |= VIDTYPE_COMPRESS;
7147 if (pbi->mmu_enable)
7148 vf->type |= VIDTYPE_SCATTER;
7149 }
7150#ifdef MULTI_INSTANCE_SUPPORT
7151 if (pbi->m_ins_flag) {
7152 vf->canvas0Addr = vf->canvas1Addr = -1;
7153 vf->plane_num = 2;
7154 vf->canvas0_config[0] =
7155 pic_config->canvas_config[0];
7156 vf->canvas0_config[1] =
7157 pic_config->canvas_config[1];
7158 vf->canvas1_config[0] =
7159 pic_config->canvas_config[0];
7160 vf->canvas1_config[1] =
7161 pic_config->canvas_config[1];
7162
7163 } else
7164#endif
7165 vf->canvas0Addr = vf->canvas1Addr =
7166 spec2canvas(pic_config);
7167 } else {
7168 vf->canvas0Addr = vf->canvas1Addr = 0;
7169 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7170 if (pbi->mmu_enable)
7171 vf->type |= VIDTYPE_SCATTER;
7172 }
7173
7174 switch (pic_config->bit_depth) {
7175 case VPX_BITS_8:
7176 vf->bitdepth = BITDEPTH_Y8 |
7177 BITDEPTH_U8 | BITDEPTH_V8;
7178 break;
7179 case VPX_BITS_10:
7180 case VPX_BITS_12:
7181 vf->bitdepth = BITDEPTH_Y10 |
7182 BITDEPTH_U10 | BITDEPTH_V10;
7183 break;
7184 default:
7185 vf->bitdepth = BITDEPTH_Y10 |
7186 BITDEPTH_U10 | BITDEPTH_V10;
7187 break;
7188 }
7189 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7190 vf->bitdepth =
7191 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7192 if (pic_config->bit_depth == VPX_BITS_8)
7193 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7194
7195 /* if((vf->width!=pic_config->width)|
7196 * (vf->height!=pic_config->height))
7197 */
7198 /* pr_info("aaa: %d/%d, %d/%d\n",
7199 vf->width,vf->height, pic_config->width,
7200 pic_config->height); */
7201 vf->width = pic_config->y_crop_width /
7202 get_double_write_ratio(pbi,
7203 pic_config->double_write_mode);
7204 vf->height = pic_config->y_crop_height /
7205 get_double_write_ratio(pbi,
7206 pic_config->double_write_mode);
7207 if (force_w_h != 0) {
7208 vf->width = (force_w_h >> 16) & 0xffff;
7209 vf->height = force_w_h & 0xffff;
7210 }
7211 vf->compWidth = pic_config->y_crop_width;
7212 vf->compHeight = pic_config->y_crop_height;
7213 set_frame_info(pbi, vf);
7214 if (force_fps & 0x100) {
7215 u32 rate = force_fps & 0xff;
7216
7217 if (rate)
7218 vf->duration = 96000/rate;
7219 else
7220 vf->duration = 0;
7221 }
7222 update_vf_memhandle(pbi, vf, pic_config);
7223 if (!(pic_config->y_crop_width == 196
7224 && pic_config->y_crop_height == 196
7225 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7226 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7227 inc_vf_ref(pbi, pic_config->index);
7228 decoder_do_frame_check(hw_to_vdec(pbi), vf);
7229 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7230 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7231 pbi->vf_pre_count++;
7232#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7233 /*count info*/
7234 gvs->frame_dur = pbi->frame_dur;
7235 vdec_count_info(gvs, 0, stream_offset);
7236#endif
7237 hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
7238 if (without_display_mode == 0) {
7239 vf_notify_receiver(pbi->provider_name,
7240 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7241 } else
7242 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7243 } else {
7244 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7245 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7246 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7247 __func__, __LINE__, vf->width,
7248 vf->height, pbi->stat);
7249 }
7250 }
7251
7252 return 0;
7253}
7254
7255static int notify_v4l_eos(struct vdec_s *vdec)
7256{
7257 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7258 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7259 struct vframe_s *vf = NULL;
7260 int index = INVALID_IDX;
7261 ulong expires;
7262
7263 if (hw->is_used_v4l && hw->eos) {
7264 if (kfifo_get(&hw->newframe_q, &vf) == 0 || vf == NULL) {
7265 vp9_print(hw, 0,
7266 "%s fatal error, no available buffer slot.\n",
7267 __func__);
7268 return -1;
7269 }
7270
7271 expires = jiffies + msecs_to_jiffies(2000);
7272 while (INVALID_IDX == (index = get_free_fb(hw))) {
7273 if (time_after(jiffies, expires))
7274 break;
7275 }
7276
7277 if (index == INVALID_IDX) {
7278 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7279 return -1;
7280 }
7281
7282 vf->type |= VIDTYPE_V4L_EOS;
7283 vf->timestamp = ULONG_MAX;
7284 vf->v4l_mem_handle = hw->m_BUF[index].v4l_ref_buf_addr;
7285 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7286
7287 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7288 vf_notify_receiver(vdec->vf_provider_name,
7289 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7290
7291 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7292 }
7293
7294 return 0;
7295}
7296
7297static void get_rpm_param(union param_u *params)
7298{
7299 int i;
7300 unsigned int data32;
7301
7302 if (debug & VP9_DEBUG_BUFMGR)
7303 pr_info("enter %s\r\n", __func__);
7304 for (i = 0; i < 128; i++) {
7305 do {
7306 data32 = READ_VREG(RPM_CMD_REG);
7307 /*pr_info("%x\n", data32);*/
7308 } while ((data32 & 0x10000) == 0);
7309 params->l.data[i] = data32&0xffff;
7310 /*pr_info("%x\n", data32);*/
7311 WRITE_VREG(RPM_CMD_REG, 0);
7312 }
7313 if (debug & VP9_DEBUG_BUFMGR)
7314 pr_info("leave %s\r\n", __func__);
7315}
7316static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7317{
7318 int i;
7319
7320 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7321 return;
7322 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7323 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7324 pr_info("%04x ", vp9_param.l.data[i]);
7325 if (((i + 1) & 0xf) == 0)
7326 pr_info("\n");
7327 }
7328 pr_info("=============param==========\r\n");
7329 pr_info("profile %x\r\n", vp9_param.p.profile);
7330 pr_info("show_existing_frame %x\r\n",
7331 vp9_param.p.show_existing_frame);
7332 pr_info("frame_to_show_idx %x\r\n",
7333 vp9_param.p.frame_to_show_idx);
7334 pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7335 pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7336 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7337 vp9_param.p.error_resilient_mode);
7338 pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7339 pr_info("display_size_present %x\r\n",
7340 vp9_param.p.display_size_present);
7341 pr_info("reset_frame_context %x\r\n",
7342 vp9_param.p.reset_frame_context);
7343 pr_info("refresh_frame_flags %x\r\n",
7344 vp9_param.p.refresh_frame_flags);
7345 pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7346 pr_info("width %x\r\n", vp9_param.p.width);
7347 pr_info("height %x\r\n", vp9_param.p.height);
7348 pr_info("display_width %x\r\n", vp9_param.p.display_width);
7349 pr_info("display_height %x\r\n", vp9_param.p.display_height);
7350 pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7351 pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7352 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7353 return;
7354 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7355 vp9_param.p.mode_ref_delta_enabled);
7356 pr_info("sharpness_level: 0x%x\r\n",
7357 vp9_param.p.sharpness_level);
7358 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7359 vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7360 vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7361 pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7362 vp9_param.p.mode_deltas[1]);
7363 pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7364 pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7365 pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7366 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7367 (vp9_param.p.seg_lf_info[0]>>15 & 1),
7368 (vp9_param.p.seg_lf_info[1]>>15 & 1),
7369 (vp9_param.p.seg_lf_info[2]>>15 & 1),
7370 (vp9_param.p.seg_lf_info[3]>>15 & 1),
7371 (vp9_param.p.seg_lf_info[4]>>15 & 1),
7372 (vp9_param.p.seg_lf_info[5]>>15 & 1),
7373 (vp9_param.p.seg_lf_info[6]>>15 & 1),
7374 (vp9_param.p.seg_lf_info[7]>>15 & 1));
7375 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7376 (vp9_param.p.seg_lf_info[0] & 0x13f),
7377 (vp9_param.p.seg_lf_info[1] & 0x13f),
7378 (vp9_param.p.seg_lf_info[2] & 0x13f),
7379 (vp9_param.p.seg_lf_info[3] & 0x13f),
7380 (vp9_param.p.seg_lf_info[4] & 0x13f),
7381 (vp9_param.p.seg_lf_info[5] & 0x13f),
7382 (vp9_param.p.seg_lf_info[6] & 0x13f),
7383 (vp9_param.p.seg_lf_info[7] & 0x13f));
7384
7385}
7386
7387
7388static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7389{
7390 struct VP9_Common_s *const cm = &pbi->common;
7391 if (pbi->double_write_mode & 0x10)
7392 return;
7393 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7394 if (pbi->used_4k_num == -1) {
7395 pbi->used_4k_num =
7396 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7397 if (pbi->m_ins_flag)
7398 hevc_mmu_dma_check(hw_to_vdec(pbi));
7399 }
7400 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7401 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7402 cm->cur_fb_idx_mmu = INVALID_IDX;
7403 pbi->used_4k_num = -1;
7404 }
7405}
7406
7407#ifdef MULTI_INSTANCE_SUPPORT
7408static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7409{
7410 struct VP9_Common_s *const cm = &pbi->common;
7411 if (pbi->double_write_mode & 0x10)
7412 return;
7413 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7414 decoder_mmu_box_free_idx(pbi->mmu_box,
7415 cm->cur_fb_idx_mmu);
7416
7417 cm->cur_fb_idx_mmu = INVALID_IDX;
7418 pbi->used_4k_num = -1;
7419 }
7420}
7421#endif
7422
7423
7424static void dec_again_process(struct VP9Decoder_s *pbi)
7425{
7426 amhevc_stop();
7427 pbi->dec_result = DEC_RESULT_AGAIN;
7428 if (pbi->process_state ==
7429 PROC_STATE_DECODESLICE) {
7430 pbi->process_state =
7431 PROC_STATE_SENDAGAIN;
7432 if (pbi->mmu_enable)
7433 vp9_recycle_mmu_buf(pbi);
7434 }
7435 reset_process_time(pbi);
7436 vdec_schedule_work(&pbi->work);
7437}
7438
7439int continue_decoding(struct VP9Decoder_s *pbi)
7440{
7441 int ret;
7442 int i;
7443 struct VP9_Common_s *const cm = &pbi->common;
7444 debug_buffer_mgr_more(pbi);
7445
7446 bit_depth_luma = vp9_param.p.bit_depth;
7447 bit_depth_chroma = vp9_param.p.bit_depth;
7448
7449 if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7450 (get_double_write_mode(pbi) == 0x10)) {
7451 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7452 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7453 vp9_param.p.bit_depth);
7454 return -1;
7455 }
7456
7457 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7458 ret = vp9_bufmgr_process(pbi, &vp9_param);
7459 if (!pbi->m_ins_flag)
7460 pbi->slice_idx++;
7461 } else {
7462 union param_u *params = &vp9_param;
7463 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7464 ret = vp9_alloc_mmu(pbi,
7465 cm->new_fb_idx,
7466 params->p.width,
7467 params->p.height,
7468 params->p.bit_depth,
7469 pbi->frame_mmu_map_addr);
7470 if (ret >= 0)
7471 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7472 else
7473 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7474 cm->new_fb_idx,
7475 ret);
7476 } else {
7477 ret = 0;
7478 }
7479 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7480 (params->p.height << 16) | params->p.width);
7481 }
7482 if (ret < 0) {
7483 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7484 ret);
7485 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7486 cm->show_frame = 0;
7487 if (pbi->mmu_enable)
7488 vp9_recycle_mmu_buf(pbi);
7489#ifdef MULTI_INSTANCE_SUPPORT
7490 if (pbi->m_ins_flag) {
7491 pbi->dec_result = DEC_RESULT_DONE;
7492#ifdef SUPPORT_FB_DECODING
7493 if (pbi->used_stage_buf_num == 0)
7494#endif
7495 amhevc_stop();
7496 vdec_schedule_work(&pbi->work);
7497 }
7498#endif
7499 return ret;
7500 } else if (ret == 0) {
7501 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7502 = &cm->cur_frame->buf;
7503 cur_pic_config->decode_idx = pbi->frame_count;
7504
7505 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7506 if (!pbi->m_ins_flag) {
7507 pbi->frame_count++;
7508 decode_frame_count[pbi->index]
7509 = pbi->frame_count;
7510 }
7511#ifdef MULTI_INSTANCE_SUPPORT
7512 if (pbi->chunk) {
7513 cur_pic_config->pts = pbi->chunk->pts;
7514 cur_pic_config->pts64 = pbi->chunk->pts64;
7515 cur_pic_config->timestamp = pbi->chunk->timestamp;
7516 }
7517#endif
7518 }
7519 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7520 config_pic_size(pbi, vp9_param.p.bit_depth);
7521
7522 if ((pbi->common.frame_type != KEY_FRAME)
7523 && (!pbi->common.intra_only)) {
7524 config_mc_buffer(pbi, vp9_param.p.bit_depth);
7525#ifdef SUPPORT_FB_DECODING
7526 if (pbi->used_stage_buf_num == 0)
7527#endif
7528 config_mpred_hw(pbi);
7529 } else {
7530#ifdef SUPPORT_FB_DECODING
7531 if (pbi->used_stage_buf_num == 0)
7532#endif
7533 clear_mpred_hw(pbi);
7534 }
7535#ifdef MCRCC_ENABLE
7536 if (mcrcc_cache_alg_flag)
7537 config_mcrcc_axi_hw_new(pbi);
7538 else
7539 config_mcrcc_axi_hw(pbi);
7540#endif
7541 config_sao_hw(pbi, &vp9_param);
7542
7543#ifdef VP9_LPF_LVL_UPDATE
7544 /*
7545 * Get loop filter related picture level parameters from Parser
7546 */
7547 pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7548 pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7549 for (i = 0; i < 4; i++)
7550 pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7551 for (i = 0; i < 2; i++)
7552 pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7553 pbi->default_filt_lvl = vp9_param.p.filter_level;
7554 pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7555 pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7556 for (i = 0; i < MAX_SEGMENTS; i++)
7557 pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7558 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7559 for (i = 0; i < MAX_SEGMENTS; i++)
7560 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7561 = (vp9_param.p.seg_lf_info[i]
7562 & 0x100) ? -(vp9_param.p.seg_lf_info[i]
7563 & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7564 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7565 /*Set pipeline mode*/
7566 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7567 /*dblk pipeline mode=1 for performance*/
7568 if (vp9_param.p.width >= 1280)
7569 lpf_data32 |= (0x1 << 4);
7570 else
7571 lpf_data32 &= ~(0x3 << 4);
7572 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7573 }
7574 /*
7575 * Update loop filter Thr/Lvl table for every frame
7576 */
7577 /*pr_info
7578 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7579 vp9_loop_filter_frame_init(pbi->seg_4lf,
7580 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7581#endif
7582 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7583 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7584 } else {
7585 pr_info("Skip search next start code\n");
7586 cm->prev_fb_idx = INVALID_IDX;
7587 /*skip, search next start code*/
7588 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7589 }
7590 pbi->process_state = PROC_STATE_DECODESLICE;
7591 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7592 if (pbi->last_put_idx < pbi->used_buf_num) {
7593 struct RefCntBuffer_s *frame_bufs =
7594 cm->buffer_pool->frame_bufs;
7595 int i = pbi->last_put_idx;
7596 /*free not used buffers.*/
7597 if ((frame_bufs[i].ref_count == 0) &&
7598 (frame_bufs[i].buf.vf_ref == 0) &&
7599 (frame_bufs[i].buf.index != -1)) {
7600 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7601 }
7602 pbi->last_put_idx = -1;
7603 }
7604 }
7605 return ret;
7606}
7607
7608static void fill_frame_info(struct VP9Decoder_s *pbi,
7609 struct PIC_BUFFER_CONFIG_s *frame,
7610 unsigned int framesize,
7611 unsigned int pts)
7612{
7613 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7614
7615 if (frame->slice_type == KEY_FRAME)
7616 vframe_qos->type = 1;
7617 else if (frame->slice_type == INTER_FRAME)
7618 vframe_qos->type = 2;
7619/*
7620#define SHOW_QOS_INFO
7621*/
7622 vframe_qos->size = framesize;
7623 vframe_qos->pts = pts;
7624#ifdef SHOW_QOS_INFO
7625 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7626#endif
7627 vframe_qos->max_mv = frame->max_mv;
7628 vframe_qos->avg_mv = frame->avg_mv;
7629 vframe_qos->min_mv = frame->min_mv;
7630#ifdef SHOW_QOS_INFO
7631 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7632 vframe_qos->max_mv,
7633 vframe_qos->avg_mv,
7634 vframe_qos->min_mv);
7635#endif
7636 vframe_qos->max_qp = frame->max_qp;
7637 vframe_qos->avg_qp = frame->avg_qp;
7638 vframe_qos->min_qp = frame->min_qp;
7639#ifdef SHOW_QOS_INFO
7640 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7641 vframe_qos->max_qp,
7642 vframe_qos->avg_qp,
7643 vframe_qos->min_qp);
7644#endif
7645 vframe_qos->max_skip = frame->max_skip;
7646 vframe_qos->avg_skip = frame->avg_skip;
7647 vframe_qos->min_skip = frame->min_skip;
7648#ifdef SHOW_QOS_INFO
7649 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7650 vframe_qos->max_skip,
7651 vframe_qos->avg_skip,
7652 vframe_qos->min_skip);
7653#endif
7654 vframe_qos->num++;
7655
7656 if (pbi->frameinfo_enable)
7657 vdec_fill_frame_info(vframe_qos, 1);
7658}
7659
7660/* only when we decoded one field or one frame,
7661we can call this function to get qos info*/
7662static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7663{
7664 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7665
7666 if (!frame)
7667 return;
7668
7669 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7670 unsigned char a[3];
7671 unsigned char i, j, t;
7672 unsigned long data;
7673
7674 data = READ_VREG(HEVC_MV_INFO);
7675 if (frame->slice_type == KEY_FRAME)
7676 data = 0;
7677 a[0] = data & 0xff;
7678 a[1] = (data >> 8) & 0xff;
7679 a[2] = (data >> 16) & 0xff;
7680
7681 for (i = 0; i < 3; i++) {
7682 for (j = i+1; j < 3; j++) {
7683 if (a[j] < a[i]) {
7684 t = a[j];
7685 a[j] = a[i];
7686 a[i] = t;
7687 } else if (a[j] == a[i]) {
7688 a[i]++;
7689 t = a[j];
7690 a[j] = a[i];
7691 a[i] = t;
7692 }
7693 }
7694 }
7695 frame->max_mv = a[2];
7696 frame->avg_mv = a[1];
7697 frame->min_mv = a[0];
7698
7699 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7700 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7701 data, a[0], a[1], a[2]);
7702
7703 data = READ_VREG(HEVC_QP_INFO);
7704 a[0] = data & 0x1f;
7705 a[1] = (data >> 8) & 0x3f;
7706 a[2] = (data >> 16) & 0x7f;
7707
7708 for (i = 0; i < 3; i++) {
7709 for (j = i+1; j < 3; j++) {
7710 if (a[j] < a[i]) {
7711 t = a[j];
7712 a[j] = a[i];
7713 a[i] = t;
7714 } else if (a[j] == a[i]) {
7715 a[i]++;
7716 t = a[j];
7717 a[j] = a[i];
7718 a[i] = t;
7719 }
7720 }
7721 }
7722 frame->max_qp = a[2];
7723 frame->avg_qp = a[1];
7724 frame->min_qp = a[0];
7725
7726 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7727 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7728 data, a[0], a[1], a[2]);
7729
7730 data = READ_VREG(HEVC_SKIP_INFO);
7731 a[0] = data & 0x1f;
7732 a[1] = (data >> 8) & 0x3f;
7733 a[2] = (data >> 16) & 0x7f;
7734
7735 for (i = 0; i < 3; i++) {
7736 for (j = i+1; j < 3; j++) {
7737 if (a[j] < a[i]) {
7738 t = a[j];
7739 a[j] = a[i];
7740 a[i] = t;
7741 } else if (a[j] == a[i]) {
7742 a[i]++;
7743 t = a[j];
7744 a[j] = a[i];
7745 a[i] = t;
7746 }
7747 }
7748 }
7749 frame->max_skip = a[2];
7750 frame->avg_skip = a[1];
7751 frame->min_skip = a[0];
7752
7753 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7754 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7755 data, a[0], a[1], a[2]);
7756 } else {
7757 uint32_t blk88_y_count;
7758 uint32_t blk88_c_count;
7759 uint32_t blk22_mv_count;
7760 uint32_t rdata32;
7761 int32_t mv_hi;
7762 int32_t mv_lo;
7763 uint32_t rdata32_l;
7764 uint32_t mvx_L0_hi;
7765 uint32_t mvy_L0_hi;
7766 uint32_t mvx_L1_hi;
7767 uint32_t mvy_L1_hi;
7768 int64_t value;
7769 uint64_t temp_value;
7770 int pic_number = frame->decode_idx;
7771
7772 frame->max_mv = 0;
7773 frame->avg_mv = 0;
7774 frame->min_mv = 0;
7775
7776 frame->max_skip = 0;
7777 frame->avg_skip = 0;
7778 frame->min_skip = 0;
7779
7780 frame->max_qp = 0;
7781 frame->avg_qp = 0;
7782 frame->min_qp = 0;
7783
7784 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7785 frame->slice_type,
7786 pic_number);
7787
7788 /* set rd_idx to 0 */
7789 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7790
7791 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7792 if (blk88_y_count == 0) {
7793
7794 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7795 "[Picture %d Quality] NO Data yet.\n",
7796 pic_number);
7797
7798 /* reset all counts */
7799 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7800 return;
7801 }
7802 /* qp_y_sum */
7803 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7804
7805 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7806 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7807 pic_number, rdata32/blk88_y_count,
7808 rdata32, blk88_y_count);
7809
7810 frame->avg_qp = rdata32/blk88_y_count;
7811 /* intra_y_count */
7812 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7813
7814 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7815 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7816 pic_number, rdata32*100/blk88_y_count,
7817 '%', rdata32);
7818
7819 /* skipped_y_count */
7820 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7821
7822 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7823 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7824 pic_number, rdata32*100/blk88_y_count,
7825 '%', rdata32);
7826
7827 frame->avg_skip = rdata32*100/blk88_y_count;
7828 /* coeff_non_zero_y_count */
7829 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7830
7831 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7832 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7833 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7834 '%', rdata32);
7835
7836 /* blk66_c_count */
7837 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7838 if (blk88_c_count == 0) {
7839 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7840 "[Picture %d Quality] NO Data yet.\n",
7841 pic_number);
7842 /* reset all counts */
7843 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7844 return;
7845 }
7846 /* qp_c_sum */
7847 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7848
7849 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7850 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7851 pic_number, rdata32/blk88_c_count,
7852 rdata32, blk88_c_count);
7853
7854 /* intra_c_count */
7855 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7856
7857 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7858 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7859 pic_number, rdata32*100/blk88_c_count,
7860 '%', rdata32);
7861
7862 /* skipped_cu_c_count */
7863 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7864
7865 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7866 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7867 pic_number, rdata32*100/blk88_c_count,
7868 '%', rdata32);
7869
7870 /* coeff_non_zero_c_count */
7871 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7872
7873 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7874 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7875 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7876 '%', rdata32);
7877
7878 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7879 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7880 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7881
7882 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7883 "[Picture %d Quality] Y QP min : %d\n",
7884 pic_number, (rdata32>>0)&0xff);
7885
7886 frame->min_qp = (rdata32>>0)&0xff;
7887
7888 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7889 "[Picture %d Quality] Y QP max : %d\n",
7890 pic_number, (rdata32>>8)&0xff);
7891
7892 frame->max_qp = (rdata32>>8)&0xff;
7893
7894 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7895 "[Picture %d Quality] C QP min : %d\n",
7896 pic_number, (rdata32>>16)&0xff);
7897 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7898 "[Picture %d Quality] C QP max : %d\n",
7899 pic_number, (rdata32>>24)&0xff);
7900
7901 /* blk22_mv_count */
7902 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7903 if (blk22_mv_count == 0) {
7904 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7905 "[Picture %d Quality] NO MV Data yet.\n",
7906 pic_number);
7907 /* reset all counts */
7908 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7909 return;
7910 }
7911 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7912 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7913 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7914 /* should all be 0x00 or 0xff */
7915 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7916 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7917 pic_number, rdata32);
7918
7919 mvx_L0_hi = ((rdata32>>0)&0xff);
7920 mvy_L0_hi = ((rdata32>>8)&0xff);
7921 mvx_L1_hi = ((rdata32>>16)&0xff);
7922 mvy_L1_hi = ((rdata32>>24)&0xff);
7923
7924 /* mvx_L0_count[31:0] */
7925 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7926 temp_value = mvx_L0_hi;
7927 temp_value = (temp_value << 32) | rdata32_l;
7928
7929 if (mvx_L0_hi & 0x80)
7930 value = 0xFFFFFFF000000000 | temp_value;
7931 else
7932 value = temp_value;
7933
7934 value = div_s64(value, blk22_mv_count);
7935
7936 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7937 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7938 pic_number, (int)value,
7939 value, blk22_mv_count);
7940
7941 frame->avg_mv = value;
7942
7943 /* mvy_L0_count[31:0] */
7944 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7945 temp_value = mvy_L0_hi;
7946 temp_value = (temp_value << 32) | rdata32_l;
7947
7948 if (mvy_L0_hi & 0x80)
7949 value = 0xFFFFFFF000000000 | temp_value;
7950 else
7951 value = temp_value;
7952
7953 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7954 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7955 pic_number, rdata32_l/blk22_mv_count,
7956 value, blk22_mv_count);
7957
7958 /* mvx_L1_count[31:0] */
7959 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7960 temp_value = mvx_L1_hi;
7961 temp_value = (temp_value << 32) | rdata32_l;
7962 if (mvx_L1_hi & 0x80)
7963 value = 0xFFFFFFF000000000 | temp_value;
7964 else
7965 value = temp_value;
7966
7967 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7968 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
7969 pic_number, rdata32_l/blk22_mv_count,
7970 value, blk22_mv_count);
7971
7972 /* mvy_L1_count[31:0] */
7973 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7974 temp_value = mvy_L1_hi;
7975 temp_value = (temp_value << 32) | rdata32_l;
7976 if (mvy_L1_hi & 0x80)
7977 value = 0xFFFFFFF000000000 | temp_value;
7978 else
7979 value = temp_value;
7980
7981 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7982 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
7983 pic_number, rdata32_l/blk22_mv_count,
7984 value, blk22_mv_count);
7985
7986 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
7987 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7988 mv_hi = (rdata32>>16)&0xffff;
7989 if (mv_hi & 0x8000)
7990 mv_hi = 0x8000 - mv_hi;
7991
7992 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7993 "[Picture %d Quality] MVX_L0 MAX : %d\n",
7994 pic_number, mv_hi);
7995
7996 frame->max_mv = mv_hi;
7997
7998 mv_lo = (rdata32>>0)&0xffff;
7999 if (mv_lo & 0x8000)
8000 mv_lo = 0x8000 - mv_lo;
8001
8002 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8003 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8004 pic_number, mv_lo);
8005
8006 frame->min_mv = mv_lo;
8007
8008 /* {mvy_L0_max, mvy_L0_min} */
8009 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8010 mv_hi = (rdata32>>16)&0xffff;
8011 if (mv_hi & 0x8000)
8012 mv_hi = 0x8000 - mv_hi;
8013
8014 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8015 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8016 pic_number, mv_hi);
8017
8018 mv_lo = (rdata32>>0)&0xffff;
8019 if (mv_lo & 0x8000)
8020 mv_lo = 0x8000 - mv_lo;
8021
8022 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8023 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8024 pic_number, mv_lo);
8025
8026 /* {mvx_L1_max, mvx_L1_min} */
8027 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8028 mv_hi = (rdata32>>16)&0xffff;
8029 if (mv_hi & 0x8000)
8030 mv_hi = 0x8000 - mv_hi;
8031
8032 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8033 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8034 pic_number, mv_hi);
8035
8036 mv_lo = (rdata32>>0)&0xffff;
8037 if (mv_lo & 0x8000)
8038 mv_lo = 0x8000 - mv_lo;
8039
8040 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8041 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8042 pic_number, mv_lo);
8043
8044 /* {mvy_L1_max, mvy_L1_min} */
8045 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8046 mv_hi = (rdata32>>16)&0xffff;
8047 if (mv_hi & 0x8000)
8048 mv_hi = 0x8000 - mv_hi;
8049
8050 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8051 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8052 pic_number, mv_hi);
8053
8054 mv_lo = (rdata32>>0)&0xffff;
8055 if (mv_lo & 0x8000)
8056 mv_lo = 0x8000 - mv_lo;
8057
8058 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8059 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8060 pic_number, mv_lo);
8061
8062 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8063
8064 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8065 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8066 pic_number, rdata32);
8067
8068 /* reset all counts */
8069 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8070 }
8071}
8072
8073static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8074{
8075 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8076 unsigned int dec_status = pbi->dec_status;
8077 int i;
8078
8079 /*if (pbi->wait_buf)
8080 * pr_info("set wait_buf to 0\r\n");
8081 */
8082 if (pbi->eos)
8083 return IRQ_HANDLED;
8084 pbi->wait_buf = 0;
8085#ifdef MULTI_INSTANCE_SUPPORT
8086#ifdef SUPPORT_FB_DECODING
8087#ifdef FB_DECODING_TEST_SCHEDULE
8088 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8089 dec_status = HEVC_DECPIC_DATA_DONE;
8090 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8091 && dec_status == HEVC_DECPIC_DATA_DONE)
8092 dec_status = HEVC_S2_DECODING_DONE;
8093 pbi->s1_test_cmd = TEST_SET_NONE;
8094#else
8095 /*if (irq != VDEC_IRQ_0)
8096 dec_status = HEVC_S2_DECODING_DONE;*/
8097#endif
8098 if (dec_status == HEVC_S2_DECODING_DONE) {
8099 pbi->dec_result = DEC_RESULT_DONE;
8100 vdec_schedule_work(&pbi->work);
8101#ifdef FB_DECODING_TEST_SCHEDULE
8102 amhevc_stop();
8103 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8104 vdec_schedule_work(&pbi->s1_work);
8105#endif
8106 } else
8107#endif
8108 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8109 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8110 (dec_status == HEVC_DECODE_BUFEMPTY)
8111 ) {
8112 if (pbi->m_ins_flag) {
8113 reset_process_time(pbi);
8114 if (!vdec_frame_based(hw_to_vdec(pbi)))
8115 dec_again_process(pbi);
8116 else {
8117 pbi->dec_result = DEC_RESULT_GET_DATA;
8118 vdec_schedule_work(&pbi->work);
8119 }
8120 }
8121 pbi->process_busy = 0;
8122 return IRQ_HANDLED;
8123 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8124 if (pbi->m_ins_flag) {
8125 get_picture_qos_info(pbi);
8126#ifdef SUPPORT_FB_DECODING
8127 if (pbi->used_stage_buf_num > 0) {
8128 reset_process_time(pbi);
8129 inc_s1_pos(pbi);
8130 trigger_schedule(pbi);
8131#ifdef FB_DECODING_TEST_SCHEDULE
8132 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8133#else
8134 amhevc_stop();
8135 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8136 vdec_schedule_work(&pbi->s1_work);
8137#endif
8138 } else
8139#endif
8140 {
8141 reset_process_time(pbi);
8142 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8143 vp9_bufmgr_postproc(pbi);
8144
8145 pbi->dec_result = DEC_RESULT_DONE;
8146 amhevc_stop();
8147 if (mcrcc_cache_alg_flag)
8148 dump_hit_rate(pbi);
8149 vdec_schedule_work(&pbi->work);
8150 }
8151 } else {
8152 if (pbi->low_latency_flag) {
8153 vp9_bufmgr_postproc(pbi);
8154 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8155#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8156 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8157 if (debug & PRINT_FLAG_VDEC_DETAIL)
8158 pr_info("%s VP9 frame done \n", __func__);
8159#endif
8160 }
8161 }
8162
8163 pbi->process_busy = 0;
8164 return IRQ_HANDLED;
8165 }
8166#endif
8167
8168 if (dec_status == VP9_EOS) {
8169#ifdef MULTI_INSTANCE_SUPPORT
8170 if (pbi->m_ins_flag)
8171 reset_process_time(pbi);
8172#endif
8173
8174 pr_info("VP9_EOS, flush buffer\r\n");
8175
8176 vp9_bufmgr_postproc(pbi);
8177
8178 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8179 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8180 pbi->process_busy = 0;
8181#ifdef MULTI_INSTANCE_SUPPORT
8182 if (pbi->m_ins_flag) {
8183 pbi->dec_result = DEC_RESULT_DONE;
8184 amhevc_stop();
8185 vdec_schedule_work(&pbi->work);
8186 }
8187#endif
8188 return IRQ_HANDLED;
8189 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8190 pr_info("vp9 decode oversize !!\n");
8191 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8192 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8193 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8194#ifdef MULTI_INSTANCE_SUPPORT
8195 if (pbi->m_ins_flag)
8196 reset_process_time(pbi);
8197#endif
8198 return IRQ_HANDLED;
8199 }
8200
8201 if (dec_status != VP9_HEAD_PARSER_DONE) {
8202 pbi->process_busy = 0;
8203 return IRQ_HANDLED;
8204 }
8205
8206
8207#ifdef MULTI_INSTANCE_SUPPORT
8208#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8209 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8210 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8211 if (debug & PRINT_FLAG_VDEC_DETAIL)
8212 pr_info("%s VP9 frame header found \n", __func__);
8213 }
8214#endif
8215 if (pbi->m_ins_flag)
8216 reset_process_time(pbi);
8217#endif
8218 if (pbi->process_state != PROC_STATE_SENDAGAIN
8219#ifdef SUPPORT_FB_DECODING
8220 && pbi->used_stage_buf_num == 0
8221#endif
8222 ) {
8223 if (pbi->mmu_enable)
8224 vp9_recycle_mmu_buf_tail(pbi);
8225
8226
8227 if (pbi->frame_count > 0)
8228 vp9_bufmgr_postproc(pbi);
8229 }
8230
8231 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8232 get_rpm_param(&vp9_param);
8233 } else {
8234#ifdef SUPPORT_FB_DECODING
8235 if (pbi->used_stage_buf_num > 0) {
8236 reset_process_time(pbi);
8237 get_s1_buf(pbi);
8238
8239 if (get_mv_buf(pbi,
8240 &pbi->s1_mv_buf_index,
8241 &pbi->s1_mpred_mv_wr_start_addr
8242 ) < 0) {
8243 vp9_print(pbi, 0,
8244 "%s: Error get_mv_buf fail\n",
8245 __func__);
8246 }
8247
8248 if (pbi->s1_buf == NULL) {
8249 vp9_print(pbi, 0,
8250 "%s: Error get_s1_buf fail\n",
8251 __func__);
8252 pbi->process_busy = 0;
8253 return IRQ_HANDLED;
8254 }
8255
8256 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8257 int ii;
8258 for (ii = 0; ii < 4; ii++) {
8259 pbi->s1_buf->rpm[i + 3 - ii] =
8260 pbi->rpm_ptr[i + 3 - ii];
8261 pbi->s1_param.l.data[i + ii] =
8262 pbi->rpm_ptr[i + 3 - ii];
8263 }
8264 }
8265
8266 mpred_process(pbi);
8267#ifdef FB_DECODING_TEST_SCHEDULE
8268 pbi->dec_s1_result =
8269 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8270 vdec_schedule_work(&pbi->s1_work);
8271#else
8272 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8273 pbi->stage_mmu_map_phy_addr +
8274 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8275
8276 start_s1_decoding(pbi);
8277#endif
8278 start_process_time(pbi);
8279 pbi->process_busy = 0;
8280 return IRQ_HANDLED;
8281 } else
8282#endif
8283 {
8284 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8285 int ii;
8286 for (ii = 0; ii < 4; ii++)
8287 vp9_param.l.data[i + ii] =
8288 pbi->rpm_ptr[i + 3 - ii];
8289 }
8290 }
8291 }
8292
8293 if (pbi->is_used_v4l) {
8294 struct aml_vcodec_ctx *ctx =
8295 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8296
8297 pbi->frame_width = vp9_param.p.width;
8298 pbi->frame_height = vp9_param.p.height;
8299 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8300 struct aml_vdec_pic_infos info;
8301
8302 info.visible_width = pbi->frame_width;
8303 info.visible_height = pbi->frame_height;
8304 info.coded_width = ALIGN(pbi->frame_width, 32);
8305 info.coded_height = ALIGN(pbi->frame_height, 32);
8306 info.dpb_size = pbi->used_buf_num;
8307 pbi->v4l_params_parsed = true;
8308 vdec_v4l_set_pic_infos(ctx, &info);
8309 }
8310 }
8311
8312 if (pbi->is_used_v4l) {
8313 pbi->dec_result = DEC_V4L2_CONTINUE_DECODING;
8314 vdec_schedule_work(&pbi->work);
8315 } else {
8316 continue_decoding(pbi);
8317 pbi->postproc_done = 0;
8318 pbi->process_busy = 0;
8319 }
8320
8321#ifdef MULTI_INSTANCE_SUPPORT
8322 if (pbi->m_ins_flag)
8323 start_process_time(pbi);
8324#endif
8325
8326 return IRQ_HANDLED;
8327}
8328
8329static irqreturn_t vvp9_isr(int irq, void *data)
8330{
8331 int i;
8332 unsigned int dec_status;
8333 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8334 unsigned int adapt_prob_status;
8335 struct VP9_Common_s *const cm = &pbi->common;
8336 uint debug_tag;
8337
8338 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8339
8340 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8341 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8342 if (!pbi)
8343 return IRQ_HANDLED;
8344 if (pbi->init_flag == 0)
8345 return IRQ_HANDLED;
8346 if (pbi->process_busy)/*on process.*/
8347 return IRQ_HANDLED;
8348 pbi->dec_status = dec_status;
8349 pbi->process_busy = 1;
8350 if (debug & VP9_DEBUG_BUFMGR)
8351 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8352 irq,
8353 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8354 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8355 READ_VREG(HEVC_STREAM_START_ADDR),
8356 READ_VREG(HEVC_STREAM_END_ADDR),
8357 READ_VREG(HEVC_STREAM_LEVEL),
8358 READ_VREG(HEVC_STREAM_WR_PTR),
8359 READ_VREG(HEVC_STREAM_RD_PTR)
8360 );
8361#ifdef SUPPORT_FB_DECODING
8362 /*if (irq != VDEC_IRQ_0)
8363 return IRQ_WAKE_THREAD;*/
8364#endif
8365
8366 debug_tag = READ_HREG(DEBUG_REG1);
8367 if (debug_tag & 0x10000) {
8368 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8369 for (i = 0; i < 0x400; i += 4) {
8370 int ii;
8371 if ((i & 0xf) == 0)
8372 pr_info("%03x: ", i);
8373 for (ii = 0; ii < 4; ii++) {
8374 pr_info("%04x ",
8375 pbi->lmem_ptr[i + 3 - ii]);
8376 }
8377 if (((i + ii) & 0xf) == 0)
8378 pr_info("\n");
8379 }
8380
8381 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8382 (udebug_pause_decode_idx == 0 ||
8383 udebug_pause_decode_idx == pbi->slice_idx) &&
8384 (udebug_pause_val == 0 ||
8385 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8386 pbi->ucode_pause_pos = udebug_pause_pos;
8387 else if (debug_tag & 0x20000)
8388 pbi->ucode_pause_pos = 0xffffffff;
8389 if (pbi->ucode_pause_pos)
8390 reset_process_time(pbi);
8391 else
8392 WRITE_HREG(DEBUG_REG1, 0);
8393 } else if (debug_tag != 0) {
8394 pr_info(
8395 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8396 READ_HREG(DEBUG_REG2),
8397 READ_VREG(HEVC_PARSER_LCU_START));
8398 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8399 (udebug_pause_decode_idx == 0 ||
8400 udebug_pause_decode_idx == pbi->slice_idx) &&
8401 (udebug_pause_val == 0 ||
8402 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8403 pbi->ucode_pause_pos = udebug_pause_pos;
8404 if (pbi->ucode_pause_pos)
8405 reset_process_time(pbi);
8406 else
8407 WRITE_HREG(DEBUG_REG1, 0);
8408 pbi->process_busy = 0;
8409 return IRQ_HANDLED;
8410 }
8411
8412#ifdef MULTI_INSTANCE_SUPPORT
8413 if (!pbi->m_ins_flag) {
8414#endif
8415 if (pbi->error_flag == 1) {
8416 pbi->error_flag = 2;
8417 pbi->process_busy = 0;
8418 return IRQ_HANDLED;
8419 } else if (pbi->error_flag == 3) {
8420 pbi->process_busy = 0;
8421 return IRQ_HANDLED;
8422 }
8423
8424 if (get_free_buf_count(pbi) <= 0) {
8425 /*
8426 if (pbi->wait_buf == 0)
8427 pr_info("set wait_buf to 1\r\n");
8428 */
8429 pbi->wait_buf = 1;
8430 pbi->process_busy = 0;
8431 return IRQ_HANDLED;
8432 }
8433#ifdef MULTI_INSTANCE_SUPPORT
8434 }
8435#endif
8436 if ((adapt_prob_status & 0xff) == 0xfd) {
8437 /*VP9_REQ_ADAPT_PROB*/
8438 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8439 uint8_t *prev_prob_b =
8440 ((uint8_t *)pbi->prob_buffer_addr) +
8441 ((adapt_prob_status >> 8) * 0x1000);
8442 uint8_t *cur_prob_b =
8443 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8444 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8445#ifdef MULTI_INSTANCE_SUPPORT
8446 if (pbi->m_ins_flag)
8447 reset_process_time(pbi);
8448#endif
8449 adapt_coef_probs(pbi->pic_count,
8450 (cm->last_frame_type == KEY_FRAME),
8451 pre_fc, (adapt_prob_status >> 8),
8452 (unsigned int *)prev_prob_b,
8453 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8454
8455 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8456 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8457 pbi->pic_count += 1;
8458#ifdef MULTI_INSTANCE_SUPPORT
8459 if (pbi->m_ins_flag)
8460 start_process_time(pbi);
8461#endif
8462
8463 /*return IRQ_HANDLED;*/
8464 }
8465 return IRQ_WAKE_THREAD;
8466}
8467
8468static void vp9_set_clk(struct work_struct *work)
8469{
8470 struct VP9Decoder_s *pbi = container_of(work,
8471 struct VP9Decoder_s, set_clk_work);
8472 int fps = 96000 / pbi->frame_dur;
8473
8474 if (hevc_source_changed(VFORMAT_VP9,
8475 frame_width, frame_height, fps) > 0)
8476 pbi->saved_resolution = frame_width *
8477 frame_height * fps;
8478}
8479
8480static void vvp9_put_timer_func(unsigned long arg)
8481{
8482 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8483 struct timer_list *timer = &pbi->timer;
8484 uint8_t empty_flag;
8485 unsigned int buf_level;
8486
8487 enum receviver_start_e state = RECEIVER_INACTIVE;
8488
8489 if (pbi->m_ins_flag) {
8490 if (hw_to_vdec(pbi)->next_status
8491 == VDEC_STATUS_DISCONNECTED) {
8492#ifdef SUPPORT_FB_DECODING
8493 if (pbi->run2_busy)
8494 return;
8495
8496 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8497 vdec_schedule_work(&pbi->s1_work);
8498#endif
8499 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8500 vdec_schedule_work(&pbi->work);
8501 pr_debug(
8502 "vdec requested to be disconnected\n");
8503 return;
8504 }
8505 }
8506 if (pbi->init_flag == 0) {
8507 if (pbi->stat & STAT_TIMER_ARM) {
8508 timer->expires = jiffies + PUT_INTERVAL;
8509 add_timer(&pbi->timer);
8510 }
8511 return;
8512 }
8513 if (pbi->m_ins_flag == 0) {
8514 if (vf_get_receiver(pbi->provider_name)) {
8515 state =
8516 vf_notify_receiver(pbi->provider_name,
8517 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8518 NULL);
8519 if ((state == RECEIVER_STATE_NULL)
8520 || (state == RECEIVER_STATE_NONE))
8521 state = RECEIVER_INACTIVE;
8522 } else
8523 state = RECEIVER_INACTIVE;
8524
8525 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8526 /* error watchdog */
8527 if (empty_flag == 0) {
8528 /* decoder has input */
8529 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8530
8531 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8532 /* receiver has no buffer to recycle */
8533 if ((state == RECEIVER_INACTIVE) &&
8534 (kfifo_is_empty(&pbi->display_q) &&
8535 buf_level > 0x200)
8536 ) {
8537 WRITE_VREG
8538 (HEVC_ASSIST_MBOX0_IRQ_REG,
8539 0x1);
8540 }
8541 }
8542
8543 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8544 /* receiver has no buffer to recycle */
8545 /*if ((state == RECEIVER_INACTIVE) &&
8546 * (kfifo_is_empty(&pbi->display_q))) {
8547 *pr_info("vp9 something error,need reset\n");
8548 *}
8549 */
8550 }
8551 }
8552 }
8553#ifdef MULTI_INSTANCE_SUPPORT
8554 else {
8555 if (
8556 (decode_timeout_val > 0) &&
8557 (pbi->start_process_time > 0) &&
8558 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8559 > decode_timeout_val)
8560 ) {
8561 int current_lcu_idx =
8562 READ_VREG(HEVC_PARSER_LCU_START)
8563 & 0xffffff;
8564 if (pbi->last_lcu_idx == current_lcu_idx) {
8565 if (pbi->decode_timeout_count > 0)
8566 pbi->decode_timeout_count--;
8567 if (pbi->decode_timeout_count == 0) {
8568 if (input_frame_based(
8569 hw_to_vdec(pbi)) ||
8570 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8571 timeout_process(pbi);
8572 else {
8573 vp9_print(pbi, 0,
8574 "timeout & empty, again\n");
8575 dec_again_process(pbi);
8576 }
8577 }
8578 } else {
8579 start_process_time(pbi);
8580 pbi->last_lcu_idx = current_lcu_idx;
8581 }
8582 }
8583 }
8584#endif
8585
8586 if ((pbi->ucode_pause_pos != 0) &&
8587 (pbi->ucode_pause_pos != 0xffffffff) &&
8588 udebug_pause_pos != pbi->ucode_pause_pos) {
8589 pbi->ucode_pause_pos = 0;
8590 WRITE_HREG(DEBUG_REG1, 0);
8591 }
8592#ifdef MULTI_INSTANCE_SUPPORT
8593 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8594 pr_info(
8595 "Force Send Again\r\n");
8596 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8597 reset_process_time(pbi);
8598 pbi->dec_result = DEC_RESULT_AGAIN;
8599 if (pbi->process_state ==
8600 PROC_STATE_DECODESLICE) {
8601 if (pbi->mmu_enable)
8602 vp9_recycle_mmu_buf(pbi);
8603 pbi->process_state =
8604 PROC_STATE_SENDAGAIN;
8605 }
8606 amhevc_stop();
8607
8608 vdec_schedule_work(&pbi->work);
8609 }
8610
8611 if (debug & VP9_DEBUG_DUMP_DATA) {
8612 debug &= ~VP9_DEBUG_DUMP_DATA;
8613 vp9_print(pbi, 0,
8614 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8615 __func__,
8616 pbi->chunk->size,
8617 pbi->chunk->offset,
8618 get_data_check_sum(pbi, pbi->chunk->size)
8619 );
8620 dump_data(pbi, pbi->chunk->size);
8621 }
8622#endif
8623 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8624 dump_pic_list(pbi);
8625 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8626 }
8627 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8628 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8629 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8630 }
8631 /*if (debug & VP9_DEBUG_HW_RESET) {
8632 }*/
8633
8634 if (radr != 0) {
8635 if (rval != 0) {
8636 WRITE_VREG(radr, rval);
8637 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8638 } else
8639 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8640 rval = 0;
8641 radr = 0;
8642 }
8643 if (pop_shorts != 0) {
8644 int i;
8645 u32 sum = 0;
8646
8647 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8648 for (i = 0; i < pop_shorts; i++) {
8649 u32 data =
8650 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8651 WRITE_HREG(HEVC_SHIFT_COMMAND,
8652 (1<<7)|16);
8653 if ((i & 0xf) == 0)
8654 pr_info("%04x:", i);
8655 pr_info("%04x ", data);
8656 if (((i + 1) & 0xf) == 0)
8657 pr_info("\r\n");
8658 sum += data;
8659 }
8660 pr_info("\r\nsum = %x\r\n", sum);
8661 pop_shorts = 0;
8662 }
8663 if (dbg_cmd != 0) {
8664 if (dbg_cmd == 1) {
8665 u32 disp_laddr;
8666
8667 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8668 get_double_write_mode(pbi) == 0) {
8669 disp_laddr =
8670 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8671 } else {
8672 struct canvas_s cur_canvas;
8673
8674 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8675 & 0xff), &cur_canvas);
8676 disp_laddr = cur_canvas.addr;
8677 }
8678 pr_info("current displayed buffer address %x\r\n",
8679 disp_laddr);
8680 }
8681 dbg_cmd = 0;
8682 }
8683 /*don't changed at start.*/
8684 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8685 pbi->frame_dur > 0 && pbi->saved_resolution !=
8686 frame_width * frame_height *
8687 (96000 / pbi->frame_dur))
8688 vdec_schedule_work(&pbi->set_clk_work);
8689
8690 timer->expires = jiffies + PUT_INTERVAL;
8691 add_timer(timer);
8692}
8693
8694
8695int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8696{
8697 struct VP9Decoder_s *vp9 =
8698 (struct VP9Decoder_s *)vdec->private;
8699
8700 if (!vp9)
8701 return -1;
8702
8703 vstatus->frame_width = frame_width;
8704 vstatus->frame_height = frame_height;
8705 if (vp9->frame_dur != 0)
8706 vstatus->frame_rate = 96000 / vp9->frame_dur;
8707 else
8708 vstatus->frame_rate = -1;
8709 vstatus->error_count = 0;
8710 vstatus->status = vp9->stat | vp9->fatal_error;
8711 vstatus->frame_dur = vp9->frame_dur;
8712#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8713 vstatus->bit_rate = gvs->bit_rate;
8714 vstatus->frame_data = gvs->frame_data;
8715 vstatus->total_data = gvs->total_data;
8716 vstatus->frame_count = gvs->frame_count;
8717 vstatus->error_frame_count = gvs->error_frame_count;
8718 vstatus->drop_frame_count = gvs->drop_frame_count;
8719 vstatus->total_data = gvs->total_data;
8720 vstatus->samp_cnt = gvs->samp_cnt;
8721 vstatus->offset = gvs->offset;
8722 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8723 "%s", DRIVER_NAME);
8724#endif
8725 return 0;
8726}
8727
8728int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8729{
8730 is_reset = isreset;
8731 return 0;
8732}
8733
8734#if 0
8735static void VP9_DECODE_INIT(void)
8736{
8737 /* enable vp9 clocks */
8738 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8739 /* *************************************************************** */
8740 /* Power ON HEVC */
8741 /* *************************************************************** */
8742 /* Powerup HEVC */
8743 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8744 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8745 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8746 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8747 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8748 /* remove isolations */
8749 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8750 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8751
8752}
8753#endif
8754
8755static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8756{
8757 unsigned int data32;
8758 /* VP9_DECODE_INIT(); */
8759 vp9_config_work_space_hw(pbi, mask);
8760 if (mask & HW_MASK_BACK)
8761 init_pic_list_hw(pbi);
8762
8763 vp9_init_decoder_hw(pbi, mask);
8764
8765#ifdef VP9_LPF_LVL_UPDATE
8766 if (mask & HW_MASK_BACK)
8767 vp9_loop_filter_init(pbi);
8768#endif
8769
8770 if ((mask & HW_MASK_FRONT) == 0)
8771 return;
8772#if 1
8773 if (debug & VP9_DEBUG_BUFMGR_MORE)
8774 pr_info("%s\n", __func__);
8775 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8776 data32 = data32 |
8777 (1 << 0)/*stream_fetch_enable*/
8778 ;
8779 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8780
8781 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8782 if (debug & VP9_DEBUG_BUFMGR)
8783 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8784 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8785 data32 = data32 |
8786 (1 << 29) // stream_fifo_hole
8787 ;
8788 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8789 }
8790#if 0
8791 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8792 if (data32 != 0x00000100) {
8793 pr_info("vp9 prot init error %d\n", __LINE__);
8794 return;
8795 }
8796 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8797 if (data32 != 0x00000300) {
8798 pr_info("vp9 prot init error %d\n", __LINE__);
8799 return;
8800 }
8801 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8802 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8803 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8804 if (data32 != 0x12345678) {
8805 pr_info("vp9 prot init error %d\n", __LINE__);
8806 return;
8807 }
8808 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8809 if (data32 != 0x9abcdef0) {
8810 pr_info("vp9 prot init error %d\n", __LINE__);
8811 return;
8812 }
8813#endif
8814 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8815 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8816#endif
8817
8818
8819
8820 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8821
8822 /* WRITE_VREG(HEVC_MPSR, 1); */
8823
8824 /* clear mailbox interrupt */
8825 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8826
8827 /* enable mailbox interrupt */
8828 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8829
8830 /* disable PSCALE for hardware sharing */
8831 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8832
8833 WRITE_VREG(DEBUG_REG1, 0x0);
8834 /*check vps/sps/pps/i-slice in ucode*/
8835 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8836
8837 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8838#ifdef SUPPORT_FB_DECODING
8839#ifndef FB_DECODING_TEST_SCHEDULE
8840 if (pbi->used_stage_buf_num > 0) {
8841 if (mask & HW_MASK_FRONT) {
8842 data32 = READ_VREG(
8843 HEVC_ASSIST_HED_FB_W_CTL);
8844 data32 = data32 |
8845 (1 << 0) /*hed_fb_wr_en*/
8846 ;
8847 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8848 data32);
8849 }
8850 if (mask & HW_MASK_BACK) {
8851 data32 = READ_VREG(
8852 HEVC_ASSIST_HED_FB_R_CTL);
8853 while (data32 & (1 << 7)) {
8854 /*wait finish*/
8855 data32 = READ_VREG(
8856 HEVC_ASSIST_HED_FB_R_CTL);
8857 }
8858 data32 &= (~(0x1 << 0));
8859 /*hed_fb_rd_addr_auto_rd*/
8860 data32 &= (~(0x1 << 1));
8861 /*rd_id = 0, hed_rd_map_auto_halt_num,
8862 after wr 2 ready, then start reading*/
8863 data32 |= (0x2 << 16);
8864 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8865 data32);
8866
8867 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8868 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8869 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8870 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8871 data32);
8872 }
8873
8874 }
8875#endif
8876#endif
8877}
8878
8879static int vvp9_local_init(struct VP9Decoder_s *pbi)
8880{
8881 int i;
8882 int ret;
8883 int width, height;
8884 if (alloc_lf_buf(pbi) < 0)
8885 return -1;
8886
8887 pbi->gvs = vzalloc(sizeof(struct vdec_info));
8888 if (NULL == pbi->gvs) {
8889 pr_info("the struct of vdec status malloc failed.\n");
8890 return -1;
8891 }
8892#ifdef DEBUG_PTS
8893 pbi->pts_missed = 0;
8894 pbi->pts_hit = 0;
8895#endif
8896 pbi->new_frame_displayed = 0;
8897 pbi->last_put_idx = -1;
8898 pbi->saved_resolution = 0;
8899 pbi->get_frame_dur = false;
8900 on_no_keyframe_skiped = 0;
8901 pbi->duration_from_pts_done = 0;
8902 pbi->vp9_first_pts_ready = 0;
8903 pbi->frame_cnt_window = 0;
8904 width = pbi->vvp9_amstream_dec_info.width;
8905 height = pbi->vvp9_amstream_dec_info.height;
8906 pbi->frame_dur =
8907 (pbi->vvp9_amstream_dec_info.rate ==
8908 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8909 if (width && height)
8910 pbi->frame_ar = height * 0x100 / width;
8911/*
8912 *TODO:FOR VERSION
8913 */
8914 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8915 0, width, height, pbi->frame_dur);
8916
8917 if (pbi->frame_dur == 0)
8918 pbi->frame_dur = 96000 / 24;
8919
8920 INIT_KFIFO(pbi->display_q);
8921 INIT_KFIFO(pbi->newframe_q);
8922
8923
8924 for (i = 0; i < VF_POOL_SIZE; i++) {
8925 const struct vframe_s *vf = &pbi->vfpool[i];
8926
8927 pbi->vfpool[i].index = -1;
8928 kfifo_put(&pbi->newframe_q, vf);
8929 }
8930
8931
8932 ret = vp9_local_init(pbi);
8933
8934 if (!pbi->pts_unstable) {
8935 pbi->pts_unstable =
8936 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8937 pr_info("set pts unstable\n");
8938 }
8939
8940 return ret;
8941}
8942
8943
8944#ifdef MULTI_INSTANCE_SUPPORT
8945static s32 vvp9_init(struct vdec_s *vdec)
8946{
8947 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8948#else
8949static s32 vvp9_init(struct VP9Decoder_s *pbi)
8950{
8951#endif
8952 int ret;
8953 int fw_size = 0x1000 * 16;
8954 struct firmware_s *fw = NULL;
8955
8956 pbi->stat |= STAT_TIMER_INIT;
8957
8958 if (vvp9_local_init(pbi) < 0)
8959 return -EBUSY;
8960
8961 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8962 if (IS_ERR_OR_NULL(fw))
8963 return -ENOMEM;
8964
8965 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8966 pr_err("get firmware fail.\n");
8967 vfree(fw);
8968 return -1;
8969 }
8970
8971 fw->len = fw_size;
8972
8973 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
8974 init_timer(&pbi->timer);
8975
8976#ifdef MULTI_INSTANCE_SUPPORT
8977 if (pbi->m_ins_flag) {
8978 pbi->timer.data = (ulong) pbi;
8979 pbi->timer.function = vvp9_put_timer_func;
8980 pbi->timer.expires = jiffies + PUT_INTERVAL;
8981
8982 /*add_timer(&pbi->timer);
8983
8984 pbi->stat |= STAT_TIMER_ARM;
8985 pbi->stat |= STAT_ISR_REG;*/
8986
8987 INIT_WORK(&pbi->work, vp9_work);
8988#ifdef SUPPORT_FB_DECODING
8989 if (pbi->used_stage_buf_num > 0)
8990 INIT_WORK(&pbi->s1_work, vp9_s1_work);
8991#endif
8992 pbi->fw = fw;
8993
8994 /* picture list init.*/
8995 pbi->dec_result = DEC_INIT_PICLIST;
8996 vdec_schedule_work(&pbi->work);
8997
8998 return 0;
8999 }
9000#endif
9001 amhevc_enable();
9002
9003 init_pic_list(pbi);
9004
9005 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9006 if (ret < 0) {
9007 amhevc_disable();
9008 vfree(fw);
9009 pr_err("VP9: the %s fw loading failed, err: %x\n",
9010 tee_enabled() ? "TEE" : "local", ret);
9011 return -EBUSY;
9012 }
9013
9014 vfree(fw);
9015
9016 pbi->stat |= STAT_MC_LOAD;
9017
9018 /* enable AMRISC side protocol */
9019 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9020
9021 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9022 vvp9_isr,
9023 vvp9_isr_thread_fn,
9024 IRQF_ONESHOT,/*run thread on this irq disabled*/
9025 "vvp9-irq", (void *)pbi)) {
9026 pr_info("vvp9 irq register error.\n");
9027 amhevc_disable();
9028 return -ENOENT;
9029 }
9030
9031 pbi->stat |= STAT_ISR_REG;
9032
9033 pbi->provider_name = PROVIDER_NAME;
9034#ifdef MULTI_INSTANCE_SUPPORT
9035 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9036 &vvp9_vf_provider, pbi);
9037 vf_reg_provider(&vvp9_vf_prov);
9038 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9039 if (pbi->frame_dur != 0) {
9040 if (!is_reset)
9041 vf_notify_receiver(pbi->provider_name,
9042 VFRAME_EVENT_PROVIDER_FR_HINT,
9043 (void *)
9044 ((unsigned long)pbi->frame_dur));
9045 }
9046#else
9047 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9048 pbi);
9049 vf_reg_provider(&vvp9_vf_prov);
9050 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9051 if (!is_reset)
9052 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9053 (void *)((unsigned long)pbi->frame_dur));
9054#endif
9055 pbi->stat |= STAT_VF_HOOK;
9056
9057 pbi->timer.data = (ulong)pbi;
9058 pbi->timer.function = vvp9_put_timer_func;
9059 pbi->timer.expires = jiffies + PUT_INTERVAL;
9060
9061 pbi->stat |= STAT_VDEC_RUN;
9062
9063 add_timer(&pbi->timer);
9064
9065 pbi->stat |= STAT_TIMER_ARM;
9066
9067 amhevc_start();
9068
9069 pbi->init_flag = 1;
9070 pbi->process_busy = 0;
9071 pr_info("%d, vvp9_init, RP=0x%x\n",
9072 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9073 return 0;
9074}
9075
9076static int vmvp9_stop(struct VP9Decoder_s *pbi)
9077{
9078 pbi->init_flag = 0;
9079
9080 if (pbi->stat & STAT_VDEC_RUN) {
9081 amhevc_stop();
9082 pbi->stat &= ~STAT_VDEC_RUN;
9083 }
9084 if (pbi->stat & STAT_ISR_REG) {
9085 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9086 pbi->stat &= ~STAT_ISR_REG;
9087 }
9088 if (pbi->stat & STAT_TIMER_ARM) {
9089 del_timer_sync(&pbi->timer);
9090 pbi->stat &= ~STAT_TIMER_ARM;
9091 }
9092
9093 if (pbi->stat & STAT_VF_HOOK) {
9094 if (!is_reset)
9095 vf_notify_receiver(pbi->provider_name,
9096 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9097 NULL);
9098
9099 vf_unreg_provider(&vvp9_vf_prov);
9100 pbi->stat &= ~STAT_VF_HOOK;
9101 }
9102 vp9_local_uninit(pbi);
9103 reset_process_time(pbi);
9104 cancel_work_sync(&pbi->work);
9105#ifdef SUPPORT_FB_DECODING
9106 if (pbi->used_stage_buf_num > 0)
9107 cancel_work_sync(&pbi->s1_work);
9108#endif
9109 cancel_work_sync(&pbi->set_clk_work);
9110 uninit_mmu_buffers(pbi);
9111 if (pbi->fw)
9112 vfree(pbi->fw);
9113 pbi->fw = NULL;
9114 return 0;
9115}
9116
9117static int vvp9_stop(struct VP9Decoder_s *pbi)
9118{
9119
9120 pbi->init_flag = 0;
9121 pbi->first_sc_checked = 0;
9122 if (pbi->stat & STAT_VDEC_RUN) {
9123 amhevc_stop();
9124 pbi->stat &= ~STAT_VDEC_RUN;
9125 }
9126
9127 if (pbi->stat & STAT_ISR_REG) {
9128#ifdef MULTI_INSTANCE_SUPPORT
9129 if (!pbi->m_ins_flag)
9130#endif
9131 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9132 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9133 pbi->stat &= ~STAT_ISR_REG;
9134 }
9135
9136 if (pbi->stat & STAT_TIMER_ARM) {
9137 del_timer_sync(&pbi->timer);
9138 pbi->stat &= ~STAT_TIMER_ARM;
9139 }
9140
9141 if (pbi->stat & STAT_VF_HOOK) {
9142 if (!is_reset)
9143 vf_notify_receiver(pbi->provider_name,
9144 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9145 NULL);
9146
9147 vf_unreg_provider(&vvp9_vf_prov);
9148 pbi->stat &= ~STAT_VF_HOOK;
9149 }
9150 vp9_local_uninit(pbi);
9151
9152 cancel_work_sync(&pbi->set_clk_work);
9153#ifdef MULTI_INSTANCE_SUPPORT
9154 if (pbi->m_ins_flag) {
9155#ifdef SUPPORT_FB_DECODING
9156 if (pbi->used_stage_buf_num > 0)
9157 cancel_work_sync(&pbi->s1_work);
9158#endif
9159 cancel_work_sync(&pbi->work);
9160 } else
9161 amhevc_disable();
9162#else
9163 amhevc_disable();
9164#endif
9165 uninit_mmu_buffers(pbi);
9166
9167 vfree(pbi->fw);
9168 pbi->fw = NULL;
9169 return 0;
9170}
9171static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9172{
9173 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9174 CODEC_MM_FLAGS_TVP : 0;
9175 int buf_size = 48;
9176
9177 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9178 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9179 buf_size = 12;
9180 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9181 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9182 buf_size = 4;
9183 }
9184 pbi->need_cache_size = buf_size * SZ_1M;
9185 pbi->sc_start_time = get_jiffies_64();
9186 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9187 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9188 pbi->index, FRAME_BUFFERS,
9189 pbi->need_cache_size,
9190 tvp_flag
9191 );
9192 if (!pbi->mmu_box) {
9193 pr_err("vp9 alloc mmu box failed!!\n");
9194 return -1;
9195 }
9196 }
9197 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9198 DRIVER_NAME,
9199 pbi->index,
9200 MAX_BMMU_BUFFER_NUM,
9201 4 + PAGE_SHIFT,
9202 CODEC_MM_FLAGS_CMA_CLEAR |
9203 CODEC_MM_FLAGS_FOR_VDECODER |
9204 tvp_flag);
9205 if (!pbi->bmmu_box) {
9206 pr_err("vp9 alloc bmmu box failed!!\n");
9207 return -1;
9208 }
9209 return 0;
9210}
9211
9212static struct VP9Decoder_s *gHevc;
9213
9214static int amvdec_vp9_probe(struct platform_device *pdev)
9215{
9216 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9217 struct BUF_s BUF[MAX_BUF_NUM];
9218 struct VP9Decoder_s *pbi;
9219 int ret;
9220#ifndef MULTI_INSTANCE_SUPPORT
9221 int i;
9222#endif
9223 pr_debug("%s\n", __func__);
9224
9225 mutex_lock(&vvp9_mutex);
9226 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9227 if (pbi == NULL) {
9228 pr_info("\namvdec_vp9 device data allocation failed\n");
9229 mutex_unlock(&vvp9_mutex);
9230 return -ENOMEM;
9231 }
9232
9233 gHevc = pbi;
9234 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9235 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9236 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9237
9238 pbi->init_flag = 0;
9239 pbi->first_sc_checked= 0;
9240 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9241 vp9_max_pic_w = 8192;
9242 vp9_max_pic_h = 4608;
9243 }
9244 pbi->max_pic_w = vp9_max_pic_w;
9245 pbi->max_pic_h = vp9_max_pic_h;
9246
9247#ifdef MULTI_INSTANCE_SUPPORT
9248 pbi->eos = 0;
9249 pbi->start_process_time = 0;
9250 pbi->timeout_num = 0;
9251#endif
9252 pbi->fatal_error = 0;
9253 pbi->show_frame_num = 0;
9254 if (pdata == NULL) {
9255 pr_info("\namvdec_vp9 memory resource undefined.\n");
9256 vfree(pbi);
9257 mutex_unlock(&vvp9_mutex);
9258 return -EFAULT;
9259 }
9260 pbi->m_ins_flag = 0;
9261#ifdef MULTI_INSTANCE_SUPPORT
9262 pbi->platform_dev = pdev;
9263 platform_set_drvdata(pdev, pdata);
9264#endif
9265 pbi->double_write_mode = double_write_mode;
9266 pbi->mmu_enable = 1;
9267 if (amvdec_vp9_mmu_init(pbi) < 0) {
9268 vfree(pbi);
9269 mutex_unlock(&vvp9_mutex);
9270 pr_err("vp9 alloc bmmu box failed!!\n");
9271 return -1;
9272 }
9273
9274 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9275 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9276 if (ret < 0) {
9277 uninit_mmu_buffers(pbi);
9278 vfree(pbi);
9279 mutex_unlock(&vvp9_mutex);
9280 return ret;
9281 }
9282 pbi->buf_size = work_buf_size;
9283
9284#ifdef MULTI_INSTANCE_SUPPORT
9285 pbi->buf_start = pdata->mem_start;
9286#else
9287 if (!pbi->mmu_enable)
9288 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9289
9290 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9291 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9292#endif
9293
9294
9295 if (debug) {
9296 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9297 pdata->mem_start, pbi->buf_size);
9298 }
9299
9300 if (pdata->sys_info)
9301 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9302 else {
9303 pbi->vvp9_amstream_dec_info.width = 0;
9304 pbi->vvp9_amstream_dec_info.height = 0;
9305 pbi->vvp9_amstream_dec_info.rate = 30;
9306 }
9307 pbi->no_head = no_head;
9308#ifdef MULTI_INSTANCE_SUPPORT
9309 pbi->cma_dev = pdata->cma_dev;
9310#else
9311 cma_dev = pdata->cma_dev;
9312#endif
9313
9314#ifdef MULTI_INSTANCE_SUPPORT
9315 pdata->private = pbi;
9316 pdata->dec_status = vvp9_dec_status;
9317 pdata->set_isreset = vvp9_set_isreset;
9318 is_reset = 0;
9319 if (vvp9_init(pdata) < 0) {
9320#else
9321 if (vvp9_init(pbi) < 0) {
9322#endif
9323 pr_info("\namvdec_vp9 init failed.\n");
9324 vp9_local_uninit(pbi);
9325 uninit_mmu_buffers(pbi);
9326 vfree(pbi);
9327 pdata->dec_status = NULL;
9328 mutex_unlock(&vvp9_mutex);
9329 return -ENODEV;
9330 }
9331 /*set the max clk for smooth playing...*/
9332 hevc_source_changed(VFORMAT_VP9,
9333 4096, 2048, 60);
9334 mutex_unlock(&vvp9_mutex);
9335
9336 return 0;
9337}
9338
9339static int amvdec_vp9_remove(struct platform_device *pdev)
9340{
9341 struct VP9Decoder_s *pbi = gHevc;
9342 struct vdec_s *vdec = hw_to_vdec(pbi);
9343 int i;
9344
9345 if (debug)
9346 pr_info("amvdec_vp9_remove\n");
9347
9348 mutex_lock(&vvp9_mutex);
9349
9350 vvp9_stop(pbi);
9351
9352 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9353
9354 if (vdec->parallel_dec == 1) {
9355 for (i = 0; i < FRAME_BUFFERS; i++) {
9356 vdec->free_canvas_ex(pbi->common.buffer_pool->
9357 frame_bufs[i].buf.y_canvas_index, vdec->id);
9358 vdec->free_canvas_ex(pbi->common.buffer_pool->
9359 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9360 }
9361 }
9362
9363#ifdef DEBUG_PTS
9364 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9365 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9366#endif
9367 mem_map_mode = 0;
9368
9369 vfree(pbi);
9370 mutex_unlock(&vvp9_mutex);
9371
9372 return 0;
9373}
9374
9375/****************************************/
9376#ifdef CONFIG_PM
9377static int vp9_suspend(struct device *dev)
9378{
9379 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9380 return 0;
9381}
9382
9383static int vp9_resume(struct device *dev)
9384{
9385 amhevc_resume(to_platform_device(dev));
9386 return 0;
9387}
9388
9389static const struct dev_pm_ops vp9_pm_ops = {
9390 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9391};
9392#endif
9393
9394static struct platform_driver amvdec_vp9_driver = {
9395 .probe = amvdec_vp9_probe,
9396 .remove = amvdec_vp9_remove,
9397 .driver = {
9398 .name = DRIVER_NAME,
9399#ifdef CONFIG_PM
9400 .pm = &vp9_pm_ops,
9401#endif
9402 }
9403};
9404
9405static struct codec_profile_t amvdec_vp9_profile = {
9406 .name = "vp9",
9407 .profile = ""
9408};
9409
9410static struct codec_profile_t amvdec_vp9_profile_mult;
9411
9412static unsigned char get_data_check_sum
9413 (struct VP9Decoder_s *pbi, int size)
9414{
9415 int jj;
9416 int sum = 0;
9417 u8 *data = NULL;
9418
9419 if (!pbi->chunk->block->is_mapped)
9420 data = codec_mm_vmap(pbi->chunk->block->start +
9421 pbi->chunk->offset, size);
9422 else
9423 data = ((u8 *)pbi->chunk->block->start_virt) +
9424 pbi->chunk->offset;
9425
9426 for (jj = 0; jj < size; jj++)
9427 sum += data[jj];
9428
9429 if (!pbi->chunk->block->is_mapped)
9430 codec_mm_unmap_phyaddr(data);
9431 return sum;
9432}
9433
9434static void dump_data(struct VP9Decoder_s *pbi, int size)
9435{
9436 int jj;
9437 u8 *data = NULL;
9438 int padding_size = pbi->chunk->offset &
9439 (VDEC_FIFO_ALIGN - 1);
9440
9441 if (!pbi->chunk->block->is_mapped)
9442 data = codec_mm_vmap(pbi->chunk->block->start +
9443 pbi->chunk->offset, size);
9444 else
9445 data = ((u8 *)pbi->chunk->block->start_virt) +
9446 pbi->chunk->offset;
9447
9448 vp9_print(pbi, 0, "padding: ");
9449 for (jj = padding_size; jj > 0; jj--)
9450 vp9_print_cont(pbi,
9451 0,
9452 "%02x ", *(data - jj));
9453 vp9_print_cont(pbi, 0, "data adr %p\n",
9454 data);
9455
9456 for (jj = 0; jj < size; jj++) {
9457 if ((jj & 0xf) == 0)
9458 vp9_print(pbi,
9459 0,
9460 "%06x:", jj);
9461 vp9_print_cont(pbi,
9462 0,
9463 "%02x ", data[jj]);
9464 if (((jj + 1) & 0xf) == 0)
9465 vp9_print(pbi,
9466 0,
9467 "\n");
9468 }
9469 vp9_print(pbi,
9470 0,
9471 "\n");
9472
9473 if (!pbi->chunk->block->is_mapped)
9474 codec_mm_unmap_phyaddr(data);
9475}
9476
9477static void vp9_work(struct work_struct *work)
9478{
9479 struct VP9Decoder_s *pbi = container_of(work,
9480 struct VP9Decoder_s, work);
9481 struct vdec_s *vdec = hw_to_vdec(pbi);
9482 /* finished decoding one frame or error,
9483 * notify vdec core to switch context
9484 */
9485 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9486 "%s dec_result %d %x %x %x\n",
9487 __func__,
9488 pbi->dec_result,
9489 READ_VREG(HEVC_STREAM_LEVEL),
9490 READ_VREG(HEVC_STREAM_WR_PTR),
9491 READ_VREG(HEVC_STREAM_RD_PTR));
9492
9493 if (pbi->dec_result == DEC_INIT_PICLIST) {
9494 init_pic_list(pbi);
9495 pbi->pic_list_init_done = true;
9496 return;
9497 }
9498
9499 if (pbi->dec_result == DEC_V4L2_CONTINUE_DECODING) {
9500 struct aml_vcodec_ctx *ctx =
9501 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9502
9503 if (ctx->param_sets_from_ucode) {
9504 reset_process_time(pbi);
9505 if (wait_event_interruptible_timeout(ctx->wq,
9506 ctx->v4l_codec_ready,
9507 msecs_to_jiffies(500)) < 0)
9508 return;
9509 }
9510
9511 continue_decoding(pbi);
9512 pbi->postproc_done = 0;
9513 pbi->process_busy = 0;
9514
9515 return;
9516 }
9517
9518 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9519 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9520 && (hw_to_vdec(pbi)->next_status !=
9521 VDEC_STATUS_DISCONNECTED)) {
9522 if (!vdec_has_more_input(vdec)) {
9523 pbi->dec_result = DEC_RESULT_EOS;
9524 vdec_schedule_work(&pbi->work);
9525 return;
9526 }
9527
9528 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9529 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9530 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9531 __func__,
9532 READ_VREG(HEVC_STREAM_LEVEL),
9533 READ_VREG(HEVC_STREAM_WR_PTR),
9534 READ_VREG(HEVC_STREAM_RD_PTR));
9535 vdec_vframe_dirty(vdec, pbi->chunk);
9536 vdec_clean_input(vdec);
9537 }
9538
9539 if (get_free_buf_count(pbi) >=
9540 run_ready_min_buf_num) {
9541 int r;
9542 int decode_size;
9543 r = vdec_prepare_input(vdec, &pbi->chunk);
9544 if (r < 0) {
9545 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9546
9547 vp9_print(pbi,
9548 PRINT_FLAG_VDEC_DETAIL,
9549 "amvdec_vh265: Insufficient data\n");
9550
9551 vdec_schedule_work(&pbi->work);
9552 return;
9553 }
9554 pbi->dec_result = DEC_RESULT_NONE;
9555 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9556 "%s: chunk size 0x%x sum 0x%x\n",
9557 __func__, r,
9558 (debug & PRINT_FLAG_VDEC_STATUS) ?
9559 get_data_check_sum(pbi, r) : 0
9560 );
9561
9562 if (debug & PRINT_FLAG_VDEC_DATA)
9563 dump_data(pbi, pbi->chunk->size);
9564
9565 decode_size = pbi->chunk->size +
9566 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9567
9568 WRITE_VREG(HEVC_DECODE_SIZE,
9569 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9570
9571 vdec_enable_input(vdec);
9572
9573 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9574
9575 start_process_time(pbi);
9576
9577 } else{
9578 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9579
9580 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9581 "amvdec_vh265: Insufficient data\n");
9582
9583 vdec_schedule_work(&pbi->work);
9584 }
9585 return;
9586 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9587#ifdef SUPPORT_FB_DECODING
9588 if (pbi->used_stage_buf_num > 0) {
9589#ifndef FB_DECODING_TEST_SCHEDULE
9590 if (!is_s2_decoding_finished(pbi)) {
9591 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9592 "s2 decoding not done, check again later\n");
9593 vdec_schedule_work(&pbi->work);
9594 }
9595#endif
9596 inc_s2_pos(pbi);
9597 if (mcrcc_cache_alg_flag)
9598 dump_hit_rate(pbi);
9599 }
9600#endif
9601 /* if (!pbi->ctx_valid)
9602 pbi->ctx_valid = 1; */
9603 pbi->slice_idx++;
9604 pbi->frame_count++;
9605 pbi->process_state = PROC_STATE_INIT;
9606 decode_frame_count[pbi->index] = pbi->frame_count;
9607
9608 if (pbi->mmu_enable)
9609 pbi->used_4k_num =
9610 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9611 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9612 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9613 __func__,
9614 pbi->frame_count,
9615 pbi->dec_result,
9616 READ_VREG(HEVC_STREAM_LEVEL),
9617 READ_VREG(HEVC_STREAM_WR_PTR),
9618 READ_VREG(HEVC_STREAM_RD_PTR),
9619 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9620 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9621 pbi->start_shift_bytes
9622 );
9623 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9624 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9625 /*
9626 stream base: stream buf empty or timeout
9627 frame base: vdec_prepare_input fail
9628 */
9629 if (!vdec_has_more_input(vdec)) {
9630 pbi->dec_result = DEC_RESULT_EOS;
9631 vdec_schedule_work(&pbi->work);
9632 return;
9633 }
9634 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9635 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9636 "%s: end of stream\n",
9637 __func__);
9638 pbi->eos = 1;
9639 vp9_bufmgr_postproc(pbi);
9640
9641 if (pbi->is_used_v4l)
9642 notify_v4l_eos(hw_to_vdec(pbi));
9643
9644 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9645 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9646 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9647 "%s: force exit\n",
9648 __func__);
9649 if (pbi->stat & STAT_VDEC_RUN) {
9650 amhevc_stop();
9651 pbi->stat &= ~STAT_VDEC_RUN;
9652 }
9653
9654 if (pbi->stat & STAT_ISR_REG) {
9655#ifdef MULTI_INSTANCE_SUPPORT
9656 if (!pbi->m_ins_flag)
9657#endif
9658 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9659 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9660 pbi->stat &= ~STAT_ISR_REG;
9661 }
9662 }
9663 if (pbi->stat & STAT_VDEC_RUN) {
9664 amhevc_stop();
9665 pbi->stat &= ~STAT_VDEC_RUN;
9666 }
9667
9668 if (pbi->stat & STAT_TIMER_ARM) {
9669 del_timer_sync(&pbi->timer);
9670 pbi->stat &= ~STAT_TIMER_ARM;
9671 }
9672 /* mark itself has all HW resource released and input released */
9673#ifdef SUPPORT_FB_DECODING
9674 if (pbi->used_stage_buf_num > 0)
9675 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9676 else
9677 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9678 | CORE_MASK_HEVC
9679 | CORE_MASK_HEVC_FRONT
9680 | CORE_MASK_HEVC_BACK
9681 );
9682#else
9683 if (vdec->parallel_dec == 1)
9684 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9685 else
9686 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9687 | CORE_MASK_HEVC);
9688#endif
9689 trigger_schedule(pbi);
9690}
9691
9692static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9693{
9694 /* new to do ... */
9695#if (!defined SUPPORT_FB_DECODING)
9696 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9697#elif (defined FB_DECODING_TEST_SCHEDULE)
9698 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9699#else
9700 if (pbi->used_stage_buf_num > 0)
9701 vvp9_prot_init(pbi, HW_MASK_FRONT);
9702 else
9703 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9704#endif
9705 return 0;
9706}
9707static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9708{
9709 struct VP9Decoder_s *pbi =
9710 (struct VP9Decoder_s *)vdec->private;
9711 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9712 CODEC_MM_FLAGS_TVP : 0;
9713 unsigned long ret = 0;
9714
9715 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9716 return ret;
9717 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9718 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9719 pbi->first_sc_checked = 1;
9720 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9721 size, (pbi->need_cache_size >> PAGE_SHIFT),
9722 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9723 }
9724
9725#ifdef SUPPORT_FB_DECODING
9726 if (pbi->used_stage_buf_num > 0) {
9727 if (mask & CORE_MASK_HEVC_FRONT) {
9728 if (get_free_stage_buf_num(pbi) > 0
9729 && mv_buf_available(pbi))
9730 ret |= CORE_MASK_HEVC_FRONT;
9731 }
9732 if (mask & CORE_MASK_HEVC_BACK) {
9733 if (s2_buf_available(pbi) &&
9734 (get_free_buf_count(pbi) >=
9735 run_ready_min_buf_num)) {
9736 ret |= CORE_MASK_HEVC_BACK;
9737 pbi->back_not_run_ready = 0;
9738 } else
9739 pbi->back_not_run_ready = 1;
9740#if 0
9741 if (get_free_buf_count(pbi) <
9742 run_ready_min_buf_num)
9743 dump_pic_list(pbi);
9744#endif
9745 }
9746 } else if (get_free_buf_count(pbi) >=
9747 run_ready_min_buf_num)
9748 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9749 | CORE_MASK_HEVC_FRONT
9750 | CORE_MASK_HEVC_BACK;
9751
9752 if (ret & CORE_MASK_HEVC_FRONT)
9753 not_run_ready[pbi->index] = 0;
9754 else
9755 not_run_ready[pbi->index]++;
9756
9757 if (ret & CORE_MASK_HEVC_BACK)
9758 not_run2_ready[pbi->index] = 0;
9759 else
9760 not_run2_ready[pbi->index]++;
9761
9762 vp9_print(pbi,
9763 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9764 __func__, mask, ret,
9765 get_free_stage_buf_num(pbi),
9766 mv_buf_available(pbi),
9767 s2_buf_available(pbi),
9768 get_free_buf_count(pbi)
9769 );
9770
9771 return ret;
9772
9773#else
9774 if (get_free_buf_count(pbi) >=
9775 run_ready_min_buf_num) {
9776 if (vdec->parallel_dec == 1)
9777 ret = CORE_MASK_HEVC;
9778 else
9779 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9780 }
9781
9782 if (pbi->is_used_v4l) {
9783 struct aml_vcodec_ctx *ctx =
9784 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9785
9786 if (ctx->param_sets_from_ucode &&
9787 !ctx->v4l_codec_ready &&
9788 pbi->v4l_params_parsed) {
9789 ret = 0; /*the params has parsed.*/
9790 } else if (!ctx->v4l_codec_dpb_ready)
9791 ret = 0;
9792 }
9793
9794 if (ret)
9795 not_run_ready[pbi->index] = 0;
9796 else
9797 not_run_ready[pbi->index]++;
9798
9799 vp9_print(pbi,
9800 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9801 __func__, mask, ret);
9802 return ret;
9803#endif
9804}
9805
9806static void run_front(struct vdec_s *vdec)
9807{
9808 struct VP9Decoder_s *pbi =
9809 (struct VP9Decoder_s *)vdec->private;
9810 int ret, size;
9811
9812 run_count[pbi->index]++;
9813 /* pbi->chunk = vdec_prepare_input(vdec); */
9814#if (!defined SUPPORT_FB_DECODING)
9815 hevc_reset_core(vdec);
9816#elif (defined FB_DECODING_TEST_SCHEDULE)
9817 hevc_reset_core(vdec);
9818#else
9819 if (pbi->used_stage_buf_num > 0)
9820 fb_reset_core(vdec, HW_MASK_FRONT);
9821 else
9822 hevc_reset_core(vdec);
9823#endif
9824
9825 size = vdec_prepare_input(vdec, &pbi->chunk);
9826 if (size < 0) {
9827 input_empty[pbi->index]++;
9828
9829 pbi->dec_result = DEC_RESULT_AGAIN;
9830
9831 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9832 "ammvdec_vh265: Insufficient data\n");
9833
9834 vdec_schedule_work(&pbi->work);
9835 return;
9836 }
9837
9838 input_empty[pbi->index] = 0;
9839 pbi->dec_result = DEC_RESULT_NONE;
9840 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9841
9842 if (debug & PRINT_FLAG_VDEC_STATUS) {
9843 int ii;
9844 vp9_print(pbi, 0,
9845 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9846 __func__,
9847 pbi->frame_count, size,
9848 pbi->chunk ? pbi->chunk->size : 0,
9849 pbi->chunk ? pbi->chunk->offset : 0,
9850 pbi->chunk ? ((vdec_frame_based(vdec) &&
9851 (debug & PRINT_FLAG_VDEC_STATUS)) ?
9852 get_data_check_sum(pbi, size) : 0) : 0,
9853 READ_VREG(HEVC_STREAM_START_ADDR),
9854 READ_VREG(HEVC_STREAM_END_ADDR),
9855 READ_VREG(HEVC_STREAM_LEVEL),
9856 READ_VREG(HEVC_STREAM_WR_PTR),
9857 READ_VREG(HEVC_STREAM_RD_PTR),
9858 pbi->start_shift_bytes);
9859 if (vdec_frame_based(vdec) && pbi->chunk) {
9860 u8 *data = NULL;
9861
9862 if (!pbi->chunk->block->is_mapped)
9863 data = codec_mm_vmap(pbi->chunk->block->start +
9864 pbi->chunk->offset, 8);
9865 else
9866 data = ((u8 *)pbi->chunk->block->start_virt) +
9867 pbi->chunk->offset;
9868
9869 vp9_print_cont(pbi, 0, "data adr %p:",
9870 data);
9871 for (ii = 0; ii < 8; ii++)
9872 vp9_print_cont(pbi, 0, "%02x ",
9873 data[ii]);
9874
9875 if (!pbi->chunk->block->is_mapped)
9876 codec_mm_unmap_phyaddr(data);
9877 }
9878 vp9_print_cont(pbi, 0, "\r\n");
9879 }
9880 if (vdec->mc_loaded) {
9881 /*firmware have load before,
9882 and not changes to another.
9883 ignore reload.
9884 */
9885 } else {
9886 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9887 if (ret < 0) {
9888 amhevc_disable();
9889 vp9_print(pbi, PRINT_FLAG_ERROR,
9890 "VP9: the %s fw loading failed, err: %x\n",
9891 tee_enabled() ? "TEE" : "local", ret);
9892 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9893 vdec_schedule_work(&pbi->work);
9894 return;
9895 }
9896 vdec->mc_loaded = 1;
9897 vdec->mc_type = VFORMAT_VP9;
9898 }
9899
9900 if (vp9_hw_ctx_restore(pbi) < 0) {
9901 vdec_schedule_work(&pbi->work);
9902 return;
9903 }
9904
9905 vdec_enable_input(vdec);
9906
9907 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9908
9909 if (vdec_frame_based(vdec)) {
9910 if (debug & PRINT_FLAG_VDEC_DATA)
9911 dump_data(pbi, pbi->chunk->size);
9912
9913 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9914 size = pbi->chunk->size +
9915 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9916 }
9917 WRITE_VREG(HEVC_DECODE_SIZE, size);
9918 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9919 pbi->init_flag = 1;
9920
9921 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9922 "%s: start hevc (%x %x %x)\n",
9923 __func__,
9924 READ_VREG(HEVC_DEC_STATUS_REG),
9925 READ_VREG(HEVC_MPC_E),
9926 READ_VREG(HEVC_MPSR));
9927
9928 start_process_time(pbi);
9929 mod_timer(&pbi->timer, jiffies);
9930 pbi->stat |= STAT_TIMER_ARM;
9931 pbi->stat |= STAT_ISR_REG;
9932 amhevc_start();
9933 pbi->stat |= STAT_VDEC_RUN;
9934}
9935
9936#ifdef SUPPORT_FB_DECODING
9937static void mpred_process(struct VP9Decoder_s *pbi)
9938{
9939 union param_u *params = &pbi->s1_param;
9940 unsigned char use_prev_frame_mvs =
9941 !params->p.error_resilient_mode &&
9942 params->p.width == pbi->s1_width &&
9943 params->p.height == pbi->s1_height &&
9944 !pbi->s1_intra_only &&
9945 pbi->s1_last_show_frame &&
9946 (pbi->s1_frame_type != KEY_FRAME);
9947 pbi->s1_width = params->p.width;
9948 pbi->s1_height = params->p.height;
9949 pbi->s1_frame_type = params->p.frame_type;
9950 pbi->s1_intra_only =
9951 (params->p.show_frame ||
9952 params->p.show_existing_frame)
9953 ? 0 : params->p.intra_only;
9954 if ((pbi->s1_frame_type != KEY_FRAME)
9955 && (!pbi->s1_intra_only)) {
9956 unsigned int data32;
9957 int mpred_mv_rd_end_addr;
9958
9959 mpred_mv_rd_end_addr =
9960 pbi->s1_mpred_mv_wr_start_addr_pre
9961 + (pbi->lcu_total * MV_MEM_UNIT);
9962
9963 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
9964 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
9965 pbi->work_space_buf->
9966 mpred_above.buf_start);
9967
9968 data32 = READ_VREG(HEVC_MPRED_CTRL4);
9969
9970 data32 &= (~(1 << 6));
9971 data32 |= (use_prev_frame_mvs << 6);
9972 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
9973
9974 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
9975 pbi->s1_mpred_mv_wr_start_addr);
9976 WRITE_VREG(HEVC_MPRED_MV_WPTR,
9977 pbi->s1_mpred_mv_wr_start_addr);
9978
9979 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
9980 pbi->s1_mpred_mv_wr_start_addr_pre);
9981 WRITE_VREG(HEVC_MPRED_MV_RPTR,
9982 pbi->s1_mpred_mv_wr_start_addr_pre);
9983
9984 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
9985 mpred_mv_rd_end_addr);
9986
9987 } else
9988 clear_mpred_hw(pbi);
9989
9990 if (!params->p.show_existing_frame) {
9991 pbi->s1_mpred_mv_wr_start_addr_pre =
9992 pbi->s1_mpred_mv_wr_start_addr;
9993 pbi->s1_last_show_frame =
9994 params->p.show_frame;
9995 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
9996 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
9997 pbi->s1_mv_buf_index_pre_pre =
9998 pbi->s1_mv_buf_index_pre;
9999 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10000 } else
10001 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10002}
10003
10004static void vp9_s1_work(struct work_struct *s1_work)
10005{
10006 struct VP9Decoder_s *pbi = container_of(s1_work,
10007 struct VP9Decoder_s, s1_work);
10008 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10009 "%s dec_s1_result %d\n",
10010 __func__,
10011 pbi->dec_s1_result);
10012
10013#ifdef FB_DECODING_TEST_SCHEDULE
10014 if (pbi->dec_s1_result ==
10015 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10016 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10017 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10018 }
10019#endif
10020 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10021 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10022
10023 vdec_core_finish_run(hw_to_vdec(pbi),
10024 CORE_MASK_HEVC_FRONT);
10025
10026 trigger_schedule(pbi);
10027 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10028 }
10029
10030}
10031
10032static void run_back(struct vdec_s *vdec)
10033{
10034 struct VP9Decoder_s *pbi =
10035 (struct VP9Decoder_s *)vdec->private;
10036 int i;
10037 run2_count[pbi->index]++;
10038 if (debug & PRINT_FLAG_VDEC_STATUS) {
10039 vp9_print(pbi, 0,
10040 "%s", __func__);
10041 }
10042 pbi->run2_busy = 1;
10043#ifndef FB_DECODING_TEST_SCHEDULE
10044 fb_reset_core(vdec, HW_MASK_BACK);
10045
10046 vvp9_prot_init(pbi, HW_MASK_BACK);
10047#endif
10048 vp9_recycle_mmu_buf_tail(pbi);
10049
10050 if (pbi->frame_count > 0)
10051 vp9_bufmgr_postproc(pbi);
10052
10053 if (get_s2_buf(pbi) >= 0) {
10054 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10055 int ii;
10056 for (ii = 0; ii < 4; ii++)
10057 vp9_param.l.data[i + ii] =
10058 pbi->s2_buf->rpm[i + 3 - ii];
10059 }
10060#ifndef FB_DECODING_TEST_SCHEDULE
10061 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10062 pbi->stage_mmu_map_phy_addr +
10063 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10064#endif
10065 continue_decoding(pbi);
10066 }
10067 pbi->run2_busy = 0;
10068}
10069#endif
10070
10071static void run(struct vdec_s *vdec, unsigned long mask,
10072 void (*callback)(struct vdec_s *, void *), void *arg)
10073{
10074 struct VP9Decoder_s *pbi =
10075 (struct VP9Decoder_s *)vdec->private;
10076
10077 vp9_print(pbi,
10078 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10079 __func__, mask);
10080
10081 run_count[pbi->index]++;
10082 pbi->vdec_cb_arg = arg;
10083 pbi->vdec_cb = callback;
10084#ifdef SUPPORT_FB_DECODING
10085 if ((mask & CORE_MASK_HEVC) ||
10086 (mask & CORE_MASK_HEVC_FRONT))
10087 run_front(vdec);
10088
10089 if ((pbi->used_stage_buf_num > 0)
10090 && (mask & CORE_MASK_HEVC_BACK))
10091 run_back(vdec);
10092#else
10093 run_front(vdec);
10094#endif
10095}
10096
10097static void init_frame_bufs(struct VP9Decoder_s *pbi)
10098{
10099 struct vdec_s *vdec = hw_to_vdec(pbi);
10100 struct VP9_Common_s *const cm = &pbi->common;
10101 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10102 int i;
10103
10104 for (i = 0; i < pbi->used_buf_num; ++i) {
10105 frame_bufs[i].ref_count = 0;
10106 frame_bufs[i].buf.vf_ref = 0;
10107 frame_bufs[i].buf.decode_idx = 0;
10108 frame_bufs[i].buf.cma_alloc_addr = 0;
10109 frame_bufs[i].buf.index = i;
10110 }
10111
10112 if (vdec->parallel_dec == 1) {
10113 for (i = 0; i < FRAME_BUFFERS; i++) {
10114 vdec->free_canvas_ex
10115 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10116 vdec->id);
10117 vdec->free_canvas_ex
10118 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10119 vdec->id);
10120 }
10121 }
10122}
10123
10124static void reset(struct vdec_s *vdec)
10125{
10126
10127 struct VP9Decoder_s *pbi =
10128 (struct VP9Decoder_s *)vdec->private;
10129
10130 cancel_work_sync(&pbi->work);
10131 if (pbi->stat & STAT_VDEC_RUN) {
10132 amhevc_stop();
10133 pbi->stat &= ~STAT_VDEC_RUN;
10134 }
10135
10136 if (pbi->stat & STAT_TIMER_ARM) {
10137 del_timer_sync(&pbi->timer);
10138 pbi->stat &= ~STAT_TIMER_ARM;
10139 }
10140 pbi->dec_result = DEC_RESULT_NONE;
10141 reset_process_time(pbi);
10142 dealloc_mv_bufs(pbi);
10143 vp9_local_uninit(pbi);
10144 if (vvp9_local_init(pbi) < 0)
10145 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10146 init_frame_bufs(pbi);
10147
10148 pbi->eos = 0;
10149
10150 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10151}
10152
10153static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10154{
10155 struct VP9Decoder_s *pbi =
10156 (struct VP9Decoder_s *)vdec->private;
10157 return vvp9_isr(0, pbi);
10158}
10159
10160static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10161{
10162 struct VP9Decoder_s *pbi =
10163 (struct VP9Decoder_s *)vdec->private;
10164 return vvp9_isr_thread_fn(0, pbi);
10165}
10166
10167static void vp9_dump_state(struct vdec_s *vdec)
10168{
10169 struct VP9Decoder_s *pbi =
10170 (struct VP9Decoder_s *)vdec->private;
10171 struct VP9_Common_s *const cm = &pbi->common;
10172 int i;
10173 vp9_print(pbi, 0, "====== %s\n", __func__);
10174
10175 vp9_print(pbi, 0,
10176 "width/height (%d/%d), used_buf_num %d\n",
10177 cm->width,
10178 cm->height,
10179 pbi->used_buf_num
10180 );
10181
10182 vp9_print(pbi, 0,
10183 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10184 input_frame_based(vdec),
10185 pbi->eos,
10186 pbi->dec_result,
10187 decode_frame_count[pbi->index],
10188 display_frame_count[pbi->index],
10189 run_count[pbi->index],
10190 not_run_ready[pbi->index],
10191 input_empty[pbi->index],
10192 pbi->low_latency_flag,
10193 pbi->no_head
10194 );
10195
10196 if (vf_get_receiver(vdec->vf_provider_name)) {
10197 enum receviver_start_e state =
10198 vf_notify_receiver(vdec->vf_provider_name,
10199 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10200 NULL);
10201 vp9_print(pbi, 0,
10202 "\nreceiver(%s) state %d\n",
10203 vdec->vf_provider_name,
10204 state);
10205 }
10206
10207 vp9_print(pbi, 0,
10208 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10209 __func__,
10210 kfifo_len(&pbi->newframe_q),
10211 VF_POOL_SIZE,
10212 kfifo_len(&pbi->display_q),
10213 VF_POOL_SIZE,
10214 pbi->vf_pre_count,
10215 pbi->vf_get_count,
10216 pbi->vf_put_count,
10217 get_free_buf_count(pbi),
10218 run_ready_min_buf_num
10219 );
10220
10221 dump_pic_list(pbi);
10222
10223 for (i = 0; i < MAX_BUF_NUM; i++) {
10224 vp9_print(pbi, 0,
10225 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10226 i,
10227 pbi->m_mv_BUF[i].start_adr,
10228 pbi->m_mv_BUF[i].size,
10229 pbi->m_mv_BUF[i].used_flag);
10230 }
10231
10232 vp9_print(pbi, 0,
10233 "HEVC_DEC_STATUS_REG=0x%x\n",
10234 READ_VREG(HEVC_DEC_STATUS_REG));
10235 vp9_print(pbi, 0,
10236 "HEVC_MPC_E=0x%x\n",
10237 READ_VREG(HEVC_MPC_E));
10238 vp9_print(pbi, 0,
10239 "DECODE_MODE=0x%x\n",
10240 READ_VREG(DECODE_MODE));
10241 vp9_print(pbi, 0,
10242 "NAL_SEARCH_CTL=0x%x\n",
10243 READ_VREG(NAL_SEARCH_CTL));
10244 vp9_print(pbi, 0,
10245 "HEVC_PARSER_LCU_START=0x%x\n",
10246 READ_VREG(HEVC_PARSER_LCU_START));
10247 vp9_print(pbi, 0,
10248 "HEVC_DECODE_SIZE=0x%x\n",
10249 READ_VREG(HEVC_DECODE_SIZE));
10250 vp9_print(pbi, 0,
10251 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10252 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10253 vp9_print(pbi, 0,
10254 "HEVC_STREAM_START_ADDR=0x%x\n",
10255 READ_VREG(HEVC_STREAM_START_ADDR));
10256 vp9_print(pbi, 0,
10257 "HEVC_STREAM_END_ADDR=0x%x\n",
10258 READ_VREG(HEVC_STREAM_END_ADDR));
10259 vp9_print(pbi, 0,
10260 "HEVC_STREAM_LEVEL=0x%x\n",
10261 READ_VREG(HEVC_STREAM_LEVEL));
10262 vp9_print(pbi, 0,
10263 "HEVC_STREAM_WR_PTR=0x%x\n",
10264 READ_VREG(HEVC_STREAM_WR_PTR));
10265 vp9_print(pbi, 0,
10266 "HEVC_STREAM_RD_PTR=0x%x\n",
10267 READ_VREG(HEVC_STREAM_RD_PTR));
10268 vp9_print(pbi, 0,
10269 "PARSER_VIDEO_RP=0x%x\n",
10270 READ_PARSER_REG(PARSER_VIDEO_RP));
10271 vp9_print(pbi, 0,
10272 "PARSER_VIDEO_WP=0x%x\n",
10273 READ_PARSER_REG(PARSER_VIDEO_WP));
10274
10275 if (input_frame_based(vdec) &&
10276 (debug & PRINT_FLAG_VDEC_DATA)
10277 ) {
10278 int jj;
10279 if (pbi->chunk && pbi->chunk->block &&
10280 pbi->chunk->size > 0) {
10281 u8 *data = NULL;
10282
10283 if (!pbi->chunk->block->is_mapped)
10284 data = codec_mm_vmap(
10285 pbi->chunk->block->start +
10286 pbi->chunk->offset,
10287 pbi->chunk->size);
10288 else
10289 data = ((u8 *)pbi->chunk->block->start_virt)
10290 + pbi->chunk->offset;
10291 vp9_print(pbi, 0,
10292 "frame data size 0x%x\n",
10293 pbi->chunk->size);
10294 for (jj = 0; jj < pbi->chunk->size; jj++) {
10295 if ((jj & 0xf) == 0)
10296 vp9_print(pbi, 0,
10297 "%06x:", jj);
10298 vp9_print_cont(pbi, 0,
10299 "%02x ", data[jj]);
10300 if (((jj + 1) & 0xf) == 0)
10301 vp9_print_cont(pbi, 0,
10302 "\n");
10303 }
10304
10305 if (!pbi->chunk->block->is_mapped)
10306 codec_mm_unmap_phyaddr(data);
10307 }
10308 }
10309
10310}
10311
10312static int ammvdec_vp9_probe(struct platform_device *pdev)
10313{
10314 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10315 int ret;
10316 int config_val;
10317 struct vframe_content_light_level_s content_light_level;
10318 struct vframe_master_display_colour_s vf_dp;
10319
10320 struct BUF_s BUF[MAX_BUF_NUM];
10321 struct VP9Decoder_s *pbi = NULL;
10322 pr_debug("%s\n", __func__);
10323
10324 if (pdata == NULL) {
10325 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10326 return -EFAULT;
10327 }
10328 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10329 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10330 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10331 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10332 if (pbi == NULL) {
10333 pr_info("\nammvdec_vp9 device data allocation failed\n");
10334 return -ENOMEM;
10335 }
10336 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10337
10338 /* the ctx from v4l2 driver. */
10339 pbi->v4l2_ctx = pdata->private;
10340
10341 pdata->private = pbi;
10342 pdata->dec_status = vvp9_dec_status;
10343 /* pdata->set_trickmode = set_trickmode; */
10344 pdata->run_ready = run_ready;
10345 pdata->run = run;
10346 pdata->reset = reset;
10347 pdata->irq_handler = vp9_irq_cb;
10348 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10349 pdata->dump_state = vp9_dump_state;
10350
10351 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10352 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10353
10354 pbi->index = pdev->id;
10355
10356 if (pdata->use_vfm_path)
10357 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10358 VFM_DEC_PROVIDER_NAME);
10359 else
10360 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10361 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10362
10363 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10364 &vvp9_vf_provider, pbi);
10365
10366 pbi->provider_name = pdata->vf_provider_name;
10367 platform_set_drvdata(pdev, pdata);
10368
10369 pbi->platform_dev = pdev;
10370 pbi->video_signal_type = 0;
10371 pbi->m_ins_flag = 1;
10372 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10373 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10374
10375 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10376 pbi->max_pic_w = 8192;
10377 pbi->max_pic_h = 4608;
10378 } else {
10379 pbi->max_pic_w = 4096;
10380 pbi->max_pic_h = 2304;
10381 }
10382#if 1
10383 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10384 pdata->config_len) {
10385#ifdef MULTI_INSTANCE_SUPPORT
10386 int vp9_buf_width = 0;
10387 int vp9_buf_height = 0;
10388 /*use ptr config for doubel_write_mode, etc*/
10389 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10390 if (get_config_int(pdata->config, "vp9_double_write_mode",
10391 &config_val) == 0)
10392 pbi->double_write_mode = config_val;
10393 else
10394 pbi->double_write_mode = double_write_mode;
10395
10396 if (get_config_int(pdata->config, "save_buffer_mode",
10397 &config_val) == 0)
10398 pbi->save_buffer_mode = config_val;
10399 else
10400 pbi->save_buffer_mode = 0;
10401 if (get_config_int(pdata->config, "vp9_buf_width",
10402 &config_val) == 0) {
10403 vp9_buf_width = config_val;
10404 }
10405 if (get_config_int(pdata->config, "vp9_buf_height",
10406 &config_val) == 0) {
10407 vp9_buf_height = config_val;
10408 }
10409
10410 if (get_config_int(pdata->config, "no_head",
10411 &config_val) == 0)
10412 pbi->no_head = config_val;
10413 else
10414 pbi->no_head = no_head;
10415
10416 /*use ptr config for max_pic_w, etc*/
10417 if (get_config_int(pdata->config, "vp9_max_pic_w",
10418 &config_val) == 0) {
10419 pbi->max_pic_w = config_val;
10420 }
10421 if (get_config_int(pdata->config, "vp9_max_pic_h",
10422 &config_val) == 0) {
10423 pbi->max_pic_h = config_val;
10424 }
10425 if ((pbi->max_pic_w * pbi->max_pic_h)
10426 < (vp9_buf_width * vp9_buf_height)) {
10427 pbi->max_pic_w = vp9_buf_width;
10428 pbi->max_pic_h = vp9_buf_height;
10429 vp9_print(pbi, 0, "use buf resolution\n");
10430 }
10431
10432 if (get_config_int(pdata->config,
10433 "parm_v4l_codec_enable",
10434 &config_val) == 0)
10435 pbi->is_used_v4l = config_val;
10436
10437 if (get_config_int(pdata->config,
10438 "parm_v4l_buffer_margin",
10439 &config_val) == 0)
10440 pbi->dynamic_buf_num_margin = config_val;
10441#endif
10442 if (get_config_int(pdata->config, "HDRStaticInfo",
10443 &vf_dp.present_flag) == 0
10444 && vf_dp.present_flag == 1) {
10445 get_config_int(pdata->config, "mG.x",
10446 &vf_dp.primaries[0][0]);
10447 get_config_int(pdata->config, "mG.y",
10448 &vf_dp.primaries[0][1]);
10449 get_config_int(pdata->config, "mB.x",
10450 &vf_dp.primaries[1][0]);
10451 get_config_int(pdata->config, "mB.y",
10452 &vf_dp.primaries[1][1]);
10453 get_config_int(pdata->config, "mR.x",
10454 &vf_dp.primaries[2][0]);
10455 get_config_int(pdata->config, "mR.y",
10456 &vf_dp.primaries[2][1]);
10457 get_config_int(pdata->config, "mW.x",
10458 &vf_dp.white_point[0]);
10459 get_config_int(pdata->config, "mW.y",
10460 &vf_dp.white_point[1]);
10461 get_config_int(pdata->config, "mMaxDL",
10462 &vf_dp.luminance[0]);
10463 get_config_int(pdata->config, "mMinDL",
10464 &vf_dp.luminance[1]);
10465 vf_dp.content_light_level.present_flag = 1;
10466 get_config_int(pdata->config, "mMaxCLL",
10467 &content_light_level.max_content);
10468 get_config_int(pdata->config, "mMaxFALL",
10469 &content_light_level.max_pic_average);
10470 vf_dp.content_light_level = content_light_level;
10471 pbi->video_signal_type = (1 << 29)
10472 | (5 << 26) /* unspecified */
10473 | (0 << 25) /* limit */
10474 | (1 << 24) /* color available */
10475 | (9 << 16) /* 2020 */
10476 | (16 << 8) /* 2084 */
10477 | (9 << 0); /* 2020 */
10478 }
10479 pbi->vf_dp = vf_dp;
10480 } else
10481#endif
10482 {
10483 /*pbi->vvp9_amstream_dec_info.width = 0;
10484 pbi->vvp9_amstream_dec_info.height = 0;
10485 pbi->vvp9_amstream_dec_info.rate = 30;*/
10486 pbi->double_write_mode = double_write_mode;
10487 }
10488 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10489 pr_err("over size: %dx%d, probe failed\n",
10490 pbi->max_pic_w, pbi->max_pic_h);
10491 return -1;
10492 }
10493 pbi->mmu_enable = 1;
10494 video_signal_type = pbi->video_signal_type;
10495
10496 if (pdata->sys_info) {
10497 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10498 } else {
10499 pbi->vvp9_amstream_dec_info.width = 0;
10500 pbi->vvp9_amstream_dec_info.height = 0;
10501 pbi->vvp9_amstream_dec_info.rate = 30;
10502 }
10503 pbi->low_latency_flag = 1;
10504
10505 vp9_print(pbi, 0,
10506 "no_head %d low_latency %d\n",
10507 pbi->no_head, pbi->low_latency_flag);
10508#if 0
10509 pbi->buf_start = pdata->mem_start;
10510 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10511#else
10512 if (amvdec_vp9_mmu_init(pbi) < 0) {
10513 pr_err("vp9 alloc bmmu box failed!!\n");
10514 /* devm_kfree(&pdev->dev, (void *)pbi); */
10515 vfree((void *)pbi);
10516 pdata->dec_status = NULL;
10517 return -1;
10518 }
10519
10520 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10521 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10522 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10523 &pbi->cma_alloc_addr);
10524 if (ret < 0) {
10525 uninit_mmu_buffers(pbi);
10526 /* devm_kfree(&pdev->dev, (void *)pbi); */
10527 vfree((void *)pbi);
10528 pdata->dec_status = NULL;
10529 return ret;
10530 }
10531 pbi->buf_start = pbi->cma_alloc_addr;
10532 pbi->buf_size = work_buf_size;
10533#endif
10534
10535 pbi->init_flag = 0;
10536 pbi->first_sc_checked = 0;
10537 pbi->fatal_error = 0;
10538 pbi->show_frame_num = 0;
10539
10540 if (debug) {
10541 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10542 pbi->buf_start,
10543 pbi->buf_size);
10544 }
10545
10546 pbi->cma_dev = pdata->cma_dev;
10547 if (vvp9_init(pdata) < 0) {
10548 pr_info("\namvdec_vp9 init failed.\n");
10549 vp9_local_uninit(pbi);
10550 uninit_mmu_buffers(pbi);
10551 /* devm_kfree(&pdev->dev, (void *)pbi); */
10552 vfree((void *)pbi);
10553 pdata->dec_status = NULL;
10554 return -ENODEV;
10555 }
10556 vdec_set_prepare_level(pdata, start_decode_buf_level);
10557 hevc_source_changed(VFORMAT_VP9,
10558 4096, 2048, 60);
10559#ifdef SUPPORT_FB_DECODING
10560 if (pbi->used_stage_buf_num > 0)
10561 vdec_core_request(pdata,
10562 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10563 else
10564 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10565 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10566 | CORE_MASK_COMBINE);
10567#else
10568 if (pdata->parallel_dec == 1)
10569 vdec_core_request(pdata, CORE_MASK_HEVC);
10570 else
10571 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10572 | CORE_MASK_COMBINE);
10573#endif
10574 pbi->pic_list_init_done2 = true;
10575 return 0;
10576}
10577
10578static int ammvdec_vp9_remove(struct platform_device *pdev)
10579{
10580 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10581 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10582 struct vdec_s *vdec = hw_to_vdec(pbi);
10583 int i;
10584 if (debug)
10585 pr_info("amvdec_vp9_remove\n");
10586
10587 vmvp9_stop(pbi);
10588
10589#ifdef SUPPORT_FB_DECODING
10590 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10591 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10592 );
10593#else
10594 if (vdec->parallel_dec == 1)
10595 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10596 else
10597 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10598#endif
10599 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10600
10601 if (vdec->parallel_dec == 1) {
10602 for (i = 0; i < FRAME_BUFFERS; i++) {
10603 vdec->free_canvas_ex
10604 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10605 vdec->id);
10606 vdec->free_canvas_ex
10607 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10608 vdec->id);
10609 }
10610 }
10611
10612
10613#ifdef DEBUG_PTS
10614 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10615 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10616#endif
10617 mem_map_mode = 0;
10618
10619 /* devm_kfree(&pdev->dev, (void *)pbi); */
10620 vfree((void *)pbi);
10621 return 0;
10622}
10623
10624static struct platform_driver ammvdec_vp9_driver = {
10625 .probe = ammvdec_vp9_probe,
10626 .remove = ammvdec_vp9_remove,
10627 .driver = {
10628 .name = MULTI_DRIVER_NAME,
10629#ifdef CONFIG_PM
10630 .pm = &vp9_pm_ops,
10631#endif
10632 }
10633};
10634#endif
10635static struct mconfig vp9_configs[] = {
10636 MC_PU32("bit_depth_luma", &bit_depth_luma),
10637 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10638 MC_PU32("frame_width", &frame_width),
10639 MC_PU32("frame_height", &frame_height),
10640 MC_PU32("debug", &debug),
10641 MC_PU32("radr", &radr),
10642 MC_PU32("rval", &rval),
10643 MC_PU32("pop_shorts", &pop_shorts),
10644 MC_PU32("dbg_cmd", &dbg_cmd),
10645 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10646 MC_PU32("endian", &endian),
10647 MC_PU32("step", &step),
10648 MC_PU32("udebug_flag", &udebug_flag),
10649 MC_PU32("decode_pic_begin", &decode_pic_begin),
10650 MC_PU32("slice_parse_begin", &slice_parse_begin),
10651 MC_PU32("i_only_flag", &i_only_flag),
10652 MC_PU32("error_handle_policy", &error_handle_policy),
10653 MC_PU32("buf_alloc_width", &buf_alloc_width),
10654 MC_PU32("buf_alloc_height", &buf_alloc_height),
10655 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10656 MC_PU32("buf_alloc_size", &buf_alloc_size),
10657 MC_PU32("buffer_mode", &buffer_mode),
10658 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10659 MC_PU32("max_buf_num", &max_buf_num),
10660 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10661 MC_PU32("mem_map_mode", &mem_map_mode),
10662 MC_PU32("double_write_mode", &double_write_mode),
10663 MC_PU32("enable_mem_saving", &enable_mem_saving),
10664 MC_PU32("force_w_h", &force_w_h),
10665 MC_PU32("force_fps", &force_fps),
10666 MC_PU32("max_decoding_time", &max_decoding_time),
10667 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10668 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10669 MC_PU32("decode_timeout_val", &decode_timeout_val),
10670 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10671 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10672};
10673static struct mconfig_node vp9_node;
10674
10675static int __init amvdec_vp9_driver_init_module(void)
10676{
10677
10678 struct BuffInfo_s *p_buf_info;
10679
10680 if (vdec_is_support_4k()) {
10681 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10682 p_buf_info = &amvvp9_workbuff_spec[2];
10683 else
10684 p_buf_info = &amvvp9_workbuff_spec[1];
10685 } else
10686 p_buf_info = &amvvp9_workbuff_spec[0];
10687
10688 init_buff_spec(NULL, p_buf_info);
10689 work_buf_size =
10690 (p_buf_info->end_adr - p_buf_info->start_adr
10691 + 0xffff) & (~0xffff);
10692
10693 pr_debug("amvdec_vp9 module init\n");
10694
10695 error_handle_policy = 0;
10696
10697#ifdef ERROR_HANDLE_DEBUG
10698 dbg_nal_skip_flag = 0;
10699 dbg_nal_skip_count = 0;
10700#endif
10701 udebug_flag = 0;
10702 decode_pic_begin = 0;
10703 slice_parse_begin = 0;
10704 step = 0;
10705 buf_alloc_size = 0;
10706#ifdef MULTI_INSTANCE_SUPPORT
10707 if (platform_driver_register(&ammvdec_vp9_driver))
10708 pr_err("failed to register ammvdec_vp9 driver\n");
10709
10710#endif
10711 if (platform_driver_register(&amvdec_vp9_driver)) {
10712 pr_err("failed to register amvdec_vp9 driver\n");
10713 return -ENODEV;
10714 }
10715
10716 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10717 amvdec_vp9_profile.profile =
10718 "8k, 10bit, dwrite, compressed, no_head";
10719 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10720 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10721 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10722 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10723 if (vdec_is_support_4k())
10724 amvdec_vp9_profile.profile =
10725 "4k, 10bit, dwrite, compressed";
10726 else
10727 amvdec_vp9_profile.profile =
10728 "10bit, dwrite, compressed";
10729 } else {
10730 if (vdec_is_support_4k())
10731 amvdec_vp9_profile.profile =
10732 "4k, 10bit, dwrite, compressed, no_head";
10733 else
10734 amvdec_vp9_profile.profile =
10735 "10bit, dwrite, compressed, no_head";
10736 }
10737
10738 } else {
10739 amvdec_vp9_profile.name = "vp9_unsupport";
10740 }
10741
10742 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10743 max_buf_num = MAX_BUF_NUM_LESS;
10744
10745 vcodec_profile_register(&amvdec_vp9_profile);
10746 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10747 amvdec_vp9_profile_mult.name = "mvp9";
10748 vcodec_profile_register(&amvdec_vp9_profile_mult);
10749 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10750 "vp9", vp9_configs, CONFIG_FOR_RW);
10751
10752 return 0;
10753}
10754
10755static void __exit amvdec_vp9_driver_remove_module(void)
10756{
10757 pr_debug("amvdec_vp9 module remove.\n");
10758#ifdef MULTI_INSTANCE_SUPPORT
10759 platform_driver_unregister(&ammvdec_vp9_driver);
10760#endif
10761 platform_driver_unregister(&amvdec_vp9_driver);
10762}
10763
10764/****************************************/
10765
10766module_param(bit_depth_luma, uint, 0664);
10767MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10768
10769module_param(bit_depth_chroma, uint, 0664);
10770MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10771
10772module_param(frame_width, uint, 0664);
10773MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10774
10775module_param(frame_height, uint, 0664);
10776MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10777
10778module_param(debug, uint, 0664);
10779MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10780
10781module_param(radr, uint, 0664);
10782MODULE_PARM_DESC(radr, "\n radr\n");
10783
10784module_param(rval, uint, 0664);
10785MODULE_PARM_DESC(rval, "\n rval\n");
10786
10787module_param(pop_shorts, uint, 0664);
10788MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10789
10790module_param(dbg_cmd, uint, 0664);
10791MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10792
10793module_param(dbg_skip_decode_index, uint, 0664);
10794MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10795
10796module_param(endian, uint, 0664);
10797MODULE_PARM_DESC(endian, "\n rval\n");
10798
10799module_param(step, uint, 0664);
10800MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10801
10802module_param(decode_pic_begin, uint, 0664);
10803MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10804
10805module_param(slice_parse_begin, uint, 0664);
10806MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10807
10808module_param(i_only_flag, uint, 0664);
10809MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10810
10811module_param(low_latency_flag, uint, 0664);
10812MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10813
10814module_param(no_head, uint, 0664);
10815MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10816
10817module_param(error_handle_policy, uint, 0664);
10818MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10819
10820module_param(buf_alloc_width, uint, 0664);
10821MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10822
10823module_param(buf_alloc_height, uint, 0664);
10824MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10825
10826module_param(buf_alloc_depth, uint, 0664);
10827MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10828
10829module_param(buf_alloc_size, uint, 0664);
10830MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10831
10832module_param(buffer_mode, uint, 0664);
10833MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10834
10835module_param(buffer_mode_dbg, uint, 0664);
10836MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10837/*USE_BUF_BLOCK*/
10838module_param(max_buf_num, uint, 0664);
10839MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10840
10841module_param(dynamic_buf_num_margin, uint, 0664);
10842MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10843
10844module_param(mv_buf_margin, uint, 0664);
10845MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10846
10847module_param(run_ready_min_buf_num, uint, 0664);
10848MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10849
10850/**/
10851
10852module_param(mem_map_mode, uint, 0664);
10853MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10854
10855#ifdef SUPPORT_10BIT
10856module_param(double_write_mode, uint, 0664);
10857MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10858
10859module_param(enable_mem_saving, uint, 0664);
10860MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10861
10862module_param(force_w_h, uint, 0664);
10863MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10864#endif
10865
10866module_param(force_fps, uint, 0664);
10867MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10868
10869module_param(max_decoding_time, uint, 0664);
10870MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10871
10872module_param(on_no_keyframe_skiped, uint, 0664);
10873MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10874
10875module_param(mcrcc_cache_alg_flag, uint, 0664);
10876MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10877
10878#ifdef MULTI_INSTANCE_SUPPORT
10879module_param(start_decode_buf_level, int, 0664);
10880MODULE_PARM_DESC(start_decode_buf_level,
10881 "\n vp9 start_decode_buf_level\n");
10882
10883module_param(decode_timeout_val, uint, 0664);
10884MODULE_PARM_DESC(decode_timeout_val,
10885 "\n vp9 decode_timeout_val\n");
10886
10887module_param(vp9_max_pic_w, uint, 0664);
10888MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10889
10890module_param(vp9_max_pic_h, uint, 0664);
10891MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10892
10893module_param_array(decode_frame_count, uint,
10894 &max_decode_instance_num, 0664);
10895
10896module_param_array(display_frame_count, uint,
10897 &max_decode_instance_num, 0664);
10898
10899module_param_array(max_process_time, uint,
10900 &max_decode_instance_num, 0664);
10901
10902module_param_array(run_count, uint,
10903 &max_decode_instance_num, 0664);
10904
10905module_param_array(input_empty, uint,
10906 &max_decode_instance_num, 0664);
10907
10908module_param_array(not_run_ready, uint,
10909 &max_decode_instance_num, 0664);
10910#endif
10911
10912#ifdef SUPPORT_FB_DECODING
10913module_param_array(not_run2_ready, uint,
10914 &max_decode_instance_num, 0664);
10915
10916module_param_array(run2_count, uint,
10917 &max_decode_instance_num, 0664);
10918
10919module_param(stage_buf_num, uint, 0664);
10920MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10921#endif
10922
10923module_param(udebug_flag, uint, 0664);
10924MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10925
10926module_param(udebug_pause_pos, uint, 0664);
10927MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10928
10929module_param(udebug_pause_val, uint, 0664);
10930MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10931
10932module_param(udebug_pause_decode_idx, uint, 0664);
10933MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10934
10935module_param(without_display_mode, uint, 0664);
10936MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10937
10938module_init(amvdec_vp9_driver_init_module);
10939module_exit(amvdec_vp9_driver_remove_module);
10940
10941MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
10942MODULE_LICENSE("GPL");
10943
10944
generated by cgit at 2024-05-17 10:00:47 (GMT)