path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: 171706f894b9a29c6a3dccbaf8d0be21ce290368

1	/*
2	* drivers/amlogic/amports/vvp9.c
3	*
4	* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful, but WITHOUT
12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14	* more details.
15	*
16	*/
17	#define DEBUG
18	#include <linux/kernel.h>
19	#include <linux/module.h>
20	#include <linux/types.h>
21	#include <linux/errno.h>
22	#include <linux/interrupt.h>
23	#include <linux/semaphore.h>
24	#include <linux/delay.h>
25	#include <linux/timer.h>
26	#include <linux/kfifo.h>
27	#include <linux/kthread.h>
28	#include <linux/spinlock.h>
29	#include <linux/platform_device.h>
30	#include <linux/amlogic/media/vfm/vframe.h>
31	#include <linux/amlogic/media/utils/amstream.h>
32	#include <linux/amlogic/media/utils/vformat.h>
33	#include <linux/amlogic/media/frame_sync/ptsserv.h>
34	#include <linux/amlogic/media/canvas/canvas.h>
35	#include <linux/amlogic/media/vfm/vframe_provider.h>
36	#include <linux/amlogic/media/vfm/vframe_receiver.h>
37	#include <linux/dma-mapping.h>
38	#include <linux/dma-contiguous.h>
39	#include <linux/slab.h>
40	#include <linux/amlogic/tee.h>
41	#include "../../../stream_input/amports/amports_priv.h"
42	#include <linux/amlogic/media/codec_mm/codec_mm.h>
43	#include "../utils/decoder_mmu_box.h"
44	#include "../utils/decoder_bmmu_box.h"
45
46	#define MEM_NAME "codec_vp9"
47	/* #include <mach/am_regs.h> */
48	#include <linux/amlogic/media/utils/vdec_reg.h>
49	#include "../utils/vdec.h"
50	#include "../utils/amvdec.h"
51	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52	#include "../utils/vdec_profile.h"
53	#endif
54
55	#include <linux/amlogic/media/video_sink/video.h>
56	#include <linux/amlogic/media/codec_mm/configs.h>
57	#include "../utils/config_parser.h"
58	#include "../utils/firmware.h"
59	#include "../../../common/chips/decoder_cpu_ver_info.h"
60	#include "../utils/vdec_v4l2_buffer_ops.h"
61	#include <media/v4l2-mem2mem.h>
62
63	#define MIX_STREAM_SUPPORT
64
65	#include "vvp9.h"
66
67
68	/*#define SUPPORT_FB_DECODING*/
69	/*#define FB_DECODING_TEST_SCHEDULE*/
70
71
72	#define HW_MASK_FRONT 0x1
73	#define HW_MASK_BACK 0x2
74
75	#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
76	#define VP9D_MPP_REFINFO_DATA 0x3443
77	#define VP9D_MPP_REF_SCALE_ENBL 0x3441
78	#define HEVC_MPRED_CTRL4 0x324c
79	#define HEVC_CM_HEADER_START_ADDR 0x3628
80	#define HEVC_DBLK_CFGB 0x350b
81	#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
82	#define HEVC_SAO_MMU_VH1_ADDR 0x363b
83	#define HEVC_SAO_MMU_VH0_ADDR 0x363a
84
85	#define HEVC_MV_INFO 0x310d
86	#define HEVC_QP_INFO 0x3137
87	#define HEVC_SKIP_INFO 0x3136
88
89	#define VP9_10B_DEC_IDLE 0
90	#define VP9_10B_DEC_FRAME_HEADER 1
91	#define VP9_10B_DEC_SLICE_SEGMENT 2
92	#define VP9_10B_DECODE_SLICE 5
93	#define VP9_10B_DISCARD_NAL 6
94	#define VP9_DUMP_LMEM 7
95	#define HEVC_DECPIC_DATA_DONE 0xa
96	#define HEVC_DECPIC_DATA_ERROR 0xb
97	#define HEVC_NAL_DECODE_DONE 0xe
98	#define HEVC_DECODE_BUFEMPTY 0x20
99	#define HEVC_DECODE_TIMEOUT 0x21
100	#define HEVC_SEARCH_BUFEMPTY 0x22
101	#define HEVC_DECODE_OVER_SIZE 0x23
102	#define HEVC_S2_DECODING_DONE 0x50
103	#define VP9_HEAD_PARSER_DONE 0xf0
104	#define VP9_HEAD_SEARCH_DONE 0xf1
105	#define VP9_EOS 0xf2
106	#define HEVC_ACTION_DONE 0xff
107
108	#define VF_POOL_SIZE 32
109
110	#undef pr_info
111	#define pr_info printk
112
113	#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
114	#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
115	#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
116	#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
117	#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
118
119	#define VP9_TRIGGER_FRAME_DONE 0x100
120	#define VP9_TRIGGER_FRAME_ENABLE 0x200
121
122	#define MV_MEM_UNIT 0x240
123	/*---------------------------------------------------
124	* Include "parser_cmd.h"
125	*---------------------------------------------------
126	*/
127	#define PARSER_CMD_SKIP_CFG_0 0x0000090b
128
129	#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
130
131	#define PARSER_CMD_SKIP_CFG_2 0x001b1910
132
133	#define PARSER_CMD_NUMBER 37
134
135	/*#define HEVC_PIC_STRUCT_SUPPORT*/
136	/* to remove, fix build error */
137
138	/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
139
140	#define MULTI_INSTANCE_SUPPORT
141	#define SUPPORT_10BIT
142	/* #define ERROR_HANDLE_DEBUG */
143
144	#ifndef STAT_KTHREAD
145	#define STAT_KTHREAD 0x40
146	#endif
147
148	#ifdef MULTI_INSTANCE_SUPPORT
149	#define MAX_DECODE_INSTANCE_NUM 9
150	#define MULTI_DRIVER_NAME "ammvdec_vp9"
151	static unsigned int max_decode_instance_num
152	= MAX_DECODE_INSTANCE_NUM;
153	static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
154	static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
155	static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
156	static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
157	static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
158	static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
159
160	static u32 decode_timeout_val = 200;
161	static int start_decode_buf_level = 0x8000;
162	static u32 work_buf_size;
163
164	static u32 mv_buf_margin;
165
166	/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
167	/* double_write_mode:
168	* 0, no double write;
169	* 1, 1:1 ratio;
170	* 2, (1/4):(1/4) ratio;
171	* 3, (1/4):(1/4) ratio, with both compressed frame included
172	* 4, (1/2):(1/2) ratio;
173	* 0x10, double write only
174	* 0x100, if > 1080p,use mode 4,else use mode 1;
175	* 0x200, if > 1080p,use mode 2,else use mode 1;
176	* 0x300, if > 720p, use mode 4, else use mode 1;
177	*/
178	static u32 double_write_mode;
179
180	#define DRIVER_NAME "amvdec_vp9"
181	#define MODULE_NAME "amvdec_vp9"
182	#define DRIVER_HEADER_NAME "amvdec_vp9_header"
183
184
185	#define PUT_INTERVAL (HZ/100)
186	#define ERROR_SYSTEM_RESET_COUNT 200
187
188	#define PTS_NORMAL 0
189	#define PTS_NONE_REF_USE_DURATION 1
190
191	#define PTS_MODE_SWITCHING_THRESHOLD 3
192	#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
193
194	#define DUR2PTS(x) ((x)*90/96)
195
196	struct VP9Decoder_s;
197	static int vvp9_vf_states(struct vframe_states *states, void *);
198	static struct vframe_s *vvp9_vf_peek(void *);
199	static struct vframe_s *vvp9_vf_get(void *);
200	static void vvp9_vf_put(struct vframe_s *, void *);
201	static int vvp9_event_cb(int type, void *data, void *private_data);
202
203	static int vvp9_stop(struct VP9Decoder_s *pbi);
204	#ifdef MULTI_INSTANCE_SUPPORT
205	static s32 vvp9_init(struct vdec_s *vdec);
206	#else
207	static s32 vvp9_init(struct VP9Decoder_s *pbi);
208	#endif
209	static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
210	static int vvp9_local_init(struct VP9Decoder_s *pbi);
211	static void vvp9_put_timer_func(unsigned long arg);
212	static void dump_data(struct VP9Decoder_s *pbi, int size);
213	static unsigned char get_data_check_sum
214	(struct VP9Decoder_s *pbi, int size);
215	static void dump_pic_list(struct VP9Decoder_s *pbi);
216	static int vp9_alloc_mmu(
217	struct VP9Decoder_s *pbi,
218	int cur_buf_idx,
219	int pic_width,
220	int pic_height,
221	unsigned short bit_depth,
222	unsigned int *mmu_index_adr);
223
224
225	static const char vvp9_dec_id[] = "vvp9-dev";
226
227	#define PROVIDER_NAME "decoder.vp9"
228	#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
229
230	static const struct vframe_operations_s vvp9_vf_provider = {
231	.peek = vvp9_vf_peek,
232	.get = vvp9_vf_get,
233	.put = vvp9_vf_put,
234	.event_cb = vvp9_event_cb,
235	.vf_states = vvp9_vf_states,
236	};
237
238	static struct vframe_provider_s vvp9_vf_prov;
239
240	static u32 bit_depth_luma;
241	static u32 bit_depth_chroma;
242	static u32 frame_width;
243	static u32 frame_height;
244	static u32 video_signal_type;
245
246	static u32 on_no_keyframe_skiped;
247
248	#define PROB_SIZE (496 * 2 * 4)
249	#define PROB_BUF_SIZE (0x5000)
250	#define COUNT_BUF_SIZE (0x300 * 4 * 4)
251	/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
252	#define MAX_FRAME_4K_NUM 0x1200
253	#define MAX_FRAME_8K_NUM 0x4800
254
255	#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
256
257	#ifdef SUPPORT_FB_DECODING
258	/* register define */
259	#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
260	#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
261	#define HEVC_ASSIST_HED_FB_ADDR 0x3008
262	#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
263	#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
264
265
266	#define MAX_STAGE_PAGE_NUM 0x1200
267	#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
268	#endif
269	static inline int div_r32(int64_t m, int n)
270	{
271	/*
272	*return (int)(m/n)
273	*/
274	#ifndef CONFIG_ARM64
275	int64_t qu = 0;
276	qu = div_s64(m, n);
277	return (int)qu;
278	#else
279	return (int)(m/n);
280	#endif
281	}
282
283	/*USE_BUF_BLOCK*/
284	struct BUF_s {
285	int index;
286	unsigned int alloc_flag;
287	/*buffer */
288	unsigned int cma_page_count;
289	unsigned long alloc_addr;
290	unsigned long start_adr;
291	unsigned int size;
292
293	unsigned int free_start_adr;
294	ulong v4l_ref_buf_addr;
295	ulong header_addr;
296	u32 header_size;
297	u32 luma_size;
298	} /*BUF_t */;
299
300	struct MVBUF_s {
301	unsigned long start_adr;
302	unsigned int size;
303	int used_flag;
304	} /*MVBUF_t */;
305
306	/* #undef BUFMGR_ONLY to enable hardware configuration */
307
308	/*#define TEST_WR_PTR_INC*/
309	/*#define WR_PTR_INC_NUM 128*/
310	#define WR_PTR_INC_NUM 1
311
312	#define SIMULATION
313	#define DOS_PROJECT
314	#undef MEMORY_MAP_IN_REAL_CHIP
315
316	/*#undef DOS_PROJECT*/
317	/*#define MEMORY_MAP_IN_REAL_CHIP*/
318
319	/*#define BUFFER_MGR_ONLY*/
320	/*#define CONFIG_HEVC_CLK_FORCED_ON*/
321	/*#define ENABLE_SWAP_TEST*/
322	#define MCRCC_ENABLE
323
324	#define VP9_LPF_LVL_UPDATE
325	/*#define DBG_LF_PRINT*/
326
327	#ifdef VP9_10B_NV21
328	#else
329	#define LOSLESS_COMPRESS_MODE
330	#endif
331
332	#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
333	#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
334
335
336
337	typedef unsigned int u32;
338	typedef unsigned short u16;
339
340	#define VP9_DEBUG_BUFMGR 0x01
341	#define VP9_DEBUG_BUFMGR_MORE 0x02
342	#define VP9_DEBUG_BUFMGR_DETAIL 0x04
343	#define VP9_DEBUG_OUT_PTS 0x10
344	#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
345	#define VP9_DEBUG_MERGE 0x200
346	#define VP9_DEBUG_DBG_LF_PRINT 0x400
347	#define VP9_DEBUG_REG 0x800
348	#define VP9_DEBUG_2_STAGE 0x1000
349	#define VP9_DEBUG_2_STAGE_MORE 0x2000
350	#define VP9_DEBUG_QOS_INFO 0x4000
351	#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
352	#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
353	#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
354	#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
355	#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
356	#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
357	#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
358	#define VP9_DEBUG_DUMP_DATA 0x800000
359	#define VP9_DEBUG_CACHE 0x1000000
360	#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
361	#define IGNORE_PARAM_FROM_CONFIG 0x8000000
362	#ifdef MULTI_INSTANCE_SUPPORT
363	#define PRINT_FLAG_ERROR 0x0
364	#define PRINT_FLAG_V4L_DETAIL 0x10000000
365	#define PRINT_FLAG_VDEC_STATUS 0x20000000
366	#define PRINT_FLAG_VDEC_DETAIL 0x40000000
367	#define PRINT_FLAG_VDEC_DATA 0x80000000
368	#endif
369
370	static u32 debug;
371	static bool is_reset;
372	/*for debug*/
373	/*
374	udebug_flag:
375	bit 0, enable ucode print
376	bit 1, enable ucode detail print
377	bit [31:16] not 0, pos to dump lmem
378	bit 2, pop bits to lmem
379	bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
380	*/
381	static u32 udebug_flag;
382	/*
383	when udebug_flag[1:0] is not 0
384	udebug_pause_pos not 0,
385	pause position
386	*/
387	static u32 udebug_pause_pos;
388	/*
389	when udebug_flag[1:0] is not 0
390	and udebug_pause_pos is not 0,
391	pause only when DEBUG_REG2 is equal to this val
392	*/
393	static u32 udebug_pause_val;
394
395	static u32 udebug_pause_decode_idx;
396
397	static u32 without_display_mode;
398
399	#define DEBUG_REG
400	#ifdef DEBUG_REG
401	void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
402	{
403	if (debug & VP9_DEBUG_REG)
404	pr_info("%s(%x, %x)\n", __func__, adr, val);
405	if (adr != 0)
406	WRITE_VREG(adr, val);
407	}
408
409	#undef WRITE_VREG
410	#define WRITE_VREG WRITE_VREG_DBG2
411	#endif
412
413	#define FRAME_CNT_WINDOW_SIZE 59
414	#define RATE_CORRECTION_THRESHOLD 5
415	/**************************************************
416
417	VP9 buffer management start
418
419	***************************************************/
420
421	#define MMU_COMPRESS_HEADER_SIZE 0x48000
422	#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
423	#define MAX_SIZE_8K (8192 * 4608)
424	#define MAX_SIZE_4K (4096 * 2304)
425	#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
426
427	#define INVALID_IDX -1 /* Invalid buffer index.*/
428
429	#define RPM_BEGIN 0x200
430	#define RPM_END 0x280
431
432	union param_u {
433	struct {
434	unsigned short data[RPM_END - RPM_BEGIN];
435	} l;
436	struct {
437	/* from ucode lmem, do not change this struct */
438	unsigned short profile;
439	unsigned short show_existing_frame;
440	unsigned short frame_to_show_idx;
441	unsigned short frame_type; /*1 bit*/
442	unsigned short show_frame; /*1 bit*/
443	unsigned short error_resilient_mode; /*1 bit*/
444	unsigned short intra_only; /*1 bit*/
445	unsigned short display_size_present; /*1 bit*/
446	unsigned short reset_frame_context;
447	unsigned short refresh_frame_flags;
448	unsigned short width;
449	unsigned short height;
450	unsigned short display_width;
451	unsigned short display_height;
452	/*
453	*bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
454	*bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
455	*bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
456	*/
457	unsigned short ref_info;
458	/*
459	*bit[2]: same_frame_size0
460	*bit[1]: same_frame_size1
461	*bit[0]: same_frame_size2
462	*/
463	unsigned short same_frame_size;
464
465	unsigned short mode_ref_delta_enabled;
466	unsigned short ref_deltas[4];
467	unsigned short mode_deltas[2];
468	unsigned short filter_level;
469	unsigned short sharpness_level;
470	unsigned short bit_depth;
471	unsigned short seg_quant_info[8];
472	unsigned short seg_enabled;
473	unsigned short seg_abs_delta;
474	/* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
475	unsigned short seg_lf_info[8];
476	} p;
477	};
478
479
480	struct vpx_codec_frame_buffer_s {
481	uint8_t *data; /**< Pointer to the data buffer */
482	size_t size; /**< Size of data in bytes */
483	void *priv; /**< Frame's private data */
484	};
485
486	enum vpx_color_space_t {
487	VPX_CS_UNKNOWN = 0, /**< Unknown */
488	VPX_CS_BT_601 = 1, /**< BT.601 */
489	VPX_CS_BT_709 = 2, /**< BT.709 */
490	VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
491	VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
492	VPX_CS_BT_2020 = 5, /**< BT.2020 */
493	VPX_CS_RESERVED = 6, /**< Reserved */
494	VPX_CS_SRGB = 7 /**< sRGB */
495	}; /**< alias for enum vpx_color_space */
496
497	enum vpx_bit_depth_t {
498	VPX_BITS_8 = 8, /**< 8 bits */
499	VPX_BITS_10 = 10, /**< 10 bits */
500	VPX_BITS_12 = 12, /**< 12 bits */
501	};
502
503	#define MAX_SLICE_NUM 1024
504	struct PIC_BUFFER_CONFIG_s {
505	int index;
506	int BUF_index;
507	int mv_buf_index;
508	int comp_body_size;
509	int buf_size;
510	int vf_ref;
511	int y_canvas_index;
512	int uv_canvas_index;
513	#ifdef MULTI_INSTANCE_SUPPORT
514	struct canvas_config_s canvas_config[2];
515	#endif
516	int decode_idx;
517	int slice_type;
518	int stream_offset;
519	u32 pts;
520	u64 pts64;
521	u64 timestamp;
522	uint8_t error_mark;
523	/**/
524	int slice_idx;
525	/*buffer*/
526	unsigned long header_adr;
527	unsigned long mpred_mv_wr_start_addr;
528	/*unsigned long mc_y_adr;
529	*unsigned long mc_u_v_adr;
530	*/
531	unsigned int dw_y_adr;
532	unsigned int dw_u_v_adr;
533	int mc_canvas_y;
534	int mc_canvas_u_v;
535
536	int lcu_total;
537	/**/
538	int y_width;
539	int y_height;
540	int y_crop_width;
541	int y_crop_height;
542	int y_stride;
543
544	int uv_width;
545	int uv_height;
546	int uv_crop_width;
547	int uv_crop_height;
548	int uv_stride;
549
550	int alpha_width;
551	int alpha_height;
552	int alpha_stride;
553
554	uint8_t *y_buffer;
555	uint8_t *u_buffer;
556	uint8_t *v_buffer;
557	uint8_t *alpha_buffer;
558
559	uint8_t *buffer_alloc;
560	int buffer_alloc_sz;
561	int border;
562	int frame_size;
563	int subsampling_x;
564	int subsampling_y;
565	unsigned int bit_depth;
566	enum vpx_color_space_t color_space;
567
568	int corrupted;
569	int flags;
570	unsigned long cma_alloc_addr;
571
572	int double_write_mode;
573
574	/* picture qos infomation*/
575	int max_qp;
576	int avg_qp;
577	int min_qp;
578	int max_skip;
579	int avg_skip;
580	int min_skip;
581	int max_mv;
582	int min_mv;
583	int avg_mv;
584
585	bool vframe_bound;
586	} PIC_BUFFER_CONFIG;
587
588	enum BITSTREAM_PROFILE {
589	PROFILE_0,
590	PROFILE_1,
591	PROFILE_2,
592	PROFILE_3,
593	MAX_PROFILES
594	};
595
596	enum FRAME_TYPE {
597	KEY_FRAME = 0,
598	INTER_FRAME = 1,
599	FRAME_TYPES,
600	};
601
602	enum REFERENCE_MODE {
603	SINGLE_REFERENCE = 0,
604	COMPOUND_REFERENCE = 1,
605	REFERENCE_MODE_SELECT = 2,
606	REFERENCE_MODES = 3,
607	};
608
609	#define NONE -1
610	#define INTRA_FRAME 0
611	#define LAST_FRAME 1
612	#define GOLDEN_FRAME 2
613	#define ALTREF_FRAME 3
614	#define MAX_REF_FRAMES 4
615
616	#define REFS_PER_FRAME 3
617
618	#define REF_FRAMES_LOG2 3
619	#define REF_FRAMES (1 << REF_FRAMES_LOG2)
620	#define REF_FRAMES_4K (6)
621
622	/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
623	*in parallel, 3 for scaled references on the encoder.
624	*TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
625	* // of framebuffers.
626	*TODO(jkoleszar): These 3 extra references could probably come from the
627	*normal reference pool.
628	*/
629	#define FRAME_BUFFERS (REF_FRAMES + 16)
630	#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
631	#define MAX_BUF_NUM (FRAME_BUFFERS)
632	#define MV_BUFFER_NUM FRAME_BUFFERS
633	#ifdef SUPPORT_FB_DECODING
634	#define STAGE_MAX_BUFFERS 16
635	#else
636	#define STAGE_MAX_BUFFERS 0
637	#endif
638
639	#define FRAME_CONTEXTS_LOG2 2
640	#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
641	/*buffer + header buffer + workspace*/
642	#ifdef MV_USE_FIXED_BUF
643	#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
644	#define VF_BUFFER_IDX(n) (n)
645	#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
646	#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
647	#else
648	#define MAX_BMMU_BUFFER_NUM \
649	(FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
650	#define VF_BUFFER_IDX(n) (n)
651	#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
652	#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
653	#define WORK_SPACE_BUF_ID \
654	(FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
655	#endif
656
657	struct RefCntBuffer_s {
658	int ref_count;
659	/*MV_REF *mvs;*/
660	int mi_rows;
661	int mi_cols;
662	struct vpx_codec_frame_buffer_s raw_frame_buffer;
663	struct PIC_BUFFER_CONFIG_s buf;
664
665	/*The Following variables will only be used in frame parallel decode.
666	*
667	*frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
668	*that no FrameWorker owns, or is decoding, this buffer.
669	*VP9Worker *frame_worker_owner;
670	*
671	*row and col indicate which position frame has been decoded to in real
672	*pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
673	*when the frame is fully decoded.
674	*/
675	int row;
676	int col;
677	} RefCntBuffer;
678
679	struct RefBuffer_s {
680	/*TODO(dkovalev): idx is not really required and should be removed, now it
681	*is used in vp9_onyxd_if.c
682	*/
683	int idx;
684	struct PIC_BUFFER_CONFIG_s *buf;
685	/*struct scale_factors sf;*/
686	} RefBuffer;
687
688	struct InternalFrameBuffer_s {
689	uint8_t *data;
690	size_t size;
691	int in_use;
692	} InternalFrameBuffer;
693
694	struct InternalFrameBufferList_s {
695	int num_internal_frame_buffers;
696	struct InternalFrameBuffer_s *int_fb;
697	} InternalFrameBufferList;
698
699	struct BufferPool_s {
700	/*Protect BufferPool from being accessed by several FrameWorkers at
701	*the same time during frame parallel decode.
702	*TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
703	*
704	*Private data associated with the frame buffer callbacks.
705	*void *cb_priv;
706	*
707	*vpx_get_frame_buffer_cb_fn_t get_fb_cb;
708	*vpx_release_frame_buffer_cb_fn_t release_fb_cb;
709	*/
710
711	struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
712
713	/*Frame buffers allocated internally by the codec.*/
714	struct InternalFrameBufferList_s int_frame_buffers;
715	unsigned long flags;
716	spinlock_t lock;
717
718	} BufferPool;
719
720	#define lock_buffer_pool(pool, flags) \
721	spin_lock_irqsave(&pool->lock, flags)
722
723	#define unlock_buffer_pool(pool, flags) \
724	spin_unlock_irqrestore(&pool->lock, flags)
725
726	struct VP9_Common_s {
727	enum vpx_color_space_t color_space;
728	int width;
729	int height;
730	int display_width;
731	int display_height;
732	int last_width;
733	int last_height;
734
735	int subsampling_x;
736	int subsampling_y;
737
738	int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
739
740	struct PIC_BUFFER_CONFIG_s *frame_to_show;
741	struct RefCntBuffer_s *prev_frame;
742
743	/*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
744	struct RefCntBuffer_s *cur_frame;
745
746	int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
747
748	/*Prepare ref_frame_map for the next frame.
749	*Only used in frame parallel decode.
750	*/
751	int next_ref_frame_map[REF_FRAMES];
752
753	/* TODO(jkoleszar): could expand active_ref_idx to 4,
754	*with 0 as intra, and roll new_fb_idx into it.
755	*/
756
757	/*Each frame can reference REFS_PER_FRAME buffers*/
758	struct RefBuffer_s frame_refs[REFS_PER_FRAME];
759
760	int prev_fb_idx;
761	int new_fb_idx;
762	int cur_fb_idx_mmu;
763	/*last frame's frame type for motion search*/
764	enum FRAME_TYPE last_frame_type;
765	enum FRAME_TYPE frame_type;
766
767	int show_frame;
768	int last_show_frame;
769	int show_existing_frame;
770
771	/*Flag signaling that the frame is encoded using only INTRA modes.*/
772	uint8_t intra_only;
773	uint8_t last_intra_only;
774
775	int allow_high_precision_mv;
776
777	/*Flag signaling that the frame context should be reset to default
778	*values. 0 or 1 implies don't reset, 2 reset just the context
779	*specified in the frame header, 3 reset all contexts.
780	*/
781	int reset_frame_context;
782
783	/*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
784	* MODE_INFO (8-pixel) units.
785	*/
786	int MBs;
787	int mb_rows, mi_rows;
788	int mb_cols, mi_cols;
789	int mi_stride;
790
791	/*Whether to use previous frame's motion vectors for prediction.*/
792	int use_prev_frame_mvs;
793
794	int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
795
796	int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
797
798	/*struct loopfilter lf;*/
799	/*struct segmentation seg;*/
800
801	/*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
802	/* in pbi.*/
803	int frame_parallel_decode; /* frame-based threading.*/
804
805	/*Context probabilities for reference frame prediction*/
806	/*MV_REFERENCE_FRAME comp_fixed_ref;*/
807	/*MV_REFERENCE_FRAME comp_var_ref[2];*/
808	enum REFERENCE_MODE reference_mode;
809
810	/*FRAME_CONTEXT *fc; */ /* this frame entropy */
811	/*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
812	/*unsigned int frame_context_idx; *//* Context to use/update */
813	/*FRAME_COUNTS counts;*/
814
815	unsigned int current_video_frame;
816	enum BITSTREAM_PROFILE profile;
817
818	enum vpx_bit_depth_t bit_depth;
819
820	int error_resilient_mode;
821	int frame_parallel_decoding_mode;
822
823	int byte_alignment;
824	int skip_loop_filter;
825
826	/*External BufferPool passed from outside.*/
827	struct BufferPool_s *buffer_pool;
828
829	int above_context_alloc_cols;
830
831	};
832
833	static void set_canvas(struct VP9Decoder_s *pbi,
834	struct PIC_BUFFER_CONFIG_s *pic_config);
835	static int prepare_display_buf(struct VP9Decoder_s *pbi,
836	struct PIC_BUFFER_CONFIG_s *pic_config);
837
838	static void fill_frame_info(struct VP9Decoder_s *pbi,
839	struct PIC_BUFFER_CONFIG_s *frame,
840	unsigned int framesize,
841	unsigned int pts);
842
843	static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
844	{
845	return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
846	}
847
848	static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
849	{
850	const int ref_index = *idx;
851
852	if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
853	bufs[ref_index].ref_count--;
854	/*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
855	* ref_index, bufs[ref_index].ref_count);
856	*/
857	}
858
859	*idx = new_idx;
860
861	bufs[new_idx].ref_count++;
862	/*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
863	* new_idx, bufs[new_idx].ref_count);
864	*/
865	}
866
867	int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
868	{
869	struct InternalFrameBuffer_s *const int_fb =
870	(struct InternalFrameBuffer_s *)fb->priv;
871	if (int_fb)
872	int_fb->in_use = 0;
873	return 0;
874	}
875
876	static int compute_losless_comp_body_size(int width, int height,
877	uint8_t is_bit_depth_10);
878
879	static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
880	int print_header_info)
881	{
882	cm->display_width = cm->width;
883	cm->display_height = cm->height;
884	if (params->p.display_size_present) {
885	if (print_header_info)
886	pr_info(" * 1-bit display_size_present read : 1\n");
887	cm->display_width = params->p.display_width;
888	cm->display_height = params->p.display_height;
889	/*vp9_read_frame_size(rb, &cm->display_width,
890	* &cm->display_height);
891	*/
892	} else {
893	if (print_header_info)
894	pr_info(" * 1-bit display_size_present read : 0\n");
895	}
896	}
897
898
899	uint8_t print_header_info = 0;
900
901	struct buff_s {
902	u32 buf_start;
903	u32 buf_size;
904	u32 buf_end;
905	} buff_t;
906
907	struct BuffInfo_s {
908	u32 max_width;
909	u32 max_height;
910	u32 start_adr;
911	u32 end_adr;
912	struct buff_s ipp;
913	struct buff_s sao_abv;
914	struct buff_s sao_vb;
915	struct buff_s short_term_rps;
916	struct buff_s vps;
917	struct buff_s sps;
918	struct buff_s pps;
919	struct buff_s sao_up;
920	struct buff_s swap_buf;
921	struct buff_s swap_buf2;
922	struct buff_s scalelut;
923	struct buff_s dblk_para;
924	struct buff_s dblk_data;
925	struct buff_s seg_map;
926	struct buff_s mmu_vbh;
927	struct buff_s cm_header;
928	struct buff_s mpred_above;
929	#ifdef MV_USE_FIXED_BUF
930	struct buff_s mpred_mv;
931	#endif
932	struct buff_s rpm;
933	struct buff_s lmem;
934	} BuffInfo_t;
935	#ifdef MULTI_INSTANCE_SUPPORT
936	#define DEC_RESULT_NONE 0
937	#define DEC_RESULT_DONE 1
938	#define DEC_RESULT_AGAIN 2
939	#define DEC_RESULT_CONFIG_PARAM 3
940	#define DEC_RESULT_ERROR 4
941	#define DEC_INIT_PICLIST 5
942	#define DEC_UNINIT_PICLIST 6
943	#define DEC_RESULT_GET_DATA 7
944	#define DEC_RESULT_GET_DATA_RETRY 8
945	#define DEC_RESULT_EOS 9
946	#define DEC_RESULT_FORCE_EXIT 10
947	#define DEC_V4L2_CONTINUE_DECODING 18
948
949	#define DEC_S1_RESULT_NONE 0
950	#define DEC_S1_RESULT_DONE 1
951	#define DEC_S1_RESULT_FORCE_EXIT 2
952	#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
953
954	#ifdef FB_DECODING_TEST_SCHEDULE
955	#define TEST_SET_NONE 0
956	#define TEST_SET_PIC_DONE 1
957	#define TEST_SET_S2_DONE 2
958	#endif
959
960	static void vp9_work(struct work_struct *work);
961	#endif
962	struct loop_filter_info_n;
963	struct loopfilter;
964	struct segmentation;
965
966	#ifdef SUPPORT_FB_DECODING
967	static void mpred_process(struct VP9Decoder_s *pbi);
968	static void vp9_s1_work(struct work_struct *work);
969
970	struct stage_buf_s {
971	int index;
972	unsigned short rpm[RPM_END - RPM_BEGIN];
973	};
974
975	static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
976
977	static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
978
979	#ifdef FB_DECODING_TEST_SCHEDULE
980	u32 stage_buf_num; /* = 16;*/
981	#else
982	u32 stage_buf_num;
983	#endif
984	#endif
985
986	struct VP9Decoder_s {
987	#ifdef MULTI_INSTANCE_SUPPORT
988	unsigned char index;
989
990	struct device *cma_dev;
991	struct platform_device *platform_dev;
992	void (*vdec_cb)(struct vdec_s *, void *);
993	void *vdec_cb_arg;
994	struct vframe_chunk_s *chunk;
995	int dec_result;
996	struct work_struct work;
997	struct work_struct set_clk_work;
998	u32 start_shift_bytes;
999
1000	struct BuffInfo_s work_space_buf_store;
1001	unsigned long buf_start;
1002	u32 buf_size;
1003	u32 cma_alloc_count;
1004	unsigned long cma_alloc_addr;
1005	uint8_t eos;
1006	unsigned long int start_process_time;
1007	unsigned last_lcu_idx;
1008	int decode_timeout_count;
1009	unsigned timeout_num;
1010	int save_buffer_mode;
1011
1012	int double_write_mode;
1013	#endif
1014	long used_4k_num;
1015
1016	unsigned char m_ins_flag;
1017	char *provider_name;
1018	union param_u param;
1019	int frame_count;
1020	int pic_count;
1021	u32 stat;
1022	struct timer_list timer;
1023	u32 frame_dur;
1024	u32 frame_ar;
1025	int fatal_error;
1026	uint8_t init_flag;
1027	uint8_t first_sc_checked;
1028	uint8_t process_busy;
1029	#define PROC_STATE_INIT 0
1030	#define PROC_STATE_DECODESLICE 1
1031	#define PROC_STATE_SENDAGAIN 2
1032	uint8_t process_state;
1033	u32 ucode_pause_pos;
1034
1035	int show_frame_num;
1036	struct buff_s mc_buf_spec;
1037	struct dec_sysinfo vvp9_amstream_dec_info;
1038	void *rpm_addr;
1039	void *lmem_addr;
1040	dma_addr_t rpm_phy_addr;
1041	dma_addr_t lmem_phy_addr;
1042	unsigned short *lmem_ptr;
1043	unsigned short *debug_ptr;
1044
1045	void *prob_buffer_addr;
1046	void *count_buffer_addr;
1047	dma_addr_t prob_buffer_phy_addr;
1048	dma_addr_t count_buffer_phy_addr;
1049
1050	void *frame_mmu_map_addr;
1051	dma_addr_t frame_mmu_map_phy_addr;
1052
1053	unsigned int use_cma_flag;
1054
1055	struct BUF_s m_BUF[MAX_BUF_NUM];
1056	struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1057	u32 used_buf_num;
1058	DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1059	DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1060	DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1061	struct vframe_s vfpool[VF_POOL_SIZE];
1062	u32 vf_pre_count;
1063	u32 vf_get_count;
1064	u32 vf_put_count;
1065	int buf_num;
1066	int pic_num;
1067	int lcu_size_log2;
1068	unsigned int losless_comp_body_size;
1069
1070	u32 video_signal_type;
1071
1072	int pts_mode;
1073	int last_lookup_pts;
1074	int last_pts;
1075	u64 last_lookup_pts_us64;
1076	u64 last_pts_us64;
1077	u64 shift_byte_count;
1078
1079	u32 pts_unstable;
1080	u32 frame_cnt_window;
1081	u32 pts1, pts2;
1082	u32 last_duration;
1083	u32 duration_from_pts_done;
1084	bool vp9_first_pts_ready;
1085
1086	u32 shift_byte_count_lo;
1087	u32 shift_byte_count_hi;
1088	int pts_mode_switching_count;
1089	int pts_mode_recovery_count;
1090
1091	bool get_frame_dur;
1092	u32 saved_resolution;
1093
1094	/**/
1095	struct VP9_Common_s common;
1096	struct RefCntBuffer_s *cur_buf;
1097	int refresh_frame_flags;
1098	uint8_t need_resync;
1099	uint8_t hold_ref_buf;
1100	uint8_t ready_for_new_data;
1101	struct BufferPool_s vp9_buffer_pool;
1102
1103	struct BuffInfo_s *work_space_buf;
1104
1105	struct buff_s *mc_buf;
1106
1107	unsigned int frame_width;
1108	unsigned int frame_height;
1109
1110	unsigned short *rpm_ptr;
1111	int init_pic_w;
1112	int init_pic_h;
1113	int lcu_total;
1114	int lcu_size;
1115
1116	int slice_type;
1117
1118	int skip_flag;
1119	int decode_idx;
1120	int slice_idx;
1121	uint8_t has_keyframe;
1122	uint8_t wait_buf;
1123	uint8_t error_flag;
1124
1125	/* bit 0, for decoding; bit 1, for displaying */
1126	uint8_t ignore_bufmgr_error;
1127	int PB_skip_mode;
1128	int PB_skip_count_after_decoding;
1129	/*hw*/
1130
1131	/*lf*/
1132	int default_filt_lvl;
1133	struct loop_filter_info_n *lfi;
1134	struct loopfilter *lf;
1135	struct segmentation *seg_4lf;
1136	/**/
1137	struct vdec_info *gvs;
1138
1139	u32 pre_stream_offset;
1140
1141	unsigned int dec_status;
1142	u32 last_put_idx;
1143	int new_frame_displayed;
1144	void *mmu_box;
1145	void *bmmu_box;
1146	int mmu_enable;
1147	struct vframe_master_display_colour_s vf_dp;
1148	struct firmware_s *fw;
1149	int max_pic_w;
1150	int max_pic_h;
1151	#ifdef SUPPORT_FB_DECODING
1152	int dec_s1_result;
1153	int s1_test_cmd;
1154	struct work_struct s1_work;
1155	int used_stage_buf_num;
1156	int s1_pos;
1157	int s2_pos;
1158	void *stage_mmu_map_addr;
1159	dma_addr_t stage_mmu_map_phy_addr;
1160	struct stage_buf_s *s1_buf;
1161	struct stage_buf_s *s2_buf;
1162	struct stage_buf_s *stage_bufs
1163	[STAGE_MAX_BUFFERS];
1164	unsigned char run2_busy;
1165
1166	int s1_mv_buf_index;
1167	int s1_mv_buf_index_pre;
1168	int s1_mv_buf_index_pre_pre;
1169	unsigned long s1_mpred_mv_wr_start_addr;
1170	unsigned long s1_mpred_mv_wr_start_addr_pre;
1171	unsigned short s1_intra_only;
1172	unsigned short s1_frame_type;
1173	unsigned short s1_width;
1174	unsigned short s1_height;
1175	unsigned short s1_last_show_frame;
1176	union param_u s1_param;
1177	u8 back_not_run_ready;
1178	#endif
1179	int need_cache_size;
1180	u64 sc_start_time;
1181	bool postproc_done;
1182	int low_latency_flag;
1183	bool no_head;
1184	bool pic_list_init_done;
1185	bool pic_list_init_done2;
1186	bool is_used_v4l;
1187	void *v4l2_ctx;
1188	bool v4l_params_parsed;
1189	int frameinfo_enable;
1190	struct vframe_qos_s vframe_qos;
1191	u32 mem_map_mode;
1192	u32 dynamic_buf_num_margin;
1193	struct vframe_s vframe_dummy;
1194	};
1195
1196	static int vp9_print(struct VP9Decoder_s *pbi,
1197	int flag, const char *fmt, ...)
1198	{
1199	#define HEVC_PRINT_BUF 256
1200	unsigned char buf[HEVC_PRINT_BUF];
1201	int len = 0;
1202
1203	if (pbi == NULL ||
1204	(flag == 0) ||
1205	(debug & flag)) {
1206	va_list args;
1207
1208	va_start(args, fmt);
1209	if (pbi)
1210	len = sprintf(buf, "[%d]", pbi->index);
1211	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1212	pr_debug("%s", buf);
1213	va_end(args);
1214	}
1215	return 0;
1216	}
1217
1218	static int is_oversize(int w, int h)
1219	{
1220	int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1221	MAX_SIZE_8K : MAX_SIZE_4K;
1222
1223	if (w <= 0 || h <= 0)
1224	return true;
1225
1226	if (h != 0 && (w > max / h))
1227	return true;
1228
1229	return false;
1230	}
1231
1232	static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1233	struct PIC_BUFFER_CONFIG_s *pic);
1234
1235	static void resize_context_buffers(struct VP9Decoder_s *pbi,
1236	struct VP9_Common_s *cm, int width, int height)
1237	{
1238	if (cm->width != width || cm->height != height) {
1239	/* to do ..*/
1240	if (pbi != NULL) {
1241	pbi->vp9_first_pts_ready = 0;
1242	pbi->duration_from_pts_done = 0;
1243	}
1244	pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1245	cm->height, width, height);
1246
1247	if (pbi->is_used_v4l) {
1248	struct PIC_BUFFER_CONFIG_s *pic = &cm->cur_frame->buf;
1249
1250	/* resolution change happend need to reconfig buffs if true. */
1251	if (pic->y_crop_width != width || pic->y_crop_height != height) {
1252	int i;
1253	for (i = 0; i < pbi->used_buf_num; i++) {
1254	pic = &cm->buffer_pool->frame_bufs[i].buf;
1255	pic->y_crop_width = width;
1256	pic->y_crop_height = height;
1257	if (!v4l_alloc_and_config_pic(pbi, pic))
1258	set_canvas(pbi, pic);
1259	else
1260	vp9_print(pbi, 0,
1261	"v4l: reconfig buff fail.\n");
1262	}
1263	}
1264	}
1265
1266	cm->width = width;
1267	cm->height = height;
1268	}
1269	/*
1270	*if (cm->cur_frame->mvs == NULL ||
1271	* cm->mi_rows > cm->cur_frame->mi_rows ||
1272	* cm->mi_cols > cm->cur_frame->mi_cols) {
1273	* resize_mv_buffer(cm);
1274	*}
1275	*/
1276	}
1277
1278	static int valid_ref_frame_size(int ref_width, int ref_height,
1279	int this_width, int this_height) {
1280	return 2 * this_width >= ref_width &&
1281	2 * this_height >= ref_height &&
1282	this_width <= 16 * ref_width &&
1283	this_height <= 16 * ref_height;
1284	}
1285
1286	/*
1287	*static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1288	* int ref_xss, int ref_yss,
1289	* enum vpx_bit_depth_t this_bit_depth,
1290	* int this_xss, int this_yss) {
1291	* return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1292	* ref_yss == this_yss;
1293	*}
1294	*/
1295
1296
1297	static int setup_frame_size(
1298	struct VP9Decoder_s *pbi,
1299	struct VP9_Common_s *cm, union param_u *params,
1300	unsigned int *mmu_index_adr,
1301	int print_header_info) {
1302	int width, height;
1303	struct BufferPool_s * const pool = cm->buffer_pool;
1304	struct PIC_BUFFER_CONFIG_s *ybf;
1305	int ret = 0;
1306
1307	width = params->p.width;
1308	height = params->p.height;
1309	if (is_oversize(width, height)) {
1310	vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1311	return -1;
1312	}
1313
1314	/*vp9_read_frame_size(rb, &width, &height);*/
1315	if (print_header_info)
1316	pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1317	if (print_header_info)
1318	pr_info
1319	(" * 16-bits h read : %d (height : %d)\n", width, height);
1320
1321	WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1322	#ifdef VP9_10B_HED_FB
1323	WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1324	#endif
1325	if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1326	ret = vp9_alloc_mmu(pbi,
1327	cm->new_fb_idx,
1328	params->p.width,
1329	params->p.height,
1330	params->p.bit_depth,
1331	mmu_index_adr);
1332	if (ret != 0) {
1333	pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1334	cm->new_fb_idx,
1335	ret);
1336	return ret;
1337	}
1338	cm->cur_fb_idx_mmu = cm->new_fb_idx;
1339	}
1340
1341	resize_context_buffers(pbi, cm, width, height);
1342	setup_display_size(cm, params, print_header_info);
1343	#if 0
1344	lock_buffer_pool(pool);
1345	if (vp9_realloc_frame_buffer(
1346	get_frame_new_buffer(cm), cm->width, cm->height,
1347	cm->subsampling_x, cm->subsampling_y,
1348	#if CONFIG_VP9_HIGHBITDEPTH
1349	cm->use_highbitdepth,
1350	#endif
1351	VP9_DEC_BORDER_IN_PIXELS,
1352	cm->byte_alignment,
1353	&pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1354	pool->get_fb_cb, pool->cb_priv)) {
1355	unlock_buffer_pool(pool);
1356	vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1357	"Failed to allocate frame buffer");
1358	}
1359	unlock_buffer_pool(pool);
1360	#else
1361	/* porting */
1362	ybf = get_frame_new_buffer(cm);
1363	if (!ybf)
1364	return -1;
1365
1366	ybf->y_crop_width = width;
1367	ybf->y_crop_height = height;
1368	ybf->bit_depth = params->p.bit_depth;
1369	#endif
1370	pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1371	pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1372	pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1373	(unsigned int)cm->bit_depth;
1374	pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1375	return ret;
1376	}
1377
1378	static int setup_frame_size_with_refs(
1379	struct VP9Decoder_s *pbi,
1380	struct VP9_Common_s *cm,
1381	union param_u *params,
1382	unsigned int *mmu_index_adr,
1383	int print_header_info) {
1384
1385	int width, height;
1386	int found = 0, i;
1387	int has_valid_ref_frame = 0;
1388	struct PIC_BUFFER_CONFIG_s *ybf;
1389	struct BufferPool_s * const pool = cm->buffer_pool;
1390	int ret = 0;
1391
1392	for (i = 0; i < REFS_PER_FRAME; ++i) {
1393	if ((params->p.same_frame_size >>
1394	(REFS_PER_FRAME - i - 1)) & 0x1) {
1395	struct PIC_BUFFER_CONFIG_s *const buf =
1396	cm->frame_refs[i].buf;
1397	/*if (print_header_info)
1398	* pr_info
1399	* ("1-bit same_frame_size[%d] read : 1\n", i);
1400	*/
1401	width = buf->y_crop_width;
1402	height = buf->y_crop_height;
1403	/*if (print_header_info)
1404	* pr_info
1405	* (" - same_frame_size width : %d\n", width);
1406	*/
1407	/*if (print_header_info)
1408	* pr_info
1409	* (" - same_frame_size height : %d\n", height);
1410	*/
1411	found = 1;
1412	break;
1413	} else {
1414	/*if (print_header_info)
1415	* pr_info
1416	* ("1-bit same_frame_size[%d] read : 0\n", i);
1417	*/
1418	}
1419	}
1420
1421	if (!found) {
1422	/*vp9_read_frame_size(rb, &width, &height);*/
1423	width = params->p.width;
1424	height = params->p.height;
1425	/*if (print_header_info)
1426	* pr_info
1427	* (" * 16-bits w read : %d (width : %d)\n",
1428	* width, height);
1429	*if (print_header_info)
1430	* pr_info
1431	* (" * 16-bits h read : %d (height : %d)\n",
1432	* width, height);
1433	*/
1434	}
1435
1436	if (is_oversize(width, height)) {
1437	vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1438	return -1;
1439	}
1440
1441	params->p.width = width;
1442	params->p.height = height;
1443
1444	WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1445	if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1446	/*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1447	*cm->prev_fb_idx = cm->new_fb_idx;
1448	*/
1449	/* pr_info
1450	* ("[DEBUG DEBUG]Before alloc_mmu,
1451	* prev_fb_idx : %d, new_fb_idx : %d\r\n",
1452	* cm->prev_fb_idx, cm->new_fb_idx);
1453	*/
1454	ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1455	params->p.width, params->p.height,
1456	params->p.bit_depth, mmu_index_adr);
1457	if (ret != 0) {
1458	pr_err("can't alloc need mmu,idx %d\r\n",
1459	cm->new_fb_idx);
1460	return ret;
1461	}
1462	cm->cur_fb_idx_mmu = cm->new_fb_idx;
1463	}
1464
1465	/*Check to make sure at least one of frames that this frame references
1466	*has valid dimensions.
1467	*/
1468	for (i = 0; i < REFS_PER_FRAME; ++i) {
1469	struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1470
1471	has_valid_ref_frame |=
1472	valid_ref_frame_size(ref_frame->buf->y_crop_width,
1473	ref_frame->buf->y_crop_height,
1474	width, height);
1475	}
1476	if (!has_valid_ref_frame) {
1477	pr_err("Error: Referenced frame has invalid size\r\n");
1478	return -1;
1479	}
1480	#if 0
1481	for (i = 0; i < REFS_PER_FRAME; ++i) {
1482	struct RefBuffer_s * const ref_frame =
1483	&cm->frame_refs[i];
1484	if (!valid_ref_frame_img_fmt(
1485	ref_frame->buf->bit_depth,
1486	ref_frame->buf->subsampling_x,
1487	ref_frame->buf->subsampling_y,
1488	cm->bit_depth,
1489	cm->subsampling_x,
1490	cm->subsampling_y))
1491	pr_err
1492	("Referenced frame incompatible color fmt\r\n");
1493	return -1;
1494	}
1495	#endif
1496	resize_context_buffers(pbi, cm, width, height);
1497	setup_display_size(cm, params, print_header_info);
1498
1499	#if 0
1500	lock_buffer_pool(pool);
1501	if (vp9_realloc_frame_buffer(
1502	get_frame_new_buffer(cm), cm->width, cm->height,
1503	cm->subsampling_x, cm->subsampling_y,
1504	#if CONFIG_VP9_HIGHBITDEPTH
1505	cm->use_highbitdepth,
1506	#endif
1507	VP9_DEC_BORDER_IN_PIXELS,
1508	cm->byte_alignment,
1509	&pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1510	pool->get_fb_cb,
1511	pool->cb_priv)) {
1512	unlock_buffer_pool(pool);
1513	vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1514	"Failed to allocate frame buffer");
1515	}
1516	unlock_buffer_pool(pool);
1517	#else
1518	/* porting */
1519	ybf = get_frame_new_buffer(cm);
1520	if (!ybf)
1521	return -1;
1522
1523	ybf->y_crop_width = width;
1524	ybf->y_crop_height = height;
1525	ybf->bit_depth = params->p.bit_depth;
1526	#endif
1527	pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1528	pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1529	pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1530	(unsigned int)cm->bit_depth;
1531	pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1532	return ret;
1533	}
1534
1535	static inline bool close_to(int a, int b, int m)
1536	{
1537	return (abs(a - b) < m) ? true : false;
1538	}
1539
1540	#ifdef MULTI_INSTANCE_SUPPORT
1541	static int vp9_print_cont(struct VP9Decoder_s *pbi,
1542	int flag, const char *fmt, ...)
1543	{
1544	unsigned char buf[HEVC_PRINT_BUF];
1545	int len = 0;
1546
1547	if (pbi == NULL ||
1548	(flag == 0) ||
1549	(debug & flag)) {
1550	va_list args;
1551
1552	va_start(args, fmt);
1553	vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1554	pr_debug("%s", buf);
1555	va_end(args);
1556	}
1557	return 0;
1558	}
1559
1560	static void trigger_schedule(struct VP9Decoder_s *pbi)
1561	{
1562	if (pbi->is_used_v4l) {
1563	struct aml_vcodec_ctx *ctx =
1564	(struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1565
1566	if (ctx->param_sets_from_ucode &&
1567	!pbi->v4l_params_parsed)
1568	vdec_v4l_write_frame_sync(ctx);
1569	}
1570
1571	if (pbi->vdec_cb)
1572	pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1573	}
1574
1575	static void reset_process_time(struct VP9Decoder_s *pbi)
1576	{
1577	if (pbi->start_process_time) {
1578	unsigned process_time =
1579	1000 * (jiffies - pbi->start_process_time) / HZ;
1580	pbi->start_process_time = 0;
1581	if (process_time > max_process_time[pbi->index])
1582	max_process_time[pbi->index] = process_time;
1583	}
1584	}
1585
1586	static void start_process_time(struct VP9Decoder_s *pbi)
1587	{
1588	pbi->start_process_time = jiffies;
1589	pbi->decode_timeout_count = 0;
1590	pbi->last_lcu_idx = 0;
1591	}
1592
1593	static void timeout_process(struct VP9Decoder_s *pbi)
1594	{
1595	pbi->timeout_num++;
1596	amhevc_stop();
1597	vp9_print(pbi,
1598	0, "%s decoder timeout\n", __func__);
1599
1600	pbi->dec_result = DEC_RESULT_DONE;
1601	reset_process_time(pbi);
1602	vdec_schedule_work(&pbi->work);
1603	}
1604
1605	static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1606	{
1607	return ((double_write_mode & 0x80000000) == 0) ?
1608	pbi->double_write_mode :
1609	(double_write_mode & 0x7fffffff);
1610	}
1611
1612	static int get_double_write_mode(struct VP9Decoder_s *pbi)
1613	{
1614	u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1615	u32 dw;
1616	int w, h;
1617	struct VP9_Common_s *cm = &pbi->common;
1618	struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1619
1620	/* mask for supporting double write value bigger than 0x100 */
1621	if (valid_dw_mode & 0xffffff00) {
1622	if (!cm->cur_frame)
1623	return 1;/*no valid frame,*/
1624	cur_pic_config = &cm->cur_frame->buf;
1625	w = cur_pic_config->y_crop_width;
1626	h = cur_pic_config->y_crop_height;
1627
1628	dw = 0x1; /*1:1*/
1629	switch (valid_dw_mode) {
1630	case 0x100:
1631	if (w > 1920 && h > 1088)
1632	dw = 0x4; /*1:2*/
1633	break;
1634	case 0x200:
1635	if (w > 1920 && h > 1088)
1636	dw = 0x2; /*1:4*/
1637	break;
1638	case 0x300:
1639	if (w > 1280 && h > 720)
1640	dw = 0x4; /*1:2*/
1641	break;
1642	default:
1643	break;
1644	}
1645	return dw;
1646	}
1647
1648	return valid_dw_mode;
1649	}
1650
1651	/* for double write buf alloc */
1652	static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1653	{
1654	u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1655	u32 dw;
1656	int w = pbi->init_pic_w;
1657	int h = pbi->init_pic_h;
1658
1659	dw = 0x1; /*1:1*/
1660	switch (valid_dw_mode) {
1661	case 0x100:
1662	if (w > 1920 && h > 1088)
1663	dw = 0x4; /*1:2*/
1664	break;
1665	case 0x200:
1666	if (w > 1920 && h > 1088)
1667	dw = 0x2; /*1:4*/
1668	break;
1669	case 0x300:
1670	if (w > 1280 && h > 720)
1671	dw = 0x4; /*1:2*/
1672	break;
1673	default:
1674	dw = valid_dw_mode;
1675	break;
1676	}
1677	return dw;
1678	}
1679	#endif
1680
1681	static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1682	int dw_mode)
1683	{
1684	int ratio = 1;
1685	if ((dw_mode == 2) ||
1686	(dw_mode == 3))
1687	ratio = 4;
1688	else if (dw_mode == 4)
1689	ratio = 2;
1690	return ratio;
1691	}
1692
1693	//#define MAX_4K_NUM 0x1200
1694
1695	int vp9_alloc_mmu(
1696	struct VP9Decoder_s *pbi,
1697	int cur_buf_idx,
1698	int pic_width,
1699	int pic_height,
1700	unsigned short bit_depth,
1701	unsigned int *mmu_index_adr)
1702	{
1703	int bit_depth_10 = (bit_depth == VPX_BITS_10);
1704	int picture_size;
1705	int cur_mmu_4k_number, max_frame_num;
1706	if (!pbi->mmu_box) {
1707	pr_err("error no mmu box!\n");
1708	return -1;
1709	}
1710	if (pbi->double_write_mode & 0x10)
1711	return 0;
1712	if (bit_depth >= VPX_BITS_12) {
1713	pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1714	pr_err("fatal_error, un support bit depth 12!\n\n");
1715	return -1;
1716	}
1717	picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1718	bit_depth_10);
1719	cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1720
1721	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1722	max_frame_num = MAX_FRAME_8K_NUM;
1723	else
1724	max_frame_num = MAX_FRAME_4K_NUM;
1725
1726	if (cur_mmu_4k_number > max_frame_num) {
1727	pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1728	cur_mmu_4k_number, pic_width, pic_height);
1729	return -1;
1730	}
1731	return decoder_mmu_box_alloc_idx(
1732	pbi->mmu_box,
1733	cur_buf_idx,
1734	cur_mmu_4k_number,
1735	mmu_index_adr);
1736	}
1737
1738
1739	#ifndef MV_USE_FIXED_BUF
1740	static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1741	{
1742	int i;
1743	for (i = 0; i < MV_BUFFER_NUM; i++) {
1744	if (pbi->m_mv_BUF[i].start_adr) {
1745	if (debug)
1746	pr_info(
1747	"dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1748	i, pbi->m_mv_BUF[i].start_adr,
1749	pbi->m_mv_BUF[i].size,
1750	pbi->m_mv_BUF[i].used_flag);
1751	decoder_bmmu_box_free_idx(
1752	pbi->bmmu_box,
1753	MV_BUFFER_IDX(i));
1754	pbi->m_mv_BUF[i].start_adr = 0;
1755	pbi->m_mv_BUF[i].size = 0;
1756	pbi->m_mv_BUF[i].used_flag = 0;
1757	}
1758	}
1759	}
1760
1761	static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1762	int i, int size)
1763	{
1764	int ret = 0;
1765	if (decoder_bmmu_box_alloc_buf_phy
1766	(pbi->bmmu_box,
1767	MV_BUFFER_IDX(i), size,
1768	DRIVER_NAME,
1769	&pbi->m_mv_BUF[i].start_adr) < 0) {
1770	pbi->m_mv_BUF[i].start_adr = 0;
1771	ret = -1;
1772	} else {
1773	pbi->m_mv_BUF[i].size = size;
1774	pbi->m_mv_BUF[i].used_flag = 0;
1775	ret = 0;
1776	if (debug) {
1777	pr_info(
1778	"MV Buffer %d: start_adr %p size %x\n",
1779	i,
1780	(void *)pbi->m_mv_BUF[i].start_adr,
1781	pbi->m_mv_BUF[i].size);
1782	}
1783	}
1784	return ret;
1785	}
1786
1787	static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1788	{
1789	int i;
1790	int ret = 0;
1791	int count = MV_BUFFER_NUM;
1792	int pic_width = pbi->init_pic_w;
1793	int pic_height = pbi->init_pic_h;
1794	int lcu_size = 64; /*fixed 64*/
1795	int pic_width_64 = (pic_width + 63) & (~0x3f);
1796	int pic_height_32 = (pic_height + 31) & (~0x1f);
1797	int pic_width_lcu = (pic_width_64 % lcu_size) ?
1798	pic_width_64 / lcu_size + 1
1799	: pic_width_64 / lcu_size;
1800	int pic_height_lcu = (pic_height_32 % lcu_size) ?
1801	pic_height_32 / lcu_size + 1
1802	: pic_height_32 / lcu_size;
1803	int lcu_total = pic_width_lcu * pic_height_lcu;
1804	int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1805	(~0xffff);
1806	if (mv_buf_margin > 0)
1807	count = REF_FRAMES + mv_buf_margin;
1808
1809	if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1810	count = REF_FRAMES_4K + mv_buf_margin;
1811
1812	if (debug) {
1813	pr_info("%s w:%d, h:%d, count: %d\n",
1814	__func__, pbi->init_pic_w, pbi->init_pic_h, count);
1815	}
1816
1817	for (i = 0;
1818	i < count && i < MV_BUFFER_NUM; i++) {
1819	if (alloc_mv_buf(pbi, i, size) < 0) {
1820	ret = -1;
1821	break;
1822	}
1823	}
1824	return ret;
1825	}
1826
1827	static int get_mv_buf(struct VP9Decoder_s *pbi,
1828	int *mv_buf_index,
1829	unsigned long *mpred_mv_wr_start_addr)
1830	{
1831	int i;
1832	int ret = -1;
1833	for (i = 0; i < MV_BUFFER_NUM; i++) {
1834	if (pbi->m_mv_BUF[i].start_adr &&
1835	pbi->m_mv_BUF[i].used_flag == 0) {
1836	pbi->m_mv_BUF[i].used_flag = 1;
1837	ret = i;
1838	break;
1839	}
1840	}
1841
1842	if (ret >= 0) {
1843	*mv_buf_index = ret;
1844	*mpred_mv_wr_start_addr =
1845	(pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1846	(~0xffff);
1847	if (debug & VP9_DEBUG_BUFMGR_MORE)
1848	pr_info(
1849	"%s => %d (%ld) size 0x%x\n",
1850	__func__, ret,
1851	*mpred_mv_wr_start_addr,
1852	pbi->m_mv_BUF[ret].size);
1853	} else {
1854	pr_info(
1855	"%s: Error, mv buf is not enough\n",
1856	__func__);
1857	}
1858	return ret;
1859	}
1860
1861	static void put_mv_buf(struct VP9Decoder_s *pbi,
1862	int *mv_buf_index)
1863	{
1864	int i = *mv_buf_index;
1865	if (i >= MV_BUFFER_NUM) {
1866	if (debug & VP9_DEBUG_BUFMGR_MORE)
1867	pr_info(
1868	"%s: index %d beyond range\n",
1869	__func__, i);
1870	return;
1871	}
1872	if (debug & VP9_DEBUG_BUFMGR_MORE)
1873	pr_info(
1874	"%s(%d): used_flag(%d)\n",
1875	__func__, i,
1876	pbi->m_mv_BUF[i].used_flag);
1877
1878	*mv_buf_index = -1;
1879	if (pbi->m_mv_BUF[i].start_adr &&
1880	pbi->m_mv_BUF[i].used_flag)
1881	pbi->m_mv_BUF[i].used_flag = 0;
1882	}
1883
1884	static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1885	{
1886	struct VP9_Common_s *const cm = &pbi->common;
1887	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1888	int i;
1889	for (i = 0; i < pbi->used_buf_num; ++i) {
1890	if ((frame_bufs[i].ref_count == 0) &&
1891	(frame_bufs[i].buf.index != -1) &&
1892	(frame_bufs[i].buf.mv_buf_index >= 0)
1893	)
1894	put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1895	}
1896	}
1897
1898	#ifdef SUPPORT_FB_DECODING
1899	static bool mv_buf_available(struct VP9Decoder_s *pbi)
1900	{
1901	int i;
1902	bool ret = 0;
1903	for (i = 0; i < MV_BUFFER_NUM; i++) {
1904	if (pbi->m_mv_BUF[i].start_adr &&
1905	pbi->m_mv_BUF[i].used_flag == 0) {
1906	ret = 1;
1907	break;
1908	}
1909	}
1910	return ret;
1911	}
1912	#endif
1913	#endif
1914
1915	#ifdef SUPPORT_FB_DECODING
1916	static void init_stage_buf(struct VP9Decoder_s *pbi)
1917	{
1918	uint i;
1919	for (i = 0; i < STAGE_MAX_BUFFERS
1920	&& i < stage_buf_num; i++) {
1921	pbi->stage_bufs[i] =
1922	vmalloc(sizeof(struct stage_buf_s));
1923	if (pbi->stage_bufs[i] == NULL) {
1924	vp9_print(pbi,
1925	0, "%s vmalloc fail\n", __func__);
1926	break;
1927	}
1928	pbi->stage_bufs[i]->index = i;
1929	}
1930	pbi->used_stage_buf_num = i;
1931	pbi->s1_pos = 0;
1932	pbi->s2_pos = 0;
1933	pbi->s1_buf = NULL;
1934	pbi->s2_buf = NULL;
1935	pbi->s1_mv_buf_index = FRAME_BUFFERS;
1936	pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1937	pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1938
1939	if (pbi->used_stage_buf_num > 0)
1940	vp9_print(pbi,
1941	0, "%s 2 stage decoding buf %d\n",
1942	__func__,
1943	pbi->used_stage_buf_num);
1944	}
1945
1946	static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1947	{
1948	int i;
1949	for (i = 0; i < pbi->used_stage_buf_num; i++) {
1950	if (pbi->stage_bufs[i])
1951	vfree(pbi->stage_bufs[i]);
1952	pbi->stage_bufs[i] = NULL;
1953	}
1954	pbi->used_stage_buf_num = 0;
1955	pbi->s1_pos = 0;
1956	pbi->s2_pos = 0;
1957	pbi->s1_buf = NULL;
1958	pbi->s2_buf = NULL;
1959	}
1960
1961	static int get_s1_buf(
1962	struct VP9Decoder_s *pbi)
1963	{
1964	struct stage_buf_s *buf = NULL;
1965	int ret = -1;
1966	int buf_page_num = MAX_STAGE_PAGE_NUM;
1967	int next_s1_pos = pbi->s1_pos + 1;
1968
1969	if (next_s1_pos >= pbi->used_stage_buf_num)
1970	next_s1_pos = 0;
1971	if (next_s1_pos == pbi->s2_pos) {
1972	pbi->s1_buf = NULL;
1973	return ret;
1974	}
1975
1976	buf = pbi->stage_bufs[pbi->s1_pos];
1977	ret = decoder_mmu_box_alloc_idx(
1978	pbi->mmu_box,
1979	buf->index,
1980	buf_page_num,
1981	pbi->stage_mmu_map_addr);
1982	if (ret < 0) {
1983	vp9_print(pbi, 0,
1984	"%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1985	__func__, buf->index,
1986	pbi->s1_pos, pbi->s2_pos);
1987	buf = NULL;
1988	} else {
1989	vp9_print(pbi, VP9_DEBUG_2_STAGE,
1990	"%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1991	__func__, buf_page_num, buf->index,
1992	pbi->s1_pos, pbi->s2_pos);
1993	}
1994	pbi->s1_buf = buf;
1995	return ret;
1996	}
1997
1998	static void inc_s1_pos(struct VP9Decoder_s *pbi)
1999	{
2000	struct stage_buf_s *buf =
2001	pbi->stage_bufs[pbi->s1_pos];
2002
2003	int used_page_num =
2004	#ifdef FB_DECODING_TEST_SCHEDULE
2005	MAX_STAGE_PAGE_NUM/2;
2006	#else
2007	(READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
2008	#endif
2009	decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2010	FRAME_BUFFERS + buf->index, used_page_num);
2011
2012	pbi->s1_pos++;
2013	if (pbi->s1_pos >= pbi->used_stage_buf_num)
2014	pbi->s1_pos = 0;
2015
2016	vp9_print(pbi, VP9_DEBUG_2_STAGE,
2017	"%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
2018	__func__, used_page_num, buf->index,
2019	pbi->s1_pos, pbi->s2_pos);
2020	}
2021
2022	#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2023
2024	static int get_s2_buf(
2025	struct VP9Decoder_s *pbi)
2026	{
2027	int ret = -1;
2028	struct stage_buf_s *buf = NULL;
2029	if (s2_buf_available(pbi)) {
2030	buf = pbi->stage_bufs[pbi->s2_pos];
2031	vp9_print(pbi, VP9_DEBUG_2_STAGE,
2032	"%s for index %d (s1_pos %d s2_pos %d)\n",
2033	__func__, buf->index,
2034	pbi->s1_pos, pbi->s2_pos);
2035	pbi->s2_buf = buf;
2036	ret = 0;
2037	}
2038	return ret;
2039	}
2040
2041	static void inc_s2_pos(struct VP9Decoder_s *pbi)
2042	{
2043	struct stage_buf_s *buf =
2044	pbi->stage_bufs[pbi->s2_pos];
2045	decoder_mmu_box_free_idx(pbi->mmu_box,
2046	FRAME_BUFFERS + buf->index);
2047	pbi->s2_pos++;
2048	if (pbi->s2_pos >= pbi->used_stage_buf_num)
2049	pbi->s2_pos = 0;
2050	vp9_print(pbi, VP9_DEBUG_2_STAGE,
2051	"%s for index %d (s1_pos %d s2_pos %d)\n",
2052	__func__, buf->index,
2053	pbi->s1_pos, pbi->s2_pos);
2054	}
2055
2056	static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2057	{
2058	int num;
2059	if (pbi->s1_pos >= pbi->s2_pos)
2060	num = pbi->used_stage_buf_num -
2061	(pbi->s1_pos - pbi->s2_pos) - 1;
2062	else
2063	num = (pbi->s2_pos - pbi->s1_pos) - 1;
2064	return num;
2065	}
2066
2067	#ifndef FB_DECODING_TEST_SCHEDULE
2068	static DEFINE_SPINLOCK(fb_core_spin_lock);
2069
2070	static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2071	{
2072	/* to do: VLSI review
2073	completion of last LCU decoding in BACK
2074	*/
2075	return 1;
2076	}
2077
2078	static void start_s1_decoding(struct VP9Decoder_s *pbi)
2079	{
2080	/* to do: VLSI review
2081	after parser, how to start LCU decoding in BACK
2082	*/
2083	}
2084
2085	static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2086	{
2087	/* to do: VLSI review
2088	1. how to disconnect DMC for FRONT and BACK
2089	2. reset bit 13, 24, FRONT or BACK ??
2090	*/
2091
2092	unsigned long flags;
2093	u32 reset_bits = 0;
2094	if (mask & HW_MASK_FRONT)
2095	WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2096	spin_lock_irqsave(&fb_core_spin_lock, flags);
2097	codec_dmcbus_write(DMC_REQ_CTRL,
2098	codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2099	spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2100
2101	while (!(codec_dmcbus_read(DMC_CHAN_STS)
2102	& (1 << 4)))
2103	;
2104
2105	if ((mask & HW_MASK_FRONT) &&
2106	input_frame_based(vdec))
2107	WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2108
2109	/*
2110	* 2: assist
2111	* 3: parser
2112	* 4: parser_state
2113	* 8: dblk
2114	* 11:mcpu
2115	* 12:ccpu
2116	* 13:ddr
2117	* 14:iqit
2118	* 15:ipp
2119	* 17:qdct
2120	* 18:mpred
2121	* 19:sao
2122	* 24:hevc_afifo
2123	*/
2124	if (mask & HW_MASK_FRONT) {
2125	reset_bits =
2126	(1<<3)|(1<<4)|(1<<11)|
2127	(1<<12)|(1<<18);
2128	}
2129	if (mask & HW_MASK_BACK) {
2130	reset_bits =
2131	(1<<8)|(1<<13)|(1<<14)|(1<<15)|
2132	(1<<17)|(1<<19)|(1<<24);
2133	}
2134	WRITE_VREG(DOS_SW_RESET3, reset_bits);
2135	#if 0
2136	(1<<3)|(1<<4)|(1<<8)|(1<<11)|
2137	(1<<12)|(1<<13)|(1<<14)|(1<<15)|
2138	(1<<17)|(1<<18)|(1<<19)|(1<<24);
2139	#endif
2140	WRITE_VREG(DOS_SW_RESET3, 0);
2141
2142
2143	spin_lock_irqsave(&fb_core_spin_lock, flags);
2144	codec_dmcbus_write(DMC_REQ_CTRL,
2145	codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2146	spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2147
2148	}
2149	#endif
2150
2151	#endif
2152
2153	static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2154
2155	static int get_free_fb(struct VP9Decoder_s *pbi)
2156	{
2157	struct VP9_Common_s *const cm = &pbi->common;
2158	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2159	struct PIC_BUFFER_CONFIG_s *pic = NULL;
2160	int i;
2161	unsigned long flags;
2162
2163	lock_buffer_pool(cm->buffer_pool, flags);
2164	if (debug & VP9_DEBUG_BUFMGR_MORE) {
2165	for (i = 0; i < pbi->used_buf_num; ++i) {
2166	pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2167	__func__, i, frame_bufs[i].ref_count,
2168	frame_bufs[i].buf.vf_ref,
2169	frame_bufs[i].buf.index);
2170	}
2171	}
2172	for (i = 0; i < pbi->used_buf_num; ++i) {
2173	pic = &frame_bufs[i].buf;
2174	if ((frame_bufs[i].ref_count == 0) &&
2175	(pic->vf_ref == 0) && (pic->index != -1)) {
2176	if (pbi->is_used_v4l && !pic->cma_alloc_addr) {
2177	pic->y_crop_width = pbi->frame_width;
2178	pic->y_crop_height = pbi->frame_height;
2179	if (!v4l_alloc_and_config_pic(pbi, pic)) {
2180	set_canvas(pbi, pic);
2181	init_pic_list_hw(pbi);
2182	} else
2183	i = pbi->used_buf_num;
2184	}
2185
2186	break;
2187	}
2188	}
2189	if (i != pbi->used_buf_num) {
2190	frame_bufs[i].ref_count = 1;
2191	/*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2192	i, frame_bufs[i].ref_count);*/
2193	} else {
2194	/* Reset i to be INVALID_IDX to indicate
2195	no free buffer found*/
2196	i = INVALID_IDX;
2197	}
2198
2199	unlock_buffer_pool(cm->buffer_pool, flags);
2200	return i;
2201	}
2202
2203	static int get_free_buf_count(struct VP9Decoder_s *pbi)
2204	{
2205	struct VP9_Common_s *const cm = &pbi->common;
2206	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2207	int i;
2208	int free_buf_count = 0;
2209	for (i = 0; i < pbi->used_buf_num; ++i)
2210	if ((frame_bufs[i].ref_count == 0) &&
2211	(frame_bufs[i].buf.vf_ref == 0) &&
2212	(frame_bufs[i].buf.index != -1)
2213	)
2214	free_buf_count++;
2215	return free_buf_count;
2216	}
2217
2218	static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2219	struct BufferPool_s *const pool)
2220	{
2221	if (idx >= 0) {
2222	--frame_bufs[idx].ref_count;
2223	/*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2224	* frame_bufs[idx].ref_count);
2225	*/
2226	/*A worker may only get a free framebuffer index when
2227	*calling get_free_fb. But the private buffer is not set up
2228	*until finish decoding header. So any error happens during
2229	*decoding header, the frame_bufs will not have valid priv
2230	*buffer.
2231	*/
2232
2233	if (frame_bufs[idx].ref_count == 0 &&
2234	frame_bufs[idx].raw_frame_buffer.priv)
2235	vp9_release_frame_buffer
2236	(&frame_bufs[idx].raw_frame_buffer);
2237	}
2238	}
2239
2240	static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2241	{
2242	struct VP9_Common_s *const cm = &pbi->common;
2243	struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2244	struct BufferPool_s *const pool = cm->buffer_pool;
2245	int mask, ref_index = 0;
2246	unsigned long flags;
2247
2248	/* Generate next_ref_frame_map.*/
2249	lock_buffer_pool(pool, flags);
2250	for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2251	if (mask & 1) {
2252	cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2253	++frame_bufs[cm->new_fb_idx].ref_count;
2254	/*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2255	*cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2256	*/
2257	} else
2258	cm->next_ref_frame_map[ref_index] =
2259	cm->ref_frame_map[ref_index];
2260	/* Current thread holds the reference frame.*/
2261	if (cm->ref_frame_map[ref_index] >= 0) {
2262	++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2263	/*pr_info
2264	*("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2265	*cm->ref_frame_map[ref_index],
2266	*frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2267	*/
2268	}
2269	++ref_index;
2270	}
2271
2272	for (; ref_index < REF_FRAMES; ++ref_index) {
2273	cm->next_ref_frame_map[ref_index] =
2274	cm->ref_frame_map[ref_index];
2275	/* Current thread holds the reference frame.*/
2276	if (cm->ref_frame_map[ref_index] >= 0) {
2277	++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2278	/*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2279	*cm->ref_frame_map[ref_index],
2280	*frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2281	*/
2282	}
2283	}
2284	unlock_buffer_pool(pool, flags);
2285	return;
2286	}
2287
2288	static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2289
2290	{
2291	struct VP9_Common_s *const cm = &pbi->common;
2292	struct BufferPool_s *pool = cm->buffer_pool;
2293	struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2294	int mask, ref_index = 0;
2295	unsigned long flags;
2296
2297	lock_buffer_pool(pool, flags);
2298	for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2299	const int old_idx = cm->ref_frame_map[ref_index];
2300	/*Current thread releases the holding of reference frame.*/
2301	decrease_ref_count(old_idx, frame_bufs, pool);
2302
2303	/*Release the reference frame in reference map.*/
2304	if ((mask & 1) && old_idx >= 0)
2305	decrease_ref_count(old_idx, frame_bufs, pool);
2306	cm->ref_frame_map[ref_index] =
2307	cm->next_ref_frame_map[ref_index];
2308	++ref_index;
2309	}
2310
2311	/*Current thread releases the holding of reference frame.*/
2312	for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2313	++ref_index) {
2314	const int old_idx = cm->ref_frame_map[ref_index];
2315
2316	decrease_ref_count(old_idx, frame_bufs, pool);
2317	cm->ref_frame_map[ref_index] =
2318	cm->next_ref_frame_map[ref_index];
2319	}
2320	unlock_buffer_pool(pool, flags);
2321	return;
2322	}
2323
2324	int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2325	{
2326	struct VP9_Common_s *const cm = &pbi->common;
2327	struct BufferPool_s *pool = cm->buffer_pool;
2328	struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2329	struct PIC_BUFFER_CONFIG_s *pic = NULL;
2330	int i;
2331	int ret;
2332
2333	pbi->ready_for_new_data = 0;
2334
2335	if (pbi->has_keyframe == 0 &&
2336	params->p.frame_type != KEY_FRAME){
2337	on_no_keyframe_skiped++;
2338	return -2;
2339	}
2340	pbi->has_keyframe = 1;
2341	on_no_keyframe_skiped = 0;
2342	#if 0
2343	if (pbi->mmu_enable) {
2344	if (!pbi->m_ins_flag)
2345	pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2346	if (cm->prev_fb_idx >= 0) {
2347	decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2348	cm->prev_fb_idx, pbi->used_4k_num);
2349	}
2350	}
2351	#endif
2352	if (cm->new_fb_idx >= 0
2353	&& frame_bufs[cm->new_fb_idx].ref_count == 0){
2354	vp9_release_frame_buffer
2355	(&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2356	}
2357	/*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2358	cm->prev_fb_idx, cm->new_fb_idx);*/
2359	#ifndef MV_USE_FIXED_BUF
2360	put_un_used_mv_bufs(pbi);
2361	if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2362	dump_pic_list(pbi);
2363	#endif
2364	cm->new_fb_idx = get_free_fb(pbi);
2365	if (cm->new_fb_idx == INVALID_IDX) {
2366	pr_info("get_free_fb error\r\n");
2367	return -1;
2368	}
2369	#ifndef MV_USE_FIXED_BUF
2370	#ifdef SUPPORT_FB_DECODING
2371	if (pbi->used_stage_buf_num == 0) {
2372	#endif
2373	if (get_mv_buf(pbi,
2374	&pool->frame_bufs[cm->new_fb_idx].
2375	buf.mv_buf_index,
2376	&pool->frame_bufs[cm->new_fb_idx].
2377	buf.mpred_mv_wr_start_addr
2378	) < 0) {
2379	pr_info("get_mv_buf fail\r\n");
2380	return -1;
2381	}
2382	if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2383	dump_pic_list(pbi);
2384	#ifdef SUPPORT_FB_DECODING
2385	}
2386	#endif
2387	#endif
2388	cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2389	/*if (debug & VP9_DEBUG_BUFMGR)
2390	pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2391	cm->new_fb_idx);*/
2392
2393	pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2394	if (pbi->mmu_enable) {
2395	/* moved to after picture size ready
2396	*alloc_mmu(cm, params->p.width, params->p.height,
2397	*params->p.bit_depth, pbi->frame_mmu_map_addr);
2398	*/
2399	cm->prev_fb_idx = cm->new_fb_idx;
2400	}
2401	/*read_uncompressed_header()*/
2402	cm->last_frame_type = cm->frame_type;
2403	cm->last_intra_only = cm->intra_only;
2404	cm->profile = params->p.profile;
2405	if (cm->profile >= MAX_PROFILES) {
2406	pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2407	return -1;
2408	}
2409	cm->show_existing_frame = params->p.show_existing_frame;
2410	if (cm->show_existing_frame) {
2411	/* Show an existing frame directly.*/
2412	int frame_to_show_idx = params->p.frame_to_show_idx;
2413	int frame_to_show;
2414	unsigned long flags;
2415	if (frame_to_show_idx >= REF_FRAMES) {
2416	pr_info("frame_to_show_idx %d exceed max index\r\n",
2417	frame_to_show_idx);
2418	return -1;
2419	}
2420
2421	frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2422	/*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2423	lock_buffer_pool(pool, flags);
2424	if (frame_to_show < 0 ||
2425	frame_bufs[frame_to_show].ref_count < 1) {
2426	unlock_buffer_pool(pool, flags);
2427	pr_err
2428	("Error:Buffer %d does not contain a decoded frame",
2429	frame_to_show);
2430	return -1;
2431	}
2432
2433	ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2434	unlock_buffer_pool(pool, flags);
2435	pbi->refresh_frame_flags = 0;
2436	/*cm->lf.filter_level = 0;*/
2437	cm->show_frame = 1;
2438
2439	/*
2440	*if (pbi->frame_parallel_decode) {
2441	* for (i = 0; i < REF_FRAMES; ++i)
2442	* cm->next_ref_frame_map[i] =
2443	* cm->ref_frame_map[i];
2444	*}
2445	*/
2446	/* do not decode, search next start code */
2447	return 1;
2448	}
2449	cm->frame_type = params->p.frame_type;
2450	cm->show_frame = params->p.show_frame;
2451	cm->error_resilient_mode = params->p.error_resilient_mode;
2452
2453
2454	if (cm->frame_type == KEY_FRAME) {
2455	pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2456
2457	for (i = 0; i < REFS_PER_FRAME; ++i) {
2458	cm->frame_refs[i].idx = INVALID_IDX;
2459	cm->frame_refs[i].buf = NULL;
2460	}
2461
2462	ret = setup_frame_size(pbi,
2463	cm, params, pbi->frame_mmu_map_addr,
2464	print_header_info);
2465	if (ret)
2466	return -1;
2467	if (pbi->need_resync) {
2468	memset(&cm->ref_frame_map, -1,
2469	sizeof(cm->ref_frame_map));
2470	pbi->need_resync = 0;
2471	}
2472	} else {
2473	cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2474	/*if (print_header_info) {
2475	* if (cm->show_frame)
2476	* pr_info
2477	* ("intra_only set to 0 because of show_frame\n");
2478	* else
2479	* pr_info
2480	* ("1-bit intra_only read: %d\n", cm->intra_only);
2481	*}
2482	*/
2483
2484
2485	cm->reset_frame_context = cm->error_resilient_mode ?
2486	0 : params->p.reset_frame_context;
2487	if (print_header_info) {
2488	if (cm->error_resilient_mode)
2489	pr_info
2490	("reset to 0 error_resilient_mode\n");
2491	else
2492	pr_info
2493	(" * 2-bits reset_frame_context read : %d\n",
2494	cm->reset_frame_context);
2495	}
2496
2497	if (cm->intra_only) {
2498	if (cm->profile > PROFILE_0) {
2499	/*read_bitdepth_colorspace_sampling(cm,
2500	* rb, print_header_info);
2501	*/
2502	} else {
2503	/*NOTE: The intra-only frame header
2504	*does not include the specification
2505	*of either the color format or
2506	*color sub-sampling
2507	*in profile 0. VP9 specifies that the default
2508	*color format should be YUV 4:2:0 in this
2509	*case (normative).
2510	*/
2511	cm->color_space = VPX_CS_BT_601;
2512	cm->subsampling_y = cm->subsampling_x = 1;
2513	cm->bit_depth = VPX_BITS_8;
2514	cm->use_highbitdepth = 0;
2515	}
2516
2517	pbi->refresh_frame_flags =
2518	params->p.refresh_frame_flags;
2519	/*if (print_header_info)
2520	* pr_info("*%d-bits refresh_frame read:0x%x\n",
2521	* REF_FRAMES, pbi->refresh_frame_flags);
2522	*/
2523	ret = setup_frame_size(pbi,
2524	cm,
2525	params,
2526	pbi->frame_mmu_map_addr,
2527	print_header_info);
2528	if (ret)
2529	return -1;
2530	if (pbi->need_resync) {
2531	memset(&cm->ref_frame_map, -1,
2532	sizeof(cm->ref_frame_map));
2533	pbi->need_resync = 0;
2534	}
2535	} else if (pbi->need_resync != 1) { /* Skip if need resync */
2536	pbi->refresh_frame_flags =
2537	params->p.refresh_frame_flags;
2538	if (print_header_info)
2539	pr_info
2540	("*%d-bits refresh_frame read:0x%x\n",
2541	REF_FRAMES, pbi->refresh_frame_flags);
2542	for (i = 0; i < REFS_PER_FRAME; ++i) {
2543	const int ref =
2544	(params->p.ref_info >>
2545	(((REFS_PER_FRAME-i-1)*4)+1))
2546	& 0x7;
2547	const int idx =
2548	cm->ref_frame_map[ref];
2549	struct RefBuffer_s * const ref_frame =
2550	&cm->frame_refs[i];
2551	if (print_header_info)
2552	pr_info("*%d-bits ref[%d]read:%d\n",
2553	REF_FRAMES_LOG2, i, ref);
2554	ref_frame->idx = idx;
2555	ref_frame->buf = &frame_bufs[idx].buf;
2556	cm->ref_frame_sign_bias[LAST_FRAME + i]
2557	= (params->p.ref_info >>
2558	((REFS_PER_FRAME-i-1)*4)) & 0x1;
2559	if (print_header_info)
2560	pr_info("1bit ref_frame_sign_bias");
2561	/*pr_info
2562	*("%dread: %d\n",
2563	*LAST_FRAME+i,
2564	*cm->ref_frame_sign_bias
2565	*[LAST_FRAME + i]);
2566	*/
2567	/*pr_info
2568	*("[VP9 DEBUG]%s(get ref):%d\r\n",
2569	*__func__, ref_frame->idx);
2570	*/
2571
2572	}
2573
2574	ret = setup_frame_size_with_refs(
2575	pbi,
2576	cm,
2577	params,
2578	pbi->frame_mmu_map_addr,
2579	print_header_info);
2580	if (ret)
2581	return -1;
2582	for (i = 0; i < REFS_PER_FRAME; ++i) {
2583	/*struct RefBuffer_s *const ref_buf =
2584	*&cm->frame_refs[i];
2585	*/
2586	/* to do:
2587	*vp9_setup_scale_factors_for_frame
2588	*/
2589	}
2590	}
2591	}
2592
2593	pic = get_frame_new_buffer(cm);
2594	if (!pic)
2595	return -1;
2596
2597	pic->bit_depth = cm->bit_depth;
2598	pic->color_space = cm->color_space;
2599	pic->slice_type = cm->frame_type;
2600
2601	if (pbi->need_resync) {
2602	pr_err
2603	("Error: Keyframe/intra-only frame required to reset\r\n");
2604	return -1;
2605	}
2606	generate_next_ref_frames(pbi);
2607	pbi->hold_ref_buf = 1;
2608
2609	#if 0
2610	if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2611	vp9_setup_past_independence(cm);
2612	setup_loopfilter(&cm->lf, rb, print_header_info);
2613	setup_quantization(cm, &pbi->mb, rb, print_header_info);
2614	setup_segmentation(&cm->seg, rb, print_header_info);
2615	setup_segmentation_dequant(cm, print_header_info);
2616
2617	setup_tile_info(cm, rb, print_header_info);
2618	sz = vp9_rb_read_literal(rb, 16);
2619	if (print_header_info)
2620	pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2621
2622	if (sz == 0)
2623	vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2624	"Invalid header size");
2625	#endif
2626	/*end read_uncompressed_header()*/
2627	cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2628	cm->width == cm->last_width &&
2629	cm->height == cm->last_height &&
2630	!cm->last_intra_only &&
2631	cm->last_show_frame &&
2632	(cm->last_frame_type != KEY_FRAME);
2633
2634	/*pr_info
2635	*("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2636	*cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2637	*pr_info
2638	*(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2639	*cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2640	*/
2641	return 0;
2642	}
2643
2644
2645	void swap_frame_buffers(struct VP9Decoder_s *pbi)
2646	{
2647	int ref_index = 0;
2648	struct VP9_Common_s *const cm = &pbi->common;
2649	struct BufferPool_s *const pool = cm->buffer_pool;
2650	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2651	unsigned long flags;
2652	refresh_ref_frames(pbi);
2653	pbi->hold_ref_buf = 0;
2654	cm->frame_to_show = get_frame_new_buffer(cm);
2655
2656	if (cm->frame_to_show) {
2657	/*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2658	lock_buffer_pool(pool, flags);
2659	--frame_bufs[cm->new_fb_idx].ref_count;
2660	/*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2661	* frame_bufs[cm->new_fb_idx].ref_count);
2662	*/
2663	unlock_buffer_pool(pool, flags);
2664	/*}*/
2665	}
2666
2667	/*Invalidate these references until the next frame starts.*/
2668	for (ref_index = 0; ref_index < 3; ref_index++)
2669	cm->frame_refs[ref_index].idx = -1;
2670	}
2671
2672	#if 0
2673	static void check_resync(vpx_codec_alg_priv_t *const ctx,
2674	const struct VP9Decoder_s *const pbi)
2675	{
2676	/* Clear resync flag if worker got a key frame or intra only frame.*/
2677	if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2678	(pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2679	ctx->need_resync = 0;
2680	}
2681	#endif
2682
2683	int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2684	{
2685	struct VP9_Common_s *const cm = &pbi->common;
2686	int ret = -1;
2687
2688	if (pbi->ready_for_new_data == 1)
2689	return ret;
2690
2691	pbi->ready_for_new_data = 1;
2692
2693	/* no raw frame to show!!! */
2694	if (!cm->show_frame)
2695	return ret;
2696
2697	/* may not be get buff in v4l2 */
2698	if (!cm->frame_to_show)
2699	return ret;
2700
2701	pbi->ready_for_new_data = 1;
2702
2703	*sd = *cm->frame_to_show;
2704	ret = 0;
2705
2706	return ret;
2707	}
2708
2709	int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2710	struct buff_s *mc_buf_i) {
2711	struct VP9_Common_s *cm = &pbi->common;
2712
2713	/*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2714	pbi->frame_count = 0;
2715	pbi->pic_count = 0;
2716	pbi->pre_stream_offset = 0;
2717	cm->buffer_pool = &pbi->vp9_buffer_pool;
2718	spin_lock_init(&cm->buffer_pool->lock);
2719	cm->prev_fb_idx = INVALID_IDX;
2720	cm->new_fb_idx = INVALID_IDX;
2721	pbi->used_4k_num = -1;
2722	cm->cur_fb_idx_mmu = INVALID_IDX;
2723	pr_debug
2724	("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2725	cm->prev_fb_idx, cm->new_fb_idx);
2726	pbi->need_resync = 1;
2727	/* Initialize the references to not point to any frame buffers.*/
2728	memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2729	memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2730	cm->current_video_frame = 0;
2731	pbi->ready_for_new_data = 1;
2732
2733	/* private init */
2734	pbi->work_space_buf = buf_spec_i;
2735	if (!pbi->mmu_enable)
2736	pbi->mc_buf = mc_buf_i;
2737
2738	pbi->rpm_addr = NULL;
2739	pbi->lmem_addr = NULL;
2740
2741	pbi->use_cma_flag = 0;
2742	pbi->decode_idx = 0;
2743	pbi->slice_idx = 0;
2744	/*int m_uiMaxCUWidth = 1<<7;*/
2745	/*int m_uiMaxCUHeight = 1<<7;*/
2746	pbi->has_keyframe = 0;
2747	pbi->skip_flag = 0;
2748	pbi->wait_buf = 0;
2749	pbi->error_flag = 0;
2750
2751	pbi->pts_mode = PTS_NORMAL;
2752	pbi->last_pts = 0;
2753	pbi->last_lookup_pts = 0;
2754	pbi->last_pts_us64 = 0;
2755	pbi->last_lookup_pts_us64 = 0;
2756	pbi->shift_byte_count = 0;
2757	pbi->shift_byte_count_lo = 0;
2758	pbi->shift_byte_count_hi = 0;
2759	pbi->pts_mode_switching_count = 0;
2760	pbi->pts_mode_recovery_count = 0;
2761
2762	pbi->buf_num = 0;
2763	pbi->pic_num = 0;
2764
2765	return 0;
2766	}
2767
2768	int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2769	{
2770	struct VP9_Common_s *cm = &pbi->common;
2771	struct PIC_BUFFER_CONFIG_s sd;
2772
2773	if (pbi->postproc_done)
2774	return 0;
2775	pbi->postproc_done = 1;
2776	swap_frame_buffers(pbi);
2777	if (!cm->show_existing_frame) {
2778	cm->last_show_frame = cm->show_frame;
2779	cm->prev_frame = cm->cur_frame;
2780	#if 0
2781	if (cm->seg.enabled && !pbi->frame_parallel_decode)
2782	vp9_swap_current_and_last_seg_map(cm);
2783	#endif
2784	}
2785	cm->last_width = cm->width;
2786	cm->last_height = cm->height;
2787	if (cm->show_frame)
2788	cm->current_video_frame++;
2789
2790	if (vp9_get_raw_frame(pbi, &sd) == 0) {
2791	/*pr_info("Display frame index %d\r\n", sd.index);*/
2792	sd.stream_offset = pbi->pre_stream_offset;
2793	prepare_display_buf(pbi, &sd);
2794	pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2795	}
2796
2797	/* else
2798	* pr_info
2799	* ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2800	* pbi->ready_for_new_data, cm->show_frame);
2801	*/
2802	return 0;
2803	}
2804
2805	/*struct VP9Decoder_s vp9_decoder;*/
2806	union param_u vp9_param;
2807
2808	/**************************************************
2809	*
2810	*VP9 buffer management end
2811	*
2812	***************************************************
2813	*/
2814
2815
2816	#define HEVC_CM_BODY_START_ADDR 0x3626
2817	#define HEVC_CM_BODY_LENGTH 0x3627
2818	#define HEVC_CM_HEADER_LENGTH 0x3629
2819	#define HEVC_CM_HEADER_OFFSET 0x362b
2820
2821	#define LOSLESS_COMPRESS_MODE
2822
2823	/*#define DECOMP_HEADR_SURGENT*/
2824	#ifdef VP9_10B_NV21
2825	static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2826	#else
2827	static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2828	#endif
2829	static u32 enable_mem_saving = 1;
2830	static u32 force_w_h;
2831
2832	static u32 force_fps;
2833
2834
2835	const u32 vp9_version = 201602101;
2836	static u32 debug;
2837	static u32 radr;
2838	static u32 rval;
2839	static u32 pop_shorts;
2840	static u32 dbg_cmd;
2841	static u32 dbg_skip_decode_index;
2842	static u32 endian = 0xff0;
2843	#ifdef ERROR_HANDLE_DEBUG
2844	static u32 dbg_nal_skip_flag;
2845	/* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2846	static u32 dbg_nal_skip_count;
2847	#endif
2848	/*for debug*/
2849	static u32 decode_pic_begin;
2850	static uint slice_parse_begin;
2851	static u32 step;
2852	#ifdef MIX_STREAM_SUPPORT
2853	static u32 buf_alloc_width = 4096;
2854	static u32 buf_alloc_height = 2304;
2855	static u32 vp9_max_pic_w = 4096;
2856	static u32 vp9_max_pic_h = 2304;
2857
2858	static u32 dynamic_buf_num_margin;
2859	#else
2860	static u32 buf_alloc_width;
2861	static u32 buf_alloc_height;
2862	static u32 dynamic_buf_num_margin = 7;
2863	#endif
2864	static u32 buf_alloc_depth = 10;
2865	static u32 buf_alloc_size;
2866	/*
2867	*bit[0]: 0,
2868	* bit[1]: 0, always release cma buffer when stop
2869	* bit[1]: 1, never release cma buffer when stop
2870	*bit[0]: 1, when stop, release cma buffer if blackout is 1;
2871	*do not release cma buffer is blackout is not 1
2872	*
2873	*bit[2]: 0, when start decoding, check current displayed buffer
2874	* (only for buffer decoded by vp9) if blackout is 0
2875	* 1, do not check current displayed buffer
2876	*
2877	*bit[3]: 1, if blackout is not 1, do not release current
2878	* displayed cma buffer always.
2879	*/
2880	/* set to 1 for fast play;
2881	* set to 8 for other case of "keep last frame"
2882	*/
2883	static u32 buffer_mode = 1;
2884	/* buffer_mode_dbg: debug only*/
2885	static u32 buffer_mode_dbg = 0xffff0000;
2886	/**/
2887
2888	/*
2889	*bit 0, 1: only display I picture;
2890	*bit 1, 1: only decode I picture;
2891	*/
2892	static u32 i_only_flag;
2893
2894	static u32 low_latency_flag;
2895
2896	static u32 no_head;
2897
2898	static u32 max_decoding_time;
2899	/*
2900	*error handling
2901	*/
2902	/*error_handle_policy:
2903	*bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2904	*1, skip error_skip_nal_count nals before error recovery;
2905	*bit 1 (valid only when bit0 == 1):
2906	*1, wait vps/sps/pps after error recovery;
2907	*bit 2 (valid only when bit0 == 0):
2908	*0, auto search after error recovery (vp9_recover() called);
2909	*1, manual search after error recovery
2910	*(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2911	*
2912	*bit 4: 0, set error_mark after reset/recover
2913	* 1, do not set error_mark after reset/recover
2914	*bit 5: 0, check total lcu for every picture
2915	* 1, do not check total lcu
2916	*
2917	*/
2918
2919	static u32 error_handle_policy;
2920	/*static u32 parser_sei_enable = 1;*/
2921	#define MAX_BUF_NUM_NORMAL 12
2922	#define MAX_BUF_NUM_LESS 10
2923	static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2924	#define MAX_BUF_NUM_SAVE_BUF 8
2925
2926	static u32 run_ready_min_buf_num = 2;
2927
2928
2929	static DEFINE_MUTEX(vvp9_mutex);
2930	#ifndef MULTI_INSTANCE_SUPPORT
2931	static struct device *cma_dev;
2932	#endif
2933
2934	#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2935	#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2936	#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2937	#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2938	#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2939	#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2940	#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2941	#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2942	#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2943	#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2944	#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2945	#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2946	#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2947	#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2948	#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2949	#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2950	#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2951	#ifdef MULTI_INSTANCE_SUPPORT
2952	#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2953	#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2954	#else
2955	#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2956	#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2957	#endif
2958	#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2959	#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2960
2961
2962	/*
2963	*ucode parser/search control
2964	*bit 0: 0, header auto parse; 1, header manual parse
2965	*bit 1: 0, auto skip for noneseamless stream; 1, no skip
2966	*bit [3:2]: valid when bit1==0;
2967	*0, auto skip nal before first vps/sps/pps/idr;
2968	*1, auto skip nal before first vps/sps/pps
2969	*2, auto skip nal before first vps/sps/pps,
2970	* and not decode until the first I slice (with slice address of 0)
2971	*
2972	*3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
2973	*bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
2974	*bit [16]: for NAL_UNIT_EOS when bit0 is 0:
2975	* 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
2976	*bit [17]: for NAL_SEI when bit0 is 0:
2977	* 0, do not parse SEI in ucode; 1, parse SEI in ucode
2978	*bit [31:20]: used by ucode for debug purpose
2979	*/
2980	#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
2981	/*[31:24] chip feature
2982	31: 0, use MBOX1; 1, use MBOX0
2983	*/
2984	#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
2985	#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
2986
2987	#ifdef MULTI_INSTANCE_SUPPORT
2988	#define RPM_BUF_SIZE (0x400 * 2)
2989	#else
2990	#define RPM_BUF_SIZE (0x80*2)
2991	#endif
2992	#define LMEM_BUF_SIZE (0x400 * 2)
2993
2994	#define WORK_BUF_SPEC_NUM 3
2995	static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
2996	{
2997	/* 8M bytes */
2998	.max_width = 1920,
2999	.max_height = 1088,
3000	.ipp = {
3001	/* IPP work space calculation :
3002	* 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3003	*/
3004	.buf_size = 0x4000,
3005	},
3006	.sao_abv = {
3007	.buf_size = 0x30000,
3008	},
3009	.sao_vb = {
3010	.buf_size = 0x30000,
3011	},
3012	.short_term_rps = {
3013	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3014	* total 64x16x2 = 2048 bytes (0x800)
3015	*/
3016	.buf_size = 0x800,
3017	},
3018	.vps = {
3019	/* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3020	* total 0x0800 bytes
3021	*/
3022	.buf_size = 0x800,
3023	},
3024	.sps = {
3025	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3026	* total 0x0800 bytes
3027	*/
3028	.buf_size = 0x800,
3029	},
3030	.pps = {
3031	/* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3032	* total 0x2000 bytes
3033	*/
3034	.buf_size = 0x2000,
3035	},
3036	.sao_up = {
3037	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
3038	* each has 16 bytes total 0x2800 bytes
3039	*/
3040	.buf_size = 0x2800,
3041	},
3042	.swap_buf = {
3043	/* 256cyclex64bit = 2K bytes 0x800
3044	* (only 144 cycles valid)
3045	*/
3046	.buf_size = 0x800,
3047	},
3048	.swap_buf2 = {
3049	.buf_size = 0x800,
3050	},
3051	.scalelut = {
3052	/* support up to 32 SCALELUT 1024x32 =
3053	* 32Kbytes (0x8000)
3054	*/
3055	.buf_size = 0x8000,
3056	},
3057	.dblk_para = {
3058	/* DBLK -> Max 256(4096/16) LCU,
3059	*each para 1024bytes(total:0x40000),
3060	*data 1024bytes(total:0x40000)
3061	*/
3062	.buf_size = 0x80000,
3063	},
3064	.dblk_data = {
3065	.buf_size = 0x80000,
3066	},
3067	.seg_map = {
3068	/*4096x2304/64/64 *24 = 0xd800 Bytes*/
3069	.buf_size = 0xd800,
3070	},
3071	.mmu_vbh = {
3072	.buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3073	},
3074	#if 0
3075	.cm_header = {
3076	/*add one for keeper.*/
3077	.buf_size = MMU_COMPRESS_HEADER_SIZE *
3078	(FRAME_BUFFERS + 1),
3079	/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3080	},
3081	#endif
3082	.mpred_above = {
3083	.buf_size = 0x10000, /* 2 * size of hevc*/
3084	},
3085	#ifdef MV_USE_FIXED_BUF
3086	.mpred_mv = {/* 1080p, 0x40000 per buffer */
3087	.buf_size = 0x40000 * FRAME_BUFFERS,
3088	},
3089	#endif
3090	.rpm = {
3091	.buf_size = RPM_BUF_SIZE,
3092	},
3093	.lmem = {
3094	.buf_size = 0x400 * 2,
3095	}
3096	},
3097	{
3098	.max_width = 4096,
3099	.max_height = 2304,
3100	.ipp = {
3101	/* IPP work space calculation :
3102	* 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3103	*/
3104	.buf_size = 0x4000,
3105	},
3106	.sao_abv = {
3107	.buf_size = 0x30000,
3108	},
3109	.sao_vb = {
3110	.buf_size = 0x30000,
3111	},
3112	.short_term_rps = {
3113	/* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3114	* total 64x16x2 = 2048 bytes (0x800)
3115	*/
3116	.buf_size = 0x800,
3117	},
3118	.vps = {
3119	/* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3120	* total 0x0800 bytes
3121	*/
3122	.buf_size = 0x800,
3123	},
3124	.sps = {
3125	/* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3126	* total 0x0800 bytes
3127	*/
3128	.buf_size = 0x800,
3129	},
3130	.pps = {
3131	/* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3132	* total 0x2000 bytes
3133	*/
3134	.buf_size = 0x2000,
3135	},
3136	.sao_up = {
3137	/* SAO UP STORE AREA - Max 640(10240/16) LCU,
3138	* each has 16 bytes total 0x2800 bytes
3139	*/
3140	.buf_size = 0x2800,
3141	},
3142	.swap_buf = {
3143	/* 256cyclex64bit = 2K bytes 0x800
3144	* (only 144 cycles valid)
3145	*/
3146	.buf_size = 0x800,
3147	},
3148	.swap_buf2 = {
3149	.buf_size = 0x800,
3150	},
3151	.scalelut = {
3152	/* support up to 32 SCALELUT 1024x32 = 32Kbytes
3153	* (0x8000)
3154	*/
3155	.buf_size = 0x8000,
3156	},
3157	.dblk_para = {
3158	/* DBLK -> Max 256(4096/16) LCU,
3159	*each para 1024bytes(total:0x40000),
3160	*data 1024bytes(total:0x40000)
3161	*/
3162	.buf_size = 0x80000,
3163	},
3164	.dblk_data = {
3165	.buf_size = 0x80000,
3166	},
3167	.seg_map = {
3168	/*4096x2304/64/64 *24 = 0xd800 Bytes*/
3169	.buf_size = 0xd800,
3170	},
3171	.mmu_vbh = {
3172	.buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3173	},
3174	#if 0
3175	.cm_header = {
3176	/*add one for keeper.*/
3177	.buf_size = MMU_COMPRESS_HEADER_SIZE *
3178	(FRAME_BUFFERS + 1),
3179	/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3180	},
3181	#endif
3182	.mpred_above = {
3183	.buf_size = 0x10000, /* 2 * size of hevc*/
3184	},
3185	#ifdef MV_USE_FIXED_BUF
3186	.mpred_mv = {
3187	/* .buf_size = 0x100000*16,
3188	* //4k2k , 0x100000 per buffer
3189	*/
3190	/* 4096x2304 , 0x120000 per buffer */
3191	.buf_size = 0x120000 * FRAME_BUFFERS,
3192	},
3193	#endif
3194	.rpm = {
3195	.buf_size = RPM_BUF_SIZE,
3196	},
3197	.lmem = {
3198	.buf_size = 0x400 * 2,
3199	}
3200	},
3201	{
3202	.max_width = 4096*2,
3203	.max_height = 2304*2,
3204	.ipp = {
3205	// IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3206	.buf_size = 0x4000*2,
3207	},
3208	.sao_abv = {
3209	.buf_size = 0x30000*2,
3210	},
3211	.sao_vb = {
3212	.buf_size = 0x30000*2,
3213	},
3214	.short_term_rps = {
3215	// SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3216	.buf_size = 0x800,
3217	},
3218	.vps = {
3219	// VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3220	.buf_size = 0x800,
3221	},
3222	.sps = {
3223	// SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3224	.buf_size = 0x800,
3225	},
3226	.pps = {
3227	// PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3228	.buf_size = 0x2000,
3229	},
3230	.sao_up = {
3231	// SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3232	.buf_size = 0x2800*2,
3233	},
3234	.swap_buf = {
3235	// 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3236	.buf_size = 0x800,
3237	},
3238	.swap_buf2 = {
3239	.buf_size = 0x800,
3240	},
3241	.scalelut = {
3242	// support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3243	.buf_size = 0x8000*2,
3244	},
3245	.dblk_para = {
3246	// DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3247	.buf_size = 0x80000*2,
3248	},
3249	.dblk_data = {
3250	.buf_size = 0x80000*2,
3251	},
3252	.seg_map = {
3253	/*4096x2304/64/64 *24 = 0xd800 Bytes*/
3254	.buf_size = 0xd800*4,
3255	},
3256	.mmu_vbh = {
3257	.buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3258	},
3259	#if 0
3260	.cm_header = {
3261	//.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3262	.buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3263	},
3264	#endif
3265	.mpred_above = {
3266	.buf_size = 0x10000*2, /* 2 * size of hevc*/
3267	},
3268	#ifdef MV_USE_FIXED_BUF
3269	.mpred_mv = {
3270	//4k2k , 0x100000 per buffer */
3271	/* 4096x2304 , 0x120000 per buffer */
3272	.buf_size = 0x120000 * FRAME_BUFFERS * 4,
3273	},
3274	#endif
3275	.rpm = {
3276	.buf_size = RPM_BUF_SIZE,
3277	},
3278	.lmem = {
3279	.buf_size = 0x400 * 2,
3280	}
3281	}
3282	};
3283
3284
3285	/*Losless compression body buffer size 4K per 64x32 (jt)*/
3286	int compute_losless_comp_body_size(int width, int height,
3287	uint8_t is_bit_depth_10)
3288	{
3289	int width_x64;
3290	int height_x32;
3291	int bsize;
3292
3293	width_x64 = width + 63;
3294	width_x64 >>= 6;
3295	height_x32 = height + 31;
3296	height_x32 >>= 5;
3297	bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3298	if (debug & VP9_DEBUG_BUFMGR_MORE)
3299	pr_info("%s(%d,%d,%d)=>%d\n",
3300	__func__, width, height,
3301	is_bit_depth_10, bsize);
3302
3303	return bsize;
3304	}
3305
3306	/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3307	static int compute_losless_comp_header_size(int width, int height)
3308	{
3309	int width_x128;
3310	int height_x64;
3311	int hsize;
3312
3313	width_x128 = width + 127;
3314	width_x128 >>= 7;
3315	height_x64 = height + 63;
3316	height_x64 >>= 6;
3317
3318	hsize = 32 * width_x128 * height_x64;
3319	if (debug & VP9_DEBUG_BUFMGR_MORE)
3320	pr_info("%s(%d,%d)=>%d\n",
3321	__func__, width, height,
3322	hsize);
3323
3324	return hsize;
3325	}
3326
3327	static void init_buff_spec(struct VP9Decoder_s *pbi,
3328	struct BuffInfo_s *buf_spec)
3329	{
3330	void *mem_start_virt;
3331
3332	buf_spec->ipp.buf_start = buf_spec->start_adr;
3333	buf_spec->sao_abv.buf_start =
3334	buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3335
3336	buf_spec->sao_vb.buf_start =
3337	buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3338	buf_spec->short_term_rps.buf_start =
3339	buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3340	buf_spec->vps.buf_start =
3341	buf_spec->short_term_rps.buf_start +
3342	buf_spec->short_term_rps.buf_size;
3343	buf_spec->sps.buf_start =
3344	buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3345	buf_spec->pps.buf_start =
3346	buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3347	buf_spec->sao_up.buf_start =
3348	buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3349	buf_spec->swap_buf.buf_start =
3350	buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3351	buf_spec->swap_buf2.buf_start =
3352	buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3353	buf_spec->scalelut.buf_start =
3354	buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3355	buf_spec->dblk_para.buf_start =
3356	buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3357	buf_spec->dblk_data.buf_start =
3358	buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3359	buf_spec->seg_map.buf_start =
3360	buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3361	if (pbi == NULL || pbi->mmu_enable) {
3362	buf_spec->mmu_vbh.buf_start =
3363	buf_spec->seg_map.buf_start +
3364	buf_spec->seg_map.buf_size;
3365	buf_spec->mpred_above.buf_start =
3366	buf_spec->mmu_vbh.buf_start +
3367	buf_spec->mmu_vbh.buf_size;
3368	} else {
3369	buf_spec->mpred_above.buf_start =
3370	buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3371	}
3372	#ifdef MV_USE_FIXED_BUF
3373	buf_spec->mpred_mv.buf_start =
3374	buf_spec->mpred_above.buf_start +
3375	buf_spec->mpred_above.buf_size;
3376
3377	buf_spec->rpm.buf_start =
3378	buf_spec->mpred_mv.buf_start +
3379	buf_spec->mpred_mv.buf_size;
3380	#else
3381	buf_spec->rpm.buf_start =
3382	buf_spec->mpred_above.buf_start +
3383	buf_spec->mpred_above.buf_size;
3384
3385	#endif
3386	buf_spec->lmem.buf_start =
3387	buf_spec->rpm.buf_start +
3388	buf_spec->rpm.buf_size;
3389	buf_spec->end_adr =
3390	buf_spec->lmem.buf_start +
3391	buf_spec->lmem.buf_size;
3392
3393	if (!pbi)
3394	return;
3395
3396	if (!vdec_secure(hw_to_vdec(pbi))) {
3397	mem_start_virt =
3398	codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3399	if (mem_start_virt) {
3400	memset(mem_start_virt, 0,
3401	buf_spec->dblk_para.buf_size);
3402	codec_mm_dma_flush(mem_start_virt,
3403	buf_spec->dblk_para.buf_size,
3404	DMA_TO_DEVICE);
3405	} else {
3406	mem_start_virt = codec_mm_vmap(
3407	buf_spec->dblk_para.buf_start,
3408	buf_spec->dblk_para.buf_size);
3409	if (mem_start_virt) {
3410	memset(mem_start_virt, 0,
3411	buf_spec->dblk_para.buf_size);
3412	codec_mm_dma_flush(mem_start_virt,
3413	buf_spec->dblk_para.buf_size,
3414	DMA_TO_DEVICE);
3415	codec_mm_unmap_phyaddr(mem_start_virt);
3416	} else {
3417	/*not virt for tvp playing,
3418	may need clear on ucode.*/
3419	pr_err("mem_start_virt failed\n");
3420	}
3421	}
3422	}
3423
3424	if (debug) {
3425	pr_info("%s workspace (%x %x) size = %x\n", __func__,
3426	buf_spec->start_adr, buf_spec->end_adr,
3427	buf_spec->end_adr - buf_spec->start_adr);
3428	}
3429
3430	if (debug) {
3431	pr_info("ipp.buf_start :%x\n",
3432	buf_spec->ipp.buf_start);
3433	pr_info("sao_abv.buf_start :%x\n",
3434	buf_spec->sao_abv.buf_start);
3435	pr_info("sao_vb.buf_start :%x\n",
3436	buf_spec->sao_vb.buf_start);
3437	pr_info("short_term_rps.buf_start :%x\n",
3438	buf_spec->short_term_rps.buf_start);
3439	pr_info("vps.buf_start :%x\n",
3440	buf_spec->vps.buf_start);
3441	pr_info("sps.buf_start :%x\n",
3442	buf_spec->sps.buf_start);
3443	pr_info("pps.buf_start :%x\n",
3444	buf_spec->pps.buf_start);
3445	pr_info("sao_up.buf_start :%x\n",
3446	buf_spec->sao_up.buf_start);
3447	pr_info("swap_buf.buf_start :%x\n",
3448	buf_spec->swap_buf.buf_start);
3449	pr_info("swap_buf2.buf_start :%x\n",
3450	buf_spec->swap_buf2.buf_start);
3451	pr_info("scalelut.buf_start :%x\n",
3452	buf_spec->scalelut.buf_start);
3453	pr_info("dblk_para.buf_start :%x\n",
3454	buf_spec->dblk_para.buf_start);
3455	pr_info("dblk_data.buf_start :%x\n",
3456	buf_spec->dblk_data.buf_start);
3457	pr_info("seg_map.buf_start :%x\n",
3458	buf_spec->seg_map.buf_start);
3459	if (pbi->mmu_enable) {
3460	pr_info("mmu_vbh.buf_start :%x\n",
3461	buf_spec->mmu_vbh.buf_start);
3462	}
3463	pr_info("mpred_above.buf_start :%x\n",
3464	buf_spec->mpred_above.buf_start);
3465	#ifdef MV_USE_FIXED_BUF
3466	pr_info("mpred_mv.buf_start :%x\n",
3467	buf_spec->mpred_mv.buf_start);
3468	#endif
3469	if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3470	pr_info("rpm.buf_start :%x\n",
3471	buf_spec->rpm.buf_start);
3472	}
3473	}
3474	}
3475
3476	/* cache_util.c */
3477	#define THODIYIL_MCRCC_CANVAS_ALGX 4
3478
3479	static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3480
3481	static void mcrcc_perfcount_reset(void)
3482	{
3483	if (debug & VP9_DEBUG_CACHE)
3484	pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3485	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3486	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3487	return;
3488	}
3489
3490	static unsigned raw_mcr_cnt_total_prev;
3491	static unsigned hit_mcr_0_cnt_total_prev;
3492	static unsigned hit_mcr_1_cnt_total_prev;
3493	static unsigned byp_mcr_cnt_nchcanv_total_prev;
3494	static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3495
3496	static void mcrcc_get_hitrate(unsigned reset_pre)
3497	{
3498	unsigned delta_hit_mcr_0_cnt;
3499	unsigned delta_hit_mcr_1_cnt;
3500	unsigned delta_raw_mcr_cnt;
3501	unsigned delta_mcr_cnt_nchcanv;
3502	unsigned delta_mcr_cnt_nchoutwin;
3503
3504	unsigned tmp;
3505	unsigned raw_mcr_cnt;
3506	unsigned hit_mcr_cnt;
3507	unsigned byp_mcr_cnt_nchoutwin;
3508	unsigned byp_mcr_cnt_nchcanv;
3509	int hitrate;
3510	if (reset_pre) {
3511	raw_mcr_cnt_total_prev = 0;
3512	hit_mcr_0_cnt_total_prev = 0;
3513	hit_mcr_1_cnt_total_prev = 0;
3514	byp_mcr_cnt_nchcanv_total_prev = 0;
3515	byp_mcr_cnt_nchoutwin_total_prev = 0;
3516	}
3517	if (debug & VP9_DEBUG_CACHE)
3518	pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3519	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3520	raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3521	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3522	hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3523	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3524	byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3525	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3526	byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3527
3528	if (debug & VP9_DEBUG_CACHE)
3529	pr_info("raw_mcr_cnt_total: %d\n",
3530	raw_mcr_cnt);
3531	if (debug & VP9_DEBUG_CACHE)
3532	pr_info("hit_mcr_cnt_total: %d\n",
3533	hit_mcr_cnt);
3534	if (debug & VP9_DEBUG_CACHE)
3535	pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3536	byp_mcr_cnt_nchoutwin);
3537	if (debug & VP9_DEBUG_CACHE)
3538	pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3539	byp_mcr_cnt_nchcanv);
3540
3541	delta_raw_mcr_cnt = raw_mcr_cnt -
3542	raw_mcr_cnt_total_prev;
3543	delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3544	byp_mcr_cnt_nchcanv_total_prev;
3545	delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3546	byp_mcr_cnt_nchoutwin_total_prev;
3547	raw_mcr_cnt_total_prev = raw_mcr_cnt;
3548	byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3549	byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3550
3551	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3552	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3553	if (debug & VP9_DEBUG_CACHE)
3554	pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3555	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3556	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3557	if (debug & VP9_DEBUG_CACHE)
3558	pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3559	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3560	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3561	if (debug & VP9_DEBUG_CACHE)
3562	pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3563	delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3564	hit_mcr_0_cnt_total_prev = tmp;
3565	WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3566	tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3567	if (debug & VP9_DEBUG_CACHE)
3568	pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3569	delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3570	hit_mcr_1_cnt_total_prev = tmp;
3571
3572	if (delta_raw_mcr_cnt != 0) {
3573	hitrate = 100 * delta_hit_mcr_0_cnt
3574	/ delta_raw_mcr_cnt;
3575	if (debug & VP9_DEBUG_CACHE)
3576	pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3577	hitrate = 100 * delta_hit_mcr_1_cnt
3578	/ delta_raw_mcr_cnt;
3579	if (debug & VP9_DEBUG_CACHE)
3580	pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3581	hitrate = 100 * delta_mcr_cnt_nchcanv
3582	/ delta_raw_mcr_cnt;
3583	if (debug & VP9_DEBUG_CACHE)
3584	pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3585	hitrate = 100 * delta_mcr_cnt_nchoutwin
3586	/ delta_raw_mcr_cnt;
3587	if (debug & VP9_DEBUG_CACHE)
3588	pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3589	}
3590
3591
3592	if (raw_mcr_cnt != 0) {
3593	hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3594	if (debug & VP9_DEBUG_CACHE)
3595	pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3596	hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3597	/ raw_mcr_cnt;
3598	if (debug & VP9_DEBUG_CACHE)
3599	pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3600	} else {
3601	if (debug & VP9_DEBUG_CACHE)
3602	pr_info("MCRCC_HIT_RATE : na\n");
3603	if (debug & VP9_DEBUG_CACHE)
3604	pr_info("MCRCC_BYP_RATE : na\n");
3605	}
3606	return;
3607	}
3608
3609
3610	static void decomp_perfcount_reset(void)
3611	{
3612	if (debug & VP9_DEBUG_CACHE)
3613	pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3614	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3615	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3616	return;
3617	}
3618
3619	static void decomp_get_hitrate(void)
3620	{
3621	unsigned raw_mcr_cnt;
3622	unsigned hit_mcr_cnt;
3623	int hitrate;
3624	if (debug & VP9_DEBUG_CACHE)
3625	pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3626	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3627	raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3628	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3629	hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3630
3631	if (debug & VP9_DEBUG_CACHE)
3632	pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3633	if (debug & VP9_DEBUG_CACHE)
3634	pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3635
3636	if (raw_mcr_cnt != 0) {
3637	hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3638	if (debug & VP9_DEBUG_CACHE)
3639	pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3640	} else {
3641	if (debug & VP9_DEBUG_CACHE)
3642	pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3643	}
3644	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3645	raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3646	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3647	hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3648
3649	if (debug & VP9_DEBUG_CACHE)
3650	pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3651	if (debug & VP9_DEBUG_CACHE)
3652	pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3653
3654	if (raw_mcr_cnt != 0) {
3655	hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3656	if (debug & VP9_DEBUG_CACHE)
3657	pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3658	} else {
3659	if (debug & VP9_DEBUG_CACHE)
3660	pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3661	}
3662	return;
3663	}
3664
3665	static void decomp_get_comprate(void)
3666	{
3667	unsigned raw_ucomp_cnt;
3668	unsigned fast_comp_cnt;
3669	unsigned slow_comp_cnt;
3670	int comprate;
3671
3672	if (debug & VP9_DEBUG_CACHE)
3673	pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3674	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3675	fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3676	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3677	slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3678	WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3679	raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3680
3681	if (debug & VP9_DEBUG_CACHE)
3682	pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3683	if (debug & VP9_DEBUG_CACHE)
3684	pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3685	if (debug & VP9_DEBUG_CACHE)
3686	pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3687
3688	if (raw_ucomp_cnt != 0) {
3689	comprate = (fast_comp_cnt + slow_comp_cnt)
3690	* 100 / raw_ucomp_cnt;
3691	if (debug & VP9_DEBUG_CACHE)
3692	pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3693	} else {
3694	if (debug & VP9_DEBUG_CACHE)
3695	pr_info("DECOMP_COMP_RATIO : na\n");
3696	}
3697	return;
3698	}
3699	/* cache_util.c end */
3700
3701	/*====================================================
3702	*========================================================================
3703	*vp9_prob define
3704	*========================================================================
3705	*/
3706	#define VP9_PARTITION_START 0
3707	#define VP9_PARTITION_SIZE_STEP (3 * 4)
3708	#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3709	#define VP9_PARTITION_KEY_START 0
3710	#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3711	#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3712	#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3713	#define VP9_SKIP_SIZE 4 /* only use 3*/
3714	#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3715	#define VP9_TX_MODE_8_0_OFFSET 0
3716	#define VP9_TX_MODE_8_1_OFFSET 1
3717	#define VP9_TX_MODE_16_0_OFFSET 2
3718	#define VP9_TX_MODE_16_1_OFFSET 4
3719	#define VP9_TX_MODE_32_0_OFFSET 6
3720	#define VP9_TX_MODE_32_1_OFFSET 9
3721	#define VP9_TX_MODE_SIZE 12
3722	#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3723	#define VP9_COEF_BAND_0_OFFSET 0
3724	#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3725	#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3726	#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3727	#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3728	#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3729	#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3730	#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3731	#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3732	#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3733	#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3734	#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3735	#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3736	#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3737	#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3738	#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3739	#define VP9_INTERP_SIZE 8
3740	#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3741	#define VP9_INTRA_INTER_SIZE 4
3742	#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3743	#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3744	#define VP9_COMP_INTER_START \
3745	(VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3746	#define VP9_COMP_INTER_SIZE 5
3747	#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3748	#define VP9_COMP_REF_SIZE 5
3749	#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3750	#define VP9_SINGLE_REF_SIZE 10
3751	#define VP9_REF_MODE_START VP9_COMP_INTER_START
3752	#define VP9_REF_MODE_SIZE \
3753	(VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3754	#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3755	#define VP9_IF_Y_MODE_SIZE 36
3756	#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3757	#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3758	#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3759	#define VP9_MV_JOINTS_SIZE 3
3760	#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3761	#define VP9_MV_SIGN_0_SIZE 1
3762	#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3763	#define VP9_MV_CLASSES_0_SIZE 10
3764	#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3765	#define VP9_MV_CLASS0_0_SIZE 1
3766	#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3767	#define VP9_MV_BITS_0_SIZE 10
3768	#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3769	#define VP9_MV_SIGN_1_SIZE 1
3770	#define VP9_MV_CLASSES_1_START \
3771	(VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3772	#define VP9_MV_CLASSES_1_SIZE 10
3773	#define VP9_MV_CLASS0_1_START \
3774	(VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3775	#define VP9_MV_CLASS0_1_SIZE 1
3776	#define VP9_MV_BITS_1_START \
3777	(VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3778	#define VP9_MV_BITS_1_SIZE 10
3779	#define VP9_MV_CLASS0_FP_0_START \
3780	(VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3781	#define VP9_MV_CLASS0_FP_0_SIZE 9
3782	#define VP9_MV_CLASS0_FP_1_START \
3783	(VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3784	#define VP9_MV_CLASS0_FP_1_SIZE 9
3785	#define VP9_MV_CLASS0_HP_0_START \
3786	(VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3787	#define VP9_MV_CLASS0_HP_0_SIZE 2
3788	#define VP9_MV_CLASS0_HP_1_START \
3789	(VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3790	#define VP9_MV_CLASS0_HP_1_SIZE 2
3791	#define VP9_MV_START VP9_MV_JOINTS_START
3792	#define VP9_MV_SIZE 72 /*only use 69*/
3793
3794	#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3795
3796
3797	/*========================================================================
3798	* vp9_count_mem define
3799	*========================================================================
3800	*/
3801	#define VP9_COEF_COUNT_START 0
3802	#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3803	#define VP9_COEF_COUNT_BAND_1_OFFSET \
3804	(VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3805	#define VP9_COEF_COUNT_BAND_2_OFFSET \
3806	(VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3807	#define VP9_COEF_COUNT_BAND_3_OFFSET \
3808	(VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3809	#define VP9_COEF_COUNT_BAND_4_OFFSET \
3810	(VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3811	#define VP9_COEF_COUNT_BAND_5_OFFSET \
3812	(VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3813	#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3814	#define VP9_COEF_COUNT_4X4_START \
3815	(VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3816	#define VP9_COEF_COUNT_8X8_START \
3817	(VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3818	#define VP9_COEF_COUNT_16X16_START \
3819	(VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3820	#define VP9_COEF_COUNT_32X32_START \
3821	(VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3822	#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3823	#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3824
3825	#define VP9_INTRA_INTER_COUNT_START \
3826	(VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3827	#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3828	#define VP9_COMP_INTER_COUNT_START \
3829	(VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3830	#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3831	#define VP9_COMP_REF_COUNT_START \
3832	(VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3833	#define VP9_COMP_REF_COUNT_SIZE (5*2)
3834	#define VP9_SINGLE_REF_COUNT_START \
3835	(VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3836	#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3837	#define VP9_TX_MODE_COUNT_START \
3838	(VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3839	#define VP9_TX_MODE_COUNT_SIZE (12*2)
3840	#define VP9_SKIP_COUNT_START \
3841	(VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3842	#define VP9_SKIP_COUNT_SIZE (3*2)
3843	#define VP9_MV_SIGN_0_COUNT_START \
3844	(VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3845	#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3846	#define VP9_MV_SIGN_1_COUNT_START \
3847	(VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3848	#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3849	#define VP9_MV_BITS_0_COUNT_START \
3850	(VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3851	#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3852	#define VP9_MV_BITS_1_COUNT_START \
3853	(VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3854	#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3855	#define VP9_MV_CLASS0_HP_0_COUNT_START \
3856	(VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3857	#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3858	#define VP9_MV_CLASS0_HP_1_COUNT_START \
3859	(VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3860	#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3861	/* Start merge_tree*/
3862	#define VP9_INTER_MODE_COUNT_START \
3863	(VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3864	#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3865	#define VP9_IF_Y_MODE_COUNT_START \
3866	(VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3867	#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3868	#define VP9_IF_UV_MODE_COUNT_START \
3869	(VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3870	#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3871	#define VP9_PARTITION_P_COUNT_START \
3872	(VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3873	#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3874	#define VP9_INTERP_COUNT_START \
3875	(VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3876	#define VP9_INTERP_COUNT_SIZE (4*3)
3877	#define VP9_MV_JOINTS_COUNT_START \
3878	(VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3879	#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3880	#define VP9_MV_CLASSES_0_COUNT_START \
3881	(VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3882	#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3883	#define VP9_MV_CLASS0_0_COUNT_START \
3884	(VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3885	#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3886	#define VP9_MV_CLASSES_1_COUNT_START \
3887	(VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3888	#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3889	#define VP9_MV_CLASS0_1_COUNT_START \
3890	(VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3891	#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3892	#define VP9_MV_CLASS0_FP_0_COUNT_START \
3893	(VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3894	#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3895	#define VP9_MV_CLASS0_FP_1_COUNT_START \
3896	(VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3897	#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3898
3899
3900	#define DC_PRED 0 /* Average of above and left pixels*/
3901	#define V_PRED 1 /* Vertical*/
3902	#define H_PRED 2 /* Horizontal*/
3903	#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3904	#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3905	#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3906	#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3907	#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3908	#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3909	#define TM_PRED 9 /*True-motion*/
3910
3911	int clip_prob(int p)
3912	{
3913	return (p > 255) ? 255 : (p < 1) ? 1 : p;
3914	}
3915
3916	#define ROUND_POWER_OF_TWO(value, n) \
3917	(((value) + (1 << ((n) - 1))) >> (n))
3918
3919	#define MODE_MV_COUNT_SAT 20
3920	static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3921	0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3922	70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3923	};
3924
3925	void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3926	int coef_node_start, int tree_left, int tree_right, int tree_i,
3927	int node) {
3928
3929	int prob_32, prob_res, prob_shift;
3930	int pre_prob, new_prob;
3931	int den, m_count, get_prob, factor;
3932
3933	prob_32 = prev_prob[coef_node_start / 4 * 2];
3934	prob_res = coef_node_start & 3;
3935	prob_shift = prob_res * 8;
3936	pre_prob = (prob_32 >> prob_shift) & 0xff;
3937
3938	den = tree_left + tree_right;
3939
3940	if (den == 0)
3941	new_prob = pre_prob;
3942	else {
3943	m_count = (den < MODE_MV_COUNT_SAT) ?
3944	den : MODE_MV_COUNT_SAT;
3945	get_prob = clip_prob(
3946	div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3947	den));
3948	/*weighted_prob*/
3949	factor = count_to_update_factor[m_count];
3950	new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3951	+ get_prob * factor, 8);
3952	}
3953	cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3954	& (~(0xff << prob_shift))) | (new_prob << prob_shift);
3955
3956	/*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3957	*tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3958	*cur_prob[coef_node_start/4*2]);
3959	*/
3960	}
3961
3962
3963	/*void adapt_coef_probs(void)*/
3964	void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3965	unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3966	{
3967	/* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3968	*unsigned int prev_prob[496*2];
3969	*unsigned int cur_prob[496*2];
3970	*0x300 * 128bits = 0x3000 (32K Bytes)
3971	*unsigned int count[0x300*4];
3972	*/
3973
3974	int tx_size, coef_tx_size_start, coef_count_tx_size_start;
3975	int plane, coef_plane_start, coef_count_plane_start;
3976	int type, coef_type_start, coef_count_type_start;
3977	int band, coef_band_start, coef_count_band_start;
3978	int cxt_num;
3979	int cxt, coef_cxt_start, coef_count_cxt_start;
3980	int node, coef_node_start, coef_count_node_start;
3981
3982	int tree_i, tree_left, tree_right;
3983	int mvd_i;
3984
3985	int count_sat = 24;
3986	/*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
3987	*use 128
3988	*/
3989	/* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
3990	/*int update_factor = (pic_count == 1) ? 128 : 112;*/
3991	int update_factor = cur_kf ? 112 :
3992	prev_kf ? 128 : 112;
3993
3994	int prob_32;
3995	int prob_res;
3996	int prob_shift;
3997	int pre_prob;
3998
3999	int num, den;
4000	int get_prob;
4001	int m_count;
4002	int factor;
4003
4004	int new_prob;
4005
4006	if (debug & VP9_DEBUG_MERGE)
4007	pr_info
4008	("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4009	pre_fc, prev_kf, cur_kf);
4010
4011	/*adapt_coef_probs*/
4012	for (tx_size = 0; tx_size < 4; tx_size++) {
4013	coef_tx_size_start = VP9_COEF_START
4014	+ tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4015	coef_count_tx_size_start = VP9_COEF_COUNT_START
4016	+ tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4017	coef_plane_start = coef_tx_size_start;
4018	coef_count_plane_start = coef_count_tx_size_start;
4019	for (plane = 0; plane < 2; plane++) {
4020	coef_type_start = coef_plane_start;
4021	coef_count_type_start = coef_count_plane_start;
4022	for (type = 0; type < 2; type++) {
4023	coef_band_start = coef_type_start;
4024	coef_count_band_start = coef_count_type_start;
4025	for (band = 0; band < 6; band++) {
4026	if (band == 0)
4027	cxt_num = 3;
4028	else
4029	cxt_num = 6;
4030	coef_cxt_start = coef_band_start;
4031	coef_count_cxt_start =
4032	coef_count_band_start;
4033	for (cxt = 0; cxt < cxt_num; cxt++) {
4034	const int n0 =
4035	count[coef_count_cxt_start];
4036	const int n1 =
4037	count[coef_count_cxt_start + 1];
4038	const int n2 =
4039	count[coef_count_cxt_start + 2];
4040	const int neob =
4041	count[coef_count_cxt_start + 3];
4042	const int nneob =
4043	count[coef_count_cxt_start + 4];
4044	const unsigned int
4045	branch_ct[3][2] = {
4046	{ neob, nneob },
4047	{ n0, n1 + n2 },
4048	{ n1, n2 }
4049	};
4050	coef_node_start =
4051	coef_cxt_start;
4052	for
4053	(node = 0; node < 3; node++) {
4054	prob_32 =
4055	prev_prob[
4056	coef_node_start
4057	/ 4 * 2];
4058	prob_res =
4059	coef_node_start & 3;
4060	prob_shift =
4061	prob_res * 8;
4062	pre_prob =
4063	(prob_32 >> prob_shift)
4064	& 0xff;
4065
4066	/*get_binary_prob*/
4067	num =
4068	branch_ct[node][0];
4069	den =
4070	branch_ct[node][0] +
4071	branch_ct[node][1];
4072	m_count = (den <
4073	count_sat)
4074	? den : count_sat;
4075
4076	get_prob =
4077	(den == 0) ? 128u :
4078	clip_prob(
4079	div_r32(((int64_t)
4080	num * 256
4081	+ (den >> 1)),
4082	den));
4083
4084	factor =
4085	update_factor * m_count
4086	/ count_sat;
4087	new_prob =
4088	ROUND_POWER_OF_TWO
4089	(pre_prob *
4090	(256 - factor) +
4091	get_prob * factor, 8);
4092
4093	cur_prob[coef_node_start
4094	/ 4 * 2] =
4095	(cur_prob
4096	[coef_node_start
4097	/ 4 * 2] & (~(0xff <<
4098	prob_shift))) |
4099	(new_prob <<
4100	prob_shift);
4101
4102	coef_node_start += 1;
4103	}
4104
4105	coef_cxt_start =
4106	coef_cxt_start + 3;
4107	coef_count_cxt_start =
4108	coef_count_cxt_start
4109	+ 5;
4110	}
4111	if (band == 0) {
4112	coef_band_start += 10;
4113	coef_count_band_start += 15;
4114	} else {
4115	coef_band_start += 18;
4116	coef_count_band_start += 30;
4117	}
4118	}
4119	coef_type_start += VP9_COEF_SIZE_ONE_SET;
4120	coef_count_type_start +=
4121	VP9_COEF_COUNT_SIZE_ONE_SET;
4122	}
4123	coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4124	coef_count_plane_start +=
4125	2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4126	}
4127	}
4128
4129	if (cur_kf == 0) {
4130	/*mode_mv_merge_probs - merge_intra_inter_prob*/
4131	for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4132	coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4133	VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4134
4135	if (coef_count_node_start ==
4136	VP9_INTRA_INTER_COUNT_START) {
4137	if (debug & VP9_DEBUG_MERGE)
4138	pr_info(" # merge_intra_inter_prob\n");
4139	coef_node_start = VP9_INTRA_INTER_START;
4140	} else if (coef_count_node_start ==
4141	VP9_COMP_INTER_COUNT_START) {
4142	if (debug & VP9_DEBUG_MERGE)
4143	pr_info(" # merge_comp_inter_prob\n");
4144	coef_node_start = VP9_COMP_INTER_START;
4145	}
4146	/*
4147	*else if (coef_count_node_start ==
4148	* VP9_COMP_REF_COUNT_START) {
4149	* pr_info(" # merge_comp_inter_prob\n");
4150	* coef_node_start = VP9_COMP_REF_START;
4151	*}
4152	*else if (coef_count_node_start ==
4153	* VP9_SINGLE_REF_COUNT_START) {
4154	* pr_info(" # merge_comp_inter_prob\n");
4155	* coef_node_start = VP9_SINGLE_REF_START;
4156	*}
4157	*/
4158	else if (coef_count_node_start ==
4159	VP9_TX_MODE_COUNT_START) {
4160	if (debug & VP9_DEBUG_MERGE)
4161	pr_info(" # merge_tx_mode_probs\n");
4162	coef_node_start = VP9_TX_MODE_START;
4163	} else if (coef_count_node_start ==
4164	VP9_SKIP_COUNT_START) {
4165	if (debug & VP9_DEBUG_MERGE)
4166	pr_info(" # merge_skip_probs\n");
4167	coef_node_start = VP9_SKIP_START;
4168	} else if (coef_count_node_start ==
4169	VP9_MV_SIGN_0_COUNT_START) {
4170	if (debug & VP9_DEBUG_MERGE)
4171	pr_info(" # merge_sign_0\n");
4172	coef_node_start = VP9_MV_SIGN_0_START;
4173	} else if (coef_count_node_start ==
4174	VP9_MV_SIGN_1_COUNT_START) {
4175	if (debug & VP9_DEBUG_MERGE)
4176	pr_info(" # merge_sign_1\n");
4177	coef_node_start = VP9_MV_SIGN_1_START;
4178	} else if (coef_count_node_start ==
4179	VP9_MV_BITS_0_COUNT_START) {
4180	if (debug & VP9_DEBUG_MERGE)
4181	pr_info(" # merge_bits_0\n");
4182	coef_node_start = VP9_MV_BITS_0_START;
4183	} else if (coef_count_node_start ==
4184	VP9_MV_BITS_1_COUNT_START) {
4185	if (debug & VP9_DEBUG_MERGE)
4186	pr_info(" # merge_bits_1\n");
4187	coef_node_start = VP9_MV_BITS_1_START;
4188	} else if (coef_count_node_start ==
4189	VP9_MV_CLASS0_HP_0_COUNT_START) {
4190	if (debug & VP9_DEBUG_MERGE)
4191	pr_info(" # merge_class0_hp\n");
4192	coef_node_start = VP9_MV_CLASS0_HP_0_START;
4193	}
4194
4195
4196	den = count[coef_count_node_start] +
4197	count[coef_count_node_start + 1];
4198
4199	prob_32 = prev_prob[coef_node_start / 4 * 2];
4200	prob_res = coef_node_start & 3;
4201	prob_shift = prob_res * 8;
4202	pre_prob = (prob_32 >> prob_shift) & 0xff;
4203
4204	if (den == 0)
4205	new_prob = pre_prob;
4206	else {
4207	m_count = (den < MODE_MV_COUNT_SAT) ?
4208	den : MODE_MV_COUNT_SAT;
4209	get_prob =
4210	clip_prob(
4211	div_r32(((int64_t)count[coef_count_node_start]
4212	* 256 + (den >> 1)),
4213	den));
4214	/*weighted_prob*/
4215	factor = count_to_update_factor[m_count];
4216	new_prob =
4217	ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4218	+ get_prob * factor, 8);
4219	}
4220	cur_prob[coef_node_start / 4 * 2] =
4221	(cur_prob[coef_node_start / 4 * 2] &
4222	(~(0xff << prob_shift)))
4223	| (new_prob << prob_shift);
4224
4225	coef_node_start = coef_node_start + 1;
4226	}
4227	if (debug & VP9_DEBUG_MERGE)
4228	pr_info(" # merge_vp9_inter_mode_tree\n");
4229	coef_node_start = VP9_INTER_MODE_START;
4230	coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4231	for (tree_i = 0; tree_i < 7; tree_i++) {
4232	for (node = 0; node < 3; node++) {
4233	switch (node) {
4234	case 2:
4235	tree_left =
4236	count[coef_count_node_start + 1];
4237	tree_right =
4238	count[coef_count_node_start + 3];
4239	break;
4240	case 1:
4241	tree_left =
4242	count[coef_count_node_start + 0];
4243	tree_right =
4244	count[coef_count_node_start + 1]
4245	+ count[coef_count_node_start + 3];
4246	break;
4247	default:
4248	tree_left =
4249	count[coef_count_node_start + 2];
4250	tree_right =
4251	count[coef_count_node_start + 0]
4252	+ count[coef_count_node_start + 1]
4253	+ count[coef_count_node_start + 3];
4254	break;
4255
4256	}
4257
4258	vp9_tree_merge_probs(prev_prob, cur_prob,
4259	coef_node_start, tree_left, tree_right,
4260	tree_i, node);
4261
4262	coef_node_start = coef_node_start + 1;
4263	}
4264	coef_count_node_start = coef_count_node_start + 4;
4265	}
4266	if (debug & VP9_DEBUG_MERGE)
4267	pr_info(" # merge_vp9_intra_mode_tree\n");
4268	coef_node_start = VP9_IF_Y_MODE_START;
4269	coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4270	for (tree_i = 0; tree_i < 14; tree_i++) {
4271	for (node = 0; node < 9; node++) {
4272	switch (node) {
4273	case 8:
4274	tree_left =
4275	count[coef_count_node_start+D153_PRED];
4276	tree_right =
4277	count[coef_count_node_start+D207_PRED];
4278	break;
4279	case 7:
4280	tree_left =
4281	count[coef_count_node_start+D63_PRED];
4282	tree_right =
4283	count[coef_count_node_start+D207_PRED] +
4284	count[coef_count_node_start+D153_PRED];
4285	break;
4286	case 6:
4287	tree_left =
4288	count[coef_count_node_start + D45_PRED];
4289	tree_right =
4290	count[coef_count_node_start+D207_PRED] +
4291	count[coef_count_node_start+D153_PRED] +
4292	count[coef_count_node_start+D63_PRED];
4293	break;
4294	case 5:
4295	tree_left =
4296	count[coef_count_node_start+D135_PRED];
4297	tree_right =
4298	count[coef_count_node_start+D117_PRED];
4299	break;
4300	case 4:
4301	tree_left =
4302	count[coef_count_node_start+H_PRED];
4303	tree_right =
4304	count[coef_count_node_start+D117_PRED] +
4305	count[coef_count_node_start+D135_PRED];
4306	break;
4307	case 3:
4308	tree_left =
4309	count[coef_count_node_start+H_PRED] +
4310	count[coef_count_node_start+D117_PRED] +
4311	count[coef_count_node_start+D135_PRED];
4312	tree_right =
4313	count[coef_count_node_start+D45_PRED] +
4314	count[coef_count_node_start+D207_PRED] +
4315	count[coef_count_node_start+D153_PRED] +
4316	count[coef_count_node_start+D63_PRED];
4317	break;
4318	case 2:
4319	tree_left =
4320	count[coef_count_node_start+V_PRED];
4321	tree_right =
4322	count[coef_count_node_start+H_PRED] +
4323	count[coef_count_node_start+D117_PRED] +
4324	count[coef_count_node_start+D135_PRED] +
4325	count[coef_count_node_start+D45_PRED] +
4326	count[coef_count_node_start+D207_PRED] +
4327	count[coef_count_node_start+D153_PRED] +
4328	count[coef_count_node_start+D63_PRED];
4329	break;
4330	case 1:
4331	tree_left =
4332	count[coef_count_node_start+TM_PRED];
4333	tree_right =
4334	count[coef_count_node_start+V_PRED] +
4335	count[coef_count_node_start+H_PRED] +
4336	count[coef_count_node_start+D117_PRED] +
4337	count[coef_count_node_start+D135_PRED] +
4338	count[coef_count_node_start+D45_PRED] +
4339	count[coef_count_node_start+D207_PRED] +
4340	count[coef_count_node_start+D153_PRED] +
4341	count[coef_count_node_start+D63_PRED];
4342	break;
4343	default:
4344	tree_left =
4345	count[coef_count_node_start+DC_PRED];
4346	tree_right =
4347	count[coef_count_node_start+TM_PRED] +
4348	count[coef_count_node_start+V_PRED] +
4349	count[coef_count_node_start+H_PRED] +
4350	count[coef_count_node_start+D117_PRED] +
4351	count[coef_count_node_start+D135_PRED] +
4352	count[coef_count_node_start+D45_PRED] +
4353	count[coef_count_node_start+D207_PRED] +
4354	count[coef_count_node_start+D153_PRED] +
4355	count[coef_count_node_start+D63_PRED];
4356	break;
4357
4358	}
4359
4360	vp9_tree_merge_probs(prev_prob, cur_prob,
4361	coef_node_start, tree_left, tree_right,
4362	tree_i, node);
4363
4364	coef_node_start = coef_node_start + 1;
4365	}
4366	coef_count_node_start = coef_count_node_start + 10;
4367	}
4368
4369	if (debug & VP9_DEBUG_MERGE)
4370	pr_info(" # merge_vp9_partition_tree\n");
4371	coef_node_start = VP9_PARTITION_P_START;
4372	coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4373	for (tree_i = 0; tree_i < 16; tree_i++) {
4374	for (node = 0; node < 3; node++) {
4375	switch (node) {
4376	case 2:
4377	tree_left =
4378	count[coef_count_node_start + 2];
4379	tree_right =
4380	count[coef_count_node_start + 3];
4381	break;
4382	case 1:
4383	tree_left =
4384	count[coef_count_node_start + 1];
4385	tree_right =
4386	count[coef_count_node_start + 2] +
4387	count[coef_count_node_start + 3];
4388	break;
4389	default:
4390	tree_left =
4391	count[coef_count_node_start + 0];
4392	tree_right =
4393	count[coef_count_node_start + 1] +
4394	count[coef_count_node_start + 2] +
4395	count[coef_count_node_start + 3];
4396	break;
4397
4398	}
4399
4400	vp9_tree_merge_probs(prev_prob, cur_prob,
4401	coef_node_start,
4402	tree_left, tree_right, tree_i, node);
4403
4404	coef_node_start = coef_node_start + 1;
4405	}
4406	coef_count_node_start = coef_count_node_start + 4;
4407	}
4408
4409	if (debug & VP9_DEBUG_MERGE)
4410	pr_info(" # merge_vp9_switchable_interp_tree\n");
4411	coef_node_start = VP9_INTERP_START;
4412	coef_count_node_start = VP9_INTERP_COUNT_START;
4413	for (tree_i = 0; tree_i < 4; tree_i++) {
4414	for (node = 0; node < 2; node++) {
4415	switch (node) {
4416	case 1:
4417	tree_left =
4418	count[coef_count_node_start + 1];
4419	tree_right =
4420	count[coef_count_node_start + 2];
4421	break;
4422	default:
4423	tree_left =
4424	count[coef_count_node_start + 0];
4425	tree_right =
4426	count[coef_count_node_start + 1] +
4427	count[coef_count_node_start + 2];
4428	break;
4429
4430	}
4431
4432	vp9_tree_merge_probs(prev_prob, cur_prob,
4433	coef_node_start,
4434	tree_left, tree_right, tree_i, node);
4435
4436	coef_node_start = coef_node_start + 1;
4437	}
4438	coef_count_node_start = coef_count_node_start + 3;
4439	}
4440
4441	if (debug & VP9_DEBUG_MERGE)
4442	pr_info("# merge_vp9_mv_joint_tree\n");
4443	coef_node_start = VP9_MV_JOINTS_START;
4444	coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4445	for (tree_i = 0; tree_i < 1; tree_i++) {
4446	for (node = 0; node < 3; node++) {
4447	switch (node) {
4448	case 2:
4449	tree_left =
4450	count[coef_count_node_start + 2];
4451	tree_right =
4452	count[coef_count_node_start + 3];
4453	break;
4454	case 1:
4455	tree_left =
4456	count[coef_count_node_start + 1];
4457	tree_right =
4458	count[coef_count_node_start + 2] +
4459	count[coef_count_node_start + 3];
4460	break;
4461	default:
4462	tree_left =
4463	count[coef_count_node_start + 0];
4464	tree_right =
4465	count[coef_count_node_start + 1] +
4466	count[coef_count_node_start + 2] +
4467	count[coef_count_node_start + 3];
4468	break;
4469	}
4470
4471	vp9_tree_merge_probs(prev_prob, cur_prob,
4472	coef_node_start,
4473	tree_left, tree_right, tree_i, node);
4474
4475	coef_node_start = coef_node_start + 1;
4476	}
4477	coef_count_node_start = coef_count_node_start + 4;
4478	}
4479
4480	for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4481	if (debug & VP9_DEBUG_MERGE)
4482	pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4483	coef_node_start =
4484	mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4485	coef_count_node_start =
4486	mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4487	: VP9_MV_CLASSES_0_COUNT_START;
4488	tree_i = 0;
4489	for (node = 0; node < 10; node++) {
4490	switch (node) {
4491	case 9:
4492	tree_left =
4493	count[coef_count_node_start + 9];
4494	tree_right =
4495	count[coef_count_node_start + 10];
4496	break;
4497	case 8:
4498	tree_left =
4499	count[coef_count_node_start + 7];
4500	tree_right =
4501	count[coef_count_node_start + 8];
4502	break;
4503	case 7:
4504	tree_left =
4505	count[coef_count_node_start + 7] +
4506	count[coef_count_node_start + 8];
4507	tree_right =
4508	count[coef_count_node_start + 9] +
4509	count[coef_count_node_start + 10];
4510	break;
4511	case 6:
4512	tree_left =
4513	count[coef_count_node_start + 6];
4514	tree_right =
4515	count[coef_count_node_start + 7] +
4516	count[coef_count_node_start + 8] +
4517	count[coef_count_node_start + 9] +
4518	count[coef_count_node_start + 10];
4519	break;
4520	case 5:
4521	tree_left =
4522	count[coef_count_node_start + 4];
4523	tree_right =
4524	count[coef_count_node_start + 5];
4525	break;
4526	case 4:
4527	tree_left =
4528	count[coef_count_node_start + 4] +
4529	count[coef_count_node_start + 5];
4530	tree_right =
4531	count[coef_count_node_start + 6] +
4532	count[coef_count_node_start + 7] +
4533	count[coef_count_node_start + 8] +
4534	count[coef_count_node_start + 9] +
4535	count[coef_count_node_start + 10];
4536	break;
4537	case 3:
4538	tree_left =
4539	count[coef_count_node_start + 2];
4540	tree_right =
4541	count[coef_count_node_start + 3];
4542	break;
4543	case 2:
4544	tree_left =
4545	count[coef_count_node_start + 2] +
4546	count[coef_count_node_start + 3];
4547	tree_right =
4548	count[coef_count_node_start + 4] +
4549	count[coef_count_node_start + 5] +
4550	count[coef_count_node_start + 6] +
4551	count[coef_count_node_start + 7] +
4552	count[coef_count_node_start + 8] +
4553	count[coef_count_node_start + 9] +
4554	count[coef_count_node_start + 10];
4555	break;
4556	case 1:
4557	tree_left =
4558	count[coef_count_node_start + 1];
4559	tree_right =
4560	count[coef_count_node_start + 2] +
4561	count[coef_count_node_start + 3] +
4562	count[coef_count_node_start + 4] +
4563	count[coef_count_node_start + 5] +
4564	count[coef_count_node_start + 6] +
4565	count[coef_count_node_start + 7] +
4566	count[coef_count_node_start + 8] +
4567	count[coef_count_node_start + 9] +
4568	count[coef_count_node_start + 10];
4569	break;
4570	default:
4571	tree_left =
4572	count[coef_count_node_start + 0];
4573	tree_right =
4574	count[coef_count_node_start + 1] +
4575	count[coef_count_node_start + 2] +
4576	count[coef_count_node_start + 3] +
4577	count[coef_count_node_start + 4] +
4578	count[coef_count_node_start + 5] +
4579	count[coef_count_node_start + 6] +
4580	count[coef_count_node_start + 7] +
4581	count[coef_count_node_start + 8] +
4582	count[coef_count_node_start + 9] +
4583	count[coef_count_node_start + 10];
4584	break;
4585
4586	}
4587
4588	vp9_tree_merge_probs(prev_prob, cur_prob,
4589	coef_node_start, tree_left, tree_right,
4590	tree_i, node);
4591
4592	coef_node_start = coef_node_start + 1;
4593	}
4594
4595	if (debug & VP9_DEBUG_MERGE)
4596	pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4597	coef_node_start =
4598	mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4599	coef_count_node_start =
4600	mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4601	VP9_MV_CLASS0_0_COUNT_START;
4602	tree_i = 0;
4603	node = 0;
4604	tree_left = count[coef_count_node_start + 0];
4605	tree_right = count[coef_count_node_start + 1];
4606
4607	vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4608	tree_left, tree_right, tree_i, node);
4609	if (debug & VP9_DEBUG_MERGE)
4610	pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4611	mvd_i);
4612	coef_node_start =
4613	mvd_i ? VP9_MV_CLASS0_FP_1_START :
4614	VP9_MV_CLASS0_FP_0_START;
4615	coef_count_node_start =
4616	mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4617	VP9_MV_CLASS0_FP_0_COUNT_START;
4618	for (tree_i = 0; tree_i < 3; tree_i++) {
4619	for (node = 0; node < 3; node++) {
4620	switch (node) {
4621	case 2:
4622	tree_left =
4623	count[coef_count_node_start + 2];
4624	tree_right =
4625	count[coef_count_node_start + 3];
4626	break;
4627	case 1:
4628	tree_left =
4629	count[coef_count_node_start + 1];
4630	tree_right =
4631	count[coef_count_node_start + 2]
4632	+ count[coef_count_node_start + 3];
4633	break;
4634	default:
4635	tree_left =
4636	count[coef_count_node_start + 0];
4637	tree_right =
4638	count[coef_count_node_start + 1]
4639	+ count[coef_count_node_start + 2]
4640	+ count[coef_count_node_start + 3];
4641	break;
4642
4643	}
4644
4645	vp9_tree_merge_probs(prev_prob, cur_prob,
4646	coef_node_start, tree_left, tree_right,
4647	tree_i, node);
4648
4649	coef_node_start = coef_node_start + 1;
4650	}
4651	coef_count_node_start = coef_count_node_start + 4;
4652	}
4653
4654	} /* for mvd_i (mvd_y or mvd_x)*/
4655	}
4656
4657	}
4658
4659	static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4660	{
4661	int i;
4662	struct VP9_Common_s *const cm = &pbi->common;
4663	struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4664
4665	for (i = 0; i < pbi->used_buf_num; ++i) {
4666	if (frame_bufs[i].buf.vframe_bound)
4667	return true;
4668	}
4669
4670	return false;
4671	}
4672
4673	static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4674	{
4675	struct VP9_Common_s *const cm = &pbi->common;
4676	struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4677	int i;
4678
4679	/* release workspace */
4680	if (pbi->bmmu_box)
4681	decoder_bmmu_box_free_idx(pbi->bmmu_box,
4682	WORK_SPACE_BUF_ID);
4683	/*
4684	* it's only when vframe get back to driver, right now we can be sure
4685	* that vframe and fd are related. if the playback exits, the capture
4686	* requires the upper app to release when the fd is closed, and others
4687	* buffers drivers are released by driver.
4688	*/
4689	for (i = 0; i < pbi->used_buf_num; ++i) {
4690	if (!frame_bufs[i].buf.vframe_bound) {
4691	if (pbi->bmmu_box)
4692	decoder_bmmu_box_free_idx(pbi->bmmu_box,
4693	HEADER_BUFFER_IDX(i));
4694	if (pbi->mmu_box)
4695	decoder_mmu_box_free_idx(pbi->mmu_box, i);
4696
4697	vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4698	"%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4699	__func__, i, pbi->bmmu_box, pbi->mmu_box);
4700	}
4701	}
4702	}
4703
4704	static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4705	{
4706	#ifndef MV_USE_FIXED_BUF
4707	dealloc_mv_bufs(pbi);
4708	#endif
4709	if (pbi->is_used_v4l &&
4710	v4l_is_there_vframe_bound(pbi)) {
4711	if (get_double_write_mode(pbi) != 0x10) {
4712	v4l_mmu_buffer_release(pbi);
4713	return;
4714	}
4715	}
4716
4717	if (pbi->mmu_box)
4718	decoder_mmu_box_free(pbi->mmu_box);
4719	pbi->mmu_box = NULL;
4720
4721	if (pbi->bmmu_box)
4722	decoder_bmmu_box_free(pbi->bmmu_box);
4723	pbi->bmmu_box = NULL;
4724	}
4725
4726	static int calc_luc_quantity(u32 w, u32 h)
4727	{
4728	int lcu_size = 64; /*fixed 64*/
4729	int pic_width_64 = (w + 63) & (~0x3f);
4730	int pic_height_32 = (h + 31) & (~0x1f);
4731	int pic_width_lcu = (pic_width_64 % lcu_size) ?
4732	pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4733	int pic_height_lcu = (pic_height_32 % lcu_size) ?
4734	pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4735
4736	return pic_width_lcu * pic_height_lcu;
4737	}
4738
4739	static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4740	struct PIC_BUFFER_CONFIG_s *pic)
4741	{
4742	int ret = -1;
4743	int i = pic->index;
4744	int dw_mode = get_double_write_mode_init(pbi);
4745	int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4746	#ifdef MV_USE_FIXED_BUF
4747	u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4748	pbi->work_space_buf->mpred_mv.buf_size;
4749	#endif
4750	struct vdec_v4l2_buffer *fb = NULL;
4751
4752	ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4753	if (ret < 0) {
4754	vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4755	((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4756	return ret;
4757	}
4758
4759	if (pbi->mmu_enable) {
4760	pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4761	pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4762	if (debug & VP9_DEBUG_BUFMGR_MORE) {
4763	pr_info("MMU header_adr %d: %ld\n",
4764	i, pbi->m_BUF[i].header_addr);
4765	}
4766	}
4767
4768	#ifdef MV_USE_FIXED_BUF
4769	if ((pbi->work_space_buf->mpred_mv.buf_start +
4770	(((i + 1) * lcu_total) * MV_MEM_UNIT))
4771	<= mpred_mv_end) {
4772	#endif
4773	pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4774	pic->cma_alloc_addr = fb->m.mem[0].addr;
4775	if (fb->num_planes == 1) {
4776	pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4777	pbi->m_BUF[i].size = fb->m.mem[0].size;
4778	pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4779	fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4780	} else if (fb->num_planes == 2) {
4781	pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4782	pbi->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
4783	pbi->m_BUF[i].luma_size = fb->m.mem[0].size;
4784	fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4785	fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4786	}
4787
4788	/* config frame buffer */
4789	if (pbi->mmu_enable)
4790	pic->header_adr = pbi->m_BUF[i].header_addr;
4791
4792	pic->BUF_index = i;
4793	pic->lcu_total = lcu_total;
4794	pic->mc_canvas_y = pic->index;
4795	pic->mc_canvas_u_v = pic->index;
4796
4797	if (dw_mode & 0x10) {
4798	pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4799	pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4800	pic->mc_canvas_y = (pic->index << 1);
4801	pic->mc_canvas_u_v = (pic->index << 1) + 1;
4802	} else if (dw_mode) {
4803	pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4804	pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4805	}
4806
4807	#ifdef MV_USE_FIXED_BUF
4808	pic->mpred_mv_wr_start_addr =
4809	pbi->work_space_buf->mpred_mv.buf_start +
4810	((pic->index * lcu_total) * MV_MEM_UNIT);
4811	#endif
4812	if (debug) {
4813	pr_info("%s index %d BUF_index %d ",
4814	__func__, pic->index,
4815	pic->BUF_index);
4816	pr_info("comp_body_size %x comp_buf_size %x ",
4817	pic->comp_body_size,
4818	pic->buf_size);
4819	pr_info("mpred_mv_wr_start_adr %ld\n",
4820	pic->mpred_mv_wr_start_addr);
4821	pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4822	pic->dw_y_adr,
4823	pic->dw_u_v_adr);
4824	}
4825	#ifdef MV_USE_FIXED_BUF
4826	}
4827	#endif
4828	return ret;
4829	}
4830
4831	static int config_pic(struct VP9Decoder_s *pbi,
4832	struct PIC_BUFFER_CONFIG_s *pic_config)
4833	{
4834	int ret = -1;
4835	int i;
4836	int pic_width = pbi->init_pic_w;
4837	int pic_height = pbi->init_pic_h;
4838	int lcu_size = 64; /*fixed 64*/
4839	int pic_width_64 = (pic_width + 63) & (~0x3f);
4840	int pic_height_32 = (pic_height + 31) & (~0x1f);
4841	int pic_width_lcu = (pic_width_64 % lcu_size) ?
4842	pic_width_64 / lcu_size + 1
4843	: pic_width_64 / lcu_size;
4844	int pic_height_lcu = (pic_height_32 % lcu_size) ?
4845	pic_height_32 / lcu_size + 1
4846	: pic_height_32 / lcu_size;
4847	int lcu_total = pic_width_lcu * pic_height_lcu;
4848	#ifdef MV_USE_FIXED_BUF
4849	u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4850	pbi->work_space_buf->mpred_mv.buf_size;
4851	#endif
4852	u32 y_adr = 0;
4853	int buf_size = 0;
4854
4855	int losless_comp_header_size =
4856	compute_losless_comp_header_size(pic_width,
4857	pic_height);
4858	int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4859	pic_height, buf_alloc_depth == 10);
4860	int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4861	int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4862	int mc_buffer_size_u_v = 0;
4863	int mc_buffer_size_u_v_h = 0;
4864	int dw_mode = get_double_write_mode_init(pbi);
4865
4866	pbi->lcu_total = lcu_total;
4867
4868	if (dw_mode) {
4869	int pic_width_dw = pic_width /
4870	get_double_write_ratio(pbi, dw_mode);
4871	int pic_height_dw = pic_height /
4872	get_double_write_ratio(pbi, dw_mode);
4873
4874	int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4875	int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4876	int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4877	pic_width_64_dw / lcu_size + 1
4878	: pic_width_64_dw / lcu_size;
4879	int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4880	pic_height_32_dw / lcu_size + 1
4881	: pic_height_32_dw / lcu_size;
4882	int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4883	mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4884	mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4885	/*64k alignment*/
4886	buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4887	buf_size = ((buf_size + 0xffff) >> 16) << 16;
4888	}
4889
4890	if (mc_buffer_size & 0xffff) /*64k alignment*/
4891	mc_buffer_size_h += 1;
4892	if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4893	buf_size += (mc_buffer_size_h << 16);
4894
4895	if (pbi->mmu_enable) {
4896	pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4897	pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4898
4899	if (debug & VP9_DEBUG_BUFMGR_MORE) {
4900	pr_info("MMU header_adr %d: %ld\n",
4901	pic_config->index, pic_config->header_adr);
4902	}
4903	}
4904
4905	i = pic_config->index;
4906	#ifdef MV_USE_FIXED_BUF
4907	if ((pbi->work_space_buf->mpred_mv.buf_start +
4908	(((i + 1) * lcu_total) * MV_MEM_UNIT))
4909	<= mpred_mv_end
4910	) {
4911	#endif
4912	if (buf_size > 0) {
4913	ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4914	VF_BUFFER_IDX(i),
4915	buf_size, DRIVER_NAME,
4916	&pic_config->cma_alloc_addr);
4917	if (ret < 0) {
4918	pr_info(
4919	"decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4920	VF_BUFFER_IDX(i),
4921	buf_size
4922	);
4923	return ret;
4924	}
4925
4926	if (pic_config->cma_alloc_addr)
4927	y_adr = pic_config->cma_alloc_addr;
4928	else {
4929	pr_info(
4930	"decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4931	VF_BUFFER_IDX(i),
4932	buf_size
4933	);
4934	return -1;
4935	}
4936	}
4937	{
4938	/*ensure get_pic_by_POC()
4939	not get the buffer not decoded*/
4940	pic_config->BUF_index = i;
4941	pic_config->lcu_total = lcu_total;
4942
4943	pic_config->comp_body_size = losless_comp_body_size;
4944	pic_config->buf_size = buf_size;
4945
4946	pic_config->mc_canvas_y = pic_config->index;
4947	pic_config->mc_canvas_u_v = pic_config->index;
4948	if (dw_mode & 0x10) {
4949	pic_config->dw_y_adr = y_adr;
4950	pic_config->dw_u_v_adr = y_adr +
4951	((mc_buffer_size_u_v_h << 16) << 1);
4952
4953	pic_config->mc_canvas_y =
4954	(pic_config->index << 1);
4955	pic_config->mc_canvas_u_v =
4956	(pic_config->index << 1) + 1;
4957	} else if (dw_mode) {
4958	pic_config->dw_y_adr = y_adr;
4959	pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4960	((mc_buffer_size_u_v_h << 16) << 1);
4961	}
4962	#ifdef MV_USE_FIXED_BUF
4963	pic_config->mpred_mv_wr_start_addr =
4964	pbi->work_space_buf->mpred_mv.buf_start +
4965	((pic_config->index * lcu_total)
4966	* MV_MEM_UNIT);
4967	#endif
4968	if (debug) {
4969	pr_info
4970	("%s index %d BUF_index %d ",
4971	__func__, pic_config->index,
4972	pic_config->BUF_index);
4973	pr_info
4974	("comp_body_size %x comp_buf_size %x ",
4975	pic_config->comp_body_size,
4976	pic_config->buf_size);
4977	pr_info
4978	("mpred_mv_wr_start_adr %ld\n",
4979	pic_config->mpred_mv_wr_start_addr);
4980	pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4981	pic_config->dw_y_adr,
4982	pic_config->dw_u_v_adr);
4983	}
4984	ret = 0;
4985	}
4986	#ifdef MV_USE_FIXED_BUF
4987	}
4988	#endif
4989	return ret;
4990	}
4991
4992	static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
4993	{
4994	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
4995	IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
4996	return (MMU_COMPRESS_8K_HEADER_SIZE);
4997
4998	return (MMU_COMPRESS_HEADER_SIZE);
4999	}
5000
5001	/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5002	static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5003	{
5004	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5005	IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5006	return (MAX_FRAME_8K_NUM * 4);
5007
5008	return (MAX_FRAME_4K_NUM * 4);
5009	}
5010
5011	static void init_pic_list(struct VP9Decoder_s *pbi)
5012	{
5013	int i;
5014	struct VP9_Common_s *cm = &pbi->common;
5015	struct PIC_BUFFER_CONFIG_s *pic_config;
5016	u32 header_size;
5017	struct vdec_s *vdec = hw_to_vdec(pbi);
5018
5019	if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5020	header_size = vvp9_mmu_compress_header_size(pbi);
5021	/*alloc VP9 compress header first*/
5022	for (i = 0; i < pbi->used_buf_num; i++) {
5023	unsigned long buf_addr;
5024	if (decoder_bmmu_box_alloc_buf_phy
5025	(pbi->bmmu_box,
5026	HEADER_BUFFER_IDX(i), header_size,
5027	DRIVER_HEADER_NAME,
5028	&buf_addr) < 0) {
5029	pr_info("%s malloc compress header failed %d\n",
5030	DRIVER_HEADER_NAME, i);
5031	pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5032	return;
5033	}
5034	}
5035	}
5036	for (i = 0; i < pbi->used_buf_num; i++) {
5037	pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5038	pic_config->index = i;
5039	pic_config->BUF_index = -1;
5040	pic_config->mv_buf_index = -1;
5041	if (vdec->parallel_dec == 1) {
5042	pic_config->y_canvas_index = -1;
5043	pic_config->uv_canvas_index = -1;
5044	}
5045	pic_config->y_crop_width = pbi->init_pic_w;
5046	pic_config->y_crop_height = pbi->init_pic_h;
5047	pic_config->double_write_mode = get_double_write_mode(pbi);
5048
5049	if (!pbi->is_used_v4l) {
5050	if (config_pic(pbi, pic_config) < 0) {
5051	if (debug)
5052	pr_info("Config_pic %d fail\n",
5053	pic_config->index);
5054	pic_config->index = -1;
5055	break;
5056	}
5057
5058	if (pic_config->double_write_mode) {
5059	set_canvas(pbi, pic_config);
5060	}
5061	}
5062	}
5063	for (; i < pbi->used_buf_num; i++) {
5064	pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5065	pic_config->index = -1;
5066	pic_config->BUF_index = -1;
5067	pic_config->mv_buf_index = -1;
5068	if (vdec->parallel_dec == 1) {
5069	pic_config->y_canvas_index = -1;
5070	pic_config->uv_canvas_index = -1;
5071	}
5072	}
5073	pr_info("%s ok, used_buf_num = %d\n",
5074	__func__, pbi->used_buf_num);
5075	}
5076
5077	static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5078	{
5079	int i;
5080	struct VP9_Common_s *cm = &pbi->common;
5081	struct PIC_BUFFER_CONFIG_s *pic_config;
5082	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5083	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5084	(0x1 << 1) | (0x1 << 2));
5085
5086
5087	for (i = 0; i < pbi->used_buf_num; i++) {
5088	pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5089	if (pic_config->index < 0)
5090	break;
5091
5092	if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5093
5094	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5095	pic_config->header_adr >> 5);
5096	} else {
5097	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5098	* pic_config->mc_y_adr
5099	* | (pic_config->mc_canvas_y << 8) | 0x1);
5100	*/
5101	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5102	pic_config->dw_y_adr >> 5);
5103	}
5104	#ifndef LOSLESS_COMPRESS_MODE
5105	/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5106	* pic_config->mc_u_v_adr
5107	* | (pic_config->mc_canvas_u_v << 8)| 0x1);
5108	*/
5109	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5110	pic_config->header_adr >> 5);
5111	#else
5112	if (pic_config->double_write_mode & 0x10) {
5113	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5114	pic_config->dw_u_v_adr >> 5);
5115	}
5116	#endif
5117	}
5118	WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5119
5120	/*Zero out canvas registers in IPP -- avoid simulation X*/
5121	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5122	(0 << 8) | (0 << 1) | 1);
5123	for (i = 0; i < 32; i++)
5124	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5125	}
5126
5127
5128	static void dump_pic_list(struct VP9Decoder_s *pbi)
5129	{
5130	struct VP9_Common_s *const cm = &pbi->common;
5131	struct PIC_BUFFER_CONFIG_s *pic_config;
5132	int i;
5133	for (i = 0; i < FRAME_BUFFERS; i++) {
5134	pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5135	vp9_print(pbi, 0,
5136	"Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5137	i,
5138	pic_config->index,
5139	#ifndef MV_USE_FIXED_BUF
5140	pic_config->mv_buf_index,
5141	#else
5142	-1,
5143	#endif
5144	cm->buffer_pool->
5145	frame_bufs[i].ref_count,
5146	pic_config->vf_ref,
5147	pic_config->decode_idx,
5148	pic_config->slice_type,
5149	pic_config->y_crop_width,
5150	pic_config->y_crop_height,
5151	pic_config->cma_alloc_addr
5152	);
5153	}
5154	return;
5155	}
5156
5157	static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5158	{
5159	#ifdef LOSLESS_COMPRESS_MODE
5160	unsigned int data32;
5161	#endif
5162	int losless_comp_header_size, losless_comp_body_size;
5163	struct VP9_Common_s *cm = &pbi->common;
5164	struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5165
5166	frame_width = cur_pic_config->y_crop_width;
5167	frame_height = cur_pic_config->y_crop_height;
5168	cur_pic_config->bit_depth = bit_depth;
5169	cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5170	losless_comp_header_size =
5171	compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5172	cur_pic_config->y_crop_height);
5173	losless_comp_body_size =
5174	compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5175	cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5176	cur_pic_config->comp_body_size = losless_comp_body_size;
5177	#ifdef LOSLESS_COMPRESS_MODE
5178	data32 = READ_VREG(HEVC_SAO_CTRL5);
5179	if (bit_depth == VPX_BITS_10)
5180	data32 &= ~(1 << 9);
5181	else
5182	data32 |= (1 << 9);
5183
5184	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5185
5186	if (pbi->mmu_enable) {
5187	/*bit[4] : paged_mem_mode*/
5188	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5189	} else {
5190	/*bit[3] smem mdoe*/
5191	if (bit_depth == VPX_BITS_10)
5192	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5193	else
5194	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5195	}
5196	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5197	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5198	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5199	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5200	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5201	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5202	if (get_double_write_mode(pbi) & 0x10)
5203	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5204	#else
5205	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5206	#endif
5207	return 0;
5208	}
5209
5210	static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5211	{
5212	int i;
5213	struct VP9_Common_s *cm = &pbi->common;
5214	struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5215	uint8_t scale_enable = 0;
5216
5217	if (debug&VP9_DEBUG_BUFMGR_MORE)
5218	pr_info("config_mc_buffer entered .....\n");
5219
5220	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5221	(0 << 8) | (0 << 1) | 1);
5222	for (i = 0; i < REFS_PER_FRAME; ++i) {
5223	struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5224	if (!pic_config)
5225	continue;
5226	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5227	(pic_config->mc_canvas_u_v << 16)
5228	| (pic_config->mc_canvas_u_v << 8)
5229	| pic_config->mc_canvas_y);
5230	if (debug & VP9_DEBUG_BUFMGR_MORE)
5231	pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5232	i, pic_config->mc_canvas_u_v,
5233	pic_config->mc_canvas_y);
5234	}
5235	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5236	(16 << 8) | (0 << 1) | 1);
5237	for (i = 0; i < REFS_PER_FRAME; ++i) {
5238	struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5239	if (!pic_config)
5240	continue;
5241	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5242	(pic_config->mc_canvas_u_v << 16)
5243	| (pic_config->mc_canvas_u_v << 8)
5244	| pic_config->mc_canvas_y);
5245	}
5246
5247	/*auto_inc start index:0 field:0*/
5248	WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5249	/*index 0:last 1:golden 2:altref*/
5250	for (i = 0; i < REFS_PER_FRAME; i++) {
5251	int ref_pic_body_size;
5252	struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5253	if (!pic_config)
5254	continue;
5255	WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5256	WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5257
5258	if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5259	pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5260	scale_enable |= (1 << i);
5261	}
5262	ref_pic_body_size =
5263	compute_losless_comp_body_size(pic_config->y_crop_width,
5264	pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5265	WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5266	(pic_config->y_crop_width << 14)
5267	/ cur_pic_config->y_crop_width);
5268	WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5269	(pic_config->y_crop_height << 14)
5270	/ cur_pic_config->y_crop_height);
5271	if (pbi->mmu_enable)
5272	WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5273	else
5274	WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5275	}
5276	WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5277	return 0;
5278	}
5279
5280	static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5281	{
5282	unsigned int data32;
5283
5284	data32 = READ_VREG(HEVC_MPRED_CTRL4);
5285	data32 &= (~(1 << 6));
5286	WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5287	}
5288
5289	static void config_mpred_hw(struct VP9Decoder_s *pbi)
5290	{
5291	struct VP9_Common_s *cm = &pbi->common;
5292	struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5293	struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5294	&cm->prev_frame->buf;
5295
5296	unsigned int data32;
5297	int mpred_curr_lcu_x;
5298	int mpred_curr_lcu_y;
5299	int mpred_mv_rd_end_addr;
5300
5301
5302	mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5303	+ (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5304
5305	data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5306	mpred_curr_lcu_x = data32 & 0xffff;
5307	mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5308
5309	if (debug & VP9_DEBUG_BUFMGR)
5310	pr_info("cur pic_config index %d col pic_config index %d\n",
5311	cur_pic_config->index, last_frame_pic_config->index);
5312	WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5313	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5314	pbi->work_space_buf->mpred_above.buf_start);
5315
5316	data32 = READ_VREG(HEVC_MPRED_CTRL4);
5317
5318	data32 &= (~(1 << 6));
5319	data32 |= (cm->use_prev_frame_mvs << 6);
5320	WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5321
5322	WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5323	cur_pic_config->mpred_mv_wr_start_addr);
5324	WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5325
5326	WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5327	last_frame_pic_config->mpred_mv_wr_start_addr);
5328	WRITE_VREG(HEVC_MPRED_MV_RPTR,
5329	last_frame_pic_config->mpred_mv_wr_start_addr);
5330	/*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5331	/*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5332	/*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5333	WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5334
5335	}
5336
5337	static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5338	{
5339	struct VP9_Common_s *cm = &pbi->common;
5340	struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5341
5342	unsigned int data32;
5343	int lcu_size = 64;
5344	int mc_buffer_size_u_v =
5345	pic_config->lcu_total * lcu_size*lcu_size/2;
5346	int mc_buffer_size_u_v_h =
5347	(mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5348	struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5349
5350	if (get_double_write_mode(pbi)) {
5351	WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5352	WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5353	WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5354	WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5355	} else {
5356	WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5357	WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5358	}
5359	if (pbi->mmu_enable)
5360	WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5361
5362	data32 = (mc_buffer_size_u_v_h << 16) << 1;
5363	/*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5364	* data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5365	*/
5366	WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5367
5368	data32 = (mc_buffer_size_u_v_h << 16);
5369	WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5370
5371	#ifdef VP9_10B_NV21
5372	#ifdef DOS_PROJECT
5373	data32 = READ_VREG(HEVC_SAO_CTRL1);
5374	data32 &= (~0x3000);
5375	/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5376	data32 |= (pbi->mem_map_mode << 12);
5377	data32 &= (~0x3);
5378	data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5379	WRITE_VREG(HEVC_SAO_CTRL1, data32);
5380	/*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5381	* [17:16] dw_h0_ctrl
5382	*/
5383	data32 = READ_VREG(HEVC_SAO_CTRL5);
5384	/*set them all 0 for H265_NV21 (no down-scale)*/
5385	data32 &= ~(0xff << 16);
5386	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5387	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5388	data32 &= (~0x30);
5389	/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5390	data32 |= (pbi->mem_map_mode << 4);
5391	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5392	#else
5393	/*m8baby test1902*/
5394	data32 = READ_VREG(HEVC_SAO_CTRL1);
5395	data32 &= (~0x3000);
5396	/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5397	data32 |= (pbi->mem_map_mode << 12);
5398	data32 &= (~0xff0);
5399	/*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5400	data32 |= 0x880; /*.Big-Endian per 64-bit */
5401	data32 &= (~0x3);
5402	data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5403	WRITE_VREG(HEVC_SAO_CTRL1, data32);
5404	/* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5405	*[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5406	*/
5407	data32 = READ_VREG(HEVC_SAO_CTRL5);
5408	/* set them all 0 for H265_NV21 (no down-scale)*/
5409	data32 &= ~(0xff << 16);
5410	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5411
5412	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5413	data32 &= (~0x30);
5414	/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5415	data32 |= (pbi->mem_map_mode << 4);
5416	data32 &= (~0xF);
5417	data32 |= 0x8; /*Big-Endian per 64-bit*/
5418	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5419	#endif
5420	#else
5421	data32 = READ_VREG(HEVC_SAO_CTRL1);
5422	data32 &= (~0x3000);
5423	data32 |= (pbi->mem_map_mode <<
5424	12);
5425
5426	/* [13:12] axi_aformat, 0-Linear,
5427	* 1-32x32, 2-64x32
5428	*/
5429	data32 &= (~0xff0);
5430	/* data32 |= 0x670; // Big-Endian per 64-bit */
5431	data32 |= endian; /* Big-Endian per 64-bit */
5432	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5433	data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5434	if (get_double_write_mode(pbi) == 0)
5435	data32 |= 0x2; /*disable double write*/
5436	else if (get_double_write_mode(pbi) & 0x10)
5437	data32 |= 0x1; /*disable cm*/
5438	} else { /* >= G12A dw write control */
5439	unsigned int data;
5440	data = READ_VREG(HEVC_DBLK_CFGB);
5441	data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5442	if (get_double_write_mode(pbi) == 0)
5443	data |= (0x1 << 8); /*enable first write*/
5444	else if (get_double_write_mode(pbi) & 0x10)
5445	data |= (0x1 << 9); /*double write only*/
5446	else
5447	data |= ((0x1 << 8) |(0x1 << 9));
5448	WRITE_VREG(HEVC_DBLK_CFGB, data);
5449	}
5450
5451	/* swap uv */
5452	if (pbi->is_used_v4l) {
5453	if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5454	(v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5455	data32 &= ~(1 << 8); /* NV21 */
5456	else
5457	data32 |= (1 << 8); /* NV12 */
5458	}
5459
5460	/*
5461	* [31:24] ar_fifo1_axi_thred
5462	* [23:16] ar_fifo0_axi_thred
5463	* [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5464	* [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5465	* [11:08] axi_lendian_C
5466	* [07:04] axi_lendian_Y
5467	* [3] reserved
5468	* [2] clk_forceon
5469	* [1] dw_disable:disable double write output
5470	* [0] cm_disable:disable compress output
5471	*/
5472	WRITE_VREG(HEVC_SAO_CTRL1, data32);
5473
5474	if (get_double_write_mode(pbi) & 0x10) {
5475	/* [23:22] dw_v1_ctrl
5476	*[21:20] dw_v0_ctrl
5477	*[19:18] dw_h1_ctrl
5478	*[17:16] dw_h0_ctrl
5479	*/
5480	data32 = READ_VREG(HEVC_SAO_CTRL5);
5481	/*set them all 0 for H265_NV21 (no down-scale)*/
5482	data32 &= ~(0xff << 16);
5483	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5484	} else {
5485	data32 = READ_VREG(HEVC_SAO_CTRL5);
5486	data32 &= (~(0xff << 16));
5487	if (get_double_write_mode(pbi) == 2 ||
5488	get_double_write_mode(pbi) == 3)
5489	data32 |= (0xff<<16);
5490	else if (get_double_write_mode(pbi) == 4)
5491	data32 |= (0x33<<16);
5492	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5493	}
5494
5495	data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5496	data32 &= (~0x30);
5497	/* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5498	data32 |= (pbi->mem_map_mode <<
5499	4);
5500	data32 &= (~0xF);
5501	data32 |= 0xf; /* valid only when double write only */
5502	/*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5503
5504	/* swap uv */
5505	if (pbi->is_used_v4l) {
5506	if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5507	(v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5508	data32 |= (1 << 12); /* NV21 */
5509	else
5510	data32 &= ~(1 << 12); /* NV12 */
5511	}
5512
5513	/*
5514	* [3:0] little_endian
5515	* [5:4] address_format 00:linear 01:32x32 10:64x32
5516	* [7:6] reserved
5517	* [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5518	* [11:10] reserved
5519	* [12] CbCr_byte_swap
5520	* [31:13] reserved
5521	*/
5522	WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5523	#endif
5524	}
5525
5526	static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5527	{
5528	struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5529	unsigned int data32;
5530
5531	if (debug && pbi->init_flag == 0)
5532	pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5533	__func__,
5534	buf_spec->ipp.buf_start,
5535	buf_spec->start_adr,
5536	buf_spec->short_term_rps.buf_start,
5537	buf_spec->vps.buf_start,
5538	buf_spec->sps.buf_start,
5539	buf_spec->pps.buf_start,
5540	buf_spec->sao_up.buf_start,
5541	buf_spec->swap_buf.buf_start,
5542	buf_spec->swap_buf2.buf_start,
5543	buf_spec->scalelut.buf_start,
5544	buf_spec->dblk_para.buf_start,
5545	buf_spec->dblk_data.buf_start);
5546
5547	if (mask & HW_MASK_FRONT) {
5548	if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5549	WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5550
5551	WRITE_VREG(HEVC_SHORT_TERM_RPS,
5552	buf_spec->short_term_rps.buf_start);
5553	/*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5554	/*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5555	WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5556	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5557	buf_spec->swap_buf.buf_start);
5558	WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5559	buf_spec->swap_buf2.buf_start);
5560	WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5561
5562	}
5563
5564	if (mask & HW_MASK_BACK) {
5565	#ifdef LOSLESS_COMPRESS_MODE
5566	int losless_comp_header_size =
5567	compute_losless_comp_header_size(pbi->init_pic_w,
5568	pbi->init_pic_h);
5569	int losless_comp_body_size =
5570	compute_losless_comp_body_size(pbi->init_pic_w,
5571	pbi->init_pic_h, buf_alloc_depth == 10);
5572	#endif
5573	WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5574	buf_spec->ipp.buf_start);
5575	WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5576	WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5577	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5578	/* cfg_addr_adp*/
5579	WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5580	if (debug & VP9_DEBUG_BUFMGR_MORE)
5581	pr_info("Write HEVC_DBLK_CFGE\n");
5582	}
5583	/* cfg_p_addr */
5584	WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5585	/* cfg_d_addr */
5586	WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5587
5588	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5589	/*
5590	* data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5591	* data32 = data32 * 2;
5592	* data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5593	* data32 = data32 * 2;
5594	*/
5595	WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5596	}
5597	#ifdef LOSLESS_COMPRESS_MODE
5598	if (pbi->mmu_enable) {
5599	/*bit[4] : paged_mem_mode*/
5600	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5601	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5602	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5603	} else {
5604	/*if(cur_pic_config->bit_depth == VPX_BITS_10)
5605	* WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5606	*/
5607	/*bit[3] smem mdoe*/
5608	/*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5609	/*bit[3] smem mdoe*/
5610	WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5611	(losless_comp_body_size >> 5));
5612	}
5613	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5614	(losless_comp_body_size >> 5));*/
5615	/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5616	(0xff<<20) | (0xff<<10) | 0xff);*/
5617	/*8-bit mode */
5618	WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5619	WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5620	WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5621	if (get_double_write_mode(pbi) & 0x10)
5622	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5623	#else
5624	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5625	#endif
5626
5627	if (pbi->mmu_enable) {
5628	WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5629	WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5630	+ buf_spec->mmu_vbh.buf_size/2);
5631	/*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5632	/*data32 |= 0x1;*/
5633	/*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5634
5635	/* use HEVC_CM_HEADER_START_ADDR */
5636	data32 = READ_VREG(HEVC_SAO_CTRL5);
5637	data32 |= (1<<10);
5638	WRITE_VREG(HEVC_SAO_CTRL5, data32);
5639	}
5640
5641	WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5642
5643	WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5644	/**/
5645	WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5646	WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5647	if (pbi->mmu_enable) {
5648	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5649	WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5650	else
5651	WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5652	}
5653	}
5654	}
5655
5656
5657	#ifdef VP9_LPF_LVL_UPDATE
5658	/*
5659	* Defines, declarations, sub-functions for vp9 de-block loop
5660	filter Thr/Lvl table update
5661	* - struct segmentation is for loop filter only (removed something)
5662	* - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5663	be instantiated in C_Entry
5664	* - vp9_loop_filter_init run once before decoding start
5665	* - vp9_loop_filter_frame_init run before every frame decoding start
5666	* - set video format to VP9 is in vp9_loop_filter_init
5667	*/
5668	#define MAX_LOOP_FILTER 63
5669	#define MAX_REF_LF_DELTAS 4
5670	#define MAX_MODE_LF_DELTAS 2
5671	/*#define INTRA_FRAME 0*/
5672	/*#define LAST_FRAME 1*/
5673	/*#define MAX_REF_FRAMES 4*/
5674	#define SEGMENT_DELTADATA 0
5675	#define SEGMENT_ABSDATA 1
5676	#define MAX_SEGMENTS 8
5677	/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5678	/*no use for loop filter, if this struct for common use, pls add it back*/
5679	/*#define PREDICTION_PROBS 3*/
5680	/* no use for loop filter, if this struct for common use, pls add it back*/
5681
5682	enum SEG_LVL_FEATURES {
5683	SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5684	SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5685	SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5686	SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5687	SEG_LVL_MAX = 4 /*Number of features supported*/
5688	};
5689
5690	struct segmentation {
5691	uint8_t enabled;
5692	uint8_t update_map;
5693	uint8_t update_data;
5694	uint8_t abs_delta;
5695	uint8_t temporal_update;
5696
5697	/*no use for loop filter, if this struct
5698	*for common use, pls add it back
5699	*/
5700	/*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5701	/* no use for loop filter, if this struct
5702	* for common use, pls add it back
5703	*/
5704	/*vp9_prob pred_probs[PREDICTION_PROBS];*/
5705
5706	int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5707	unsigned int feature_mask[MAX_SEGMENTS];
5708	};
5709
5710	struct loop_filter_thresh {
5711	uint8_t mblim;
5712	uint8_t lim;
5713	uint8_t hev_thr;
5714	};
5715
5716	struct loop_filter_info_n {
5717	struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5718	uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5719	};
5720
5721	struct loopfilter {
5722	int filter_level;
5723
5724	int sharpness_level;
5725	int last_sharpness_level;
5726
5727	uint8_t mode_ref_delta_enabled;
5728	uint8_t mode_ref_delta_update;
5729
5730	/*0 = Intra, Last, GF, ARF*/
5731	signed char ref_deltas[MAX_REF_LF_DELTAS];
5732	signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5733
5734	/*0 = ZERO_MV, MV*/
5735	signed char mode_deltas[MAX_MODE_LF_DELTAS];
5736	signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5737	};
5738
5739	static int vp9_clamp(int value, int low, int high)
5740	{
5741	return value < low ? low : (value > high ? high : value);
5742	}
5743
5744	int segfeature_active(struct segmentation *seg,
5745	int segment_id,
5746	enum SEG_LVL_FEATURES feature_id) {
5747	return seg->enabled &&
5748	(seg->feature_mask[segment_id] & (1 << feature_id));
5749	}
5750
5751	int get_segdata(struct segmentation *seg, int segment_id,
5752	enum SEG_LVL_FEATURES feature_id) {
5753	return seg->feature_data[segment_id][feature_id];
5754	}
5755
5756	static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5757	int sharpness_lvl)
5758	{
5759	int lvl;
5760	/*For each possible value for the loop filter fill out limits*/
5761	for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5762	/*Set loop filter parameters that control sharpness.*/
5763	int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5764	(sharpness_lvl > 4));
5765
5766	if (sharpness_lvl > 0) {
5767	if (block_inside_limit > (9 - sharpness_lvl))
5768	block_inside_limit = (9 - sharpness_lvl);
5769	}
5770
5771	if (block_inside_limit < 1)
5772	block_inside_limit = 1;
5773
5774	lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5775	lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5776	block_inside_limit);
5777	}
5778	}
5779
5780	/*instantiate this function once when decode is started*/
5781	void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5782	{
5783	struct loop_filter_info_n *lfi = pbi->lfi;
5784	struct loopfilter *lf = pbi->lf;
5785	struct segmentation *seg_4lf = pbi->seg_4lf;
5786	int i;
5787	unsigned int data32;
5788
5789	memset(lfi, 0, sizeof(struct loop_filter_info_n));
5790	memset(lf, 0, sizeof(struct loopfilter));
5791	memset(seg_4lf, 0, sizeof(struct segmentation));
5792	lf->sharpness_level = 0; /*init to 0 */
5793	/*init limits for given sharpness*/
5794	vp9_update_sharpness(lfi, lf->sharpness_level);
5795	lf->last_sharpness_level = lf->sharpness_level;
5796	/*init hev threshold const vectors (actually no use)
5797	*for (i = 0; i <= MAX_LOOP_FILTER; i++)
5798	* lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5799	*/
5800
5801	/*Write to register*/
5802	for (i = 0; i < 32; i++) {
5803	unsigned int thr;
5804
5805	thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5806	(lfi->lfthr[i * 2 + 1].mblim & 0xff);
5807	thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5808	(lfi->lfthr[i * 2].mblim & 0xff);
5809	WRITE_VREG(HEVC_DBLK_CFG9, thr);
5810	}
5811
5812	/*video format is VP9*/
5813	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5814	data32 = (0x3 << 14) | // (dw fifo thres r and b)
5815	(0x3 << 12) | // (dw fifo thres r or b)
5816	(0x3 << 10) | // (dw fifo thres not r/b)
5817	(0x3 << 8) | // 1st/2nd write both enable
5818	(0x1 << 0); // vp9 video format
5819	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5820	data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5821	(0x1 << 0); /*vp9 video format*/
5822	} else
5823	data32 = 0x40400001;
5824
5825	WRITE_VREG(HEVC_DBLK_CFGB, data32);
5826	if (debug & VP9_DEBUG_BUFMGR_MORE)
5827	pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5828	}
5829	/* perform this function per frame*/
5830	void vp9_loop_filter_frame_init(struct segmentation *seg,
5831	struct loop_filter_info_n *lfi, struct loopfilter *lf,
5832	int default_filt_lvl) {
5833	int i;
5834	int seg_id;
5835	/*n_shift is the multiplier for lf_deltas
5836	*the multiplier is 1 for when filter_lvl is between 0 and 31;
5837	*2 when filter_lvl is between 32 and 63
5838	*/
5839	const int scale = 1 << (default_filt_lvl >> 5);
5840
5841	/*update limits if sharpness has changed*/
5842	if (lf->last_sharpness_level != lf->sharpness_level) {
5843	vp9_update_sharpness(lfi, lf->sharpness_level);
5844	lf->last_sharpness_level = lf->sharpness_level;
5845
5846	/*Write to register*/
5847	for (i = 0; i < 32; i++) {
5848	unsigned int thr;
5849
5850	thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5851	| (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5852	thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5853	| (lfi->lfthr[i * 2].mblim & 0xff);
5854	WRITE_VREG(HEVC_DBLK_CFG9, thr);
5855	}
5856	}
5857
5858	for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5859	int lvl_seg = default_filt_lvl;
5860
5861	if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5862	const int data = get_segdata(seg, seg_id,
5863	SEG_LVL_ALT_LF);
5864	lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5865	data : default_filt_lvl + data,
5866	0, MAX_LOOP_FILTER);
5867	#ifdef DBG_LF_PRINT
5868	pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5869	#endif
5870	}
5871
5872	if (!lf->mode_ref_delta_enabled) {
5873	/*we could get rid of this if we assume that deltas are set to
5874	*zero when not in use; encoder always uses deltas
5875	*/
5876	memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5877	} else {
5878	int ref, mode;
5879	const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5880	* scale;
5881	#ifdef DBG_LF_PRINT
5882	pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5883	pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5884	#endif
5885	lfi->lvl[seg_id][INTRA_FRAME][0] =
5886	vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5887
5888	for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5889	/* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5890	for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5891	/*MAX_MODE_LF_DELTAS = 2*/
5892	const int inter_lvl =
5893	lvl_seg + lf->ref_deltas[ref] * scale
5894	+ lf->mode_deltas[mode] * scale;
5895	#ifdef DBG_LF_PRINT
5896	#endif
5897	lfi->lvl[seg_id][ref][mode] =
5898	vp9_clamp(inter_lvl, 0,
5899	MAX_LOOP_FILTER);
5900	}
5901	}
5902	}
5903	}
5904
5905	#ifdef DBG_LF_PRINT
5906	/*print out thr/lvl table per frame*/
5907	for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5908	pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5909	i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5910	lfi->lfthr[i].lim);
5911	}
5912	for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5913	pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5914	seg_id, lfi->lvl[seg_id][0][0],
5915	lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5916	lfi->lvl[seg_id][3][0]);
5917	pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5918	lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5919	lfi->lvl[seg_id][3][1]);
5920	}
5921	#endif
5922
5923	/*Write to register */
5924	for (i = 0; i < 16; i++) {
5925	unsigned int level;
5926
5927	level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5928	((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5929	((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5930	(lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5931	if (!default_filt_lvl)
5932	level = 0;
5933	WRITE_VREG(HEVC_DBLK_CFGA, level);
5934	}
5935	}
5936	/* VP9_LPF_LVL_UPDATE */
5937	#endif
5938
5939	static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5940	{
5941	unsigned int data32;
5942	int i;
5943	const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5944	0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5945	0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5946	0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5947	0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5948	0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5949	0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5950	0x7C00
5951	};
5952	#if 0
5953	if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5954	/* Set MCR fetch priorities*/
5955	data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5956	(24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5957	WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5958	}
5959	#endif
5960	/*if (debug & VP9_DEBUG_BUFMGR_MORE)
5961	pr_info("%s\n", __func__);*/
5962	if (mask & HW_MASK_FRONT) {
5963	data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5964	#if 1
5965	/* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5966	data32 &= ~(7 << 29);
5967	data32 |= (3 << 29);
5968	#endif
5969	data32 = data32 |
5970	(1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
5971	(1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
5972	(1 << 7) |/*dec_done_int_cpu_enable*/
5973	(1 << 4) |/*startcode_found_int_cpu_enable*/
5974	(0 << 3) |/*startcode_found_int_amrisc_enable*/
5975	(1 << 0) /*parser_int_enable*/
5976	;
5977	#ifdef SUPPORT_FB_DECODING
5978	#ifndef FB_DECODING_TEST_SCHEDULE
5979	/*fed_fb_slice_done_int_cpu_enable*/
5980	if (pbi->used_stage_buf_num > 0)
5981	data32 |= (1 << 10);
5982	#endif
5983	#endif
5984	WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
5985
5986	data32 = READ_VREG(HEVC_SHIFT_STATUS);
5987	data32 = data32 |
5988	(0 << 1) |/*emulation_check_off VP9
5989	do not have emulation*/
5990	(1 << 0)/*startcode_check_on*/
5991	;
5992	WRITE_VREG(HEVC_SHIFT_STATUS, data32);
5993	WRITE_VREG(HEVC_SHIFT_CONTROL,
5994	(0 << 14) | /*disable_start_code_protect*/
5995	(1 << 10) | /*length_zero_startcode_en for VP9*/
5996	(1 << 9) | /*length_valid_startcode_en for VP9*/
5997	(3 << 6) | /*sft_valid_wr_position*/
5998	(2 << 4) | /*emulate_code_length_sub_1*/
5999	(3 << 1) | /*start_code_length_sub_1
6000	VP9 use 0x00000001 as startcode (4 Bytes)*/
6001	(1 << 0) /*stream_shift_enable*/
6002	);
6003
6004	WRITE_VREG(HEVC_CABAC_CONTROL,
6005	(1 << 0)/*cabac_enable*/
6006	);
6007
6008	WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6009	(1 << 0)/* hevc_parser_core_clk_en*/
6010	);
6011
6012
6013	WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6014
6015	}
6016
6017	if (mask & HW_MASK_BACK) {
6018	/*Initial IQIT_SCALELUT memory
6019	-- just to avoid X in simulation*/
6020
6021	WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6022	for (i = 0; i < 1024; i++)
6023	WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6024	}
6025
6026	if (mask & HW_MASK_FRONT) {
6027	u32 decode_mode;
6028	#ifdef ENABLE_SWAP_TEST
6029	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6030	#else
6031	WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6032	#endif
6033	#ifdef MULTI_INSTANCE_SUPPORT
6034	if (!pbi->m_ins_flag) {
6035	if (pbi->low_latency_flag)
6036	decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6037	else
6038	decode_mode = DECODE_MODE_SINGLE;
6039	} else if (vdec_frame_based(hw_to_vdec(pbi)))
6040	decode_mode = pbi->no_head ?
6041	DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6042	DECODE_MODE_MULTI_FRAMEBASE;
6043	else
6044	decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6045	#ifdef SUPPORT_FB_DECODING
6046	#ifndef FB_DECODING_TEST_SCHEDULE
6047	if (pbi->used_stage_buf_num > 0)
6048	decode_mode |= (0x01 << 24);
6049	#endif
6050	#endif
6051	WRITE_VREG(DECODE_MODE, decode_mode);
6052	WRITE_VREG(HEVC_DECODE_SIZE, 0);
6053	WRITE_VREG(HEVC_DECODE_COUNT, 0);
6054	#else
6055	WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6056	WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6057	WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6058	#endif
6059	/*Send parser_cmd*/
6060	WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6061	for (i = 0; i < PARSER_CMD_NUMBER; i++)
6062	WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6063	WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6064	WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6065	WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6066
6067
6068	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6069	/* (1 << 8) |*/ /*sao_sw_pred_enable*/
6070	(1 << 5) | /*parser_sao_if_en*/
6071	(1 << 2) | /*parser_mpred_if_en*/
6072	(1 << 0) /*parser_scaler_if_en*/
6073	);
6074	}
6075
6076	if (mask & HW_MASK_BACK) {
6077	/*Changed to Start MPRED in microcode*/
6078	/*
6079	pr_info("[test.c] Start MPRED\n");
6080	WRITE_VREG(HEVC_MPRED_INT_STATUS,
6081	(1<<31)
6082	);
6083	*/
6084	WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6085	(0 << 1) | /*enable ipp*/
6086	(1 << 0) /*software reset ipp and mpp*/
6087	);
6088	WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6089	(1 << 1) | /*enable ipp*/
6090	(0 << 0) /*software reset ipp and mpp*/
6091	);
6092	if (get_double_write_mode(pbi) & 0x10) {
6093	/*Enable NV21 reference read mode for MC*/
6094	WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6095	}
6096
6097	/*Initialize mcrcc and decomp perf counters*/
6098	if (mcrcc_cache_alg_flag &&
6099	pbi->init_flag == 0) {
6100	mcrcc_perfcount_reset();
6101	decomp_perfcount_reset();
6102	}
6103	}
6104	return;
6105	}
6106
6107
6108	#ifdef CONFIG_HEVC_CLK_FORCED_ON
6109	static void config_vp9_clk_forced_on(void)
6110	{
6111	unsigned int rdata32;
6112	/*IQIT*/
6113	rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6114	WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6115
6116	/* DBLK*/
6117	rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6118	WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6119
6120	/* SAO*/
6121	rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6122	WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6123
6124	/*MPRED*/
6125	rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6126	WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6127
6128	/* PARSER*/
6129	rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6130	WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6131	rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6132	WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6133	rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6134	WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6135	rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6136	WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6137	rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6138	WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6139	rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6140	WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6141	rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6142
6143	/*IPP*/
6144	rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6145	WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6146
6147	/* MCRCC*/
6148	rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6149	WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6150	}
6151	#endif
6152
6153
6154	#ifdef MCRCC_ENABLE
6155	static void dump_hit_rate(struct VP9Decoder_s *pbi)
6156	{
6157	if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6158	mcrcc_get_hitrate(pbi->m_ins_flag);
6159	decomp_get_hitrate();
6160	decomp_get_comprate();
6161	}
6162	}
6163
6164	static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6165	{
6166	unsigned int rdata32;
6167	unsigned short is_inter;
6168	/*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6169	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6170	is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6171	(!pbi->common.intra_only)) ? 1 : 0;
6172	if (!is_inter) { /* I-PIC*/
6173	/*remove reset -- disables clock*/
6174	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6175	return;
6176	}
6177
6178	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6179	mcrcc_get_hitrate(pbi->m_ins_flag);
6180	decomp_get_hitrate();
6181	decomp_get_comprate();
6182	}
6183
6184	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6185	(0 << 8) | (1 << 1) | 0);
6186	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6187	rdata32 = rdata32 & 0xffff;
6188	rdata32 = rdata32 | (rdata32 << 16);
6189	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6190	/*Programme canvas1 */
6191	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6192	rdata32 = rdata32 & 0xffff;
6193	rdata32 = rdata32 | (rdata32 << 16);
6194	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6195	/*enable mcrcc progressive-mode*/
6196	WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6197	}
6198
6199	static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6200	{
6201	u32 curr_picnum = -1;
6202	u32 lastref_picnum = -1;
6203	u32 goldenref_picnum = -1;
6204	u32 altref_picnum = -1;
6205
6206	u32 lastref_delta_picnum;
6207	u32 goldenref_delta_picnum;
6208	u32 altref_delta_picnum;
6209
6210	u32 rdata32;
6211
6212	u32 lastcanvas;
6213	u32 goldencanvas;
6214	u32 altrefcanvas;
6215
6216	u16 is_inter;
6217	u16 lastref_inref;
6218	u16 goldenref_inref;
6219	u16 altref_inref;
6220
6221	u32 refcanvas_array[3], utmp;
6222	int deltapicnum_array[3], tmp;
6223
6224	struct VP9_Common_s *cm = &pbi->common;
6225	struct PIC_BUFFER_CONFIG_s *cur_pic_config
6226	= &cm->cur_frame->buf;
6227	curr_picnum = cur_pic_config->decode_idx;
6228	if (cm->frame_refs[0].buf)
6229	lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6230	if (cm->frame_refs[1].buf)
6231	goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6232	if (cm->frame_refs[2].buf)
6233	altref_picnum = cm->frame_refs[2].buf->decode_idx;
6234
6235	lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6236	(lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6237	goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6238	(goldenref_picnum - curr_picnum) :
6239	(curr_picnum - goldenref_picnum);
6240	altref_delta_picnum =
6241	(altref_picnum >= curr_picnum) ?
6242	(altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6243
6244	lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6245	goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6246	altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6247
6248	if (debug & VP9_DEBUG_CACHE)
6249	pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6250	__func__, lastref_inref, goldenref_inref, altref_inref);
6251
6252	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6253
6254	is_inter = ((pbi->common.frame_type != KEY_FRAME)
6255	&& (!pbi->common.intra_only)) ? 1 : 0;
6256
6257	if (!is_inter) { /* I-PIC */
6258	/* remove reset -- disables clock */
6259	WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6260	return;
6261	}
6262
6263	if (!pbi->m_ins_flag)
6264	dump_hit_rate(pbi);
6265
6266	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6267	lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6268	goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6269	altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6270
6271	if (debug & VP9_DEBUG_CACHE)
6272	pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6273	lastcanvas, goldencanvas, altrefcanvas);
6274
6275	altref_inref = ((altref_inref == 1) &&
6276	(altrefcanvas != (goldenref_inref
6277	? goldencanvas : 0xffffffff)) &&
6278	(altrefcanvas != (lastref_inref ?
6279	lastcanvas : 0xffffffff))) ? 1 : 0;
6280	goldenref_inref = ((goldenref_inref == 1) &&
6281	(goldencanvas != (lastref_inref ?
6282	lastcanvas : 0xffffffff))) ? 1 : 0;
6283	if (debug & VP9_DEBUG_CACHE)
6284	pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6285	lastref_inref, goldenref_inref, altref_inref);
6286
6287	altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6288	goldenref_delta_picnum = goldenref_inref ?
6289	goldenref_delta_picnum : 0x7fffffff;
6290	lastref_delta_picnum = lastref_inref ?
6291	lastref_delta_picnum : 0x7fffffff;
6292	if (debug & VP9_DEBUG_CACHE)
6293	pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6294	lastref_delta_picnum, goldenref_delta_picnum,
6295	altref_delta_picnum);
6296	/*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6297
6298	refcanvas_array[0] = lastcanvas;
6299	refcanvas_array[1] = goldencanvas;
6300	refcanvas_array[2] = altrefcanvas;
6301
6302	deltapicnum_array[0] = lastref_delta_picnum;
6303	deltapicnum_array[1] = goldenref_delta_picnum;
6304	deltapicnum_array[2] = altref_delta_picnum;
6305
6306	/* sort0 : 2-to-1 */
6307	if (deltapicnum_array[2] < deltapicnum_array[1]) {
6308	utmp = refcanvas_array[2];
6309	refcanvas_array[2] = refcanvas_array[1];
6310	refcanvas_array[1] = utmp;
6311	tmp = deltapicnum_array[2];
6312	deltapicnum_array[2] = deltapicnum_array[1];
6313	deltapicnum_array[1] = tmp;
6314	}
6315	/* sort1 : 1-to-0 */
6316	if (deltapicnum_array[1] < deltapicnum_array[0]) {
6317	utmp = refcanvas_array[1];
6318	refcanvas_array[1] = refcanvas_array[0];
6319	refcanvas_array[0] = utmp;
6320	tmp = deltapicnum_array[1];
6321	deltapicnum_array[1] = deltapicnum_array[0];
6322	deltapicnum_array[0] = tmp;
6323	}
6324	/* sort2 : 2-to-1 */
6325	if (deltapicnum_array[2] < deltapicnum_array[1]) {
6326	utmp = refcanvas_array[2]; refcanvas_array[2] =
6327	refcanvas_array[1]; refcanvas_array[1] = utmp;
6328	tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6329	deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6330	}
6331	if (mcrcc_cache_alg_flag ==
6332	THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6333	/* lowest delta_picnum */
6334	rdata32 = refcanvas_array[0];
6335	rdata32 = rdata32 & 0xffff;
6336	rdata32 = rdata32 | (rdata32 << 16);
6337	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6338
6339	/* 2nd-lowest delta_picnum */
6340	rdata32 = refcanvas_array[1];
6341	rdata32 = rdata32 & 0xffff;
6342	rdata32 = rdata32 | (rdata32 << 16);
6343	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6344	} else {
6345	/* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6346	WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6347	(0 << 8) | (1<<1) | 0);
6348	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6349	rdata32 = rdata32 & 0xffff;
6350	rdata32 = rdata32 | (rdata32 << 16);
6351	WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6352
6353	/* Programme canvas1 */
6354	rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6355	rdata32 = rdata32 & 0xffff;
6356	rdata32 = rdata32 | (rdata32 << 16);
6357	WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6358	}
6359
6360	WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6361	return;
6362	}
6363
6364	#endif
6365
6366
6367	static void free_lf_buf(struct VP9Decoder_s *pbi)
6368	{
6369	if (pbi->lfi)
6370	vfree(pbi->lfi);
6371	if (pbi->lf)
6372	vfree(pbi->lf);
6373	if (pbi->seg_4lf)
6374	vfree(pbi->seg_4lf);
6375	pbi->lfi = NULL;
6376	pbi->lf = NULL;
6377	pbi->seg_4lf = NULL;
6378	}
6379
6380	static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6381	{
6382	pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6383	pbi->lf = vmalloc(sizeof(struct loopfilter));
6384	pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6385	if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6386	free_lf_buf(pbi);
6387	pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6388	return -1;
6389	}
6390	return 0;
6391	}
6392
6393	static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6394	{
6395	pbi->rpm_ptr = NULL;
6396	pbi->lmem_ptr = NULL;
6397	if (pbi->rpm_addr) {
6398	dma_free_coherent(amports_get_dma_device(),
6399	RPM_BUF_SIZE,
6400	pbi->rpm_addr,
6401	pbi->rpm_phy_addr);
6402	pbi->rpm_addr = NULL;
6403	}
6404	if (pbi->lmem_addr) {
6405	if (pbi->lmem_phy_addr)
6406	dma_free_coherent(amports_get_dma_device(),
6407	LMEM_BUF_SIZE, pbi->lmem_addr,
6408	pbi->lmem_phy_addr);
6409	pbi->lmem_addr = NULL;
6410	}
6411	if (pbi->prob_buffer_addr) {
6412	if (pbi->prob_buffer_phy_addr)
6413	dma_free_coherent(amports_get_dma_device(),
6414	PROB_BUF_SIZE, pbi->prob_buffer_addr,
6415	pbi->prob_buffer_phy_addr);
6416
6417	pbi->prob_buffer_addr = NULL;
6418	}
6419	if (pbi->count_buffer_addr) {
6420	if (pbi->count_buffer_phy_addr)
6421	dma_free_coherent(amports_get_dma_device(),
6422	COUNT_BUF_SIZE, pbi->count_buffer_addr,
6423	pbi->count_buffer_phy_addr);
6424
6425	pbi->count_buffer_addr = NULL;
6426	}
6427	if (pbi->mmu_enable) {
6428	u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6429	if (pbi->frame_mmu_map_addr) {
6430	if (pbi->frame_mmu_map_phy_addr)
6431	dma_free_coherent(amports_get_dma_device(),
6432	mmu_map_size,
6433	pbi->frame_mmu_map_addr,
6434	pbi->frame_mmu_map_phy_addr);
6435	pbi->frame_mmu_map_addr = NULL;
6436	}
6437	}
6438	#ifdef SUPPORT_FB_DECODING
6439	if (pbi->stage_mmu_map_addr) {
6440	if (pbi->stage_mmu_map_phy_addr)
6441	dma_free_coherent(amports_get_dma_device(),
6442	STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6443	pbi->stage_mmu_map_addr,
6444	pbi->stage_mmu_map_phy_addr);
6445	pbi->stage_mmu_map_addr = NULL;
6446	}
6447
6448	uninit_stage_buf(pbi);
6449	#endif
6450
6451	#ifdef VP9_LPF_LVL_UPDATE
6452	free_lf_buf(pbi);
6453	#endif
6454	if (pbi->gvs)
6455	vfree(pbi->gvs);
6456	pbi->gvs = NULL;
6457	}
6458
6459	static int vp9_local_init(struct VP9Decoder_s *pbi)
6460	{
6461	int ret = -1;
6462	/*int losless_comp_header_size, losless_comp_body_size;*/
6463
6464	struct BuffInfo_s *cur_buf_info = NULL;
6465
6466	memset(&pbi->param, 0, sizeof(union param_u));
6467	memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6468	#ifdef MULTI_INSTANCE_SUPPORT
6469	cur_buf_info = &pbi->work_space_buf_store;
6470
6471	if (vdec_is_support_4k()) {
6472	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6473	memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6474	sizeof(struct BuffInfo_s));
6475	} else
6476	memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6477	sizeof(struct BuffInfo_s));
6478	} else
6479	memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6480	sizeof(struct BuffInfo_s));
6481
6482	cur_buf_info->start_adr = pbi->buf_start;
6483	if (!pbi->mmu_enable)
6484	pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6485
6486	#else
6487	/*! MULTI_INSTANCE_SUPPORT*/
6488	if (vdec_is_support_4k()) {
6489	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6490	cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6491	else
6492	cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6493	} else
6494	cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6495
6496	#endif
6497
6498	init_buff_spec(pbi, cur_buf_info);
6499	vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6500
6501	if (!vdec_is_support_4k()
6502	&& (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6503	buf_alloc_width = 1920;
6504	buf_alloc_height = 1088;
6505	if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6506	pbi->max_pic_w = 1920;
6507	pbi->max_pic_h = 1088;
6508	}
6509	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6510	buf_alloc_width = 8192;
6511	buf_alloc_height = 4608;
6512	}
6513	pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6514	(buf_alloc_width ? buf_alloc_width :
6515	(pbi->vvp9_amstream_dec_info.width ?
6516	pbi->vvp9_amstream_dec_info.width :
6517	pbi->work_space_buf->max_width));
6518	pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6519	(buf_alloc_height ? buf_alloc_height :
6520	(pbi->vvp9_amstream_dec_info.height ?
6521	pbi->vvp9_amstream_dec_info.height :
6522	pbi->work_space_buf->max_height));
6523
6524	/* video is not support unaligned with 64 in tl1
6525	** vdec canvas mode will be linear when dump yuv is set
6526	*/
6527	if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6528	(pbi->double_write_mode != 0) &&
6529	(((pbi->max_pic_w % 64) != 0) ||
6530	(pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6531	if (hw_to_vdec(pbi)->canvas_mode !=
6532	CANVAS_BLKMODE_LINEAR)
6533	pbi->mem_map_mode = 2;
6534	else {
6535	pbi->mem_map_mode = 0;
6536	pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6537	}
6538	}
6539
6540	#ifndef MV_USE_FIXED_BUF
6541	if (init_mv_buf_list(pbi) < 0) {
6542	pr_err("%s: init_mv_buf_list fail\n", __func__);
6543	return -1;
6544	}
6545	#endif
6546	if (pbi->save_buffer_mode)
6547	pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6548	else {
6549	if (pbi->is_used_v4l)
6550	pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6551	else
6552	pbi->used_buf_num = max_buf_num;
6553	}
6554
6555	if (pbi->used_buf_num > MAX_BUF_NUM)
6556	pbi->used_buf_num = MAX_BUF_NUM;
6557	if (pbi->used_buf_num > FRAME_BUFFERS)
6558	pbi->used_buf_num = FRAME_BUFFERS;
6559
6560	pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6561	& 0x40) >> 6;
6562
6563	if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6564	pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6565	RPM_BUF_SIZE,
6566	&pbi->rpm_phy_addr, GFP_KERNEL);
6567	if (pbi->rpm_addr == NULL) {
6568	pr_err("%s: failed to alloc rpm buffer\n", __func__);
6569	return -1;
6570	}
6571
6572	pbi->rpm_ptr = pbi->rpm_addr;
6573	}
6574
6575	pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6576	LMEM_BUF_SIZE,
6577	&pbi->lmem_phy_addr, GFP_KERNEL);
6578	if (pbi->lmem_addr == NULL) {
6579	pr_err("%s: failed to alloc lmem buffer\n", __func__);
6580	return -1;
6581	}
6582	pbi->lmem_ptr = pbi->lmem_addr;
6583
6584	pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6585	PROB_BUF_SIZE,
6586	&pbi->prob_buffer_phy_addr, GFP_KERNEL);
6587	if (pbi->prob_buffer_addr == NULL) {
6588	pr_err("%s: failed to alloc prob_buffer\n", __func__);
6589	return -1;
6590	}
6591	memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6592	pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6593	COUNT_BUF_SIZE,
6594	&pbi->count_buffer_phy_addr, GFP_KERNEL);
6595	if (pbi->count_buffer_addr == NULL) {
6596	pr_err("%s: failed to alloc count_buffer\n", __func__);
6597	return -1;
6598	}
6599	memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6600
6601	if (pbi->mmu_enable) {
6602	u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6603	pbi->frame_mmu_map_addr =
6604	dma_alloc_coherent(amports_get_dma_device(),
6605	mmu_map_size,
6606	&pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6607	if (pbi->frame_mmu_map_addr == NULL) {
6608	pr_err("%s: failed to alloc count_buffer\n", __func__);
6609	return -1;
6610	}
6611	memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6612	}
6613	#ifdef SUPPORT_FB_DECODING
6614	if (pbi->m_ins_flag && stage_buf_num > 0) {
6615	pbi->stage_mmu_map_addr =
6616	dma_alloc_coherent(amports_get_dma_device(),
6617	STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6618	&pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6619	if (pbi->stage_mmu_map_addr == NULL) {
6620	pr_err("%s: failed to alloc count_buffer\n", __func__);
6621	return -1;
6622	}
6623	memset(pbi->stage_mmu_map_addr,
6624	0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6625
6626	init_stage_buf(pbi);
6627	}
6628	#endif
6629
6630	ret = 0;
6631	return ret;
6632	}
6633
6634	/********************************************
6635	* Mailbox command
6636	********************************************/
6637	#define CMD_FINISHED 0
6638	#define CMD_ALLOC_VIEW 1
6639	#define CMD_FRAME_DISPLAY 3
6640	#define CMD_DEBUG 10
6641
6642
6643	#define DECODE_BUFFER_NUM_MAX 32
6644	#define DISPLAY_BUFFER_NUM 6
6645
6646	#define video_domain_addr(adr) (adr&0x7fffffff)
6647	#define DECODER_WORK_SPACE_SIZE 0x800000
6648
6649	#define spec2canvas(x) \
6650	(((x)->uv_canvas_index << 16) | \
6651	((x)->uv_canvas_index << 8) | \
6652	((x)->y_canvas_index << 0))
6653
6654
6655	static void set_canvas(struct VP9Decoder_s *pbi,
6656	struct PIC_BUFFER_CONFIG_s *pic_config)
6657	{
6658	struct vdec_s *vdec = hw_to_vdec(pbi);
6659	int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6660	int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6661	int blkmode = pbi->mem_map_mode;
6662	/*CANVAS_BLKMODE_64X32*/
6663	if (pic_config->double_write_mode) {
6664	canvas_w = pic_config->y_crop_width /
6665	get_double_write_ratio(pbi,
6666	pic_config->double_write_mode);
6667	canvas_h = pic_config->y_crop_height /
6668	get_double_write_ratio(pbi,
6669	pic_config->double_write_mode);
6670
6671	if (pbi->mem_map_mode == 0)
6672	canvas_w = ALIGN(canvas_w, 32);
6673	else
6674	canvas_w = ALIGN(canvas_w, 64);
6675	canvas_h = ALIGN(canvas_h, 32);
6676
6677	if (vdec->parallel_dec == 1) {
6678	if (pic_config->y_canvas_index == -1)
6679	pic_config->y_canvas_index =
6680	vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6681	if (pic_config->uv_canvas_index == -1)
6682	pic_config->uv_canvas_index =
6683	vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6684	} else {
6685	pic_config->y_canvas_index = 128 + pic_config->index * 2;
6686	pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6687	}
6688
6689	canvas_config_ex(pic_config->y_canvas_index,
6690	pic_config->dw_y_adr, canvas_w, canvas_h,
6691	CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6692	canvas_config_ex(pic_config->uv_canvas_index,
6693	pic_config->dw_u_v_adr, canvas_w, canvas_h,
6694	CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6695
6696	#ifdef MULTI_INSTANCE_SUPPORT
6697	pic_config->canvas_config[0].phy_addr =
6698	pic_config->dw_y_adr;
6699	pic_config->canvas_config[0].width =
6700	canvas_w;
6701	pic_config->canvas_config[0].height =
6702	canvas_h;
6703	pic_config->canvas_config[0].block_mode =
6704	blkmode;
6705	pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6706
6707	pic_config->canvas_config[1].phy_addr =
6708	pic_config->dw_u_v_adr;
6709	pic_config->canvas_config[1].width =
6710	canvas_w;
6711	pic_config->canvas_config[1].height =
6712	canvas_h;
6713	pic_config->canvas_config[1].block_mode =
6714	blkmode;
6715	pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6716	#endif
6717	}
6718	}
6719
6720
6721	static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6722	{
6723	unsigned int ar;
6724	vf->duration = pbi->frame_dur;
6725	vf->duration_pulldown = 0;
6726	vf->flag = 0;
6727	vf->prop.master_display_colour = pbi->vf_dp;
6728	vf->signal_type = pbi->video_signal_type;
6729	if (vf->compWidth && vf->compHeight)
6730	pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6731	ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6732	vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6733
6734	if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6735	struct aml_vdec_hdr_infos hdr;
6736	struct aml_vcodec_ctx *ctx =
6737	(struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6738
6739	memset(&hdr, 0, sizeof(hdr));
6740	hdr.signal_type = vf->signal_type;
6741	hdr.color_parms = pbi->vf_dp;
6742	vdec_v4l_set_hdr_infos(ctx, &hdr);
6743	}
6744	}
6745
6746	static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6747	{
6748	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6749
6750	states->vf_pool_size = VF_POOL_SIZE;
6751	states->buf_free_num = kfifo_len(&pbi->newframe_q);
6752	states->buf_avail_num = kfifo_len(&pbi->display_q);
6753
6754	if (step == 2)
6755	states->buf_avail_num = 0;
6756	return 0;
6757	}
6758
6759	static struct vframe_s *vvp9_vf_peek(void *op_arg)
6760	{
6761	struct vframe_s *vf[2] = {0, 0};
6762	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6763
6764	if (step == 2)
6765	return NULL;
6766
6767	if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6768	if (vf[1]) {
6769	vf[0]->next_vf_pts_valid = true;
6770	vf[0]->next_vf_pts = vf[1]->pts;
6771	} else
6772	vf[0]->next_vf_pts_valid = false;
6773	return vf[0];
6774	}
6775
6776	return NULL;
6777	}
6778
6779	static struct vframe_s *vvp9_vf_get(void *op_arg)
6780	{
6781	struct vframe_s *vf;
6782	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6783
6784	if (step == 2)
6785	return NULL;
6786	else if (step == 1)
6787	step = 2;
6788
6789	if (kfifo_get(&pbi->display_q, &vf)) {
6790	struct vframe_s *next_vf;
6791	uint8_t index = vf->index & 0xff;
6792	if (index < pbi->used_buf_num ||
6793	(vf->type & VIDTYPE_V4L_EOS)) {
6794	pbi->vf_get_count++;
6795	if (debug & VP9_DEBUG_BUFMGR)
6796	pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6797	__func__, vf->type,
6798	vf->width, vf->height,
6799	vf->pts,
6800	vf->pts_us64);
6801
6802	if (kfifo_peek(&pbi->display_q, &next_vf)) {
6803	vf->next_vf_pts_valid = true;
6804	vf->next_vf_pts = next_vf->pts;
6805	} else
6806	vf->next_vf_pts_valid = false;
6807
6808	return vf;
6809	}
6810	}
6811	return NULL;
6812	}
6813
6814	static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6815	{
6816	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6817	uint8_t index = vf->index & 0xff;
6818
6819	if (vf == (&pbi->vframe_dummy))
6820	return;
6821
6822	kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6823	pbi->vf_put_count++;
6824	if (index < pbi->used_buf_num) {
6825	struct VP9_Common_s *cm = &pbi->common;
6826	struct BufferPool_s *pool = cm->buffer_pool;
6827	unsigned long flags;
6828
6829	lock_buffer_pool(pool, flags);
6830	if (pool->frame_bufs[index].buf.vf_ref > 0)
6831	pool->frame_bufs[index].buf.vf_ref--;
6832
6833	if (pbi->is_used_v4l)
6834	pool->frame_bufs[index].buf.vframe_bound = true;
6835
6836	if (pbi->wait_buf)
6837	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6838	0x1);
6839	pbi->last_put_idx = index;
6840	pbi->new_frame_displayed++;
6841	unlock_buffer_pool(pool, flags);
6842	#ifdef SUPPORT_FB_DECODING
6843	if (pbi->used_stage_buf_num > 0 &&
6844	pbi->back_not_run_ready)
6845	trigger_schedule(pbi);
6846	#endif
6847	}
6848
6849	}
6850
6851	static int vvp9_event_cb(int type, void *data, void *private_data)
6852	{
6853	if (type & VFRAME_EVENT_RECEIVER_RESET) {
6854	#if 0
6855	unsigned long flags;
6856
6857	amhevc_stop();
6858	#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6859	vf_light_unreg_provider(&vvp9_vf_prov);
6860	#endif
6861	spin_lock_irqsave(&pbi->lock, flags);
6862	vvp9_local_init();
6863	vvp9_prot_init();
6864	spin_unlock_irqrestore(&pbi->lock, flags);
6865	#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6866	vf_reg_provider(&vvp9_vf_prov);
6867	#endif
6868	amhevc_start();
6869	#endif
6870	}
6871
6872	return 0;
6873	}
6874
6875	void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6876	{
6877	struct VP9_Common_s *cm = &pbi->common;
6878
6879	cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6880
6881	if (debug & VP9_DEBUG_BUFMGR_MORE)
6882	pr_info("%s index = %d new vf_ref = %d\r\n",
6883	__func__, index,
6884	cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6885	}
6886
6887	static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6888	{
6889	u32 old_duration, pts_duration = 0;
6890	u32 pts = vf->pts;
6891
6892	if (pbi->get_frame_dur == true)
6893	return true;
6894
6895	pbi->frame_cnt_window++;
6896	if (!(pbi->vp9_first_pts_ready == 1)) {
6897	if (valid) {
6898	pbi->pts1 = pts;
6899	pbi->frame_cnt_window = 0;
6900	pbi->duration_from_pts_done = 0;
6901	pbi->vp9_first_pts_ready = 1;
6902	} else {
6903	return false;
6904	}
6905	} else {
6906	if (pts < pbi->pts1) {
6907	if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6908	pbi->pts1 = pts;
6909	pbi->frame_cnt_window = 0;
6910	}
6911	}
6912
6913	if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6914	(pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6915	old_duration = pbi->frame_dur;
6916	pbi->pts2 = pts;
6917	pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6918	(pbi->frame_cnt_window * 15));
6919
6920	if (close_to(pts_duration, old_duration, 2000)) {
6921	pbi->frame_dur = pts_duration;
6922	if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6923	pr_info("use calc duration %d\n", pts_duration);
6924	}
6925
6926	if (pbi->duration_from_pts_done == 0) {
6927	if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6928	pbi->duration_from_pts_done = 1;
6929	} else {
6930	if (!close_to(pts_duration,
6931	old_duration, 1000) &&
6932	!close_to(pts_duration,
6933	pbi->frame_dur, 1000) &&
6934	close_to(pts_duration,
6935	pbi->last_duration, 200)) {
6936	/* frame_dur must
6937	* wrong,recover it.
6938	*/
6939	pbi->frame_dur = pts_duration;
6940	}
6941	pbi->pts1 = pbi->pts2;
6942	pbi->frame_cnt_window = 0;
6943	pbi->duration_from_pts_done = 0;
6944	}
6945	}
6946	pbi->last_duration = pts_duration;
6947	}
6948	}
6949	return true;
6950	}
6951
6952	static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6953	struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6954	{
6955	if (pic->index < 0) {
6956	vf->mem_handle = NULL;
6957	vf->mem_head_handle = NULL;
6958	} else if (vf->type & VIDTYPE_SCATTER) {
6959	vf->mem_handle =
6960	decoder_mmu_box_get_mem_handle(
6961	pbi->mmu_box, pic->index);
6962	vf->mem_head_handle =
6963	decoder_bmmu_box_get_mem_handle(
6964	pbi->bmmu_box,
6965	HEADER_BUFFER_IDX(pic->BUF_index));
6966	} else {
6967	vf->mem_handle =
6968	decoder_bmmu_box_get_mem_handle(
6969	pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
6970	vf->mem_head_handle = NULL;
6971	/*vf->mem_head_handle =
6972	*decoder_bmmu_box_get_mem_handle(
6973	*hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
6974	*/
6975	}
6976	}
6977
6978	static int prepare_display_buf(struct VP9Decoder_s *pbi,
6979	struct PIC_BUFFER_CONFIG_s *pic_config)
6980	{
6981	struct vframe_s *vf = NULL;
6982	int stream_offset = pic_config->stream_offset;
6983	unsigned short slice_type = pic_config->slice_type;
6984	u32 pts_valid = 0, pts_us64_valid = 0;
6985	u32 pts_save;
6986	u64 pts_us64_save;
6987	u32 frame_size;
6988
6989	if (debug & VP9_DEBUG_BUFMGR)
6990	pr_info("%s index = %d\r\n", __func__, pic_config->index);
6991	if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
6992	pr_info("fatal error, no available buffer slot.");
6993	return -1;
6994	}
6995
6996	if (pic_config->double_write_mode)
6997	set_canvas(pbi, pic_config);
6998
6999	display_frame_count[pbi->index]++;
7000	if (vf) {
7001	if (pbi->is_used_v4l) {
7002	vf->v4l_mem_handle
7003	= pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7004	if (pbi->mmu_enable) {
7005	vf->mm_box.bmmu_box = pbi->bmmu_box;
7006	vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7007	vf->mm_box.mmu_box = pbi->mmu_box;
7008	vf->mm_box.mmu_idx = pic_config->index;
7009	}
7010	}
7011
7012	#ifdef MULTI_INSTANCE_SUPPORT
7013	if (vdec_frame_based(hw_to_vdec(pbi))) {
7014	vf->pts = pic_config->pts;
7015	vf->pts_us64 = pic_config->pts64;
7016	vf->timestamp = pic_config->timestamp;
7017	if (vf->pts != 0 || vf->pts_us64 != 0) {
7018	pts_valid = 1;
7019	pts_us64_valid = 1;
7020	} else {
7021	pts_valid = 0;
7022	pts_us64_valid = 0;
7023	}
7024	} else
7025	#endif
7026	/* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7027	* stream_offset, &vf->pts, 0) != 0) {
7028	*/
7029	if (pts_lookup_offset_us64
7030	(PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7031	&frame_size, 0,
7032	&vf->pts_us64) != 0) {
7033	#ifdef DEBUG_PTS
7034	pbi->pts_missed++;
7035	#endif
7036	vf->pts = 0;
7037	vf->pts_us64 = 0;
7038	pts_valid = 0;
7039	pts_us64_valid = 0;
7040	} else {
7041	#ifdef DEBUG_PTS
7042	pbi->pts_hit++;
7043	#endif
7044	pts_valid = 1;
7045	pts_us64_valid = 1;
7046	}
7047
7048	fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7049
7050	pts_save = vf->pts;
7051	pts_us64_save = vf->pts_us64;
7052	if (pbi->pts_unstable) {
7053	frame_duration_adapt(pbi, vf, pts_valid);
7054	if (pbi->duration_from_pts_done) {
7055	pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7056	} else {
7057	if (pts_valid || pts_us64_valid)
7058	pbi->pts_mode = PTS_NORMAL;
7059	}
7060	}
7061
7062	if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7063	&& pbi->get_frame_dur) {
7064	int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7065
7066	if (pts_diff < 0) {
7067	pbi->pts_mode_switching_count++;
7068	pbi->pts_mode_recovery_count = 0;
7069
7070	if (pbi->pts_mode_switching_count >=
7071	PTS_MODE_SWITCHING_THRESHOLD) {
7072	pbi->pts_mode =
7073	PTS_NONE_REF_USE_DURATION;
7074	pr_info
7075	("HEVC: switch to n_d mode.\n");
7076	}
7077
7078	} else {
7079	int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7080
7081	pbi->pts_mode_recovery_count++;
7082	if (pbi->pts_mode_recovery_count > p) {
7083	pbi->pts_mode_switching_count = 0;
7084	pbi->pts_mode_recovery_count = 0;
7085	}
7086	}
7087	}
7088
7089	if (vf->pts != 0)
7090	pbi->last_lookup_pts = vf->pts;
7091
7092	if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7093	&& (slice_type != KEY_FRAME))
7094	vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7095	pbi->last_pts = vf->pts;
7096
7097	if (vf->pts_us64 != 0)
7098	pbi->last_lookup_pts_us64 = vf->pts_us64;
7099
7100	if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7101	&& (slice_type != KEY_FRAME)) {
7102	vf->pts_us64 =
7103	pbi->last_pts_us64 +
7104	(DUR2PTS(pbi->frame_dur) * 100 / 9);
7105	}
7106	pbi->last_pts_us64 = vf->pts_us64;
7107	if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7108	pr_info
7109	("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7110	pbi->pts_mode, pbi->frame_dur, vf->pts,
7111	vf->pts_us64, pts_save, pts_us64_save);
7112	}
7113
7114	if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7115	vf->disp_pts = vf->pts;
7116	vf->disp_pts_us64 = vf->pts_us64;
7117	vf->pts = pts_save;
7118	vf->pts_us64 = pts_us64_save;
7119	} else {
7120	vf->disp_pts = 0;
7121	vf->disp_pts_us64 = 0;
7122	}
7123
7124	vf->index = 0xff00 | pic_config->index;
7125
7126	if (pic_config->double_write_mode & 0x10) {
7127	/* double write only */
7128	vf->compBodyAddr = 0;
7129	vf->compHeadAddr = 0;
7130	} else {
7131	if (pbi->mmu_enable) {
7132	vf->compBodyAddr = 0;
7133	vf->compHeadAddr = pic_config->header_adr;
7134	} else {
7135	/*vf->compBodyAddr = pic_config->mc_y_adr;
7136	*vf->compHeadAddr = pic_config->mc_y_adr +
7137	*pic_config->comp_body_size; */
7138	/*head adr*/
7139	}
7140	vf->canvas0Addr = vf->canvas1Addr = 0;
7141	}
7142	if (pic_config->double_write_mode) {
7143	vf->type = VIDTYPE_PROGRESSIVE |
7144	VIDTYPE_VIU_FIELD;
7145	vf->type |= VIDTYPE_VIU_NV21;
7146	if ((pic_config->double_write_mode == 3) &&
7147	(!IS_8K_SIZE(pic_config->y_crop_width,
7148	pic_config->y_crop_height))) {
7149	vf->type |= VIDTYPE_COMPRESS;
7150	if (pbi->mmu_enable)
7151	vf->type |= VIDTYPE_SCATTER;
7152	}
7153	#ifdef MULTI_INSTANCE_SUPPORT
7154	if (pbi->m_ins_flag) {
7155	vf->canvas0Addr = vf->canvas1Addr = -1;
7156	vf->plane_num = 2;
7157	vf->canvas0_config[0] =
7158	pic_config->canvas_config[0];
7159	vf->canvas0_config[1] =
7160	pic_config->canvas_config[1];
7161	vf->canvas1_config[0] =
7162	pic_config->canvas_config[0];
7163	vf->canvas1_config[1] =
7164	pic_config->canvas_config[1];
7165
7166	} else
7167	#endif
7168	vf->canvas0Addr = vf->canvas1Addr =
7169	spec2canvas(pic_config);
7170	} else {
7171	vf->canvas0Addr = vf->canvas1Addr = 0;
7172	vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7173	if (pbi->mmu_enable)
7174	vf->type |= VIDTYPE_SCATTER;
7175	}
7176
7177	switch (pic_config->bit_depth) {
7178	case VPX_BITS_8:
7179	vf->bitdepth = BITDEPTH_Y8 |
7180	BITDEPTH_U8 | BITDEPTH_V8;
7181	break;
7182	case VPX_BITS_10:
7183	case VPX_BITS_12:
7184	vf->bitdepth = BITDEPTH_Y10 |
7185	BITDEPTH_U10 | BITDEPTH_V10;
7186	break;
7187	default:
7188	vf->bitdepth = BITDEPTH_Y10 |
7189	BITDEPTH_U10 | BITDEPTH_V10;
7190	break;
7191	}
7192	if ((vf->type & VIDTYPE_COMPRESS) == 0)
7193	vf->bitdepth =
7194	BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7195	if (pic_config->bit_depth == VPX_BITS_8)
7196	vf->bitdepth |= BITDEPTH_SAVING_MODE;
7197
7198	/* if((vf->width!=pic_config->width)|
7199	* (vf->height!=pic_config->height))
7200	*/
7201	/* pr_info("aaa: %d/%d, %d/%d\n",
7202	vf->width,vf->height, pic_config->width,
7203	pic_config->height); */
7204	vf->width = pic_config->y_crop_width /
7205	get_double_write_ratio(pbi,
7206	pic_config->double_write_mode);
7207	vf->height = pic_config->y_crop_height /
7208	get_double_write_ratio(pbi,
7209	pic_config->double_write_mode);
7210	if (force_w_h != 0) {
7211	vf->width = (force_w_h >> 16) & 0xffff;
7212	vf->height = force_w_h & 0xffff;
7213	}
7214	vf->compWidth = pic_config->y_crop_width;
7215	vf->compHeight = pic_config->y_crop_height;
7216	set_frame_info(pbi, vf);
7217	if (force_fps & 0x100) {
7218	u32 rate = force_fps & 0xff;
7219
7220	if (rate)
7221	vf->duration = 96000/rate;
7222	else
7223	vf->duration = 0;
7224	}
7225	update_vf_memhandle(pbi, vf, pic_config);
7226	if (!(pic_config->y_crop_width == 196
7227	&& pic_config->y_crop_height == 196
7228	&& (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7229	&& (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7230	inc_vf_ref(pbi, pic_config->index);
7231	decoder_do_frame_check(hw_to_vdec(pbi), vf);
7232	kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7233	ATRACE_COUNTER(MODULE_NAME, vf->pts);
7234	pbi->vf_pre_count++;
7235	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7236	/*count info*/
7237	gvs->frame_dur = pbi->frame_dur;
7238	vdec_count_info(gvs, 0, stream_offset);
7239	#endif
7240	hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
7241	if (without_display_mode == 0) {
7242	vf_notify_receiver(pbi->provider_name,
7243	VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7244	} else
7245	vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7246	} else {
7247	pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7248	hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7249	pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7250	__func__, __LINE__, vf->width,
7251	vf->height, pbi->stat);
7252	}
7253	}
7254
7255	return 0;
7256	}
7257
7258	static int notify_v4l_eos(struct vdec_s *vdec)
7259	{
7260	struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7261	struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7262	struct vframe_s *vf = &hw->vframe_dummy;
7263	struct vdec_v4l2_buffer *fb = NULL;
7264	int index = INVALID_IDX;
7265	ulong expires;
7266
7267	if (hw->is_used_v4l && hw->eos) {
7268	expires = jiffies + msecs_to_jiffies(2000);
7269	while (INVALID_IDX == (index = get_free_fb(hw))) {
7270	if (time_after(jiffies, expires))
7271	break;
7272	}
7273
7274	if (index == INVALID_IDX) {
7275	if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7276	pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7277	return -1;
7278	}
7279	}
7280
7281	vf->type |= VIDTYPE_V4L_EOS;
7282	vf->timestamp = ULONG_MAX;
7283	vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7284	vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7285	hw->m_BUF[index].v4l_ref_buf_addr;
7286
7287	kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7288	vf_notify_receiver(vdec->vf_provider_name,
7289	VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7290
7291	pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7292	}
7293
7294	return 0;
7295	}
7296
7297	static void get_rpm_param(union param_u *params)
7298	{
7299	int i;
7300	unsigned int data32;
7301
7302	if (debug & VP9_DEBUG_BUFMGR)
7303	pr_info("enter %s\r\n", __func__);
7304	for (i = 0; i < 128; i++) {
7305	do {
7306	data32 = READ_VREG(RPM_CMD_REG);
7307	/*pr_info("%x\n", data32);*/
7308	} while ((data32 & 0x10000) == 0);
7309	params->l.data[i] = data32&0xffff;
7310	/*pr_info("%x\n", data32);*/
7311	WRITE_VREG(RPM_CMD_REG, 0);
7312	}
7313	if (debug & VP9_DEBUG_BUFMGR)
7314	pr_info("leave %s\r\n", __func__);
7315	}
7316	static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7317	{
7318	int i;
7319
7320	if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7321	return;
7322	pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7323	for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7324	pr_info("%04x ", vp9_param.l.data[i]);
7325	if (((i + 1) & 0xf) == 0)
7326	pr_info("\n");
7327	}
7328	pr_info("=============param==========\r\n");
7329	pr_info("profile %x\r\n", vp9_param.p.profile);
7330	pr_info("show_existing_frame %x\r\n",
7331	vp9_param.p.show_existing_frame);
7332	pr_info("frame_to_show_idx %x\r\n",
7333	vp9_param.p.frame_to_show_idx);
7334	pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7335	pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7336	pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7337	vp9_param.p.error_resilient_mode);
7338	pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7339	pr_info("display_size_present %x\r\n",
7340	vp9_param.p.display_size_present);
7341	pr_info("reset_frame_context %x\r\n",
7342	vp9_param.p.reset_frame_context);
7343	pr_info("refresh_frame_flags %x\r\n",
7344	vp9_param.p.refresh_frame_flags);
7345	pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7346	pr_info("width %x\r\n", vp9_param.p.width);
7347	pr_info("height %x\r\n", vp9_param.p.height);
7348	pr_info("display_width %x\r\n", vp9_param.p.display_width);
7349	pr_info("display_height %x\r\n", vp9_param.p.display_height);
7350	pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7351	pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7352	if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7353	return;
7354	pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7355	vp9_param.p.mode_ref_delta_enabled);
7356	pr_info("sharpness_level: 0x%x\r\n",
7357	vp9_param.p.sharpness_level);
7358	pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7359	vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7360	vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7361	pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7362	vp9_param.p.mode_deltas[1]);
7363	pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7364	pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7365	pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7366	pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7367	(vp9_param.p.seg_lf_info[0]>>15 & 1),
7368	(vp9_param.p.seg_lf_info[1]>>15 & 1),
7369	(vp9_param.p.seg_lf_info[2]>>15 & 1),
7370	(vp9_param.p.seg_lf_info[3]>>15 & 1),
7371	(vp9_param.p.seg_lf_info[4]>>15 & 1),
7372	(vp9_param.p.seg_lf_info[5]>>15 & 1),
7373	(vp9_param.p.seg_lf_info[6]>>15 & 1),
7374	(vp9_param.p.seg_lf_info[7]>>15 & 1));
7375	pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7376	(vp9_param.p.seg_lf_info[0] & 0x13f),
7377	(vp9_param.p.seg_lf_info[1] & 0x13f),
7378	(vp9_param.p.seg_lf_info[2] & 0x13f),
7379	(vp9_param.p.seg_lf_info[3] & 0x13f),
7380	(vp9_param.p.seg_lf_info[4] & 0x13f),
7381	(vp9_param.p.seg_lf_info[5] & 0x13f),
7382	(vp9_param.p.seg_lf_info[6] & 0x13f),
7383	(vp9_param.p.seg_lf_info[7] & 0x13f));
7384
7385	}
7386
7387
7388	static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7389	{
7390	struct VP9_Common_s *const cm = &pbi->common;
7391	if (pbi->double_write_mode & 0x10)
7392	return;
7393	if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7394	if (pbi->used_4k_num == -1) {
7395	pbi->used_4k_num =
7396	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7397	if (pbi->m_ins_flag)
7398	hevc_mmu_dma_check(hw_to_vdec(pbi));
7399	}
7400	decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7401	cm->cur_fb_idx_mmu, pbi->used_4k_num);
7402	cm->cur_fb_idx_mmu = INVALID_IDX;
7403	pbi->used_4k_num = -1;
7404	}
7405	}
7406
7407	#ifdef MULTI_INSTANCE_SUPPORT
7408	static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7409	{
7410	struct VP9_Common_s *const cm = &pbi->common;
7411	if (pbi->double_write_mode & 0x10)
7412	return;
7413	if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7414	decoder_mmu_box_free_idx(pbi->mmu_box,
7415	cm->cur_fb_idx_mmu);
7416
7417	cm->cur_fb_idx_mmu = INVALID_IDX;
7418	pbi->used_4k_num = -1;
7419	}
7420	}
7421	#endif
7422
7423
7424	static void dec_again_process(struct VP9Decoder_s *pbi)
7425	{
7426	amhevc_stop();
7427	pbi->dec_result = DEC_RESULT_AGAIN;
7428	if (pbi->process_state ==
7429	PROC_STATE_DECODESLICE) {
7430	pbi->process_state =
7431	PROC_STATE_SENDAGAIN;
7432	if (pbi->mmu_enable)
7433	vp9_recycle_mmu_buf(pbi);
7434	}
7435	reset_process_time(pbi);
7436	vdec_schedule_work(&pbi->work);
7437	}
7438
7439	int continue_decoding(struct VP9Decoder_s *pbi)
7440	{
7441	int ret;
7442	int i;
7443	struct VP9_Common_s *const cm = &pbi->common;
7444	debug_buffer_mgr_more(pbi);
7445
7446	bit_depth_luma = vp9_param.p.bit_depth;
7447	bit_depth_chroma = vp9_param.p.bit_depth;
7448
7449	if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7450	(get_double_write_mode(pbi) == 0x10)) {
7451	pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7452	pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7453	vp9_param.p.bit_depth);
7454	return -1;
7455	}
7456
7457	if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7458	ret = vp9_bufmgr_process(pbi, &vp9_param);
7459	if (!pbi->m_ins_flag)
7460	pbi->slice_idx++;
7461	} else {
7462	union param_u *params = &vp9_param;
7463	if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7464	ret = vp9_alloc_mmu(pbi,
7465	cm->new_fb_idx,
7466	params->p.width,
7467	params->p.height,
7468	params->p.bit_depth,
7469	pbi->frame_mmu_map_addr);
7470	if (ret >= 0)
7471	cm->cur_fb_idx_mmu = cm->new_fb_idx;
7472	else
7473	pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7474	cm->new_fb_idx,
7475	ret);
7476	} else {
7477	ret = 0;
7478	}
7479	WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7480	(params->p.height << 16) | params->p.width);
7481	}
7482	if (ret < 0) {
7483	pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7484	ret);
7485	WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7486	cm->show_frame = 0;
7487	if (pbi->mmu_enable)
7488	vp9_recycle_mmu_buf(pbi);
7489	#ifdef MULTI_INSTANCE_SUPPORT
7490	if (pbi->m_ins_flag) {
7491	pbi->dec_result = DEC_RESULT_DONE;
7492	#ifdef SUPPORT_FB_DECODING
7493	if (pbi->used_stage_buf_num == 0)
7494	#endif
7495	amhevc_stop();
7496	vdec_schedule_work(&pbi->work);
7497	}
7498	#endif
7499	return ret;
7500	} else if (ret == 0) {
7501	struct PIC_BUFFER_CONFIG_s *cur_pic_config
7502	= &cm->cur_frame->buf;
7503	cur_pic_config->decode_idx = pbi->frame_count;
7504
7505	if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7506	if (!pbi->m_ins_flag) {
7507	pbi->frame_count++;
7508	decode_frame_count[pbi->index]
7509	= pbi->frame_count;
7510	}
7511	#ifdef MULTI_INSTANCE_SUPPORT
7512	if (pbi->chunk) {
7513	cur_pic_config->pts = pbi->chunk->pts;
7514	cur_pic_config->pts64 = pbi->chunk->pts64;
7515	cur_pic_config->timestamp = pbi->chunk->timestamp;
7516	}
7517	#endif
7518	}
7519	/*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7520	config_pic_size(pbi, vp9_param.p.bit_depth);
7521
7522	if ((pbi->common.frame_type != KEY_FRAME)
7523	&& (!pbi->common.intra_only)) {
7524	config_mc_buffer(pbi, vp9_param.p.bit_depth);
7525	#ifdef SUPPORT_FB_DECODING
7526	if (pbi->used_stage_buf_num == 0)
7527	#endif
7528	config_mpred_hw(pbi);
7529	} else {
7530	#ifdef SUPPORT_FB_DECODING
7531	if (pbi->used_stage_buf_num == 0)
7532	#endif
7533	clear_mpred_hw(pbi);
7534	}
7535	#ifdef MCRCC_ENABLE
7536	if (mcrcc_cache_alg_flag)
7537	config_mcrcc_axi_hw_new(pbi);
7538	else
7539	config_mcrcc_axi_hw(pbi);
7540	#endif
7541	config_sao_hw(pbi, &vp9_param);
7542
7543	#ifdef VP9_LPF_LVL_UPDATE
7544	/*
7545	* Get loop filter related picture level parameters from Parser
7546	*/
7547	pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7548	pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7549	for (i = 0; i < 4; i++)
7550	pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7551	for (i = 0; i < 2; i++)
7552	pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7553	pbi->default_filt_lvl = vp9_param.p.filter_level;
7554	pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7555	pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7556	for (i = 0; i < MAX_SEGMENTS; i++)
7557	pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7558	0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7559	for (i = 0; i < MAX_SEGMENTS; i++)
7560	pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7561	= (vp9_param.p.seg_lf_info[i]
7562	& 0x100) ? -(vp9_param.p.seg_lf_info[i]
7563	& 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7564	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7565	/*Set pipeline mode*/
7566	uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7567	/*dblk pipeline mode=1 for performance*/
7568	if (vp9_param.p.width >= 1280)
7569	lpf_data32 |= (0x1 << 4);
7570	else
7571	lpf_data32 &= ~(0x3 << 4);
7572	WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7573	}
7574	/*
7575	* Update loop filter Thr/Lvl table for every frame
7576	*/
7577	/*pr_info
7578	("vp9_loop_filter (run before every frame decoding start)\n");*/
7579	vp9_loop_filter_frame_init(pbi->seg_4lf,
7580	pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7581	#endif
7582	/*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7583	WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7584	} else {
7585	pr_info("Skip search next start code\n");
7586	cm->prev_fb_idx = INVALID_IDX;
7587	/*skip, search next start code*/
7588	WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7589	}
7590	pbi->process_state = PROC_STATE_DECODESLICE;
7591	if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7592	if (pbi->last_put_idx < pbi->used_buf_num) {
7593	struct RefCntBuffer_s *frame_bufs =
7594	cm->buffer_pool->frame_bufs;
7595	int i = pbi->last_put_idx;
7596	/*free not used buffers.*/
7597	if ((frame_bufs[i].ref_count == 0) &&
7598	(frame_bufs[i].buf.vf_ref == 0) &&
7599	(frame_bufs[i].buf.index != -1)) {
7600	decoder_mmu_box_free_idx(pbi->mmu_box, i);
7601	}
7602	pbi->last_put_idx = -1;
7603	}
7604	}
7605	return ret;
7606	}
7607
7608	static void fill_frame_info(struct VP9Decoder_s *pbi,
7609	struct PIC_BUFFER_CONFIG_s *frame,
7610	unsigned int framesize,
7611	unsigned int pts)
7612	{
7613	struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7614
7615	if (frame->slice_type == KEY_FRAME)
7616	vframe_qos->type = 1;
7617	else if (frame->slice_type == INTER_FRAME)
7618	vframe_qos->type = 2;
7619	/*
7620	#define SHOW_QOS_INFO
7621	*/
7622	vframe_qos->size = framesize;
7623	vframe_qos->pts = pts;
7624	#ifdef SHOW_QOS_INFO
7625	vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7626	#endif
7627	vframe_qos->max_mv = frame->max_mv;
7628	vframe_qos->avg_mv = frame->avg_mv;
7629	vframe_qos->min_mv = frame->min_mv;
7630	#ifdef SHOW_QOS_INFO
7631	vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7632	vframe_qos->max_mv,
7633	vframe_qos->avg_mv,
7634	vframe_qos->min_mv);
7635	#endif
7636	vframe_qos->max_qp = frame->max_qp;
7637	vframe_qos->avg_qp = frame->avg_qp;
7638	vframe_qos->min_qp = frame->min_qp;
7639	#ifdef SHOW_QOS_INFO
7640	vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7641	vframe_qos->max_qp,
7642	vframe_qos->avg_qp,
7643	vframe_qos->min_qp);
7644	#endif
7645	vframe_qos->max_skip = frame->max_skip;
7646	vframe_qos->avg_skip = frame->avg_skip;
7647	vframe_qos->min_skip = frame->min_skip;
7648	#ifdef SHOW_QOS_INFO
7649	vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7650	vframe_qos->max_skip,
7651	vframe_qos->avg_skip,
7652	vframe_qos->min_skip);
7653	#endif
7654	vframe_qos->num++;
7655
7656	if (pbi->frameinfo_enable)
7657	vdec_fill_frame_info(vframe_qos, 1);
7658	}
7659
7660	/* only when we decoded one field or one frame,
7661	we can call this function to get qos info*/
7662	static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7663	{
7664	struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7665
7666	if (!frame)
7667	return;
7668
7669	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7670	unsigned char a[3];
7671	unsigned char i, j, t;
7672	unsigned long data;
7673
7674	data = READ_VREG(HEVC_MV_INFO);
7675	if (frame->slice_type == KEY_FRAME)
7676	data = 0;
7677	a[0] = data & 0xff;
7678	a[1] = (data >> 8) & 0xff;
7679	a[2] = (data >> 16) & 0xff;
7680
7681	for (i = 0; i < 3; i++) {
7682	for (j = i+1; j < 3; j++) {
7683	if (a[j] < a[i]) {
7684	t = a[j];
7685	a[j] = a[i];
7686	a[i] = t;
7687	} else if (a[j] == a[i]) {
7688	a[i]++;
7689	t = a[j];
7690	a[j] = a[i];
7691	a[i] = t;
7692	}
7693	}
7694	}
7695	frame->max_mv = a[2];
7696	frame->avg_mv = a[1];
7697	frame->min_mv = a[0];
7698
7699	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7700	"mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7701	data, a[0], a[1], a[2]);
7702
7703	data = READ_VREG(HEVC_QP_INFO);
7704	a[0] = data & 0x1f;
7705	a[1] = (data >> 8) & 0x3f;
7706	a[2] = (data >> 16) & 0x7f;
7707
7708	for (i = 0; i < 3; i++) {
7709	for (j = i+1; j < 3; j++) {
7710	if (a[j] < a[i]) {
7711	t = a[j];
7712	a[j] = a[i];
7713	a[i] = t;
7714	} else if (a[j] == a[i]) {
7715	a[i]++;
7716	t = a[j];
7717	a[j] = a[i];
7718	a[i] = t;
7719	}
7720	}
7721	}
7722	frame->max_qp = a[2];
7723	frame->avg_qp = a[1];
7724	frame->min_qp = a[0];
7725
7726	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7727	"qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7728	data, a[0], a[1], a[2]);
7729
7730	data = READ_VREG(HEVC_SKIP_INFO);
7731	a[0] = data & 0x1f;
7732	a[1] = (data >> 8) & 0x3f;
7733	a[2] = (data >> 16) & 0x7f;
7734
7735	for (i = 0; i < 3; i++) {
7736	for (j = i+1; j < 3; j++) {
7737	if (a[j] < a[i]) {
7738	t = a[j];
7739	a[j] = a[i];
7740	a[i] = t;
7741	} else if (a[j] == a[i]) {
7742	a[i]++;
7743	t = a[j];
7744	a[j] = a[i];
7745	a[i] = t;
7746	}
7747	}
7748	}
7749	frame->max_skip = a[2];
7750	frame->avg_skip = a[1];
7751	frame->min_skip = a[0];
7752
7753	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7754	"skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7755	data, a[0], a[1], a[2]);
7756	} else {
7757	uint32_t blk88_y_count;
7758	uint32_t blk88_c_count;
7759	uint32_t blk22_mv_count;
7760	uint32_t rdata32;
7761	int32_t mv_hi;
7762	int32_t mv_lo;
7763	uint32_t rdata32_l;
7764	uint32_t mvx_L0_hi;
7765	uint32_t mvy_L0_hi;
7766	uint32_t mvx_L1_hi;
7767	uint32_t mvy_L1_hi;
7768	int64_t value;
7769	uint64_t temp_value;
7770	int pic_number = frame->decode_idx;
7771
7772	frame->max_mv = 0;
7773	frame->avg_mv = 0;
7774	frame->min_mv = 0;
7775
7776	frame->max_skip = 0;
7777	frame->avg_skip = 0;
7778	frame->min_skip = 0;
7779
7780	frame->max_qp = 0;
7781	frame->avg_qp = 0;
7782	frame->min_qp = 0;
7783
7784	vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7785	frame->slice_type,
7786	pic_number);
7787
7788	/* set rd_idx to 0 */
7789	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7790
7791	blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7792	if (blk88_y_count == 0) {
7793
7794	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7795	"[Picture %d Quality] NO Data yet.\n",
7796	pic_number);
7797
7798	/* reset all counts */
7799	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7800	return;
7801	}
7802	/* qp_y_sum */
7803	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7804
7805	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7806	"[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7807	pic_number, rdata32/blk88_y_count,
7808	rdata32, blk88_y_count);
7809
7810	frame->avg_qp = rdata32/blk88_y_count;
7811	/* intra_y_count */
7812	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7813
7814	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7815	"[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7816	pic_number, rdata32*100/blk88_y_count,
7817	'%', rdata32);
7818
7819	/* skipped_y_count */
7820	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7821
7822	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7823	"[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7824	pic_number, rdata32*100/blk88_y_count,
7825	'%', rdata32);
7826
7827	frame->avg_skip = rdata32*100/blk88_y_count;
7828	/* coeff_non_zero_y_count */
7829	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7830
7831	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7832	"[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7833	pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7834	'%', rdata32);
7835
7836	/* blk66_c_count */
7837	blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7838	if (blk88_c_count == 0) {
7839	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7840	"[Picture %d Quality] NO Data yet.\n",
7841	pic_number);
7842	/* reset all counts */
7843	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7844	return;
7845	}
7846	/* qp_c_sum */
7847	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7848
7849	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7850	"[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7851	pic_number, rdata32/blk88_c_count,
7852	rdata32, blk88_c_count);
7853
7854	/* intra_c_count */
7855	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7856
7857	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7858	"[Picture %d Quality] C intra rate : %d%c (%d)\n",
7859	pic_number, rdata32*100/blk88_c_count,
7860	'%', rdata32);
7861
7862	/* skipped_cu_c_count */
7863	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7864
7865	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7866	"[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7867	pic_number, rdata32*100/blk88_c_count,
7868	'%', rdata32);
7869
7870	/* coeff_non_zero_c_count */
7871	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7872
7873	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7874	"[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7875	pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7876	'%', rdata32);
7877
7878	/* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7879	1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7880	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7881
7882	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7883	"[Picture %d Quality] Y QP min : %d\n",
7884	pic_number, (rdata32>>0)&0xff);
7885
7886	frame->min_qp = (rdata32>>0)&0xff;
7887
7888	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7889	"[Picture %d Quality] Y QP max : %d\n",
7890	pic_number, (rdata32>>8)&0xff);
7891
7892	frame->max_qp = (rdata32>>8)&0xff;
7893
7894	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7895	"[Picture %d Quality] C QP min : %d\n",
7896	pic_number, (rdata32>>16)&0xff);
7897	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7898	"[Picture %d Quality] C QP max : %d\n",
7899	pic_number, (rdata32>>24)&0xff);
7900
7901	/* blk22_mv_count */
7902	blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7903	if (blk22_mv_count == 0) {
7904	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7905	"[Picture %d Quality] NO MV Data yet.\n",
7906	pic_number);
7907	/* reset all counts */
7908	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7909	return;
7910	}
7911	/* mvy_L1_count[39:32], mvx_L1_count[39:32],
7912	mvy_L0_count[39:32], mvx_L0_count[39:32] */
7913	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7914	/* should all be 0x00 or 0xff */
7915	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7916	"[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7917	pic_number, rdata32);
7918
7919	mvx_L0_hi = ((rdata32>>0)&0xff);
7920	mvy_L0_hi = ((rdata32>>8)&0xff);
7921	mvx_L1_hi = ((rdata32>>16)&0xff);
7922	mvy_L1_hi = ((rdata32>>24)&0xff);
7923
7924	/* mvx_L0_count[31:0] */
7925	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7926	temp_value = mvx_L0_hi;
7927	temp_value = (temp_value << 32) | rdata32_l;
7928
7929	if (mvx_L0_hi & 0x80)
7930	value = 0xFFFFFFF000000000 | temp_value;
7931	else
7932	value = temp_value;
7933
7934	value = div_s64(value, blk22_mv_count);
7935
7936	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7937	"[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7938	pic_number, (int)value,
7939	value, blk22_mv_count);
7940
7941	frame->avg_mv = value;
7942
7943	/* mvy_L0_count[31:0] */
7944	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7945	temp_value = mvy_L0_hi;
7946	temp_value = (temp_value << 32) | rdata32_l;
7947
7948	if (mvy_L0_hi & 0x80)
7949	value = 0xFFFFFFF000000000 | temp_value;
7950	else
7951	value = temp_value;
7952
7953	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7954	"[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7955	pic_number, rdata32_l/blk22_mv_count,
7956	value, blk22_mv_count);
7957
7958	/* mvx_L1_count[31:0] */
7959	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7960	temp_value = mvx_L1_hi;
7961	temp_value = (temp_value << 32) | rdata32_l;
7962	if (mvx_L1_hi & 0x80)
7963	value = 0xFFFFFFF000000000 | temp_value;
7964	else
7965	value = temp_value;
7966
7967	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7968	"[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
7969	pic_number, rdata32_l/blk22_mv_count,
7970	value, blk22_mv_count);
7971
7972	/* mvy_L1_count[31:0] */
7973	rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7974	temp_value = mvy_L1_hi;
7975	temp_value = (temp_value << 32) | rdata32_l;
7976	if (mvy_L1_hi & 0x80)
7977	value = 0xFFFFFFF000000000 | temp_value;
7978	else
7979	value = temp_value;
7980
7981	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7982	"[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
7983	pic_number, rdata32_l/blk22_mv_count,
7984	value, blk22_mv_count);
7985
7986	/* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
7987	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7988	mv_hi = (rdata32>>16)&0xffff;
7989	if (mv_hi & 0x8000)
7990	mv_hi = 0x8000 - mv_hi;
7991
7992	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7993	"[Picture %d Quality] MVX_L0 MAX : %d\n",
7994	pic_number, mv_hi);
7995
7996	frame->max_mv = mv_hi;
7997
7998	mv_lo = (rdata32>>0)&0xffff;
7999	if (mv_lo & 0x8000)
8000	mv_lo = 0x8000 - mv_lo;
8001
8002	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8003	"[Picture %d Quality] MVX_L0 MIN : %d\n",
8004	pic_number, mv_lo);
8005
8006	frame->min_mv = mv_lo;
8007
8008	/* {mvy_L0_max, mvy_L0_min} */
8009	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8010	mv_hi = (rdata32>>16)&0xffff;
8011	if (mv_hi & 0x8000)
8012	mv_hi = 0x8000 - mv_hi;
8013
8014	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8015	"[Picture %d Quality] MVY_L0 MAX : %d\n",
8016	pic_number, mv_hi);
8017
8018	mv_lo = (rdata32>>0)&0xffff;
8019	if (mv_lo & 0x8000)
8020	mv_lo = 0x8000 - mv_lo;
8021
8022	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8023	"[Picture %d Quality] MVY_L0 MIN : %d\n",
8024	pic_number, mv_lo);
8025
8026	/* {mvx_L1_max, mvx_L1_min} */
8027	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8028	mv_hi = (rdata32>>16)&0xffff;
8029	if (mv_hi & 0x8000)
8030	mv_hi = 0x8000 - mv_hi;
8031
8032	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8033	"[Picture %d Quality] MVX_L1 MAX : %d\n",
8034	pic_number, mv_hi);
8035
8036	mv_lo = (rdata32>>0)&0xffff;
8037	if (mv_lo & 0x8000)
8038	mv_lo = 0x8000 - mv_lo;
8039
8040	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8041	"[Picture %d Quality] MVX_L1 MIN : %d\n",
8042	pic_number, mv_lo);
8043
8044	/* {mvy_L1_max, mvy_L1_min} */
8045	rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8046	mv_hi = (rdata32>>16)&0xffff;
8047	if (mv_hi & 0x8000)
8048	mv_hi = 0x8000 - mv_hi;
8049
8050	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8051	"[Picture %d Quality] MVY_L1 MAX : %d\n",
8052	pic_number, mv_hi);
8053
8054	mv_lo = (rdata32>>0)&0xffff;
8055	if (mv_lo & 0x8000)
8056	mv_lo = 0x8000 - mv_lo;
8057
8058	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8059	"[Picture %d Quality] MVY_L1 MIN : %d\n",
8060	pic_number, mv_lo);
8061
8062	rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8063
8064	vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8065	"[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8066	pic_number, rdata32);
8067
8068	/* reset all counts */
8069	WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8070	}
8071	}
8072
8073	static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8074	{
8075	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8076	unsigned int dec_status = pbi->dec_status;
8077	int i;
8078
8079	/*if (pbi->wait_buf)
8080	* pr_info("set wait_buf to 0\r\n");
8081	*/
8082	if (pbi->eos)
8083	return IRQ_HANDLED;
8084	pbi->wait_buf = 0;
8085	#ifdef MULTI_INSTANCE_SUPPORT
8086	#ifdef SUPPORT_FB_DECODING
8087	#ifdef FB_DECODING_TEST_SCHEDULE
8088	if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8089	dec_status = HEVC_DECPIC_DATA_DONE;
8090	else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8091	&& dec_status == HEVC_DECPIC_DATA_DONE)
8092	dec_status = HEVC_S2_DECODING_DONE;
8093	pbi->s1_test_cmd = TEST_SET_NONE;
8094	#else
8095	/*if (irq != VDEC_IRQ_0)
8096	dec_status = HEVC_S2_DECODING_DONE;*/
8097	#endif
8098	if (dec_status == HEVC_S2_DECODING_DONE) {
8099	pbi->dec_result = DEC_RESULT_DONE;
8100	vdec_schedule_work(&pbi->work);
8101	#ifdef FB_DECODING_TEST_SCHEDULE
8102	amhevc_stop();
8103	pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8104	vdec_schedule_work(&pbi->s1_work);
8105	#endif
8106	} else
8107	#endif
8108	if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8109	(dec_status == HEVC_SEARCH_BUFEMPTY) ||
8110	(dec_status == HEVC_DECODE_BUFEMPTY)
8111	) {
8112	if (pbi->m_ins_flag) {
8113	reset_process_time(pbi);
8114	if (!vdec_frame_based(hw_to_vdec(pbi)))
8115	dec_again_process(pbi);
8116	else {
8117	pbi->dec_result = DEC_RESULT_GET_DATA;
8118	vdec_schedule_work(&pbi->work);
8119	}
8120	}
8121	pbi->process_busy = 0;
8122	return IRQ_HANDLED;
8123	} else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8124	if (pbi->m_ins_flag) {
8125	get_picture_qos_info(pbi);
8126	#ifdef SUPPORT_FB_DECODING
8127	if (pbi->used_stage_buf_num > 0) {
8128	reset_process_time(pbi);
8129	inc_s1_pos(pbi);
8130	trigger_schedule(pbi);
8131	#ifdef FB_DECODING_TEST_SCHEDULE
8132	pbi->s1_test_cmd = TEST_SET_S2_DONE;
8133	#else
8134	amhevc_stop();
8135	pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8136	vdec_schedule_work(&pbi->s1_work);
8137	#endif
8138	} else
8139	#endif
8140	{
8141	reset_process_time(pbi);
8142	if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8143	vp9_bufmgr_postproc(pbi);
8144
8145	pbi->dec_result = DEC_RESULT_DONE;
8146	amhevc_stop();
8147	if (mcrcc_cache_alg_flag)
8148	dump_hit_rate(pbi);
8149	vdec_schedule_work(&pbi->work);
8150	}
8151	} else {
8152	if (pbi->low_latency_flag) {
8153	vp9_bufmgr_postproc(pbi);
8154	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8155	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8156	vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8157	if (debug & PRINT_FLAG_VDEC_DETAIL)
8158	pr_info("%s VP9 frame done \n", __func__);
8159	#endif
8160	}
8161	}
8162
8163	pbi->process_busy = 0;
8164	return IRQ_HANDLED;
8165	}
8166	#endif
8167
8168	if (dec_status == VP9_EOS) {
8169	#ifdef MULTI_INSTANCE_SUPPORT
8170	if (pbi->m_ins_flag)
8171	reset_process_time(pbi);
8172	#endif
8173
8174	pr_info("VP9_EOS, flush buffer\r\n");
8175
8176	vp9_bufmgr_postproc(pbi);
8177
8178	pr_info("send VP9_10B_DISCARD_NAL\r\n");
8179	WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8180	pbi->process_busy = 0;
8181	#ifdef MULTI_INSTANCE_SUPPORT
8182	if (pbi->m_ins_flag) {
8183	pbi->dec_result = DEC_RESULT_DONE;
8184	amhevc_stop();
8185	vdec_schedule_work(&pbi->work);
8186	}
8187	#endif
8188	return IRQ_HANDLED;
8189	} else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8190	pr_info("vp9 decode oversize !!\n");
8191	debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8192	VP9_DEBUG_DIS_SYS_ERROR_PROC);
8193	pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8194	#ifdef MULTI_INSTANCE_SUPPORT
8195	if (pbi->m_ins_flag)
8196	reset_process_time(pbi);
8197	#endif
8198	return IRQ_HANDLED;
8199	}
8200
8201	if (dec_status != VP9_HEAD_PARSER_DONE) {
8202	pbi->process_busy = 0;
8203	return IRQ_HANDLED;
8204	}
8205
8206
8207	#ifdef MULTI_INSTANCE_SUPPORT
8208	#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8209	if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8210	vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8211	if (debug & PRINT_FLAG_VDEC_DETAIL)
8212	pr_info("%s VP9 frame header found \n", __func__);
8213	}
8214	#endif
8215	if (pbi->m_ins_flag)
8216	reset_process_time(pbi);
8217	#endif
8218	if (pbi->process_state != PROC_STATE_SENDAGAIN
8219	#ifdef SUPPORT_FB_DECODING
8220	&& pbi->used_stage_buf_num == 0
8221	#endif
8222	) {
8223	if (pbi->mmu_enable)
8224	vp9_recycle_mmu_buf_tail(pbi);
8225
8226
8227	if (pbi->frame_count > 0)
8228	vp9_bufmgr_postproc(pbi);
8229	}
8230
8231	if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8232	get_rpm_param(&vp9_param);
8233	} else {
8234	#ifdef SUPPORT_FB_DECODING
8235	if (pbi->used_stage_buf_num > 0) {
8236	reset_process_time(pbi);
8237	get_s1_buf(pbi);
8238
8239	if (get_mv_buf(pbi,
8240	&pbi->s1_mv_buf_index,
8241	&pbi->s1_mpred_mv_wr_start_addr
8242	) < 0) {
8243	vp9_print(pbi, 0,
8244	"%s: Error get_mv_buf fail\n",
8245	__func__);
8246	}
8247
8248	if (pbi->s1_buf == NULL) {
8249	vp9_print(pbi, 0,
8250	"%s: Error get_s1_buf fail\n",
8251	__func__);
8252	pbi->process_busy = 0;
8253	return IRQ_HANDLED;
8254	}
8255
8256	for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8257	int ii;
8258	for (ii = 0; ii < 4; ii++) {
8259	pbi->s1_buf->rpm[i + 3 - ii] =
8260	pbi->rpm_ptr[i + 3 - ii];
8261	pbi->s1_param.l.data[i + ii] =
8262	pbi->rpm_ptr[i + 3 - ii];
8263	}
8264	}
8265
8266	mpred_process(pbi);
8267	#ifdef FB_DECODING_TEST_SCHEDULE
8268	pbi->dec_s1_result =
8269	DEC_S1_RESULT_TEST_TRIGGER_DONE;
8270	vdec_schedule_work(&pbi->s1_work);
8271	#else
8272	WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8273	pbi->stage_mmu_map_phy_addr +
8274	pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8275
8276	start_s1_decoding(pbi);
8277	#endif
8278	start_process_time(pbi);
8279	pbi->process_busy = 0;
8280	return IRQ_HANDLED;
8281	} else
8282	#endif
8283	{
8284	for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8285	int ii;
8286	for (ii = 0; ii < 4; ii++)
8287	vp9_param.l.data[i + ii] =
8288	pbi->rpm_ptr[i + 3 - ii];
8289	}
8290	}
8291	}
8292
8293	if (pbi->is_used_v4l) {
8294	struct aml_vcodec_ctx *ctx =
8295	(struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8296
8297	pbi->frame_width = vp9_param.p.width;
8298	pbi->frame_height = vp9_param.p.height;
8299	if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8300	struct aml_vdec_ps_infos ps;
8301
8302	ps.visible_width = pbi->frame_width;
8303	ps.visible_height = pbi->frame_height;
8304	ps.coded_width = ALIGN(pbi->frame_width, 32);
8305	ps.coded_height = ALIGN(pbi->frame_height, 32);
8306	ps.dpb_size = pbi->used_buf_num;
8307	pbi->v4l_params_parsed = true;
8308	vdec_v4l_set_ps_infos(ctx, &ps);
8309	}
8310	}
8311
8312	if (pbi->is_used_v4l) {
8313	pbi->dec_result = DEC_V4L2_CONTINUE_DECODING;
8314	vdec_schedule_work(&pbi->work);
8315	} else {
8316	continue_decoding(pbi);
8317	pbi->postproc_done = 0;
8318	pbi->process_busy = 0;
8319	}
8320
8321	#ifdef MULTI_INSTANCE_SUPPORT
8322	if (pbi->m_ins_flag)
8323	start_process_time(pbi);
8324	#endif
8325
8326	return IRQ_HANDLED;
8327	}
8328
8329	static irqreturn_t vvp9_isr(int irq, void *data)
8330	{
8331	int i;
8332	unsigned int dec_status;
8333	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8334	unsigned int adapt_prob_status;
8335	struct VP9_Common_s *const cm = &pbi->common;
8336	uint debug_tag;
8337
8338	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8339
8340	dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8341	adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8342	if (!pbi)
8343	return IRQ_HANDLED;
8344	if (pbi->init_flag == 0)
8345	return IRQ_HANDLED;
8346	if (pbi->process_busy)/*on process.*/
8347	return IRQ_HANDLED;
8348	pbi->dec_status = dec_status;
8349	pbi->process_busy = 1;
8350	if (debug & VP9_DEBUG_BUFMGR)
8351	pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8352	irq,
8353	dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8354	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8355	READ_VREG(HEVC_STREAM_START_ADDR),
8356	READ_VREG(HEVC_STREAM_END_ADDR),
8357	READ_VREG(HEVC_STREAM_LEVEL),
8358	READ_VREG(HEVC_STREAM_WR_PTR),
8359	READ_VREG(HEVC_STREAM_RD_PTR)
8360	);
8361	#ifdef SUPPORT_FB_DECODING
8362	/*if (irq != VDEC_IRQ_0)
8363	return IRQ_WAKE_THREAD;*/
8364	#endif
8365
8366	debug_tag = READ_HREG(DEBUG_REG1);
8367	if (debug_tag & 0x10000) {
8368	pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8369	for (i = 0; i < 0x400; i += 4) {
8370	int ii;
8371	if ((i & 0xf) == 0)
8372	pr_info("%03x: ", i);
8373	for (ii = 0; ii < 4; ii++) {
8374	pr_info("%04x ",
8375	pbi->lmem_ptr[i + 3 - ii]);
8376	}
8377	if (((i + ii) & 0xf) == 0)
8378	pr_info("\n");
8379	}
8380
8381	if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8382	(udebug_pause_decode_idx == 0 ||
8383	udebug_pause_decode_idx == pbi->slice_idx) &&
8384	(udebug_pause_val == 0 ||
8385	udebug_pause_val == READ_HREG(DEBUG_REG2)))
8386	pbi->ucode_pause_pos = udebug_pause_pos;
8387	else if (debug_tag & 0x20000)
8388	pbi->ucode_pause_pos = 0xffffffff;
8389	if (pbi->ucode_pause_pos)
8390	reset_process_time(pbi);
8391	else
8392	WRITE_HREG(DEBUG_REG1, 0);
8393	} else if (debug_tag != 0) {
8394	pr_info(
8395	"dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8396	READ_HREG(DEBUG_REG2),
8397	READ_VREG(HEVC_PARSER_LCU_START));
8398	if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8399	(udebug_pause_decode_idx == 0 ||
8400	udebug_pause_decode_idx == pbi->slice_idx) &&
8401	(udebug_pause_val == 0 ||
8402	udebug_pause_val == READ_HREG(DEBUG_REG2)))
8403	pbi->ucode_pause_pos = udebug_pause_pos;
8404	if (pbi->ucode_pause_pos)
8405	reset_process_time(pbi);
8406	else
8407	WRITE_HREG(DEBUG_REG1, 0);
8408	pbi->process_busy = 0;
8409	return IRQ_HANDLED;
8410	}
8411
8412	#ifdef MULTI_INSTANCE_SUPPORT
8413	if (!pbi->m_ins_flag) {
8414	#endif
8415	if (pbi->error_flag == 1) {
8416	pbi->error_flag = 2;
8417	pbi->process_busy = 0;
8418	return IRQ_HANDLED;
8419	} else if (pbi->error_flag == 3) {
8420	pbi->process_busy = 0;
8421	return IRQ_HANDLED;
8422	}
8423
8424	if (get_free_buf_count(pbi) <= 0) {
8425	/*
8426	if (pbi->wait_buf == 0)
8427	pr_info("set wait_buf to 1\r\n");
8428	*/
8429	pbi->wait_buf = 1;
8430	pbi->process_busy = 0;
8431	return IRQ_HANDLED;
8432	}
8433	#ifdef MULTI_INSTANCE_SUPPORT
8434	}
8435	#endif
8436	if ((adapt_prob_status & 0xff) == 0xfd) {
8437	/*VP9_REQ_ADAPT_PROB*/
8438	int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8439	uint8_t *prev_prob_b =
8440	((uint8_t *)pbi->prob_buffer_addr) +
8441	((adapt_prob_status >> 8) * 0x1000);
8442	uint8_t *cur_prob_b =
8443	((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8444	uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8445	#ifdef MULTI_INSTANCE_SUPPORT
8446	if (pbi->m_ins_flag)
8447	reset_process_time(pbi);
8448	#endif
8449	adapt_coef_probs(pbi->pic_count,
8450	(cm->last_frame_type == KEY_FRAME),
8451	pre_fc, (adapt_prob_status >> 8),
8452	(unsigned int *)prev_prob_b,
8453	(unsigned int *)cur_prob_b, (unsigned int *)count_b);
8454
8455	memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8456	WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8457	pbi->pic_count += 1;
8458	#ifdef MULTI_INSTANCE_SUPPORT
8459	if (pbi->m_ins_flag)
8460	start_process_time(pbi);
8461	#endif
8462
8463	/*return IRQ_HANDLED;*/
8464	}
8465	return IRQ_WAKE_THREAD;
8466	}
8467
8468	static void vp9_set_clk(struct work_struct *work)
8469	{
8470	struct VP9Decoder_s *pbi = container_of(work,
8471	struct VP9Decoder_s, set_clk_work);
8472	int fps = 96000 / pbi->frame_dur;
8473
8474	if (hevc_source_changed(VFORMAT_VP9,
8475	frame_width, frame_height, fps) > 0)
8476	pbi->saved_resolution = frame_width *
8477	frame_height * fps;
8478	}
8479
8480	static void vvp9_put_timer_func(unsigned long arg)
8481	{
8482	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8483	struct timer_list *timer = &pbi->timer;
8484	uint8_t empty_flag;
8485	unsigned int buf_level;
8486
8487	enum receviver_start_e state = RECEIVER_INACTIVE;
8488
8489	if (pbi->m_ins_flag) {
8490	if (hw_to_vdec(pbi)->next_status
8491	== VDEC_STATUS_DISCONNECTED) {
8492	#ifdef SUPPORT_FB_DECODING
8493	if (pbi->run2_busy)
8494	return;
8495
8496	pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8497	vdec_schedule_work(&pbi->s1_work);
8498	#endif
8499	pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8500	vdec_schedule_work(&pbi->work);
8501	pr_debug(
8502	"vdec requested to be disconnected\n");
8503	return;
8504	}
8505	}
8506	if (pbi->init_flag == 0) {
8507	if (pbi->stat & STAT_TIMER_ARM) {
8508	timer->expires = jiffies + PUT_INTERVAL;
8509	add_timer(&pbi->timer);
8510	}
8511	return;
8512	}
8513	if (pbi->m_ins_flag == 0) {
8514	if (vf_get_receiver(pbi->provider_name)) {
8515	state =
8516	vf_notify_receiver(pbi->provider_name,
8517	VFRAME_EVENT_PROVIDER_QUREY_STATE,
8518	NULL);
8519	if ((state == RECEIVER_STATE_NULL)
8520	|| (state == RECEIVER_STATE_NONE))
8521	state = RECEIVER_INACTIVE;
8522	} else
8523	state = RECEIVER_INACTIVE;
8524
8525	empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8526	/* error watchdog */
8527	if (empty_flag == 0) {
8528	/* decoder has input */
8529	if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8530
8531	buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8532	/* receiver has no buffer to recycle */
8533	if ((state == RECEIVER_INACTIVE) &&
8534	(kfifo_is_empty(&pbi->display_q) &&
8535	buf_level > 0x200)
8536	) {
8537	WRITE_VREG
8538	(HEVC_ASSIST_MBOX0_IRQ_REG,
8539	0x1);
8540	}
8541	}
8542
8543	if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8544	/* receiver has no buffer to recycle */
8545	/*if ((state == RECEIVER_INACTIVE) &&
8546	* (kfifo_is_empty(&pbi->display_q))) {
8547	*pr_info("vp9 something error,need reset\n");
8548	*}
8549	*/
8550	}
8551	}
8552	}
8553	#ifdef MULTI_INSTANCE_SUPPORT
8554	else {
8555	if (
8556	(decode_timeout_val > 0) &&
8557	(pbi->start_process_time > 0) &&
8558	((1000 * (jiffies - pbi->start_process_time) / HZ)
8559	> decode_timeout_val)
8560	) {
8561	int current_lcu_idx =
8562	READ_VREG(HEVC_PARSER_LCU_START)
8563	& 0xffffff;
8564	if (pbi->last_lcu_idx == current_lcu_idx) {
8565	if (pbi->decode_timeout_count > 0)
8566	pbi->decode_timeout_count--;
8567	if (pbi->decode_timeout_count == 0) {
8568	if (input_frame_based(
8569	hw_to_vdec(pbi)) ||
8570	(READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8571	timeout_process(pbi);
8572	else {
8573	vp9_print(pbi, 0,
8574	"timeout & empty, again\n");
8575	dec_again_process(pbi);
8576	}
8577	}
8578	} else {
8579	start_process_time(pbi);
8580	pbi->last_lcu_idx = current_lcu_idx;
8581	}
8582	}
8583	}
8584	#endif
8585
8586	if ((pbi->ucode_pause_pos != 0) &&
8587	(pbi->ucode_pause_pos != 0xffffffff) &&
8588	udebug_pause_pos != pbi->ucode_pause_pos) {
8589	pbi->ucode_pause_pos = 0;
8590	WRITE_HREG(DEBUG_REG1, 0);
8591	}
8592	#ifdef MULTI_INSTANCE_SUPPORT
8593	if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8594	pr_info(
8595	"Force Send Again\r\n");
8596	debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8597	reset_process_time(pbi);
8598	pbi->dec_result = DEC_RESULT_AGAIN;
8599	if (pbi->process_state ==
8600	PROC_STATE_DECODESLICE) {
8601	if (pbi->mmu_enable)
8602	vp9_recycle_mmu_buf(pbi);
8603	pbi->process_state =
8604	PROC_STATE_SENDAGAIN;
8605	}
8606	amhevc_stop();
8607
8608	vdec_schedule_work(&pbi->work);
8609	}
8610
8611	if (debug & VP9_DEBUG_DUMP_DATA) {
8612	debug &= ~VP9_DEBUG_DUMP_DATA;
8613	vp9_print(pbi, 0,
8614	"%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8615	__func__,
8616	pbi->chunk->size,
8617	pbi->chunk->offset,
8618	get_data_check_sum(pbi, pbi->chunk->size)
8619	);
8620	dump_data(pbi, pbi->chunk->size);
8621	}
8622	#endif
8623	if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8624	dump_pic_list(pbi);
8625	debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8626	}
8627	if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8628	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8629	debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8630	}
8631	/*if (debug & VP9_DEBUG_HW_RESET) {
8632	}*/
8633
8634	if (radr != 0) {
8635	if (rval != 0) {
8636	WRITE_VREG(radr, rval);
8637	pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8638	} else
8639	pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8640	rval = 0;
8641	radr = 0;
8642	}
8643	if (pop_shorts != 0) {
8644	int i;
8645	u32 sum = 0;
8646
8647	pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8648	for (i = 0; i < pop_shorts; i++) {
8649	u32 data =
8650	(READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8651	WRITE_HREG(HEVC_SHIFT_COMMAND,
8652	(1<<7)|16);
8653	if ((i & 0xf) == 0)
8654	pr_info("%04x:", i);
8655	pr_info("%04x ", data);
8656	if (((i + 1) & 0xf) == 0)
8657	pr_info("\r\n");
8658	sum += data;
8659	}
8660	pr_info("\r\nsum = %x\r\n", sum);
8661	pop_shorts = 0;
8662	}
8663	if (dbg_cmd != 0) {
8664	if (dbg_cmd == 1) {
8665	u32 disp_laddr;
8666
8667	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8668	get_double_write_mode(pbi) == 0) {
8669	disp_laddr =
8670	READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8671	} else {
8672	struct canvas_s cur_canvas;
8673
8674	canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8675	& 0xff), &cur_canvas);
8676	disp_laddr = cur_canvas.addr;
8677	}
8678	pr_info("current displayed buffer address %x\r\n",
8679	disp_laddr);
8680	}
8681	dbg_cmd = 0;
8682	}
8683	/*don't changed at start.*/
8684	if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8685	pbi->frame_dur > 0 && pbi->saved_resolution !=
8686	frame_width * frame_height *
8687	(96000 / pbi->frame_dur))
8688	vdec_schedule_work(&pbi->set_clk_work);
8689
8690	timer->expires = jiffies + PUT_INTERVAL;
8691	add_timer(timer);
8692	}
8693
8694
8695	int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8696	{
8697	struct VP9Decoder_s *vp9 =
8698	(struct VP9Decoder_s *)vdec->private;
8699
8700	if (!vp9)
8701	return -1;
8702
8703	vstatus->frame_width = frame_width;
8704	vstatus->frame_height = frame_height;
8705	if (vp9->frame_dur != 0)
8706	vstatus->frame_rate = 96000 / vp9->frame_dur;
8707	else
8708	vstatus->frame_rate = -1;
8709	vstatus->error_count = 0;
8710	vstatus->status = vp9->stat | vp9->fatal_error;
8711	vstatus->frame_dur = vp9->frame_dur;
8712	#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8713	vstatus->bit_rate = gvs->bit_rate;
8714	vstatus->frame_data = gvs->frame_data;
8715	vstatus->total_data = gvs->total_data;
8716	vstatus->frame_count = gvs->frame_count;
8717	vstatus->error_frame_count = gvs->error_frame_count;
8718	vstatus->drop_frame_count = gvs->drop_frame_count;
8719	vstatus->total_data = gvs->total_data;
8720	vstatus->samp_cnt = gvs->samp_cnt;
8721	vstatus->offset = gvs->offset;
8722	snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8723	"%s", DRIVER_NAME);
8724	#endif
8725	return 0;
8726	}
8727
8728	int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8729	{
8730	is_reset = isreset;
8731	return 0;
8732	}
8733
8734	#if 0
8735	static void VP9_DECODE_INIT(void)
8736	{
8737	/* enable vp9 clocks */
8738	WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8739	/* *************************************************************** */
8740	/* Power ON HEVC */
8741	/* *************************************************************** */
8742	/* Powerup HEVC */
8743	WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8744	READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8745	WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8746	WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8747	WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8748	/* remove isolations */
8749	WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8750	READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8751
8752	}
8753	#endif
8754
8755	static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8756	{
8757	unsigned int data32;
8758	/* VP9_DECODE_INIT(); */
8759	vp9_config_work_space_hw(pbi, mask);
8760	if (mask & HW_MASK_BACK)
8761	init_pic_list_hw(pbi);
8762
8763	vp9_init_decoder_hw(pbi, mask);
8764
8765	#ifdef VP9_LPF_LVL_UPDATE
8766	if (mask & HW_MASK_BACK)
8767	vp9_loop_filter_init(pbi);
8768	#endif
8769
8770	if ((mask & HW_MASK_FRONT) == 0)
8771	return;
8772	#if 1
8773	if (debug & VP9_DEBUG_BUFMGR_MORE)
8774	pr_info("%s\n", __func__);
8775	data32 = READ_VREG(HEVC_STREAM_CONTROL);
8776	data32 = data32 |
8777	(1 << 0)/*stream_fetch_enable*/
8778	;
8779	WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8780
8781	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8782	if (debug & VP9_DEBUG_BUFMGR)
8783	pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8784	data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8785	data32 = data32 |
8786	(1 << 29) // stream_fifo_hole
8787	;
8788	WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8789	}
8790	#if 0
8791	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8792	if (data32 != 0x00000100) {
8793	pr_info("vp9 prot init error %d\n", __LINE__);
8794	return;
8795	}
8796	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8797	if (data32 != 0x00000300) {
8798	pr_info("vp9 prot init error %d\n", __LINE__);
8799	return;
8800	}
8801	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8802	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8803	data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8804	if (data32 != 0x12345678) {
8805	pr_info("vp9 prot init error %d\n", __LINE__);
8806	return;
8807	}
8808	data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8809	if (data32 != 0x9abcdef0) {
8810	pr_info("vp9 prot init error %d\n", __LINE__);
8811	return;
8812	}
8813	#endif
8814	WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8815	WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8816	#endif
8817
8818
8819
8820	WRITE_VREG(HEVC_WAIT_FLAG, 1);
8821
8822	/* WRITE_VREG(HEVC_MPSR, 1); */
8823
8824	/* clear mailbox interrupt */
8825	WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8826
8827	/* enable mailbox interrupt */
8828	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8829
8830	/* disable PSCALE for hardware sharing */
8831	WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8832
8833	WRITE_VREG(DEBUG_REG1, 0x0);
8834	/*check vps/sps/pps/i-slice in ucode*/
8835	WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8836
8837	WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8838	#ifdef SUPPORT_FB_DECODING
8839	#ifndef FB_DECODING_TEST_SCHEDULE
8840	if (pbi->used_stage_buf_num > 0) {
8841	if (mask & HW_MASK_FRONT) {
8842	data32 = READ_VREG(
8843	HEVC_ASSIST_HED_FB_W_CTL);
8844	data32 = data32 |
8845	(1 << 0) /*hed_fb_wr_en*/
8846	;
8847	WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8848	data32);
8849	}
8850	if (mask & HW_MASK_BACK) {
8851	data32 = READ_VREG(
8852	HEVC_ASSIST_HED_FB_R_CTL);
8853	while (data32 & (1 << 7)) {
8854	/*wait finish*/
8855	data32 = READ_VREG(
8856	HEVC_ASSIST_HED_FB_R_CTL);
8857	}
8858	data32 &= (~(0x1 << 0));
8859	/*hed_fb_rd_addr_auto_rd*/
8860	data32 &= (~(0x1 << 1));
8861	/*rd_id = 0, hed_rd_map_auto_halt_num,
8862	after wr 2 ready, then start reading*/
8863	data32 |= (0x2 << 16);
8864	WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8865	data32);
8866
8867	data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8868	data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8869	data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8870	WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8871	data32);
8872	}
8873
8874	}
8875	#endif
8876	#endif
8877	}
8878
8879	static int vvp9_local_init(struct VP9Decoder_s *pbi)
8880	{
8881	int i;
8882	int ret;
8883	int width, height;
8884	if (alloc_lf_buf(pbi) < 0)
8885	return -1;
8886
8887	pbi->gvs = vzalloc(sizeof(struct vdec_info));
8888	if (NULL == pbi->gvs) {
8889	pr_info("the struct of vdec status malloc failed.\n");
8890	return -1;
8891	}
8892	#ifdef DEBUG_PTS
8893	pbi->pts_missed = 0;
8894	pbi->pts_hit = 0;
8895	#endif
8896	pbi->new_frame_displayed = 0;
8897	pbi->last_put_idx = -1;
8898	pbi->saved_resolution = 0;
8899	pbi->get_frame_dur = false;
8900	on_no_keyframe_skiped = 0;
8901	pbi->duration_from_pts_done = 0;
8902	pbi->vp9_first_pts_ready = 0;
8903	pbi->frame_cnt_window = 0;
8904	width = pbi->vvp9_amstream_dec_info.width;
8905	height = pbi->vvp9_amstream_dec_info.height;
8906	pbi->frame_dur =
8907	(pbi->vvp9_amstream_dec_info.rate ==
8908	0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8909	if (width && height)
8910	pbi->frame_ar = height * 0x100 / width;
8911	/*
8912	*TODO:FOR VERSION
8913	*/
8914	pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8915	0, width, height, pbi->frame_dur);
8916
8917	if (pbi->frame_dur == 0)
8918	pbi->frame_dur = 96000 / 24;
8919
8920	INIT_KFIFO(pbi->display_q);
8921	INIT_KFIFO(pbi->newframe_q);
8922
8923
8924	for (i = 0; i < VF_POOL_SIZE; i++) {
8925	const struct vframe_s *vf = &pbi->vfpool[i];
8926
8927	pbi->vfpool[i].index = -1;
8928	kfifo_put(&pbi->newframe_q, vf);
8929	}
8930
8931
8932	ret = vp9_local_init(pbi);
8933
8934	if (!pbi->pts_unstable) {
8935	pbi->pts_unstable =
8936	(pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8937	pr_info("set pts unstable\n");
8938	}
8939
8940	return ret;
8941	}
8942
8943
8944	#ifdef MULTI_INSTANCE_SUPPORT
8945	static s32 vvp9_init(struct vdec_s *vdec)
8946	{
8947	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8948	#else
8949	static s32 vvp9_init(struct VP9Decoder_s *pbi)
8950	{
8951	#endif
8952	int ret;
8953	int fw_size = 0x1000 * 16;
8954	struct firmware_s *fw = NULL;
8955
8956	pbi->stat |= STAT_TIMER_INIT;
8957
8958	if (vvp9_local_init(pbi) < 0)
8959	return -EBUSY;
8960
8961	fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8962	if (IS_ERR_OR_NULL(fw))
8963	return -ENOMEM;
8964
8965	if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8966	pr_err("get firmware fail.\n");
8967	vfree(fw);
8968	return -1;
8969	}
8970
8971	fw->len = fw_size;
8972
8973	INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
8974	init_timer(&pbi->timer);
8975
8976	#ifdef MULTI_INSTANCE_SUPPORT
8977	if (pbi->m_ins_flag) {
8978	pbi->timer.data = (ulong) pbi;
8979	pbi->timer.function = vvp9_put_timer_func;
8980	pbi->timer.expires = jiffies + PUT_INTERVAL;
8981
8982	/*add_timer(&pbi->timer);
8983
8984	pbi->stat |= STAT_TIMER_ARM;
8985	pbi->stat |= STAT_ISR_REG;*/
8986
8987	INIT_WORK(&pbi->work, vp9_work);
8988	#ifdef SUPPORT_FB_DECODING
8989	if (pbi->used_stage_buf_num > 0)
8990	INIT_WORK(&pbi->s1_work, vp9_s1_work);
8991	#endif
8992	pbi->fw = fw;
8993
8994	/* picture list init.*/
8995	pbi->dec_result = DEC_INIT_PICLIST;
8996	vdec_schedule_work(&pbi->work);
8997
8998	return 0;
8999	}
9000	#endif
9001	amhevc_enable();
9002
9003	init_pic_list(pbi);
9004
9005	ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9006	if (ret < 0) {
9007	amhevc_disable();
9008	vfree(fw);
9009	pr_err("VP9: the %s fw loading failed, err: %x\n",
9010	tee_enabled() ? "TEE" : "local", ret);
9011	return -EBUSY;
9012	}
9013
9014	vfree(fw);
9015
9016	pbi->stat |= STAT_MC_LOAD;
9017
9018	/* enable AMRISC side protocol */
9019	vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9020
9021	if (vdec_request_threaded_irq(VDEC_IRQ_0,
9022	vvp9_isr,
9023	vvp9_isr_thread_fn,
9024	IRQF_ONESHOT,/*run thread on this irq disabled*/
9025	"vvp9-irq", (void *)pbi)) {
9026	pr_info("vvp9 irq register error.\n");
9027	amhevc_disable();
9028	return -ENOENT;
9029	}
9030
9031	pbi->stat |= STAT_ISR_REG;
9032
9033	pbi->provider_name = PROVIDER_NAME;
9034	#ifdef MULTI_INSTANCE_SUPPORT
9035	vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9036	&vvp9_vf_provider, pbi);
9037	vf_reg_provider(&vvp9_vf_prov);
9038	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9039	if (pbi->frame_dur != 0) {
9040	if (!is_reset)
9041	vf_notify_receiver(pbi->provider_name,
9042	VFRAME_EVENT_PROVIDER_FR_HINT,
9043	(void *)
9044	((unsigned long)pbi->frame_dur));
9045	}
9046	#else
9047	vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9048	pbi);
9049	vf_reg_provider(&vvp9_vf_prov);
9050	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9051	if (!is_reset)
9052	vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9053	(void *)((unsigned long)pbi->frame_dur));
9054	#endif
9055	pbi->stat |= STAT_VF_HOOK;
9056
9057	pbi->timer.data = (ulong)pbi;
9058	pbi->timer.function = vvp9_put_timer_func;
9059	pbi->timer.expires = jiffies + PUT_INTERVAL;
9060
9061	pbi->stat |= STAT_VDEC_RUN;
9062
9063	add_timer(&pbi->timer);
9064
9065	pbi->stat |= STAT_TIMER_ARM;
9066
9067	amhevc_start();
9068
9069	pbi->init_flag = 1;
9070	pbi->process_busy = 0;
9071	pr_info("%d, vvp9_init, RP=0x%x\n",
9072	__LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9073	return 0;
9074	}
9075
9076	static int vmvp9_stop(struct VP9Decoder_s *pbi)
9077	{
9078	pbi->init_flag = 0;
9079
9080	if (pbi->stat & STAT_VDEC_RUN) {
9081	amhevc_stop();
9082	pbi->stat &= ~STAT_VDEC_RUN;
9083	}
9084	if (pbi->stat & STAT_ISR_REG) {
9085	vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9086	pbi->stat &= ~STAT_ISR_REG;
9087	}
9088	if (pbi->stat & STAT_TIMER_ARM) {
9089	del_timer_sync(&pbi->timer);
9090	pbi->stat &= ~STAT_TIMER_ARM;
9091	}
9092
9093	if (pbi->stat & STAT_VF_HOOK) {
9094	if (!is_reset)
9095	vf_notify_receiver(pbi->provider_name,
9096	VFRAME_EVENT_PROVIDER_FR_END_HINT,
9097	NULL);
9098
9099	vf_unreg_provider(&vvp9_vf_prov);
9100	pbi->stat &= ~STAT_VF_HOOK;
9101	}
9102	vp9_local_uninit(pbi);
9103	reset_process_time(pbi);
9104	cancel_work_sync(&pbi->work);
9105	#ifdef SUPPORT_FB_DECODING
9106	if (pbi->used_stage_buf_num > 0)
9107	cancel_work_sync(&pbi->s1_work);
9108	#endif
9109	cancel_work_sync(&pbi->set_clk_work);
9110	uninit_mmu_buffers(pbi);
9111	if (pbi->fw)
9112	vfree(pbi->fw);
9113	pbi->fw = NULL;
9114	return 0;
9115	}
9116
9117	static int vvp9_stop(struct VP9Decoder_s *pbi)
9118	{
9119
9120	pbi->init_flag = 0;
9121	pbi->first_sc_checked = 0;
9122	if (pbi->stat & STAT_VDEC_RUN) {
9123	amhevc_stop();
9124	pbi->stat &= ~STAT_VDEC_RUN;
9125	}
9126
9127	if (pbi->stat & STAT_ISR_REG) {
9128	#ifdef MULTI_INSTANCE_SUPPORT
9129	if (!pbi->m_ins_flag)
9130	#endif
9131	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9132	vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9133	pbi->stat &= ~STAT_ISR_REG;
9134	}
9135
9136	if (pbi->stat & STAT_TIMER_ARM) {
9137	del_timer_sync(&pbi->timer);
9138	pbi->stat &= ~STAT_TIMER_ARM;
9139	}
9140
9141	if (pbi->stat & STAT_VF_HOOK) {
9142	if (!is_reset)
9143	vf_notify_receiver(pbi->provider_name,
9144	VFRAME_EVENT_PROVIDER_FR_END_HINT,
9145	NULL);
9146
9147	vf_unreg_provider(&vvp9_vf_prov);
9148	pbi->stat &= ~STAT_VF_HOOK;
9149	}
9150	vp9_local_uninit(pbi);
9151
9152	cancel_work_sync(&pbi->set_clk_work);
9153	#ifdef MULTI_INSTANCE_SUPPORT
9154	if (pbi->m_ins_flag) {
9155	#ifdef SUPPORT_FB_DECODING
9156	if (pbi->used_stage_buf_num > 0)
9157	cancel_work_sync(&pbi->s1_work);
9158	#endif
9159	cancel_work_sync(&pbi->work);
9160	} else
9161	amhevc_disable();
9162	#else
9163	amhevc_disable();
9164	#endif
9165	uninit_mmu_buffers(pbi);
9166
9167	vfree(pbi->fw);
9168	pbi->fw = NULL;
9169	return 0;
9170	}
9171	static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9172	{
9173	int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9174	CODEC_MM_FLAGS_TVP : 0;
9175	int buf_size = 48;
9176
9177	if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9178	(pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9179	buf_size = 12;
9180	} else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9181	(pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9182	buf_size = 4;
9183	}
9184	pbi->need_cache_size = buf_size * SZ_1M;
9185	pbi->sc_start_time = get_jiffies_64();
9186	if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9187	pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9188	pbi->index, FRAME_BUFFERS,
9189	pbi->need_cache_size,
9190	tvp_flag
9191	);
9192	if (!pbi->mmu_box) {
9193	pr_err("vp9 alloc mmu box failed!!\n");
9194	return -1;
9195	}
9196	}
9197	pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9198	DRIVER_NAME,
9199	pbi->index,
9200	MAX_BMMU_BUFFER_NUM,
9201	4 + PAGE_SHIFT,
9202	CODEC_MM_FLAGS_CMA_CLEAR |
9203	CODEC_MM_FLAGS_FOR_VDECODER |
9204	tvp_flag);
9205	if (!pbi->bmmu_box) {
9206	pr_err("vp9 alloc bmmu box failed!!\n");
9207	return -1;
9208	}
9209	return 0;
9210	}
9211
9212	static struct VP9Decoder_s *gHevc;
9213
9214	static int amvdec_vp9_probe(struct platform_device *pdev)
9215	{
9216	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9217	struct BUF_s BUF[MAX_BUF_NUM];
9218	struct VP9Decoder_s *pbi;
9219	int ret;
9220	#ifndef MULTI_INSTANCE_SUPPORT
9221	int i;
9222	#endif
9223	pr_debug("%s\n", __func__);
9224
9225	mutex_lock(&vvp9_mutex);
9226	pbi = vmalloc(sizeof(struct VP9Decoder_s));
9227	if (pbi == NULL) {
9228	pr_info("\namvdec_vp9 device data allocation failed\n");
9229	mutex_unlock(&vvp9_mutex);
9230	return -ENOMEM;
9231	}
9232
9233	gHevc = pbi;
9234	memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9235	memset(pbi, 0, sizeof(struct VP9Decoder_s));
9236	memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9237
9238	pbi->init_flag = 0;
9239	pbi->first_sc_checked= 0;
9240	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9241	vp9_max_pic_w = 8192;
9242	vp9_max_pic_h = 4608;
9243	}
9244	pbi->max_pic_w = vp9_max_pic_w;
9245	pbi->max_pic_h = vp9_max_pic_h;
9246
9247	#ifdef MULTI_INSTANCE_SUPPORT
9248	pbi->eos = 0;
9249	pbi->start_process_time = 0;
9250	pbi->timeout_num = 0;
9251	#endif
9252	pbi->fatal_error = 0;
9253	pbi->show_frame_num = 0;
9254	if (pdata == NULL) {
9255	pr_info("\namvdec_vp9 memory resource undefined.\n");
9256	vfree(pbi);
9257	mutex_unlock(&vvp9_mutex);
9258	return -EFAULT;
9259	}
9260	pbi->m_ins_flag = 0;
9261	#ifdef MULTI_INSTANCE_SUPPORT
9262	pbi->platform_dev = pdev;
9263	platform_set_drvdata(pdev, pdata);
9264	#endif
9265	pbi->double_write_mode = double_write_mode;
9266	pbi->mmu_enable = 1;
9267	if (amvdec_vp9_mmu_init(pbi) < 0) {
9268	vfree(pbi);
9269	mutex_unlock(&vvp9_mutex);
9270	pr_err("vp9 alloc bmmu box failed!!\n");
9271	return -1;
9272	}
9273
9274	ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9275	work_buf_size, DRIVER_NAME, &pdata->mem_start);
9276	if (ret < 0) {
9277	uninit_mmu_buffers(pbi);
9278	vfree(pbi);
9279	mutex_unlock(&vvp9_mutex);
9280	return ret;
9281	}
9282	pbi->buf_size = work_buf_size;
9283
9284	#ifdef MULTI_INSTANCE_SUPPORT
9285	pbi->buf_start = pdata->mem_start;
9286	#else
9287	if (!pbi->mmu_enable)
9288	pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9289
9290	for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9291	amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9292	#endif
9293
9294
9295	if (debug) {
9296	pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9297	pdata->mem_start, pbi->buf_size);
9298	}
9299
9300	if (pdata->sys_info)
9301	pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9302	else {
9303	pbi->vvp9_amstream_dec_info.width = 0;
9304	pbi->vvp9_amstream_dec_info.height = 0;
9305	pbi->vvp9_amstream_dec_info.rate = 30;
9306	}
9307	pbi->no_head = no_head;
9308	#ifdef MULTI_INSTANCE_SUPPORT
9309	pbi->cma_dev = pdata->cma_dev;
9310	#else
9311	cma_dev = pdata->cma_dev;
9312	#endif
9313
9314	#ifdef MULTI_INSTANCE_SUPPORT
9315	pdata->private = pbi;
9316	pdata->dec_status = vvp9_dec_status;
9317	pdata->set_isreset = vvp9_set_isreset;
9318	is_reset = 0;
9319	if (vvp9_init(pdata) < 0) {
9320	#else
9321	if (vvp9_init(pbi) < 0) {
9322	#endif
9323	pr_info("\namvdec_vp9 init failed.\n");
9324	vp9_local_uninit(pbi);
9325	uninit_mmu_buffers(pbi);
9326	vfree(pbi);
9327	pdata->dec_status = NULL;
9328	mutex_unlock(&vvp9_mutex);
9329	return -ENODEV;
9330	}
9331	/*set the max clk for smooth playing...*/
9332	hevc_source_changed(VFORMAT_VP9,
9333	4096, 2048, 60);
9334	mutex_unlock(&vvp9_mutex);
9335
9336	return 0;
9337	}
9338
9339	static int amvdec_vp9_remove(struct platform_device *pdev)
9340	{
9341	struct VP9Decoder_s *pbi = gHevc;
9342	struct vdec_s *vdec = hw_to_vdec(pbi);
9343	int i;
9344
9345	if (debug)
9346	pr_info("amvdec_vp9_remove\n");
9347
9348	mutex_lock(&vvp9_mutex);
9349
9350	vvp9_stop(pbi);
9351
9352	hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9353
9354	if (vdec->parallel_dec == 1) {
9355	for (i = 0; i < FRAME_BUFFERS; i++) {
9356	vdec->free_canvas_ex(pbi->common.buffer_pool->
9357	frame_bufs[i].buf.y_canvas_index, vdec->id);
9358	vdec->free_canvas_ex(pbi->common.buffer_pool->
9359	frame_bufs[i].buf.uv_canvas_index, vdec->id);
9360	}
9361	}
9362
9363	#ifdef DEBUG_PTS
9364	pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9365	pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9366	#endif
9367	mem_map_mode = 0;
9368
9369	vfree(pbi);
9370	mutex_unlock(&vvp9_mutex);
9371
9372	return 0;
9373	}
9374
9375	/****************************************/
9376	#ifdef CONFIG_PM
9377	static int vp9_suspend(struct device *dev)
9378	{
9379	amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9380	return 0;
9381	}
9382
9383	static int vp9_resume(struct device *dev)
9384	{
9385	amhevc_resume(to_platform_device(dev));
9386	return 0;
9387	}
9388
9389	static const struct dev_pm_ops vp9_pm_ops = {
9390	SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9391	};
9392	#endif
9393
9394	static struct platform_driver amvdec_vp9_driver = {
9395	.probe = amvdec_vp9_probe,
9396	.remove = amvdec_vp9_remove,
9397	.driver = {
9398	.name = DRIVER_NAME,
9399	#ifdef CONFIG_PM
9400	.pm = &vp9_pm_ops,
9401	#endif
9402	}
9403	};
9404
9405	static struct codec_profile_t amvdec_vp9_profile = {
9406	.name = "vp9",
9407	.profile = ""
9408	};
9409
9410	static struct codec_profile_t amvdec_vp9_profile_mult;
9411
9412	static unsigned char get_data_check_sum
9413	(struct VP9Decoder_s *pbi, int size)
9414	{
9415	int jj;
9416	int sum = 0;
9417	u8 *data = NULL;
9418
9419	if (!pbi->chunk->block->is_mapped)
9420	data = codec_mm_vmap(pbi->chunk->block->start +
9421	pbi->chunk->offset, size);
9422	else
9423	data = ((u8 *)pbi->chunk->block->start_virt) +
9424	pbi->chunk->offset;
9425
9426	for (jj = 0; jj < size; jj++)
9427	sum += data[jj];
9428
9429	if (!pbi->chunk->block->is_mapped)
9430	codec_mm_unmap_phyaddr(data);
9431	return sum;
9432	}
9433
9434	static void dump_data(struct VP9Decoder_s *pbi, int size)
9435	{
9436	int jj;
9437	u8 *data = NULL;
9438	int padding_size = pbi->chunk->offset &
9439	(VDEC_FIFO_ALIGN - 1);
9440
9441	if (!pbi->chunk->block->is_mapped)
9442	data = codec_mm_vmap(pbi->chunk->block->start +
9443	pbi->chunk->offset, size);
9444	else
9445	data = ((u8 *)pbi->chunk->block->start_virt) +
9446	pbi->chunk->offset;
9447
9448	vp9_print(pbi, 0, "padding: ");
9449	for (jj = padding_size; jj > 0; jj--)
9450	vp9_print_cont(pbi,
9451	0,
9452	"%02x ", *(data - jj));
9453	vp9_print_cont(pbi, 0, "data adr %p\n",
9454	data);
9455
9456	for (jj = 0; jj < size; jj++) {
9457	if ((jj & 0xf) == 0)
9458	vp9_print(pbi,
9459	0,
9460	"%06x:", jj);
9461	vp9_print_cont(pbi,
9462	0,
9463	"%02x ", data[jj]);
9464	if (((jj + 1) & 0xf) == 0)
9465	vp9_print(pbi,
9466	0,
9467	"\n");
9468	}
9469	vp9_print(pbi,
9470	0,
9471	"\n");
9472
9473	if (!pbi->chunk->block->is_mapped)
9474	codec_mm_unmap_phyaddr(data);
9475	}
9476
9477	static void vp9_work(struct work_struct *work)
9478	{
9479	struct VP9Decoder_s *pbi = container_of(work,
9480	struct VP9Decoder_s, work);
9481	struct vdec_s *vdec = hw_to_vdec(pbi);
9482	/* finished decoding one frame or error,
9483	* notify vdec core to switch context
9484	*/
9485	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9486	"%s dec_result %d %x %x %x\n",
9487	__func__,
9488	pbi->dec_result,
9489	READ_VREG(HEVC_STREAM_LEVEL),
9490	READ_VREG(HEVC_STREAM_WR_PTR),
9491	READ_VREG(HEVC_STREAM_RD_PTR));
9492
9493	if (pbi->dec_result == DEC_INIT_PICLIST) {
9494	init_pic_list(pbi);
9495	pbi->pic_list_init_done = true;
9496	return;
9497	}
9498
9499	if (pbi->dec_result == DEC_V4L2_CONTINUE_DECODING) {
9500	struct aml_vcodec_ctx *ctx =
9501	(struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9502
9503	if (ctx->param_sets_from_ucode) {
9504	reset_process_time(pbi);
9505	if (wait_event_interruptible_timeout(ctx->wq,
9506	ctx->v4l_codec_ready,
9507	msecs_to_jiffies(500)) < 0)
9508	return;
9509	}
9510
9511	continue_decoding(pbi);
9512	pbi->postproc_done = 0;
9513	pbi->process_busy = 0;
9514
9515	return;
9516	}
9517
9518	if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9519	(pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9520	&& (hw_to_vdec(pbi)->next_status !=
9521	VDEC_STATUS_DISCONNECTED)) {
9522	if (!vdec_has_more_input(vdec)) {
9523	pbi->dec_result = DEC_RESULT_EOS;
9524	vdec_schedule_work(&pbi->work);
9525	return;
9526	}
9527
9528	if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9529	vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9530	"%s DEC_RESULT_GET_DATA %x %x %x\n",
9531	__func__,
9532	READ_VREG(HEVC_STREAM_LEVEL),
9533	READ_VREG(HEVC_STREAM_WR_PTR),
9534	READ_VREG(HEVC_STREAM_RD_PTR));
9535	vdec_vframe_dirty(vdec, pbi->chunk);
9536	vdec_clean_input(vdec);
9537	}
9538
9539	if (get_free_buf_count(pbi) >=
9540	run_ready_min_buf_num) {
9541	int r;
9542	int decode_size;
9543	r = vdec_prepare_input(vdec, &pbi->chunk);
9544	if (r < 0) {
9545	pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9546
9547	vp9_print(pbi,
9548	PRINT_FLAG_VDEC_DETAIL,
9549	"amvdec_vh265: Insufficient data\n");
9550
9551	vdec_schedule_work(&pbi->work);
9552	return;
9553	}
9554	pbi->dec_result = DEC_RESULT_NONE;
9555	vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9556	"%s: chunk size 0x%x sum 0x%x\n",
9557	__func__, r,
9558	(debug & PRINT_FLAG_VDEC_STATUS) ?
9559	get_data_check_sum(pbi, r) : 0
9560	);
9561
9562	if (debug & PRINT_FLAG_VDEC_DATA)
9563	dump_data(pbi, pbi->chunk->size);
9564
9565	decode_size = pbi->chunk->size +
9566	(pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9567
9568	WRITE_VREG(HEVC_DECODE_SIZE,
9569	READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9570
9571	vdec_enable_input(vdec);
9572
9573	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9574
9575	start_process_time(pbi);
9576
9577	} else{
9578	pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9579
9580	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9581	"amvdec_vh265: Insufficient data\n");
9582
9583	vdec_schedule_work(&pbi->work);
9584	}
9585	return;
9586	} else if (pbi->dec_result == DEC_RESULT_DONE) {
9587	#ifdef SUPPORT_FB_DECODING
9588	if (pbi->used_stage_buf_num > 0) {
9589	#ifndef FB_DECODING_TEST_SCHEDULE
9590	if (!is_s2_decoding_finished(pbi)) {
9591	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9592	"s2 decoding not done, check again later\n");
9593	vdec_schedule_work(&pbi->work);
9594	}
9595	#endif
9596	inc_s2_pos(pbi);
9597	if (mcrcc_cache_alg_flag)
9598	dump_hit_rate(pbi);
9599	}
9600	#endif
9601	/* if (!pbi->ctx_valid)
9602	pbi->ctx_valid = 1; */
9603	pbi->slice_idx++;
9604	pbi->frame_count++;
9605	pbi->process_state = PROC_STATE_INIT;
9606	decode_frame_count[pbi->index] = pbi->frame_count;
9607
9608	if (pbi->mmu_enable)
9609	pbi->used_4k_num =
9610	(READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9611	vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9612	"%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9613	__func__,
9614	pbi->frame_count,
9615	pbi->dec_result,
9616	READ_VREG(HEVC_STREAM_LEVEL),
9617	READ_VREG(HEVC_STREAM_WR_PTR),
9618	READ_VREG(HEVC_STREAM_RD_PTR),
9619	READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9620	READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9621	pbi->start_shift_bytes
9622	);
9623	vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9624	} else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9625	/*
9626	stream base: stream buf empty or timeout
9627	frame base: vdec_prepare_input fail
9628	*/
9629	if (!vdec_has_more_input(vdec)) {
9630	pbi->dec_result = DEC_RESULT_EOS;
9631	vdec_schedule_work(&pbi->work);
9632	return;
9633	}
9634	} else if (pbi->dec_result == DEC_RESULT_EOS) {
9635	vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9636	"%s: end of stream\n",
9637	__func__);
9638	pbi->eos = 1;
9639	vp9_bufmgr_postproc(pbi);
9640
9641	if (pbi->is_used_v4l)
9642	notify_v4l_eos(hw_to_vdec(pbi));
9643
9644	vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9645	} else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9646	vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9647	"%s: force exit\n",
9648	__func__);
9649	if (pbi->stat & STAT_VDEC_RUN) {
9650	amhevc_stop();
9651	pbi->stat &= ~STAT_VDEC_RUN;
9652	}
9653
9654	if (pbi->stat & STAT_ISR_REG) {
9655	#ifdef MULTI_INSTANCE_SUPPORT
9656	if (!pbi->m_ins_flag)
9657	#endif
9658	WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9659	vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9660	pbi->stat &= ~STAT_ISR_REG;
9661	}
9662	}
9663	if (pbi->stat & STAT_VDEC_RUN) {
9664	amhevc_stop();
9665	pbi->stat &= ~STAT_VDEC_RUN;
9666	}
9667
9668	if (pbi->stat & STAT_TIMER_ARM) {
9669	del_timer_sync(&pbi->timer);
9670	pbi->stat &= ~STAT_TIMER_ARM;
9671	}
9672	/* mark itself has all HW resource released and input released */
9673	#ifdef SUPPORT_FB_DECODING
9674	if (pbi->used_stage_buf_num > 0)
9675	vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9676	else
9677	vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9678	| CORE_MASK_HEVC
9679	| CORE_MASK_HEVC_FRONT
9680	| CORE_MASK_HEVC_BACK
9681	);
9682	#else
9683	if (vdec->parallel_dec == 1)
9684	vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9685	else
9686	vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9687	| CORE_MASK_HEVC);
9688	#endif
9689	trigger_schedule(pbi);
9690	}
9691
9692	static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9693	{
9694	/* new to do ... */
9695	#if (!defined SUPPORT_FB_DECODING)
9696	vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9697	#elif (defined FB_DECODING_TEST_SCHEDULE)
9698	vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9699	#else
9700	if (pbi->used_stage_buf_num > 0)
9701	vvp9_prot_init(pbi, HW_MASK_FRONT);
9702	else
9703	vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9704	#endif
9705	return 0;
9706	}
9707	static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9708	{
9709	struct VP9Decoder_s *pbi =
9710	(struct VP9Decoder_s *)vdec->private;
9711	int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9712	CODEC_MM_FLAGS_TVP : 0;
9713	unsigned long ret = 0;
9714
9715	if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9716	return ret;
9717	if (!pbi->first_sc_checked && pbi->mmu_enable) {
9718	int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9719	pbi->first_sc_checked = 1;
9720	vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9721	size, (pbi->need_cache_size >> PAGE_SHIFT),
9722	(int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9723	}
9724
9725	#ifdef SUPPORT_FB_DECODING
9726	if (pbi->used_stage_buf_num > 0) {
9727	if (mask & CORE_MASK_HEVC_FRONT) {
9728	if (get_free_stage_buf_num(pbi) > 0
9729	&& mv_buf_available(pbi))
9730	ret |= CORE_MASK_HEVC_FRONT;
9731	}
9732	if (mask & CORE_MASK_HEVC_BACK) {
9733	if (s2_buf_available(pbi) &&
9734	(get_free_buf_count(pbi) >=
9735	run_ready_min_buf_num)) {
9736	ret |= CORE_MASK_HEVC_BACK;
9737	pbi->back_not_run_ready = 0;
9738	} else
9739	pbi->back_not_run_ready = 1;
9740	#if 0
9741	if (get_free_buf_count(pbi) <
9742	run_ready_min_buf_num)
9743	dump_pic_list(pbi);
9744	#endif
9745	}
9746	} else if (get_free_buf_count(pbi) >=
9747	run_ready_min_buf_num)
9748	ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9749	| CORE_MASK_HEVC_FRONT
9750	| CORE_MASK_HEVC_BACK;
9751
9752	if (ret & CORE_MASK_HEVC_FRONT)
9753	not_run_ready[pbi->index] = 0;
9754	else
9755	not_run_ready[pbi->index]++;
9756
9757	if (ret & CORE_MASK_HEVC_BACK)
9758	not_run2_ready[pbi->index] = 0;
9759	else
9760	not_run2_ready[pbi->index]++;
9761
9762	vp9_print(pbi,
9763	PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9764	__func__, mask, ret,
9765	get_free_stage_buf_num(pbi),
9766	mv_buf_available(pbi),
9767	s2_buf_available(pbi),
9768	get_free_buf_count(pbi)
9769	);
9770
9771	return ret;
9772
9773	#else
9774	if (get_free_buf_count(pbi) >=
9775	run_ready_min_buf_num) {
9776	if (vdec->parallel_dec == 1)
9777	ret = CORE_MASK_HEVC;
9778	else
9779	ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9780	}
9781
9782	if (pbi->is_used_v4l) {
9783	struct aml_vcodec_ctx *ctx =
9784	(struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9785
9786	if (ctx->param_sets_from_ucode &&
9787	!ctx->v4l_codec_ready &&
9788	pbi->v4l_params_parsed) {
9789	ret = 0; /*the params has parsed.*/
9790	} else if (!ctx->v4l_codec_dpb_ready) {
9791	if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
9792	run_ready_min_buf_num)
9793	ret = 0;
9794	}
9795	}
9796
9797	if (ret)
9798	not_run_ready[pbi->index] = 0;
9799	else
9800	not_run_ready[pbi->index]++;
9801
9802	vp9_print(pbi,
9803	PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9804	__func__, mask, ret);
9805	return ret;
9806	#endif
9807	}
9808
9809	static void run_front(struct vdec_s *vdec)
9810	{
9811	struct VP9Decoder_s *pbi =
9812	(struct VP9Decoder_s *)vdec->private;
9813	int ret, size;
9814
9815	run_count[pbi->index]++;
9816	/* pbi->chunk = vdec_prepare_input(vdec); */
9817	#if (!defined SUPPORT_FB_DECODING)
9818	hevc_reset_core(vdec);
9819	#elif (defined FB_DECODING_TEST_SCHEDULE)
9820	hevc_reset_core(vdec);
9821	#else
9822	if (pbi->used_stage_buf_num > 0)
9823	fb_reset_core(vdec, HW_MASK_FRONT);
9824	else
9825	hevc_reset_core(vdec);
9826	#endif
9827
9828	size = vdec_prepare_input(vdec, &pbi->chunk);
9829	if (size < 0) {
9830	input_empty[pbi->index]++;
9831
9832	pbi->dec_result = DEC_RESULT_AGAIN;
9833
9834	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9835	"ammvdec_vh265: Insufficient data\n");
9836
9837	vdec_schedule_work(&pbi->work);
9838	return;
9839	}
9840
9841	input_empty[pbi->index] = 0;
9842	pbi->dec_result = DEC_RESULT_NONE;
9843	pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9844
9845	if (debug & PRINT_FLAG_VDEC_STATUS) {
9846	int ii;
9847	vp9_print(pbi, 0,
9848	"%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9849	__func__,
9850	pbi->frame_count, size,
9851	pbi->chunk ? pbi->chunk->size : 0,
9852	pbi->chunk ? pbi->chunk->offset : 0,
9853	pbi->chunk ? ((vdec_frame_based(vdec) &&
9854	(debug & PRINT_FLAG_VDEC_STATUS)) ?
9855	get_data_check_sum(pbi, size) : 0) : 0,
9856	READ_VREG(HEVC_STREAM_START_ADDR),
9857	READ_VREG(HEVC_STREAM_END_ADDR),
9858	READ_VREG(HEVC_STREAM_LEVEL),
9859	READ_VREG(HEVC_STREAM_WR_PTR),
9860	READ_VREG(HEVC_STREAM_RD_PTR),
9861	pbi->start_shift_bytes);
9862	if (vdec_frame_based(vdec) && pbi->chunk) {
9863	u8 *data = NULL;
9864
9865	if (!pbi->chunk->block->is_mapped)
9866	data = codec_mm_vmap(pbi->chunk->block->start +
9867	pbi->chunk->offset, 8);
9868	else
9869	data = ((u8 *)pbi->chunk->block->start_virt) +
9870	pbi->chunk->offset;
9871
9872	vp9_print_cont(pbi, 0, "data adr %p:",
9873	data);
9874	for (ii = 0; ii < 8; ii++)
9875	vp9_print_cont(pbi, 0, "%02x ",
9876	data[ii]);
9877
9878	if (!pbi->chunk->block->is_mapped)
9879	codec_mm_unmap_phyaddr(data);
9880	}
9881	vp9_print_cont(pbi, 0, "\r\n");
9882	}
9883	if (vdec->mc_loaded) {
9884	/*firmware have load before,
9885	and not changes to another.
9886	ignore reload.
9887	*/
9888	} else {
9889	ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9890	if (ret < 0) {
9891	amhevc_disable();
9892	vp9_print(pbi, PRINT_FLAG_ERROR,
9893	"VP9: the %s fw loading failed, err: %x\n",
9894	tee_enabled() ? "TEE" : "local", ret);
9895	pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9896	vdec_schedule_work(&pbi->work);
9897	return;
9898	}
9899	vdec->mc_loaded = 1;
9900	vdec->mc_type = VFORMAT_VP9;
9901	}
9902
9903	if (vp9_hw_ctx_restore(pbi) < 0) {
9904	vdec_schedule_work(&pbi->work);
9905	return;
9906	}
9907
9908	vdec_enable_input(vdec);
9909
9910	WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9911
9912	if (vdec_frame_based(vdec)) {
9913	if (debug & PRINT_FLAG_VDEC_DATA)
9914	dump_data(pbi, pbi->chunk->size);
9915
9916	WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9917	size = pbi->chunk->size +
9918	(pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9919	}
9920	WRITE_VREG(HEVC_DECODE_SIZE, size);
9921	WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9922	pbi->init_flag = 1;
9923
9924	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9925	"%s: start hevc (%x %x %x)\n",
9926	__func__,
9927	READ_VREG(HEVC_DEC_STATUS_REG),
9928	READ_VREG(HEVC_MPC_E),
9929	READ_VREG(HEVC_MPSR));
9930
9931	start_process_time(pbi);
9932	mod_timer(&pbi->timer, jiffies);
9933	pbi->stat |= STAT_TIMER_ARM;
9934	pbi->stat |= STAT_ISR_REG;
9935	amhevc_start();
9936	pbi->stat |= STAT_VDEC_RUN;
9937	}
9938
9939	#ifdef SUPPORT_FB_DECODING
9940	static void mpred_process(struct VP9Decoder_s *pbi)
9941	{
9942	union param_u *params = &pbi->s1_param;
9943	unsigned char use_prev_frame_mvs =
9944	!params->p.error_resilient_mode &&
9945	params->p.width == pbi->s1_width &&
9946	params->p.height == pbi->s1_height &&
9947	!pbi->s1_intra_only &&
9948	pbi->s1_last_show_frame &&
9949	(pbi->s1_frame_type != KEY_FRAME);
9950	pbi->s1_width = params->p.width;
9951	pbi->s1_height = params->p.height;
9952	pbi->s1_frame_type = params->p.frame_type;
9953	pbi->s1_intra_only =
9954	(params->p.show_frame ||
9955	params->p.show_existing_frame)
9956	? 0 : params->p.intra_only;
9957	if ((pbi->s1_frame_type != KEY_FRAME)
9958	&& (!pbi->s1_intra_only)) {
9959	unsigned int data32;
9960	int mpred_mv_rd_end_addr;
9961
9962	mpred_mv_rd_end_addr =
9963	pbi->s1_mpred_mv_wr_start_addr_pre
9964	+ (pbi->lcu_total * MV_MEM_UNIT);
9965
9966	WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
9967	WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
9968	pbi->work_space_buf->
9969	mpred_above.buf_start);
9970
9971	data32 = READ_VREG(HEVC_MPRED_CTRL4);
9972
9973	data32 &= (~(1 << 6));
9974	data32 |= (use_prev_frame_mvs << 6);
9975	WRITE_VREG(HEVC_MPRED_CTRL4, data32);
9976
9977	WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
9978	pbi->s1_mpred_mv_wr_start_addr);
9979	WRITE_VREG(HEVC_MPRED_MV_WPTR,
9980	pbi->s1_mpred_mv_wr_start_addr);
9981
9982	WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
9983	pbi->s1_mpred_mv_wr_start_addr_pre);
9984	WRITE_VREG(HEVC_MPRED_MV_RPTR,
9985	pbi->s1_mpred_mv_wr_start_addr_pre);
9986
9987	WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
9988	mpred_mv_rd_end_addr);
9989
9990	} else
9991	clear_mpred_hw(pbi);
9992
9993	if (!params->p.show_existing_frame) {
9994	pbi->s1_mpred_mv_wr_start_addr_pre =
9995	pbi->s1_mpred_mv_wr_start_addr;
9996	pbi->s1_last_show_frame =
9997	params->p.show_frame;
9998	if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
9999	put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
10000	pbi->s1_mv_buf_index_pre_pre =
10001	pbi->s1_mv_buf_index_pre;
10002	pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10003	} else
10004	put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10005	}
10006
10007	static void vp9_s1_work(struct work_struct *s1_work)
10008	{
10009	struct VP9Decoder_s *pbi = container_of(s1_work,
10010	struct VP9Decoder_s, s1_work);
10011	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10012	"%s dec_s1_result %d\n",
10013	__func__,
10014	pbi->dec_s1_result);
10015
10016	#ifdef FB_DECODING_TEST_SCHEDULE
10017	if (pbi->dec_s1_result ==
10018	DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10019	pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10020	WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10021	}
10022	#endif
10023	if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10024	pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10025
10026	vdec_core_finish_run(hw_to_vdec(pbi),
10027	CORE_MASK_HEVC_FRONT);
10028
10029	trigger_schedule(pbi);
10030	/*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10031	}
10032
10033	}
10034
10035	static void run_back(struct vdec_s *vdec)
10036	{
10037	struct VP9Decoder_s *pbi =
10038	(struct VP9Decoder_s *)vdec->private;
10039	int i;
10040	run2_count[pbi->index]++;
10041	if (debug & PRINT_FLAG_VDEC_STATUS) {
10042	vp9_print(pbi, 0,
10043	"%s", __func__);
10044	}
10045	pbi->run2_busy = 1;
10046	#ifndef FB_DECODING_TEST_SCHEDULE
10047	fb_reset_core(vdec, HW_MASK_BACK);
10048
10049	vvp9_prot_init(pbi, HW_MASK_BACK);
10050	#endif
10051	vp9_recycle_mmu_buf_tail(pbi);
10052
10053	if (pbi->frame_count > 0)
10054	vp9_bufmgr_postproc(pbi);
10055
10056	if (get_s2_buf(pbi) >= 0) {
10057	for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10058	int ii;
10059	for (ii = 0; ii < 4; ii++)
10060	vp9_param.l.data[i + ii] =
10061	pbi->s2_buf->rpm[i + 3 - ii];
10062	}
10063	#ifndef FB_DECODING_TEST_SCHEDULE
10064	WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10065	pbi->stage_mmu_map_phy_addr +
10066	pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10067	#endif
10068	continue_decoding(pbi);
10069	}
10070	pbi->run2_busy = 0;
10071	}
10072	#endif
10073
10074	static void run(struct vdec_s *vdec, unsigned long mask,
10075	void (*callback)(struct vdec_s *, void *), void *arg)
10076	{
10077	struct VP9Decoder_s *pbi =
10078	(struct VP9Decoder_s *)vdec->private;
10079
10080	vp9_print(pbi,
10081	PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10082	__func__, mask);
10083
10084	run_count[pbi->index]++;
10085	pbi->vdec_cb_arg = arg;
10086	pbi->vdec_cb = callback;
10087	#ifdef SUPPORT_FB_DECODING
10088	if ((mask & CORE_MASK_HEVC) ||
10089	(mask & CORE_MASK_HEVC_FRONT))
10090	run_front(vdec);
10091
10092	if ((pbi->used_stage_buf_num > 0)
10093	&& (mask & CORE_MASK_HEVC_BACK))
10094	run_back(vdec);
10095	#else
10096	run_front(vdec);
10097	#endif
10098	}
10099
10100	static void init_frame_bufs(struct VP9Decoder_s *pbi)
10101	{
10102	struct vdec_s *vdec = hw_to_vdec(pbi);
10103	struct VP9_Common_s *const cm = &pbi->common;
10104	struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10105	int i;
10106
10107	for (i = 0; i < pbi->used_buf_num; ++i) {
10108	frame_bufs[i].ref_count = 0;
10109	frame_bufs[i].buf.vf_ref = 0;
10110	frame_bufs[i].buf.decode_idx = 0;
10111	frame_bufs[i].buf.cma_alloc_addr = 0;
10112	frame_bufs[i].buf.index = i;
10113	}
10114
10115	if (vdec->parallel_dec == 1) {
10116	for (i = 0; i < FRAME_BUFFERS; i++) {
10117	vdec->free_canvas_ex
10118	(pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10119	vdec->id);
10120	vdec->free_canvas_ex
10121	(pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10122	vdec->id);
10123	}
10124	}
10125	}
10126
10127	static void reset(struct vdec_s *vdec)
10128	{
10129
10130	struct VP9Decoder_s *pbi =
10131	(struct VP9Decoder_s *)vdec->private;
10132
10133	cancel_work_sync(&pbi->work);
10134	if (pbi->stat & STAT_VDEC_RUN) {
10135	amhevc_stop();
10136	pbi->stat &= ~STAT_VDEC_RUN;
10137	}
10138
10139	if (pbi->stat & STAT_TIMER_ARM) {
10140	del_timer_sync(&pbi->timer);
10141	pbi->stat &= ~STAT_TIMER_ARM;
10142	}
10143	pbi->dec_result = DEC_RESULT_NONE;
10144	reset_process_time(pbi);
10145	dealloc_mv_bufs(pbi);
10146	vp9_local_uninit(pbi);
10147	if (vvp9_local_init(pbi) < 0)
10148	vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10149	init_frame_bufs(pbi);
10150
10151	pbi->eos = 0;
10152
10153	vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10154	}
10155
10156	static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10157	{
10158	struct VP9Decoder_s *pbi =
10159	(struct VP9Decoder_s *)vdec->private;
10160	return vvp9_isr(0, pbi);
10161	}
10162
10163	static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10164	{
10165	struct VP9Decoder_s *pbi =
10166	(struct VP9Decoder_s *)vdec->private;
10167	return vvp9_isr_thread_fn(0, pbi);
10168	}
10169
10170	static void vp9_dump_state(struct vdec_s *vdec)
10171	{
10172	struct VP9Decoder_s *pbi =
10173	(struct VP9Decoder_s *)vdec->private;
10174	struct VP9_Common_s *const cm = &pbi->common;
10175	int i;
10176	vp9_print(pbi, 0, "====== %s\n", __func__);
10177
10178	vp9_print(pbi, 0,
10179	"width/height (%d/%d), used_buf_num %d\n",
10180	cm->width,
10181	cm->height,
10182	pbi->used_buf_num
10183	);
10184
10185	vp9_print(pbi, 0,
10186	"is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10187	input_frame_based(vdec),
10188	pbi->eos,
10189	pbi->dec_result,
10190	decode_frame_count[pbi->index],
10191	display_frame_count[pbi->index],
10192	run_count[pbi->index],
10193	not_run_ready[pbi->index],
10194	input_empty[pbi->index],
10195	pbi->low_latency_flag,
10196	pbi->no_head
10197	);
10198
10199	if (vf_get_receiver(vdec->vf_provider_name)) {
10200	enum receviver_start_e state =
10201	vf_notify_receiver(vdec->vf_provider_name,
10202	VFRAME_EVENT_PROVIDER_QUREY_STATE,
10203	NULL);
10204	vp9_print(pbi, 0,
10205	"\nreceiver(%s) state %d\n",
10206	vdec->vf_provider_name,
10207	state);
10208	}
10209
10210	vp9_print(pbi, 0,
10211	"%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10212	__func__,
10213	kfifo_len(&pbi->newframe_q),
10214	VF_POOL_SIZE,
10215	kfifo_len(&pbi->display_q),
10216	VF_POOL_SIZE,
10217	pbi->vf_pre_count,
10218	pbi->vf_get_count,
10219	pbi->vf_put_count,
10220	get_free_buf_count(pbi),
10221	run_ready_min_buf_num
10222	);
10223
10224	dump_pic_list(pbi);
10225
10226	for (i = 0; i < MAX_BUF_NUM; i++) {
10227	vp9_print(pbi, 0,
10228	"mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10229	i,
10230	pbi->m_mv_BUF[i].start_adr,
10231	pbi->m_mv_BUF[i].size,
10232	pbi->m_mv_BUF[i].used_flag);
10233	}
10234
10235	vp9_print(pbi, 0,
10236	"HEVC_DEC_STATUS_REG=0x%x\n",
10237	READ_VREG(HEVC_DEC_STATUS_REG));
10238	vp9_print(pbi, 0,
10239	"HEVC_MPC_E=0x%x\n",
10240	READ_VREG(HEVC_MPC_E));
10241	vp9_print(pbi, 0,
10242	"DECODE_MODE=0x%x\n",
10243	READ_VREG(DECODE_MODE));
10244	vp9_print(pbi, 0,
10245	"NAL_SEARCH_CTL=0x%x\n",
10246	READ_VREG(NAL_SEARCH_CTL));
10247	vp9_print(pbi, 0,
10248	"HEVC_PARSER_LCU_START=0x%x\n",
10249	READ_VREG(HEVC_PARSER_LCU_START));
10250	vp9_print(pbi, 0,
10251	"HEVC_DECODE_SIZE=0x%x\n",
10252	READ_VREG(HEVC_DECODE_SIZE));
10253	vp9_print(pbi, 0,
10254	"HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10255	READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10256	vp9_print(pbi, 0,
10257	"HEVC_STREAM_START_ADDR=0x%x\n",
10258	READ_VREG(HEVC_STREAM_START_ADDR));
10259	vp9_print(pbi, 0,
10260	"HEVC_STREAM_END_ADDR=0x%x\n",
10261	READ_VREG(HEVC_STREAM_END_ADDR));
10262	vp9_print(pbi, 0,
10263	"HEVC_STREAM_LEVEL=0x%x\n",
10264	READ_VREG(HEVC_STREAM_LEVEL));
10265	vp9_print(pbi, 0,
10266	"HEVC_STREAM_WR_PTR=0x%x\n",
10267	READ_VREG(HEVC_STREAM_WR_PTR));
10268	vp9_print(pbi, 0,
10269	"HEVC_STREAM_RD_PTR=0x%x\n",
10270	READ_VREG(HEVC_STREAM_RD_PTR));
10271	vp9_print(pbi, 0,
10272	"PARSER_VIDEO_RP=0x%x\n",
10273	READ_PARSER_REG(PARSER_VIDEO_RP));
10274	vp9_print(pbi, 0,
10275	"PARSER_VIDEO_WP=0x%x\n",
10276	READ_PARSER_REG(PARSER_VIDEO_WP));
10277
10278	if (input_frame_based(vdec) &&
10279	(debug & PRINT_FLAG_VDEC_DATA)
10280	) {
10281	int jj;
10282	if (pbi->chunk && pbi->chunk->block &&
10283	pbi->chunk->size > 0) {
10284	u8 *data = NULL;
10285
10286	if (!pbi->chunk->block->is_mapped)
10287	data = codec_mm_vmap(
10288	pbi->chunk->block->start +
10289	pbi->chunk->offset,
10290	pbi->chunk->size);
10291	else
10292	data = ((u8 *)pbi->chunk->block->start_virt)
10293	+ pbi->chunk->offset;
10294	vp9_print(pbi, 0,
10295	"frame data size 0x%x\n",
10296	pbi->chunk->size);
10297	for (jj = 0; jj < pbi->chunk->size; jj++) {
10298	if ((jj & 0xf) == 0)
10299	vp9_print(pbi, 0,
10300	"%06x:", jj);
10301	vp9_print_cont(pbi, 0,
10302	"%02x ", data[jj]);
10303	if (((jj + 1) & 0xf) == 0)
10304	vp9_print_cont(pbi, 0,
10305	"\n");
10306	}
10307
10308	if (!pbi->chunk->block->is_mapped)
10309	codec_mm_unmap_phyaddr(data);
10310	}
10311	}
10312
10313	}
10314
10315	static int ammvdec_vp9_probe(struct platform_device *pdev)
10316	{
10317	struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10318	int ret;
10319	int config_val;
10320	struct vframe_content_light_level_s content_light_level;
10321	struct vframe_master_display_colour_s vf_dp;
10322
10323	struct BUF_s BUF[MAX_BUF_NUM];
10324	struct VP9Decoder_s *pbi = NULL;
10325	pr_debug("%s\n", __func__);
10326
10327	if (pdata == NULL) {
10328	pr_info("\nammvdec_vp9 memory resource undefined.\n");
10329	return -EFAULT;
10330	}
10331	/*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10332	sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10333	memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10334	pbi = vmalloc(sizeof(struct VP9Decoder_s));
10335	if (pbi == NULL) {
10336	pr_info("\nammvdec_vp9 device data allocation failed\n");
10337	return -ENOMEM;
10338	}
10339	memset(pbi, 0, sizeof(struct VP9Decoder_s));
10340
10341	/* the ctx from v4l2 driver. */
10342	pbi->v4l2_ctx = pdata->private;
10343
10344	pdata->private = pbi;
10345	pdata->dec_status = vvp9_dec_status;
10346	/* pdata->set_trickmode = set_trickmode; */
10347	pdata->run_ready = run_ready;
10348	pdata->run = run;
10349	pdata->reset = reset;
10350	pdata->irq_handler = vp9_irq_cb;
10351	pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10352	pdata->dump_state = vp9_dump_state;
10353
10354	memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10355	memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10356
10357	pbi->index = pdev->id;
10358
10359	if (pdata->use_vfm_path)
10360	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10361	VFM_DEC_PROVIDER_NAME);
10362	else
10363	snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10364	MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10365
10366	vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10367	&vvp9_vf_provider, pbi);
10368
10369	pbi->provider_name = pdata->vf_provider_name;
10370	platform_set_drvdata(pdev, pdata);
10371
10372	pbi->platform_dev = pdev;
10373	pbi->video_signal_type = 0;
10374	pbi->m_ins_flag = 1;
10375	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10376	pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10377
10378	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10379	pbi->max_pic_w = 8192;
10380	pbi->max_pic_h = 4608;
10381	} else {
10382	pbi->max_pic_w = 4096;
10383	pbi->max_pic_h = 2304;
10384	}
10385	#if 1
10386	if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10387	pdata->config_len) {
10388	#ifdef MULTI_INSTANCE_SUPPORT
10389	int vp9_buf_width = 0;
10390	int vp9_buf_height = 0;
10391	/*use ptr config for doubel_write_mode, etc*/
10392	vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10393	if (get_config_int(pdata->config, "vp9_double_write_mode",
10394	&config_val) == 0)
10395	pbi->double_write_mode = config_val;
10396	else
10397	pbi->double_write_mode = double_write_mode;
10398
10399	if (get_config_int(pdata->config, "save_buffer_mode",
10400	&config_val) == 0)
10401	pbi->save_buffer_mode = config_val;
10402	else
10403	pbi->save_buffer_mode = 0;
10404	if (get_config_int(pdata->config, "vp9_buf_width",
10405	&config_val) == 0) {
10406	vp9_buf_width = config_val;
10407	}
10408	if (get_config_int(pdata->config, "vp9_buf_height",
10409	&config_val) == 0) {
10410	vp9_buf_height = config_val;
10411	}
10412
10413	if (get_config_int(pdata->config, "no_head",
10414	&config_val) == 0)
10415	pbi->no_head = config_val;
10416	else
10417	pbi->no_head = no_head;
10418
10419	/*use ptr config for max_pic_w, etc*/
10420	if (get_config_int(pdata->config, "vp9_max_pic_w",
10421	&config_val) == 0) {
10422	pbi->max_pic_w = config_val;
10423	}
10424	if (get_config_int(pdata->config, "vp9_max_pic_h",
10425	&config_val) == 0) {
10426	pbi->max_pic_h = config_val;
10427	}
10428	if ((pbi->max_pic_w * pbi->max_pic_h)
10429	< (vp9_buf_width * vp9_buf_height)) {
10430	pbi->max_pic_w = vp9_buf_width;
10431	pbi->max_pic_h = vp9_buf_height;
10432	vp9_print(pbi, 0, "use buf resolution\n");
10433	}
10434
10435	if (get_config_int(pdata->config,
10436	"parm_v4l_codec_enable",
10437	&config_val) == 0)
10438	pbi->is_used_v4l = config_val;
10439
10440	if (get_config_int(pdata->config,
10441	"parm_v4l_buffer_margin",
10442	&config_val) == 0)
10443	pbi->dynamic_buf_num_margin = config_val;
10444
10445	if (get_config_int(pdata->config,
10446	"parm_v4l_canvas_mem_mode",
10447	&config_val) == 0)
10448	pbi->mem_map_mode = config_val;
10449	#endif
10450	if (get_config_int(pdata->config, "HDRStaticInfo",
10451	&vf_dp.present_flag) == 0
10452	&& vf_dp.present_flag == 1) {
10453	get_config_int(pdata->config, "mG.x",
10454	&vf_dp.primaries[0][0]);
10455	get_config_int(pdata->config, "mG.y",
10456	&vf_dp.primaries[0][1]);
10457	get_config_int(pdata->config, "mB.x",
10458	&vf_dp.primaries[1][0]);
10459	get_config_int(pdata->config, "mB.y",
10460	&vf_dp.primaries[1][1]);
10461	get_config_int(pdata->config, "mR.x",
10462	&vf_dp.primaries[2][0]);
10463	get_config_int(pdata->config, "mR.y",
10464	&vf_dp.primaries[2][1]);
10465	get_config_int(pdata->config, "mW.x",
10466	&vf_dp.white_point[0]);
10467	get_config_int(pdata->config, "mW.y",
10468	&vf_dp.white_point[1]);
10469	get_config_int(pdata->config, "mMaxDL",
10470	&vf_dp.luminance[0]);
10471	get_config_int(pdata->config, "mMinDL",
10472	&vf_dp.luminance[1]);
10473	vf_dp.content_light_level.present_flag = 1;
10474	get_config_int(pdata->config, "mMaxCLL",
10475	&content_light_level.max_content);
10476	get_config_int(pdata->config, "mMaxFALL",
10477	&content_light_level.max_pic_average);
10478	vf_dp.content_light_level = content_light_level;
10479	pbi->video_signal_type = (1 << 29)
10480	| (5 << 26) /* unspecified */
10481	| (0 << 25) /* limit */
10482	| (1 << 24) /* color available */
10483	| (9 << 16) /* 2020 */
10484	| (16 << 8) /* 2084 */
10485	| (9 << 0); /* 2020 */
10486	}
10487	pbi->vf_dp = vf_dp;
10488	} else
10489	#endif
10490	{
10491	/*pbi->vvp9_amstream_dec_info.width = 0;
10492	pbi->vvp9_amstream_dec_info.height = 0;
10493	pbi->vvp9_amstream_dec_info.rate = 30;*/
10494	pbi->double_write_mode = double_write_mode;
10495	}
10496
10497	if (!pbi->is_used_v4l) {
10498	pbi->mem_map_mode = mem_map_mode;
10499	}
10500
10501	if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10502	pr_err("over size: %dx%d, probe failed\n",
10503	pbi->max_pic_w, pbi->max_pic_h);
10504	return -1;
10505	}
10506	pbi->mmu_enable = 1;
10507	video_signal_type = pbi->video_signal_type;
10508
10509	if (pdata->sys_info) {
10510	pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10511	} else {
10512	pbi->vvp9_amstream_dec_info.width = 0;
10513	pbi->vvp9_amstream_dec_info.height = 0;
10514	pbi->vvp9_amstream_dec_info.rate = 30;
10515	}
10516	pbi->low_latency_flag = 1;
10517
10518	vp9_print(pbi, 0,
10519	"no_head %d low_latency %d\n",
10520	pbi->no_head, pbi->low_latency_flag);
10521	#if 0
10522	pbi->buf_start = pdata->mem_start;
10523	pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10524	#else
10525	if (amvdec_vp9_mmu_init(pbi) < 0) {
10526	pr_err("vp9 alloc bmmu box failed!!\n");
10527	/* devm_kfree(&pdev->dev, (void *)pbi); */
10528	vfree((void *)pbi);
10529	pdata->dec_status = NULL;
10530	return -1;
10531	}
10532
10533	pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10534	ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10535	pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10536	&pbi->cma_alloc_addr);
10537	if (ret < 0) {
10538	uninit_mmu_buffers(pbi);
10539	/* devm_kfree(&pdev->dev, (void *)pbi); */
10540	vfree((void *)pbi);
10541	pdata->dec_status = NULL;
10542	return ret;
10543	}
10544	pbi->buf_start = pbi->cma_alloc_addr;
10545	pbi->buf_size = work_buf_size;
10546	#endif
10547
10548	pbi->init_flag = 0;
10549	pbi->first_sc_checked = 0;
10550	pbi->fatal_error = 0;
10551	pbi->show_frame_num = 0;
10552
10553	if (debug) {
10554	pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10555	pbi->buf_start,
10556	pbi->buf_size);
10557	}
10558
10559	pbi->cma_dev = pdata->cma_dev;
10560	if (vvp9_init(pdata) < 0) {
10561	pr_info("\namvdec_vp9 init failed.\n");
10562	vp9_local_uninit(pbi);
10563	uninit_mmu_buffers(pbi);
10564	/* devm_kfree(&pdev->dev, (void *)pbi); */
10565	vfree((void *)pbi);
10566	pdata->dec_status = NULL;
10567	return -ENODEV;
10568	}
10569	vdec_set_prepare_level(pdata, start_decode_buf_level);
10570	hevc_source_changed(VFORMAT_VP9,
10571	4096, 2048, 60);
10572	#ifdef SUPPORT_FB_DECODING
10573	if (pbi->used_stage_buf_num > 0)
10574	vdec_core_request(pdata,
10575	CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10576	else
10577	vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10578	| CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10579	| CORE_MASK_COMBINE);
10580	#else
10581	if (pdata->parallel_dec == 1)
10582	vdec_core_request(pdata, CORE_MASK_HEVC);
10583	else
10584	vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10585	| CORE_MASK_COMBINE);
10586	#endif
10587	pbi->pic_list_init_done2 = true;
10588	return 0;
10589	}
10590
10591	static int ammvdec_vp9_remove(struct platform_device *pdev)
10592	{
10593	struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10594	(((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10595	struct vdec_s *vdec = hw_to_vdec(pbi);
10596	int i;
10597	if (debug)
10598	pr_info("amvdec_vp9_remove\n");
10599
10600	vmvp9_stop(pbi);
10601
10602	#ifdef SUPPORT_FB_DECODING
10603	vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10604	| CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10605	);
10606	#else
10607	if (vdec->parallel_dec == 1)
10608	vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10609	else
10610	vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10611	#endif
10612	vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10613
10614	if (vdec->parallel_dec == 1) {
10615	for (i = 0; i < FRAME_BUFFERS; i++) {
10616	vdec->free_canvas_ex
10617	(pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10618	vdec->id);
10619	vdec->free_canvas_ex
10620	(pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10621	vdec->id);
10622	}
10623	}
10624
10625
10626	#ifdef DEBUG_PTS
10627	pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10628	pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10629	#endif
10630	mem_map_mode = 0;
10631
10632	/* devm_kfree(&pdev->dev, (void *)pbi); */
10633	vfree((void *)pbi);
10634	return 0;
10635	}
10636
10637	static struct platform_driver ammvdec_vp9_driver = {
10638	.probe = ammvdec_vp9_probe,
10639	.remove = ammvdec_vp9_remove,
10640	.driver = {
10641	.name = MULTI_DRIVER_NAME,
10642	#ifdef CONFIG_PM
10643	.pm = &vp9_pm_ops,
10644	#endif
10645	}
10646	};
10647	#endif
10648	static struct mconfig vp9_configs[] = {
10649	MC_PU32("bit_depth_luma", &bit_depth_luma),
10650	MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10651	MC_PU32("frame_width", &frame_width),
10652	MC_PU32("frame_height", &frame_height),
10653	MC_PU32("debug", &debug),
10654	MC_PU32("radr", &radr),
10655	MC_PU32("rval", &rval),
10656	MC_PU32("pop_shorts", &pop_shorts),
10657	MC_PU32("dbg_cmd", &dbg_cmd),
10658	MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10659	MC_PU32("endian", &endian),
10660	MC_PU32("step", &step),
10661	MC_PU32("udebug_flag", &udebug_flag),
10662	MC_PU32("decode_pic_begin", &decode_pic_begin),
10663	MC_PU32("slice_parse_begin", &slice_parse_begin),
10664	MC_PU32("i_only_flag", &i_only_flag),
10665	MC_PU32("error_handle_policy", &error_handle_policy),
10666	MC_PU32("buf_alloc_width", &buf_alloc_width),
10667	MC_PU32("buf_alloc_height", &buf_alloc_height),
10668	MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10669	MC_PU32("buf_alloc_size", &buf_alloc_size),
10670	MC_PU32("buffer_mode", &buffer_mode),
10671	MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10672	MC_PU32("max_buf_num", &max_buf_num),
10673	MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10674	MC_PU32("mem_map_mode", &mem_map_mode),
10675	MC_PU32("double_write_mode", &double_write_mode),
10676	MC_PU32("enable_mem_saving", &enable_mem_saving),
10677	MC_PU32("force_w_h", &force_w_h),
10678	MC_PU32("force_fps", &force_fps),
10679	MC_PU32("max_decoding_time", &max_decoding_time),
10680	MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10681	MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10682	MC_PU32("decode_timeout_val", &decode_timeout_val),
10683	MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10684	MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10685	};
10686	static struct mconfig_node vp9_node;
10687
10688	static int __init amvdec_vp9_driver_init_module(void)
10689	{
10690
10691	struct BuffInfo_s *p_buf_info;
10692
10693	if (vdec_is_support_4k()) {
10694	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10695	p_buf_info = &amvvp9_workbuff_spec[2];
10696	else
10697	p_buf_info = &amvvp9_workbuff_spec[1];
10698	} else
10699	p_buf_info = &amvvp9_workbuff_spec[0];
10700
10701	init_buff_spec(NULL, p_buf_info);
10702	work_buf_size =
10703	(p_buf_info->end_adr - p_buf_info->start_adr
10704	+ 0xffff) & (~0xffff);
10705
10706	pr_debug("amvdec_vp9 module init\n");
10707
10708	error_handle_policy = 0;
10709
10710	#ifdef ERROR_HANDLE_DEBUG
10711	dbg_nal_skip_flag = 0;
10712	dbg_nal_skip_count = 0;
10713	#endif
10714	udebug_flag = 0;
10715	decode_pic_begin = 0;
10716	slice_parse_begin = 0;
10717	step = 0;
10718	buf_alloc_size = 0;
10719	#ifdef MULTI_INSTANCE_SUPPORT
10720	if (platform_driver_register(&ammvdec_vp9_driver))
10721	pr_err("failed to register ammvdec_vp9 driver\n");
10722
10723	#endif
10724	if (platform_driver_register(&amvdec_vp9_driver)) {
10725	pr_err("failed to register amvdec_vp9 driver\n");
10726	return -ENODEV;
10727	}
10728
10729	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10730	amvdec_vp9_profile.profile =
10731	"8k, 10bit, dwrite, compressed, no_head";
10732	} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10733	/*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10734	&& get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10735	if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10736	if (vdec_is_support_4k())
10737	amvdec_vp9_profile.profile =
10738	"4k, 10bit, dwrite, compressed";
10739	else
10740	amvdec_vp9_profile.profile =
10741	"10bit, dwrite, compressed";
10742	} else {
10743	if (vdec_is_support_4k())
10744	amvdec_vp9_profile.profile =
10745	"4k, 10bit, dwrite, compressed, no_head";
10746	else
10747	amvdec_vp9_profile.profile =
10748	"10bit, dwrite, compressed, no_head";
10749	}
10750
10751	} else {
10752	amvdec_vp9_profile.name = "vp9_unsupport";
10753	}
10754
10755	if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10756	max_buf_num = MAX_BUF_NUM_LESS;
10757
10758	vcodec_profile_register(&amvdec_vp9_profile);
10759	amvdec_vp9_profile_mult = amvdec_vp9_profile;
10760	amvdec_vp9_profile_mult.name = "mvp9";
10761	vcodec_profile_register(&amvdec_vp9_profile_mult);
10762	INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10763	"vp9", vp9_configs, CONFIG_FOR_RW);
10764
10765	return 0;
10766	}
10767
10768	static void __exit amvdec_vp9_driver_remove_module(void)
10769	{
10770	pr_debug("amvdec_vp9 module remove.\n");
10771	#ifdef MULTI_INSTANCE_SUPPORT
10772	platform_driver_unregister(&ammvdec_vp9_driver);
10773	#endif
10774	platform_driver_unregister(&amvdec_vp9_driver);
10775	}
10776
10777	/****************************************/
10778
10779	module_param(bit_depth_luma, uint, 0664);
10780	MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10781
10782	module_param(bit_depth_chroma, uint, 0664);
10783	MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10784
10785	module_param(frame_width, uint, 0664);
10786	MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10787
10788	module_param(frame_height, uint, 0664);
10789	MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10790
10791	module_param(debug, uint, 0664);
10792	MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10793
10794	module_param(radr, uint, 0664);
10795	MODULE_PARM_DESC(radr, "\n radr\n");
10796
10797	module_param(rval, uint, 0664);
10798	MODULE_PARM_DESC(rval, "\n rval\n");
10799
10800	module_param(pop_shorts, uint, 0664);
10801	MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10802
10803	module_param(dbg_cmd, uint, 0664);
10804	MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10805
10806	module_param(dbg_skip_decode_index, uint, 0664);
10807	MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10808
10809	module_param(endian, uint, 0664);
10810	MODULE_PARM_DESC(endian, "\n rval\n");
10811
10812	module_param(step, uint, 0664);
10813	MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10814
10815	module_param(decode_pic_begin, uint, 0664);
10816	MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10817
10818	module_param(slice_parse_begin, uint, 0664);
10819	MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10820
10821	module_param(i_only_flag, uint, 0664);
10822	MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10823
10824	module_param(low_latency_flag, uint, 0664);
10825	MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10826
10827	module_param(no_head, uint, 0664);
10828	MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10829
10830	module_param(error_handle_policy, uint, 0664);
10831	MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10832
10833	module_param(buf_alloc_width, uint, 0664);
10834	MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10835
10836	module_param(buf_alloc_height, uint, 0664);
10837	MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10838
10839	module_param(buf_alloc_depth, uint, 0664);
10840	MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10841
10842	module_param(buf_alloc_size, uint, 0664);
10843	MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10844
10845	module_param(buffer_mode, uint, 0664);
10846	MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10847
10848	module_param(buffer_mode_dbg, uint, 0664);
10849	MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10850	/*USE_BUF_BLOCK*/
10851	module_param(max_buf_num, uint, 0664);
10852	MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10853
10854	module_param(dynamic_buf_num_margin, uint, 0664);
10855	MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10856
10857	module_param(mv_buf_margin, uint, 0664);
10858	MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10859
10860	module_param(run_ready_min_buf_num, uint, 0664);
10861	MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10862
10863	/**/
10864
10865	module_param(mem_map_mode, uint, 0664);
10866	MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10867
10868	#ifdef SUPPORT_10BIT
10869	module_param(double_write_mode, uint, 0664);
10870	MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10871
10872	module_param(enable_mem_saving, uint, 0664);
10873	MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10874
10875	module_param(force_w_h, uint, 0664);
10876	MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10877	#endif
10878
10879	module_param(force_fps, uint, 0664);
10880	MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10881
10882	module_param(max_decoding_time, uint, 0664);
10883	MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10884
10885	module_param(on_no_keyframe_skiped, uint, 0664);
10886	MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10887
10888	module_param(mcrcc_cache_alg_flag, uint, 0664);
10889	MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10890
10891	#ifdef MULTI_INSTANCE_SUPPORT
10892	module_param(start_decode_buf_level, int, 0664);
10893	MODULE_PARM_DESC(start_decode_buf_level,
10894	"\n vp9 start_decode_buf_level\n");
10895
10896	module_param(decode_timeout_val, uint, 0664);
10897	MODULE_PARM_DESC(decode_timeout_val,
10898	"\n vp9 decode_timeout_val\n");
10899
10900	module_param(vp9_max_pic_w, uint, 0664);
10901	MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10902
10903	module_param(vp9_max_pic_h, uint, 0664);
10904	MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10905
10906	module_param_array(decode_frame_count, uint,
10907	&max_decode_instance_num, 0664);
10908
10909	module_param_array(display_frame_count, uint,
10910	&max_decode_instance_num, 0664);
10911
10912	module_param_array(max_process_time, uint,
10913	&max_decode_instance_num, 0664);
10914
10915	module_param_array(run_count, uint,
10916	&max_decode_instance_num, 0664);
10917
10918	module_param_array(input_empty, uint,
10919	&max_decode_instance_num, 0664);
10920
10921	module_param_array(not_run_ready, uint,
10922	&max_decode_instance_num, 0664);
10923	#endif
10924
10925	#ifdef SUPPORT_FB_DECODING
10926	module_param_array(not_run2_ready, uint,
10927	&max_decode_instance_num, 0664);
10928
10929	module_param_array(run2_count, uint,
10930	&max_decode_instance_num, 0664);
10931
10932	module_param(stage_buf_num, uint, 0664);
10933	MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10934	#endif
10935
10936	module_param(udebug_flag, uint, 0664);
10937	MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10938
10939	module_param(udebug_pause_pos, uint, 0664);
10940	MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10941
10942	module_param(udebug_pause_val, uint, 0664);
10943	MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10944
10945	module_param(udebug_pause_decode_idx, uint, 0664);
10946	MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10947
10948	module_param(without_display_mode, uint, 0664);
10949	MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10950
10951	module_init(amvdec_vp9_driver_init_module);
10952	module_exit(amvdec_vp9_driver_remove_module);
10953
10954	MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
10955	MODULE_LICENSE("GPL");
10956
10957