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path: root/drivers/frame_provider/decoder/vp9/vvp9.c (plain)
blob: 8c302c7170d285ba268616f6c85a1b0f40cd27cd
1 /*
2 * drivers/amlogic/amports/vvp9.c
3 *
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 */
17#define DEBUG
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/semaphore.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/kfifo.h>
27#include <linux/kthread.h>
28#include <linux/spinlock.h>
29#include <linux/platform_device.h>
30#include <linux/amlogic/media/vfm/vframe.h>
31#include <linux/amlogic/media/utils/amstream.h>
32#include <linux/amlogic/media/utils/vformat.h>
33#include <linux/amlogic/media/frame_sync/ptsserv.h>
34#include <linux/amlogic/media/canvas/canvas.h>
35#include <linux/amlogic/media/vfm/vframe_provider.h>
36#include <linux/amlogic/media/vfm/vframe_receiver.h>
37#include <linux/dma-mapping.h>
38#include <linux/dma-contiguous.h>
39#include <linux/slab.h>
40#include <linux/amlogic/tee.h>
41#include "../../../stream_input/amports/amports_priv.h"
42#include <linux/amlogic/media/codec_mm/codec_mm.h>
43#include "../utils/decoder_mmu_box.h"
44#include "../utils/decoder_bmmu_box.h"
45
46#define MEM_NAME "codec_vp9"
47/* #include <mach/am_regs.h> */
48#include <linux/amlogic/media/utils/vdec_reg.h>
49#include "../utils/vdec.h"
50#include "../utils/amvdec.h"
51#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
52#include "../utils/vdec_profile.h"
53#endif
54
55#include <linux/amlogic/media/video_sink/video.h>
56#include <linux/amlogic/media/codec_mm/configs.h>
57#include "../utils/config_parser.h"
58#include "../utils/firmware.h"
59#include "../../../common/chips/decoder_cpu_ver_info.h"
60#include "../utils/vdec_v4l2_buffer_ops.h"
61#include <media/v4l2-mem2mem.h>
62
63#define MIX_STREAM_SUPPORT
64
65#include "vvp9.h"
66
67
68/*#define SUPPORT_FB_DECODING*/
69/*#define FB_DECODING_TEST_SCHEDULE*/
70
71
72#define HW_MASK_FRONT 0x1
73#define HW_MASK_BACK 0x2
74
75#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442
76#define VP9D_MPP_REFINFO_DATA 0x3443
77#define VP9D_MPP_REF_SCALE_ENBL 0x3441
78#define HEVC_MPRED_CTRL4 0x324c
79#define HEVC_CM_HEADER_START_ADDR 0x3628
80#define HEVC_DBLK_CFGB 0x350b
81#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464
82#define HEVC_SAO_MMU_VH1_ADDR 0x363b
83#define HEVC_SAO_MMU_VH0_ADDR 0x363a
84
85#define HEVC_MV_INFO 0x310d
86#define HEVC_QP_INFO 0x3137
87#define HEVC_SKIP_INFO 0x3136
88
89#define VP9_10B_DEC_IDLE 0
90#define VP9_10B_DEC_FRAME_HEADER 1
91#define VP9_10B_DEC_SLICE_SEGMENT 2
92#define VP9_10B_DECODE_SLICE 5
93#define VP9_10B_DISCARD_NAL 6
94#define VP9_DUMP_LMEM 7
95#define HEVC_DECPIC_DATA_DONE 0xa
96#define HEVC_DECPIC_DATA_ERROR 0xb
97#define HEVC_NAL_DECODE_DONE 0xe
98#define HEVC_DECODE_BUFEMPTY 0x20
99#define HEVC_DECODE_TIMEOUT 0x21
100#define HEVC_SEARCH_BUFEMPTY 0x22
101#define HEVC_DECODE_OVER_SIZE 0x23
102#define HEVC_S2_DECODING_DONE 0x50
103#define VP9_HEAD_PARSER_DONE 0xf0
104#define VP9_HEAD_SEARCH_DONE 0xf1
105#define VP9_EOS 0xf2
106#define HEVC_ACTION_DONE 0xff
107
108#define VF_POOL_SIZE 32
109
110#undef pr_info
111#define pr_info printk
112
113#define DECODE_MODE_SINGLE ((0x80 << 24) | 0)
114#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1)
115#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2)
116#define DECODE_MODE_SINGLE_LOW_LATENCY ((0x80 << 24) | 3)
117#define DECODE_MODE_MULTI_FRAMEBASE_NOHEAD ((0x80 << 24) | 4)
118
119#define VP9_TRIGGER_FRAME_DONE 0x100
120#define VP9_TRIGGER_FRAME_ENABLE 0x200
121
122#define MV_MEM_UNIT 0x240
123/*---------------------------------------------------
124 * Include "parser_cmd.h"
125 *---------------------------------------------------
126 */
127#define PARSER_CMD_SKIP_CFG_0 0x0000090b
128
129#define PARSER_CMD_SKIP_CFG_1 0x1b14140f
130
131#define PARSER_CMD_SKIP_CFG_2 0x001b1910
132
133#define PARSER_CMD_NUMBER 37
134
135/*#define HEVC_PIC_STRUCT_SUPPORT*/
136/* to remove, fix build error */
137
138/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/
139
140#define MULTI_INSTANCE_SUPPORT
141#define SUPPORT_10BIT
142/* #define ERROR_HANDLE_DEBUG */
143
144#ifndef STAT_KTHREAD
145#define STAT_KTHREAD 0x40
146#endif
147
148#ifdef MULTI_INSTANCE_SUPPORT
149#define MAX_DECODE_INSTANCE_NUM 9
150#define MULTI_DRIVER_NAME "ammvdec_vp9"
151static unsigned int max_decode_instance_num
152 = MAX_DECODE_INSTANCE_NUM;
153static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM];
154static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM];
155static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM];
156static unsigned int run_count[MAX_DECODE_INSTANCE_NUM];
157static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM];
158static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM];
159
160static u32 decode_timeout_val = 200;
161static int start_decode_buf_level = 0x8000;
162static u32 work_buf_size;
163
164static u32 mv_buf_margin;
165
166/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */
167/* double_write_mode:
168 * 0, no double write;
169 * 1, 1:1 ratio;
170 * 2, (1/4):(1/4) ratio;
171 * 3, (1/4):(1/4) ratio, with both compressed frame included
172 * 4, (1/2):(1/2) ratio;
173 * 0x10, double write only
174 * 0x100, if > 1080p,use mode 4,else use mode 1;
175 * 0x200, if > 1080p,use mode 2,else use mode 1;
176 * 0x300, if > 720p, use mode 4, else use mode 1;
177 */
178static u32 double_write_mode;
179
180#define DRIVER_NAME "amvdec_vp9"
181#define MODULE_NAME "amvdec_vp9"
182#define DRIVER_HEADER_NAME "amvdec_vp9_header"
183
184
185#define PUT_INTERVAL (HZ/100)
186#define ERROR_SYSTEM_RESET_COUNT 200
187
188#define PTS_NORMAL 0
189#define PTS_NONE_REF_USE_DURATION 1
190
191#define PTS_MODE_SWITCHING_THRESHOLD 3
192#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
193
194#define DUR2PTS(x) ((x)*90/96)
195
196struct VP9Decoder_s;
197static int vvp9_vf_states(struct vframe_states *states, void *);
198static struct vframe_s *vvp9_vf_peek(void *);
199static struct vframe_s *vvp9_vf_get(void *);
200static void vvp9_vf_put(struct vframe_s *, void *);
201static int vvp9_event_cb(int type, void *data, void *private_data);
202
203static int vvp9_stop(struct VP9Decoder_s *pbi);
204#ifdef MULTI_INSTANCE_SUPPORT
205static s32 vvp9_init(struct vdec_s *vdec);
206#else
207static s32 vvp9_init(struct VP9Decoder_s *pbi);
208#endif
209static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask);
210static int vvp9_local_init(struct VP9Decoder_s *pbi);
211static void vvp9_put_timer_func(unsigned long arg);
212static void dump_data(struct VP9Decoder_s *pbi, int size);
213static unsigned char get_data_check_sum
214 (struct VP9Decoder_s *pbi, int size);
215static void dump_pic_list(struct VP9Decoder_s *pbi);
216static int vp9_alloc_mmu(
217 struct VP9Decoder_s *pbi,
218 int cur_buf_idx,
219 int pic_width,
220 int pic_height,
221 unsigned short bit_depth,
222 unsigned int *mmu_index_adr);
223
224
225static const char vvp9_dec_id[] = "vvp9-dev";
226
227#define PROVIDER_NAME "decoder.vp9"
228#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9"
229
230static const struct vframe_operations_s vvp9_vf_provider = {
231 .peek = vvp9_vf_peek,
232 .get = vvp9_vf_get,
233 .put = vvp9_vf_put,
234 .event_cb = vvp9_event_cb,
235 .vf_states = vvp9_vf_states,
236};
237
238static struct vframe_provider_s vvp9_vf_prov;
239
240static u32 bit_depth_luma;
241static u32 bit_depth_chroma;
242static u32 frame_width;
243static u32 frame_height;
244static u32 video_signal_type;
245
246static u32 on_no_keyframe_skiped;
247
248#define PROB_SIZE (496 * 2 * 4)
249#define PROB_BUF_SIZE (0x5000)
250#define COUNT_BUF_SIZE (0x300 * 4 * 4)
251/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
252#define MAX_FRAME_4K_NUM 0x1200
253#define MAX_FRAME_8K_NUM 0x4800
254
255#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
256
257#ifdef SUPPORT_FB_DECODING
258/* register define */
259#define HEVC_ASSIST_HED_FB_W_CTL 0x3006
260#define HEVC_ASSIST_HED_FB_R_CTL 0x3007
261#define HEVC_ASSIST_HED_FB_ADDR 0x3008
262#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a
263#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b
264
265
266#define MAX_STAGE_PAGE_NUM 0x1200
267#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4)
268#endif
269static inline int div_r32(int64_t m, int n)
270{
271/*
272 *return (int)(m/n)
273 */
274#ifndef CONFIG_ARM64
275 int64_t qu = 0;
276 qu = div_s64(m, n);
277 return (int)qu;
278#else
279 return (int)(m/n);
280#endif
281}
282
283/*USE_BUF_BLOCK*/
284struct BUF_s {
285 int index;
286 unsigned int alloc_flag;
287 /*buffer */
288 unsigned int cma_page_count;
289 unsigned long alloc_addr;
290 unsigned long start_adr;
291 unsigned int size;
292
293 unsigned int free_start_adr;
294 ulong v4l_ref_buf_addr;
295 ulong header_addr;
296 u32 header_size;
297 u32 luma_size;
298} /*BUF_t */;
299
300struct MVBUF_s {
301 unsigned long start_adr;
302 unsigned int size;
303 int used_flag;
304} /*MVBUF_t */;
305
306 /* #undef BUFMGR_ONLY to enable hardware configuration */
307
308/*#define TEST_WR_PTR_INC*/
309/*#define WR_PTR_INC_NUM 128*/
310#define WR_PTR_INC_NUM 1
311
312#define SIMULATION
313#define DOS_PROJECT
314#undef MEMORY_MAP_IN_REAL_CHIP
315
316/*#undef DOS_PROJECT*/
317/*#define MEMORY_MAP_IN_REAL_CHIP*/
318
319/*#define BUFFER_MGR_ONLY*/
320/*#define CONFIG_HEVC_CLK_FORCED_ON*/
321/*#define ENABLE_SWAP_TEST*/
322#define MCRCC_ENABLE
323
324#define VP9_LPF_LVL_UPDATE
325/*#define DBG_LF_PRINT*/
326
327#ifdef VP9_10B_NV21
328#else
329#define LOSLESS_COMPRESS_MODE
330#endif
331
332#define DOUBLE_WRITE_YSTART_TEMP 0x02000000
333#define DOUBLE_WRITE_CSTART_TEMP 0x02900000
334
335
336
337typedef unsigned int u32;
338typedef unsigned short u16;
339
340#define VP9_DEBUG_BUFMGR 0x01
341#define VP9_DEBUG_BUFMGR_MORE 0x02
342#define VP9_DEBUG_BUFMGR_DETAIL 0x04
343#define VP9_DEBUG_OUT_PTS 0x10
344#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100
345#define VP9_DEBUG_MERGE 0x200
346#define VP9_DEBUG_DBG_LF_PRINT 0x400
347#define VP9_DEBUG_REG 0x800
348#define VP9_DEBUG_2_STAGE 0x1000
349#define VP9_DEBUG_2_STAGE_MORE 0x2000
350#define VP9_DEBUG_QOS_INFO 0x4000
351#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000
352#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000
353#define VP9_DEBUG_DUMP_PIC_LIST 0x40000
354#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000
355#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000
356#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000
357#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000
358#define VP9_DEBUG_DUMP_DATA 0x800000
359#define VP9_DEBUG_CACHE 0x1000000
360#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000
361#define IGNORE_PARAM_FROM_CONFIG 0x8000000
362#ifdef MULTI_INSTANCE_SUPPORT
363#define PRINT_FLAG_ERROR 0x0
364#define PRINT_FLAG_V4L_DETAIL 0x10000000
365#define PRINT_FLAG_VDEC_STATUS 0x20000000
366#define PRINT_FLAG_VDEC_DETAIL 0x40000000
367#define PRINT_FLAG_VDEC_DATA 0x80000000
368#endif
369
370static u32 debug;
371static bool is_reset;
372/*for debug*/
373/*
374 udebug_flag:
375 bit 0, enable ucode print
376 bit 1, enable ucode detail print
377 bit [31:16] not 0, pos to dump lmem
378 bit 2, pop bits to lmem
379 bit [11:8], pre-pop bits for alignment (when bit 2 is 1)
380*/
381static u32 udebug_flag;
382/*
383 when udebug_flag[1:0] is not 0
384 udebug_pause_pos not 0,
385 pause position
386*/
387static u32 udebug_pause_pos;
388/*
389 when udebug_flag[1:0] is not 0
390 and udebug_pause_pos is not 0,
391 pause only when DEBUG_REG2 is equal to this val
392*/
393static u32 udebug_pause_val;
394
395static u32 udebug_pause_decode_idx;
396
397static u32 without_display_mode;
398
399#define DEBUG_REG
400#ifdef DEBUG_REG
401void WRITE_VREG_DBG2(unsigned int adr, unsigned int val)
402{
403 if (debug & VP9_DEBUG_REG)
404 pr_info("%s(%x, %x)\n", __func__, adr, val);
405 if (adr != 0)
406 WRITE_VREG(adr, val);
407}
408
409#undef WRITE_VREG
410#define WRITE_VREG WRITE_VREG_DBG2
411#endif
412
413#define FRAME_CNT_WINDOW_SIZE 59
414#define RATE_CORRECTION_THRESHOLD 5
415/**************************************************
416
417VP9 buffer management start
418
419***************************************************/
420
421#define MMU_COMPRESS_HEADER_SIZE 0x48000
422#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
423#define MAX_SIZE_8K (8192 * 4608)
424#define MAX_SIZE_4K (4096 * 2304)
425#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
426
427#define INVALID_IDX -1 /* Invalid buffer index.*/
428
429#define RPM_BEGIN 0x200
430#define RPM_END 0x280
431
432union param_u {
433 struct {
434 unsigned short data[RPM_END - RPM_BEGIN];
435 } l;
436 struct {
437 /* from ucode lmem, do not change this struct */
438 unsigned short profile;
439 unsigned short show_existing_frame;
440 unsigned short frame_to_show_idx;
441 unsigned short frame_type; /*1 bit*/
442 unsigned short show_frame; /*1 bit*/
443 unsigned short error_resilient_mode; /*1 bit*/
444 unsigned short intra_only; /*1 bit*/
445 unsigned short display_size_present; /*1 bit*/
446 unsigned short reset_frame_context;
447 unsigned short refresh_frame_flags;
448 unsigned short width;
449 unsigned short height;
450 unsigned short display_width;
451 unsigned short display_height;
452 /*
453 *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit))
454 *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit))
455 *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit))
456 */
457 unsigned short ref_info;
458 /*
459 *bit[2]: same_frame_size0
460 *bit[1]: same_frame_size1
461 *bit[0]: same_frame_size2
462 */
463 unsigned short same_frame_size;
464
465 unsigned short mode_ref_delta_enabled;
466 unsigned short ref_deltas[4];
467 unsigned short mode_deltas[2];
468 unsigned short filter_level;
469 unsigned short sharpness_level;
470 unsigned short bit_depth;
471 unsigned short seg_quant_info[8];
472 unsigned short seg_enabled;
473 unsigned short seg_abs_delta;
474 /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */
475 unsigned short seg_lf_info[8];
476 } p;
477};
478
479
480struct vpx_codec_frame_buffer_s {
481 uint8_t *data; /**< Pointer to the data buffer */
482 size_t size; /**< Size of data in bytes */
483 void *priv; /**< Frame's private data */
484};
485
486enum vpx_color_space_t {
487 VPX_CS_UNKNOWN = 0, /**< Unknown */
488 VPX_CS_BT_601 = 1, /**< BT.601 */
489 VPX_CS_BT_709 = 2, /**< BT.709 */
490 VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */
491 VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */
492 VPX_CS_BT_2020 = 5, /**< BT.2020 */
493 VPX_CS_RESERVED = 6, /**< Reserved */
494 VPX_CS_SRGB = 7 /**< sRGB */
495}; /**< alias for enum vpx_color_space */
496
497enum vpx_bit_depth_t {
498 VPX_BITS_8 = 8, /**< 8 bits */
499 VPX_BITS_10 = 10, /**< 10 bits */
500 VPX_BITS_12 = 12, /**< 12 bits */
501};
502
503#define MAX_SLICE_NUM 1024
504struct PIC_BUFFER_CONFIG_s {
505 int index;
506 int BUF_index;
507 int mv_buf_index;
508 int comp_body_size;
509 int buf_size;
510 int vf_ref;
511 int y_canvas_index;
512 int uv_canvas_index;
513#ifdef MULTI_INSTANCE_SUPPORT
514 struct canvas_config_s canvas_config[2];
515#endif
516 int decode_idx;
517 int slice_type;
518 int stream_offset;
519 u32 pts;
520 u64 pts64;
521 u64 timestamp;
522 uint8_t error_mark;
523 /**/
524 int slice_idx;
525 /*buffer*/
526 unsigned long header_adr;
527 unsigned long mpred_mv_wr_start_addr;
528 /*unsigned long mc_y_adr;
529 *unsigned long mc_u_v_adr;
530 */
531 unsigned int dw_y_adr;
532 unsigned int dw_u_v_adr;
533 int mc_canvas_y;
534 int mc_canvas_u_v;
535
536 int lcu_total;
537 /**/
538 int y_width;
539 int y_height;
540 int y_crop_width;
541 int y_crop_height;
542 int y_stride;
543
544 int uv_width;
545 int uv_height;
546 int uv_crop_width;
547 int uv_crop_height;
548 int uv_stride;
549
550 int alpha_width;
551 int alpha_height;
552 int alpha_stride;
553
554 uint8_t *y_buffer;
555 uint8_t *u_buffer;
556 uint8_t *v_buffer;
557 uint8_t *alpha_buffer;
558
559 uint8_t *buffer_alloc;
560 int buffer_alloc_sz;
561 int border;
562 int frame_size;
563 int subsampling_x;
564 int subsampling_y;
565 unsigned int bit_depth;
566 enum vpx_color_space_t color_space;
567
568 int corrupted;
569 int flags;
570 unsigned long cma_alloc_addr;
571
572 int double_write_mode;
573
574 /* picture qos infomation*/
575 int max_qp;
576 int avg_qp;
577 int min_qp;
578 int max_skip;
579 int avg_skip;
580 int min_skip;
581 int max_mv;
582 int min_mv;
583 int avg_mv;
584
585 bool vframe_bound;
586} PIC_BUFFER_CONFIG;
587
588enum BITSTREAM_PROFILE {
589 PROFILE_0,
590 PROFILE_1,
591 PROFILE_2,
592 PROFILE_3,
593 MAX_PROFILES
594};
595
596enum FRAME_TYPE {
597 KEY_FRAME = 0,
598 INTER_FRAME = 1,
599 FRAME_TYPES,
600};
601
602enum REFERENCE_MODE {
603 SINGLE_REFERENCE = 0,
604 COMPOUND_REFERENCE = 1,
605 REFERENCE_MODE_SELECT = 2,
606 REFERENCE_MODES = 3,
607};
608
609#define NONE -1
610#define INTRA_FRAME 0
611#define LAST_FRAME 1
612#define GOLDEN_FRAME 2
613#define ALTREF_FRAME 3
614#define MAX_REF_FRAMES 4
615
616#define REFS_PER_FRAME 3
617
618#define REF_FRAMES_LOG2 3
619#define REF_FRAMES (1 << REF_FRAMES_LOG2)
620#define REF_FRAMES_4K (6)
621
622/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
623 *in parallel, 3 for scaled references on the encoder.
624 *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number
625 * // of framebuffers.
626 *TODO(jkoleszar): These 3 extra references could probably come from the
627 *normal reference pool.
628 */
629#define FRAME_BUFFERS (REF_FRAMES + 16)
630#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS)
631#define MAX_BUF_NUM (FRAME_BUFFERS)
632#define MV_BUFFER_NUM FRAME_BUFFERS
633#ifdef SUPPORT_FB_DECODING
634#define STAGE_MAX_BUFFERS 16
635#else
636#define STAGE_MAX_BUFFERS 0
637#endif
638
639#define FRAME_CONTEXTS_LOG2 2
640#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2)
641/*buffer + header buffer + workspace*/
642#ifdef MV_USE_FIXED_BUF
643#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1)
644#define VF_BUFFER_IDX(n) (n)
645#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
646#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS)
647#else
648#define MAX_BMMU_BUFFER_NUM \
649 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1)
650#define VF_BUFFER_IDX(n) (n)
651#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n)
652#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n)
653#define WORK_SPACE_BUF_ID \
654 (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM)
655#endif
656
657struct RefCntBuffer_s {
658 int ref_count;
659 /*MV_REF *mvs;*/
660 int mi_rows;
661 int mi_cols;
662 struct vpx_codec_frame_buffer_s raw_frame_buffer;
663 struct PIC_BUFFER_CONFIG_s buf;
664
665/*The Following variables will only be used in frame parallel decode.
666 *
667 *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means
668 *that no FrameWorker owns, or is decoding, this buffer.
669 *VP9Worker *frame_worker_owner;
670 *
671 *row and col indicate which position frame has been decoded to in real
672 *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX
673 *when the frame is fully decoded.
674 */
675 int row;
676 int col;
677} RefCntBuffer;
678
679struct RefBuffer_s {
680/*TODO(dkovalev): idx is not really required and should be removed, now it
681 *is used in vp9_onyxd_if.c
682 */
683 int idx;
684 struct PIC_BUFFER_CONFIG_s *buf;
685 /*struct scale_factors sf;*/
686} RefBuffer;
687
688struct InternalFrameBuffer_s {
689 uint8_t *data;
690 size_t size;
691 int in_use;
692} InternalFrameBuffer;
693
694struct InternalFrameBufferList_s {
695 int num_internal_frame_buffers;
696 struct InternalFrameBuffer_s *int_fb;
697} InternalFrameBufferList;
698
699struct BufferPool_s {
700/*Protect BufferPool from being accessed by several FrameWorkers at
701 *the same time during frame parallel decode.
702 *TODO(hkuang): Try to use atomic variable instead of locking the whole pool.
703 *
704 *Private data associated with the frame buffer callbacks.
705 *void *cb_priv;
706 *
707 *vpx_get_frame_buffer_cb_fn_t get_fb_cb;
708 *vpx_release_frame_buffer_cb_fn_t release_fb_cb;
709 */
710
711 struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS];
712
713/*Frame buffers allocated internally by the codec.*/
714 struct InternalFrameBufferList_s int_frame_buffers;
715 unsigned long flags;
716 spinlock_t lock;
717
718} BufferPool;
719
720#define lock_buffer_pool(pool, flags) \
721 spin_lock_irqsave(&pool->lock, flags)
722
723#define unlock_buffer_pool(pool, flags) \
724 spin_unlock_irqrestore(&pool->lock, flags)
725
726struct VP9_Common_s {
727 enum vpx_color_space_t color_space;
728 int width;
729 int height;
730 int display_width;
731 int display_height;
732 int last_width;
733 int last_height;
734
735 int subsampling_x;
736 int subsampling_y;
737
738 int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/
739
740 struct PIC_BUFFER_CONFIG_s *frame_to_show;
741 struct RefCntBuffer_s *prev_frame;
742
743 /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/
744 struct RefCntBuffer_s *cur_frame;
745
746 int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */
747
748 /*Prepare ref_frame_map for the next frame.
749 *Only used in frame parallel decode.
750 */
751 int next_ref_frame_map[REF_FRAMES];
752
753 /* TODO(jkoleszar): could expand active_ref_idx to 4,
754 *with 0 as intra, and roll new_fb_idx into it.
755 */
756
757 /*Each frame can reference REFS_PER_FRAME buffers*/
758 struct RefBuffer_s frame_refs[REFS_PER_FRAME];
759
760 int prev_fb_idx;
761 int new_fb_idx;
762 int cur_fb_idx_mmu;
763 /*last frame's frame type for motion search*/
764 enum FRAME_TYPE last_frame_type;
765 enum FRAME_TYPE frame_type;
766
767 int show_frame;
768 int last_show_frame;
769 int show_existing_frame;
770
771 /*Flag signaling that the frame is encoded using only INTRA modes.*/
772 uint8_t intra_only;
773 uint8_t last_intra_only;
774
775 int allow_high_precision_mv;
776
777 /*Flag signaling that the frame context should be reset to default
778 *values. 0 or 1 implies don't reset, 2 reset just the context
779 *specified in the frame header, 3 reset all contexts.
780 */
781 int reset_frame_context;
782
783 /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in
784 * MODE_INFO (8-pixel) units.
785 */
786 int MBs;
787 int mb_rows, mi_rows;
788 int mb_cols, mi_cols;
789 int mi_stride;
790
791 /*Whether to use previous frame's motion vectors for prediction.*/
792 int use_prev_frame_mvs;
793
794 int refresh_frame_context; /* Two state 0 = NO, 1 = YES */
795
796 int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */
797
798 /*struct loopfilter lf;*/
799 /*struct segmentation seg;*/
800
801 /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/
802 /* in pbi.*/
803 int frame_parallel_decode; /* frame-based threading.*/
804
805 /*Context probabilities for reference frame prediction*/
806 /*MV_REFERENCE_FRAME comp_fixed_ref;*/
807 /*MV_REFERENCE_FRAME comp_var_ref[2];*/
808 enum REFERENCE_MODE reference_mode;
809
810 /*FRAME_CONTEXT *fc; */ /* this frame entropy */
811 /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/
812 /*unsigned int frame_context_idx; *//* Context to use/update */
813 /*FRAME_COUNTS counts;*/
814
815 unsigned int current_video_frame;
816 enum BITSTREAM_PROFILE profile;
817
818 enum vpx_bit_depth_t bit_depth;
819
820 int error_resilient_mode;
821 int frame_parallel_decoding_mode;
822
823 int byte_alignment;
824 int skip_loop_filter;
825
826 /*External BufferPool passed from outside.*/
827 struct BufferPool_s *buffer_pool;
828
829 int above_context_alloc_cols;
830
831};
832
833static void set_canvas(struct VP9Decoder_s *pbi,
834 struct PIC_BUFFER_CONFIG_s *pic_config);
835static int prepare_display_buf(struct VP9Decoder_s *pbi,
836 struct PIC_BUFFER_CONFIG_s *pic_config);
837
838static void fill_frame_info(struct VP9Decoder_s *pbi,
839 struct PIC_BUFFER_CONFIG_s *frame,
840 unsigned int framesize,
841 unsigned int pts);
842
843static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm)
844{
845 return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf;
846}
847
848static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx)
849{
850 const int ref_index = *idx;
851
852 if (ref_index >= 0 && bufs[ref_index].ref_count > 0) {
853 bufs[ref_index].ref_count--;
854 /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n",
855 * ref_index, bufs[ref_index].ref_count);
856 */
857 }
858
859 *idx = new_idx;
860
861 bufs[new_idx].ref_count++;
862 /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n",
863 * new_idx, bufs[new_idx].ref_count);
864 */
865}
866
867int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb)
868{
869 struct InternalFrameBuffer_s *const int_fb =
870 (struct InternalFrameBuffer_s *)fb->priv;
871 if (int_fb)
872 int_fb->in_use = 0;
873 return 0;
874}
875
876static int compute_losless_comp_body_size(int width, int height,
877 uint8_t is_bit_depth_10);
878
879static void setup_display_size(struct VP9_Common_s *cm, union param_u *params,
880 int print_header_info)
881{
882 cm->display_width = cm->width;
883 cm->display_height = cm->height;
884 if (params->p.display_size_present) {
885 if (print_header_info)
886 pr_info(" * 1-bit display_size_present read : 1\n");
887 cm->display_width = params->p.display_width;
888 cm->display_height = params->p.display_height;
889 /*vp9_read_frame_size(rb, &cm->display_width,
890 * &cm->display_height);
891 */
892 } else {
893 if (print_header_info)
894 pr_info(" * 1-bit display_size_present read : 0\n");
895 }
896}
897
898
899uint8_t print_header_info = 0;
900
901struct buff_s {
902 u32 buf_start;
903 u32 buf_size;
904 u32 buf_end;
905} buff_t;
906
907struct BuffInfo_s {
908 u32 max_width;
909 u32 max_height;
910 u32 start_adr;
911 u32 end_adr;
912 struct buff_s ipp;
913 struct buff_s sao_abv;
914 struct buff_s sao_vb;
915 struct buff_s short_term_rps;
916 struct buff_s vps;
917 struct buff_s sps;
918 struct buff_s pps;
919 struct buff_s sao_up;
920 struct buff_s swap_buf;
921 struct buff_s swap_buf2;
922 struct buff_s scalelut;
923 struct buff_s dblk_para;
924 struct buff_s dblk_data;
925 struct buff_s seg_map;
926 struct buff_s mmu_vbh;
927 struct buff_s cm_header;
928 struct buff_s mpred_above;
929#ifdef MV_USE_FIXED_BUF
930 struct buff_s mpred_mv;
931#endif
932 struct buff_s rpm;
933 struct buff_s lmem;
934} BuffInfo_t;
935#ifdef MULTI_INSTANCE_SUPPORT
936#define DEC_RESULT_NONE 0
937#define DEC_RESULT_DONE 1
938#define DEC_RESULT_AGAIN 2
939#define DEC_RESULT_CONFIG_PARAM 3
940#define DEC_RESULT_ERROR 4
941#define DEC_INIT_PICLIST 5
942#define DEC_UNINIT_PICLIST 6
943#define DEC_RESULT_GET_DATA 7
944#define DEC_RESULT_GET_DATA_RETRY 8
945#define DEC_RESULT_EOS 9
946#define DEC_RESULT_FORCE_EXIT 10
947#define DEC_V4L2_CONTINUE_DECODING 18
948
949#define DEC_S1_RESULT_NONE 0
950#define DEC_S1_RESULT_DONE 1
951#define DEC_S1_RESULT_FORCE_EXIT 2
952#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0
953
954#ifdef FB_DECODING_TEST_SCHEDULE
955#define TEST_SET_NONE 0
956#define TEST_SET_PIC_DONE 1
957#define TEST_SET_S2_DONE 2
958#endif
959
960static void vp9_work(struct work_struct *work);
961#endif
962struct loop_filter_info_n;
963struct loopfilter;
964struct segmentation;
965
966#ifdef SUPPORT_FB_DECODING
967static void mpred_process(struct VP9Decoder_s *pbi);
968static void vp9_s1_work(struct work_struct *work);
969
970struct stage_buf_s {
971 int index;
972 unsigned short rpm[RPM_END - RPM_BEGIN];
973};
974
975static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM];
976
977static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM];
978
979#ifdef FB_DECODING_TEST_SCHEDULE
980u32 stage_buf_num; /* = 16;*/
981#else
982u32 stage_buf_num;
983#endif
984#endif
985
986struct VP9Decoder_s {
987#ifdef MULTI_INSTANCE_SUPPORT
988 unsigned char index;
989
990 struct device *cma_dev;
991 struct platform_device *platform_dev;
992 void (*vdec_cb)(struct vdec_s *, void *);
993 void *vdec_cb_arg;
994 struct vframe_chunk_s *chunk;
995 int dec_result;
996 struct work_struct work;
997 struct work_struct set_clk_work;
998 u32 start_shift_bytes;
999
1000 struct BuffInfo_s work_space_buf_store;
1001 unsigned long buf_start;
1002 u32 buf_size;
1003 u32 cma_alloc_count;
1004 unsigned long cma_alloc_addr;
1005 uint8_t eos;
1006 unsigned long int start_process_time;
1007 unsigned last_lcu_idx;
1008 int decode_timeout_count;
1009 unsigned timeout_num;
1010 int save_buffer_mode;
1011
1012 int double_write_mode;
1013#endif
1014 long used_4k_num;
1015
1016 unsigned char m_ins_flag;
1017 char *provider_name;
1018 union param_u param;
1019 int frame_count;
1020 int pic_count;
1021 u32 stat;
1022 struct timer_list timer;
1023 u32 frame_dur;
1024 u32 frame_ar;
1025 int fatal_error;
1026 uint8_t init_flag;
1027 uint8_t first_sc_checked;
1028 uint8_t process_busy;
1029#define PROC_STATE_INIT 0
1030#define PROC_STATE_DECODESLICE 1
1031#define PROC_STATE_SENDAGAIN 2
1032 uint8_t process_state;
1033 u32 ucode_pause_pos;
1034
1035 int show_frame_num;
1036 struct buff_s mc_buf_spec;
1037 struct dec_sysinfo vvp9_amstream_dec_info;
1038 void *rpm_addr;
1039 void *lmem_addr;
1040 dma_addr_t rpm_phy_addr;
1041 dma_addr_t lmem_phy_addr;
1042 unsigned short *lmem_ptr;
1043 unsigned short *debug_ptr;
1044
1045 void *prob_buffer_addr;
1046 void *count_buffer_addr;
1047 dma_addr_t prob_buffer_phy_addr;
1048 dma_addr_t count_buffer_phy_addr;
1049
1050 void *frame_mmu_map_addr;
1051 dma_addr_t frame_mmu_map_phy_addr;
1052
1053 unsigned int use_cma_flag;
1054
1055 struct BUF_s m_BUF[MAX_BUF_NUM];
1056 struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM];
1057 u32 used_buf_num;
1058 DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE);
1059 DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE);
1060 DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE);
1061 struct vframe_s vfpool[VF_POOL_SIZE];
1062 u32 vf_pre_count;
1063 u32 vf_get_count;
1064 u32 vf_put_count;
1065 int buf_num;
1066 int pic_num;
1067 int lcu_size_log2;
1068 unsigned int losless_comp_body_size;
1069
1070 u32 video_signal_type;
1071
1072 int pts_mode;
1073 int last_lookup_pts;
1074 int last_pts;
1075 u64 last_lookup_pts_us64;
1076 u64 last_pts_us64;
1077 u64 shift_byte_count;
1078
1079 u32 pts_unstable;
1080 u32 frame_cnt_window;
1081 u32 pts1, pts2;
1082 u32 last_duration;
1083 u32 duration_from_pts_done;
1084 bool vp9_first_pts_ready;
1085
1086 u32 shift_byte_count_lo;
1087 u32 shift_byte_count_hi;
1088 int pts_mode_switching_count;
1089 int pts_mode_recovery_count;
1090
1091 bool get_frame_dur;
1092 u32 saved_resolution;
1093
1094 /**/
1095 struct VP9_Common_s common;
1096 struct RefCntBuffer_s *cur_buf;
1097 int refresh_frame_flags;
1098 uint8_t need_resync;
1099 uint8_t hold_ref_buf;
1100 uint8_t ready_for_new_data;
1101 struct BufferPool_s vp9_buffer_pool;
1102
1103 struct BuffInfo_s *work_space_buf;
1104
1105 struct buff_s *mc_buf;
1106
1107 unsigned int frame_width;
1108 unsigned int frame_height;
1109
1110 unsigned short *rpm_ptr;
1111 int init_pic_w;
1112 int init_pic_h;
1113 int lcu_total;
1114 int lcu_size;
1115
1116 int slice_type;
1117
1118 int skip_flag;
1119 int decode_idx;
1120 int slice_idx;
1121 uint8_t has_keyframe;
1122 uint8_t wait_buf;
1123 uint8_t error_flag;
1124
1125 /* bit 0, for decoding; bit 1, for displaying */
1126 uint8_t ignore_bufmgr_error;
1127 int PB_skip_mode;
1128 int PB_skip_count_after_decoding;
1129 /*hw*/
1130
1131 /*lf*/
1132 int default_filt_lvl;
1133 struct loop_filter_info_n *lfi;
1134 struct loopfilter *lf;
1135 struct segmentation *seg_4lf;
1136 /**/
1137 struct vdec_info *gvs;
1138
1139 u32 pre_stream_offset;
1140
1141 unsigned int dec_status;
1142 u32 last_put_idx;
1143 int new_frame_displayed;
1144 void *mmu_box;
1145 void *bmmu_box;
1146 int mmu_enable;
1147 struct vframe_master_display_colour_s vf_dp;
1148 struct firmware_s *fw;
1149 int max_pic_w;
1150 int max_pic_h;
1151#ifdef SUPPORT_FB_DECODING
1152 int dec_s1_result;
1153 int s1_test_cmd;
1154 struct work_struct s1_work;
1155 int used_stage_buf_num;
1156 int s1_pos;
1157 int s2_pos;
1158 void *stage_mmu_map_addr;
1159 dma_addr_t stage_mmu_map_phy_addr;
1160 struct stage_buf_s *s1_buf;
1161 struct stage_buf_s *s2_buf;
1162 struct stage_buf_s *stage_bufs
1163 [STAGE_MAX_BUFFERS];
1164 unsigned char run2_busy;
1165
1166 int s1_mv_buf_index;
1167 int s1_mv_buf_index_pre;
1168 int s1_mv_buf_index_pre_pre;
1169 unsigned long s1_mpred_mv_wr_start_addr;
1170 unsigned long s1_mpred_mv_wr_start_addr_pre;
1171 unsigned short s1_intra_only;
1172 unsigned short s1_frame_type;
1173 unsigned short s1_width;
1174 unsigned short s1_height;
1175 unsigned short s1_last_show_frame;
1176 union param_u s1_param;
1177 u8 back_not_run_ready;
1178#endif
1179 int need_cache_size;
1180 u64 sc_start_time;
1181 bool postproc_done;
1182 int low_latency_flag;
1183 bool no_head;
1184 bool pic_list_init_done;
1185 bool pic_list_init_done2;
1186 bool is_used_v4l;
1187 void *v4l2_ctx;
1188 bool v4l_params_parsed;
1189 int frameinfo_enable;
1190 struct vframe_qos_s vframe_qos;
1191 u32 mem_map_mode;
1192 u32 dynamic_buf_num_margin;
1193 struct vframe_s vframe_dummy;
1194};
1195
1196static int vp9_print(struct VP9Decoder_s *pbi,
1197 int flag, const char *fmt, ...)
1198{
1199#define HEVC_PRINT_BUF 256
1200 unsigned char buf[HEVC_PRINT_BUF];
1201 int len = 0;
1202
1203 if (pbi == NULL ||
1204 (flag == 0) ||
1205 (debug & flag)) {
1206 va_list args;
1207
1208 va_start(args, fmt);
1209 if (pbi)
1210 len = sprintf(buf, "[%d]", pbi->index);
1211 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1212 pr_debug("%s", buf);
1213 va_end(args);
1214 }
1215 return 0;
1216}
1217
1218static int is_oversize(int w, int h)
1219{
1220 int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)?
1221 MAX_SIZE_8K : MAX_SIZE_4K;
1222
1223 if (w <= 0 || h <= 0)
1224 return true;
1225
1226 if (h != 0 && (w > max / h))
1227 return true;
1228
1229 return false;
1230}
1231
1232static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
1233 struct PIC_BUFFER_CONFIG_s *pic);
1234
1235static void resize_context_buffers(struct VP9Decoder_s *pbi,
1236 struct VP9_Common_s *cm, int width, int height)
1237{
1238 if (cm->width != width || cm->height != height) {
1239 /* to do ..*/
1240 if (pbi != NULL) {
1241 pbi->vp9_first_pts_ready = 0;
1242 pbi->duration_from_pts_done = 0;
1243 }
1244 pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width,
1245 cm->height, width, height);
1246 cm->width = width;
1247 cm->height = height;
1248 }
1249 /*
1250 *if (cm->cur_frame->mvs == NULL ||
1251 * cm->mi_rows > cm->cur_frame->mi_rows ||
1252 * cm->mi_cols > cm->cur_frame->mi_cols) {
1253 * resize_mv_buffer(cm);
1254 *}
1255 */
1256}
1257
1258static int valid_ref_frame_size(int ref_width, int ref_height,
1259 int this_width, int this_height) {
1260 return 2 * this_width >= ref_width &&
1261 2 * this_height >= ref_height &&
1262 this_width <= 16 * ref_width &&
1263 this_height <= 16 * ref_height;
1264}
1265
1266/*
1267 *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth,
1268 * int ref_xss, int ref_yss,
1269 * enum vpx_bit_depth_t this_bit_depth,
1270 * int this_xss, int this_yss) {
1271 * return ref_bit_depth == this_bit_depth && ref_xss == this_xss &&
1272 * ref_yss == this_yss;
1273 *}
1274 */
1275
1276
1277static int setup_frame_size(
1278 struct VP9Decoder_s *pbi,
1279 struct VP9_Common_s *cm, union param_u *params,
1280 unsigned int *mmu_index_adr,
1281 int print_header_info) {
1282 int width, height;
1283 struct BufferPool_s * const pool = cm->buffer_pool;
1284 struct PIC_BUFFER_CONFIG_s *ybf;
1285 int ret = 0;
1286
1287 width = params->p.width;
1288 height = params->p.height;
1289 if (is_oversize(width, height)) {
1290 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1291 return -1;
1292 }
1293
1294 /*vp9_read_frame_size(rb, &width, &height);*/
1295 if (print_header_info)
1296 pr_info(" * 16-bits w read : %d (width : %d)\n", width, height);
1297 if (print_header_info)
1298 pr_info
1299 (" * 16-bits h read : %d (height : %d)\n", width, height);
1300
1301 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1302#ifdef VP9_10B_HED_FB
1303 WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
1304#endif
1305 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1306 ret = vp9_alloc_mmu(pbi,
1307 cm->new_fb_idx,
1308 params->p.width,
1309 params->p.height,
1310 params->p.bit_depth,
1311 mmu_index_adr);
1312 if (ret != 0) {
1313 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
1314 cm->new_fb_idx,
1315 ret);
1316 return ret;
1317 }
1318 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1319 }
1320
1321 resize_context_buffers(pbi, cm, width, height);
1322 setup_display_size(cm, params, print_header_info);
1323#if 0
1324 lock_buffer_pool(pool);
1325 if (vp9_realloc_frame_buffer(
1326 get_frame_new_buffer(cm), cm->width, cm->height,
1327 cm->subsampling_x, cm->subsampling_y,
1328#if CONFIG_VP9_HIGHBITDEPTH
1329 cm->use_highbitdepth,
1330#endif
1331 VP9_DEC_BORDER_IN_PIXELS,
1332 cm->byte_alignment,
1333 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1334 pool->get_fb_cb, pool->cb_priv)) {
1335 unlock_buffer_pool(pool);
1336 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1337 "Failed to allocate frame buffer");
1338 }
1339 unlock_buffer_pool(pool);
1340#else
1341 /* porting */
1342 ybf = get_frame_new_buffer(cm);
1343 if (!ybf)
1344 return -1;
1345
1346 ybf->y_crop_width = width;
1347 ybf->y_crop_height = height;
1348 ybf->bit_depth = params->p.bit_depth;
1349#endif
1350 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1351 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1352 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1353 (unsigned int)cm->bit_depth;
1354 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1355 return ret;
1356}
1357
1358static int setup_frame_size_with_refs(
1359 struct VP9Decoder_s *pbi,
1360 struct VP9_Common_s *cm,
1361 union param_u *params,
1362 unsigned int *mmu_index_adr,
1363 int print_header_info) {
1364
1365 int width, height;
1366 int found = 0, i;
1367 int has_valid_ref_frame = 0;
1368 struct PIC_BUFFER_CONFIG_s *ybf;
1369 struct BufferPool_s * const pool = cm->buffer_pool;
1370 int ret = 0;
1371
1372 for (i = 0; i < REFS_PER_FRAME; ++i) {
1373 if ((params->p.same_frame_size >>
1374 (REFS_PER_FRAME - i - 1)) & 0x1) {
1375 struct PIC_BUFFER_CONFIG_s *const buf =
1376 cm->frame_refs[i].buf;
1377 /*if (print_header_info)
1378 * pr_info
1379 * ("1-bit same_frame_size[%d] read : 1\n", i);
1380 */
1381 width = buf->y_crop_width;
1382 height = buf->y_crop_height;
1383 /*if (print_header_info)
1384 * pr_info
1385 * (" - same_frame_size width : %d\n", width);
1386 */
1387 /*if (print_header_info)
1388 * pr_info
1389 * (" - same_frame_size height : %d\n", height);
1390 */
1391 found = 1;
1392 break;
1393 } else {
1394 /*if (print_header_info)
1395 * pr_info
1396 * ("1-bit same_frame_size[%d] read : 0\n", i);
1397 */
1398 }
1399 }
1400
1401 if (!found) {
1402 /*vp9_read_frame_size(rb, &width, &height);*/
1403 width = params->p.width;
1404 height = params->p.height;
1405 /*if (print_header_info)
1406 * pr_info
1407 * (" * 16-bits w read : %d (width : %d)\n",
1408 * width, height);
1409 *if (print_header_info)
1410 * pr_info
1411 * (" * 16-bits h read : %d (height : %d)\n",
1412 * width, height);
1413 */
1414 }
1415
1416 if (is_oversize(width, height)) {
1417 vp9_print(pbi, 0, "%s, Error: Invalid frame size\n", __func__);
1418 return -1;
1419 }
1420
1421 params->p.width = width;
1422 params->p.height = height;
1423
1424 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
1425 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
1426 /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);
1427 *cm->prev_fb_idx = cm->new_fb_idx;
1428 */
1429 /* pr_info
1430 * ("[DEBUG DEBUG]Before alloc_mmu,
1431 * prev_fb_idx : %d, new_fb_idx : %d\r\n",
1432 * cm->prev_fb_idx, cm->new_fb_idx);
1433 */
1434 ret = vp9_alloc_mmu(pbi, cm->new_fb_idx,
1435 params->p.width, params->p.height,
1436 params->p.bit_depth, mmu_index_adr);
1437 if (ret != 0) {
1438 pr_err("can't alloc need mmu,idx %d\r\n",
1439 cm->new_fb_idx);
1440 return ret;
1441 }
1442 cm->cur_fb_idx_mmu = cm->new_fb_idx;
1443 }
1444
1445 /*Check to make sure at least one of frames that this frame references
1446 *has valid dimensions.
1447 */
1448 for (i = 0; i < REFS_PER_FRAME; ++i) {
1449 struct RefBuffer_s * const ref_frame = &cm->frame_refs[i];
1450
1451 has_valid_ref_frame |=
1452 valid_ref_frame_size(ref_frame->buf->y_crop_width,
1453 ref_frame->buf->y_crop_height,
1454 width, height);
1455 }
1456 if (!has_valid_ref_frame) {
1457 pr_err("Error: Referenced frame has invalid size\r\n");
1458 return -1;
1459 }
1460#if 0
1461 for (i = 0; i < REFS_PER_FRAME; ++i) {
1462 struct RefBuffer_s * const ref_frame =
1463 &cm->frame_refs[i];
1464 if (!valid_ref_frame_img_fmt(
1465 ref_frame->buf->bit_depth,
1466 ref_frame->buf->subsampling_x,
1467 ref_frame->buf->subsampling_y,
1468 cm->bit_depth,
1469 cm->subsampling_x,
1470 cm->subsampling_y))
1471 pr_err
1472 ("Referenced frame incompatible color fmt\r\n");
1473 return -1;
1474 }
1475#endif
1476 resize_context_buffers(pbi, cm, width, height);
1477 setup_display_size(cm, params, print_header_info);
1478
1479#if 0
1480 lock_buffer_pool(pool);
1481 if (vp9_realloc_frame_buffer(
1482 get_frame_new_buffer(cm), cm->width, cm->height,
1483 cm->subsampling_x, cm->subsampling_y,
1484#if CONFIG_VP9_HIGHBITDEPTH
1485 cm->use_highbitdepth,
1486#endif
1487 VP9_DEC_BORDER_IN_PIXELS,
1488 cm->byte_alignment,
1489 &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer,
1490 pool->get_fb_cb,
1491 pool->cb_priv)) {
1492 unlock_buffer_pool(pool);
1493 vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR,
1494 "Failed to allocate frame buffer");
1495 }
1496 unlock_buffer_pool(pool);
1497#else
1498 /* porting */
1499 ybf = get_frame_new_buffer(cm);
1500 if (!ybf)
1501 return -1;
1502
1503 ybf->y_crop_width = width;
1504 ybf->y_crop_height = height;
1505 ybf->bit_depth = params->p.bit_depth;
1506#endif
1507 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x;
1508 pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y;
1509 pool->frame_bufs[cm->new_fb_idx].buf.bit_depth =
1510 (unsigned int)cm->bit_depth;
1511 pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space;
1512 return ret;
1513}
1514
1515static inline bool close_to(int a, int b, int m)
1516{
1517 return (abs(a - b) < m) ? true : false;
1518}
1519
1520#ifdef MULTI_INSTANCE_SUPPORT
1521static int vp9_print_cont(struct VP9Decoder_s *pbi,
1522 int flag, const char *fmt, ...)
1523{
1524 unsigned char buf[HEVC_PRINT_BUF];
1525 int len = 0;
1526
1527 if (pbi == NULL ||
1528 (flag == 0) ||
1529 (debug & flag)) {
1530 va_list args;
1531
1532 va_start(args, fmt);
1533 vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args);
1534 pr_debug("%s", buf);
1535 va_end(args);
1536 }
1537 return 0;
1538}
1539
1540static void trigger_schedule(struct VP9Decoder_s *pbi)
1541{
1542 if (pbi->is_used_v4l) {
1543 struct aml_vcodec_ctx *ctx =
1544 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
1545
1546 if (ctx->param_sets_from_ucode &&
1547 !pbi->v4l_params_parsed)
1548 vdec_v4l_write_frame_sync(ctx);
1549 }
1550
1551 if (pbi->vdec_cb)
1552 pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg);
1553}
1554
1555static void reset_process_time(struct VP9Decoder_s *pbi)
1556{
1557 if (pbi->start_process_time) {
1558 unsigned process_time =
1559 1000 * (jiffies - pbi->start_process_time) / HZ;
1560 pbi->start_process_time = 0;
1561 if (process_time > max_process_time[pbi->index])
1562 max_process_time[pbi->index] = process_time;
1563 }
1564}
1565
1566static void start_process_time(struct VP9Decoder_s *pbi)
1567{
1568 pbi->start_process_time = jiffies;
1569 pbi->decode_timeout_count = 0;
1570 pbi->last_lcu_idx = 0;
1571}
1572
1573static void timeout_process(struct VP9Decoder_s *pbi)
1574{
1575 pbi->timeout_num++;
1576 amhevc_stop();
1577 vp9_print(pbi,
1578 0, "%s decoder timeout\n", __func__);
1579
1580 pbi->dec_result = DEC_RESULT_DONE;
1581 reset_process_time(pbi);
1582 vdec_schedule_work(&pbi->work);
1583}
1584
1585static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi)
1586{
1587 return ((double_write_mode & 0x80000000) == 0) ?
1588 pbi->double_write_mode :
1589 (double_write_mode & 0x7fffffff);
1590}
1591
1592static int get_double_write_mode(struct VP9Decoder_s *pbi)
1593{
1594 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1595 u32 dw;
1596 int w, h;
1597 struct VP9_Common_s *cm = &pbi->common;
1598 struct PIC_BUFFER_CONFIG_s *cur_pic_config;
1599
1600 /* mask for supporting double write value bigger than 0x100 */
1601 if (valid_dw_mode & 0xffffff00) {
1602 if (!cm->cur_frame)
1603 return 1;/*no valid frame,*/
1604 cur_pic_config = &cm->cur_frame->buf;
1605 w = cur_pic_config->y_crop_width;
1606 h = cur_pic_config->y_crop_height;
1607
1608 dw = 0x1; /*1:1*/
1609 switch (valid_dw_mode) {
1610 case 0x100:
1611 if (w > 1920 && h > 1088)
1612 dw = 0x4; /*1:2*/
1613 break;
1614 case 0x200:
1615 if (w > 1920 && h > 1088)
1616 dw = 0x2; /*1:4*/
1617 break;
1618 case 0x300:
1619 if (w > 1280 && h > 720)
1620 dw = 0x4; /*1:2*/
1621 break;
1622 default:
1623 break;
1624 }
1625 return dw;
1626 }
1627
1628 return valid_dw_mode;
1629}
1630
1631/* for double write buf alloc */
1632static int get_double_write_mode_init(struct VP9Decoder_s *pbi)
1633{
1634 u32 valid_dw_mode = get_valid_double_write_mode(pbi);
1635 u32 dw;
1636 int w = pbi->init_pic_w;
1637 int h = pbi->init_pic_h;
1638
1639 dw = 0x1; /*1:1*/
1640 switch (valid_dw_mode) {
1641 case 0x100:
1642 if (w > 1920 && h > 1088)
1643 dw = 0x4; /*1:2*/
1644 break;
1645 case 0x200:
1646 if (w > 1920 && h > 1088)
1647 dw = 0x2; /*1:4*/
1648 break;
1649 case 0x300:
1650 if (w > 1280 && h > 720)
1651 dw = 0x4; /*1:2*/
1652 break;
1653 default:
1654 dw = valid_dw_mode;
1655 break;
1656 }
1657 return dw;
1658}
1659#endif
1660
1661static int get_double_write_ratio(struct VP9Decoder_s *pbi,
1662 int dw_mode)
1663{
1664 int ratio = 1;
1665 if ((dw_mode == 2) ||
1666 (dw_mode == 3))
1667 ratio = 4;
1668 else if (dw_mode == 4)
1669 ratio = 2;
1670 return ratio;
1671}
1672
1673//#define MAX_4K_NUM 0x1200
1674
1675int vp9_alloc_mmu(
1676 struct VP9Decoder_s *pbi,
1677 int cur_buf_idx,
1678 int pic_width,
1679 int pic_height,
1680 unsigned short bit_depth,
1681 unsigned int *mmu_index_adr)
1682{
1683 int bit_depth_10 = (bit_depth == VPX_BITS_10);
1684 int picture_size;
1685 int cur_mmu_4k_number, max_frame_num;
1686 if (!pbi->mmu_box) {
1687 pr_err("error no mmu box!\n");
1688 return -1;
1689 }
1690 if (pbi->double_write_mode & 0x10)
1691 return 0;
1692 if (bit_depth >= VPX_BITS_12) {
1693 pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW;
1694 pr_err("fatal_error, un support bit depth 12!\n\n");
1695 return -1;
1696 }
1697 picture_size = compute_losless_comp_body_size(pic_width, pic_height,
1698 bit_depth_10);
1699 cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
1700
1701 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
1702 max_frame_num = MAX_FRAME_8K_NUM;
1703 else
1704 max_frame_num = MAX_FRAME_4K_NUM;
1705
1706 if (cur_mmu_4k_number > max_frame_num) {
1707 pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
1708 cur_mmu_4k_number, pic_width, pic_height);
1709 return -1;
1710 }
1711 return decoder_mmu_box_alloc_idx(
1712 pbi->mmu_box,
1713 cur_buf_idx,
1714 cur_mmu_4k_number,
1715 mmu_index_adr);
1716}
1717
1718
1719#ifndef MV_USE_FIXED_BUF
1720static void dealloc_mv_bufs(struct VP9Decoder_s *pbi)
1721{
1722 int i;
1723 for (i = 0; i < MV_BUFFER_NUM; i++) {
1724 if (pbi->m_mv_BUF[i].start_adr) {
1725 if (debug)
1726 pr_info(
1727 "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n",
1728 i, pbi->m_mv_BUF[i].start_adr,
1729 pbi->m_mv_BUF[i].size,
1730 pbi->m_mv_BUF[i].used_flag);
1731 decoder_bmmu_box_free_idx(
1732 pbi->bmmu_box,
1733 MV_BUFFER_IDX(i));
1734 pbi->m_mv_BUF[i].start_adr = 0;
1735 pbi->m_mv_BUF[i].size = 0;
1736 pbi->m_mv_BUF[i].used_flag = 0;
1737 }
1738 }
1739}
1740
1741static int alloc_mv_buf(struct VP9Decoder_s *pbi,
1742 int i, int size)
1743{
1744 int ret = 0;
1745 if (decoder_bmmu_box_alloc_buf_phy
1746 (pbi->bmmu_box,
1747 MV_BUFFER_IDX(i), size,
1748 DRIVER_NAME,
1749 &pbi->m_mv_BUF[i].start_adr) < 0) {
1750 pbi->m_mv_BUF[i].start_adr = 0;
1751 ret = -1;
1752 } else {
1753 pbi->m_mv_BUF[i].size = size;
1754 pbi->m_mv_BUF[i].used_flag = 0;
1755 ret = 0;
1756 if (debug) {
1757 pr_info(
1758 "MV Buffer %d: start_adr %p size %x\n",
1759 i,
1760 (void *)pbi->m_mv_BUF[i].start_adr,
1761 pbi->m_mv_BUF[i].size);
1762 }
1763 }
1764 return ret;
1765}
1766
1767static int init_mv_buf_list(struct VP9Decoder_s *pbi)
1768{
1769 int i;
1770 int ret = 0;
1771 int count = MV_BUFFER_NUM;
1772 int pic_width = pbi->init_pic_w;
1773 int pic_height = pbi->init_pic_h;
1774 int lcu_size = 64; /*fixed 64*/
1775 int pic_width_64 = (pic_width + 63) & (~0x3f);
1776 int pic_height_32 = (pic_height + 31) & (~0x1f);
1777 int pic_width_lcu = (pic_width_64 % lcu_size) ?
1778 pic_width_64 / lcu_size + 1
1779 : pic_width_64 / lcu_size;
1780 int pic_height_lcu = (pic_height_32 % lcu_size) ?
1781 pic_height_32 / lcu_size + 1
1782 : pic_height_32 / lcu_size;
1783 int lcu_total = pic_width_lcu * pic_height_lcu;
1784 int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
1785 (~0xffff);
1786 if (mv_buf_margin > 0)
1787 count = REF_FRAMES + mv_buf_margin;
1788
1789 if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
1790 count = REF_FRAMES_4K + mv_buf_margin;
1791
1792 if (debug) {
1793 pr_info("%s w:%d, h:%d, count: %d\n",
1794 __func__, pbi->init_pic_w, pbi->init_pic_h, count);
1795 }
1796
1797 for (i = 0;
1798 i < count && i < MV_BUFFER_NUM; i++) {
1799 if (alloc_mv_buf(pbi, i, size) < 0) {
1800 ret = -1;
1801 break;
1802 }
1803 }
1804 return ret;
1805}
1806
1807static int get_mv_buf(struct VP9Decoder_s *pbi,
1808 int *mv_buf_index,
1809 unsigned long *mpred_mv_wr_start_addr)
1810{
1811 int i;
1812 int ret = -1;
1813 for (i = 0; i < MV_BUFFER_NUM; i++) {
1814 if (pbi->m_mv_BUF[i].start_adr &&
1815 pbi->m_mv_BUF[i].used_flag == 0) {
1816 pbi->m_mv_BUF[i].used_flag = 1;
1817 ret = i;
1818 break;
1819 }
1820 }
1821
1822 if (ret >= 0) {
1823 *mv_buf_index = ret;
1824 *mpred_mv_wr_start_addr =
1825 (pbi->m_mv_BUF[ret].start_adr + 0xffff) &
1826 (~0xffff);
1827 if (debug & VP9_DEBUG_BUFMGR_MORE)
1828 pr_info(
1829 "%s => %d (%ld) size 0x%x\n",
1830 __func__, ret,
1831 *mpred_mv_wr_start_addr,
1832 pbi->m_mv_BUF[ret].size);
1833 } else {
1834 pr_info(
1835 "%s: Error, mv buf is not enough\n",
1836 __func__);
1837 }
1838 return ret;
1839}
1840
1841static void put_mv_buf(struct VP9Decoder_s *pbi,
1842 int *mv_buf_index)
1843{
1844 int i = *mv_buf_index;
1845 if (i >= MV_BUFFER_NUM) {
1846 if (debug & VP9_DEBUG_BUFMGR_MORE)
1847 pr_info(
1848 "%s: index %d beyond range\n",
1849 __func__, i);
1850 return;
1851 }
1852 if (debug & VP9_DEBUG_BUFMGR_MORE)
1853 pr_info(
1854 "%s(%d): used_flag(%d)\n",
1855 __func__, i,
1856 pbi->m_mv_BUF[i].used_flag);
1857
1858 *mv_buf_index = -1;
1859 if (pbi->m_mv_BUF[i].start_adr &&
1860 pbi->m_mv_BUF[i].used_flag)
1861 pbi->m_mv_BUF[i].used_flag = 0;
1862}
1863
1864static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi)
1865{
1866 struct VP9_Common_s *const cm = &pbi->common;
1867 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
1868 int i;
1869 for (i = 0; i < pbi->used_buf_num; ++i) {
1870 if ((frame_bufs[i].ref_count == 0) &&
1871 (frame_bufs[i].buf.index != -1) &&
1872 (frame_bufs[i].buf.mv_buf_index >= 0)
1873 )
1874 put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index);
1875 }
1876}
1877
1878#ifdef SUPPORT_FB_DECODING
1879static bool mv_buf_available(struct VP9Decoder_s *pbi)
1880{
1881 int i;
1882 bool ret = 0;
1883 for (i = 0; i < MV_BUFFER_NUM; i++) {
1884 if (pbi->m_mv_BUF[i].start_adr &&
1885 pbi->m_mv_BUF[i].used_flag == 0) {
1886 ret = 1;
1887 break;
1888 }
1889 }
1890 return ret;
1891}
1892#endif
1893#endif
1894
1895#ifdef SUPPORT_FB_DECODING
1896static void init_stage_buf(struct VP9Decoder_s *pbi)
1897{
1898 uint i;
1899 for (i = 0; i < STAGE_MAX_BUFFERS
1900 && i < stage_buf_num; i++) {
1901 pbi->stage_bufs[i] =
1902 vmalloc(sizeof(struct stage_buf_s));
1903 if (pbi->stage_bufs[i] == NULL) {
1904 vp9_print(pbi,
1905 0, "%s vmalloc fail\n", __func__);
1906 break;
1907 }
1908 pbi->stage_bufs[i]->index = i;
1909 }
1910 pbi->used_stage_buf_num = i;
1911 pbi->s1_pos = 0;
1912 pbi->s2_pos = 0;
1913 pbi->s1_buf = NULL;
1914 pbi->s2_buf = NULL;
1915 pbi->s1_mv_buf_index = FRAME_BUFFERS;
1916 pbi->s1_mv_buf_index_pre = FRAME_BUFFERS;
1917 pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS;
1918
1919 if (pbi->used_stage_buf_num > 0)
1920 vp9_print(pbi,
1921 0, "%s 2 stage decoding buf %d\n",
1922 __func__,
1923 pbi->used_stage_buf_num);
1924}
1925
1926static void uninit_stage_buf(struct VP9Decoder_s *pbi)
1927{
1928 int i;
1929 for (i = 0; i < pbi->used_stage_buf_num; i++) {
1930 if (pbi->stage_bufs[i])
1931 vfree(pbi->stage_bufs[i]);
1932 pbi->stage_bufs[i] = NULL;
1933 }
1934 pbi->used_stage_buf_num = 0;
1935 pbi->s1_pos = 0;
1936 pbi->s2_pos = 0;
1937 pbi->s1_buf = NULL;
1938 pbi->s2_buf = NULL;
1939}
1940
1941static int get_s1_buf(
1942 struct VP9Decoder_s *pbi)
1943{
1944 struct stage_buf_s *buf = NULL;
1945 int ret = -1;
1946 int buf_page_num = MAX_STAGE_PAGE_NUM;
1947 int next_s1_pos = pbi->s1_pos + 1;
1948
1949 if (next_s1_pos >= pbi->used_stage_buf_num)
1950 next_s1_pos = 0;
1951 if (next_s1_pos == pbi->s2_pos) {
1952 pbi->s1_buf = NULL;
1953 return ret;
1954 }
1955
1956 buf = pbi->stage_bufs[pbi->s1_pos];
1957 ret = decoder_mmu_box_alloc_idx(
1958 pbi->mmu_box,
1959 buf->index,
1960 buf_page_num,
1961 pbi->stage_mmu_map_addr);
1962 if (ret < 0) {
1963 vp9_print(pbi, 0,
1964 "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n",
1965 __func__, buf->index,
1966 pbi->s1_pos, pbi->s2_pos);
1967 buf = NULL;
1968 } else {
1969 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1970 "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n",
1971 __func__, buf_page_num, buf->index,
1972 pbi->s1_pos, pbi->s2_pos);
1973 }
1974 pbi->s1_buf = buf;
1975 return ret;
1976}
1977
1978static void inc_s1_pos(struct VP9Decoder_s *pbi)
1979{
1980 struct stage_buf_s *buf =
1981 pbi->stage_bufs[pbi->s1_pos];
1982
1983 int used_page_num =
1984#ifdef FB_DECODING_TEST_SCHEDULE
1985 MAX_STAGE_PAGE_NUM/2;
1986#else
1987 (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16);
1988#endif
1989 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
1990 FRAME_BUFFERS + buf->index, used_page_num);
1991
1992 pbi->s1_pos++;
1993 if (pbi->s1_pos >= pbi->used_stage_buf_num)
1994 pbi->s1_pos = 0;
1995
1996 vp9_print(pbi, VP9_DEBUG_2_STAGE,
1997 "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n",
1998 __func__, used_page_num, buf->index,
1999 pbi->s1_pos, pbi->s2_pos);
2000}
2001
2002#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos)
2003
2004static int get_s2_buf(
2005 struct VP9Decoder_s *pbi)
2006{
2007 int ret = -1;
2008 struct stage_buf_s *buf = NULL;
2009 if (s2_buf_available(pbi)) {
2010 buf = pbi->stage_bufs[pbi->s2_pos];
2011 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2012 "%s for index %d (s1_pos %d s2_pos %d)\n",
2013 __func__, buf->index,
2014 pbi->s1_pos, pbi->s2_pos);
2015 pbi->s2_buf = buf;
2016 ret = 0;
2017 }
2018 return ret;
2019}
2020
2021static void inc_s2_pos(struct VP9Decoder_s *pbi)
2022{
2023 struct stage_buf_s *buf =
2024 pbi->stage_bufs[pbi->s2_pos];
2025 decoder_mmu_box_free_idx(pbi->mmu_box,
2026 FRAME_BUFFERS + buf->index);
2027 pbi->s2_pos++;
2028 if (pbi->s2_pos >= pbi->used_stage_buf_num)
2029 pbi->s2_pos = 0;
2030 vp9_print(pbi, VP9_DEBUG_2_STAGE,
2031 "%s for index %d (s1_pos %d s2_pos %d)\n",
2032 __func__, buf->index,
2033 pbi->s1_pos, pbi->s2_pos);
2034}
2035
2036static int get_free_stage_buf_num(struct VP9Decoder_s *pbi)
2037{
2038 int num;
2039 if (pbi->s1_pos >= pbi->s2_pos)
2040 num = pbi->used_stage_buf_num -
2041 (pbi->s1_pos - pbi->s2_pos) - 1;
2042 else
2043 num = (pbi->s2_pos - pbi->s1_pos) - 1;
2044 return num;
2045}
2046
2047#ifndef FB_DECODING_TEST_SCHEDULE
2048static DEFINE_SPINLOCK(fb_core_spin_lock);
2049
2050static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi)
2051{
2052 /* to do: VLSI review
2053 completion of last LCU decoding in BACK
2054 */
2055 return 1;
2056}
2057
2058static void start_s1_decoding(struct VP9Decoder_s *pbi)
2059{
2060 /* to do: VLSI review
2061 after parser, how to start LCU decoding in BACK
2062 */
2063}
2064
2065static void fb_reset_core(struct vdec_s *vdec, u32 mask)
2066{
2067 /* to do: VLSI review
2068 1. how to disconnect DMC for FRONT and BACK
2069 2. reset bit 13, 24, FRONT or BACK ??
2070 */
2071
2072 unsigned long flags;
2073 u32 reset_bits = 0;
2074 if (mask & HW_MASK_FRONT)
2075 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2076 spin_lock_irqsave(&fb_core_spin_lock, flags);
2077 codec_dmcbus_write(DMC_REQ_CTRL,
2078 codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4)));
2079 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2080
2081 while (!(codec_dmcbus_read(DMC_CHAN_STS)
2082 & (1 << 4)))
2083 ;
2084
2085 if ((mask & HW_MASK_FRONT) &&
2086 input_frame_based(vdec))
2087 WRITE_VREG(HEVC_STREAM_CONTROL, 0);
2088
2089 /*
2090 * 2: assist
2091 * 3: parser
2092 * 4: parser_state
2093 * 8: dblk
2094 * 11:mcpu
2095 * 12:ccpu
2096 * 13:ddr
2097 * 14:iqit
2098 * 15:ipp
2099 * 17:qdct
2100 * 18:mpred
2101 * 19:sao
2102 * 24:hevc_afifo
2103 */
2104 if (mask & HW_MASK_FRONT) {
2105 reset_bits =
2106 (1<<3)|(1<<4)|(1<<11)|
2107 (1<<12)|(1<<18);
2108 }
2109 if (mask & HW_MASK_BACK) {
2110 reset_bits =
2111 (1<<8)|(1<<13)|(1<<14)|(1<<15)|
2112 (1<<17)|(1<<19)|(1<<24);
2113 }
2114 WRITE_VREG(DOS_SW_RESET3, reset_bits);
2115#if 0
2116 (1<<3)|(1<<4)|(1<<8)|(1<<11)|
2117 (1<<12)|(1<<13)|(1<<14)|(1<<15)|
2118 (1<<17)|(1<<18)|(1<<19)|(1<<24);
2119#endif
2120 WRITE_VREG(DOS_SW_RESET3, 0);
2121
2122
2123 spin_lock_irqsave(&fb_core_spin_lock, flags);
2124 codec_dmcbus_write(DMC_REQ_CTRL,
2125 codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4));
2126 spin_unlock_irqrestore(&fb_core_spin_lock, flags);
2127
2128}
2129#endif
2130
2131#endif
2132
2133static void init_pic_list_hw(struct VP9Decoder_s *pbi);
2134
2135static int get_free_fb(struct VP9Decoder_s *pbi)
2136{
2137 struct VP9_Common_s *const cm = &pbi->common;
2138 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2139 int i;
2140 unsigned long flags;
2141
2142 lock_buffer_pool(cm->buffer_pool, flags);
2143 if (debug & VP9_DEBUG_BUFMGR_MORE) {
2144 for (i = 0; i < pbi->used_buf_num; ++i) {
2145 pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n",
2146 __func__, i, frame_bufs[i].ref_count,
2147 frame_bufs[i].buf.vf_ref,
2148 frame_bufs[i].buf.index);
2149 }
2150 }
2151 for (i = 0; i < pbi->used_buf_num; ++i) {
2152 if ((frame_bufs[i].ref_count == 0) &&
2153 (frame_bufs[i].buf.vf_ref == 0) &&
2154 (frame_bufs[i].buf.index != -1)
2155 )
2156 break;
2157 }
2158 if (i != pbi->used_buf_num) {
2159 frame_bufs[i].ref_count = 1;
2160 /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n",
2161 i, frame_bufs[i].ref_count);*/
2162 } else {
2163 /* Reset i to be INVALID_IDX to indicate
2164 no free buffer found*/
2165 i = INVALID_IDX;
2166 }
2167
2168 unlock_buffer_pool(cm->buffer_pool, flags);
2169 return i;
2170}
2171
2172static int v4l_get_free_fb(struct VP9Decoder_s *pbi)
2173{
2174 struct VP9_Common_s *const cm = &pbi->common;
2175 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2176 struct aml_vcodec_ctx * v4l = pbi->v4l2_ctx;
2177 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2178 int i, idx = INVALID_IDX;
2179 ulong flags;
2180
2181 lock_buffer_pool(cm->buffer_pool, flags);
2182
2183 for (i = 0; i < pbi->used_buf_num; ++i) {
2184 struct v4l_buff_pool *pool = &v4l->cap_pool;
2185 u32 state = (pool->seq[i] >> 16);
2186 u32 index = (pool->seq[i] & 0xffff);
2187
2188 switch (state) {
2189 case V4L_CAP_BUFF_IN_DEC:
2190 pic = &frame_bufs[i].buf;
2191 if ((frame_bufs[i].ref_count == 0) &&
2192 (pic->vf_ref == 0) &&
2193 (pic->index != -1) &&
2194 pic->cma_alloc_addr) {
2195 idx = i;
2196 }
2197 break;
2198 case V4L_CAP_BUFF_IN_M2M:
2199 pic = &frame_bufs[index].buf;
2200 pic->y_crop_width = pbi->frame_width;
2201 pic->y_crop_height = pbi->frame_height;
2202 if (!v4l_alloc_and_config_pic(pbi, pic)) {
2203 set_canvas(pbi, pic);
2204 init_pic_list_hw(pbi);
2205 idx = index;
2206 }
2207 break;
2208 default:
2209 pr_err("v4l buffer state err %d.\n", state);
2210 break;
2211 }
2212
2213 if (idx != INVALID_IDX) {
2214 frame_bufs[idx].ref_count = 1;
2215 break;
2216 }
2217 }
2218
2219 unlock_buffer_pool(cm->buffer_pool, flags);
2220
2221 return idx;
2222}
2223
2224static int get_free_buf_count(struct VP9Decoder_s *pbi)
2225{
2226 struct VP9_Common_s *const cm = &pbi->common;
2227 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2228 int i;
2229 int free_buf_count = 0;
2230 for (i = 0; i < pbi->used_buf_num; ++i)
2231 if ((frame_bufs[i].ref_count == 0) &&
2232 (frame_bufs[i].buf.vf_ref == 0) &&
2233 (frame_bufs[i].buf.index != -1)
2234 )
2235 free_buf_count++;
2236 return free_buf_count;
2237}
2238
2239static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs,
2240 struct BufferPool_s *const pool)
2241{
2242 if (idx >= 0) {
2243 --frame_bufs[idx].ref_count;
2244 /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx,
2245 * frame_bufs[idx].ref_count);
2246 */
2247 /*A worker may only get a free framebuffer index when
2248 *calling get_free_fb. But the private buffer is not set up
2249 *until finish decoding header. So any error happens during
2250 *decoding header, the frame_bufs will not have valid priv
2251 *buffer.
2252 */
2253
2254 if (frame_bufs[idx].ref_count == 0 &&
2255 frame_bufs[idx].raw_frame_buffer.priv)
2256 vp9_release_frame_buffer
2257 (&frame_bufs[idx].raw_frame_buffer);
2258 }
2259}
2260
2261static void generate_next_ref_frames(struct VP9Decoder_s *pbi)
2262{
2263 struct VP9_Common_s *const cm = &pbi->common;
2264 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2265 struct BufferPool_s *const pool = cm->buffer_pool;
2266 int mask, ref_index = 0;
2267 unsigned long flags;
2268
2269 /* Generate next_ref_frame_map.*/
2270 lock_buffer_pool(pool, flags);
2271 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2272 if (mask & 1) {
2273 cm->next_ref_frame_map[ref_index] = cm->new_fb_idx;
2274 ++frame_bufs[cm->new_fb_idx].ref_count;
2275 /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n",
2276 *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count);
2277 */
2278 } else
2279 cm->next_ref_frame_map[ref_index] =
2280 cm->ref_frame_map[ref_index];
2281 /* Current thread holds the reference frame.*/
2282 if (cm->ref_frame_map[ref_index] >= 0) {
2283 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2284 /*pr_info
2285 *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n",
2286 *cm->ref_frame_map[ref_index],
2287 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2288 */
2289 }
2290 ++ref_index;
2291 }
2292
2293 for (; ref_index < REF_FRAMES; ++ref_index) {
2294 cm->next_ref_frame_map[ref_index] =
2295 cm->ref_frame_map[ref_index];
2296 /* Current thread holds the reference frame.*/
2297 if (cm->ref_frame_map[ref_index] >= 0) {
2298 ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count;
2299 /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n",
2300 *cm->ref_frame_map[ref_index],
2301 *frame_bufs[cm->ref_frame_map[ref_index]].ref_count);
2302 */
2303 }
2304 }
2305 unlock_buffer_pool(pool, flags);
2306 return;
2307}
2308
2309static void refresh_ref_frames(struct VP9Decoder_s *pbi)
2310
2311{
2312 struct VP9_Common_s *const cm = &pbi->common;
2313 struct BufferPool_s *pool = cm->buffer_pool;
2314 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2315 int mask, ref_index = 0;
2316 unsigned long flags;
2317
2318 lock_buffer_pool(pool, flags);
2319 for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) {
2320 const int old_idx = cm->ref_frame_map[ref_index];
2321 /*Current thread releases the holding of reference frame.*/
2322 decrease_ref_count(old_idx, frame_bufs, pool);
2323
2324 /*Release the reference frame in reference map.*/
2325 if ((mask & 1) && old_idx >= 0)
2326 decrease_ref_count(old_idx, frame_bufs, pool);
2327 cm->ref_frame_map[ref_index] =
2328 cm->next_ref_frame_map[ref_index];
2329 ++ref_index;
2330 }
2331
2332 /*Current thread releases the holding of reference frame.*/
2333 for (; ref_index < REF_FRAMES && !cm->show_existing_frame;
2334 ++ref_index) {
2335 const int old_idx = cm->ref_frame_map[ref_index];
2336
2337 decrease_ref_count(old_idx, frame_bufs, pool);
2338 cm->ref_frame_map[ref_index] =
2339 cm->next_ref_frame_map[ref_index];
2340 }
2341 unlock_buffer_pool(pool, flags);
2342 return;
2343}
2344
2345int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params)
2346{
2347 struct VP9_Common_s *const cm = &pbi->common;
2348 struct BufferPool_s *pool = cm->buffer_pool;
2349 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
2350 struct PIC_BUFFER_CONFIG_s *pic = NULL;
2351 int i;
2352 int ret;
2353
2354 pbi->ready_for_new_data = 0;
2355
2356 if (pbi->has_keyframe == 0 &&
2357 params->p.frame_type != KEY_FRAME){
2358 on_no_keyframe_skiped++;
2359 return -2;
2360 }
2361 pbi->has_keyframe = 1;
2362 on_no_keyframe_skiped = 0;
2363#if 0
2364 if (pbi->mmu_enable) {
2365 if (!pbi->m_ins_flag)
2366 pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
2367 if (cm->prev_fb_idx >= 0) {
2368 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
2369 cm->prev_fb_idx, pbi->used_4k_num);
2370 }
2371 }
2372#endif
2373 if (cm->new_fb_idx >= 0
2374 && frame_bufs[cm->new_fb_idx].ref_count == 0){
2375 vp9_release_frame_buffer
2376 (&frame_bufs[cm->new_fb_idx].raw_frame_buffer);
2377 }
2378 /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2379 cm->prev_fb_idx, cm->new_fb_idx);*/
2380#ifndef MV_USE_FIXED_BUF
2381 put_un_used_mv_bufs(pbi);
2382 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2383 dump_pic_list(pbi);
2384#endif
2385 cm->new_fb_idx = pbi->is_used_v4l ?
2386 v4l_get_free_fb(pbi) :
2387 get_free_fb(pbi);
2388 if (cm->new_fb_idx == INVALID_IDX) {
2389 pr_info("get_free_fb error\r\n");
2390 return -1;
2391 }
2392#ifndef MV_USE_FIXED_BUF
2393#ifdef SUPPORT_FB_DECODING
2394 if (pbi->used_stage_buf_num == 0) {
2395#endif
2396 if (get_mv_buf(pbi,
2397 &pool->frame_bufs[cm->new_fb_idx].
2398 buf.mv_buf_index,
2399 &pool->frame_bufs[cm->new_fb_idx].
2400 buf.mpred_mv_wr_start_addr
2401 ) < 0) {
2402 pr_info("get_mv_buf fail\r\n");
2403 return -1;
2404 }
2405 if (debug & VP9_DEBUG_BUFMGR_DETAIL)
2406 dump_pic_list(pbi);
2407#ifdef SUPPORT_FB_DECODING
2408 }
2409#endif
2410#endif
2411 cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx];
2412 /*if (debug & VP9_DEBUG_BUFMGR)
2413 pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__,
2414 cm->new_fb_idx);*/
2415
2416 pbi->cur_buf = &frame_bufs[cm->new_fb_idx];
2417 if (pbi->mmu_enable) {
2418 /* moved to after picture size ready
2419 *alloc_mmu(cm, params->p.width, params->p.height,
2420 *params->p.bit_depth, pbi->frame_mmu_map_addr);
2421 */
2422 cm->prev_fb_idx = cm->new_fb_idx;
2423 }
2424 /*read_uncompressed_header()*/
2425 cm->last_frame_type = cm->frame_type;
2426 cm->last_intra_only = cm->intra_only;
2427 cm->profile = params->p.profile;
2428 if (cm->profile >= MAX_PROFILES) {
2429 pr_err("Error: Unsupported profile %d\r\n", cm->profile);
2430 return -1;
2431 }
2432 cm->show_existing_frame = params->p.show_existing_frame;
2433 if (cm->show_existing_frame) {
2434 /* Show an existing frame directly.*/
2435 int frame_to_show_idx = params->p.frame_to_show_idx;
2436 int frame_to_show;
2437 unsigned long flags;
2438 if (frame_to_show_idx >= REF_FRAMES) {
2439 pr_info("frame_to_show_idx %d exceed max index\r\n",
2440 frame_to_show_idx);
2441 return -1;
2442 }
2443
2444 frame_to_show = cm->ref_frame_map[frame_to_show_idx];
2445 /*pr_info("frame_to_show %d\r\n", frame_to_show);*/
2446 lock_buffer_pool(pool, flags);
2447 if (frame_to_show < 0 ||
2448 frame_bufs[frame_to_show].ref_count < 1) {
2449 unlock_buffer_pool(pool, flags);
2450 pr_err
2451 ("Error:Buffer %d does not contain a decoded frame",
2452 frame_to_show);
2453 return -1;
2454 }
2455
2456 ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show);
2457 unlock_buffer_pool(pool, flags);
2458 pbi->refresh_frame_flags = 0;
2459 /*cm->lf.filter_level = 0;*/
2460 cm->show_frame = 1;
2461
2462 /*
2463 *if (pbi->frame_parallel_decode) {
2464 * for (i = 0; i < REF_FRAMES; ++i)
2465 * cm->next_ref_frame_map[i] =
2466 * cm->ref_frame_map[i];
2467 *}
2468 */
2469 /* do not decode, search next start code */
2470 return 1;
2471 }
2472 cm->frame_type = params->p.frame_type;
2473 cm->show_frame = params->p.show_frame;
2474 cm->error_resilient_mode = params->p.error_resilient_mode;
2475
2476
2477 if (cm->frame_type == KEY_FRAME) {
2478 pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1;
2479
2480 for (i = 0; i < REFS_PER_FRAME; ++i) {
2481 cm->frame_refs[i].idx = INVALID_IDX;
2482 cm->frame_refs[i].buf = NULL;
2483 }
2484
2485 ret = setup_frame_size(pbi,
2486 cm, params, pbi->frame_mmu_map_addr,
2487 print_header_info);
2488 if (ret)
2489 return -1;
2490 if (pbi->need_resync) {
2491 memset(&cm->ref_frame_map, -1,
2492 sizeof(cm->ref_frame_map));
2493 pbi->need_resync = 0;
2494 }
2495 } else {
2496 cm->intra_only = cm->show_frame ? 0 : params->p.intra_only;
2497 /*if (print_header_info) {
2498 * if (cm->show_frame)
2499 * pr_info
2500 * ("intra_only set to 0 because of show_frame\n");
2501 * else
2502 * pr_info
2503 * ("1-bit intra_only read: %d\n", cm->intra_only);
2504 *}
2505 */
2506
2507
2508 cm->reset_frame_context = cm->error_resilient_mode ?
2509 0 : params->p.reset_frame_context;
2510 if (print_header_info) {
2511 if (cm->error_resilient_mode)
2512 pr_info
2513 ("reset to 0 error_resilient_mode\n");
2514 else
2515 pr_info
2516 (" * 2-bits reset_frame_context read : %d\n",
2517 cm->reset_frame_context);
2518 }
2519
2520 if (cm->intra_only) {
2521 if (cm->profile > PROFILE_0) {
2522 /*read_bitdepth_colorspace_sampling(cm,
2523 * rb, print_header_info);
2524 */
2525 } else {
2526 /*NOTE: The intra-only frame header
2527 *does not include the specification
2528 *of either the color format or
2529 *color sub-sampling
2530 *in profile 0. VP9 specifies that the default
2531 *color format should be YUV 4:2:0 in this
2532 *case (normative).
2533 */
2534 cm->color_space = VPX_CS_BT_601;
2535 cm->subsampling_y = cm->subsampling_x = 1;
2536 cm->bit_depth = VPX_BITS_8;
2537 cm->use_highbitdepth = 0;
2538 }
2539
2540 pbi->refresh_frame_flags =
2541 params->p.refresh_frame_flags;
2542 /*if (print_header_info)
2543 * pr_info("*%d-bits refresh_frame read:0x%x\n",
2544 * REF_FRAMES, pbi->refresh_frame_flags);
2545 */
2546 ret = setup_frame_size(pbi,
2547 cm,
2548 params,
2549 pbi->frame_mmu_map_addr,
2550 print_header_info);
2551 if (ret)
2552 return -1;
2553 if (pbi->need_resync) {
2554 memset(&cm->ref_frame_map, -1,
2555 sizeof(cm->ref_frame_map));
2556 pbi->need_resync = 0;
2557 }
2558 } else if (pbi->need_resync != 1) { /* Skip if need resync */
2559 pbi->refresh_frame_flags =
2560 params->p.refresh_frame_flags;
2561 if (print_header_info)
2562 pr_info
2563 ("*%d-bits refresh_frame read:0x%x\n",
2564 REF_FRAMES, pbi->refresh_frame_flags);
2565 for (i = 0; i < REFS_PER_FRAME; ++i) {
2566 const int ref =
2567 (params->p.ref_info >>
2568 (((REFS_PER_FRAME-i-1)*4)+1))
2569 & 0x7;
2570 const int idx =
2571 cm->ref_frame_map[ref];
2572 struct RefBuffer_s * const ref_frame =
2573 &cm->frame_refs[i];
2574 if (print_header_info)
2575 pr_info("*%d-bits ref[%d]read:%d\n",
2576 REF_FRAMES_LOG2, i, ref);
2577 ref_frame->idx = idx;
2578 ref_frame->buf = &frame_bufs[idx].buf;
2579 cm->ref_frame_sign_bias[LAST_FRAME + i]
2580 = (params->p.ref_info >>
2581 ((REFS_PER_FRAME-i-1)*4)) & 0x1;
2582 if (print_header_info)
2583 pr_info("1bit ref_frame_sign_bias");
2584 /*pr_info
2585 *("%dread: %d\n",
2586 *LAST_FRAME+i,
2587 *cm->ref_frame_sign_bias
2588 *[LAST_FRAME + i]);
2589 */
2590 /*pr_info
2591 *("[VP9 DEBUG]%s(get ref):%d\r\n",
2592 *__func__, ref_frame->idx);
2593 */
2594
2595 }
2596
2597 ret = setup_frame_size_with_refs(
2598 pbi,
2599 cm,
2600 params,
2601 pbi->frame_mmu_map_addr,
2602 print_header_info);
2603 if (ret)
2604 return -1;
2605 for (i = 0; i < REFS_PER_FRAME; ++i) {
2606 /*struct RefBuffer_s *const ref_buf =
2607 *&cm->frame_refs[i];
2608 */
2609 /* to do:
2610 *vp9_setup_scale_factors_for_frame
2611 */
2612 }
2613 }
2614 }
2615
2616 pic = get_frame_new_buffer(cm);
2617 if (!pic)
2618 return -1;
2619
2620 pic->bit_depth = cm->bit_depth;
2621 pic->color_space = cm->color_space;
2622 pic->slice_type = cm->frame_type;
2623
2624 if (pbi->need_resync) {
2625 pr_err
2626 ("Error: Keyframe/intra-only frame required to reset\r\n");
2627 return -1;
2628 }
2629 generate_next_ref_frames(pbi);
2630 pbi->hold_ref_buf = 1;
2631
2632#if 0
2633 if (frame_is_intra_only(cm) || cm->error_resilient_mode)
2634 vp9_setup_past_independence(cm);
2635 setup_loopfilter(&cm->lf, rb, print_header_info);
2636 setup_quantization(cm, &pbi->mb, rb, print_header_info);
2637 setup_segmentation(&cm->seg, rb, print_header_info);
2638 setup_segmentation_dequant(cm, print_header_info);
2639
2640 setup_tile_info(cm, rb, print_header_info);
2641 sz = vp9_rb_read_literal(rb, 16);
2642 if (print_header_info)
2643 pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz);
2644
2645 if (sz == 0)
2646 vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME,
2647 "Invalid header size");
2648#endif
2649 /*end read_uncompressed_header()*/
2650 cm->use_prev_frame_mvs = !cm->error_resilient_mode &&
2651 cm->width == cm->last_width &&
2652 cm->height == cm->last_height &&
2653 !cm->last_intra_only &&
2654 cm->last_show_frame &&
2655 (cm->last_frame_type != KEY_FRAME);
2656
2657 /*pr_info
2658 *("set use_prev_frame_mvs to %d (last_width %d last_height %d",
2659 *cm->use_prev_frame_mvs, cm->last_width, cm->last_height);
2660 *pr_info
2661 *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n",
2662 *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type);
2663 */
2664 return 0;
2665}
2666
2667
2668void swap_frame_buffers(struct VP9Decoder_s *pbi)
2669{
2670 int ref_index = 0;
2671 struct VP9_Common_s *const cm = &pbi->common;
2672 struct BufferPool_s *const pool = cm->buffer_pool;
2673 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
2674 unsigned long flags;
2675 refresh_ref_frames(pbi);
2676 pbi->hold_ref_buf = 0;
2677 cm->frame_to_show = get_frame_new_buffer(cm);
2678
2679 if (cm->frame_to_show) {
2680 /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/
2681 lock_buffer_pool(pool, flags);
2682 --frame_bufs[cm->new_fb_idx].ref_count;
2683 /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx,
2684 * frame_bufs[cm->new_fb_idx].ref_count);
2685 */
2686 unlock_buffer_pool(pool, flags);
2687 /*}*/
2688 }
2689
2690 /*Invalidate these references until the next frame starts.*/
2691 for (ref_index = 0; ref_index < 3; ref_index++)
2692 cm->frame_refs[ref_index].idx = -1;
2693}
2694
2695#if 0
2696static void check_resync(vpx_codec_alg_priv_t *const ctx,
2697 const struct VP9Decoder_s *const pbi)
2698{
2699 /* Clear resync flag if worker got a key frame or intra only frame.*/
2700 if (ctx->need_resync == 1 && pbi->need_resync == 0 &&
2701 (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME))
2702 ctx->need_resync = 0;
2703}
2704#endif
2705
2706int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd)
2707{
2708 struct VP9_Common_s *const cm = &pbi->common;
2709 int ret = -1;
2710
2711 if (pbi->ready_for_new_data == 1)
2712 return ret;
2713
2714 pbi->ready_for_new_data = 1;
2715
2716 /* no raw frame to show!!! */
2717 if (!cm->show_frame)
2718 return ret;
2719
2720 /* may not be get buff in v4l2 */
2721 if (!cm->frame_to_show)
2722 return ret;
2723
2724 pbi->ready_for_new_data = 1;
2725
2726 *sd = *cm->frame_to_show;
2727 ret = 0;
2728
2729 return ret;
2730}
2731
2732int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
2733 struct buff_s *mc_buf_i) {
2734 struct VP9_Common_s *cm = &pbi->common;
2735
2736 /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
2737 pbi->frame_count = 0;
2738 pbi->pic_count = 0;
2739 pbi->pre_stream_offset = 0;
2740 cm->buffer_pool = &pbi->vp9_buffer_pool;
2741 spin_lock_init(&cm->buffer_pool->lock);
2742 cm->prev_fb_idx = INVALID_IDX;
2743 cm->new_fb_idx = INVALID_IDX;
2744 pbi->used_4k_num = -1;
2745 cm->cur_fb_idx_mmu = INVALID_IDX;
2746 pr_debug
2747 ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n",
2748 cm->prev_fb_idx, cm->new_fb_idx);
2749 pbi->need_resync = 1;
2750 /* Initialize the references to not point to any frame buffers.*/
2751 memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map));
2752 memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map));
2753 cm->current_video_frame = 0;
2754 pbi->ready_for_new_data = 1;
2755
2756 /* private init */
2757 pbi->work_space_buf = buf_spec_i;
2758 if (!pbi->mmu_enable)
2759 pbi->mc_buf = mc_buf_i;
2760
2761 pbi->rpm_addr = NULL;
2762 pbi->lmem_addr = NULL;
2763
2764 pbi->use_cma_flag = 0;
2765 pbi->decode_idx = 0;
2766 pbi->slice_idx = 0;
2767 /*int m_uiMaxCUWidth = 1<<7;*/
2768 /*int m_uiMaxCUHeight = 1<<7;*/
2769 pbi->has_keyframe = 0;
2770 pbi->skip_flag = 0;
2771 pbi->wait_buf = 0;
2772 pbi->error_flag = 0;
2773
2774 pbi->pts_mode = PTS_NORMAL;
2775 pbi->last_pts = 0;
2776 pbi->last_lookup_pts = 0;
2777 pbi->last_pts_us64 = 0;
2778 pbi->last_lookup_pts_us64 = 0;
2779 pbi->shift_byte_count = 0;
2780 pbi->shift_byte_count_lo = 0;
2781 pbi->shift_byte_count_hi = 0;
2782 pbi->pts_mode_switching_count = 0;
2783 pbi->pts_mode_recovery_count = 0;
2784
2785 pbi->buf_num = 0;
2786 pbi->pic_num = 0;
2787
2788 return 0;
2789}
2790
2791int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi)
2792{
2793 struct VP9_Common_s *cm = &pbi->common;
2794 struct PIC_BUFFER_CONFIG_s sd;
2795
2796 if (pbi->postproc_done)
2797 return 0;
2798 pbi->postproc_done = 1;
2799 swap_frame_buffers(pbi);
2800 if (!cm->show_existing_frame) {
2801 cm->last_show_frame = cm->show_frame;
2802 cm->prev_frame = cm->cur_frame;
2803#if 0
2804 if (cm->seg.enabled && !pbi->frame_parallel_decode)
2805 vp9_swap_current_and_last_seg_map(cm);
2806#endif
2807 }
2808 cm->last_width = cm->width;
2809 cm->last_height = cm->height;
2810 if (cm->show_frame)
2811 cm->current_video_frame++;
2812
2813 if (vp9_get_raw_frame(pbi, &sd) == 0) {
2814 /*pr_info("Display frame index %d\r\n", sd.index);*/
2815 sd.stream_offset = pbi->pre_stream_offset;
2816 prepare_display_buf(pbi, &sd);
2817 pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
2818 }
2819
2820/* else
2821 * pr_info
2822 * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n",
2823 * pbi->ready_for_new_data, cm->show_frame);
2824 */
2825 return 0;
2826}
2827
2828/*struct VP9Decoder_s vp9_decoder;*/
2829union param_u vp9_param;
2830
2831/**************************************************
2832 *
2833 *VP9 buffer management end
2834 *
2835 ***************************************************
2836 */
2837
2838
2839#define HEVC_CM_BODY_START_ADDR 0x3626
2840#define HEVC_CM_BODY_LENGTH 0x3627
2841#define HEVC_CM_HEADER_LENGTH 0x3629
2842#define HEVC_CM_HEADER_OFFSET 0x362b
2843
2844#define LOSLESS_COMPRESS_MODE
2845
2846/*#define DECOMP_HEADR_SURGENT*/
2847#ifdef VP9_10B_NV21
2848static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
2849#else
2850static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
2851#endif
2852static u32 enable_mem_saving = 1;
2853static u32 force_w_h;
2854
2855static u32 force_fps;
2856
2857
2858const u32 vp9_version = 201602101;
2859static u32 debug;
2860static u32 radr;
2861static u32 rval;
2862static u32 pop_shorts;
2863static u32 dbg_cmd;
2864static u32 dbg_skip_decode_index;
2865static u32 endian = 0xff0;
2866#ifdef ERROR_HANDLE_DEBUG
2867static u32 dbg_nal_skip_flag;
2868 /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */
2869static u32 dbg_nal_skip_count;
2870#endif
2871/*for debug*/
2872static u32 decode_pic_begin;
2873static uint slice_parse_begin;
2874static u32 step;
2875#ifdef MIX_STREAM_SUPPORT
2876static u32 buf_alloc_width = 4096;
2877static u32 buf_alloc_height = 2304;
2878static u32 vp9_max_pic_w = 4096;
2879static u32 vp9_max_pic_h = 2304;
2880
2881static u32 dynamic_buf_num_margin;
2882#else
2883static u32 buf_alloc_width;
2884static u32 buf_alloc_height;
2885static u32 dynamic_buf_num_margin = 7;
2886#endif
2887static u32 buf_alloc_depth = 10;
2888static u32 buf_alloc_size;
2889/*
2890 *bit[0]: 0,
2891 * bit[1]: 0, always release cma buffer when stop
2892 * bit[1]: 1, never release cma buffer when stop
2893 *bit[0]: 1, when stop, release cma buffer if blackout is 1;
2894 *do not release cma buffer is blackout is not 1
2895 *
2896 *bit[2]: 0, when start decoding, check current displayed buffer
2897 * (only for buffer decoded by vp9) if blackout is 0
2898 * 1, do not check current displayed buffer
2899 *
2900 *bit[3]: 1, if blackout is not 1, do not release current
2901 * displayed cma buffer always.
2902 */
2903/* set to 1 for fast play;
2904 * set to 8 for other case of "keep last frame"
2905 */
2906static u32 buffer_mode = 1;
2907/* buffer_mode_dbg: debug only*/
2908static u32 buffer_mode_dbg = 0xffff0000;
2909/**/
2910
2911/*
2912 *bit 0, 1: only display I picture;
2913 *bit 1, 1: only decode I picture;
2914 */
2915static u32 i_only_flag;
2916
2917static u32 low_latency_flag;
2918
2919static u32 no_head;
2920
2921static u32 max_decoding_time;
2922/*
2923 *error handling
2924 */
2925/*error_handle_policy:
2926 *bit 0: 0, auto skip error_skip_nal_count nals before error recovery;
2927 *1, skip error_skip_nal_count nals before error recovery;
2928 *bit 1 (valid only when bit0 == 1):
2929 *1, wait vps/sps/pps after error recovery;
2930 *bit 2 (valid only when bit0 == 0):
2931 *0, auto search after error recovery (vp9_recover() called);
2932 *1, manual search after error recovery
2933 *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2))
2934 *
2935 *bit 4: 0, set error_mark after reset/recover
2936 * 1, do not set error_mark after reset/recover
2937 *bit 5: 0, check total lcu for every picture
2938 * 1, do not check total lcu
2939 *
2940 */
2941
2942static u32 error_handle_policy;
2943/*static u32 parser_sei_enable = 1;*/
2944#define MAX_BUF_NUM_NORMAL 12
2945#define MAX_BUF_NUM_LESS 10
2946static u32 max_buf_num = MAX_BUF_NUM_NORMAL;
2947#define MAX_BUF_NUM_SAVE_BUF 8
2948
2949static u32 run_ready_min_buf_num = 2;
2950
2951
2952static DEFINE_MUTEX(vvp9_mutex);
2953#ifndef MULTI_INSTANCE_SUPPORT
2954static struct device *cma_dev;
2955#endif
2956
2957#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
2958#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
2959#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
2960#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3
2961#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4
2962#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
2963#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6
2964#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
2965#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
2966#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9
2967#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A
2968#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B
2969#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D
2970#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E
2971#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F
2972#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F
2973#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L
2974#ifdef MULTI_INSTANCE_SUPPORT
2975#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M
2976#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N
2977#else
2978#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M
2979#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N
2980#endif
2981#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G
2982#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H
2983
2984
2985/*
2986 *ucode parser/search control
2987 *bit 0: 0, header auto parse; 1, header manual parse
2988 *bit 1: 0, auto skip for noneseamless stream; 1, no skip
2989 *bit [3:2]: valid when bit1==0;
2990 *0, auto skip nal before first vps/sps/pps/idr;
2991 *1, auto skip nal before first vps/sps/pps
2992 *2, auto skip nal before first vps/sps/pps,
2993 * and not decode until the first I slice (with slice address of 0)
2994 *
2995 *3, auto skip before first I slice (nal_type >=16 && nal_type<=21)
2996 *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) )
2997 *bit [16]: for NAL_UNIT_EOS when bit0 is 0:
2998 * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm
2999 *bit [17]: for NAL_SEI when bit0 is 0:
3000 * 0, do not parse SEI in ucode; 1, parse SEI in ucode
3001 *bit [31:20]: used by ucode for debug purpose
3002 */
3003#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I
3004 /*[31:24] chip feature
3005 31: 0, use MBOX1; 1, use MBOX0
3006 */
3007#define DECODE_MODE HEVC_ASSIST_SCRATCH_J
3008#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K
3009
3010#ifdef MULTI_INSTANCE_SUPPORT
3011#define RPM_BUF_SIZE (0x400 * 2)
3012#else
3013#define RPM_BUF_SIZE (0x80*2)
3014#endif
3015#define LMEM_BUF_SIZE (0x400 * 2)
3016
3017#define WORK_BUF_SPEC_NUM 3
3018static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
3019 {
3020 /* 8M bytes */
3021 .max_width = 1920,
3022 .max_height = 1088,
3023 .ipp = {
3024 /* IPP work space calculation :
3025 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3026 */
3027 .buf_size = 0x4000,
3028 },
3029 .sao_abv = {
3030 .buf_size = 0x30000,
3031 },
3032 .sao_vb = {
3033 .buf_size = 0x30000,
3034 },
3035 .short_term_rps = {
3036 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3037 * total 64x16x2 = 2048 bytes (0x800)
3038 */
3039 .buf_size = 0x800,
3040 },
3041 .vps = {
3042 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3043 * total 0x0800 bytes
3044 */
3045 .buf_size = 0x800,
3046 },
3047 .sps = {
3048 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3049 * total 0x0800 bytes
3050 */
3051 .buf_size = 0x800,
3052 },
3053 .pps = {
3054 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3055 * total 0x2000 bytes
3056 */
3057 .buf_size = 0x2000,
3058 },
3059 .sao_up = {
3060 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3061 * each has 16 bytes total 0x2800 bytes
3062 */
3063 .buf_size = 0x2800,
3064 },
3065 .swap_buf = {
3066 /* 256cyclex64bit = 2K bytes 0x800
3067 * (only 144 cycles valid)
3068 */
3069 .buf_size = 0x800,
3070 },
3071 .swap_buf2 = {
3072 .buf_size = 0x800,
3073 },
3074 .scalelut = {
3075 /* support up to 32 SCALELUT 1024x32 =
3076 * 32Kbytes (0x8000)
3077 */
3078 .buf_size = 0x8000,
3079 },
3080 .dblk_para = {
3081 /* DBLK -> Max 256(4096/16) LCU,
3082 *each para 1024bytes(total:0x40000),
3083 *data 1024bytes(total:0x40000)
3084 */
3085 .buf_size = 0x80000,
3086 },
3087 .dblk_data = {
3088 .buf_size = 0x80000,
3089 },
3090 .seg_map = {
3091 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3092 .buf_size = 0xd800,
3093 },
3094 .mmu_vbh = {
3095 .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/
3096 },
3097#if 0
3098 .cm_header = {
3099 /*add one for keeper.*/
3100 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3101 (FRAME_BUFFERS + 1),
3102 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3103 },
3104#endif
3105 .mpred_above = {
3106 .buf_size = 0x10000, /* 2 * size of hevc*/
3107 },
3108#ifdef MV_USE_FIXED_BUF
3109 .mpred_mv = {/* 1080p, 0x40000 per buffer */
3110 .buf_size = 0x40000 * FRAME_BUFFERS,
3111 },
3112#endif
3113 .rpm = {
3114 .buf_size = RPM_BUF_SIZE,
3115 },
3116 .lmem = {
3117 .buf_size = 0x400 * 2,
3118 }
3119 },
3120 {
3121 .max_width = 4096,
3122 .max_height = 2304,
3123 .ipp = {
3124 /* IPP work space calculation :
3125 * 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3126 */
3127 .buf_size = 0x4000,
3128 },
3129 .sao_abv = {
3130 .buf_size = 0x30000,
3131 },
3132 .sao_vb = {
3133 .buf_size = 0x30000,
3134 },
3135 .short_term_rps = {
3136 /* SHORT_TERM_RPS - Max 64 set, 16 entry every set,
3137 * total 64x16x2 = 2048 bytes (0x800)
3138 */
3139 .buf_size = 0x800,
3140 },
3141 .vps = {
3142 /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes,
3143 * total 0x0800 bytes
3144 */
3145 .buf_size = 0x800,
3146 },
3147 .sps = {
3148 /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes,
3149 * total 0x0800 bytes
3150 */
3151 .buf_size = 0x800,
3152 },
3153 .pps = {
3154 /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes,
3155 * total 0x2000 bytes
3156 */
3157 .buf_size = 0x2000,
3158 },
3159 .sao_up = {
3160 /* SAO UP STORE AREA - Max 640(10240/16) LCU,
3161 * each has 16 bytes total 0x2800 bytes
3162 */
3163 .buf_size = 0x2800,
3164 },
3165 .swap_buf = {
3166 /* 256cyclex64bit = 2K bytes 0x800
3167 * (only 144 cycles valid)
3168 */
3169 .buf_size = 0x800,
3170 },
3171 .swap_buf2 = {
3172 .buf_size = 0x800,
3173 },
3174 .scalelut = {
3175 /* support up to 32 SCALELUT 1024x32 = 32Kbytes
3176 * (0x8000)
3177 */
3178 .buf_size = 0x8000,
3179 },
3180 .dblk_para = {
3181 /* DBLK -> Max 256(4096/16) LCU,
3182 *each para 1024bytes(total:0x40000),
3183 *data 1024bytes(total:0x40000)
3184 */
3185 .buf_size = 0x80000,
3186 },
3187 .dblk_data = {
3188 .buf_size = 0x80000,
3189 },
3190 .seg_map = {
3191 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3192 .buf_size = 0xd800,
3193 },
3194 .mmu_vbh = {
3195 .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/
3196 },
3197#if 0
3198 .cm_header = {
3199 /*add one for keeper.*/
3200 .buf_size = MMU_COMPRESS_HEADER_SIZE *
3201 (FRAME_BUFFERS + 1),
3202 /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */
3203 },
3204#endif
3205 .mpred_above = {
3206 .buf_size = 0x10000, /* 2 * size of hevc*/
3207 },
3208#ifdef MV_USE_FIXED_BUF
3209 .mpred_mv = {
3210 /* .buf_size = 0x100000*16,
3211 * //4k2k , 0x100000 per buffer
3212 */
3213 /* 4096x2304 , 0x120000 per buffer */
3214 .buf_size = 0x120000 * FRAME_BUFFERS,
3215 },
3216#endif
3217 .rpm = {
3218 .buf_size = RPM_BUF_SIZE,
3219 },
3220 .lmem = {
3221 .buf_size = 0x400 * 2,
3222 }
3223 },
3224 {
3225 .max_width = 4096*2,
3226 .max_height = 2304*2,
3227 .ipp = {
3228 // IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
3229 .buf_size = 0x4000*2,
3230 },
3231 .sao_abv = {
3232 .buf_size = 0x30000*2,
3233 },
3234 .sao_vb = {
3235 .buf_size = 0x30000*2,
3236 },
3237 .short_term_rps = {
3238 // SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
3239 .buf_size = 0x800,
3240 },
3241 .vps = {
3242 // VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
3243 .buf_size = 0x800,
3244 },
3245 .sps = {
3246 // SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
3247 .buf_size = 0x800,
3248 },
3249 .pps = {
3250 // PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
3251 .buf_size = 0x2000,
3252 },
3253 .sao_up = {
3254 // SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
3255 .buf_size = 0x2800*2,
3256 },
3257 .swap_buf = {
3258 // 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
3259 .buf_size = 0x800,
3260 },
3261 .swap_buf2 = {
3262 .buf_size = 0x800,
3263 },
3264 .scalelut = {
3265 // support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
3266 .buf_size = 0x8000*2,
3267 },
3268 .dblk_para = {
3269 // DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
3270 .buf_size = 0x80000*2,
3271 },
3272 .dblk_data = {
3273 .buf_size = 0x80000*2,
3274 },
3275 .seg_map = {
3276 /*4096x2304/64/64 *24 = 0xd800 Bytes*/
3277 .buf_size = 0xd800*4,
3278 },
3279 .mmu_vbh = {
3280 .buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
3281 },
3282#if 0
3283 .cm_header = {
3284 //.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3285 .buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
3286 },
3287#endif
3288 .mpred_above = {
3289 .buf_size = 0x10000*2, /* 2 * size of hevc*/
3290 },
3291#ifdef MV_USE_FIXED_BUF
3292 .mpred_mv = {
3293 //4k2k , 0x100000 per buffer */
3294 /* 4096x2304 , 0x120000 per buffer */
3295 .buf_size = 0x120000 * FRAME_BUFFERS * 4,
3296 },
3297#endif
3298 .rpm = {
3299 .buf_size = RPM_BUF_SIZE,
3300 },
3301 .lmem = {
3302 .buf_size = 0x400 * 2,
3303 }
3304 }
3305};
3306
3307
3308/*Losless compression body buffer size 4K per 64x32 (jt)*/
3309int compute_losless_comp_body_size(int width, int height,
3310 uint8_t is_bit_depth_10)
3311{
3312 int width_x64;
3313 int height_x32;
3314 int bsize;
3315
3316 width_x64 = width + 63;
3317 width_x64 >>= 6;
3318 height_x32 = height + 31;
3319 height_x32 >>= 5;
3320 bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32;
3321 if (debug & VP9_DEBUG_BUFMGR_MORE)
3322 pr_info("%s(%d,%d,%d)=>%d\n",
3323 __func__, width, height,
3324 is_bit_depth_10, bsize);
3325
3326 return bsize;
3327}
3328
3329/* Losless compression header buffer size 32bytes per 128x64 (jt)*/
3330static int compute_losless_comp_header_size(int width, int height)
3331{
3332 int width_x128;
3333 int height_x64;
3334 int hsize;
3335
3336 width_x128 = width + 127;
3337 width_x128 >>= 7;
3338 height_x64 = height + 63;
3339 height_x64 >>= 6;
3340
3341 hsize = 32 * width_x128 * height_x64;
3342 if (debug & VP9_DEBUG_BUFMGR_MORE)
3343 pr_info("%s(%d,%d)=>%d\n",
3344 __func__, width, height,
3345 hsize);
3346
3347 return hsize;
3348}
3349
3350static void init_buff_spec(struct VP9Decoder_s *pbi,
3351 struct BuffInfo_s *buf_spec)
3352{
3353 void *mem_start_virt;
3354
3355 buf_spec->ipp.buf_start = buf_spec->start_adr;
3356 buf_spec->sao_abv.buf_start =
3357 buf_spec->ipp.buf_start + buf_spec->ipp.buf_size;
3358
3359 buf_spec->sao_vb.buf_start =
3360 buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size;
3361 buf_spec->short_term_rps.buf_start =
3362 buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size;
3363 buf_spec->vps.buf_start =
3364 buf_spec->short_term_rps.buf_start +
3365 buf_spec->short_term_rps.buf_size;
3366 buf_spec->sps.buf_start =
3367 buf_spec->vps.buf_start + buf_spec->vps.buf_size;
3368 buf_spec->pps.buf_start =
3369 buf_spec->sps.buf_start + buf_spec->sps.buf_size;
3370 buf_spec->sao_up.buf_start =
3371 buf_spec->pps.buf_start + buf_spec->pps.buf_size;
3372 buf_spec->swap_buf.buf_start =
3373 buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size;
3374 buf_spec->swap_buf2.buf_start =
3375 buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size;
3376 buf_spec->scalelut.buf_start =
3377 buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size;
3378 buf_spec->dblk_para.buf_start =
3379 buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size;
3380 buf_spec->dblk_data.buf_start =
3381 buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size;
3382 buf_spec->seg_map.buf_start =
3383 buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size;
3384 if (pbi == NULL || pbi->mmu_enable) {
3385 buf_spec->mmu_vbh.buf_start =
3386 buf_spec->seg_map.buf_start +
3387 buf_spec->seg_map.buf_size;
3388 buf_spec->mpred_above.buf_start =
3389 buf_spec->mmu_vbh.buf_start +
3390 buf_spec->mmu_vbh.buf_size;
3391 } else {
3392 buf_spec->mpred_above.buf_start =
3393 buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size;
3394 }
3395#ifdef MV_USE_FIXED_BUF
3396 buf_spec->mpred_mv.buf_start =
3397 buf_spec->mpred_above.buf_start +
3398 buf_spec->mpred_above.buf_size;
3399
3400 buf_spec->rpm.buf_start =
3401 buf_spec->mpred_mv.buf_start +
3402 buf_spec->mpred_mv.buf_size;
3403#else
3404 buf_spec->rpm.buf_start =
3405 buf_spec->mpred_above.buf_start +
3406 buf_spec->mpred_above.buf_size;
3407
3408#endif
3409 buf_spec->lmem.buf_start =
3410 buf_spec->rpm.buf_start +
3411 buf_spec->rpm.buf_size;
3412 buf_spec->end_adr =
3413 buf_spec->lmem.buf_start +
3414 buf_spec->lmem.buf_size;
3415
3416 if (!pbi)
3417 return;
3418
3419 if (!vdec_secure(hw_to_vdec(pbi))) {
3420 mem_start_virt =
3421 codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start);
3422 if (mem_start_virt) {
3423 memset(mem_start_virt, 0,
3424 buf_spec->dblk_para.buf_size);
3425 codec_mm_dma_flush(mem_start_virt,
3426 buf_spec->dblk_para.buf_size,
3427 DMA_TO_DEVICE);
3428 } else {
3429 mem_start_virt = codec_mm_vmap(
3430 buf_spec->dblk_para.buf_start,
3431 buf_spec->dblk_para.buf_size);
3432 if (mem_start_virt) {
3433 memset(mem_start_virt, 0,
3434 buf_spec->dblk_para.buf_size);
3435 codec_mm_dma_flush(mem_start_virt,
3436 buf_spec->dblk_para.buf_size,
3437 DMA_TO_DEVICE);
3438 codec_mm_unmap_phyaddr(mem_start_virt);
3439 } else {
3440 /*not virt for tvp playing,
3441 may need clear on ucode.*/
3442 pr_err("mem_start_virt failed\n");
3443 }
3444 }
3445 }
3446
3447 if (debug) {
3448 pr_info("%s workspace (%x %x) size = %x\n", __func__,
3449 buf_spec->start_adr, buf_spec->end_adr,
3450 buf_spec->end_adr - buf_spec->start_adr);
3451 }
3452
3453 if (debug) {
3454 pr_info("ipp.buf_start :%x\n",
3455 buf_spec->ipp.buf_start);
3456 pr_info("sao_abv.buf_start :%x\n",
3457 buf_spec->sao_abv.buf_start);
3458 pr_info("sao_vb.buf_start :%x\n",
3459 buf_spec->sao_vb.buf_start);
3460 pr_info("short_term_rps.buf_start :%x\n",
3461 buf_spec->short_term_rps.buf_start);
3462 pr_info("vps.buf_start :%x\n",
3463 buf_spec->vps.buf_start);
3464 pr_info("sps.buf_start :%x\n",
3465 buf_spec->sps.buf_start);
3466 pr_info("pps.buf_start :%x\n",
3467 buf_spec->pps.buf_start);
3468 pr_info("sao_up.buf_start :%x\n",
3469 buf_spec->sao_up.buf_start);
3470 pr_info("swap_buf.buf_start :%x\n",
3471 buf_spec->swap_buf.buf_start);
3472 pr_info("swap_buf2.buf_start :%x\n",
3473 buf_spec->swap_buf2.buf_start);
3474 pr_info("scalelut.buf_start :%x\n",
3475 buf_spec->scalelut.buf_start);
3476 pr_info("dblk_para.buf_start :%x\n",
3477 buf_spec->dblk_para.buf_start);
3478 pr_info("dblk_data.buf_start :%x\n",
3479 buf_spec->dblk_data.buf_start);
3480 pr_info("seg_map.buf_start :%x\n",
3481 buf_spec->seg_map.buf_start);
3482 if (pbi->mmu_enable) {
3483 pr_info("mmu_vbh.buf_start :%x\n",
3484 buf_spec->mmu_vbh.buf_start);
3485 }
3486 pr_info("mpred_above.buf_start :%x\n",
3487 buf_spec->mpred_above.buf_start);
3488#ifdef MV_USE_FIXED_BUF
3489 pr_info("mpred_mv.buf_start :%x\n",
3490 buf_spec->mpred_mv.buf_start);
3491#endif
3492 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
3493 pr_info("rpm.buf_start :%x\n",
3494 buf_spec->rpm.buf_start);
3495 }
3496 }
3497}
3498
3499/* cache_util.c */
3500#define THODIYIL_MCRCC_CANVAS_ALGX 4
3501
3502static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX;
3503
3504static void mcrcc_perfcount_reset(void)
3505{
3506 if (debug & VP9_DEBUG_CACHE)
3507 pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
3508 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
3509 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
3510 return;
3511}
3512
3513static unsigned raw_mcr_cnt_total_prev;
3514static unsigned hit_mcr_0_cnt_total_prev;
3515static unsigned hit_mcr_1_cnt_total_prev;
3516static unsigned byp_mcr_cnt_nchcanv_total_prev;
3517static unsigned byp_mcr_cnt_nchoutwin_total_prev;
3518
3519static void mcrcc_get_hitrate(unsigned reset_pre)
3520{
3521 unsigned delta_hit_mcr_0_cnt;
3522 unsigned delta_hit_mcr_1_cnt;
3523 unsigned delta_raw_mcr_cnt;
3524 unsigned delta_mcr_cnt_nchcanv;
3525 unsigned delta_mcr_cnt_nchoutwin;
3526
3527 unsigned tmp;
3528 unsigned raw_mcr_cnt;
3529 unsigned hit_mcr_cnt;
3530 unsigned byp_mcr_cnt_nchoutwin;
3531 unsigned byp_mcr_cnt_nchcanv;
3532 int hitrate;
3533 if (reset_pre) {
3534 raw_mcr_cnt_total_prev = 0;
3535 hit_mcr_0_cnt_total_prev = 0;
3536 hit_mcr_1_cnt_total_prev = 0;
3537 byp_mcr_cnt_nchcanv_total_prev = 0;
3538 byp_mcr_cnt_nchoutwin_total_prev = 0;
3539 }
3540 if (debug & VP9_DEBUG_CACHE)
3541 pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
3542 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
3543 raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3544 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
3545 hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3546 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
3547 byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3548 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
3549 byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3550
3551 if (debug & VP9_DEBUG_CACHE)
3552 pr_info("raw_mcr_cnt_total: %d\n",
3553 raw_mcr_cnt);
3554 if (debug & VP9_DEBUG_CACHE)
3555 pr_info("hit_mcr_cnt_total: %d\n",
3556 hit_mcr_cnt);
3557 if (debug & VP9_DEBUG_CACHE)
3558 pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",
3559 byp_mcr_cnt_nchoutwin);
3560 if (debug & VP9_DEBUG_CACHE)
3561 pr_info("byp_mcr_cnt_nchcanv_total: %d\n",
3562 byp_mcr_cnt_nchcanv);
3563
3564 delta_raw_mcr_cnt = raw_mcr_cnt -
3565 raw_mcr_cnt_total_prev;
3566 delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv -
3567 byp_mcr_cnt_nchcanv_total_prev;
3568 delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin -
3569 byp_mcr_cnt_nchoutwin_total_prev;
3570 raw_mcr_cnt_total_prev = raw_mcr_cnt;
3571 byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv;
3572 byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin;
3573
3574 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
3575 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3576 if (debug & VP9_DEBUG_CACHE)
3577 pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
3578 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
3579 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3580 if (debug & VP9_DEBUG_CACHE)
3581 pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
3582 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
3583 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3584 if (debug & VP9_DEBUG_CACHE)
3585 pr_info("hit_mcr_0_cnt_total: %d\n", tmp);
3586 delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev;
3587 hit_mcr_0_cnt_total_prev = tmp;
3588 WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
3589 tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
3590 if (debug & VP9_DEBUG_CACHE)
3591 pr_info("hit_mcr_1_cnt_total: %d\n", tmp);
3592 delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev;
3593 hit_mcr_1_cnt_total_prev = tmp;
3594
3595 if (delta_raw_mcr_cnt != 0) {
3596 hitrate = 100 * delta_hit_mcr_0_cnt
3597 / delta_raw_mcr_cnt;
3598 if (debug & VP9_DEBUG_CACHE)
3599 pr_info("CANV0_HIT_RATE : %d\n", hitrate);
3600 hitrate = 100 * delta_hit_mcr_1_cnt
3601 / delta_raw_mcr_cnt;
3602 if (debug & VP9_DEBUG_CACHE)
3603 pr_info("CANV1_HIT_RATE : %d\n", hitrate);
3604 hitrate = 100 * delta_mcr_cnt_nchcanv
3605 / delta_raw_mcr_cnt;
3606 if (debug & VP9_DEBUG_CACHE)
3607 pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate);
3608 hitrate = 100 * delta_mcr_cnt_nchoutwin
3609 / delta_raw_mcr_cnt;
3610 if (debug & VP9_DEBUG_CACHE)
3611 pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate);
3612 }
3613
3614
3615 if (raw_mcr_cnt != 0) {
3616 hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt;
3617 if (debug & VP9_DEBUG_CACHE)
3618 pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
3619 hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
3620 / raw_mcr_cnt;
3621 if (debug & VP9_DEBUG_CACHE)
3622 pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
3623 } else {
3624 if (debug & VP9_DEBUG_CACHE)
3625 pr_info("MCRCC_HIT_RATE : na\n");
3626 if (debug & VP9_DEBUG_CACHE)
3627 pr_info("MCRCC_BYP_RATE : na\n");
3628 }
3629 return;
3630}
3631
3632
3633static void decomp_perfcount_reset(void)
3634{
3635 if (debug & VP9_DEBUG_CACHE)
3636 pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
3637 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
3638 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
3639 return;
3640}
3641
3642static void decomp_get_hitrate(void)
3643{
3644 unsigned raw_mcr_cnt;
3645 unsigned hit_mcr_cnt;
3646 int hitrate;
3647 if (debug & VP9_DEBUG_CACHE)
3648 pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
3649 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
3650 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3651 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
3652 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3653
3654 if (debug & VP9_DEBUG_CACHE)
3655 pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3656 if (debug & VP9_DEBUG_CACHE)
3657 pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3658
3659 if (raw_mcr_cnt != 0) {
3660 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3661 if (debug & VP9_DEBUG_CACHE)
3662 pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
3663 } else {
3664 if (debug & VP9_DEBUG_CACHE)
3665 pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
3666 }
3667 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
3668 raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3669 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
3670 hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3671
3672 if (debug & VP9_DEBUG_CACHE)
3673 pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
3674 if (debug & VP9_DEBUG_CACHE)
3675 pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
3676
3677 if (raw_mcr_cnt != 0) {
3678 hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt;
3679 if (debug & VP9_DEBUG_CACHE)
3680 pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
3681 } else {
3682 if (debug & VP9_DEBUG_CACHE)
3683 pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
3684 }
3685 return;
3686}
3687
3688static void decomp_get_comprate(void)
3689{
3690 unsigned raw_ucomp_cnt;
3691 unsigned fast_comp_cnt;
3692 unsigned slow_comp_cnt;
3693 int comprate;
3694
3695 if (debug & VP9_DEBUG_CACHE)
3696 pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
3697 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
3698 fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3699 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
3700 slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3701 WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
3702 raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
3703
3704 if (debug & VP9_DEBUG_CACHE)
3705 pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
3706 if (debug & VP9_DEBUG_CACHE)
3707 pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
3708 if (debug & VP9_DEBUG_CACHE)
3709 pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
3710
3711 if (raw_ucomp_cnt != 0) {
3712 comprate = (fast_comp_cnt + slow_comp_cnt)
3713 * 100 / raw_ucomp_cnt;
3714 if (debug & VP9_DEBUG_CACHE)
3715 pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
3716 } else {
3717 if (debug & VP9_DEBUG_CACHE)
3718 pr_info("DECOMP_COMP_RATIO : na\n");
3719 }
3720 return;
3721}
3722/* cache_util.c end */
3723
3724/*====================================================
3725 *========================================================================
3726 *vp9_prob define
3727 *========================================================================
3728 */
3729#define VP9_PARTITION_START 0
3730#define VP9_PARTITION_SIZE_STEP (3 * 4)
3731#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP)
3732#define VP9_PARTITION_KEY_START 0
3733#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE
3734#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE)
3735#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE)
3736#define VP9_SKIP_SIZE 4 /* only use 3*/
3737#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE)
3738#define VP9_TX_MODE_8_0_OFFSET 0
3739#define VP9_TX_MODE_8_1_OFFSET 1
3740#define VP9_TX_MODE_16_0_OFFSET 2
3741#define VP9_TX_MODE_16_1_OFFSET 4
3742#define VP9_TX_MODE_32_0_OFFSET 6
3743#define VP9_TX_MODE_32_1_OFFSET 9
3744#define VP9_TX_MODE_SIZE 12
3745#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE)
3746#define VP9_COEF_BAND_0_OFFSET 0
3747#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1)
3748#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3)
3749#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3)
3750#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3)
3751#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3)
3752#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/
3753#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET)
3754#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET)
3755#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET)
3756#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET)
3757#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET)
3758#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET)
3759#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE)
3760#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/
3761#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE)
3762#define VP9_INTERP_SIZE 8
3763#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE)
3764#define VP9_INTRA_INTER_SIZE 4
3765#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START
3766#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE)
3767#define VP9_COMP_INTER_START \
3768 (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE)
3769#define VP9_COMP_INTER_SIZE 5
3770#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE)
3771#define VP9_COMP_REF_SIZE 5
3772#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE)
3773#define VP9_SINGLE_REF_SIZE 10
3774#define VP9_REF_MODE_START VP9_COMP_INTER_START
3775#define VP9_REF_MODE_SIZE \
3776 (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE)
3777#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE)
3778#define VP9_IF_Y_MODE_SIZE 36
3779#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE)
3780#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/
3781#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE)
3782#define VP9_MV_JOINTS_SIZE 3
3783#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE)
3784#define VP9_MV_SIGN_0_SIZE 1
3785#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE)
3786#define VP9_MV_CLASSES_0_SIZE 10
3787#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE)
3788#define VP9_MV_CLASS0_0_SIZE 1
3789#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE)
3790#define VP9_MV_BITS_0_SIZE 10
3791#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE)
3792#define VP9_MV_SIGN_1_SIZE 1
3793#define VP9_MV_CLASSES_1_START \
3794 (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE)
3795#define VP9_MV_CLASSES_1_SIZE 10
3796#define VP9_MV_CLASS0_1_START \
3797 (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE)
3798#define VP9_MV_CLASS0_1_SIZE 1
3799#define VP9_MV_BITS_1_START \
3800 (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE)
3801#define VP9_MV_BITS_1_SIZE 10
3802#define VP9_MV_CLASS0_FP_0_START \
3803 (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE)
3804#define VP9_MV_CLASS0_FP_0_SIZE 9
3805#define VP9_MV_CLASS0_FP_1_START \
3806 (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE)
3807#define VP9_MV_CLASS0_FP_1_SIZE 9
3808#define VP9_MV_CLASS0_HP_0_START \
3809 (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE)
3810#define VP9_MV_CLASS0_HP_0_SIZE 2
3811#define VP9_MV_CLASS0_HP_1_START \
3812 (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE)
3813#define VP9_MV_CLASS0_HP_1_SIZE 2
3814#define VP9_MV_START VP9_MV_JOINTS_START
3815#define VP9_MV_SIZE 72 /*only use 69*/
3816
3817#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE)
3818
3819
3820/*========================================================================
3821 * vp9_count_mem define
3822 *========================================================================
3823 */
3824#define VP9_COEF_COUNT_START 0
3825#define VP9_COEF_COUNT_BAND_0_OFFSET 0
3826#define VP9_COEF_COUNT_BAND_1_OFFSET \
3827 (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5)
3828#define VP9_COEF_COUNT_BAND_2_OFFSET \
3829 (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5)
3830#define VP9_COEF_COUNT_BAND_3_OFFSET \
3831 (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5)
3832#define VP9_COEF_COUNT_BAND_4_OFFSET \
3833 (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5)
3834#define VP9_COEF_COUNT_BAND_5_OFFSET \
3835 (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5)
3836#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */
3837#define VP9_COEF_COUNT_4X4_START \
3838 (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET)
3839#define VP9_COEF_COUNT_8X8_START \
3840 (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET)
3841#define VP9_COEF_COUNT_16X16_START \
3842 (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET)
3843#define VP9_COEF_COUNT_32X32_START \
3844 (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET)
3845#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3846#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET)
3847
3848#define VP9_INTRA_INTER_COUNT_START \
3849 (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE)
3850#define VP9_INTRA_INTER_COUNT_SIZE (4*2)
3851#define VP9_COMP_INTER_COUNT_START \
3852 (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE)
3853#define VP9_COMP_INTER_COUNT_SIZE (5*2)
3854#define VP9_COMP_REF_COUNT_START \
3855 (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE)
3856#define VP9_COMP_REF_COUNT_SIZE (5*2)
3857#define VP9_SINGLE_REF_COUNT_START \
3858 (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE)
3859#define VP9_SINGLE_REF_COUNT_SIZE (10*2)
3860#define VP9_TX_MODE_COUNT_START \
3861 (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE)
3862#define VP9_TX_MODE_COUNT_SIZE (12*2)
3863#define VP9_SKIP_COUNT_START \
3864 (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE)
3865#define VP9_SKIP_COUNT_SIZE (3*2)
3866#define VP9_MV_SIGN_0_COUNT_START \
3867 (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE)
3868#define VP9_MV_SIGN_0_COUNT_SIZE (1*2)
3869#define VP9_MV_SIGN_1_COUNT_START \
3870 (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE)
3871#define VP9_MV_SIGN_1_COUNT_SIZE (1*2)
3872#define VP9_MV_BITS_0_COUNT_START \
3873 (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE)
3874#define VP9_MV_BITS_0_COUNT_SIZE (10*2)
3875#define VP9_MV_BITS_1_COUNT_START \
3876 (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE)
3877#define VP9_MV_BITS_1_COUNT_SIZE (10*2)
3878#define VP9_MV_CLASS0_HP_0_COUNT_START \
3879 (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE)
3880#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2)
3881#define VP9_MV_CLASS0_HP_1_COUNT_START \
3882 (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE)
3883#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2)
3884/* Start merge_tree*/
3885#define VP9_INTER_MODE_COUNT_START \
3886 (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE)
3887#define VP9_INTER_MODE_COUNT_SIZE (7*4)
3888#define VP9_IF_Y_MODE_COUNT_START \
3889 (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE)
3890#define VP9_IF_Y_MODE_COUNT_SIZE (10*4)
3891#define VP9_IF_UV_MODE_COUNT_START \
3892 (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE)
3893#define VP9_IF_UV_MODE_COUNT_SIZE (10*10)
3894#define VP9_PARTITION_P_COUNT_START \
3895 (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE)
3896#define VP9_PARTITION_P_COUNT_SIZE (4*4*4)
3897#define VP9_INTERP_COUNT_START \
3898 (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE)
3899#define VP9_INTERP_COUNT_SIZE (4*3)
3900#define VP9_MV_JOINTS_COUNT_START \
3901 (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE)
3902#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4)
3903#define VP9_MV_CLASSES_0_COUNT_START \
3904 (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE)
3905#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11)
3906#define VP9_MV_CLASS0_0_COUNT_START \
3907 (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE)
3908#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2)
3909#define VP9_MV_CLASSES_1_COUNT_START \
3910 (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE)
3911#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11)
3912#define VP9_MV_CLASS0_1_COUNT_START \
3913 (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE)
3914#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2)
3915#define VP9_MV_CLASS0_FP_0_COUNT_START \
3916 (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE)
3917#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4)
3918#define VP9_MV_CLASS0_FP_1_COUNT_START \
3919 (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE)
3920#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4)
3921
3922
3923#define DC_PRED 0 /* Average of above and left pixels*/
3924#define V_PRED 1 /* Vertical*/
3925#define H_PRED 2 /* Horizontal*/
3926#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/
3927#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/
3928#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/
3929#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/
3930#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/
3931#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/
3932#define TM_PRED 9 /*True-motion*/
3933
3934int clip_prob(int p)
3935{
3936 return (p > 255) ? 255 : (p < 1) ? 1 : p;
3937}
3938
3939#define ROUND_POWER_OF_TWO(value, n) \
3940 (((value) + (1 << ((n) - 1))) >> (n))
3941
3942#define MODE_MV_COUNT_SAT 20
3943static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = {
3944 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64,
3945 70, 76, 83, 89, 96, 102, 108, 115, 121, 128
3946};
3947
3948void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob,
3949 int coef_node_start, int tree_left, int tree_right, int tree_i,
3950 int node) {
3951
3952 int prob_32, prob_res, prob_shift;
3953 int pre_prob, new_prob;
3954 int den, m_count, get_prob, factor;
3955
3956 prob_32 = prev_prob[coef_node_start / 4 * 2];
3957 prob_res = coef_node_start & 3;
3958 prob_shift = prob_res * 8;
3959 pre_prob = (prob_32 >> prob_shift) & 0xff;
3960
3961 den = tree_left + tree_right;
3962
3963 if (den == 0)
3964 new_prob = pre_prob;
3965 else {
3966 m_count = (den < MODE_MV_COUNT_SAT) ?
3967 den : MODE_MV_COUNT_SAT;
3968 get_prob = clip_prob(
3969 div_r32(((int64_t)tree_left * 256 + (den >> 1)),
3970 den));
3971 /*weighted_prob*/
3972 factor = count_to_update_factor[m_count];
3973 new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
3974 + get_prob * factor, 8);
3975 }
3976 cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2]
3977 & (~(0xff << prob_shift))) | (new_prob << prob_shift);
3978
3979 /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n",
3980 *tree_i, node, pre_prob, new_prob, tree_left, tree_right,
3981 *cur_prob[coef_node_start/4*2]);
3982 */
3983}
3984
3985
3986/*void adapt_coef_probs(void)*/
3987void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc,
3988 unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count)
3989{
3990 /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes)
3991 *unsigned int prev_prob[496*2];
3992 *unsigned int cur_prob[496*2];
3993 *0x300 * 128bits = 0x3000 (32K Bytes)
3994 *unsigned int count[0x300*4];
3995 */
3996
3997 int tx_size, coef_tx_size_start, coef_count_tx_size_start;
3998 int plane, coef_plane_start, coef_count_plane_start;
3999 int type, coef_type_start, coef_count_type_start;
4000 int band, coef_band_start, coef_count_band_start;
4001 int cxt_num;
4002 int cxt, coef_cxt_start, coef_count_cxt_start;
4003 int node, coef_node_start, coef_count_node_start;
4004
4005 int tree_i, tree_left, tree_right;
4006 int mvd_i;
4007
4008 int count_sat = 24;
4009 /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY,
4010 *use 128
4011 */
4012 /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/
4013 /*int update_factor = (pic_count == 1) ? 128 : 112;*/
4014 int update_factor = cur_kf ? 112 :
4015 prev_kf ? 128 : 112;
4016
4017 int prob_32;
4018 int prob_res;
4019 int prob_shift;
4020 int pre_prob;
4021
4022 int num, den;
4023 int get_prob;
4024 int m_count;
4025 int factor;
4026
4027 int new_prob;
4028
4029 if (debug & VP9_DEBUG_MERGE)
4030 pr_info
4031 ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n",
4032 pre_fc, prev_kf, cur_kf);
4033
4034 /*adapt_coef_probs*/
4035 for (tx_size = 0; tx_size < 4; tx_size++) {
4036 coef_tx_size_start = VP9_COEF_START
4037 + tx_size * 4 * VP9_COEF_SIZE_ONE_SET;
4038 coef_count_tx_size_start = VP9_COEF_COUNT_START
4039 + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET;
4040 coef_plane_start = coef_tx_size_start;
4041 coef_count_plane_start = coef_count_tx_size_start;
4042 for (plane = 0; plane < 2; plane++) {
4043 coef_type_start = coef_plane_start;
4044 coef_count_type_start = coef_count_plane_start;
4045 for (type = 0; type < 2; type++) {
4046 coef_band_start = coef_type_start;
4047 coef_count_band_start = coef_count_type_start;
4048 for (band = 0; band < 6; band++) {
4049 if (band == 0)
4050 cxt_num = 3;
4051 else
4052 cxt_num = 6;
4053 coef_cxt_start = coef_band_start;
4054 coef_count_cxt_start =
4055 coef_count_band_start;
4056 for (cxt = 0; cxt < cxt_num; cxt++) {
4057 const int n0 =
4058 count[coef_count_cxt_start];
4059 const int n1 =
4060 count[coef_count_cxt_start + 1];
4061 const int n2 =
4062 count[coef_count_cxt_start + 2];
4063 const int neob =
4064 count[coef_count_cxt_start + 3];
4065 const int nneob =
4066 count[coef_count_cxt_start + 4];
4067 const unsigned int
4068 branch_ct[3][2] = {
4069 { neob, nneob },
4070 { n0, n1 + n2 },
4071 { n1, n2 }
4072 };
4073 coef_node_start =
4074 coef_cxt_start;
4075 for
4076 (node = 0; node < 3; node++) {
4077 prob_32 =
4078 prev_prob[
4079 coef_node_start
4080 / 4 * 2];
4081 prob_res =
4082 coef_node_start & 3;
4083 prob_shift =
4084 prob_res * 8;
4085 pre_prob =
4086 (prob_32 >> prob_shift)
4087 & 0xff;
4088
4089 /*get_binary_prob*/
4090 num =
4091 branch_ct[node][0];
4092 den =
4093 branch_ct[node][0] +
4094 branch_ct[node][1];
4095 m_count = (den <
4096 count_sat)
4097 ? den : count_sat;
4098
4099 get_prob =
4100 (den == 0) ? 128u :
4101 clip_prob(
4102 div_r32(((int64_t)
4103 num * 256
4104 + (den >> 1)),
4105 den));
4106
4107 factor =
4108 update_factor * m_count
4109 / count_sat;
4110 new_prob =
4111 ROUND_POWER_OF_TWO
4112 (pre_prob *
4113 (256 - factor) +
4114 get_prob * factor, 8);
4115
4116 cur_prob[coef_node_start
4117 / 4 * 2] =
4118 (cur_prob
4119 [coef_node_start
4120 / 4 * 2] & (~(0xff <<
4121 prob_shift))) |
4122 (new_prob <<
4123 prob_shift);
4124
4125 coef_node_start += 1;
4126 }
4127
4128 coef_cxt_start =
4129 coef_cxt_start + 3;
4130 coef_count_cxt_start =
4131 coef_count_cxt_start
4132 + 5;
4133 }
4134 if (band == 0) {
4135 coef_band_start += 10;
4136 coef_count_band_start += 15;
4137 } else {
4138 coef_band_start += 18;
4139 coef_count_band_start += 30;
4140 }
4141 }
4142 coef_type_start += VP9_COEF_SIZE_ONE_SET;
4143 coef_count_type_start +=
4144 VP9_COEF_COUNT_SIZE_ONE_SET;
4145 }
4146 coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET;
4147 coef_count_plane_start +=
4148 2 * VP9_COEF_COUNT_SIZE_ONE_SET;
4149 }
4150 }
4151
4152 if (cur_kf == 0) {
4153 /*mode_mv_merge_probs - merge_intra_inter_prob*/
4154 for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START;
4155 coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START +
4156 VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) {
4157
4158 if (coef_count_node_start ==
4159 VP9_INTRA_INTER_COUNT_START) {
4160 if (debug & VP9_DEBUG_MERGE)
4161 pr_info(" # merge_intra_inter_prob\n");
4162 coef_node_start = VP9_INTRA_INTER_START;
4163 } else if (coef_count_node_start ==
4164 VP9_COMP_INTER_COUNT_START) {
4165 if (debug & VP9_DEBUG_MERGE)
4166 pr_info(" # merge_comp_inter_prob\n");
4167 coef_node_start = VP9_COMP_INTER_START;
4168 }
4169 /*
4170 *else if (coef_count_node_start ==
4171 * VP9_COMP_REF_COUNT_START) {
4172 * pr_info(" # merge_comp_inter_prob\n");
4173 * coef_node_start = VP9_COMP_REF_START;
4174 *}
4175 *else if (coef_count_node_start ==
4176 * VP9_SINGLE_REF_COUNT_START) {
4177 * pr_info(" # merge_comp_inter_prob\n");
4178 * coef_node_start = VP9_SINGLE_REF_START;
4179 *}
4180 */
4181 else if (coef_count_node_start ==
4182 VP9_TX_MODE_COUNT_START) {
4183 if (debug & VP9_DEBUG_MERGE)
4184 pr_info(" # merge_tx_mode_probs\n");
4185 coef_node_start = VP9_TX_MODE_START;
4186 } else if (coef_count_node_start ==
4187 VP9_SKIP_COUNT_START) {
4188 if (debug & VP9_DEBUG_MERGE)
4189 pr_info(" # merge_skip_probs\n");
4190 coef_node_start = VP9_SKIP_START;
4191 } else if (coef_count_node_start ==
4192 VP9_MV_SIGN_0_COUNT_START) {
4193 if (debug & VP9_DEBUG_MERGE)
4194 pr_info(" # merge_sign_0\n");
4195 coef_node_start = VP9_MV_SIGN_0_START;
4196 } else if (coef_count_node_start ==
4197 VP9_MV_SIGN_1_COUNT_START) {
4198 if (debug & VP9_DEBUG_MERGE)
4199 pr_info(" # merge_sign_1\n");
4200 coef_node_start = VP9_MV_SIGN_1_START;
4201 } else if (coef_count_node_start ==
4202 VP9_MV_BITS_0_COUNT_START) {
4203 if (debug & VP9_DEBUG_MERGE)
4204 pr_info(" # merge_bits_0\n");
4205 coef_node_start = VP9_MV_BITS_0_START;
4206 } else if (coef_count_node_start ==
4207 VP9_MV_BITS_1_COUNT_START) {
4208 if (debug & VP9_DEBUG_MERGE)
4209 pr_info(" # merge_bits_1\n");
4210 coef_node_start = VP9_MV_BITS_1_START;
4211 } else if (coef_count_node_start ==
4212 VP9_MV_CLASS0_HP_0_COUNT_START) {
4213 if (debug & VP9_DEBUG_MERGE)
4214 pr_info(" # merge_class0_hp\n");
4215 coef_node_start = VP9_MV_CLASS0_HP_0_START;
4216 }
4217
4218
4219 den = count[coef_count_node_start] +
4220 count[coef_count_node_start + 1];
4221
4222 prob_32 = prev_prob[coef_node_start / 4 * 2];
4223 prob_res = coef_node_start & 3;
4224 prob_shift = prob_res * 8;
4225 pre_prob = (prob_32 >> prob_shift) & 0xff;
4226
4227 if (den == 0)
4228 new_prob = pre_prob;
4229 else {
4230 m_count = (den < MODE_MV_COUNT_SAT) ?
4231 den : MODE_MV_COUNT_SAT;
4232 get_prob =
4233 clip_prob(
4234 div_r32(((int64_t)count[coef_count_node_start]
4235 * 256 + (den >> 1)),
4236 den));
4237 /*weighted_prob*/
4238 factor = count_to_update_factor[m_count];
4239 new_prob =
4240 ROUND_POWER_OF_TWO(pre_prob * (256 - factor)
4241 + get_prob * factor, 8);
4242 }
4243 cur_prob[coef_node_start / 4 * 2] =
4244 (cur_prob[coef_node_start / 4 * 2] &
4245 (~(0xff << prob_shift)))
4246 | (new_prob << prob_shift);
4247
4248 coef_node_start = coef_node_start + 1;
4249 }
4250 if (debug & VP9_DEBUG_MERGE)
4251 pr_info(" # merge_vp9_inter_mode_tree\n");
4252 coef_node_start = VP9_INTER_MODE_START;
4253 coef_count_node_start = VP9_INTER_MODE_COUNT_START;
4254 for (tree_i = 0; tree_i < 7; tree_i++) {
4255 for (node = 0; node < 3; node++) {
4256 switch (node) {
4257 case 2:
4258 tree_left =
4259 count[coef_count_node_start + 1];
4260 tree_right =
4261 count[coef_count_node_start + 3];
4262 break;
4263 case 1:
4264 tree_left =
4265 count[coef_count_node_start + 0];
4266 tree_right =
4267 count[coef_count_node_start + 1]
4268 + count[coef_count_node_start + 3];
4269 break;
4270 default:
4271 tree_left =
4272 count[coef_count_node_start + 2];
4273 tree_right =
4274 count[coef_count_node_start + 0]
4275 + count[coef_count_node_start + 1]
4276 + count[coef_count_node_start + 3];
4277 break;
4278
4279 }
4280
4281 vp9_tree_merge_probs(prev_prob, cur_prob,
4282 coef_node_start, tree_left, tree_right,
4283 tree_i, node);
4284
4285 coef_node_start = coef_node_start + 1;
4286 }
4287 coef_count_node_start = coef_count_node_start + 4;
4288 }
4289 if (debug & VP9_DEBUG_MERGE)
4290 pr_info(" # merge_vp9_intra_mode_tree\n");
4291 coef_node_start = VP9_IF_Y_MODE_START;
4292 coef_count_node_start = VP9_IF_Y_MODE_COUNT_START;
4293 for (tree_i = 0; tree_i < 14; tree_i++) {
4294 for (node = 0; node < 9; node++) {
4295 switch (node) {
4296 case 8:
4297 tree_left =
4298 count[coef_count_node_start+D153_PRED];
4299 tree_right =
4300 count[coef_count_node_start+D207_PRED];
4301 break;
4302 case 7:
4303 tree_left =
4304 count[coef_count_node_start+D63_PRED];
4305 tree_right =
4306 count[coef_count_node_start+D207_PRED] +
4307 count[coef_count_node_start+D153_PRED];
4308 break;
4309 case 6:
4310 tree_left =
4311 count[coef_count_node_start + D45_PRED];
4312 tree_right =
4313 count[coef_count_node_start+D207_PRED] +
4314 count[coef_count_node_start+D153_PRED] +
4315 count[coef_count_node_start+D63_PRED];
4316 break;
4317 case 5:
4318 tree_left =
4319 count[coef_count_node_start+D135_PRED];
4320 tree_right =
4321 count[coef_count_node_start+D117_PRED];
4322 break;
4323 case 4:
4324 tree_left =
4325 count[coef_count_node_start+H_PRED];
4326 tree_right =
4327 count[coef_count_node_start+D117_PRED] +
4328 count[coef_count_node_start+D135_PRED];
4329 break;
4330 case 3:
4331 tree_left =
4332 count[coef_count_node_start+H_PRED] +
4333 count[coef_count_node_start+D117_PRED] +
4334 count[coef_count_node_start+D135_PRED];
4335 tree_right =
4336 count[coef_count_node_start+D45_PRED] +
4337 count[coef_count_node_start+D207_PRED] +
4338 count[coef_count_node_start+D153_PRED] +
4339 count[coef_count_node_start+D63_PRED];
4340 break;
4341 case 2:
4342 tree_left =
4343 count[coef_count_node_start+V_PRED];
4344 tree_right =
4345 count[coef_count_node_start+H_PRED] +
4346 count[coef_count_node_start+D117_PRED] +
4347 count[coef_count_node_start+D135_PRED] +
4348 count[coef_count_node_start+D45_PRED] +
4349 count[coef_count_node_start+D207_PRED] +
4350 count[coef_count_node_start+D153_PRED] +
4351 count[coef_count_node_start+D63_PRED];
4352 break;
4353 case 1:
4354 tree_left =
4355 count[coef_count_node_start+TM_PRED];
4356 tree_right =
4357 count[coef_count_node_start+V_PRED] +
4358 count[coef_count_node_start+H_PRED] +
4359 count[coef_count_node_start+D117_PRED] +
4360 count[coef_count_node_start+D135_PRED] +
4361 count[coef_count_node_start+D45_PRED] +
4362 count[coef_count_node_start+D207_PRED] +
4363 count[coef_count_node_start+D153_PRED] +
4364 count[coef_count_node_start+D63_PRED];
4365 break;
4366 default:
4367 tree_left =
4368 count[coef_count_node_start+DC_PRED];
4369 tree_right =
4370 count[coef_count_node_start+TM_PRED] +
4371 count[coef_count_node_start+V_PRED] +
4372 count[coef_count_node_start+H_PRED] +
4373 count[coef_count_node_start+D117_PRED] +
4374 count[coef_count_node_start+D135_PRED] +
4375 count[coef_count_node_start+D45_PRED] +
4376 count[coef_count_node_start+D207_PRED] +
4377 count[coef_count_node_start+D153_PRED] +
4378 count[coef_count_node_start+D63_PRED];
4379 break;
4380
4381 }
4382
4383 vp9_tree_merge_probs(prev_prob, cur_prob,
4384 coef_node_start, tree_left, tree_right,
4385 tree_i, node);
4386
4387 coef_node_start = coef_node_start + 1;
4388 }
4389 coef_count_node_start = coef_count_node_start + 10;
4390 }
4391
4392 if (debug & VP9_DEBUG_MERGE)
4393 pr_info(" # merge_vp9_partition_tree\n");
4394 coef_node_start = VP9_PARTITION_P_START;
4395 coef_count_node_start = VP9_PARTITION_P_COUNT_START;
4396 for (tree_i = 0; tree_i < 16; tree_i++) {
4397 for (node = 0; node < 3; node++) {
4398 switch (node) {
4399 case 2:
4400 tree_left =
4401 count[coef_count_node_start + 2];
4402 tree_right =
4403 count[coef_count_node_start + 3];
4404 break;
4405 case 1:
4406 tree_left =
4407 count[coef_count_node_start + 1];
4408 tree_right =
4409 count[coef_count_node_start + 2] +
4410 count[coef_count_node_start + 3];
4411 break;
4412 default:
4413 tree_left =
4414 count[coef_count_node_start + 0];
4415 tree_right =
4416 count[coef_count_node_start + 1] +
4417 count[coef_count_node_start + 2] +
4418 count[coef_count_node_start + 3];
4419 break;
4420
4421 }
4422
4423 vp9_tree_merge_probs(prev_prob, cur_prob,
4424 coef_node_start,
4425 tree_left, tree_right, tree_i, node);
4426
4427 coef_node_start = coef_node_start + 1;
4428 }
4429 coef_count_node_start = coef_count_node_start + 4;
4430 }
4431
4432 if (debug & VP9_DEBUG_MERGE)
4433 pr_info(" # merge_vp9_switchable_interp_tree\n");
4434 coef_node_start = VP9_INTERP_START;
4435 coef_count_node_start = VP9_INTERP_COUNT_START;
4436 for (tree_i = 0; tree_i < 4; tree_i++) {
4437 for (node = 0; node < 2; node++) {
4438 switch (node) {
4439 case 1:
4440 tree_left =
4441 count[coef_count_node_start + 1];
4442 tree_right =
4443 count[coef_count_node_start + 2];
4444 break;
4445 default:
4446 tree_left =
4447 count[coef_count_node_start + 0];
4448 tree_right =
4449 count[coef_count_node_start + 1] +
4450 count[coef_count_node_start + 2];
4451 break;
4452
4453 }
4454
4455 vp9_tree_merge_probs(prev_prob, cur_prob,
4456 coef_node_start,
4457 tree_left, tree_right, tree_i, node);
4458
4459 coef_node_start = coef_node_start + 1;
4460 }
4461 coef_count_node_start = coef_count_node_start + 3;
4462 }
4463
4464 if (debug & VP9_DEBUG_MERGE)
4465 pr_info("# merge_vp9_mv_joint_tree\n");
4466 coef_node_start = VP9_MV_JOINTS_START;
4467 coef_count_node_start = VP9_MV_JOINTS_COUNT_START;
4468 for (tree_i = 0; tree_i < 1; tree_i++) {
4469 for (node = 0; node < 3; node++) {
4470 switch (node) {
4471 case 2:
4472 tree_left =
4473 count[coef_count_node_start + 2];
4474 tree_right =
4475 count[coef_count_node_start + 3];
4476 break;
4477 case 1:
4478 tree_left =
4479 count[coef_count_node_start + 1];
4480 tree_right =
4481 count[coef_count_node_start + 2] +
4482 count[coef_count_node_start + 3];
4483 break;
4484 default:
4485 tree_left =
4486 count[coef_count_node_start + 0];
4487 tree_right =
4488 count[coef_count_node_start + 1] +
4489 count[coef_count_node_start + 2] +
4490 count[coef_count_node_start + 3];
4491 break;
4492 }
4493
4494 vp9_tree_merge_probs(prev_prob, cur_prob,
4495 coef_node_start,
4496 tree_left, tree_right, tree_i, node);
4497
4498 coef_node_start = coef_node_start + 1;
4499 }
4500 coef_count_node_start = coef_count_node_start + 4;
4501 }
4502
4503 for (mvd_i = 0; mvd_i < 2; mvd_i++) {
4504 if (debug & VP9_DEBUG_MERGE)
4505 pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i);
4506 coef_node_start =
4507 mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START;
4508 coef_count_node_start =
4509 mvd_i ? VP9_MV_CLASSES_1_COUNT_START
4510 : VP9_MV_CLASSES_0_COUNT_START;
4511 tree_i = 0;
4512 for (node = 0; node < 10; node++) {
4513 switch (node) {
4514 case 9:
4515 tree_left =
4516 count[coef_count_node_start + 9];
4517 tree_right =
4518 count[coef_count_node_start + 10];
4519 break;
4520 case 8:
4521 tree_left =
4522 count[coef_count_node_start + 7];
4523 tree_right =
4524 count[coef_count_node_start + 8];
4525 break;
4526 case 7:
4527 tree_left =
4528 count[coef_count_node_start + 7] +
4529 count[coef_count_node_start + 8];
4530 tree_right =
4531 count[coef_count_node_start + 9] +
4532 count[coef_count_node_start + 10];
4533 break;
4534 case 6:
4535 tree_left =
4536 count[coef_count_node_start + 6];
4537 tree_right =
4538 count[coef_count_node_start + 7] +
4539 count[coef_count_node_start + 8] +
4540 count[coef_count_node_start + 9] +
4541 count[coef_count_node_start + 10];
4542 break;
4543 case 5:
4544 tree_left =
4545 count[coef_count_node_start + 4];
4546 tree_right =
4547 count[coef_count_node_start + 5];
4548 break;
4549 case 4:
4550 tree_left =
4551 count[coef_count_node_start + 4] +
4552 count[coef_count_node_start + 5];
4553 tree_right =
4554 count[coef_count_node_start + 6] +
4555 count[coef_count_node_start + 7] +
4556 count[coef_count_node_start + 8] +
4557 count[coef_count_node_start + 9] +
4558 count[coef_count_node_start + 10];
4559 break;
4560 case 3:
4561 tree_left =
4562 count[coef_count_node_start + 2];
4563 tree_right =
4564 count[coef_count_node_start + 3];
4565 break;
4566 case 2:
4567 tree_left =
4568 count[coef_count_node_start + 2] +
4569 count[coef_count_node_start + 3];
4570 tree_right =
4571 count[coef_count_node_start + 4] +
4572 count[coef_count_node_start + 5] +
4573 count[coef_count_node_start + 6] +
4574 count[coef_count_node_start + 7] +
4575 count[coef_count_node_start + 8] +
4576 count[coef_count_node_start + 9] +
4577 count[coef_count_node_start + 10];
4578 break;
4579 case 1:
4580 tree_left =
4581 count[coef_count_node_start + 1];
4582 tree_right =
4583 count[coef_count_node_start + 2] +
4584 count[coef_count_node_start + 3] +
4585 count[coef_count_node_start + 4] +
4586 count[coef_count_node_start + 5] +
4587 count[coef_count_node_start + 6] +
4588 count[coef_count_node_start + 7] +
4589 count[coef_count_node_start + 8] +
4590 count[coef_count_node_start + 9] +
4591 count[coef_count_node_start + 10];
4592 break;
4593 default:
4594 tree_left =
4595 count[coef_count_node_start + 0];
4596 tree_right =
4597 count[coef_count_node_start + 1] +
4598 count[coef_count_node_start + 2] +
4599 count[coef_count_node_start + 3] +
4600 count[coef_count_node_start + 4] +
4601 count[coef_count_node_start + 5] +
4602 count[coef_count_node_start + 6] +
4603 count[coef_count_node_start + 7] +
4604 count[coef_count_node_start + 8] +
4605 count[coef_count_node_start + 9] +
4606 count[coef_count_node_start + 10];
4607 break;
4608
4609 }
4610
4611 vp9_tree_merge_probs(prev_prob, cur_prob,
4612 coef_node_start, tree_left, tree_right,
4613 tree_i, node);
4614
4615 coef_node_start = coef_node_start + 1;
4616 }
4617
4618 if (debug & VP9_DEBUG_MERGE)
4619 pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i);
4620 coef_node_start =
4621 mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START;
4622 coef_count_node_start =
4623 mvd_i ? VP9_MV_CLASS0_1_COUNT_START :
4624 VP9_MV_CLASS0_0_COUNT_START;
4625 tree_i = 0;
4626 node = 0;
4627 tree_left = count[coef_count_node_start + 0];
4628 tree_right = count[coef_count_node_start + 1];
4629
4630 vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start,
4631 tree_left, tree_right, tree_i, node);
4632 if (debug & VP9_DEBUG_MERGE)
4633 pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n",
4634 mvd_i);
4635 coef_node_start =
4636 mvd_i ? VP9_MV_CLASS0_FP_1_START :
4637 VP9_MV_CLASS0_FP_0_START;
4638 coef_count_node_start =
4639 mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START :
4640 VP9_MV_CLASS0_FP_0_COUNT_START;
4641 for (tree_i = 0; tree_i < 3; tree_i++) {
4642 for (node = 0; node < 3; node++) {
4643 switch (node) {
4644 case 2:
4645 tree_left =
4646 count[coef_count_node_start + 2];
4647 tree_right =
4648 count[coef_count_node_start + 3];
4649 break;
4650 case 1:
4651 tree_left =
4652 count[coef_count_node_start + 1];
4653 tree_right =
4654 count[coef_count_node_start + 2]
4655 + count[coef_count_node_start + 3];
4656 break;
4657 default:
4658 tree_left =
4659 count[coef_count_node_start + 0];
4660 tree_right =
4661 count[coef_count_node_start + 1]
4662 + count[coef_count_node_start + 2]
4663 + count[coef_count_node_start + 3];
4664 break;
4665
4666 }
4667
4668 vp9_tree_merge_probs(prev_prob, cur_prob,
4669 coef_node_start, tree_left, tree_right,
4670 tree_i, node);
4671
4672 coef_node_start = coef_node_start + 1;
4673 }
4674 coef_count_node_start = coef_count_node_start + 4;
4675 }
4676
4677 } /* for mvd_i (mvd_y or mvd_x)*/
4678}
4679
4680}
4681
4682static bool v4l_is_there_vframe_bound(struct VP9Decoder_s *pbi)
4683{
4684 int i;
4685 struct VP9_Common_s *const cm = &pbi->common;
4686 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4687
4688 for (i = 0; i < pbi->used_buf_num; ++i) {
4689 if (frame_bufs[i].buf.vframe_bound)
4690 return true;
4691 }
4692
4693 return false;
4694}
4695
4696static void v4l_mmu_buffer_release(struct VP9Decoder_s *pbi)
4697{
4698 struct VP9_Common_s *const cm = &pbi->common;
4699 struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs;
4700 int i;
4701
4702 /* release workspace */
4703 if (pbi->bmmu_box)
4704 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4705 WORK_SPACE_BUF_ID);
4706 /*
4707 * it's only when vframe get back to driver, right now we can be sure
4708 * that vframe and fd are related. if the playback exits, the capture
4709 * requires the upper app to release when the fd is closed, and others
4710 * buffers drivers are released by driver.
4711 */
4712 for (i = 0; i < pbi->used_buf_num; ++i) {
4713 if (!frame_bufs[i].buf.vframe_bound) {
4714 if (pbi->bmmu_box)
4715 decoder_bmmu_box_free_idx(pbi->bmmu_box,
4716 HEADER_BUFFER_IDX(i));
4717 if (pbi->mmu_box)
4718 decoder_mmu_box_free_idx(pbi->mmu_box, i);
4719
4720 vp9_print(pbi, PRINT_FLAG_V4L_DETAIL,
4721 "%s free buffer[%d], bmmu_box: %p, mmu_box: %p\n",
4722 __func__, i, pbi->bmmu_box, pbi->mmu_box);
4723 }
4724 }
4725}
4726
4727static void uninit_mmu_buffers(struct VP9Decoder_s *pbi)
4728{
4729#ifndef MV_USE_FIXED_BUF
4730 dealloc_mv_bufs(pbi);
4731#endif
4732 if (pbi->is_used_v4l &&
4733 v4l_is_there_vframe_bound(pbi)) {
4734 if (get_double_write_mode(pbi) != 0x10) {
4735 v4l_mmu_buffer_release(pbi);
4736 return;
4737 }
4738 }
4739
4740 if (pbi->mmu_box)
4741 decoder_mmu_box_free(pbi->mmu_box);
4742 pbi->mmu_box = NULL;
4743
4744 if (pbi->bmmu_box)
4745 decoder_bmmu_box_free(pbi->bmmu_box);
4746 pbi->bmmu_box = NULL;
4747}
4748
4749static int calc_luc_quantity(u32 w, u32 h)
4750{
4751 int lcu_size = 64; /*fixed 64*/
4752 int pic_width_64 = (w + 63) & (~0x3f);
4753 int pic_height_32 = (h + 31) & (~0x1f);
4754 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4755 pic_width_64 / lcu_size + 1 : pic_width_64 / lcu_size;
4756 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4757 pic_height_32 / lcu_size + 1 : pic_height_32 / lcu_size;
4758
4759 return pic_width_lcu * pic_height_lcu;
4760}
4761
4762static int v4l_alloc_and_config_pic(struct VP9Decoder_s *pbi,
4763 struct PIC_BUFFER_CONFIG_s *pic)
4764{
4765 int ret = -1;
4766 int i = pic->index;
4767 int dw_mode = get_double_write_mode_init(pbi);
4768 int lcu_total = calc_luc_quantity(pbi->frame_width, pbi->frame_height);
4769#ifdef MV_USE_FIXED_BUF
4770 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4771 pbi->work_space_buf->mpred_mv.buf_size;
4772#endif
4773 struct vdec_v4l2_buffer *fb = NULL;
4774
4775 ret = vdec_v4l_get_buffer(pbi->v4l2_ctx, &fb);
4776 if (ret < 0) {
4777 vp9_print(pbi, 0, "[%d] VP9 get buffer fail.\n",
4778 ((struct aml_vcodec_ctx *) (pbi->v4l2_ctx))->id);
4779 return ret;
4780 }
4781
4782 if (pbi->mmu_enable) {
4783 pbi->m_BUF[i].header_addr = decoder_bmmu_box_get_phy_addr(
4784 pbi->bmmu_box, HEADER_BUFFER_IDX(i));
4785 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4786 pr_info("MMU header_adr %d: %ld\n",
4787 i, pbi->m_BUF[i].header_addr);
4788 }
4789 }
4790
4791#ifdef MV_USE_FIXED_BUF
4792 if ((pbi->work_space_buf->mpred_mv.buf_start +
4793 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4794 <= mpred_mv_end) {
4795#endif
4796 pbi->m_BUF[i].v4l_ref_buf_addr = (ulong)fb;
4797 pic->cma_alloc_addr = fb->m.mem[0].addr;
4798 if (fb->num_planes == 1) {
4799 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4800 pbi->m_BUF[i].size = fb->m.mem[0].size;
4801 pbi->m_BUF[i].luma_size = fb->m.mem[0].offset;
4802 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4803 } else if (fb->num_planes == 2) {
4804 pbi->m_BUF[i].start_adr = fb->m.mem[0].addr;
4805 pbi->m_BUF[i].size = fb->m.mem[0].size + fb->m.mem[1].size;
4806 pbi->m_BUF[i].luma_size = fb->m.mem[0].size;
4807 fb->m.mem[0].bytes_used = fb->m.mem[0].size;
4808 fb->m.mem[1].bytes_used = fb->m.mem[1].size;
4809 }
4810
4811 /* config frame buffer */
4812 if (pbi->mmu_enable)
4813 pic->header_adr = pbi->m_BUF[i].header_addr;
4814
4815 pic->BUF_index = i;
4816 pic->lcu_total = lcu_total;
4817 pic->mc_canvas_y = pic->index;
4818 pic->mc_canvas_u_v = pic->index;
4819
4820 if (dw_mode & 0x10) {
4821 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4822 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4823 pic->mc_canvas_y = (pic->index << 1);
4824 pic->mc_canvas_u_v = (pic->index << 1) + 1;
4825 } else if (dw_mode) {
4826 pic->dw_y_adr = pbi->m_BUF[i].start_adr;
4827 pic->dw_u_v_adr = pic->dw_y_adr + pbi->m_BUF[i].luma_size;
4828 }
4829
4830#ifdef MV_USE_FIXED_BUF
4831 pic->mpred_mv_wr_start_addr =
4832 pbi->work_space_buf->mpred_mv.buf_start +
4833 ((pic->index * lcu_total) * MV_MEM_UNIT);
4834#endif
4835 if (debug) {
4836 pr_info("%s index %d BUF_index %d ",
4837 __func__, pic->index,
4838 pic->BUF_index);
4839 pr_info("comp_body_size %x comp_buf_size %x ",
4840 pic->comp_body_size,
4841 pic->buf_size);
4842 pr_info("mpred_mv_wr_start_adr %ld\n",
4843 pic->mpred_mv_wr_start_addr);
4844 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
4845 pic->dw_y_adr,
4846 pic->dw_u_v_adr);
4847 }
4848#ifdef MV_USE_FIXED_BUF
4849 }
4850#endif
4851 return ret;
4852}
4853
4854static int config_pic(struct VP9Decoder_s *pbi,
4855 struct PIC_BUFFER_CONFIG_s *pic_config)
4856{
4857 int ret = -1;
4858 int i;
4859 int pic_width = pbi->init_pic_w;
4860 int pic_height = pbi->init_pic_h;
4861 int lcu_size = 64; /*fixed 64*/
4862 int pic_width_64 = (pic_width + 63) & (~0x3f);
4863 int pic_height_32 = (pic_height + 31) & (~0x1f);
4864 int pic_width_lcu = (pic_width_64 % lcu_size) ?
4865 pic_width_64 / lcu_size + 1
4866 : pic_width_64 / lcu_size;
4867 int pic_height_lcu = (pic_height_32 % lcu_size) ?
4868 pic_height_32 / lcu_size + 1
4869 : pic_height_32 / lcu_size;
4870 int lcu_total = pic_width_lcu * pic_height_lcu;
4871#ifdef MV_USE_FIXED_BUF
4872 u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start +
4873 pbi->work_space_buf->mpred_mv.buf_size;
4874#endif
4875 u32 y_adr = 0;
4876 int buf_size = 0;
4877
4878 int losless_comp_header_size =
4879 compute_losless_comp_header_size(pic_width,
4880 pic_height);
4881 int losless_comp_body_size = compute_losless_comp_body_size(pic_width,
4882 pic_height, buf_alloc_depth == 10);
4883 int mc_buffer_size = losless_comp_header_size + losless_comp_body_size;
4884 int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
4885 int mc_buffer_size_u_v = 0;
4886 int mc_buffer_size_u_v_h = 0;
4887 int dw_mode = get_double_write_mode_init(pbi);
4888
4889 pbi->lcu_total = lcu_total;
4890
4891 if (dw_mode) {
4892 int pic_width_dw = pic_width /
4893 get_double_write_ratio(pbi, dw_mode);
4894 int pic_height_dw = pic_height /
4895 get_double_write_ratio(pbi, dw_mode);
4896
4897 int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f);
4898 int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f);
4899 int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ?
4900 pic_width_64_dw / lcu_size + 1
4901 : pic_width_64_dw / lcu_size;
4902 int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ?
4903 pic_height_32_dw / lcu_size + 1
4904 : pic_height_32_dw / lcu_size;
4905 int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw;
4906 mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2;
4907 mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16;
4908 /*64k alignment*/
4909 buf_size = ((mc_buffer_size_u_v_h << 16) * 3);
4910 buf_size = ((buf_size + 0xffff) >> 16) << 16;
4911 }
4912
4913 if (mc_buffer_size & 0xffff) /*64k alignment*/
4914 mc_buffer_size_h += 1;
4915 if ((!pbi->mmu_enable) && ((dw_mode & 0x10) == 0))
4916 buf_size += (mc_buffer_size_h << 16);
4917
4918 if (pbi->mmu_enable) {
4919 pic_config->header_adr = decoder_bmmu_box_get_phy_addr(
4920 pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index));
4921
4922 if (debug & VP9_DEBUG_BUFMGR_MORE) {
4923 pr_info("MMU header_adr %d: %ld\n",
4924 pic_config->index, pic_config->header_adr);
4925 }
4926 }
4927
4928 i = pic_config->index;
4929#ifdef MV_USE_FIXED_BUF
4930 if ((pbi->work_space_buf->mpred_mv.buf_start +
4931 (((i + 1) * lcu_total) * MV_MEM_UNIT))
4932 <= mpred_mv_end
4933 ) {
4934#endif
4935 if (buf_size > 0) {
4936 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box,
4937 VF_BUFFER_IDX(i),
4938 buf_size, DRIVER_NAME,
4939 &pic_config->cma_alloc_addr);
4940 if (ret < 0) {
4941 pr_info(
4942 "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n",
4943 VF_BUFFER_IDX(i),
4944 buf_size
4945 );
4946 return ret;
4947 }
4948
4949 if (pic_config->cma_alloc_addr)
4950 y_adr = pic_config->cma_alloc_addr;
4951 else {
4952 pr_info(
4953 "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n",
4954 VF_BUFFER_IDX(i),
4955 buf_size
4956 );
4957 return -1;
4958 }
4959 }
4960 {
4961 /*ensure get_pic_by_POC()
4962 not get the buffer not decoded*/
4963 pic_config->BUF_index = i;
4964 pic_config->lcu_total = lcu_total;
4965
4966 pic_config->comp_body_size = losless_comp_body_size;
4967 pic_config->buf_size = buf_size;
4968
4969 pic_config->mc_canvas_y = pic_config->index;
4970 pic_config->mc_canvas_u_v = pic_config->index;
4971 if (dw_mode & 0x10) {
4972 pic_config->dw_y_adr = y_adr;
4973 pic_config->dw_u_v_adr = y_adr +
4974 ((mc_buffer_size_u_v_h << 16) << 1);
4975
4976 pic_config->mc_canvas_y =
4977 (pic_config->index << 1);
4978 pic_config->mc_canvas_u_v =
4979 (pic_config->index << 1) + 1;
4980 } else if (dw_mode) {
4981 pic_config->dw_y_adr = y_adr;
4982 pic_config->dw_u_v_adr = pic_config->dw_y_adr +
4983 ((mc_buffer_size_u_v_h << 16) << 1);
4984 }
4985#ifdef MV_USE_FIXED_BUF
4986 pic_config->mpred_mv_wr_start_addr =
4987 pbi->work_space_buf->mpred_mv.buf_start +
4988 ((pic_config->index * lcu_total)
4989 * MV_MEM_UNIT);
4990#endif
4991 if (debug) {
4992 pr_info
4993 ("%s index %d BUF_index %d ",
4994 __func__, pic_config->index,
4995 pic_config->BUF_index);
4996 pr_info
4997 ("comp_body_size %x comp_buf_size %x ",
4998 pic_config->comp_body_size,
4999 pic_config->buf_size);
5000 pr_info
5001 ("mpred_mv_wr_start_adr %ld\n",
5002 pic_config->mpred_mv_wr_start_addr);
5003 pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n",
5004 pic_config->dw_y_adr,
5005 pic_config->dw_u_v_adr);
5006 }
5007 ret = 0;
5008 }
5009#ifdef MV_USE_FIXED_BUF
5010 }
5011#endif
5012 return ret;
5013}
5014
5015static int vvp9_mmu_compress_header_size(struct VP9Decoder_s *pbi)
5016{
5017 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5018 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5019 return (MMU_COMPRESS_8K_HEADER_SIZE);
5020
5021 return (MMU_COMPRESS_HEADER_SIZE);
5022}
5023
5024/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
5025static int vvp9_frame_mmu_map_size(struct VP9Decoder_s *pbi)
5026{
5027 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
5028 IS_8K_SIZE(pbi->max_pic_w, pbi->max_pic_h))
5029 return (MAX_FRAME_8K_NUM * 4);
5030
5031 return (MAX_FRAME_4K_NUM * 4);
5032}
5033
5034static void init_pic_list(struct VP9Decoder_s *pbi)
5035{
5036 int i;
5037 struct VP9_Common_s *cm = &pbi->common;
5038 struct PIC_BUFFER_CONFIG_s *pic_config;
5039 u32 header_size;
5040 struct vdec_s *vdec = hw_to_vdec(pbi);
5041
5042 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
5043 header_size = vvp9_mmu_compress_header_size(pbi);
5044 /*alloc VP9 compress header first*/
5045 for (i = 0; i < pbi->used_buf_num; i++) {
5046 unsigned long buf_addr;
5047 if (decoder_bmmu_box_alloc_buf_phy
5048 (pbi->bmmu_box,
5049 HEADER_BUFFER_IDX(i), header_size,
5050 DRIVER_HEADER_NAME,
5051 &buf_addr) < 0) {
5052 pr_info("%s malloc compress header failed %d\n",
5053 DRIVER_HEADER_NAME, i);
5054 pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM;
5055 return;
5056 }
5057 }
5058 }
5059 for (i = 0; i < pbi->used_buf_num; i++) {
5060 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5061 pic_config->index = i;
5062 pic_config->BUF_index = -1;
5063 pic_config->mv_buf_index = -1;
5064 if (vdec->parallel_dec == 1) {
5065 pic_config->y_canvas_index = -1;
5066 pic_config->uv_canvas_index = -1;
5067 }
5068 pic_config->y_crop_width = pbi->init_pic_w;
5069 pic_config->y_crop_height = pbi->init_pic_h;
5070 pic_config->double_write_mode = get_double_write_mode(pbi);
5071
5072 if (!pbi->is_used_v4l) {
5073 if (config_pic(pbi, pic_config) < 0) {
5074 if (debug)
5075 pr_info("Config_pic %d fail\n",
5076 pic_config->index);
5077 pic_config->index = -1;
5078 break;
5079 }
5080
5081 if (pic_config->double_write_mode) {
5082 set_canvas(pbi, pic_config);
5083 }
5084 }
5085 }
5086 for (; i < pbi->used_buf_num; i++) {
5087 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5088 pic_config->index = -1;
5089 pic_config->BUF_index = -1;
5090 pic_config->mv_buf_index = -1;
5091 if (vdec->parallel_dec == 1) {
5092 pic_config->y_canvas_index = -1;
5093 pic_config->uv_canvas_index = -1;
5094 }
5095 }
5096 pr_info("%s ok, used_buf_num = %d\n",
5097 __func__, pbi->used_buf_num);
5098}
5099
5100static void init_pic_list_hw(struct VP9Decoder_s *pbi)
5101{
5102 int i;
5103 struct VP9_Common_s *cm = &pbi->common;
5104 struct PIC_BUFFER_CONFIG_s *pic_config;
5105 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
5106 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
5107 (0x1 << 1) | (0x1 << 2));
5108
5109
5110 for (i = 0; i < pbi->used_buf_num; i++) {
5111 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5112 if (pic_config->index < 0)
5113 break;
5114
5115 if (pbi->mmu_enable && ((pic_config->double_write_mode & 0x10) == 0)) {
5116
5117 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5118 pic_config->header_adr >> 5);
5119 } else {
5120 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5121 * pic_config->mc_y_adr
5122 * | (pic_config->mc_canvas_y << 8) | 0x1);
5123 */
5124 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5125 pic_config->dw_y_adr >> 5);
5126 }
5127#ifndef LOSLESS_COMPRESS_MODE
5128 /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
5129 * pic_config->mc_u_v_adr
5130 * | (pic_config->mc_canvas_u_v << 8)| 0x1);
5131 */
5132 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5133 pic_config->header_adr >> 5);
5134#else
5135 if (pic_config->double_write_mode & 0x10) {
5136 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA,
5137 pic_config->dw_u_v_adr >> 5);
5138 }
5139#endif
5140 }
5141 WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1);
5142
5143 /*Zero out canvas registers in IPP -- avoid simulation X*/
5144 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5145 (0 << 8) | (0 << 1) | 1);
5146 for (i = 0; i < 32; i++)
5147 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
5148}
5149
5150
5151static void dump_pic_list(struct VP9Decoder_s *pbi)
5152{
5153 struct VP9_Common_s *const cm = &pbi->common;
5154 struct PIC_BUFFER_CONFIG_s *pic_config;
5155 int i;
5156 for (i = 0; i < FRAME_BUFFERS; i++) {
5157 pic_config = &cm->buffer_pool->frame_bufs[i].buf;
5158 vp9_print(pbi, 0,
5159 "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n",
5160 i,
5161 pic_config->index,
5162#ifndef MV_USE_FIXED_BUF
5163 pic_config->mv_buf_index,
5164#else
5165 -1,
5166#endif
5167 cm->buffer_pool->
5168 frame_bufs[i].ref_count,
5169 pic_config->vf_ref,
5170 pic_config->decode_idx,
5171 pic_config->slice_type,
5172 pic_config->y_crop_width,
5173 pic_config->y_crop_height,
5174 pic_config->cma_alloc_addr
5175 );
5176 }
5177 return;
5178}
5179
5180static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5181{
5182#ifdef LOSLESS_COMPRESS_MODE
5183 unsigned int data32;
5184#endif
5185 int losless_comp_header_size, losless_comp_body_size;
5186 struct VP9_Common_s *cm = &pbi->common;
5187 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5188
5189 frame_width = cur_pic_config->y_crop_width;
5190 frame_height = cur_pic_config->y_crop_height;
5191 cur_pic_config->bit_depth = bit_depth;
5192 cur_pic_config->double_write_mode = get_double_write_mode(pbi);
5193 losless_comp_header_size =
5194 compute_losless_comp_header_size(cur_pic_config->y_crop_width,
5195 cur_pic_config->y_crop_height);
5196 losless_comp_body_size =
5197 compute_losless_comp_body_size(cur_pic_config->y_crop_width,
5198 cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5199 cur_pic_config->comp_body_size = losless_comp_body_size;
5200#ifdef LOSLESS_COMPRESS_MODE
5201 data32 = READ_VREG(HEVC_SAO_CTRL5);
5202 if (bit_depth == VPX_BITS_10)
5203 data32 &= ~(1 << 9);
5204 else
5205 data32 |= (1 << 9);
5206
5207 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5208
5209 if (pbi->mmu_enable) {
5210 /*bit[4] : paged_mem_mode*/
5211 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5212 } else {
5213 /*bit[3] smem mdoe*/
5214 if (bit_depth == VPX_BITS_10)
5215 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3));
5216 else
5217 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
5218 }
5219 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5220 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
5221 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
5222 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5223 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5224 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5225 if (get_double_write_mode(pbi) & 0x10)
5226 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5227#else
5228 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5229#endif
5230 return 0;
5231}
5232
5233static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth)
5234{
5235 int i;
5236 struct VP9_Common_s *cm = &pbi->common;
5237 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5238 uint8_t scale_enable = 0;
5239
5240 if (debug&VP9_DEBUG_BUFMGR_MORE)
5241 pr_info("config_mc_buffer entered .....\n");
5242
5243 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5244 (0 << 8) | (0 << 1) | 1);
5245 for (i = 0; i < REFS_PER_FRAME; ++i) {
5246 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5247 if (!pic_config)
5248 continue;
5249 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5250 (pic_config->mc_canvas_u_v << 16)
5251 | (pic_config->mc_canvas_u_v << 8)
5252 | pic_config->mc_canvas_y);
5253 if (debug & VP9_DEBUG_BUFMGR_MORE)
5254 pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n",
5255 i, pic_config->mc_canvas_u_v,
5256 pic_config->mc_canvas_y);
5257 }
5258 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
5259 (16 << 8) | (0 << 1) | 1);
5260 for (i = 0; i < REFS_PER_FRAME; ++i) {
5261 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5262 if (!pic_config)
5263 continue;
5264 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
5265 (pic_config->mc_canvas_u_v << 16)
5266 | (pic_config->mc_canvas_u_v << 8)
5267 | pic_config->mc_canvas_y);
5268 }
5269
5270 /*auto_inc start index:0 field:0*/
5271 WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2);
5272 /*index 0:last 1:golden 2:altref*/
5273 for (i = 0; i < REFS_PER_FRAME; i++) {
5274 int ref_pic_body_size;
5275 struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf;
5276 if (!pic_config)
5277 continue;
5278 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width);
5279 WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height);
5280
5281 if (pic_config->y_crop_width != cur_pic_config->y_crop_width ||
5282 pic_config->y_crop_height != cur_pic_config->y_crop_height) {
5283 scale_enable |= (1 << i);
5284 }
5285 ref_pic_body_size =
5286 compute_losless_comp_body_size(pic_config->y_crop_width,
5287 pic_config->y_crop_height, (bit_depth == VPX_BITS_10));
5288 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5289 (pic_config->y_crop_width << 14)
5290 / cur_pic_config->y_crop_width);
5291 WRITE_VREG(VP9D_MPP_REFINFO_DATA,
5292 (pic_config->y_crop_height << 14)
5293 / cur_pic_config->y_crop_height);
5294 if (pbi->mmu_enable)
5295 WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0);
5296 else
5297 WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5);
5298 }
5299 WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable);
5300 return 0;
5301}
5302
5303static void clear_mpred_hw(struct VP9Decoder_s *pbi)
5304{
5305 unsigned int data32;
5306
5307 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5308 data32 &= (~(1 << 6));
5309 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5310}
5311
5312static void config_mpred_hw(struct VP9Decoder_s *pbi)
5313{
5314 struct VP9_Common_s *cm = &pbi->common;
5315 struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf;
5316 struct PIC_BUFFER_CONFIG_s *last_frame_pic_config =
5317 &cm->prev_frame->buf;
5318
5319 unsigned int data32;
5320 int mpred_curr_lcu_x;
5321 int mpred_curr_lcu_y;
5322 int mpred_mv_rd_end_addr;
5323
5324
5325 mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr
5326 + (last_frame_pic_config->lcu_total * MV_MEM_UNIT);
5327
5328 data32 = READ_VREG(HEVC_MPRED_CURR_LCU);
5329 mpred_curr_lcu_x = data32 & 0xffff;
5330 mpred_curr_lcu_y = (data32 >> 16) & 0xffff;
5331
5332 if (debug & VP9_DEBUG_BUFMGR)
5333 pr_info("cur pic_config index %d col pic_config index %d\n",
5334 cur_pic_config->index, last_frame_pic_config->index);
5335 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
5336 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
5337 pbi->work_space_buf->mpred_above.buf_start);
5338
5339 data32 = READ_VREG(HEVC_MPRED_CTRL4);
5340
5341 data32 &= (~(1 << 6));
5342 data32 |= (cm->use_prev_frame_mvs << 6);
5343 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
5344
5345 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
5346 cur_pic_config->mpred_mv_wr_start_addr);
5347 WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr);
5348
5349 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
5350 last_frame_pic_config->mpred_mv_wr_start_addr);
5351 WRITE_VREG(HEVC_MPRED_MV_RPTR,
5352 last_frame_pic_config->mpred_mv_wr_start_addr);
5353 /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/
5354 /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/
5355 /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/
5356 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
5357
5358}
5359
5360static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
5361{
5362 struct VP9_Common_s *cm = &pbi->common;
5363 struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf;
5364
5365 unsigned int data32;
5366 int lcu_size = 64;
5367 int mc_buffer_size_u_v =
5368 pic_config->lcu_total * lcu_size*lcu_size/2;
5369 int mc_buffer_size_u_v_h =
5370 (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/
5371 struct aml_vcodec_ctx * v4l2_ctx = pbi->v4l2_ctx;
5372
5373 if (get_double_write_mode(pbi)) {
5374 WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr);
5375 WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr);
5376 WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr);
5377 WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr);
5378 } else {
5379 WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff);
5380 WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff);
5381 }
5382 if (pbi->mmu_enable)
5383 WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr);
5384
5385 data32 = (mc_buffer_size_u_v_h << 16) << 1;
5386 /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n",
5387 * data32, mc_buffer_size_u_v_h, pic_config->lcu_total);
5388 */
5389 WRITE_VREG(HEVC_SAO_Y_LENGTH, data32);
5390
5391 data32 = (mc_buffer_size_u_v_h << 16);
5392 WRITE_VREG(HEVC_SAO_C_LENGTH, data32);
5393
5394#ifdef VP9_10B_NV21
5395#ifdef DOS_PROJECT
5396 data32 = READ_VREG(HEVC_SAO_CTRL1);
5397 data32 &= (~0x3000);
5398 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5399 data32 |= (pbi->mem_map_mode << 12);
5400 data32 &= (~0x3);
5401 data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
5402 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5403 /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl
5404 * [17:16] dw_h0_ctrl
5405 */
5406 data32 = READ_VREG(HEVC_SAO_CTRL5);
5407 /*set them all 0 for H265_NV21 (no down-scale)*/
5408 data32 &= ~(0xff << 16);
5409 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5410 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5411 data32 &= (~0x30);
5412 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5413 data32 |= (pbi->mem_map_mode << 4);
5414 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5415#else
5416 /*m8baby test1902*/
5417 data32 = READ_VREG(HEVC_SAO_CTRL1);
5418 data32 &= (~0x3000);
5419 /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
5420 data32 |= (pbi->mem_map_mode << 12);
5421 data32 &= (~0xff0);
5422 /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
5423 data32 |= 0x880; /*.Big-Endian per 64-bit */
5424 data32 &= (~0x3);
5425 data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/
5426 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5427 /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl
5428 *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl
5429 */
5430 data32 = READ_VREG(HEVC_SAO_CTRL5);
5431 /* set them all 0 for H265_NV21 (no down-scale)*/
5432 data32 &= ~(0xff << 16);
5433 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5434
5435 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5436 data32 &= (~0x30);
5437 /*[5:4] address_format 00:linear 01:32x32 10:64x32*/
5438 data32 |= (pbi->mem_map_mode << 4);
5439 data32 &= (~0xF);
5440 data32 |= 0x8; /*Big-Endian per 64-bit*/
5441 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5442#endif
5443#else
5444 data32 = READ_VREG(HEVC_SAO_CTRL1);
5445 data32 &= (~0x3000);
5446 data32 |= (pbi->mem_map_mode <<
5447 12);
5448
5449/* [13:12] axi_aformat, 0-Linear,
5450 * 1-32x32, 2-64x32
5451 */
5452 data32 &= (~0xff0);
5453 /* data32 |= 0x670; // Big-Endian per 64-bit */
5454 data32 |= endian; /* Big-Endian per 64-bit */
5455 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
5456 data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
5457 if (get_double_write_mode(pbi) == 0)
5458 data32 |= 0x2; /*disable double write*/
5459 else if (get_double_write_mode(pbi) & 0x10)
5460 data32 |= 0x1; /*disable cm*/
5461 } else { /* >= G12A dw write control */
5462 unsigned int data;
5463 data = READ_VREG(HEVC_DBLK_CFGB);
5464 data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
5465 if (get_double_write_mode(pbi) == 0)
5466 data |= (0x1 << 8); /*enable first write*/
5467 else if (get_double_write_mode(pbi) & 0x10)
5468 data |= (0x1 << 9); /*double write only*/
5469 else
5470 data |= ((0x1 << 8) |(0x1 << 9));
5471 WRITE_VREG(HEVC_DBLK_CFGB, data);
5472 }
5473
5474 /* swap uv */
5475 if (pbi->is_used_v4l) {
5476 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5477 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5478 data32 &= ~(1 << 8); /* NV21 */
5479 else
5480 data32 |= (1 << 8); /* NV12 */
5481 }
5482
5483 /*
5484 * [31:24] ar_fifo1_axi_thred
5485 * [23:16] ar_fifo0_axi_thred
5486 * [15:14] axi_linealign, 0-16bytes, 1-32bytes, 2-64bytes
5487 * [13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32
5488 * [11:08] axi_lendian_C
5489 * [07:04] axi_lendian_Y
5490 * [3] reserved
5491 * [2] clk_forceon
5492 * [1] dw_disable:disable double write output
5493 * [0] cm_disable:disable compress output
5494 */
5495 WRITE_VREG(HEVC_SAO_CTRL1, data32);
5496
5497 if (get_double_write_mode(pbi) & 0x10) {
5498 /* [23:22] dw_v1_ctrl
5499 *[21:20] dw_v0_ctrl
5500 *[19:18] dw_h1_ctrl
5501 *[17:16] dw_h0_ctrl
5502 */
5503 data32 = READ_VREG(HEVC_SAO_CTRL5);
5504 /*set them all 0 for H265_NV21 (no down-scale)*/
5505 data32 &= ~(0xff << 16);
5506 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5507 } else {
5508 data32 = READ_VREG(HEVC_SAO_CTRL5);
5509 data32 &= (~(0xff << 16));
5510 if (get_double_write_mode(pbi) == 2 ||
5511 get_double_write_mode(pbi) == 3)
5512 data32 |= (0xff<<16);
5513 else if (get_double_write_mode(pbi) == 4)
5514 data32 |= (0x33<<16);
5515 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5516 }
5517
5518 data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
5519 data32 &= (~0x30);
5520 /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */
5521 data32 |= (pbi->mem_map_mode <<
5522 4);
5523 data32 &= (~0xF);
5524 data32 |= 0xf; /* valid only when double write only */
5525 /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */
5526
5527 /* swap uv */
5528 if (pbi->is_used_v4l) {
5529 if ((v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21) ||
5530 (v4l2_ctx->q_data[AML_Q_DATA_DST].fmt->fourcc == V4L2_PIX_FMT_NV21M))
5531 data32 |= (1 << 12); /* NV21 */
5532 else
5533 data32 &= ~(1 << 12); /* NV12 */
5534 }
5535
5536 /*
5537 * [3:0] little_endian
5538 * [5:4] address_format 00:linear 01:32x32 10:64x32
5539 * [7:6] reserved
5540 * [9:8] Linear_LineAlignment 00:16byte 01:32byte 10:64byte
5541 * [11:10] reserved
5542 * [12] CbCr_byte_swap
5543 * [31:13] reserved
5544 */
5545 WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
5546#endif
5547}
5548
5549static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
5550{
5551 struct BuffInfo_s *buf_spec = pbi->work_space_buf;
5552 unsigned int data32;
5553
5554 if (debug && pbi->init_flag == 0)
5555 pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n",
5556 __func__,
5557 buf_spec->ipp.buf_start,
5558 buf_spec->start_adr,
5559 buf_spec->short_term_rps.buf_start,
5560 buf_spec->vps.buf_start,
5561 buf_spec->sps.buf_start,
5562 buf_spec->pps.buf_start,
5563 buf_spec->sao_up.buf_start,
5564 buf_spec->swap_buf.buf_start,
5565 buf_spec->swap_buf2.buf_start,
5566 buf_spec->scalelut.buf_start,
5567 buf_spec->dblk_para.buf_start,
5568 buf_spec->dblk_data.buf_start);
5569
5570 if (mask & HW_MASK_FRONT) {
5571 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0)
5572 WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr);
5573
5574 WRITE_VREG(HEVC_SHORT_TERM_RPS,
5575 buf_spec->short_term_rps.buf_start);
5576 /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/
5577 /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/
5578 WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
5579 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER,
5580 buf_spec->swap_buf.buf_start);
5581 WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2,
5582 buf_spec->swap_buf2.buf_start);
5583 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5584
5585 }
5586
5587 if (mask & HW_MASK_BACK) {
5588#ifdef LOSLESS_COMPRESS_MODE
5589 int losless_comp_header_size =
5590 compute_losless_comp_header_size(pbi->init_pic_w,
5591 pbi->init_pic_h);
5592 int losless_comp_body_size =
5593 compute_losless_comp_body_size(pbi->init_pic_w,
5594 pbi->init_pic_h, buf_alloc_depth == 10);
5595#endif
5596 WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE,
5597 buf_spec->ipp.buf_start);
5598 WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start);
5599 WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start);
5600 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5601 /* cfg_addr_adp*/
5602 WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start);
5603 if (debug & VP9_DEBUG_BUFMGR_MORE)
5604 pr_info("Write HEVC_DBLK_CFGE\n");
5605 }
5606 /* cfg_p_addr */
5607 WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start);
5608 /* cfg_d_addr */
5609 WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
5610
5611 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5612 /*
5613 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
5614 * data32 = data32 * 2;
5615 * data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
5616 * data32 = data32 * 2;
5617 */
5618 WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
5619 }
5620#ifdef LOSLESS_COMPRESS_MODE
5621 if (pbi->mmu_enable) {
5622 /*bit[4] : paged_mem_mode*/
5623 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
5624 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SM1)
5625 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
5626 } else {
5627 /*if(cur_pic_config->bit_depth == VPX_BITS_10)
5628 * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
5629 */
5630 /*bit[3] smem mdoe*/
5631 /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/
5632 /*bit[3] smem mdoe*/
5633 WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5634 (losless_comp_body_size >> 5));
5635 }
5636 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,
5637 (losless_comp_body_size >> 5));*/
5638 /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,
5639 (0xff<<20) | (0xff<<10) | 0xff);*/
5640 /*8-bit mode */
5641 WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
5642 WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
5643 WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size);
5644 if (get_double_write_mode(pbi) & 0x10)
5645 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5646#else
5647 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
5648#endif
5649
5650 if (pbi->mmu_enable) {
5651 WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start);
5652 WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start
5653 + buf_spec->mmu_vbh.buf_size/2);
5654 /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/
5655 /*data32 |= 0x1;*/
5656 /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/
5657
5658 /* use HEVC_CM_HEADER_START_ADDR */
5659 data32 = READ_VREG(HEVC_SAO_CTRL5);
5660 data32 |= (1<<10);
5661 WRITE_VREG(HEVC_SAO_CTRL5, data32);
5662 }
5663
5664 WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start);
5665
5666 WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr);
5667 /**/
5668 WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr);
5669 WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr);
5670 if (pbi->mmu_enable) {
5671 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
5672 WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr);
5673 else
5674 WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr);
5675 }
5676 }
5677}
5678
5679
5680#ifdef VP9_LPF_LVL_UPDATE
5681/*
5682 * Defines, declarations, sub-functions for vp9 de-block loop
5683 filter Thr/Lvl table update
5684 * - struct segmentation is for loop filter only (removed something)
5685 * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will
5686 be instantiated in C_Entry
5687 * - vp9_loop_filter_init run once before decoding start
5688 * - vp9_loop_filter_frame_init run before every frame decoding start
5689 * - set video format to VP9 is in vp9_loop_filter_init
5690 */
5691#define MAX_LOOP_FILTER 63
5692#define MAX_REF_LF_DELTAS 4
5693#define MAX_MODE_LF_DELTAS 2
5694/*#define INTRA_FRAME 0*/
5695/*#define LAST_FRAME 1*/
5696/*#define MAX_REF_FRAMES 4*/
5697#define SEGMENT_DELTADATA 0
5698#define SEGMENT_ABSDATA 1
5699#define MAX_SEGMENTS 8
5700/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/
5701/*no use for loop filter, if this struct for common use, pls add it back*/
5702/*#define PREDICTION_PROBS 3*/
5703/* no use for loop filter, if this struct for common use, pls add it back*/
5704
5705enum SEG_LVL_FEATURES {
5706 SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/
5707 SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/
5708 SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/
5709 SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/
5710 SEG_LVL_MAX = 4 /*Number of features supported*/
5711};
5712
5713struct segmentation {
5714 uint8_t enabled;
5715 uint8_t update_map;
5716 uint8_t update_data;
5717 uint8_t abs_delta;
5718 uint8_t temporal_update;
5719
5720 /*no use for loop filter, if this struct
5721 *for common use, pls add it back
5722 */
5723 /*vp9_prob tree_probs[SEG_TREE_PROBS]; */
5724 /* no use for loop filter, if this struct
5725 * for common use, pls add it back
5726 */
5727 /*vp9_prob pred_probs[PREDICTION_PROBS];*/
5728
5729 int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX];
5730 unsigned int feature_mask[MAX_SEGMENTS];
5731};
5732
5733struct loop_filter_thresh {
5734 uint8_t mblim;
5735 uint8_t lim;
5736 uint8_t hev_thr;
5737};
5738
5739struct loop_filter_info_n {
5740 struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1];
5741 uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS];
5742};
5743
5744struct loopfilter {
5745 int filter_level;
5746
5747 int sharpness_level;
5748 int last_sharpness_level;
5749
5750 uint8_t mode_ref_delta_enabled;
5751 uint8_t mode_ref_delta_update;
5752
5753 /*0 = Intra, Last, GF, ARF*/
5754 signed char ref_deltas[MAX_REF_LF_DELTAS];
5755 signed char last_ref_deltas[MAX_REF_LF_DELTAS];
5756
5757 /*0 = ZERO_MV, MV*/
5758 signed char mode_deltas[MAX_MODE_LF_DELTAS];
5759 signed char last_mode_deltas[MAX_MODE_LF_DELTAS];
5760};
5761
5762static int vp9_clamp(int value, int low, int high)
5763{
5764 return value < low ? low : (value > high ? high : value);
5765}
5766
5767int segfeature_active(struct segmentation *seg,
5768 int segment_id,
5769 enum SEG_LVL_FEATURES feature_id) {
5770 return seg->enabled &&
5771 (seg->feature_mask[segment_id] & (1 << feature_id));
5772}
5773
5774int get_segdata(struct segmentation *seg, int segment_id,
5775 enum SEG_LVL_FEATURES feature_id) {
5776 return seg->feature_data[segment_id][feature_id];
5777}
5778
5779static void vp9_update_sharpness(struct loop_filter_info_n *lfi,
5780 int sharpness_lvl)
5781{
5782 int lvl;
5783 /*For each possible value for the loop filter fill out limits*/
5784 for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) {
5785 /*Set loop filter parameters that control sharpness.*/
5786 int block_inside_limit = lvl >> ((sharpness_lvl > 0) +
5787 (sharpness_lvl > 4));
5788
5789 if (sharpness_lvl > 0) {
5790 if (block_inside_limit > (9 - sharpness_lvl))
5791 block_inside_limit = (9 - sharpness_lvl);
5792 }
5793
5794 if (block_inside_limit < 1)
5795 block_inside_limit = 1;
5796
5797 lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit;
5798 lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) +
5799 block_inside_limit);
5800 }
5801}
5802
5803/*instantiate this function once when decode is started*/
5804void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
5805{
5806 struct loop_filter_info_n *lfi = pbi->lfi;
5807 struct loopfilter *lf = pbi->lf;
5808 struct segmentation *seg_4lf = pbi->seg_4lf;
5809 int i;
5810 unsigned int data32;
5811
5812 memset(lfi, 0, sizeof(struct loop_filter_info_n));
5813 memset(lf, 0, sizeof(struct loopfilter));
5814 memset(seg_4lf, 0, sizeof(struct segmentation));
5815 lf->sharpness_level = 0; /*init to 0 */
5816 /*init limits for given sharpness*/
5817 vp9_update_sharpness(lfi, lf->sharpness_level);
5818 lf->last_sharpness_level = lf->sharpness_level;
5819 /*init hev threshold const vectors (actually no use)
5820 *for (i = 0; i <= MAX_LOOP_FILTER; i++)
5821 * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4);
5822 */
5823
5824 /*Write to register*/
5825 for (i = 0; i < 32; i++) {
5826 unsigned int thr;
5827
5828 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) |
5829 (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5830 thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) |
5831 (lfi->lfthr[i * 2].mblim & 0xff);
5832 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5833 }
5834
5835 /*video format is VP9*/
5836 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
5837 data32 = (0x3 << 14) | // (dw fifo thres r and b)
5838 (0x3 << 12) | // (dw fifo thres r or b)
5839 (0x3 << 10) | // (dw fifo thres not r/b)
5840 (0x3 << 8) | // 1st/2nd write both enable
5841 (0x1 << 0); // vp9 video format
5842 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
5843 data32 = (0x57 << 8) | /*1st/2nd write both enable*/
5844 (0x1 << 0); /*vp9 video format*/
5845 } else
5846 data32 = 0x40400001;
5847
5848 WRITE_VREG(HEVC_DBLK_CFGB, data32);
5849 if (debug & VP9_DEBUG_BUFMGR_MORE)
5850 pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
5851}
5852 /* perform this function per frame*/
5853void vp9_loop_filter_frame_init(struct segmentation *seg,
5854 struct loop_filter_info_n *lfi, struct loopfilter *lf,
5855 int default_filt_lvl) {
5856 int i;
5857 int seg_id;
5858 /*n_shift is the multiplier for lf_deltas
5859 *the multiplier is 1 for when filter_lvl is between 0 and 31;
5860 *2 when filter_lvl is between 32 and 63
5861 */
5862 const int scale = 1 << (default_filt_lvl >> 5);
5863
5864 /*update limits if sharpness has changed*/
5865 if (lf->last_sharpness_level != lf->sharpness_level) {
5866 vp9_update_sharpness(lfi, lf->sharpness_level);
5867 lf->last_sharpness_level = lf->sharpness_level;
5868
5869 /*Write to register*/
5870 for (i = 0; i < 32; i++) {
5871 unsigned int thr;
5872
5873 thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8)
5874 | (lfi->lfthr[i * 2 + 1].mblim & 0xff);
5875 thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8)
5876 | (lfi->lfthr[i * 2].mblim & 0xff);
5877 WRITE_VREG(HEVC_DBLK_CFG9, thr);
5878 }
5879 }
5880
5881 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/
5882 int lvl_seg = default_filt_lvl;
5883
5884 if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) {
5885 const int data = get_segdata(seg, seg_id,
5886 SEG_LVL_ALT_LF);
5887 lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ?
5888 data : default_filt_lvl + data,
5889 0, MAX_LOOP_FILTER);
5890#ifdef DBG_LF_PRINT
5891 pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg);
5892#endif
5893 }
5894
5895 if (!lf->mode_ref_delta_enabled) {
5896 /*we could get rid of this if we assume that deltas are set to
5897 *zero when not in use; encoder always uses deltas
5898 */
5899 memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id]));
5900 } else {
5901 int ref, mode;
5902 const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME]
5903 * scale;
5904#ifdef DBG_LF_PRINT
5905 pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id);
5906 pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]);
5907#endif
5908 lfi->lvl[seg_id][INTRA_FRAME][0] =
5909 vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER);
5910
5911 for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) {
5912 /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/
5913 for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) {
5914 /*MAX_MODE_LF_DELTAS = 2*/
5915 const int inter_lvl =
5916 lvl_seg + lf->ref_deltas[ref] * scale
5917 + lf->mode_deltas[mode] * scale;
5918#ifdef DBG_LF_PRINT
5919#endif
5920 lfi->lvl[seg_id][ref][mode] =
5921 vp9_clamp(inter_lvl, 0,
5922 MAX_LOOP_FILTER);
5923 }
5924 }
5925 }
5926 }
5927
5928#ifdef DBG_LF_PRINT
5929 /*print out thr/lvl table per frame*/
5930 for (i = 0; i <= MAX_LOOP_FILTER; i++) {
5931 pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n",
5932 i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim,
5933 lfi->lfthr[i].lim);
5934 }
5935 for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {
5936 pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n",
5937 seg_id, lfi->lvl[seg_id][0][0],
5938 lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0],
5939 lfi->lvl[seg_id][3][0]);
5940 pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1],
5941 lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1],
5942 lfi->lvl[seg_id][3][1]);
5943 }
5944#endif
5945
5946 /*Write to register */
5947 for (i = 0; i < 16; i++) {
5948 unsigned int level;
5949
5950 level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) |
5951 ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) |
5952 ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) |
5953 (lfi->lvl[i >> 1][0][i & 1] & 0x3f);
5954 if (!default_filt_lvl)
5955 level = 0;
5956 WRITE_VREG(HEVC_DBLK_CFGA, level);
5957 }
5958}
5959/* VP9_LPF_LVL_UPDATE */
5960#endif
5961
5962static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
5963{
5964 unsigned int data32;
5965 int i;
5966 const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
5967 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
5968 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
5969 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
5970 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
5971 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
5972 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
5973 0x7C00
5974 };
5975#if 0
5976 if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
5977 /* Set MCR fetch priorities*/
5978 data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
5979 (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
5980 WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32);
5981 }
5982#endif
5983 /*if (debug & VP9_DEBUG_BUFMGR_MORE)
5984 pr_info("%s\n", __func__);*/
5985 if (mask & HW_MASK_FRONT) {
5986 data32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
5987#if 1
5988 /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */
5989 data32 &= ~(7 << 29);
5990 data32 |= (3 << 29);
5991#endif
5992 data32 = data32 |
5993 (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/
5994 (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/
5995 (1 << 7) |/*dec_done_int_cpu_enable*/
5996 (1 << 4) |/*startcode_found_int_cpu_enable*/
5997 (0 << 3) |/*startcode_found_int_amrisc_enable*/
5998 (1 << 0) /*parser_int_enable*/
5999 ;
6000#ifdef SUPPORT_FB_DECODING
6001#ifndef FB_DECODING_TEST_SCHEDULE
6002 /*fed_fb_slice_done_int_cpu_enable*/
6003 if (pbi->used_stage_buf_num > 0)
6004 data32 |= (1 << 10);
6005#endif
6006#endif
6007 WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32);
6008
6009 data32 = READ_VREG(HEVC_SHIFT_STATUS);
6010 data32 = data32 |
6011 (0 << 1) |/*emulation_check_off VP9
6012 do not have emulation*/
6013 (1 << 0)/*startcode_check_on*/
6014 ;
6015 WRITE_VREG(HEVC_SHIFT_STATUS, data32);
6016 WRITE_VREG(HEVC_SHIFT_CONTROL,
6017 (0 << 14) | /*disable_start_code_protect*/
6018 (1 << 10) | /*length_zero_startcode_en for VP9*/
6019 (1 << 9) | /*length_valid_startcode_en for VP9*/
6020 (3 << 6) | /*sft_valid_wr_position*/
6021 (2 << 4) | /*emulate_code_length_sub_1*/
6022 (3 << 1) | /*start_code_length_sub_1
6023 VP9 use 0x00000001 as startcode (4 Bytes)*/
6024 (1 << 0) /*stream_shift_enable*/
6025 );
6026
6027 WRITE_VREG(HEVC_CABAC_CONTROL,
6028 (1 << 0)/*cabac_enable*/
6029 );
6030
6031 WRITE_VREG(HEVC_PARSER_CORE_CONTROL,
6032 (1 << 0)/* hevc_parser_core_clk_en*/
6033 );
6034
6035
6036 WRITE_VREG(HEVC_DEC_STATUS_REG, 0);
6037
6038 }
6039
6040 if (mask & HW_MASK_BACK) {
6041 /*Initial IQIT_SCALELUT memory
6042 -- just to avoid X in simulation*/
6043
6044 WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/
6045 for (i = 0; i < 1024; i++)
6046 WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0);
6047 }
6048
6049 if (mask & HW_MASK_FRONT) {
6050 u32 decode_mode;
6051#ifdef ENABLE_SWAP_TEST
6052 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100);
6053#else
6054 WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0);
6055#endif
6056#ifdef MULTI_INSTANCE_SUPPORT
6057 if (!pbi->m_ins_flag) {
6058 if (pbi->low_latency_flag)
6059 decode_mode = DECODE_MODE_SINGLE_LOW_LATENCY;
6060 else
6061 decode_mode = DECODE_MODE_SINGLE;
6062 } else if (vdec_frame_based(hw_to_vdec(pbi)))
6063 decode_mode = pbi->no_head ?
6064 DECODE_MODE_MULTI_FRAMEBASE_NOHEAD :
6065 DECODE_MODE_MULTI_FRAMEBASE;
6066 else
6067 decode_mode = DECODE_MODE_MULTI_STREAMBASE;
6068#ifdef SUPPORT_FB_DECODING
6069#ifndef FB_DECODING_TEST_SCHEDULE
6070 if (pbi->used_stage_buf_num > 0)
6071 decode_mode |= (0x01 << 24);
6072#endif
6073#endif
6074 WRITE_VREG(DECODE_MODE, decode_mode);
6075 WRITE_VREG(HEVC_DECODE_SIZE, 0);
6076 WRITE_VREG(HEVC_DECODE_COUNT, 0);
6077#else
6078 WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE);
6079 WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);
6080 WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/
6081#endif
6082 /*Send parser_cmd*/
6083 WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
6084 for (i = 0; i < PARSER_CMD_NUMBER; i++)
6085 WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
6086 WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
6087 WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
6088 WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
6089
6090
6091 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6092 /* (1 << 8) |*/ /*sao_sw_pred_enable*/
6093 (1 << 5) | /*parser_sao_if_en*/
6094 (1 << 2) | /*parser_mpred_if_en*/
6095 (1 << 0) /*parser_scaler_if_en*/
6096 );
6097 }
6098
6099 if (mask & HW_MASK_BACK) {
6100 /*Changed to Start MPRED in microcode*/
6101 /*
6102 pr_info("[test.c] Start MPRED\n");
6103 WRITE_VREG(HEVC_MPRED_INT_STATUS,
6104 (1<<31)
6105 );
6106 */
6107 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6108 (0 << 1) | /*enable ipp*/
6109 (1 << 0) /*software reset ipp and mpp*/
6110 );
6111 WRITE_VREG(HEVCD_IPP_TOP_CNTL,
6112 (1 << 1) | /*enable ipp*/
6113 (0 << 0) /*software reset ipp and mpp*/
6114 );
6115 if (get_double_write_mode(pbi) & 0x10) {
6116 /*Enable NV21 reference read mode for MC*/
6117 WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31);
6118 }
6119
6120 /*Initialize mcrcc and decomp perf counters*/
6121 if (mcrcc_cache_alg_flag &&
6122 pbi->init_flag == 0) {
6123 mcrcc_perfcount_reset();
6124 decomp_perfcount_reset();
6125 }
6126 }
6127 return;
6128}
6129
6130
6131#ifdef CONFIG_HEVC_CLK_FORCED_ON
6132static void config_vp9_clk_forced_on(void)
6133{
6134 unsigned int rdata32;
6135 /*IQIT*/
6136 rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL);
6137 WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2));
6138
6139 /* DBLK*/
6140 rdata32 = READ_VREG(HEVC_DBLK_CFG0);
6141 WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2));
6142
6143 /* SAO*/
6144 rdata32 = READ_VREG(HEVC_SAO_CTRL1);
6145 WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2));
6146
6147 /*MPRED*/
6148 rdata32 = READ_VREG(HEVC_MPRED_CTRL1);
6149 WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24));
6150
6151 /* PARSER*/
6152 rdata32 = READ_VREG(HEVC_STREAM_CONTROL);
6153 WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15));
6154 rdata32 = READ_VREG(HEVC_SHIFT_CONTROL);
6155 WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15));
6156 rdata32 = READ_VREG(HEVC_CABAC_CONTROL);
6157 WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13));
6158 rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL);
6159 WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15));
6160 rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL);
6161 WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15));
6162 rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL);
6163 WRITE_VREG(HEVC_PARSER_IF_CONTROL,
6164 rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1));
6165
6166 /*IPP*/
6167 rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG);
6168 WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff);
6169
6170 /* MCRCC*/
6171 rdata32 = READ_VREG(HEVCD_MCRCC_CTL1);
6172 WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3));
6173}
6174#endif
6175
6176
6177#ifdef MCRCC_ENABLE
6178static void dump_hit_rate(struct VP9Decoder_s *pbi)
6179{
6180 if (debug & VP9_DEBUG_CACHE_HIT_RATE) {
6181 mcrcc_get_hitrate(pbi->m_ins_flag);
6182 decomp_get_hitrate();
6183 decomp_get_comprate();
6184 }
6185}
6186
6187static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
6188{
6189 unsigned int rdata32;
6190 unsigned short is_inter;
6191 /*pr_info("Entered config_mcrcc_axi_hw...\n");*/
6192 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/
6193 is_inter = ((pbi->common.frame_type != KEY_FRAME) &&
6194 (!pbi->common.intra_only)) ? 1 : 0;
6195 if (!is_inter) { /* I-PIC*/
6196 /*remove reset -- disables clock*/
6197 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6198 return;
6199 }
6200
6201 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6202 mcrcc_get_hitrate(pbi->m_ins_flag);
6203 decomp_get_hitrate();
6204 decomp_get_comprate();
6205 }
6206
6207 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6208 (0 << 8) | (1 << 1) | 0);
6209 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6210 rdata32 = rdata32 & 0xffff;
6211 rdata32 = rdata32 | (rdata32 << 16);
6212 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6213 /*Programme canvas1 */
6214 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6215 rdata32 = rdata32 & 0xffff;
6216 rdata32 = rdata32 | (rdata32 << 16);
6217 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6218 /*enable mcrcc progressive-mode*/
6219 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0);
6220}
6221
6222static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
6223{
6224 u32 curr_picnum = -1;
6225 u32 lastref_picnum = -1;
6226 u32 goldenref_picnum = -1;
6227 u32 altref_picnum = -1;
6228
6229 u32 lastref_delta_picnum;
6230 u32 goldenref_delta_picnum;
6231 u32 altref_delta_picnum;
6232
6233 u32 rdata32;
6234
6235 u32 lastcanvas;
6236 u32 goldencanvas;
6237 u32 altrefcanvas;
6238
6239 u16 is_inter;
6240 u16 lastref_inref;
6241 u16 goldenref_inref;
6242 u16 altref_inref;
6243
6244 u32 refcanvas_array[3], utmp;
6245 int deltapicnum_array[3], tmp;
6246
6247 struct VP9_Common_s *cm = &pbi->common;
6248 struct PIC_BUFFER_CONFIG_s *cur_pic_config
6249 = &cm->cur_frame->buf;
6250 curr_picnum = cur_pic_config->decode_idx;
6251 if (cm->frame_refs[0].buf)
6252 lastref_picnum = cm->frame_refs[0].buf->decode_idx;
6253 if (cm->frame_refs[1].buf)
6254 goldenref_picnum = cm->frame_refs[1].buf->decode_idx;
6255 if (cm->frame_refs[2].buf)
6256 altref_picnum = cm->frame_refs[2].buf->decode_idx;
6257
6258 lastref_delta_picnum = (lastref_picnum >= curr_picnum) ?
6259 (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum);
6260 goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ?
6261 (goldenref_picnum - curr_picnum) :
6262 (curr_picnum - goldenref_picnum);
6263 altref_delta_picnum =
6264 (altref_picnum >= curr_picnum) ?
6265 (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum);
6266
6267 lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0;
6268 goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0;
6269 altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0;
6270
6271 if (debug & VP9_DEBUG_CACHE)
6272 pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6273 __func__, lastref_inref, goldenref_inref, altref_inref);
6274
6275 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */
6276
6277 is_inter = ((pbi->common.frame_type != KEY_FRAME)
6278 && (!pbi->common.intra_only)) ? 1 : 0;
6279
6280 if (!is_inter) { /* I-PIC */
6281 /* remove reset -- disables clock */
6282 WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
6283 return;
6284 }
6285
6286 if (!pbi->m_ins_flag)
6287 dump_hit_rate(pbi);
6288
6289 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0);
6290 lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6291 goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6292 altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6293
6294 if (debug & VP9_DEBUG_CACHE)
6295 pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n",
6296 lastcanvas, goldencanvas, altrefcanvas);
6297
6298 altref_inref = ((altref_inref == 1) &&
6299 (altrefcanvas != (goldenref_inref
6300 ? goldencanvas : 0xffffffff)) &&
6301 (altrefcanvas != (lastref_inref ?
6302 lastcanvas : 0xffffffff))) ? 1 : 0;
6303 goldenref_inref = ((goldenref_inref == 1) &&
6304 (goldencanvas != (lastref_inref ?
6305 lastcanvas : 0xffffffff))) ? 1 : 0;
6306 if (debug & VP9_DEBUG_CACHE)
6307 pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n",
6308 lastref_inref, goldenref_inref, altref_inref);
6309
6310 altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff;
6311 goldenref_delta_picnum = goldenref_inref ?
6312 goldenref_delta_picnum : 0x7fffffff;
6313 lastref_delta_picnum = lastref_inref ?
6314 lastref_delta_picnum : 0x7fffffff;
6315 if (debug & VP9_DEBUG_CACHE)
6316 pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n",
6317 lastref_delta_picnum, goldenref_delta_picnum,
6318 altref_delta_picnum);
6319 /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/
6320
6321 refcanvas_array[0] = lastcanvas;
6322 refcanvas_array[1] = goldencanvas;
6323 refcanvas_array[2] = altrefcanvas;
6324
6325 deltapicnum_array[0] = lastref_delta_picnum;
6326 deltapicnum_array[1] = goldenref_delta_picnum;
6327 deltapicnum_array[2] = altref_delta_picnum;
6328
6329 /* sort0 : 2-to-1 */
6330 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6331 utmp = refcanvas_array[2];
6332 refcanvas_array[2] = refcanvas_array[1];
6333 refcanvas_array[1] = utmp;
6334 tmp = deltapicnum_array[2];
6335 deltapicnum_array[2] = deltapicnum_array[1];
6336 deltapicnum_array[1] = tmp;
6337 }
6338 /* sort1 : 1-to-0 */
6339 if (deltapicnum_array[1] < deltapicnum_array[0]) {
6340 utmp = refcanvas_array[1];
6341 refcanvas_array[1] = refcanvas_array[0];
6342 refcanvas_array[0] = utmp;
6343 tmp = deltapicnum_array[1];
6344 deltapicnum_array[1] = deltapicnum_array[0];
6345 deltapicnum_array[0] = tmp;
6346 }
6347 /* sort2 : 2-to-1 */
6348 if (deltapicnum_array[2] < deltapicnum_array[1]) {
6349 utmp = refcanvas_array[2]; refcanvas_array[2] =
6350 refcanvas_array[1]; refcanvas_array[1] = utmp;
6351 tmp = deltapicnum_array[2]; deltapicnum_array[2] =
6352 deltapicnum_array[1]; deltapicnum_array[1] = tmp;
6353 }
6354 if (mcrcc_cache_alg_flag ==
6355 THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/
6356 /* lowest delta_picnum */
6357 rdata32 = refcanvas_array[0];
6358 rdata32 = rdata32 & 0xffff;
6359 rdata32 = rdata32 | (rdata32 << 16);
6360 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6361
6362 /* 2nd-lowest delta_picnum */
6363 rdata32 = refcanvas_array[1];
6364 rdata32 = rdata32 & 0xffff;
6365 rdata32 = rdata32 | (rdata32 << 16);
6366 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6367 } else {
6368 /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/
6369 WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
6370 (0 << 8) | (1<<1) | 0);
6371 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6372 rdata32 = rdata32 & 0xffff;
6373 rdata32 = rdata32 | (rdata32 << 16);
6374 WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32);
6375
6376 /* Programme canvas1 */
6377 rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
6378 rdata32 = rdata32 & 0xffff;
6379 rdata32 = rdata32 | (rdata32 << 16);
6380 WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32);
6381 }
6382
6383 WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */
6384 return;
6385}
6386
6387#endif
6388
6389
6390static void free_lf_buf(struct VP9Decoder_s *pbi)
6391{
6392 if (pbi->lfi)
6393 vfree(pbi->lfi);
6394 if (pbi->lf)
6395 vfree(pbi->lf);
6396 if (pbi->seg_4lf)
6397 vfree(pbi->seg_4lf);
6398 pbi->lfi = NULL;
6399 pbi->lf = NULL;
6400 pbi->seg_4lf = NULL;
6401}
6402
6403static int alloc_lf_buf(struct VP9Decoder_s *pbi)
6404{
6405 pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n));
6406 pbi->lf = vmalloc(sizeof(struct loopfilter));
6407 pbi->seg_4lf = vmalloc(sizeof(struct segmentation));
6408 if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) {
6409 free_lf_buf(pbi);
6410 pr_err("[test.c] vp9_loop_filter init malloc error!!!\n");
6411 return -1;
6412 }
6413 return 0;
6414}
6415
6416static void vp9_local_uninit(struct VP9Decoder_s *pbi)
6417{
6418 pbi->rpm_ptr = NULL;
6419 pbi->lmem_ptr = NULL;
6420 if (pbi->rpm_addr) {
6421 dma_free_coherent(amports_get_dma_device(),
6422 RPM_BUF_SIZE,
6423 pbi->rpm_addr,
6424 pbi->rpm_phy_addr);
6425 pbi->rpm_addr = NULL;
6426 }
6427 if (pbi->lmem_addr) {
6428 if (pbi->lmem_phy_addr)
6429 dma_free_coherent(amports_get_dma_device(),
6430 LMEM_BUF_SIZE, pbi->lmem_addr,
6431 pbi->lmem_phy_addr);
6432 pbi->lmem_addr = NULL;
6433 }
6434 if (pbi->prob_buffer_addr) {
6435 if (pbi->prob_buffer_phy_addr)
6436 dma_free_coherent(amports_get_dma_device(),
6437 PROB_BUF_SIZE, pbi->prob_buffer_addr,
6438 pbi->prob_buffer_phy_addr);
6439
6440 pbi->prob_buffer_addr = NULL;
6441 }
6442 if (pbi->count_buffer_addr) {
6443 if (pbi->count_buffer_phy_addr)
6444 dma_free_coherent(amports_get_dma_device(),
6445 COUNT_BUF_SIZE, pbi->count_buffer_addr,
6446 pbi->count_buffer_phy_addr);
6447
6448 pbi->count_buffer_addr = NULL;
6449 }
6450 if (pbi->mmu_enable) {
6451 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6452 if (pbi->frame_mmu_map_addr) {
6453 if (pbi->frame_mmu_map_phy_addr)
6454 dma_free_coherent(amports_get_dma_device(),
6455 mmu_map_size,
6456 pbi->frame_mmu_map_addr,
6457 pbi->frame_mmu_map_phy_addr);
6458 pbi->frame_mmu_map_addr = NULL;
6459 }
6460 }
6461#ifdef SUPPORT_FB_DECODING
6462 if (pbi->stage_mmu_map_addr) {
6463 if (pbi->stage_mmu_map_phy_addr)
6464 dma_free_coherent(amports_get_dma_device(),
6465 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6466 pbi->stage_mmu_map_addr,
6467 pbi->stage_mmu_map_phy_addr);
6468 pbi->stage_mmu_map_addr = NULL;
6469 }
6470
6471 uninit_stage_buf(pbi);
6472#endif
6473
6474#ifdef VP9_LPF_LVL_UPDATE
6475 free_lf_buf(pbi);
6476#endif
6477 if (pbi->gvs)
6478 vfree(pbi->gvs);
6479 pbi->gvs = NULL;
6480}
6481
6482static int vp9_local_init(struct VP9Decoder_s *pbi)
6483{
6484 int ret = -1;
6485 /*int losless_comp_header_size, losless_comp_body_size;*/
6486
6487 struct BuffInfo_s *cur_buf_info = NULL;
6488
6489 memset(&pbi->param, 0, sizeof(union param_u));
6490 memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
6491#ifdef MULTI_INSTANCE_SUPPORT
6492 cur_buf_info = &pbi->work_space_buf_store;
6493
6494 if (vdec_is_support_4k()) {
6495 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6496 memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
6497 sizeof(struct BuffInfo_s));
6498 } else
6499 memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
6500 sizeof(struct BuffInfo_s));
6501 } else
6502 memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
6503 sizeof(struct BuffInfo_s));
6504
6505 cur_buf_info->start_adr = pbi->buf_start;
6506 if (!pbi->mmu_enable)
6507 pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
6508
6509#else
6510/*! MULTI_INSTANCE_SUPPORT*/
6511 if (vdec_is_support_4k()) {
6512 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
6513 cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
6514 else
6515 cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
6516 } else
6517 cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
6518
6519#endif
6520
6521 init_buff_spec(pbi, cur_buf_info);
6522 vp9_bufmgr_init(pbi, cur_buf_info, NULL);
6523
6524 if (!vdec_is_support_4k()
6525 && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
6526 buf_alloc_width = 1920;
6527 buf_alloc_height = 1088;
6528 if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) {
6529 pbi->max_pic_w = 1920;
6530 pbi->max_pic_h = 1088;
6531 }
6532 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
6533 buf_alloc_width = 8192;
6534 buf_alloc_height = 4608;
6535 }
6536 pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
6537 (buf_alloc_width ? buf_alloc_width :
6538 (pbi->vvp9_amstream_dec_info.width ?
6539 pbi->vvp9_amstream_dec_info.width :
6540 pbi->work_space_buf->max_width));
6541 pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h :
6542 (buf_alloc_height ? buf_alloc_height :
6543 (pbi->vvp9_amstream_dec_info.height ?
6544 pbi->vvp9_amstream_dec_info.height :
6545 pbi->work_space_buf->max_height));
6546
6547 /* video is not support unaligned with 64 in tl1
6548 ** vdec canvas mode will be linear when dump yuv is set
6549 */
6550 if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
6551 (pbi->double_write_mode != 0) &&
6552 (((pbi->max_pic_w % 64) != 0) ||
6553 (pbi->vvp9_amstream_dec_info.width % 64) != 0)) {
6554 if (hw_to_vdec(pbi)->canvas_mode !=
6555 CANVAS_BLKMODE_LINEAR)
6556 pbi->mem_map_mode = 2;
6557 else {
6558 pbi->mem_map_mode = 0;
6559 pr_info("vdec blkmod linear, force mem_map_mode 0\n");
6560 }
6561 }
6562
6563#ifndef MV_USE_FIXED_BUF
6564 if (init_mv_buf_list(pbi) < 0) {
6565 pr_err("%s: init_mv_buf_list fail\n", __func__);
6566 return -1;
6567 }
6568#endif
6569 if (pbi->save_buffer_mode)
6570 pbi->used_buf_num = MAX_BUF_NUM_SAVE_BUF;
6571 else {
6572 if (pbi->is_used_v4l)
6573 pbi->used_buf_num = 5 + pbi->dynamic_buf_num_margin;
6574 else
6575 pbi->used_buf_num = max_buf_num;
6576 }
6577
6578 if (pbi->used_buf_num > MAX_BUF_NUM)
6579 pbi->used_buf_num = MAX_BUF_NUM;
6580 if (pbi->used_buf_num > FRAME_BUFFERS)
6581 pbi->used_buf_num = FRAME_BUFFERS;
6582
6583 pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param)
6584 & 0x40) >> 6;
6585
6586 if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) {
6587 pbi->rpm_addr = dma_alloc_coherent(amports_get_dma_device(),
6588 RPM_BUF_SIZE,
6589 &pbi->rpm_phy_addr, GFP_KERNEL);
6590 if (pbi->rpm_addr == NULL) {
6591 pr_err("%s: failed to alloc rpm buffer\n", __func__);
6592 return -1;
6593 }
6594
6595 pbi->rpm_ptr = pbi->rpm_addr;
6596 }
6597
6598 pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(),
6599 LMEM_BUF_SIZE,
6600 &pbi->lmem_phy_addr, GFP_KERNEL);
6601 if (pbi->lmem_addr == NULL) {
6602 pr_err("%s: failed to alloc lmem buffer\n", __func__);
6603 return -1;
6604 }
6605 pbi->lmem_ptr = pbi->lmem_addr;
6606
6607 pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6608 PROB_BUF_SIZE,
6609 &pbi->prob_buffer_phy_addr, GFP_KERNEL);
6610 if (pbi->prob_buffer_addr == NULL) {
6611 pr_err("%s: failed to alloc prob_buffer\n", __func__);
6612 return -1;
6613 }
6614 memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE);
6615 pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(),
6616 COUNT_BUF_SIZE,
6617 &pbi->count_buffer_phy_addr, GFP_KERNEL);
6618 if (pbi->count_buffer_addr == NULL) {
6619 pr_err("%s: failed to alloc count_buffer\n", __func__);
6620 return -1;
6621 }
6622 memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE);
6623
6624 if (pbi->mmu_enable) {
6625 u32 mmu_map_size = vvp9_frame_mmu_map_size(pbi);
6626 pbi->frame_mmu_map_addr =
6627 dma_alloc_coherent(amports_get_dma_device(),
6628 mmu_map_size,
6629 &pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
6630 if (pbi->frame_mmu_map_addr == NULL) {
6631 pr_err("%s: failed to alloc count_buffer\n", __func__);
6632 return -1;
6633 }
6634 memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
6635 }
6636#ifdef SUPPORT_FB_DECODING
6637 if (pbi->m_ins_flag && stage_buf_num > 0) {
6638 pbi->stage_mmu_map_addr =
6639 dma_alloc_coherent(amports_get_dma_device(),
6640 STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS,
6641 &pbi->stage_mmu_map_phy_addr, GFP_KERNEL);
6642 if (pbi->stage_mmu_map_addr == NULL) {
6643 pr_err("%s: failed to alloc count_buffer\n", __func__);
6644 return -1;
6645 }
6646 memset(pbi->stage_mmu_map_addr,
6647 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS);
6648
6649 init_stage_buf(pbi);
6650 }
6651#endif
6652
6653 ret = 0;
6654 return ret;
6655}
6656
6657/********************************************
6658 * Mailbox command
6659 ********************************************/
6660#define CMD_FINISHED 0
6661#define CMD_ALLOC_VIEW 1
6662#define CMD_FRAME_DISPLAY 3
6663#define CMD_DEBUG 10
6664
6665
6666#define DECODE_BUFFER_NUM_MAX 32
6667#define DISPLAY_BUFFER_NUM 6
6668
6669#define video_domain_addr(adr) (adr&0x7fffffff)
6670#define DECODER_WORK_SPACE_SIZE 0x800000
6671
6672#define spec2canvas(x) \
6673 (((x)->uv_canvas_index << 16) | \
6674 ((x)->uv_canvas_index << 8) | \
6675 ((x)->y_canvas_index << 0))
6676
6677
6678static void set_canvas(struct VP9Decoder_s *pbi,
6679 struct PIC_BUFFER_CONFIG_s *pic_config)
6680{
6681 struct vdec_s *vdec = hw_to_vdec(pbi);
6682 int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4;
6683 int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4;
6684 int blkmode = pbi->mem_map_mode;
6685 /*CANVAS_BLKMODE_64X32*/
6686 if (pic_config->double_write_mode) {
6687 canvas_w = pic_config->y_crop_width /
6688 get_double_write_ratio(pbi,
6689 pic_config->double_write_mode);
6690 canvas_h = pic_config->y_crop_height /
6691 get_double_write_ratio(pbi,
6692 pic_config->double_write_mode);
6693
6694 if (pbi->mem_map_mode == 0)
6695 canvas_w = ALIGN(canvas_w, 32);
6696 else
6697 canvas_w = ALIGN(canvas_w, 64);
6698 canvas_h = ALIGN(canvas_h, 32);
6699
6700 if (vdec->parallel_dec == 1) {
6701 if (pic_config->y_canvas_index == -1)
6702 pic_config->y_canvas_index =
6703 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6704 if (pic_config->uv_canvas_index == -1)
6705 pic_config->uv_canvas_index =
6706 vdec->get_canvas_ex(CORE_MASK_HEVC, vdec->id);
6707 } else {
6708 pic_config->y_canvas_index = 128 + pic_config->index * 2;
6709 pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1;
6710 }
6711
6712 canvas_config_ex(pic_config->y_canvas_index,
6713 pic_config->dw_y_adr, canvas_w, canvas_h,
6714 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6715 canvas_config_ex(pic_config->uv_canvas_index,
6716 pic_config->dw_u_v_adr, canvas_w, canvas_h,
6717 CANVAS_ADDR_NOWRAP, blkmode, pbi->is_used_v4l ? 0 : 7);
6718
6719#ifdef MULTI_INSTANCE_SUPPORT
6720 pic_config->canvas_config[0].phy_addr =
6721 pic_config->dw_y_adr;
6722 pic_config->canvas_config[0].width =
6723 canvas_w;
6724 pic_config->canvas_config[0].height =
6725 canvas_h;
6726 pic_config->canvas_config[0].block_mode =
6727 blkmode;
6728 pic_config->canvas_config[0].endian = pbi->is_used_v4l ? 0 : 7;
6729
6730 pic_config->canvas_config[1].phy_addr =
6731 pic_config->dw_u_v_adr;
6732 pic_config->canvas_config[1].width =
6733 canvas_w;
6734 pic_config->canvas_config[1].height =
6735 canvas_h;
6736 pic_config->canvas_config[1].block_mode =
6737 blkmode;
6738 pic_config->canvas_config[1].endian = pbi->is_used_v4l ? 0 : 7;
6739#endif
6740 }
6741}
6742
6743
6744static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf)
6745{
6746 unsigned int ar;
6747 vf->duration = pbi->frame_dur;
6748 vf->duration_pulldown = 0;
6749 vf->flag = 0;
6750 vf->prop.master_display_colour = pbi->vf_dp;
6751 vf->signal_type = pbi->video_signal_type;
6752 if (vf->compWidth && vf->compHeight)
6753 pbi->frame_ar = vf->compHeight * 0x100 / vf->compWidth;
6754 ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX);
6755 vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT);
6756
6757 if (pbi->is_used_v4l && pbi->vf_dp.present_flag) {
6758 struct aml_vdec_hdr_infos hdr;
6759 struct aml_vcodec_ctx *ctx =
6760 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
6761
6762 memset(&hdr, 0, sizeof(hdr));
6763 hdr.signal_type = vf->signal_type;
6764 hdr.color_parms = pbi->vf_dp;
6765 vdec_v4l_set_hdr_infos(ctx, &hdr);
6766 }
6767}
6768
6769static int vvp9_vf_states(struct vframe_states *states, void *op_arg)
6770{
6771 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6772
6773 states->vf_pool_size = VF_POOL_SIZE;
6774 states->buf_free_num = kfifo_len(&pbi->newframe_q);
6775 states->buf_avail_num = kfifo_len(&pbi->display_q);
6776
6777 if (step == 2)
6778 states->buf_avail_num = 0;
6779 return 0;
6780}
6781
6782static struct vframe_s *vvp9_vf_peek(void *op_arg)
6783{
6784 struct vframe_s *vf[2] = {0, 0};
6785 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6786
6787 if (step == 2)
6788 return NULL;
6789
6790 if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) {
6791 if (vf[1]) {
6792 vf[0]->next_vf_pts_valid = true;
6793 vf[0]->next_vf_pts = vf[1]->pts;
6794 } else
6795 vf[0]->next_vf_pts_valid = false;
6796 return vf[0];
6797 }
6798
6799 return NULL;
6800}
6801
6802static struct vframe_s *vvp9_vf_get(void *op_arg)
6803{
6804 struct vframe_s *vf;
6805 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6806
6807 if (step == 2)
6808 return NULL;
6809 else if (step == 1)
6810 step = 2;
6811
6812 if (kfifo_get(&pbi->display_q, &vf)) {
6813 struct vframe_s *next_vf;
6814 uint8_t index = vf->index & 0xff;
6815 if (index < pbi->used_buf_num ||
6816 (vf->type & VIDTYPE_V4L_EOS)) {
6817 pbi->vf_get_count++;
6818 if (debug & VP9_DEBUG_BUFMGR)
6819 pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n",
6820 __func__, vf->type,
6821 vf->width, vf->height,
6822 vf->pts,
6823 vf->pts_us64);
6824
6825 if (kfifo_peek(&pbi->display_q, &next_vf)) {
6826 vf->next_vf_pts_valid = true;
6827 vf->next_vf_pts = next_vf->pts;
6828 } else
6829 vf->next_vf_pts_valid = false;
6830
6831 return vf;
6832 }
6833 }
6834 return NULL;
6835}
6836
6837static void vvp9_vf_put(struct vframe_s *vf, void *op_arg)
6838{
6839 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg;
6840 uint8_t index = vf->index & 0xff;
6841
6842 if (vf == (&pbi->vframe_dummy))
6843 return;
6844
6845 kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf);
6846 pbi->vf_put_count++;
6847 if (index < pbi->used_buf_num) {
6848 struct VP9_Common_s *cm = &pbi->common;
6849 struct BufferPool_s *pool = cm->buffer_pool;
6850 unsigned long flags;
6851
6852 lock_buffer_pool(pool, flags);
6853 if (pool->frame_bufs[index].buf.vf_ref > 0)
6854 pool->frame_bufs[index].buf.vf_ref--;
6855
6856 if (pbi->is_used_v4l)
6857 pool->frame_bufs[index].buf.vframe_bound = true;
6858
6859 if (pbi->wait_buf)
6860 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG,
6861 0x1);
6862 pbi->last_put_idx = index;
6863 pbi->new_frame_displayed++;
6864 unlock_buffer_pool(pool, flags);
6865#ifdef SUPPORT_FB_DECODING
6866 if (pbi->used_stage_buf_num > 0 &&
6867 pbi->back_not_run_ready)
6868 trigger_schedule(pbi);
6869#endif
6870 }
6871
6872}
6873
6874static int vvp9_event_cb(int type, void *data, void *private_data)
6875{
6876 if (type & VFRAME_EVENT_RECEIVER_RESET) {
6877#if 0
6878 unsigned long flags;
6879
6880 amhevc_stop();
6881#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6882 vf_light_unreg_provider(&vvp9_vf_prov);
6883#endif
6884 spin_lock_irqsave(&pbi->lock, flags);
6885 vvp9_local_init();
6886 vvp9_prot_init();
6887 spin_unlock_irqrestore(&pbi->lock, flags);
6888#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER
6889 vf_reg_provider(&vvp9_vf_prov);
6890#endif
6891 amhevc_start();
6892#endif
6893 }
6894
6895 return 0;
6896}
6897
6898void inc_vf_ref(struct VP9Decoder_s *pbi, int index)
6899{
6900 struct VP9_Common_s *cm = &pbi->common;
6901
6902 cm->buffer_pool->frame_bufs[index].buf.vf_ref++;
6903
6904 if (debug & VP9_DEBUG_BUFMGR_MORE)
6905 pr_info("%s index = %d new vf_ref = %d\r\n",
6906 __func__, index,
6907 cm->buffer_pool->frame_bufs[index].buf.vf_ref);
6908}
6909
6910static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid)
6911{
6912 u32 old_duration, pts_duration = 0;
6913 u32 pts = vf->pts;
6914
6915 if (pbi->get_frame_dur == true)
6916 return true;
6917
6918 pbi->frame_cnt_window++;
6919 if (!(pbi->vp9_first_pts_ready == 1)) {
6920 if (valid) {
6921 pbi->pts1 = pts;
6922 pbi->frame_cnt_window = 0;
6923 pbi->duration_from_pts_done = 0;
6924 pbi->vp9_first_pts_ready = 1;
6925 } else {
6926 return false;
6927 }
6928 } else {
6929 if (pts < pbi->pts1) {
6930 if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) {
6931 pbi->pts1 = pts;
6932 pbi->frame_cnt_window = 0;
6933 }
6934 }
6935
6936 if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) &&
6937 (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) {
6938 old_duration = pbi->frame_dur;
6939 pbi->pts2 = pts;
6940 pts_duration = (((pbi->pts2 - pbi->pts1) * 16) /
6941 (pbi->frame_cnt_window * 15));
6942
6943 if (close_to(pts_duration, old_duration, 2000)) {
6944 pbi->frame_dur = pts_duration;
6945 if ((debug & VP9_DEBUG_OUT_PTS) != 0)
6946 pr_info("use calc duration %d\n", pts_duration);
6947 }
6948
6949 if (pbi->duration_from_pts_done == 0) {
6950 if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) {
6951 pbi->duration_from_pts_done = 1;
6952 } else {
6953 if (!close_to(pts_duration,
6954 old_duration, 1000) &&
6955 !close_to(pts_duration,
6956 pbi->frame_dur, 1000) &&
6957 close_to(pts_duration,
6958 pbi->last_duration, 200)) {
6959 /* frame_dur must
6960 * wrong,recover it.
6961 */
6962 pbi->frame_dur = pts_duration;
6963 }
6964 pbi->pts1 = pbi->pts2;
6965 pbi->frame_cnt_window = 0;
6966 pbi->duration_from_pts_done = 0;
6967 }
6968 }
6969 pbi->last_duration = pts_duration;
6970 }
6971 }
6972 return true;
6973}
6974
6975static void update_vf_memhandle(struct VP9Decoder_s *pbi,
6976 struct vframe_s *vf, struct PIC_BUFFER_CONFIG_s *pic)
6977{
6978 if (pic->index < 0) {
6979 vf->mem_handle = NULL;
6980 vf->mem_head_handle = NULL;
6981 } else if (vf->type & VIDTYPE_SCATTER) {
6982 vf->mem_handle =
6983 decoder_mmu_box_get_mem_handle(
6984 pbi->mmu_box, pic->index);
6985 vf->mem_head_handle =
6986 decoder_bmmu_box_get_mem_handle(
6987 pbi->bmmu_box,
6988 HEADER_BUFFER_IDX(pic->BUF_index));
6989 } else {
6990 vf->mem_handle =
6991 decoder_bmmu_box_get_mem_handle(
6992 pbi->bmmu_box, VF_BUFFER_IDX(pic->BUF_index));
6993 vf->mem_head_handle = NULL;
6994 /*vf->mem_head_handle =
6995 *decoder_bmmu_box_get_mem_handle(
6996 *hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));
6997 */
6998 }
6999}
7000
7001static int prepare_display_buf(struct VP9Decoder_s *pbi,
7002 struct PIC_BUFFER_CONFIG_s *pic_config)
7003{
7004 struct vframe_s *vf = NULL;
7005 int stream_offset = pic_config->stream_offset;
7006 unsigned short slice_type = pic_config->slice_type;
7007 u32 pts_valid = 0, pts_us64_valid = 0;
7008 u32 pts_save;
7009 u64 pts_us64_save;
7010 u32 frame_size;
7011
7012 if (debug & VP9_DEBUG_BUFMGR)
7013 pr_info("%s index = %d\r\n", __func__, pic_config->index);
7014 if (kfifo_get(&pbi->newframe_q, &vf) == 0) {
7015 pr_info("fatal error, no available buffer slot.");
7016 return -1;
7017 }
7018
7019 if (pic_config->double_write_mode)
7020 set_canvas(pbi, pic_config);
7021
7022 display_frame_count[pbi->index]++;
7023 if (vf) {
7024 if (pbi->is_used_v4l) {
7025 vf->v4l_mem_handle
7026 = pbi->m_BUF[pic_config->BUF_index].v4l_ref_buf_addr;
7027 if (pbi->mmu_enable) {
7028 vf->mm_box.bmmu_box = pbi->bmmu_box;
7029 vf->mm_box.bmmu_idx = HEADER_BUFFER_IDX(pic_config->BUF_index);
7030 vf->mm_box.mmu_box = pbi->mmu_box;
7031 vf->mm_box.mmu_idx = pic_config->index;
7032 }
7033 }
7034
7035#ifdef MULTI_INSTANCE_SUPPORT
7036 if (vdec_frame_based(hw_to_vdec(pbi))) {
7037 vf->pts = pic_config->pts;
7038 vf->pts_us64 = pic_config->pts64;
7039 vf->timestamp = pic_config->timestamp;
7040 if (vf->pts != 0 || vf->pts_us64 != 0) {
7041 pts_valid = 1;
7042 pts_us64_valid = 1;
7043 } else {
7044 pts_valid = 0;
7045 pts_us64_valid = 0;
7046 }
7047 } else
7048#endif
7049 /* if (pts_lookup_offset(PTS_TYPE_VIDEO,
7050 * stream_offset, &vf->pts, 0) != 0) {
7051 */
7052 if (pts_lookup_offset_us64
7053 (PTS_TYPE_VIDEO, stream_offset, &vf->pts,
7054 &frame_size, 0,
7055 &vf->pts_us64) != 0) {
7056#ifdef DEBUG_PTS
7057 pbi->pts_missed++;
7058#endif
7059 vf->pts = 0;
7060 vf->pts_us64 = 0;
7061 pts_valid = 0;
7062 pts_us64_valid = 0;
7063 } else {
7064#ifdef DEBUG_PTS
7065 pbi->pts_hit++;
7066#endif
7067 pts_valid = 1;
7068 pts_us64_valid = 1;
7069 }
7070
7071 fill_frame_info(pbi, pic_config, frame_size, vf->pts);
7072
7073 pts_save = vf->pts;
7074 pts_us64_save = vf->pts_us64;
7075 if (pbi->pts_unstable) {
7076 frame_duration_adapt(pbi, vf, pts_valid);
7077 if (pbi->duration_from_pts_done) {
7078 pbi->pts_mode = PTS_NONE_REF_USE_DURATION;
7079 } else {
7080 if (pts_valid || pts_us64_valid)
7081 pbi->pts_mode = PTS_NORMAL;
7082 }
7083 }
7084
7085 if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0)
7086 && pbi->get_frame_dur) {
7087 int pts_diff = (int)vf->pts - pbi->last_lookup_pts;
7088
7089 if (pts_diff < 0) {
7090 pbi->pts_mode_switching_count++;
7091 pbi->pts_mode_recovery_count = 0;
7092
7093 if (pbi->pts_mode_switching_count >=
7094 PTS_MODE_SWITCHING_THRESHOLD) {
7095 pbi->pts_mode =
7096 PTS_NONE_REF_USE_DURATION;
7097 pr_info
7098 ("HEVC: switch to n_d mode.\n");
7099 }
7100
7101 } else {
7102 int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD;
7103
7104 pbi->pts_mode_recovery_count++;
7105 if (pbi->pts_mode_recovery_count > p) {
7106 pbi->pts_mode_switching_count = 0;
7107 pbi->pts_mode_recovery_count = 0;
7108 }
7109 }
7110 }
7111
7112 if (vf->pts != 0)
7113 pbi->last_lookup_pts = vf->pts;
7114
7115 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7116 && (slice_type != KEY_FRAME))
7117 vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur);
7118 pbi->last_pts = vf->pts;
7119
7120 if (vf->pts_us64 != 0)
7121 pbi->last_lookup_pts_us64 = vf->pts_us64;
7122
7123 if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION)
7124 && (slice_type != KEY_FRAME)) {
7125 vf->pts_us64 =
7126 pbi->last_pts_us64 +
7127 (DUR2PTS(pbi->frame_dur) * 100 / 9);
7128 }
7129 pbi->last_pts_us64 = vf->pts_us64;
7130 if ((debug & VP9_DEBUG_OUT_PTS) != 0) {
7131 pr_info
7132 ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n",
7133 pbi->pts_mode, pbi->frame_dur, vf->pts,
7134 vf->pts_us64, pts_save, pts_us64_save);
7135 }
7136
7137 if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) {
7138 vf->disp_pts = vf->pts;
7139 vf->disp_pts_us64 = vf->pts_us64;
7140 vf->pts = pts_save;
7141 vf->pts_us64 = pts_us64_save;
7142 } else {
7143 vf->disp_pts = 0;
7144 vf->disp_pts_us64 = 0;
7145 }
7146
7147 vf->index = 0xff00 | pic_config->index;
7148
7149 if (pic_config->double_write_mode & 0x10) {
7150 /* double write only */
7151 vf->compBodyAddr = 0;
7152 vf->compHeadAddr = 0;
7153 } else {
7154 if (pbi->mmu_enable) {
7155 vf->compBodyAddr = 0;
7156 vf->compHeadAddr = pic_config->header_adr;
7157 } else {
7158 /*vf->compBodyAddr = pic_config->mc_y_adr;
7159 *vf->compHeadAddr = pic_config->mc_y_adr +
7160 *pic_config->comp_body_size; */
7161 /*head adr*/
7162 }
7163 vf->canvas0Addr = vf->canvas1Addr = 0;
7164 }
7165 if (pic_config->double_write_mode) {
7166 vf->type = VIDTYPE_PROGRESSIVE |
7167 VIDTYPE_VIU_FIELD;
7168 vf->type |= VIDTYPE_VIU_NV21;
7169 if ((pic_config->double_write_mode == 3) &&
7170 (!IS_8K_SIZE(pic_config->y_crop_width,
7171 pic_config->y_crop_height))) {
7172 vf->type |= VIDTYPE_COMPRESS;
7173 if (pbi->mmu_enable)
7174 vf->type |= VIDTYPE_SCATTER;
7175 }
7176#ifdef MULTI_INSTANCE_SUPPORT
7177 if (pbi->m_ins_flag) {
7178 vf->canvas0Addr = vf->canvas1Addr = -1;
7179 vf->plane_num = 2;
7180 vf->canvas0_config[0] =
7181 pic_config->canvas_config[0];
7182 vf->canvas0_config[1] =
7183 pic_config->canvas_config[1];
7184 vf->canvas1_config[0] =
7185 pic_config->canvas_config[0];
7186 vf->canvas1_config[1] =
7187 pic_config->canvas_config[1];
7188
7189 } else
7190#endif
7191 vf->canvas0Addr = vf->canvas1Addr =
7192 spec2canvas(pic_config);
7193 } else {
7194 vf->canvas0Addr = vf->canvas1Addr = 0;
7195 vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD;
7196 if (pbi->mmu_enable)
7197 vf->type |= VIDTYPE_SCATTER;
7198 }
7199
7200 switch (pic_config->bit_depth) {
7201 case VPX_BITS_8:
7202 vf->bitdepth = BITDEPTH_Y8 |
7203 BITDEPTH_U8 | BITDEPTH_V8;
7204 break;
7205 case VPX_BITS_10:
7206 case VPX_BITS_12:
7207 vf->bitdepth = BITDEPTH_Y10 |
7208 BITDEPTH_U10 | BITDEPTH_V10;
7209 break;
7210 default:
7211 vf->bitdepth = BITDEPTH_Y10 |
7212 BITDEPTH_U10 | BITDEPTH_V10;
7213 break;
7214 }
7215 if ((vf->type & VIDTYPE_COMPRESS) == 0)
7216 vf->bitdepth =
7217 BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8;
7218 if (pic_config->bit_depth == VPX_BITS_8)
7219 vf->bitdepth |= BITDEPTH_SAVING_MODE;
7220
7221 /* if((vf->width!=pic_config->width)|
7222 * (vf->height!=pic_config->height))
7223 */
7224 /* pr_info("aaa: %d/%d, %d/%d\n",
7225 vf->width,vf->height, pic_config->width,
7226 pic_config->height); */
7227 vf->width = pic_config->y_crop_width /
7228 get_double_write_ratio(pbi,
7229 pic_config->double_write_mode);
7230 vf->height = pic_config->y_crop_height /
7231 get_double_write_ratio(pbi,
7232 pic_config->double_write_mode);
7233 if (force_w_h != 0) {
7234 vf->width = (force_w_h >> 16) & 0xffff;
7235 vf->height = force_w_h & 0xffff;
7236 }
7237 vf->compWidth = pic_config->y_crop_width;
7238 vf->compHeight = pic_config->y_crop_height;
7239 set_frame_info(pbi, vf);
7240 if (force_fps & 0x100) {
7241 u32 rate = force_fps & 0xff;
7242
7243 if (rate)
7244 vf->duration = 96000/rate;
7245 else
7246 vf->duration = 0;
7247 }
7248 update_vf_memhandle(pbi, vf, pic_config);
7249 if (!(pic_config->y_crop_width == 196
7250 && pic_config->y_crop_height == 196
7251 && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0
7252 && (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX))) {
7253 inc_vf_ref(pbi, pic_config->index);
7254 decoder_do_frame_check(hw_to_vdec(pbi), vf);
7255 kfifo_put(&pbi->display_q, (const struct vframe_s *)vf);
7256 ATRACE_COUNTER(MODULE_NAME, vf->pts);
7257 pbi->vf_pre_count++;
7258#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
7259 /*count info*/
7260 gvs->frame_dur = pbi->frame_dur;
7261 vdec_count_info(gvs, 0, stream_offset);
7262#endif
7263 hw_to_vdec(pbi)->vdec_fps_detec(hw_to_vdec(pbi)->id);
7264 if (without_display_mode == 0) {
7265 vf_notify_receiver(pbi->provider_name,
7266 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7267 } else
7268 vvp9_vf_put(vvp9_vf_get(pbi), pbi);
7269 } else {
7270 pbi->stat |= VP9_TRIGGER_FRAME_DONE;
7271 hevc_source_changed(VFORMAT_VP9, 196, 196, 30);
7272 pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n",
7273 __func__, __LINE__, vf->width,
7274 vf->height, pbi->stat);
7275 }
7276 }
7277
7278 return 0;
7279}
7280
7281static int notify_v4l_eos(struct vdec_s *vdec)
7282{
7283 struct VP9Decoder_s *hw = (struct VP9Decoder_s *)vdec->private;
7284 struct aml_vcodec_ctx *ctx = (struct aml_vcodec_ctx *)(hw->v4l2_ctx);
7285 struct vframe_s *vf = &hw->vframe_dummy;
7286 struct vdec_v4l2_buffer *fb = NULL;
7287 int index = INVALID_IDX;
7288 ulong expires;
7289
7290 if (hw->is_used_v4l && hw->eos) {
7291 expires = jiffies + msecs_to_jiffies(2000);
7292 while (INVALID_IDX == (index = get_free_fb(hw))) {
7293 if (time_after(jiffies, expires))
7294 break;
7295 }
7296
7297 if (index == INVALID_IDX) {
7298 if (vdec_v4l_get_buffer(hw->v4l2_ctx, &fb) < 0) {
7299 pr_err("[%d] EOS get free buff fail.\n", ctx->id);
7300 return -1;
7301 }
7302 }
7303
7304 vf->type |= VIDTYPE_V4L_EOS;
7305 vf->timestamp = ULONG_MAX;
7306 vf->flag = VFRAME_FLAG_EMPTY_FRAME_V4L;
7307 vf->v4l_mem_handle = (index == INVALID_IDX) ? (ulong)fb :
7308 hw->m_BUF[index].v4l_ref_buf_addr;
7309
7310 kfifo_put(&hw->display_q, (const struct vframe_s *)vf);
7311 vf_notify_receiver(vdec->vf_provider_name,
7312 VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL);
7313
7314 pr_info("[%d] VP9 EOS notify.\n", ctx->id);
7315 }
7316
7317 return 0;
7318}
7319
7320static void get_rpm_param(union param_u *params)
7321{
7322 int i;
7323 unsigned int data32;
7324
7325 if (debug & VP9_DEBUG_BUFMGR)
7326 pr_info("enter %s\r\n", __func__);
7327 for (i = 0; i < 128; i++) {
7328 do {
7329 data32 = READ_VREG(RPM_CMD_REG);
7330 /*pr_info("%x\n", data32);*/
7331 } while ((data32 & 0x10000) == 0);
7332 params->l.data[i] = data32&0xffff;
7333 /*pr_info("%x\n", data32);*/
7334 WRITE_VREG(RPM_CMD_REG, 0);
7335 }
7336 if (debug & VP9_DEBUG_BUFMGR)
7337 pr_info("leave %s\r\n", __func__);
7338}
7339static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi)
7340{
7341 int i;
7342
7343 if (!(debug & VP9_DEBUG_BUFMGR_MORE))
7344 return;
7345 pr_info("vp9_param: (%d)\n", pbi->slice_idx);
7346 for (i = 0; i < (RPM_END-RPM_BEGIN); i++) {
7347 pr_info("%04x ", vp9_param.l.data[i]);
7348 if (((i + 1) & 0xf) == 0)
7349 pr_info("\n");
7350 }
7351 pr_info("=============param==========\r\n");
7352 pr_info("profile %x\r\n", vp9_param.p.profile);
7353 pr_info("show_existing_frame %x\r\n",
7354 vp9_param.p.show_existing_frame);
7355 pr_info("frame_to_show_idx %x\r\n",
7356 vp9_param.p.frame_to_show_idx);
7357 pr_info("frame_type %x\r\n", vp9_param.p.frame_type);
7358 pr_info("show_frame %x\r\n", vp9_param.p.show_frame);
7359 pr_info("e.r.r.o.r_resilient_mode %x\r\n",
7360 vp9_param.p.error_resilient_mode);
7361 pr_info("intra_only %x\r\n", vp9_param.p.intra_only);
7362 pr_info("display_size_present %x\r\n",
7363 vp9_param.p.display_size_present);
7364 pr_info("reset_frame_context %x\r\n",
7365 vp9_param.p.reset_frame_context);
7366 pr_info("refresh_frame_flags %x\r\n",
7367 vp9_param.p.refresh_frame_flags);
7368 pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth);
7369 pr_info("width %x\r\n", vp9_param.p.width);
7370 pr_info("height %x\r\n", vp9_param.p.height);
7371 pr_info("display_width %x\r\n", vp9_param.p.display_width);
7372 pr_info("display_height %x\r\n", vp9_param.p.display_height);
7373 pr_info("ref_info %x\r\n", vp9_param.p.ref_info);
7374 pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size);
7375 if (!(debug & VP9_DEBUG_DBG_LF_PRINT))
7376 return;
7377 pr_info("mode_ref_delta_enabled: 0x%x\r\n",
7378 vp9_param.p.mode_ref_delta_enabled);
7379 pr_info("sharpness_level: 0x%x\r\n",
7380 vp9_param.p.sharpness_level);
7381 pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n",
7382 vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1],
7383 vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]);
7384 pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0],
7385 vp9_param.p.mode_deltas[1]);
7386 pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level);
7387 pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled);
7388 pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta);
7389 pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7390 (vp9_param.p.seg_lf_info[0]>>15 & 1),
7391 (vp9_param.p.seg_lf_info[1]>>15 & 1),
7392 (vp9_param.p.seg_lf_info[2]>>15 & 1),
7393 (vp9_param.p.seg_lf_info[3]>>15 & 1),
7394 (vp9_param.p.seg_lf_info[4]>>15 & 1),
7395 (vp9_param.p.seg_lf_info[5]>>15 & 1),
7396 (vp9_param.p.seg_lf_info[6]>>15 & 1),
7397 (vp9_param.p.seg_lf_info[7]>>15 & 1));
7398 pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n",
7399 (vp9_param.p.seg_lf_info[0] & 0x13f),
7400 (vp9_param.p.seg_lf_info[1] & 0x13f),
7401 (vp9_param.p.seg_lf_info[2] & 0x13f),
7402 (vp9_param.p.seg_lf_info[3] & 0x13f),
7403 (vp9_param.p.seg_lf_info[4] & 0x13f),
7404 (vp9_param.p.seg_lf_info[5] & 0x13f),
7405 (vp9_param.p.seg_lf_info[6] & 0x13f),
7406 (vp9_param.p.seg_lf_info[7] & 0x13f));
7407
7408}
7409
7410
7411static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi)
7412{
7413 struct VP9_Common_s *const cm = &pbi->common;
7414 if (pbi->double_write_mode & 0x10)
7415 return;
7416 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7417 if (pbi->used_4k_num == -1) {
7418 pbi->used_4k_num =
7419 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
7420 if (pbi->m_ins_flag)
7421 hevc_mmu_dma_check(hw_to_vdec(pbi));
7422 }
7423 decoder_mmu_box_free_idx_tail(pbi->mmu_box,
7424 cm->cur_fb_idx_mmu, pbi->used_4k_num);
7425 cm->cur_fb_idx_mmu = INVALID_IDX;
7426 pbi->used_4k_num = -1;
7427 }
7428}
7429
7430#ifdef MULTI_INSTANCE_SUPPORT
7431static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi)
7432{
7433 struct VP9_Common_s *const cm = &pbi->common;
7434 if (pbi->double_write_mode & 0x10)
7435 return;
7436 if (cm->cur_fb_idx_mmu != INVALID_IDX) {
7437 decoder_mmu_box_free_idx(pbi->mmu_box,
7438 cm->cur_fb_idx_mmu);
7439
7440 cm->cur_fb_idx_mmu = INVALID_IDX;
7441 pbi->used_4k_num = -1;
7442 }
7443}
7444#endif
7445
7446
7447static void dec_again_process(struct VP9Decoder_s *pbi)
7448{
7449 amhevc_stop();
7450 pbi->dec_result = DEC_RESULT_AGAIN;
7451 if (pbi->process_state ==
7452 PROC_STATE_DECODESLICE) {
7453 pbi->process_state =
7454 PROC_STATE_SENDAGAIN;
7455 if (pbi->mmu_enable)
7456 vp9_recycle_mmu_buf(pbi);
7457 }
7458 reset_process_time(pbi);
7459 vdec_schedule_work(&pbi->work);
7460}
7461
7462int continue_decoding(struct VP9Decoder_s *pbi)
7463{
7464 int ret;
7465 int i;
7466 struct VP9_Common_s *const cm = &pbi->common;
7467 debug_buffer_mgr_more(pbi);
7468
7469 bit_depth_luma = vp9_param.p.bit_depth;
7470 bit_depth_chroma = vp9_param.p.bit_depth;
7471
7472 if ((vp9_param.p.bit_depth >= VPX_BITS_10) &&
7473 (get_double_write_mode(pbi) == 0x10)) {
7474 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
7475 pr_err("fatal err, bit_depth %d, unsupport dw 0x10\n",
7476 vp9_param.p.bit_depth);
7477 return -1;
7478 }
7479
7480 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7481 ret = vp9_bufmgr_process(pbi, &vp9_param);
7482 if (!pbi->m_ins_flag)
7483 pbi->slice_idx++;
7484 } else {
7485 union param_u *params = &vp9_param;
7486 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7487 ret = vp9_alloc_mmu(pbi,
7488 cm->new_fb_idx,
7489 params->p.width,
7490 params->p.height,
7491 params->p.bit_depth,
7492 pbi->frame_mmu_map_addr);
7493 if (ret >= 0)
7494 cm->cur_fb_idx_mmu = cm->new_fb_idx;
7495 else
7496 pr_err("can't alloc need mmu1,idx %d ret =%d\n",
7497 cm->new_fb_idx,
7498 ret);
7499 } else {
7500 ret = 0;
7501 }
7502 WRITE_VREG(HEVC_PARSER_PICTURE_SIZE,
7503 (params->p.height << 16) | params->p.width);
7504 }
7505 if (ret < 0) {
7506 pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n",
7507 ret);
7508 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
7509 cm->show_frame = 0;
7510 if (pbi->mmu_enable)
7511 vp9_recycle_mmu_buf(pbi);
7512#ifdef MULTI_INSTANCE_SUPPORT
7513 if (pbi->m_ins_flag) {
7514 pbi->dec_result = DEC_RESULT_DONE;
7515#ifdef SUPPORT_FB_DECODING
7516 if (pbi->used_stage_buf_num == 0)
7517#endif
7518 amhevc_stop();
7519 vdec_schedule_work(&pbi->work);
7520 }
7521#endif
7522 return ret;
7523 } else if (ret == 0) {
7524 struct PIC_BUFFER_CONFIG_s *cur_pic_config
7525 = &cm->cur_frame->buf;
7526 cur_pic_config->decode_idx = pbi->frame_count;
7527
7528 if (pbi->process_state != PROC_STATE_SENDAGAIN) {
7529 if (!pbi->m_ins_flag) {
7530 pbi->frame_count++;
7531 decode_frame_count[pbi->index]
7532 = pbi->frame_count;
7533 }
7534#ifdef MULTI_INSTANCE_SUPPORT
7535 if (pbi->chunk) {
7536 cur_pic_config->pts = pbi->chunk->pts;
7537 cur_pic_config->pts64 = pbi->chunk->pts64;
7538 cur_pic_config->timestamp = pbi->chunk->timestamp;
7539 }
7540#endif
7541 }
7542 /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/
7543 config_pic_size(pbi, vp9_param.p.bit_depth);
7544
7545 if ((pbi->common.frame_type != KEY_FRAME)
7546 && (!pbi->common.intra_only)) {
7547 config_mc_buffer(pbi, vp9_param.p.bit_depth);
7548#ifdef SUPPORT_FB_DECODING
7549 if (pbi->used_stage_buf_num == 0)
7550#endif
7551 config_mpred_hw(pbi);
7552 } else {
7553#ifdef SUPPORT_FB_DECODING
7554 if (pbi->used_stage_buf_num == 0)
7555#endif
7556 clear_mpred_hw(pbi);
7557 }
7558#ifdef MCRCC_ENABLE
7559 if (mcrcc_cache_alg_flag)
7560 config_mcrcc_axi_hw_new(pbi);
7561 else
7562 config_mcrcc_axi_hw(pbi);
7563#endif
7564 config_sao_hw(pbi, &vp9_param);
7565
7566#ifdef VP9_LPF_LVL_UPDATE
7567 /*
7568 * Get loop filter related picture level parameters from Parser
7569 */
7570 pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled;
7571 pbi->lf->sharpness_level = vp9_param.p.sharpness_level;
7572 for (i = 0; i < 4; i++)
7573 pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i];
7574 for (i = 0; i < 2; i++)
7575 pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i];
7576 pbi->default_filt_lvl = vp9_param.p.filter_level;
7577 pbi->seg_4lf->enabled = vp9_param.p.seg_enabled;
7578 pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta;
7579 for (i = 0; i < MAX_SEGMENTS; i++)
7580 pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] &
7581 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0;
7582 for (i = 0; i < MAX_SEGMENTS; i++)
7583 pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF]
7584 = (vp9_param.p.seg_lf_info[i]
7585 & 0x100) ? -(vp9_param.p.seg_lf_info[i]
7586 & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f);
7587 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
7588 /*Set pipeline mode*/
7589 uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB);
7590 /*dblk pipeline mode=1 for performance*/
7591 if (vp9_param.p.width >= 1280)
7592 lpf_data32 |= (0x1 << 4);
7593 else
7594 lpf_data32 &= ~(0x3 << 4);
7595 WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32);
7596 }
7597 /*
7598 * Update loop filter Thr/Lvl table for every frame
7599 */
7600 /*pr_info
7601 ("vp9_loop_filter (run before every frame decoding start)\n");*/
7602 vp9_loop_filter_frame_init(pbi->seg_4lf,
7603 pbi->lfi, pbi->lf, pbi->default_filt_lvl);
7604#endif
7605 /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/
7606 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7607 } else {
7608 pr_info("Skip search next start code\n");
7609 cm->prev_fb_idx = INVALID_IDX;
7610 /*skip, search next start code*/
7611 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
7612 }
7613 pbi->process_state = PROC_STATE_DECODESLICE;
7614 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
7615 if (pbi->last_put_idx < pbi->used_buf_num) {
7616 struct RefCntBuffer_s *frame_bufs =
7617 cm->buffer_pool->frame_bufs;
7618 int i = pbi->last_put_idx;
7619 /*free not used buffers.*/
7620 if ((frame_bufs[i].ref_count == 0) &&
7621 (frame_bufs[i].buf.vf_ref == 0) &&
7622 (frame_bufs[i].buf.index != -1)) {
7623 decoder_mmu_box_free_idx(pbi->mmu_box, i);
7624 }
7625 pbi->last_put_idx = -1;
7626 }
7627 }
7628 return ret;
7629}
7630
7631static void fill_frame_info(struct VP9Decoder_s *pbi,
7632 struct PIC_BUFFER_CONFIG_s *frame,
7633 unsigned int framesize,
7634 unsigned int pts)
7635{
7636 struct vframe_qos_s *vframe_qos = &pbi->vframe_qos;
7637
7638 if (frame->slice_type == KEY_FRAME)
7639 vframe_qos->type = 1;
7640 else if (frame->slice_type == INTER_FRAME)
7641 vframe_qos->type = 2;
7642/*
7643#define SHOW_QOS_INFO
7644*/
7645 vframe_qos->size = framesize;
7646 vframe_qos->pts = pts;
7647#ifdef SHOW_QOS_INFO
7648 vp9_print(pbi, 0, "slice:%d\n", frame->slice_type);
7649#endif
7650 vframe_qos->max_mv = frame->max_mv;
7651 vframe_qos->avg_mv = frame->avg_mv;
7652 vframe_qos->min_mv = frame->min_mv;
7653#ifdef SHOW_QOS_INFO
7654 vp9_print(pbi, 0, "mv: max:%d, avg:%d, min:%d\n",
7655 vframe_qos->max_mv,
7656 vframe_qos->avg_mv,
7657 vframe_qos->min_mv);
7658#endif
7659 vframe_qos->max_qp = frame->max_qp;
7660 vframe_qos->avg_qp = frame->avg_qp;
7661 vframe_qos->min_qp = frame->min_qp;
7662#ifdef SHOW_QOS_INFO
7663 vp9_print(pbi, 0, "qp: max:%d, avg:%d, min:%d\n",
7664 vframe_qos->max_qp,
7665 vframe_qos->avg_qp,
7666 vframe_qos->min_qp);
7667#endif
7668 vframe_qos->max_skip = frame->max_skip;
7669 vframe_qos->avg_skip = frame->avg_skip;
7670 vframe_qos->min_skip = frame->min_skip;
7671#ifdef SHOW_QOS_INFO
7672 vp9_print(pbi, 0, "skip: max:%d, avg:%d, min:%d\n",
7673 vframe_qos->max_skip,
7674 vframe_qos->avg_skip,
7675 vframe_qos->min_skip);
7676#endif
7677 vframe_qos->num++;
7678
7679 if (pbi->frameinfo_enable)
7680 vdec_fill_frame_info(vframe_qos, 1);
7681}
7682
7683/* only when we decoded one field or one frame,
7684we can call this function to get qos info*/
7685static void get_picture_qos_info(struct VP9Decoder_s *pbi)
7686{
7687 struct PIC_BUFFER_CONFIG_s *frame = &pbi->cur_buf->buf;
7688
7689 if (!frame)
7690 return;
7691
7692 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
7693 unsigned char a[3];
7694 unsigned char i, j, t;
7695 unsigned long data;
7696
7697 data = READ_VREG(HEVC_MV_INFO);
7698 if (frame->slice_type == KEY_FRAME)
7699 data = 0;
7700 a[0] = data & 0xff;
7701 a[1] = (data >> 8) & 0xff;
7702 a[2] = (data >> 16) & 0xff;
7703
7704 for (i = 0; i < 3; i++) {
7705 for (j = i+1; j < 3; j++) {
7706 if (a[j] < a[i]) {
7707 t = a[j];
7708 a[j] = a[i];
7709 a[i] = t;
7710 } else if (a[j] == a[i]) {
7711 a[i]++;
7712 t = a[j];
7713 a[j] = a[i];
7714 a[i] = t;
7715 }
7716 }
7717 }
7718 frame->max_mv = a[2];
7719 frame->avg_mv = a[1];
7720 frame->min_mv = a[0];
7721
7722 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7723 "mv data %x a[0]= %x a[1]= %x a[2]= %x\n",
7724 data, a[0], a[1], a[2]);
7725
7726 data = READ_VREG(HEVC_QP_INFO);
7727 a[0] = data & 0x1f;
7728 a[1] = (data >> 8) & 0x3f;
7729 a[2] = (data >> 16) & 0x7f;
7730
7731 for (i = 0; i < 3; i++) {
7732 for (j = i+1; j < 3; j++) {
7733 if (a[j] < a[i]) {
7734 t = a[j];
7735 a[j] = a[i];
7736 a[i] = t;
7737 } else if (a[j] == a[i]) {
7738 a[i]++;
7739 t = a[j];
7740 a[j] = a[i];
7741 a[i] = t;
7742 }
7743 }
7744 }
7745 frame->max_qp = a[2];
7746 frame->avg_qp = a[1];
7747 frame->min_qp = a[0];
7748
7749 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7750 "qp data %x a[0]= %x a[1]= %x a[2]= %x\n",
7751 data, a[0], a[1], a[2]);
7752
7753 data = READ_VREG(HEVC_SKIP_INFO);
7754 a[0] = data & 0x1f;
7755 a[1] = (data >> 8) & 0x3f;
7756 a[2] = (data >> 16) & 0x7f;
7757
7758 for (i = 0; i < 3; i++) {
7759 for (j = i+1; j < 3; j++) {
7760 if (a[j] < a[i]) {
7761 t = a[j];
7762 a[j] = a[i];
7763 a[i] = t;
7764 } else if (a[j] == a[i]) {
7765 a[i]++;
7766 t = a[j];
7767 a[j] = a[i];
7768 a[i] = t;
7769 }
7770 }
7771 }
7772 frame->max_skip = a[2];
7773 frame->avg_skip = a[1];
7774 frame->min_skip = a[0];
7775
7776 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7777 "skip data %x a[0]= %x a[1]= %x a[2]= %x\n",
7778 data, a[0], a[1], a[2]);
7779 } else {
7780 uint32_t blk88_y_count;
7781 uint32_t blk88_c_count;
7782 uint32_t blk22_mv_count;
7783 uint32_t rdata32;
7784 int32_t mv_hi;
7785 int32_t mv_lo;
7786 uint32_t rdata32_l;
7787 uint32_t mvx_L0_hi;
7788 uint32_t mvy_L0_hi;
7789 uint32_t mvx_L1_hi;
7790 uint32_t mvy_L1_hi;
7791 int64_t value;
7792 uint64_t temp_value;
7793 int pic_number = frame->decode_idx;
7794
7795 frame->max_mv = 0;
7796 frame->avg_mv = 0;
7797 frame->min_mv = 0;
7798
7799 frame->max_skip = 0;
7800 frame->avg_skip = 0;
7801 frame->min_skip = 0;
7802
7803 frame->max_qp = 0;
7804 frame->avg_qp = 0;
7805 frame->min_qp = 0;
7806
7807 vp9_print(pbi, VP9_DEBUG_QOS_INFO, "slice_type:%d, poc:%d\n",
7808 frame->slice_type,
7809 pic_number);
7810
7811 /* set rd_idx to 0 */
7812 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, 0);
7813
7814 blk88_y_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7815 if (blk88_y_count == 0) {
7816
7817 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7818 "[Picture %d Quality] NO Data yet.\n",
7819 pic_number);
7820
7821 /* reset all counts */
7822 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7823 return;
7824 }
7825 /* qp_y_sum */
7826 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7827
7828 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7829 "[Picture %d Quality] Y QP AVG : %d (%d/%d)\n",
7830 pic_number, rdata32/blk88_y_count,
7831 rdata32, blk88_y_count);
7832
7833 frame->avg_qp = rdata32/blk88_y_count;
7834 /* intra_y_count */
7835 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7836
7837 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7838 "[Picture %d Quality] Y intra rate : %d%c (%d)\n",
7839 pic_number, rdata32*100/blk88_y_count,
7840 '%', rdata32);
7841
7842 /* skipped_y_count */
7843 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7844
7845 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7846 "[Picture %d Quality] Y skipped rate : %d%c (%d)\n",
7847 pic_number, rdata32*100/blk88_y_count,
7848 '%', rdata32);
7849
7850 frame->avg_skip = rdata32*100/blk88_y_count;
7851 /* coeff_non_zero_y_count */
7852 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7853
7854 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7855 "[Picture %d Quality] Y ZERO_Coeff rate : %d%c (%d)\n",
7856 pic_number, (100 - rdata32*100/(blk88_y_count*1)),
7857 '%', rdata32);
7858
7859 /* blk66_c_count */
7860 blk88_c_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7861 if (blk88_c_count == 0) {
7862 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7863 "[Picture %d Quality] NO Data yet.\n",
7864 pic_number);
7865 /* reset all counts */
7866 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7867 return;
7868 }
7869 /* qp_c_sum */
7870 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7871
7872 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7873 "[Picture %d Quality] C QP AVG : %d (%d/%d)\n",
7874 pic_number, rdata32/blk88_c_count,
7875 rdata32, blk88_c_count);
7876
7877 /* intra_c_count */
7878 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7879
7880 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7881 "[Picture %d Quality] C intra rate : %d%c (%d)\n",
7882 pic_number, rdata32*100/blk88_c_count,
7883 '%', rdata32);
7884
7885 /* skipped_cu_c_count */
7886 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7887
7888 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7889 "[Picture %d Quality] C skipped rate : %d%c (%d)\n",
7890 pic_number, rdata32*100/blk88_c_count,
7891 '%', rdata32);
7892
7893 /* coeff_non_zero_c_count */
7894 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7895
7896 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7897 "[Picture %d Quality] C ZERO_Coeff rate : %d%c (%d)\n",
7898 pic_number, (100 - rdata32*100/(blk88_c_count*1)),
7899 '%', rdata32);
7900
7901 /* 1'h0, qp_c_max[6:0], 1'h0, qp_c_min[6:0],
7902 1'h0, qp_y_max[6:0], 1'h0, qp_y_min[6:0] */
7903 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7904
7905 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7906 "[Picture %d Quality] Y QP min : %d\n",
7907 pic_number, (rdata32>>0)&0xff);
7908
7909 frame->min_qp = (rdata32>>0)&0xff;
7910
7911 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7912 "[Picture %d Quality] Y QP max : %d\n",
7913 pic_number, (rdata32>>8)&0xff);
7914
7915 frame->max_qp = (rdata32>>8)&0xff;
7916
7917 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7918 "[Picture %d Quality] C QP min : %d\n",
7919 pic_number, (rdata32>>16)&0xff);
7920 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7921 "[Picture %d Quality] C QP max : %d\n",
7922 pic_number, (rdata32>>24)&0xff);
7923
7924 /* blk22_mv_count */
7925 blk22_mv_count = READ_VREG(HEVC_PIC_QUALITY_DATA);
7926 if (blk22_mv_count == 0) {
7927 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7928 "[Picture %d Quality] NO MV Data yet.\n",
7929 pic_number);
7930 /* reset all counts */
7931 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
7932 return;
7933 }
7934 /* mvy_L1_count[39:32], mvx_L1_count[39:32],
7935 mvy_L0_count[39:32], mvx_L0_count[39:32] */
7936 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
7937 /* should all be 0x00 or 0xff */
7938 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7939 "[Picture %d Quality] MV AVG High Bits: 0x%X\n",
7940 pic_number, rdata32);
7941
7942 mvx_L0_hi = ((rdata32>>0)&0xff);
7943 mvy_L0_hi = ((rdata32>>8)&0xff);
7944 mvx_L1_hi = ((rdata32>>16)&0xff);
7945 mvy_L1_hi = ((rdata32>>24)&0xff);
7946
7947 /* mvx_L0_count[31:0] */
7948 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7949 temp_value = mvx_L0_hi;
7950 temp_value = (temp_value << 32) | rdata32_l;
7951
7952 if (mvx_L0_hi & 0x80)
7953 value = 0xFFFFFFF000000000 | temp_value;
7954 else
7955 value = temp_value;
7956
7957 value = div_s64(value, blk22_mv_count);
7958
7959 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7960 "[Picture %d Quality] MVX_L0 AVG : %d (%lld/%d)\n",
7961 pic_number, (int)value,
7962 value, blk22_mv_count);
7963
7964 frame->avg_mv = value;
7965
7966 /* mvy_L0_count[31:0] */
7967 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7968 temp_value = mvy_L0_hi;
7969 temp_value = (temp_value << 32) | rdata32_l;
7970
7971 if (mvy_L0_hi & 0x80)
7972 value = 0xFFFFFFF000000000 | temp_value;
7973 else
7974 value = temp_value;
7975
7976 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7977 "[Picture %d Quality] MVY_L0 AVG : %d (%lld/%d)\n",
7978 pic_number, rdata32_l/blk22_mv_count,
7979 value, blk22_mv_count);
7980
7981 /* mvx_L1_count[31:0] */
7982 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7983 temp_value = mvx_L1_hi;
7984 temp_value = (temp_value << 32) | rdata32_l;
7985 if (mvx_L1_hi & 0x80)
7986 value = 0xFFFFFFF000000000 | temp_value;
7987 else
7988 value = temp_value;
7989
7990 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
7991 "[Picture %d Quality] MVX_L1 AVG : %d (%lld/%d)\n",
7992 pic_number, rdata32_l/blk22_mv_count,
7993 value, blk22_mv_count);
7994
7995 /* mvy_L1_count[31:0] */
7996 rdata32_l = READ_VREG(HEVC_PIC_QUALITY_DATA);
7997 temp_value = mvy_L1_hi;
7998 temp_value = (temp_value << 32) | rdata32_l;
7999 if (mvy_L1_hi & 0x80)
8000 value = 0xFFFFFFF000000000 | temp_value;
8001 else
8002 value = temp_value;
8003
8004 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8005 "[Picture %d Quality] MVY_L1 AVG : %d (%lld/%d)\n",
8006 pic_number, rdata32_l/blk22_mv_count,
8007 value, blk22_mv_count);
8008
8009 /* {mvx_L0_max, mvx_L0_min} // format : {sign, abs[14:0]} */
8010 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8011 mv_hi = (rdata32>>16)&0xffff;
8012 if (mv_hi & 0x8000)
8013 mv_hi = 0x8000 - mv_hi;
8014
8015 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8016 "[Picture %d Quality] MVX_L0 MAX : %d\n",
8017 pic_number, mv_hi);
8018
8019 frame->max_mv = mv_hi;
8020
8021 mv_lo = (rdata32>>0)&0xffff;
8022 if (mv_lo & 0x8000)
8023 mv_lo = 0x8000 - mv_lo;
8024
8025 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8026 "[Picture %d Quality] MVX_L0 MIN : %d\n",
8027 pic_number, mv_lo);
8028
8029 frame->min_mv = mv_lo;
8030
8031 /* {mvy_L0_max, mvy_L0_min} */
8032 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8033 mv_hi = (rdata32>>16)&0xffff;
8034 if (mv_hi & 0x8000)
8035 mv_hi = 0x8000 - mv_hi;
8036
8037 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8038 "[Picture %d Quality] MVY_L0 MAX : %d\n",
8039 pic_number, mv_hi);
8040
8041 mv_lo = (rdata32>>0)&0xffff;
8042 if (mv_lo & 0x8000)
8043 mv_lo = 0x8000 - mv_lo;
8044
8045 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8046 "[Picture %d Quality] MVY_L0 MIN : %d\n",
8047 pic_number, mv_lo);
8048
8049 /* {mvx_L1_max, mvx_L1_min} */
8050 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8051 mv_hi = (rdata32>>16)&0xffff;
8052 if (mv_hi & 0x8000)
8053 mv_hi = 0x8000 - mv_hi;
8054
8055 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8056 "[Picture %d Quality] MVX_L1 MAX : %d\n",
8057 pic_number, mv_hi);
8058
8059 mv_lo = (rdata32>>0)&0xffff;
8060 if (mv_lo & 0x8000)
8061 mv_lo = 0x8000 - mv_lo;
8062
8063 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8064 "[Picture %d Quality] MVX_L1 MIN : %d\n",
8065 pic_number, mv_lo);
8066
8067 /* {mvy_L1_max, mvy_L1_min} */
8068 rdata32 = READ_VREG(HEVC_PIC_QUALITY_DATA);
8069 mv_hi = (rdata32>>16)&0xffff;
8070 if (mv_hi & 0x8000)
8071 mv_hi = 0x8000 - mv_hi;
8072
8073 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8074 "[Picture %d Quality] MVY_L1 MAX : %d\n",
8075 pic_number, mv_hi);
8076
8077 mv_lo = (rdata32>>0)&0xffff;
8078 if (mv_lo & 0x8000)
8079 mv_lo = 0x8000 - mv_lo;
8080
8081 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8082 "[Picture %d Quality] MVY_L1 MIN : %d\n",
8083 pic_number, mv_lo);
8084
8085 rdata32 = READ_VREG(HEVC_PIC_QUALITY_CTRL);
8086
8087 vp9_print(pbi, VP9_DEBUG_QOS_INFO,
8088 "[Picture %d Quality] After Read : VDEC_PIC_QUALITY_CTRL : 0x%x\n",
8089 pic_number, rdata32);
8090
8091 /* reset all counts */
8092 WRITE_VREG(HEVC_PIC_QUALITY_CTRL, (1<<8));
8093 }
8094}
8095
8096static irqreturn_t vvp9_isr_thread_fn(int irq, void *data)
8097{
8098 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8099 unsigned int dec_status = pbi->dec_status;
8100 int i;
8101
8102 /*if (pbi->wait_buf)
8103 * pr_info("set wait_buf to 0\r\n");
8104 */
8105 if (pbi->eos)
8106 return IRQ_HANDLED;
8107 pbi->wait_buf = 0;
8108#ifdef MULTI_INSTANCE_SUPPORT
8109#ifdef SUPPORT_FB_DECODING
8110#ifdef FB_DECODING_TEST_SCHEDULE
8111 if (pbi->s1_test_cmd == TEST_SET_PIC_DONE)
8112 dec_status = HEVC_DECPIC_DATA_DONE;
8113 else if (pbi->s1_test_cmd == TEST_SET_S2_DONE
8114 && dec_status == HEVC_DECPIC_DATA_DONE)
8115 dec_status = HEVC_S2_DECODING_DONE;
8116 pbi->s1_test_cmd = TEST_SET_NONE;
8117#else
8118 /*if (irq != VDEC_IRQ_0)
8119 dec_status = HEVC_S2_DECODING_DONE;*/
8120#endif
8121 if (dec_status == HEVC_S2_DECODING_DONE) {
8122 pbi->dec_result = DEC_RESULT_DONE;
8123 vdec_schedule_work(&pbi->work);
8124#ifdef FB_DECODING_TEST_SCHEDULE
8125 amhevc_stop();
8126 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8127 vdec_schedule_work(&pbi->s1_work);
8128#endif
8129 } else
8130#endif
8131 if ((dec_status == HEVC_NAL_DECODE_DONE) ||
8132 (dec_status == HEVC_SEARCH_BUFEMPTY) ||
8133 (dec_status == HEVC_DECODE_BUFEMPTY)
8134 ) {
8135 if (pbi->m_ins_flag) {
8136 reset_process_time(pbi);
8137 if (!vdec_frame_based(hw_to_vdec(pbi)))
8138 dec_again_process(pbi);
8139 else {
8140 pbi->dec_result = DEC_RESULT_GET_DATA;
8141 vdec_schedule_work(&pbi->work);
8142 }
8143 }
8144 pbi->process_busy = 0;
8145 return IRQ_HANDLED;
8146 } else if (dec_status == HEVC_DECPIC_DATA_DONE) {
8147 if (pbi->m_ins_flag) {
8148 get_picture_qos_info(pbi);
8149#ifdef SUPPORT_FB_DECODING
8150 if (pbi->used_stage_buf_num > 0) {
8151 reset_process_time(pbi);
8152 inc_s1_pos(pbi);
8153 trigger_schedule(pbi);
8154#ifdef FB_DECODING_TEST_SCHEDULE
8155 pbi->s1_test_cmd = TEST_SET_S2_DONE;
8156#else
8157 amhevc_stop();
8158 pbi->dec_s1_result = DEC_S1_RESULT_DONE;
8159 vdec_schedule_work(&pbi->s1_work);
8160#endif
8161 } else
8162#endif
8163 {
8164 reset_process_time(pbi);
8165 if (pbi->vf_pre_count == 0 || pbi->low_latency_flag)
8166 vp9_bufmgr_postproc(pbi);
8167
8168 pbi->dec_result = DEC_RESULT_DONE;
8169 amhevc_stop();
8170 if (mcrcc_cache_alg_flag)
8171 dump_hit_rate(pbi);
8172 vdec_schedule_work(&pbi->work);
8173 }
8174 } else {
8175 if (pbi->low_latency_flag) {
8176 vp9_bufmgr_postproc(pbi);
8177 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
8178#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8179 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_CB);
8180 if (debug & PRINT_FLAG_VDEC_DETAIL)
8181 pr_info("%s VP9 frame done \n", __func__);
8182#endif
8183 }
8184 }
8185
8186 pbi->process_busy = 0;
8187 return IRQ_HANDLED;
8188 }
8189#endif
8190
8191 if (dec_status == VP9_EOS) {
8192#ifdef MULTI_INSTANCE_SUPPORT
8193 if (pbi->m_ins_flag)
8194 reset_process_time(pbi);
8195#endif
8196
8197 pr_info("VP9_EOS, flush buffer\r\n");
8198
8199 vp9_bufmgr_postproc(pbi);
8200
8201 pr_info("send VP9_10B_DISCARD_NAL\r\n");
8202 WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL);
8203 pbi->process_busy = 0;
8204#ifdef MULTI_INSTANCE_SUPPORT
8205 if (pbi->m_ins_flag) {
8206 pbi->dec_result = DEC_RESULT_DONE;
8207 amhevc_stop();
8208 vdec_schedule_work(&pbi->work);
8209 }
8210#endif
8211 return IRQ_HANDLED;
8212 } else if (dec_status == HEVC_DECODE_OVER_SIZE) {
8213 pr_info("vp9 decode oversize !!\n");
8214 debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC |
8215 VP9_DEBUG_DIS_SYS_ERROR_PROC);
8216 pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
8217#ifdef MULTI_INSTANCE_SUPPORT
8218 if (pbi->m_ins_flag)
8219 reset_process_time(pbi);
8220#endif
8221 return IRQ_HANDLED;
8222 }
8223
8224 if (dec_status != VP9_HEAD_PARSER_DONE) {
8225 pbi->process_busy = 0;
8226 return IRQ_HANDLED;
8227 }
8228
8229
8230#ifdef MULTI_INSTANCE_SUPPORT
8231#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8232 if (pbi->m_ins_flag ==0 && pbi->low_latency_flag) {
8233 vdec_profile(hw_to_vdec(pbi), VDEC_PROFILE_EVENT_RUN);
8234 if (debug & PRINT_FLAG_VDEC_DETAIL)
8235 pr_info("%s VP9 frame header found \n", __func__);
8236 }
8237#endif
8238 if (pbi->m_ins_flag)
8239 reset_process_time(pbi);
8240#endif
8241 if (pbi->process_state != PROC_STATE_SENDAGAIN
8242#ifdef SUPPORT_FB_DECODING
8243 && pbi->used_stage_buf_num == 0
8244#endif
8245 ) {
8246 if (pbi->mmu_enable)
8247 vp9_recycle_mmu_buf_tail(pbi);
8248
8249
8250 if (pbi->frame_count > 0)
8251 vp9_bufmgr_postproc(pbi);
8252 }
8253
8254 if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) {
8255 get_rpm_param(&vp9_param);
8256 } else {
8257#ifdef SUPPORT_FB_DECODING
8258 if (pbi->used_stage_buf_num > 0) {
8259 reset_process_time(pbi);
8260 get_s1_buf(pbi);
8261
8262 if (get_mv_buf(pbi,
8263 &pbi->s1_mv_buf_index,
8264 &pbi->s1_mpred_mv_wr_start_addr
8265 ) < 0) {
8266 vp9_print(pbi, 0,
8267 "%s: Error get_mv_buf fail\n",
8268 __func__);
8269 }
8270
8271 if (pbi->s1_buf == NULL) {
8272 vp9_print(pbi, 0,
8273 "%s: Error get_s1_buf fail\n",
8274 __func__);
8275 pbi->process_busy = 0;
8276 return IRQ_HANDLED;
8277 }
8278
8279 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8280 int ii;
8281 for (ii = 0; ii < 4; ii++) {
8282 pbi->s1_buf->rpm[i + 3 - ii] =
8283 pbi->rpm_ptr[i + 3 - ii];
8284 pbi->s1_param.l.data[i + ii] =
8285 pbi->rpm_ptr[i + 3 - ii];
8286 }
8287 }
8288
8289 mpred_process(pbi);
8290#ifdef FB_DECODING_TEST_SCHEDULE
8291 pbi->dec_s1_result =
8292 DEC_S1_RESULT_TEST_TRIGGER_DONE;
8293 vdec_schedule_work(&pbi->s1_work);
8294#else
8295 WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR,
8296 pbi->stage_mmu_map_phy_addr +
8297 pbi->s1_buf->index * STAGE_MMU_MAP_SIZE);
8298
8299 start_s1_decoding(pbi);
8300#endif
8301 start_process_time(pbi);
8302 pbi->process_busy = 0;
8303 return IRQ_HANDLED;
8304 } else
8305#endif
8306 {
8307 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
8308 int ii;
8309 for (ii = 0; ii < 4; ii++)
8310 vp9_param.l.data[i + ii] =
8311 pbi->rpm_ptr[i + 3 - ii];
8312 }
8313 }
8314 }
8315
8316 if (pbi->is_used_v4l) {
8317 struct aml_vcodec_ctx *ctx =
8318 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
8319
8320 pbi->frame_width = vp9_param.p.width;
8321 pbi->frame_height = vp9_param.p.height;
8322 if (ctx->param_sets_from_ucode && !pbi->v4l_params_parsed) {
8323 struct aml_vdec_ps_infos ps;
8324
8325 ps.visible_width = pbi->frame_width;
8326 ps.visible_height = pbi->frame_height;
8327 ps.coded_width = ALIGN(pbi->frame_width, 32);
8328 ps.coded_height = ALIGN(pbi->frame_height, 32);
8329 ps.dpb_size = pbi->used_buf_num;
8330 pbi->v4l_params_parsed = true;
8331 vdec_v4l_set_ps_infos(ctx, &ps);
8332 }
8333 }
8334
8335 if (pbi->is_used_v4l) {
8336 pbi->dec_result = DEC_V4L2_CONTINUE_DECODING;
8337 vdec_schedule_work(&pbi->work);
8338 } else {
8339 continue_decoding(pbi);
8340 pbi->postproc_done = 0;
8341 pbi->process_busy = 0;
8342 }
8343
8344#ifdef MULTI_INSTANCE_SUPPORT
8345 if (pbi->m_ins_flag)
8346 start_process_time(pbi);
8347#endif
8348
8349 return IRQ_HANDLED;
8350}
8351
8352static irqreturn_t vvp9_isr(int irq, void *data)
8353{
8354 int i;
8355 unsigned int dec_status;
8356 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data;
8357 unsigned int adapt_prob_status;
8358 struct VP9_Common_s *const cm = &pbi->common;
8359 uint debug_tag;
8360
8361 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8362
8363 dec_status = READ_VREG(HEVC_DEC_STATUS_REG);
8364 adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG);
8365 if (!pbi)
8366 return IRQ_HANDLED;
8367 if (pbi->init_flag == 0)
8368 return IRQ_HANDLED;
8369 if (pbi->process_busy)/*on process.*/
8370 return IRQ_HANDLED;
8371 pbi->dec_status = dec_status;
8372 pbi->process_busy = 1;
8373 if (debug & VP9_DEBUG_BUFMGR)
8374 pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n",
8375 irq,
8376 dec_status, READ_VREG(HEVC_PARSER_LCU_START),
8377 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
8378 READ_VREG(HEVC_STREAM_START_ADDR),
8379 READ_VREG(HEVC_STREAM_END_ADDR),
8380 READ_VREG(HEVC_STREAM_LEVEL),
8381 READ_VREG(HEVC_STREAM_WR_PTR),
8382 READ_VREG(HEVC_STREAM_RD_PTR)
8383 );
8384#ifdef SUPPORT_FB_DECODING
8385 /*if (irq != VDEC_IRQ_0)
8386 return IRQ_WAKE_THREAD;*/
8387#endif
8388
8389 debug_tag = READ_HREG(DEBUG_REG1);
8390 if (debug_tag & 0x10000) {
8391 pr_info("LMEM<tag %x>:\n", READ_HREG(DEBUG_REG1));
8392 for (i = 0; i < 0x400; i += 4) {
8393 int ii;
8394 if ((i & 0xf) == 0)
8395 pr_info("%03x: ", i);
8396 for (ii = 0; ii < 4; ii++) {
8397 pr_info("%04x ",
8398 pbi->lmem_ptr[i + 3 - ii]);
8399 }
8400 if (((i + ii) & 0xf) == 0)
8401 pr_info("\n");
8402 }
8403
8404 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8405 (udebug_pause_decode_idx == 0 ||
8406 udebug_pause_decode_idx == pbi->slice_idx) &&
8407 (udebug_pause_val == 0 ||
8408 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8409 pbi->ucode_pause_pos = udebug_pause_pos;
8410 else if (debug_tag & 0x20000)
8411 pbi->ucode_pause_pos = 0xffffffff;
8412 if (pbi->ucode_pause_pos)
8413 reset_process_time(pbi);
8414 else
8415 WRITE_HREG(DEBUG_REG1, 0);
8416 } else if (debug_tag != 0) {
8417 pr_info(
8418 "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1),
8419 READ_HREG(DEBUG_REG2),
8420 READ_VREG(HEVC_PARSER_LCU_START));
8421 if ((udebug_pause_pos == (debug_tag & 0xffff)) &&
8422 (udebug_pause_decode_idx == 0 ||
8423 udebug_pause_decode_idx == pbi->slice_idx) &&
8424 (udebug_pause_val == 0 ||
8425 udebug_pause_val == READ_HREG(DEBUG_REG2)))
8426 pbi->ucode_pause_pos = udebug_pause_pos;
8427 if (pbi->ucode_pause_pos)
8428 reset_process_time(pbi);
8429 else
8430 WRITE_HREG(DEBUG_REG1, 0);
8431 pbi->process_busy = 0;
8432 return IRQ_HANDLED;
8433 }
8434
8435#ifdef MULTI_INSTANCE_SUPPORT
8436 if (!pbi->m_ins_flag) {
8437#endif
8438 if (pbi->error_flag == 1) {
8439 pbi->error_flag = 2;
8440 pbi->process_busy = 0;
8441 return IRQ_HANDLED;
8442 } else if (pbi->error_flag == 3) {
8443 pbi->process_busy = 0;
8444 return IRQ_HANDLED;
8445 }
8446
8447 if (get_free_buf_count(pbi) <= 0) {
8448 /*
8449 if (pbi->wait_buf == 0)
8450 pr_info("set wait_buf to 1\r\n");
8451 */
8452 pbi->wait_buf = 1;
8453 pbi->process_busy = 0;
8454 return IRQ_HANDLED;
8455 }
8456#ifdef MULTI_INSTANCE_SUPPORT
8457 }
8458#endif
8459 if ((adapt_prob_status & 0xff) == 0xfd) {
8460 /*VP9_REQ_ADAPT_PROB*/
8461 int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0;
8462 uint8_t *prev_prob_b =
8463 ((uint8_t *)pbi->prob_buffer_addr) +
8464 ((adapt_prob_status >> 8) * 0x1000);
8465 uint8_t *cur_prob_b =
8466 ((uint8_t *)pbi->prob_buffer_addr) + 0x4000;
8467 uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr;
8468#ifdef MULTI_INSTANCE_SUPPORT
8469 if (pbi->m_ins_flag)
8470 reset_process_time(pbi);
8471#endif
8472 adapt_coef_probs(pbi->pic_count,
8473 (cm->last_frame_type == KEY_FRAME),
8474 pre_fc, (adapt_prob_status >> 8),
8475 (unsigned int *)prev_prob_b,
8476 (unsigned int *)cur_prob_b, (unsigned int *)count_b);
8477
8478 memcpy(prev_prob_b, cur_prob_b, PROB_SIZE);
8479 WRITE_VREG(VP9_ADAPT_PROB_REG, 0);
8480 pbi->pic_count += 1;
8481#ifdef MULTI_INSTANCE_SUPPORT
8482 if (pbi->m_ins_flag)
8483 start_process_time(pbi);
8484#endif
8485
8486 /*return IRQ_HANDLED;*/
8487 }
8488 return IRQ_WAKE_THREAD;
8489}
8490
8491static void vp9_set_clk(struct work_struct *work)
8492{
8493 struct VP9Decoder_s *pbi = container_of(work,
8494 struct VP9Decoder_s, set_clk_work);
8495 int fps = 96000 / pbi->frame_dur;
8496
8497 if (hevc_source_changed(VFORMAT_VP9,
8498 frame_width, frame_height, fps) > 0)
8499 pbi->saved_resolution = frame_width *
8500 frame_height * fps;
8501}
8502
8503static void vvp9_put_timer_func(unsigned long arg)
8504{
8505 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg;
8506 struct timer_list *timer = &pbi->timer;
8507 uint8_t empty_flag;
8508 unsigned int buf_level;
8509
8510 enum receviver_start_e state = RECEIVER_INACTIVE;
8511
8512 if (pbi->m_ins_flag) {
8513 if (hw_to_vdec(pbi)->next_status
8514 == VDEC_STATUS_DISCONNECTED) {
8515#ifdef SUPPORT_FB_DECODING
8516 if (pbi->run2_busy)
8517 return;
8518
8519 pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT;
8520 vdec_schedule_work(&pbi->s1_work);
8521#endif
8522 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
8523 vdec_schedule_work(&pbi->work);
8524 pr_debug(
8525 "vdec requested to be disconnected\n");
8526 return;
8527 }
8528 }
8529 if (pbi->init_flag == 0) {
8530 if (pbi->stat & STAT_TIMER_ARM) {
8531 timer->expires = jiffies + PUT_INTERVAL;
8532 add_timer(&pbi->timer);
8533 }
8534 return;
8535 }
8536 if (pbi->m_ins_flag == 0) {
8537 if (vf_get_receiver(pbi->provider_name)) {
8538 state =
8539 vf_notify_receiver(pbi->provider_name,
8540 VFRAME_EVENT_PROVIDER_QUREY_STATE,
8541 NULL);
8542 if ((state == RECEIVER_STATE_NULL)
8543 || (state == RECEIVER_STATE_NONE))
8544 state = RECEIVER_INACTIVE;
8545 } else
8546 state = RECEIVER_INACTIVE;
8547
8548 empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1;
8549 /* error watchdog */
8550 if (empty_flag == 0) {
8551 /* decoder has input */
8552 if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) {
8553
8554 buf_level = READ_VREG(HEVC_STREAM_LEVEL);
8555 /* receiver has no buffer to recycle */
8556 if ((state == RECEIVER_INACTIVE) &&
8557 (kfifo_is_empty(&pbi->display_q) &&
8558 buf_level > 0x200)
8559 ) {
8560 WRITE_VREG
8561 (HEVC_ASSIST_MBOX0_IRQ_REG,
8562 0x1);
8563 }
8564 }
8565
8566 if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) {
8567 /* receiver has no buffer to recycle */
8568 /*if ((state == RECEIVER_INACTIVE) &&
8569 * (kfifo_is_empty(&pbi->display_q))) {
8570 *pr_info("vp9 something error,need reset\n");
8571 *}
8572 */
8573 }
8574 }
8575 }
8576#ifdef MULTI_INSTANCE_SUPPORT
8577 else {
8578 if (
8579 (decode_timeout_val > 0) &&
8580 (pbi->start_process_time > 0) &&
8581 ((1000 * (jiffies - pbi->start_process_time) / HZ)
8582 > decode_timeout_val)
8583 ) {
8584 int current_lcu_idx =
8585 READ_VREG(HEVC_PARSER_LCU_START)
8586 & 0xffffff;
8587 if (pbi->last_lcu_idx == current_lcu_idx) {
8588 if (pbi->decode_timeout_count > 0)
8589 pbi->decode_timeout_count--;
8590 if (pbi->decode_timeout_count == 0) {
8591 if (input_frame_based(
8592 hw_to_vdec(pbi)) ||
8593 (READ_VREG(HEVC_STREAM_LEVEL) > 0x200))
8594 timeout_process(pbi);
8595 else {
8596 vp9_print(pbi, 0,
8597 "timeout & empty, again\n");
8598 dec_again_process(pbi);
8599 }
8600 }
8601 } else {
8602 start_process_time(pbi);
8603 pbi->last_lcu_idx = current_lcu_idx;
8604 }
8605 }
8606 }
8607#endif
8608
8609 if ((pbi->ucode_pause_pos != 0) &&
8610 (pbi->ucode_pause_pos != 0xffffffff) &&
8611 udebug_pause_pos != pbi->ucode_pause_pos) {
8612 pbi->ucode_pause_pos = 0;
8613 WRITE_HREG(DEBUG_REG1, 0);
8614 }
8615#ifdef MULTI_INSTANCE_SUPPORT
8616 if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) {
8617 pr_info(
8618 "Force Send Again\r\n");
8619 debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN;
8620 reset_process_time(pbi);
8621 pbi->dec_result = DEC_RESULT_AGAIN;
8622 if (pbi->process_state ==
8623 PROC_STATE_DECODESLICE) {
8624 if (pbi->mmu_enable)
8625 vp9_recycle_mmu_buf(pbi);
8626 pbi->process_state =
8627 PROC_STATE_SENDAGAIN;
8628 }
8629 amhevc_stop();
8630
8631 vdec_schedule_work(&pbi->work);
8632 }
8633
8634 if (debug & VP9_DEBUG_DUMP_DATA) {
8635 debug &= ~VP9_DEBUG_DUMP_DATA;
8636 vp9_print(pbi, 0,
8637 "%s: chunk size 0x%x off 0x%x sum 0x%x\n",
8638 __func__,
8639 pbi->chunk->size,
8640 pbi->chunk->offset,
8641 get_data_check_sum(pbi, pbi->chunk->size)
8642 );
8643 dump_data(pbi, pbi->chunk->size);
8644 }
8645#endif
8646 if (debug & VP9_DEBUG_DUMP_PIC_LIST) {
8647 dump_pic_list(pbi);
8648 debug &= ~VP9_DEBUG_DUMP_PIC_LIST;
8649 }
8650 if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) {
8651 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
8652 debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC;
8653 }
8654 /*if (debug & VP9_DEBUG_HW_RESET) {
8655 }*/
8656
8657 if (radr != 0) {
8658 if (rval != 0) {
8659 WRITE_VREG(radr, rval);
8660 pr_info("WRITE_VREG(%x,%x)\n", radr, rval);
8661 } else
8662 pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr));
8663 rval = 0;
8664 radr = 0;
8665 }
8666 if (pop_shorts != 0) {
8667 int i;
8668 u32 sum = 0;
8669
8670 pr_info("pop stream 0x%x shorts\r\n", pop_shorts);
8671 for (i = 0; i < pop_shorts; i++) {
8672 u32 data =
8673 (READ_HREG(HEVC_SHIFTED_DATA) >> 16);
8674 WRITE_HREG(HEVC_SHIFT_COMMAND,
8675 (1<<7)|16);
8676 if ((i & 0xf) == 0)
8677 pr_info("%04x:", i);
8678 pr_info("%04x ", data);
8679 if (((i + 1) & 0xf) == 0)
8680 pr_info("\r\n");
8681 sum += data;
8682 }
8683 pr_info("\r\nsum = %x\r\n", sum);
8684 pop_shorts = 0;
8685 }
8686 if (dbg_cmd != 0) {
8687 if (dbg_cmd == 1) {
8688 u32 disp_laddr;
8689
8690 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXBB &&
8691 get_double_write_mode(pbi) == 0) {
8692 disp_laddr =
8693 READ_VCBUS_REG(AFBC_BODY_BADDR) << 4;
8694 } else {
8695 struct canvas_s cur_canvas;
8696
8697 canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0)
8698 & 0xff), &cur_canvas);
8699 disp_laddr = cur_canvas.addr;
8700 }
8701 pr_info("current displayed buffer address %x\r\n",
8702 disp_laddr);
8703 }
8704 dbg_cmd = 0;
8705 }
8706 /*don't changed at start.*/
8707 if (pbi->get_frame_dur && pbi->show_frame_num > 60 &&
8708 pbi->frame_dur > 0 && pbi->saved_resolution !=
8709 frame_width * frame_height *
8710 (96000 / pbi->frame_dur))
8711 vdec_schedule_work(&pbi->set_clk_work);
8712
8713 timer->expires = jiffies + PUT_INTERVAL;
8714 add_timer(timer);
8715}
8716
8717
8718int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus)
8719{
8720 struct VP9Decoder_s *vp9 =
8721 (struct VP9Decoder_s *)vdec->private;
8722
8723 if (!vp9)
8724 return -1;
8725
8726 vstatus->frame_width = frame_width;
8727 vstatus->frame_height = frame_height;
8728 if (vp9->frame_dur != 0)
8729 vstatus->frame_rate = 96000 / vp9->frame_dur;
8730 else
8731 vstatus->frame_rate = -1;
8732 vstatus->error_count = 0;
8733 vstatus->status = vp9->stat | vp9->fatal_error;
8734 vstatus->frame_dur = vp9->frame_dur;
8735#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
8736 vstatus->bit_rate = gvs->bit_rate;
8737 vstatus->frame_data = gvs->frame_data;
8738 vstatus->total_data = gvs->total_data;
8739 vstatus->frame_count = gvs->frame_count;
8740 vstatus->error_frame_count = gvs->error_frame_count;
8741 vstatus->drop_frame_count = gvs->drop_frame_count;
8742 vstatus->total_data = gvs->total_data;
8743 vstatus->samp_cnt = gvs->samp_cnt;
8744 vstatus->offset = gvs->offset;
8745 snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name),
8746 "%s", DRIVER_NAME);
8747#endif
8748 return 0;
8749}
8750
8751int vvp9_set_isreset(struct vdec_s *vdec, int isreset)
8752{
8753 is_reset = isreset;
8754 return 0;
8755}
8756
8757#if 0
8758static void VP9_DECODE_INIT(void)
8759{
8760 /* enable vp9 clocks */
8761 WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);
8762 /* *************************************************************** */
8763 /* Power ON HEVC */
8764 /* *************************************************************** */
8765 /* Powerup HEVC */
8766 WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0,
8767 READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6)));
8768 WRITE_VREG(DOS_MEM_PD_HEVC, 0x0);
8769 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2));
8770 WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2)));
8771 /* remove isolations */
8772 WRITE_VREG(AO_RTI_GEN_PWR_ISO0,
8773 READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10)));
8774
8775}
8776#endif
8777
8778static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask)
8779{
8780 unsigned int data32;
8781 /* VP9_DECODE_INIT(); */
8782 vp9_config_work_space_hw(pbi, mask);
8783 if (mask & HW_MASK_BACK)
8784 init_pic_list_hw(pbi);
8785
8786 vp9_init_decoder_hw(pbi, mask);
8787
8788#ifdef VP9_LPF_LVL_UPDATE
8789 if (mask & HW_MASK_BACK)
8790 vp9_loop_filter_init(pbi);
8791#endif
8792
8793 if ((mask & HW_MASK_FRONT) == 0)
8794 return;
8795#if 1
8796 if (debug & VP9_DEBUG_BUFMGR_MORE)
8797 pr_info("%s\n", __func__);
8798 data32 = READ_VREG(HEVC_STREAM_CONTROL);
8799 data32 = data32 |
8800 (1 << 0)/*stream_fetch_enable*/
8801 ;
8802 WRITE_VREG(HEVC_STREAM_CONTROL, data32);
8803
8804 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
8805 if (debug & VP9_DEBUG_BUFMGR)
8806 pr_info("[test.c] Config STREAM_FIFO_CTL\n");
8807 data32 = READ_VREG(HEVC_STREAM_FIFO_CTL);
8808 data32 = data32 |
8809 (1 << 29) // stream_fifo_hole
8810 ;
8811 WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32);
8812 }
8813#if 0
8814 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8815 if (data32 != 0x00000100) {
8816 pr_info("vp9 prot init error %d\n", __LINE__);
8817 return;
8818 }
8819 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8820 if (data32 != 0x00000300) {
8821 pr_info("vp9 prot init error %d\n", __LINE__);
8822 return;
8823 }
8824 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678);
8825 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0);
8826 data32 = READ_VREG(HEVC_SHIFT_STARTCODE);
8827 if (data32 != 0x12345678) {
8828 pr_info("vp9 prot init error %d\n", __LINE__);
8829 return;
8830 }
8831 data32 = READ_VREG(HEVC_SHIFT_EMULATECODE);
8832 if (data32 != 0x9abcdef0) {
8833 pr_info("vp9 prot init error %d\n", __LINE__);
8834 return;
8835 }
8836#endif
8837 WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001);
8838 WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300);
8839#endif
8840
8841
8842
8843 WRITE_VREG(HEVC_WAIT_FLAG, 1);
8844
8845 /* WRITE_VREG(HEVC_MPSR, 1); */
8846
8847 /* clear mailbox interrupt */
8848 WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1);
8849
8850 /* enable mailbox interrupt */
8851 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1);
8852
8853 /* disable PSCALE for hardware sharing */
8854 WRITE_VREG(HEVC_PSCALE_CTRL, 0);
8855
8856 WRITE_VREG(DEBUG_REG1, 0x0);
8857 /*check vps/sps/pps/i-slice in ucode*/
8858 WRITE_VREG(NAL_SEARCH_CTL, 0x8);
8859
8860 WRITE_VREG(DECODE_STOP_POS, udebug_flag);
8861#ifdef SUPPORT_FB_DECODING
8862#ifndef FB_DECODING_TEST_SCHEDULE
8863 if (pbi->used_stage_buf_num > 0) {
8864 if (mask & HW_MASK_FRONT) {
8865 data32 = READ_VREG(
8866 HEVC_ASSIST_HED_FB_W_CTL);
8867 data32 = data32 |
8868 (1 << 0) /*hed_fb_wr_en*/
8869 ;
8870 WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL,
8871 data32);
8872 }
8873 if (mask & HW_MASK_BACK) {
8874 data32 = READ_VREG(
8875 HEVC_ASSIST_HED_FB_R_CTL);
8876 while (data32 & (1 << 7)) {
8877 /*wait finish*/
8878 data32 = READ_VREG(
8879 HEVC_ASSIST_HED_FB_R_CTL);
8880 }
8881 data32 &= (~(0x1 << 0));
8882 /*hed_fb_rd_addr_auto_rd*/
8883 data32 &= (~(0x1 << 1));
8884 /*rd_id = 0, hed_rd_map_auto_halt_num,
8885 after wr 2 ready, then start reading*/
8886 data32 |= (0x2 << 16);
8887 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8888 data32);
8889
8890 data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/
8891 data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/
8892 data32 |= (0x1 << 0); /*hed_fb_rd_en*/
8893 WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL,
8894 data32);
8895 }
8896
8897 }
8898#endif
8899#endif
8900}
8901
8902static int vvp9_local_init(struct VP9Decoder_s *pbi)
8903{
8904 int i;
8905 int ret;
8906 int width, height;
8907 if (alloc_lf_buf(pbi) < 0)
8908 return -1;
8909
8910 pbi->gvs = vzalloc(sizeof(struct vdec_info));
8911 if (NULL == pbi->gvs) {
8912 pr_info("the struct of vdec status malloc failed.\n");
8913 return -1;
8914 }
8915#ifdef DEBUG_PTS
8916 pbi->pts_missed = 0;
8917 pbi->pts_hit = 0;
8918#endif
8919 pbi->new_frame_displayed = 0;
8920 pbi->last_put_idx = -1;
8921 pbi->saved_resolution = 0;
8922 pbi->get_frame_dur = false;
8923 on_no_keyframe_skiped = 0;
8924 pbi->duration_from_pts_done = 0;
8925 pbi->vp9_first_pts_ready = 0;
8926 pbi->frame_cnt_window = 0;
8927 width = pbi->vvp9_amstream_dec_info.width;
8928 height = pbi->vvp9_amstream_dec_info.height;
8929 pbi->frame_dur =
8930 (pbi->vvp9_amstream_dec_info.rate ==
8931 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate;
8932 if (width && height)
8933 pbi->frame_ar = height * 0x100 / width;
8934/*
8935 *TODO:FOR VERSION
8936 */
8937 pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version,
8938 0, width, height, pbi->frame_dur);
8939
8940 if (pbi->frame_dur == 0)
8941 pbi->frame_dur = 96000 / 24;
8942
8943 INIT_KFIFO(pbi->display_q);
8944 INIT_KFIFO(pbi->newframe_q);
8945
8946
8947 for (i = 0; i < VF_POOL_SIZE; i++) {
8948 const struct vframe_s *vf = &pbi->vfpool[i];
8949
8950 pbi->vfpool[i].index = -1;
8951 kfifo_put(&pbi->newframe_q, vf);
8952 }
8953
8954
8955 ret = vp9_local_init(pbi);
8956
8957 if (!pbi->pts_unstable) {
8958 pbi->pts_unstable =
8959 (pbi->vvp9_amstream_dec_info.rate == 0)?1:0;
8960 pr_info("set pts unstable\n");
8961 }
8962
8963 return ret;
8964}
8965
8966
8967#ifdef MULTI_INSTANCE_SUPPORT
8968static s32 vvp9_init(struct vdec_s *vdec)
8969{
8970 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private;
8971#else
8972static s32 vvp9_init(struct VP9Decoder_s *pbi)
8973{
8974#endif
8975 int ret;
8976 int fw_size = 0x1000 * 16;
8977 struct firmware_s *fw = NULL;
8978
8979 pbi->stat |= STAT_TIMER_INIT;
8980
8981 if (vvp9_local_init(pbi) < 0)
8982 return -EBUSY;
8983
8984 fw = vmalloc(sizeof(struct firmware_s) + fw_size);
8985 if (IS_ERR_OR_NULL(fw))
8986 return -ENOMEM;
8987
8988 if (get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data) < 0) {
8989 pr_err("get firmware fail.\n");
8990 vfree(fw);
8991 return -1;
8992 }
8993
8994 fw->len = fw_size;
8995
8996 INIT_WORK(&pbi->set_clk_work, vp9_set_clk);
8997 init_timer(&pbi->timer);
8998
8999#ifdef MULTI_INSTANCE_SUPPORT
9000 if (pbi->m_ins_flag) {
9001 pbi->timer.data = (ulong) pbi;
9002 pbi->timer.function = vvp9_put_timer_func;
9003 pbi->timer.expires = jiffies + PUT_INTERVAL;
9004
9005 /*add_timer(&pbi->timer);
9006
9007 pbi->stat |= STAT_TIMER_ARM;
9008 pbi->stat |= STAT_ISR_REG;*/
9009
9010 INIT_WORK(&pbi->work, vp9_work);
9011#ifdef SUPPORT_FB_DECODING
9012 if (pbi->used_stage_buf_num > 0)
9013 INIT_WORK(&pbi->s1_work, vp9_s1_work);
9014#endif
9015 pbi->fw = fw;
9016
9017 /* picture list init.*/
9018 pbi->dec_result = DEC_INIT_PICLIST;
9019 vdec_schedule_work(&pbi->work);
9020
9021 return 0;
9022 }
9023#endif
9024 amhevc_enable();
9025
9026 init_pic_list(pbi);
9027
9028 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data);
9029 if (ret < 0) {
9030 amhevc_disable();
9031 vfree(fw);
9032 pr_err("VP9: the %s fw loading failed, err: %x\n",
9033 tee_enabled() ? "TEE" : "local", ret);
9034 return -EBUSY;
9035 }
9036
9037 vfree(fw);
9038
9039 pbi->stat |= STAT_MC_LOAD;
9040
9041 /* enable AMRISC side protocol */
9042 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9043
9044 if (vdec_request_threaded_irq(VDEC_IRQ_0,
9045 vvp9_isr,
9046 vvp9_isr_thread_fn,
9047 IRQF_ONESHOT,/*run thread on this irq disabled*/
9048 "vvp9-irq", (void *)pbi)) {
9049 pr_info("vvp9 irq register error.\n");
9050 amhevc_disable();
9051 return -ENOENT;
9052 }
9053
9054 pbi->stat |= STAT_ISR_REG;
9055
9056 pbi->provider_name = PROVIDER_NAME;
9057#ifdef MULTI_INSTANCE_SUPPORT
9058 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME,
9059 &vvp9_vf_provider, pbi);
9060 vf_reg_provider(&vvp9_vf_prov);
9061 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9062 if (pbi->frame_dur != 0) {
9063 if (!is_reset)
9064 vf_notify_receiver(pbi->provider_name,
9065 VFRAME_EVENT_PROVIDER_FR_HINT,
9066 (void *)
9067 ((unsigned long)pbi->frame_dur));
9068 }
9069#else
9070 vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider,
9071 pbi);
9072 vf_reg_provider(&vvp9_vf_prov);
9073 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL);
9074 if (!is_reset)
9075 vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT,
9076 (void *)((unsigned long)pbi->frame_dur));
9077#endif
9078 pbi->stat |= STAT_VF_HOOK;
9079
9080 pbi->timer.data = (ulong)pbi;
9081 pbi->timer.function = vvp9_put_timer_func;
9082 pbi->timer.expires = jiffies + PUT_INTERVAL;
9083
9084 pbi->stat |= STAT_VDEC_RUN;
9085
9086 add_timer(&pbi->timer);
9087
9088 pbi->stat |= STAT_TIMER_ARM;
9089
9090 amhevc_start();
9091
9092 pbi->init_flag = 1;
9093 pbi->process_busy = 0;
9094 pr_info("%d, vvp9_init, RP=0x%x\n",
9095 __LINE__, READ_VREG(HEVC_STREAM_RD_PTR));
9096 return 0;
9097}
9098
9099static int vmvp9_stop(struct VP9Decoder_s *pbi)
9100{
9101 pbi->init_flag = 0;
9102
9103 if (pbi->stat & STAT_VDEC_RUN) {
9104 amhevc_stop();
9105 pbi->stat &= ~STAT_VDEC_RUN;
9106 }
9107 if (pbi->stat & STAT_ISR_REG) {
9108 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9109 pbi->stat &= ~STAT_ISR_REG;
9110 }
9111 if (pbi->stat & STAT_TIMER_ARM) {
9112 del_timer_sync(&pbi->timer);
9113 pbi->stat &= ~STAT_TIMER_ARM;
9114 }
9115
9116 if (pbi->stat & STAT_VF_HOOK) {
9117 if (!is_reset)
9118 vf_notify_receiver(pbi->provider_name,
9119 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9120 NULL);
9121
9122 vf_unreg_provider(&vvp9_vf_prov);
9123 pbi->stat &= ~STAT_VF_HOOK;
9124 }
9125 vp9_local_uninit(pbi);
9126 reset_process_time(pbi);
9127 cancel_work_sync(&pbi->work);
9128#ifdef SUPPORT_FB_DECODING
9129 if (pbi->used_stage_buf_num > 0)
9130 cancel_work_sync(&pbi->s1_work);
9131#endif
9132 cancel_work_sync(&pbi->set_clk_work);
9133 uninit_mmu_buffers(pbi);
9134 if (pbi->fw)
9135 vfree(pbi->fw);
9136 pbi->fw = NULL;
9137 return 0;
9138}
9139
9140static int vvp9_stop(struct VP9Decoder_s *pbi)
9141{
9142
9143 pbi->init_flag = 0;
9144 pbi->first_sc_checked = 0;
9145 if (pbi->stat & STAT_VDEC_RUN) {
9146 amhevc_stop();
9147 pbi->stat &= ~STAT_VDEC_RUN;
9148 }
9149
9150 if (pbi->stat & STAT_ISR_REG) {
9151#ifdef MULTI_INSTANCE_SUPPORT
9152 if (!pbi->m_ins_flag)
9153#endif
9154 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9155 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9156 pbi->stat &= ~STAT_ISR_REG;
9157 }
9158
9159 if (pbi->stat & STAT_TIMER_ARM) {
9160 del_timer_sync(&pbi->timer);
9161 pbi->stat &= ~STAT_TIMER_ARM;
9162 }
9163
9164 if (pbi->stat & STAT_VF_HOOK) {
9165 if (!is_reset)
9166 vf_notify_receiver(pbi->provider_name,
9167 VFRAME_EVENT_PROVIDER_FR_END_HINT,
9168 NULL);
9169
9170 vf_unreg_provider(&vvp9_vf_prov);
9171 pbi->stat &= ~STAT_VF_HOOK;
9172 }
9173 vp9_local_uninit(pbi);
9174
9175 cancel_work_sync(&pbi->set_clk_work);
9176#ifdef MULTI_INSTANCE_SUPPORT
9177 if (pbi->m_ins_flag) {
9178#ifdef SUPPORT_FB_DECODING
9179 if (pbi->used_stage_buf_num > 0)
9180 cancel_work_sync(&pbi->s1_work);
9181#endif
9182 cancel_work_sync(&pbi->work);
9183 } else
9184 amhevc_disable();
9185#else
9186 amhevc_disable();
9187#endif
9188 uninit_mmu_buffers(pbi);
9189
9190 vfree(pbi->fw);
9191 pbi->fw = NULL;
9192 return 0;
9193}
9194static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
9195{
9196 int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ?
9197 CODEC_MM_FLAGS_TVP : 0;
9198 int buf_size = 48;
9199
9200 if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) &&
9201 (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) {
9202 buf_size = 12;
9203 } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) &&
9204 (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) {
9205 buf_size = 4;
9206 }
9207 pbi->need_cache_size = buf_size * SZ_1M;
9208 pbi->sc_start_time = get_jiffies_64();
9209 if (pbi->mmu_enable && ((pbi->double_write_mode & 0x10) == 0)) {
9210 pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
9211 pbi->index, FRAME_BUFFERS,
9212 pbi->need_cache_size,
9213 tvp_flag
9214 );
9215 if (!pbi->mmu_box) {
9216 pr_err("vp9 alloc mmu box failed!!\n");
9217 return -1;
9218 }
9219 }
9220 pbi->bmmu_box = decoder_bmmu_box_alloc_box(
9221 DRIVER_NAME,
9222 pbi->index,
9223 MAX_BMMU_BUFFER_NUM,
9224 4 + PAGE_SHIFT,
9225 CODEC_MM_FLAGS_CMA_CLEAR |
9226 CODEC_MM_FLAGS_FOR_VDECODER |
9227 tvp_flag);
9228 if (!pbi->bmmu_box) {
9229 pr_err("vp9 alloc bmmu box failed!!\n");
9230 return -1;
9231 }
9232 return 0;
9233}
9234
9235static struct VP9Decoder_s *gHevc;
9236
9237static int amvdec_vp9_probe(struct platform_device *pdev)
9238{
9239 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
9240 struct BUF_s BUF[MAX_BUF_NUM];
9241 struct VP9Decoder_s *pbi;
9242 int ret;
9243#ifndef MULTI_INSTANCE_SUPPORT
9244 int i;
9245#endif
9246 pr_debug("%s\n", __func__);
9247
9248 mutex_lock(&vvp9_mutex);
9249 pbi = vmalloc(sizeof(struct VP9Decoder_s));
9250 if (pbi == NULL) {
9251 pr_info("\namvdec_vp9 device data allocation failed\n");
9252 mutex_unlock(&vvp9_mutex);
9253 return -ENOMEM;
9254 }
9255
9256 gHevc = pbi;
9257 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9258 memset(pbi, 0, sizeof(struct VP9Decoder_s));
9259 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
9260
9261 pbi->init_flag = 0;
9262 pbi->first_sc_checked= 0;
9263 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
9264 vp9_max_pic_w = 8192;
9265 vp9_max_pic_h = 4608;
9266 }
9267 pbi->max_pic_w = vp9_max_pic_w;
9268 pbi->max_pic_h = vp9_max_pic_h;
9269
9270#ifdef MULTI_INSTANCE_SUPPORT
9271 pbi->eos = 0;
9272 pbi->start_process_time = 0;
9273 pbi->timeout_num = 0;
9274#endif
9275 pbi->fatal_error = 0;
9276 pbi->show_frame_num = 0;
9277 if (pdata == NULL) {
9278 pr_info("\namvdec_vp9 memory resource undefined.\n");
9279 vfree(pbi);
9280 mutex_unlock(&vvp9_mutex);
9281 return -EFAULT;
9282 }
9283 pbi->m_ins_flag = 0;
9284#ifdef MULTI_INSTANCE_SUPPORT
9285 pbi->platform_dev = pdev;
9286 platform_set_drvdata(pdev, pdata);
9287#endif
9288 pbi->double_write_mode = double_write_mode;
9289 pbi->mmu_enable = 1;
9290 if (amvdec_vp9_mmu_init(pbi) < 0) {
9291 vfree(pbi);
9292 mutex_unlock(&vvp9_mutex);
9293 pr_err("vp9 alloc bmmu box failed!!\n");
9294 return -1;
9295 }
9296
9297 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
9298 work_buf_size, DRIVER_NAME, &pdata->mem_start);
9299 if (ret < 0) {
9300 uninit_mmu_buffers(pbi);
9301 vfree(pbi);
9302 mutex_unlock(&vvp9_mutex);
9303 return ret;
9304 }
9305 pbi->buf_size = work_buf_size;
9306
9307#ifdef MULTI_INSTANCE_SUPPORT
9308 pbi->buf_start = pdata->mem_start;
9309#else
9310 if (!pbi->mmu_enable)
9311 pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size;
9312
9313 for (i = 0; i < WORK_BUF_SPEC_NUM; i++)
9314 amvvp9_workbuff_spec[i].start_adr = pdata->mem_start;
9315#endif
9316
9317
9318 if (debug) {
9319 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
9320 pdata->mem_start, pbi->buf_size);
9321 }
9322
9323 if (pdata->sys_info)
9324 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
9325 else {
9326 pbi->vvp9_amstream_dec_info.width = 0;
9327 pbi->vvp9_amstream_dec_info.height = 0;
9328 pbi->vvp9_amstream_dec_info.rate = 30;
9329 }
9330 pbi->no_head = no_head;
9331#ifdef MULTI_INSTANCE_SUPPORT
9332 pbi->cma_dev = pdata->cma_dev;
9333#else
9334 cma_dev = pdata->cma_dev;
9335#endif
9336
9337#ifdef MULTI_INSTANCE_SUPPORT
9338 pdata->private = pbi;
9339 pdata->dec_status = vvp9_dec_status;
9340 pdata->set_isreset = vvp9_set_isreset;
9341 is_reset = 0;
9342 if (vvp9_init(pdata) < 0) {
9343#else
9344 if (vvp9_init(pbi) < 0) {
9345#endif
9346 pr_info("\namvdec_vp9 init failed.\n");
9347 vp9_local_uninit(pbi);
9348 uninit_mmu_buffers(pbi);
9349 vfree(pbi);
9350 pdata->dec_status = NULL;
9351 mutex_unlock(&vvp9_mutex);
9352 return -ENODEV;
9353 }
9354 /*set the max clk for smooth playing...*/
9355 hevc_source_changed(VFORMAT_VP9,
9356 4096, 2048, 60);
9357 mutex_unlock(&vvp9_mutex);
9358
9359 return 0;
9360}
9361
9362static int amvdec_vp9_remove(struct platform_device *pdev)
9363{
9364 struct VP9Decoder_s *pbi = gHevc;
9365 struct vdec_s *vdec = hw_to_vdec(pbi);
9366 int i;
9367
9368 if (debug)
9369 pr_info("amvdec_vp9_remove\n");
9370
9371 mutex_lock(&vvp9_mutex);
9372
9373 vvp9_stop(pbi);
9374
9375 hevc_source_changed(VFORMAT_VP9, 0, 0, 0);
9376
9377 if (vdec->parallel_dec == 1) {
9378 for (i = 0; i < FRAME_BUFFERS; i++) {
9379 vdec->free_canvas_ex(pbi->common.buffer_pool->
9380 frame_bufs[i].buf.y_canvas_index, vdec->id);
9381 vdec->free_canvas_ex(pbi->common.buffer_pool->
9382 frame_bufs[i].buf.uv_canvas_index, vdec->id);
9383 }
9384 }
9385
9386#ifdef DEBUG_PTS
9387 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
9388 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
9389#endif
9390 mem_map_mode = 0;
9391
9392 vfree(pbi);
9393 mutex_unlock(&vvp9_mutex);
9394
9395 return 0;
9396}
9397
9398/****************************************/
9399#ifdef CONFIG_PM
9400static int vp9_suspend(struct device *dev)
9401{
9402 amhevc_suspend(to_platform_device(dev), dev->power.power_state);
9403 return 0;
9404}
9405
9406static int vp9_resume(struct device *dev)
9407{
9408 amhevc_resume(to_platform_device(dev));
9409 return 0;
9410}
9411
9412static const struct dev_pm_ops vp9_pm_ops = {
9413 SET_SYSTEM_SLEEP_PM_OPS(vp9_suspend, vp9_resume)
9414};
9415#endif
9416
9417static struct platform_driver amvdec_vp9_driver = {
9418 .probe = amvdec_vp9_probe,
9419 .remove = amvdec_vp9_remove,
9420 .driver = {
9421 .name = DRIVER_NAME,
9422#ifdef CONFIG_PM
9423 .pm = &vp9_pm_ops,
9424#endif
9425 }
9426};
9427
9428static struct codec_profile_t amvdec_vp9_profile = {
9429 .name = "vp9",
9430 .profile = ""
9431};
9432
9433static struct codec_profile_t amvdec_vp9_profile_mult;
9434
9435static unsigned char get_data_check_sum
9436 (struct VP9Decoder_s *pbi, int size)
9437{
9438 int jj;
9439 int sum = 0;
9440 u8 *data = NULL;
9441
9442 if (!pbi->chunk->block->is_mapped)
9443 data = codec_mm_vmap(pbi->chunk->block->start +
9444 pbi->chunk->offset, size);
9445 else
9446 data = ((u8 *)pbi->chunk->block->start_virt) +
9447 pbi->chunk->offset;
9448
9449 for (jj = 0; jj < size; jj++)
9450 sum += data[jj];
9451
9452 if (!pbi->chunk->block->is_mapped)
9453 codec_mm_unmap_phyaddr(data);
9454 return sum;
9455}
9456
9457static void dump_data(struct VP9Decoder_s *pbi, int size)
9458{
9459 int jj;
9460 u8 *data = NULL;
9461 int padding_size = pbi->chunk->offset &
9462 (VDEC_FIFO_ALIGN - 1);
9463
9464 if (!pbi->chunk->block->is_mapped)
9465 data = codec_mm_vmap(pbi->chunk->block->start +
9466 pbi->chunk->offset, size);
9467 else
9468 data = ((u8 *)pbi->chunk->block->start_virt) +
9469 pbi->chunk->offset;
9470
9471 vp9_print(pbi, 0, "padding: ");
9472 for (jj = padding_size; jj > 0; jj--)
9473 vp9_print_cont(pbi,
9474 0,
9475 "%02x ", *(data - jj));
9476 vp9_print_cont(pbi, 0, "data adr %p\n",
9477 data);
9478
9479 for (jj = 0; jj < size; jj++) {
9480 if ((jj & 0xf) == 0)
9481 vp9_print(pbi,
9482 0,
9483 "%06x:", jj);
9484 vp9_print_cont(pbi,
9485 0,
9486 "%02x ", data[jj]);
9487 if (((jj + 1) & 0xf) == 0)
9488 vp9_print(pbi,
9489 0,
9490 "\n");
9491 }
9492 vp9_print(pbi,
9493 0,
9494 "\n");
9495
9496 if (!pbi->chunk->block->is_mapped)
9497 codec_mm_unmap_phyaddr(data);
9498}
9499
9500static void vp9_work(struct work_struct *work)
9501{
9502 struct VP9Decoder_s *pbi = container_of(work,
9503 struct VP9Decoder_s, work);
9504 struct vdec_s *vdec = hw_to_vdec(pbi);
9505 /* finished decoding one frame or error,
9506 * notify vdec core to switch context
9507 */
9508 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9509 "%s dec_result %d %x %x %x\n",
9510 __func__,
9511 pbi->dec_result,
9512 READ_VREG(HEVC_STREAM_LEVEL),
9513 READ_VREG(HEVC_STREAM_WR_PTR),
9514 READ_VREG(HEVC_STREAM_RD_PTR));
9515
9516 if (pbi->dec_result == DEC_INIT_PICLIST) {
9517 init_pic_list(pbi);
9518 pbi->pic_list_init_done = true;
9519 return;
9520 }
9521
9522 if (pbi->dec_result == DEC_V4L2_CONTINUE_DECODING) {
9523 struct aml_vcodec_ctx *ctx =
9524 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9525
9526 if (ctx->param_sets_from_ucode) {
9527 reset_process_time(pbi);
9528 if (wait_event_interruptible_timeout(ctx->wq,
9529 ctx->v4l_codec_ready,
9530 msecs_to_jiffies(500)) < 0)
9531 return;
9532 }
9533
9534 continue_decoding(pbi);
9535 pbi->postproc_done = 0;
9536 pbi->process_busy = 0;
9537
9538 return;
9539 }
9540
9541 if (((pbi->dec_result == DEC_RESULT_GET_DATA) ||
9542 (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY))
9543 && (hw_to_vdec(pbi)->next_status !=
9544 VDEC_STATUS_DISCONNECTED)) {
9545 if (!vdec_has_more_input(vdec)) {
9546 pbi->dec_result = DEC_RESULT_EOS;
9547 vdec_schedule_work(&pbi->work);
9548 return;
9549 }
9550
9551 if (pbi->dec_result == DEC_RESULT_GET_DATA) {
9552 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9553 "%s DEC_RESULT_GET_DATA %x %x %x\n",
9554 __func__,
9555 READ_VREG(HEVC_STREAM_LEVEL),
9556 READ_VREG(HEVC_STREAM_WR_PTR),
9557 READ_VREG(HEVC_STREAM_RD_PTR));
9558 vdec_vframe_dirty(vdec, pbi->chunk);
9559 vdec_clean_input(vdec);
9560 }
9561
9562 if (get_free_buf_count(pbi) >=
9563 run_ready_min_buf_num) {
9564 int r;
9565 int decode_size;
9566 r = vdec_prepare_input(vdec, &pbi->chunk);
9567 if (r < 0) {
9568 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9569
9570 vp9_print(pbi,
9571 PRINT_FLAG_VDEC_DETAIL,
9572 "amvdec_vh265: Insufficient data\n");
9573
9574 vdec_schedule_work(&pbi->work);
9575 return;
9576 }
9577 pbi->dec_result = DEC_RESULT_NONE;
9578 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9579 "%s: chunk size 0x%x sum 0x%x\n",
9580 __func__, r,
9581 (debug & PRINT_FLAG_VDEC_STATUS) ?
9582 get_data_check_sum(pbi, r) : 0
9583 );
9584
9585 if (debug & PRINT_FLAG_VDEC_DATA)
9586 dump_data(pbi, pbi->chunk->size);
9587
9588 decode_size = pbi->chunk->size +
9589 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9590
9591 WRITE_VREG(HEVC_DECODE_SIZE,
9592 READ_VREG(HEVC_DECODE_SIZE) + decode_size);
9593
9594 vdec_enable_input(vdec);
9595
9596 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9597
9598 start_process_time(pbi);
9599
9600 } else{
9601 pbi->dec_result = DEC_RESULT_GET_DATA_RETRY;
9602
9603 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9604 "amvdec_vh265: Insufficient data\n");
9605
9606 vdec_schedule_work(&pbi->work);
9607 }
9608 return;
9609 } else if (pbi->dec_result == DEC_RESULT_DONE) {
9610#ifdef SUPPORT_FB_DECODING
9611 if (pbi->used_stage_buf_num > 0) {
9612#ifndef FB_DECODING_TEST_SCHEDULE
9613 if (!is_s2_decoding_finished(pbi)) {
9614 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9615 "s2 decoding not done, check again later\n");
9616 vdec_schedule_work(&pbi->work);
9617 }
9618#endif
9619 inc_s2_pos(pbi);
9620 if (mcrcc_cache_alg_flag)
9621 dump_hit_rate(pbi);
9622 }
9623#endif
9624 /* if (!pbi->ctx_valid)
9625 pbi->ctx_valid = 1; */
9626 pbi->slice_idx++;
9627 pbi->frame_count++;
9628 pbi->process_state = PROC_STATE_INIT;
9629 decode_frame_count[pbi->index] = pbi->frame_count;
9630
9631 if (pbi->mmu_enable)
9632 pbi->used_4k_num =
9633 (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16);
9634 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9635 "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n",
9636 __func__,
9637 pbi->frame_count,
9638 pbi->dec_result,
9639 READ_VREG(HEVC_STREAM_LEVEL),
9640 READ_VREG(HEVC_STREAM_WR_PTR),
9641 READ_VREG(HEVC_STREAM_RD_PTR),
9642 READ_VREG(HEVC_SHIFT_BYTE_COUNT),
9643 READ_VREG(HEVC_SHIFT_BYTE_COUNT) -
9644 pbi->start_shift_bytes
9645 );
9646 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9647 } else if (pbi->dec_result == DEC_RESULT_AGAIN) {
9648 /*
9649 stream base: stream buf empty or timeout
9650 frame base: vdec_prepare_input fail
9651 */
9652 if (!vdec_has_more_input(vdec)) {
9653 pbi->dec_result = DEC_RESULT_EOS;
9654 vdec_schedule_work(&pbi->work);
9655 return;
9656 }
9657 } else if (pbi->dec_result == DEC_RESULT_EOS) {
9658 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9659 "%s: end of stream\n",
9660 __func__);
9661 pbi->eos = 1;
9662 vp9_bufmgr_postproc(pbi);
9663
9664 if (pbi->is_used_v4l)
9665 notify_v4l_eos(hw_to_vdec(pbi));
9666
9667 vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk);
9668 } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) {
9669 vp9_print(pbi, PRINT_FLAG_VDEC_STATUS,
9670 "%s: force exit\n",
9671 __func__);
9672 if (pbi->stat & STAT_VDEC_RUN) {
9673 amhevc_stop();
9674 pbi->stat &= ~STAT_VDEC_RUN;
9675 }
9676
9677 if (pbi->stat & STAT_ISR_REG) {
9678#ifdef MULTI_INSTANCE_SUPPORT
9679 if (!pbi->m_ins_flag)
9680#endif
9681 WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0);
9682 vdec_free_irq(VDEC_IRQ_0, (void *)pbi);
9683 pbi->stat &= ~STAT_ISR_REG;
9684 }
9685 }
9686 if (pbi->stat & STAT_VDEC_RUN) {
9687 amhevc_stop();
9688 pbi->stat &= ~STAT_VDEC_RUN;
9689 }
9690
9691 if (pbi->stat & STAT_TIMER_ARM) {
9692 del_timer_sync(&pbi->timer);
9693 pbi->stat &= ~STAT_TIMER_ARM;
9694 }
9695 /* mark itself has all HW resource released and input released */
9696#ifdef SUPPORT_FB_DECODING
9697 if (pbi->used_stage_buf_num > 0)
9698 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK);
9699 else
9700 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9701 | CORE_MASK_HEVC
9702 | CORE_MASK_HEVC_FRONT
9703 | CORE_MASK_HEVC_BACK
9704 );
9705#else
9706 if (vdec->parallel_dec == 1)
9707 vdec_core_finish_run(vdec, CORE_MASK_HEVC);
9708 else
9709 vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1
9710 | CORE_MASK_HEVC);
9711#endif
9712 trigger_schedule(pbi);
9713}
9714
9715static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi)
9716{
9717 /* new to do ... */
9718#if (!defined SUPPORT_FB_DECODING)
9719 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9720#elif (defined FB_DECODING_TEST_SCHEDULE)
9721 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9722#else
9723 if (pbi->used_stage_buf_num > 0)
9724 vvp9_prot_init(pbi, HW_MASK_FRONT);
9725 else
9726 vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK);
9727#endif
9728 return 0;
9729}
9730static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask)
9731{
9732 struct VP9Decoder_s *pbi =
9733 (struct VP9Decoder_s *)vdec->private;
9734 int tvp = vdec_secure(hw_to_vdec(pbi)) ?
9735 CODEC_MM_FLAGS_TVP : 0;
9736 unsigned long ret = 0;
9737
9738 if (!(pbi->pic_list_init_done && pbi->pic_list_init_done2) || pbi->eos)
9739 return ret;
9740 if (!pbi->first_sc_checked && pbi->mmu_enable) {
9741 int size = decoder_mmu_box_sc_check(pbi->mmu_box, tvp);
9742 pbi->first_sc_checked = 1;
9743 vp9_print(pbi, 0, "vp9 cached=%d need_size=%d speed= %d ms\n",
9744 size, (pbi->need_cache_size >> PAGE_SHIFT),
9745 (int)(get_jiffies_64() - pbi->sc_start_time) * 1000/HZ);
9746 }
9747
9748#ifdef SUPPORT_FB_DECODING
9749 if (pbi->used_stage_buf_num > 0) {
9750 if (mask & CORE_MASK_HEVC_FRONT) {
9751 if (get_free_stage_buf_num(pbi) > 0
9752 && mv_buf_available(pbi))
9753 ret |= CORE_MASK_HEVC_FRONT;
9754 }
9755 if (mask & CORE_MASK_HEVC_BACK) {
9756 if (s2_buf_available(pbi) &&
9757 (get_free_buf_count(pbi) >=
9758 run_ready_min_buf_num)) {
9759 ret |= CORE_MASK_HEVC_BACK;
9760 pbi->back_not_run_ready = 0;
9761 } else
9762 pbi->back_not_run_ready = 1;
9763#if 0
9764 if (get_free_buf_count(pbi) <
9765 run_ready_min_buf_num)
9766 dump_pic_list(pbi);
9767#endif
9768 }
9769 } else if (get_free_buf_count(pbi) >=
9770 run_ready_min_buf_num)
9771 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC
9772 | CORE_MASK_HEVC_FRONT
9773 | CORE_MASK_HEVC_BACK;
9774
9775 if (ret & CORE_MASK_HEVC_FRONT)
9776 not_run_ready[pbi->index] = 0;
9777 else
9778 not_run_ready[pbi->index]++;
9779
9780 if (ret & CORE_MASK_HEVC_BACK)
9781 not_run2_ready[pbi->index] = 0;
9782 else
9783 not_run2_ready[pbi->index]++;
9784
9785 vp9_print(pbi,
9786 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n",
9787 __func__, mask, ret,
9788 get_free_stage_buf_num(pbi),
9789 mv_buf_available(pbi),
9790 s2_buf_available(pbi),
9791 get_free_buf_count(pbi)
9792 );
9793
9794 return ret;
9795
9796#else
9797 if (get_free_buf_count(pbi) >=
9798 run_ready_min_buf_num) {
9799 if (vdec->parallel_dec == 1)
9800 ret = CORE_MASK_HEVC;
9801 else
9802 ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC;
9803 }
9804
9805 if (pbi->is_used_v4l) {
9806 struct aml_vcodec_ctx *ctx =
9807 (struct aml_vcodec_ctx *)(pbi->v4l2_ctx);
9808
9809 if (ctx->param_sets_from_ucode &&
9810 !ctx->v4l_codec_ready &&
9811 pbi->v4l_params_parsed) {
9812 ret = 0; /*the params has parsed.*/
9813 } else if (!ctx->v4l_codec_dpb_ready) {
9814 if (v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx) <
9815 run_ready_min_buf_num)
9816 ret = 0;
9817 }
9818 }
9819
9820 if (ret)
9821 not_run_ready[pbi->index] = 0;
9822 else
9823 not_run_ready[pbi->index]++;
9824
9825 vp9_print(pbi,
9826 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n",
9827 __func__, mask, ret);
9828 return ret;
9829#endif
9830}
9831
9832static void run_front(struct vdec_s *vdec)
9833{
9834 struct VP9Decoder_s *pbi =
9835 (struct VP9Decoder_s *)vdec->private;
9836 int ret, size;
9837
9838 run_count[pbi->index]++;
9839 /* pbi->chunk = vdec_prepare_input(vdec); */
9840#if (!defined SUPPORT_FB_DECODING)
9841 hevc_reset_core(vdec);
9842#elif (defined FB_DECODING_TEST_SCHEDULE)
9843 hevc_reset_core(vdec);
9844#else
9845 if (pbi->used_stage_buf_num > 0)
9846 fb_reset_core(vdec, HW_MASK_FRONT);
9847 else
9848 hevc_reset_core(vdec);
9849#endif
9850
9851 size = vdec_prepare_input(vdec, &pbi->chunk);
9852 if (size < 0) {
9853 input_empty[pbi->index]++;
9854
9855 pbi->dec_result = DEC_RESULT_AGAIN;
9856
9857 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9858 "ammvdec_vh265: Insufficient data\n");
9859
9860 vdec_schedule_work(&pbi->work);
9861 return;
9862 }
9863
9864 input_empty[pbi->index] = 0;
9865 pbi->dec_result = DEC_RESULT_NONE;
9866 pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT);
9867
9868 if (debug & PRINT_FLAG_VDEC_STATUS) {
9869 int ii;
9870 vp9_print(pbi, 0,
9871 "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x",
9872 __func__,
9873 pbi->frame_count, size,
9874 pbi->chunk ? pbi->chunk->size : 0,
9875 pbi->chunk ? pbi->chunk->offset : 0,
9876 pbi->chunk ? ((vdec_frame_based(vdec) &&
9877 (debug & PRINT_FLAG_VDEC_STATUS)) ?
9878 get_data_check_sum(pbi, size) : 0) : 0,
9879 READ_VREG(HEVC_STREAM_START_ADDR),
9880 READ_VREG(HEVC_STREAM_END_ADDR),
9881 READ_VREG(HEVC_STREAM_LEVEL),
9882 READ_VREG(HEVC_STREAM_WR_PTR),
9883 READ_VREG(HEVC_STREAM_RD_PTR),
9884 pbi->start_shift_bytes);
9885 if (vdec_frame_based(vdec) && pbi->chunk) {
9886 u8 *data = NULL;
9887
9888 if (!pbi->chunk->block->is_mapped)
9889 data = codec_mm_vmap(pbi->chunk->block->start +
9890 pbi->chunk->offset, 8);
9891 else
9892 data = ((u8 *)pbi->chunk->block->start_virt) +
9893 pbi->chunk->offset;
9894
9895 vp9_print_cont(pbi, 0, "data adr %p:",
9896 data);
9897 for (ii = 0; ii < 8; ii++)
9898 vp9_print_cont(pbi, 0, "%02x ",
9899 data[ii]);
9900
9901 if (!pbi->chunk->block->is_mapped)
9902 codec_mm_unmap_phyaddr(data);
9903 }
9904 vp9_print_cont(pbi, 0, "\r\n");
9905 }
9906 if (vdec->mc_loaded) {
9907 /*firmware have load before,
9908 and not changes to another.
9909 ignore reload.
9910 */
9911 } else {
9912 ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data);
9913 if (ret < 0) {
9914 amhevc_disable();
9915 vp9_print(pbi, PRINT_FLAG_ERROR,
9916 "VP9: the %s fw loading failed, err: %x\n",
9917 tee_enabled() ? "TEE" : "local", ret);
9918 pbi->dec_result = DEC_RESULT_FORCE_EXIT;
9919 vdec_schedule_work(&pbi->work);
9920 return;
9921 }
9922 vdec->mc_loaded = 1;
9923 vdec->mc_type = VFORMAT_VP9;
9924 }
9925
9926 if (vp9_hw_ctx_restore(pbi) < 0) {
9927 vdec_schedule_work(&pbi->work);
9928 return;
9929 }
9930
9931 vdec_enable_input(vdec);
9932
9933 WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE);
9934
9935 if (vdec_frame_based(vdec)) {
9936 if (debug & PRINT_FLAG_VDEC_DATA)
9937 dump_data(pbi, pbi->chunk->size);
9938
9939 WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0);
9940 size = pbi->chunk->size +
9941 (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1));
9942 }
9943 WRITE_VREG(HEVC_DECODE_SIZE, size);
9944 WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx);
9945 pbi->init_flag = 1;
9946
9947 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
9948 "%s: start hevc (%x %x %x)\n",
9949 __func__,
9950 READ_VREG(HEVC_DEC_STATUS_REG),
9951 READ_VREG(HEVC_MPC_E),
9952 READ_VREG(HEVC_MPSR));
9953
9954 start_process_time(pbi);
9955 mod_timer(&pbi->timer, jiffies);
9956 pbi->stat |= STAT_TIMER_ARM;
9957 pbi->stat |= STAT_ISR_REG;
9958 amhevc_start();
9959 pbi->stat |= STAT_VDEC_RUN;
9960}
9961
9962#ifdef SUPPORT_FB_DECODING
9963static void mpred_process(struct VP9Decoder_s *pbi)
9964{
9965 union param_u *params = &pbi->s1_param;
9966 unsigned char use_prev_frame_mvs =
9967 !params->p.error_resilient_mode &&
9968 params->p.width == pbi->s1_width &&
9969 params->p.height == pbi->s1_height &&
9970 !pbi->s1_intra_only &&
9971 pbi->s1_last_show_frame &&
9972 (pbi->s1_frame_type != KEY_FRAME);
9973 pbi->s1_width = params->p.width;
9974 pbi->s1_height = params->p.height;
9975 pbi->s1_frame_type = params->p.frame_type;
9976 pbi->s1_intra_only =
9977 (params->p.show_frame ||
9978 params->p.show_existing_frame)
9979 ? 0 : params->p.intra_only;
9980 if ((pbi->s1_frame_type != KEY_FRAME)
9981 && (!pbi->s1_intra_only)) {
9982 unsigned int data32;
9983 int mpred_mv_rd_end_addr;
9984
9985 mpred_mv_rd_end_addr =
9986 pbi->s1_mpred_mv_wr_start_addr_pre
9987 + (pbi->lcu_total * MV_MEM_UNIT);
9988
9989 WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412);
9990 WRITE_VREG(HEVC_MPRED_ABV_START_ADDR,
9991 pbi->work_space_buf->
9992 mpred_above.buf_start);
9993
9994 data32 = READ_VREG(HEVC_MPRED_CTRL4);
9995
9996 data32 &= (~(1 << 6));
9997 data32 |= (use_prev_frame_mvs << 6);
9998 WRITE_VREG(HEVC_MPRED_CTRL4, data32);
9999
10000 WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR,
10001 pbi->s1_mpred_mv_wr_start_addr);
10002 WRITE_VREG(HEVC_MPRED_MV_WPTR,
10003 pbi->s1_mpred_mv_wr_start_addr);
10004
10005 WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR,
10006 pbi->s1_mpred_mv_wr_start_addr_pre);
10007 WRITE_VREG(HEVC_MPRED_MV_RPTR,
10008 pbi->s1_mpred_mv_wr_start_addr_pre);
10009
10010 WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR,
10011 mpred_mv_rd_end_addr);
10012
10013 } else
10014 clear_mpred_hw(pbi);
10015
10016 if (!params->p.show_existing_frame) {
10017 pbi->s1_mpred_mv_wr_start_addr_pre =
10018 pbi->s1_mpred_mv_wr_start_addr;
10019 pbi->s1_last_show_frame =
10020 params->p.show_frame;
10021 if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM)
10022 put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre);
10023 pbi->s1_mv_buf_index_pre_pre =
10024 pbi->s1_mv_buf_index_pre;
10025 pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index;
10026 } else
10027 put_mv_buf(pbi, &pbi->s1_mv_buf_index);
10028}
10029
10030static void vp9_s1_work(struct work_struct *s1_work)
10031{
10032 struct VP9Decoder_s *pbi = container_of(s1_work,
10033 struct VP9Decoder_s, s1_work);
10034 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL,
10035 "%s dec_s1_result %d\n",
10036 __func__,
10037 pbi->dec_s1_result);
10038
10039#ifdef FB_DECODING_TEST_SCHEDULE
10040 if (pbi->dec_s1_result ==
10041 DEC_S1_RESULT_TEST_TRIGGER_DONE) {
10042 pbi->s1_test_cmd = TEST_SET_PIC_DONE;
10043 WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1);
10044 }
10045#endif
10046 if (pbi->dec_s1_result == DEC_S1_RESULT_DONE ||
10047 pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) {
10048
10049 vdec_core_finish_run(hw_to_vdec(pbi),
10050 CORE_MASK_HEVC_FRONT);
10051
10052 trigger_schedule(pbi);
10053 /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/
10054 }
10055
10056}
10057
10058static void run_back(struct vdec_s *vdec)
10059{
10060 struct VP9Decoder_s *pbi =
10061 (struct VP9Decoder_s *)vdec->private;
10062 int i;
10063 run2_count[pbi->index]++;
10064 if (debug & PRINT_FLAG_VDEC_STATUS) {
10065 vp9_print(pbi, 0,
10066 "%s", __func__);
10067 }
10068 pbi->run2_busy = 1;
10069#ifndef FB_DECODING_TEST_SCHEDULE
10070 fb_reset_core(vdec, HW_MASK_BACK);
10071
10072 vvp9_prot_init(pbi, HW_MASK_BACK);
10073#endif
10074 vp9_recycle_mmu_buf_tail(pbi);
10075
10076 if (pbi->frame_count > 0)
10077 vp9_bufmgr_postproc(pbi);
10078
10079 if (get_s2_buf(pbi) >= 0) {
10080 for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) {
10081 int ii;
10082 for (ii = 0; ii < 4; ii++)
10083 vp9_param.l.data[i + ii] =
10084 pbi->s2_buf->rpm[i + 3 - ii];
10085 }
10086#ifndef FB_DECODING_TEST_SCHEDULE
10087 WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR,
10088 pbi->stage_mmu_map_phy_addr +
10089 pbi->s2_buf->index * STAGE_MMU_MAP_SIZE);
10090#endif
10091 continue_decoding(pbi);
10092 }
10093 pbi->run2_busy = 0;
10094}
10095#endif
10096
10097static void run(struct vdec_s *vdec, unsigned long mask,
10098 void (*callback)(struct vdec_s *, void *), void *arg)
10099{
10100 struct VP9Decoder_s *pbi =
10101 (struct VP9Decoder_s *)vdec->private;
10102
10103 vp9_print(pbi,
10104 PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n",
10105 __func__, mask);
10106
10107 run_count[pbi->index]++;
10108 pbi->vdec_cb_arg = arg;
10109 pbi->vdec_cb = callback;
10110#ifdef SUPPORT_FB_DECODING
10111 if ((mask & CORE_MASK_HEVC) ||
10112 (mask & CORE_MASK_HEVC_FRONT))
10113 run_front(vdec);
10114
10115 if ((pbi->used_stage_buf_num > 0)
10116 && (mask & CORE_MASK_HEVC_BACK))
10117 run_back(vdec);
10118#else
10119 run_front(vdec);
10120#endif
10121}
10122
10123static void init_frame_bufs(struct VP9Decoder_s *pbi)
10124{
10125 struct vdec_s *vdec = hw_to_vdec(pbi);
10126 struct VP9_Common_s *const cm = &pbi->common;
10127 struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs;
10128 int i;
10129
10130 for (i = 0; i < pbi->used_buf_num; ++i) {
10131 frame_bufs[i].ref_count = 0;
10132 frame_bufs[i].buf.vf_ref = 0;
10133 frame_bufs[i].buf.decode_idx = 0;
10134 frame_bufs[i].buf.cma_alloc_addr = 0;
10135 frame_bufs[i].buf.index = i;
10136 }
10137
10138 if (vdec->parallel_dec == 1) {
10139 for (i = 0; i < FRAME_BUFFERS; i++) {
10140 vdec->free_canvas_ex
10141 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10142 vdec->id);
10143 vdec->free_canvas_ex
10144 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10145 vdec->id);
10146 }
10147 }
10148}
10149
10150static void reset(struct vdec_s *vdec)
10151{
10152 struct VP9Decoder_s *pbi =
10153 (struct VP9Decoder_s *)vdec->private;
10154
10155 cancel_work_sync(&pbi->work);
10156 if (pbi->stat & STAT_VDEC_RUN) {
10157 amhevc_stop();
10158 pbi->stat &= ~STAT_VDEC_RUN;
10159 }
10160
10161 if (pbi->stat & STAT_TIMER_ARM) {
10162 del_timer_sync(&pbi->timer);
10163 pbi->stat &= ~STAT_TIMER_ARM;
10164 }
10165 pbi->dec_result = DEC_RESULT_NONE;
10166 reset_process_time(pbi);
10167 dealloc_mv_bufs(pbi);
10168 vp9_local_uninit(pbi);
10169 if (vvp9_local_init(pbi) < 0)
10170 vp9_print(pbi, 0, "%s local_init failed \r\n", __func__);
10171 init_frame_bufs(pbi);
10172
10173 pbi->eos = 0;
10174
10175 vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__);
10176}
10177
10178static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq)
10179{
10180 struct VP9Decoder_s *pbi =
10181 (struct VP9Decoder_s *)vdec->private;
10182 return vvp9_isr(0, pbi);
10183}
10184
10185static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq)
10186{
10187 struct VP9Decoder_s *pbi =
10188 (struct VP9Decoder_s *)vdec->private;
10189 return vvp9_isr_thread_fn(0, pbi);
10190}
10191
10192static void vp9_dump_state(struct vdec_s *vdec)
10193{
10194 struct VP9Decoder_s *pbi =
10195 (struct VP9Decoder_s *)vdec->private;
10196 struct VP9_Common_s *const cm = &pbi->common;
10197 int i;
10198 vp9_print(pbi, 0, "====== %s\n", __func__);
10199
10200 vp9_print(pbi, 0,
10201 "width/height (%d/%d), used_buf_num %d\n",
10202 cm->width,
10203 cm->height,
10204 pbi->used_buf_num
10205 );
10206
10207 vp9_print(pbi, 0,
10208 "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d low_latency %d no_head %d \n",
10209 input_frame_based(vdec),
10210 pbi->eos,
10211 pbi->dec_result,
10212 decode_frame_count[pbi->index],
10213 display_frame_count[pbi->index],
10214 run_count[pbi->index],
10215 not_run_ready[pbi->index],
10216 input_empty[pbi->index],
10217 pbi->low_latency_flag,
10218 pbi->no_head
10219 );
10220
10221 if (vf_get_receiver(vdec->vf_provider_name)) {
10222 enum receviver_start_e state =
10223 vf_notify_receiver(vdec->vf_provider_name,
10224 VFRAME_EVENT_PROVIDER_QUREY_STATE,
10225 NULL);
10226 vp9_print(pbi, 0,
10227 "\nreceiver(%s) state %d\n",
10228 vdec->vf_provider_name,
10229 state);
10230 }
10231
10232 vp9_print(pbi, 0,
10233 "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n",
10234 __func__,
10235 kfifo_len(&pbi->newframe_q),
10236 VF_POOL_SIZE,
10237 kfifo_len(&pbi->display_q),
10238 VF_POOL_SIZE,
10239 pbi->vf_pre_count,
10240 pbi->vf_get_count,
10241 pbi->vf_put_count,
10242 get_free_buf_count(pbi),
10243 run_ready_min_buf_num
10244 );
10245
10246 dump_pic_list(pbi);
10247
10248 for (i = 0; i < MAX_BUF_NUM; i++) {
10249 vp9_print(pbi, 0,
10250 "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n",
10251 i,
10252 pbi->m_mv_BUF[i].start_adr,
10253 pbi->m_mv_BUF[i].size,
10254 pbi->m_mv_BUF[i].used_flag);
10255 }
10256
10257 vp9_print(pbi, 0,
10258 "HEVC_DEC_STATUS_REG=0x%x\n",
10259 READ_VREG(HEVC_DEC_STATUS_REG));
10260 vp9_print(pbi, 0,
10261 "HEVC_MPC_E=0x%x\n",
10262 READ_VREG(HEVC_MPC_E));
10263 vp9_print(pbi, 0,
10264 "DECODE_MODE=0x%x\n",
10265 READ_VREG(DECODE_MODE));
10266 vp9_print(pbi, 0,
10267 "NAL_SEARCH_CTL=0x%x\n",
10268 READ_VREG(NAL_SEARCH_CTL));
10269 vp9_print(pbi, 0,
10270 "HEVC_PARSER_LCU_START=0x%x\n",
10271 READ_VREG(HEVC_PARSER_LCU_START));
10272 vp9_print(pbi, 0,
10273 "HEVC_DECODE_SIZE=0x%x\n",
10274 READ_VREG(HEVC_DECODE_SIZE));
10275 vp9_print(pbi, 0,
10276 "HEVC_SHIFT_BYTE_COUNT=0x%x\n",
10277 READ_VREG(HEVC_SHIFT_BYTE_COUNT));
10278 vp9_print(pbi, 0,
10279 "HEVC_STREAM_START_ADDR=0x%x\n",
10280 READ_VREG(HEVC_STREAM_START_ADDR));
10281 vp9_print(pbi, 0,
10282 "HEVC_STREAM_END_ADDR=0x%x\n",
10283 READ_VREG(HEVC_STREAM_END_ADDR));
10284 vp9_print(pbi, 0,
10285 "HEVC_STREAM_LEVEL=0x%x\n",
10286 READ_VREG(HEVC_STREAM_LEVEL));
10287 vp9_print(pbi, 0,
10288 "HEVC_STREAM_WR_PTR=0x%x\n",
10289 READ_VREG(HEVC_STREAM_WR_PTR));
10290 vp9_print(pbi, 0,
10291 "HEVC_STREAM_RD_PTR=0x%x\n",
10292 READ_VREG(HEVC_STREAM_RD_PTR));
10293 vp9_print(pbi, 0,
10294 "PARSER_VIDEO_RP=0x%x\n",
10295 READ_PARSER_REG(PARSER_VIDEO_RP));
10296 vp9_print(pbi, 0,
10297 "PARSER_VIDEO_WP=0x%x\n",
10298 READ_PARSER_REG(PARSER_VIDEO_WP));
10299
10300 if (input_frame_based(vdec) &&
10301 (debug & PRINT_FLAG_VDEC_DATA)
10302 ) {
10303 int jj;
10304 if (pbi->chunk && pbi->chunk->block &&
10305 pbi->chunk->size > 0) {
10306 u8 *data = NULL;
10307
10308 if (!pbi->chunk->block->is_mapped)
10309 data = codec_mm_vmap(
10310 pbi->chunk->block->start +
10311 pbi->chunk->offset,
10312 pbi->chunk->size);
10313 else
10314 data = ((u8 *)pbi->chunk->block->start_virt)
10315 + pbi->chunk->offset;
10316 vp9_print(pbi, 0,
10317 "frame data size 0x%x\n",
10318 pbi->chunk->size);
10319 for (jj = 0; jj < pbi->chunk->size; jj++) {
10320 if ((jj & 0xf) == 0)
10321 vp9_print(pbi, 0,
10322 "%06x:", jj);
10323 vp9_print_cont(pbi, 0,
10324 "%02x ", data[jj]);
10325 if (((jj + 1) & 0xf) == 0)
10326 vp9_print_cont(pbi, 0,
10327 "\n");
10328 }
10329
10330 if (!pbi->chunk->block->is_mapped)
10331 codec_mm_unmap_phyaddr(data);
10332 }
10333 }
10334
10335}
10336
10337static int ammvdec_vp9_probe(struct platform_device *pdev)
10338{
10339 struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
10340 int ret;
10341 int config_val;
10342 struct vframe_content_light_level_s content_light_level;
10343 struct vframe_master_display_colour_s vf_dp;
10344
10345 struct BUF_s BUF[MAX_BUF_NUM];
10346 struct VP9Decoder_s *pbi = NULL;
10347 pr_debug("%s\n", __func__);
10348
10349 if (pdata == NULL) {
10350 pr_info("\nammvdec_vp9 memory resource undefined.\n");
10351 return -EFAULT;
10352 }
10353 /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev,
10354 sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
10355 memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
10356 pbi = vmalloc(sizeof(struct VP9Decoder_s));
10357 if (pbi == NULL) {
10358 pr_info("\nammvdec_vp9 device data allocation failed\n");
10359 return -ENOMEM;
10360 }
10361 memset(pbi, 0, sizeof(struct VP9Decoder_s));
10362
10363 /* the ctx from v4l2 driver. */
10364 pbi->v4l2_ctx = pdata->private;
10365
10366 pdata->private = pbi;
10367 pdata->dec_status = vvp9_dec_status;
10368 /* pdata->set_trickmode = set_trickmode; */
10369 pdata->run_ready = run_ready;
10370 pdata->run = run;
10371 pdata->reset = reset;
10372 pdata->irq_handler = vp9_irq_cb;
10373 pdata->threaded_irq_handler = vp9_threaded_irq_cb;
10374 pdata->dump_state = vp9_dump_state;
10375
10376 memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10377 memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
10378
10379 pbi->index = pdev->id;
10380
10381 if (pdata->use_vfm_path)
10382 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10383 VFM_DEC_PROVIDER_NAME);
10384 else
10385 snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE,
10386 MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff);
10387
10388 vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name,
10389 &vvp9_vf_provider, pbi);
10390
10391 pbi->provider_name = pdata->vf_provider_name;
10392 platform_set_drvdata(pdev, pdata);
10393
10394 pbi->platform_dev = pdev;
10395 pbi->video_signal_type = 0;
10396 pbi->m_ins_flag = 1;
10397 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX)
10398 pbi->stat |= VP9_TRIGGER_FRAME_ENABLE;
10399
10400 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10401 pbi->max_pic_w = 8192;
10402 pbi->max_pic_h = 4608;
10403 } else {
10404 pbi->max_pic_w = 4096;
10405 pbi->max_pic_h = 2304;
10406 }
10407#if 1
10408 if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 &&
10409 pdata->config_len) {
10410#ifdef MULTI_INSTANCE_SUPPORT
10411 int vp9_buf_width = 0;
10412 int vp9_buf_height = 0;
10413 /*use ptr config for doubel_write_mode, etc*/
10414 vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config);
10415 if (get_config_int(pdata->config, "vp9_double_write_mode",
10416 &config_val) == 0)
10417 pbi->double_write_mode = config_val;
10418 else
10419 pbi->double_write_mode = double_write_mode;
10420
10421 if (get_config_int(pdata->config, "save_buffer_mode",
10422 &config_val) == 0)
10423 pbi->save_buffer_mode = config_val;
10424 else
10425 pbi->save_buffer_mode = 0;
10426 if (get_config_int(pdata->config, "vp9_buf_width",
10427 &config_val) == 0) {
10428 vp9_buf_width = config_val;
10429 }
10430 if (get_config_int(pdata->config, "vp9_buf_height",
10431 &config_val) == 0) {
10432 vp9_buf_height = config_val;
10433 }
10434
10435 if (get_config_int(pdata->config, "no_head",
10436 &config_val) == 0)
10437 pbi->no_head = config_val;
10438 else
10439 pbi->no_head = no_head;
10440
10441 /*use ptr config for max_pic_w, etc*/
10442 if (get_config_int(pdata->config, "vp9_max_pic_w",
10443 &config_val) == 0) {
10444 pbi->max_pic_w = config_val;
10445 }
10446 if (get_config_int(pdata->config, "vp9_max_pic_h",
10447 &config_val) == 0) {
10448 pbi->max_pic_h = config_val;
10449 }
10450 if ((pbi->max_pic_w * pbi->max_pic_h)
10451 < (vp9_buf_width * vp9_buf_height)) {
10452 pbi->max_pic_w = vp9_buf_width;
10453 pbi->max_pic_h = vp9_buf_height;
10454 vp9_print(pbi, 0, "use buf resolution\n");
10455 }
10456
10457 if (get_config_int(pdata->config,
10458 "parm_v4l_codec_enable",
10459 &config_val) == 0)
10460 pbi->is_used_v4l = config_val;
10461
10462 if (get_config_int(pdata->config,
10463 "parm_v4l_buffer_margin",
10464 &config_val) == 0)
10465 pbi->dynamic_buf_num_margin = config_val;
10466
10467 if (get_config_int(pdata->config,
10468 "parm_v4l_canvas_mem_mode",
10469 &config_val) == 0)
10470 pbi->mem_map_mode = config_val;
10471#endif
10472 if (get_config_int(pdata->config, "HDRStaticInfo",
10473 &vf_dp.present_flag) == 0
10474 && vf_dp.present_flag == 1) {
10475 get_config_int(pdata->config, "mG.x",
10476 &vf_dp.primaries[0][0]);
10477 get_config_int(pdata->config, "mG.y",
10478 &vf_dp.primaries[0][1]);
10479 get_config_int(pdata->config, "mB.x",
10480 &vf_dp.primaries[1][0]);
10481 get_config_int(pdata->config, "mB.y",
10482 &vf_dp.primaries[1][1]);
10483 get_config_int(pdata->config, "mR.x",
10484 &vf_dp.primaries[2][0]);
10485 get_config_int(pdata->config, "mR.y",
10486 &vf_dp.primaries[2][1]);
10487 get_config_int(pdata->config, "mW.x",
10488 &vf_dp.white_point[0]);
10489 get_config_int(pdata->config, "mW.y",
10490 &vf_dp.white_point[1]);
10491 get_config_int(pdata->config, "mMaxDL",
10492 &vf_dp.luminance[0]);
10493 get_config_int(pdata->config, "mMinDL",
10494 &vf_dp.luminance[1]);
10495 vf_dp.content_light_level.present_flag = 1;
10496 get_config_int(pdata->config, "mMaxCLL",
10497 &content_light_level.max_content);
10498 get_config_int(pdata->config, "mMaxFALL",
10499 &content_light_level.max_pic_average);
10500 vf_dp.content_light_level = content_light_level;
10501 pbi->video_signal_type = (1 << 29)
10502 | (5 << 26) /* unspecified */
10503 | (0 << 25) /* limit */
10504 | (1 << 24) /* color available */
10505 | (9 << 16) /* 2020 */
10506 | (16 << 8) /* 2084 */
10507 | (9 << 0); /* 2020 */
10508 }
10509 pbi->vf_dp = vf_dp;
10510 } else
10511#endif
10512 {
10513 /*pbi->vvp9_amstream_dec_info.width = 0;
10514 pbi->vvp9_amstream_dec_info.height = 0;
10515 pbi->vvp9_amstream_dec_info.rate = 30;*/
10516 pbi->double_write_mode = double_write_mode;
10517 }
10518
10519 if (!pbi->is_used_v4l) {
10520 pbi->mem_map_mode = mem_map_mode;
10521 }
10522
10523 if (is_oversize(pbi->max_pic_w, pbi->max_pic_h)) {
10524 pr_err("over size: %dx%d, probe failed\n",
10525 pbi->max_pic_w, pbi->max_pic_h);
10526 return -1;
10527 }
10528 pbi->mmu_enable = 1;
10529 video_signal_type = pbi->video_signal_type;
10530
10531 if (pdata->sys_info) {
10532 pbi->vvp9_amstream_dec_info = *pdata->sys_info;
10533 } else {
10534 pbi->vvp9_amstream_dec_info.width = 0;
10535 pbi->vvp9_amstream_dec_info.height = 0;
10536 pbi->vvp9_amstream_dec_info.rate = 30;
10537 }
10538 pbi->low_latency_flag = 1;
10539
10540 vp9_print(pbi, 0,
10541 "no_head %d low_latency %d\n",
10542 pbi->no_head, pbi->low_latency_flag);
10543#if 0
10544 pbi->buf_start = pdata->mem_start;
10545 pbi->buf_size = pdata->mem_end - pdata->mem_start + 1;
10546#else
10547 if (amvdec_vp9_mmu_init(pbi) < 0) {
10548 pr_err("vp9 alloc bmmu box failed!!\n");
10549 /* devm_kfree(&pdev->dev, (void *)pbi); */
10550 vfree((void *)pbi);
10551 pdata->dec_status = NULL;
10552 return -1;
10553 }
10554
10555 pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE;
10556 ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID,
10557 pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME,
10558 &pbi->cma_alloc_addr);
10559 if (ret < 0) {
10560 uninit_mmu_buffers(pbi);
10561 /* devm_kfree(&pdev->dev, (void *)pbi); */
10562 vfree((void *)pbi);
10563 pdata->dec_status = NULL;
10564 return ret;
10565 }
10566 pbi->buf_start = pbi->cma_alloc_addr;
10567 pbi->buf_size = work_buf_size;
10568#endif
10569
10570 pbi->init_flag = 0;
10571 pbi->first_sc_checked = 0;
10572 pbi->fatal_error = 0;
10573 pbi->show_frame_num = 0;
10574
10575 if (debug) {
10576 pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n",
10577 pbi->buf_start,
10578 pbi->buf_size);
10579 }
10580
10581 pbi->cma_dev = pdata->cma_dev;
10582 if (vvp9_init(pdata) < 0) {
10583 pr_info("\namvdec_vp9 init failed.\n");
10584 vp9_local_uninit(pbi);
10585 uninit_mmu_buffers(pbi);
10586 /* devm_kfree(&pdev->dev, (void *)pbi); */
10587 vfree((void *)pbi);
10588 pdata->dec_status = NULL;
10589 return -ENODEV;
10590 }
10591 vdec_set_prepare_level(pdata, start_decode_buf_level);
10592 hevc_source_changed(VFORMAT_VP9,
10593 4096, 2048, 60);
10594#ifdef SUPPORT_FB_DECODING
10595 if (pbi->used_stage_buf_num > 0)
10596 vdec_core_request(pdata,
10597 CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK);
10598 else
10599 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10600 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10601 | CORE_MASK_COMBINE);
10602#else
10603 if (pdata->parallel_dec == 1)
10604 vdec_core_request(pdata, CORE_MASK_HEVC);
10605 else
10606 vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10607 | CORE_MASK_COMBINE);
10608#endif
10609 pbi->pic_list_init_done2 = true;
10610 return 0;
10611}
10612
10613static int ammvdec_vp9_remove(struct platform_device *pdev)
10614{
10615 struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)
10616 (((struct vdec_s *)(platform_get_drvdata(pdev)))->private);
10617 struct vdec_s *vdec = hw_to_vdec(pbi);
10618 int i;
10619 if (debug)
10620 pr_info("amvdec_vp9_remove\n");
10621
10622 vmvp9_stop(pbi);
10623
10624#ifdef SUPPORT_FB_DECODING
10625 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC
10626 | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK
10627 );
10628#else
10629 if (vdec->parallel_dec == 1)
10630 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_HEVC);
10631 else
10632 vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC);
10633#endif
10634 vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED);
10635
10636 if (vdec->parallel_dec == 1) {
10637 for (i = 0; i < FRAME_BUFFERS; i++) {
10638 vdec->free_canvas_ex
10639 (pbi->common.buffer_pool->frame_bufs[i].buf.y_canvas_index,
10640 vdec->id);
10641 vdec->free_canvas_ex
10642 (pbi->common.buffer_pool->frame_bufs[i].buf.uv_canvas_index,
10643 vdec->id);
10644 }
10645 }
10646
10647
10648#ifdef DEBUG_PTS
10649 pr_info("pts missed %ld, pts hit %ld, duration %d\n",
10650 pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
10651#endif
10652 mem_map_mode = 0;
10653
10654 /* devm_kfree(&pdev->dev, (void *)pbi); */
10655 vfree((void *)pbi);
10656 return 0;
10657}
10658
10659static struct platform_driver ammvdec_vp9_driver = {
10660 .probe = ammvdec_vp9_probe,
10661 .remove = ammvdec_vp9_remove,
10662 .driver = {
10663 .name = MULTI_DRIVER_NAME,
10664#ifdef CONFIG_PM
10665 .pm = &vp9_pm_ops,
10666#endif
10667 }
10668};
10669#endif
10670static struct mconfig vp9_configs[] = {
10671 MC_PU32("bit_depth_luma", &bit_depth_luma),
10672 MC_PU32("bit_depth_chroma", &bit_depth_chroma),
10673 MC_PU32("frame_width", &frame_width),
10674 MC_PU32("frame_height", &frame_height),
10675 MC_PU32("debug", &debug),
10676 MC_PU32("radr", &radr),
10677 MC_PU32("rval", &rval),
10678 MC_PU32("pop_shorts", &pop_shorts),
10679 MC_PU32("dbg_cmd", &dbg_cmd),
10680 MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index),
10681 MC_PU32("endian", &endian),
10682 MC_PU32("step", &step),
10683 MC_PU32("udebug_flag", &udebug_flag),
10684 MC_PU32("decode_pic_begin", &decode_pic_begin),
10685 MC_PU32("slice_parse_begin", &slice_parse_begin),
10686 MC_PU32("i_only_flag", &i_only_flag),
10687 MC_PU32("error_handle_policy", &error_handle_policy),
10688 MC_PU32("buf_alloc_width", &buf_alloc_width),
10689 MC_PU32("buf_alloc_height", &buf_alloc_height),
10690 MC_PU32("buf_alloc_depth", &buf_alloc_depth),
10691 MC_PU32("buf_alloc_size", &buf_alloc_size),
10692 MC_PU32("buffer_mode", &buffer_mode),
10693 MC_PU32("buffer_mode_dbg", &buffer_mode_dbg),
10694 MC_PU32("max_buf_num", &max_buf_num),
10695 MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin),
10696 MC_PU32("mem_map_mode", &mem_map_mode),
10697 MC_PU32("double_write_mode", &double_write_mode),
10698 MC_PU32("enable_mem_saving", &enable_mem_saving),
10699 MC_PU32("force_w_h", &force_w_h),
10700 MC_PU32("force_fps", &force_fps),
10701 MC_PU32("max_decoding_time", &max_decoding_time),
10702 MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped),
10703 MC_PU32("start_decode_buf_level", &start_decode_buf_level),
10704 MC_PU32("decode_timeout_val", &decode_timeout_val),
10705 MC_PU32("vp9_max_pic_w", &vp9_max_pic_w),
10706 MC_PU32("vp9_max_pic_h", &vp9_max_pic_h),
10707};
10708static struct mconfig_node vp9_node;
10709
10710static int __init amvdec_vp9_driver_init_module(void)
10711{
10712
10713 struct BuffInfo_s *p_buf_info;
10714
10715 if (vdec_is_support_4k()) {
10716 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1)
10717 p_buf_info = &amvvp9_workbuff_spec[2];
10718 else
10719 p_buf_info = &amvvp9_workbuff_spec[1];
10720 } else
10721 p_buf_info = &amvvp9_workbuff_spec[0];
10722
10723 init_buff_spec(NULL, p_buf_info);
10724 work_buf_size =
10725 (p_buf_info->end_adr - p_buf_info->start_adr
10726 + 0xffff) & (~0xffff);
10727
10728 pr_debug("amvdec_vp9 module init\n");
10729
10730 error_handle_policy = 0;
10731
10732#ifdef ERROR_HANDLE_DEBUG
10733 dbg_nal_skip_flag = 0;
10734 dbg_nal_skip_count = 0;
10735#endif
10736 udebug_flag = 0;
10737 decode_pic_begin = 0;
10738 slice_parse_begin = 0;
10739 step = 0;
10740 buf_alloc_size = 0;
10741#ifdef MULTI_INSTANCE_SUPPORT
10742 if (platform_driver_register(&ammvdec_vp9_driver))
10743 pr_err("failed to register ammvdec_vp9 driver\n");
10744
10745#endif
10746 if (platform_driver_register(&amvdec_vp9_driver)) {
10747 pr_err("failed to register amvdec_vp9 driver\n");
10748 return -ENODEV;
10749 }
10750
10751 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) {
10752 amvdec_vp9_profile.profile =
10753 "8k, 10bit, dwrite, compressed, no_head";
10754 } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
10755 /*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/
10756 && get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TXL) {
10757 if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TXLX) {
10758 if (vdec_is_support_4k())
10759 amvdec_vp9_profile.profile =
10760 "4k, 10bit, dwrite, compressed";
10761 else
10762 amvdec_vp9_profile.profile =
10763 "10bit, dwrite, compressed";
10764 } else {
10765 if (vdec_is_support_4k())
10766 amvdec_vp9_profile.profile =
10767 "4k, 10bit, dwrite, compressed, no_head";
10768 else
10769 amvdec_vp9_profile.profile =
10770 "10bit, dwrite, compressed, no_head";
10771 }
10772
10773 } else {
10774 amvdec_vp9_profile.name = "vp9_unsupport";
10775 }
10776
10777 if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
10778 max_buf_num = MAX_BUF_NUM_LESS;
10779
10780 vcodec_profile_register(&amvdec_vp9_profile);
10781 amvdec_vp9_profile_mult = amvdec_vp9_profile;
10782 amvdec_vp9_profile_mult.name = "mvp9";
10783 vcodec_profile_register(&amvdec_vp9_profile_mult);
10784 INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node,
10785 "vp9", vp9_configs, CONFIG_FOR_RW);
10786
10787 return 0;
10788}
10789
10790static void __exit amvdec_vp9_driver_remove_module(void)
10791{
10792 pr_debug("amvdec_vp9 module remove.\n");
10793#ifdef MULTI_INSTANCE_SUPPORT
10794 platform_driver_unregister(&ammvdec_vp9_driver);
10795#endif
10796 platform_driver_unregister(&amvdec_vp9_driver);
10797}
10798
10799/****************************************/
10800
10801module_param(bit_depth_luma, uint, 0664);
10802MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n");
10803
10804module_param(bit_depth_chroma, uint, 0664);
10805MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n");
10806
10807module_param(frame_width, uint, 0664);
10808MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n");
10809
10810module_param(frame_height, uint, 0664);
10811MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n");
10812
10813module_param(debug, uint, 0664);
10814MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n");
10815
10816module_param(radr, uint, 0664);
10817MODULE_PARM_DESC(radr, "\n radr\n");
10818
10819module_param(rval, uint, 0664);
10820MODULE_PARM_DESC(rval, "\n rval\n");
10821
10822module_param(pop_shorts, uint, 0664);
10823MODULE_PARM_DESC(pop_shorts, "\n rval\n");
10824
10825module_param(dbg_cmd, uint, 0664);
10826MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n");
10827
10828module_param(dbg_skip_decode_index, uint, 0664);
10829MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n");
10830
10831module_param(endian, uint, 0664);
10832MODULE_PARM_DESC(endian, "\n rval\n");
10833
10834module_param(step, uint, 0664);
10835MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n");
10836
10837module_param(decode_pic_begin, uint, 0664);
10838MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n");
10839
10840module_param(slice_parse_begin, uint, 0664);
10841MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n");
10842
10843module_param(i_only_flag, uint, 0664);
10844MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n");
10845
10846module_param(low_latency_flag, uint, 0664);
10847MODULE_PARM_DESC(low_latency_flag, "\n amvdec_vp9 low_latency_flag\n");
10848
10849module_param(no_head, uint, 0664);
10850MODULE_PARM_DESC(no_head, "\n amvdec_vp9 no_head\n");
10851
10852module_param(error_handle_policy, uint, 0664);
10853MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n");
10854
10855module_param(buf_alloc_width, uint, 0664);
10856MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n");
10857
10858module_param(buf_alloc_height, uint, 0664);
10859MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n");
10860
10861module_param(buf_alloc_depth, uint, 0664);
10862MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n");
10863
10864module_param(buf_alloc_size, uint, 0664);
10865MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n");
10866
10867module_param(buffer_mode, uint, 0664);
10868MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n");
10869
10870module_param(buffer_mode_dbg, uint, 0664);
10871MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n");
10872/*USE_BUF_BLOCK*/
10873module_param(max_buf_num, uint, 0664);
10874MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n");
10875
10876module_param(dynamic_buf_num_margin, uint, 0664);
10877MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n");
10878
10879module_param(mv_buf_margin, uint, 0664);
10880MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n");
10881
10882module_param(run_ready_min_buf_num, uint, 0664);
10883MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n");
10884
10885/**/
10886
10887module_param(mem_map_mode, uint, 0664);
10888MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n");
10889
10890#ifdef SUPPORT_10BIT
10891module_param(double_write_mode, uint, 0664);
10892MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n");
10893
10894module_param(enable_mem_saving, uint, 0664);
10895MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n");
10896
10897module_param(force_w_h, uint, 0664);
10898MODULE_PARM_DESC(force_w_h, "\n force_w_h\n");
10899#endif
10900
10901module_param(force_fps, uint, 0664);
10902MODULE_PARM_DESC(force_fps, "\n force_fps\n");
10903
10904module_param(max_decoding_time, uint, 0664);
10905MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n");
10906
10907module_param(on_no_keyframe_skiped, uint, 0664);
10908MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n");
10909
10910module_param(mcrcc_cache_alg_flag, uint, 0664);
10911MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n");
10912
10913#ifdef MULTI_INSTANCE_SUPPORT
10914module_param(start_decode_buf_level, int, 0664);
10915MODULE_PARM_DESC(start_decode_buf_level,
10916 "\n vp9 start_decode_buf_level\n");
10917
10918module_param(decode_timeout_val, uint, 0664);
10919MODULE_PARM_DESC(decode_timeout_val,
10920 "\n vp9 decode_timeout_val\n");
10921
10922module_param(vp9_max_pic_w, uint, 0664);
10923MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n");
10924
10925module_param(vp9_max_pic_h, uint, 0664);
10926MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n");
10927
10928module_param_array(decode_frame_count, uint,
10929 &max_decode_instance_num, 0664);
10930
10931module_param_array(display_frame_count, uint,
10932 &max_decode_instance_num, 0664);
10933
10934module_param_array(max_process_time, uint,
10935 &max_decode_instance_num, 0664);
10936
10937module_param_array(run_count, uint,
10938 &max_decode_instance_num, 0664);
10939
10940module_param_array(input_empty, uint,
10941 &max_decode_instance_num, 0664);
10942
10943module_param_array(not_run_ready, uint,
10944 &max_decode_instance_num, 0664);
10945#endif
10946
10947#ifdef SUPPORT_FB_DECODING
10948module_param_array(not_run2_ready, uint,
10949 &max_decode_instance_num, 0664);
10950
10951module_param_array(run2_count, uint,
10952 &max_decode_instance_num, 0664);
10953
10954module_param(stage_buf_num, uint, 0664);
10955MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n");
10956#endif
10957
10958module_param(udebug_flag, uint, 0664);
10959MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n");
10960
10961module_param(udebug_pause_pos, uint, 0664);
10962MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n");
10963
10964module_param(udebug_pause_val, uint, 0664);
10965MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n");
10966
10967module_param(udebug_pause_decode_idx, uint, 0664);
10968MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n");
10969
10970module_param(without_display_mode, uint, 0664);
10971MODULE_PARM_DESC(without_display_mode, "\n without_display_mode\n");
10972
10973module_init(amvdec_vp9_driver_init_module);
10974module_exit(amvdec_vp9_driver_remove_module);
10975
10976MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver");
10977MODULE_LICENSE("GPL");
10978
10979
generated by cgit at 2024-05-17 07:43:58 (GMT)