blob: c48ecc1806c5bcf0166b901654566e13ecdc0a66
1 | /* |
2 | * TVIN Modules Exported Header File |
3 | * |
4 | * Author: Lin Xu <lin.xu@amlogic.com> |
5 | * Bobby Yang <bo.yang@amlogic.com> |
6 | * |
7 | * Copyright (C) 2010 Amlogic Inc. |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. |
12 | */ |
13 | |
14 | |
15 | #ifndef _CTVIN_H |
16 | #define _CTVIN_H |
17 | |
18 | |
19 | #include <pthread.h> |
20 | #include <cm.h> |
21 | #include <ve.h> |
22 | #include "../tvutils/CThread.h" |
23 | #include <hdmirx_cec.h> |
24 | #include "../tv/CFrontEnd.h" |
25 | |
26 | #define DEPTH_LEVEL_2DTO3D 33 |
27 | static const int DepthTable_2DTO3D[DEPTH_LEVEL_2DTO3D] = { |
28 | -64, // -16 |
29 | -60, // -15 |
30 | -56, // -14 |
31 | -52, // -13 |
32 | -49, // -12 |
33 | -46, // -11 |
34 | -43, // -10 |
35 | -40, // -09 |
36 | -37, // -08 |
37 | -34, // -07 |
38 | -31, // -06 |
39 | -28, // -05 |
40 | -25, // -04 |
41 | -22, // -03 |
42 | -19, // -02 |
43 | -16, // -01 |
44 | -13, // 0 |
45 | 3, // 1 |
46 | 6, // 2 |
47 | 9, // 3 |
48 | 12, // 4 |
49 | 15, // 5 |
50 | 18, // 6 |
51 | 21, // 7 |
52 | 24, // 8 |
53 | 28, // 9 |
54 | 32, // 10 |
55 | 36, // 11 |
56 | 40, // 12 |
57 | 44, // 13 |
58 | 48, // 14 |
59 | 52, // 15 |
60 | 56, // 16 |
61 | }; |
62 | |
63 | enum { |
64 | MEMP_VDIN_WITHOUT_3D = 0, |
65 | MEMP_VDIN_WITH_3D, |
66 | MEMP_DCDR_WITHOUT_3D, |
67 | MEMP_DCDR_WITH_3D, |
68 | MEMP_ATV_WITHOUT_3D, |
69 | MEMP_ATV_WITH_3D, |
70 | }; |
71 | |
72 | // *************************************************************************** |
73 | // *** TVIN general definition/enum/struct *********************************** |
74 | // *************************************************************************** |
75 | /* tvin input port select */ |
76 | typedef enum tvin_port_e { |
77 | TVIN_PORT_NULL = 0x00000000, |
78 | TVIN_PORT_MPEG0 = 0x00000100, |
79 | TVIN_PORT_BT656 = 0x00000200, |
80 | TVIN_PORT_BT601, |
81 | TVIN_PORT_CAMERA, |
82 | TVIN_PORT_VGA0 = 0x00000400, |
83 | TVIN_PORT_VGA1, |
84 | TVIN_PORT_VGA2, |
85 | TVIN_PORT_VGA3, |
86 | TVIN_PORT_VGA4, |
87 | TVIN_PORT_VGA5, |
88 | TVIN_PORT_VGA6, |
89 | TVIN_PORT_VGA7, |
90 | TVIN_PORT_COMP0 = 0x00000800, |
91 | TVIN_PORT_COMP1, |
92 | TVIN_PORT_COMP2, |
93 | TVIN_PORT_COMP3, |
94 | TVIN_PORT_COMP4, |
95 | TVIN_PORT_COMP5, |
96 | TVIN_PORT_COMP6, |
97 | TVIN_PORT_COMP7, |
98 | TVIN_PORT_CVBS0 = 0x00001000, |
99 | TVIN_PORT_CVBS1, |
100 | TVIN_PORT_CVBS2, |
101 | TVIN_PORT_CVBS3, //as atv demod to tvafe |
102 | TVIN_PORT_CVBS4, |
103 | TVIN_PORT_CVBS5, |
104 | TVIN_PORT_CVBS6, |
105 | TVIN_PORT_CVBS7, |
106 | TVIN_PORT_SVIDEO0 = 0x00002000, |
107 | TVIN_PORT_SVIDEO1, |
108 | TVIN_PORT_SVIDEO2, |
109 | TVIN_PORT_SVIDEO3, |
110 | TVIN_PORT_SVIDEO4, |
111 | TVIN_PORT_SVIDEO5, |
112 | TVIN_PORT_SVIDEO6, |
113 | TVIN_PORT_SVIDEO7, |
114 | TVIN_PORT_HDMI0 = 0x00004000, |
115 | TVIN_PORT_HDMI1, |
116 | TVIN_PORT_HDMI2, |
117 | TVIN_PORT_HDMI3, |
118 | TVIN_PORT_HDMI4, |
119 | TVIN_PORT_HDMI5, |
120 | TVIN_PORT_HDMI6, |
121 | TVIN_PORT_HDMI7, |
122 | TVIN_PORT_DVIN0 = 0x00008000, |
123 | TVIN_PORT_VIU = 0x0000C000, |
124 | TVIN_PORT_MIPI = 0x00010000, |
125 | TVIN_PORT_ISP = 0x00020000, |
126 | TVIN_PORT_DTV = 0x00040000, |
127 | TVIN_PORT_MAX = 0x80000000, |
128 | } tvin_port_t; |
129 | |
130 | const char *tvin_port_str(enum tvin_port_e port); |
131 | |
132 | |
133 | /* tvin signal format table */ |
134 | typedef enum tvin_sig_fmt_e { |
135 | TVIN_SIG_FMT_NULL = 0, |
136 | //VGA Formats |
137 | TVIN_SIG_FMT_VGA_512X384P_60HZ_D147 = 0x001, |
138 | TVIN_SIG_FMT_VGA_560X384P_60HZ_D147 = 0x002, |
139 | TVIN_SIG_FMT_VGA_640X200P_59HZ_D924 = 0x003, |
140 | TVIN_SIG_FMT_VGA_640X350P_85HZ_D080 = 0x004, |
141 | TVIN_SIG_FMT_VGA_640X400P_59HZ_D940 = 0x005, |
142 | TVIN_SIG_FMT_VGA_640X400P_85HZ_D080 = 0x006, |
143 | TVIN_SIG_FMT_VGA_640X400P_59HZ_D638 = 0x007, |
144 | TVIN_SIG_FMT_VGA_640X400P_56HZ_D416 = 0x008, |
145 | TVIN_SIG_FMT_VGA_640X480P_66HZ_D619 = 0x009, |
146 | TVIN_SIG_FMT_VGA_640X480P_66HZ_D667 = 0x00a, |
147 | TVIN_SIG_FMT_VGA_640X480P_59HZ_D940 = 0x00b, |
148 | TVIN_SIG_FMT_VGA_640X480P_60HZ_D000 = 0x00c, |
149 | TVIN_SIG_FMT_VGA_640X480P_72HZ_D809 = 0x00d, |
150 | TVIN_SIG_FMT_VGA_640X480P_75HZ_D000_A = 0x00e, |
151 | TVIN_SIG_FMT_VGA_640X480P_85HZ_D008 = 0x00f, |
152 | TVIN_SIG_FMT_VGA_640X480P_59HZ_D638 = 0x010, |
153 | TVIN_SIG_FMT_VGA_640X480P_75HZ_D000_B = 0x011, |
154 | TVIN_SIG_FMT_VGA_640X870P_75HZ_D000 = 0x012, |
155 | TVIN_SIG_FMT_VGA_720X350P_70HZ_D086 = 0x013, |
156 | TVIN_SIG_FMT_VGA_720X400P_85HZ_D039 = 0x014, |
157 | TVIN_SIG_FMT_VGA_720X400P_70HZ_D086 = 0x015, |
158 | TVIN_SIG_FMT_VGA_720X400P_87HZ_D849 = 0x016, |
159 | TVIN_SIG_FMT_VGA_720X400P_59HZ_D940 = 0x017, |
160 | TVIN_SIG_FMT_VGA_720X480P_59HZ_D940 = 0x018, |
161 | TVIN_SIG_FMT_VGA_768X480P_59HZ_D896 = 0x019, |
162 | TVIN_SIG_FMT_VGA_800X600P_56HZ_D250 = 0x01a, |
163 | TVIN_SIG_FMT_VGA_800X600P_60HZ_D000 = 0x01b, |
164 | TVIN_SIG_FMT_VGA_800X600P_60HZ_D000_A = 0x01c, |
165 | TVIN_SIG_FMT_VGA_800X600P_60HZ_D317 = 0x01d, |
166 | TVIN_SIG_FMT_VGA_800X600P_72HZ_D188 = 0x01e, |
167 | TVIN_SIG_FMT_VGA_800X600P_75HZ_D000 = 0x01f, |
168 | TVIN_SIG_FMT_VGA_800X600P_85HZ_D061 = 0x020, |
169 | TVIN_SIG_FMT_VGA_832X624P_75HZ_D087 = 0x021, |
170 | TVIN_SIG_FMT_VGA_848X480P_84HZ_D751 = 0x022, |
171 | TVIN_SIG_FMT_VGA_960X600P_59HZ_D635 = 0x023, |
172 | TVIN_SIG_FMT_VGA_1024X768P_59HZ_D278 = 0x024, |
173 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D000 = 0x025, |
174 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D000_A = 0x026, |
175 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D000_B = 0x027, |
176 | TVIN_SIG_FMT_VGA_1024X768P_74HZ_D927 = 0x028, |
177 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D004 = 0x029, |
178 | TVIN_SIG_FMT_VGA_1024X768P_70HZ_D069 = 0x02a, |
179 | TVIN_SIG_FMT_VGA_1024X768P_75HZ_D029 = 0x02b, |
180 | TVIN_SIG_FMT_VGA_1024X768P_84HZ_D997 = 0x02c, |
181 | TVIN_SIG_FMT_VGA_1024X768P_74HZ_D925 = 0x02d, |
182 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D020 = 0x02e, |
183 | TVIN_SIG_FMT_VGA_1024X768P_70HZ_D008 = 0x02f, |
184 | TVIN_SIG_FMT_VGA_1024X768P_75HZ_D782 = 0x030, |
185 | TVIN_SIG_FMT_VGA_1024X768P_77HZ_D069 = 0x031, |
186 | TVIN_SIG_FMT_VGA_1024X768P_71HZ_D799 = 0x032, |
187 | TVIN_SIG_FMT_VGA_1024X1024P_60HZ_D000 = 0x033, |
188 | TVIN_SIG_FMT_VGA_1152X864P_60HZ_D000 = 0x034, |
189 | TVIN_SIG_FMT_VGA_1152X864P_70HZ_D012 = 0x035, |
190 | TVIN_SIG_FMT_VGA_1152X864P_75HZ_D000 = 0x036, |
191 | TVIN_SIG_FMT_VGA_1152X864P_84HZ_D999 = 0x037, |
192 | TVIN_SIG_FMT_VGA_1152X870P_75HZ_D062 = 0x038, |
193 | TVIN_SIG_FMT_VGA_1152X900P_65HZ_D950 = 0x039, |
194 | TVIN_SIG_FMT_VGA_1152X900P_66HZ_D004 = 0x03a, |
195 | TVIN_SIG_FMT_VGA_1152X900P_76HZ_D047 = 0x03b, |
196 | TVIN_SIG_FMT_VGA_1152X900P_76HZ_D149 = 0x03c, |
197 | TVIN_SIG_FMT_VGA_1280X720P_59HZ_D855 = 0x03d, |
198 | TVIN_SIG_FMT_VGA_1280X720P_60HZ_D000_A = 0x03e, |
199 | TVIN_SIG_FMT_VGA_1280X720P_60HZ_D000_B = 0x03f, |
200 | TVIN_SIG_FMT_VGA_1280X720P_60HZ_D000_C = 0x040, |
201 | TVIN_SIG_FMT_VGA_1280X720P_60HZ_D000_D = 0x041, |
202 | TVIN_SIG_FMT_VGA_1280X768P_59HZ_D870 = 0x042, |
203 | TVIN_SIG_FMT_VGA_1280X768P_59HZ_D995 = 0x043, |
204 | TVIN_SIG_FMT_VGA_1280X768P_60HZ_D100 = 0x044, |
205 | TVIN_SIG_FMT_VGA_1280X768P_85HZ_D000 = 0x045, |
206 | TVIN_SIG_FMT_VGA_1280X768P_74HZ_D893 = 0x046, |
207 | TVIN_SIG_FMT_VGA_1280X768P_84HZ_D837 = 0x047, |
208 | TVIN_SIG_FMT_VGA_1280X800P_59HZ_D810 = 0x048, |
209 | TVIN_SIG_FMT_VGA_1280X800P_59HZ_D810_A = 0x049, |
210 | TVIN_SIG_FMT_VGA_1280X800P_60HZ_D000 = 0x04a, |
211 | TVIN_SIG_FMT_VGA_1280X800P_85HZ_D000 = 0x04b, |
212 | TVIN_SIG_FMT_VGA_1280X960P_60HZ_D000 = 0x04c, |
213 | TVIN_SIG_FMT_VGA_1280X960P_60HZ_D000_A = 0x04d, |
214 | TVIN_SIG_FMT_VGA_1280X960P_75HZ_D000 = 0x04e, |
215 | TVIN_SIG_FMT_VGA_1280X960P_85HZ_D002 = 0x04f, |
216 | TVIN_SIG_FMT_VGA_1280X1024P_60HZ_D020 = 0x050, |
217 | TVIN_SIG_FMT_VGA_1280X1024P_60HZ_D020_A = 0x051, |
218 | TVIN_SIG_FMT_VGA_1280X1024P_75HZ_D025 = 0x052, |
219 | TVIN_SIG_FMT_VGA_1280X1024P_85HZ_D024 = 0x053, |
220 | TVIN_SIG_FMT_VGA_1280X1024P_59HZ_D979 = 0x054, |
221 | TVIN_SIG_FMT_VGA_1280X1024P_72HZ_D005 = 0x055, |
222 | TVIN_SIG_FMT_VGA_1280X1024P_60HZ_D002 = 0x056, |
223 | TVIN_SIG_FMT_VGA_1280X1024P_67HZ_D003 = 0x057, |
224 | TVIN_SIG_FMT_VGA_1280X1024P_74HZ_D112 = 0x058, |
225 | TVIN_SIG_FMT_VGA_1280X1024P_76HZ_D179 = 0x059, |
226 | TVIN_SIG_FMT_VGA_1280X1024P_66HZ_D718 = 0x05a, |
227 | TVIN_SIG_FMT_VGA_1280X1024P_66HZ_D677 = 0x05b, |
228 | TVIN_SIG_FMT_VGA_1280X1024P_76HZ_D107 = 0x05c, |
229 | TVIN_SIG_FMT_VGA_1280X1024P_59HZ_D996 = 0x05d, |
230 | TVIN_SIG_FMT_VGA_1280X1024P_60HZ_D000 = 0x05e, |
231 | TVIN_SIG_FMT_VGA_1360X768P_59HZ_D799 = 0x05f, |
232 | TVIN_SIG_FMT_VGA_1360X768P_60HZ_D015 = 0x060, |
233 | TVIN_SIG_FMT_VGA_1360X768P_60HZ_D015_A = 0x061, |
234 | TVIN_SIG_FMT_VGA_1360X850P_60HZ_D000 = 0x062, |
235 | TVIN_SIG_FMT_VGA_1360X1024P_60HZ_D000 = 0x063, |
236 | TVIN_SIG_FMT_VGA_1366X768P_59HZ_D790 = 0x064, |
237 | TVIN_SIG_FMT_VGA_1366X768P_60HZ_D000 = 0x065, |
238 | TVIN_SIG_FMT_VGA_1400X1050P_59HZ_D978 = 0x066, |
239 | TVIN_SIG_FMT_VGA_1440X900P_59HZ_D887 = 0x067, |
240 | TVIN_SIG_FMT_VGA_1440X1080P_60HZ_D000 = 0x068, |
241 | TVIN_SIG_FMT_VGA_1600X900P_60HZ_D000 = 0x069, |
242 | TVIN_SIG_FMT_VGA_1600X1024P_60HZ_D000 = 0x06a, |
243 | TVIN_SIG_FMT_VGA_1600X1200P_59HZ_D869 = 0x06b, |
244 | TVIN_SIG_FMT_VGA_1600X1200P_60HZ_D000 = 0x06c, |
245 | TVIN_SIG_FMT_VGA_1600X1200P_65HZ_D000 = 0x06d, |
246 | TVIN_SIG_FMT_VGA_1600X1200P_70HZ_D000 = 0x06e, |
247 | TVIN_SIG_FMT_VGA_1680X1050P_59HZ_D954 = 0x06f, |
248 | TVIN_SIG_FMT_VGA_1680X1080P_60HZ_D000 = 0x070, |
249 | TVIN_SIG_FMT_VGA_1920X1080P_49HZ_D929 = 0x071, |
250 | TVIN_SIG_FMT_VGA_1920X1080P_59HZ_D963_A = 0x072, |
251 | TVIN_SIG_FMT_VGA_1920X1080P_59HZ_D963 = 0x073, |
252 | TVIN_SIG_FMT_VGA_1920X1080P_60HZ_D000 = 0x074, |
253 | TVIN_SIG_FMT_VGA_1920X1200P_59HZ_D950 = 0x075, |
254 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D000_C = 0x076, |
255 | TVIN_SIG_FMT_VGA_1024X768P_60HZ_D000_D = 0x077, |
256 | TVIN_SIG_FMT_VGA_1920X1200P_59HZ_D988 = 0x078, |
257 | TVIN_SIG_FMT_VGA_1400X900P_60HZ_D000 = 0x079, |
258 | TVIN_SIG_FMT_VGA_1680X1050P_60HZ_D000 = 0x07a, |
259 | TVIN_SIG_FMT_VGA_800X600P_60HZ_D062 = 0x07b, |
260 | TVIN_SIG_FMT_VGA_800X600P_60HZ_317_B = 0x07c, |
261 | TVIN_SIG_FMT_VGA_RESERVE8 = 0x07d, |
262 | TVIN_SIG_FMT_VGA_RESERVE9 = 0x07e, |
263 | TVIN_SIG_FMT_VGA_RESERVE10 = 0x07f, |
264 | TVIN_SIG_FMT_VGA_RESERVE11 = 0x080, |
265 | TVIN_SIG_FMT_VGA_RESERVE12 = 0x081, |
266 | TVIN_SIG_FMT_VGA_MAX = 0x082, |
267 | TVIN_SIG_FMT_VGA_THRESHOLD = 0x200, |
268 | //Component Formats |
269 | TVIN_SIG_FMT_COMP_480P_60HZ_D000 = 0x201, |
270 | TVIN_SIG_FMT_COMP_480I_59HZ_D940 = 0x202, |
271 | TVIN_SIG_FMT_COMP_576P_50HZ_D000 = 0x203, |
272 | TVIN_SIG_FMT_COMP_576I_50HZ_D000 = 0x204, |
273 | TVIN_SIG_FMT_COMP_720P_59HZ_D940 = 0x205, |
274 | TVIN_SIG_FMT_COMP_720P_50HZ_D000 = 0x206, |
275 | TVIN_SIG_FMT_COMP_1080P_23HZ_D976 = 0x207, |
276 | TVIN_SIG_FMT_COMP_1080P_24HZ_D000 = 0x208, |
277 | TVIN_SIG_FMT_COMP_1080P_25HZ_D000 = 0x209, |
278 | TVIN_SIG_FMT_COMP_1080P_30HZ_D000 = 0x20a, |
279 | TVIN_SIG_FMT_COMP_1080P_50HZ_D000 = 0x20b, |
280 | TVIN_SIG_FMT_COMP_1080P_60HZ_D000 = 0x20c, |
281 | TVIN_SIG_FMT_COMP_1080I_47HZ_D952 = 0x20d, |
282 | TVIN_SIG_FMT_COMP_1080I_48HZ_D000 = 0x20e, |
283 | TVIN_SIG_FMT_COMP_1080I_50HZ_D000_A = 0x20f, |
284 | TVIN_SIG_FMT_COMP_1080I_50HZ_D000_B = 0x210, |
285 | TVIN_SIG_FMT_COMP_1080I_50HZ_D000_C = 0x211, |
286 | TVIN_SIG_FMT_COMP_1080I_60HZ_D000 = 0x212, |
287 | TVIN_SIG_FMT_COMP_MAX = 0x213, |
288 | TVIN_SIG_FMT_COMP_THRESHOLD = 0x400, |
289 | //HDMI Formats |
290 | TVIN_SIG_FMT_HDMI_640X480P_60HZ = 0x401, |
291 | TVIN_SIG_FMT_HDMI_720X480P_60HZ = 0x402, |
292 | TVIN_SIG_FMT_HDMI_1280X720P_60HZ = 0x403, |
293 | TVIN_SIG_FMT_HDMI_1920X1080I_60HZ = 0x404, |
294 | TVIN_SIG_FMT_HDMI_1440X480I_60HZ = 0x405, |
295 | TVIN_SIG_FMT_HDMI_1440X240P_60HZ = 0x406, |
296 | TVIN_SIG_FMT_HDMI_2880X480I_60HZ = 0x407, |
297 | TVIN_SIG_FMT_HDMI_2880X240P_60HZ = 0x408, |
298 | TVIN_SIG_FMT_HDMI_1440X480P_60HZ = 0x409, |
299 | TVIN_SIG_FMT_HDMI_1920X1080P_60HZ = 0x40a, |
300 | TVIN_SIG_FMT_HDMI_720X576P_50HZ = 0x40b, |
301 | TVIN_SIG_FMT_HDMI_1280X720P_50HZ = 0x40c, |
302 | TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_A = 0x40d, |
303 | TVIN_SIG_FMT_HDMI_1440X576I_50HZ = 0x40e, |
304 | TVIN_SIG_FMT_HDMI_1440X288P_50HZ = 0x40f, |
305 | TVIN_SIG_FMT_HDMI_2880X576I_50HZ = 0x410, |
306 | TVIN_SIG_FMT_HDMI_2880X288P_50HZ = 0x411, |
307 | TVIN_SIG_FMT_HDMI_1440X576P_50HZ = 0x412, |
308 | TVIN_SIG_FMT_HDMI_1920X1080P_50HZ = 0x413, |
309 | TVIN_SIG_FMT_HDMI_1920X1080P_24HZ = 0x414, |
310 | TVIN_SIG_FMT_HDMI_1920X1080P_25HZ = 0x415, |
311 | TVIN_SIG_FMT_HDMI_1920X1080P_30HZ = 0x416, |
312 | TVIN_SIG_FMT_HDMI_2880X480P_60HZ = 0x417, |
313 | TVIN_SIG_FMT_HDMI_2880X576P_60HZ = 0x418, |
314 | TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_B = 0x419, |
315 | TVIN_SIG_FMT_HDMI_1920X1080I_100HZ = 0x41a, |
316 | TVIN_SIG_FMT_HDMI_1280X720P_100HZ = 0x41b, |
317 | TVIN_SIG_FMT_HDMI_720X576P_100HZ = 0x41c, |
318 | TVIN_SIG_FMT_HDMI_1440X576I_100HZ = 0x41d, |
319 | TVIN_SIG_FMT_HDMI_1920X1080I_120HZ = 0x41e, |
320 | TVIN_SIG_FMT_HDMI_1280X720P_120HZ = 0x41f, |
321 | TVIN_SIG_FMT_HDMI_720X480P_120HZ = 0x420, |
322 | TVIN_SIG_FMT_HDMI_1440X480I_120HZ = 0x421, |
323 | TVIN_SIG_FMT_HDMI_720X576P_200HZ = 0x422, |
324 | TVIN_SIG_FMT_HDMI_1440X576I_200HZ = 0x423, |
325 | TVIN_SIG_FMT_HDMI_720X480P_240HZ = 0x424, |
326 | TVIN_SIG_FMT_HDMI_1440X480I_240HZ = 0x425, |
327 | TVIN_SIG_FMT_HDMI_1280X720P_24HZ = 0x426, |
328 | TVIN_SIG_FMT_HDMI_1280X720P_25HZ = 0x427, |
329 | TVIN_SIG_FMT_HDMI_1280X720P_30HZ = 0x428, |
330 | TVIN_SIG_FMT_HDMI_1920X1080P_120HZ = 0x429, |
331 | TVIN_SIG_FMT_HDMI_1920X1080P_100HZ = 0x42a, |
332 | TVIN_SIG_FMT_HDMI_1280X720P_60HZ_FRAME_PACKING = 0x42b, |
333 | TVIN_SIG_FMT_HDMI_1280X720P_50HZ_FRAME_PACKING = 0x42c, |
334 | TVIN_SIG_FMT_HDMI_1280X720P_24HZ_FRAME_PACKING = 0x42d, |
335 | TVIN_SIG_FMT_HDMI_1280X720P_30HZ_FRAME_PACKING = 0x42e, |
336 | TVIN_SIG_FMT_HDMI_1920X1080I_60HZ_FRAME_PACKING = 0x42f, |
337 | TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_FRAME_PACKING = 0x430, |
338 | TVIN_SIG_FMT_HDMI_1920X1080P_24HZ_FRAME_PACKING = 0x431, |
339 | TVIN_SIG_FMT_HDMI_1920X1080P_30HZ_FRAME_PACKING = 0x432, |
340 | TVIN_SIG_FMT_HDMI_800X600_00HZ = 0x433, |
341 | TVIN_SIG_FMT_HDMI_1024X768_00HZ = 0x434, |
342 | TVIN_SIG_FMT_HDMI_720X400_00HZ = 0x435, |
343 | TVIN_SIG_FMT_HDMI_1280X768_00HZ = 0x436, |
344 | TVIN_SIG_FMT_HDMI_1280X800_00HZ = 0x437, |
345 | TVIN_SIG_FMT_HDMI_1280X960_00HZ = 0x438, |
346 | TVIN_SIG_FMT_HDMI_1280X1024_00HZ = 0x439, |
347 | TVIN_SIG_FMT_HDMI_1360X768_00HZ = 0x43a, |
348 | TVIN_SIG_FMT_HDMI_1366X768_00HZ = 0x43b, |
349 | TVIN_SIG_FMT_HDMI_1600X1200_00HZ = 0x43c, |
350 | TVIN_SIG_FMT_HDMI_1920X1200_00HZ = 0x43d, |
351 | TVIN_SIG_FMT_HDMI_1440X900_00HZ = 0x43e, |
352 | TVIN_SIG_FMT_HDMI_1400X1050_00HZ = 0x43f, |
353 | TVIN_SIG_FMT_HDMI_1680X1050_00HZ = 0x440, |
354 | /* for alternative and 4k2k */ |
355 | TVIN_SIG_FMT_HDMI_1920X1080I_60HZ_ALTERNATIVE = 0x441, |
356 | TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_ALTERNATIVE = 0x442, |
357 | TVIN_SIG_FMT_HDMI_1920X1080P_24HZ_ALTERNATIVE = 0x443, |
358 | TVIN_SIG_FMT_HDMI_1920X1080P_30HZ_ALTERNATIVE = 0x444, |
359 | TVIN_SIG_FMT_HDMI_3840_2160_00HZ = 0x445, |
360 | TVIN_SIG_FMT_HDMI_4096_2160_00HZ = 0x446, |
361 | TVIN_SIG_FMT_HDMI_RESERVE7 = 0x447, |
362 | TVIN_SIG_FMT_HDMI_RESERVE8 = 0x448, |
363 | TVIN_SIG_FMT_HDMI_RESERVE9 = 0x449, |
364 | TVIN_SIG_FMT_HDMI_RESERVE10 = 0x44a, |
365 | TVIN_SIG_FMT_HDMI_RESERVE11 = 0x44b, |
366 | TVIN_SIG_FMT_HDMI_720X480P_60HZ_FRAME_PACKING = 0x44c, |
367 | TVIN_SIG_FMT_HDMI_720X576P_50HZ_FRAME_PACKING = 0x44d, |
368 | TVIN_SIG_FMT_HDMI_MAX = 0x44e, |
369 | TVIN_SIG_FMT_HDMI_THRESHOLD = 0x600, |
370 | //Video Formats |
371 | TVIN_SIG_FMT_CVBS_NTSC_M = 0x601, |
372 | TVIN_SIG_FMT_CVBS_NTSC_443 = 0x602, |
373 | TVIN_SIG_FMT_CVBS_PAL_I = 0x603, |
374 | TVIN_SIG_FMT_CVBS_PAL_M = 0x604, |
375 | TVIN_SIG_FMT_CVBS_PAL_60 = 0x605, |
376 | TVIN_SIG_FMT_CVBS_PAL_CN = 0x606, |
377 | TVIN_SIG_FMT_CVBS_SECAM = 0x607, |
378 | TVIN_SIG_FMT_CVBS_MAX = 0x608, |
379 | TVIN_SIG_FMT_CVBS_THRESHOLD = 0x800, |
380 | //656 Formats |
381 | TVIN_SIG_FMT_BT656IN_576I_50HZ = 0x801, |
382 | TVIN_SIG_FMT_BT656IN_480I_60HZ = 0x802, |
383 | //601 Formats |
384 | TVIN_SIG_FMT_BT601IN_576I_50HZ = 0x803, |
385 | TVIN_SIG_FMT_BT601IN_480I_60HZ = 0x804, |
386 | //Camera Formats |
387 | TVIN_SIG_FMT_CAMERA_640X480P_30HZ = 0x805, |
388 | TVIN_SIG_FMT_CAMERA_800X600P_30HZ = 0x806, |
389 | TVIN_SIG_FMT_CAMERA_1024X768P_30HZ = 0x807, |
390 | TVIN_SIG_FMT_CAMERA_1920X1080P_30HZ = 0x808, |
391 | TVIN_SIG_FMT_CAMERA_1280X720P_30HZ = 0x809, |
392 | TVIN_SIG_FMT_BT601_MAX = 0x80a, |
393 | TVIN_SIG_FMT_BT601_THRESHOLD = 0xa00, |
394 | TVIN_SIG_FMT_MAX, |
395 | } tvin_sig_fmt_t; |
396 | |
397 | //tvin signal status |
398 | typedef enum tvin_sig_status_e { |
399 | TVIN_SIG_STATUS_NULL = 0, // processing status from init to the finding of the 1st confirmed status |
400 | TVIN_SIG_STATUS_NOSIG, // no signal - physically no signal |
401 | TVIN_SIG_STATUS_UNSTABLE, // unstable - physically bad signal |
402 | TVIN_SIG_STATUS_NOTSUP, // not supported - physically good signal & not supported |
403 | TVIN_SIG_STATUS_STABLE, // stable - physically good signal & supported |
404 | } tvin_sig_status_t; |
405 | |
406 | const char *tvin_sig_status_str(enum tvin_sig_status_e status); |
407 | |
408 | // tvin parameters |
409 | #define TVIN_PARM_FLAG_CAP 0x00000001 //tvin_parm_t.flag[ 0]: 1/enable or 0/disable frame capture function |
410 | #define TVIN_PARM_FLAG_CAL 0x00000002 //tvin_parm_t.flag[ 1]: 1/enable or 0/disable adc calibration |
411 | /*used for processing 3d in ppmgr set this flag to drop one field and send real height in vframe*/ |
412 | #define TVIN_PARM_FLAG_2D_TO_3D 0x00000004 //tvin_parm_t.flag[ 2]: 1/enable or 0/disable 2D->3D mode |
413 | |
414 | typedef enum tvin_trans_fmt { |
415 | TVIN_TFMT_2D = 0, |
416 | TVIN_TFMT_3D_LRH_OLOR, // 1 Primary: Side-by-Side(Half) Odd/Left picture, Odd/Right p |
417 | TVIN_TFMT_3D_LRH_OLER, // 2 Primary: Side-by-Side(Half) Odd/Left picture, Even/Right picture |
418 | TVIN_TFMT_3D_LRH_ELOR, // 3 Primary: Side-by-Side(Half) Even/Left picture, Odd/Right picture |
419 | TVIN_TFMT_3D_LRH_ELER, // 4 Primary: Side-by-Side(Half) Even/Left picture, Even/Right picture |
420 | TVIN_TFMT_3D_TB, // 5 Primary: Top-and-Bottom |
421 | TVIN_TFMT_3D_FP, // 6 Primary: Frame Packing |
422 | TVIN_TFMT_3D_FA, // 7 Secondary: Field Alternative |
423 | TVIN_TFMT_3D_LA, // 8 Secondary: Line Alternative |
424 | TVIN_TFMT_3D_LRF, // 9 Secondary: Side-by-Side(Full) |
425 | TVIN_TFMT_3D_LD, // 10 Secondary: L+depth |
426 | TVIN_TFMT_3D_LDGD, // 11 Secondary: L+depth+Graphics+Graphics-depth |
427 | /* normal 3D format */ |
428 | TVIN_TFMT_3D_DET_TB,// 12 |
429 | TVIN_TFMT_3D_DET_LR,// 13 |
430 | TVIN_TFMT_3D_DET_INTERLACE,// 14 |
431 | TVIN_TFMT_3D_DET_CHESSBOARD,// 15 |
432 | TVIN_TFMT_3D_MAX, |
433 | } tvin_trans_fmt_t; |
434 | |
435 | const char *tvin_trans_fmt_str(enum tvin_trans_fmt trans_fmt); |
436 | |
437 | typedef enum tvin_color_fmt_e { |
438 | TVIN_RGB444 = 0, |
439 | TVIN_YUV422, // 1 |
440 | TVIN_YUV444, // 2 |
441 | TVIN_YUYV422,// 3 |
442 | TVIN_YVYU422,// 4 |
443 | TVIN_UYVY422,// 5 |
444 | TVIN_VYUY422,// 6 |
445 | TVIN_NV12, // 7 |
446 | TVIN_NV21, // 8 |
447 | TVIN_BGGR, // 9 raw data |
448 | TVIN_RGGB, // 10 raw data |
449 | TVIN_GBRG, // 11 raw data |
450 | TVIN_GRBG, // 12 raw data |
451 | TVIN_COLOR_FMT_MAX, |
452 | } tvin_color_fmt_t; |
453 | |
454 | const char *tvin_color_fmt_str(enum tvin_color_fmt_e color_fmt); |
455 | typedef enum tvin_scan_mode_e { |
456 | TVIN_SCAN_MODE_NULL = 0, |
457 | TVIN_SCAN_MODE_PROGRESSIVE, |
458 | TVIN_SCAN_MODE_INTERLACED, |
459 | } tvin_scan_mode_t; |
460 | |
461 | typedef struct tvin_info_s { |
462 | enum tvin_trans_fmt trans_fmt; |
463 | enum tvin_sig_fmt_e fmt; |
464 | volatile enum tvin_sig_status_e status; |
465 | enum tvin_color_fmt_e cfmt; |
466 | unsigned int fps; |
467 | unsigned int reserved; |
468 | } tvin_info_t; |
469 | |
470 | typedef struct tvin_buf_info_s { |
471 | unsigned int vf_size; |
472 | unsigned int buf_count; |
473 | unsigned int buf_width; |
474 | unsigned int buf_height; |
475 | unsigned int buf_size; |
476 | unsigned int wr_list_size; |
477 | } tvin_buf_info_t; |
478 | |
479 | typedef struct tvin_video_buf_s { |
480 | unsigned int index; |
481 | unsigned int reserved; |
482 | } tvin_video_buf_t; |
483 | |
484 | // hs=he=vs=ve=0 is to disable Cut Window |
485 | typedef struct tvin_cutwin_s { |
486 | unsigned short hs; |
487 | unsigned short he; |
488 | unsigned short vs; |
489 | unsigned short ve; |
490 | } tvin_cutwin_t; |
491 | |
492 | typedef struct tvin_parm_s { |
493 | int index; // index of frontend for vdin |
494 | enum tvin_port_e port; // must set port in IOCTL |
495 | struct tvin_info_s info; |
496 | unsigned int hist_pow; |
497 | unsigned int luma_sum; |
498 | unsigned int pixel_sum; |
499 | unsigned short histgram[64]; |
500 | unsigned int flag; |
501 | unsigned short dest_width;//for vdin horizontal scale down |
502 | unsigned short dest_height;//for vdin vertical scale down |
503 | bool h_reverse;//for vdin horizontal reverse |
504 | bool v_reverse;//for vdin vertical reverse |
505 | unsigned int reserved; |
506 | } tvin_parm_t; |
507 | |
508 | |
509 | |
510 | // *************************************************************************** |
511 | // *** AFE module definition/enum/struct ************************************* |
512 | // *************************************************************************** |
513 | |
514 | typedef enum tvafe_cmd_status_e { |
515 | TVAFE_CMD_STATUS_IDLE = 0, // idle, be ready for TVIN_IOC_S_AFE_VGA_AUTO command |
516 | TVAFE_CMD_STATUS_PROCESSING, // TVIN_IOC_S_AFE_VGA_AUTO command is in process |
517 | TVAFE_CMD_STATUS_SUCCESSFUL, // TVIN_IOC_S_AFE_VGA_AUTO command is done with success |
518 | TVAFE_CMD_STATUS_FAILED, // TVIN_IOC_S_AFE_VGA_AUTO command is done with failure |
519 | TVAFE_CMD_STATUS_TERMINATED, // TVIN_IOC_S_AFE_VGA_AUTO command is terminated by others related |
520 | } tvafe_cmd_status_t; |
521 | |
522 | typedef struct tvafe_vga_edid_s { |
523 | unsigned char value[256]; //256 byte EDID |
524 | } tvafe_vga_edid_t; |
525 | |
526 | typedef struct tvafe_comp_wss_s { |
527 | unsigned int wss1[5]; |
528 | unsigned int wss2[5]; |
529 | } tvafe_comp_wss_t; |
530 | |
531 | typedef struct tvafe_vga_parm_s { |
532 | signed short clk_step; // clock < 0, tune down clock freq |
533 | // clock > 0, tune up clock freq |
534 | unsigned short phase; // phase is 0~31, it is absolute value |
535 | signed short hpos_step; // hpos_step < 0, shift display to left |
536 | // hpos_step > 0, shift display to right |
537 | signed short vpos_step; // vpos_step < 0, shift display to top |
538 | // vpos_step > 0, shift display to bottom |
539 | unsigned int vga_in_clean; // flage for vga clean screen |
540 | } tvafe_vga_parm_t; |
541 | |
542 | #define TVAFE_ADC_CAL_VALID 0x00000001 |
543 | typedef struct tvafe_adc_cal_s { |
544 | // ADC A |
545 | unsigned short a_analog_clamp; // 0x00~0x7f |
546 | unsigned short a_analog_gain; // 0x00~0xff, means 0dB~6dB |
547 | unsigned short a_digital_offset1; // offset for fine-tuning |
548 | // s11.0: signed value, 11 integer bits, 0 fraction bits |
549 | unsigned short a_digital_gain; // 0~3.999 |
550 | // u2.10: unsigned value, 2 integer bits, 10 fraction bits |
551 | unsigned short a_digital_offset2; // offset for format |
552 | // s11.0: signed value, 11 integer bits, 0 fraction bits |
553 | // ADC B |
554 | unsigned short b_analog_clamp; // ditto to ADC A |
555 | unsigned short b_analog_gain; |
556 | unsigned short b_digital_offset1; |
557 | unsigned short b_digital_gain; |
558 | unsigned short b_digital_offset2; |
559 | // ADC C |
560 | unsigned short c_analog_clamp; // ditto to ADC A |
561 | unsigned short c_analog_gain; |
562 | unsigned short c_digital_offset1; |
563 | unsigned short c_digital_gain; |
564 | unsigned short c_digital_offset2; |
565 | // ADC D |
566 | unsigned short d_analog_clamp; // ditto to ADC A |
567 | unsigned short d_analog_gain; |
568 | unsigned short d_digital_offset1; |
569 | unsigned short d_digital_gain; |
570 | unsigned short d_digital_offset2; |
571 | unsigned int reserved; // bit[ 0]: TVAFE_ADC_CAL_VALID |
572 | } tvafe_adc_cal_t; |
573 | |
574 | typedef struct tvafe_adc_cal_clamp_s { |
575 | short a_analog_clamp_diff; |
576 | short b_analog_clamp_diff; |
577 | short c_analog_clamp_diff; |
578 | } tvafe_adc_cal_clamp_t; |
579 | |
580 | typedef struct tvafe_adc_comp_cal_s { |
581 | struct tvafe_adc_cal_s comp_cal_val[3]; |
582 | } tvafe_adc_comp_cal_t; |
583 | |
584 | typedef enum tvafe_cvbs_video_e { |
585 | TVAFE_CVBS_VIDEO_HV_UNLOCKED = 0, |
586 | TVAFE_CVBS_VIDEO_H_LOCKED, |
587 | TVAFE_CVBS_VIDEO_V_LOCKED, |
588 | TVAFE_CVBS_VIDEO_HV_LOCKED, |
589 | } tvafe_cvbs_video_t; |
590 | |
591 | // for pin selection |
592 | typedef enum tvafe_adc_pin_e { |
593 | TVAFE_ADC_PIN_NULL = 0, |
594 | #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) |
595 | TVAFE_CVBS_IN0 = 1, |
596 | TVAFE_CVBS_IN1 = 2, |
597 | TVAFE_CVBS_IN2 = 3, |
598 | TVAFE_CVBS_IN3 = 4,//as atvdemod to tvafe |
599 | #else |
600 | TVAFE_ADC_PIN_A_PGA_0 = 1, |
601 | TVAFE_ADC_PIN_A_PGA_1 = 2, |
602 | TVAFE_ADC_PIN_A_PGA_2 = 3, |
603 | TVAFE_ADC_PIN_A_PGA_3 = 4, |
604 | TVAFE_ADC_PIN_A_PGA_4 = 5, |
605 | TVAFE_ADC_PIN_A_PGA_5 = 6, |
606 | TVAFE_ADC_PIN_A_PGA_6 = 7, |
607 | TVAFE_ADC_PIN_A_PGA_7 = 8, |
608 | TVAFE_ADC_PIN_A_0 = 9, |
609 | TVAFE_ADC_PIN_A_1 = 10, |
610 | TVAFE_ADC_PIN_A_2 = 11, |
611 | TVAFE_ADC_PIN_A_3 = 12, |
612 | TVAFE_ADC_PIN_A_4 = 13, |
613 | TVAFE_ADC_PIN_A_5 = 14, |
614 | TVAFE_ADC_PIN_A_6 = 15, |
615 | TVAFE_ADC_PIN_A_7 = 16, |
616 | TVAFE_ADC_PIN_B_0 = 17, |
617 | TVAFE_ADC_PIN_B_1 = 18, |
618 | TVAFE_ADC_PIN_B_2 = 19, |
619 | TVAFE_ADC_PIN_B_3 = 20, |
620 | TVAFE_ADC_PIN_B_4 = 21, |
621 | TVAFE_ADC_PIN_B_5 = 22, |
622 | TVAFE_ADC_PIN_B_6 = 23, |
623 | TVAFE_ADC_PIN_B_7 = 24, |
624 | TVAFE_ADC_PIN_C_0 = 25, |
625 | TVAFE_ADC_PIN_C_1 = 26, |
626 | TVAFE_ADC_PIN_C_2 = 27, |
627 | TVAFE_ADC_PIN_C_3 = 28, |
628 | TVAFE_ADC_PIN_C_4 = 29, |
629 | TVAFE_ADC_PIN_C_5 = 30, |
630 | TVAFE_ADC_PIN_C_6 = 31, |
631 | TVAFE_ADC_PIN_C_7 = 32, |
632 | TVAFE_ADC_PIN_D_0 = 33, |
633 | TVAFE_ADC_PIN_D_1 = 34, |
634 | TVAFE_ADC_PIN_D_2 = 35, |
635 | TVAFE_ADC_PIN_D_3 = 36, |
636 | TVAFE_ADC_PIN_D_4 = 37, |
637 | TVAFE_ADC_PIN_D_5 = 38, |
638 | TVAFE_ADC_PIN_D_6 = 39, |
639 | TVAFE_ADC_PIN_D_7 = 40, |
640 | TVAFE_ADC_PIN_SOG_0 = 41, |
641 | TVAFE_ADC_PIN_SOG_1 = 42, |
642 | TVAFE_ADC_PIN_SOG_2 = 43, |
643 | TVAFE_ADC_PIN_SOG_3 = 44, |
644 | TVAFE_ADC_PIN_SOG_4 = 45, |
645 | TVAFE_ADC_PIN_SOG_5 = 46, |
646 | TVAFE_ADC_PIN_SOG_6 = 47, |
647 | TVAFE_ADC_PIN_SOG_7 = 48, |
648 | #endif |
649 | TVAFE_ADC_PIN_MAX, |
650 | } tvafe_adc_pin_t; |
651 | |
652 | typedef enum tvafe_src_sig_e { |
653 | #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) |
654 | CVBS_IN0 = 0, |
655 | CVBS_IN1, |
656 | CVBS_IN2, |
657 | CVBS_IN3, |
658 | #else |
659 | CVBS0_Y = 0, |
660 | CVBS0_SOG, |
661 | CVBS1_Y, |
662 | CVBS1_SOG, |
663 | CVBS2_Y, |
664 | CVBS2_SOG, |
665 | CVBS3_Y, |
666 | CVBS3_SOG, |
667 | CVBS4_Y, |
668 | CVBS4_SOG, |
669 | CVBS5_Y, |
670 | CVBS5_SOG, |
671 | CVBS6_Y, |
672 | CVBS6_SOG, |
673 | CVBS7_Y, |
674 | CVBS7_SOG, |
675 | S_VIDEO0_Y, |
676 | S_VIDEO0_C, |
677 | S_VIDEO0_SOG, |
678 | S_VIDEO1_Y, |
679 | S_VIDEO1_C, |
680 | S_VIDEO1_SOG, |
681 | S_VIDEO2_Y, |
682 | S_VIDEO2_C, |
683 | S_VIDEO2_SOG, |
684 | S_VIDEO3_Y, |
685 | S_VIDEO3_C, |
686 | S_VIDEO3_SOG, |
687 | S_VIDEO4_Y, |
688 | S_VIDEO4_C, |
689 | S_VIDEO4_SOG, |
690 | S_VIDEO5_Y, |
691 | S_VIDEO5_C, |
692 | S_VIDEO5_SOG, |
693 | S_VIDEO6_Y, |
694 | S_VIDEO6_C, |
695 | S_VIDEO6_SOG, |
696 | S_VIDEO7_Y, |
697 | S_VIDEO7_C, |
698 | S_VIDEO7_SOG, |
699 | VGA0_G, |
700 | VGA0_B, |
701 | VGA0_R, |
702 | VGA0_SOG, |
703 | VGA1_G, |
704 | VGA1_B, |
705 | VGA1_R, |
706 | VGA1_SOG, |
707 | VGA2_G, |
708 | VGA2_B, |
709 | VGA2_R, |
710 | VGA2_SOG, |
711 | VGA3_G, |
712 | VGA3_B, |
713 | VGA3_R, |
714 | VGA3_SOG, |
715 | VGA4_G, |
716 | VGA4_B, |
717 | VGA4_R, |
718 | VGA4_SOG, |
719 | VGA5_G, |
720 | VGA5_B, |
721 | VGA5_R, |
722 | VGA5_SOG, |
723 | VGA6_G, |
724 | VGA6_B, |
725 | VGA6_R, |
726 | VGA6_SOG, |
727 | VGA7_G, |
728 | VGA7_B, |
729 | VGA7_R, |
730 | VGA7_SOG, |
731 | COMP0_Y, |
732 | COMP0_PB, |
733 | COMP0_PR, |
734 | COMP0_SOG, |
735 | COMP1_Y, |
736 | COMP1_PB, |
737 | COMP1_PR, |
738 | COMP1_SOG, |
739 | COMP2_Y, |
740 | COMP2_PB, |
741 | COMP2_PR, |
742 | COMP2_SOG, |
743 | COMP3_Y, |
744 | COMP3_PB, |
745 | COMP3_PR, |
746 | COMP3_SOG, |
747 | COMP4_Y, |
748 | COMP4_PB, |
749 | COMP4_PR, |
750 | COMP4_SOG, |
751 | COMP5_Y, |
752 | COMP5_PB, |
753 | COMP5_PR, |
754 | COMP5_SOG, |
755 | COMP6_Y, |
756 | COMP6_PB, |
757 | COMP6_PR, |
758 | COMP6_SOG, |
759 | COMP7_Y, |
760 | COMP7_PB, |
761 | COMP7_PR, |
762 | COMP7_SOG, |
763 | SCART0_G, |
764 | SCART0_B, |
765 | SCART0_R, |
766 | SCART0_CVBS, |
767 | SCART1_G, |
768 | SCART1_B, |
769 | SCART1_R, |
770 | SCART1_CVBS, |
771 | SCART2_G, |
772 | SCART2_B, |
773 | SCART2_R, |
774 | SCART2_CVBS, |
775 | SCART3_G, |
776 | SCART3_B, |
777 | SCART3_R, |
778 | SCART3_CVBS, |
779 | SCART4_G, |
780 | SCART4_B, |
781 | SCART4_R, |
782 | SCART4_CVBS, |
783 | SCART5_G, |
784 | SCART5_B, |
785 | SCART5_R, |
786 | SCART5_CVBS, |
787 | SCART6_G, |
788 | SCART6_B, |
789 | SCART6_R, |
790 | SCART6_CVBS, |
791 | SCART7_G, |
792 | SCART7_B, |
793 | SCART7_R, |
794 | SCART7_CVBS, |
795 | #endif |
796 | TVAFE_SRC_SIG_MAX_NUM, |
797 | } tvafe_src_sig_t; |
798 | |
799 | typedef struct tvafe_pin_mux_s { |
800 | enum tvafe_adc_pin_e pin[TVAFE_SRC_SIG_MAX_NUM]; |
801 | } tvafe_pin_mux_t; |
802 | |
803 | |
804 | // *************************************************************************** |
805 | // *** IOCTL command definition ********************************************** |
806 | // *************************************************************************** |
807 | |
808 | #define TVIN_IOC_MAGIC 'T' |
809 | |
810 | //GENERAL |
811 | #define TVIN_IOC_OPEN _IOW(TVIN_IOC_MAGIC, 0x01, struct tvin_parm_s) |
812 | #define TVIN_IOC_START_DEC _IOW(TVIN_IOC_MAGIC, 0x02, struct tvin_parm_s) |
813 | #define TVIN_IOC_STOP_DEC _IO( TVIN_IOC_MAGIC, 0x03) |
814 | #define TVIN_IOC_CLOSE _IO( TVIN_IOC_MAGIC, 0x04) |
815 | #define TVIN_IOC_G_PARM _IOR(TVIN_IOC_MAGIC, 0x05, struct tvin_parm_s) |
816 | #define TVIN_IOC_S_PARM _IOW(TVIN_IOC_MAGIC, 0x06, struct tvin_parm_s) |
817 | #define TVIN_IOC_G_SIG_INFO _IOR(TVIN_IOC_MAGIC, 0x07, struct tvin_info_s) |
818 | #define TVIN_IOC_G_BUF_INFO _IOR(TVIN_IOC_MAGIC, 0x08, struct tvin_buf_info_s) |
819 | #define TVIN_IOC_START_GET_BUF _IO( TVIN_IOC_MAGIC, 0x09) |
820 | #define TVIN_IOC_GET_BUF _IOR(TVIN_IOC_MAGIC, 0x10, struct tvin_video_buf_s) |
821 | #define TVIN_IOC_PAUSE_DEC _IO(TVIN_IOC_MAGIC, 0x41) |
822 | #define TVIN_IOC_RESUME_DEC _IO(TVIN_IOC_MAGIC, 0x42) |
823 | #define TVIN_IOC_VF_REG _IO(TVIN_IOC_MAGIC, 0x43) |
824 | #define TVIN_IOC_VF_UNREG _IO(TVIN_IOC_MAGIC, 0x44) |
825 | #define TVIN_IOC_FREEZE_VF _IO(TVIN_IOC_MAGIC, 0x45) |
826 | #define TVIN_IOC_UNFREEZE_VF _IO(TVIN_IOC_MAGIC, 0x46) |
827 | |
828 | //HDMI |
829 | #define HDMI_IOC_HDCP_KSV _IOR(HDMI_IOC_MAGIC, 0x09, struct _hdcp_ksv) |
830 | |
831 | |
832 | |
833 | //TVAFE |
834 | #define TVIN_IOC_S_AFE_ADC_CAL _IOW(TVIN_IOC_MAGIC, 0x11, struct tvafe_adc_cal_s) |
835 | #define TVIN_IOC_G_AFE_ADC_CAL _IOR(TVIN_IOC_MAGIC, 0x12, struct tvafe_adc_cal_s) |
836 | #define TVIN_IOC_G_AFE_COMP_WSS _IOR(TVIN_IOC_MAGIC, 0x13, struct tvafe_comp_wss_s) |
837 | #define TVIN_IOC_S_AFE_VGA_EDID _IOW(TVIN_IOC_MAGIC, 0x14, struct tvafe_vga_edid_s) |
838 | #define TVIN_IOC_G_AFE_VGA_EDID _IOR(TVIN_IOC_MAGIC, 0x15, struct tvafe_vga_edid_s) |
839 | #define TVIN_IOC_S_AFE_VGA_PARM _IOW(TVIN_IOC_MAGIC, 0x16, struct tvafe_vga_parm_s) |
840 | #define TVIN_IOC_G_AFE_VGA_PARM _IOR(TVIN_IOC_MAGIC, 0x17, struct tvafe_vga_parm_s) |
841 | #define TVIN_IOC_S_AFE_VGA_AUTO _IO( TVIN_IOC_MAGIC, 0x18) |
842 | #define TVIN_IOC_G_AFE_CMD_STATUS _IOR(TVIN_IOC_MAGIC, 0x19, enum tvafe_cmd_status_e) |
843 | #define TVIN_IOC_G_AFE_CVBS_LOCK _IOR(TVIN_IOC_MAGIC, 0x1a, enum tvafe_cvbs_video_e) |
844 | #define TVIN_IOC_S_AFE_CVBS_STD _IOW(TVIN_IOC_MAGIC, 0x1b, enum tvin_sig_fmt_e) |
845 | #define TVIN_IOC_CALLMASTER_SET _IOW(TVIN_IOC_MAGIC, 0x1c, enum tvin_port_e) |
846 | #define TVIN_IOC_CALLMASTER_GET _IO( TVIN_IOC_MAGIC, 0x1d) |
847 | #define TVIN_IOC_S_AFE_ADC_COMP_CAL _IOW(TVIN_IOC_MAGIC, 0x1e, struct tvafe_adc_comp_cal_s) |
848 | #define TVIN_IOC_G_AFE_ADC_COMP_CAL _IOR(TVIN_IOC_MAGIC, 0x1f, struct tvafe_adc_comp_cal_s) |
849 | #define TVIN_IOC_LOAD_REG _IOW(TVIN_IOC_MAGIC, 0x20, struct am_regs_s) |
850 | #define TVIN_IOC_S_AFE_ADC_DIFF _IOW(TVIN_IOC_MAGIC, 0x21, struct tvafe_adc_cal_clamp_s) |
851 | |
852 | // *************************************************************************** |
853 | // *** add more ********************************************** |
854 | // *************************************************************************** |
855 | |
856 | typedef enum tvin_path_id_e { |
857 | TV_PATH_VDIN_AMVIDEO, |
858 | TV_PATH_VDIN_DEINTERLACE_AMVIDEO, |
859 | TV_PATH_VDIN_3D_AMVIDEO, |
860 | TV_PATH_VDIN_NEW3D_AMVIDEO, |
861 | TV_PATH_VDIN_NEW3D_WITHOUTPPMGR_AMVIDEO, |
862 | TV_PATH_VDIN_FREESCALE_AMVIDEO, |
863 | TV_PATH_DECODER_3D_AMVIDEO, |
864 | TV_PATH_DECODER_AMVIDEO, |
865 | TV_PATH_DECODER_NEW3D_AMVIDEO, |
866 | TV_PATH_DECODER_NEW3D_WITHOUTPPMGR_AMVIDEO, |
867 | TV_PATH_MAX, |
868 | } tvin_path_id_t; |
869 | |
870 | #define CAMERA_IOC_MAGIC 'C' |
871 | #define CAMERA_IOC_START _IOW(CAMERA_IOC_MAGIC, 0x01, struct camera_info_s) |
872 | #define CAMERA_IOC_STOP _IO(CAMERA_IOC_MAGIC, 0x02) |
873 | #define CAMERA_IOC_SET_PARA _IOW(CAMERA_IOC_MAGIC, 0x03, struct camera_info_s) |
874 | #define CAMERA_IOC_GET_PARA _IOR(CAMERA_IOC_MAGIC, 0x04, struct camera_info_s) |
875 | |
876 | |
877 | #define CC_HIST_GRAM_BUF_SIZE (64) |
878 | /*******************************extend define*******************************/ |
879 | |
880 | typedef enum tv_source_input_e { |
881 | SOURCE_INVALID = -1, |
882 | SOURCE_TV = 0, |
883 | SOURCE_AV1, |
884 | SOURCE_AV2, |
885 | SOURCE_YPBPR1, |
886 | SOURCE_YPBPR2, |
887 | SOURCE_HDMI1, |
888 | SOURCE_HDMI2, |
889 | SOURCE_HDMI3, |
890 | SOURCE_VGA, |
891 | SOURCE_MPEG, |
892 | SOURCE_DTV, |
893 | SOURCE_SVIDEO, |
894 | SOURCE_IPTV, |
895 | SOURCE_DUMMY, |
896 | SOURCE_MAX, |
897 | } tv_source_input_t; |
898 | |
899 | typedef enum tv_source_input_type_e { |
900 | SOURCE_TYPE_TV, |
901 | SOURCE_TYPE_AV, |
902 | SOURCE_TYPE_COMPONENT, |
903 | SOURCE_TYPE_HDMI, |
904 | SOURCE_TYPE_VGA, |
905 | SOURCE_TYPE_MPEG, |
906 | SOURCE_TYPE_DTV, |
907 | SOURCE_TYPE_SVIDEO, |
908 | SOURCE_TYPE_IPTV, |
909 | SOURCE_TYPE_MAX, |
910 | } tv_source_input_type_t; |
911 | |
912 | typedef enum adc_cal_type_e { |
913 | CAL_YPBPR = 0, |
914 | CAL_VGA, |
915 | CAL_CVBS, |
916 | } adc_cal_type_t; |
917 | |
918 | typedef enum signal_range_e { |
919 | RANGE100 = 0, |
920 | RANGE75, |
921 | } signal_range_t; |
922 | |
923 | typedef struct adc_cal_s { |
924 | unsigned int rcr_max; |
925 | unsigned int rcr_min; |
926 | unsigned int g_y_max; |
927 | unsigned int g_y_min; |
928 | unsigned int bcb_max; |
929 | unsigned int bcb_min; |
930 | unsigned int cr_white; |
931 | unsigned int cb_white; |
932 | unsigned int cr_black; |
933 | unsigned int cb_black; |
934 | } adc_cal_t; |
935 | |
936 | typedef struct tvin_window_pos_s { |
937 | int x1; |
938 | int y1; |
939 | int x2; |
940 | int y2; |
941 | } tvin_window_pos_t; |
942 | |
943 | |
944 | typedef enum tv_path_type_e { |
945 | TV_PATH_TYPE_DEFAULT, |
946 | TV_PATH_TYPE_TVIN, |
947 | TV_PATH_TYPE_TVIN_PREVIEW, |
948 | TV_PATH_TYPE_MAX, |
949 | } tv_path_type_t; |
950 | |
951 | typedef enum tv_path_status_e { |
952 | TV_PATH_STATUS_NO_DEV = -2, |
953 | TV_PATH_STATUS_ERROR = -1, |
954 | TV_PATH_STATUS_INACTIVE = 0, |
955 | TV_PATH_STATUS_ACTIVE = 1, |
956 | TV_PATH_STATUS_MAX, |
957 | } tv_path_status_t; |
958 | |
959 | typedef enum tv_audio_channel_e { |
960 | TV_AUDIO_LINE_IN_0, |
961 | TV_AUDIO_LINE_IN_1, |
962 | TV_AUDIO_LINE_IN_2, |
963 | TV_AUDIO_LINE_IN_3, |
964 | TV_AUDIO_LINE_IN_4, |
965 | TV_AUDIO_LINE_IN_5, |
966 | TV_AUDIO_LINE_IN_6, |
967 | TV_AUDIO_LINE_IN_7, |
968 | TV_AUDIO_LINE_IN_MAX, |
969 | } tv_audio_channel_t; |
970 | |
971 | typedef enum tv_audio_in_source_type_e { |
972 | TV_AUDIO_IN_SOURCE_TYPE_LINEIN, |
973 | TV_AUDIO_IN_SOURCE_TYPE_ATV, |
974 | TV_AUDIO_IN_SOURCE_TYPE_HDMI, |
975 | TV_AUDIO_IN_SOURCE_TYPE_MAX, |
976 | } tv_audio_in_source_type_t; |
977 | |
978 | #define CC_RESOLUTION_1366X768_W (1366) |
979 | #define CC_RESOLUTION_1366X768_H (768) |
980 | #define CC_RESOLUTION_1920X1080_W (1920) |
981 | #define CC_RESOLUTION_1920X1080_H (1080) |
982 | #define CC_RESOLUTION_3840X2160_W (3840) |
983 | #define CC_RESOLUTION_3840X2160_H (2160) |
984 | |
985 | typedef enum tv_source_connect_detect_status_e { |
986 | CC_SOURCE_PLUG_OUT = 0, |
987 | CC_SOURCE_PLUG_IN = 1, |
988 | } tv_source_connect_detect_status_t; |
989 | |
990 | //HDMI rx cec |
991 | typedef struct tagHDMIRxRequestReplyItem { |
992 | CCondition WaitReplyCondition; |
993 | int WaitCmd; |
994 | int WaitLogicAddr; |
995 | int WaitTimeOut; |
996 | int WaitFlag; |
997 | int DataFlag; |
998 | struct _cec_msg msg; |
999 | } HDMIRxRequestReplyItem; |
1000 | |
1001 | typedef struct _hdcp_ksv { |
1002 | int bksv0; |
1003 | int bksv1; |
1004 | } _hdcp_ksv; |
1005 | |
1006 | |
1007 | typedef struct am_phase_s { |
1008 | unsigned int length; // Length of total |
1009 | unsigned int phase[TVIN_SIG_FMT_COMP_MAX - TVIN_SIG_FMT_VGA_THRESHOLD]; |
1010 | } am_phase_t; |
1011 | |
1012 | |
1013 | #define CC_REQUEST_LIST_SIZE (32) |
1014 | #define CC_CEC_STREAM_SIZE (sizeof(struct _cec_msg)) |
1015 | #define CC_SOURCE_DEV_REFRESH_CNT (E_LA_MAX) |
1016 | |
1017 | class CTvin { |
1018 | public: |
1019 | CTvin(); |
1020 | ~CTvin(); |
1021 | int OpenTvin(); |
1022 | int init_vdin(); |
1023 | int uninit_vdin ( void ); |
1024 | int Tv_init_afe ( void ); |
1025 | int Tv_uninit_afe ( void ); |
1026 | int Tvin_AddPath ( tvin_path_id_t pathid ); |
1027 | int Tvin_RemovePath ( tv_path_type_t pathtype ); |
1028 | int Tvin_CheckPathActive ( tv_path_type_t path_type, int isCheckD2D3 ); |
1029 | int setMpeg2Vdin(int enable); |
1030 | //pre apis |
1031 | int AFE_DeviceIOCtl ( int request, ... ); |
1032 | void TvinApi_CloseAFEModule ( void ); |
1033 | int TvinApi_SetVdinHVScale ( int vdinx, int hscale, int vscale ); |
1034 | int TvinApi_SetCompPhase ( am_phase_t &am_phase ); |
1035 | int TvinApi_SetStartDropFrameCn ( int count ); |
1036 | int TvinApi_SetCompPhaseEnable ( int enable ); |
1037 | tvin_trans_fmt TvinApi_Get3DDectMode(); |
1038 | int TvinApi_GetHDMIAudioStatus ( void ); |
1039 | int TvinApi_LoadPLLValues ( am_regs_t regs ); |
1040 | int TvinApi_LoadCVD2Values ( am_regs_t regs ); |
1041 | int TvinApi_GetFbSize ( unsigned int *fb_width, unsigned int *fb_height ); |
1042 | int Tvin_StartDecoder ( tvin_info_t &info ); |
1043 | int Tvin_StopDecoder(); |
1044 | int get_hdmi_sampling_rate(); |
1045 | int get_hdmi_ksv_info(int source_input, int data_buf[]); |
1046 | int SwitchPort (tvin_port_t source_port ); |
1047 | // |
1048 | void Tvin_SetDepthOf2Dto3D ( int value ); |
1049 | int set3D_FL_Frame(int value); |
1050 | int setLatchFlag(int value); |
1051 | // |
1052 | int IsFileExist ( const char *file_name ); |
1053 | char *DelSub ( char *str, char *sub ); |
1054 | char *VDIN_CheckVideoPath ( const char *videopath ); |
1055 | int VDIN_AddPath ( const char *videopath ); |
1056 | int VDIN_RmDefPath ( void ); |
1057 | int VDIN_RmTvPath ( void ); |
1058 | int VDIN_AddVideoPath ( int selPath ); |
1059 | int VDIN_RmPreviewPath ( void ); |
1060 | int VDIN_GetVdinFd(); |
1061 | |
1062 | int VDIN_OpenModule(); |
1063 | int VDIN_CloseModule(); |
1064 | int VDIN_DeviceIOCtl ( int request, ... ); |
1065 | int VDIN_GetDeviceFileHandle(); |
1066 | int VDIN_OpenPort ( tvin_port_t port ); |
1067 | int VDIN_ClosePort(); |
1068 | int VDIN_StartDec ( const struct tvin_parm_s *vdinParam ); |
1069 | int VDIN_StopDec(); |
1070 | int VDIN_GetSignalInfo ( struct tvin_info_s *SignalInfo ); |
1071 | int VDIN_SetVdinParam ( const struct tvin_parm_s *vdinParam ); |
1072 | int VDIN_GetVdinParam ( const struct tvin_parm_s *vdinParam ); |
1073 | int VDIN_OnoffVScaler ( int isOn ); |
1074 | int VDIN_GetDisplayVFreq ( void ); |
1075 | int VDIN_SetDisplayVFreq ( int freq, int display_resolution , bool isFbc); |
1076 | |
1077 | int VDIN_Set2D3DDepth ( int count ); |
1078 | |
1079 | int VDIN_Set2Dto3D ( int on_off ); |
1080 | int VDIN_Set3DCmd ( int cmd ); |
1081 | |
1082 | int VDIN_Get_avg_luma(void); |
1083 | int VDIN_GetHistgram ( int *hisgram ); |
1084 | int VDIN_SetMVCViewMode ( int mode ); |
1085 | int VDIN_GetMVCViewMode ( void ); |
1086 | int VDIN_SetDIBuffMgrMode ( int mgr_mode ); |
1087 | int VDIN_SetDICFG ( int cfg ); |
1088 | int VDIN_SetDI3DDetc ( int enable ); |
1089 | int VDIN_Get3DDetc ( void ); |
1090 | int VDIN_GetVscalerStatus ( void ); |
1091 | int VDIN_TurnOnBlackBarDetect ( int isEnable ); |
1092 | int VDIN_LoadHdcpKey ( unsigned char *hdcpkey_buff ); |
1093 | int VDIN_KeepLastFrame ( int enable ); |
1094 | int VDIN_SetVideoFreeze ( int enable ); |
1095 | int VDIN_SetDIBypasshd ( int enable ); |
1096 | int VDIN_SetDIBypassAll ( int enable ); |
1097 | int VDIN_SetDIBypass_Get_Buf_Threshold ( int enable ); |
1098 | int VDIN_SetDIBypassProg ( int enable ); |
1099 | int VDIN_SetDIBypassDynamic ( int flag ); |
1100 | int VDIN_SetDIDet3DMode ( int value ); |
1101 | int VDIN_SetDIBypass3D ( int enable ); |
1102 | int VDIN_SetDIBypassPost ( int enable ); |
1103 | int VDIN_SetDIProg_Proc_Config ( int value ); |
1104 | int VDIN_SetDIInput2Pre ( int value ); |
1105 | int VDIN_SetVdinFlag ( int flag ); |
1106 | int VDIN_EnableRDMA ( int enable ); |
1107 | int VDIN_GetHdmiHdcpKeyKsvInfo(struct _hdcp_ksv *msg); |
1108 | int AFE_OpenModule ( void ); |
1109 | void AFE_CloseModule ( void ); |
1110 | int AFE_GetDeviceFileHandle(); |
1111 | int AFE_SetCVBSStd ( tvin_sig_fmt_t cvbs_fmt ); |
1112 | int AFE_SetVGAEdid ( const unsigned char *ediddata ); |
1113 | int AFE_GetVGAEdid ( unsigned char *ediddata ); |
1114 | int AFE_SetADCTimingAdjust ( const struct tvafe_vga_parm_s *timingadj ); |
1115 | int AFE_GetADCCurrentTimingAdjust ( struct tvafe_vga_parm_s *timingadj ); |
1116 | int AFE_VGAAutoAdjust ( struct tvafe_vga_parm_s *timingadj ); |
1117 | int AFE_SetVGAAutoAjust ( void ); |
1118 | int AFE_GetVGAAutoAdjustCMDStatus ( tvafe_cmd_status_t *Status ); |
1119 | int AFE_GetAdcCal ( struct tvafe_adc_cal_s *adccalvalue ); |
1120 | int AFE_SetAdcCal ( struct tvafe_adc_cal_s *adccalvalue ); |
1121 | int AFE_GetAdcCompCal ( struct tvafe_adc_comp_cal_s *adccalvalue ); |
1122 | int AFE_SetAdcCompCal ( struct tvafe_adc_comp_cal_s *adccalvalue ); |
1123 | int AFE_GetYPbPrWSSinfo ( struct tvafe_comp_wss_s *wssinfo ); |
1124 | unsigned int data_limit ( float data ); |
1125 | void matrix_convert_yuv709_to_rgb ( unsigned int y, unsigned int u, unsigned int v, unsigned int *r, unsigned int *g, unsigned int *b ); |
1126 | void re_order ( unsigned int *a, unsigned int *b ); |
1127 | char *get_cap_addr ( enum adc_cal_type_e calType ); |
1128 | inline unsigned char get_mem_data ( char *dp, unsigned int addr ); |
1129 | int get_frame_average ( enum adc_cal_type_e calType, struct adc_cal_s *mem_data ); |
1130 | struct adc_cal_s get_n_frame_average ( enum adc_cal_type_e calType ) ; |
1131 | int AFE_GetMemData ( int typeSel, struct adc_cal_s *mem_data ); |
1132 | int AFE_GetCVBSLockStatus ( enum tvafe_cvbs_video_e *cvbs_lock_status ); |
1133 | static int CvbsFtmToColorStdEnum(tvin_sig_fmt_t fmt); |
1134 | int VDIN_GetPortConnect ( int port ); |
1135 | int VDIN_OpenHDMIPinMuxOn ( bool flag ); |
1136 | int TVAFE_EnablePlugInDetect ( bool flag ); |
1137 | int GetITContent(); |
1138 | /*******************************************extend funs*********************/ |
1139 | static tv_source_input_type_t Tvin_SourcePortToSourceInputType ( tvin_port_t source_port ); |
1140 | static tv_source_input_type_t Tvin_SourceInputToSourceInputType ( tv_source_input_t source_input ); |
1141 | static tvin_port_t Tvin_GetSourcePortBySourceType ( tv_source_input_type_t source_type ); |
1142 | static tvin_port_t Tvin_GetSourcePortBySourceInput ( tv_source_input_t source_input ); |
1143 | static unsigned int Tvin_TransPortStringToValue(const char *port_str); |
1144 | static void Tvin_LoadSourceInputToPortMap(); |
1145 | static int Tvin_GetSourcePortByCECPhysicalAddress(int physical_addr); |
1146 | static tv_audio_channel_t Tvin_GetInputSourceAudioChannelIndex ( tv_source_input_t source_input ); |
1147 | static tv_audio_in_source_type_t Tvin_GetAudioInSourceType ( tv_source_input_t source_input ); |
1148 | static tv_source_input_t Tvin_PortToSourceInput ( tvin_port_t port ); |
1149 | static int isVgaFmtInHdmi ( tvin_sig_fmt_t fmt ); |
1150 | static int isSDFmtInHdmi ( tvin_sig_fmt_t fmt ); |
1151 | static bool Tvin_is50HzFrameRateFmt ( tvin_sig_fmt_t fmt ); |
1152 | static bool Tvin_IsDeinterlaceFmt ( tvin_sig_fmt_t fmt ); |
1153 | static v4l2_std_id CvbsFtmToV4l2ColorStd(tvin_sig_fmt_t fmt); |
1154 | |
1155 | static CTvin *getInstance(); |
1156 | |
1157 | public: |
1158 | class CTvinSigDetect: public CThread { |
1159 | public: |
1160 | static const int VDIN_NOSIG_DEFAULT_CHECK_TIMES = 1; |
1161 | CTvinSigDetect (); |
1162 | ~CTvinSigDetect(); |
1163 | int startDetect(bool bPause = true); |
1164 | int stopDetect(); |
1165 | int pauseDetect(); |
1166 | int resumeDetect(int later = 0); |
1167 | int initSigState(); |
1168 | void setVdinNoSigCheckKeepTimes(int times, bool isOnce);//times is time, ms |
1169 | int requestAndWaitPauseDetect(); |
1170 | //first pause detect? ok |
1171 | tvin_info_t &getCurSigInfo() |
1172 | { |
1173 | return m_cur_sig_info; |
1174 | } |
1175 | class ISigDetectObserver { |
1176 | public: |
1177 | ISigDetectObserver() |
1178 | {}; |
1179 | virtual ~ISigDetectObserver() |
1180 | {}; |
1181 | virtual void onSigToStable() |
1182 | {}; |
1183 | virtual void onSigStableToUnstable() {}; |
1184 | virtual void onSigStableToUnSupport() {}; |
1185 | virtual void onSigStableToNoSig() {}; |
1186 | virtual void onSigUnStableToUnSupport() {}; |
1187 | virtual void onSigUnStableToNoSig() {}; |
1188 | virtual void onSigNullToNoSig() {}; |
1189 | virtual void onSigNoSigToUnstable() {}; |
1190 | |
1191 | virtual void onSigStillStable() {}; |
1192 | virtual void onSigStillUnstable() {}; |
1193 | virtual void onSigStillNosig() {}; |
1194 | virtual void onSigStillNoSupport() {}; |
1195 | virtual void onSigStillNull() {}; |
1196 | virtual void onStableSigFmtChange() {}; |
1197 | virtual void onStableTransFmtChange() {}; |
1198 | |
1199 | virtual void onSigDetectEnter() {}; |
1200 | virtual void onSigDetectLoop() {}; |
1201 | }; |
1202 | void setObserver ( ISigDetectObserver *pOb ) |
1203 | { |
1204 | mpObserver = pOb; |
1205 | }; |
1206 | private: |
1207 | bool threadLoop(); |
1208 | int Tv_TvinSigDetect ( int &args ); |
1209 | |
1210 | //member |
1211 | tvin_info_t m_cur_sig_info; |
1212 | tvin_info_t m_pre_sig_info; |
1213 | int mKeepNosigTime; |
1214 | bool m_is_nosig_checktimes_once_valid; |
1215 | mutable CMutex mLock; |
1216 | CCondition mDetectPauseCondition; |
1217 | CCondition mRequestPauseCondition; |
1218 | volatile int m_sig_detect_status; |
1219 | volatile bool m_request_pause_detect; |
1220 | enum DetectState { |
1221 | STATE_STOPED = 0, |
1222 | STATE_RUNNING, |
1223 | STATE_PAUSE |
1224 | }; |
1225 | int mDetectState; |
1226 | int mResumeLaterTime; |
1227 | ISigDetectObserver *mpObserver; |
1228 | };// |
1229 | |
1230 | private: |
1231 | static CTvin *mInstance; |
1232 | int m_vdin_dev_fd; |
1233 | int afe_dev_fd; |
1234 | tvin_parm_t m_tvin_param; |
1235 | tvin_parm_t gTvinVDINParam; |
1236 | tvin_info_t gTvinVDINSignalInfo; |
1237 | tvin_parm_t gTvinAFEParam; |
1238 | tvin_info_t gTvinAFESignalInfo; |
1239 | static int mSourceInputToPortMap[SOURCE_MAX]; |
1240 | int gExistD2D3; |
1241 | char gVideoPath[256]; |
1242 | int m_is_decoder_start; |
1243 | |
1244 | enum tvin_path_id_e m_pathid; |
1245 | char config_tv_path[64]; |
1246 | char config_default_path[64]; |
1247 | }; |
1248 | #endif |
1249 |