| author | jie.yuan <jie.yuan@amlogic.com> | 2019-05-24 11:51:42 (GMT) |
|---|---|---|
| committer | jie.yuan <jie.yuan@amlogic.com> | 2019-05-24 11:51:42 (GMT) |
| commit | bacc893faae7a6752c180185ce766e3ae193278f (patch) | |
| tree | 01838dc0b735ed5267cd98d5676b3ddabe2b8d10 | |
| parent | b29c474eac6e7cdfac98ff58c9423297dc2ef2c8 (diff) | |
| parent | 24559ad7868e38d0ca2316a4917aaeb73593fa10 (diff) | |
| download | uboot-p-tv-openlinux-nov-1.3.zip uboot-p-tv-openlinux-nov-1.3.tar.gz uboot-p-tv-openlinux-nov-1.3.tar.bz2 | |
Merge remote-tracking branch 'remotes/openlinux/p-tv-openlinux-nov' into p-tv-openlinux-nov-1.3
71 files changed, 14166 insertions, 23 deletions
@@ -1199,6 +1199,8 @@ define filechk_version.h (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \ echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \ echo \#define CONFIG_SYSTEM_AS_ROOT \"${SYSTEMMODE}\"; \ + echo \#define CONFIG_BUILD_TYPE \"${BUILD_TYPE}\"; \ + echo \#define CONFIG_BOARD_NAME \"${BOARD_NAME}\"; \ echo \#define CONFIG_AVB2 \"${AVBMODE}\"; \ echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \ echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; ) @@ -1206,7 +1208,8 @@ endef define filechk_timestamp.h (LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ - LC_ALL=C date +'#define U_BOOT_TIME "%T"') + LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ + LC_ALL=C date +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"';) endef $(version_h): include/config/uboot.release FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a86d56d..c3ea307 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1017,6 +1017,7 @@ source "board/xaeniax/Kconfig" source "board/zipitz2/Kconfig" source "board/amlogic/Kconfig" +source "board/harman/Kconfig" source "customer/board/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c index b177a21..0204dd4 100644 --- a/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c +++ b/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c @@ -604,7 +604,8 @@ static unsigned int cec_handle_message(void) { unsigned char opcode; unsigned char source; - unsigned int phy_addr, wake; + unsigned int phy_addr; + __attribute__((unused)) unsigned int wake; source = (cec_msg.buf[cec_msg.rx_read_pos].msg[0] >> 4) & 0xf; if (((hdmi_cec_func_config>>CEC_FUNC_MASK) & 0x1) && diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig index f0bb887..9816005 100644..100755 --- a/board/amlogic/Kconfig +++ b/board/amlogic/Kconfig @@ -43,6 +43,10 @@ config GXL_SKT_V1 bool "Support amlogic gxl socket v1 board" default n +config GXL_SEI210_V1 + bool "Support amlogic gxl sei210 board" + default n + config GXL_P212_V1 bool "Support amlogic gxl p212 board" default n @@ -188,6 +192,10 @@ config G12A_U212_V1 bool "Support amlogic g12a u212 v1 board" default n +config G12A_DEADPOOL_V1 + bool "Support amlogic g12a deadpool v1 board" + default n + config G12A_U220_V1 bool "Support amlogic g12a u220 v1 board" default n @@ -213,7 +221,11 @@ config SM1_AC200_V1 default n config SM1_AC213_V1 - bool "Support amlogic sm1 ac213 v1 board" + bool "Support amlogic sm1 ac213 v1 board" + default n + +config SM1_SABRINA_V1 + bool "Support amlogic sm1 sabrina v1 board" default n config PXP_EMULATOR @@ -275,6 +287,10 @@ if GXL_P212_V1 source "board/amlogic/gxl_p212_v1/Kconfig" endif +if GXL_SEI210_V1 +source "board/amlogic/gxl_beast_v1/Kconfig" +endif + if GXL_P281_V1 source "board/amlogic/gxl_p281_v1/Kconfig" endif @@ -416,6 +432,10 @@ if G12A_U212_V1 source "board/amlogic/g12a_u212_v1/Kconfig" endif +if G12A_DEADPOOL_V1 +source "board/amlogic/g12a_deadpool_v1/Kconfig" +endif + if G12A_U220_V1 source "board/amlogic/g12a_u220_v1/Kconfig" endif @@ -444,6 +464,10 @@ if SM1_AC213_V1 source "board/amlogic/sm1_ac213_v1/Kconfig" endif +if SM1_SABRINA_V1 +source "board/amlogic/sm1_sabrina_v1/Kconfig" +endif + if ODROID_C2 source "board/hardkernel/odroidc2/Kconfig" endif diff --git a/board/amlogic/configs/g12a_deadpool_v1.h b/board/amlogic/configs/g12a_deadpool_v1.h new file mode 100644 index 0000000..1549220 --- a/dev/null +++ b/board/amlogic/configs/g12a_deadpool_v1.h @@ -0,0 +1,664 @@ + +/* + * board/amlogic/configs/g12a_u212_v1.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __G12A_DEADPOOL_V1_H__ +#define __G12A_DEADPOOL_V1_H__ + +#include <asm/arch/cpu.h> + +#define CONFIG_SYS_GENERIC_BOARD 1 +#ifndef CONFIG_AML_MESON +#warning "include warning" +#endif + +/* + * platform power init config + */ +#define CONFIG_PLATFORM_POWER_INIT +#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage +#define CONFIG_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage +#define CONFIG_VDDEE_SLEEP_VOLTAGE 770 // VDDEE suspend voltage + +/* configs for CEC */ +#define CONFIG_CEC_OSD_NAME "AML_TV" +#define CONFIG_CEC_WAKEUP +/*if use bt-wakeup,open it*/ +#define CONFIG_BT_WAKEUP +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* config saradc*/ +#define CONFIG_CMD_SARADC 1 + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#define CONFIG_CMD_BOOTCTOL_AVB + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_AML_MESON_SERIAL 1 +#define CONFIG_SERIAL_MULTI 1 + +//Enable ir remote wake up for bl30 +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=1080000\0"\ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x1000000\0" \ + "fb_addr=0x3d800000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=update 1000\0" \ + "fdt_high=0x20000000\0"\ + "try_auto_burn=update 700 750;\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "sdc_burning=sdc_burn ${sdcburncfg}\0"\ + "wipe_data=successful\0"\ + "wipe_cache=successful\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "lock=10001000\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "reboot_mode_android=""normal""\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then "\ + "run init_display; run storeargs; run update;"\ + "else fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "else if test ${reboot_mode} = fastboot -o ${reboot_mode} = bootloader; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "boot_cooling;"\ + "get_system_as_root_mode;"\ + "echo system_mode: ${system_mode};"\ + "if test ${system_mode} = 1; then "\ + "setenv fs_type ""ro rootwait skip_initramfs"";"\ + "run storeargs;"\ + "fi;"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot: ${active_slot};"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if test ${avb2} = 0; then "\ + "if test ${active_slot} = _a; then "\ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\ + "else if test ${active_slot} = _b; then "\ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\ + "fi;fi;"\ + "fi;"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "run update;"\ + "\0"\ + "factory_reset_poweroff_protect="\ + "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\ + "if test ${wipe_data} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; "\ + "if test ${wipe_cache} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; \0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run sdc_burning; "\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_sdcard="\ + "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload mmc 0 ${loadaddr} recovery.img; then "\ + "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload usb 0 ${loadaddr} recovery.img; then "\ + "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\ + "setenv serial 1234567890;"\ + "fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOAO_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + "recovery_key="\ + "if gpio input GPIOAO_3; then "\ + "echo detect recovery key; run recovery_from_flash;"\ + "fi;"\ + "\0"\ + "irremote_update="\ + "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\ + "echo read irkey ok!; " \ + "if itest ${irkey_value} == 0xe31cfb04; then " \ + "run update;" \ + "else if itest ${irkey_value} == 0xb748fb04; then " \ + "run update;\n" \ + "fi;fi;" \ + "fi;\0" \ + + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run factory_reset_poweroff_protect;"\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run recovery_key;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" + +#define CONFIG_BOOTCOMMAND "run storeboot" + +//#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_ANDROID_IMG 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* cpu */ +#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd +#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd +#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_STORE_COMPATIBLE 1 +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CMD_SAVEENV +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ +/* support for mtd */ +#define CONFIG_AML_MTD 1 +/* support for nftl */ +//#define CONFIG_AML_NAND 1 + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD) +#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime; +#endif + +#ifdef CONFIG_AML_MTD + +/* bootlaoder is construct by bl2 and fip + * when DISCRETE_BOOTLOADER is enabled, bl2 & fip + * will not be stored continuously, and nand layout + * would be bl2|rsv|fip|normal, but not + * bl2|fip|rsv|noraml anymore + */ +#define CONFIG_DISCRETE_BOOTLOADER + +#ifdef CONFIG_DISCRETE_BOOTLOADER +#define CONFIG_TPL_SIZE_PER_COPY 0x200000 +#define CONFIG_TPL_COPY_NUM 4 +#define CONFIG_TPL_PART_NAME "tpl" +/* for bl2, restricted by romboot */ +//SKT 1024 pages only support 4 block, so 4 copies +#define CONFIG_BL2_COPY_NUM 4 +#endif /* CONFIG_DISCRETE_BOOTLOADER */ + +#define CONFIG_CMD_NAND 1 +#define CONFIG_MTD_DEVICE y +/* mtd parts of ourown.*/ +#define CONFIFG_AML_MTDPART 1 +/* mtd parts by env default way.*/ +/* +#define MTDIDS_NAME_STR "aml_nand.0" +#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "3M@8192K(logo)," \ + "10M(recovery)," \ + "8M(kernel)," \ + "40M(rootfs)," \ + "-(data)" +*/ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_CMD_NAND_TORTURE 1 +#define CONFIG_CMD_MTDPARTS 1 +#define CONFIG_MTD_PARTITIONS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_SYS_NAND_BASE_LIST {0} +#endif +/* endof CONFIG_AML_MTD */ +#define CONFIG_AML_SD_EMMC 1 +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#define CONFIG_SYS_NO_FLASH 1 +//#define CONFIG_AML_GPT + +/* meson SPI */ +#define CONFIG_AML_SPIFC +//#define CONFIG_AML_SPICC +#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC + #define CONFIG_OF_SPI + #define CONFIG_DM_SPI + #define CONFIG_CMD_SPI +#endif +/* SPI flash config */ +#ifdef CONFIG_AML_SPIFC + #define CONFIG_SPI_FLASH + #define CONFIG_DM_SPI_FLASH + #define CONFIG_CMD_SF + /* SPI flash surpport list */ + #define CONFIG_SPI_FLASH_ATMEL + #define CONFIG_SPI_FLASH_EON + #define CONFIG_SPI_FLASH_GIGADEVICE + #define CONFIG_SPI_FLASH_MACRONIX + #define CONFIG_SPI_FLASH_SPANSION + #define CONFIG_SPI_FLASH_STMICRO + #define CONFIG_SPI_FLASH_SST + #define CONFIG_SPI_FLASH_WINBOND + #define CONFIG_SPI_FRAM_RAMTRON + #define CONFIG_SPI_M95XXX + #define CONFIG_SPI_FLASH_ESMT + /* SPI nand flash support */ + #define CONFIG_SPI_NAND + #define CONFIG_BL2_SIZE (64 * 1024) +#endif + +#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE y + #define CONFIG_RBTREE + #define CONFIG_CMD_NAND_TORTURE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_SYS_MAX_NAND_DEVICE 2 + #define CONFIG_SYS_NAND_BASE_LIST {0} +#endif + +/* vpu */ +#define CONFIG_AML_VPU 1 +//#define CONFIG_VPU_CLK_LEVEL_DFT 7 + +/* DISPLAY & HDMITX */ +#define CONFIG_AML_HDMITX20 1 +#define CONFIG_AML_CANVAS 1 +#define CONFIG_AML_VOUT 1 +#define CONFIG_AML_OSD 1 +#define CONFIG_AML_MINUI 1 +#define CONFIG_OSD_SCALE_ENABLE 1 +#define CONFIG_CMD_BMP 1 + +#if defined(CONFIG_AML_VOUT) +#define CONFIG_AML_CVBS 1 +#endif + +// #define CONFIG_AML_LCD 1 +// #define CONFIG_AML_LCD_TABLET 1 +// #define CONFIG_AML_LCD_EXTERN 1 + + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +#define CONFIG_CMD_USB 1 +#if defined(CONFIG_CMD_USB) + #define CONFIG_GXL_XHCI_BASE 0xff500000 + #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000 + #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080 + #define CONFIG_USB_PHY_20 0xff636000 + #define CONFIG_USB_PHY_21 0xff63A000 + #define CONFIG_USB_STORAGE 1 + #define CONFIG_USB_XHCI 1 + #define CONFIG_USB_XHCI_AMLOGIC_V2 1 + #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6) + #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6" + //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1 +#endif //#if defined(CONFIG_CMD_USB) + +#define CONFIG_TXLX_USB 1 +#define CONFIG_USB_DEVICE_V2 1 +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +//UBOOT fastboot config +#define CONFIG_CMD_FASTBOOT 1 +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#define CONFIG_FASTBOOT_FLASH 1 +#define CONFIG_USB_GADGET 1 +#define CONFIG_USBDOWNLOAD_GADGET 1 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000 +#define CONFIG_DEVICE_PRODUCT "deadpool" + +//UBOOT Facotry usb/sdcard burning config +#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning +#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning +#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning +#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning + +#define CONFIG_AML_SECURITY_KEY 1 +#define CONFIG_UNIFY_KEY_MANAGE 1 + +/* net */ +#define CONFIG_CMD_NET 1 +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME arm_gxbb +// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +/* other devices */ +/* I2C DM driver*/ +//#define CONFIG_DM_I2C + +#if defined(CONFIG_DM_I2C) +#define CONFIG_SYS_I2C_MESON 1 +#else +#define CONFIG_SYS_I2C_AML 1 +#define CONFIG_SYS_I2C_SPEED 400000 +#endif + +#define CONFIG_EFUSE 1 + +/* commands */ +#define CONFIG_CMD_CACHE 1 +#define CONFIG_CMD_BOOTI 1 +#define CONFIG_CMD_EFUSE 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_GPIO 1 +#define CONFIG_CMD_RUN +#define CONFIG_CMD_REBOOT 1 +#define CONFIG_CMD_ECHO 1 +#define CONFIG_CMD_JTAG 1 +#define CONFIG_CMD_AUTOSCRIPT 1 +#define CONFIG_CMD_MISC 1 + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +#define CONFIG_AML_PARTITION 1 +#define CONFIG_MMC 1 +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +//#define CONFIG_SYS_DCACHE_OFF +//#define CONFIG_SYS_ICACHE_OFF + +/* other functions */ +#define CONFIG_NEED_BL301 1 +#define CONFIG_NEED_BL32 1 +#define CONFIG_CMD_RSVMEM 1 +#define CONFIG_FIP_IMG_SUPPORT 1 +#define CONFIG_BOOTDELAY 1 //delay 1s +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMD_MISC 1 +#define CONFIG_CMD_ITEST 1 +#define CONFIG_CMD_CPU_TEMP 1 +#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve +#define CONFIG_CMD_LOADB 1 + +//#define CONFIG_MULTI_DTB 1 + +/* debug mode defines */ +//#define CONFIG_DEBUG_MODE 1 +#ifdef CONFIG_DEBUG_MODE +#define CONFIG_DDR_CLK_DEBUG 636 +#define CONFIG_CPU_CLK_DEBUG 600 +#endif + +//support secure boot +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +//for SRAM size limitation just disable NAND +//as the socket board default has no NAND +//#undef CONFIG_AML_NAND + +//unify build for generate encrypted bootloader "u-boot.bin.encrypt" +#define CONFIG_AML_CRYPTO_UBOOT 1 + +//unify build for generate encrypted kernel image +//SRC : "board/amlogic/(board)/boot.img" +//DST : "fip/boot.img.encrypt" +//#define CONFIG_AML_CRYPTO_IMG 1 + +#endif //CONFIG_AML_SECURE_UBOOT + +#define CONFIG_SECURE_STORAGE 1 + +//build with uboot auto test +//#define CONFIG_AML_UBOOT_AUTO_TEST 1 + +//board customer ID +//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) + +#if defined(CONFIG_CUSTOMER_ID) + #undef CONFIG_AML_CUSTOMER_ID + #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID +#endif + +/* Choose One of Ethernet Type */ +#undef CONFIG_ETHERNET_NONE +#define ETHERNET_INTERNAL_PHY +#undef ETHERNET_EXTERNAL_PHY + +#define CONFIG_HIGH_TEMP_COOL 90 +#endif + diff --git a/board/amlogic/configs/gxl_beast_v1.h b/board/amlogic/configs/gxl_beast_v1.h new file mode 100644 index 0000000..a7dd1fa --- a/dev/null +++ b/board/amlogic/configs/gxl_beast_v1.h @@ -0,0 +1,613 @@ + +/* + * board/amlogic/configs/gxl_sei210_v1.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __GXL_SEI210_V1_H__ +#define __GXL_SEI210_V1_H__ + +#ifndef __SUSPEND_FIRMWARE__ +#include <asm/arch/cpu.h> +#endif /* for compile problem of A53 and m3 */ + +#define CONFIG_SYS_GENERIC_BOARD 1 +#ifndef __SUSPEND_FIRMWARE__ +#ifndef CONFIG_AML_MESON +#warning "include warning" +#endif +#endif /* for compile problem of A53 and m3 */ + +/* + * platform power init config + */ +#define CONFIG_PLATFORM_POWER_INIT +#define CONFIG_VCCK_INIT_VOLTAGE 1120 +#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up +#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend + +#define CONFIG_SEI_FASTBOOT 1 +/* configs for CEC */ +#define CONFIG_CEC_OSD_NAME "Mbox" +#define CONFIG_CEC_WAKEUP + +#define CONFIG_INSTABOOT +/* configs for dtb in boot.img */ +//#define DTB_BIND_KERNEL + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* config saradc*/ +#define CONFIG_CMD_SARADC 1 + +/*config irblaster*/ +#define CONFIG_CMD_IRBLASTER 1 + +/* support ext4*/ +#define CONFIG_CMD_EXT4 1 + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +/*a/b update */ +#define CONFIG_CMD_BOOTCTOL_AVB + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_AML_MESON_SERIAL 1 +#define CONFIG_SERIAL_MULTI 1 + +//Enable ir remote wake up for bl30 +//#define CONFIG_IR_REMOTE +//#define CONFIG_AML_IRDETECT_EARLY +#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4 +#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+ +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch- +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02 + +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=0\0"\ + "upgrade_step=0\0"\ + "jtag=apao\0"\ + "loadaddr=1080000\0"\ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd1\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x1000000\0" \ + "fb_addr=0x3d800000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=update 1000\0" \ + "fdt_high=0x20000000\0"\ + "lock=00000000\0"\ + "try_auto_burn=update 700 750;\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "sdc_burning=sdc_burn ${sdcburncfg}\0"\ + "wipe_data=successful\0"\ + "wipe_cache=successful\0"\ + "EnableSelinux=enforcing\0"\ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "active_slot=normal\0"\ + "page_trace=on\0"\ + "boot_part=boot\0"\ + "rpmb_state=0\0"\ + "upgradekey_val=0\0"\ + "reboot_mode_android=""normal""\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then "\ + "run init_display; run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "setenv bootargs ${bootargs} page_trace=${page_trace};" \ + "setenv bootargs ${bootargs} androidboot.rpmb_state=${rpmb_state};"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run update;"\ + "else if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "fastboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1; run try_auto_burn;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1; run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run try_auto_burn;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "get_system_as_root_mode;"\ + "echo system_mode: ${system_mode};"\ + "if test ${system_mode} = 1; then "\ + "setenv fs_type ""ro rootwait skip_initramfs"";"\ + "run storeargs;"\ + "fi;"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot: ${active_slot} avb2: ${avb2};"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if test ${avb2} = 0; then "\ + "if test ${active_slot} = _a; then "\ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\ + "else if test ${active_slot} = _b; then "\ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\ + "fi;fi;"\ + "fi;"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "run update;"\ + "\0"\ + "factory_reset_poweroff_protect="\ + "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\ + "if test ${wipe_data} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; "\ + "if test ${wipe_cache} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; \0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run sdc_burning; "\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload mmc 0 ${loadaddr} recovery.img; then "\ + "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload usb 0 ${loadaddr} recovery.img; then "\ + "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if itest ${upgrade_step} == 3; then "\ + "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\ + "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\ + "else fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1; osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1; osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale; "\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\ + "setenv serial 1234567890;"\ + "fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "if keyman read region_code ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "\0"\ + "upgrade_key="\ + "if detect_upgradekey;then "\ + "if test ${upgradekey_val} = fastboot ; then "\ + "osd clear;imgread pic logo fastboot $loadaddr;bmp display $fastboot_offset;bmp scale; "\ + "fastboot;"\ + "else if test ${upgradekey_val} = upgrade; then "\ + "run update;"\ + "fi;"\ + "fi;"\ + "fi;"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run factory_reset_poweroff_protect;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" + +#define CONFIG_BOOTCOMMAND \ + "run upgrade_check;"\ + "bcb uboot-command;" \ + "run switch_bootmode;" \ + "run storeboot;" + + +//#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_ANDROID_IMG 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* cpu */ +#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24 + +/* ddr */ +#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect +#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24 +#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip +/* DDR type setting + * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3 + * CONFIG_DDR_TYPE_DDR3 : DDR3 + * CONFIG_DDR_TYPE_DDR4 : DDR4 + * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */ +#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO +/* DDR channel setting, please refer hardware design. + * CONFIG_DDR0_RANK0 : DDR0 rank0 + * CONFIG_DDR0_RANK01 : DDR0 rank0+1 + * CONFIG_DDR0_16BIT : DDR0 16bit mode + * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */ +#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO +#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test +#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd +#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd +#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window + +/* storage: emmc/nand/sd */ +#define CONFIG_STORE_COMPATIBLE 1 +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +*/ + +/* swither for mtd nand which is for slc only. */ +/* support for mtd */ +//#define CONFIG_AML_MTD 1 +/* support for nftl */ +#define CONFIG_AML_NAND 1 + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD) +#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime; +#endif + +#ifdef CONFIG_AML_MTD +#define CONFIG_CMD_NAND 1 +#define CONFIG_MTD_DEVICE y +/* mtd parts of ourown.*/ +#define CONFIFG_AML_MTDPART 1 +/* mtd parts by env default way.*/ +/* +#define MTDIDS_NAME_STR "aml_nand.0" +#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "3M@8192K(logo)," \ + "10M(recovery)," \ + "8M(kernel)," \ + "40M(rootfs)," \ + "-(data)" +*/ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_CMD_NAND_TORTURE 1 +#define CONFIG_CMD_MTDPARTS 1 +#define CONFIG_MTD_PARTITIONS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_SYS_NAND_BASE_LIST {0} +#endif +/* endof CONFIG_AML_MTD */ + + +#define CONFIG_AML_SD_EMMC 1 +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 + /* + flash/erase operation region on boot1 + in bytes, 2M by default + */ + //#define CONFIG_EMMC_BOOT1_TOUCH_REGION (0x200000) + +#endif +/* storage macro checks */ +#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND) +#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled. +#endif + +/* env */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CMD_SAVEENV + + +/* env checks */ +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +#define CONFIG_PARTITIONS 1 +#define CONFIG_SYS_NO_FLASH 1 + +/* vpu */ +#define CONFIG_AML_VPU 1 +#define CONFIG_VPU_CLK_LEVEL_DFT 7 + +/* DISPLAY & HDMITX */ +#define CONFIG_AML_HDMITX20 1 +#define CONFIG_AML_CANVAS 1 +#define CONFIG_AML_VOUT 1 +#define CONFIG_AML_OSD 1 +#define CONFIG_OSD_SCALE_ENABLE 1 +#define CONFIG_CMD_BMP 1 + +#if defined(CONFIG_AML_VOUT) +#define CONFIG_AML_CVBS 1 +#endif + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +#define CONFIG_CMD_USB 1 +#if defined(CONFIG_CMD_USB) + #define CONFIG_GXL_XHCI_BASE 0xc9000000 + #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000 + #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080 + #define CONFIG_USB_STORAGE 1 + #define CONFIG_USB_XHCI 1 + #define CONFIG_USB_XHCI_AMLOGIC_GXL 1 +#endif //#if defined(CONFIG_CMD_USB) + +//UBOOT fastboot config +#define CONFIG_CMD_FASTBOOT 1 +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#ifdef CONFIG_AML_MTD +#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1 +#endif +#define CONFIG_FASTBOOT_FLASH 1 +#define CONFIG_USB_GADGET 1 +#define CONFIG_USBDOWNLOAD_GADGET 1 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000 +#define CONFIG_DEVICE_PRODUCT "Beast" + +//UBOOT Facotry usb/sdcard burning config +#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning +#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning +#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning +#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning + +#define CONFIG_AML_SECURITY_KEY 1 +#ifndef DTB_BIND_KERNEL +#define CONFIG_UNIFY_KEY_MANAGE 1 +#endif + +/* net */ +#define CONFIG_CMD_NET 1 +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME arm_gxbb + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +/* other devices */ +#define CONFIG_EFUSE 1 +#define CONFIG_SYS_I2C_AML 1 +#define CONFIG_SYS_I2C_SPEED 400000 + +/* commands */ +#define CONFIG_CMD_CACHE 1 +#define CONFIG_CMD_BOOTI 1 +#define CONFIG_CMD_EFUSE 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_GPIO 1 +#define CONFIG_CMD_RUN +#define CONFIG_CMD_REBOOT 1 +#define CONFIG_CMD_ECHO 1 +#define CONFIG_CMD_JTAG 1 +#define CONFIG_CMD_AUTOSCRIPT 1 +#define CONFIG_CMD_MISC 1 + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_AML_PARTITION 1 +#define CONFIG_MMC 1 +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +//#define CONFIG_SYS_DCACHE_OFF +//#define CONFIG_SYS_ICACHE_OFF + +/* other functions */ +#define CONFIG_NEED_BL301 1 +#define CONFIG_NEED_BL32 1 +#define CONFIG_CMD_RSVMEM 1 +#define CONFIG_FIP_IMG_SUPPORT 1 +#define CONFIG_BOOTDELAY 1 //delay 1s +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMD_MISC 1 +#define CONFIG_CMD_ITEST 1 +#define CONFIG_CMD_CPU_TEMP 1 +#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve +#define CONFIG_MULTI_DTB 1 + +#define CONFIG_CMD_CHIPID 1 +/* debug mode defines */ +//#define CONFIG_DEBUG_MODE 1 +#ifdef CONFIG_DEBUG_MODE +#define CONFIG_DDR_CLK_DEBUG 636 +#define CONFIG_CPU_CLK_DEBUG 600 +#endif + +//support secure boot +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +//for SRAM size limitation just disable NAND +//as the socket board default has no NAND +//#undef CONFIG_AML_NAND + +//unify build for generate encrypted bootloader "u-boot.bin.encrypt" +#define CONFIG_AML_CRYPTO_UBOOT 1 + +//unify build for generate encrypted kernel image +//SRC : "board/amlogic/(board)/boot.img" +//DST : "fip/boot.img.encrypt" +//#define CONFIG_AML_CRYPTO_IMG 1 + +#endif //CONFIG_AML_SECURE_UBOOT + +#define CONFIG_SECURE_STORAGE 1 + +//build with uboot auto test +//#define CONFIG_AML_UBOOT_AUTO_TEST 1 + +//board customer ID +//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) + +#if defined(CONFIG_CUSTOMER_ID) + #undef CONFIG_AML_CUSTOMER_ID + #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID +#endif +#define CONFIG_INTERNAL_PHY + +//#define CONFIG_AVB2 + +#endif + diff --git a/board/amlogic/configs/sm1_sabrina_v1.h b/board/amlogic/configs/sm1_sabrina_v1.h new file mode 100755 index 0000000..efe3df5 --- a/dev/null +++ b/board/amlogic/configs/sm1_sabrina_v1.h @@ -0,0 +1,680 @@ + +/* + * board/amlogic/configs/sm1_sabrina_v1.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __SM1_SABRINA_V1_H__ +#define __SM1_SABRINA_V1_H__ + +#include <asm/arch/cpu.h> + +#define CONFIG_SYS_GENERIC_BOARD 1 +#ifndef CONFIG_AML_MESON +#warning "include warning" +#endif + +/* + * platform power init config + */ +#define CONFIG_PLATFORM_POWER_INIT +#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage +#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage +#define CONFIG_VDDEE_SLEEP_VOLTAGE 770 // VDDEE suspend voltage + +/* configs for CEC */ +#define CONFIG_CEC_OSD_NAME "AML_TV" +#define CONFIG_CEC_WAKEUP +/*if use bt-wakeup,open it*/ +#define CONFIG_BT_WAKEUP +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* config saradc*/ +#define CONFIG_CMD_SARADC 1 +#define CONFIG_SARADC_CH 2 + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#define CONFIG_CMD_BOOTCTOL_AVB + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_AML_MESON_SERIAL 1 +#define CONFIG_SERIAL_MULTI 1 + +//Enable ir remote wake up for bl30 +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=1080000\0"\ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x1000000\0" \ + "fb_addr=0x3d800000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "sdr2hdr=2\0" \ + "hdmi_read_edid=1\0" \ + "usb_burning=update 1000\0" \ + "fdt_high=0x20000000\0"\ + "try_auto_burn=update 700 750;\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "sdc_burning=sdc_burn ${sdcburncfg}\0"\ + "wipe_data=successful\0"\ + "wipe_cache=successful\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "lock=10001000\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "reboot_mode_android=""normal""\0"\ + "Irq_check_en=0\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then "\ + "run init_display; run storeargs; run update;"\ + "else fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "else if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "boot_cooling;"\ + "get_system_as_root_mode;"\ + "echo system_mode: ${system_mode};"\ + "if test ${system_mode} = 1; then "\ + "setenv fs_type ""ro rootwait skip_initramfs"";"\ + "run storeargs;"\ + "fi;"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot: ${active_slot};"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if test ${avb2} = 0; then "\ + "if test ${active_slot} = _a; then "\ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\ + "else if test ${active_slot} = _b; then "\ + "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\ + "fi;fi;"\ + "fi;"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "run update;"\ + "\0"\ + "factory_reset_poweroff_protect="\ + "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\ + "if test ${wipe_data} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; "\ + "if test ${wipe_cache} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; \0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run sdc_burning; "\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_sdcard="\ + "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload mmc 0 ${loadaddr} recovery.img; then "\ + "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload usb 0 ${loadaddr} recovery.img; then "\ + "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;hdmitx get_preferred_mode;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\ + "setenv serial 1234567890;"\ + "fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "if keyman read region_code ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOAO_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + "irremote_update="\ + "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\ + "echo read irkey ok!; " \ + "if itest ${irkey_value} == 0xe31cfb04; then " \ + "run update;" \ + "else if itest ${irkey_value} == 0xb748fb04; then " \ + "run update;\n" \ + "fi;fi;" \ + "fi;\0" \ + + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run factory_reset_poweroff_protect;"\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" \ + "forceupdate;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" + +#define CONFIG_BOOTCOMMAND "run storeboot" + +//#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_ANDROID_IMG 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* cpu */ +#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd +#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd +#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_STORE_COMPATIBLE 1 +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CMD_SAVEENV +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ +/* support for mtd */ +#define CONFIG_AML_MTD 1 +/* support for nftl */ +//#define CONFIG_AML_NAND 1 + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD) +#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime; +#endif + +#ifdef CONFIG_AML_MTD + +/* bootlaoder is construct by bl2 and fip + * when DISCRETE_BOOTLOADER is enabled, bl2 & fip + * will not be stored continuously, and nand layout + * would be bl2|rsv|fip|normal, but not + * bl2|fip|rsv|noraml anymore + */ +#define CONFIG_DISCRETE_BOOTLOADER + +#ifdef CONFIG_DISCRETE_BOOTLOADER +#define CONFIG_TPL_SIZE_PER_COPY 0x200000 +#define CONFIG_TPL_COPY_NUM 4 +#define CONFIG_TPL_PART_NAME "tpl" +/* for bl2, restricted by romboot */ +//SKT 1024 pages only support 4 block, so 4 copies +#define CONFIG_BL2_COPY_NUM 4 +#endif /* CONFIG_DISCRETE_BOOTLOADER */ + +#define CONFIG_CMD_NAND 1 +#define CONFIG_MTD_DEVICE y +/* mtd parts of ourown.*/ +#define CONFIFG_AML_MTDPART 1 +/* mtd parts by env default way.*/ +/* +#define MTDIDS_NAME_STR "aml_nand.0" +#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "3M@8192K(logo)," \ + "10M(recovery)," \ + "8M(kernel)," \ + "40M(rootfs)," \ + "-(data)" +*/ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_CMD_NAND_TORTURE 1 +#define CONFIG_CMD_MTDPARTS 1 +#define CONFIG_MTD_PARTITIONS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_SYS_NAND_BASE_LIST {0} +#endif +/* endof CONFIG_AML_MTD */ +#define CONFIG_AML_SD_EMMC 1 +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#define CONFIG_SYS_NO_FLASH 1 +//#define CONFIG_AML_GPT + +/* meson SPI */ +#define CONFIG_AML_SPIFC +//#define CONFIG_AML_SPICC +#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC + #define CONFIG_OF_SPI + #define CONFIG_DM_SPI + #define CONFIG_CMD_SPI +#endif +/* SPI flash config */ +#ifdef CONFIG_AML_SPIFC + #define CONFIG_SPI_FLASH + #define CONFIG_DM_SPI_FLASH + #define CONFIG_CMD_SF + /* SPI flash surpport list */ + #define CONFIG_SPI_FLASH_ATMEL + #define CONFIG_SPI_FLASH_EON + #define CONFIG_SPI_FLASH_GIGADEVICE + #define CONFIG_SPI_FLASH_MACRONIX + #define CONFIG_SPI_FLASH_SPANSION + #define CONFIG_SPI_FLASH_STMICRO + #define CONFIG_SPI_FLASH_SST + #define CONFIG_SPI_FLASH_WINBOND + #define CONFIG_SPI_FRAM_RAMTRON + #define CONFIG_SPI_M95XXX + #define CONFIG_SPI_FLASH_ESMT + /* SPI nand flash support */ + #define CONFIG_SPI_NAND + #define CONFIG_BL2_SIZE (64 * 1024) +#endif + +#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE y + #define CONFIG_RBTREE + #define CONFIG_CMD_NAND_TORTURE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_SYS_MAX_NAND_DEVICE 2 + #define CONFIG_SYS_NAND_BASE_LIST {0} +#endif + +/* vpu */ +#define CONFIG_AML_VPU 1 +//#define CONFIG_VPU_CLK_LEVEL_DFT 7 + +/* DISPLAY & HDMITX */ +#define CONFIG_AML_HDMITX20 1 +#define CONFIG_AML_CANVAS 1 +#define CONFIG_AML_VOUT 1 +#define CONFIG_AML_OSD 1 +#define CONFIG_OSD_SCALE_ENABLE 1 +#define CONFIG_CMD_BMP 1 +#define CONFIG_AML_MINUI 1 + +#if defined(CONFIG_AML_VOUT) +#define CONFIG_AML_CVBS 1 +#endif + +//#define CONFIG_AML_LCD 1 +//#define CONFIG_AML_LCD_TABLET 1 +//#define CONFIG_AML_LCD_EXTERN 1 + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +#define CONFIG_CMD_USB 1 +#if defined(CONFIG_CMD_USB) + #define CONFIG_GXL_XHCI_BASE 0xff500000 + #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000 + #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080 + #define CONFIG_USB_PHY_20 0xff636000 + #define CONFIG_USB_PHY_21 0xff63A000 + #define CONFIG_USB_STORAGE 1 + #define CONFIG_USB_XHCI 1 + #define CONFIG_USB_XHCI_AMLOGIC_V2 1 + #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6) + #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6" + //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1 +#endif //#if defined(CONFIG_CMD_USB) + +#define CONFIG_TXLX_USB 1 +#define CONFIG_USB_DEVICE_V2 1 +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +//UBOOT fastboot config +#define CONFIG_CMD_FASTBOOT 1 +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#define CONFIG_FASTBOOT_FLASH 1 +#define CONFIG_USB_GADGET 1 +#define CONFIG_USBDOWNLOAD_GADGET 1 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000 +#define CONFIG_DEVICE_PRODUCT "sabrina" + +//UBOOT Facotry usb/sdcard burning config +#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning +#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning +#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning +#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning + +#define CONFIG_AML_SECURITY_KEY 1 +#define CONFIG_UNIFY_KEY_MANAGE 1 + +/* net */ +#define CONFIG_CMD_NET 1 +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME arm_gxbb +// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +/* other devices */ +/* I2C DM driver*/ +//#define CONFIG_DM_I2C + +#if defined(CONFIG_DM_I2C) +#define CONFIG_SYS_I2C_MESON 1 +#else +#define CONFIG_SYS_I2C_AML 1 +#define CONFIG_SYS_I2C_SPEED 400000 +#endif + +#define CONFIG_EFUSE 1 + +/* commands */ +#define CONFIG_CMD_CACHE 1 +#define CONFIG_CMD_BOOTI 1 +#define CONFIG_CMD_EFUSE 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_GPIO 1 +#define CONFIG_CMD_RUN +#define CONFIG_CMD_REBOOT 1 +#define CONFIG_CMD_ECHO 1 +#define CONFIG_CMD_JTAG 1 +#define CONFIG_CMD_AUTOSCRIPT 1 +#define CONFIG_CMD_MISC 1 + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +#define CONFIG_AML_PARTITION 1 +#define CONFIG_MMC 1 +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +#define CONFIG_MDUMP_COMPRESS 1 + +/* Cache Definitions */ +//#define CONFIG_SYS_DCACHE_OFF +//#define CONFIG_SYS_ICACHE_OFF + +/* other functions */ +#define CONFIG_NEED_BL301 1 +#define CONFIG_NEED_BL32 1 +#define CONFIG_CMD_RSVMEM 1 +#define CONFIG_FIP_IMG_SUPPORT 1 +#define CONFIG_BOOTDELAY 1 //delay 1s +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMD_MISC 1 +#define CONFIG_CMD_ITEST 1 +#define CONFIG_CMD_CPU_TEMP 1 +#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve +#define CONFIG_CMD_LOADB 1 + +#define CONFIG_MULTI_DTB 1 + +/* debug mode defines */ +//#define CONFIG_DEBUG_MODE 1 +#ifdef CONFIG_DEBUG_MODE +#define CONFIG_DDR_CLK_DEBUG 636 +#define CONFIG_CPU_CLK_DEBUG 600 +#endif + +//support secure boot +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +//for SRAM size limitation just disable NAND +//as the socket board default has no NAND +//#undef CONFIG_AML_NAND + +//unify build for generate encrypted bootloader "u-boot.bin.encrypt" +#define CONFIG_AML_CRYPTO_UBOOT 1 + +//unify build for generate encrypted kernel image +//SRC : "board/amlogic/(board)/boot.img" +//DST : "fip/boot.img.encrypt" +//#define CONFIG_AML_CRYPTO_IMG 1 + +#endif //CONFIG_AML_SECURE_UBOOT + +#define CONFIG_SECURE_STORAGE 1 + +//build with uboot auto test +//#define CONFIG_AML_UBOOT_AUTO_TEST 1 + +//board customer ID +//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) + +#if defined(CONFIG_CUSTOMER_ID) + #undef CONFIG_AML_CUSTOMER_ID + #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID +#endif + +/* Choose One of Ethernet Type */ +#define CONFIG_ETHERNET_NONE +#undef ETHERNET_INTERNAL_PHY +#undef ETHERNET_EXTERNAL_PHY + +#define CONFIG_CMD_AML_MTEST 1 +#if defined(CONFIG_CMD_AML_MTEST) +#if !defined(CONFIG_SYS_MEM_TOP_HIDE) +#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE; +#endif +#if !(CONFIG_SYS_MEM_TOP_HIDE) +#error CONFIG_SYS_MEM_TOP_HIDE should not be zero; +#endif +#endif + +#define CONFIG_HIGH_TEMP_COOL 90 +#endif + diff --git a/board/amlogic/defconfigs/g12a_deadpool_v1_defconfig b/board/amlogic/defconfigs/g12a_deadpool_v1_defconfig new file mode 100644 index 0000000..ae08a87 --- a/dev/null +++ b/board/amlogic/defconfigs/g12a_deadpool_v1_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_MESON_G12A=y +CONFIG_G12A_DEADPOOL_V1=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_AML_GPIO=y diff --git a/board/amlogic/defconfigs/gxl_beast_v1_defconfig b/board/amlogic/defconfigs/gxl_beast_v1_defconfig new file mode 100644 index 0000000..9da1f44 --- a/dev/null +++ b/board/amlogic/defconfigs/gxl_beast_v1_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_MESON_GX=y +CONFIG_GXL_SEI210_V1=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_AML_GPIO=y diff --git a/board/amlogic/defconfigs/sm1_sabrina_v1_defconfig b/board/amlogic/defconfigs/sm1_sabrina_v1_defconfig new file mode 100644 index 0000000..2bcd7d9 --- a/dev/null +++ b/board/amlogic/defconfigs/sm1_sabrina_v1_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_MESON_G12A=y +CONFIG_SM1_SABRINA_V1=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_AML_GPIO=y diff --git a/board/amlogic/g12a_deadpool_v1/Kconfig b/board/amlogic/g12a_deadpool_v1/Kconfig new file mode 100644 index 0000000..37b4120 --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/Kconfig @@ -0,0 +1,22 @@ +if TARGET_MESON_G12A + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "g12a_deadpool_v1" + +config SYS_VENDOR + string + default "amlogic" + +config SYS_SOC + string + default "g12a" + +config SYS_CONFIG_NAME + default "g12a_deadpool_v1" + +endif diff --git a/board/amlogic/g12a_deadpool_v1/Makefile b/board/amlogic/g12a_deadpool_v1/Makefile new file mode 100644 index 0000000..fb7f59a --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/Makefile @@ -0,0 +1,3 @@ + +obj-y += $(BOARD).o eth_setup.o +obj-$(CONFIG_AML_LCD) += lcd.o diff --git a/board/amlogic/g12a_deadpool_v1/aml-user-key.sig b/board/amlogic/g12a_deadpool_v1/aml-user-key.sig new file mode 100644 index 0000000..2ceabc1 --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/aml-user-key.sig @@ -0,0 +1,28 @@ +yÅtÃ}| 4B²/i Ö»x¹nÜ:fÙÞžpdd'üá¹àê¯të©NöZ ¿!˜£òÄ@í $ ã×-È°°ÃÒ š‰°2³{ñ^žsWµñí ²`Dù‚#”@¸>…+äbŒqÏŽy”¡dàéÊÇ:“TŒ8Ο„
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âÈcÊ] +|¬$ô! O"QK +q'¡îçü>õìo‹éÜdÚ WÏ|û¤Œv¼K´f1$z‚îÓA×'ê<ªÊFxPTõÑ³ç ‚³ÿpüëyy̽±[’Ëkq¦A<œˆ¸'¼BNFÇ‹‡#Ï0Û{ã¹¥ˆvÝxõãøÖ( º4ªiWA¹Ç“ÍažJK¼êäÚ¶ë ðØÕÆèªù†Z‰;Å–;(YZË~ŒÀ@0†Å~< +ÑÒ“Jÿƒ—–Øy8ýûÛ·Ûkx +²KÕ\E¦=ò + diff --git a/board/amlogic/g12a_deadpool_v1/eth_setup.c b/board/amlogic/g12a_deadpool_v1/eth_setup.c new file mode 100644 index 0000000..882a37d --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/eth_setup.c @@ -0,0 +1,51 @@ + +/* + * board/amlogic/txl_skt_v1/eth_setup.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/arch/eth_setup.h> +/* + * + *setup eth device board socket + * + */ +struct eth_board_socket* eth_board_setup(char *name){ + struct eth_board_socket* new_board; + new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket)); + if (NULL == new_board) return NULL; + if (name != NULL) { + new_board->name=(char*)malloc(strlen(name)); + strncpy(new_board->name,name,strlen(name)); + }else{ + new_board->name="gxb"; + } + + new_board->eth_pinmux_setup=NULL ; + new_board->eth_clock_configure=NULL; + new_board->eth_hw_reset=NULL; + return new_board; +} +//pinmux HHI_GCLK_MPEG1[bit 3] +// diff --git a/board/amlogic/g12a_deadpool_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_deadpool_v1/firmware/scp_task/pwm_ctrl.h new file mode 100644 index 0000000..26d5d52 --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/firmware/scp_task/pwm_ctrl.h @@ -0,0 +1,61 @@ +/* +*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h +*table for Dynamic Voltage/Frequency Scaling +*/ +#ifndef __PWM_CTRL_H__ +#define __PWM_CTRL_H__ + +static int pwm_voltage_table_ee[][2] = { + { 0x1c0000, 681}, + { 0x1b0001, 691}, + { 0x1a0002, 701}, + { 0x190003, 711}, + { 0x180004, 721}, + { 0x170005, 731}, + { 0x160006, 741}, + { 0x150007, 751}, + { 0x140008, 761}, + { 0x130009, 772}, + { 0x12000a, 782}, + { 0x11000b, 792}, + { 0x10000c, 802}, + { 0x0f000d, 812}, + { 0x0e000e, 822}, + { 0x0d000f, 832}, + { 0x0c0010, 842}, + { 0x0b0011, 852}, + { 0x0a0012, 862}, + { 0x090013, 872}, + { 0x080014, 882}, + { 0x070015, 892}, + { 0x060016, 902}, + { 0x050017, 912}, + { 0x040018, 922}, + { 0x030019, 932}, + { 0x02001a, 942}, + { 0x01001b, 952}, + { 0x00001c, 962} +}; + +static int pwm_voltage_table_ee_new[][2] = { + { 0x120000, 700}, + { 0x110001, 710}, + { 0x100002, 720}, + { 0x0f0003, 730}, + { 0x0e0004, 740}, + { 0x0d0005, 750}, + { 0x0c0006, 760}, + { 0x0b0007, 770}, + { 0x0a0008, 780}, + { 0x090009, 790}, + { 0x08000a, 800}, + { 0x07000b, 810}, + { 0x06000c, 820}, + { 0x05000d, 830}, + { 0x04000e, 840}, + { 0x03000f, 850}, + { 0x020010, 860}, + { 0x010011, 870}, + { 0x000012, 880}, +}; +#endif //__PWM_CTRL_H__ diff --git a/board/amlogic/g12a_deadpool_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_deadpool_v1/firmware/scp_task/pwr_ctrl.c new file mode 100644 index 0000000..07610bb --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/firmware/scp_task/pwr_ctrl.c @@ -0,0 +1,182 @@ + +/* + * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <gpio.h> +#include "pwm_ctrl.h" +#ifdef CONFIG_CEC_WAKEUP +#include <cec_tx_reg.h> +#endif + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static void set_vddee_voltage(unsigned int target_voltage) +{ + unsigned int to, pwm_size = 0; + static int (*pwm_voltage_ee)[2]; + + /* BOOT_9 = H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */ + /*set BOOT_9 input mode*/ + writel((readl(PREG_PAD_GPIO0_EN_N) | 0x200), PREG_PAD_GPIO0_EN_N); + if (((readl(PREG_PAD_GPIO0_EN_N) & 0x200 ) == 0x200) && + ((readl(PREG_PAD_GPIO0_I) & 0x200 ) == 0x0)) { + uart_puts("use vddee new table!"); + uart_puts("\n"); + pwm_voltage_ee = pwm_voltage_table_ee_new; + pwm_size = ARRAY_SIZE(pwm_voltage_table_ee_new); + } else { + uart_puts("use vddee table!"); + uart_puts("\n"); + pwm_voltage_ee = pwm_voltage_table_ee; + pwm_size = ARRAY_SIZE(pwm_voltage_table_ee); + } + + for (to = 0; to < pwm_size; to++) { + if (pwm_voltage_ee[to][1] >= target_voltage) { + break; + } + } + + if (to >= pwm_size) { + to = pwm_size - 1; + } + + writel(*(*(pwm_voltage_ee + to)), AO_PWM_PWM_B); +} + +static void power_off_at_24M(unsigned int suspend_from) +{ + /*set gpioH_8 high to power off vcc 5v*/ + writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N); + writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C); + + /*set test_n low to power off vcck*/ + writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O); + writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N); + writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1); + + /*step down ee voltage*/ + set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE); +} + +static void power_on_at_24M(unsigned int suspend_from) +{ + /*step up ee voltage*/ + set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE); + + /*set test_n low to power on vcck*/ + writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O); + writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N); + writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1); + _udelay(100); + + /*set gpioH_8 low to power on vcc 5v*/ + writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N); + writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C); + _udelay(10000); +} + +void get_wakeup_source(void *response, unsigned int suspend_from) +{ + struct wakeup_info *p = (struct wakeup_info *)response; + struct wakeup_gpio_info *gpio; + unsigned val; + unsigned i = 0; + + p->status = RESPONSE_OK; + val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC | + BT_WAKEUP_SRC | CECB_WAKEUP_SRC); + + p->sources = val; + p->gpio_info_count = i; + +/*bt wake host*/ + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = BT_WAKEUP_SRC; + gpio->gpio_in_idx = GPIOX_18; + gpio->gpio_in_ao = 0; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_GPIO1_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; +} +extern void __switch_idle_task(void); + +static unsigned int detect_key(unsigned int suspend_from) +{ + int exit_reason = 0; + unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE; + init_remote(); +#ifdef CONFIG_CEC_WAKEUP + if (hdmi_cec_func_config & 0x1) { + remote_cec_hw_reset(); + cec_node_init(); + } +#endif + + do { + #ifdef CONFIG_CEC_WAKEUP + if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) { + irq[IRQ_AO_CECB] = 0xFFFFFFFF; + if (cec_power_on_check()) + exit_reason = CEC_WAKEUP; + } + #endif + if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) { + irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF; + if (remote_detect_key()) + exit_reason = REMOTE_WAKEUP; + } + + if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) { + irq[IRQ_VRTC] = 0xFFFFFFFF; + exit_reason = RTC_WAKEUP; + } + + if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) { + irq[IRQ_GPIO1] = 0xFFFFFFFF; + if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18)) + && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17)) + && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17))) + exit_reason = BT_WAKEUP; + } + + if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) { + irq[IRQ_ETH_PTM]= 0xFFFFFFFF; + exit_reason = ETH_PMT_WAKEUP; + } + + if (exit_reason) + break; + else + __switch_idle_task(); + } while (1); + + return exit_reason; +} + +static void pwr_op_init(struct pwr_op *pwr_op) +{ + pwr_op->power_off_at_24M = power_off_at_24M; + pwr_op->power_on_at_24M = power_on_at_24M; + pwr_op->detect_key = detect_key; + pwr_op->get_wakeup_source = get_wakeup_source; +} diff --git a/board/amlogic/g12a_deadpool_v1/firmware/timing.c b/board/amlogic/g12a_deadpool_v1/firmware/timing.c new file mode 100644 index 0000000..6caabbb --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/firmware/timing.c @@ -0,0 +1,576 @@ + +/* + * board/amlogic/txl_skt_v1/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + + + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] = { +{ + /* g12a skt (u209) ddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1200, 0, 0, 0}, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0808, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, //60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 0,//700, + .vref_dram_permil = 0,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* g12a skt (u209) ddr3 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0xffff, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0c0c, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* g12a skt (u209) lpddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1392, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0xffff,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0808, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 120, + .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, +}, +{ + /* g12a Y2 dongle */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1392, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0808, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 120, + .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28}, + .dram_rtt_nom_wr_park = {00,00}, + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* lpddr3 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR3, + .DRAMFreq = {600, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa,//0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0xffff,//1024, + .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x00c, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 30, // + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x3ff,//0x253, + .soc_ac_slew_rate = 0x3ff,//0x253, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 800,//200, + .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why? + .vref_dram_permil = 500,//875, + //.vref_reverse = 0, + .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ), + [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8}, + .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24}, + //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6}, + .dram_rtt_nom_wr_park = {00,00}, + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, +}, +}; + +pll_set_t __pll_setting = { + .cpu_clk = CONFIG_CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = CONFIG_AML_CUSTOMER_ID, +#ifdef CONFIG_DEBUG_MODE + .debug_mode = CONFIG_DEBUG_MODE, + .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG, + .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG, +#endif +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + +#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE +#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 800) + #define VCCK_VAL_REG 0x00150007 +#elif (VCCK_VAL == 810) + #define VCCK_VAL_REG 0x00140008 +#elif (VCCK_VAL == 820) + #define VCCK_VAL_REG 0x00130009 +#elif (VCCK_VAL == 830) + #define VCCK_VAL_REG 0x0012000a +#elif (VCCK_VAL == 840) + #define VCCK_VAL_REG 0x0011000b +#elif (VCCK_VAL == 850) + #define VCCK_VAL_REG 0x0010000c +#elif (VCCK_VAL == 860) + #define VCCK_VAL_REG 0x000f000d +#elif (VCCK_VAL == 870) + #define VCCK_VAL_REG 0x000e000e +#elif (VCCK_VAL == 880) + #define VCCK_VAL_REG 0x000d000f +#elif (VCCK_VAL == 890) + #define VCCK_VAL_REG 0x000c0010 +#elif (VCCK_VAL == 900) + #define VCCK_VAL_REG 0x000b0011 +#elif (VCCK_VAL == 910) + #define VCCK_VAL_REG 0x000a0012 +#elif (VCCK_VAL == 920) + #define VCCK_VAL_REG 0x00090013 +#elif (VCCK_VAL == 930) + #define VCCK_VAL_REG 0x00080014 +#elif (VCCK_VAL == 940) + #define VCCK_VAL_REG 0x00070015 +#elif (VCCK_VAL == 950) + #define VCCK_VAL_REG 0x00060016 +#elif (VCCK_VAL == 960) + #define VCCK_VAL_REG 0x00050017 +#elif (VCCK_VAL == 970) + #define VCCK_VAL_REG 0x00040018 +#elif (VCCK_VAL == 980) + #define VCCK_VAL_REG 0x00030019 +#elif (VCCK_VAL == 990) + #define VCCK_VAL_REG 0x0002001a +#elif (VCCK_VAL == 1000) + #define VCCK_VAL_REG 0x0001001b +#elif (VCCK_VAL == 1010) + #define VCCK_VAL_REG 0x0000001c +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/ +/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 800) + #define VDDEE_VAL_REG0 0x0010000c + #define VDDEE_VAL_REG1 0x0008000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG0 0x000f000d + #define VDDEE_VAL_REG1 0x0007000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG0 0x000e000e + #define VDDEE_VAL_REG1 0x0006000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG0 0x000d000f + #define VDDEE_VAL_REG1 0x0005000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG0 0x000c0010 + #define VDDEE_VAL_REG1 0x0004000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG0 0x000b0011 + #define VDDEE_VAL_REG1 0x0003000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG0 0x000a0012 + #define VDDEE_VAL_REG1 0x00020010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG0 0x00090013 + #define VDDEE_VAL_REG1 0x00010011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG0 0x00080014 + #define VDDEE_VAL_REG1 0x00000012 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2))) +#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2))) +#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2))) +#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2))) +#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2))) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + /* eg: PWM init */ + + /* PWM_AO_D */ + /* VCCK_VAL_REG: check PWM table */ + {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0}, + {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0}, + + /* set BOOT_9 input */ + //{PAD_PULL_UP_EN_REG0, 1 << 9, 1 << 9, 0, BL2_INIT_STAGE_1, 0}, + + /* PWM_AO_B */ + /* VDDEE init start */ + /* step1: CHK HW */ + {(uint64_t)P_ASSIST_POR_CONFIG, 7, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0}, + + /* step2: match PWM config */ + /* GPIO9[BIT7]=H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */ + {0x1, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0}, + {0x0, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0}, + + /* step3: config PWM */ + /* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/ + {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0}, + {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0}, + {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0}, + /* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/ + {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0}, + {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0}, + {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0}, + /* VDDEE init done */ + /* Enable 5V_EN */ + {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0}, + {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* Enable VCCK */ + {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* Init sys led*/ + {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0}, + {AO_GPIO_O, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0}, +}; diff --git a/board/amlogic/g12a_deadpool_v1/g12a_deadpool_v1.c b/board/amlogic/g12a_deadpool_v1/g12a_deadpool_v1.c new file mode 100644 index 0000000..5c7ace7 --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/g12a_deadpool_v1.c @@ -0,0 +1,838 @@ + +/* + * board/amlogic/txl_skt_v1/txl_skt_v1.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/cpu_id.h> +#include <asm/arch/secure_apb.h> +#ifdef CONFIG_SYS_I2C_AML +#include <aml_i2c.h> +#endif +#ifdef CONFIG_SYS_I2C_MESON +#include <amlogic/i2c.h> +#endif +#ifdef CONFIG_PWM_MESON +#include <pwm.h> +#include <amlogic/pwm.h> +#endif +#ifdef CONFIG_AML_VPU +#include <vpu.h> +#endif +#include <vpp.h> +#ifdef CONFIG_AML_V2_FACTORY_BURN +#include <amlogic/aml_v2_burning.h> +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/hdmi.h> +#endif +#ifdef CONFIG_AML_LCD +#include <amlogic/aml_lcd.h> +#endif +#include <asm/arch/eth_setup.h> +#include <phy.h> +#include <linux/mtd/partitions.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#ifdef CONFIG_AML_SPIFC +#include <amlogic/spifc.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; +#define P_EE_PCIE_A_CTRL (volatile uint32_t *)(0xff646000 + (0x000 << 2)) + +//new static eth setup +struct eth_board_socket* eth_board_skt; + +static void pcie_phy_shutdown(void) +{ + /*power down pcieA*/ + writel(0x20000060, P_HHI_PCIE_PLL_CNTL5); + writel(0x20090496, P_HHI_PCIE_PLL_CNTL0); + writel(0x1d, P_EE_PCIE_A_CTRL); +} + +int serial_set_pin_port(unsigned long port_base) +{ + //UART in "Always On Module" + //GPIOAO_0==tx,GPIOAO_1==rx + //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} +#ifdef ETHERNET_INTERNAL_PHY +void internalPhyConfig(struct phy_device *phydev) +{ +} + +static int dwmac_meson_cfg_pll(void) +{ + writel(0x39C0040A, P_ETH_PLL_CTL0); + writel(0x927E0000, P_ETH_PLL_CTL1); + writel(0xAC5F49E5, P_ETH_PLL_CTL2); + writel(0x00000000, P_ETH_PLL_CTL3); + udelay(200); + writel(0x19C0040A, P_ETH_PLL_CTL0); + return 0; +} + +static int dwmac_meson_cfg_analog(void) +{ + /*Analog*/ + writel(0x20200000, P_ETH_PLL_CTL5); + writel(0x0000c002, P_ETH_PLL_CTL6); + writel(0x00000023, P_ETH_PLL_CTL7); + + return 0; +} + +static int dwmac_meson_cfg_ctrl(void) +{ + /*config phyid should between a 0~0xffffffff*/ + /*please don't use 44000181, this has been used by internal phy*/ + writel(0x33000180, P_ETH_PHY_CNTL0); + + /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/ + writel(0x260, P_ETH_PHY_CNTL2); + + writel(0x74043, P_ETH_PHY_CNTL1); + writel(0x34043, P_ETH_PHY_CNTL1); + writel(0x74043, P_ETH_PHY_CNTL1); + return 0; +} + +static void setup_net_chip(void) +{ + eth_aml_reg0_t eth_reg0; + + eth_reg0.d32 = 0; + eth_reg0.b.phy_intf_sel = 4; + eth_reg0.b.rx_clk_rmii_invert = 0; + eth_reg0.b.rgmii_tx_clk_src = 0; + eth_reg0.b.rgmii_tx_clk_phase = 0; + eth_reg0.b.rgmii_tx_clk_ratio = 4; + eth_reg0.b.phy_ref_clk_enable = 1; + eth_reg0.b.clk_rmii_i_invert = 1; + eth_reg0.b.clk_en = 1; + eth_reg0.b.adj_enable = 1; + eth_reg0.b.adj_setup = 0; + eth_reg0.b.adj_delay = 9; + eth_reg0.b.adj_skew = 0; + eth_reg0.b.cali_start = 0; + eth_reg0.b.cali_rise = 0; + eth_reg0.b.cali_sel = 0; + eth_reg0.b.rgmii_rx_reuse = 0; + eth_reg0.b.eth_urgent = 0; + setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode + + dwmac_meson_cfg_pll(); + dwmac_meson_cfg_analog(); + dwmac_meson_cfg_ctrl(); + + /* eth core clock */ + setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3)); + /* eth phy clock */ + setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4)); + + /* eth phy pll, clk50m */ + setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5)); + + /* power on memory */ + clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); +} +#endif + +#ifdef ETHERNET_EXTERNAL_PHY + +static int dwmac_meson_cfg_drive_strength(void) +{ + writel(0xaaaaaaa5, P_PAD_DS_REG4A); + return 0; +} + +static void setup_net_chip_ext(void) +{ + eth_aml_reg0_t eth_reg0; + writel(0x11111111, P_PERIPHS_PIN_MUX_6); + writel(0x111111, P_PERIPHS_PIN_MUX_7); + + eth_reg0.d32 = 0; + eth_reg0.b.phy_intf_sel = 1; + eth_reg0.b.rx_clk_rmii_invert = 0; + eth_reg0.b.rgmii_tx_clk_src = 0; + eth_reg0.b.rgmii_tx_clk_phase = 1; + eth_reg0.b.rgmii_tx_clk_ratio = 4; + eth_reg0.b.phy_ref_clk_enable = 1; + eth_reg0.b.clk_rmii_i_invert = 0; + eth_reg0.b.clk_en = 1; + eth_reg0.b.adj_enable = 0; + eth_reg0.b.adj_setup = 0; + eth_reg0.b.adj_delay = 0; + eth_reg0.b.adj_skew = 0; + eth_reg0.b.cali_start = 0; + eth_reg0.b.cali_rise = 0; + eth_reg0.b.cali_sel = 0; + eth_reg0.b.rgmii_rx_reuse = 0; + eth_reg0.b.eth_urgent = 0; + setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode + + setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3); + /* power on memory */ + clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); +} +#endif +extern struct eth_board_socket* eth_board_setup(char *name); +extern int designware_initialize(ulong base_addr, u32 interface); + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_ETHERNET_NONE + return 0; +#endif + +#ifdef ETHERNET_EXTERNAL_PHY + dwmac_meson_cfg_drive_strength(); + setup_net_chip_ext(); +#endif +#ifdef ETHERNET_INTERNAL_PHY + setup_net_chip(); +#endif + udelay(1000); + designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII); + return 0; +} + +#if CONFIG_AML_SD_EMMC +#include <mmc.h> +#include <asm/arch/sd_emmc.h> +static int sd_emmc_init(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: + //todo add card detect + /* check card detect */ + clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24); + setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6); + setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6); + setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6); + break; + case SDIO_PORT_C: + //enable pull up + //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0); + break; + default: + break; + } + + return cpu_sd_emmc_init(port); +} + +extern unsigned sd_debug_board_1bit_flag; + + +static void sd_emmc_pwr_prepare(unsigned port) +{ + cpu_sd_emmc_pwr_prepare(port); +} + +static void sd_emmc_pwr_on(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + /// @todo NOT FINISH + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} +static void sd_emmc_pwr_off(unsigned port) +{ + /// @todo NOT FINISH + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} + +// #define CONFIG_TSD 1 +static void board_mmc_register(unsigned port) +{ + struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port); + if (aml_priv == NULL) + return; + + aml_priv->sd_emmc_init=sd_emmc_init; + aml_priv->sd_emmc_detect=sd_emmc_detect; + aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off; + aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on; + aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare; + aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info))); + + if (NULL == aml_priv->desc_buf) + printf(" desc_buf Dma alloc Fail!\n"); + else + printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf); + + sd_emmc_register(aml_priv); +} +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_VLSI_EMULATOR + //board_mmc_register(SDIO_PORT_A); +#else + //board_mmc_register(SDIO_PORT_B); +#endif + board_mmc_register(SDIO_PORT_B); + board_mmc_register(SDIO_PORT_C); +// board_mmc_register(SDIO_PORT_B1); + return 0; +} + +#ifdef CONFIG_SYS_I2C_AML +#if 0 +static void board_i2c_set_pinmux(void){ + /*********************************************/ + /* | I2C_Master_AO |I2C_Slave | */ + /*********************************************/ + /* | I2C_SCK | I2C_SCK_SLAVE | */ + /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */ + /*********************************************/ + /* | I2C_SDA | I2C_SDA_SLAVE | */ + /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */ + /*********************************************/ + + //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO + clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23))); + //enable I2C MASTER AO pins + setbits_le32(P_AO_RTI_PIN_MUX_REG, + (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT)); + + udelay(10); +}; +#endif +struct aml_i2c_platform g_aml_i2c_plat = { + .wait_count = 1000000, + .wait_ack_interval = 5, + .wait_read_interval = 5, + .wait_xfer_interval = 5, + .master_no = AML_I2C_MASTER_AO, + .use_pio = 0, + .master_i2c_speed = AML_I2C_SPPED_400K, + .master_ao_pinmux = { + .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG, + .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT, + .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG, + .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT, + } +}; +#if 0 +static void board_i2c_init(void) +{ + //set I2C pinmux with PCB board layout + board_i2c_set_pinmux(); + + //Amlogic I2C controller initialized + //note: it must be call before any I2C operation + aml_i2c_init(); + + udelay(10); +} +#endif +#endif +#endif + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void){ + /*add board early init function here*/ + return 0; +} +#endif + +#ifdef CONFIG_USB_XHCI_AMLOGIC_V2 +#include <asm/arch/usb-v2.h> +#include <asm/arch/gpio.h> +#define CONFIG_GXL_USB_U2_PORT_NUM 2 + +#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2 +#define CONFIG_GXL_USB_U3_PORT_NUM 1 +#else +#define CONFIG_GXL_USB_U3_PORT_NUM 0 +#endif + +static void gpio_set_vbus_power(char is_power_on) +{ + int ret; + + ret = gpio_request(CONFIG_USB_GPIO_PWR, + CONFIG_USB_GPIO_PWR_NAME); + if (ret && ret != -EBUSY) { + printf("gpio: requesting pin %u failed\n", + CONFIG_USB_GPIO_PWR); + return; + } + + if (is_power_on) { + gpio_direction_output(CONFIG_USB_GPIO_PWR, 1); + } else { + gpio_direction_output(CONFIG_USB_GPIO_PWR, 0); + } +} + +struct amlogic_usb_config g_usb_config_GXL_skt={ + CONFIG_GXL_XHCI_BASE, + USB_ID_MODE_HARDWARE, + gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power + CONFIG_GXL_USB_PHY2_BASE, + CONFIG_GXL_USB_PHY3_BASE, + CONFIG_GXL_USB_U2_PORT_NUM, + CONFIG_GXL_USB_U3_PORT_NUM, + .usb_phy2_pll_base_addr = { + CONFIG_USB_PHY_20, + CONFIG_USB_PHY_21, + } +}; + +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#ifdef CONFIG_AML_HDMITX20 +static void hdmi_tx_set_hdmi_5v(void) +{ +} +#endif + +/* + * mtd nand partition table, only care the size! + * offset will be calculated by nand driver. + */ +#ifdef CONFIG_AML_MTD +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER + /* MUST NOT CHANGE this part unless u know what you are doing! + * inherent parition for descrete bootloader to store fip + * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM + * name must be same with TPL_PART_NAME + */ + { + .name = "tpl", + .offset = 0, + .size = 0, + }, +#endif + { + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 15*SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 280*SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif /* CONFIG_AML_MTD */ + +#ifdef CONFIG_AML_SPIFC +/* + * BOOT_3: NOR_HOLDn:reg0[15:12]=3 + * BOOT_4: NOR_D:reg0[19:16]=3 + * BOOT_5: NOR_Q:reg0[23:20]=3 + * BOOT_6: NOR_C:reg0[27:24]=3 + * BOOT_7: NOR_WPn:reg0[31:28]=3 + * BOOT_14: NOR_CS:reg1[27:24]=3 + */ +#define SPIFC_NUM_CS 1 +static int spifc_cs_gpios[SPIFC_NUM_CS] = {54}; + +static int spifc_pinctrl_enable(void *pinctrl, bool enable) +{ + unsigned int val; + + val = readl(P_PERIPHS_PIN_MUX_0); + val &= ~(0xfffff << 12); + if (enable) + val |= 0x33333 << 12; + writel(val, P_PERIPHS_PIN_MUX_0); + + val = readl(P_PERIPHS_PIN_MUX_1); + val &= ~(0xf << 24); + writel(val, P_PERIPHS_PIN_MUX_1); + return 0; +} + +static const struct spifc_platdata spifc_platdata = { + .reg = 0xffd14000, + .mem_map = 0xf6000000, + .pinctrl_enable = spifc_pinctrl_enable, + .num_chipselect = SPIFC_NUM_CS, + .cs_gpios = spifc_cs_gpios, +}; + +U_BOOT_DEVICE(spifc) = { + .name = "spifc", + .platdata = &spifc_platdata, +}; +#endif /* CONFIG_AML_SPIFC */ + +extern void aml_pwm_cal_init(int mode); + +#ifdef CONFIG_SYS_I2C_MESON +static const struct meson_i2c_platdata i2c_data[] = { + { 0, 0xffd1f000, 166666666, 3, 15, 100000 }, + { 1, 0xffd1e000, 166666666, 3, 15, 100000 }, + { 2, 0xffd1d000, 166666666, 3, 15, 100000 }, + { 3, 0xffd1c000, 166666666, 3, 15, 100000 }, + { 4, 0xff805000, 166666666, 3, 15, 100000 }, +}; + +U_BOOT_DEVICES(meson_i2cs) = { + { "i2c_meson", &i2c_data[0] }, + { "i2c_meson", &i2c_data[1] }, + { "i2c_meson", &i2c_data[2] }, + { "i2c_meson", &i2c_data[3] }, + { "i2c_meson", &i2c_data[4] }, +}; + +/* + *GPIOAO_10//I2C_SDA_AO + *GPIOAO_11//I2C_SCK_AO + *pinmux configuration seperated with i2c controller configuration + * config it when you use + */ +void set_i2c_ao_pinmux(void) +{ + return; +} +#endif /*end CONFIG_SYS_I2C_MESON*/ + +#ifdef CONFIG_PWM_MESON +static const struct meson_pwm_platdata pwm_data[] = { + { PWM_AB, 0xffd1b000, IS_DOUBLE_CHANNEL, IS_BLINK }, + { PWM_CD, 0xffd1a000, IS_DOUBLE_CHANNEL, IS_BLINK }, + { PWM_EF, 0xffd19000, IS_DOUBLE_CHANNEL, IS_BLINK }, + { PWMAO_AB, 0xff807000, IS_DOUBLE_CHANNEL, IS_BLINK }, + { PWMAO_CD, 0xff802000, IS_DOUBLE_CHANNEL, IS_BLINK }, +}; + +U_BOOT_DEVICES(meson_pwm) = { + { "amlogic,general-pwm", &pwm_data[0] }, + { "amlogic,general-pwm", &pwm_data[1] }, + { "amlogic,general-pwm", &pwm_data[2] }, + { "amlogic,general-pwm", &pwm_data[3] }, + { "amlogic,general-pwm", &pwm_data[4] }, +}; +#endif /*end CONFIG_PWM_MESON*/ + +extern void aml_pwm_cal_init(int mode); + +int board_init(void) +{ + //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init + //As NOT NEED other board init If USB BOOT MODE +#ifdef CONFIG_AML_V2_FACTORY_BURN + if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) { + aml_try_factory_usb_burning(0, gd->bd); + } +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN +#ifdef CONFIG_USB_XHCI_AMLOGIC_V2 + board_usb_pll_disable(&g_usb_config_GXL_skt); + board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST); +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#if 0 + aml_pwm_cal_init(0); +#endif// +#ifdef CONFIG_AML_NAND + extern int amlnf_init(unsigned char flag); + amlnf_init(0); +#endif + +#ifdef CONFIG_SYS_I2C_MESON + set_i2c_ao_pinmux(); +#endif + + return 0; +} + +/* set dts props */ +void aml_config_dtb(void) +{ + cpu_id_t cpuid = get_cpu_id(); + if (MESON_CPU_MAJOR_ID_G12A != cpuid.family_id) + return; + + run_command("fdt address $dtb_mem_addr", 0); + printf("%s %d\n", __func__, __LINE__); + if (cpuid.chip_rev == 0xA) { + printf("%s %d\n", __func__, __LINE__); + run_command("fdt set /emmc/emmc co_phase <0x2>", 0); + run_command("fdt rm /emmc/emmc caps2", 0); + run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0); + + run_command("fdt set /sdio status okay", 0); + run_command("fdt set /sd1 status okay", 0); + run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0); + run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0); + /* debug */ + run_command("fdt print /emmc/emmc co_phase", 0); + run_command("fdt print /emmc/emmc caps2", 0); + run_command("fdt print /emmc/emmc f_max", 0); + + run_command("fdt print /sdio status", 0); + run_command("fdt print /sd1 status ", 0); + run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0); + } else { + + printf("%s %d\n", __func__, __LINE__); + run_command("fdt set /emmc/emmc co_phase <0x3>", 0); + run_command("fdt set /sdio status disabled", 0); + run_command("fdt set /sd2 status okay", 0); + /* debug */ + run_command("fdt print /emmc/emmc co_phase", 0); + run_command("fdt print /emmc/emmc caps2", 0); + run_command("fdt print /emmc/emmc f_max", 0); + run_command("fdt print /sdio status", 0); + run_command("fdt print /sd2 status", 0); + } + + return; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + //update env before anyone using it + run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\ + "if test ${reboot_mode} = factory_reset; then "\ + "defenv_reserv;save; fi;", 0); + run_command("if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + /*add board late init function here*/ +#ifndef DTB_BIND_KERNEL + int ret; + ret = run_command("store dtb read $dtb_mem_addr", 1); + if (ret) { + printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__); +#ifdef CONFIG_DTB_MEM_ADDR + char cmd[64]; + printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR); + sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR); + ret = run_command(cmd, 1); + if (ret) { + printf("%s(): %s fail\n", __func__, cmd); + } +#endif + } +#elif defined(CONFIG_DTB_MEM_ADDR) + { + char cmd[128]; + int ret; + if (!getenv("dtb_mem_addr")) { + sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR); + run_command(cmd, 0); + } + sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}"); + ret = run_command(cmd, 0); + if (ret) { + printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret); + } + } +#endif// #ifndef DTB_BIND_KERNEL + + /* load unifykey */ + run_command("keyunify init 0x1234", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif + vpp_init(); +#ifdef CONFIG_AML_HDMITX20 + hdmi_tx_set_hdmi_5v(); + hdmi_tx_init(); +#endif +#ifdef CONFIG_AML_CVBS + run_command("cvbs init", 0); +#endif +#ifdef CONFIG_AML_LCD + lcd_probe(); +#endif + +#ifdef CONFIG_AML_V2_FACTORY_BURN + if (0x1b8ec003 == readl(P_PREG_STICKY_REG2)) + aml_try_factory_usb_burning(1, gd->bd); + aml_try_factory_sdcard_burning(0, gd->bd); +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN + + /* close pcie phy */ + pcie_phy_shutdown(); + + if (MESON_CPU_MAJOR_ID_SM1 == get_cpu_id().family_id) { + setenv("board_defined_bootup", "bootup_Y3"); + } + /**/ + aml_config_dtb(); + return 0; +} +#endif + +#ifdef CONFIG_AML_TINY_USBTOOL +int usb_get_update_result(void) +{ + unsigned long upgrade_step; + upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16); + printf("upgrade_step = %d\n", (int)upgrade_step); + if (upgrade_step == 1) + { + run_command("defenv", 1); + run_command("setenv upgrade_step 2", 1); + run_command("saveenv", 1); + return 0; + } + else + { + return -1; + } +} +#endif + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4); +#endif +} + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + /* + * read board hw id + * set and select the dts according the board hw id. + * + * hwid = 1 p321 v1 + * hwid = 2 p321 v2 + */ + unsigned int hwid = 1; + char loc_name[64] = {0}; + + /* read hwid */ + hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF; + + printf("checkhw: hwid = %d\n", hwid); + + + switch (hwid) { + case 1: + strcpy(loc_name, "txl_p321_v1\0"); + break; + case 2: + strcpy(loc_name, "txl_p321_v2\0"); + break; + default: + strcpy(loc_name, "txl_p321_v1"); + break; + } + strcpy(name, loc_name); + setenv("aml_dt", loc_name); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "aml_dt", + "firstboot", + "lock", + "upgrade_step", + + NULL//Keep NULL be last to tell END +}; diff --git a/board/amlogic/g12a_deadpool_v1/lcd.c b/board/amlogic/g12a_deadpool_v1/lcd.c new file mode 100644 index 0000000..2f352f6 --- a/dev/null +++ b/board/amlogic/g12a_deadpool_v1/lcd.c @@ -0,0 +1,475 @@ +/* + * AMLOGIC LCD panel driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the named License, + * or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <amlogic/aml_lcd.h> +#include <asm/arch/gpio.h> + +static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "GPIOZ_9", /* panel rst */ + "GPIOZ_8", /* panel power */ + "invalid", /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step[] = { + {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = { + {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */ +#if 1 + {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */ +#endif + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = { + {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */ + {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "GPIOH_4", /* BL_EN */ + "GPIOH_5", /* BL_PWM */ + "invalid", /* ending flag */ +}; + +struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = { + {/* B080XAN01*/ + "lcd_0",LCD_MIPI,8, + /* basic timing */ + 768,1024,948,1140,64,56,0,50,30,0, + /* clk_attr */ + 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* TV070WSM*/ + "lcd_1",LCD_MIPI,8, + /* basic timing */ + 600,1024,700,1053,24,36,0,2,8,0, + /* clk_attr */ + 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,360,0,1,0,2,0,0,Rsv_val,1, + /* power step */ + lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* P070ACB*/ + "lcd_2",LCD_MIPI,8, + /* basic timing */ + 600,1024,680,1194,24,36,0,10,80,0, + /* clk_attr */ + 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,400,0,1,0,2,0,0,Rsv_val,2, + /* power step */ + lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {.panel_type = "invalid"}, +}; + +static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = { + { + .name = "lcd_pin", + .pinmux_set = {{LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{LCD_PINMUX_END, 0x0}}, + }, + { + .name = "invalid", + }, +}; + +static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = { + { + .name = "bl_pwm_on_pin", //GPIOH_5 + .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}}, + }, + { + .name = "invalid", + }, +}; + +static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100 + 0x05, 1, 0x11, + 0xfd, 1, 20, + 0x05, 1, 0x29, + 0xfd, 1, 20, + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50 + 0x05, 1, 0x28, + 0xfd, 1, 10, + 0x05, 1, 0x10, + 0xfd, 1, 10, + 0xff, 0, //ending +}; + +static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100 + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50 + 0xff, 0, //ending +}; + +static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100 + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50 + 0xff, 0, //ending +}; + +static struct dsi_config_s lcd_mipi_config = { + .lane_num = 4, + .bit_rate_max = 550, /* MHz */ + .factor_numerator = 0, + .factor_denominator = 100, + .operation_mode_init = 1, /* 0=video mode, 1=command mode */ + .operation_mode_display = 0, /* 0=video mode, 1=command mode */ + .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */ + .clk_always_hs = 1, /* 0=disable, 1=enable */ + .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */ + + .dsi_init_on = &mipi_init_on_table[0], + .dsi_init_off = &mipi_init_off_table[0], + .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */ + .check_en = 0, + .check_state = 0, +}; + +static struct lcd_power_ctrl_s lcd_power_ctrl = { + .power_on_step = { + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 10, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 20, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 20, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_SIGNAL, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 0, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, + .power_off_step = { + { + .type = LCD_POWER_TYPE_SIGNAL, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 100, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 100, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, +}; + +struct lcd_config_s lcd_config_dft = { + .lcd_mode = LCD_MODE_TABLET, + .lcd_key_valid = 0, + .lcd_clk_path = 0, + .lcd_basic = { + .model_name = "default", + .lcd_type = LCD_TYPE_MAX, + .lcd_bits = 8, + .h_active = 768, + .v_active = 1024, + .h_period = 948, + .v_period = 1140, + + .screen_width = 119, + .screen_height = 159, + }, + + .lcd_timing = { + .clk_auto = 1, + .lcd_clk = 64843200, + .ss_level = 0, + .fr_adjust_type = 0, + + .hsync_width = 64, + .hsync_bp = 56, + .hsync_pol = 0, + .vsync_width = 50, + .vsync_bp = 30, + .vsync_pol = 0, + }, + + .lcd_control = { + .mipi_config= &lcd_mipi_config, + }, + .lcd_power = &lcd_power_ctrl, + + .pinctrl_ver = 2, + .lcd_pinmux = lcd_pinmux_ctrl, + .pinmux_set = {{LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{LCD_PINMUX_END, 0x0}}, +}; + +#ifdef CONFIG_AML_LCD_EXTERN +static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = { + "invalid", /* ending flag */ +}; + +static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = { + 0xff, 0, //ending flag +}; + +static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = { + 0xff, 0, //ending flag +}; + +struct lcd_extern_common_s ext_common_dft = { + .lcd_ext_key_valid = 0, + .lcd_ext_num = 3, + .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */ + .pinmux_set = {{LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{LCD_PINMUX_END, 0x0}}, +}; + +struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = { + { + .index = 0, + .name = "ext_default", + .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 0, /* 0=disable, 1=enable */ + .i2c_addr = 0x1c, /* 7bit i2c address */ + .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table, + .table_init_on_cnt = sizeof(ext_init_on_table), + .table_init_off = ext_init_off_table, + .table_init_off_cnt = sizeof(ext_init_off_table), + }, + { + .index = 1, + .name = "mipi_TV070WSM", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table, + .table_init_on_cnt = sizeof(ext_init_on_table), + .table_init_off = ext_init_off_table, + .table_init_off_cnt = sizeof(ext_init_off_table), + }, + { + .index = 2, + .name = "mipi_P070ACB", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table, + .table_init_on_cnt = sizeof(ext_init_on_table), + .table_init_off = ext_init_off_table, + .table_init_off_cnt = sizeof(ext_init_off_table), + }, + { + .index = LCD_EXTERN_INDEX_INVALID, + }, +}; +#endif + +struct bl_config_s bl_config_dft = { + .name = "default", + .bl_key_valid = 0, + + .level_default = 100, + .level_min = 10, + .level_max = 255, + .level_mid = 128, + .level_mid_mapping = 128, + .level = 0, + + .method = BL_CTRL_MAX, + .power_on_delay = 200, + .power_off_delay = 200, + + .en_gpio = 0xff, + .en_gpio_on = 1, + .en_gpio_off = 0, + + .bl_pwm = NULL, + .bl_pwm_combo0 = NULL, + .bl_pwm_combo1 = NULL, + .pwm_on_delay = 10, + .pwm_off_delay = 10, + + .bl_extern_index = 0xff, + + .pinctrl_ver = 2, + .bl_pinmux = bl_pinmux_ctrl, + .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}}, +}; + +#ifdef CONFIG_AML_BL_EXTERN +static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX]; +static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX]; +struct bl_extern_config_s bl_extern_config_dtf = { + .index = BL_EXTERN_INDEX_INVALID, + .name = "none", + .type = BL_EXTERN_MAX, + .i2c_addr = 0xff, + .i2c_bus = BL_EXTERN_I2C_BUS_MAX, + .dim_min = 10, + .dim_max = 255, + + .init_loaded = 0, + .cmd_size = 0xff, + .init_on = bl_ext_init_on, + .init_off = bl_ext_init_off, + .init_on_cnt = sizeof(bl_ext_init_on), + .init_off_cnt = sizeof(bl_ext_init_off), +}; +#endif + +void lcd_config_bsp_init(void) +{ + int i, j; + char *str; + struct ext_lcd_config_s *ext_lcd = NULL; + + str = getenv("panel_type"); + if (str) { + for (i = 0 ; i < LCD_NUM_MAX ; i++) { + ext_lcd = &ext_lcd_config[i]; + if (strcmp(ext_lcd->panel_type, str) == 0) { + switch (i) { + case 1: + lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM; + lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM; + break; + case 2: + lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB; + lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB; + break; + case 0: + default: + lcd_mipi_config.dsi_init_on = mipi_init_on_table; + lcd_mipi_config.dsi_init_off = mipi_init_off_table; + break; + } + break; + } + } + } + + for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_cpu_gpio[i], "invalid") == 0) + break; + strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]); + } + for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++) + strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid"); + for (i = 0; i < BL_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_bl_gpio[i], "invalid") == 0) + break; + strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]); + } + for (j = i; j < BL_GPIO_NUM_MAX; j++) + strcpy(bl_config_dft.gpio_name[j], "invalid"); + +#ifdef CONFIG_AML_LCD_EXTERN + for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) { + if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID) + break; + } + ext_common_dft.lcd_ext_num = i; + + for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_ext_gpio[i], "invalid") == 0) + break; + strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]); + } + for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++) + strcpy(ext_common_dft.gpio_name[j], "invalid"); + +#endif +} diff --git a/board/amlogic/gxl_beast_v1/Kconfig b/board/amlogic/gxl_beast_v1/Kconfig new file mode 100644 index 0000000..fc87d9e --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/Kconfig @@ -0,0 +1,22 @@ +if TARGET_MESON_GX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "gxl_beast_v1" + +config SYS_VENDOR + string + default "amlogic" + +config SYS_SOC + string + default "gxl" + +config SYS_CONFIG_NAME + default "beast" + +endif diff --git a/board/amlogic/gxl_beast_v1/Makefile b/board/amlogic/gxl_beast_v1/Makefile new file mode 100644 index 0000000..35a1991 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/Makefile @@ -0,0 +1,2 @@ + +obj-y += $(BOARD).o eth_setup.o diff --git a/board/amlogic/gxl_beast_v1/aml-user-key.sig b/board/amlogic/gxl_beast_v1/aml-user-key.sig new file mode 100644 index 0000000..b6c5722 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/aml-user-key.sig @@ -0,0 +1,29 @@ +yÅtÃ}| 4B²/i Ö»x¹nÜ:fÙÞžpdd'üá¹àê¯të©NöZ ¿!˜£òÄ@í $ ã×-È°°ÃÒ š‰°2³{ñ^žsWµñí ²`Dù‚#”@¸>…+äbŒqÏŽy”¡dàéÊÇ:“TŒ8Ο„
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âÈcÊ] + +úB†el—âLv¯–Ýö¯Û4dHlÁøƒgÂrü*xg. +0Ù5‘ û €+O÷X´b9RrÙ”5–ãŒÅF<ÅY¸sËŸ€ö׻ϗ¼Vg ©aHD~—J¦½®‹$hD_’FIÒœ +ÑÒ“Jÿƒ—–Øy8ýûÛ·Ûkx +²KÕ\E¦=ò + diff --git a/board/amlogic/gxl_beast_v1/eth_setup.c b/board/amlogic/gxl_beast_v1/eth_setup.c new file mode 100644 index 0000000..33b5db1 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/eth_setup.c @@ -0,0 +1,50 @@ + +/* + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/arch/eth_setup.h> +/* + * + *setup eth device board socket + * + */ +struct eth_board_socket* eth_board_setup(char *name){ + struct eth_board_socket* new_board; + new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket)); + if (NULL == new_board) return NULL; + if (name != NULL) { + new_board->name=(char*)malloc(strlen(name)); + strncpy(new_board->name,name,strlen(name)); + }else{ + new_board->name="gxb"; + } + + new_board->eth_pinmux_setup=NULL ; + new_board->eth_clock_configure=NULL; + new_board->eth_hw_reset=NULL; + return new_board; +} +//pinmux HHI_GCLK_MPEG1[bit 3] +// diff --git a/board/amlogic/gxl_beast_v1/firmware/board_init.c b/board/amlogic/gxl_beast_v1/firmware/board_init.c new file mode 100644 index 0000000..22c36d1 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/firmware/board_init.c @@ -0,0 +1,28 @@ + +/* + * board/amlogic/gxb_p201_v1/firmware/board_init.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include "power.c" + +/* bl2 customer code */ +void board_init(void) +{ + power_init(0); +}
\ No newline at end of file diff --git a/board/amlogic/gxl_beast_v1/firmware/power.c b/board/amlogic/gxl_beast_v1/firmware/power.c new file mode 100644 index 0000000..fce6e3c --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/firmware/power.c @@ -0,0 +1,185 @@ + +/* + * board/amlogic/gxb_p200_v1/firmware/power.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include "config.h" +#include <serial.h> +//#include <stdio.h> + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static int pwm_voltage_table[][2] = { + { 0x1c0000, 860}, + { 0x1b0001, 870}, + { 0x1a0002, 880}, + { 0x190003, 890}, + { 0x180004, 900}, + { 0x170005, 910}, + { 0x160006, 920}, + { 0x150007, 930}, + { 0x140008, 940}, + { 0x130009, 950}, + { 0x12000a, 960}, + { 0x11000b, 970}, + { 0x10000c, 980}, + { 0x0f000d, 990}, + { 0x0e000e, 1000}, + { 0x0d000f, 1010}, + { 0x0c0010, 1020}, + { 0x0b0011, 1030}, + { 0x0a0012, 1040}, + { 0x090013, 1050}, + { 0x080014, 1060}, + { 0x070015, 1070}, + { 0x060016, 1080}, + { 0x050017, 1090}, + { 0x040018, 1100}, + { 0x030019, 1110}, + { 0x02001a, 1120}, + { 0x01001b, 1130}, + { 0x00001c, 1140} +}; +#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2)))) +#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2)))) +#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2)))) +#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2)))) + +#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2)))) +#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2)))) +#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2)))) +#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2)))) + +#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2)))) + +enum pwm_id { + pwm_a = 0, + pwm_b, + pwm_c, + pwm_d, + pwm_e, + pwm_f, +}; + +unsigned int _get_time(void) +{ + return P_EE_TIMER_E; +} + +void _udelay_(unsigned int us) +{ + unsigned int t0 = _get_time(); + + while (_get_time() - t0 <= us) + ; +} + +void pwm_init(int id) +{ + unsigned int reg; + + /* + * TODO: support more pwm controllers, right now only support + * PWM_B, PWM_D + */ + + switch (id) { + case pwm_b: + reg = P_PWM_MISC_REG_AB; + reg &= ~(0x7f << 16); + reg |= ((1 << 23) | (1 << 1)); + P_PWM_MISC_REG_AB = reg; + /* + * default set to max voltage + */ + P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0]; + reg = P_PIN_MUX_REG1; + reg &= ~(1 << 10); + P_PIN_MUX_REG1 = reg; + + reg = P_PIN_MUX_REG2; + reg &= ~(1 << 5); + reg |= (1 << 11); // enable PWM_B + P_PIN_MUX_REG2 = reg; + break; + + case pwm_d: + reg = P_PWM_MISC_REG_CD; + reg &= ~(0x7f << 16); + reg |= ((1 << 23) | (1 << 1)); + P_PWM_MISC_REG_CD = reg; + /* + * default set to max voltage + */ + P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0]; + reg = P_PIN_MUX_REG1; + reg &= ~(1 << 9); + reg &= ~(1 << 11); + P_PIN_MUX_REG1 = reg; + + reg = P_PIN_MUX_REG2; + reg |= (1 << 12); // enable PWM_D + P_PIN_MUX_REG2 = reg; + break; + default: + break; + } + + _udelay_(200); +} + +void pwm_set_voltage(unsigned int id, unsigned int voltage) +{ + int to; + + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= voltage) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) { + to = ARRAY_SIZE(pwm_voltage_table) - 1; + } + switch (id) { + case pwm_b: + P_PWM_PWM_B = pwm_voltage_table[to][0]; + break; + + case pwm_d: + P_PWM_PWM_D = pwm_voltage_table[to][0]; + break; + default: + break; + } + _udelay_(200); +} + +void power_init(int mode) +{ + pwm_init(pwm_b); + pwm_init(pwm_d); + serial_puts("set vcck to "); + serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE); + serial_puts(" mv\n"); + pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE); + serial_puts("set vddee to "); + serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE); + serial_puts(" mv\n"); + pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE); +} diff --git a/board/amlogic/gxl_beast_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_beast_v1/firmware/scp_task/dvfs_board.c new file mode 100644 index 0000000..0dd6ab6 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/firmware/scp_task/dvfs_board.c @@ -0,0 +1,171 @@ + +int pwm_voltage_table[][2] = { + { 0x1c0000, 860}, + { 0x1b0001, 870}, + { 0x1a0002, 880}, + { 0x190003, 890}, + { 0x180004, 900}, + { 0x170005, 910}, + { 0x160006, 920}, + { 0x150007, 930}, + { 0x140008, 940}, + { 0x130009, 950}, + { 0x12000a, 960}, + { 0x11000b, 970}, + { 0x10000c, 980}, + { 0x0f000d, 990}, + { 0x0e000e, 1000}, + { 0x0d000f, 1010}, + { 0x0c0010, 1020}, + { 0x0b0011, 1030}, + { 0x0a0012, 1040}, + { 0x090013, 1050}, + { 0x080014, 1060}, + { 0x070015, 1070}, + { 0x060016, 1080}, + { 0x050017, 1090}, + { 0x040018, 1100}, + { 0x030019, 1110}, + { 0x02001a, 1120}, + { 0x01001b, 1130}, + { 0x00001c, 1140} +}; + +struct scpi_opp_entry cpu_dvfs_tbl[] = { + DVFS( 100000000, 860), + DVFS( 250000000, 860), + DVFS( 500000000, 860), + DVFS( 667000000, 900), + DVFS(1000000000, 940), + DVFS(1200000000, 1020), + DVFS(1512000000, 1110+30), +}; + + + +#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2)))) +#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2)))) + +#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2)))) +#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2)))) + + +enum pwm_id { + pwm_a = 0, + pwm_b, + pwm_c, + pwm_d, + pwm_e, + pwm_f, +}; + + +void pwm_init(int id) +{ + /* + * TODO: support more pwm controllers, right now only support PWM_B + */ + unsigned int reg; + reg = P_PWM_MISC_REG_CD; + reg &= ~(0x7f << 16); + reg |= ((1 << 23) | (1 << 1)); + P_PWM_MISC_REG_CD = reg; + /* + * default set to max voltage + */ + P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0]; + reg = P_PIN_MUX_REG1; + reg &= ~(1 << 9); + reg &= ~(1 << 11); + P_PIN_MUX_REG1 = reg; + + reg = P_PIN_MUX_REG2; + reg |= (1 << 12); // enable PWM_D + P_PIN_MUX_REG2 = reg; + + + _udelay(200); +} + +int dvfs_get_voltage(void) +{ + int i = 0; + unsigned int reg_val; + + reg_val = P_PWM_PWM_D; + for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) { + if (pwm_voltage_table[i][0] == reg_val) { + return i; + } + } + if (i >= ARRAY_SIZE(pwm_voltage_table)) { + return -1; + } + return -1; +} + +void set_dvfs(unsigned int domain, unsigned int index) +{ + int cur, to; + static int init_flag = 0; + + if (!init_flag) { + pwm_init(pwm_b); + init_flag = 1; + } + cur = dvfs_get_voltage(); + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) { + to = ARRAY_SIZE(pwm_voltage_table) - 1; + } + if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) { + P_PWM_PWM_D = pwm_voltage_table[to][0]; + _udelay(200); + return ; + } + while (cur != to) { + /* + * if target step is far away from current step, don't change + * voltage by one-step-done. You should change voltage step by + * step to make sure voltage output is stable + */ + if (cur < to) { + if (cur < to - 3) { + cur += 3; + } else { + cur = to; + } + } else { + if (cur > to + 3) { + cur -= 3; + } else { + cur = to; + } + } + P_PWM_PWM_D = pwm_voltage_table[cur][0]; + _udelay(100); + } + _udelay(200); +} +void get_dvfs_info_board(unsigned int domain, + unsigned char *info_out, unsigned int *size_out) +{ + unsigned int cnt; + cnt = ARRAY_SIZE(cpu_dvfs_tbl); + + buf_opp.latency = 200; + buf_opp.count = cnt; + memset(&buf_opp.opp[0], 0, + MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry)); + + memcpy(&buf_opp.opp[0], cpu_dvfs_tbl , + cnt * sizeof(struct scpi_opp_entry)); + + memcpy(info_out, &buf_opp, sizeof(struct scpi_opp)); + *size_out = sizeof(struct scpi_opp); + return; +} diff --git a/board/amlogic/gxl_beast_v1/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_beast_v1/firmware/scp_task/dvfs_board.h new file mode 100644 index 0000000..ceede58 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/firmware/scp_task/dvfs_board.h @@ -0,0 +1,3 @@ +#ifndef __DVFS_BOARD_H__ +extern int pwm_voltage_table[31][2]; +#endif diff --git a/board/amlogic/gxl_beast_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_beast_v1/firmware/scp_task/pwr_ctrl.c new file mode 100644 index 0000000..6e75686 --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/firmware/scp_task/pwr_ctrl.c @@ -0,0 +1,287 @@ +/*p200/201 GPIOAO_2 powr on :0, power_off :1*/ + +#define __SUSPEND_FIRMWARE__ +#include <config.h> +#undef __SUSPEND_FIRMWARE__ + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#ifdef CONFIG_CEC_WAKEUP +#include <cec_tx_reg.h> +#endif +#include <gpio-gxbb.h> +#include "dvfs_board.h" + +#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2)))) +#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2)))) + +#define P_PWM_MISC_REG_AB \ + (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2)))) +#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2)))) +#define P_PWM_MISC_REG_CD \ + (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2)))) +#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2)))) + +#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2)))) +#define ON 1 +#define OFF 0 +enum pwm_id { + pwm_a = 0, + pwm_b, + pwm_c, + pwm_d, + pwm_e, + pwm_f, +}; +static struct pwr_op *g_pwr_op; +void pwm_set_voltage(unsigned int id, unsigned int voltage) +{ + int to; + + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= voltage) + break; + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) + to = ARRAY_SIZE(pwm_voltage_table) - 1; + + switch (id) { + case pwm_b: + uart_puts("set vddee to 0x"); + uart_put_hex(pwm_voltage_table[to][1], 16); + uart_puts("mv\n"); + P_PWM_PWM_B = pwm_voltage_table[to][0]; + break; + + case pwm_d: + uart_puts("set vcck to 0x"); + uart_put_hex(pwm_voltage_table[to][1], 16); + uart_puts("mv\n"); + P_PWM_PWM_D = pwm_voltage_table[to][0]; + break; + default: + break; + } + _udelay(200); +} +/*GPIOH_3*/ +static void hdmi_5v_ctrl(unsigned int ctrl) +{ + if (ctrl == ON) { + /* VCC5V ON GPIOH_3 output mode*/ + aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0); + } else { + /* VCC5V OFF GPIOH_3 input mode*/ + aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23); + } +} +/*GPIODV_25*/ +static void vcck_ctrl(unsigned int ctrl) +{ + if (ctrl == ON) { + aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0); + aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25); + /* after power on vcck, should init vcck*/ + _udelay(5000); + pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE); + } else { + aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0); + aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0); + } +} + +static void power_off_at_clk81(void) +{ + hdmi_5v_ctrl(OFF); + vcck_ctrl(OFF); + pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE); + /* reduce power */ +} +static void power_on_at_clk81(void) +{ + pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE); + vcck_ctrl(ON); + hdmi_5v_ctrl(ON); +} + +static void power_off_at_24M(void) +{ + /* LED GPIODV_24*/ + aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0); + aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0); +} + +static void power_on_at_24M(void) +{ + if (g_pwr_op->exit_reason != 4) { + /* bluetooth wakeup */ + aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0); + aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24); + } +} + +static void power_off_at_32k(void) +{ +} + +static void power_on_at_32k(void) +{ +} + +void get_wakeup_source(void *response, unsigned int suspend_from) +{ + struct wakeup_info *p = (struct wakeup_info *)response; + unsigned val; + struct wakeup_gpio_info *gpio; + unsigned i = 0; + + p->status = RESPONSE_OK; + val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC | + ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC); +#ifdef CONFIG_CEC_WAKEUP + if (suspend_from != SYS_POWEROFF) + val |= CEC_WAKEUP_SRC; +#endif + p->sources = val; + + /* Power Key: AO_GPIO[3]*/ + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = POWER_KEY_WAKEUP_SRC; + gpio->gpio_in_idx = GPIOAO_2; + gpio->gpio_in_ao = 1; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_AO_GPIO0_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; + + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = BT_WAKEUP_SRC; + gpio->gpio_in_idx = GPIOX_18; + gpio->gpio_in_ao = 0; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_GPIO0_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; +} +void wakeup_timer_setup(void) +{ + /* 1ms resolution*/ + unsigned value; + value = readl(P_ISA_TIMER_MUX); + value |= ((0x3<<0) | (0x1<<12) | (0x1<<16)); + writel(value, P_ISA_TIMER_MUX); + /*10ms generate an interrupt*/ + writel(10, P_ISA_TIMERA); +} +void wakeup_timer_clear(void) +{ + unsigned value; + value = readl(P_ISA_TIMER_MUX); + value &= ~((0x1<<12) | (0x1<<16)); + writel(value, P_ISA_TIMER_MUX); +} +static unsigned int detect_key(unsigned int suspend_from) +{ + int exit_reason = 0; + unsigned int time_out = readl(AO_DEBUG_REG2); + unsigned time_out_ms = time_out*100; + unsigned int ret; + unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE; + /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */ + + /* setup wakeup resources*/ + /*auto suspend: timerA 10ms resolution*/ + if (time_out_ms != 0) + wakeup_timer_setup(); + + init_remote(); +#ifdef CONFIG_CEC_WAKEUP + if (hdmi_cec_func_config & 0x1) { + remote_cec_hw_reset(); + cec_node_init(); + } +#endif + + /* *wakeup_en = 1;*/ + do { +#ifdef CONFIG_CEC_WAKEUP + if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) { + irq[IRQ_AO_CEC] = 0xFFFFFFFF; + if (suspend_from == SYS_POWEROFF) + continue; + if (cec_msg.log_addr) { + if (hdmi_cec_func_config & 0x1) { + cec_handler(); + if (cec_msg.cec_power == 0x1) { + /*cec power key*/ + exit_reason = CEC_WAKEUP; + break; + } + } + } else if (hdmi_cec_func_config & 0x1) { + cec_node_init(); + } + } +#endif + if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) { + irq[IRQ_TIMERA] = 0xFFFFFFFF; + if (time_out_ms != 0) + time_out_ms--; + if (time_out_ms == 0) { + wakeup_timer_clear(); + exit_reason = AUTO_WAKEUP; + } + } + + if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) { + irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF; + ret = remote_detect_key(); + if (ret == 1) + exit_reason = REMOTE_WAKEUP; + if (ret == 2) + exit_reason = REMOTE_CUS_WAKEUP; + } + + if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) { + irq[IRQ_AO_GPIO0] = 0xFFFFFFFF; + if ((readl(AO_GPIO_I) & (1<<2)) == 0) + exit_reason = POWER_KEY_WAKEUP; + } + if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) { + irq[IRQ_GPIO0] = 0xFFFFFFFF; + if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18)) + && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17)) + && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17))) + exit_reason = BT_WAKEUP; + } + if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) { + irq[IRQ_ETH_PHY] = 0xFFFFFFFF; + exit_reason = ETH_PHY_WAKEUP; + } + if (exit_reason) + break; + else + asm volatile("wfi"); + } while (1); + + wakeup_timer_clear(); + return exit_reason; +} + +static void pwr_op_init(struct pwr_op *pwr_op) +{ + pwr_op->power_off_at_clk81 = power_off_at_clk81; + pwr_op->power_on_at_clk81 = power_on_at_clk81; + pwr_op->power_off_at_24M = power_off_at_24M; + pwr_op->power_on_at_24M = power_on_at_24M; + pwr_op->power_off_at_32k = power_off_at_32k; + pwr_op->power_on_at_32k = power_on_at_32k; + + pwr_op->detect_key = detect_key; + pwr_op->get_wakeup_source = get_wakeup_source; + pwr_op->exit_reason = 0; + g_pwr_op = pwr_op; +} + diff --git a/board/amlogic/gxl_beast_v1/firmware/timing.c b/board/amlogic/gxl_beast_v1/firmware/timing.c new file mode 100644 index 0000000..f7c4b0c --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/firmware/timing.c @@ -0,0 +1,694 @@ + + +/* + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* DDR freq range */ +#define CONFIG_DDR_CLK_LOW 375 +#define CONFIG_DDR_CLK_HIGH 1500 +/* DON'T OVER THESE RANGE */ +#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH) + #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n" +#endif + +/* CPU freq range */ +#define CONFIG_CPU_CLK_LOW 600 +#define CONFIG_CPU_CLK_HIGH 2000 +/* DON'T OVER THESE RANGE */ +#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH) + #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n" +#endif + +#define DDR3_DRV_40OHM 0 +#define DDR3_DRV_34OHM 1 +#define DDR3_ODT_0OHM 0 +#define DDR3_ODT_60OHM 1 +#define DDR3_ODT_120OHM 2 +#define DDR3_ODT_40OHM 3 +#define DDR3_ODT_20OHM 4 +#define DDR3_ODT_30OHM 5 + +/* lpddr2 drv odt */ +#define LPDDR2_DRV_34OHM 1 +#define LPDDR2_DRV_40OHM 2 +#define LPDDR2_DRV_48OHM 3 +#define LPDDR2_DRV_60OHM 4 +#define LPDDR2_DRV_80OHM 6 +#define LPDDR2_DRV_120OHM 7 +#define LPDDR2_ODT_0OHM 0 + +/* lpddr3 drv odt */ +#define LPDDR3_DRV_34OHM 1 +#define LPDDR3_DRV_40OHM 2 +#define LPDDR3_DRV_48OHM 3 +#define LPDDR3_DRV_60OHM 4 +#define LPDDR3_DRV_80OHM 6 +#define LPDDR3_DRV_34_40OHM 9 +#define LPDDR3_DRV_40_48OHM 10 +#define LPDDR3_DRV_34_48OHM 11 +#define LPDDR3_ODT_0OHM 0 +#define LPDDR3_ODT_60OHM 1 +#define LPDDR3_ODT_120OHM 2 +#define LPDDR3_ODT_240OHM 3 + +#define DDR4_DRV_34OHM 0 +#define DDR4_DRV_48OHM 1 +#define DDR4_ODT_0OHM 0 +#define DDR4_ODT_60OHM 1 +#define DDR4_ODT_120OHM 2 +#define DDR4_ODT_40OHM 3 +#define DDR4_ODT_240OHM 4 +#define DDR4_ODT_48OHM 5 +#define DDR4_ODT_80OHM 6 +#define DDR4_ODT_34OHM 7 + +#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)) +#define CFG_DDR_DRV DDR3_DRV_40OHM +#define CFG_DDR_ODT DDR3_ODT_120OHM +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2) +#define CFG_DDR_DRV LPDDR2_DRV_48OHM +#define CFG_DDR_ODT DDR3_ODT_120OHM +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define CFG_DDR_DRV LPDDR3_DRV_48OHM +#define CFG_DDR_ODT LPDDR3_ODT_0OHM +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) +#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect +#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect +#endif + +#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one +#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one +//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one +//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one +#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)) +#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 % +#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 % +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define CONFIG_SOC_VREF 51 +#define CONFIG_DRAM_VREF 51 +#else +#define CONFIG_SOC_VREF 51 +#define CONFIG_DRAM_VREF 51 +#endif + +#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0 + +/* + * these parameters are corresponding to the pcb layout, + * please don't enable this function unless these signals + * has been measured by oscilloscope. + */ +#ifdef CONFIG_DDR_CMD_BDL_TUNE +#define DDR_AC_LCDLR 0 +#define DDR_CK0_BDL 18 +#define DDR_RAS_BDL 18 +#define DDR_CAS_BDL 24 +#define DDR_WE_BDL 21 +#define DDR_BA0_BDL 16 +#define DDR_BA1_BDL 2 +#define DDR_BA2_BDL 13 +#define DDR_ACPDD_BDL 27 +#define DDR_CS0_BDL 27 +#define DDR_CS1_BDL 27 +#define DDR_ODT0_BDL 27 +#define DDR_ODT1_BDL 27 +#define DDR_CKE0_BDL 27 +#define DDR_CKE1_BDL 27 +#define DDR_A0_BDL 14 +#define DDR_A1_BDL 9 +#define DDR_A2_BDL 5 +#define DDR_A3_BDL 18 +#define DDR_A4_BDL 4 +#define DDR_A5_BDL 16 +#define DDR_A6_BDL 1 +#define DDR_A7_BDL 10 +#define DDR_A8_BDL 4 +#define DDR_A9_BDL 7 +#define DDR_A10_BDL 10 +#define DDR_A11_BDL 9 +#define DDR_A12_BDL 6 +#define DDR_A13_BDL 16 +#define DDR_A14_BDL 8 +#define DDR_A15_BDL 27 +#endif + +/* CAUTION!! */ +/* + * For DDR3: + * 7-7-7: CONFIG_DDR_CLK range 375~ 533 + * 9-9-9: CONFIG_DDR_CLK range 533~ 667 + * 11-11-11: CONFIG_DDR_CLK range 667~ 800 + * 12-12-12: CONFIG_DDR_CLK range 800~ 933 + * 13-13-13: CONFIG_DDR_CLK range 933~1066 + * 14-14-14: CONFIG_DDR_CLK range 1066~1200 + */ +ddr_timing_t __ddr_timming[] = { + //ddr3_7_7_7 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_7, + .cfg_ddr_rtp = (6), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (7), + .cfg_ddr_rcd = (7), + .cfg_ddr_ras = (20), + .cfg_ddr_rrd = (6), + .cfg_ddr_rc = (27), + .cfg_ddr_mrd = (4), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (27), + .cfg_ddr_rfc = (160), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (6), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (4), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (4), + .cfg_ddr_refi = (78-2), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (7), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (5), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (4), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (512), + .cfg_ddr_xpdll = (20), + .cfg_ddr_zqcsi = (1000), + }, + //ddr3_9_9_9 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_9, + .cfg_ddr_rtp = (6), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (9), + .cfg_ddr_rcd = (9), + .cfg_ddr_ras = (27), + .cfg_ddr_rrd = (6), + .cfg_ddr_rc = (33), + .cfg_ddr_mrd = (4), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (30), + .cfg_ddr_rfc = (196), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (6), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (4), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (6), + .cfg_ddr_refi = (78-2), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (9), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (7), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (136), + .cfg_ddr_xpdll = (20), + .cfg_ddr_zqcsi = (1000), + }, + //ddr3_11_11_11 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_11, + .cfg_ddr_rtp = (7), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (11), + .cfg_ddr_rcd = (11), + .cfg_ddr_ras = (35), + .cfg_ddr_rrd = (7), + .cfg_ddr_rc = (45), + .cfg_ddr_mrd = (6), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (33), + .cfg_ddr_rfc = (280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (7), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (5), + .cfg_ddr_cke = (4), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78-2), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (11), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (8), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (136), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + }, + //ddr3_13_13_13 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_13, + .cfg_ddr_rtp = (7), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (13), + .cfg_ddr_rcd = (13), + .cfg_ddr_ras = (37), + .cfg_ddr_rrd = (7), + .cfg_ddr_rc = (52), + .cfg_ddr_mrd = (6), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (33), + .cfg_ddr_rfc = (280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (7), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78-2), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (13), + .cfg_ddr_wr = (16), + .cfg_ddr_cwl = (9), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (136), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + }, + /* ddr4 1600 timing */ + { + .identifier = CONFIG_DDR_TIMMING_DDR4_1600, + .cfg_ddr_rtp = (4), + .cfg_ddr_wtr = (6), + .cfg_ddr_rp = (11), + .cfg_ddr_rcd = (11), + .cfg_ddr_ras = (35), + .cfg_ddr_rrd = (4), + .cfg_ddr_rc = (46),//RAS+RP + .cfg_ddr_mrd = (8), + .cfg_ddr_mod = (24), + .cfg_ddr_faw = (28), + .cfg_ddr_rfc = (280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (8), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (1024), //597 768 1024 + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78-2), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (11), + .cfg_ddr_wr = (13), //15NS+1CLK + .cfg_ddr_cwl = (11), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (1024), //597 768 1024 + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = 128, + .cfg_ddr_zqcl = (256), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + .cfg_ddr_tccdl = (5), + }, + /* ddr4 2400 timing */ + { + .identifier = CONFIG_DDR_TIMMING_DDR4_2400, + .cfg_ddr_rtp = 9,//(4), + .cfg_ddr_wtr = 9,//(6), + .cfg_ddr_rp = 15*1.2,//(11), + .cfg_ddr_rcd = 15*1.2,//(11), + .cfg_ddr_ras = 35*1.2,//(35), + .cfg_ddr_rrd = (8), + .cfg_ddr_rc =50*1.2,// (46),//RAS+RP + .cfg_ddr_mrd = (8), + .cfg_ddr_mod = (24), + .cfg_ddr_faw = 35*1.2,//(28), + .cfg_ddr_rfc = 350*1.2,//(280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = 9.5*1.2,//(8), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (1024), //597 768 1024 + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (9), + .cfg_ddr_refi = (78-2), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = 15*1.2,// (11), + .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK + .cfg_ddr_cwl = 12,// (11), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (1024), //597 768 1024 + .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ? + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = 128, + .cfg_ddr_zqcl = (256), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + .cfg_ddr_tccdl = (6), + }, + /* lpddr3 timing */ + { + .identifier = CONFIG_DDR_TIMMING_LPDDR3, + .cfg_ddr_rtp = 6,// (6),0 + .cfg_ddr_wtr = (6+2), + .cfg_ddr_rp = (17), + .cfg_ddr_rcd = (15), + .cfg_ddr_ras = (34), + .cfg_ddr_rrd = (8), + .cfg_ddr_rc = (51), + .cfg_ddr_mrd = (11), + .cfg_ddr_mod = (12),//12-17 + .cfg_ddr_faw = (40), + .cfg_ddr_rfc = (168), + .cfg_ddr_wlmrd = (32), + .cfg_ddr_wlo = (8), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (6), + .cfg_ddr_cke = 7,//(6),//need <=7 + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (39-2), + .cfg_ddr_refi_mddr3 = (0), + .cfg_ddr_cl = (12), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (6), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (112), + .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3 + .cfg_ddr_cksre = 12,// (12),//pctl need 2? + .cfg_ddr_cksrx = 12,// (12),//pctl need 2? + .cfg_ddr_zqcs = (100), + .cfg_ddr_zqcl = (288), + .cfg_ddr_xpdll = (12), + .cfg_ddr_zqcsi = (1000), + // .cfg_ddr_rpab = (17), + // .cfg_ddr_rppb = (15), + // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1) + // .cfg_ddr_tdqsckmax = (5), + // .cfg_ddr_tckesr = (12), + // .cfg_ddr_tdpd = (500), + // .cfg_ddr_taond_aofd = 2, + } +}; + +ddr_set_t __ddr_setting = { + /* common and function defines */ + .ddr_channel_set = CONFIG_DDR_CHANNEL_SET, + .ddr_type = CONFIG_DDR_TYPE, + .ddr_clk = CONFIG_DDR_CLK, + .ddr4_clk = CONFIG_DDR4_CLK, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .ddr_timing_ind = 0, + .ddr_size = CONFIG_DDR_SIZE, + .ddr_pll_ctrl = (0), + .ddr_dmc_ctrl = 0, +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9) + .ddr0_addrmap = { + [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) , + [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) , + [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) , + [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) , + [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) , + }, + .ddr1_addrmap = { + [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) , + [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) , + [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) , + [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) , + [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) , + }, +#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10) + .ddr0_addrmap = { + [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) , + [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) , + [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) , + [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) , + [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) , + }, + .ddr1_addrmap = { + [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) , + [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) , + [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) , + [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) , + [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) , + }, +#endif /*CONFIG_LPDDR_REMAP_SET*/ +#else + .ddr0_addrmap = {0}, + .ddr1_addrmap = {0}, +#endif /*CONFIG_DDR_TYPE_LPDDR3*/ + .ddr_2t_mode = 1, + .ddr_full_test = CONFIG_DDR_FULL_TEST, +#if (0 == CONFIG_DDR_SIZE) + .ddr_size_detect = 1, +#else + .ddr_size_detect = 0, +#endif + .ddr_drv = CFG_DDR_DRV, + .ddr_odt = CFG_DDR_ODT, + .ddr4_drv = CFG_DDR4_DRV, + .ddr4_odt = CFG_DDR4_ODT, + + /* pub defines */ + .t_pub_ptr = { + [0] = ( 6 | (320 << 6) | (80 << 21)), + [1] = (120 | (1000 << 16)), + [2] = 0, + [3] = (20000 | (136 << 20)), + [4] = (1000 | (180 << 16)), + }, //PUB PTR0-3 + .t_pub_odtcr = 0x00030000, + .t_pub_mr = { + (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)), + (0X6|(1<<6)), + 0X20, + 0, + }, + .t_pub_dtpr = {0}, + .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0 + .t_pub_pgcr1 = 0x02004620, //PUB PGCR1 + .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2 + //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2 + .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3 + .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR + .t_pub_aciocr = {0}, //PUB ACIOCRx + .t_pub_dx0gcr = {0}, //PUB DX0GCRx + .t_pub_dx1gcr = {0}, //PUB DX1GCRx + .t_pub_dx2gcr = {0}, //PUB DX2GCRx + .t_pub_dx3gcr = {0}, //PUB DX3GCRx +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) + .t_pub_dcr = 0XB, //PUB DCR + .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, //PUB DTCR + .t_pub_dsgcr = 0x020641b, +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) + .t_pub_dcr = 0X40C, //PUB DCR + .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, + .t_pub_dsgcr = 0x020641b, +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) + .t_pub_dcr = 0X89, //PUB DCR + .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, + .t_pub_dsgcr = 0x02064db, +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO) + .t_pub_dcr = 0XB, //PUB DCR + .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, //PUB DTCR + .t_pub_dsgcr = 0x020641b, +#endif + .t_pub_vtcr1 = 0x0fc00172, + .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)), + +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +//lpddr3 + .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3 + .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR + .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR + .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR + +/* 2layer board + .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad + .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d, + .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d, +*/ +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) +/* 4layer ddr4 */ + .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR + .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR + .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR + .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR +#else // ddr3 and auto +/* sei210 4layer board ddr3 */ + .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR + .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR + .t_pub_zq2pr = 0x5d95d, //PUB ZQ2PR + .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR +#endif + + /* pctl0 defines */ + /* pctl1 use same define as pctl0 */ + .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U + .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N + .t_pctl0_init_us = 2, //PCTL TINIT + .t_pctl0_rsth_us = 2, //PCTL TRSTH + .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T + //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1 + .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset + //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1 + .t_pctl0_scfg = 0xF01, //PCTL SCFG + .t_pctl0_sctl = 0x1, //PCTL SCTL + .t_pctl0_ppcfg = 0, + .t_pctl0_dfistcfg0 = 0x4, + .t_pctl0_dfistcfg1 = 0x1, + .t_pctl0_dfitctrldelay = 2, + .t_pctl0_dfitphywrdata = 2, + .t_pctl0_dfitphywrlta = 7, + .t_pctl0_dfitrddataen = 8, + .t_pctl0_dfitphyrdlat = 22, + .t_pctl0_dfitdramclkdis = 1, + .t_pctl0_dfitdramclken = 1, + .t_pctl0_dfitphyupdtype0 = 16, + .t_pctl0_dfitphyupdtype1 = 16, + .t_pctl0_dfitctrlupdmin = 16, + .t_pctl0_dfitctrlupdmax = 64, + .t_pctl0_dfiupdcfg = 0x3, + .t_pctl0_cmdtstaten = 1, + //.t_pctl0_dfiodtcfg = 8, + //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ), + .t_pctl0_dfiodtcfg = (1<<3)|(1<<11), + .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)), + + .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)), + +///*lpddr3 +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) + .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY + .t_pub_aclcdlr = 0, + .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13 +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) +//2layer board DDR4 + .t_pub_acbdlr0 = 0, //0x3f, + .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value + .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10 +#else // ddr3 and auto +//4layer ddr3 + .t_pub_acbdlr0 = 0, + .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value + .t_pub_acbdlr3 = 0,//0xa, //cs +#endif + .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|( + (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))): + ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))), + .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608 + .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */ + +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) + //tianhe lpddr3 20161013 + .wr_adj_per = { + [0] = 90, //aclcdlr + [1] = 100, + [2] = 120, + [3] = 110, + [4] = 120, + [5] = 105, + }, + .rd_adj_per = { + [0] = 100, + [1] = 100, + [2] = 110, + [3] = 110, + [4] = 110, + [5] = 110,}, +#else + /* P212 */ + .wr_adj_per = { + [0]=100, + [1]=100, + [2]=95, + [3]=95, + [4]=95, + [5]=95, + }, + .rd_adj_per = { + [0]=100, + [1]=100, + [2]=88, + [3]=95, + [4]=95, + [5]=100, + }, +#endif + +}; + +pll_set_t __pll_setting = { + .cpu_clk = CONFIG_CPU_CLK / 24 * 24, + .spi_ctrl = 0, + .vddee = CONFIG_VDDEE_INIT_VOLTAGE, + .vcck = CONFIG_VCCK_INIT_VOLTAGE, + .lCustomerID = CONFIG_AML_CUSTOMER_ID, +#ifdef CONFIG_DEBUG_MODE + .debug_mode = CONFIG_DEBUG_MODE, + .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG, + .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG, +#endif + /* pll ssc setting: + + .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000 + .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+ + .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000- + + .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000 + .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+ + .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000- + + .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000 + .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+ + .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000- + */ + .ddr_pll_ssc = 0, +}; diff --git a/board/amlogic/gxl_beast_v1/gxl_beast_v1.c b/board/amlogic/gxl_beast_v1/gxl_beast_v1.c new file mode 100644 index 0000000..2352cef --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/gxl_beast_v1.c @@ -0,0 +1,696 @@ +/* + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <command.h> +#ifdef CONFIG_SYS_I2C_AML +#include <aml_i2c.h> +#include <asm/arch/secure_apb.h> +#endif +#include <amlogic/canvas.h> +#ifdef CONFIG_AML_VPU +#include <vpu.h> +#endif +#include <vpp.h> +#ifdef CONFIG_AML_V2_FACTORY_BURN +#include <amlogic/aml_v2_burning.h> +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/hdmi.h> +#endif +#include <asm/arch/eth_setup.h> +#include <phy.h> +#include <asm/cpu_id.h> +#include <asm/arch/mailbox.h> +#ifdef DTB_BIND_KERNEL +#include "storage.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +//new static eth setup +struct eth_board_socket* eth_board_skt; + +int serial_set_pin_port(unsigned long port_base) +{ + //UART in "Always On Module" + //GPIOAO_0==tx,GPIOAO_1==rx + //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} +void internalPhyConfig(struct phy_device *phydev) +{ + /*Enable Analog and DSP register Bank access by*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + /*Write Analog register 23*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417); + /*Enable fractional PLL*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B); + //Programme fraction FR_PLL_DIV1 + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D); + //## programme fraction FR_PLL_DiV1 + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C); +} + + +static void setup_net_chip(void) +{ + eth_aml_reg0_t eth_reg0; + + eth_reg0.d32 = 0; + eth_reg0.b.phy_intf_sel = 0; + eth_reg0.b.data_endian = 0; + eth_reg0.b.desc_endian = 0; + eth_reg0.b.rx_clk_rmii_invert = 0; + eth_reg0.b.rgmii_tx_clk_src = 0; + eth_reg0.b.rgmii_tx_clk_phase = 0; + eth_reg0.b.rgmii_tx_clk_ratio = 0; + eth_reg0.b.phy_ref_clk_enable = 0; + eth_reg0.b.clk_rmii_i_invert = 1; + eth_reg0.b.clk_en = 1; + eth_reg0.b.adj_enable = 0; + eth_reg0.b.adj_setup = 0; + eth_reg0.b.adj_delay = 0; + eth_reg0.b.adj_skew = 0; + eth_reg0.b.cali_start = 0; + eth_reg0.b.cali_rise = 0; + eth_reg0.b.cali_sel = 0; + eth_reg0.b.rgmii_rx_reuse = 0; + eth_reg0.b.eth_urgent = 0; + setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode + *P_PREG_ETH_REG2 = 0x10110181; + *P_PREG_ETH_REG3 = 0xe409087f; + setbits_le32(HHI_GCLK_MPEG1,1<<3); + /* power on memory */ + clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); + +} + + +extern struct eth_board_socket* eth_board_setup(char *name); +extern int designware_initialize(ulong base_addr, u32 interface); +int board_eth_init(bd_t *bis) +{ + setup_net_chip(); + udelay(1000); + designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII); + + return 0; +} + +#if CONFIG_AML_SD_EMMC +#include <mmc.h> +#include <asm/arch/sd_emmc.h> +static int sd_emmc_init(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: + //todo add card detect + //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6 + break; + case SDIO_PORT_C: + //enable pull up + //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0); + break; + default: + break; + } + + return cpu_sd_emmc_init(port); +} + +extern unsigned sd_debug_board_1bit_flag; +static int sd_emmc_detect(unsigned port) +{ + int ret; + switch (port) { + + case SDIO_PORT_A: + break; + case SDIO_PORT_B: + setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6 + ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1; + printf("%s\n", ret ? "card in" : "card out"); + if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in + if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) { + printf("sdio debug board detected, sd card with 1bit mode\n"); + sd_debug_board_1bit_flag = 1; + } else{ + printf("sdio debug board detected, no sd card in\n"); + sd_debug_board_1bit_flag = 0; + return 1; + } + } + break; + default: + break; + } + return 0; +} + + +static void sd_emmc_pwr_prepare(unsigned port) +{ + cpu_sd_emmc_pwr_prepare(port); +} + +static void sd_emmc_pwr_on(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + /// @todo NOT FINISH + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} +static void sd_emmc_pwr_off(unsigned port) +{ + /// @todo NOT FINISH + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} + +// #define CONFIG_TSD 1 +static void board_mmc_register(unsigned port) +{ + struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port); + if (aml_priv == NULL) + return; + + aml_priv->sd_emmc_init=sd_emmc_init; + aml_priv->sd_emmc_detect=sd_emmc_detect; + aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off; + aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on; + aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare; + aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info))); + + if (NULL == aml_priv->desc_buf) + printf(" desc_buf Dma alloc Fail!\n"); + else + printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf); + + sd_emmc_register(aml_priv); +} +int board_mmc_init(bd_t *bis) +{ + __maybe_unused struct mmc *mmc; +#ifdef CONFIG_VLSI_EMULATOR + //board_mmc_register(SDIO_PORT_A); +#else + //board_mmc_register(SDIO_PORT_B); +#endif + board_mmc_register(SDIO_PORT_B); + board_mmc_register(SDIO_PORT_C); +// board_mmc_register(SDIO_PORT_B1); +#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC) + /* try emmc here. */ + mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + if (!mmc) + printf("%s() %d: No MMC found\n", __func__, __LINE__); + else if (mmc_init(mmc)) + printf("%s() %d: MMC init failed\n", __func__, __LINE__); +#endif + return 0; +} + +#ifdef CONFIG_SYS_I2C_AML +#if 0 +static void board_i2c_set_pinmux(void){ + /*********************************************/ + /* | I2C_Master_AO |I2C_Slave | */ + /*********************************************/ + /* | I2C_SCK | I2C_SCK_SLAVE | */ + /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */ + /*********************************************/ + /* | I2C_SDA | I2C_SDA_SLAVE | */ + /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */ + /*********************************************/ + + //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO + clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23))); + //enable I2C MASTER AO pins + setbits_le32(P_AO_RTI_PIN_MUX_REG, + (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT)); + + udelay(10); +}; +#endif +struct aml_i2c_platform g_aml_i2c_plat = { + .wait_count = 1000000, + .wait_ack_interval = 5, + .wait_read_interval = 5, + .wait_xfer_interval = 5, + .master_no = AML_I2C_MASTER_AO, + .use_pio = 0, + .master_i2c_speed = AML_I2C_SPPED_400K, + .master_ao_pinmux = { + .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG, + .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT, + .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG, + .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT, + } +}; +#if 0 +static void board_i2c_init(void) +{ + //set I2C pinmux with PCB board layout + board_i2c_set_pinmux(); + + //Amlogic I2C controller initialized + //note: it must be call before any I2C operation + aml_i2c_init(); + + udelay(10); +} +#endif +#endif +#endif + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void){ + /*add board early init function here*/ + return 0; +} +#endif + +#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL +#include <asm/arch/usb-new.h> +#include <asm/arch/gpio.h> +#define CONFIG_GXL_USB_U2_PORT_NUM 2 +#define CONFIG_GXL_USB_U3_PORT_NUM 0 + +struct amlogic_usb_config g_usb_config_GXL_skt={ + CONFIG_GXL_XHCI_BASE, + USB_ID_MODE_HARDWARE, + NULL,//gpio_set_vbus_power, //set_vbus_power + CONFIG_GXL_USB_PHY2_BASE, + CONFIG_GXL_USB_PHY3_BASE, + CONFIG_GXL_USB_U2_PORT_NUM, + CONFIG_GXL_USB_U3_PORT_NUM, +}; +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#ifdef CONFIG_AML_HDMITX20 +static void hdmi_tx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ + clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23); + clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23); +} +#endif + +void msleep (ulong delay) +{ + ulong start = get_timer(0); + while (get_timer(start) < delay) { + if (ctrlc ()) + return; + udelay (100); + } +} + +static int do_detect_upgradekey(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int keyRet = 1; + char keyValArr[10]; + char* p_keyVal = keyValArr; + int mCnt = 0; + setbits_le32(P_AO_GPIO_O_EN_N, (1 << 2)); //GPIOAO_2 input + readl(AO_GPIO_I); + while(!(readl(AO_GPIO_I) & (0x01 << 2))) + { + if(mCnt == 1) { + run_command("osd clear;imgread pic logo fastboot $loadaddr;bmp display $fastboot_offset;bmp scale;",0); + } else if (mCnt == 31) { + run_command("osd clear;imgread pic logo burn $loadaddr;bmp display $burn_offset;bmp scale;",0); + } + mdelay(200); + mCnt++; + printf("--upgrade key press--\n"); + + if(mCnt > 30) { + printf("--be upgrade state--\n"); + } else if(mCnt > 3000) { + printf("--upgrade key press too long--\n"); + break; + } + } + if(mCnt > 30) { + p_keyVal = "upgrade"; + keyRet = 0; + } else if(mCnt > 1) { + //run_command("osd clear;imgread pic logo fastboot_recovery $loadaddr;bmp display $fastboot_recovery_offset;bmp scale;",0); + p_keyVal = "fastboot"; + keyRet = 0; + } + + printf("upgradekey_val:%s\n", p_keyVal); + setenv("upgradekey_val", p_keyVal); + return keyRet; +} + +U_BOOT_CMD( + detect_upgradekey, 1, 1, do_detect_upgradekey, + "Detect recovery key press","\n" +); +int board_init(void) +{ + //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init +#ifdef CONFIG_AML_V2_FACTORY_BURN + if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) { + aml_try_factory_usb_burning(0, gd->bd); + } +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN + /*for LED*/ + //clear pinmux + clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4))); + clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31))); + //set output mode + clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24)); + //set output 1 + setbits_le32(PREG_PAD_GPIO0_O, (1 << 24)); + + /*Power on GPIOAO_2 for VCC_5V*/ + clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18))); +#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL + board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST); +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + canvas_init(); + +#ifndef CONFIG_AML_IRDETECT_EARLY +#ifdef CONFIG_AML_HDMITX20 + hdmi_tx_set_hdmi_5v(); + hdmi_tx_init(); +#endif +#endif +#ifdef CONFIG_AML_NAND + extern int amlnf_init(unsigned char flag); + amlnf_init(0); +#endif + return 0; +} +#ifdef CONFIG_AML_IRDETECT_EARLY +#ifdef CONFIG_AML_HDMITX20 +static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + hdmi_tx_set_hdmi_5v(); + hdmi_tx_init(); +return 0; +} + +U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init, + "HDMI_INIT sub-system", + "hdmit init\n") +#endif +#endif +#ifdef CONFIG_BOARD_LATE_INIT +#define SAMPLE_BIT_MASK 0xfff +#define NUM 50 +#define BASE_CH7 1843 +#define P_SAR_ADC_REG0 (volatile unsigned int *)0xc1108680 +#define P_SAR_ADC_CHAN_LIST (volatile unsigned int *)0xc1108684 +#define P_SAR_ADC_REG3 (volatile unsigned int *)0xc110868c +#define P_SAR_ADC_FIFO_RD (volatile unsigned int *)0xc1108698 +#define P_SAR_ADC_DETECT_IDLE_SW (volatile unsigned int *)0xc11086a4 +#define P_SAR_ADC_REG13 (volatile unsigned int *)0xc11086b4 +#if 0 +#define dbgv(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else +#define dbgv(fmt, ...) +#endif +void quicksort1(unsigned int a[], int numsize) +{ + int i = 0, j = numsize-1; + int val = a[0]; + if (numsize > 1) { + while (i < j) { + for (; j > i; j--) + if (a[j] < val) { + a[i] = a[j]; + break; + } + for (; i < j; i++) + if (a[i] > val) { + a[j] = a[i]; + break; + } + } + a[i] = val; + quicksort1(a, i); + quicksort1(a+i+1, numsize-1-i); +} +} +int check_vref(void) +{ + int i,count; + unsigned int value[50]; + unsigned int value7=0; + unsigned int bak, bak_reg3; + unsigned int vref_efuse = (readl(SEC_AO_SEC_SD_CFG12)>>19)&(0x1f); + + if (!vref_efuse) { + dbgv("This chip has no FT vref, no need to check, PASS\n"); + return 0; + } + //run_command("md 0xc1108680 0x10", 0); + dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12)); + dbgv("vref_efuse: %d\n",vref_efuse); + + dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13)); + bak = (readl(P_SAR_ADC_REG13)>>8)&0x3f; /*back up SAR_ADC_REG13[13:8]*/ + writel((readl(P_SAR_ADC_REG13)&(~(0x3f<<8)))|(vref_efuse<<9), P_SAR_ADC_REG13); + dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13)); + writel(0x00000007, P_SAR_ADC_CHAN_LIST);/*ch7*/ + //writel(0xc000c|(0x7<<23)|(0x7<<7), P_SAR_ADC_DETECT_IDLE_SW);/*channel 7*/ + bak_reg3 = readl(P_SAR_ADC_REG3); + writel((readl(P_SAR_ADC_REG3)&(~(0x7<<23)))|(0x2<<23), P_SAR_ADC_REG3);/*AVDD18/2*/ + dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13)); + //run_command("md 0xc1108680 0x10", 0); + for (i=0;i<NUM;i++) { + writel((readl(P_SAR_ADC_REG0)&(~(1<<0))), P_SAR_ADC_REG0); + writel((readl(P_SAR_ADC_REG0)|(1<<0)), P_SAR_ADC_REG0); + writel((readl(P_SAR_ADC_REG0)|(1<<2)), P_SAR_ADC_REG0);/*start sample*/ + count = 0; + do { + udelay(20); + count++; + } while ((readl(P_SAR_ADC_REG0) & (0x7<<28)) + && (count < 100));/*finish sample?*/ + if (count == 100) { + printf("%s : ch7 wait finish sample timeout!\n",__func__); + return -1; + } + value[i] = readl(P_SAR_ADC_FIFO_RD); /*read saradc*/ + if (((value[i]>>12) & 0x7) == 0x7) + value[i] = value[i]&SAMPLE_BIT_MASK; + else { + printf("%s : not ch7! sample err!\n",__func__); + return -1; + } + } + quicksort1(value, NUM); + for (i = 0; i < NUM; i++) + dbgv("%d ", value[i]); + dbgv("\n"); + for (i = 2; i < NUM-2; i++) + value7 += value[i]; + value7 = value7/(NUM-4); + dbgv("the average ch7 adc=%d\n", value7); + dbgv("vref_efuse: %d\n",vref_efuse); + if ((value7 < (BASE_CH7*94/100)) || (value7 > (BASE_CH7*106/100))) { //1843 + printf("the average ch7 : %d out of range: %d ~ %d\n", + value7, (BASE_CH7*94/100), (BASE_CH7*106/100)); + printf("replace FT vref...\n"); + thermal_calibration(4, bak>>1); /*[13:9]*/ + } + /*write back SAR_ADC_REG13[13:8]*/ + writel(((readl(P_SAR_ADC_REG13))&(~(0x3f<<8)))| + ((bak & 0x3f)<<8), + P_SAR_ADC_REG13); + writel(bak_reg3, P_SAR_ADC_REG3); + dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13)); + dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12)); + //run_command("md 0xc1108680 0x10", 0); + return 0; +} + +int board_late_init(void){ + + //update env before anyone using it + run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\ + "if test ${reboot_mode} = factory_reset; then "\ + "defenv_reserv;setenv upgrade_step 2;save; fi;", 0); + run_command("if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + + /*add board late init function here*/ +#ifndef DTB_BIND_KERNEL + int ret; + ret = run_command("store dtb read $dtb_mem_addr", 1); + if (ret) { + printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__); + #ifdef CONFIG_DTB_MEM_ADDR + char cmd[64]; + printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR); + sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR); + ret = run_command(cmd, 1); + if (ret) { + printf("%s(): %s fail\n", __func__, cmd); + } + #endif + } +#elif defined(CONFIG_DTB_MEM_ADDR) + { + char cmd[128]; + int ret; + if (!getenv("dtb_mem_addr")) { + sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR); + run_command(cmd, 0); + } + sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}"); + ret = run_command(cmd, 0); + if (ret) { + printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret); + } + } +#endif// #ifndef DTB_BIND_KERNEL + +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif + vpp_init(); +#ifndef CONFIG_AML_IRDETECT_EARLY + /* after */ + run_command("cvbs init;hdmitx hpd", 0); + run_command("vout output $outputmode", 0); +#endif + +#ifdef CONFIG_AML_V2_FACTORY_BURN + if (0x1b8ec003 == readl(P_PREG_STICKY_REG2)) + aml_try_factory_usb_burning(1, gd->bd); + aml_try_factory_sdcard_burning(0, gd->bd); +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN + ret = check_vref(); + if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) { + setenv("maxcpus","4"); + } + return 0; +} +#endif + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4); +#endif +} + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + unsigned int ddr_size=0; + char loc_name[64] = {0}; + int i; + for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) { + ddr_size += gd->bd->bi_dram[i].size; + } +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + ddr_size += CONFIG_SYS_MEM_TOP_HIDE; +#endif + switch (ddr_size) { + case 0x80000000: + strcpy(loc_name, "gxl_sei210_2g\0"); + break; + case 0x40000000: + strcpy(loc_name, "gxl_sei210_1g\0"); + break; + case 0x2000000: + strcpy(loc_name, "gxl_sei210_512m\0"); + break; + default: + //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size); + strcpy(loc_name, "gxl_sei210_unsupport"); + break; + } + strcpy(name, loc_name); + setenv("aml_dt", loc_name); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "aml_dt", + "firstboot", + "lock", + + NULL//Keep NULL be last to tell END +}; diff --git a/board/amlogic/gxl_beast_v1/lcd.c b/board/amlogic/gxl_beast_v1/lcd.c new file mode 100644 index 0000000..24dae0f --- a/dev/null +++ b/board/amlogic/gxl_beast_v1/lcd.c @@ -0,0 +1,236 @@ +/* + * AMLOGIC TV LCD panel driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the named License, + * or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <amlogic/aml_lcd.h> +#include <asm/arch/gpio.h> + +//Rsv_val = 0xffffffff + +static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "invalid", /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "invalid", /* ending flag */ +}; + +struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = { + { + "lcd_0",LCD_TTL,6, + /* basic timing */ + 1280,720,1650,750,40,220,1,5,20,1, + /* clk_attr */ + 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* ttl_attr */ + 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 60,255,10,128,128, + 0xff,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, +}; + +//**** Special parameters just for ttl ***// +static struct ttl_config_s lcd_ttl_config = { + .clk_pol = 0, + .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */ + .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */ +}; + +//**** Special parameters just for lvds ***// +static struct lvds_config_s lcd_lvds_config = { + .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode + .dual_port = 1, //0=single port, 1=double port + .pn_swap = 0, //0=normal, 1=swap + .port_swap = 0, //0=normal, 1=swap + .lane_reverse = 0, //0=normal, 1=swap +}; + +static struct lcd_power_ctrl_s lcd_power_ctrl = { + .power_on_step = { + { + .type = LCD_POWER_TYPE_SIGNAL, + .delay = 0, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, + .power_off_step = { + { + .type = LCD_POWER_TYPE_SIGNAL, + .delay = 50, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, +}; + +struct lcd_config_s lcd_config_dft = { + .lcd_mode = LCD_MODE_TABLET, + .lcd_key_valid = 0, + .lcd_basic = { + .model_name = "default", + .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE + .lcd_bits = 8, + .h_active = 1920, + .v_active = 1080, + .h_period = 2200, + .v_period = 1125, + + .screen_width = 16, + .screen_height = 9, + }, + + .lcd_timing = { + .clk_auto = 1, + .lcd_clk = 60, + .ss_level = 0, + .fr_adjust_type = 0, + + .hsync_width = 44, + .hsync_bp = 148, + .hsync_pol = 0, + .vsync_width = 5, + .vsync_bp = 36, + .vsync_pol = 0, + }, + + .lcd_control = { + .ttl_config = &lcd_ttl_config, + .lvds_config = &lcd_lvds_config, + }, + .lcd_power = &lcd_power_ctrl, + .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}}, +}; + +#ifdef CONFIG_AML_LCD_EXTERN +static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = { + "invalid", /* ending flag */ +}; + +#define LCD_EXTERN_NAME "ext_default" +#define LCD_EXTERN_CMD_SIZE 9 +static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = { + 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00, + 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00, + 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00, + 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */ + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */ +}; + +static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = { + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */ +}; + +struct lcd_extern_config_s ext_config_dtf = { + .lcd_ext_key_valid = 0, + .index = LCD_EXTERN_INDEX_INVALID, + .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */ + .status = 0, /* 0=disable, 1=enable */ + .i2c_addr = 0x1c, /* 7bit i2c address */ + .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */ + .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */ + .spi_gpio_cs = 0, + .spi_gpio_clk = 1, + .spi_gpio_data = 2, + .spi_clk_freq = 0, /* hz */ + .spi_clk_pol = 0, + .cmd_size = LCD_EXTERN_CMD_SIZE, + .table_init_on = init_on_table, + .table_init_off = init_off_table, +}; +#endif + +struct bl_config_s bl_config_dft = { + .name = "default", + .bl_key_valid = 0, + + .level_default = 100, + .level_min = 10, + .level_max = 255, + .level_mid = 128, + .level_mid_mapping = 128, + .level = 0, + + .method = BL_CTRL_MAX, + .power_on_delay = 200, + .power_off_delay = 200, + + .en_gpio = 0xff, + .en_gpio_on = 1, + .en_gpio_off = 0, + + .bl_pwm = NULL, + .bl_pwm_combo0 = NULL, + .bl_pwm_combo1 = NULL, + .pwm_on_delay = 10, + .pwm_off_delay = 10, + + .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}}, +}; + +void lcd_config_bsp_init(void) +{ + int i, j; + + for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_cpu_gpio[i], "invalid") == 0) + break; + strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]); + } + for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++) + strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid"); + for (i = 0; i < BL_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_bl_gpio[i], "invalid") == 0) + break; + strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]); + } + for (j = i; j < BL_GPIO_NUM_MAX; j++) + strcpy(bl_config_dft.gpio_name[j], "invalid"); + +#ifdef CONFIG_AML_LCD_EXTERN + for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_ext_gpio[i], "invalid") == 0) + break; + strcpy(ext_config_dtf.gpio_name[i], lcd_ext_gpio[i]); + } + for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++) + strcpy(ext_config_dtf.gpio_name[j], "invalid"); + + strcpy(ext_config_dtf.name, LCD_EXTERN_NAME); +#endif +} diff --git a/board/amlogic/sm1_sabrina_v1/Kconfig b/board/amlogic/sm1_sabrina_v1/Kconfig new file mode 100755 index 0000000..db63492 --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/Kconfig @@ -0,0 +1,22 @@ +if TARGET_MESON_G12A + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "sm1_sabrina_v1" + +config SYS_VENDOR + string + default "amlogic" + +config SYS_SOC + string + default "g12a" + +config SYS_CONFIG_NAME + default "sm1_sabrina_v1" + +endif diff --git a/board/amlogic/sm1_sabrina_v1/Makefile b/board/amlogic/sm1_sabrina_v1/Makefile new file mode 100755 index 0000000..fb7f59a --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/Makefile @@ -0,0 +1,3 @@ + +obj-y += $(BOARD).o eth_setup.o +obj-$(CONFIG_AML_LCD) += lcd.o diff --git a/board/amlogic/sm1_sabrina_v1/aml-user-key.sig b/board/amlogic/sm1_sabrina_v1/aml-user-key.sig new file mode 100755 index 0000000..2ceabc1 --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/aml-user-key.sig @@ -0,0 +1,28 @@ +yÅtÃ}| 4B²/i Ö»x¹nÜ:fÙÞžpdd'üá¹àê¯të©NöZ ¿!˜£òÄ@í $ ã×-È°°ÃÒ š‰°2³{ñ^žsWµñí ²`Dù‚#”@¸>…+äbŒqÏŽy”¡dàéÊÇ:“TŒ8Ο„
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âÈcÊ] +|¬$ô! O"QK +q'¡îçü>õìo‹éÜdÚ WÏ|û¤Œv¼K´f1$z‚îÓA×'ê<ªÊFxPTõÑ³ç ‚³ÿpüëyy̽±[’Ëkq¦A<œˆ¸'¼BNFÇ‹‡#Ï0Û{ã¹¥ˆvÝxõãøÖ( º4ªiWA¹Ç“ÍažJK¼êäÚ¶ë ðØÕÆèªù†Z‰;Å–;(YZË~ŒÀ@0†Å~< +ÑÒ“Jÿƒ—–Øy8ýûÛ·Ûkx +²KÕ\E¦=ò + diff --git a/board/amlogic/sm1_sabrina_v1/eth_setup.c b/board/amlogic/sm1_sabrina_v1/eth_setup.c new file mode 100755 index 0000000..882a37d --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/eth_setup.c @@ -0,0 +1,51 @@ + +/* + * board/amlogic/txl_skt_v1/eth_setup.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/arch/eth_setup.h> +/* + * + *setup eth device board socket + * + */ +struct eth_board_socket* eth_board_setup(char *name){ + struct eth_board_socket* new_board; + new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket)); + if (NULL == new_board) return NULL; + if (name != NULL) { + new_board->name=(char*)malloc(strlen(name)); + strncpy(new_board->name,name,strlen(name)); + }else{ + new_board->name="gxb"; + } + + new_board->eth_pinmux_setup=NULL ; + new_board->eth_clock_configure=NULL; + new_board->eth_hw_reset=NULL; + return new_board; +} +//pinmux HHI_GCLK_MPEG1[bit 3] +// diff --git a/board/amlogic/sm1_sabrina_v1/firmware/ramdump.c b/board/amlogic/sm1_sabrina_v1/firmware/ramdump.c new file mode 100755 index 0000000..e03dcd2 --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/firmware/ramdump.c @@ -0,0 +1,45 @@ + +#ifdef CONFIG_MDUMP_COMPRESS +#include "ramdump.h" + +struct ram_compress_full __ramdump_data = { + .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR, + .full_memsize = CONFIG_DDR_TOTAL_SIZE, + .section_count = CONFIG_COMPRESS_SECTION, + .sections = { + { + /* memory afer compressed data address */ + .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR, + .section_size = CONFIG_DDR_TOTAL_SIZE - + CONFIG_COMPRESSED_DATA_ADDR, + .section_index = 4, + .compress_type = RAM_COMPRESS_NORMAL, + }, + { + /* memory before bl2 */ + .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR, + .section_size = CONFIG_BL2_IGNORE_ADDR - + CONFIG_COMPRESS_START_ADDR, + .section_index = 1, + .compress_type = RAM_COMPRESS_NORMAL, + }, + { + /* memory in reserved bl2 */ + .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR, + .section_size = CONFIG_BL2_IGNORE_SIZE, + .section_index = 2, + .compress_type = RAM_COMPRESS_SET, + .set_value = 0x0, + }, + { + /* segment 4: normal compress */ + .phy_addr = (void *)CONFIG_SEG4_ADDR, + .section_size = CONFIG_COMPRESSED_DATA_ADDR - + CONFIG_SEG4_ADDR, + .section_index = 3, + .compress_type = RAM_COMPRESS_NORMAL, + } + }, +}; +#endif /* CONFIG_MDUMP_COMPRESS */ + diff --git a/board/amlogic/sm1_sabrina_v1/firmware/ramdump.h b/board/amlogic/sm1_sabrina_v1/firmware/ramdump.h new file mode 100755 index 0000000..0671567 --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/firmware/ramdump.h @@ -0,0 +1,75 @@ +#ifndef __RAM_DUMP_H__ +#define __RAM_DUMP_H__ + +#include <config.h> +#ifdef CONFIG_MDUMP_COMPRESS +#define CONFIG_COMPRESS_SECTION 4 + +#if CONFIG_COMPRESS_SECTION > 8 +#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8 +#endif +/* + * Full Memory lay out for RAM compress: + * + * DDR_TOP -> +--------+ + * | | + * | | + * | 4 | + * | | + * | | + * |~~~~~~~~| <- store compressing data + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * COMPRESSED_DATA -> +--------+ + * | | + * | 3 | + * | | + * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE + * |||||||||| + * ||||2||||| + * |||||||||| + * BL2_IGNORE_ADDR -> +--------+ + * | | + * | 1 | + * | | + * COMPRESS_START_ADDR -> +--------+ + */ +#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20) +#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000) +#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000) + +#define CONFIG_COMPRESS_START_ADDR (0x00000000) +#define CONFIG_BL2_IGNORE_ADDR (0x05000000) +#define CONFIG_BL2_IGNORE_SIZE (0x00300000) +#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \ + CONFIG_BL2_IGNORE_SIZE) + +enum { + RAM_COMPRESS_NORMAL = 1, + RAM_COMPRESS_COPY = 2, + RAM_COMPRESS_SET = 3 /* set ram content to same vale */ +}; + +struct ram_compress_section { + void *phy_addr; + unsigned int section_size; + unsigned int section_index : 8; + unsigned int compress_type : 8; + unsigned int set_value : 16; +}; + +struct ram_compress_full { + void *store_phy_addr; + unsigned int full_memsize; + unsigned int section_count; + struct ram_compress_section sections[CONFIG_COMPRESS_SECTION]; +}; + +#endif +#endif /* __RAM_DUMP_H__ */ diff --git a/board/amlogic/sm1_sabrina_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_sabrina_v1/firmware/scp_task/pwm_ctrl.h new file mode 100755 index 0000000..b05c1fa --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/firmware/scp_task/pwm_ctrl.h @@ -0,0 +1,60 @@ +/* +*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h +*table for Dynamic Voltage/Frequency Scaling +*/ +#ifndef __PWM_CTRL_H__ +#define __PWM_CTRL_H__ + +static int pwm_voltage_table_ee[][2] = { + { 0x1c0000, 681}, + { 0x1b0001, 691}, + { 0x1a0002, 701}, + { 0x190003, 711}, + { 0x180004, 721}, + { 0x170005, 731}, + { 0x160006, 741}, + { 0x150007, 751}, + { 0x140008, 761}, + { 0x130009, 772}, + { 0x12000a, 782}, + { 0x11000b, 792}, + { 0x10000c, 802}, + { 0x0f000d, 812}, + { 0x0e000e, 822}, + { 0x0d000f, 832}, + { 0x0c0010, 842}, + { 0x0b0011, 852}, + { 0x0a0012, 862}, + { 0x090013, 872}, + { 0x080014, 882}, + { 0x070015, 892}, + { 0x060016, 902}, + { 0x050017, 912}, + { 0x040018, 922}, + { 0x030019, 932}, + { 0x02001a, 942}, + { 0x01001b, 952}, + { 0x00001c, 962} +}; +static int pwm_voltage_table_ee_new[][2] = { + { 0x120000, 700}, + { 0x110001, 710}, + { 0x100002, 720}, + { 0x0f0003, 730}, + { 0x0e0004, 740}, + { 0x0d0005, 750}, + { 0x0c0006, 760}, + { 0x0b0007, 770}, + { 0x0a0008, 780}, + { 0x090009, 790}, + { 0x08000a, 800}, + { 0x07000b, 810}, + { 0x06000c, 820}, + { 0x05000d, 830}, + { 0x04000e, 840}, + { 0x03000f, 850}, + { 0x020010, 860}, + { 0x010011, 870}, + { 0x000012, 880}, +}; +#endif //__PWM_CTRL_H__ diff --git a/board/amlogic/sm1_sabrina_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_sabrina_v1/firmware/scp_task/pwr_ctrl.c new file mode 100755 index 0000000..0f1467d --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/firmware/scp_task/pwr_ctrl.c @@ -0,0 +1,216 @@ + +/* + * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <gpio.h> +#include "pwm_ctrl.h" +#ifdef CONFIG_CEC_WAKEUP +#include <cec_tx_reg.h> +#endif + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static void set_vddee_voltage(unsigned int target_voltage) +{ + unsigned int to, pwm_size = 0; + static int (*pwm_voltage_ee)[2]; + + /* BOOT_9 = H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */ + /*set BOOT_9 input mode*/ + writel((readl(PREG_PAD_GPIO0_EN_N) | 0x200), PREG_PAD_GPIO0_EN_N); + if (((readl(PREG_PAD_GPIO0_EN_N) & 0x200 ) == 0x200) && + ((readl(PREG_PAD_GPIO0_I) & 0x200 ) == 0x0)) { + uart_puts("use vddee new table!"); + uart_puts("\n"); + pwm_voltage_ee = pwm_voltage_table_ee_new; + pwm_size = ARRAY_SIZE(pwm_voltage_table_ee_new); + } else { + uart_puts("use vddee table!"); + uart_puts("\n"); + pwm_voltage_ee = pwm_voltage_table_ee; + pwm_size = ARRAY_SIZE(pwm_voltage_table_ee); + } + + for (to = 0; to < pwm_size; to++) { + if (pwm_voltage_ee[to][1] >= target_voltage) { + break; + } + } + + if (to >= pwm_size) { + to = pwm_size - 1; + } + + writel(*(*(pwm_voltage_ee + to)), AO_PWM_PWM_B); +} + +static void power_off_at_24M(unsigned int suspend_from) +{ + /*set gpioH_8 low to power off vcc 5v*/ + writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N); + writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C); + + /*set test_n low to power off vcck & vcc 3.3v*/ + writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O); + writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N); + writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1); + + /*step down ee voltage*/ + set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE); +} + +static void power_on_at_24M(unsigned int suspend_from) +{ + /*step up ee voltage*/ + set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE); + + /*set test_n low to power on vcck & vcc 3.3v*/ + writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O); + writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N); + writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1); + _udelay(100); + + /*set gpioH_8 low to power on vcc 5v*/ + writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N); + writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C); + _udelay(10000); +} + +void get_wakeup_source(void *response, unsigned int suspend_from) +{ + struct wakeup_info *p = (struct wakeup_info *)response; + struct wakeup_gpio_info *gpio; + unsigned val; + unsigned i = 0; + + p->status = RESPONSE_OK; + val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC | + BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC | CECB_WAKEUP_SRC); + + p->sources = val; + + /* Power Key: AO_GPIO[3]*/ + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = POWER_KEY_WAKEUP_SRC; + gpio->gpio_in_idx = GPIOAO_3; + gpio->gpio_in_ao = 1; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_AO_GPIO0_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; + + /*Eth:GPIOZ_14*/ + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = ETH_PHY_GPIO_SRC; + gpio->gpio_in_idx = GPIOZ_14; + gpio->gpio_in_ao = 0; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_GPIO1_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; + + /*bt wake host*/ + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = BT_WAKEUP_SRC; + gpio->gpio_in_idx = GPIOX_18; + gpio->gpio_in_ao = 0; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_GPIO0_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; +} +extern void __switch_idle_task(void); + +static unsigned int detect_key(unsigned int suspend_from) +{ + int exit_reason = 0; + unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE; + init_remote(); +#ifdef CONFIG_CEC_WAKEUP + if (hdmi_cec_func_config & 0x1) { + remote_cec_hw_reset(); + cec_node_init(); + } +#endif + + do { + #ifdef CONFIG_CEC_WAKEUP + if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) { + irq[IRQ_AO_CECB] = 0xFFFFFFFF; + if (cec_power_on_check()) + exit_reason = CEC_WAKEUP; + } + #endif + if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) { + irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF; + if (remote_detect_key()) + exit_reason = REMOTE_WAKEUP; + } + + if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) { + irq[IRQ_VRTC] = 0xFFFFFFFF; + exit_reason = RTC_WAKEUP; + } + + if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) { + irq[IRQ_AO_GPIO0] = 0xFFFFFFFF; + if ((readl(AO_GPIO_I) & (1<<3)) == 0) + exit_reason = POWER_KEY_WAKEUP; + } +#if 0 + if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) { + irq[IRQ_GPIO1] = 0xFFFFFFFF; + if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14)) + && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14))) + exit_reason = ETH_PHY_GPIO; + } +#endif + if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) { + irq[IRQ_GPIO0] = 0xFFFFFFFF; + if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18)) + && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17)) + && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17))) + exit_reason = BT_WAKEUP; + } + + if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) { + irq[IRQ_ETH_PTM]= 0xFFFFFFFF; + exit_reason = ETH_PMT_WAKEUP; + } + + if (exit_reason) + break; + else + __switch_idle_task(); + } while (1); + + return exit_reason; +} + +static void pwr_op_init(struct pwr_op *pwr_op) +{ + pwr_op->power_off_at_24M = power_off_at_24M; + pwr_op->power_on_at_24M = power_on_at_24M; + pwr_op->detect_key = detect_key; + pwr_op->get_wakeup_source = get_wakeup_source; +} diff --git a/board/amlogic/sm1_sabrina_v1/firmware/timing.c b/board/amlogic/sm1_sabrina_v1/firmware/timing.c new file mode 100755 index 0000000..f85122e --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/firmware/timing.c @@ -0,0 +1,662 @@ + +/* + * board/amlogic/txl_skt_v1/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + + + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] = { +{ + /* g12a (Google) lpddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.fast_boot[0]=6, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1584, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 2048,//1024, + .dram_cs1_size_MB = 0,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .pll_ssc_mode = 0, + .clk_drv_ohm = 48, + .cs_drv_ohm = 48, + .ac_drv_ohm = 48, + .soc_data_drv_ohm_p = 48, + .soc_data_drv_ohm_n = 48, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 48, + .dram_data_drv_ohm = 48, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 48,//120,// 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = +//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29}, + {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, + .bitTimeControl_2d = 1, + //.slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT, + //.dqs_adjust={100,100,100,100,100,100,100,100, + // 100,100,100,100,100,100,100,100, + //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read +}, +{ + /* g12a skt (u209) ddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1584, 0, 0, 0}, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, //60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 0,//700, + .vref_dram_permil = 0,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* g12a skt (u209) ddr3 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0xffff, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0c0c, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* g12a skt (u209) lpddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1392, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0xffff,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0808, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 120, + .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, +}, +#if 0 +{ + /* g12a Y2 dongle */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1392, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0808, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 120, + .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29}, + .dram_rtt_nom_wr_park = {00,00}, + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* lpddr3 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR3, + .DRAMFreq = {600, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa,//0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0xffff,//1024, + .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x00c, + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 30, // + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x3ff,//0x253, + .soc_ac_slew_rate = 0x3ff,//0x253, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 800,//200, + .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why? + .vref_dram_permil = 500,//875, + //.vref_reverse = 0, + .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ), + [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8}, + .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24}, + //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6}, + .dram_rtt_nom_wr_park = {00,00}, + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, +}, +#endif +}; + +pll_set_t __pll_setting = { + .cpu_clk = CONFIG_CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = CONFIG_AML_CUSTOMER_ID, +#ifdef CONFIG_DEBUG_MODE + .debug_mode = CONFIG_DEBUG_MODE, + .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG, + .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG, +#endif +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + +#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE +#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 800) + #define VCCK_VAL_REG 0x00150007 +#elif (VCCK_VAL == 810) + #define VCCK_VAL_REG 0x00140008 +#elif (VCCK_VAL == 820) + #define VCCK_VAL_REG 0x00130009 +#elif (VCCK_VAL == 830) + #define VCCK_VAL_REG 0x0012000a +#elif (VCCK_VAL == 840) + #define VCCK_VAL_REG 0x0011000b +#elif (VCCK_VAL == 850) + #define VCCK_VAL_REG 0x0010000c +#elif (VCCK_VAL == 860) + #define VCCK_VAL_REG 0x000f000d +#elif (VCCK_VAL == 870) + #define VCCK_VAL_REG 0x000e000e +#elif (VCCK_VAL == 880) + #define VCCK_VAL_REG 0x000d000f +#elif (VCCK_VAL == 890) + #define VCCK_VAL_REG 0x000c0010 +#elif (VCCK_VAL == 900) + #define VCCK_VAL_REG 0x000b0011 +#elif (VCCK_VAL == 910) + #define VCCK_VAL_REG 0x000a0012 +#elif (VCCK_VAL == 920) + #define VCCK_VAL_REG 0x00090013 +#elif (VCCK_VAL == 930) + #define VCCK_VAL_REG 0x00080014 +#elif (VCCK_VAL == 940) + #define VCCK_VAL_REG 0x00070015 +#elif (VCCK_VAL == 950) + #define VCCK_VAL_REG 0x00060016 +#elif (VCCK_VAL == 960) + #define VCCK_VAL_REG 0x00050017 +#elif (VCCK_VAL == 970) + #define VCCK_VAL_REG 0x00040018 +#elif (VCCK_VAL == 980) + #define VCCK_VAL_REG 0x00030019 +#elif (VCCK_VAL == 990) + #define VCCK_VAL_REG 0x0002001a +#elif (VCCK_VAL == 1000) + #define VCCK_VAL_REG 0x0001001b +#elif (VCCK_VAL == 1010) + #define VCCK_VAL_REG 0x0000001c +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/ +/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 800) + #define VDDEE_VAL_REG0 0x0010000c + #define VDDEE_VAL_REG1 0x0008000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG0 0x000f000d + #define VDDEE_VAL_REG1 0x0007000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG0 0x000e000e + #define VDDEE_VAL_REG1 0x0006000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG0 0x000d000f + #define VDDEE_VAL_REG1 0x0005000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG0 0x000c0010 + #define VDDEE_VAL_REG1 0x0004000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG0 0x000b0011 + #define VDDEE_VAL_REG1 0x0003000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG0 0x000a0012 + #define VDDEE_VAL_REG1 0x00020010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG0 0x00090013 + #define VDDEE_VAL_REG1 0x00010011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG0 0x00080014 + #define VDDEE_VAL_REG1 0x00000012 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2))) +#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2))) +#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2))) +#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2))) +#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2))) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + /* eg: PWM init */ + + /* PWM_AO_D */ + /* VCCK_VAL_REG: check PWM table */ + {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0}, + {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0}, + + /* set BOOT_9 input */ + //{PAD_PULL_UP_EN_REG0, 1 << 9, 1 << 9, 0, BL2_INIT_STAGE_1, 0}, + + /* PWM_AO_B */ + /* VDDEE init start */ + /* step1: CHK HW */ + {(uint64_t)P_ASSIST_POR_CONFIG, 7, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0}, + + /* step2: match PWM config */ + /* GPIO9[BIT7]=H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */ + {0x1, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0}, + {0x0, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0}, + + /* step3: config PWM */ + /* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/ + {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0}, + {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0}, + {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0}, + /* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/ + {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0}, + {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0}, + {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0}, + /* VDDEE init done */ + /* Enable 5V_EN */ + {GPIO_O_EN_N_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0}, + {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* Enable VCCK */ + {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* Init sys led*/ + {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0}, + {AO_GPIO_O, (1 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0}, +}; diff --git a/board/amlogic/sm1_sabrina_v1/lcd.c b/board/amlogic/sm1_sabrina_v1/lcd.c new file mode 100755 index 0000000..7127f30 --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/lcd.c @@ -0,0 +1,652 @@ +/* + * AMLOGIC LCD panel driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the named License, + * or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <amlogic/aml_lcd.h> +#include <asm/arch/gpio.h> + +#ifdef CONFIG_AML_LCD_EXTERN +#include "lcd_extern.h" +#endif + +static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "GPIOZ_9", /* panel rst */ + "GPIOZ_8", /* panel power */ + "invalid", /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step[] = { + {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = { + {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */ +#if 0 + {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */ +#endif + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = { + {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = { + {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */ + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */ + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = { + {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */ + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */ + {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "GPIOH_4", /* BL_EN */ + "GPIOH_5", /* BL_PWM */ + "invalid", /* ending flag */ +}; + +struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = { + {/* B080XAN01*/ + "lcd_0",LCD_MIPI,8, + /* basic timing */ + 768,1024,948,1140,64,56,0,50,30,0, + /* clk_attr */ + 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* TV070WSM*/ + "lcd_1",LCD_MIPI,8, + /* basic timing */ + 600,1024,700,1053,24,36,0,2,8,0, + /* clk_attr */ + 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,360,0,1,0,2,0,0,Rsv_val,1, + /* power step */ + lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* P070ACB*/ + "lcd_2",LCD_MIPI,8, + /* basic timing */ + 600,1024,680,1194,24,36,0,10,80,0, + /* clk_attr */ + 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,400,0,1,0,2,0,0,Rsv_val,2, + /* power step */ + lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* TL050FHV02CT*/ + "lcd_3",LCD_MIPI,8, + /* basic timing */ + 1080,1920,1125,2100,5,30,0,44,108,0, + /* clk_attr */ + 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,960,0,1,0,2,1,0,Rsv_val,3, + /* power step */ + lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* TL070WSH27*/ + "lcd_4",LCD_MIPI,8, + /* basic timing */ + 1024,600,1250,630,80,100,0,5,20,0, + /* clk_attr */ + 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* TV070WSM_FT*/ + "lcd_5",LCD_MIPI,8, + /* basic timing */ + 600,1024,700,1053,24,36,0,2,8,0, + /* clk_attr */ + 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,360,0,1,0,2,0,0,Rsv_val,4, + /* power step */ + lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* P070ACB_FT*/ + "lcd_6",LCD_MIPI,8, + /* basic timing */ + 600,1024,770,1070,10,80,0,6,20,0, + /* clk_attr */ + 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* mipi_attr */ + 4,400,0,1,0,2,0,0,Rsv_val,5, + /* power step */ + lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB, + /* backlight */ + 100,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {.panel_type = "invalid"}, +}; + +static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = { + { + .name = "lcd_pin", + .pinmux_set = {{LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{LCD_PINMUX_END, 0x0}}, + }, + { + .name = "invalid", + }, +}; + +static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = { + { + .name = "bl_pwm_on_pin", //GPIOH_5 + .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}}, + }, + { + .name = "invalid", + }, +}; + +static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100 + 0x05, 1, 0x11, + 0xfd, 1, 20, + 0x05, 1, 0x29, + 0xfd, 1, 20, + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50 + 0x05, 1, 0x28, + 0xfd, 1, 10, + 0x05, 1, 0x10, + 0xfd, 1, 10, + 0xff, 0, //ending +}; + +static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100 + 0xfd, 1, 10, + 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */ + 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */ + 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */ + 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */ + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50 + 0xff, 0, //ending +}; + +static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100 + 0xfd, 1, 10, + 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */ + 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */ + 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */ + 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */ + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50 + 0xff, 0, //ending +}; + +static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100 + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50 + 0xff, 0, //ending +}; + +static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100 + 0x05, 1, 0x11, + 0xfd, 1, 100, + 0x05, 1, 0x29, + 0xfd, 1, 20, + 0xff, 0, //ending +}; +static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50 + 0x05, 1, 0x28, + 0xfd, 1, 100, + 0x05, 1, 0x10, + 0xfd, 1, 10, + 0xff, 0, //ending +}; + +static struct dsi_config_s lcd_mipi_config = { + .lane_num = 4, + .bit_rate_max = 550, /* MHz */ + .factor_numerator = 0, + .factor_denominator = 100, + .operation_mode_init = 1, /* 0=video mode, 1=command mode */ + .operation_mode_display = 0, /* 0=video mode, 1=command mode */ + .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */ + .clk_always_hs = 1, /* 0=disable, 1=enable */ + .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */ + + .dsi_init_on = &mipi_init_on_table[0], + .dsi_init_off = &mipi_init_off_table[0], + .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */ + .check_en = 0, + .check_state = 0, +}; + +static struct lcd_power_ctrl_s lcd_power_ctrl = { + .power_on_step = { + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 10, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 20, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 20, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_SIGNAL, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 0, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, + .power_off_step = { + { + .type = LCD_POWER_TYPE_SIGNAL, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 100, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 100, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, +}; + +struct lcd_config_s lcd_config_dft = { + .lcd_mode = LCD_MODE_TABLET, + .lcd_key_valid = 0, + .lcd_clk_path = 0, + .lcd_basic = { + .model_name = "default", + .lcd_type = LCD_TYPE_MAX, + .lcd_bits = 8, + .h_active = 768, + .v_active = 1024, + .h_period = 948, + .v_period = 1140, + + .screen_width = 119, + .screen_height = 159, + }, + + .lcd_timing = { + .clk_auto = 1, + .lcd_clk = 64843200, + .ss_level = 0, + .fr_adjust_type = 0, + + .hsync_width = 64, + .hsync_bp = 56, + .hsync_pol = 0, + .vsync_width = 50, + .vsync_bp = 30, + .vsync_pol = 0, + }, + + .lcd_control = { + .mipi_config= &lcd_mipi_config, + }, + .lcd_power = &lcd_power_ctrl, + + .pinctrl_ver = 2, + .lcd_pinmux = lcd_pinmux_ctrl, + .pinmux_set = {{LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{LCD_PINMUX_END, 0x0}}, +}; + +#ifdef CONFIG_AML_LCD_EXTERN +static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = { + "invalid", /* ending flag */ +}; + +static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = { + 0xff, 0, //ending flag +}; + +static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = { + 0xff, 0, //ending flag +}; + +struct lcd_extern_common_s ext_common_dft = { + .lcd_ext_key_valid = 0, + .lcd_ext_num = 6, + .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */ + .pinmux_set = {{LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{LCD_PINMUX_END, 0x0}}, +}; + +struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = { + { + .index = 0, + .name = "ext_default", + .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 0, /* 0=disable, 1=enable */ + .i2c_addr = 0x1c, /* 7bit i2c address */ + .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table, + .table_init_on_cnt = sizeof(ext_init_on_table), + .table_init_off = ext_init_off_table, + .table_init_off_cnt = sizeof(ext_init_off_table), + }, + { /* TV070WSM */ + .index = 1, + .name = "mipi_default", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table_TV070WSM, + .table_init_on_cnt = sizeof(ext_init_on_table_TV070WSM), + .table_init_off = ext_init_off_table_TV070WSM, + .table_init_off_cnt = sizeof(ext_init_off_table_TV070WSM), + }, + { /* P070ACB */ + .index = 2, + .name = "mipi_default", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table_P070ACB, + .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB), + .table_init_off = ext_init_off_table_P070ACB, + .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB), + }, + { /* TL050FHV02CT */ + .index = 3, + .name = "mipi_default", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table_TL050FHV02CT, + .table_init_on_cnt = sizeof(ext_init_on_table_TL050FHV02CT), + .table_init_off = ext_init_off_table_TL050FHV02CT, + .table_init_off_cnt = sizeof(ext_init_off_table_TL050FHV02CT), + }, + { /* TV070WSM_FT */ + .index = 4, + .name = "mipi_default", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table_TV070WSM_FT, + .table_init_on_cnt = sizeof(ext_init_on_table_TV070WSM_FT), + .table_init_off = ext_init_off_table_TV070WSM_FT, + .table_init_off_cnt = sizeof(ext_init_off_table_TV070WSM_FT), + }, + { /* P070ACB_FT */ + .index = 5, + .name = "mipi_default", + .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */ + .status = 1, /* 0=disable, 1=enable */ + .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC, + .table_init_on = ext_init_on_table_P070ACB_FT, + .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB_FT), + .table_init_off = ext_init_off_table_P070ACB_FT, + .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB_FT), + }, + { + .index = LCD_EXTERN_INDEX_INVALID, + }, +}; +#endif + +struct bl_config_s bl_config_dft = { + .name = "default", + .bl_key_valid = 0, + + .level_default = 100, + .level_min = 10, + .level_max = 255, + .level_mid = 128, + .level_mid_mapping = 128, + .level = 0, + + .method = BL_CTRL_MAX, + .power_on_delay = 200, + .power_off_delay = 200, + + .en_gpio = 0xff, + .en_gpio_on = 1, + .en_gpio_off = 0, + + .bl_pwm = NULL, + .bl_pwm_combo0 = NULL, + .bl_pwm_combo1 = NULL, + .pwm_on_delay = 10, + .pwm_off_delay = 10, + + .bl_extern_index = 0xff, + + .pinctrl_ver = 2, + .bl_pinmux = bl_pinmux_ctrl, + .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}}, +}; + +#ifdef CONFIG_AML_BL_EXTERN +static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX]; +static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX]; +struct bl_extern_config_s bl_extern_config_dtf = { + .index = BL_EXTERN_INDEX_INVALID, + .name = "none", + .type = BL_EXTERN_MAX, + .i2c_addr = 0xff, + .i2c_bus = BL_EXTERN_I2C_BUS_MAX, + .dim_min = 10, + .dim_max = 255, + + .init_loaded = 0, + .cmd_size = 0xff, + .init_on = bl_ext_init_on, + .init_off = bl_ext_init_off, + .init_on_cnt = sizeof(bl_ext_init_on), + .init_off_cnt = sizeof(bl_ext_init_off), +}; +#endif + +void lcd_config_bsp_init(void) +{ + int i, j; + char *str; + struct ext_lcd_config_s *ext_lcd = NULL; + + str = getenv("panel_type"); + if (str) { + for (i = 0 ; i < LCD_NUM_MAX ; i++) { + ext_lcd = &ext_lcd_config[i]; + if (strcmp(ext_lcd->panel_type, str) == 0) { + switch (i) { + case 1:/* TV070WSM*/ + case 5:/* TV070WSM_FT*/ + lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM; + lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM; + break; + case 2:/* P070ACB*/ + case 6:/* P070ACB_FT*/ + lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB; + lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB; + break; + case 3: + lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL050FHV02CT; + lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL050FHV02CT; + break; + case 4: + lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL070WSH27; + lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL070WSH27; + break; + case 0: + default: + lcd_mipi_config.dsi_init_on = mipi_init_on_table; + lcd_mipi_config.dsi_init_off = mipi_init_off_table; + break; + } + break; + } + } + } + + for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_cpu_gpio[i], "invalid") == 0) + break; + strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]); + } + for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++) + strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid"); + for (i = 0; i < BL_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_bl_gpio[i], "invalid") == 0) + break; + strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]); + } + for (j = i; j < BL_GPIO_NUM_MAX; j++) + strcpy(bl_config_dft.gpio_name[j], "invalid"); + +#ifdef CONFIG_AML_LCD_EXTERN + for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) { + if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID) + break; + } + ext_common_dft.lcd_ext_num = i; + + for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_ext_gpio[i], "invalid") == 0) + break; + strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]); + } + for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++) + strcpy(ext_common_dft.gpio_name[j], "invalid"); + +#endif +} diff --git a/board/amlogic/sm1_sabrina_v1/lcd_extern.h b/board/amlogic/sm1_sabrina_v1/lcd_extern.h new file mode 100755 index 0000000..67f00fc --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/lcd_extern.h @@ -0,0 +1,1392 @@ +/* + * board/amlogic/g12a_u200_v1/lcd_extern.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the named License, + * or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _DFT_LCD_EXTERN_H_ +#define _DFT_LCD_EXTERN_H_ + +static unsigned char ext_init_on_table_TV070WSM[LCD_EXTERN_INIT_ON_MAX] = { + 0xfd, 1, 100, /* delay */ + 0x15, 2, 0x62, 0x01, + 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x01, + 0x15, 2, 0xfc, 0x08, + 0xfd, 1, 1, /* delay */ + 0x15, 2, 0xfc, 0x00, + 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x00, + 0xfd, 1, 20, /* delay */ + 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00, + 0x39, 3, 0xb1, 0x68, 0x41, + 0x15, 2, 0xb5, 0x88, + 0x15, 2, 0xb6, 0x0f, + 0x39, 5, 0xb8, 0x01, 0x01, 0x12, 0x01, + 0x39, 3, 0xbb, 0x11, 0x11, + 0x39, 3, 0xbc, 0x05, 0x05, + 0x15, 2, 0xc7, 0x03, + 0x39, 6, 0xbd, 0x03, 0x02, 0x19, 0x17, 0x00, + 0x15, 2, 0xc8, 0x80, + 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01, + 0x39, 3, 0xB2, 0x01, 0x01, + 0x39, 3, 0xB3, 0x28, 0x28, + 0x39, 3, 0xB4, 0x14, 0x14, + 0x39, 3, 0xB8, 0x05, 0x05, + 0x39, 3, 0xB9, 0x45, 0x45, + 0x39, 3, 0xBA, 0x25, 0x25, + 0x39, 3, 0xBC, 0x88, 0x00, + 0x39, 3, 0xBD, 0x88, 0x00, + 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02, + 0x15, 2, 0xEE, 0x00, + 0x39, 17, 0xB0, 0x00, 0x4B, 0x00, 0x5C, 0x00, 0x79, 0x00, 0x94, 0x00, 0xA6, 0x00, 0xD8, 0x00, 0xF2, 0x01, 0x19, + 0x39, 17, 0xB1, 0x01, 0x39, 0x01, 0x77, 0x01, 0xA2, 0x01, 0xF2, 0x02, 0x32, 0x02, 0x34, 0x02, 0x6D, 0x02, 0xA2, + 0x39, 17, 0xB2, 0x02, 0xC7, 0x02, 0xF2, 0x03, 0x18, 0x03, 0x43, 0x03, 0x65, 0x03, 0x86, 0x03, 0x8F, 0x03, 0x94, + 0x39, 5, 0xB3, 0x03, 0x96, 0x03, 0x98, + 0x39, 17, 0xB4, 0x00, 0x84, 0x00, 0x91, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xCA, 0x00, 0xE9, 0x01, 0x02, 0x01, 0x2A, + 0x39, 17, 0xB5, 0x01, 0x49, 0x01, 0x82, 0x01, 0xAF, 0x01, 0xF7, 0x02, 0x36, 0x02, 0x38, 0x02, 0x70, 0x02, 0xA6, + 0x39, 17, 0xB6, 0x02, 0xC8, 0x02, 0xF5, 0x03, 0x1A, 0x03, 0x43, 0x03, 0x62, 0x03, 0x82, 0x03, 0x8F, 0x03, 0x94, + 0x39, 5, 0xB7, 0x03, 0x96, 0x03, 0x98, + 0x39, 17, 0xB8, 0x01, 0x22, 0x01, 0x27, 0x01, 0x2E, 0x01, 0x38, 0x01, 0x40, 0x01, 0x53, 0x01, 0x60, 0x01, 0x7B, + 0x39, 17, 0xB9, 0x01, 0x8C, 0x01, 0xB5, 0x01, 0xD3, 0x02, 0x11, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x7F, 0x02, 0xB1, + 0x39, 17, 0xBA, 0x02, 0xD1, 0x03, 0x00, 0x03, 0x22, 0x03, 0x49, 0x03, 0x60, 0x03, 0x7A, 0x03, 0x8B, 0x03, 0x8F, + 0x39, 5, 0xBB, 0x03, 0x93, 0x03, 0x9A, + 0x39, 17, 0xBC, 0x00, 0x37, 0x00, 0x48, 0x00, 0x65, 0x00, 0x80, 0x00, 0x92, 0x00, 0xC4, 0x00, 0xDE, 0x01, 0x05, + 0x39, 17, 0xBD, 0x01, 0x31, 0x01, 0x6F, 0x01, 0x9E, 0x01, 0xEE, 0x02, 0x32, 0x02, 0x34, 0x02, 0x71, 0x02, 0xA7, + 0x39, 17, 0xBE, 0x02, 0xD3, 0x02, 0xFE, 0x03, 0x24, 0x03, 0x4F, 0x03, 0x71, 0x03, 0x92, 0x03, 0x9B, 0x03, 0xA0, + 0x39, 5, 0xBF, 0x03, 0xA6, 0x03, 0xA8, + 0x39, 17, 0xC0, 0x00, 0x70, 0x00, 0x7D, 0x00, 0x90, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xD5, 0x00, 0xEE, 0x01, 0x16, + 0x39, 17, 0xC1, 0x01, 0x41, 0x01, 0x7A, 0x01, 0xAB, 0x01, 0xF3, 0x02, 0x36, 0x02, 0x38, 0x02, 0x74, 0x02, 0xAA, + 0x39, 17, 0xC2, 0x02, 0xD4, 0x03, 0x01, 0x03, 0x26, 0x03, 0x4F, 0x03, 0x6E, 0x03, 0x8E, 0x03, 0x9B, 0x03, 0xA0, + 0x39, 5, 0xC3, 0x03, 0xA6, 0x03, 0xA8, + 0x39, 17, 0xC4, 0x01, 0x0E, 0x01, 0x13, 0x01, 0x1A, 0x01, 0x24, 0x01, 0x2C, 0x01, 0x3F, 0x01, 0x4C, 0x01, 0x67, + 0x39, 17, 0xC5, 0x01, 0x84, 0x01, 0xAD, 0x01, 0xCF, 0x02, 0x0D, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x83, 0x02, 0xB5, + 0x39, 17, 0xC6, 0x02, 0xDD, 0x03, 0x0C, 0x03, 0x2E, 0x03, 0x55, 0x03, 0x6B, 0x03, 0x86, 0x03, 0x97, 0x03, 0x9B, + 0x39, 5, 0xC7, 0x03, 0xA1, 0x03, 0xA8, + 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04, + 0x39, 6, 0xB1, 0x03, 0x02, 0x02, 0x02, 0x00, + 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06, + 0x39, 3, 0xB0, 0x11, 0x11, + 0x39, 3, 0xB1, 0x13, 0x13, + 0x39, 3, 0xB2, 0x03, 0x03, + 0x39, 3, 0xB3, 0x34, 0x34, + 0x39, 3, 0xB4, 0x34, 0x34, + 0x39, 3, 0xB5, 0x34, 0x34, + 0x39, 3, 0xB6, 0x34, 0x34, + 0x39, 3, 0xB7, 0x34, 0x34, + 0x39, 3, 0xB8, 0x34, 0x34, + 0x39, 3, 0xB9, 0x34, 0x34, + 0x39, 3, 0xBA, 0x34, 0x34, + 0x39, 3, 0xBB, 0x34, 0x34, + 0x39, 3, 0xBC, 0x34, 0x34, + 0x39, 3, 0xBD, 0x34, 0x34, + 0x39, 3, 0xBE, 0x34, 0x34, + 0x39, 3, 0xBF, 0x34, 0x34, + 0x39, 3, 0xC0, 0x34, 0x34, + 0x39, 3, 0xC1, 0x02, 0x02, + 0x39, 3, 0xC2, 0x12, 0x12, + 0x39, 3, 0xC3, 0x10, 0x10, + 0x39, 3, 0xE5, 0x34, 0x34, + 0x39, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x39, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05, + 0x15, 2, 0xC0, 0x03, + 0x15, 2, 0xC1, 0x02, + 0x39, 3, 0xC8, 0x01, 0x20, + 0x15, 2, 0xE5, 0x03, + 0x15, 2, 0xE6, 0x03, + 0x15, 2, 0xE7, 0x03, + 0x15, 2, 0xE8, 0x03, + 0x15, 2, 0xE9, 0x03, + 0x39, 5, 0xD1, 0x03, 0x00, 0x3D, 0x00, + 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03, + 0x39, 3, 0xB0, 0x11, 0x00, + 0x39, 3, 0xB1, 0x11, 0x00, + 0x39, 6, 0xB2, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x39, 6, 0xB3, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x39, 6, 0xBA, 0x31, 0x00, 0x00, 0x00, 0x00, + 0x15, 2, 0x35, 0x00, + 0x15, 2, 0x51, 0xFF, + 0x15, 2, 0x53, 0x2C, + 0x15, 2, 0x55, 0x03, + 0x05, 1, 0x11, + 0xfd, 1, 120, /* delay 120ms */ + 0x05, 1, 0x29, + 0xff, 0, /* ending flag */ +}; + +static unsigned char ext_init_off_table_TV070WSM[LCD_EXTERN_INIT_OFF_MAX] = { + 0x05, 1, 0x28, /* display off */ + 0xfd, 1, 30, /* delay 30ms */ + 0x05, 1, 0x10, /* sleep in */ + 0xfd, 1, 10, + 0xff, 0, /* ending flag */ +}; + +static unsigned char ext_init_on_table_P070ACB[LCD_EXTERN_INIT_ON_MAX] = { + 0xfd, 1, 100, /* delay */ + 0x15, 2, 0x62, 0x01, + 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01, + 0x23, 2, 0xFC, 0x08, + 0xfd, 1, 1, /* delay(ms) */ + 0x23, 2, 0xFC, 0x00, + + 0xfd, 1, 1, /* delay(ms) */ + 0x23, 2, 0x6F, 0x21, + 0x23, 2, 0xF7, 0x01, + 0xfd, 1, 1, /* delay(ms) */ + 0x23, 2, 0x6F, 0x21, + 0x23, 2, 0xF7, 0x00, + 0xfd, 1, 1, /* delay(ms) */ + + 0x23, 2, 0x6F, 0x1A, + 0x23, 2, 0xF7, 0x05, + 0xfd, 1, 1, /* delay(ms) */ + + 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00, + 0x29, 3, 0xB1, 0x68, 0x41, + 0x23, 2, 0xB5, 0x88, + 0x29, 6, 0xBD, 0x02, 0xB0, 0x0C, 0x14, 0x00, + 0x23, 2, 0xC8, 0x80, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01, + 0x29, 3, 0xB3, 0x2D, 0x2D, + 0x29, 3, 0xB4, 0x19, 0x19, + 0x23, 2, 0xB5, 0x06, + + 0x29, 3, 0xB9, 0x36, 0x36, + 0x29, 3, 0xBA, 0x26, 0x26, + 0x29, 3, 0xBC, 0xA8, 0x01, + 0x29, 3, 0xBD, 0xAB, 0x01, + 0x23, 2, 0xC0, 0x0C, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02, + 0x23, 2, 0xEE, 0x02, + 0x29, 7, 0xB0, 0x00, 0x50, 0x00, 0x52, 0x00, 0x73, + 0x23, 2, 0x6F, 0x06, + 0x29, 7, 0xB0, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA, + 0x23, 2, 0x6F, 0x0C, + 0x29, 5, 0xB0, 0x00, 0xEA, 0x01, 0x1B, + 0x29, 7, 0xB1, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3, + 0x23, 2, 0x6F, 0x06, + 0x29, 7, 0xB1, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42, + 0x23, 2, 0x6F, 0x0C, + 0x29, 5, 0xB1, 0x02, 0x78, 0x02, 0xB5, + 0x29, 7, 0xB2, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A, + 0x23, 2, 0x6F, 0x06, + 0x29, 7, 0xB2, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1, + 0x23, 2, 0x6F, 0x0C, + 0x29, 5, 0xB2, 0x03, 0xCA, 0x03, 0xE8, + 0x29, 5, 0xB3, 0x03, 0xF4, 0x03, 0xFF, + + 0x29, 7, 0xBC, 0x00, 0x05, 0x00, 0x52, 0x00, 0x73, + 0x23, 2, 0x6F, 0x06, + 0x29, 7, 0xBC, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA, + 0x23, 2, 0x6F, 0x0C, + 0x29, 5, 0xBC, 0x00, 0xEA, 0x01, 0x1B, + 0x29, 7, 0xBD, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3, + 0x23, 2, 0x6F, 0x06, + 0x29, 7, 0xBD, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42, + 0x23, 2, 0x6F, 0x0C, + 0x29, 5, 0xBD, 0x02, 0x78, 0x02, 0xB5, + 0x29, 7, 0xBE, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A, + 0x23, 2, 0x6F, 0x06, + 0x29, 7, 0xBE, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1, + 0x23, 2, 0x6F, 0x0C, + 0x29, 5, 0xBE, 0x03, 0xCA, 0x03, 0xE8, + 0x29, 5, 0xBF, 0x03, 0xF4, 0x03, 0xFF, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03, + 0x29, 6, 0xB2, 0x05, 0x00, 0x00, 0x00, 0x00, + 0x29, 6, 0xB6, 0x05, 0x00, 0x00, 0x00, 0x00, + 0x29, 6, 0xB7, 0x05, 0x00, 0x00, 0x00, 0x00, + 0x29, 6, 0xBA, 0x57, 0x00, 0x00, 0x00, 0x00, + 0x29, 6, 0xBB, 0x57, 0x00, 0x00, 0x00, 0x00, + 0x29, 5, 0xC0, 0x00, 0x34, 0x00, 0x00, + 0x29, 5, 0xC1, 0x00, 0x00, 0x34, 0x00, + 0x23, 2, 0xC4, 0x40, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05, + 0x29, 3, 0xB0, 0x17, 0x06, + 0x29, 3, 0xB1, 0x17, 0x06, + 0x29, 3, 0xB2, 0x17, 0x06, + 0x29, 3, 0xB3, 0x17, 0x06, + 0x29, 3, 0xB4, 0x17, 0x06, + + 0x29, 6, 0xBD, 0x03, 0x01, 0x03, 0x03, 0x01, + 0x23, 2, 0xC0, 0x05, + 0x23, 2, 0xC4, 0x82, + 0x23, 2, 0xC5, 0xA2, + 0x29, 3, 0xC8, 0x03, 0x30, + 0x29, 3, 0xC9, 0x03, 0x31, + 0x29, 4, 0xCC, 0x00, 0x00, 0x3C, + 0x29, 4, 0xCD, 0x00, 0x00, 0x3C, + 0x29, 6, 0xD1, 0x00, 0x44, 0x09, 0x00, 0x00, + 0x29, 6, 0xD2, 0x00, 0x04, 0x0B, 0x00, 0x00, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06, + 0x29, 3, 0xB0, 0x0B, 0x2D, + 0x29, 3, 0xB1, 0x2D, 0x09, + 0x29, 3, 0xB2, 0x2A, 0x29, + 0x29, 3, 0xB3, 0x34, 0x1B, + 0x29, 3, 0xB4, 0x19, 0x17, + 0x29, 3, 0xB5, 0x15, 0x13, + 0x29, 3, 0xB6, 0x11, 0x01, + 0x29, 3, 0xB7, 0x34, 0x34, + 0x29, 3, 0xB8, 0x34, 0x2D, + 0x29, 3, 0xB9, 0x2D, 0x34, + 0x29, 3, 0xBA, 0x2D, 0x2D, + 0x29, 3, 0xBB, 0x34, 0x34, + 0x29, 3, 0xBC, 0x34, 0x34, + 0x29, 3, 0xBD, 0x00, 0x10, + 0x29, 3, 0xBE, 0x12, 0x14, + 0x29, 3, 0xBF, 0x16, 0x18, + + 0x29, 3, 0xC0, 0x1A, 0x34, + 0x29, 3, 0xC1, 0x29, 0x2A, + 0x29, 3, 0xC2, 0x08, 0x2D, + 0x29, 3, 0xC3, 0x2D, 0x0A, + 0x29, 3, 0xC4, 0x0A, 0x2D, + 0x29, 3, 0xC5, 0x2D, 0x00, + 0x29, 3, 0xC6, 0x2A, 0x29, + 0x29, 3, 0xC7, 0x34, 0x14, + 0x29, 3, 0xC8, 0x16, 0x18, + 0x29, 3, 0xC9, 0x1A, 0x10, + 0x29, 3, 0xCA, 0x12, 0x08, + 0x29, 3, 0xCB, 0x34, 0x34, + 0x29, 3, 0xCC, 0x34, 0x2D, + 0x29, 3, 0xCD, 0x2D, 0x34, + 0x29, 3, 0xCE, 0x2D, 0x2D, + 0x29, 3, 0xCF, 0x34, 0x34, + + 0x29, 3, 0xD0, 0x34, 0x34, + 0x29, 3, 0xD1, 0x09, 0x13, + 0x29, 3, 0xD2, 0x11, 0x1B, + 0x29, 3, 0xD3, 0x19, 0x17, + 0x29, 3, 0xD4, 0x15, 0x34, + 0x29, 3, 0xD5, 0x29, 0x2A, + 0x29, 3, 0xD6, 0x01, 0x2D, + 0x29, 3, 0xD7, 0x2D, 0x0B, + 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x29, 3, 0xE5, 0x34, 0x34, + 0x29, 3, 0xE6, 0x34, 0x34, + 0x23, 2, 0xE7, 0x00, + 0x29, 3, 0xE8, 0x34, 0x34, + 0x29, 3, 0xE9, 0x34, 0x34, + 0x23, 2, 0xEA, 0x00, + + 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00, + + 0x13, 1, 0x35, + 0x13, 1, 0x11, + 0xfd, 1, 120, /* delay(ms) */ + 0x13, 1, 0x29, + 0xfd, 1, 20, /* delay(ms) */ + 0xFF, 0, /* ending flag */ +}; + +static unsigned char ext_init_off_table_P070ACB[LCD_EXTERN_INIT_OFF_MAX] = { + 0x05, 1, 0x28, /* display off */ + 0xfd, 1, 10, /* delay 10ms */ + 0x05, 1, 0x10, /* sleep in */ + 0xfd, 1, 150, /* delay 150ms */ + 0xFF, 0, /* ending flag */ +}; + +static unsigned char ext_init_on_table_TV070WSM_FT[LCD_EXTERN_INIT_ON_MAX] = { + 0x23,2,0xE0,0x00, + 0x23,2,0xE1,0x93, + 0x23,2,0xE2,0x65, + 0x23,2,0xE3,0xF8, + 0x23,2,0xE0,0x01, + 0x23,2,0x00,0x00, + 0x23,2,0x01,0x90, + 0x23,2,0x03,0x00, + 0x23,2,0x04,0x90, + 0x23,2,0x17,0x00, + 0x23,2,0x18,0xB0, + 0x23,2,0x19,0x01, + 0x23,2,0x1A,0x00, + 0x23,2,0x1B,0xB0, + 0x23,2,0x1C,0x01, + 0x23,2,0x1F,0x3E, + 0x23,2,0x20,0x2F, + 0x23,2,0x21,0x2F, + 0x23,2,0x22,0x0E, + 0x23,2,0x37,0x69, + 0x23,2,0x38,0x05, + 0x23,2,0x39,0x00, + 0x23,2,0x3A,0x01, + 0x23,2,0x3C,0x90, + 0x23,2,0x3D,0xFF, + 0x23,2,0x3E,0xFF, + 0x23,2,0x3F,0xFF, + 0x23,2,0x40,0x02, + 0x23,2,0x41,0x80, + 0x23,2,0x42,0x99, + 0x23,2,0x43,0x06, + 0x23,2,0x44,0x09, + 0x23,2,0x45,0x3C, + 0x23,2,0x4B,0x04, + 0x23,2,0x55,0x0F, + 0x23,2,0x56,0x01, + 0x23,2,0x57,0x89, + 0x23,2,0x58,0x0A, + 0x23,2,0x59,0x0A, + 0x23,2,0x5A,0x27, + 0x23,2,0x5B,0x15, + 0x23,2,0x5D,0x7C, + 0x23,2,0x5E,0x67, + 0x23,2,0x5F,0x58, + 0x23,2,0x60,0x4C, + 0x23,2,0x61,0x48, + 0x23,2,0x62,0x38, + 0x23,2,0x63,0x3C, + 0x23,2,0x64,0x24, + 0x23,2,0x65,0x3B, + 0x23,2,0x66,0x38, + 0x23,2,0x67,0x36, + 0x23,2,0x68,0x53, + 0x23,2,0x69,0x3F, + 0x23,2,0x6A,0x44, + 0x23,2,0x6B,0x35, + 0x23,2,0x6C,0x2E, + 0x23,2,0x6D,0x1F, + 0x23,2,0x6E,0x0C, + 0x23,2,0x6F,0x00, + 0x23,2,0x70,0x7C, + 0x23,2,0x71,0x67, + 0x23,2,0x72,0x58, + 0x23,2,0x73,0x4C, + 0x23,2,0x74,0x48, + 0x23,2,0x75,0x38, + 0x23,2,0x76,0x3C, + 0x23,2,0x77,0x24, + 0x23,2,0x78,0x3B, + 0x23,2,0x79,0x38, + 0x23,2,0x7A,0x36, + 0x23,2,0x7B,0x53, + 0x23,2,0x7C,0x3F, + 0x23,2,0x7D,0x44, + 0x23,2,0x7E,0x35, + 0x23,2,0x7F,0x2E, + 0x23,2,0x80,0x1F, + 0x23,2,0x81,0x0C, + 0x23,2,0x82,0x00, + 0x23,2,0xE0,0x02, + 0x23,2,0x00,0x45, + 0x23,2,0x01,0x45, + 0x23,2,0x02,0x47, + 0x23,2,0x03,0x47, + 0x23,2,0x04,0x41, + 0x23,2,0x05,0x41, + 0x23,2,0x06,0x1F, + 0x23,2,0x07,0x1F, + 0x23,2,0x08,0x1F, + 0x23,2,0x09,0x1F, + 0x23,2,0x0A,0x1F, + 0x23,2,0x0B,0x1F, + 0x23,2,0x0C,0x1F, + 0x23,2,0x0D,0x1D, + 0x23,2,0x0E,0x1D, + 0x23,2,0x0F,0x1D, + 0x23,2,0x10,0x1F, + 0x23,2,0x11,0x1F, + 0x23,2,0x12,0x1F, + 0x23,2,0x13,0x1F, + 0x23,2,0x14,0x1F, + 0x23,2,0x15,0x1F, + 0x23,2,0x16,0x44, + 0x23,2,0x17,0x44, + 0x23,2,0x18,0x46, + 0x23,2,0x19,0x46, + 0x23,2,0x1A,0x40, + 0x23,2,0x1B,0x40, + 0x23,2,0x1C,0x1F, + 0x23,2,0x1D,0x1F, + 0x23,2,0x1E,0x1F, + 0x23,2,0x1F,0x1F, + 0x23,2,0x20,0x1F, + 0x23,2,0x21,0x1F, + 0x23,2,0x22,0x1F, + 0x23,2,0x23,0x1D, + 0x23,2,0x24,0x1D, + 0x23,2,0x25,0x1D, + 0x23,2,0x26,0x1F, + 0x23,2,0x27,0x1F, + 0x23,2,0x28,0x1F, + 0x23,2,0x29,0x1F, + 0x23,2,0x2A,0x1F, + 0x23,2,0x2B,0x1F, + 0x23,2,0x58,0x40, + 0x23,2,0x59,0x00, + 0x23,2,0x5A,0x00, + 0x23,2,0x5B,0x10, + 0x23,2,0x5C,0x06, + 0x23,2,0x5D,0x20, + 0x23,2,0x5E,0x00, + 0x23,2,0x5F,0x00, + 0x23,2,0x61,0x00, + 0x23,2,0x62,0x00, + 0x23,2,0x63,0x7A, + 0x23,2,0x64,0x7A, + 0x23,2,0x65,0x00, + 0x23,2,0x66,0x00, + 0x23,2,0x67,0x32, + 0x23,2,0x68,0x08, + 0x23,2,0x69,0x7A, + 0x23,2,0x6A,0x7A, + 0x23,2,0x6B,0x00, + 0x23,2,0x6C,0x00, + 0x23,2,0x6D,0x04, + 0x23,2,0x6E,0x04, + 0x23,2,0x6F,0x88, + 0x23,2,0x70,0x00, + 0x23,2,0x71,0x00, + 0x23,2,0x72,0x06, + 0x23,2,0x73,0x7B, + 0x23,2,0x74,0x00, + 0x23,2,0x75,0x07, + 0x23,2,0x76,0x00, + 0x23,2,0x77,0x5D, + 0x23,2,0x78,0x17, + 0x23,2,0x79,0x1F, + 0x23,2,0x7A,0x00, + 0x23,2,0x7B,0x00, + 0x23,2,0x7C,0x00, + 0x23,2,0x7D,0x03, + 0x23,2,0x7E,0x7B, + 0x23,2,0xE0,0x03, + 0x23,2,0xAF,0x20, + 0x23,2,0xE0,0x04, + 0x23,2,0x09,0x11, + 0x23,2,0x0E,0x48, + 0x23,2,0x2B,0x2B, + 0x23,2,0x2E,0x44, + 0x23,2,0x41,0xFF, + 0x23,2,0xE0,0x00, + 0x23,2,0xE6,0x02, + 0x23,2,0xE7,0x0C, + 0x05,1,0x11, + 0xfd, 1,120,/* delay 120ms */ + + 0x23,2,0xE0,0x03, + 0x23,2,0x2B,0x01, + 0x23,2,0x2C,0x00, + 0x23,2,0x30,0x03, + 0x23,2,0x31,0xCC, + 0x23,2,0x32,0x03, + 0x23,2,0x33,0xC9, + 0x23,2,0x34,0x03, + 0x23,2,0x35,0xC0, + 0x23,2,0x36,0x03, + 0x23,2,0x37,0xB3, + 0x23,2,0x38,0x03, + 0x23,2,0x39,0xAB, + 0x23,2,0x3A,0x03, + 0x23,2,0x3B,0x9D, + 0x23,2,0x3C,0x03, + 0x23,2,0x3D,0x8F, + 0x23,2,0x3E,0x03, + 0x23,2,0x3F,0x6D, + 0x23,2,0x40,0x03, + 0x23,2,0x41,0x51, + 0x23,2,0x42,0x03, + 0x23,2,0x43,0x17, + 0x23,2,0x44,0x02, + 0x23,2,0x45,0xD8, + 0x23,2,0x46,0x02, + 0x23,2,0x47,0x60, + 0x23,2,0x48,0x01, + 0x23,2,0x49,0xEB, + 0x23,2,0x4A,0x01, + 0x23,2,0x4B,0xE5, + 0x23,2,0x4C,0x01, + 0x23,2,0x4D,0x6C, + 0x23,2,0x4E,0x00, + 0x23,2,0x4F,0xF2, + 0x23,2,0x50,0x00, + 0x23,2,0x51,0xB4, + 0x23,2,0x52,0x00, + 0x23,2,0x53,0x74, + 0x23,2,0x54,0x00, + 0x23,2,0x55,0x54, + 0x23,2,0x56,0x00, + 0x23,2,0x57,0x34, + 0x23,2,0x58,0x00, + 0x23,2,0x59,0x26, + 0x23,2,0x5A,0x00, + 0x23,2,0x5B,0x18, + 0x23,2,0x5C,0x00, + 0x23,2,0x5D,0x11, + 0x23,2,0x5E,0x00, + 0x23,2,0x5F,0x0A, + 0x23,2,0x60,0x00, + 0x23,2,0x61,0x03, + 0x23,2,0x62,0x00, + 0x23,2,0x63,0x00, + 0x23,2,0x64,0x03, + 0x23,2,0x65,0x9E, + 0x23,2,0x66,0x03, + 0x23,2,0x67,0x9B, + 0x23,2,0x68,0x03, + 0x23,2,0x69,0x94, + 0x23,2,0x6A,0x03, + 0x23,2,0x6B,0x8C, + 0x23,2,0x6C,0x03, + 0x23,2,0x6D,0x85, + 0x23,2,0x6E,0x03, + 0x23,2,0x6F,0x76, + 0x23,2,0x70,0x03, + 0x23,2,0x71,0x67, + 0x23,2,0x72,0x03, + 0x23,2,0x73,0x4B, + 0x23,2,0x74,0x03, + 0x23,2,0x75,0x2E, + 0x23,2,0x76,0x02, + 0x23,2,0x77,0xF7, + 0x23,2,0x78,0x02, + 0x23,2,0x79,0xB8, + 0x23,2,0x7A,0x02, + 0x23,2,0x7B,0x46, + 0x23,2,0x7C,0x01, + 0x23,2,0x7D,0xD6, + 0x23,2,0x7E,0x01, + 0x23,2,0x7F,0xD0, + 0x23,2,0x80,0x01, + 0x23,2,0x81,0x5C, + 0x23,2,0x82,0x00, + 0x23,2,0x83,0xE7, + 0x23,2,0x84,0x00, + 0x23,2,0x85,0xAA, + 0x23,2,0x86,0x00, + 0x23,2,0x87,0x74, + 0x23,2,0x88,0x00, + 0x23,2,0x89,0x5A, + 0x23,2,0x8A,0x00, + 0x23,2,0x8B,0x3C, + 0x23,2,0x8C,0x00, + 0x23,2,0x8D,0x2C, + 0x23,2,0x8E,0x00, + 0x23,2,0x8F,0x1C, + 0x23,2,0x90,0x00, + 0x23,2,0x91,0x14, + 0x23,2,0x92,0x00, + 0x23,2,0x93,0x0C, + 0x23,2,0x94,0x00, + 0x23,2,0x95,0x04, + 0x23,2,0x96,0x00, + 0x23,2,0x97,0x00, + 0x23,2,0xE0,0x00, + 0x05,1,0x29, + 0xfd, 1,5, + 0xff, 0, /* ending flag */ +}; + +static unsigned char ext_init_off_table_TV070WSM_FT[LCD_EXTERN_INIT_OFF_MAX] = { + 0x05, 1, 0x28, /* display off */ + 0xfd, 1, 30, /* delay 30ms */ + 0x05, 1, 0x10, /* sleep in */ + 0xfd, 1, 10, + 0xff, 0, /* ending flag */ +}; + +static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = { + 0x23,2,0xE0,0x00,//Page 0 + 0x23,2,0xE1,0x93,// PASSWORD + 0x23,2,0xE2,0x65, + 0x23,2,0xE3,0xF8, + 0x23,2,0x80,0x03, + 0x23,2,0xE0,0x01,//Page 01 + 0x23,2,0x0C,0x74,//Set PWRIC + 0x23,2,0x17,0x00,//Set Gamma Power + 0x23,2,0x18,0xEF,//VGMP=5.1V + 0x23,2,0x19,0x00, + 0x23,2,0x1A,0x00, + 0x23,2,0x1B,0xEF,//VGMN=-5.1V + 0x23,2,0x1C,0x00, + 0x23,2,0x1F,0x70,//Set Gate Power + 0x23,2,0x20,0x2D, + 0x23,2,0x21,0x2D, + 0x23,2,0x22,0x7E, + 0x23,2,0x26,0xF3,//VDDD from IOVCC + 0x23,2,0x37,0x09,//SetPanel + 0x23,2,0x38,0x04,//SET RGBCYC + 0x23,2,0x39,0x00, + 0x23,2,0x3A,0x01, + 0x23,2,0x3C,0x90, + 0x23,2,0x3D,0xFF, + 0x23,2,0x3E,0xFF, + 0x23,2,0x3F,0xFF, + 0x23,2,0x40,0x02,//Set TCON + 0x23,2,0x41,0x80, + 0x23,2,0x42,0x99, + 0x23,2,0x43,0x14, + 0x23,2,0x44,0x19, + 0x23,2,0x45,0x5A, + 0x23,2,0x4B,0x04, + 0x23,2,0x55,0x02,//power voltage + 0x23,2,0x56,0x01, + 0x23,2,0x57,0x69, + 0x23,2,0x58,0x0A, + 0x23,2,0x59,0x0A, + 0x23,2,0x5A,0x2E,//VGH = 16.2V + 0x23,2,0x5B,0x19,//VGL = -12V + 0x23,2,0x5C,0x15, + 0x23,2,0x5D,0x77,//Gamma + 0x23,2,0x5E,0x56, + 0x23,2,0x5F,0x45, + 0x23,2,0x60,0x38, + 0x23,2,0x61,0x35, + 0x23,2,0x62,0x27, + 0x23,2,0x63,0x2D, + 0x23,2,0x64,0x18, + 0x23,2,0x65,0x33, + 0x23,2,0x66,0x34, + 0x23,2,0x67,0x35, + 0x23,2,0x68,0x56, + 0x23,2,0x69,0x45, + 0x23,2,0x6A,0x4F, + 0x23,2,0x6B,0x42, + 0x23,2,0x6C,0x40, + 0x23,2,0x6D,0x34, + 0x23,2,0x6E,0x25, + 0x23,2,0x6F,0x02, + 0x23,2,0x70,0x77, + 0x23,2,0x71,0x56, + 0x23,2,0x72,0x45, + 0x23,2,0x73,0x38, + 0x23,2,0x74,0x35, + 0x23,2,0x75,0x27, + 0x23,2,0x76,0x2D, + 0x23,2,0x77,0x18, + 0x23,2,0x78,0x33, + 0x23,2,0x79,0x34, + 0x23,2,0x7A,0x35, + 0x23,2,0x7B,0x56, + 0x23,2,0x7C,0x45, + 0x23,2,0x7D,0x4F, + 0x23,2,0x7E,0x42, + 0x23,2,0x7F,0x40, + 0x23,2,0x80,0x34, + 0x23,2,0x81,0x25, + 0x23,2,0x82,0x02, + 0x23,2,0xE0,0x02,//Page2 + 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN + 0x23,2,0x01,0x55,//VSSG_EVEN + 0x23,2,0x02,0x55,//VSSA_EVEN + 0x23,2,0x03,0x51,//STV2_EVEN + 0x23,2,0x04,0x77,//VDD2_EVEN + 0x23,2,0x05,0x57,//VDD1_EVEN + 0x23,2,0x06,0x1F, + 0x23,2,0x07,0x4F, //CK12 + 0x23,2,0x08,0x4D, //CK10 + 0x23,2,0x09,0x1F, + 0x23,2,0x0A,0x4B, //CK8 + 0x23,2,0x0B,0x49, //CK6 + 0x23,2,0x0C,0x1F, + 0x23,2,0x0D,0x47, //CK4 + 0x23,2,0x0E,0x45, //CK2 + 0x23,2,0x0F,0x41, //STV1_EVEN + 0x23,2,0x10,0x1F, + 0x23,2,0x11,0x1F, + 0x23,2,0x12,0x1F, + 0x23,2,0x13,0x55, //VGG + 0x23,2,0x14,0x1F, + 0x23,2,0x15,0x1F, + 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD + 0x23,2,0x17,0x55, //VSSG_ODD + 0x23,2,0x18,0x55, //VSSA_ODD + 0x23,2,0x19,0x50, //STV2_ODD + 0x23,2,0x1A,0x77,//VDD2_ODD + 0x23,2,0x1B,0x57,//VDD1_ODD + 0x23,2,0x1C,0x1F, + 0x23,2,0x1D,0x4E, //CK11 + 0x23,2,0x1E,0x4C, //CK9 + 0x23,2,0x1F,0x1F, + 0x23,2,0x20,0x4A, //CK7 + 0x23,2,0x21,0x48, //CK5 + 0x23,2,0x22,0x1F, + 0x23,2,0x23,0x46, //CK3 + 0x23,2,0x24,0x44, //CK1 + 0x23,2,0x25,0x40,//STV1_ODD + 0x23,2,0x26,0x1F, + 0x23,2,0x27,0x1F, + 0x23,2,0x28,0x1F, + 0x23,2,0x29,0x1F, + 0x23,2,0x2A,0x1F, + 0x23,2,0x2B,0x55, //VGG + 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping + 0x23,2,0x2D,0x15, + 0x23,2,0x2E,0x15, + 0x23,2,0x2F,0x00, + 0x23,2,0x30,0x37, + 0x23,2,0x31,0x17, + 0x23,2,0x32,0x1F, + 0x23,2,0x33,0x08, + 0x23,2,0x34,0x0A, + 0x23,2,0x35,0x1F, + 0x23,2,0x36,0x0C, + 0x23,2,0x37,0x0E, + 0x23,2,0x38,0x1F, + 0x23,2,0x39,0x04, + 0x23,2,0x3A,0x06, + 0x23,2,0x3B,0x10, + 0x23,2,0x3C,0x1F, + 0x23,2,0x3D,0x1F, + 0x23,2,0x3E,0x1F, + 0x23,2,0x3F,0x15, + 0x23,2,0x40,0x1F, + 0x23,2,0x41,0x1F, + 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping + 0x23,2,0x43,0x15, + 0x23,2,0x44,0x15, + 0x23,2,0x45,0x01, + 0x23,2,0x46,0x37, + 0x23,2,0x47,0x17, + 0x23,2,0x48,0x1F, + 0x23,2,0x49,0x09, + 0x23,2,0x4A,0x0B, + 0x23,2,0x4B,0x1F, + 0x23,2,0x4C,0x0D, + 0x23,2,0x4D,0x0F, + 0x23,2,0x4E,0x1F, + 0x23,2,0x4F,0x05, + 0x23,2,0x50,0x07, + 0x23,2,0x51,0x11, + 0x23,2,0x52,0x1F, + 0x23,2,0x53,0x1F, + 0x23,2,0x54,0x1F, + 0x23,2,0x55,0x1F, + 0x23,2,0x56,0x1F, + 0x23,2,0x57,0x15, + 0x23,2,0x58,0x40,//GIP Timing + 0x23,2,0x59,0x00, + 0x23,2,0x5A,0x00, + 0x23,2,0x5B,0x10, + 0x23,2,0x5C,0x14, + 0x23,2,0x5D,0x40, + 0x23,2,0x5E,0x01, + 0x23,2,0x5F,0x02, + 0x23,2,0x60,0x40, + 0x23,2,0x61,0x03, + 0x23,2,0x62,0x04, + 0x23,2,0x63,0x7A, + 0x23,2,0x64,0x7A, + 0x23,2,0x65,0x74, + 0x23,2,0x66,0x16, + 0x23,2,0x67,0xB4, + 0x23,2,0x68,0x16, + 0x23,2,0x69,0x7A, + 0x23,2,0x6A,0x7A, + 0x23,2,0x6B,0x0C, + 0x23,2,0x6C,0x00, + 0x23,2,0x6D,0x04, + 0x23,2,0x6E,0x04, + 0x23,2,0x6F,0x88, + 0x23,2,0x70,0x00, + 0x23,2,0x71,0x00, + 0x23,2,0x72,0x06, + 0x23,2,0x73,0x7B, + 0x23,2,0x74,0x00, + 0x23,2,0x75,0xBC, + 0x23,2,0x76,0x00, + 0x23,2,0x77,0x04, + 0x23,2,0x78,0x2C, + 0x23,2,0x79,0x00, + 0x23,2,0x7A,0x00, + 0x23,2,0x7B,0x00, + 0x23,2,0x7C,0x00, + 0x23,2,0x7D,0x03, + 0x23,2,0x7E,0x7B, + 0x23,2,0xE0,0x04,//Page4 + 0x23,2,0x09,0x11,//Set RGBCYC2 + 0x23,2,0x0E,0x48, + 0x23,2,0x2B,0x2B,//ESD Protect + 0x23,2,0x2E,0x44, + 0x23,2,0xE0,0x00,//Page0 + 0x23,2,0xE6,0x02,//Watch dog + 0x23,2,0xE7,0x0C, + 0x05,1,0x11,//sleep out + 0xfd, 1,120, + 0x05,1,0x29,//display on + 0x05,1,0x35, + 0xfd, 1, 20, /* delay(ms) */ + 0xFF, 0, /* ending flag */ +}; + +static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = { + 0x05, 1, 0x28, /* display off */ + 0xfd, 1, 10, /* delay 10ms */ + 0x05, 1, 0x10, /* sleep in */ + 0xfd, 1, 150, /* delay 150ms */ + 0xFF, 0, /* ending flag */ +}; + +static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = { + //LCD driver initialization + 0x23, 2, 0XFF, 0X05, + 0x23, 2, 0XFB, 0X01, + 0x23, 2, 0XC5, 0X01, //TURN ON + 0xfd, 1, 100, + + //AUO4.97+NT35596_intial + 0x23, 2, 0XFF, 0XEE, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0X1F, 0X45, + 0x23, 2, 0X24, 0X4F, + 0x23, 2, 0X38, 0XC8, + 0x23, 2, 0X39, 0X2C, + 0x23, 2, 0X1E, 0XBB, + 0x23, 2, 0X1D, 0X0F, + 0x23, 2, 0X7E, 0XB1, + + 0x23, 2, 0XFF, 0X00, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0X35, 0X01, + + 0x23, 2, 0XFF, 0X01, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0X00, 0X01, + 0x23, 2, 0X01, 0X55, + 0x23, 2, 0X02, 0X40, + 0x23, 2, 0X05, 0X40, + 0x23, 2, 0X06, 0X4A, + 0x23, 2, 0X07, 0X24, + 0x23, 2, 0X08, 0X0C, + 0x23, 2, 0X0B, 0X87, + 0x23, 2, 0X0C, 0X87, + 0x23, 2, 0X0E, 0XB0, + 0x23, 2, 0X0F, 0XB3, + 0x23, 2, 0X11, 0X10, + 0x23, 2, 0X12, 0X10, + 0x23, 2, 0X13, 0X05, + 0x23, 2, 0X14, 0X4A, + 0x23, 2, 0X15, 0X18, + 0x23, 2, 0X16, 0X18, + 0x23, 2, 0X18, 0X00, + 0x23, 2, 0X19, 0X77, + 0x23, 2, 0X1A, 0X55, + 0x23, 2, 0X1B, 0X13, + 0x23, 2, 0X1C, 0X00, + 0x23, 2, 0X1D, 0X00, + 0x23, 2, 0X1E, 0X13, + 0x23, 2, 0X1F, 0X00, + 0x23, 2, 0X23, 0X00, + 0x23, 2, 0X24, 0X00, + 0x23, 2, 0X25, 0X00, + 0x23, 2, 0X26, 0X00, + 0x23, 2, 0X27, 0X00, + 0x23, 2, 0X28, 0X00, + 0x23, 2, 0X35, 0X00, + 0x23, 2, 0X66, 0X00, + 0x23, 2, 0X58, 0X82, + 0x23, 2, 0X59, 0X02, + 0x23, 2, 0X5A, 0X02, + 0x23, 2, 0X5B, 0X02, + 0x23, 2, 0X5C, 0X82, + 0x23, 2, 0X5D, 0X82, + 0x23, 2, 0X5E, 0X02, + 0x23, 2, 0X5F, 0X02, + 0x23, 2, 0X72, 0X31, + + 0x23, 2, 0XFF, 0X05, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0X00, 0X01, + 0x23, 2, 0X01, 0X0B, + 0x23, 2, 0X02, 0X0C, + 0x23, 2, 0X03, 0X09, + 0x23, 2, 0X04, 0X0A, + 0x23, 2, 0X05, 0X00, + 0x23, 2, 0X06, 0X0F, + 0x23, 2, 0X07, 0X10, + 0x23, 2, 0X08, 0X00, + 0x23, 2, 0X09, 0X00, + 0x23, 2, 0X0A, 0X00, + 0x23, 2, 0X0B, 0X00, + 0x23, 2, 0X0C, 0X00, + 0x23, 2, 0X0D, 0X13, + 0x23, 2, 0X0E, 0X15, + 0x23, 2, 0X0F, 0X17, + 0x23, 2, 0X10, 0X01, + 0x23, 2, 0X11, 0X0B, + 0x23, 2, 0X12, 0X0C, + 0x23, 2, 0X13, 0X09, + 0x23, 2, 0X14, 0X0A, + 0x23, 2, 0X15, 0X00, + 0x23, 2, 0X16, 0X0F, + 0x23, 2, 0X17, 0X10, + 0x23, 2, 0X18, 0X00, + 0x23, 2, 0X19, 0X00, + 0x23, 2, 0X1A, 0X00, + 0x23, 2, 0X1B, 0X00, + 0x23, 2, 0X1C, 0X00, + 0x23, 2, 0X1D, 0X13, + 0x23, 2, 0X1E, 0X15, + 0x23, 2, 0X1F, 0X17, + 0x23, 2, 0X20, 0X00, + 0x23, 2, 0X21, 0X03, + 0x23, 2, 0X22, 0X01, + 0x23, 2, 0X23, 0X40, + 0x23, 2, 0X24, 0X40, + 0x23, 2, 0X25, 0XED, + 0x23, 2, 0X29, 0X58, + 0x23, 2, 0X2A, 0X12, + 0x23, 2, 0X2B, 0X01, + 0x23, 2, 0X4B, 0X06, + 0x23, 2, 0X4C, 0X11, + 0x23, 2, 0X4D, 0X20, + 0x23, 2, 0X4E, 0X02, + 0x23, 2, 0X4F, 0X02, + 0x23, 2, 0X50, 0X20, + 0x23, 2, 0X51, 0X61, + 0x23, 2, 0X52, 0X01, + 0x23, 2, 0X53, 0X63, + 0x23, 2, 0X54, 0X77, + 0x23, 2, 0X55, 0XED, + 0x23, 2, 0X5B, 0X00, + 0x23, 2, 0X5C, 0X00, + 0x23, 2, 0X5D, 0X00, + 0x23, 2, 0X5E, 0X00, + 0x23, 2, 0X5F, 0X15, + 0x23, 2, 0X60, 0X75, + 0x23, 2, 0X61, 0X00, + 0x23, 2, 0X62, 0X00, + 0x23, 2, 0X63, 0X00, + 0x23, 2, 0X64, 0X00, + 0x23, 2, 0X65, 0X00, + 0x23, 2, 0X66, 0X00, + 0x23, 2, 0X67, 0X00, + 0x23, 2, 0X68, 0X04, + 0x23, 2, 0X69, 0X00, + 0x23, 2, 0X6A, 0X00, + 0x23, 2, 0X6C, 0X40, + 0x23, 2, 0X75, 0X01, + 0x23, 2, 0X76, 0X01, + 0x23, 2, 0X7A, 0X80, + 0x23, 2, 0X7B, 0XC5, + 0x23, 2, 0X7C, 0XD8, + 0x23, 2, 0X7D, 0X60, + 0x23, 2, 0X7F, 0X15, + 0x23, 2, 0X80, 0X81, + 0x23, 2, 0X83, 0X05, + 0x23, 2, 0X93, 0X08, + 0x23, 2, 0X94, 0X10, + 0x23, 2, 0X8A, 0X00, + 0x23, 2, 0X9B, 0X0F, + 0x23, 2, 0XEA, 0XFF, + 0x23, 2, 0XEC, 0X00, + + 0x23, 2, 0XFF, 0X01, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0X75, 0X00, //Gamma R+ + 0x23, 2, 0X76, 0X18, + 0x23, 2, 0X77, 0X00, + 0x23, 2, 0X78, 0X38, + 0x23, 2, 0X79, 0X00, + 0x23, 2, 0X7A, 0X65, + 0x23, 2, 0X7B, 0X00, + 0x23, 2, 0X7C, 0X84, + 0x23, 2, 0X7D, 0X00, + 0x23, 2, 0X7E, 0X9B, + 0x23, 2, 0X7F, 0X00, + 0x23, 2, 0X80, 0XAF, + 0x23, 2, 0X81, 0X00, + 0x23, 2, 0X82, 0XC1, + 0x23, 2, 0X83, 0X00, + 0x23, 2, 0X84, 0XD2, + 0x23, 2, 0X85, 0X00, + 0x23, 2, 0X86, 0XDF, + 0x23, 2, 0X87, 0X01, + 0x23, 2, 0X88, 0X11, + 0x23, 2, 0X89, 0X01, + 0x23, 2, 0X8A, 0X38, + 0x23, 2, 0X8B, 0X01, + 0x23, 2, 0X8C, 0X76, + 0x23, 2, 0X8D, 0X01, + 0x23, 2, 0X8E, 0XA7, + 0x23, 2, 0X8F, 0X01, + 0x23, 2, 0X90, 0XF3, + 0x23, 2, 0X91, 0X02, + 0x23, 2, 0X92, 0X2F, + 0x23, 2, 0X93, 0X02, + 0x23, 2, 0X94, 0X30, + 0x23, 2, 0X95, 0X02, + 0x23, 2, 0X96, 0X66, + 0x23, 2, 0X97, 0X02, + 0x23, 2, 0X98, 0XA0, + 0x23, 2, 0X99, 0X02, + 0x23, 2, 0X9A, 0XC5, + 0x23, 2, 0X9B, 0X02, + 0x23, 2, 0X9C, 0XF8, + 0x23, 2, 0X9D, 0X03, + 0x23, 2, 0X9E, 0X1B, + 0x23, 2, 0X9F, 0X03, + 0x23, 2, 0XA0, 0X46, + 0x23, 2, 0XA2, 0X03, + 0x23, 2, 0XA3, 0X52, + 0x23, 2, 0XA4, 0X03, + 0x23, 2, 0XA5, 0X62, + 0x23, 2, 0XA6, 0X03, + 0x23, 2, 0XA7, 0X71, + 0x23, 2, 0XA9, 0X03, + 0x23, 2, 0XAA, 0X83, + 0x23, 2, 0XAB, 0X03, + 0x23, 2, 0XAC, 0X94, + 0x23, 2, 0XAD, 0X03, + 0x23, 2, 0XAE, 0XA3, + 0x23, 2, 0XAF, 0X03, + 0x23, 2, 0XB0, 0XAD, + 0x23, 2, 0XB1, 0X03, + 0x23, 2, 0XB2, 0XCC, + + 0x23, 2, 0XB3, 0X00, //Gamma R- + 0x23, 2, 0XB4, 0X18, + 0x23, 2, 0XB5, 0X00, + 0x23, 2, 0XB6, 0X38, + 0x23, 2, 0XB7, 0X00, + 0x23, 2, 0XB8, 0X65, + 0x23, 2, 0XB9, 0X00, + 0x23, 2, 0XBA, 0X84, + 0x23, 2, 0XBB, 0X00, + 0x23, 2, 0XBC, 0X9B, + 0x23, 2, 0XBD, 0X00, + 0x23, 2, 0XBE, 0XAF, + 0x23, 2, 0XBF, 0X00, + 0x23, 2, 0XC0, 0XC1, + 0x23, 2, 0XC1, 0X00, + 0x23, 2, 0XC2, 0XD2, + 0x23, 2, 0XC3, 0X00, + 0x23, 2, 0XC4, 0XDF, + 0x23, 2, 0XC5, 0X01, + 0x23, 2, 0XC6, 0X11, + 0x23, 2, 0XC7, 0X01, + 0x23, 2, 0XC8, 0X38, + 0x23, 2, 0XC9, 0X01, + 0x23, 2, 0XCA, 0X76, + 0x23, 2, 0XCB, 0X01, + 0x23, 2, 0XCC, 0XA7, + 0x23, 2, 0XCD, 0X01, + 0x23, 2, 0XCE, 0XF3, + 0x23, 2, 0XCF, 0X02, + 0x23, 2, 0XD0, 0X2F, + 0x23, 2, 0XD1, 0X02, + 0x23, 2, 0XD2, 0X30, + 0x23, 2, 0XD3, 0X02, + 0x23, 2, 0XD4, 0X66, + 0x23, 2, 0XD5, 0X02, + 0x23, 2, 0XD6, 0XA0, + 0x23, 2, 0XD7, 0X02, + 0x23, 2, 0XD8, 0XC5, + 0x23, 2, 0XD9, 0X02, + 0x23, 2, 0XDA, 0XF8, + 0x23, 2, 0XDB, 0X03, + 0x23, 2, 0XDC, 0X1B, + 0x23, 2, 0XDD, 0X03, + 0x23, 2, 0XDE, 0X46, + 0x23, 2, 0XDF, 0X03, + 0x23, 2, 0XE0, 0X52, + 0x23, 2, 0XE1, 0X03, + 0x23, 2, 0XE2, 0X62, + 0x23, 2, 0XE3, 0X03, + 0x23, 2, 0XE4, 0X71, + 0x23, 2, 0XE5, 0X03, + 0x23, 2, 0XE6, 0X83, + 0x23, 2, 0XE7, 0X03, + 0x23, 2, 0XE8, 0X94, + 0x23, 2, 0XE9, 0X03, + 0x23, 2, 0XEA, 0XA3, + 0x23, 2, 0XEB, 0X03, + 0x23, 2, 0XEC, 0XAD, + 0x23, 2, 0XED, 0X03, + 0x23, 2, 0XEE, 0XCC, + + 0x23, 2, 0XEF, 0X00, //Gamma G+ + 0x23, 2, 0XF0, 0X18, + 0x23, 2, 0XF1, 0X00, + 0x23, 2, 0XF2, 0X38, + 0x23, 2, 0XF3, 0X00, + 0x23, 2, 0XF4, 0X65, + 0x23, 2, 0XF5, 0X00, + 0x23, 2, 0XF6, 0X84, + 0x23, 2, 0XF7, 0X00, + 0x23, 2, 0XF8, 0X9B, + 0x23, 2, 0XF9, 0X00, + 0x23, 2, 0XFA, 0XAF, + 0x23, 2, 0XFF, 0X02, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0X00, 0X00, + 0x23, 2, 0X01, 0XC1, + 0x23, 2, 0X02, 0X00, + 0x23, 2, 0X03, 0XD2, + 0x23, 2, 0X04, 0X00, + 0x23, 2, 0X05, 0XDF, + 0x23, 2, 0X06, 0X01, + 0x23, 2, 0X07, 0X11, + 0x23, 2, 0X08, 0X01, + 0x23, 2, 0X09, 0X38, + 0x23, 2, 0X0A, 0X01, + 0x23, 2, 0X0B, 0X76, + 0x23, 2, 0X0C, 0X01, + 0x23, 2, 0X0D, 0XA7, + 0x23, 2, 0X0E, 0X01, + 0x23, 2, 0X0F, 0XF3, + 0x23, 2, 0X10, 0X02, + 0x23, 2, 0X11, 0X2F, + 0x23, 2, 0X12, 0X02, + 0x23, 2, 0X13, 0X30, + 0x23, 2, 0X14, 0X02, + 0x23, 2, 0X15, 0X66, + 0x23, 2, 0X16, 0X02, + 0x23, 2, 0X17, 0XA0, + 0x23, 2, 0X18, 0X02, + 0x23, 2, 0X19, 0XC5, + 0x23, 2, 0X1A, 0X02, + 0x23, 2, 0X1B, 0XF8, + 0x23, 2, 0X1C, 0X03, + 0x23, 2, 0X1D, 0X1B, + 0x23, 2, 0X1E, 0X03, + 0x23, 2, 0X1F, 0X46, + 0x23, 2, 0X20, 0X03, + 0x23, 2, 0X21, 0X52, + 0x23, 2, 0X22, 0X03, + 0x23, 2, 0X23, 0X62, + 0x23, 2, 0X24, 0X03, + 0x23, 2, 0X25, 0X71, + 0x23, 2, 0X26, 0X03, + 0x23, 2, 0X27, 0X83, + 0x23, 2, 0X28, 0X03, + 0x23, 2, 0X29, 0X94, + 0x23, 2, 0X2A, 0X03, + 0x23, 2, 0X2B, 0XA3, + 0x23, 2, 0X2D, 0X03, + 0x23, 2, 0X2F, 0XAD, + 0x23, 2, 0X30, 0X03, + 0x23, 2, 0X31, 0XCC, + + 0x23, 2, 0X32, 0X00, //Gamma G- + 0x23, 2, 0X33, 0X18, + 0x23, 2, 0X34, 0X00, + 0x23, 2, 0X35, 0X38, + 0x23, 2, 0X36, 0X00, + 0x23, 2, 0X37, 0X65, + 0x23, 2, 0X38, 0X00, + 0x23, 2, 0X39, 0X84, + 0x23, 2, 0X3A, 0X00, + 0x23, 2, 0X3B, 0X9B, + 0x23, 2, 0X3D, 0X00, + 0x23, 2, 0X3F, 0XAF, + 0x23, 2, 0X40, 0X00, + 0x23, 2, 0X41, 0XC1, + 0x23, 2, 0X42, 0X00, + 0x23, 2, 0X43, 0XD2, + 0x23, 2, 0X44, 0X00, + 0x23, 2, 0X45, 0XDF, + 0x23, 2, 0X46, 0X01, + 0x23, 2, 0X47, 0X11, + 0x23, 2, 0X48, 0X01, + 0x23, 2, 0X49, 0X38, + 0x23, 2, 0X4A, 0X01, + 0x23, 2, 0X4B, 0X76, + 0x23, 2, 0X4C, 0X01, + 0x23, 2, 0X4D, 0XA7, + 0x23, 2, 0X4E, 0X01, + 0x23, 2, 0X4F, 0XF3, + 0x23, 2, 0X50, 0X02, + 0x23, 2, 0X51, 0X2F, + 0x23, 2, 0X52, 0X02, + 0x23, 2, 0X53, 0X30, + 0x23, 2, 0X54, 0X02, + 0x23, 2, 0X55, 0X66, + 0x23, 2, 0X56, 0X02, + 0x23, 2, 0X58, 0XA0, + 0x23, 2, 0X59, 0X02, + 0x23, 2, 0X5A, 0XC5, + 0x23, 2, 0X5B, 0X02, + 0x23, 2, 0X5C, 0XF8, + 0x23, 2, 0X5D, 0X03, + 0x23, 2, 0X5E, 0X1B, + 0x23, 2, 0X5F, 0X03, + 0x23, 2, 0X60, 0X46, + 0x23, 2, 0X61, 0X03, + 0x23, 2, 0X62, 0X52, + 0x23, 2, 0X63, 0X03, + 0x23, 2, 0X64, 0X62, + 0x23, 2, 0X65, 0X03, + 0x23, 2, 0X66, 0X71, + 0x23, 2, 0X67, 0X03, + 0x23, 2, 0X68, 0X83, + 0x23, 2, 0X69, 0X03, + 0x23, 2, 0X6A, 0X94, + 0x23, 2, 0X6B, 0X03, + 0x23, 2, 0X6C, 0XA3, + 0x23, 2, 0X6D, 0X03, + 0x23, 2, 0X6E, 0XAD, + 0x23, 2, 0X6F, 0X03, + 0x23, 2, 0X70, 0XCC, + + 0x23, 2, 0X71, 0X00, //Gamma B+ + 0x23, 2, 0X72, 0X18, + 0x23, 2, 0X73, 0X00, + 0x23, 2, 0X74, 0X38, + 0x23, 2, 0X75, 0X00, + 0x23, 2, 0X76, 0X65, + 0x23, 2, 0X77, 0X00, + 0x23, 2, 0X78, 0X84, + 0x23, 2, 0X79, 0X00, + 0x23, 2, 0X7A, 0X9B, + 0x23, 2, 0X7B, 0X00, + 0x23, 2, 0X7C, 0XAF, + 0x23, 2, 0X7D, 0X00, + 0x23, 2, 0X7E, 0XC1, + 0x23, 2, 0X7F, 0X00, + 0x23, 2, 0X80, 0XD2, + 0x23, 2, 0X81, 0X00, + 0x23, 2, 0X82, 0XDF, + 0x23, 2, 0X83, 0X01, + 0x23, 2, 0X84, 0X11, + 0x23, 2, 0X85, 0X01, + 0x23, 2, 0X86, 0X38, + 0x23, 2, 0X87, 0X01, + 0x23, 2, 0X88, 0X76, + 0x23, 2, 0X89, 0X01, + 0x23, 2, 0X8A, 0XA7, + 0x23, 2, 0X8B, 0X01, + 0x23, 2, 0X8C, 0XF3, + 0x23, 2, 0X8D, 0X02, + 0x23, 2, 0X8E, 0X2F, + 0x23, 2, 0X8F, 0X02, + 0x23, 2, 0X90, 0X30, + 0x23, 2, 0X91, 0X02, + 0x23, 2, 0X92, 0X66, + 0x23, 2, 0X93, 0X02, + 0x23, 2, 0X94, 0XA0, + 0x23, 2, 0X95, 0X02, + 0x23, 2, 0X96, 0XC5, + 0x23, 2, 0X97, 0X02, + 0x23, 2, 0X98, 0XF8, + 0x23, 2, 0X99, 0X03, + 0x23, 2, 0X9A, 0X1B, + 0x23, 2, 0X9B, 0X03, + 0x23, 2, 0X9C, 0X46, + 0x23, 2, 0X9D, 0X03, + 0x23, 2, 0X9E, 0X52, + 0x23, 2, 0X9F, 0X03, + 0x23, 2, 0XA0, 0X62, + 0x23, 2, 0XA2, 0X03, + 0x23, 2, 0XA3, 0X71, + 0x23, 2, 0XA4, 0X03, + 0x23, 2, 0XA5, 0X83, + 0x23, 2, 0XA6, 0X03, + 0x23, 2, 0XA7, 0X94, + 0x23, 2, 0XA9, 0X03, + 0x23, 2, 0XAA, 0XA3, + 0x23, 2, 0XAB, 0X03, + 0x23, 2, 0XAC, 0XAD, + 0x23, 2, 0XAD, 0X03, + 0x23, 2, 0XAE, 0XCC, + + 0x23, 2, 0XAF, 0X00, //Gamma B- + 0x23, 2, 0XB0, 0X18, + 0x23, 2, 0XB1, 0X00, + 0x23, 2, 0XB2, 0X38, + 0x23, 2, 0XB3, 0X00, + 0x23, 2, 0XB4, 0X65, + 0x23, 2, 0XB5, 0X00, + 0x23, 2, 0XB6, 0X84, + 0x23, 2, 0XB7, 0X00, + 0x23, 2, 0XB8, 0X9B, + 0x23, 2, 0XB9, 0X00, + 0x23, 2, 0XBA, 0XAF, + 0x23, 2, 0XBB, 0X00, + 0x23, 2, 0XBC, 0XC1, + 0x23, 2, 0XBD, 0X00, + 0x23, 2, 0XBE, 0XD2, + 0x23, 2, 0XBF, 0X00, + 0x23, 2, 0XC0, 0XDF, + 0x23, 2, 0XC1, 0X01, + 0x23, 2, 0XC2, 0X11, + 0x23, 2, 0XC3, 0X01, + 0x23, 2, 0XC4, 0X38, + 0x23, 2, 0XC5, 0X01, + 0x23, 2, 0XC6, 0X76, + 0x23, 2, 0XC7, 0X01, + 0x23, 2, 0XC8, 0XA7, + 0x23, 2, 0XC9, 0X01, + 0x23, 2, 0XCA, 0XF3, + 0x23, 2, 0XCB, 0X02, + 0x23, 2, 0XCC, 0X2F, + 0x23, 2, 0XCD, 0X02, + 0x23, 2, 0XCE, 0X30, + 0x23, 2, 0XCF, 0X02, + 0x23, 2, 0XD0, 0X66, + 0x23, 2, 0XD1, 0X02, + 0x23, 2, 0XD2, 0XA0, + 0x23, 2, 0XD3, 0X02, + 0x23, 2, 0XD4, 0XC5, + 0x23, 2, 0XD5, 0X02, + 0x23, 2, 0XD6, 0XF8, + 0x23, 2, 0XD7, 0X03, + 0x23, 2, 0XD8, 0X1B, + 0x23, 2, 0XD9, 0X03, + 0x23, 2, 0XDA, 0X46, + 0x23, 2, 0XDB, 0X03, + 0x23, 2, 0XDC, 0X52, + 0x23, 2, 0XDD, 0X03, + 0x23, 2, 0XDE, 0X62, + 0x23, 2, 0XDF, 0X03, + 0x23, 2, 0XE0, 0X71, + 0x23, 2, 0XE1, 0X03, + 0x23, 2, 0XE2, 0X83, + 0x23, 2, 0XE3, 0X03, + 0x23, 2, 0XE4, 0X94, + 0x23, 2, 0XE5, 0X03, + 0x23, 2, 0XE6, 0XA3, + 0x23, 2, 0XE7, 0X03, + 0x23, 2, 0XE8, 0XAD, + 0x23, 2, 0XE9, 0X03, + 0x23, 2, 0XEA, 0XCC, + + 0x23, 2, 0XFF, 0X01, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0XFF, 0X02, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0XFF, 0X04, //CMD page select + 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD + 0x23, 2, 0XFF, 0X00, //CMD page select + + 0x23, 2, 0XD3, 0X05, + 0x23, 2, 0XD4, 0X04, + + 0x23, 2, 0X11, 0X00, //Sleep out + 0xfd, 1, 100, //delay 100ms + 0x23, 2, 0XFF, 0X00, + + 0x23, 2, 0X35, 0X00, //TE on + + 0x23, 2, 0X29, 0X00, //Display on + 0xfd, 1, 100, //delay 100ms + 0xff, 0, /* ending flag */ +}; + +static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = { + 0x05, 1, 0x28, /* display off */ + 0xfd, 1, 10, /* delay 10ms */ + 0x05, 1, 0x10, /* sleep in */ + 0xfd, 1, 150, /* delay 150ms */ + 0xFF, 0, /* ending flag */ +}; + +#endif + diff --git a/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c b/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c new file mode 100755 index 0000000..37c13d4 --- a/dev/null +++ b/board/amlogic/sm1_sabrina_v1/sm1_sabrina_v1.c @@ -0,0 +1,836 @@ + +/* + * board/amlogic/txl_skt_v1/txl_skt_v1.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/cpu_id.h> +#include <asm/arch/secure_apb.h> +#ifdef CONFIG_SYS_I2C_AML +#include <aml_i2c.h> +#endif +#ifdef CONFIG_SYS_I2C_MESON +#include <amlogic/i2c.h> +#endif +#ifdef CONFIG_AML_VPU +#include <vpu.h> +#endif +#include <vpp.h> +#ifdef CONFIG_AML_V2_FACTORY_BURN +#include <amlogic/aml_v2_burning.h> +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/hdmi.h> +#endif +#ifdef CONFIG_AML_LCD +#include <amlogic/aml_lcd.h> +#endif +#include <asm/arch/eth_setup.h> +#include <phy.h> +#include <linux/mtd/partitions.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#ifdef CONFIG_AML_SPIFC +#include <amlogic/spifc.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +//new static eth setup +struct eth_board_socket* eth_board_skt; + +void sys_led_init(void) +{ + //set GPIOAO_11 drive strength + setbits_le32(AO_PAD_DS_A,(3<<22)); //GPIOAO_11 set drive strength "3" +} + +int serial_set_pin_port(unsigned long port_base) +{ + //UART in "Always On Module" + //GPIOAO_0==tx,GPIOAO_1==rx + //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} +#ifdef ETHERNET_INTERNAL_PHY +void internalPhyConfig(struct phy_device *phydev) +{ +} + +static int dwmac_meson_cfg_pll(void) +{ + writel(0x39C0040A, P_ETH_PLL_CTL0); + writel(0x927E0000, P_ETH_PLL_CTL1); + writel(0xAC5F49E5, P_ETH_PLL_CTL2); + writel(0x00000000, P_ETH_PLL_CTL3); + udelay(200); + writel(0x19C0040A, P_ETH_PLL_CTL0); + return 0; +} + +static int dwmac_meson_cfg_analog(void) +{ + /*Analog*/ + writel(0x20200000, P_ETH_PLL_CTL5); + writel(0x0000c002, P_ETH_PLL_CTL6); + writel(0x00000023, P_ETH_PLL_CTL7); + + return 0; +} + +static int dwmac_meson_cfg_ctrl(void) +{ + /*config phyid should between a 0~0xffffffff*/ + /*please don't use 44000181, this has been used by internal phy*/ + writel(0x33000180, P_ETH_PHY_CNTL0); + + /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/ + writel(0x260, P_ETH_PHY_CNTL2); + + writel(0x74043, P_ETH_PHY_CNTL1); + writel(0x34043, P_ETH_PHY_CNTL1); + writel(0x74043, P_ETH_PHY_CNTL1); + return 0; +} + +static void setup_net_chip(void) +{ + eth_aml_reg0_t eth_reg0; + + eth_reg0.d32 = 0; + eth_reg0.b.phy_intf_sel = 4; + eth_reg0.b.rx_clk_rmii_invert = 0; + eth_reg0.b.rgmii_tx_clk_src = 0; + eth_reg0.b.rgmii_tx_clk_phase = 0; + eth_reg0.b.rgmii_tx_clk_ratio = 4; + eth_reg0.b.phy_ref_clk_enable = 1; + eth_reg0.b.clk_rmii_i_invert = 1; + eth_reg0.b.clk_en = 1; + eth_reg0.b.adj_enable = 1; + eth_reg0.b.adj_setup = 0; + eth_reg0.b.adj_delay = 9; + eth_reg0.b.adj_skew = 0; + eth_reg0.b.cali_start = 0; + eth_reg0.b.cali_rise = 0; + eth_reg0.b.cali_sel = 0; + eth_reg0.b.rgmii_rx_reuse = 0; + eth_reg0.b.eth_urgent = 0; + setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode + + dwmac_meson_cfg_pll(); + dwmac_meson_cfg_analog(); + dwmac_meson_cfg_ctrl(); + + /* eth core clock */ + setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3)); + /* eth phy clock */ + setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4)); + + /* eth phy pll, clk50m */ + setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5)); + + /* power on memory */ + clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); +} +#endif + +#ifdef ETHERNET_EXTERNAL_PHY + +static int dwmac_meson_cfg_drive_strength(void) +{ + writel(0xaaaaaaa5, P_PAD_DS_REG4A); + return 0; +} + +static void setup_net_chip_ext(void) +{ + eth_aml_reg0_t eth_reg0; + writel(0x11111111, P_PERIPHS_PIN_MUX_6); + writel(0x111111, P_PERIPHS_PIN_MUX_7); + + eth_reg0.d32 = 0; + eth_reg0.b.phy_intf_sel = 1; + eth_reg0.b.rx_clk_rmii_invert = 0; + eth_reg0.b.rgmii_tx_clk_src = 0; + eth_reg0.b.rgmii_tx_clk_phase = 1; + eth_reg0.b.rgmii_tx_clk_ratio = 4; + eth_reg0.b.phy_ref_clk_enable = 1; + eth_reg0.b.clk_rmii_i_invert = 0; + eth_reg0.b.clk_en = 1; + eth_reg0.b.adj_enable = 0; + eth_reg0.b.adj_setup = 0; + eth_reg0.b.adj_delay = 0; + eth_reg0.b.adj_skew = 0; + eth_reg0.b.cali_start = 0; + eth_reg0.b.cali_rise = 0; + eth_reg0.b.cali_sel = 0; + eth_reg0.b.rgmii_rx_reuse = 0; + eth_reg0.b.eth_urgent = 0; + setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode + + setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3); + /* power on memory */ + clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); +} +#endif +extern struct eth_board_socket* eth_board_setup(char *name); +extern int designware_initialize(ulong base_addr, u32 interface); + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_ETHERNET_NONE + return 0; +#endif + +#ifdef ETHERNET_EXTERNAL_PHY + dwmac_meson_cfg_drive_strength(); + setup_net_chip_ext(); +#endif +#ifdef ETHERNET_INTERNAL_PHY + setup_net_chip(); +#endif + udelay(1000); + designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII); + return 0; +} + +#if CONFIG_AML_SD_EMMC +#include <mmc.h> +#include <asm/arch/sd_emmc.h> +static int sd_emmc_init(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: + //todo add card detect + /* check card detect */ + clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24); + setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6); + setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6); + setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6); + break; + case SDIO_PORT_C: + //enable pull up + //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0); + break; + default: + break; + } + + return cpu_sd_emmc_init(port); +} + +extern unsigned sd_debug_board_1bit_flag; + + +static void sd_emmc_pwr_prepare(unsigned port) +{ + cpu_sd_emmc_pwr_prepare(port); +} + +static void sd_emmc_pwr_on(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + /// @todo NOT FINISH + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} +static void sd_emmc_pwr_off(unsigned port) +{ + /// @todo NOT FINISH + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} + +// #define CONFIG_TSD 1 +static void board_mmc_register(unsigned port) +{ + struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port); + if (aml_priv == NULL) + return; + + aml_priv->sd_emmc_init=sd_emmc_init; + aml_priv->sd_emmc_detect=sd_emmc_detect; + aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off; + aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on; + aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare; + aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info))); + + if (NULL == aml_priv->desc_buf) + printf(" desc_buf Dma alloc Fail!\n"); + else + printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf); + + sd_emmc_register(aml_priv); +} +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_VLSI_EMULATOR + //board_mmc_register(SDIO_PORT_A); +#else + //board_mmc_register(SDIO_PORT_B); +#endif + board_mmc_register(SDIO_PORT_B); + board_mmc_register(SDIO_PORT_C); +// board_mmc_register(SDIO_PORT_B1); + return 0; +} + +#ifdef CONFIG_SYS_I2C_AML +#if 0 +static void board_i2c_set_pinmux(void){ + /*********************************************/ + /* | I2C_Master_AO |I2C_Slave | */ + /*********************************************/ + /* | I2C_SCK | I2C_SCK_SLAVE | */ + /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */ + /*********************************************/ + /* | I2C_SDA | I2C_SDA_SLAVE | */ + /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */ + /*********************************************/ + + //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO + clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23))); + //enable I2C MASTER AO pins + setbits_le32(P_AO_RTI_PIN_MUX_REG, + (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT)); + + udelay(10); +}; +#endif +struct aml_i2c_platform g_aml_i2c_plat = { + .wait_count = 1000000, + .wait_ack_interval = 5, + .wait_read_interval = 5, + .wait_xfer_interval = 5, + .master_no = AML_I2C_MASTER_AO, + .use_pio = 0, + .master_i2c_speed = AML_I2C_SPPED_400K, + .master_ao_pinmux = { + .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG, + .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT, + .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG, + .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT, + } +}; +#if 0 +static void board_i2c_init(void) +{ + //set I2C pinmux with PCB board layout + board_i2c_set_pinmux(); + + //Amlogic I2C controller initialized + //note: it must be call before any I2C operation + aml_i2c_init(); + + udelay(10); +} +#endif +#endif +#endif + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void){ + /*add board early init function here*/ + return 0; +} +#endif + +#ifdef CONFIG_USB_XHCI_AMLOGIC_V2 +#include <asm/arch/usb-v2.h> +#include <asm/arch/gpio.h> +#define CONFIG_GXL_USB_U2_PORT_NUM 2 + +#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2 +#define CONFIG_GXL_USB_U3_PORT_NUM 1 +#else +#define CONFIG_GXL_USB_U3_PORT_NUM 0 +#endif + +static void gpio_set_vbus_power(char is_power_on) +{ + int ret; + + ret = gpio_request(CONFIG_USB_GPIO_PWR, + CONFIG_USB_GPIO_PWR_NAME); + if (ret && ret != -EBUSY) { + printf("gpio: requesting pin %u failed\n", + CONFIG_USB_GPIO_PWR); + return; + } + + if (is_power_on) { + gpio_direction_output(CONFIG_USB_GPIO_PWR, 1); + } else { + gpio_direction_output(CONFIG_USB_GPIO_PWR, 0); + } +} + +struct amlogic_usb_config g_usb_config_GXL_skt={ + CONFIG_GXL_XHCI_BASE, + USB_ID_MODE_HARDWARE, + gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power + CONFIG_GXL_USB_PHY2_BASE, + CONFIG_GXL_USB_PHY3_BASE, + CONFIG_GXL_USB_U2_PORT_NUM, + CONFIG_GXL_USB_U3_PORT_NUM, + .usb_phy2_pll_base_addr = { + CONFIG_USB_PHY_20, + CONFIG_USB_PHY_21, + } +}; + +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#ifdef CONFIG_AML_HDMITX20 +static void hdmi_tx_set_hdmi_5v(void) +{ + run_command("gpio set GPIOZ_12", 0); +} +#endif + +/* + * mtd nand partition table, only care the size! + * offset will be calculated by nand driver. + */ +#ifdef CONFIG_AML_MTD +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER + /* MUST NOT CHANGE this part unless u know what you are doing! + * inherent parition for descrete bootloader to store fip + * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM + * name must be same with TPL_PART_NAME + */ + { + .name = "tpl", + .offset = 0, + .size = 0, + }, +#endif + { + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 15*SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 280*SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif /* CONFIG_AML_MTD */ + +#ifdef CONFIG_AML_SPIFC +/* + * BOOT_3: NOR_HOLDn:reg0[15:12]=3 + * BOOT_4: NOR_D:reg0[19:16]=3 + * BOOT_5: NOR_Q:reg0[23:20]=3 + * BOOT_6: NOR_C:reg0[27:24]=3 + * BOOT_7: NOR_WPn:reg0[31:28]=3 + * BOOT_14: NOR_CS:reg1[27:24]=3 + */ +#define SPIFC_NUM_CS 1 +static int spifc_cs_gpios[SPIFC_NUM_CS] = {54}; + +static int spifc_pinctrl_enable(void *pinctrl, bool enable) +{ + unsigned int val; + + val = readl(P_PERIPHS_PIN_MUX_0); + val &= ~(0xfffff << 12); + if (enable) + val |= 0x33333 << 12; + writel(val, P_PERIPHS_PIN_MUX_0); + + val = readl(P_PERIPHS_PIN_MUX_1); + val &= ~(0xf << 24); + writel(val, P_PERIPHS_PIN_MUX_1); + return 0; +} + +static const struct spifc_platdata spifc_platdata = { + .reg = 0xffd14000, + .mem_map = 0xf6000000, + .pinctrl_enable = spifc_pinctrl_enable, + .num_chipselect = SPIFC_NUM_CS, + .cs_gpios = spifc_cs_gpios, +}; + +U_BOOT_DEVICE(spifc) = { + .name = "spifc", + .platdata = &spifc_platdata, +}; +#endif /* CONFIG_AML_SPIFC */ + +extern void aml_pwm_cal_init(int mode); + +#ifdef CONFIG_SYS_I2C_MESON +static const struct meson_i2c_platdata i2c_data[] = { + { 0, 0xffd1f000, 166666666, 3, 15, 100000 }, + { 1, 0xffd1e000, 166666666, 3, 15, 100000 }, + { 2, 0xffd1d000, 166666666, 3, 15, 100000 }, + { 3, 0xffd1c000, 166666666, 3, 15, 100000 }, + { 4, 0xff805000, 166666666, 3, 15, 100000 }, +}; + +U_BOOT_DEVICES(meson_i2cs) = { + { "i2c_meson", &i2c_data[0] }, + { "i2c_meson", &i2c_data[1] }, + { "i2c_meson", &i2c_data[2] }, + { "i2c_meson", &i2c_data[3] }, + { "i2c_meson", &i2c_data[4] }, +}; + +/* + *GPIOAO_10//I2C_SDA_AO + *GPIOAO_11//I2C_SCK_AO + *pinmux configuration seperated with i2c controller configuration + * config it when you use + */ +void set_i2c_ao_pinmux(void) +{ + return; +} +#endif /*end CONFIG_SYS_I2C_MESON*/ + +int board_init(void) +{ + sys_led_init(); + //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init + //As NOT NEED other board init If USB BOOT MODE +#ifdef CONFIG_AML_V2_FACTORY_BURN + if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) { + aml_try_factory_usb_burning(0, gd->bd); + } +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN +#ifdef CONFIG_USB_XHCI_AMLOGIC_V2 + board_usb_pll_disable(&g_usb_config_GXL_skt); + board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST); +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#if 0 + aml_pwm_cal_init(0); +#endif// +#ifdef CONFIG_AML_NAND + extern int amlnf_init(unsigned char flag); + amlnf_init(0); +#endif +#ifdef CONFIG_SYS_I2C_MESON + set_i2c_ao_pinmux(); +#endif + + return 0; +} + +/* set dts props */ +void aml_config_dtb(void) +{ + cpu_id_t cpuid = get_cpu_id(); + if (MESON_CPU_MAJOR_ID_G12A != cpuid.family_id) + return; + run_command("fdt address $dtb_mem_addr", 0); + printf("%s %d\n", __func__, __LINE__); + if (cpuid.chip_rev == 0xA) { + printf("%s %d\n", __func__, __LINE__); + run_command("fdt set /emmc/emmc co_phase <0x2>", 0); + run_command("fdt rm /emmc/emmc caps2", 0); + run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0); + + run_command("fdt set /sdio status okay", 0); + run_command("fdt set /sd1 status okay", 0); + run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0); + run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0); + run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0); + /* debug */ + run_command("fdt print /emmc/emmc co_phase", 0); + run_command("fdt print /emmc/emmc caps2", 0); + run_command("fdt print /emmc/emmc f_max", 0); + + run_command("fdt print /sdio status", 0); + run_command("fdt print /sd1 status ", 0); + run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0); + run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0); + } else { + + printf("%s %d\n", __func__, __LINE__); + run_command("fdt set /emmc/emmc co_phase <0x3>", 0); + run_command("fdt set /sdio status disabled", 0); + run_command("fdt set /sd2 status okay", 0); + /* debug */ + run_command("fdt print /emmc/emmc co_phase", 0); + run_command("fdt print /emmc/emmc caps2", 0); + run_command("fdt print /emmc/emmc f_max", 0); + run_command("fdt print /sdio status", 0); + run_command("fdt print /sd2 status", 0); + } + + return; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + //update env before anyone using it + run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\ + "if test ${reboot_mode} = factory_reset; then "\ + "defenv_reserv;save; fi;", 0); + run_command("if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + /*add board late init function here*/ +#ifndef DTB_BIND_KERNEL + int ret; + ret = run_command("store dtb read $dtb_mem_addr", 1); + if (ret) { + printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__); +#ifdef CONFIG_DTB_MEM_ADDR + char cmd[64]; + printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR); + sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR); + ret = run_command(cmd, 1); + if (ret) { + printf("%s(): %s fail\n", __func__, cmd); + } +#endif + } +#elif defined(CONFIG_DTB_MEM_ADDR) + { + char cmd[128]; + int ret; + if (!getenv("dtb_mem_addr")) { + sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR); + run_command(cmd, 0); + } + sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}"); + ret = run_command(cmd, 0); + if (ret) { + printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret); + } + } +#endif// #ifndef DTB_BIND_KERNEL + + /* load unifykey */ + run_command("keyunify init 0x1234", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif + vpp_init(); +#ifdef CONFIG_AML_HDMITX20 + hdmi_tx_set_hdmi_5v(); + hdmi_tx_init(); +#endif +#ifdef CONFIG_AML_CVBS + run_command("cvbs init", 0); +#endif +#ifdef CONFIG_AML_LCD + lcd_probe(); +#endif + +#ifdef CONFIG_AML_V2_FACTORY_BURN + if (0x1b8ec003 == readl(P_PREG_STICKY_REG2)) + aml_try_factory_usb_burning(1, gd->bd); + aml_try_factory_sdcard_burning(0, gd->bd); +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN + + if (MESON_CPU_MAJOR_ID_SM1 == get_cpu_id().family_id) { + setenv("board_defined_bootup", "bootup_D3"); + } + /**/ + aml_config_dtb(); + return 0; +} +#endif + +#ifdef CONFIG_AML_TINY_USBTOOL +int usb_get_update_result(void) +{ + unsigned long upgrade_step; + upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16); + printf("upgrade_step = %d\n", (int)upgrade_step); + if (upgrade_step == 1) + { + run_command("defenv", 1); + run_command("setenv upgrade_step 2", 1); + run_command("saveenv", 1); + return 0; + } + else + { + return -1; + } +} +#endif + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4); +#endif +} + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + /* + * set aml_dt according to chip and dram capacity + */ + unsigned int ddr_size=0; + char loc_name[64] = {0}; + int i; + cpu_id_t cpu_id=get_cpu_id(); + + for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) { + ddr_size += gd->bd->bi_dram[i].size; + } +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + ddr_size += CONFIG_SYS_MEM_TOP_HIDE; +#endif + char *ddr_mode = getenv("mem_size"); + if (MESON_CPU_MAJOR_ID_SM1 == cpu_id.family_id) { + switch (ddr_size) { + case 0x80000000: + if (!strcmp(ddr_mode, "1g")) { + strcpy(loc_name, "sm1_ac200_1g\0"); + break; + } + strcpy(loc_name, "sm1_ac200_2g\0"); + break; + case 0x40000000: + strcpy(loc_name, "sm1_ac200_1g\0"); + break; + case 0x2000000: + strcpy(loc_name, "sm1_ac200_512m\0"); + break; + default: + strcpy(loc_name, "sm1_ac200_unsupport"); + break; + } + } + else { + switch (ddr_size) { + case 0x80000000: + if (!strcmp(ddr_mode, "1g")) { + strcpy(loc_name, "g12a_u200_1g\0"); + break; + } + strcpy(loc_name, "g12a_u200_2g\0"); + break; + case 0x40000000: + strcpy(loc_name, "g12a_u200_1g\0"); + break; + case 0x2000000: + strcpy(loc_name, "g12a_u200_512m\0"); + break; + default: + strcpy(loc_name, "g12a_u200_unsupport"); + break; + } + } + strcpy(name, loc_name); + setenv("aml_dt", loc_name); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "aml_dt", + "firstboot", + "lock", + "upgrade_step", + + NULL//Keep NULL be last to tell END +}; diff --git a/board/harman/Kconfig b/board/harman/Kconfig new file mode 100644 index 0000000..7c1588b --- a/dev/null +++ b/board/harman/Kconfig @@ -0,0 +1,8 @@ +config ATOM_V1 + bool "Support harman atom v1 board" + default n + +if ATOM_V1 +source "board/harman/atom_v1/Kconfig" +endif + diff --git a/board/harman/atom_v1/Kconfig b/board/harman/atom_v1/Kconfig new file mode 100644 index 0000000..d00348d --- a/dev/null +++ b/board/harman/atom_v1/Kconfig @@ -0,0 +1,22 @@ +if TARGET_MESON_TXLX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "atom_v1" + +config SYS_VENDOR + string + default "harman" + +config SYS_SOC + string + default "txlx" + +config SYS_CONFIG_NAME + default "atom_v1" + +endif diff --git a/board/harman/atom_v1/Makefile b/board/harman/atom_v1/Makefile new file mode 100644 index 0000000..963e9c5 --- a/dev/null +++ b/board/harman/atom_v1/Makefile @@ -0,0 +1,4 @@ + +obj-y += $(BOARD).o eth_setup.o +obj-$(CONFIG_AML_LCD) += lcd.o +obj-y += pwm_table.o diff --git a/board/harman/atom_v1/aml-user-key.sig b/board/harman/atom_v1/aml-user-key.sig new file mode 100755 index 0000000..2ceabc1 --- a/dev/null +++ b/board/harman/atom_v1/aml-user-key.sig @@ -0,0 +1,28 @@ +yÅtÃ}| 4B²/i Ö»x¹nÜ:fÙÞžpdd'üá¹àê¯të©NöZ ¿!˜£òÄ@í $ ã×-È°°ÃÒ š‰°2³{ñ^žsWµñí ²`Dù‚#”@¸>…+äbŒqÏŽy”¡dàéÊÇ:“TŒ8Ο„
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âÈcÊ] +|¬$ô! O"QK +q'¡îçü>õìo‹éÜdÚ WÏ|û¤Œv¼K´f1$z‚îÓA×'ê<ªÊFxPTõÑ³ç ‚³ÿpüëyy̽±[’Ëkq¦A<œˆ¸'¼BNFÇ‹‡#Ï0Û{ã¹¥ˆvÝxõãøÖ( º4ªiWA¹Ç“ÍažJK¼êäÚ¶ë ðØÕÆèªù†Z‰;Å–;(YZË~ŒÀ@0†Å~< +ÑÒ“Jÿƒ—–Øy8ýûÛ·Ûkx +²KÕ\E¦=ò + diff --git a/board/harman/atom_v1/atom_v1.c b/board/harman/atom_v1/atom_v1.c new file mode 100644 index 0000000..fd458fb --- a/dev/null +++ b/board/harman/atom_v1/atom_v1.c @@ -0,0 +1,554 @@ +/* + * board/harman/atom_v1/atom_v1.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/cpu_id.h> +#ifdef CONFIG_SYS_I2C_AML +#include <aml_i2c.h> +#include <asm/arch/secure_apb.h> +#endif +#ifdef CONFIG_AML_VPU +#include <vpu.h> +#endif +#include <vpp.h> +#ifdef CONFIG_AML_V2_FACTORY_BURN +#include <amlogic/aml_v2_burning.h> +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/hdmi.h> +#endif +#ifdef CONFIG_AML_LCD +#include <amlogic/aml_lcd.h> +#endif +#include <asm/arch/eth_setup.h> +#include <phy.h> +#include <asm-generic/gpio.h> +#include "avb2_kpub.c" + +DECLARE_GLOBAL_DATA_PTR; + +//new static eth setup +struct eth_board_socket* eth_board_skt; + + +int serial_set_pin_port(unsigned long port_base) +{ + //UART in "Always On Module" + //GPIOAO_0==tx,GPIOAO_1==rx + //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} +void internalPhyConfig(struct phy_device *phydev) +{ + /*Enable Analog and DSP register Bank access by*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + /*Write Analog register 23*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417); + /*Enable fractional PLL*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B); + //Programme fraction FR_PLL_DIV1 + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D); + //## programme fraction FR_PLL_DiV1 + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C); +} + + +static void setup_net_chip(void) +{ + eth_aml_reg0_t eth_reg0; + + eth_reg0.d32 = 0; + eth_reg0.b.phy_intf_sel = 4; + eth_reg0.b.rx_clk_rmii_invert = 0; + eth_reg0.b.rgmii_tx_clk_src = 0; + eth_reg0.b.rgmii_tx_clk_phase = 0; + eth_reg0.b.rgmii_tx_clk_ratio = 0; + eth_reg0.b.phy_ref_clk_enable = 0; + eth_reg0.b.clk_rmii_i_invert = 1; + eth_reg0.b.clk_en = 1; + eth_reg0.b.adj_enable = 0; + eth_reg0.b.adj_setup = 0; + eth_reg0.b.adj_delay = 0; + eth_reg0.b.adj_skew = 0; + eth_reg0.b.cali_start = 0; + eth_reg0.b.cali_rise = 0; + eth_reg0.b.cali_sel = 0; + eth_reg0.b.rgmii_rx_reuse = 0; + eth_reg0.b.eth_urgent = 0; + setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode + *P_PREG_ETH_REG2 = 0x10110181; + *P_PREG_ETH_REG3 = 0xe409087f; + setbits_le32(HHI_GCLK_MPEG1,1<<3); + /* power on memory */ + clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); + +} + +extern struct eth_board_socket* eth_board_setup(char *name); +extern int designware_initialize(ulong base_addr, u32 interface); + +int board_eth_init(bd_t *bis) +{ + setup_net_chip(); + udelay(1000); + designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII); + return 0; +} + +#if CONFIG_AML_SD_EMMC +#include <mmc.h> +#include <asm/arch/sd_emmc.h> +static int sd_emmc_init(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: + //todo add card detect + //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6 + break; + case SDIO_PORT_C: + //enable pull up + //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0); + break; + default: + break; + } + + return cpu_sd_emmc_init(port); +} + +static void sd_emmc_pwr_prepare(unsigned port) +{ + cpu_sd_emmc_pwr_prepare(port); +} + +static void sd_emmc_pwr_on(unsigned port) +{ + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + /// @todo NOT FINISH + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} +static void sd_emmc_pwr_off(unsigned port) +{ + /// @todo NOT FINISH + switch (port) + { + case SDIO_PORT_A: + break; + case SDIO_PORT_B: +// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8 +// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31)); + break; + case SDIO_PORT_C: + break; + default: + break; + } + return; +} + +// #define CONFIG_TSD 1 +static void board_mmc_register(unsigned port) +{ + struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port); + if (aml_priv == NULL) + return; + + aml_priv->sd_emmc_init=sd_emmc_init; + aml_priv->sd_emmc_detect=sd_emmc_detect; + aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off; + aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on; + aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare; + aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info))); + + if (NULL == aml_priv->desc_buf) + printf(" desc_buf Dma alloc Fail!\n"); + else + printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf); + + sd_emmc_register(aml_priv); +} +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_VLSI_EMULATOR + //board_mmc_register(SDIO_PORT_A); +#else + //board_mmc_register(SDIO_PORT_B); +#endif + board_mmc_register(SDIO_PORT_B); + board_mmc_register(SDIO_PORT_C); +// board_mmc_register(SDIO_PORT_B1); + return 0; +} + +#ifdef CONFIG_SYS_I2C_AML +#if 0 +static void board_i2c_set_pinmux(void){ + /*********************************************/ + /* | I2C_Master_AO |I2C_Slave | */ + /*********************************************/ + /* | I2C_SCK | I2C_SCK_SLAVE | */ + /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */ + /*********************************************/ + /* | I2C_SDA | I2C_SDA_SLAVE | */ + /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */ + /*********************************************/ + + //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO + clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23))); + //enable I2C MASTER AO pins + setbits_le32(P_AO_RTI_PIN_MUX_REG, + (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT)); + + udelay(10); +}; +#endif +struct aml_i2c_platform g_aml_i2c_plat = { + .wait_count = 1000000, + .wait_ack_interval = 5, + .wait_read_interval = 5, + .wait_xfer_interval = 5, + .master_no = AML_I2C_MASTER_AO, + .use_pio = 0, + .master_i2c_speed = AML_I2C_SPPED_400K, + .master_ao_pinmux = { + .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG, + .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT, + .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG, + .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT, + } +}; +#if 0 +static void board_i2c_init(void) +{ + //set I2C pinmux with PCB board layout + board_i2c_set_pinmux(); + + //Amlogic I2C controller initialized + //note: it must be call before any I2C operation + aml_i2c_init(); + + udelay(10); +} +#endif +#endif +#endif + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void){ + /*add board early init function here*/ + return 0; +} +#endif + +#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL +#include <asm/arch/usb-new.h> +#include <asm/arch/gpio.h> +#define CONFIG_GXL_USB_U2_PORT_NUM 4 +#define CONFIG_GXL_USB_U3_PORT_NUM 0 + +struct amlogic_usb_config g_usb_config_GXL_skt={ + CONFIG_GXL_XHCI_BASE, + USB_ID_MODE_HARDWARE, + NULL,//gpio_set_vbus_power, //set_vbus_power + CONFIG_GXL_USB_PHY2_BASE, + CONFIG_GXL_USB_PHY3_BASE, + CONFIG_GXL_USB_U2_PORT_NUM, + CONFIG_GXL_USB_U3_PORT_NUM, +}; +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#ifdef CONFIG_AML_HDMITX20 +static void hdmi_tx_set_hdmi_5v(void) +{ +} +#endif + +#ifdef CONFIG_AML_SPICC +#include <amlogic/spicc.h> +#include <dm.h> +#include <amlogic/spicc.h> +#include <asm/arch/secure_apb.h> + +/* generic config in arch gpio/clock.c */ +extern int spicc0_clk_enable(bool enable); + +/* generic pins control for txlx spicc0. + 285 * if deleted, you have to add it into all txlx board files as necessary. + 286 * GPIOZ_0: MOSI:regB[19:16]=3 + 287 * GPIOZ_1: MISO:regB[23:20]=3 + 288 * GPIOZ_2: CLK:regB[31:28]=3 + 289 * GPIOZ_3: SS0:regB[27:24]=3 + 290 */ +int atom_spicc0_pinctrl_enable(bool enable) +{ + u32 regv; + + regv = readl(P_PERIPHS_PIN_MUX_4); + regv &= ~0x80000000; + if (enable) { + regv |= 0x80000000; + regv &= ~0x2000000; + } + writel(regv, P_PERIPHS_PIN_MUX_4); + + if (enable) { + regv = readl(P_PERIPHS_PIN_MUX_3); + regv &= ~0x210000; + writel(regv, P_PERIPHS_PIN_MUX_3); + } + + return 0; +} + + +static const struct spicc_platdata spicc0_platdata = { + .compatible = "amlogic,meson-txl-spicc", + .reg = (void __iomem *)0xffd13000, + .clk_rate = 166666666, + .clk_enable = spicc0_clk_enable, + .pinctrl_enable = atom_spicc0_pinctrl_enable, + /* case one slave without cs: {"no_cs", 0} */ + .cs_gpio_names = {"no_cs", 0}, + }; + +U_BOOT_DEVICE(spicc0) = { + .name = "spicc", + .platdata = &spicc0_platdata, + }; +#endif /* CONFIG_AML_SPICC */ + + + +extern void aml_pwm_cal_init(int mode); + +int board_init(void) +{ +#ifdef CONFIG_AML_V2_FACTORY_BURN + if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) { + aml_try_factory_usb_burning(0, gd->bd); + } +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN + aml_pwm_cal_init(0); +#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL + board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST); +#endif /*CONFIG_USB_XHCI_AMLOGIC*/ + +#ifdef CONFIG_AML_NAND + extern int amlnf_init(unsigned char flag); + amlnf_init(0); +#endif + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + int ret; + + //update env before anyone using it + run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\ + "if test ${reboot_mode} = factory_reset; then "\ + "defenv_reserv;save; fi;", 0); + run_command("if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + /*add board late init function here*/ + ret = run_command("store dtb read $dtb_mem_addr", 1); + if (ret) { + printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__); + #ifdef CONFIG_DTB_MEM_ADDR + char cmd[64]; + printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR); + sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR); + ret = run_command(cmd, 1); + if (ret) { + printf("%s(): %s fail\n", __func__, cmd); + } + #endif + } + + run_command("sspi 0:0.0.3300000.8 384 888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE888EEEEE", 0); + + run_command("gpio clear gpiodv_5", 0); //amp 0: mute; 1: unmute + run_command("gpio clear gpioz_2", 0); //amp 0: power down; 1: normal + run_command("gpio set gpiodv_4", 1); //amp 1: supply power + + // GPIOW_9 Default to low level for AUX/RF_SW + run_command("gpio set gpiow_9", 0); + + // for rf subwoofer + run_command("gpio input gpioz_8", 0); + run_command("gpio input gpioz_9", 0); + + run_command("gpio input gpioh_10", 0);//i2c busy gpio as input + run_command("gpio clear gpioh_0", 0); //reset Syncomm TX module + udelay(50000); + run_command("gpio set gpioh_0", 0); + + /* load unifykey */ + run_command("keyunify init 0x1234", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif + vpp_init(); +#ifdef CONFIG_AML_HDMITX20 + hdmi_tx_set_hdmi_5v(); + hdmi_tx_init(); +#endif +#ifdef CONFIG_AML_CVBS + run_command("cvbs init", 0); +#endif +#ifdef CONFIG_AML_LCD + lcd_probe(); +#endif + +#ifdef CONFIG_AML_V2_FACTORY_BURN + if (0x1b8ec003 == readl(P_PREG_STICKY_REG2)) + aml_try_factory_usb_burning(1, gd->bd); + /*aml_try_factory_sdcard_burning(0, gd->bd);*/ +#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN + + /*for auto insert recovery_key env*/ + if (!getenv("recovery_key")) + { + setenv("recovery_key", + "if saradc open 2; then echo recovery from flash key detect; if saradc get_in_range 1 5; then sleep 5; if saradc get_in_range 1 5; then echo enter recovery mode;run recovery_from_flash; fi; fi; fi;"); + setenv("switch_bootmode", + "run clear_demomode; get_rebootmode; if test ${reboot_mode} = factory_reset; then run recovery_from_flash; else if test ${reboot_mode} = update; then run update; else if test ${reboot_mode} = fastboot; then fastboot; else if test ${reboot_mode} = cold_boot; then run demomode_enter_key; run demomode_exit_key; run fastboot_key; run recovery_key; run try_auto_burn; fi;fi;fi;fi; run set_demomode;"); + } + + return 0; +} +#endif + +#ifdef CONFIG_AML_TINY_USBTOOL +int usb_get_update_result(void) +{ + unsigned long upgrade_step; + upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16); + printf("upgrade_step = %d\n", (int)upgrade_step); + if (upgrade_step == 1) + { + run_command("defenv", 1); + run_command("setenv upgrade_step 2", 1); + run_command("saveenv", 1); + return 0; + } + else + { + return -1; + } +} +#endif + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4); +#endif +} + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + /* + * read board hw id + * set and select the dts according the board hw id. + * + * hwid = 1 p321 v1 + * hwid = 2 p321 v2 + */ + unsigned int hwid = 1; + char loc_name[64] = {0}; + + /* read hwid */ + hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF; + + printf("checkhw: hwid = %d\n", hwid); + + + switch (hwid) { + case 1: + strcpy(loc_name, "txl_p321_v1\0"); + break; + case 2: + strcpy(loc_name, "txl_p321_v2\0"); + break; + default: + strcpy(loc_name, "txl_p321_v1"); + break; + } + strcpy(name, loc_name); + setenv("aml_dt", loc_name); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "aml_dt", + "firstboot", + "lock", + "upgrade_step", + + NULL//Keep NULL be last to tell END +}; diff --git a/board/harman/atom_v1/avb2_kpub.c b/board/harman/atom_v1/avb2_kpub.c new file mode 100644 index 0000000..ba50d78 --- a/dev/null +++ b/board/harman/atom_v1/avb2_kpub.c @@ -0,0 +1,54 @@ +#ifdef CONFIG_AVB2_KPUB_VENDOR +const char avb2_kpub_vendor[520] = { + 0x00, 0x00, 0x08, 0x00, 0xb8, 0xb4, 0x90, 0x29, 0xb4, 0x85, 0x71, + 0xda, 0x54, 0x63, 0xa4, 0xcb, 0x80, 0xe6, 0xab, 0x30, 0x48, 0x53, + 0xc8, 0xd0, 0x2b, 0xab, 0x28, 0x4e, 0xb2, 0x1f, 0x30, 0xf3, 0xed, + 0xb1, 0x16, 0x7d, 0x2a, 0x4e, 0xa0, 0xc6, 0x16, 0x98, 0xbc, 0x7d, + 0x18, 0x36, 0x46, 0x80, 0x90, 0x31, 0x66, 0x66, 0xf3, 0xd3, 0x7d, + 0x4c, 0x64, 0x1b, 0x92, 0xa6, 0x88, 0x22, 0x53, 0x0d, 0x0d, 0x9f, + 0x22, 0x1e, 0x12, 0xc3, 0x74, 0xbb, 0x75, 0xaa, 0x6e, 0x0e, 0x89, + 0x29, 0x98, 0x70, 0x9f, 0x04, 0xfb, 0x03, 0x31, 0xba, 0x55, 0x1f, + 0x6c, 0x6a, 0xd0, 0xf2, 0xae, 0x72, 0xce, 0x8b, 0x05, 0x21, 0x49, + 0x3b, 0x6a, 0xb8, 0xea, 0x84, 0x1c, 0xba, 0x02, 0x2e, 0x7a, 0x8f, + 0xc6, 0x7f, 0x57, 0x88, 0xb9, 0xf6, 0xca, 0x50, 0x82, 0x07, 0x2d, + 0xb4, 0xd3, 0xcf, 0x7c, 0x17, 0xd2, 0x4e, 0x1c, 0xe9, 0xdc, 0x66, + 0x24, 0xec, 0x45, 0x77, 0x0c, 0x83, 0x67, 0xb3, 0xf8, 0xe7, 0xd6, + 0xc7, 0x80, 0x48, 0x89, 0x33, 0x4e, 0xe2, 0x67, 0xf7, 0x36, 0xa4, + 0x1a, 0xcb, 0xd6, 0xca, 0xb6, 0xac, 0xa1, 0x66, 0x26, 0x14, 0x25, + 0x42, 0x18, 0xb7, 0xb8, 0x55, 0xa3, 0x80, 0x45, 0x1c, 0xb9, 0x4e, + 0x32, 0x95, 0x0d, 0xf4, 0x4d, 0xda, 0x69, 0xfa, 0x55, 0x1a, 0xfa, + 0xea, 0x44, 0x94, 0xba, 0x86, 0xfb, 0x84, 0x5d, 0x31, 0xab, 0x37, + 0xea, 0x54, 0xba, 0x72, 0xcd, 0x7a, 0x1c, 0xad, 0xab, 0x36, 0x32, + 0xdb, 0x75, 0x42, 0x1f, 0x4e, 0x4b, 0xca, 0x8b, 0x8f, 0xd3, 0x93, + 0xab, 0x7f, 0x25, 0xbd, 0xc0, 0x89, 0x89, 0xd9, 0xb6, 0xfa, 0x20, + 0xc9, 0x8d, 0xf4, 0x26, 0xaa, 0x90, 0x16, 0xd3, 0xca, 0x4f, 0xb7, + 0x6f, 0x62, 0x56, 0x8d, 0x2f, 0xa0, 0x27, 0x83, 0xf9, 0xcc, 0x9d, + 0xb2, 0xfd, 0xfc, 0xa6, 0xb4, 0x31, 0xfc, 0x39, 0xc3, 0xf3, 0xe7, + 0x90, 0xb9, 0x40, 0x50, 0xde, 0x48, 0xd7, 0x45, 0xab, 0xc5, 0xd2, + 0xcf, 0xc7, 0x8e, 0x56, 0x6f, 0xa1, 0x01, 0xed, 0x62, 0x6e, 0x0f, + 0xb5, 0x43, 0x89, 0xf2, 0xfd, 0xe6, 0xcb, 0x33, 0x4e, 0x8e, 0x57, + 0x42, 0xf4, 0x2b, 0xe1, 0x19, 0xec, 0x30, 0xcd, 0xe2, 0xf9, 0x8e, + 0xcd, 0x17, 0xe8, 0x8c, 0x21, 0x8d, 0xd5, 0x62, 0xab, 0x14, 0x50, + 0xcd, 0x70, 0x91, 0xe7, 0xd9, 0x67, 0x9a, 0xb3, 0xd6, 0x96, 0xe1, + 0x7a, 0xfc, 0x1a, 0xc4, 0x4d, 0x5a, 0xcf, 0x9d, 0xc1, 0x31, 0x71, + 0xc0, 0x53, 0x91, 0xa1, 0x94, 0xf0, 0xf9, 0xce, 0x1b, 0x59, 0x40, + 0xd3, 0x52, 0xba, 0x2b, 0x67, 0xe0, 0x24, 0x4d, 0x2e, 0x96, 0x2c, + 0x27, 0x6a, 0xac, 0xbf, 0x92, 0xd2, 0xf1, 0x4f, 0x42, 0x13, 0x6d, + 0xfb, 0xe3, 0xa4, 0x2c, 0x9c, 0x37, 0x90, 0x7c, 0xb5, 0x3b, 0xe8, + 0x30, 0xf2, 0x8e, 0x82, 0x45, 0x43, 0xc8, 0x70, 0xd2, 0x4b, 0xd6, + 0x4c, 0x73, 0x5e, 0xf9, 0xa8, 0x9c, 0x19, 0xc7, 0x71, 0xc3, 0xbd, + 0xc1, 0x25, 0x5e, 0xd3, 0xbc, 0xe8, 0xda, 0x2e, 0x4c, 0x90, 0xaa, + 0xad, 0x03, 0x00, 0x11, 0xb9, 0xae, 0x07, 0xa4, 0x95, 0x7b, 0x4d, + 0x90, 0xfd, 0x98, 0x01, 0xa1, 0x49, 0xe2, 0x10, 0x38, 0x4d, 0x2e, + 0x99, 0xa6, 0x90, 0x88, 0x4e, 0xbb, 0x63, 0x0e, 0x9f, 0x39, 0x41, + 0xc5, 0xd1, 0x70, 0x5e, 0x5e, 0x61, 0x71, 0x5b, 0x6b, 0xb3, 0x3f, + 0x17, 0x35, 0x03, 0x8a, 0x28, 0xff, 0xaa, 0x81, 0x7e, 0x42, 0x6b, + 0xa0, 0xb9, 0x6c, 0x0d, 0x2d, 0xc9, 0xec, 0xcc, 0x7f, 0x82, 0x8a, + 0xf1, 0xbf, 0x43, 0x74, 0x7b, 0x06, 0x2c, 0x62, 0xcf, 0x19, 0xb9, + 0x36, 0xc3, 0x76, 0xc0, 0x73, 0x5c, 0xe6, 0xd7, 0x5f, 0x6d, 0x8d, + 0x7f, 0xec, 0x86, 0xbf, 0xab, 0x5a, 0xbe, 0xf7, 0xda, 0xe2, 0x8d, + 0x04, 0x7f, 0x1f +}; + +const int avb2_kpub_vendor_len = sizeof(avb2_kpub_vendor) / sizeof(char); +#endif /* CONFIG_AVB2_KPUB_VENDOR */ diff --git a/board/harman/atom_v1/config.mk b/board/harman/atom_v1/config.mk new file mode 100644 index 0000000..8a583ac --- a/dev/null +++ b/board/harman/atom_v1/config.mk @@ -0,0 +1,12 @@ +ifdef CONFIG_AVB2_KPUB_DEFAULT_VENDOR +PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_DEFAULT_VENDOR=1 +PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1 +endif + +ifdef CONFIG_AVB2_KPUB_VENDOR +PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1 +else +# Default Atom build to support both default and vendor public key +PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_DEFAULT_VENDOR=1 +PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1 +endif diff --git a/board/harman/atom_v1/eth_setup.c b/board/harman/atom_v1/eth_setup.c new file mode 100644 index 0000000..8e0ec94 --- a/dev/null +++ b/board/harman/atom_v1/eth_setup.c @@ -0,0 +1,51 @@ + +/* + * board/harman/atom_v1/eth_setup.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <libfdt.h> +#include <asm/arch/eth_setup.h> +/* + * + *setup eth device board socket + * + */ +struct eth_board_socket* eth_board_setup(char *name){ + struct eth_board_socket* new_board; + new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket)); + if (NULL == new_board) return NULL; + if (name != NULL) { + new_board->name=(char*)malloc(strlen(name)); + strncpy(new_board->name,name,strlen(name)); + }else{ + new_board->name="gxb"; + } + + new_board->eth_pinmux_setup=NULL ; + new_board->eth_clock_configure=NULL; + new_board->eth_hw_reset=NULL; + return new_board; +} +//pinmux HHI_GCLK_MPEG1[bit 3] +// diff --git a/board/harman/atom_v1/firmware/board_init.c b/board/harman/atom_v1/firmware/board_init.c new file mode 100644 index 0000000..7e73134 --- a/dev/null +++ b/board/harman/atom_v1/firmware/board_init.c @@ -0,0 +1,65 @@ + +/* + * board/harman/atom_v1/firmware/board_init.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include "power.c" + +/* bl2 customer code */ + +#define PNL_PREG_PAD_GPIO1_EN_N 0x0f +#define PNL_PREG_PAD_GPIO1_O 0x10 +#define PNL_PREG_PAD_GPIO1_I 0x11 + +#define PNL_PREG_PAD_GPIO3_EN_N 0x15 +#define PNL_PREG_PAD_GPIO3_O 0x16 +#define PNL_PREG_PAD_GPIO3_I 0x17 + +#define PNL_REG_BASE (0xff634400L) +#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2)) +#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg)) +#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value); +static void panel_power_init(void) +{ + serial_puts("init panel power\n"); + + /* panel: GPIOZ_13/8/9 */ /* remove GPIOZ_10 for 2D/3D special case */ + PNL_REG_W(PNL_PREG_PAD_GPIO3_O, + (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((0x3 << 8) | (1 << 13)))); + PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N, + (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((0x3 << 8) | (1 << 13)))); + /* panel: GPIOH_4/5 */ + PNL_REG_W(PNL_PREG_PAD_GPIO1_O, + (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x3 << 24))); + PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N, + (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x3 << 24))); + + /* backlight: GPIOZ_4/6/7 */ + PNL_REG_W(PNL_PREG_PAD_GPIO3_O, + (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 4) | (0x3 << 6)))); + PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N, + (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 4) | (0x3 << 6)))); +} + +void board_init(void) +{ + power_init(0); + + panel_power_init(); +}
\ No newline at end of file diff --git a/board/harman/atom_v1/firmware/power.c b/board/harman/atom_v1/firmware/power.c new file mode 100644 index 0000000..cdfe60a --- a/dev/null +++ b/board/harman/atom_v1/firmware/power.c @@ -0,0 +1,254 @@ + +/* + * board/harman/atom_v1/firmware/power.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include "config.h" +#include <serial.h> +//#include <stdio.h> + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static int pwm_voltage_table[][2] = { + { 0x1c0000, 860}, + { 0x1b0001, 870}, + { 0x1a0002, 880}, + { 0x190003, 890}, + { 0x180004, 900}, + { 0x170005, 910}, + { 0x160006, 920}, + { 0x150007, 930}, + { 0x140008, 940}, + { 0x130009, 950}, + { 0x12000a, 960}, + { 0x11000b, 970}, + { 0x10000c, 980}, + { 0x0f000d, 990}, + { 0x0e000e, 1000}, + { 0x0d000f, 1010}, + { 0x0c0010, 1020}, + { 0x0b0011, 1030}, + { 0x0a0012, 1040}, + { 0x090013, 1050}, + { 0x080014, 1060}, + { 0x070015, 1070}, + { 0x060016, 1080}, + { 0x050017, 1090}, + { 0x040018, 1100}, + { 0x030019, 1110}, + { 0x02001a, 1120}, + { 0x01001b, 1130}, + { 0x00001c, 1140} +}; +static int pwm_voltage_table_ee[][2] = { + { 0x1c0000, 810}, + { 0x1b0001, 820}, + { 0x1a0002, 830}, + { 0x190003, 840}, + { 0x180004, 850}, + { 0x170005, 860}, + { 0x160006, 870}, + { 0x150007, 880}, + { 0x140008, 890}, + { 0x130009, 900}, + { 0x12000a, 910}, + { 0x11000b, 920}, + { 0x10000c, 930}, + { 0x0f000d, 940}, + { 0x0e000e, 950}, + { 0x0d000f, 960}, + { 0x0c0010, 970}, + { 0x0b0011, 980}, + { 0x0a0012, 990}, + { 0x090013, 1000}, + { 0x080014, 1010}, + { 0x070015, 1020}, + { 0x060016, 1030}, + { 0x050017, 1040}, + { 0x040018, 1050}, + { 0x030019, 1060}, + { 0x02001a, 1070}, + { 0x01001b, 1080}, + { 0x00001c, 1090} +}; + + +#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2)))) +#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2)))) +#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2)))) + +#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2)))) +#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2)))) + +#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2)))) +#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2)))) + +enum pwm_id { + pwm_a = 0, + pwm_ao_b, +}; + +unsigned int _get_time(void) +{ + return P_EE_TIMER_E; +} + +void _udelay_(unsigned int us) +{ + unsigned int t0 = _get_time(); + + while (_get_time() - t0 <= us) + ; +} + +void pwm_init(int id) +{ + unsigned int reg; + int vol; + + switch (id) { + case pwm_a: + reg = P_PWM_MISC_REG_AB; + reg &= ~(0x7f << 8); + reg |= ((1 << 15) | (1 << 0)); + P_PWM_MISC_REG_AB = reg; + /* + * default set to max voltage + */ + //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0]; + reg = P_PIN_MUX_REG3; + reg &= ~((1 << 21) | 1 << 12); + P_PIN_MUX_REG3 = reg; + reg = P_PIN_MUX_REG10; + reg &= ~(1 << 16); + P_PIN_MUX_REG10 = reg;//clear reg10 + + reg = P_PIN_MUX_REG4; + reg &= ~(1 << 26); + reg |= (1 << 17); + P_PIN_MUX_REG4 = reg; + break; + + case pwm_ao_b: + reg = readl(AO_PWM_MISC_REG_AB); + reg &= ~(0x7f << 16); + reg |= ((1 << 23) | (1 << 1)); + writel(reg, AO_PWM_MISC_REG_AB); + /* + * default set to max voltage + */ + //writel( pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0],AO_PWM_PWM_B); + reg = AO_PIN_MUX_REG; + reg |= (1 << 3); + AO_PIN_MUX_REG = reg; + + break; + default: + break; + } + + _udelay_(200); +} +/* +void pwm_set_voltage(unsigned int id, unsigned int voltage) +{ + int to; + + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= voltage) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) { + to = ARRAY_SIZE(pwm_voltage_table) - 1; + } + switch (id) { + case pwm_a: + P_PWM_PWM_A = pwm_voltage_table[to][0]; + break; + + case pwm_ao_b: + writel(pwm_voltage_table[to][0], AO_PWM_PWM_B); + break; + default: + break; + } + _udelay_(200); +} +*/ +void pwm_set_voltage(unsigned int id, unsigned int voltage) +{ + int to; + + switch (id) { + case pwm_a: + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= voltage) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) { + to = ARRAY_SIZE(pwm_voltage_table) - 1; + } + P_PWM_PWM_A = pwm_voltage_table[to][0]; + break; + + case pwm_ao_b: + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) { + if (pwm_voltage_table_ee[to][1] >= voltage) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) { + to = ARRAY_SIZE(pwm_voltage_table_ee) - 1; + } + writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B); + break; + default: + break; + } + _udelay_(200); +} + +void power_init(int mode) +{ + unsigned int reg; + serial_puts("set vcck to "); + serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE); + serial_puts(" mv\n"); + pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE); + serial_puts("set vddee to "); + serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE); + serial_puts(" mv\n"); + pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE); + pwm_init(pwm_a); + pwm_init(pwm_ao_b); + serial_puts("set AO 2/10/11 to high\n "); + reg = readl(AO_GPIO_O_EN_N); + reg &= ~((1 << 2)|(1 << 10)|(1 << 11)); + reg |= ((1 << 18)|(1 << 26)|(1 << 27)); + writel(reg, AO_GPIO_O_EN_N); + serial_puts("set test_n to high\n "); + reg = readl(AO_SEC_REG0); + reg |= (1 << 0); + writel(reg, AO_SEC_REG0); + reg = readl(AO_GPIO_O_EN_N); + reg |= (1 << 31); + writel(reg, AO_GPIO_O_EN_N); +} diff --git a/board/harman/atom_v1/firmware/scp_task/dvfs_board.c b/board/harman/atom_v1/firmware/scp_task/dvfs_board.c new file mode 100644 index 0000000..18ee6db --- a/dev/null +++ b/board/harman/atom_v1/firmware/scp_task/dvfs_board.c @@ -0,0 +1,194 @@ + +/* + * board/harman/atom_v1/firmware/scp_task/dvfs_board.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ +/* +int pwm_voltage_table[ ][2] = { + { 0x1c0000, 860}, + { 0x1b0001, 870}, + { 0x1a0002, 880}, + { 0x190003, 890}, + { 0x180004, 900}, + { 0x170005, 910}, + { 0x160006, 920}, + { 0x150007, 930}, + { 0x140008, 940}, + { 0x130009, 950}, + { 0x12000a, 960}, + { 0x11000b, 970}, + { 0x10000c, 980}, + { 0x0f000d, 990}, + { 0x0e000e, 1000}, + { 0x0d000f, 1010}, + { 0x0c0010, 1020}, + { 0x0b0011, 1030}, + { 0x0a0012, 1040}, + { 0x090013, 1050}, + { 0x080014, 1060}, + { 0x070015, 1070}, + { 0x060016, 1080}, + { 0x050017, 1090}, + { 0x040018, 1100}, + { 0x030019, 1110}, + { 0x02001a, 1120}, + { 0x01001b, 1130}, + { 0x00001c, 1140} +}; +*/ +#include "pwm_ctrl.h" + +#define CHIP_ADJUST 20 +#define RIPPLE_ADJUST 30 +struct scpi_opp_entry cpu_dvfs_tbl[] = { + DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS(1200000000, 960+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS(1296000000, 1000+CHIP_ADJUST+RIPPLE_ADJUST), + DVFS(1416000000, 1080+CHIP_ADJUST+RIPPLE_ADJUST), +}; + + +#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2)))) +#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2)))) +#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2)))) + +#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2)))) +#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2)))) + + +enum pwm_id { + pwm_a = 0, +}; + + +void pwm_init(int id) +{ + /* + * TODO: support more pwm controllers, right now only support PWM_B + */ + unsigned int reg; + reg = P_PWM_MISC_REG_AB; + reg &= ~(0x7f << 8); + reg |= ((1 << 15) | (1 << 0)); + P_PWM_MISC_REG_AB = reg; + /* + * default set to max voltage + */ + //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0]; + reg = P_PIN_MUX_REG3; + reg &= ~((1 << 21) | 1 << 12); + P_PIN_MUX_REG3 = reg; + + reg = P_PIN_MUX_REG10; + reg &= ~(1 << 16); + P_PIN_MUX_REG10 = reg;//clear reg10 + reg = P_PIN_MUX_REG4; + reg &= ~(1 << 26); // clear PWM_VS + reg |= (1 << 17); // enable PWM_A + P_PIN_MUX_REG4 = reg; + + + _udelay(200); +} + +int dvfs_get_voltage(void) +{ + int i = 0; + unsigned int reg_val; + + reg_val = P_PWM_PWM_A; + for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) { + if (pwm_voltage_table[i][0] == reg_val) { + return i; + } + } + if (i >= ARRAY_SIZE(pwm_voltage_table)) { + return -1; + } + return -1; +} + +void set_dvfs(unsigned int domain, unsigned int index) +{ + int cur, to; + static int init_flag = 0; + + if (!init_flag) { + pwm_init(pwm_a); + init_flag = 1; + } + cur = dvfs_get_voltage(); + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) { + to = ARRAY_SIZE(pwm_voltage_table) - 1; + } + if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) { + P_PWM_PWM_A = pwm_voltage_table[to][0]; + _udelay(200); + return ; + } + while (cur != to) { + /* + * if target step is far away from current step, don't change + * voltage by one-step-done. You should change voltage step by + * step to make sure voltage output is stable + */ + if (cur < to) { + if (cur < to - 3) { + cur += 3; + } else { + cur = to; + } + } else { + if (cur > to + 3) { + cur -= 3; + } else { + cur = to; + } + } + P_PWM_PWM_A = pwm_voltage_table[cur][0]; + _udelay(100); + } + _udelay(200); +} +void get_dvfs_info_board(unsigned int domain, + unsigned char *info_out, unsigned int *size_out) +{ + unsigned int cnt; + cnt = ARRAY_SIZE(cpu_dvfs_tbl); + + buf_opp.latency = 200; + buf_opp.count = cnt; + memset(&buf_opp.opp[0], 0, + MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry)); + + memcpy(&buf_opp.opp[0], cpu_dvfs_tbl , + cnt * sizeof(struct scpi_opp_entry)); + + memcpy(info_out, &buf_opp, sizeof(struct scpi_opp)); + *size_out = sizeof(struct scpi_opp); + return; +} diff --git a/board/harman/atom_v1/firmware/scp_task/pwm_ctrl.h b/board/harman/atom_v1/firmware/scp_task/pwm_ctrl.h new file mode 100644 index 0000000..57e503b --- a/dev/null +++ b/board/harman/atom_v1/firmware/scp_task/pwm_ctrl.h @@ -0,0 +1,37 @@ +/* +*board/harman/atom_v1/firmware/scp_task/pwm_vol_tab.h +*table for Dynamic Voltage/Frequency Scaling +*/ + + +static int pwm_voltage_table[][2] = { + { 0x1c0000, 860}, + { 0x1b0001, 870}, + { 0x1a0002, 880}, + { 0x190003, 890}, + { 0x180004, 900}, + { 0x170005, 910}, + { 0x160006, 920}, + { 0x150007, 930}, + { 0x140008, 940}, + { 0x130009, 950}, + { 0x12000a, 960}, + { 0x11000b, 970}, + { 0x10000c, 980}, + { 0x0f000d, 990}, + { 0x0e000e, 1000}, + { 0x0d000f, 1010}, + { 0x0c0010, 1020}, + { 0x0b0011, 1030}, + { 0x0a0012, 1040}, + { 0x090013, 1050}, + { 0x080014, 1060}, + { 0x070015, 1070}, + { 0x060016, 1080}, + { 0x050017, 1090}, + { 0x040018, 1100}, + { 0x030019, 1110}, + { 0x02001a, 1120}, + { 0x01001b, 1130}, + { 0x00001c, 1140} +}; diff --git a/board/harman/atom_v1/firmware/scp_task/pwr_ctrl.c b/board/harman/atom_v1/firmware/scp_task/pwr_ctrl.c new file mode 100644 index 0000000..c002d85 --- a/dev/null +++ b/board/harman/atom_v1/firmware/scp_task/pwr_ctrl.c @@ -0,0 +1,412 @@ + +/* + * board/harman/atom_v1/firmware/scp_task/pwr_ctrl.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + + +#ifdef CONFIG_CEC_WAKEUP +#include <asm/arch/cec_tx_reg.h> +#include <hdmi_cec_arc.h> +#include <amlogic/aml_cec.h> +#endif +#include <gpio-gxbb.h> +#include "pwm_ctrl.h" + +#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2)))) +#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2)))) +#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2)))) + +#define ON 1 +#define OFF 0 + +static int pwm_voltage_table_ee[][2] = { + { 0x1c0000, 810}, + { 0x1b0001, 820}, + { 0x1a0002, 830}, + { 0x190003, 840}, + { 0x180004, 850}, + { 0x170005, 860}, + { 0x160006, 870}, + { 0x150007, 880}, + { 0x140008, 890}, + { 0x130009, 900}, + { 0x12000a, 910}, + { 0x11000b, 920}, + { 0x10000c, 930}, + { 0x0f000d, 940}, + { 0x0e000e, 950}, + { 0x0d000f, 960}, + { 0x0c0010, 970}, + { 0x0b0011, 980}, + { 0x0a0012, 990}, + { 0x090013, 1000}, + { 0x080014, 1010}, + { 0x070015, 1020}, + { 0x060016, 1030}, + { 0x050017, 1040}, + { 0x040018, 1050}, + { 0x030019, 1060}, + { 0x02001a, 1070}, + { 0x01001b, 1080}, + { 0x00001c, 1090} +}; + + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static void power_on_ddr(void); +enum pwm_id { + pwm_a = 0, + pwm_b, + pwm_c, + pwm_d, + pwm_e, + pwm_f, + pwm_ao_a, + pwm_ao_b, +}; + +#if 0 +static void power_switch_to_ee(unsigned int pwr_ctrl) +{ + if (pwr_ctrl == ON) { + writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0); + _udelay(1000); + writel(readl(AO_RTI_PWR_CNTL_REG0) + & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0); + } else { + writel(readl(AO_RTI_PWR_CNTL_REG0) + | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0); + + writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)), + AO_RTI_PWR_CNTL_REG0); + + } +} +#endif + +static void pwm_set_voltage(unsigned int id, unsigned int voltage) +{ + int to; + switch (id) { + case pwm_a: + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) { + if (pwm_voltage_table[to][1] >= voltage) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table)) { + to = ARRAY_SIZE(pwm_voltage_table) - 1; + } + uart_puts("set vcck to 0x"); + uart_put_hex(to, 16); + uart_puts("mv\n"); + P_PWM_PWM_A = pwm_voltage_table[to][0]; + break; + + case pwm_ao_b: + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) { + if (pwm_voltage_table_ee[to][1] >= voltage) { + break; + } + } + if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) { + to = ARRAY_SIZE(pwm_voltage_table_ee) - 1; + } + uart_puts("set vddee to 0x"); + uart_put_hex(to, 16); + uart_puts("mv\n"); + P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0]; + break; + default: + break; + } + _udelay(200); +} + +static void power_off_3v3_5v(void) +{ + aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0); + aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0); +} + +static void power_on_3v3_5v(void) +{ + aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0); + aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18); +} + +static void power_off_usb5v(void) +{ + aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0); + aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0); +} + +static void power_on_usb5v(void) +{ + aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0); + aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26); +} + +static void power_off_at_clk81(void) +{ + +} + +static void power_on_at_clk81(unsigned int suspend_from) +{ + +} + +static void power_off_at_24M(void) +{ +} +static void power_on_at_24M(void) +{ +} + +static void power_off_ddr(void) +{ + aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0); + aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0); +} + +static void power_on_ddr(void) +{ + aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0); + aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27); + _udelay(10000); +} + +/*timing request: + *poweroff vddio3.3v-->delay 20ms-->poweroff vddee + */ +static void power_off_vddee(void) +{ + unsigned int val; + + /*set test n output low level */ + _udelay(10000);/*the other 10ms in power_off_at_32k()*/ + val = readl(AO_GPIO_O_EN_N); + val &= ~(0x1 << 31); + writel(val, AO_GPIO_O_EN_N); + +} + +/*timing request: + *poweron vddee-->delay 20ms-->poweron vddio3.3v + */ +static void power_on_vddee(void) +{ + unsigned int val; + + /*set test n output high level */ + val = readl(AO_GPIO_O_EN_N); + val |= 0x1 << 31; + writel(val, AO_GPIO_O_EN_N); + _udelay(10000);/*the other 10ms in power_on_at_32k()*/ +} + +static void power_off_at_32k(unsigned int suspend_from) +{ + power_off_usb5v(); + _udelay(5000); + power_off_3v3_5v(); + _udelay(5000); + pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */ + if (suspend_from == SYS_POWEROFF) { + power_off_vddee(); + power_off_ddr(); + } +} + +static void power_on_at_32k(unsigned int suspend_from) +{ + if (suspend_from == SYS_POWEROFF) + power_on_vddee(); + pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE); + _udelay(10000); + power_on_3v3_5v(); + _udelay(10000); + pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE); + _udelay(10000); + _udelay(10000); + power_on_usb5v(); + + if (suspend_from == SYS_POWEROFF) + power_on_ddr(); +} + +void get_wakeup_source(void *response, unsigned int suspend_from) +{ + struct wakeup_info *p = (struct wakeup_info *)response; + unsigned val; + unsigned i = 0; + + p->status = RESPONSE_OK; + p->gpio_info_count = i; + val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC | + ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC); +#ifdef CONFIG_CEC_WAKEUP + val |= CECB_WAKEUP_SRC; +#endif + +#ifdef CONFIG_BT_WAKEUP + { + struct wakeup_gpio_info *gpio; + /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20] */ + gpio = &(p->gpio_info[i]); + gpio->wakeup_id = BT_WAKEUP_SRC; + gpio->gpio_in_idx = GPIOAO_12; + gpio->gpio_in_ao = 1; + gpio->gpio_out_idx = -1; + gpio->gpio_out_ao = -1; + gpio->irq = IRQ_AO_GPIO0_NUM; + gpio->trig_type = GPIO_IRQ_FALLING_EDGE; + p->gpio_info_count = ++i; + } +#endif + p->sources = val; + +} +void wakeup_timer_setup(void) +{ + /* 1ms resolution*/ + unsigned value; + value = readl(P_ISA_TIMER_MUX); + value |= ((0x3<<0) | (0x1<<12) | (0x1<<16)); + writel(value, P_ISA_TIMER_MUX); + /*10ms generate an interrupt*/ + writel(9, P_ISA_TIMERA); +} +void wakeup_timer_clear(void) +{ + unsigned value; + value = readl(P_ISA_TIMER_MUX); + value &= ~((0x1<<12) | (0x1<<16)); + writel(value, P_ISA_TIMER_MUX); +} +static unsigned int detect_key(unsigned int suspend_from) +{ + int exit_reason = 0; + unsigned int time_out = readl(AO_DEBUG_REG2); + unsigned time_out_ms = time_out*100; + unsigned char adc_key_cnt = 0; + unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE; + /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */ + + /* setup wakeup resources*/ + /*auto suspend: timerA 10ms resolution*/ + if (time_out_ms != 0) + wakeup_timer_setup(); + init_remote(); + saradc_enable(); +#ifdef CONFIG_CEC_WAKEUP + if (hdmi_cec_func_config & 0x1) { + cec_hw_reset(); + cec_node_init(); + } +#endif + + /* *wakeup_en = 1;*/ + do { +#ifdef CONFIG_CEC_WAKEUP + if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) { + irq[IRQ_AO_CECB] = 0xFFFFFFFF; +// if (suspend_from == SYS_POWEROFF) +// continue; + if (cec_msg.log_addr) { + if (hdmi_cec_func_config & 0x1) { + cec_handler(); + if (cec_msg.cec_power == 0x1) { + /*cec power key*/ + exit_reason = CEC_WAKEUP; + break; + } + } + } else if (hdmi_cec_func_config & 0x1) + cec_node_init(); + } +#endif + if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) { + irq[IRQ_TIMERA] = 0xFFFFFFFF; + if (time_out_ms != 0) + time_out_ms--; + if (time_out_ms == 0) { + wakeup_timer_clear(); + exit_reason = AUTO_WAKEUP; + } + } + if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) { + irq[IRQ_AO_TIMERA] = 0xFFFFFFFF; + if (check_adc_key_resume()) { + adc_key_cnt++; + /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/ + if (2 == adc_key_cnt) + exit_reason = POWER_KEY_WAKEUP; + } else { + adc_key_cnt = 0; + } + } +#ifdef CONFIG_BT_WAKEUP + if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) { + irq[IRQ_AO_GPIO0] = 0xFFFFFFFF; + if (!(readl(P_AO_GPIO_O_EN_N) + & (0x01 << 13)) && (readl(P_AO_GPIO_O_EN_N) + & (0x01 << 29)) && + !(readl(P_AO_GPIO_I) + & (0x01 << 12))){ + uart_puts("bt wakeup pin\n"); + exit_reason = BT_WAKEUP; + } + } +#endif + + if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) { + irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF; + if (remote_detect_key()) + exit_reason = REMOTE_WAKEUP; + } + if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) { + irq[IRQ_ETH_PHY] = 0xFFFFFFFF; + exit_reason = ETH_PHY_WAKEUP; + } + if (exit_reason) + break; + else + asm volatile("wfi"); + } while (1); + + saradc_disable(); + + return exit_reason; +} + +static void pwr_op_init(struct pwr_op *pwr_op) +{ + pwr_op->power_off_at_clk81 = power_off_at_clk81; + pwr_op->power_on_at_clk81 = power_on_at_clk81; + pwr_op->power_off_at_24M = power_off_at_24M; + pwr_op->power_on_at_24M = power_on_at_24M; + pwr_op->power_off_at_32k = power_off_at_32k; + pwr_op->power_on_at_32k = power_on_at_32k; + + pwr_op->detect_key = detect_key; + pwr_op->get_wakeup_source = get_wakeup_source; +} diff --git a/board/harman/atom_v1/firmware/timing.c b/board/harman/atom_v1/firmware/timing.c new file mode 100644 index 0000000..9995646 --- a/dev/null +++ b/board/harman/atom_v1/firmware/timing.c @@ -0,0 +1,570 @@ + +/* + * board/harman/atom_v1/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* DDR freq range */ +#define CONFIG_DDR_CLK_LOW 375 +#define CONFIG_DDR_CLK_HIGH 1500 +/* DON'T OVER THESE RANGE */ +#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH) + #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n" +#endif + +/* CPU freq range */ +#define CONFIG_CPU_CLK_LOW 600 +#define CONFIG_CPU_CLK_HIGH 2000 +/* DON'T OVER THESE RANGE */ +#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH) + #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n" +#endif + +#define DDR3_DRV_40OHM 0 +#define DDR3_DRV_34OHM 1 +#define DDR3_ODT_0OHM 0 +#define DDR3_ODT_60OHM 1 +#define DDR3_ODT_120OHM 2 +#define DDR3_ODT_40OHM 3 +#define DDR3_ODT_20OHM 4 +#define DDR3_ODT_30OHM 5 + +/* lpddr2 drv odt */ +#define LPDDR2_DRV_34OHM 1 +#define LPDDR2_DRV_40OHM 2 +#define LPDDR2_DRV_48OHM 3 +#define LPDDR2_DRV_60OHM 4 +#define LPDDR2_DRV_80OHM 6 +#define LPDDR2_DRV_120OHM 7 +#define LPDDR2_ODT_0OHM 0 + +/* lpddr3 drv odt */ +#define LPDDR3_DRV_34OHM 1 +#define LPDDR3_DRV_40OHM 2 +#define LPDDR3_DRV_48OHM 3 +#define LPDDR3_DRV_60OHM 4 +#define LPDDR3_DRV_80OHM 6 +#define LPDDR3_DRV_34_40OHM 9 +#define LPDDR3_DRV_40_48OHM 10 +#define LPDDR3_DRV_34_48OHM 11 +#define LPDDR3_ODT_0OHM 0 +#define LPDDR3_ODT_60OHM 1 +#define LPDDR3_ODT_12OHM 2 +#define LPDDR3_ODT_240HM 3 + +#define DDR4_DRV_34OHM 0 +#define DDR4_DRV_48OHM 1 +#define DDR4_ODT_0OHM 0 +#define DDR4_ODT_60OHM 1 +#define DDR4_ODT_120OHM 2 +#define DDR4_ODT_40OHM 3 +#define DDR4_ODT_240OHM 4 +#define DDR4_ODT_48OHM 5 +#define DDR4_ODT_80OHM 6 +#define DDR4_ODT_34OHM 7 + +#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)) +#define CFG_DDR_DRV DDR3_DRV_34OHM +#define CFG_DDR_ODT DDR3_ODT_60OHM +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2) +#define CFG_DDR_DRV LPDDR2_DRV_48OHM +#define CFG_DDR_ODT DDR3_ODT_120OHM +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define CFG_DDR_DRV LPDDR3_DRV_48OHM +#define CFG_DDR_ODT LPDDR3_ODT_12OHM +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) +#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect +#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect +#endif + +#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one +#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one + +/* + * these parameters are corresponding to the pcb layout, + * please don't enable this function unless these signals + * has been measured by oscilloscope. + */ +#ifdef CONFIG_DDR_CMD_BDL_TUNE +#define DDR_AC_LCDLR 0 +#define DDR_CK0_BDL 18 +#define DDR_RAS_BDL 18 +#define DDR_CAS_BDL 24 +#define DDR_WE_BDL 21 +#define DDR_BA0_BDL 16 +#define DDR_BA1_BDL 2 +#define DDR_BA2_BDL 13 +#define DDR_ACPDD_BDL 27 +#define DDR_CS0_BDL 27 +#define DDR_CS1_BDL 27 +#define DDR_ODT0_BDL 27 +#define DDR_ODT1_BDL 27 +#define DDR_CKE0_BDL 27 +#define DDR_CKE1_BDL 27 +#define DDR_A0_BDL 14 +#define DDR_A1_BDL 9 +#define DDR_A2_BDL 5 +#define DDR_A3_BDL 18 +#define DDR_A4_BDL 4 +#define DDR_A5_BDL 16 +#define DDR_A6_BDL 1 +#define DDR_A7_BDL 10 +#define DDR_A8_BDL 4 +#define DDR_A9_BDL 7 +#define DDR_A10_BDL 10 +#define DDR_A11_BDL 9 +#define DDR_A12_BDL 6 +#define DDR_A13_BDL 16 +#define DDR_A14_BDL 8 +#define DDR_A15_BDL 27 +#endif + +/* CAUTION!! */ +/* + * For DDR3: + * 7-7-7: CONFIG_DDR_CLK range 375~ 533 + * 9-9-9: CONFIG_DDR_CLK range 533~ 667 + * 11-11-11: CONFIG_DDR_CLK range 667~ 800 + * 12-12-12: CONFIG_DDR_CLK range 800~ 933 + * 13-13-13: CONFIG_DDR_CLK range 933~1066 + * 14-14-14: CONFIG_DDR_CLK range 1066~1200 + */ +ddr_timing_t __ddr_timming[] = { + //ddr3_7_7_7 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_7, + .cfg_ddr_rtp = (6), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (7), + .cfg_ddr_rcd = (7), + .cfg_ddr_ras = (20), + .cfg_ddr_rrd = (6), + .cfg_ddr_rc = (27), + .cfg_ddr_mrd = (4), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (27), + .cfg_ddr_rfc = (160), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (6), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (4), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (4), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (7), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (5), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (4), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (512), + .cfg_ddr_xpdll = (20), + .cfg_ddr_zqcsi = (1000), + }, + //ddr3_9_9_9 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_9, + .cfg_ddr_rtp = (6), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (9), + .cfg_ddr_rcd = (9), + .cfg_ddr_ras = (27), + .cfg_ddr_rrd = (6), + .cfg_ddr_rc = (33), + .cfg_ddr_mrd = (4), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (30), + .cfg_ddr_rfc = (196), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (6), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (4), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (6), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (9), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (7), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (136), + .cfg_ddr_xpdll = (20), + .cfg_ddr_zqcsi = (1000), + }, + //ddr3_11_11_11 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_11, + .cfg_ddr_rtp = (7), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (11), + .cfg_ddr_rcd = (11), + .cfg_ddr_ras = (35), + .cfg_ddr_rrd = (7), + .cfg_ddr_rc = (45), + .cfg_ddr_mrd = (6), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (33), + .cfg_ddr_rfc = (280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (7), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (5), + .cfg_ddr_cke = (4), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (11), + .cfg_ddr_wr = (12), + .cfg_ddr_cwl = (8), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (136), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + }, + //ddr3_13_13_13 + { + .identifier = CONFIG_DDR_TIMMING_DDR3_13, + .cfg_ddr_rtp = (7), + .cfg_ddr_wtr = (7), + .cfg_ddr_rp = (13), + .cfg_ddr_rcd = (13), + .cfg_ddr_ras = (37), + .cfg_ddr_rrd = (7), + .cfg_ddr_rc = (52), + .cfg_ddr_mrd = (6), + .cfg_ddr_mod = (12), + .cfg_ddr_faw = (33), + .cfg_ddr_rfc = (280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (7), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (512), + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (13), + .cfg_ddr_wr = (16), + .cfg_ddr_cwl = (9), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (512), + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = (64), + .cfg_ddr_zqcl = (136), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + }, + /* ddr4 1600 timing */ + { + .identifier = CONFIG_DDR_TIMMING_DDR4_1600, + .cfg_ddr_rtp = (4), + .cfg_ddr_wtr = (6), + .cfg_ddr_rp = (11), + .cfg_ddr_rcd = (11), + .cfg_ddr_ras = (35), + .cfg_ddr_rrd = (4), + .cfg_ddr_rc = (46),//RAS+RP + .cfg_ddr_mrd = (8), + .cfg_ddr_mod = (24), + .cfg_ddr_faw = (28), + .cfg_ddr_rfc = (280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = (8), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (1024), //597 768 1024 + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = (11), + .cfg_ddr_wr = (13), //15NS+1CLK + .cfg_ddr_cwl = (11), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (1024), //597 768 1024 + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = 128, + .cfg_ddr_zqcl = (256), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + .cfg_ddr_tccdl = (5), + }, + /* ddr4 2400 timing */ + { + .identifier = CONFIG_DDR_TIMMING_DDR4_2400, + .cfg_ddr_rtp = 9,//(4), + .cfg_ddr_wtr = 9,//(6), + .cfg_ddr_rp = 15*1.2,//(11), + .cfg_ddr_rcd = 15*1.2,//(11), + .cfg_ddr_ras = 35*1.2,//(35), + .cfg_ddr_rrd = (8), + .cfg_ddr_rc =50*1.2,// (46),//RAS+RP + .cfg_ddr_mrd = (8), + .cfg_ddr_mod = (24), + .cfg_ddr_faw = 35*1.2,//(28), + .cfg_ddr_rfc = 350*1.2,//(280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = 9.5*1.2,//(8), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (1024), //597 768 1024 + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = 15*1.2,// (11), + .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK + .cfg_ddr_cwl = 12,// (11), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (1024), //597 768 1024 + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = 128, + .cfg_ddr_zqcl = (256), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + .cfg_ddr_tccdl = (6), + }, + /* lpddr3 timing */ + { + .identifier = CONFIG_DDR_TIMMING_LPDDR3, + .cfg_ddr_rtp = (4), + .cfg_ddr_wtr = (6), + .cfg_ddr_rp = 15*1.2,//(11), + .cfg_ddr_rcd = 15*1.2,//(11), + .cfg_ddr_ras = 35*1.2,//(35), + .cfg_ddr_rrd = (4), + .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP + .cfg_ddr_mrd = (8), + .cfg_ddr_mod = (24), + .cfg_ddr_faw = 35*1.2,//(28), + .cfg_ddr_rfc = 350*1.2,//(280), + .cfg_ddr_wlmrd = (40), + .cfg_ddr_wlo = 9.5*1.2,//(8), + .cfg_ddr_xs = (512), + .cfg_ddr_xp = (7), + .cfg_ddr_cke = (5), + .cfg_ddr_dllk = (1024), //597 768 1024 + .cfg_ddr_rtodt = (0), + .cfg_ddr_rtw = (7), + .cfg_ddr_refi = (78), + .cfg_ddr_refi_mddr3 = (4), + .cfg_ddr_cl = 15*1.2,// (11), + .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK + .cfg_ddr_cwl = 12,// (11), + .cfg_ddr_al = (0), + .cfg_ddr_exsr = (1024), //597 768 1024 + .cfg_ddr_dqs = (23), + .cfg_ddr_cksre = (15), + .cfg_ddr_cksrx = (15), + .cfg_ddr_zqcs = 128, + .cfg_ddr_zqcl = (256), + .cfg_ddr_xpdll = (23), + .cfg_ddr_zqcsi = (1000), + .cfg_ddr_tccdl = (6), + } +}; + +ddr_set_t __ddr_setting = { + /* common and function defines */ + .ddr_channel_set = CONFIG_DDR_CHANNEL_SET, + .ddr_type = CONFIG_DDR_TYPE, + .ddr_clk = CONFIG_DDR_CLK, + .ddr4_clk = CONFIG_DDR4_CLK, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .ddr_timing_ind = 0, + .ddr_size = CONFIG_DDR_SIZE, + .ddr_pll_ctrl = (0), + .ddr_dmc_ctrl = 0, + .ddr0_addrmap = {0}, + .ddr1_addrmap = {0}, + .ddr_2t_mode = 1, + .ddr_full_test = CONFIG_DDR_FULL_TEST, +#if (0 == CONFIG_DDR_SIZE) + .ddr_size_detect = 1, +#else + .ddr_size_detect = 0, +#endif + .ddr_drv = CFG_DDR_DRV, + .ddr_odt = CFG_DDR_ODT, + .ddr4_drv = CFG_DDR4_DRV, + .ddr4_odt = CFG_DDR4_ODT, + + /* pub defines */ + .t_pub_ptr = { + [0] = ( 6 | (320 << 6) | (80 << 21)), + [1] = (120 | (1000 << 16)), + [2] = 0, + [3] = (20000 | (136 << 20)), + [4] = (1000 | (180 << 16)), + }, //PUB PTR0-3 + .t_pub_odtcr = 0x00030000, + .t_pub_mr = { + (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)), + (0X6|(1<<6)), + 0X20, + 0, + }, + .t_pub_dtpr = {0}, + .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0 + .t_pub_pgcr1 = 0x02004620, //PUB PGCR1 + .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2 + //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2 + .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3 + .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR + .t_pub_aciocr = {0}, //PUB ACIOCRx + .t_pub_dx0gcr = {0}, //PUB DX0GCRx + .t_pub_dx1gcr = {0}, //PUB DX1GCRx + .t_pub_dx2gcr = {0}, //PUB DX2GCRx + .t_pub_dx3gcr = {0}, //PUB DX3GCRx +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) + .t_pub_dcr = 0XB, //PUB DCR + .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, //PUB DTCR + .t_pub_dsgcr = 0x020641b, +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) + .t_pub_dcr = 0X40C, //PUB DCR + .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, + .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23), +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) + .t_pub_dcr = 0X89, //PUB DCR + .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, + .t_pub_dsgcr = 0x02064db, +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO) + .t_pub_dcr = 0XB, //PUB DCR + .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7 + .t_pub_dtcr1 = 0x00010237, //PUB DTCR + .t_pub_dsgcr = 0x020641b, +#endif + .t_pub_vtcr1 = 0x0fc00172, + .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)), + //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR + //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR + //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR + //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR + .t_pub_zq0pr = 0x59959, //PUB ZQ0PR + .t_pub_zq1pr = 0x6f95d, //PUB ZQ1PR + .t_pub_zq2pr = 0x6f95d, //PUB ZQ2PR + .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR + + /* pctl0 defines */ + /* pctl1 use same define as pctl0 */ + .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U + .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N + .t_pctl0_init_us = 2, //PCTL TINIT + .t_pctl0_rsth_us = 2, //PCTL TRSTH + .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T + //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1 + .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset + //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1 + .t_pctl0_scfg = 0xF01, //PCTL SCFG + .t_pctl0_sctl = 0x1, //PCTL SCTL + .t_pctl0_ppcfg = 0, + .t_pctl0_dfistcfg0 = 0x4, + .t_pctl0_dfistcfg1 = 0x1, + .t_pctl0_dfitctrldelay = 2, + .t_pctl0_dfitphywrdata = 2, + .t_pctl0_dfitphywrlta = 7, + .t_pctl0_dfitrddataen = 8, + .t_pctl0_dfitphyrdlat = 22, + .t_pctl0_dfitdramclkdis = 1, + .t_pctl0_dfitdramclken = 1, + .t_pctl0_dfitphyupdtype0 = 16, + .t_pctl0_dfitphyupdtype1 = 16, + .t_pctl0_dfitctrlupdmin = 16, + .t_pctl0_dfitctrlupdmax = 64, + .t_pctl0_dfiupdcfg = 0x3, + .t_pctl0_cmdtstaten = 1, + //.t_pctl0_dfiodtcfg = 8, + //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ), + .t_pctl0_dfiodtcfg = (1<<3)|(1<<11), + .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)), + + .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)), + .t_pub_acbdlr0 = 0x10, //CK0 delay fine tune + .t_pub_aclcdlr = 0x50, + .t_pub_acbdlr3 = 0x10,//0xa, //cs + .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */ + + .wr_adj_per = { + [0] = 100, + [1] = 100, + [2] = 100, + [3] = 100, + [4] = 100, + [5] = 100, + }, + .rd_adj_per = { + [0] = 100, + [1] = 100, + [2] = 100, + [3] = 100, + [4] = 100, + [5] = 100,}, +}; + +pll_set_t __pll_setting = { + .cpu_clk = CONFIG_CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = CONFIG_AML_CUSTOMER_ID, +#ifdef CONFIG_DEBUG_MODE + .debug_mode = CONFIG_DEBUG_MODE, + .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG, + .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG, +#endif +}; diff --git a/board/harman/atom_v1/lcd.c b/board/harman/atom_v1/lcd.c new file mode 100644 index 0000000..eb057a3 --- a/dev/null +++ b/board/harman/atom_v1/lcd.c @@ -0,0 +1,364 @@ +/* + * AMLOGIC TV LCD panel driver. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the named License, + * or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <amlogic/aml_lcd.h> +#include <asm/arch/gpio.h> + +//Rsv_val = 0xffffffff + +static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "GPIOZ_13", /* PANEL_PWR */ + "GPIOZ_8", /* SCN_EN */ + "GPIOZ_9", /* LD_EN2 */ + "GPIOZ_10", /* 2D_3D */ + "GPIOH_4", /* LR_IN */ + "GPIOH_5", /* SEL_LVDS */ + "invalid", /* ending flag */ +}; + +static struct lcd_power_step_s lcd_power_on_step[] = { + {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */ + {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = { + {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */ + {LCD_POWER_TYPE_CPU, 3,0,10,}, /* 3d_disable */ + {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; +static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = { + {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */ + {LCD_POWER_TYPE_CPU, 3,2,0,}, /* 3d_disable */ + {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */ + {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */ +}; + +static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = { + "GPIOZ_4", /* BL_EN */ + "GPIOZ_6", /* BL_PWM */ + "GPIOZ_7", /* Dimming */ + "invalid", /* ending flag */ +}; + +struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = { + {/* normal*/ + "lvds_0",LCD_LVDS,8, + /* basic timing */ + 1920,1080,2200,1125,44,148,0,5,36,0, + /* clk_attr */ + 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* lvds_attr */ + 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 60,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* for HDMI convert*/ + "lvds_1",LCD_LVDS,8, + /* basic timing */ + 1920,1080,2200,1125,44,148,0,5,36,0, + /* clk_attr */ + 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* lvds_attr */ + 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 60,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/*public 2-region vx1 : 3840x2160@60hz 8lane */ + "vbyone_0",LCD_VBYONE,10, + /* basic timing */ + 3840,2160,4400,2250,33,477,0,6,81,0, + /* clk_attr */ + 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* vbyone_attr */ + 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 60,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/*public 1-region vx1 : 3840x2160@60hz 8lane */ + "vbyone_1",LCD_VBYONE,10, + /* basic timing */ + 3840,2160,4400,2250,33,477,0,6,81,0, + /* clk_attr */ + 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* vbyone_attr */ + 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 60,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/* 2-region for HDMI convert */ + "vbyone_2",LCD_VBYONE,10, + /* basic timing */ + 3840,2160,4400,2250,33,477,0,6,81,0, + /* clk_attr */ + 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* vbyone_attr */ + 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step, lcd_power_off_step, + /* backlight */ + 60,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {/*BOE: HV550QU2: 3840x2160@60hz 8lane */ + "vbyone_3",LCD_VBYONE,10, + /* basic timing */ + 3840,2160,4400,2250,33,477,1,6,81,0, + /* clk_attr */ + 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* vbyone_attr */ + 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + /* power step */ + lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable, + /* backlight */ + 60,255,10,128,128, + BL_CTRL_PWM,0,1,0,200,200, + BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0, + Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val, + Rsv_val,Rsv_val,Rsv_val,Rsv_val, + 10,10,Rsv_val}, + + {.panel_type = "invalid"}, +}; + +//**** Special parameters just for Vbyone ***// +static struct vbyone_config_s lcd_vbyone_config = { + .lane_count = 8, + .byte_mode = 4, + .region_num = 2, + .color_fmt = 4, +}; + +//**** Special parameters just for lvds ***// +static struct lvds_config_s lcd_lvds_config = { + .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode + .dual_port = 1, //0=single port, 1=double port + .pn_swap = 0, //0=normal, 1=swap + .port_swap = 0, //0=normal, 1=swap + .lane_reverse = 0, //0=normal, 1=swap +}; + +static struct lcd_power_ctrl_s lcd_power_ctrl = { + .power_on_step = { + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 1, /* 0=output_low, 1=output_high, 2=input */ + .delay = 50, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_SIGNAL, + .delay = 0, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, + .power_off_step = { + { + .type = LCD_POWER_TYPE_SIGNAL, + .delay = 50, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_CPU, + .index = 0, /* point to cpu_gpio[] struct */ + .value = 0, /* 0=output_low, 1=output_high, 2=input */ + .delay = 100, /* unit: ms */ + }, + { + .type = LCD_POWER_TYPE_MAX, /* ending flag */ + }, + }, +}; + +struct lcd_config_s lcd_config_dft = { + .lcd_mode = LCD_MODE_TV, + .lcd_key_valid = 0, + .lcd_basic = { + .model_name = "default", + .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE + .lcd_bits = 8, + .h_active = 1920, + .v_active = 1080, + .h_period = 2200, + .v_period = 1125, + + .screen_width = 16, + .screen_height = 9, + }, + + .lcd_timing = { + .clk_auto = 1, + .lcd_clk = 60, + .ss_level = 0, + .fr_adjust_type = 0, + + .hsync_width = 44, + .hsync_bp = 148, + .hsync_pol = 0, + .vsync_width = 5, + .vsync_bp = 36, + .vsync_pol = 0, + }, + + .lcd_control = { + .lvds_config = &lcd_lvds_config, + .vbyone_config = &lcd_vbyone_config, + }, + .lcd_power = &lcd_power_ctrl, + .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}}, +}; + +#ifdef CONFIG_AML_LCD_EXTERN +static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = { + "invalid", /* ending flag */ +}; + +#define LCD_EXTERN_NAME "ext_default" +#define LCD_EXTERN_CMD_SIZE 9 +static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = { + 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00, + 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00, + 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00, + 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */ + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */ +}; + +static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = { + 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */ +}; + +struct lcd_extern_config_s ext_config_dtf = { + .lcd_ext_key_valid = 0, + .index = LCD_EXTERN_INDEX_INVALID, + .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */ + .status = 0, /* 0=disable, 1=enable */ + .i2c_addr = 0x1c, /* 7bit i2c address */ + .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */ + .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */ + .spi_gpio_cs = 0, + .spi_gpio_clk = 1, + .spi_gpio_data = 2, + .spi_clk_freq = 0, /* hz */ + .spi_clk_pol = 0, + .cmd_size = LCD_EXTERN_CMD_SIZE, + .table_init_on = init_on_table, + .table_init_off = init_off_table, +}; +#endif + +struct bl_config_s bl_config_dft = { + .name = "default", + .bl_key_valid = 0, + + .level_default = 100, + .level_min = 10, + .level_max = 255, + .level_mid = 128, + .level_mid_mapping = 128, + .level = 0, + + .method = BL_CTRL_MAX, + .power_on_delay = 200, + .power_off_delay = 200, + + .en_gpio = 0xff, + .en_gpio_on = 1, + .en_gpio_off = 0, + + .bl_pwm = NULL, + .bl_pwm_combo0 = NULL, + .bl_pwm_combo1 = NULL, + .pwm_on_delay = 10, + .pwm_off_delay = 10, + + .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}}, + .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}}, +}; + +void lcd_config_bsp_init(void) +{ + int i, j; + + for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_cpu_gpio[i], "invalid") == 0) + break; + strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]); + } + for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++) + strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid"); + for (i = 0; i < BL_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_bl_gpio[i], "invalid") == 0) + break; + strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]); + } + for (j = i; j < BL_GPIO_NUM_MAX; j++) + strcpy(bl_config_dft.gpio_name[j], "invalid"); + +#ifdef CONFIG_AML_LCD_EXTERN + for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) { + if (strcmp(lcd_ext_gpio[i], "invalid") == 0) + break; + strcpy(ext_config_dtf.gpio_name[i], lcd_ext_gpio[i]); + } + for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++) + strcpy(ext_config_dtf.gpio_name[j], "invalid"); + + strcpy(ext_config_dtf.name, LCD_EXTERN_NAME); +#endif +} diff --git a/board/harman/atom_v1/pwm_table.c b/board/harman/atom_v1/pwm_table.c new file mode 100644 index 0000000..18dc638 --- a/dev/null +++ b/board/harman/atom_v1/pwm_table.c @@ -0,0 +1,71 @@ +#include <common.h> + +const int pwm_cal_voltage_table[][2] = { + { 0x1c0000, 860}, + { 0x1b0001, 870}, + { 0x1a0002, 880}, + { 0x190003, 890}, + { 0x180004, 900}, + { 0x170005, 910}, + { 0x160006, 920}, + { 0x150007, 930}, + { 0x140008, 940}, + { 0x130009, 950}, + { 0x12000a, 960}, + { 0x11000b, 970}, + { 0x10000c, 980}, + { 0x0f000d, 990}, + { 0x0e000e, 1000}, + { 0x0d000f, 1010}, + { 0x0c0010, 1020}, + { 0x0b0011, 1030}, + { 0x0a0012, 1040}, + { 0x090013, 1050}, + { 0x080014, 1060}, + { 0x070015, 1070}, + { 0x060016, 1080}, + { 0x050017, 1090}, + { 0x040018, 1100}, + { 0x030019, 1110}, + { 0x02001a, 1120}, + { 0x01001b, 1130}, + { 0x00001c, 1140} +}; +const int pwm_cal_voltage_table_ee[][2] = { + { 0x1c0000, 810}, + { 0x1b0001, 820}, + { 0x1a0002, 830}, + { 0x190003, 840}, + { 0x180004, 850}, + { 0x170005, 860}, + { 0x160006, 870}, + { 0x150007, 880}, + { 0x140008, 890}, + { 0x130009, 900}, + { 0x12000a, 910}, + { 0x11000b, 920}, + { 0x10000c, 930}, + { 0x0f000d, 940}, + { 0x0e000e, 950}, + { 0x0d000f, 960}, + { 0x0c0010, 970}, + { 0x0b0011, 980}, + { 0x0a0012, 990}, + { 0x090013, 1000}, + { 0x080014, 1010}, + { 0x070015, 1020}, + { 0x060016, 1030}, + { 0x050017, 1040}, + { 0x040018, 1050}, + { 0x030019, 1060}, + { 0x02001a, 1070}, + { 0x01001b, 1080}, + { 0x00001c, 1090} +}; + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table); +int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee); + + diff --git a/board/harman/configs/atom_v1.h b/board/harman/configs/atom_v1.h new file mode 100644 index 0000000..8da8c80 --- a/dev/null +++ b/board/harman/configs/atom_v1.h @@ -0,0 +1,624 @@ +/* + * board/harman/configs/atom_v1.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __ATOM_V1_H__ +#define __ATOM_V1_H__ + +#include <asm/arch/cpu.h> + +#define CONFIG_SYS_GENERIC_BOARD 1 +#ifndef CONFIG_AML_MESON +#warning "include warning" +#endif + +/* + * platform power init config + */ +#define CONFIG_PLATFORM_POWER_INIT +#define CONFIG_VCCK_INIT_VOLTAGE 1050//1100 +#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up +#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend + +/* configs for CEC */ +#define CONFIG_CEC_OSD_NAME "AML_TV" +#define CONFIG_CEC_WAKEUP +/*if use bt-wakeup,open it*/ +#define CONFIG_BT_WAKEUP +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +#define CONFIG_INSTABOOT + +/* config saradc*/ +#define CONFIG_CMD_SARADC 1 + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#define CONFIG_CMD_BOOTCTOL_AVB + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_AML_MESON_SERIAL 1 +#define CONFIG_SERIAL_MULTI 1 + +//Enable ir remote wake up for bl30 +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=1080000\0"\ + "panel_type=lvds_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd1\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x1000000\0" \ + "fb_addr=0x3d800000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=update 1000\0" \ + "fdt_high=0x20000000\0"\ + "try_auto_burn=update 700 750;\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "sdc_burning=sdc_burn ${sdcburncfg}\0"\ + "wipe_data=successful\0"\ + "wipe_cache=successful\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "page_trace=on\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=_a\0"\ + "lock=10001000\0"\ + "boot_part=boot\0"\ + "reboot_mode_android=""normal""\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then "\ + "run init_display; run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} page_trace=${page_trace};" \ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "run set_demomode; " \ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "fastboot;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "run fastboot_key; "\ + "run recovery_key; "\ + "run try_auto_burn; "\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "get_system_as_root_mode;"\ + "echo system_mode: ${system_mode};"\ + "if test ${system_mode} = 1; then "\ + "setenv fs_type ""ro rootwait skip_initramfs"";"\ + "run storeargs;"\ + "fi;"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "run update;"\ + "\0"\ + "factory_reset_poweroff_protect="\ + "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\ + "if test ${wipe_data} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; "\ + "if test ${wipe_cache} = failed; then "\ + "run init_display; run storeargs;"\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "fi; \0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run sdc_burning; "\ + "if mmcinfo; then "\ + "run recovery_from_sdcard;"\ + "fi;"\ + "if usb start 0; then "\ + "run recovery_from_udisk;"\ + "fi;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_sdcard="\ + "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload mmc 0 ${loadaddr} recovery.img; then "\ + "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload usb 0 ${loadaddr} recovery.img; then "\ + "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\ + "wipeisb; "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\ + "setenv serial 1234567890;"\ + "fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "if keyman read region_code ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "else "\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "fastboot_key="\ + "if saradc open 1; then "\ + "echo fastboot key detect; " \ + "if saradc get_in_range 160 260; then " \ + "sleep 8;" \ + "if saradc get_in_range 160 260; then " \ + "echo enter fastboot mode; " \ + "fastboot;" \ + "fi;" \ + "fi;" \ + "fi;"\ + "\0"\ + "recovery_key="\ + "if saradc open 2; then "\ + "echo recovery from flash key detect; " \ + "if saradc get_in_range 1 5; then " \ + "sleep 5;" \ + "if saradc get_in_range 1 5; then " \ + "echo enter recovery mode; " \ + "run recovery_from_flash;" \ + "fi;" \ + "fi;" \ + "fi;"\ + "\0"\ + "clear_demomode="\ + "setenv demomode 0; " \ + "\0"\ + "set_demomode="\ + "setenv bootargs ${bootargs} androidboot.atvdemomode=${demomode}; " \ + "\0"\ + "demomode_key_detect="\ + "get_rebootmode;"\ + "run clear_demomode;"\ + "if test ${reboot_mode} = cold_boot; then "\ + "run demomode_video_key; "\ + "run demomode_exit_key; "\ + "run demomode_audio_key; "\ + "fi;" \ + "\0"\ + "demomode_video_key="\ + "if saradc open 1; then "\ + "echo demomode video key detect;" \ + "if saradc get_in_range 0 60; then " \ + "sleep 8;" \ + "if saradc get_in_range 0 60; then " \ + "echo enter Video-Only demomode; " \ + "setenv demomode 12345;" \ + "fi;" \ + "fi;" \ + "fi;"\ + "\0"\ + "demomode_exit_key="\ + "echo demomode exit key detect; " \ + "if gpio input gpiodv_0; then " \ + "sleep 8;" \ + "if gpio input gpiodv_0; then " \ + "echo exit demomode; " \ + "setenv demomode 54321;" \ + "fi;" \ + "fi;" \ + "\0"\ + "demomode_audio_key="\ + "echo demomode audio key detect; " \ + "if gpio input gpiodv_1; then " \ + "sleep 8;" \ + "if gpio input gpiodv_1; then " \ + "echo enter Audio-Only demomode; " \ + "setenv demomode 67890;" \ + "fi;" \ + "fi;" \ + "\0"\ + "irremote_update="\ + "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\ + "echo read irkey ok!; " \ + "if itest ${irkey_value} == 0xe31cfb04; then " \ + "run update;" \ + "else if itest ${irkey_value} == 0xb748fb04; then " \ + "run update;\n" \ + "fi;fi;" \ + "fi;\0" \ + + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run demomode_key_detect; "\ + "run factory_reset_poweroff_protect;"\ + "run init_display;"\ + "run storeargs;" + +#define CONFIG_BOOTCOMMAND \ + "run upgrade_check;"\ + "bcb uboot-command;" \ + "run switch_bootmode;" \ + "run storeboot;" + + +//#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_ANDROID_IMG 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* cpu */ +#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24 + +/* ddr */ +#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect +#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24 +#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip +#define CONFIG_NR_DRAM_BANKS 1 +/* DDR type setting + * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3 + * CONFIG_DDR_TYPE_DDR3 : DDR3 + * CONFIG_DDR_TYPE_DDR4 : DDR4 + * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */ +#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO +/* DDR channel setting, please refer hardware design. + * CONFIG_DDR0_RANK0 : DDR0 rank0 + * CONFIG_DDR0_RANK01 : DDR0 rank0+1 + * CONFIG_DDR0_16BIT : DDR0 16bit mode + * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks + * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */ +#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0 +/* ddr functions */ +#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd +#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd +#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_STORE_COMPATIBLE 1 +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CMD_SAVEENV +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif +#define CONFIG_AML_SD_EMMC 1 +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#define CONFIG_SYS_NO_FLASH 1 + + +/* vpu */ +#define CONFIG_AML_VPU 1 + +/* DISPLAY & HDMITX */ +#define CONFIG_AML_HDMITX20 1 +#define CONFIG_AML_CANVAS 1 +#define CONFIG_AML_VOUT 1 +#define CONFIG_AML_OSD 1 +#define CONFIG_OSD_SCALE_ENABLE 1 +#define CONFIG_CMD_BMP 1 + +#if defined(CONFIG_AML_VOUT) +#define CONFIG_AML_CVBS 1 +#endif + +//#define CONFIG_AML_LCD 1 +//#define CONFIG_AML_LCD_TV 1 +//#define CONFIG_AML_LCD_TABLET 1 + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +#define CONFIG_CMD_USB 1 +#if defined(CONFIG_CMD_USB) + #define CONFIG_GXL_XHCI_BASE 0xff500000 + #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000 + #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080 + #define CONFIG_USB_STORAGE 1 + #define CONFIG_USB_XHCI 1 + #define CONFIG_USB_XHCI_AMLOGIC_GXL 1 +#endif //#if defined(CONFIG_CMD_USB) + +#define CONFIG_TXLX_USB 1 +//UBOOT fastboot config +#define CONFIG_CMD_FASTBOOT 1 +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#define CONFIG_FASTBOOT_FLASH 1 +#define CONFIG_USB_GADGET 1 +#define CONFIG_USBDOWNLOAD_GADGET 1 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000 +#define CONFIG_DEVICE_PRODUCT "atom" + +//UBOOT Facotry usb/sdcard burning config +#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning +#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning +#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning +#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning + +#define CONFIG_AML_SECURITY_KEY 1 +#define CONFIG_UNIFY_KEY_MANAGE 1 + +/* net */ +#define CONFIG_CMD_NET 1 +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME arm_gxbb +// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +/* other devices */ +#define CONFIG_EFUSE 1 +#define CONFIG_SYS_I2C_AML 1 +#define CONFIG_SYS_I2C_SPEED 400000 + +/* commands */ +#define CONFIG_CMD_CACHE 1 +#define CONFIG_CMD_BOOTI 1 +#define CONFIG_CMD_EFUSE 1 +#define CONFIG_CMD_I2C 1 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_GPIO 1 +#define CONFIG_CMD_RUN +#define CONFIG_CMD_REBOOT 1 +#define CONFIG_CMD_ECHO 1 +#define CONFIG_CMD_JTAG 1 +#define CONFIG_CMD_AUTOSCRIPT 1 +#define CONFIG_CMD_MISC 1 + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_AML_PARTITION 1 +#define CONFIG_MMC 1 +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +//#define CONFIG_SYS_DCACHE_OFF +//#define CONFIG_SYS_ICACHE_OFF + +/* other functions */ +#define CONFIG_NEED_BL301 1 +#define CONFIG_NEED_BL32 1 +#define CONFIG_CMD_RSVMEM 1 +#define CONFIG_FIP_IMG_SUPPORT 1 +#define CONFIG_BOOTDELAY 1 +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMD_MISC 1 +#define CONFIG_CMD_ITEST 1 +#define CONFIG_CMD_CPU_TEMP 1 +#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve + +//#define CONFIG_MULTI_DTB 1 + +/* debug mode defines */ +//#define CONFIG_DEBUG_MODE 1 +#ifdef CONFIG_DEBUG_MODE +#define CONFIG_DDR_CLK_DEBUG 636 +#define CONFIG_CPU_CLK_DEBUG 600 +#endif + +//support secure boot +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +//for SRAM size limitation just disable NAND +//as the socket board default has no NAND +//#undef CONFIG_AML_NAND + +//unify build for generate encrypted bootloader "u-boot.bin.encrypt" +#define CONFIG_AML_CRYPTO_UBOOT 1 + +//unify build for generate encrypted kernel image +//SRC : "board/amlogic/(board)/boot.img" +//DST : "fip/boot.img.encrypt" +//#define CONFIG_AML_CRYPTO_IMG 1 + +#endif //CONFIG_AML_SECURE_UBOOT + +#define CONFIG_SECURE_STORAGE 1 + +//build with uboot auto test +//#define CONFIG_AML_UBOOT_AUTO_TEST 1 + +//board customer ID +//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) + +#if defined(CONFIG_CUSTOMER_ID) + #undef CONFIG_AML_CUSTOMER_ID + #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID +#endif +#define ETHERNET_INTERNAL_PHY + +/* meson SPI */ +#define CONFIG_AML_SPIFC +#define CONFIG_AML_SPICC +#define MAX_SPI_BYTES 48 +#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC + #define CONFIG_OF_SPI + #define CONFIG_DM_SPI + #define CONFIG_CMD_SPI +#endif + +//#define CONFIG_AVB2 +/** + * Atom will enable both vendor AVB2 public key as well as default AVB2 + * public key in build. + * + * CONFIG_AVB2_KPUB_VENDOR and CONFIG_AVB2_KPUB_DEFAULT_VENDOR will be passed + * through command line during Atom bl33 build. + * + * Example: + * + * To build production Atom AVB2 bl33 + * + * CONFIG_AVB2_KPUB_VENDOR=1 CONFIG_AVB2_KPUB_DEFAULT_VENDOR=1 ./mk atom_v1 --bl32 <xxx>/bl32.img --systemroot + * + * or just + * + * CONFIG_AVB2_KPUB_DEFAULT_VENDOR=1 ./mk atom_v1 --bl32 <xxx>/bl32.img --systemroot + * + * To build testkey bl33.bin + * + * ./mk atom_v1 --bl32 <xxx>/bl32.img --systemroot + */ +//#define CONFIG_AVB2_KPUB_VENDOR +//#define CONFIG_AVB2_KPUB_DEFAULT_VENDOR +#define CONFIG_SKIP_KERNEL_DTB_VERIFY + +#endif diff --git a/board/harman/defconfigs/atom_v1_defconfig b/board/harman/defconfigs/atom_v1_defconfig new file mode 100644 index 0000000..082dd15 --- a/dev/null +++ b/board/harman/defconfigs/atom_v1_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_MESON_TXLX=y +CONFIG_ATOM_V1=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_AML_GPIO=y diff --git a/common/Kconfig b/common/Kconfig index 8af7ef0..ca823d2 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -79,6 +79,12 @@ config CMD_XIMG help Extract a part of a multi-image. +config SEI_FASTBOOT + bool "fastboot" + default n + help + press RESET to enter recovery in fastboot. + endmenu menu "Environment commands" diff --git a/common/aml_dt.c b/common/aml_dt.c index 46d7acb..54f08c9 100644 --- a/common/aml_dt.c +++ b/common/aml_dt.c @@ -45,6 +45,28 @@ //#define readl(addr) (*(volatile unsigned int*)(addr)) extern int checkhw(char * name); +/* return 1 if dtb is encrpted */ +int is_dtb_encrypt(unsigned char *buffer) +{ +#ifdef CONFIG_SKIP_KERNEL_DTB_VERIFY + return 0; +#else +#if 0 + unsigned int magic = *(unsigned int*)buffer; + + if ((DT_HEADER_MAGIC == magic) + || (AML_DT_HEADER_MAGIC == magic) + || (IS_GZIP_FORMAT(magic))) + return 0; + return 1; +#else + const unsigned long cfg10 = readl(AO_SEC_SD_CFG10); + /*KM_MSG("cfg10=0x%lX\n", cfg10);*/ + return ( cfg10 & (0x1<< 4) ); +#endif//#if 0 +#endif /* CONFIG_SKIP_KERNEL_DTB_VERIFY */ +} + unsigned long __attribute__((unused)) get_multi_dt_entry(unsigned long fdt_addr){ unsigned int dt_magic = readl(fdt_addr); diff --git a/common/cmd_avb.c b/common/cmd_avb.c index 2e6a405..d95d432 100644 --- a/common/cmd_avb.c +++ b/common/cmd_avb.c @@ -18,13 +18,25 @@ #include <anti-rollback.h> #endif -#define AVB_USE_TESTKEY #define MAX_DTB_SIZE (256 * 1024) -#ifdef AVB_USE_TESTKEY -extern const char testkey2048[520]; -extern const int testkey2048_length; -#endif +#define CONFIG_AVB2_KPUB_EMBEDDED +#define CONFIG_AVB2_KPUB_DEFAULT + +#ifdef CONFIG_AVB2_KPUB_VENDOR +/** + * Use of vendor public key automatically disable default public key + */ +#undef CONFIG_AVB2_KPUB_DEFAULT +extern const char avb2_kpub_vendor[]; +extern const int avb2_kpub_vendor_len; +#endif /* CONFIG_AVB_KPUB_VENDOR */ + +#if defined(CONFIG_AVB2_KPUB_DEFAULT) || defined(CONFIG_AVB2_KPUB_DEFAULT_VENDOR) +extern const char avb2_kpub_default[]; +extern const int avb2_kpub_default_len; +#endif /* CONFIG_AVB_KPUB_DEFAULT || CONFIG_AVB2_KPUB_DEFAULT_VENDOR */ + AvbOps avb_ops_; static AvbIOResult read_from_partition(AvbOps* ops, const char* partition, int64_t offset, @@ -154,23 +166,75 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps* ops, const uint8_t* public size_t public_key_length, const uint8_t* public_key_metadata, size_t public_key_metadata_length, bool* out_is_trusted) { -#ifdef AVB_USE_TESTKEY - printf("Verified using testkey\n"); - if (testkey2048_length != public_key_length) { +#ifdef CONFIG_AVB2_KPUB_EMBEDDED +/** + * CONFIG_AVB2_KPUB_DEFAULT and CONFIG_AVB2_KPUB_VENDOR should be + * exclusive ideally, however the world is not ideal. + * + * Instead of forbidding it, just print out a warning to let the user + * know this is not something they should be doing unless they really + * know what they are doing. + */ +#if defined(CONFIG_AVB2_KPUB_VENDOR) && defined(CONFIG_AVB2_KPUB_DEFAULT_VENDOR) + #pragma message("Both vendor and default AVB2 public keys are enabled") +#endif /* CONFIG_AVB2_KPUB_VENDOR && CONFIG_AVB2_KPUB_DEFAULT_VENDOR */ + +#if defined(CONFIG_AVB2_KPUB_VENDOR) + printf("AVB2 verify with vendor kpub\n"); + if (avb2_kpub_vendor_len != public_key_length) *out_is_trusted = false; - return AVB_IO_RESULT_OK; + else { + if (!avb_safe_memcmp(public_key_data, avb2_kpub_vendor, avb2_kpub_vendor_len)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } + else + *out_is_trusted = false; } - if (!avb_safe_memcmp(public_key_data, testkey2048, testkey2048_length)) - *out_is_trusted = true; - else + +/** + * Allow re-verify with default AVB2 public key if really want to do. + * + * Use of this is *NOT* typical and you should really know what you are + * doing if want to enable this. + */ +#ifdef CONFIG_AVB2_KPUB_DEFAULT_VENDOR + printf("AVB2 re-verify with default kpub\n"); + if (avb2_kpub_default_len != public_key_length) + *out_is_trusted = false; + else { + if (!avb_safe_memcmp(public_key_data, avb2_kpub_default, avb2_kpub_default_len)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } + else + *out_is_trusted = false; + } +#endif /* CONFIG_AVB2_KPUB_DEFAULT_VENDOR */ +#elif defined(CONFIG_AVB2_KPUB_DEFAULT) + printf("AVB2 verify with default kpub\n"); + if (avb2_kpub_default_len != public_key_length) *out_is_trusted = false; + else { + if (!avb_safe_memcmp(public_key_data, avb2_kpub_default, avb2_kpub_default_len)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } + else + *out_is_trusted = false; + } #else + #error "No AVB2 public key defined" +#endif /* CONFIG_AVB2_KPUB_VENDOR */ + +#else /* CONFIG_AVB2_KPUB_EMBEDDED */ unsigned long bl31_addr = get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); memcpy((void *)bl31_addr, public_key_data, public_key_length); flush_cache(bl31_addr, public_key_length); *out_is_trusted = aml_sec_boot_check(AML_D_P_AVB_PUBKEY_VERIFY, bl31_addr, public_key_length, 0); -#endif +#endif /* CONFIG_AVB2_KPUB_EMBEDDED */ + return AVB_IO_RESULT_OK; } diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 3a8fe6d..8fa2be7 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -130,6 +130,7 @@ static void defendkey_process(void) int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + int nRet; char *avb_s; #ifdef CONFIG_NEEDS_MANUAL_RELOC static int relocated = 0; @@ -166,6 +167,7 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return do_bootm_subcommand(cmdtp, flag, argc, argv); } +#ifndef CONFIG_SKIP_KERNEL_DTB_VERIFY unsigned int nLoadAddr = GXB_IMG_LOAD_ADDR; //default load address if (argc > 0) @@ -175,12 +177,13 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) //printf("aml log : addr = 0x%x\n",nLoadAddr); } - int nRet = aml_sec_boot_check(AML_D_P_IMG_DECRYPT,nLoadAddr,GXB_IMG_SIZE,GXB_IMG_DEC_ALL); + nRet = aml_sec_boot_check(AML_D_P_IMG_DECRYPT,nLoadAddr,GXB_IMG_SIZE,GXB_IMG_DEC_ALL); if (nRet) { printf("\naml log : Sig Check %d\n",nRet); return nRet; } +#endif /* ! CONFIG_SKIP_KERNEL_DTB_VERIFY */ avb_s = getenv("avb2"); if (avb_s == NULL) { diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c index b72f4f3..0084b32 100644 --- a/common/cmd_fastboot.c +++ b/common/cmd_fastboot.c @@ -10,6 +10,11 @@ #include <common.h> #include <command.h> #include <g_dnl.h> +#ifdef CONFIG_SEI_FASTBOOT +#include <asm/io.h> +#include <asm/arch/secure_apb.h> +#include <asm/cpu_id.h> +#endif static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { @@ -19,13 +24,24 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) ret = g_dnl_register("usb_dnl_fastboot"); if (ret) return ret; - +#ifdef CONFIG_SEI_FASTBOOT + run_command("osd clear;imgread pic logo fastboot $loadaddr;bmp display $fastboot_offset;bmp scale;",0); +#endif while (1) { if (g_dnl_detach()) break; if (ctrlc()) break; usb_gadget_handle_interrupts(); +#ifdef CONFIG_SEI_FASTBOOT + setbits_le32(P_AO_GPIO_O_EN_N, (1 << 2)); //GPIOAO_2 input + readl(AO_GPIO_I); + if(!(readl(AO_GPIO_I) & (0x01 << 2))) + { + run_command("osd clear;imgread pic logo recovery_boot $loadaddr;bmp display $recovery_boot_offset;bmp scale;",0); + run_command("run recovery_from_flash;",0); + } +#endif } g_dnl_unregister(); diff --git a/common/store_interface.c b/common/store_interface.c index 1e68821..b13f8ce 100644 --- a/common/store_interface.c +++ b/common/store_interface.c @@ -54,6 +54,7 @@ extern int mmc_ddr_parameter_read(unsigned char *buf, unsigned int size); extern int mmc_ddr_parameter_write(unsigned char *buf, unsigned int size); extern int mmc_ddr_parameter_erase(void); +extern int is_dtb_encrypt(unsigned char *buffer); #define debugP(fmt...) //printf("Dbg[store]L%d:", __LINE__),printf(fmt) #define MsgP(fmt...) printf("[store]"fmt) #define ErrP(fmt...) printf("[store]Err:%s,L%d:", __func__, __LINE__),printf(fmt) @@ -313,6 +314,7 @@ static int do_store_dtb_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const ret = run_command(_cmdBuf, 0); unsigned long dtImgAddr = simple_strtoul(dtbLoadaddr, NULL, 16); + if (is_dtb_encrypt(NULL)) { // //ONLY need decrypting when 'store dtb read' if (!strcmp("read", argv[2])) @@ -324,6 +326,7 @@ static int do_store_dtb_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const return ret; } } + } if (!is_write && strcmp("iread", argv[2])) { diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 64ee405..0e30bf1 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -508,6 +508,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) char *s1; char *s2; char *s3; + char s_version[24]; size_t chars_left; run_command("get_valid_slot", 0); @@ -543,16 +544,21 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) chars_left -= strlen(cmd) + 1; } + strcpy(s_version, "01.01."); + printf("U_BOOT_DATE_TIME: %s\n", U_BOOT_DATE_TIME); + strcat(s_version, U_BOOT_DATE_TIME); + printf("s_version: %s\n", s_version); + if (!strcmp_l1("version-baseband", cmd)) { strncat(response, "N/A", chars_left); } else if (!strcmp_l1("version-bootloader", cmd)) { - strncat(response, U_BOOT_VERSION, chars_left); + strncat(response, s_version, chars_left); } else if (!strcmp_l1("hw-revision", cmd)) { strncat(response, "EVT", chars_left); } else if (!strcmp_l1("version", cmd)) { strncat(response, FASTBOOT_VERSION, chars_left); } else if (!strcmp_l1("bootloader-version", cmd)) { - strncat(response, U_BOOT_VERSION, chars_left); + strncat(response, s_version, chars_left); } else if (!strcmp_l1("off-mode-charge", cmd)) { strncat(response, "0", chars_left); } else if (!strcmp_l1("variant", cmd)) { diff --git a/lib/libavb/testkey.c b/lib/libavb/testkey.c index 3440146..b968f1a 100644 --- a/lib/libavb/testkey.c +++ b/lib/libavb/testkey.c @@ -1,4 +1,4 @@ -const char testkey2048[520] = { +const char avb2_kpub_default[520] = { 0x00, 0x00, 0x08, 0x00, 0xc9, 0xd8, 0x7d, 0x7b, 0xc6, 0x55, 0x51, 0xdd, 0x32, 0x24, 0xa2, 0xe0, 0x0e, 0xbc, 0x7e, 0xfd, 0xbd, 0xa2, 0x53, 0x80, 0x58, 0x69, 0x7e, 0xf5, 0x4a, 0x40, 0x87, 0x95, 0x90, @@ -48,5 +48,4 @@ const char testkey2048[520] = { 0xa9, 0x75, 0x7e, 0xe1, 0x4e, 0xe2, 0x95, 0x5b, 0x4f, 0xe6, 0xdc, 0x03, 0xb9, 0x81 }; - -const int testkey2048_length = 520; +const int avb2_kpub_default_len = sizeof(avb2_kpub_default) / sizeof(char); diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 6127503..ee72588 100755..100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -75,6 +75,10 @@ ifneq ($(config_file), $(wildcard $(config_file))) config_file=$(shell echo "$(srctree)/board/amlogic/configs/$(CONFIG_SYS_BOARD).h") ifneq ($(config_file), $(wildcard $(config_file))) +# harman configs +config_file=$(shell echo "$(srctree)/board/harman/configs/$(CONFIG_SYS_BOARD).h") +ifneq ($(config_file), $(wildcard $(config_file))) + # 3rd. this is amlogic customer config folder config_file=$(shell echo "$(srctree)/customer/board/configs/$(CONFIG_SYS_BOARD).h") ifneq ($(config_file), $(wildcard $(config_file))) @@ -82,6 +86,7 @@ $(error $(shell echo "Error: Can not find $(CONFIG_SYS_BOARD).h")) endif endif endif +endif #$(warning "final file"$(config_file)) diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index f0ed84d..2876600 100755..100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -126,6 +126,10 @@ do_board_defconfig () { if [ ! -r $defconfig_path ]; then defconfig_path=$srctree/customer/board/defconfigs/$1 fi + # harman configs support + if [ ! -r $defconfig_path ]; then + defconfig_path=$srctree/board/harman/defconfigs/$1 + fi if [ ! -r $defconfig_path ]; then echo >&2 "***" |