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authorLiang Ji <liang.ji@amlogic.com>2019-08-07 08:08:47 (GMT)
committer Liang Ji <liang.ji@amlogic.com>2019-08-07 08:21:14 (GMT)
commit1f0cb6d6e3cc7ce55b348579b88dd4f895daae96 (patch)
tree089c86e6324947825c96e61cb76b787af372af05
parent90b83c13f98282a7ff871a6a31afb86e742fb96c (diff)
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newton: bring up [6/6]
PD#SWPL-12380 issue:138451656 Problem: enable newton(S905X3) project for reference design Solution: enable newton(S905X3) project for reference design Verify: newton Change-Id: Ic3f15634aad81da3d3686806cdb576e04ca48727 Signed-off-by: Liang Ji <liang.ji@amlogic.com>
Diffstat
-rw-r--r--board/amlogic/configs/sm1_ac213_v1.h668
-rw-r--r--board/amlogic/sm1_ac213_v1/Kconfig2
-rw-r--r--board/amlogic/sm1_ac213_v1/Makefile3
-rwxr-xr-xboard/amlogic/sm1_ac213_v1/README2
-rw-r--r--board/amlogic/sm1_ac213_v1/aml-user-key.sig28
-rw-r--r--board/amlogic/sm1_ac213_v1/eth_setup.c51
-rw-r--r--board/amlogic/sm1_ac213_v1/firmware/scp_task/pwm_ctrl.h61
-rw-r--r--board/amlogic/sm1_ac213_v1/firmware/scp_task/pwr_ctrl.c182
-rw-r--r--board/amlogic/sm1_ac213_v1/firmware/timing.c576
-rw-r--r--board/amlogic/sm1_ac213_v1/lcd.c475
-rw-r--r--board/amlogic/sm1_ac213_v1/sm1_ac213_v1.c854
11 files changed, 2899 insertions, 3 deletions
diff --git a/board/amlogic/configs/sm1_ac213_v1.h b/board/amlogic/configs/sm1_ac213_v1.h
new file mode 100644
index 0000000..4d697e8
--- a/dev/null
+++ b/board/amlogic/configs/sm1_ac213_v1.h
@@ -0,0 +1,668 @@
+
+/*
+ * board/amlogic/configs/g12a_u212_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __SM1_AC213_V1_H__
+#define __SM1_AC213_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 770 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "sdr2hdr=2\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=update 1000\0" \
+ "otg_device=1\0"\
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10001000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "reboot_mode_android=""normal""\0"\
+ "Irq_check_en=0\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "boot_cooling;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "get_valid_slot;"\
+ "get_avb_mode;"\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if test ${avb2} = 0; then "\
+ "if test ${active_slot} = _a; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
+ "else if test ${active_slot} = _b; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
+ "fi;fi;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "get_valid_slot;"\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_AML_MINUI 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "newton"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON 1
+#else
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+/* PWM DM driver*/
+#define CONFIG_DM_PWM
+#define CONFIG_PWM_MESON
+
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/sm1_ac213_v1/Kconfig b/board/amlogic/sm1_ac213_v1/Kconfig
index 22853c1..ccc7ff6 100644
--- a/board/amlogic/sm1_ac213_v1/Kconfig
+++ b/board/amlogic/sm1_ac213_v1/Kconfig
@@ -6,7 +6,7 @@ config SYS_CPU
config SYS_BOARD
string
- default "g12a_u212_v1"
+ default "sm1_ac213_v1"
config SYS_VENDOR
string
diff --git a/board/amlogic/sm1_ac213_v1/Makefile b/board/amlogic/sm1_ac213_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_ac213_v1/README b/board/amlogic/sm1_ac213_v1/README
deleted file mode 100755
index c546b20..0000000
--- a/board/amlogic/sm1_ac213_v1/README
+++ b/dev/null
@@ -1,2 +0,0 @@
-README
-sm1 ac213 board share BSP code with g12a_u212_v1 \ No newline at end of file
diff --git a/board/amlogic/sm1_ac213_v1/aml-user-key.sig b/board/amlogic/sm1_ac213_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/aml-user-key.sig
@@ -0,0 +1,28 @@
+yt}|4B/iֻxn:fޞpdd'tNZ !@ $ -Ȱ 2{^sW`D#@>+bqyd:T8Ο Oh!;z|۽DȄdR!Q_IU6 w>Kox"vp}d,6ψQΆdY<_,R/sL)e'is֭HoyU%a>1&FQ#[ ⁻[޺1 rBRPH
+|݂hTsj9 }n35f3?szc.n%ZJ;.݁8MכE@_ Ji ንf_Zq"i@ctu=~t
+INKBTqa`oԿDřMg>Q/zx_Y;Vyv/U)jp`MY6UؼS)OvWz<Qǯb8ZX`SXQ,ZܳcWj]-̹
+bt
+!R
+^PD{<醎: _|M̃$.<
+M{]$:Z);KrO T\>O@hi9Y
+~f8VmJaYƶ:@O)ZS;Zyu9Tj9vI)<}G}cW.
+xc ] .Oy)4v*un&w_7",@.Q9(6xdUL74GuG^}FVl%q} FV[_?uOs;T͗fJO$vH1
+q]R2ݐ*"gd,ι
+&~AW<H/&BI,~nL1yٳ4CT' jBN=$p='G1ʋ-/ѦP * CdfؒfaΣo30>~l5AM1ut"n7\G/^ȭ Ah"2>be̐wϷ+gՀ56wqh %aU&{'؁!RX
+4%^ rIf؏%D;3WK6f ظ}BGr Un#j0^+!
+863*P
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+Qvp\tZ(F#O8F&^6a>{.ℏ{^Z 8.6Kzs'] BX>qKjC<[ִ`b4H-7Or'*rpbl!G42l@TF 02Xuf LOdvrSP0uƲI.svzㅟh~yfScܔ/i=uȊf\zzwuˈ))8{Gy彋8?>Qfh\
+=[cEwJ[Jr
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+W51sh<XEn;9WgG_)+m&$wOYRܣt)M֫Bל/k!^F=gHW'㤻yn ?ʢ
+V|0'W3ÐC¼7|g6Hxn'33"FUvQ5b
+XE*FEh\bgK~ݻܶFn<LoN?(G𶀖Q3pdq;y "AO̹S욠oI$J6+c1d"ƕ@4lNA)5NTUZ ?L[l1|5^}wc^hD}4ՊW7?)?
+ +Cը
+ Dž,#U
+1pÝަRG0\#Ixybr?' JPLC7L)^ ugd ͤ @&[BEUocs E:OU `V!)}UgM$ c]
+|$!O"QK
+q'>od W|vKf1$zA'<FxPTѳ pyy̽[kqA<'BNFNj#0{㹥vx(4iWAǓaJKڶZ;Ő;(YZ~@0~<
+ғJy8۷kx
+K\E=
+
diff --git a/board/amlogic/sm1_ac213_v1/eth_setup.c b/board/amlogic/sm1_ac213_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/sm1_ac213_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_ac213_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..26d5d52
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,61 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+static int pwm_voltage_table_ee_new[][2] = {
+ { 0x120000, 700},
+ { 0x110001, 710},
+ { 0x100002, 720},
+ { 0x0f0003, 730},
+ { 0x0e0004, 740},
+ { 0x0d0005, 750},
+ { 0x0c0006, 760},
+ { 0x0b0007, 770},
+ { 0x0a0008, 780},
+ { 0x090009, 790},
+ { 0x08000a, 800},
+ { 0x07000b, 810},
+ { 0x06000c, 820},
+ { 0x05000d, 830},
+ { 0x04000e, 840},
+ { 0x03000f, 850},
+ { 0x020010, 860},
+ { 0x010011, 870},
+ { 0x000012, 880},
+};
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_ac213_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_ac213_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..07610bb
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to, pwm_size = 0;
+ static int (*pwm_voltage_ee)[2];
+
+ /* BOOT_9 = H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+ /*set BOOT_9 input mode*/
+ writel((readl(PREG_PAD_GPIO0_EN_N) | 0x200), PREG_PAD_GPIO0_EN_N);
+ if (((readl(PREG_PAD_GPIO0_EN_N) & 0x200 ) == 0x200) &&
+ ((readl(PREG_PAD_GPIO0_I) & 0x200 ) == 0x0)) {
+ uart_puts("use vddee new table!");
+ uart_puts("\n");
+ pwm_voltage_ee = pwm_voltage_table_ee_new;
+ pwm_size = ARRAY_SIZE(pwm_voltage_table_ee_new);
+ } else {
+ uart_puts("use vddee table!");
+ uart_puts("\n");
+ pwm_voltage_ee = pwm_voltage_table_ee;
+ pwm_size = ARRAY_SIZE(pwm_voltage_table_ee);
+ }
+
+ for (to = 0; to < pwm_size; to++) {
+ if (pwm_voltage_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= pwm_size) {
+ to = pwm_size - 1;
+ }
+
+ writel(*(*(pwm_voltage_ee + to)), AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 high to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ struct wakeup_gpio_info *gpio;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ BT_WAKEUP_SRC | CECB_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+/*bt wake host*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+
+ if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) {
+ irq[IRQ_ETH_PTM]= 0xFFFFFFFF;
+ exit_reason = ETH_PMT_WAKEUP;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/sm1_ac213_v1/firmware/timing.c b/board/amlogic/sm1_ac213_v1/firmware/timing.c
new file mode 100644
index 0000000..d91893e
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/firmware/timing.c
@@ -0,0 +1,576 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
+/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG0 0x0010000c
+ #define VDDEE_VAL_REG1 0x0008000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG0 0x000f000d
+ #define VDDEE_VAL_REG1 0x0007000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG0 0x000e000e
+ #define VDDEE_VAL_REG1 0x0006000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG0 0x000d000f
+ #define VDDEE_VAL_REG1 0x0005000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG0 0x000c0010
+ #define VDDEE_VAL_REG1 0x0004000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG0 0x000b0011
+ #define VDDEE_VAL_REG1 0x0003000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG0 0x000a0012
+ #define VDDEE_VAL_REG1 0x00020010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG0 0x00090013
+ #define VDDEE_VAL_REG1 0x00010011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG0 0x00080014
+ #define VDDEE_VAL_REG1 0x00000012
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+
+ /* set BOOT_9 input */
+ //{PAD_PULL_UP_EN_REG0, 1 << 9, 1 << 9, 0, BL2_INIT_STAGE_1, 0},
+
+ /* PWM_AO_B */
+ /* VDDEE init start */
+ /* step1: CHK HW */
+ {(uint64_t)P_ASSIST_POR_CONFIG, 7, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
+
+ /* step2: match PWM config */
+ /* GPIO9[BIT7]=H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+ {0x1, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
+ {0x0, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
+
+ /* step3: config PWM */
+ /* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
+ {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
+ /* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
+ {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
+ /* VDDEE init done */
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Init sys led*/
+ {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/sm1_ac213_v1/lcd.c b/board/amlogic/sm1_ac213_v1/lcd.c
new file mode 100644
index 0000000..2f352f6
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/lcd.c
@@ -0,0 +1,475 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 20,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 10,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 3,
+ .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX];
+static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX];
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+
+ .init_loaded = 0,
+ .cmd_size = 0xff,
+ .init_on = bl_ext_init_on,
+ .init_off = bl_ext_init_off,
+ .init_on_cnt = sizeof(bl_ext_init_on),
+ .init_off_cnt = sizeof(bl_ext_init_off),
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/sm1_ac213_v1/sm1_ac213_v1.c b/board/amlogic/sm1_ac213_v1/sm1_ac213_v1.c
new file mode 100644
index 0000000..9090f86
--- a/dev/null
+++ b/board/amlogic/sm1_ac213_v1/sm1_ac213_v1.c
@@ -0,0 +1,854 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+#include <amlogic/i2c.h>
+#endif
+#ifdef CONFIG_PWM_MESON
+#include <pwm.h>
+#include <amlogic/pwm.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+#ifdef CONFIG_SYS_I2C_MESON
+static const struct meson_i2c_platdata i2c_data[] = {
+ { 0, 0xffd1f000, 166666666, 3, 15, 100000 },
+ { 1, 0xffd1e000, 166666666, 3, 15, 100000 },
+ { 2, 0xffd1d000, 166666666, 3, 15, 100000 },
+ { 3, 0xffd1c000, 166666666, 3, 15, 100000 },
+ { 4, 0xff805000, 166666666, 3, 15, 100000 },
+};
+
+U_BOOT_DEVICES(meson_i2cs) = {
+ { "i2c_meson", &i2c_data[0] },
+ { "i2c_meson", &i2c_data[1] },
+ { "i2c_meson", &i2c_data[2] },
+ { "i2c_meson", &i2c_data[3] },
+ { "i2c_meson", &i2c_data[4] },
+};
+
+/*
+ *GPIOAO_10//I2C_SDA_AO
+ *GPIOAO_11//I2C_SCK_AO
+ *pinmux configuration seperated with i2c controller configuration
+ * config it when you use
+ */
+void set_i2c_ao_pinmux(void)
+{
+ return;
+}
+#endif /*end CONFIG_SYS_I2C_MESON*/
+
+#ifdef CONFIG_PWM_MESON
+static const struct meson_pwm_platdata pwm_data[] = {
+ { PWM_AB, 0xffd1b000, IS_DOUBLE_CHANNEL, IS_BLINK },
+ { PWM_CD, 0xffd1a000, IS_DOUBLE_CHANNEL, IS_BLINK },
+ { PWM_EF, 0xffd19000, IS_DOUBLE_CHANNEL, IS_BLINK },
+ { PWMAO_AB, 0xff807000, IS_DOUBLE_CHANNEL, IS_BLINK },
+ { PWMAO_CD, 0xff802000, IS_DOUBLE_CHANNEL, IS_BLINK },
+};
+
+U_BOOT_DEVICES(meson_pwm) = {
+ { "amlogic,general-pwm", &pwm_data[0] },
+ { "amlogic,general-pwm", &pwm_data[1] },
+ { "amlogic,general-pwm", &pwm_data[2] },
+ { "amlogic,general-pwm", &pwm_data[3] },
+ { "amlogic,general-pwm", &pwm_data[4] },
+};
+#endif /*end CONFIG_PWM_MESON*/
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+ set_i2c_ao_pinmux();
+#endif
+
+ return 0;
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_G12A != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x2>", 0);
+ run_command("fdt rm /emmc/emmc caps2", 0);
+ run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0);
+
+ run_command("fdt set /sdio status okay", 0);
+ run_command("fdt set /sd1 status okay", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd1 status ", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0);
+ } else {
+
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x3>", 0);
+ run_command("fdt set /sdio status disabled", 0);
+ run_command("fdt set /sd2 status okay", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd2 status", 0);
+ }
+
+ return;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ if (MESON_CPU_MAJOR_ID_SM1 == get_cpu_id().family_id) {
+ setenv("board_defined_bootup", "bootup_X3");
+ }
+ /**/
+ aml_config_dtb();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * set aml_dt according to chip and dram capacity
+ */
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ cpu_id_t cpu_id=get_cpu_id();
+
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ char *ddr_mode = getenv("mem_size");
+ if (MESON_CPU_MAJOR_ID_SM1 == cpu_id.family_id) {
+ switch (ddr_size) {
+ case 0x80000000:
+ if (!strcmp(ddr_mode, "1g")) {
+ strcpy(loc_name, "sm1_ac213_1g\0");
+ break;
+ }
+ strcpy(loc_name, "sm1_ac213_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "sm1_ac213_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "sm1_ac213_512m\0");
+ break;
+ default:
+ strcpy(loc_name, "sm1_ac213_unsupport");
+ break;
+ }
+ }
+ else {
+ switch (ddr_size) {
+ case 0x80000000:
+ if (!strcmp(ddr_mode, "1g")) {
+ strcpy(loc_name, "g12a_u212_1g\0");
+ break;
+ }
+ strcpy(loc_name, "g12a_u212_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "g12a_u212_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "g12a_u212_512m\0");
+ break;
+ default:
+ strcpy(loc_name, "g12a_u212_unsupport");
+ break;
+ }
+ }
+
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
generated by cgit at 2024-05-19 14:27:02 (GMT)