osd: correct osd setting for rma test [1/1]

PD#OPS-906

Problem:
SLT osd test failed on SM1

Solution:
1. correct golden data setting from env params
2. modify OSD2 enable/disable conditions

Verify:
sm1 & gxl

Change-Id: I8ab58df50ee860cb5999e3a630a4a93d11182458
Signed-off-by: Cao Jian <jian.cao@amlogic.com>

2 files changed, 34 insertions, 38 deletions

diff --git a/drivers/display/osd/osd_fb.c b/drivers/display/osd/osd_fb.c
index bb6a2d1..7b0e0e8 100644
--- a/drivers/display/osd/osd_fb.c
+++ b/drivers/display/osd/osd_fb.c
@@ -1189,9 +1189,7 @@ static int _osd_hw_init(void)
 	u32 fg = 0;
 	u32 bg = 0;
 	u32 fb_width = 0;
-	u32 fb_height = 0;;
-
-	get_osd_version();
+	u32 fb_height = 0;
 
 	vout_init();
 	fb_addr = get_fb_addr();
@@ -1247,10 +1245,6 @@ static int osd_hw_init_by_index(u32 osd_index)
 	return 0;
 }
 
-
-
-
-
 static int video_display_osd(u32 osd_index)
 {
 	struct vinfo_s *info = NULL;
@@ -1349,16 +1343,16 @@ void hist_set_golden_data(void)
 		if (str) {
 			switch (i%4) {
 				case 0:
-					hist_max_min[i/4][family_id] = env_strtoul(str, 16);
+					hist_max_min[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 				case 1:
-					hist_spl_val[i/4][family_id] = env_strtoul(str, 16);
+					hist_spl_val[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 				case 2:
-					hist_spl_pix_cnt[i/4][family_id] = env_strtoul(str, 16);
+					hist_spl_pix_cnt[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 				case 3:
-					hist_cheoma_sum[i/4][family_id] = env_strtoul(str, 16);
+					hist_cheoma_sum[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 			}
 		}
@@ -1371,6 +1365,7 @@ int osd_rma_test(u32 osd_index)
 	u32 hist_result[4];
 	u32 family_id = get_cpu_id().family_id;
 
+	get_osd_version();
 	if (osd_hw.osd_ver == OSD_SIMPLE) {
 		osd_max = 0;
 	} else if (osd_hw.osd_ver == OSD_HIGH_ONE) {
diff --git a/drivers/display/osd/osd_hw.c b/drivers/display/osd/osd_hw.c
index 5b99e6f..4e0b852 100644
--- a/drivers/display/osd/osd_hw.c
+++ b/drivers/display/osd/osd_hw.c
@@ -2143,36 +2143,37 @@ static void osd2_update_enable(void)
 	u32 video_enable = 0;
 
 	if (osd_hw.free_scale_mode[OSD2]) {
-		if (osd_hw.enable[OSD2] == ENABLE) {
+		if (osd_hw.enable[OSD2] == ENABLE)
+			VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
+						   1 << 0);
+		else
+			VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
+						   1 << 0);
+
+		/* for older chips than g12a:
+		 * freescale output always on VPP_OSD1_POSTBLEND
+		 * if freescale is enable, VPP_OSD1_POSTBLEND to control OSD1&OSD2
+		 * if freescale is disable, VPP_OSD2_POSTBLEND to control OSD2
+		 */
+		if (osd_hw.osd_ver <= OSD_NORMAL) {
 			if (osd_hw.free_scale_enable[OSD2]) {
-				if (osd_hw.osd_ver <= OSD_NORMAL)
-				VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD1_POSTBLEND
-							   | VPP_POSTBLEND_EN);
-				VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
-							   1 << 0);
+				if (osd_hw.enable[OSD2] == ENABLE)
+						VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD1_POSTBLEND
+									   | VPP_POSTBLEND_EN);
+				else
+					if (!osd_hw.enable[OSD1])
+						VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD1_POSTBLEND);
 			} else {
-				VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
-							   1 << 0);
-#ifndef CONFIG_FB_OSD2_CURSOR
-				/*
-				VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
-						VPP_OSD1_POSTBLEND);
-				*/
-#endif
-				if (osd_hw.osd_ver <= OSD_NORMAL)
-				VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD2_POSTBLEND
-							   | VPP_POSTBLEND_EN);
+				if (osd_hw.enable[OSD2] == ENABLE)
+						VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD2_POSTBLEND
+									   | VPP_POSTBLEND_EN);
+				else
+						VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD2_POSTBLEND);
 			}
-		} else {
-			if (osd_hw.enable[OSD1] == ENABLE)
-				VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD2_POSTBLEND);
-			else
-				VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD1_POSTBLEND
-							   | VPP_OSD2_POSTBLEND);
 		}
 	} else if (osd_hw.osd_ver <= OSD_NORMAL){
 		video_enable |= VSYNCOSD_RD_MPEG_REG(VPP_MISC)&VPP_VD1_PREBLEND;