author | bin.yang <bin.yang@amlogic.com> | 2019-05-10 09:03:35 (GMT) |
---|---|---|
committer | bin.yang <bin.yang@amlogic.com> | 2019-05-10 09:14:17 (GMT) |
commit | 61b68bafe414e2a773b6e5f62365c789701c38f1 (patch) | |
tree | 8a9c183a610e5ec0d854616eacf46e4c64e25513 | |
parent | 032d9f5b49e7f86bdfffdbf8783ead9ab9f9a71c (diff) | |
download | uboot-61b68bafe414e2a773b6e5f62365c789701c38f1.zip uboot-61b68bafe414e2a773b6e5f62365c789701c38f1.tar.gz uboot-61b68bafe414e2a773b6e5f62365c789701c38f1.tar.bz2 |
bootloader/uboot: Power_Consumption_Patch [2/2]
PD#
Problem:
Disable the following modules for power consumption
Solution:
Disable the following modules for power consumption
Verify:
sabrina
Change-Id: I4b1880965d15658026783141d6247310b27bc896
Signed-off-by: bin.yang <bin.yang@amlogic.com>
-rwxr-xr-x | board/amlogic/configs/sm1_sabrina_v1.h | 10 | ||||
-rwxr-xr-x | board/amlogic/sm1_sabrina_v1/firmware/timing.c | 71 |
2 files changed, 75 insertions, 6 deletions
diff --git a/board/amlogic/configs/sm1_sabrina_v1.h b/board/amlogic/configs/sm1_sabrina_v1.h index 1489c83..efe3df5 100755 --- a/board/amlogic/configs/sm1_sabrina_v1.h +++ b/board/amlogic/configs/sm1_sabrina_v1.h @@ -491,9 +491,9 @@ #define CONFIG_AML_CVBS 1 #endif -#define CONFIG_AML_LCD 1 -#define CONFIG_AML_LCD_TABLET 1 -#define CONFIG_AML_LCD_EXTERN 1 +//#define CONFIG_AML_LCD 1 +//#define CONFIG_AML_LCD_TABLET 1 +//#define CONFIG_AML_LCD_EXTERN 1 /* USB * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard @@ -661,8 +661,8 @@ #endif /* Choose One of Ethernet Type */ -#undef CONFIG_ETHERNET_NONE -#define ETHERNET_INTERNAL_PHY +#define CONFIG_ETHERNET_NONE +#undef ETHERNET_INTERNAL_PHY #undef ETHERNET_EXTERNAL_PHY #define CONFIG_CMD_AML_MTEST 1 diff --git a/board/amlogic/sm1_sabrina_v1/firmware/timing.c b/board/amlogic/sm1_sabrina_v1/firmware/timing.c index 194ee7d..3299808 100755 --- a/board/amlogic/sm1_sabrina_v1/firmware/timing.c +++ b/board/amlogic/sm1_sabrina_v1/firmware/timing.c @@ -59,13 +59,80 @@ */ ddr_set_t __ddr_setting[] = { + //A311 D T400 +#if 1 +{ + /* g12a skt (u209) lpddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1584, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + .imem_load_addr = 0xFFFC0000, //sram + .dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0,//0xffff,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 3, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40,//48, + .ac_drv_ohm = 40,//48, + + ///* + .soc_data_drv_ohm_p = 48,//30,//30, + .soc_data_drv_ohm_n = 48,//30,//30, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 48,//40,//60,// 120,//120, + .dram_data_drv_ohm = 48,// 48, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 48,// 48,//48,1rank use 48 ohm ,2rank use 80 ohm + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + //*/ + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 300,//350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29}, +// .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29}, +// .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28}, + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +#endif { /* g12a skt (u209) ddr4 */ .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, .DramType = CONFIG_DDR_TYPE_DDR4, - .DRAMFreq = {1200, 0, 0, 0}, + .DRAMFreq = {1584, 0, 0, 0}, .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, @@ -284,6 +351,7 @@ ddr_set_t __ddr_setting[] = { .magic = DRAM_CFG_MAGIC, .diagnose = CONFIG_DIAGNOSE_DISABLE, }, +#if 0 { /* g12a Y2 dongle */ .board_id = CONFIG_BOARD_ID_MASK, @@ -415,6 +483,7 @@ ddr_set_t __ddr_setting[] = { .magic = DRAM_CFG_MAGIC, .diagnose = CONFIG_DIAGNOSE_DISABLE, }, +#endif }; pll_set_t __pll_setting = { |