Merge remote-tracking branch 'remotes/trunk/amlogic-dev' into HEAD

Change-Id: I4e5fc8424f1c9e561ad068ef6b4b5fd17c6a5209

137 files changed, 6616 insertions, 1212 deletions

diff --git a/Makefile b/Makefile
index 475351f..b493f6f 100644
--- a/Makefile
+++ b/Makefile
@@ -673,6 +673,11 @@ u-boot-init := $(head-y)
 u-boot-main := $(libs-y)
 
 
+ifeq ($(CONFIG_AML_DOLBY), y)
+PLATFORM_CPPFLAGS += -I$(srctree)/drivers/display/osd/dv
+PLATFORM_LIBS += $(srctree)/drivers/display/osd/dv/dovi.a
+endif
+
 # Add GCC lib
 ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
 PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
@@ -727,7 +732,6 @@ ALL-y += u-boot.hex
 ifeq ($(CONFIG_NEED_BL301), y)
 ALL-y += bl301.bin
 endif
-ALL-$(CONFIG_AML_DOLBY) += dovi
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
 ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
@@ -872,12 +876,6 @@ acs.bin: tools prepare u-boot.bin
 bl21.bin: tools prepare u-boot.bin acs.bin
 	$(Q)$(MAKE) -C $(srctree)/$(CPUDIR)/${SOC}/firmware/bl21 all FIRMWARE=$@
 
-.PHONY : dovi
-dovi: tools prepare u-boot
-ifeq ($(CONFIG_AML_DOLBY), y)
-	$(Q)$(MAKE) -C $(srctree)/drivers/display/osd/dv dovi.o
-endif
-
 #
 # U-Boot entry point, needed for booting of full-blown U-Boot
 # from the SPL U-Boot version.
@@ -1115,7 +1113,7 @@ cmd_smap = \
 	$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
 		-c $(srctree)/common/system_map.c -o common/system_map.o
 
-u-boot:	dovi $(u-boot-init) $(u-boot-main) u-boot.lds
+u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds
 	$(call if_changed,u-boot__)
 ifeq ($(CONFIG_KALLSYMS),y)
 	$(call cmd,smap)
diff --git a/arch/arm/cpu/armv8/g12a/Makefile b/arch/arm/cpu/armv8/g12a/Makefile
index a3837c2..559f9cd 100644
--- a/arch/arm/cpu/armv8/g12a/Makefile
+++ b/arch/arm/cpu/armv8/g12a/Makefile
@@ -8,6 +8,7 @@ obj-y	+= timer.o
 obj-y	+= mailbox.o
 obj-y   += gate_init.o
 obj-y   += power_cal.o
+obj-y   += power_domain.o
 obj-$(CONFIG_CMD_PLLTEST)	+= pll.o
 obj-$(CONFIG_CMD_AML_MTEST) += core.o
 obj-$(CONFIG_AML_HDMITX20) += sound.o
diff --git a/arch/arm/cpu/armv8/g12a/firmware/acs/acs.mk b/arch/arm/cpu/armv8/g12a/firmware/acs/acs.mk
index 2294d53..883a9df 100644
--- a/arch/arm/cpu/armv8/g12a/firmware/acs/acs.mk
+++ b/arch/arm/cpu/armv8/g12a/firmware/acs/acs.mk
@@ -1,8 +1,9 @@
-SOURCES		+=	acs.c				\
-			acs_entry.S
+SOURCES		+=	acs_entry.S
 
 ifdef CONFIG_MDUMP_COMPRESS
 SOURCES		+=	ramdump.c
 endif
 
+SOURCES		+=	acs.c
+
 LINKERFILE_T		:=	acs.ld.S
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
index 388096c..abb653f 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
@@ -891,6 +891,7 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
 	enum hdmi_vic vic = hdev->vic;
 	enum hdmi_color_format cs = hdev->para->cs;
 	enum hdmi_color_depth cd = hdev->para->cd;
+	char *sspll_dis = NULL;
 
 	/* YUV 422 always use 24B mode */
 	if (cs == HDMI_COLOR_FORMAT_422)
@@ -949,7 +950,9 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
 next:
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev);
-	if (!getenv("sspll_dis"))
+	sspll_dis = getenv("sspll_dis");
+	if ((!sspll_dis || !strcmp(sspll_dis, "0")) &&
+		(cd == HDMI_COLOR_DEPTH_24B))
 		set_hpll_sspll(hdev);
 	set_hpll_od1(p_enc[j].od1);
 	set_hpll_od2(p_enc[j].od2);
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
index 700d9c0..57e1f2b 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
@@ -137,9 +137,7 @@ static void dump_regs(void)
 			reg_val = hdmitx_rd_reg(reg_adr);
 		}
 		if (reg_val) {
-			// excluse HDCP regisiters
-			if ((reg_adr < HDMITX_DWC_A_HDCPCFG0) || (reg_adr > HDMITX_DWC_CEC_CTRL))
-				printk("DWC[0x%x]: 0x%x\n", reg_adr, reg_val);
+			printk("DWC[0x%x]: 0x%x\n", reg_adr, reg_val);
 		}
 	}
 }
@@ -427,6 +425,7 @@ void hdmi_tx_init(void)
 void hdmi_tx_set(struct hdmitx_dev *hdev)
 {
 	unsigned char checksum[11];
+	char *p_tmp;
 
 	aml_audio_init(); /* Init audio hw firstly */
 	hdmitx_hw_init();
@@ -436,7 +435,9 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)
 	hdmitx_set_audmode(hdev);
 	hdmitx_debug();
 	//kernel will determine output mode on its own
-	setenv("hdmimode", getenv("outputmode"));
+	p_tmp = getenv("outputmode");
+	if (NULL != p_tmp)
+		setenv("hdmimode", p_tmp);
 
 	/* null char needed to terminate the string
 	   otherwise garbage in checksum logopara */
@@ -1654,13 +1655,11 @@ static void hdmi_tvenc4k2k_set(enum hdmi_vic vic)
 	unsigned long hsync_pixels_venc = 0;
 
 	unsigned long de_h_begin = 0, de_h_end = 0;
-	unsigned long de_v_begin_even = 0, de_v_end_even = 0,
-		de_v_begin_odd = 0, de_v_end_odd = 0;
+	unsigned long de_v_begin_even = 0, de_v_end_even = 0;
 	unsigned long hs_begin = 0, hs_end = 0;
 	unsigned long vs_adjust = 0;
-	unsigned long vs_bline_evn = 0, vs_eline_evn = 0, vs_bline_odd = 0,
-		vs_eline_odd = 0;
-	unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
+	unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
+	unsigned long vso_begin_evn = 0;
 
 	switch (vic) {
 	case HDMI_3840x2160p30_16x9:
@@ -1782,16 +1781,6 @@ static void hdmi_tvenc4k2k_set(enum hdmi_vic vic)
 	de_v_end_even  = modulo(de_v_begin_even + ACTIVE_LINES, TOTAL_LINES);
 	hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
 	hd_write_reg(P_ENCP_DE_V_END_EVEN,  de_v_end_even);
-	/* Program DE timing for odd field if needed */
-	if (INTERLACE_MODE) {
-		de_v_begin_odd = to_signed(
-			(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4)
-			+ de_v_begin_even + (TOTAL_LINES-1)/2;
-		de_v_end_odd = modulo(de_v_begin_odd + ACTIVE_LINES,
-			TOTAL_LINES);
-		hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
-		hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
-	}
 
 	/* Program Hsync timing */
 	if (de_h_end + front_porch_venc >= total_pixels_venc) {
@@ -1818,17 +1807,6 @@ static void hdmi_tvenc4k2k_set(enum hdmi_vic vic)
 	vso_begin_evn = hs_begin;
 	hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn);
 	hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn);
-	/* Program Vsync timing for odd field if needed */
-	if (INTERLACE_MODE) {
-		vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
-		vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
-		vso_begin_odd  = modulo(hs_begin + (total_pixels_venc>>1),
-			total_pixels_venc);
-		hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
-	}
 	hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
 			(0 << 1) |
 			(HSYNC_POLARITY << 2) |
@@ -2025,14 +2003,13 @@ static void hdmi_tvenc_set_def(enum hdmi_vic vic)
 	unsigned long hsync_pixels_venc = 0;
 
 	unsigned long de_h_begin = 0, de_h_end = 0;
-	unsigned long de_v_begin_even = 0, de_v_end_even = 0,
-		de_v_begin_odd = 0, de_v_end_odd = 0;
+	unsigned long de_v_begin_even = 0, de_v_end_even = 0;
 	unsigned long hs_begin = 0, hs_end = 0;
 	unsigned long vs_adjust = 0;
-	unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
-		vs_bline_odd = 0, vs_eline_odd = 0;
-	unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
-        hdmitx_debug();
+	unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
+	unsigned long vso_begin_evn = 0;
+
+	hdmitx_debug();
 	switch (vic) {
 	case HDMI_720x480p60_16x9:
 	case HDMI_720x480p120_16x9:
@@ -2168,15 +2145,6 @@ static void hdmi_tvenc_set_def(enum hdmi_vic vic)
 	de_v_end_even  = de_v_begin_even + ACTIVE_LINES;
 	hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
 	hd_write_reg(P_ENCP_DE_V_END_EVEN,  de_v_end_even);	/* 522 */
-	/* Program DE timing for odd field if needed */
-	if (INTERLACE_MODE) {
-		de_v_begin_odd = to_signed(
-			(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST)
-			& 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2;
-		de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
-		hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
-		hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
-	}
 
 	/* Program Hsync timing */
 	if (de_h_end + front_porch_venc >= total_pixels_venc) {
@@ -2203,17 +2171,7 @@ static void hdmi_tvenc_set_def(enum hdmi_vic vic)
 	vso_begin_evn = hs_begin; /* 1692 */
 	hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn);  /* 1692 */
 	hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn);  /* 1692 */
-	/* Program Vsync timing for odd field if needed */
-	if (INTERLACE_MODE) {
-		vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
-		vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
-		vso_begin_odd  = modulo(hs_begin + (total_pixels_venc>>1),
-			total_pixels_venc);
-		hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
-	}
+
 	switch (vic) {
 	case HDMI_720x480i60_16x9:
 	case HDMI_720x576i50_16x9:
@@ -2323,13 +2281,11 @@ static void hdmi_tvenc_vesa_set(enum hdmi_vic vic)
 	unsigned long hsync_pixels_venc = 0;
 
 	unsigned long de_h_begin = 0, de_h_end = 0;
-	unsigned long de_v_begin_even = 0, de_v_end_even = 0,
-		de_v_begin_odd = 0, de_v_end_odd = 0;
+	unsigned long de_v_begin_even = 0, de_v_end_even = 0;
 	unsigned long hs_begin = 0, hs_end = 0;
 	unsigned long vs_adjust = 0;
-	unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
-		vs_bline_odd = 0, vs_eline_odd = 0;
-	unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
+	unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
+	unsigned long vso_begin_evn = 0;
 	struct hdmi_format_para *vpara = NULL;
 	struct hdmi_cea_timing *vtiming = NULL;
 
@@ -2377,15 +2333,6 @@ static void hdmi_tvenc_vesa_set(enum hdmi_vic vic)
 	de_v_end_even  = de_v_begin_even + ACTIVE_LINES;
 	hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
 	hd_write_reg(P_ENCP_DE_V_END_EVEN,  de_v_end_even);	/* 522 */
-	/* Program DE timing for odd field if needed */
-	if (INTERLACE_MODE) {
-		de_v_begin_odd = to_signed(
-			(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST)
-			& 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2;
-		de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
-		hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
-		hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
-	}
 
 	/* Program Hsync timing */
 	if (de_h_end + front_porch_venc >= total_pixels_venc) {
@@ -2412,17 +2359,6 @@ static void hdmi_tvenc_vesa_set(enum hdmi_vic vic)
 	vso_begin_evn = hs_begin; /* 1692 */
 	hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn);  /* 1692 */
 	hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn);  /* 1692 */
-	/* Program Vsync timing for odd field if needed */
-	if (INTERLACE_MODE) {
-		vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
-		vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
-		vso_begin_odd  = modulo(hs_begin + (total_pixels_venc>>1),
-			total_pixels_venc);
-		hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
-		hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
-	}
 
 	switch (vic) {
 	case HDMIV_640x480p60hz:
@@ -2850,11 +2786,11 @@ void hdmitx_set_drm_pkt(struct master_display_info_s *data)
 	 *hdr_transfer_feature: bit 15-8: transfer_characteristic
 	 *	1:bt709 0xe:bt2020-10 0x10:smpte-st-2084 0x12:hlg(todo)
 	 */
-	if (data) {
-		hdr_transfer_feature = (data->features >> 8) & 0xff;
-		hdr_color_feature = (data->features >> 16) & 0xff;
+	if (NULL == data) {
+		return;
 	}
-
+	hdr_transfer_feature = (data->features >> 8) & 0xff;
+	hdr_color_feature = (data->features >> 16) & 0xff;
 	DRM_DB[1] = 0x0;
 	DRM_DB[2] = GET_LOW8BIT(data->primaries[0][0]);
 	DRM_DB[3] = GET_HIGH8BIT(data->primaries[0][0]);
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/reg_ops.c b/arch/arm/cpu/armv8/g12a/hdmitx20/reg_ops.c
index 2c0e1ce..96616fe 100644
--- a/arch/arm/cpu/armv8/g12a/hdmitx20/reg_ops.c
+++ b/arch/arm/cpu/armv8/g12a/hdmitx20/reg_ops.c
@@ -80,9 +80,12 @@ unsigned int hdmitx_rd_reg(unsigned int addr)
 		small_offset = small_offset << 2;
 	}
 	data = hd_read_reg(large_offset + small_offset);
-	if (dbg_en)
-		pr_info("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
-			addr, data);
+	if (dbg_en) {
+		if (large_offset == HDMITX_DWC_BASE_OFFSET)
+			pr_info("%s rd[0x%x] 0x%x\n", "DWC", addr, data);
+		else
+			pr_info("%s rd[0x%x] 0x%x\n", "TOP", addr, data);
+	}
 	return data;
 }
 
@@ -99,9 +102,12 @@ void hdmitx_wr_reg(unsigned int addr, unsigned int data)
 	}
 	hd_write_reg(large_offset + small_offset, data);
 
-	if (dbg_en)
-		pr_info("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
-			addr, data);
+	if (dbg_en) {
+		if (large_offset == HDMITX_DWC_BASE_OFFSET)
+			pr_info("%s wr[0x%x] 0x%x\n", "DWC", addr, data);
+		else
+			pr_info("%s wr[0x%x] 0x%x\n", "TOP", addr, data);
+	}
 }
 
 void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
diff --git a/arch/arm/cpu/armv8/g12a/pll.c b/arch/arm/cpu/armv8/g12a/pll.c
index 8748a49..0750818 100644
--- a/arch/arm/cpu/armv8/g12a/pll.c
+++ b/arch/arm/cpu/armv8/g12a/pll.c
@@ -35,19 +35,23 @@ Description:
 #define STR_PLL_TEST_DDR	"ddr"
 #define STR_PLL_TEST_HDMI	"hdmi"
 #define STR_PLL_TEST_GP0	"gp0"
+#define STR_PLL_TEST_HIFI	"hifi"
+#define STR_PLL_TEST_PCIE	"pcie"
+#define STR_PLL_TEST_ETHPHY	"ethphy"
+#define STR_PLL_TEST_USBPHY	"usbphy"
 
-#define PLL_LOCK_CHECK_MAX		20
+
+#define PLL_LOCK_CHECK_MAX		3
 
 #define RET_PLL_LOCK_FAIL		0x1000
 #define RET_CLK_NOT_MATCH		0x1
-#define SYS_PLL_DIV16_CNTL		(1<<24)
-#define SYS_CLK_DIV16_CNTL		(1)
+#define SYS_PLL_DIV16_CNTL		(1 << 24)
+#define SYS_CLK_DIV16_CNTL		(1 << 1)
 #define SYS_PLL_TEST_DIV		4	/* div16 */
-#define HDMI_PLL_DIV_CNTL		(1<<18)
-#define HDMI_PLL_DIV_GATE		(1<<19)
+#define HDMI_PLL_DIV_CNTL		(1 << 18)
+#define HDMI_PLL_DIV_GATE		(1 << 19)
 
 #define PLL_DIV16_OFFSET		4	/* div2/2/4 */
-#define GP0_PLL_TEST_DIV		0	/* div1 */
 
 #define Wr(addr, data) writel(data, addr)
 #define Rd(addr) readl(addr)
@@ -61,25 +65,8 @@ static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set);
 static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set);
 static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg);
 static int gp0_pll_test(gp0_pll_set_t * gp0_pll);
-static int gp0_pll_test_all(void);
-
-#if 0
-static unsigned int pll_range[PLL_ENUM][2] = {
-	{101, 202}, //sys pll range
-	{303, 404}, //fix pll range
-	{505, 606}, //ddr pll range
-	{707, 808}, //hdmi pll range
-	{909, 999}, // pll range
-};
-
-static char pll_range_ind[PLL_ENUM][10] = {
-	"sys",
-	"fix",
-	"ddr",
-	"hdmi",
-	"gp0",
-};
-#endif
+static int gp0_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg);
+static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg);
 
 static void update_bits(size_t reg, size_t mask, unsigned int val)
 {
@@ -90,78 +77,79 @@ static void update_bits(size_t reg, size_t mask, unsigned int val)
 	writel(tmp, reg);
 }
 
-hdmi_pll_cfg_t hdmi_pll_cfg = {
-#if 0
-	.hdmi_pll[0] = {
-		.pll_clk   = 5940, /* MHz */
-		.pll_cntl0 = 0x0b3a0400 | (0x7b & 0xff) | (0x3 << 28),
-		.pll_cntl1 = 0x00018000,
+
+gp0_pll_cfg_t gp0_pll_cfg = {
+	.gp0_pll[0] = {
+		.pll_clk   = 750, /* MHz */
+		.pll_cntl0 = 0x080304fa,
+		.pll_cntl1 = 0x00000000,
 		.pll_cntl2 = 0x00000000,
-		.pll_cntl3 = 0x6a68dc00,
-		.pll_cntl4 = 0x65771290,
+		.pll_cntl3 = 0x48681c00,
+		.pll_cntl4 = 0x88770290,
 		.pll_cntl5 = 0x39272000,
 		.pll_cntl6 = 0x56540000
 	},
-#endif
-	.hdmi_pll[0] = {
-		.pll_clk   = 5405, /* MHz */
-		.pll_cntl0 = 0x3b0004e1,
-		.pll_cntl1 = 0x00007333,
-		.pll_cntl2 = 0x00000000,
-		.pll_cntl3 = 0x0a691c00,
-		.pll_cntl4 = 0x33771290,
-		.pll_cntl5 = 0x39270000,
-		.pll_cntl6 = 0x50540000
-	},
-	.hdmi_pll[1] = {
-		.pll_clk   = 4455,
-		.pll_cntl0 = 0x3b0004b9,
-		.pll_cntl1 = 0x00014000,
+	.gp0_pll[1] = {
+		.pll_clk   = 375, /* MHz */
+		.pll_cntl0 = 0X0803047d,
+		.pll_cntl1 = 0x00006aab,
 		.pll_cntl2 = 0x00000000,
-		.pll_cntl3 = 0x0a691c00,
-		.pll_cntl4 = 0x33771290,
-		.pll_cntl5 = 0x39270000,
-		.pll_cntl6 = 0x50540000
+		.pll_cntl3 = 0x6a295c00,
+		.pll_cntl4 = 0x65771290,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x54540000
 	},
-#if 0
-	.hdmi_pll[3] = {
-		.pll_clk   = 3712,
-		.pll_cntl0 = 0x3b00049a,
-		.pll_cntl1 = 0x00016000,
+};
+
+hdmi_pll_cfg_t hdmi_pll_cfg = {
+	.hdmi_pll[0] = {
+		.pll_clk   = 46, /* MHz */
+		.pll_cntl0 = 0x0b3a04f7,
+		.pll_cntl1 = 0x00010000,
 		.pll_cntl2 = 0x00000000,
-		.pll_cntl3 = 0x0a691c00,
-		.pll_cntl4 = 0x33771290,
-		.pll_cntl5 = 0x39270000,
-		.pll_cntl6 = 0x50540000
+		.pll_cntl3 = 0x6a28dc00,
+		.pll_cntl4 = 0x65771290,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x56540000
 	},
-#endif
-	.hdmi_pll[2] = {
-		.pll_clk   = 3450,
-		.pll_cntl0 = 0x3b00048f,
+	.hdmi_pll[1] = {
+		.pll_clk   = 23,
+		.pll_cntl0 = 0x0b3a047b,
 		.pll_cntl1 = 0x00018000,
 		.pll_cntl2 = 0x00000000,
-		.pll_cntl3 = 0x0a691c00,
-		.pll_cntl4 = 0x33771290,
-		.pll_cntl5 = 0x39270000,
-		.pll_cntl6 = 0x50540000
+		.pll_cntl3 = 0x6a29dc00,
+		.pll_cntl4 = 0x65771290,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x54540000
 	},
-	.hdmi_pll[3] = {
-		.pll_clk   = 2970,
-		.pll_cntl0 = 0x3b00047b,
-		.pll_cntl1 = 0x00018000,
+	.hdmi_pll[2] = {
+		.pll_clk   = 2967,
+		.pll_cntl0 = 0x0b1004f7,
+		.pll_cntl1 = 0x00008147,
 		.pll_cntl2 = 0x00000000,
-		.pll_cntl3 = 0x0a691c00,
-		.pll_cntl4 = 0x33771290,
-		.pll_cntl5 = 0x39270000,
-		.pll_cntl6 = 0x50540000
+		.pll_cntl3 = 0x6a685c00,
+		.pll_cntl4 = 0x11551293,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x56540000
 	},
 };
 
-uint32_t sys_pll_clk[PLL_TEST_SYS_TOTAL] = {960, 1056, 1152, 1248, 1344, 1440, 1536, 1632};
+uint32_t sys_pll_clk[] = {750, 375};
 sys_pll_cfg_t sys_pll_cfg = {
 	.sys_pll[0] = {
-		.cpu_clk   = 960,
-		.pll_cntl  = 0,
+		.cpu_clk   = 750,
+		.pll_cntl  = 0X080304fa,
+		.pll_cntl1 = 0x0,
+		.pll_cntl2 = 0x0,
+		.pll_cntl3 = 0x48681c00,
+		.pll_cntl4 = 0x88770290,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x56540000
+	},
+
+	.sys_pll[1] = {
+		.cpu_clk   = 375,
+		.pll_cntl  = 0X0803047d,
 		.pll_cntl1 = 0x0,
 		.pll_cntl2 = 0x0,
 		.pll_cntl3 = 0x48681c00,
@@ -171,24 +159,40 @@ sys_pll_cfg_t sys_pll_cfg = {
 	},
 };
 
-#define GPLL0_RATE(_rate, _m, _n, _od) \
-{							\
-		.rate	=	(_rate),				\
-		.m		=	(_m),					\
-		.n		=	(_n),					\
-		.od		=	(_od),					\
-}
+uint32_t hifi_pll_clk[] = {751, 375};
+hifi_pll_cfg_t hifi_pll_cfg = {
+	.hifi_pll[0] = {
+		.pll_clk   = 751,
+		.pll_cntl0 = 0X080304fa,
+		.pll_cntl1 = 0X00006aab,
+		.pll_cntl2 = 0x0,
+		.pll_cntl3 = 0x6a285c00,
+		.pll_cntl4 = 0x65771290,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x56540000
+	},
+
+	.hifi_pll[1] = {
+		.pll_clk   = 375,
+		.pll_cntl0 = 0X0803047d,
+		.pll_cntl1 = 0X00006aab,
+		.pll_cntl2 = 0x0,
+		.pll_cntl3 = 0x6a295c00,
+		.pll_cntl4 = 0x65771290,
+		.pll_cntl5 = 0x39272000,
+		.pll_cntl6 = 0x54540000
+	},
+};
 
-static gpll_rate_table_t gpll0_tbl[] = {
-	GPLL0_RATE(408,  136, 1, 3), /*DCO=3264M*/
-	GPLL0_RATE(600,  200, 1, 3), /*DCO=4800M*/
-	GPLL0_RATE(696,  232, 1, 3), /*DCO=5568M*/
-	GPLL0_RATE(792,  132, 1, 2), /*DCO=3168M*/
-	GPLL0_RATE(846,  141, 1, 2), /*DCO=3384M*/
-	GPLL0_RATE(912,  152, 1, 2), /*DCO=3648M*/
+/*PCIE clk_out = 24M*m/2^(n+1)/OD*/
+static const struct pciepll_rate_table pcie_pll_rate_table[] = {
+	PLL_RATE(100, 200, 1, 12),
 };
 
-static void pll_report(unsigned int flag, char * name) {
+unsigned long usbphy_base_cfg[2] = {CONFIG_USB_PHY_20, CONFIG_USB_PHY_21};
+
+static void pll_report(unsigned int flag, char * name)
+{
 	if (flag)
 		printf("%s pll test failed!\n", name);
 	else
@@ -196,7 +200,10 @@ static void pll_report(unsigned int flag, char * name) {
 	return;
 }
 
-static int clk_around(unsigned int clk, unsigned int cmp) {
+static int clk_around(unsigned int clk, unsigned int cmp)
+{
+	if (cmp == 1)
+		cmp += 1;
 	if (((cmp-2) <= clk) && (clk <= (cmp+2)))
 		return 1;
 	else
@@ -308,16 +315,20 @@ static void clocks_set_sys_cpu_clk(uint32_t freq, uint32_t pclk_ratio, uint32_t
 	Wr( HHI_SYS_CPU_CLK_CNTL1, control1 );
 }
 
-static int sys_pll_init(sys_pll_set_t * sys_pll_set) {
+static int sys_pll_init(sys_pll_set_t * sys_pll_set)
+{
 	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+
 	do {
-		Wr(HHI_SYS_PLL_CNTL0, sys_pll_set->pll_cntl|(1<<29));
+		Wr(HHI_SYS_PLL_CNTL0, sys_pll_set->pll_cntl);
+		Wr(HHI_SYS_PLL_CNTL0, sys_pll_set->pll_cntl | (3 << 28));
 		Wr(HHI_SYS_PLL_CNTL1, sys_pll_set->pll_cntl1);
 		Wr(HHI_SYS_PLL_CNTL2, sys_pll_set->pll_cntl2);
 		Wr(HHI_SYS_PLL_CNTL3, sys_pll_set->pll_cntl3);
 		Wr(HHI_SYS_PLL_CNTL4, sys_pll_set->pll_cntl4);
 		Wr(HHI_SYS_PLL_CNTL5, sys_pll_set->pll_cntl5);
-		Wr(HHI_SYS_PLL_CNTL0, ((1<<30)|(1<<29)|sys_pll_set->pll_cntl));
+		Wr(HHI_SYS_PLL_CNTL6, sys_pll_set->pll_cntl6);
+		Wr(HHI_SYS_PLL_CNTL0, ((1<<29) | Rd(HHI_SYS_PLL_CNTL0)));
 		Wr(HHI_SYS_PLL_CNTL0, Rd(HHI_SYS_PLL_CNTL0)&(~(1<<29)));
 		_udelay(20);
 		//printf("pll lock check %d\n", lock_check);
@@ -328,17 +339,14 @@ static int sys_pll_init(sys_pll_set_t * sys_pll_set) {
 		return RET_PLL_LOCK_FAIL;
 }
 
-static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg) {
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg)
+{
 	unsigned int i=0;
 	int ret=0;
-/*
-	for (i=0; i<(sizeof(sys_pll_cfg_t)/sizeof(sys_pll_set_t)); i++) {
-		ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
-	}
-*/
+
 	for (i=0; i<(sizeof(sys_pll_clk)/sizeof(uint32_t)); i++) {
 		sys_pll_cfg->sys_pll[0].cpu_clk = sys_pll_clk[i];
-		ret += sys_pll_test(&(sys_pll_cfg->sys_pll[0]));
+		ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
 	}
 	return ret;
 }
@@ -347,26 +355,26 @@ static int sys_pll_test(sys_pll_set_t * sys_pll_set) {
 	unsigned int clk_msr_reg = 0;
 	unsigned int clk_msr_val = 0;
 	unsigned int sys_clk = 0;
-	unsigned int sys_pll_cntl = 0;
+	sys_pll_set_t sys_pll;
 	int ret=0;
 
 	/* switch sys clk to oscillator */
 	clocks_set_sys_cpu_clk( 0, 0, 0, 0);
 
 	/* store current sys pll cntl */
-	sys_pll_set_t sys_pll;
 	sys_pll.pll_cntl = readl(HHI_SYS_PLL_CNTL0);
 	sys_pll.pll_cntl1 = readl(HHI_SYS_PLL_CNTL1);
 	sys_pll.pll_cntl2 = readl(HHI_SYS_PLL_CNTL2);
 	sys_pll.pll_cntl3 = readl(HHI_SYS_PLL_CNTL3);
 	sys_pll.pll_cntl4 = readl(HHI_SYS_PLL_CNTL4);
 	sys_pll.pll_cntl5 = readl(HHI_SYS_PLL_CNTL5);
+	sys_pll.pll_cntl6 = readl(HHI_SYS_PLL_CNTL6);
 
 	if (sys_pll_set->cpu_clk == 0) {
 		sys_clk = (24 / ((sys_pll_set->pll_cntl>>10)&0x1F) * (sys_pll_set->pll_cntl&0x1FF)) >> ((sys_pll_set->pll_cntl>>16)&0x3);
-	}
-	else {
+	} else {
 		sys_clk = sys_pll_set->cpu_clk;
+#if 0
 		if (sys_clk <= 750) {
 			/* VCO/8, OD=3 */
 			sys_pll_cntl = (3<<16/* OD */) | (1<<10/* N */) | (sys_clk / 3 /*M*/);
@@ -380,6 +388,7 @@ static int sys_pll_test(sys_pll_set_t * sys_pll_set) {
 			sys_pll_cntl = (1<<16/* OD */) | (1<<10/* N */) | (sys_clk / 12 /*M*/);
 		}
 		sys_pll_set->pll_cntl = 0x38000000 | sys_pll_cntl;
+#endif
 	}
 
 	/* store CPU clk msr reg, restore it when test done */
@@ -404,16 +413,14 @@ static int sys_pll_test(sys_pll_set_t * sys_pll_set) {
 	_udelay(100);
 	if (ret) {
 		printf("SYS pll lock Failed! - %4d MHz\n", sys_clk);
-	}
-	else {
+	} else {
 		printf("SYS pll lock OK! - %4d MHz. Div16 - %4d MHz. ", sys_clk, sys_clk>>PLL_DIV16_OFFSET);
 		clk_msr_val = clk_util_clk_msr(17);
 		printf("CLKMSR(17) - %4d MHz ", clk_msr_val);
 		if (clk_around(clk_msr_val, sys_clk>>SYS_PLL_TEST_DIV)) {
 			/* sys clk/pll div16 */
 			printf(": Match\n");
-		}
-		else {
+		} else {
 			ret = RET_CLK_NOT_MATCH;
 			printf(": MisMatch\n");
 		}
@@ -428,18 +435,23 @@ static int sys_pll_test(sys_pll_set_t * sys_pll_set) {
 	return ret;
 }
 
-static int fix_pll_test(void) {
+static int fix_pll_test(void)
+{
 	return 0;
 }
 
-static int ddr_pll_test(void) {
+static int ddr_pll_test(void)
+{
 	return 0;
 }
 
-static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set) {
+static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set)
+{
 	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+
 	do {
 		Wr(P_HHI_HDMI_PLL_CNTL0, hdmi_pll_set->pll_cntl0);
+		Wr(P_HHI_HDMI_PLL_CNTL0, hdmi_pll_set->pll_cntl0 | (3 << 28));
 		Wr(P_HHI_HDMI_PLL_CNTL1, hdmi_pll_set->pll_cntl1);
 		Wr(P_HHI_HDMI_PLL_CNTL2, hdmi_pll_set->pll_cntl2);
 		Wr(P_HHI_HDMI_PLL_CNTL3, hdmi_pll_set->pll_cntl3);
@@ -449,7 +461,7 @@ static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set) {
 		Wr(P_HHI_HDMI_PLL_CNTL0, Rd(P_HHI_HDMI_PLL_CNTL0) | (1<<29));
 		Wr(P_HHI_HDMI_PLL_CNTL0, Rd(P_HHI_HDMI_PLL_CNTL0) & (~(1<<29)));
 		//printf("lock_check: %d\n", lock_check);
-		_udelay(20);
+		_udelay(100);
 	} while ((!(0x3==((readl(P_HHI_HDMI_PLL_CNTL0)>>30)&0x3))) && --lock_check);
 	if (lock_check != 0)
 		return 0;
@@ -457,16 +469,18 @@ static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set) {
 		return RET_PLL_LOCK_FAIL;
 }
 
-static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg) {
+static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg)
+{
 	unsigned int i=0;
 	int ret=0;
-	for (i=0; i<(sizeof(hdmi_pll_cfg_t)/sizeof(hdmi_pll_set_t)); i++) {
+
+	for (i=0; i<(sizeof(hdmi_pll_cfg_t)/sizeof(hdmi_pll_set_t)); i++)
 		ret += hdmi_pll_test(&(hdmi_pll_cfg->hdmi_pll[i]));
-	}
 	return ret;
 }
 
-static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set) {
+static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set)
+{
 	unsigned int i=0;
 	unsigned int pll_clk = 0;
 	unsigned int pll_clk_div = 0;
@@ -474,28 +488,12 @@ static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set) {
 	unsigned int clk_msr_reg = 0;
 	int ret = 0;
 
-#if 0
-	/* store current pll cntl */
-	hdmi_pll_set_t hdmi_pll;
-	hdmi_pll.pll_cntl = readl(P_HHI_HDMI_PLL_CNTL0);
-	hdmi_pll.pll_cntl1 = readl(P_HHI_HDMI_PLL_CNTL1);
-	hdmi_pll.pll_cntl2 = readl(P_HHI_HDMI_PLL_CNTL2);
-	hdmi_pll.pll_cntl3 = readl(P_HHI_HDMI_PLL_CNTL3);
-	hdmi_pll.pll_cntl4 = readl(P_HHI_HDMI_PLL_CNTL4);
-	hdmi_pll.pll_cntl5 = readl(P_HHI_HDMI_PLL_CNTL5);
-#endif
-
 	/* store pll div setting */
 	clk_msr_reg = readl(HHI_VID_PLL_CLK_DIV);
 	/* connect vid_pll_div to HDMIPLL directly */
-	//writel(clk_msr_reg | HDMI_PLL_DIV_CNTL | HDMI_PLL_DIV_GATE, HHI_VID_PLL_CLK_DIV);
 	clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<19);
 	clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
 
-#if 0
-	/* div1 */
-	setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<18);
-#else
 	/* div14 */
 	clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<18);
 	clrbits_le32(HHI_VID_PLL_CLK_DIV, 0x3<<16);
@@ -505,22 +503,21 @@ static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set) {
 	setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
 	setbits_le32(HHI_VID_PLL_CLK_DIV, 0x3f80);
 	clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
-#endif
+
 	setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<19);
 
 	/* test pll */
 	for (i=0; i<(sizeof(hdmi_pll_cfg_t)/sizeof(hdmi_pll_set_t)); i++) {
-		if (hdmi_pll_set->pll_cntl0 == hdmi_pll_cfg.hdmi_pll[i].pll_cntl0) {
+		if (hdmi_pll_set->pll_cntl0 == hdmi_pll_cfg.hdmi_pll[i].pll_cntl0)
 			pll_clk = hdmi_pll_cfg.hdmi_pll[i].pll_clk;
-		}
 	}
+
 	_udelay(100);
 	ret = hdmi_pll_init(hdmi_pll_set);
 	_udelay(100);
 	if (ret) {
 		printf("HDMI pll lock Failed! - %4d MHz\n", pll_clk);
-	}
-	else {
+	} else {
 		pll_clk_div = pll_clk/14;
 		printf("HDMI pll lock OK! - %4d MHz. Div14 - %4d MHz. ", pll_clk, pll_clk_div);
 		/* get [  55][1485 MHz] vid_pll_div_clk_out */
@@ -528,64 +525,163 @@ static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set) {
 		printf("CLKMSR(55) - %4d MHz ", clk_msr_val);
 		if (clk_around(clk_msr_val, pll_clk_div)) {
 			printf(": Match\n");
-		}
-		else {
+		} else {
 			ret = RET_CLK_NOT_MATCH;
 			printf(": MisMatch\n");
 		}
 	}
 
 	/* restore pll */
-	//hdmi_pll_init(hdmi_pll);
-	//hdmi_pll_init(hdmi_pll_cfg->hdmi_pll[0]);
-
 	/* restore div cntl bit */
 	writel(clk_msr_reg, HHI_VID_PLL_CLK_DIV);
 
 	return ret;
 }
 
-static int gp0_pll_test(gp0_pll_set_t * gp0_pll) {
+static int gp0_pll_test(gp0_pll_set_t * gp0_pll)
+{
 	int ret=0;
-	unsigned int i=0, pll_clk=0;
 	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
-	unsigned int clk_msr_val = 0, od=0;
-
-	for (i=0; i<(sizeof(gpll0_tbl)/sizeof(gpll0_tbl[0])); i++) {
-		if ((gp0_pll->pll_cntl0 & 0xFF) == gpll0_tbl[i].m) {
-			pll_clk = gpll0_tbl[i].rate;
-			od = gpll0_tbl[i].od;
-		}
-	}
+	unsigned int clk_msr_val = 0;
 
-	writel(gp0_pll->pll_cntl0, HHI_GP0_PLL_CNTL0);
-	writel(gp0_pll->pll_cntl1, HHI_GP0_PLL_CNTL1);
-	writel(gp0_pll->pll_cntl2, HHI_GP0_PLL_CNTL2);
-	writel(gp0_pll->pll_cntl3, HHI_GP0_PLL_CNTL3);
-	writel(gp0_pll->pll_cntl4, HHI_GP0_PLL_CNTL4);
-	writel(gp0_pll->pll_cntl5, HHI_GP0_PLL_CNTL5);
-	writel(gp0_pll->pll_cntl6, HHI_GP0_PLL_CNTL6);
 	lock_check = PLL_LOCK_CHECK_MAX;
 	do {
-		update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 1 << 29);
+		writel(gp0_pll->pll_cntl0, HHI_GP0_PLL_CNTL0);
+		writel(gp0_pll->pll_cntl0 | (3 << 28), HHI_GP0_PLL_CNTL0);
+		writel(gp0_pll->pll_cntl1, HHI_GP0_PLL_CNTL1);
+		writel(gp0_pll->pll_cntl2, HHI_GP0_PLL_CNTL2);
+		writel(gp0_pll->pll_cntl3, HHI_GP0_PLL_CNTL3);
+		writel(gp0_pll->pll_cntl4, HHI_GP0_PLL_CNTL4);
+		writel(gp0_pll->pll_cntl5, HHI_GP0_PLL_CNTL5);
+		writel(gp0_pll->pll_cntl6, HHI_GP0_PLL_CNTL6);
+
+		writel(readl(HHI_GP0_PLL_CNTL0)|(1 << 29), HHI_GP0_PLL_CNTL0);
 		_udelay(10);
-		update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 0);
+		writel(readl(HHI_GP0_PLL_CNTL0)&(~(1<<29)), HHI_GP0_PLL_CNTL0);
 		_udelay(100);
 		//printf("gp0 lock_check: %4d\n", lock_check);
 	} while ((!((readl(HHI_GP0_PLL_CNTL0)>>31)&0x1)) && --lock_check);
 	if (0 == lock_check) {
-		printf("GP0 pll lock Failed! - %4d MHz\n", pll_clk);
+		printf("GP0 pll lock Failed! - %4d MHz\n", gp0_pll->pll_clk);
 		ret = RET_PLL_LOCK_FAIL;
-	}
-	else {
-		printf("GP0 pll lock OK! - %4d MHz. ", pll_clk);
+	} else {
+		printf("GP0 pll lock OK! - %4d MHz. ", gp0_pll->pll_clk);
 		/* get gp0_pll_clk */
-		clk_msr_val = clk_util_clk_msr(4) << (5-od);
+		clk_msr_val = clk_util_clk_msr(4);
 		printf("CLKMSR(4) - %4d MHz ", clk_msr_val);
-		if (clk_around(clk_msr_val, pll_clk)) {
+		if (clk_around(clk_msr_val, gp0_pll->pll_clk)) {
 			printf(": Match\n");
+		} else {
+			printf(": MisMatch\n");
+			ret = RET_CLK_NOT_MATCH;
 		}
-		else {
+	}
+	return ret;
+}
+
+static int gp0_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg)
+{
+	unsigned int i=0;
+	int ret=0;
+	for (i=0; i<(sizeof(gp0_pll_cfg_t)/sizeof(gp0_pll_set_t)); i++)
+		ret += gp0_pll_test(&(gp0_pll_cfg->gp0_pll[i]));
+	return ret;
+}
+
+static int hifi_pll_test(hifi_pll_set_t * hifi_pll)
+{
+	int ret=0;
+	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+	unsigned int clk_msr_val = 0;
+
+	do {
+		writel(hifi_pll->pll_cntl0, HHI_HIFI_PLL_CNTL0);
+		writel(hifi_pll->pll_cntl0 | (3 << 28), HHI_HIFI_PLL_CNTL0);
+		writel(hifi_pll->pll_cntl1, HHI_HIFI_PLL_CNTL1);
+		writel(hifi_pll->pll_cntl2, HHI_HIFI_PLL_CNTL2);
+		writel(hifi_pll->pll_cntl3, HHI_HIFI_PLL_CNTL3);
+		writel(hifi_pll->pll_cntl4, HHI_HIFI_PLL_CNTL4);
+		writel(hifi_pll->pll_cntl5, HHI_HIFI_PLL_CNTL5);
+		writel(hifi_pll->pll_cntl6, HHI_HIFI_PLL_CNTL6);
+		writel(readl(HHI_HIFI_PLL_CNTL0)|(1<<29), HHI_HIFI_PLL_CNTL0);
+		_udelay(10);
+		writel(readl(HHI_HIFI_PLL_CNTL0)&(~(1<<29)), HHI_HIFI_PLL_CNTL0);
+		_udelay(100);
+		//printf("hifi lock_check: %4d\n", lock_check);
+	} while ((!((readl(HHI_HIFI_PLL_CNTL0)>>31)&0x1)) && --lock_check);
+	if (0 == lock_check) {
+		printf("HIFI pll lock Failed! - %4d MHz\n", hifi_pll->pll_clk);
+		ret = RET_PLL_LOCK_FAIL;
+	} else {
+		printf("HIFI pll lock OK! - %4d MHz. ", hifi_pll->pll_clk);
+		/* get hifi_pll_clk */
+		clk_msr_val = clk_util_clk_msr(12);
+		printf("CLKMSR(12) - %4d MHz ", clk_msr_val);
+		if (clk_around(clk_msr_val, hifi_pll->pll_clk)) {
+			printf(": Match\n");
+		} else {
+			printf(": MisMatch\n");
+			ret = RET_CLK_NOT_MATCH;
+		}
+	}
+	return ret;
+}
+
+static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg) {
+	unsigned int i=0;
+	int ret=0;
+
+	for (i=0; i<(sizeof(hifi_pll_clk)/sizeof(uint32_t)); i++)
+		ret += hifi_pll_test(&(hifi_pll_cfg->hifi_pll[i]));
+	return ret;
+}
+
+static int pcie_pll_test(pcie_pll_set_t * pcie_pll) {
+	int ret=0;
+	unsigned int i=0, pll_clk=0;
+	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+	unsigned int clk_msr_val = 0;
+
+	for (i=0; i<(sizeof(pcie_pll_rate_table)/sizeof(pcie_pll_rate_table[0])); i++) {
+		if ((pcie_pll->pll_cntl0 & 0xFF) == pcie_pll_rate_table[i].m)
+			pll_clk = pcie_pll_rate_table[i].rate;
+	}
+
+	writel(pcie_pll->pll_cntl0, HHI_PCIE_PLL_CNTL0);
+	writel(pcie_pll->pll_cntl0 | 0x30000000, HHI_PCIE_PLL_CNTL0);
+	writel(pcie_pll->pll_cntl1, HHI_PCIE_PLL_CNTL1);
+	writel(pcie_pll->pll_cntl2, HHI_PCIE_PLL_CNTL2);
+	writel(pcie_pll->pll_cntl3, HHI_PCIE_PLL_CNTL3);
+	writel(pcie_pll->pll_cntl4, HHI_PCIE_PLL_CNTL4);
+	writel(pcie_pll->pll_cntl5, HHI_PCIE_PLL_CNTL5);
+	writel(pcie_pll->pll_cntl5 | 0x68, HHI_PCIE_PLL_CNTL5);
+	_udelay(20);
+	writel(pcie_pll->pll_cntl4 | 0x00800000, HHI_PCIE_PLL_CNTL4);
+	_udelay(10);
+	writel(pcie_pll->pll_cntl0 | 0x34000000, HHI_PCIE_PLL_CNTL0);
+	writel(((pcie_pll->pll_cntl0 & (~(1<<29)))|(1<<26))|(1<<28), HHI_PCIE_PLL_CNTL0);
+	_udelay(10);
+	writel(pcie_pll->pll_cntl2 & (~(1<<8)), HHI_PCIE_PLL_CNTL2);
+
+	lock_check = PLL_LOCK_CHECK_MAX;
+	do {
+		update_bits(HHI_PCIE_PLL_CNTL0, 1<<29, 1 << 29);
+		_udelay(10);
+		update_bits(HHI_PCIE_PLL_CNTL0, 1<<29, 0);
+		_udelay(100);
+		//printf("pcie lock_check: %4d\n", lock_check);
+	} while ((!((readl(HHI_PCIE_PLL_CNTL0)>>31)&0x1)) && --lock_check);
+	if (0 == lock_check) {
+		printf("PCIE pll lock Failed! - %4d MHz\n", pll_clk);
+		ret = RET_PLL_LOCK_FAIL;
+	} else {
+		printf("PCIE pll lock OK! - %4d MHz. ", pll_clk);
+		/* get pcie_pll_clk */
+		clk_msr_val = clk_util_clk_msr(29);
+		printf("CLKMSR(29) - %4d MHz ", clk_msr_val);
+		if (clk_around(clk_msr_val, pll_clk)) {
+			printf(": Match\n");
+		} else {
 			printf(": MisMatch\n");
 			ret = RET_CLK_NOT_MATCH;
 		}
@@ -593,53 +689,48 @@ static int gp0_pll_test(gp0_pll_set_t * gp0_pll) {
 	return ret;
 }
 
-static int gp0_pll_test_all(void) {
+static int pcie_pll_test_all(void) {
 	unsigned int i=0;
 	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
 	unsigned int clk_msr_val = 0;
 	int ret=0;
 
-	for (i=0; i<(sizeof(gpll0_tbl)/sizeof(gpll0_tbl[0])); i++) {
-		writel(0x380404e9, HHI_GP0_PLL_CNTL0);
-		writel(0x00000000, HHI_GP0_PLL_CNTL1);
-		writel(0x00000000, HHI_GP0_PLL_CNTL2);
-		writel(0x48681c00, HHI_GP0_PLL_CNTL3);
-		writel(0x33771290, HHI_GP0_PLL_CNTL4);
-		writel(0x39272000, HHI_GP0_PLL_CNTL5);
-		writel(0x56540000, HHI_GP0_PLL_CNTL6);
-		update_bits(HHI_GP0_PLL_CNTL0, (0x1ff << 0), (gpll0_tbl[i].m)<<0);
-		update_bits(HHI_GP0_PLL_CNTL0, (0x1f << 10), (gpll0_tbl[i].n)<<10);
-		update_bits(HHI_GP0_PLL_CNTL0, (0x3 << 16), (gpll0_tbl[i].od)<<16);
-/* dump paras */
-#if 0
-		printf("gp0 %d:\n", gpll0_tbl[i].rate);
-		printf("HHI_GP0_PLL_CNTL0: 0x%8x\n", readl(HHI_GP0_PLL_CNTL0));
-		//printf("HHI_GP0_PLL_CNTL2: 0x%8x\n", readl(HHI_GP0_PLL_CNTL2));
-		//printf("HHI_GP0_PLL_CNTL3: 0x%8x\n", readl(HHI_GP0_PLL_CNTL3));
-		//printf("HHI_GP0_PLL_CNTL4: 0x%8x\n", readl(HHI_GP0_PLL_CNTL4));
-		//printf("HHI_GP0_PLL_CNTL5: 0x%8x\n", readl(HHI_GP0_PLL_CNTL5));
-#endif
+	for (i=0; i<(sizeof(pcie_pll_rate_table)/sizeof(pcie_pll_rate_table[0])); i++) {
+		writel(0x28060464, HHI_PCIE_PLL_CNTL0);
+		writel(0x38060464, HHI_PCIE_PLL_CNTL0);
+		writel(0x00000000, HHI_PCIE_PLL_CNTL1);
+		writel(0x00001100, HHI_PCIE_PLL_CNTL2);
+		writel(0x10058e00, HHI_PCIE_PLL_CNTL3);
+		writel(0x000100c0, HHI_PCIE_PLL_CNTL4);
+		writel(0x68000048, HHI_PCIE_PLL_CNTL5);
+		writel(0x68000068, HHI_PCIE_PLL_CNTL5);
+		_udelay(20);
+		writel(0x008100c0, HHI_PCIE_PLL_CNTL4);
+		_udelay(10);
+		writel(0x3c060464, HHI_PCIE_PLL_CNTL0);
+		writel(0x1c060464, HHI_PCIE_PLL_CNTL0);
+		_udelay(10);
+		writel(0x00001000, HHI_PCIE_PLL_CNTL2);
+
 		lock_check = PLL_LOCK_CHECK_MAX;
 		do {
-			update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 1 << 29);
+			update_bits(HHI_PCIE_PLL_CNTL0, 1<<29, 1 << 29);
 			_udelay(10);
-			update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 0);
+			update_bits(HHI_PCIE_PLL_CNTL0, 1<<29, 0);
 			_udelay(100);
-			//printf("gp0 lock_check: %4d\n", lock_check);
-		} while ((!((readl(HHI_GP0_PLL_CNTL0)>>31)&0x1)) && --lock_check);
+			//printf("pcie lock_check: %4d\n", lock_check);
+		} while ((!((readl(HHI_PCIE_PLL_CNTL0)>>31)&0x1)) && --lock_check);
 		if (0 == lock_check) {
-			printf("GP0 pll lock Failed! - %4d MHz\n", gpll0_tbl[i].rate);
+			printf("pcie pll lock Failed! - %4d MHz\n", pcie_pll_rate_table[i].rate);
 			ret += RET_PLL_LOCK_FAIL;
-		}
-		else {
-			printf("GP0 pll lock OK! - %4d MHz. ", gpll0_tbl[i].rate);
-			/* get gp0_pll_clk */
-			clk_msr_val = clk_util_clk_msr(4) << (5-gpll0_tbl[i].od);
-			printf("CLKMSR(4) - %4d MHz ", clk_msr_val);
-			if (clk_around(clk_msr_val, gpll0_tbl[i].rate)) {
+		} else {
+			printf("pcie pll lock OK! - %4d MHz. ", pcie_pll_rate_table[i].rate);
+			/* get pcie_pll_clk */
+			clk_msr_val = clk_util_clk_msr(29);
+			printf("CLKMSR(29) - %4d MHz ", clk_msr_val);
+			if (clk_around(clk_msr_val, pcie_pll_rate_table[i].rate)) {
 				printf(": Match\n");
-			}
-			else {
+			} else {
 				printf(": MisMatch\n");
 				ret += RET_CLK_NOT_MATCH;
 			}
@@ -647,8 +738,174 @@ static int gp0_pll_test_all(void) {
 	}
 
 	return ret;
+
+}
+
+static int ethphy_pll_test(ethphy_pll_set_t * ethphy_pll) {
+	int ret=0;
+	unsigned int pll_clk=0;
+	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+	unsigned int clk_msr_val = 0;
+
+	if ((ethphy_pll->pll_cntl0 & 0x1FF) == 0xA) {
+		pll_clk = 500;
+	} else {
+		printf("input frequency point is not support\n");
+		return -1;
+	}
+
+	do {
+		writel(ethphy_pll->pll_cntl0 | 0x30000000, ETH_PLL_CTL0);
+		writel(ethphy_pll->pll_cntl1, ETH_PLL_CTL1);
+		writel(ethphy_pll->pll_cntl2, ETH_PLL_CTL2);
+		writel(ethphy_pll->pll_cntl3, ETH_PLL_CTL3);
+		_udelay(150);
+		writel(ethphy_pll->pll_cntl0 | 0x10000000, ETH_PLL_CTL0);
+		_udelay(150);
+	} while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check);
+
+	if (0 == lock_check) {
+		printf("ETHPHY pll lock Failed! - %4d MHz\n", pll_clk);
+		ret = RET_PLL_LOCK_FAIL;
+	} else {
+		printf("ETHPHY pll lock OK! - %4d MHz. ", pll_clk);
+		/* get ethphy_pll_clk */
+		clk_msr_val = clk_util_clk_msr(95)<<2;
+		printf("CLKMSR(95) - %4d MHz ", clk_msr_val);
+		if (clk_around(clk_msr_val, pll_clk)) {
+			printf(": Match\n");
+		} else {
+			printf(": MisMatch\n");
+			ret = RET_CLK_NOT_MATCH;
+		}
+	}
+	return ret;
+}
+
+
+static int ethphy_pll_test_all(void) {
+	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+	unsigned int clk_msr_val = 0;
+	int ret=0;
+
+	do {
+		writel(0x9c0040a | 0x30000000, ETH_PLL_CTL0);
+		writel(0x927e0000, ETH_PLL_CTL1);
+		writel(0xac5f49e5, ETH_PLL_CTL2);
+		writel(0x00000000, ETH_PLL_CTL3);
+		_udelay(150);
+		writel(0x9c0040a | 0x10000000, ETH_PLL_CTL0);
+		_udelay(150);
+		} while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check);
+
+	if (0 == lock_check) {
+		printf("ethphy pll lock Failed! - 500MHz\n");
+		ret += RET_PLL_LOCK_FAIL;
+	} else {
+		printf("ethphy pll lock OK! - 500MHz. ");
+		/* get ethphy_pll_clk */
+		clk_msr_val = clk_util_clk_msr(95)<<2;
+		printf("CLKMSR(95) - %4d MHz ", clk_msr_val);
+		if (clk_around(clk_msr_val, 500)) {
+			printf(": Match\n");
+		} else {
+			printf(": MisMatch\n");
+			ret += RET_CLK_NOT_MATCH;
+		}
+	}
+
+	return ret;
 }
 
+
+static int usbphy_pll_test(usbphy_pll_set_t * usbphy_pll) {
+	int ret=0;
+	unsigned int i=0, pll_clk=0;
+	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+
+	if ((usbphy_pll->pll_cntl4 & 0x1FF) == 0x14) {
+		pll_clk = 480;
+	}
+	else
+	{
+		printf("input frequency point is not support\n");
+		return -1;
+	}
+	for (i=0; i<(sizeof(usbphy_base_cfg)/sizeof(usbphy_base_cfg[0])); i++) {
+		/* TO DO set usb  PLL */
+		writel(usbphy_pll->pll_cntl4, (usbphy_base_cfg[i] + 0x40));
+		writel(usbphy_pll->pll_cntl5, (usbphy_base_cfg[i] + 0x44));
+		writel(usbphy_pll->pll_cntl6, (usbphy_base_cfg[i] + 0x48));
+		/* PHY Tune */
+		writel(usbphy_pll->pll_cntl7, (usbphy_base_cfg[i] + 0x50));
+		writel(usbphy_pll->pll_cntl0, (usbphy_base_cfg[i] + 0x10));
+		/* Recovery analog status */
+		writel(usbphy_pll->pll_cntl3, (usbphy_base_cfg[i] + 0x38));
+		writel(usbphy_pll->pll_cntl2, (usbphy_base_cfg[i] + 0x34));
+
+		writel(usbphy_pll->pll_cntl1, (usbphy_base_cfg[i] + 0xC));
+
+		lock_check = PLL_LOCK_CHECK_MAX;
+		do {
+			update_bits((usbphy_base_cfg[i] + 0x40), 1<<29, 1 << 29);
+			_udelay(10);
+			update_bits((usbphy_base_cfg[i] + 0x40), 1<<29, 0);
+			_udelay(100);
+			//printf("ethphy lock_check: %4d\n", lock_check);
+		} while ((!((readl(usbphy_base_cfg[i] + 0x40)>>31)&0x1)) && --lock_check);
+		if (0 == lock_check) {
+			printf("usbphy%d pll lock Failed! - %4d MHz\n", i+20, pll_clk);
+			ret = RET_PLL_LOCK_FAIL;
+		}
+		else{
+			printf("usbphy%d pll lock OK! - %4d MHz.\n", i+20,pll_clk);
+		}
+
+	}
+	return ret;
+}
+
+
+static int usbphy_pll_test_all(void) {
+	unsigned int i=0;
+	unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+	int ret=0;
+
+	for (i=0; i<(sizeof(usbphy_base_cfg)/sizeof(usbphy_base_cfg[0])); i++) {
+		/* TO DO set usb  PLL */
+		writel(0x09400414, (usbphy_base_cfg[i] + 0x40));
+		writel(0x927E0000, (usbphy_base_cfg[i] + 0x44));
+		writel(0xac5f69e5, (usbphy_base_cfg[i] + 0x48));
+		/* PHY Tune */
+		writel(0xfe18, (usbphy_base_cfg[i] + 0x50));
+		writel(0x8000fff, (usbphy_base_cfg[i] + 0x10));
+		/* Recovery analog status */
+		writel(0, (usbphy_base_cfg[i] + 0x38));
+		writel(0x78000, (usbphy_base_cfg[i] + 0x34));
+
+		writel(0x34, (usbphy_base_cfg[i] + 0xC));
+
+		do {
+			update_bits((usbphy_base_cfg[i] + 0x40), 1<<29, 1 << 29);
+			_udelay(10);
+			update_bits((usbphy_base_cfg[i] + 0x40), 1<<29, 0);
+			_udelay(100);
+			//printf("ethphy lock_check: %4d\n", lock_check);
+		} while ((!((readl(usbphy_base_cfg[i] + 0x40)>>31)&0x1)) && --lock_check);
+
+		if (0 == lock_check) {
+			printf("usbphy%d pll lock Failed! - 480MHz\n", i+20);
+			ret += RET_PLL_LOCK_FAIL;
+		} else {
+			printf("usbphy%d pll lock OK! - 480MHz.\n", i+20);
+		}
+	}
+
+	return ret;
+
+}
+
+
 static int pll_test_all(unsigned char * pll_list) {
 	int ret = 0;
 	unsigned char i=0;
@@ -671,9 +928,25 @@ static int pll_test_all(unsigned char * pll_list) {
 				pll_report(ret, STR_PLL_TEST_HDMI);
 				break;
 			case PLL_GP0:
-				ret = gp0_pll_test_all();
+				ret = gp0_pll_test_all(&gp0_pll_cfg);
 				pll_report(ret, STR_PLL_TEST_GP0);
 				break;
+			case PLL_HIFI:
+				ret = hifi_pll_test_all(&hifi_pll_cfg);
+				pll_report(ret, STR_PLL_TEST_HIFI);
+				break;
+			case PLL_PCIE:
+				ret = pcie_pll_test_all();
+				pll_report(ret, STR_PLL_TEST_PCIE);
+				break;
+			case PLL_ETHPHY:
+				ret = ethphy_pll_test_all();
+				pll_report(ret, STR_PLL_TEST_ETHPHY);
+				break;
+			case PLL_USBPHY:
+				ret = usbphy_pll_test_all();
+				pll_report(ret, STR_PLL_TEST_USBPHY);
+				break;
 			default:
 				break;
 		}
@@ -684,10 +957,13 @@ static int pll_test_all(unsigned char * pll_list) {
 int pll_test(int argc, char * const argv[])
 {
 	int ret = 0;
-
 	sys_pll_set_t sys_pll_set = {0};
 	hdmi_pll_set_t hdmi_pll_set = {0};
 	gp0_pll_set_t gp0_pll_set = {0};
+	hifi_pll_set_t hifi_pll_set = {0};
+	pcie_pll_set_t pcie_pll_set = {0};
+	ethphy_pll_set_t ethphy_pll_set = {0};
+	usbphy_pll_set_t usbphy_pll_set = {0};
 
 	unsigned char plls[PLL_ENUM] = {
 		PLL_SYS,
@@ -695,6 +971,10 @@ int pll_test(int argc, char * const argv[])
 		0xff,//	PLL_DDR,
 		PLL_HDMI,
 		PLL_GP0,
+		PLL_HIFI,
+		PLL_PCIE,
+		0xff,
+		PLL_USBPHY
 	};
 
 	if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) {
@@ -717,6 +997,7 @@ int pll_test(int argc, char * const argv[])
 			sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
 			sys_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
 			sys_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+			sys_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, 16);
 			ret = sys_pll_test(&sys_pll_set);
 			pll_report(ret, STR_PLL_TEST_SYS);
 		}
@@ -744,7 +1025,7 @@ int pll_test(int argc, char * const argv[])
 	}
 	else if (0 == strcmp(STR_PLL_TEST_GP0, argv[1])) {
 		if (argc == 2) {
-			ret = gp0_pll_test_all();
+			ret = gp0_pll_test_all(&gp0_pll_cfg);
 			pll_report(ret, STR_PLL_TEST_GP0);
 		}
 		else if (argc != 9){
@@ -763,6 +1044,87 @@ int pll_test(int argc, char * const argv[])
 			pll_report(ret, STR_PLL_TEST_GP0);
 		}
 	}
+	else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) {
+		if (argc == 2) {
+			ret = hifi_pll_test_all(&hifi_pll_cfg);
+			pll_report(ret, STR_PLL_TEST_HIFI);
+		}
+		else if (argc != 9){
+			printf("%s pll test: args error\n", STR_PLL_TEST_HIFI);
+			return -1;
+		}
+		else {
+			hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+			hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+			hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+			hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+			hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+			hifi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+			hifi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, 16);
+			ret = hifi_pll_test(&hifi_pll_set);
+			pll_report(ret, STR_PLL_TEST_HIFI);
+		}
+	}
+	else if (0 == strcmp(STR_PLL_TEST_PCIE, argv[1])) {
+		if (argc == 2) {
+			ret = pcie_pll_test_all();
+			pll_report(ret, STR_PLL_TEST_PCIE);
+		}
+		else if (argc != 8){
+			printf("%s pll test: args error\n", STR_PLL_TEST_PCIE);
+			return -1;
+		}
+		else {
+			pcie_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+			pcie_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+			pcie_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+			pcie_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+			pcie_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+			pcie_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+			ret = pcie_pll_test(&pcie_pll_set);
+			pll_report(ret, STR_PLL_TEST_PCIE);
+		}
+	}
+	else if (0 == strcmp(STR_PLL_TEST_ETHPHY, argv[1])) {
+		if (argc == 2) {
+			ret = ethphy_pll_test_all();
+			pll_report(ret, STR_PLL_TEST_ETHPHY);
+		}
+		else if (argc != 6){
+			printf("%s pll test: args error\n", STR_PLL_TEST_ETHPHY);
+			return -1;
+		}
+		else {
+			ethphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+			ethphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+			ethphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+			ethphy_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+			ret = ethphy_pll_test(&ethphy_pll_set);
+			pll_report(ret, STR_PLL_TEST_ETHPHY);
+		}
+	}
+	else if (0 == strcmp(STR_PLL_TEST_USBPHY, argv[1])) {
+		if (argc == 2) {
+			ret = usbphy_pll_test_all();
+			pll_report(ret, STR_PLL_TEST_USBPHY);
+		}
+		else if (argc != 10){
+			printf("%s pll test: args error\n", STR_PLL_TEST_USBPHY);
+			return -1;
+		}
+		else {
+			usbphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+			usbphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+			usbphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+			usbphy_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+			usbphy_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+			usbphy_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+			usbphy_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, 16);
+			usbphy_pll_set.pll_cntl7 = simple_strtoul(argv[9], NULL, 16);
+			ret = usbphy_pll_test(&usbphy_pll_set);
+			pll_report(ret, STR_PLL_TEST_USBPHY);
+		}
+	}
 	else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) {
 		printf("%s pll not support now\n", STR_PLL_TEST_DDR);
 		return -1;
@@ -772,23 +1134,5 @@ int pll_test(int argc, char * const argv[])
 		return -1;
 	}
 
-#if 0
-	unsigned char * pll_list = NULL;
-	switch (get_cpu_id().family_id) {
-		case MESON_CPU_MAJOR_ID_GXTVBB:
-			pll_list = gxtvbb_plls;
-			break;
-		case MESON_CPU_MAJOR_ID_GXL:
-			pll_list = gxl_plls;
-			break;
-		default:
-			printf("un-support chip\n");
-			break;
-	}
-	if (pll_list) {
-		return plltest(pll_list);
-	}
-#endif
-
 	return 0;
 }
diff --git a/arch/arm/cpu/armv8/g12a/power_domain.c b/arch/arm/cpu/armv8/g12a/power_domain.c
new file mode 100644
index 0000000..5bbb95f
--- a/dev/null
+++ b/arch/arm/cpu/armv8/g12a/power_domain.c
@@ -0,0 +1,326 @@
+/*
+ * drivers/amlogic/power/power_domain.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/power_domain.h>
+
+static void power_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+
+	value = readl(AO_RTI_GEN_PWR_SLEEP0);
+	if (pwr_switch == PWR_ON)
+		value &= ~(1 << pwr_domain);
+	else
+		value |= (1 << pwr_domain);
+	writel(value, (AO_RTI_GEN_PWR_SLEEP0));
+}
+
+static void mem_pd_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+
+	if (pwr_switch == PWR_ON) {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			writel(0x0, P_DOS_MEM_PD_HCODEC);
+			break;
+		case PM_DOS_VDEC:
+			writel(0x0, P_DOS_MEM_PD_VDEC);
+			break;
+		case PM_DOS_HEVC:
+			writel(0x0, P_DOS_MEM_PD_HEVC);
+			break;
+		case PM_WAVE420L:
+			writel(0x0, (P_DOS_MEM_PD_WAVE420L));
+			break;
+		case PM_CSI:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0x3 << 6);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_VPU:
+			writel(0x0, HHI_VPU_MEM_PD_REG0);
+			writel(0x0, HHI_VPU_MEM_PD_REG1);
+			writel(0x0, HHI_VPU_MEM_PD_REG2);
+			writel(0x0, HHI_VPU_MEM_PD_REG3);
+			writel(0x0, HHI_VPU_MEM_PD_REG4);
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xff << 8);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_NN:
+			writel(0x0, HHI_NANOQ_MEM_PD_REG0);
+			writel(0x0, HHI_NANOQ_MEM_PD_REG1);
+			break;
+		case PM_USB:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0x3 << 30);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_PCIE0:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xf<<26);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_GE2D:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xff<<18);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		}
+	} else {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			writel(0xffffffff, P_DOS_MEM_PD_HCODEC);
+			break;
+		case PM_DOS_VDEC:
+			writel(0xffffffff, P_DOS_MEM_PD_VDEC);
+			break;
+		case PM_DOS_HEVC:
+			writel(0xffffffff, P_DOS_MEM_PD_HEVC);
+			break;
+		case PM_WAVE420L:
+			writel(0xffffffff, P_DOS_MEM_PD_WAVE420L);
+			break;
+		case PM_CSI:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0x3 << 6);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_VPU:
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG0);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG1);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG2);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG3);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG4);
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xff << 8);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_NN:
+			writel(0xffffffff, HHI_NANOQ_MEM_PD_REG0);
+			writel(0xffffffff, HHI_NANOQ_MEM_PD_REG1);
+			break;
+		case PM_USB:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0x3 << 30);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_PCIE0:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xf<<26);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_GE2D:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xff<<18);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		}
+	}
+}
+
+static void reset_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+	unsigned int tmp;
+
+	if (pwr_switch == PWR_ON) {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			value = readl(P_DOS_SW_RESET1);
+			value &= ~(0xffff<<2);
+			writel(value, P_DOS_SW_RESET1);
+			break;
+		case PM_DOS_VDEC:
+			value = readl(P_DOS_SW_RESET0);
+			value &= ~(0x1fff<<2);
+			writel(value, P_DOS_SW_RESET0);
+			break;
+		case PM_DOS_HEVC:
+			value = readl(P_DOS_SW_RESET3);
+			value &= ~(0x3ffff<<2 | 1<<24);
+			writel(value, P_DOS_SW_RESET3);
+			break;
+		case PM_WAVE420L:
+			value = readl(P_DOS_SW_RESET4);
+			value &= ~(0xf<<8);
+			writel(value, P_DOS_SW_RESET4);
+			break;
+		case PM_VPU:
+			tmp = 0x1 << 5 | 0x1 << 10 | 0x1 << 19 | 0x1 << 13;
+			value = readl(P_RESET0_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET0_LEVEL);
+			tmp = 0x1 << 5 | 0x1 << 4;
+			value = readl(P_RESET1_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET1_LEVEL);
+			tmp = 0x1 << 15;
+			value = readl(P_RESET2_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET2_LEVEL);
+			tmp = 0x1 << 6 | 0x1 << 7 | 0x1 << 13 |
+			      0x1 << 5 | 0x1 << 9 | 0x1 << 4 | 0x1 << 12;
+			value = readl(P_RESET4_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET4_LEVEL);
+			tmp = 0x1 << 7;
+			value = readl(P_RESET7_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET7_LEVEL);
+			break;
+		case PM_NN:
+			value = readl(P_RESET2_LEVEL);
+			value |= (0x1<<12);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		case PM_USB:
+			value = readl(P_RESET1_LEVEL);
+			value |= (0x1<<2);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_PCIE0:
+			value = readl(P_RESET0_LEVEL);
+			value |= ((0x1<<12)|(0x3<<14));
+			writel(value, P_RESET0_LEVEL);
+			break;
+		case PM_GE2D:
+			value = readl(P_RESET2_LEVEL);
+			value |= (0x1<<6);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		}
+	} else {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			value = readl(P_DOS_SW_RESET1);
+			value |= (0xffff<<2);
+			writel(value, P_DOS_SW_RESET1);
+			break;
+		case PM_DOS_VDEC:
+			value = readl(P_DOS_SW_RESET0);
+			value |= (0x1fff<<2);
+			writel(value, P_DOS_SW_RESET0);
+			break;
+		case PM_DOS_HEVC:
+			value = readl(P_DOS_SW_RESET3);
+			value |= (0x3ffff<<2 | 1<<24);
+			writel(value, P_DOS_SW_RESET3);
+			break;
+		case PM_WAVE420L:
+			value = readl(P_DOS_SW_RESET4);
+			value |= (0xf<<8);
+			writel(value, P_DOS_SW_RESET4);
+			break;
+		case PM_VPU:
+			tmp = 0x1 << 5 | 0x1 << 10 | 0x1 << 19 | 0x1 << 13;
+			value = readl(P_RESET0_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET0_LEVEL);
+			tmp = 0x1 << 5 | 0x1 << 4;
+			value = readl(P_RESET1_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET1_LEVEL);
+			tmp = 0x1 << 15;
+			value = readl(P_RESET2_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET2_LEVEL);
+			tmp = 0x1 << 6 | 0x1 << 7 | 0x1 << 13 |
+			      0x1 << 5 | 0x1 << 9 | 0x1 << 4 | 0x1 << 12;
+			value = readl(P_RESET4_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET4_LEVEL);
+			tmp = 0x1 << 7;
+			value = readl(P_RESET7_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET7_LEVEL);
+			break;
+		case PM_NN:
+			value = readl(P_RESET2_LEVEL);
+			value &= ~(0x1<<12);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		case PM_USB:
+			value = readl(P_RESET1_LEVEL);
+			value &= ~(0x1<<2);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_PCIE0:
+			value = readl(P_RESET0_LEVEL);
+			value &= ~((0x1<<12)|(0x3<<14));
+			writel(value, P_RESET0_LEVEL);
+			break;
+		case PM_GE2D:
+			value = readl(P_RESET2_LEVEL);
+			value &= ~(0x1<<6);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		}
+	}
+}
+
+static void iso_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+
+	value = readl(AO_RTI_GEN_PWR_ISO0);
+	if (pwr_switch == PWR_ON)
+		value &= ~(1 << pwr_domain);
+	else
+		value |= (1 << pwr_domain);
+	writel(value, AO_RTI_GEN_PWR_ISO0);
+}
+
+void power_domain_switch(int pwr_domain, bool pwr_switch)
+{
+	if (pwr_switch == PWR_ON) {
+		/* Powerup Power Domain */
+		power_switch(pwr_domain, PWR_ON);
+		udelay(50);
+
+		/* Powerup memories */
+		mem_pd_switch(pwr_domain, PWR_ON);
+		udelay(150);
+
+		reset_switch(pwr_domain, PWR_OFF);
+
+		/* remove isolations */
+		iso_switch(pwr_domain, PWR_ON);
+
+		/* deassert reset */
+		reset_switch(pwr_domain, PWR_ON);
+
+	} else {
+		/* reset */
+		reset_switch(pwr_domain, PWR_OFF);
+
+		/* add isolation to domain */
+		iso_switch(pwr_domain, PWR_OFF);
+
+		/* Power down memories */
+		mem_pd_switch(pwr_domain, PWR_OFF);
+		udelay(50);
+
+		/* Power off  domain */
+		power_switch(pwr_domain, PWR_OFF);
+	}
+}
diff --git a/arch/arm/cpu/armv8/g12a/usb.c b/arch/arm/cpu/armv8/g12a/usb.c
index dec804a..2eb99cf 100644
--- a/arch/arm/cpu/armv8/g12a/usb.c
+++ b/arch/arm/cpu/armv8/g12a/usb.c
@@ -22,7 +22,7 @@
 #include <asm/arch/usb-v2.h>
 #include <asm/arch/romboot.h>
 #include <asm/cpu_id.h>
-
+#include <amlogic/power_domain.h>
 
 static struct amlogic_usb_config * g_usb_cfg[BOARD_USB_MODE_MAX][USB_PHY_PORT_MAX];
 static int Rev_flag = 0;
@@ -50,14 +50,8 @@ struct amlogic_usb_config * board_usb_start(int mode,int index)
 	printf("USB3.0 XHCI init start\n");
 	board_usb_check_sm1();
 
-	if (board_usb_get_sm1_type() == 1) {
-		writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_SLEEP0);
-		writel((readl(HHI_MEM_PD_REG0) & (~(0x3<<30))), HHI_MEM_PD_REG0);
-		udelay(100);
-		writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_ISO0);
-	}
+	if (board_usb_get_sm1_type() == 1)
+		power_domain_switch(PM_USB, PWR_ON);
 
 	if (mode < 0 || mode >= BOARD_USB_MODE_MAX||!g_usb_cfg[mode][index])
 		return 0;
diff --git a/arch/arm/cpu/armv8/g12b/firmware/acs/acs.mk b/arch/arm/cpu/armv8/g12b/firmware/acs/acs.mk
index 99b4cf5..96f76a3 100644
--- a/arch/arm/cpu/armv8/g12b/firmware/acs/acs.mk
+++ b/arch/arm/cpu/armv8/g12b/firmware/acs/acs.mk
@@ -1,8 +1,9 @@
-SOURCES		+=	acs.c						\
-				acs_entry.S
+SOURCES		+=	acs_entry.S
 
 ifdef CONFIG_MDUMP_COMPRESS
 SOURCES 	+=	ramdump.c
 endif
 
+SOURCES		+=	acs.c
+
 LINKERFILE_T		:=	acs.ld.S
diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
index 388096c..abb653f 100644
--- a/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
+++ b/arch/arm/cpu/armv8/g12b/hdmitx20/enc_clk_config.c
@@ -891,6 +891,7 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
 	enum hdmi_vic vic = hdev->vic;
 	enum hdmi_color_format cs = hdev->para->cs;
 	enum hdmi_color_depth cd = hdev->para->cd;
+	char *sspll_dis = NULL;
 
 	/* YUV 422 always use 24B mode */
 	if (cs == HDMI_COLOR_FORMAT_422)
@@ -949,7 +950,9 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
 next:
 	set_hdmitx_sys_clk();
 	set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev);
-	if (!getenv("sspll_dis"))
+	sspll_dis = getenv("sspll_dis");
+	if ((!sspll_dis || !strcmp(sspll_dis, "0")) &&
+		(cd == HDMI_COLOR_DEPTH_24B))
 		set_hpll_sspll(hdev);
 	set_hpll_od1(p_enc[j].od1);
 	set_hpll_od2(p_enc[j].od2);
diff --git a/arch/arm/cpu/armv8/tl1/firmware/acs/acs.mk b/arch/arm/cpu/armv8/tl1/firmware/acs/acs.mk
index 2294d53..883a9df 100644
--- a/arch/arm/cpu/armv8/tl1/firmware/acs/acs.mk
+++ b/arch/arm/cpu/armv8/tl1/firmware/acs/acs.mk
@@ -1,8 +1,9 @@
-SOURCES		+=	acs.c				\
-			acs_entry.S
+SOURCES		+=	acs_entry.S
 
 ifdef CONFIG_MDUMP_COMPRESS
 SOURCES		+=	ramdump.c
 endif
 
+SOURCES		+=	acs.c
+
 LINKERFILE_T		:=	acs.ld.S
diff --git a/arch/arm/cpu/armv8/tl1/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/cpu/armv8/tl1/firmware/scp_task/hdmi_cec_arc.c
index 502c08f..6955231 100644
--- a/arch/arm/cpu/armv8/tl1/firmware/scp_task/hdmi_cec_arc.c
+++ b/arch/arm/cpu/armv8/tl1/firmware/scp_task/hdmi_cec_arc.c
@@ -38,6 +38,7 @@ Description:
 cec_msg_t cec_msg;
 unsigned char hdmi_cec_func_config;
 cec_wakeup_t cec_wakup;
+static unsigned int cec_wait_addr;
 
 #ifdef CEC_DBG_PRINT
 static void cec_dbg_print(char *s, int v)
@@ -874,6 +875,7 @@ void cec_node_init(void)
 		 {CEC_PLAYBACK_DEVICE_2_ADDR, CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR},
 		 {CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR, CEC_PLAYBACK_DEVICE_2_ADDR}};
 
+	cec_wait_addr = 0;
 	if (retry >= 12) {  // retry all device addr
 		cec_msg.log_addr = 0x0f;
 		uart_puts("failed on retried all possible address\n");
@@ -974,7 +976,6 @@ void cec_node_init(void)
 
 int cec_suspend_wakeup_chk(void)
 {
-	static unsigned int cec_wait_addr = 0;
 	int exit_reason = 0;
 
 	if ((cec_msg.cec_power == 0x1) &&
diff --git a/arch/arm/cpu/armv8/tl1/usb.c b/arch/arm/cpu/armv8/tl1/usb.c
index e855a48..0111a8c 100644
--- a/arch/arm/cpu/armv8/tl1/usb.c
+++ b/arch/arm/cpu/armv8/tl1/usb.c
@@ -22,6 +22,12 @@
 #include <asm/arch/usb-v2.h>
 #include <asm/arch/romboot.h>
 
+#define USB2_PHY_PLL_OFFSET_10	(0x80000fff)
+#define USB2_PHY_PLL_OFFSET_34	(0x78000)
+#define USB2_PHY_PLL_OFFSET_38_CLEAR	(0)
+#define USB2_PHY_PLL_OFFSET_38_SET	    (0xe000c)
+#define USB2_PHY_PLL_OFFSET_50	(0xfe18)
+#define USB2_PHY_PLL_OFFSET_c	(0x3C)
 
 static struct amlogic_usb_config * g_usb_cfg[BOARD_USB_MODE_MAX][USB_PHY_PORT_MAX];
 
@@ -71,7 +77,7 @@ int get_usb_count(void)
 
 void set_usb_pll(uint32_t volatile *phy2_pll_base)
 {
-    (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+	(*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
         = (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE);
     (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
         USB_PHY2_PLL_PARAMETER_2;
@@ -81,6 +87,17 @@ void set_usb_pll(uint32_t volatile *phy2_pll_base)
     (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
         = (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE))
         & (~(USB_PHY2_RESET)));
+    (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+        = USB2_PHY_PLL_OFFSET_50;
+    (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+        = USB2_PHY_PLL_OFFSET_10;
+    (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38))
+        = USB2_PHY_PLL_OFFSET_38_CLEAR;
+    (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+        = USB2_PHY_PLL_OFFSET_34;
+
+    (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0xC))
+        = USB2_PHY_PLL_OFFSET_c;
 }
 
 void board_usb_pll_disable(struct amlogic_usb_config *cfg)
@@ -118,10 +135,10 @@ void set_usb_phy_tuning_1(int port)
 	else
 		phy_reg_base = USB_REG_B;
 
-	(*(volatile uint32_t *)(phy_reg_base + 0x10)) = 0xfff;
-	(*(volatile uint32_t *)(phy_reg_base + 0x50)) = 0xfe18;
-	(*(volatile uint32_t *)(phy_reg_base + 0x38)) = 0xe0004;
-	(*(volatile uint32_t *)(phy_reg_base + 0x34)) = 0xc8000;
+	(*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB2_PHY_PLL_OFFSET_10;
+	(*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB2_PHY_PLL_OFFSET_50;
+	(*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_SET;
+	(*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34;
 #endif
 }
 #endif
diff --git a/arch/arm/cpu/armv8/tm2/Makefile b/arch/arm/cpu/armv8/tm2/Makefile
index 4be814b..0dc8fb4 100644
--- a/arch/arm/cpu/armv8/tm2/Makefile
+++ b/arch/arm/cpu/armv8/tm2/Makefile
@@ -8,6 +8,7 @@ obj-y	+= timer.o
 obj-y	+= mailbox.o
 obj-y   += gate_init.o
 obj-y   += power_cal.o
+obj-y   += power_domain.o
 obj-$(CONFIG_CMD_PLLTEST)	+= pll.o
 obj-$(CONFIG_CMD_AML_MTEST) += core.o
 obj-$(CONFIG_CMD_HDMIRX) += hdmirx/
\ No newline at end of file
diff --git a/arch/arm/cpu/armv8/tm2/firmware/acs/acs.mk b/arch/arm/cpu/armv8/tm2/firmware/acs/acs.mk
index 2294d53..883a9df 100644
--- a/arch/arm/cpu/armv8/tm2/firmware/acs/acs.mk
+++ b/arch/arm/cpu/armv8/tm2/firmware/acs/acs.mk
@@ -1,8 +1,9 @@
-SOURCES		+=	acs.c				\
-			acs_entry.S
+SOURCES		+=	acs_entry.S
 
 ifdef CONFIG_MDUMP_COMPRESS
 SOURCES		+=	ramdump.c
 endif
 
+SOURCES		+=	acs.c
+
 LINKERFILE_T		:=	acs.ld.S
diff --git a/arch/arm/cpu/armv8/tm2/power_domain.c b/arch/arm/cpu/armv8/tm2/power_domain.c
new file mode 100644
index 0000000..1f8a479
--- a/dev/null
+++ b/arch/arm/cpu/armv8/tm2/power_domain.c
@@ -0,0 +1,402 @@
+/*
+ * drivers/amlogic/power/power_domain.c
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/power_domain.h>
+
+static void power_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+
+	value = readl(AO_RTI_GEN_PWR_SLEEP0);
+	if (pwr_switch == PWR_ON)
+		value &= ~(1 << pwr_domain);
+	else
+		value |= (1 << pwr_domain);
+	writel(value, (AO_RTI_GEN_PWR_SLEEP0));
+}
+
+static void mem_pd_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+
+	if (pwr_switch == PWR_ON) {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			writel(0x0, P_DOS_MEM_PD_HCODEC);
+			break;
+		case PM_DOS_VDEC:
+			writel(0x0, P_DOS_MEM_PD_VDEC);
+			break;
+		case PM_DOS_HEVC:
+			writel(0x0, P_DOS_MEM_PD_HEVC);
+			break;
+		case PM_CSI:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0x3 << 6);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_VPU:
+			writel(0x0, HHI_VPU_MEM_PD_REG0);
+			writel(0x0, HHI_VPU_MEM_PD_REG1);
+			writel(0x0, HHI_VPU_MEM_PD_REG2);
+			writel(0x0, HHI_VPU_MEM_PD_REG3);
+			writel(0x0, HHI_VPU_MEM_PD_REG4);
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xff << 8);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_NN:
+			writel(0x0, HHI_NANOQ_MEM_PD_REG0);
+			writel(0x0, HHI_NANOQ_MEM_PD_REG1);
+			break;
+		case PM_USB:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0x3 << 30);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_PCIE0:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xf<<26);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_GE2D:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xff<<18);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_PCIE1:
+			value = readl(HHI_MEM_PD_REG0);
+			value &= ~(0xf<<4);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_DSPA:
+			value = readl(HHI_DSP_MEM_PD_REG0);
+			value &= ~(0xffff);
+			writel(value, HHI_DSP_MEM_PD_REG0);
+			break;
+		case PM_DSPB:
+			value = readl(HHI_DSP_MEM_PD_REG0);
+			value &= ~(0xffff<<16);
+			writel(value, HHI_DSP_MEM_PD_REG0);
+			break;
+		case PM_DEMOD:
+			value = readl(HHI_DEMOD_MEM_PD_REG);
+			value &= ~0x2fff;
+			writel(value, HHI_DEMOD_MEM_PD_REG);
+			break;
+		}
+	} else {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			writel(0xffffffff, P_DOS_MEM_PD_HCODEC);
+			break;
+		case PM_DOS_VDEC:
+			writel(0xffffffff, P_DOS_MEM_PD_VDEC);
+			break;
+		case PM_DOS_HEVC:
+			writel(0xffffffff, P_DOS_MEM_PD_HEVC);
+			break;
+		case PM_CSI:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0x3 << 6);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_VPU:
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG0);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG1);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG2);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG3);
+			writel(0xffffffff, HHI_VPU_MEM_PD_REG4);
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xff << 8);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_NN:
+			writel(0xffffffff, HHI_NANOQ_MEM_PD_REG0);
+			writel(0xffffffff, HHI_NANOQ_MEM_PD_REG1);
+			break;
+		case PM_USB:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0x3 << 30);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_PCIE0:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xf<<26);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_GE2D:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xff<<18);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_PCIE1:
+			value = readl(HHI_MEM_PD_REG0);
+			value |= (0xf<<4);
+			writel(value, HHI_MEM_PD_REG0);
+			break;
+		case PM_DSPA:
+			value = readl(HHI_DSP_MEM_PD_REG0);
+			value |= (0xffff);
+			writel(value, HHI_DSP_MEM_PD_REG0);
+			break;
+		case PM_DSPB:
+			value = readl(HHI_DSP_MEM_PD_REG0);
+			value |= (0xffff<<16);
+			writel(value, HHI_DSP_MEM_PD_REG0);
+			break;
+		case PM_DEMOD:
+			value = readl(HHI_DEMOD_MEM_PD_REG);
+			value |= 0x2fff;
+			writel(value, HHI_DEMOD_MEM_PD_REG);
+			break;
+		}
+	}
+}
+
+static void reset_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+	unsigned int tmp;
+
+	if (pwr_switch == PWR_ON) {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			value = readl(P_DOS_SW_RESET1);
+			value &= ~(0xffff<<2);
+			writel(value, P_DOS_SW_RESET1);
+			break;
+		case PM_DOS_VDEC:
+			value = readl(P_DOS_SW_RESET0);
+			value &= ~(0x1fff<<2);
+			writel(value, P_DOS_SW_RESET0);
+			break;
+		case PM_DOS_HEVC:
+			value = readl(P_DOS_SW_RESET3);
+			value &= ~(0x3ffff<<2 | 1<<24);
+			writel(value, P_DOS_SW_RESET3);
+			break;
+		case PM_VPU:
+			tmp = 0x1 << 5 | 0x1 << 10 | 0x1 << 19 | 0x1 << 13;
+			value = readl(P_RESET0_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET0_LEVEL);
+			tmp = 0x1 << 5 | 0x1 << 4;
+			value = readl(P_RESET1_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET1_LEVEL);
+			tmp = 0x1 << 15;
+			value = readl(P_RESET2_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET2_LEVEL);
+			tmp = 0x1 << 6 | 0x1 << 7 | 0x1 << 13 |
+			      0x1 << 5 | 0x1 << 9 | 0x1 << 4 | 0x1 << 12;
+			value = readl(P_RESET4_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET4_LEVEL);
+			tmp = 0x1 << 7;
+			value = readl(P_RESET7_LEVEL);
+			value |= tmp;
+			writel(value, P_RESET7_LEVEL);
+			break;
+		case PM_NN:
+			value = readl(P_RESET2_LEVEL);
+			value |= (0x1<<12);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		case PM_USB:
+			value = readl(P_RESET1_LEVEL);
+			value |= (0x1<<2);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_PCIE0:
+			value = readl(P_RESET0_LEVEL);
+			value |= ((0x1<<12)|(0x3<<14));
+			writel(value, P_RESET0_LEVEL);
+			break;
+		case PM_GE2D:
+			value = readl(P_RESET2_LEVEL);
+			value |= (0x1<<6);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		case PM_PCIE1:
+			value = readl(P_RESET0_LEVEL);
+			value |= (0x7<<28);
+			writel(value, P_RESET0_LEVEL);
+			break;
+		case PM_DSPA:
+			value = readl(P_RESET4_LEVEL);
+			value |= 0x1;
+			writel(value, P_RESET4_LEVEL);
+			value = readl(P_RESET1_LEVEL);
+			value |= (0x1<<20);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_DSPB:
+			value = readl(P_RESET4_LEVEL);
+			value |= (0x1<<1);
+			writel(value, P_RESET4_LEVEL);
+			value = readl(P_RESET1_LEVEL);
+			value |= (0x1<<21);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_DEMOD:
+			value = readl(P_RESET0_LEVEL);
+			value |= (0x1<<8);
+			writel(value, P_RESET0_LEVEL);
+			break;
+		}
+	} else {
+		switch (pwr_domain) {
+		case PM_DOS_HCODEC:
+			value = readl(P_DOS_SW_RESET1);
+			value |= (0xffff<<2);
+			writel(value, P_DOS_SW_RESET1);
+			break;
+		case PM_DOS_VDEC:
+			value = readl(P_DOS_SW_RESET0);
+			value |= (0x1fff<<2);
+			writel(value, P_DOS_SW_RESET0);
+			break;
+		case PM_DOS_HEVC:
+			value = readl(P_DOS_SW_RESET3);
+			value |= (0x3ffff<<2 | 1<<24);
+			writel(value, P_DOS_SW_RESET3);
+			break;
+		case PM_VPU:
+			tmp = 0x1 << 5 | 0x1 << 10 | 0x1 << 19 | 0x1 << 13;
+			value = readl(P_RESET0_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET0_LEVEL);
+			tmp = 0x1 << 5 | 0x1 << 4;
+			value = readl(P_RESET1_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET1_LEVEL);
+			tmp = 0x1 << 15;
+			value = readl(P_RESET2_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET2_LEVEL);
+			tmp = 0x1 << 6 | 0x1 << 7 | 0x1 << 13 |
+			      0x1 << 5 | 0x1 << 9 | 0x1 << 4 | 0x1 << 12;
+			value = readl(P_RESET4_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET4_LEVEL);
+			tmp = 0x1 << 7;
+			value = readl(P_RESET7_LEVEL);
+			value &= ~tmp;
+			writel(value, P_RESET7_LEVEL);
+			break;
+		case PM_NN:
+			value = readl(P_RESET2_LEVEL);
+			value &= ~(0x1<<12);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		case PM_USB:
+			value = readl(P_RESET1_LEVEL);
+			value &= ~(0x1<<2);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_PCIE0:
+			value = readl(P_RESET0_LEVEL);
+			value &= ~((0x1<<12)|(0x3<<14));
+			writel(value, P_RESET0_LEVEL);
+			break;
+		case PM_GE2D:
+			value = readl(P_RESET2_LEVEL);
+			value &= ~(0x1<<6);
+			writel(value, P_RESET2_LEVEL);
+			break;
+		case PM_PCIE1:
+			value = readl(P_RESET0_LEVEL);
+			value &= ~(0x7<<28);
+			writel(value, P_RESET0_LEVEL);
+			break;
+		case PM_DSPA:
+			value = readl(P_RESET4_LEVEL);
+			value &= ~0x1;
+			writel(value, P_RESET4_LEVEL);
+			value = readl(P_RESET1_LEVEL);
+			value &= ~(0x1<<20);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_DSPB:
+			value = readl(P_RESET4_LEVEL);
+			value &= ~(0x1<<1);
+			writel(value, P_RESET4_LEVEL);
+			value = readl(P_RESET1_LEVEL);
+			value &= ~(0x1<<21);
+			writel(value, P_RESET1_LEVEL);
+			break;
+		case PM_DEMOD:
+			value = readl(P_RESET0_LEVEL);
+			value &= ~(0x1<<8);
+			writel(value, P_RESET0_LEVEL);
+			break;
+		}
+	}
+}
+
+static void iso_switch(int pwr_domain, bool pwr_switch)
+{
+	unsigned int value;
+
+	value = readl(AO_RTI_GEN_PWR_ISO0);
+	if (pwr_switch == PWR_ON)
+		value &= ~(1 << pwr_domain);
+	else
+		value |= (1 << pwr_domain);
+	writel(value, AO_RTI_GEN_PWR_ISO0);
+}
+
+void power_domain_switch(int pwr_domain, bool pwr_switch)
+{
+	if (pwr_switch == PWR_ON) {
+		/* Powerup Power Domain */
+		power_switch(pwr_domain, PWR_ON);
+		udelay(50);
+
+		/* Powerup memories */
+		mem_pd_switch(pwr_domain, PWR_ON);
+		udelay(150);
+
+		reset_switch(pwr_domain, PWR_OFF);
+
+		/* remove isolations */
+		iso_switch(pwr_domain, PWR_ON);
+
+		/* deassert reset */
+		reset_switch(pwr_domain, PWR_ON);
+
+	} else {
+		/* reset */
+		reset_switch(pwr_domain, PWR_OFF);
+
+		/* add isolation to domain */
+		iso_switch(pwr_domain, PWR_OFF);
+
+		/* Power down memories */
+		mem_pd_switch(pwr_domain, PWR_OFF);
+		udelay(50);
+
+		/* Power off  domain */
+		power_switch(pwr_domain, PWR_OFF);
+	}
+}
diff --git a/arch/arm/cpu/armv8/tm2/usb.c b/arch/arm/cpu/armv8/tm2/usb.c
index 367ba4b..ab27209 100644
--- a/arch/arm/cpu/armv8/tm2/usb.c
+++ b/arch/arm/cpu/armv8/tm2/usb.c
@@ -21,7 +21,7 @@
 
 #include <asm/arch/usb-v2.h>
 #include <asm/arch/romboot.h>
-
+#include <amlogic/power_domain.h>
 
 static struct amlogic_usb_config * g_usb_cfg[BOARD_USB_MODE_MAX][USB_PHY_PORT_MAX];
 
@@ -52,14 +52,7 @@ int usb_index = 0;
 void board_usb_init(struct amlogic_usb_config * usb_cfg,int mode)
 {
 #ifdef CONFIG_USB_POWER
-	writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_SLEEP0);
-	writel((readl(HHI_MEM_PD_REG0) & (~(0x3<<30))), HHI_MEM_PD_REG0);
-
-	udelay(100);
-
-	writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_ISO0);
+	power_domain_switch(PM_USB, PWR_ON);
 #endif
 
 	if (mode < 0 || mode >= BOARD_USB_MODE_MAX || !usb_cfg)
diff --git a/arch/arm/cpu/armv8/txhd/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/cpu/armv8/txhd/firmware/scp_task/hdmi_cec_arc.c
index c01523b..0023adf 100644
--- a/arch/arm/cpu/armv8/txhd/firmware/scp_task/hdmi_cec_arc.c
+++ b/arch/arm/cpu/armv8/txhd/firmware/scp_task/hdmi_cec_arc.c
@@ -29,6 +29,7 @@
 cec_msg_t cec_msg;
 unsigned char hdmi_cec_func_config;
 cec_wakeup_t cec_wakup;
+static unsigned int cec_wait_addr;
 
 #ifdef CEC_DBG_PRINT
 static void cec_dbg_print(char *s, int v)
@@ -847,6 +848,7 @@ void cec_node_init(void)
 		 {CEC_PLAYBACK_DEVICE_2_ADDR, CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR},
 		 {CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR, CEC_PLAYBACK_DEVICE_2_ADDR}};
 
+	cec_wait_addr = 0;
 	uart_puts(CEC_VERSION);
 	if (retry >= 12) {  /* retry all device addr */
 		cec_msg.log_addr = 0x0f;
@@ -946,7 +948,6 @@ void cec_node_init(void)
 
 int cec_suspend_wakeup_chk(void)
 {
-	static unsigned int cec_wait_addr = 0;
 	int exit_reason = 0;
 
 	if ((cec_msg.cec_power == 0x1) &&
diff --git a/arch/arm/cpu/armv8/txl/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/cpu/armv8/txl/firmware/scp_task/hdmi_cec_arc.c
index baca348..96141db 100644
--- a/arch/arm/cpu/armv8/txl/firmware/scp_task/hdmi_cec_arc.c
+++ b/arch/arm/cpu/armv8/txl/firmware/scp_task/hdmi_cec_arc.c
@@ -38,6 +38,7 @@ Description:
 cec_msg_t cec_msg;
 unsigned char hdmi_cec_func_config;
 cec_wakeup_t cec_wakup;
+static unsigned int cec_wait_addr;
 
 #ifdef CEC_DBG_PRINT
 static void cec_dbg_print(char *s, int v)
@@ -850,6 +851,7 @@ void cec_node_init(void)
 		 {CEC_PLAYBACK_DEVICE_2_ADDR, CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR},
 		 {CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR, CEC_PLAYBACK_DEVICE_2_ADDR}};
 
+	cec_wait_addr = 0;
 	uart_puts(CEC_VERSION);
 	if (retry >= 12) {  /* retry all device addr */
 		cec_msg.log_addr = 0x0f;
@@ -949,7 +951,6 @@ void cec_node_init(void)
 
 int cec_suspend_wakeup_chk(void)
 {
-	static unsigned int cec_wait_addr = 0;
 	int exit_reason = 0;
 
 	if ((cec_msg.cec_power == 0x1) &&
diff --git a/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c
index 44642de..caaf36d 100644
--- a/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c
+++ b/arch/arm/cpu/armv8/txlx/firmware/scp_task/hdmi_cec_arc.c
@@ -38,6 +38,7 @@ Description:
 cec_msg_t cec_msg;
 unsigned char hdmi_cec_func_config;
 cec_wakeup_t cec_wakup;
+static unsigned int cec_wait_addr;
 
 #ifdef CEC_DBG_PRINT
 static void cec_dbg_print(char *s, int v)
@@ -856,6 +857,7 @@ void cec_node_init(void)
 		 {CEC_PLAYBACK_DEVICE_2_ADDR, CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR},
 		 {CEC_PLAYBACK_DEVICE_3_ADDR, CEC_PLAYBACK_DEVICE_1_ADDR, CEC_PLAYBACK_DEVICE_2_ADDR}};
 
+	cec_wait_addr = 0;
 	uart_puts(CEC_VERSION);
 	if (retry >= 12) {  /* retry all device addr */
 		cec_msg.log_addr = 0x0f;
@@ -955,7 +957,6 @@ void cec_node_init(void)
 
 int cec_suspend_wakeup_chk(void)
 {
-	static unsigned int cec_wait_addr = 0;
 	int exit_reason = 0;
 
 	if ((cec_msg.cec_power == 0x1) &&
diff --git a/arch/arm/include/asm/arch-g12a/cpu.h b/arch/arm/include/asm/arch-g12a/cpu.h
index 636e199..c6b4200 100644
--- a/arch/arm/include/asm/arch-g12a/cpu.h
+++ b/arch/arm/include/asm/arch-g12a/cpu.h
@@ -89,6 +89,8 @@
 #define CONFIG_AML_RSVD_ADDR	0x08300000
 #define CONFIG_AML_RSVD_SIZE	0x100000
 
+#define CONFIG_AML_POWER_DOMAIN	1
+
 /* bl33 boot time */
 //#define BL33_BOOT_TIME_PROBE
 
diff --git a/arch/arm/include/asm/arch-g12a/pll.h b/arch/arm/include/asm/arch-g12a/pll.h
index bbbd8f3..e9885f9 100644
--- a/arch/arm/include/asm/arch-g12a/pll.h
+++ b/arch/arm/include/asm/arch-g12a/pll.h
@@ -22,8 +22,10 @@ Description:
 #ifndef __PLL_H
 #define __PLL_H
 
-#define PLL_TEST_SYS_TOTAL		8
-#define PLL_TEST_HDMI_TOTAL		4
+#define PLL_TEST_SYS_TOTAL		2
+#define PLL_TEST_HIFI_TOTAL		2
+#define PLL_TEST_GP0_TOTAL		2
+#define PLL_TEST_HDMI_TOTAL		3
 
 typedef struct sys_pll_set_s {
 	unsigned int cpu_clk;
@@ -40,22 +42,6 @@ typedef struct sys_pll_cfg_s {
 	sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
 }sys_pll_cfg_t;
 
-#if 0
-unsigned int fix_pll_cfg[6] = {
-			/* CNTL,	CNTL2,		CNTL3,		CNTL4,		CNTL5,		CNTL6*/
-	/*2G*/ 0x600006FA, 0x59C80000, 0xCA753822, 0x00010006, 0x95520E1A, 0xFC454545,
-};
-
-unsigned int ddr_pll_cfg[][6] = {
-	{0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0},
-};
-#endif
-
 typedef struct hdmi_pll_set_s {
 	unsigned int pll_clk;
 	unsigned int pll_cntl0;
@@ -78,6 +64,13 @@ typedef struct gpll_rate_table_s {
 	unsigned int od;
 }gpll_rate_table_t;
 
+typedef struct hifipll_rate_table_s {
+	unsigned int rate;
+	unsigned int m;
+	unsigned int n;
+	unsigned int od;
+}hifipll_rate_table_t;
+
 typedef struct gp0_pll_set_s {
 	unsigned int pll_clk;
 	unsigned int pll_cntl0;
@@ -89,20 +82,71 @@ typedef struct gp0_pll_set_s {
 	unsigned int pll_cntl6;
 }gp0_pll_set_t;
 
-#if 0
-unsigned int hdmi_pll_cfg[][7] = {
-	/* get from enc_clk_config.c */
-	/* freq, cntl, cntl1, cntl2, cntl3, cntl4, cntl5 */
-	{5940000, 0x4000027b, 0x800cb300, 0xc60f30e0, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{5405400, 0x400002e1, 0x800cb0e6, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{4455000, 0x400002b9, 0x800cb280, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{4324320, 0x400002b4, 0x800cb0b8, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{3712500, 0x4000029a, 0x800cb2c0, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{3450000, 0x4000028f, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{3243240, 0x40000287, 0x800cb08a, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
-	{2970000, 0x4000027b, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+typedef struct gp0_pll_cfg_s {
+	gp0_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL];
+}gp0_pll_cfg_t;
+
+typedef struct hifi_pll_set_s {
+	unsigned int pll_clk;
+	unsigned int pll_cntl0;
+	unsigned int pll_cntl1;
+	unsigned int pll_cntl2;
+	unsigned int pll_cntl3;
+	unsigned int pll_cntl4;
+	unsigned int pll_cntl5;
+	unsigned int pll_cntl6;
+}hifi_pll_set_t;
+
+typedef struct hifi_pll_cfg_s {
+	hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL];
+}hifi_pll_cfg_t;
+
+typedef struct pcie_pll_set_s {
+	unsigned int pll_clk;
+	unsigned int pll_cntl0;
+	unsigned int pll_cntl1;
+	unsigned int pll_cntl2;
+	unsigned int pll_cntl3;
+	unsigned int pll_cntl4;
+	unsigned int pll_cntl5;
+}pcie_pll_set_t;
+
+typedef struct ethphy_pll_set_s {
+	unsigned int pll_clk;
+	unsigned int pll_cntl0;
+	unsigned int pll_cntl1;
+	unsigned int pll_cntl2;
+	unsigned int pll_cntl3;
+}ethphy_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+	unsigned int pll_clk;
+	unsigned int pll_cntl0;
+	unsigned int pll_cntl1;
+	unsigned int pll_cntl2;
+	unsigned int pll_cntl3;
+	unsigned int pll_cntl4;
+	unsigned int pll_cntl5;
+	unsigned int pll_cntl6;
+	unsigned int pll_cntl7;
+}usbphy_pll_set_t;
+
+struct pciepll_rate_table {
+	u16		rate;
+	u16		m;
+	u16		n;
+	u16		od;
+	u16		od2;
+	u16		frac;
 };
-#endif
+
+#define PLL_RATE(_r, _m, _n, _od)					\
+	{								\
+		.rate		= (_r),					\
+		.m		= (_m),					\
+		.n		= (_n),					\
+		.od		= (_od),				\
+	}								\
 
 enum pll_enum {
 	PLL_SYS = 0,
@@ -110,9 +154,14 @@ enum pll_enum {
 	PLL_DDR,
 	PLL_HDMI,
 	PLL_GP0,
+	PLL_HIFI,
+	PLL_PCIE,
+	PLL_ETHPHY,
+	PLL_USBPHY,
 	PLL_ENUM,
+
 };
 
 int pll_test(int argc, char * const argv[]);
 
-#endif /* __PLL_H */
\ No newline at end of file
+#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-g12a/regs.h b/arch/arm/include/asm/arch-g12a/regs.h
index d5dfb56..931be25 100644
--- a/arch/arm/include/asm/arch-g12a/regs.h
+++ b/arch/arm/include/asm/arch-g12a/regs.h
@@ -6325,8 +6325,8 @@ Description:
 #define P_DOS_SW_RESET4                            (volatile unsigned int *)((0x3f37  << 2) + 0xff620000)
 #define   DOS_GCLK_EN4                             (0x3f38)
 #define P_DOS_GCLK_EN4                             (volatile unsigned int *)((0x3f38  << 2) + 0xff620000)
-#define   DOS_MEM_PD_VP9DEC                        (0x3f39)
-#define P_DOS_MEM_PD_VP9DEC                        (volatile unsigned int *)((0x3f39  << 2) + 0xff620000)
+#define   DOS_MEM_PD_WAVE420L                      (0x3f39)
+#define P_DOS_MEM_PD_WAVE420L                      (volatile unsigned int *)((0x3f39  << 2) + 0xff620000)
 // bit[31]    mcrcc_stall_en
 // bit[30:28] Reserved
 // bit[27:20] target_canvas
diff --git a/arch/arm/include/asm/arch-g12a/secure_apb.h b/arch/arm/include/asm/arch-g12a/secure_apb.h
index e3e9c89..fb98665 100644
--- a/arch/arm/include/asm/arch-g12a/secure_apb.h
+++ b/arch/arm/include/asm/arch-g12a/secure_apb.h
@@ -2461,6 +2461,13 @@ Description:
 #define     HHI_VPU_MEM_PD_REG4                                (0xff63c000 + (0x044 << 2))
 #define SEC_HHI_VPU_MEM_PD_REG4                                (0xff63c000 + (0x044 << 2))
 #define   P_HHI_VPU_MEM_PD_REG4                                (volatile uint32_t *)(0xff63c000 + (0x044 << 2))
+#define     HHI_NANOQ_MEM_PD_REG0                              (0xff63c000 + (0x046 << 2))
+#define SEC_HHI_NANOQ_MEM_PD_REG0                              (0xff63c000 + (0x046 << 2))
+#define   P_HHI_NANOQ_MEM_PD_REG0                              (volatile uint32_t *)(0xff63c000 + (0x046 << 2))
+#define     HHI_NANOQ_MEM_PD_REG1                              (0xff63c000 + (0x047 << 2))
+#define SEC_HHI_NANOQ_MEM_PD_REG1                              (0xff63c000 + (0x047 << 2))
+#define   P_HHI_NANOQ_MEM_PD_REG1                              (volatile uint32_t *)(0xff63c000 + (0x047 << 2))
+
 //`define HHI_DEMOD_MEM_PD_REG     8'h43
 //`define HHI_AUD_DAC_CTRL          8'h44
 // `define HHI_VIID_PLL_CNTL4      8'h46 // video PLL read back
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h
index 88a907a..0ba6cce 100644
--- a/arch/arm/include/asm/arch-g12a/timing.h
+++ b/arch/arm/include/asm/arch-g12a/timing.h
@@ -387,7 +387,7 @@ typedef struct ddr_set{
 	//system reserve,do not modify
 	/* align8 */
     unsigned	char	char_rev1;
-	unsigned	char	char_rev2;
+	unsigned	char	training_offset;//char_rev2;
 	unsigned	int		ddr_dmc_remap[5];
 	unsigned	int		dram_rtt_nom_wr_park[2];
 	//system reserve,do not modify
diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h
index 88a907a..0ba6cce 100644
--- a/arch/arm/include/asm/arch-g12b/timing.h
+++ b/arch/arm/include/asm/arch-g12b/timing.h
@@ -387,7 +387,7 @@ typedef struct ddr_set{
 	//system reserve,do not modify
 	/* align8 */
     unsigned	char	char_rev1;
-	unsigned	char	char_rev2;
+	unsigned	char	training_offset;//char_rev2;
 	unsigned	int		ddr_dmc_remap[5];
 	unsigned	int		dram_rtt_nom_wr_park[2];
 	//system reserve,do not modify
diff --git a/arch/arm/include/asm/arch-tl1/timing.h b/arch/arm/include/asm/arch-tl1/timing.h
index 8dc22f0..d0430b1 100644
--- a/arch/arm/include/asm/arch-tl1/timing.h
+++ b/arch/arm/include/asm/arch-tl1/timing.h
@@ -376,7 +376,7 @@ typedef struct ddr_set{
 	//system reserve,do not modify
 	/* align8 */
     unsigned	char	char_rev1;
-	unsigned	char	char_rev2;
+	unsigned	char	training_offset;//char_rev2;
 	unsigned	int		ddr_dmc_remap[5];
 	unsigned	int		dram_rtt_nom_wr_park[2];
 	//system reserve,do not modify
diff --git a/arch/arm/include/asm/arch-tm2/cpu.h b/arch/arm/include/asm/arch-tm2/cpu.h
index 3ef43e5..438daa7 100644
--- a/arch/arm/include/asm/arch-tm2/cpu.h
+++ b/arch/arm/include/asm/arch-tm2/cpu.h
@@ -81,6 +81,8 @@
 #define CONFIG_AML_RSVD_ADDR	0x08300000
 #define CONFIG_AML_RSVD_SIZE	0x100000
 
+#define CONFIG_AML_POWER_DOMAIN	1
+
 /* bl33 boot time */
 //#define BL33_BOOT_TIME_PROBE
 
diff --git a/arch/arm/include/asm/arch-tm2/timing.h b/arch/arm/include/asm/arch-tm2/timing.h
index 8dc22f0..d0430b1 100644
--- a/arch/arm/include/asm/arch-tm2/timing.h
+++ b/arch/arm/include/asm/arch-tm2/timing.h
@@ -376,7 +376,7 @@ typedef struct ddr_set{
 	//system reserve,do not modify
 	/* align8 */
     unsigned	char	char_rev1;
-	unsigned	char	char_rev2;
+	unsigned	char	training_offset;//char_rev2;
 	unsigned	int		ddr_dmc_remap[5];
 	unsigned	int		dram_rtt_nom_wr_park[2];
 	//system reserve,do not modify
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig
index a90d41c..dde1ded 100755..100644
--- a/board/amlogic/Kconfig
+++ b/board/amlogic/Kconfig
@@ -208,6 +208,10 @@ config G12A_DEADPOOL_V1
 	bool "Support amlogic g12a deadpool v1 board"
 	default n
 
+config SM1_ELEKTRA_V1
+	bool "Support amlogic sm1 elektra v1 board"
+	default n
+
 config G12A_U220_V1
 	bool "Support amlogic g12a u220 v1 board"
 	default n
@@ -507,6 +511,10 @@ if G12A_DEADPOOL_V1
 source "board/amlogic/g12a_deadpool_v1/Kconfig"
 endif
 
+if SM1_ELEKTRA_V1
+source "board/amlogic/sm1_elektra_v1/Kconfig"
+endif
+
 if G12A_U220_V1
 source "board/amlogic/g12a_u220_v1/Kconfig"
 endif
diff --git a/board/amlogic/configs/g12a_skt_v1.h b/board/amlogic/configs/g12a_skt_v1.h
index c0a7b2e..0933f80 100644
--- a/board/amlogic/configs/g12a_skt_v1.h
+++ b/board/amlogic/configs/g12a_skt_v1.h
@@ -54,6 +54,8 @@
   */
 #define CONFIG_BOOTLOADER_CONTROL_BLOCK
 
+#define CONFIG_CMD_BOOTCTOL_AVB
+
 /* Serial config */
 #define CONFIG_CONS_INDEX 2
 #define CONFIG_BAUDRATE  115200
@@ -134,7 +136,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
diff --git a/board/amlogic/configs/g12a_u200_v1.h b/board/amlogic/configs/g12a_u200_v1.h
index 1b432aa..5512f2d 100644
--- a/board/amlogic/configs/g12a_u200_v1.h
+++ b/board/amlogic/configs/g12a_u200_v1.h
@@ -141,7 +141,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -252,15 +252,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/g12a_u202_v1.h b/board/amlogic/configs/g12a_u202_v1.h
index cc9d654..17d3e73 100644
--- a/board/amlogic/configs/g12a_u202_v1.h
+++ b/board/amlogic/configs/g12a_u202_v1.h
@@ -141,7 +141,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout2=${outputmode2}, vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} ${fs_type}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout2=${outputmode2}, vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -249,15 +249,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/g12a_u211_v1.h b/board/amlogic/configs/g12a_u211_v1.h
index e034c62..63d27b9 100644
--- a/board/amlogic/configs/g12a_u211_v1.h
+++ b/board/amlogic/configs/g12a_u211_v1.h
@@ -138,7 +138,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -249,15 +249,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/g12a_u212_v1.h b/board/amlogic/configs/g12a_u212_v1.h
index 1737f7c..684f61a 100644
--- a/board/amlogic/configs/g12a_u212_v1.h
+++ b/board/amlogic/configs/g12a_u212_v1.h
@@ -140,7 +140,7 @@
             "\0"\
         "storeargs="\
 		"get_bootloaderversion;" \
-		"setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+		"setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -251,15 +251,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/g12a_u220_v1.h b/board/amlogic/configs/g12a_u220_v1.h
index 6d76504..c1306c6 100644
--- a/board/amlogic/configs/g12a_u220_v1.h
+++ b/board/amlogic/configs/g12a_u220_v1.h
@@ -137,7 +137,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -248,15 +248,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/g12a_u223_v1.h b/board/amlogic/configs/g12a_u223_v1.h
index 3867515..48abbb3 100644
--- a/board/amlogic/configs/g12a_u223_v1.h
+++ b/board/amlogic/configs/g12a_u223_v1.h
@@ -138,7 +138,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode}  hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode}  hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -249,15 +249,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/g12b_skt_v1.h b/board/amlogic/configs/g12b_skt_v1.h
index 226c477..1eb4643 100644
--- a/board/amlogic/configs/g12b_skt_v1.h
+++ b/board/amlogic/configs/g12b_skt_v1.h
@@ -133,7 +133,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
diff --git a/board/amlogic/configs/g12b_w200_v1.h b/board/amlogic/configs/g12b_w200_v1.h
index 30d1d1b..d4350e1 100644
--- a/board/amlogic/configs/g12b_w200_v1.h
+++ b/board/amlogic/configs/g12b_w200_v1.h
@@ -140,7 +140,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
diff --git a/board/amlogic/configs/g12b_w400_v1.h b/board/amlogic/configs/g12b_w400_v1.h
index f67799d..05c8c85 100644
--- a/board/amlogic/configs/g12b_w400_v1.h
+++ b/board/amlogic/configs/g12b_w400_v1.h
@@ -140,7 +140,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} vout2=${outputmode2},enable vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout2=${outputmode2},enable vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -343,12 +343,22 @@
  * logo2: bootup_rotate_secondary.bmp (for portrait screen)
  */
 #define CONFIG_DUAL_LOGO \
-	"setenv outputmode $hdmimode;setenv display_layer osd0;"\
-	"vout output $hdmimode;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;"\
+	"setenv outputmode 1080p60hz;setenv display_layer osd0;"\
+	"setenv fb_height 1080; setenv fb_width 1920;"\
+	"vout output $outputmode;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;"\
 	"setenv outputmode2 panel;setenv display_layer viu2_osd0;"\
 	"vout2 prepare panel;osd open;osd clear;imgread pic logo bootup_rotate_secondary $loadaddr;bmp display $bootup_rotate_secondary_offset;bmp scale;vout2 output panel;"\
 	"\0"\
 
+/* for portrait panel, recovery always displays on panel */
+#define CONFIG_RECOVERY_DUAL_LOGO \
+	"setenv outputmode panel;setenv display_layer osd0;"\
+	"setenv fb_height 1920; setenv fb_width 1080;"\
+	"vout output $outputmode;osd open;osd clear;imgread pic logo bootup_rotate $loadaddr;bmp display $bootup_rotate_offset;bmp scale;"\
+	"setenv outputmode2 1080p60hz;setenv display_layer viu2_osd0;"\
+	"vout2 prepare $outputmode2;vout2 output $outputmode2;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;"\
+	"\0"\
+
 /* buffer rotate for portrait screen */
 #define CONFIG_SINGLE_LOGO \
 	"setenv outputmode panel;setenv display_layer osd0;"\
diff --git a/board/amlogic/configs/g12b_w411_v1.h b/board/amlogic/configs/g12b_w411_v1.h
index 3dc4f55..62f9fce 100644
--- a/board/amlogic/configs/g12b_w411_v1.h
+++ b/board/amlogic/configs/g12b_w411_v1.h
@@ -137,7 +137,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
diff --git a/board/amlogic/configs/gxl_p212_v1.h b/board/amlogic/configs/gxl_p212_v1.h
index 918aefc..fef7028 100644
--- a/board/amlogic/configs/gxl_p212_v1.h
+++ b/board/amlogic/configs/gxl_p212_v1.h
@@ -255,15 +255,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxl_p241_v1.h b/board/amlogic/configs/gxl_p241_v1.h
index a8eb15d..98b2d4c 100644
--- a/board/amlogic/configs/gxl_p241_v1.h
+++ b/board/amlogic/configs/gxl_p241_v1.h
@@ -249,15 +249,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxl_p244_v1.h b/board/amlogic/configs/gxl_p244_v1.h
index ac7d8eb..12a75cd 100644
--- a/board/amlogic/configs/gxl_p244_v1.h
+++ b/board/amlogic/configs/gxl_p244_v1.h
@@ -255,15 +255,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxl_p271_v1.h b/board/amlogic/configs/gxl_p271_v1.h
index 8af0241..aaf8b66 100644
--- a/board/amlogic/configs/gxl_p271_v1.h
+++ b/board/amlogic/configs/gxl_p271_v1.h
@@ -246,15 +246,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxl_p281_v1.h b/board/amlogic/configs/gxl_p281_v1.h
index 39c0678..f3a48eb 100644
--- a/board/amlogic/configs/gxl_p281_v1.h
+++ b/board/amlogic/configs/gxl_p281_v1.h
@@ -255,15 +255,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxl_p400_v1.h b/board/amlogic/configs/gxl_p400_v1.h
index 9b010f7..458c22c9 100644
--- a/board/amlogic/configs/gxl_p400_v1.h
+++ b/board/amlogic/configs/gxl_p400_v1.h
@@ -242,15 +242,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxl_p401_v1.h b/board/amlogic/configs/gxl_p401_v1.h
index 7849184..6723d9b 100644
--- a/board/amlogic/configs/gxl_p401_v1.h
+++ b/board/amlogic/configs/gxl_p401_v1.h
@@ -242,15 +242,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/gxm_q200_v1.h b/board/amlogic/configs/gxm_q200_v1.h
index 52c5f8e..98f4e25 100644
--- a/board/amlogic/configs/gxm_q200_v1.h
+++ b/board/amlogic/configs/gxm_q200_v1.h
@@ -134,7 +134,7 @@
             "\0"\
     "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv}  pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv}  pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
diff --git a/board/amlogic/configs/gxm_q201_v1.h b/board/amlogic/configs/gxm_q201_v1.h
index 1fa4b05..e136fdb 100644
--- a/board/amlogic/configs/gxm_q201_v1.h
+++ b/board/amlogic/configs/gxm_q201_v1.h
@@ -132,7 +132,7 @@
             "\0"\
     "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmitx=${cecconfig},${colorattribute}  hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmitx=${cecconfig},${colorattribute}  hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
diff --git a/board/amlogic/configs/sm1_ac214_v1.h b/board/amlogic/configs/sm1_ac214_v1.h
index 240824a..24a84d6 100644
--- a/board/amlogic/configs/sm1_ac214_v1.h
+++ b/board/amlogic/configs/sm1_ac214_v1.h
@@ -140,7 +140,7 @@
             "\0"\
         "storeargs="\
 		"get_bootloaderversion;" \
-		"setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+		"setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -251,15 +251,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/sm1_ac223_v1.h b/board/amlogic/configs/sm1_ac223_v1.h
index 46e995f..b07c34c 100644
--- a/board/amlogic/configs/sm1_ac223_v1.h
+++ b/board/amlogic/configs/sm1_ac223_v1.h
@@ -135,7 +135,7 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
@@ -246,15 +246,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
diff --git a/board/amlogic/configs/sm1_elektra_v1.h b/board/amlogic/configs/sm1_elektra_v1.h
new file mode 100644
index 0000000..9fd0353
--- a/dev/null
+++ b/board/amlogic/configs/sm1_elektra_v1.h
@@ -0,0 +1,697 @@
+
+/*
+ * board/amlogic/configs/sm1_elektra_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#ifndef __SM1_ELEKTRA_V1_H__
+#define __SM1_ELEKTRA_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD  1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE	800		// VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE	800		// VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE	770		// VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME		"AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+   That is used for recovery and the bootloader to talk to each other
+  */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE  115200
+#define CONFIG_AML_MESON_SERIAL   1
+#define CONFIG_SERIAL_MULTI		1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN   2  /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL    0  /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS  64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+        "firstboot=1\0"\
+        "upgrade_step=0\0"\
+        "jtag=disable\0"\
+        "loadaddr=1080000\0"\
+        "panel_type=lcd_1\0" \
+	"lcd_ctrl=0x00000000\0" \
+	"outputmode=1080p60hz\0" \
+        "hdmimode=1080p60hz\0" \
+	"colorattribute=444,8bit\0"\
+        "cvbsmode=576cvbs\0" \
+        "display_width=1920\0" \
+        "display_height=1080\0" \
+        "display_bpp=16\0" \
+        "display_color_index=16\0" \
+        "display_layer=osd0\0" \
+        "display_color_fg=0xffff\0" \
+        "display_color_bg=0\0" \
+        "dtb_mem_addr=0x1000000\0" \
+        "fb_addr=0x3d800000\0" \
+        "fb_width=1920\0" \
+        "fb_height=1080\0" \
+        "frac_rate_policy=1\0" \
+        "sdr2hdr=2\0" \
+        "hdmi_read_edid=1\0" \
+        "hdmichecksum=0x00000000\0" \
+        "dolby_status=0\0" \
+        "dolby_vision_on=0\0" \
+        "usb_burning=update 1000\0" \
+        "otg_device=0\0"\
+        "fdt_high=0x20000000\0"\
+        "try_auto_burn=update 700 750;\0"\
+        "sdcburncfg=aml_sdc_burn.ini\0"\
+        "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+        "wipe_data=successful\0"\
+        "wipe_cache=successful\0"\
+        "EnableSelinux=enforcing\0" \
+        "recovery_part=recovery\0"\
+        "lock=10001000\0"\
+        "recovery_offset=0\0"\
+        "cvbs_drv=0\0"\
+        "osd_reverse=0\0"\
+        "video_reverse=0\0"\
+        "active_slot=normal\0"\
+        "boot_part=boot\0"\
+        "reboot_mode_android=""normal""\0"\
+        "Irq_check_en=0\0"\
+        "fs_type=""rootfstype=ramfs""\0"\
+        "initargs="\
+            "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+            "\0"\
+        "upgrade_check="\
+            "echo upgrade_step=${upgrade_step}; "\
+            "if itest ${upgrade_step} == 3; then "\
+                "run init_display; run storeargs; run update;"\
+            "else fi;"\
+            "\0"\
+        "storeargs="\
+		"get_bootloaderversion;" \
+		"setenv bootargs ${initargs}  hdr_priority=${hdr_priority} otg_device=${otg_device} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en}  androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
+            "run cmdline_keys;"\
+            "\0"\
+        "switch_bootmode="\
+            "get_rebootmode;"\
+            "if test ${reboot_mode} = factory_reset; then "\
+                    "setenv reboot_mode_android ""normal"";"\
+                    "run storeargs;"\
+                    "run recovery_from_flash;"\
+            "else if test ${reboot_mode} = update; then "\
+                    "setenv reboot_mode_android ""normal"";"\
+                    "run storeargs;"\
+                    "run update;"\
+            "else if test ${reboot_mode} = quiescent; then "\
+                    "setenv reboot_mode_android ""quiescent"";"\
+                    "run storeargs;"\
+                    "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+            "else if test ${reboot_mode} = recovery_quiescent; then "\
+                    "setenv reboot_mode_android ""quiescent"";"\
+                    "run storeargs;"\
+                    "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+                    "run recovery_from_flash;"\
+            "else if test ${reboot_mode} = cold_boot; then "\
+                    "setenv reboot_mode_android ""normal"";"\
+                    "run storeargs;"\
+            "else if test ${reboot_mode} = fastboot; then "\
+                "setenv reboot_mode_android ""normal"";"\
+                "run storeargs;"\
+                "fastboot;"\
+            "fi;fi;fi;fi;fi;fi;"\
+            "\0" \
+        "storeboot="\
+            "boot_cooling;"\
+            "get_system_as_root_mode;"\
+            "echo system_mode: ${system_mode};"\
+            "if test ${system_mode} = 1; then "\
+                    "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+            "else "\
+                    "setenv bootargs ${bootargs} ${fs_type};"\
+            "fi;"\
+            "get_valid_slot;"\
+            "get_avb_mode;"\
+            "echo active_slot: ${active_slot};"\
+            "if test ${active_slot} != normal; then "\
+                    "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+            "fi;"\
+            "if test ${avb2} = 0; then "\
+                "if test ${active_slot} = _a; then "\
+                    "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
+                "else if test ${active_slot} = _b; then "\
+                    "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
+                "fi;fi;"\
+            "fi;"\
+            "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+            "run storeargs; run update;"\
+            "\0"\
+        "factory_reset_poweroff_protect="\
+            "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+            "if test ${wipe_data} = failed; then "\
+                "run init_display; run storeargs;"\
+                "if mmcinfo; then "\
+                    "run recovery_from_sdcard;"\
+                "fi;"\
+                "if usb start 0; then "\
+                    "run recovery_from_udisk;"\
+                "fi;"\
+                "run recovery_from_flash;"\
+            "fi; "\
+            "if test ${wipe_cache} = failed; then "\
+                "run init_display; run storeargs;"\
+                "if mmcinfo; then "\
+                    "run recovery_from_sdcard;"\
+                "fi;"\
+                "if usb start 0; then "\
+                    "run recovery_from_udisk;"\
+                "fi;"\
+                "run recovery_from_flash;"\
+            "fi; \0" \
+         "update="\
+            /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+            "run usb_burning; "\
+            "run sdc_burning; "\
+            "if mmcinfo; then "\
+                "run recovery_from_sdcard;"\
+            "fi;"\
+            "if usb start 0; then "\
+                "run recovery_from_udisk;"\
+            "fi;"\
+            "run recovery_from_flash;"\
+            "\0"\
+        "recovery_from_sdcard="\
+            "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+            "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+                    "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+                    "wipeisb; "\
+                    "setenv bootargs ${bootargs} ${fs_type};"\
+                    "bootm ${loadaddr};fi;"\
+            "\0"\
+        "recovery_from_udisk="\
+            "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+            "if fatload usb 0 ${loadaddr} recovery.img; then "\
+                "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+                "wipeisb; "\
+                "setenv bootargs ${bootargs} ${fs_type};"\
+                "bootm ${loadaddr};fi;"\
+            "\0"\
+        "recovery_from_flash="\
+            "get_valid_slot;"\
+            "echo active_slot: ${active_slot};"\
+            "if test ${active_slot} = normal; then "\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "if itest ${upgrade_step} == 3; then "\
+                    "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+                    "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+                "else fi;"\
+                "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+            "else "\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+            "fi;"\
+            "\0"\
+        "init_display="\
+            "get_rebootmode;"\
+            "echo reboot_mode:::: ${reboot_mode};"\
+            "if test ${reboot_mode} = quiescent; then "\
+                    "setenv reboot_mode_android ""quiescent"";"\
+                    "run storeargs;"\
+                    "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+                    "osd open;osd clear;"\
+            "else if test ${reboot_mode} = recovery_quiescent; then "\
+                    "setenv reboot_mode_android ""quiescent"";"\
+                    "run storeargs;"\
+                    "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+                    "osd open;osd clear;"\
+            "else "\
+                "setenv reboot_mode_android ""normal"";"\
+                "run storeargs;"\
+                "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;dovi process;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};dovi set;dovi pkg;vpp hdrpkt;"\
+            "fi;fi;"\
+            "\0"\
+        "cmdline_keys="\
+            "if keyman init 0x1234; then "\
+                "if keyman read usid ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+                    "setenv serial ${usid};"\
+                "else "\
+                    "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+                    "setenv serial 1234567890;"\
+                "fi;"\
+                "if keyman read mac ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+                "fi;"\
+                "if keyman read deviceid ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+                "fi;"\
+                "if keyman read oemkey ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=${oemkey};"\
+                "else "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=ATV00104319;"\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "bcb_cmd="\
+            "get_avb_mode;"\
+            "get_valid_slot;"\
+            "\0"\
+        "upgrade_key="\
+            "if gpio input GPIOAO_3; then "\
+                "echo detect upgrade key; run update;"\
+            "fi;"\
+            "\0"\
+	"irremote_update="\
+		"if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+			"echo read irkey ok!; " \
+		"if itest ${irkey_value} == 0xe31cfb04; then " \
+			"run update;" \
+		"else if itest ${irkey_value} == 0xb748fb04; then " \
+			"run update;\n" \
+			"fi;fi;" \
+		"fi;\0" \
+
+
+#define CONFIG_PREBOOT  \
+            "run bcb_cmd; "\
+            "run factory_reset_poweroff_protect;"\
+            "run upgrade_check;"\
+            "run init_display;"\
+            "run storeargs;"\
+            "run upgrade_key;" \
+            "bcb uboot-command;"\
+            "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE  1
+#define CONFIG_ENV_SIZE   (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK					1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS			1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST			0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL			0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST				0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_CMD_DDR_TEST_G12			1 //0:disable, 1:enable. G12 ddrtest cmd
+#define CONFIG_DDR_LOW_POWER			0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD				0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF			0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST			0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS			0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define		CONFIG_STORE_COMPATIBLE 1
+#define 	CONFIG_ENV_OVERWRITE
+#define 	CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+*				storage
+*		|---------|---------|
+*		|					|
+*		emmc<--Compatible-->nand
+*					|-------|-------|
+*					|				|
+*					MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND	1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef  CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY          0x200000
+#define CONFIG_TPL_COPY_NUM               4
+#define CONFIG_TPL_PART_NAME              "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM               4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART	1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR		"aml_nand.0"
+#define MTDIDS_DEFAULT		"nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT	"mtdparts=" MTDIDS_NAME_STR ":" \
+					"3M@8192K(logo),"	\
+					"10M(recovery),"	\
+					"8M(kernel),"	\
+					"40M(rootfs),"	\
+					"-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS   1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE  2
+#define CONFIG_SYS_NAND_BASE_LIST   {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define		CONFIG_AML_SD_EMMC 1
+#ifdef		CONFIG_AML_SD_EMMC
+	#define 	CONFIG_GENERIC_MMC 1
+	#define 	CONFIG_CMD_MMC 1
+	#define CONFIG_CMD_GPT 1
+	#define	CONFIG_SYS_MMC_ENV_DEV 1
+	#define CONFIG_EMMC_DDR52_EN 0
+	#define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define		CONFIG_PARTITIONS 1
+#define 	CONFIG_SYS_NO_FLASH  1
+//#define     CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+	#define CONFIG_OF_SPI
+	#define CONFIG_DM_SPI
+	#define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+	#define CONFIG_SPI_FLASH
+	#define CONFIG_DM_SPI_FLASH
+	#define CONFIG_CMD_SF
+	/* SPI flash surpport list */
+	#define CONFIG_SPI_FLASH_ATMEL
+	#define CONFIG_SPI_FLASH_EON
+	#define CONFIG_SPI_FLASH_GIGADEVICE
+	#define CONFIG_SPI_FLASH_MACRONIX
+	#define CONFIG_SPI_FLASH_SPANSION
+	#define CONFIG_SPI_FLASH_STMICRO
+	#define CONFIG_SPI_FLASH_SST
+	#define CONFIG_SPI_FLASH_WINBOND
+	#define CONFIG_SPI_FRAM_RAMTRON
+	#define CONFIG_SPI_M95XXX
+	#define CONFIG_SPI_FLASH_ESMT
+	/* SPI nand flash support */
+	#define CONFIG_SPI_NAND
+	#define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+	#define CONFIG_CMD_NAND 1
+	#define CONFIG_MTD_DEVICE y
+	#define CONFIG_RBTREE
+	#define CONFIG_CMD_NAND_TORTURE 1
+	#define CONFIG_CMD_MTDPARTS   1
+	#define CONFIG_MTD_PARTITIONS 1
+	#define CONFIG_SYS_MAX_NAND_DEVICE  2
+	#define CONFIG_SYS_NAND_BASE_LIST   {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+
+#if defined(CONFIG_AML_HDMITX20)
+#define CONFIG_AML_DOLBY 1
+#endif
+
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_AML_MINUI 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD    1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC		1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+	#define CONFIG_GXL_XHCI_BASE            0xff500000
+	#define CONFIG_GXL_USB_PHY2_BASE        0xffe09000
+	#define CONFIG_GXL_USB_PHY3_BASE        0xffe09080
+	#define CONFIG_USB_PHY_20				0xff636000
+	#define CONFIG_USB_PHY_21				0xff63A000
+	#define CONFIG_USB_STORAGE      1
+	#define CONFIG_USB_XHCI		1
+	#define CONFIG_USB_XHCI_AMLOGIC_V2 1
+/*skyworth begin*/
+	#define CONFIG_USB_GPIO_PWR  			GPIOAO(GPIOAO_2) //GPIOEE(GPIOH_6) skyworth HPA12
+	#define CONFIG_USB_GPIO_PWR_NAME		"GPIOAO_2"       //"GPIOH_6" skyworth HPA12
+/*skyworth end*/
+	//#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2		1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB        1
+#define CONFIG_USB_DEVICE_V2    1
+#define USB_PHY2_PLL_PARAMETER_1	0x09400414
+#define USB_PHY2_PLL_PARAMETER_2	0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3	0xAC5F49E5
+#define USB_G12x_PHY_PLL_SETTING_1	(0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2	(0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3	(0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4	(0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5	(0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE	0x8000000
+#define CONFIG_DEVICE_PRODUCT	"newton"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN              1       //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE   1       //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1       //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI            1       //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY                 1
+#define CONFIG_UNIFY_KEY_MANAGE                 1
+
+/* net */
+#define CONFIG_CMD_NET   1
+#if defined(CONFIG_CMD_NET)
+	#define CONFIG_DESIGNWARE_ETH 1
+	#define CONFIG_PHYLIB	1
+	#define CONFIG_NET_MULTI 1
+	#define CONFIG_CMD_PING 1
+	#define CONFIG_CMD_DHCP 1
+	#define CONFIG_CMD_RARP 1
+	#define CONFIG_HOSTNAME        arm_gxbb
+//	#define CONFIG_RANDOM_ETHADDR  1				   /* use random eth addr, or default */
+	#define CONFIG_ETHADDR         00:15:18:01:81:31   /* Ethernet address */
+	#define CONFIG_IPADDR          10.18.9.97          /* Our ip address */
+	#define CONFIG_GATEWAYIP       10.18.9.1           /* Our getway ip address */
+	#define CONFIG_SERVERIP        10.18.9.113         /* Tftp server ip address */
+	#define CONFIG_NETMASK         255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON		1
+#else
+#define CONFIG_SYS_I2C_AML			1
+#define CONFIG_SYS_I2C_SPEED		400000
+#endif
+
+/* PWM DM driver*/
+#define CONFIG_DM_PWM
+#define CONFIG_PWM_MESON
+
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG	1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301	1
+#define CONFIG_NEED_BL32	1
+#define CONFIG_CMD_RSVMEM	1
+#define CONFIG_FIP_IMG_SUPPORT	1
+#define CONFIG_BOOTDELAY	1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC     1
+#define CONFIG_CMD_ITEST    1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB    1
+
+#define CONFIG_MULTI_DTB    1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE           1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG        636
+#define CONFIG_CPU_CLK_DEBUG        600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT   1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT   1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG       1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID  (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+  #undef CONFIG_AML_CUSTOMER_ID
+  #define CONFIG_AML_CUSTOMER_ID  CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_RING
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/configs/tl1_skt_v1.h b/board/amlogic/configs/tl1_skt_v1.h
index ab05422..ae82222 100644
--- a/board/amlogic/configs/tl1_skt_v1.h
+++ b/board/amlogic/configs/tl1_skt_v1.h
@@ -120,6 +120,8 @@
         "boot_part=boot\0"\
         "suspend=off\0"\
         "powermode=on\0"\
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
         "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
         "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
         "edid_select=0\0" \
@@ -139,59 +141,87 @@
             "else fi;"\
             "\0"\
         "storeargs="\
-            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} mem_size=${mem_size} ; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} mem_size=${mem_size} ; "\
             "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
             "run cmdline_keys;"\
             "\0"\
+        "cec_init="\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn;uboot wake up "*/\
-                "echo powermode=${powermode}; "\
-                "if test ${powermode} = on; then "\
-                    /*"run try_auto_burn; "*/\
-                "else if test ${powermode} = standby; then "\
-					"echo cec_ac_wakeup=${cec_ac_wakeup}; "\
-					"if test ${cec_ac_wakeup} = 1; then "\
-						"cec ${logic_addr} ${cec_fun}; "\
-						"if test ${edid_select} = 1111; then "\
-							"hdmirx init ${port_map} ${edid_20_dir}; "\
-						"else if test ${edid_select} != 1111; then "\
-							"hdmirx init ${port_map} ${edid_14_dir}; "\
-						"fi;fi;"\
-					"fi;"\
-                    "systemoff; "\
-                "else if test ${powermode} = last; then "\
-                    "echo suspend=${suspend}; "\
-                    "if test ${suspend} = off; then "\
-                        /*"run try_auto_burn; "*/\
-                    "else if test ${suspend} = on; then "\
-						"echo cec_ac_wakeup=${cec_ac_wakeup}; "\
-						"if test ${cec_ac_wakeup} = 1; then "\
-							"cec ${logic_addr} ${cec_fun}; "\
-							"if test ${edid_select} = 1111; then "\
-								"hdmirx init ${port_map} ${edid_20_dir}; "\
-							"else if test ${edid_select} != 1111; then "\
-								"hdmirx init ${port_map} ${edid_14_dir}; "\
-							"fi;fi;"\
-						"fi;"\
-                        "systemoff; "\
-                    "else if test ${suspend} = shutdown; then "\
-                        "systemoff; "\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
                     "fi; fi; fi; "\
-                "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
             "\0" \
         "reset_suspend="\
-            "if test ${suspend} = on || test ${suspend} = shutdown; then "\
-                "setenv ""suspend off"";"\
-                "saveenv;"\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
             "fi;"\
             "\0" \
         "storeboot="\
@@ -273,15 +303,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
@@ -303,9 +338,15 @@
                 "else "\
                     "run init_display; "\
                 "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
             "else "\
                 "run init_display; "\
-            "fi; "\
+            "fi;fi; "\
             "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
diff --git a/board/amlogic/configs/tl1_t309_v1.h b/board/amlogic/configs/tl1_t309_v1.h
index a548ec5..84a6d31 100644
--- a/board/amlogic/configs/tl1_t309_v1.h
+++ b/board/amlogic/configs/tl1_t309_v1.h
@@ -121,13 +121,28 @@
         "boot_part=boot\0"\
         "suspend=off\0"\
         "powermode=on\0"\
-		"edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
-		"edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
-		"edid_select=0\0" \
-		"port_map=0x4321\0" \
-		"cec_fun=0x2F\0" \
-		"logic_addr=0x0\0" \
-		"cec_ac_wakeup=0\0" \
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=1\0" \
+        "cec_init= "\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "echo port_map=${port_map}; "\
+            "echo cec_fun=${cec_fun}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else if test ${edid_select} != 1111; then "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;fi; "\
+            "fi; "\
+        "\0"\
         "Irq_check_en=0\0"\
         "fs_type=""rootfstype=ramfs""\0"\
         "mem_size=2g\0"\
@@ -141,59 +156,76 @@
             "else fi;"\
             "\0"\
         "storeargs="\
-            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} mem_size=${mem_size} ; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} mem_size=${mem_size} ; "\
             "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
             "run cmdline_keys;"\
             "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn;uboot wake up "*/\
-                "echo powermode=${powermode}; "\
-                "if test ${powermode} = on; then "\
-                    /*"run try_auto_burn; "*/\
-                "else if test ${powermode} = standby; then "\
-					"echo cec_ac_wakeup=${cec_ac_wakeup}; "\
-					"if test ${cec_ac_wakeup} = 1; then "\
-						"cec ${logic_addr} ${cec_fun}; "\
-						"if test ${edid_select} = 1111; then "\
-							"hdmirx init ${port_map} ${edid_20_dir}; "\
-						"else if test ${edid_select} != 1111; then "\
-							"hdmirx init ${port_map} ${edid_14_dir}; "\
-						"fi;fi;"\
-					"fi;"\
-                    "systemoff; "\
-                "else if test ${powermode} = last; then "\
-                    "echo suspend=${suspend}; "\
-                    "if test ${suspend} = off; then "\
-                        /*"run try_auto_burn; "*/\
-                    "else if test ${suspend} = on; then "\
-						"echo cec_ac_wakeup=${cec_ac_wakeup}; "\
-						"if test ${cec_ac_wakeup} = 1; then "\
-							"cec ${logic_addr} ${cec_fun}; "\
-							"if test ${edid_select} = 1111; then "\
-								"hdmirx init ${port_map} ${edid_20_dir}; "\
-							"else if test ${edid_select} != 1111; then "\
-								"hdmirx init ${port_map} ${edid_14_dir}; "\
-							"fi;fi;"\
-						"fi;"\
-                        "systemoff; "\
-                    "else if test ${suspend} = shutdown; then "\
-                         "systemoff; "\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
                     "fi; fi; fi; "\
-                "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
             "\0" \
         "reset_suspend="\
-            "if test ${suspend} = on || test ${suspend} = shutdown; then "\
-                "setenv ""suspend off"";"\
-                "saveenv;"\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
             "fi;"\
             "\0" \
         "storeboot="\
@@ -275,15 +307,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
@@ -300,14 +337,20 @@
                     "else if test ${suspend} = on; then "\
                         "echo not init_display; "\
                     "else if test ${suspend} = shutdown; then "\
-                         "echo not init_display; "\
+                        "echo not init_display; "\
                     "fi; fi; fi; "\
                 "else "\
                     "run init_display; "\
                 "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
             "else "\
                 "run init_display; "\
-            "fi; "\
+            "fi;fi; "\
             "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
diff --git a/board/amlogic/configs/tl1_x301_v1.h b/board/amlogic/configs/tl1_x301_v1.h
index f5f5d73..bf6d55f 100644
--- a/board/amlogic/configs/tl1_x301_v1.h
+++ b/board/amlogic/configs/tl1_x301_v1.h
@@ -124,13 +124,28 @@
         "boot_part=boot\0"\
         "suspend=off\0"\
         "powermode=on\0"\
-		"edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
-		"edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
-		"edid_select=0\0" \
-		"port_map=0x4321\0" \
-		"cec_fun=0x2F\0" \
-		"logic_addr=0x0\0" \
-		"cec_ac_wakeup=0\0" \
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=1\0" \
+        "cec_init= "\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "echo port_map=${port_map}; "\
+            "echo cec_fun=${cec_fun}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else"\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi; "\
+            "fi; "\
+        "\0"\
         "Irq_check_en=0\0"\
         "fs_type=""rootfstype=ramfs""\0"\
         "mem_size=2g\0"\
@@ -144,59 +159,76 @@
             "else fi;"\
             "\0"\
         "storeargs="\
-            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} mem_size=${mem_size} irq_check_en=${Irq_check_en} ; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} mem_size=${mem_size} irq_check_en=${Irq_check_en} ; "\
             "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
             "run cmdline_keys;"\
             "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn;uboot wake up "*/\
-                "echo powermode=${powermode}; "\
-                "if test ${powermode} = on; then "\
-                    /*"run try_auto_burn; "*/\
-                "else if test ${powermode} = standby; then "\
-					"echo cec_ac_wakeup=${cec_ac_wakeup}; "\
-					"if test ${cec_ac_wakeup} = 1; then "\
-						"cec ${logic_addr} ${cec_fun}; "\
-						"if test ${edid_select} = 1111; then "\
-							"hdmirx init ${port_map} ${edid_20_dir}; "\
-						"else if test ${edid_select} != 1111; then "\
-							"hdmirx init ${port_map} ${edid_14_dir}; "\
-						"fi;fi;"\
-					"fi;"\
-                    "systemoff; "\
-                "else if test ${powermode} = last; then "\
-                    "echo suspend=${suspend}; "\
-                    "if test ${suspend} = off; then "\
-                        /*"run try_auto_burn; "*/\
-                    "else if test ${suspend} = on; then "\
-						"echo cec_ac_wakeup=${cec_ac_wakeup}; "\
-						"if test ${cec_ac_wakeup} = 1; then "\
-							"cec ${logic_addr} ${cec_fun}; "\
-							"if test ${edid_select} = 1111; then "\
-								"hdmirx init ${port_map} ${edid_20_dir}; "\
-							"else if test ${edid_select} != 1111; then "\
-								"hdmirx init ${port_map} ${edid_14_dir}; "\
-							"fi;fi;"\
-						"fi;"\
-                        "systemoff; "\
-                    "else if test ${suspend} = shutdown; then "\
-                        "systemoff; "\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
                     "fi; fi; fi; "\
-                "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
             "\0" \
         "reset_suspend="\
-            "if test ${suspend} = on || test ${suspend} = shutdown; then "\
-                "setenv ""suspend off"";"\
-                "saveenv;"\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
             "fi;"\
             "\0" \
         "storeboot="\
@@ -278,15 +310,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
@@ -308,9 +345,15 @@
                 "else "\
                     "run init_display; "\
                 "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
             "else "\
                 "run init_display; "\
-            "fi; "\
+            "fi;fi; "\
             "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
@@ -327,6 +370,11 @@
                 "if keyman read deviceid ${loadaddr} str; then "\
                     "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
                 "fi;"\
+                "if keyman read oemkey ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=${oemkey};"\
+                "else "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=ATV00104319;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "bcb_cmd="\
diff --git a/board/amlogic/configs/tm2_t962e2_ab311_v1.h b/board/amlogic/configs/tm2_t962e2_ab311_v1.h
index 8f79691..be1b362 100644
--- a/board/amlogic/configs/tm2_t962e2_ab311_v1.h
+++ b/board/amlogic/configs/tm2_t962e2_ab311_v1.h
@@ -125,6 +125,15 @@
         "boot_part=boot\0"\
         "suspend=off\0"\
         "powermode=on\0"\
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=0\0" \
         "Irq_check_en=0\0"\
         "fs_type=""rootfstype=ramfs""\0"\
         "initargs="\
@@ -138,41 +147,87 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
+        "cec_init="\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn;uboot wake up "*/\
-                "echo powermode=${powermode}; "\
-                "if test ${powermode} = on; then "\
-                    /*"run try_auto_burn; "*/\
-                "else if test ${powermode} = standby; then "\
-                    "systemoff; "\
-                "else if test ${powermode} = last; then "\
-                    "echo suspend=${suspend}; "\
-                    "if test ${suspend} = off; then "\
-                        /*"run try_auto_burn; "*/\
-                    "else if test ${suspend} = on; then "\
-                        "systemoff; "\
-                    "else if test ${suspend} = shutdown; then "\
-                        "systemoff; "\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
                     "fi; fi; fi; "\
-                "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
             "\0" \
         "reset_suspend="\
-            "if test ${suspend} = on || test ${suspend} = shutdown; then "\
-                "setenv ""suspend off"";"\
-                "saveenv;"\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
             "fi;"\
             "\0" \
         "storeboot="\
@@ -180,8 +235,9 @@
             "get_system_as_root_mode;"\
             "echo system_mode: ${system_mode};"\
             "if test ${system_mode} = 1; then "\
-                    "setenv fs_type ""ro rootwait skip_initramfs"";"\
-                    "run storeargs;"\
+                "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+            "else "\
+                "setenv bootargs ${bootargs} $(fs_type);"\
             "fi;"\
             "get_valid_slot;"\
             "get_avb_mode;"\
@@ -251,15 +307,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
@@ -281,9 +342,15 @@
                 "else "\
                     "run init_display; "\
                 "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
             "else "\
                 "run init_display; "\
-            "fi; "\
+            "fi;fi; "\
             "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
@@ -300,6 +367,11 @@
                 "if keyman read deviceid ${loadaddr} str; then "\
                     "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
                 "fi;"\
+                "if keyman read oemkey ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=${oemkey};"\
+                "else "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=ATV00104319;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "bcb_cmd="\
diff --git a/board/amlogic/configs/tm2_t962e2_ab319_v1.h b/board/amlogic/configs/tm2_t962e2_ab319_v1.h
index dccb6d6..1786685 100644
--- a/board/amlogic/configs/tm2_t962e2_ab319_v1.h
+++ b/board/amlogic/configs/tm2_t962e2_ab319_v1.h
@@ -122,6 +122,17 @@
         "video_reverse=0\0"\
         "active_slot=normal\0"\
         "boot_part=boot\0"\
+        "suspend=off\0"\
+        "powermode=on\0"\
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=0\0" \
         "fs_type=""rootfstype=ramfs""\0"\
         "initargs="\
             "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 printk.devkmsg=on ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
@@ -134,29 +145,97 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	    "setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
+        "cec_init="\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn; "*/\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
+                    "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
+            "\0" \
+        "reset_suspend="\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
+            "fi;"\
             "\0" \
         "storeboot="\
             "boot_cooling;"\
             "get_system_as_root_mode;"\
             "echo system_mode: ${system_mode};"\
             "if test ${system_mode} = 1; then "\
-                    "setenv fs_type ""ro rootwait skip_initramfs"";"\
-                    "run storeargs;"\
+                "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+            "else "\
+                "setenv bootargs ${bootargs} $(fs_type);"\
             "fi;"\
             "get_valid_slot;"\
             "get_avb_mode;"\
@@ -226,20 +305,51 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
             "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
             "\0"\
+        "check_display="\
+            "if test ${reboot_mode} = cold_boot; then "\
+                "if test ${powermode} = standby; then "\
+                    "echo not init_display; "\
+                "else if test ${powermode} = last; then "\
+                    "echo suspend=${suspend}; "\
+                    "if test ${suspend} = off; then "\
+                        "run init_display; "\
+                    "else if test ${suspend} = on; then "\
+                        "echo not init_display; "\
+                    "else if test ${suspend} = shutdown; then "\
+                        "echo not init_display; "\
+                    "fi; fi; fi; "\
+                "else "\
+                    "run init_display; "\
+                "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
+            "else "\
+                "run init_display; "\
+            "fi;fi; "\
+            "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
                 "if keyman read usid ${loadaddr} str; then "\
@@ -279,10 +389,12 @@
 	"run bcb_cmd; "\
 	"run factory_reset_poweroff_protect;"\
 	"run upgrade_check;"\
-	"run init_display;"\
+	/* "run init_display;"\ */\
+	"run check_display;"\
 	"run storeargs;"\
 	"bcb uboot-command;"\
-	"run switch_bootmode;"
+	"run switch_bootmode;"\
+	"run reset_suspend;"
 
 #define CONFIG_BOOTCOMMAND "run storeboot"
 
diff --git a/board/amlogic/configs/tm2_t962x3_ab301_v1.h b/board/amlogic/configs/tm2_t962x3_ab301_v1.h
index 1d9cd74..df81b42 100644
--- a/board/amlogic/configs/tm2_t962x3_ab301_v1.h
+++ b/board/amlogic/configs/tm2_t962x3_ab301_v1.h
@@ -125,6 +125,15 @@
         "boot_part=boot\0"\
         "suspend=off\0"\
         "powermode=on\0"\
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=0\0" \
         "Irq_check_en=0\0"\
         "fs_type=""rootfstype=ramfs""\0"\
         "initargs="\
@@ -137,41 +146,87 @@
             "else fi;"\
             "\0"\
         "storeargs="\
-            "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
             "run cmdline_keys;"\
             "\0"\
+        "cec_init="\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn;uboot wake up "*/\
-                "echo powermode=${powermode}; "\
-                "if test ${powermode} = on; then "\
-                    /*"run try_auto_burn; "*/\
-                "else if test ${powermode} = standby; then "\
-                    "systemoff; "\
-                "else if test ${powermode} = last; then "\
-                    "echo suspend=${suspend}; "\
-                    "if test ${suspend} = off; then "\
-                        /*"run try_auto_burn; "*/\
-                    "else if test ${suspend} = on; then "\
-                        "systemoff; "\
-                    "else if test ${suspend} = shutdown; then "\
-                        "systemoff; "\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
                     "fi; fi; fi; "\
-                "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
             "\0" \
         "reset_suspend="\
-            "if test ${suspend} = on || test ${suspend} = shutdown; then "\
-                "setenv ""suspend off"";"\
-                "saveenv;"\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
             "fi;"\
             "\0" \
         "storeboot="\
@@ -179,8 +234,9 @@
             "get_system_as_root_mode;"\
             "echo system_mode: ${system_mode};"\
             "if test ${system_mode} = 1; then "\
-                    "setenv fs_type ""ro rootwait skip_initramfs"";"\
-                    "run storeargs;"\
+                "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+            "else "\
+                "setenv bootargs ${bootargs} $(fs_type);"\
             "fi;"\
             "get_valid_slot;"\
             "get_avb_mode;"\
@@ -250,15 +306,20 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
@@ -280,9 +341,15 @@
                 "else "\
                     "run init_display; "\
                 "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
             "else "\
                 "run init_display; "\
-            "fi; "\
+            "fi;fi; "\
             "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
diff --git a/board/amlogic/configs/tm2_t962x3_ab309_v1.h b/board/amlogic/configs/tm2_t962x3_ab309_v1.h
index e7473e4..617cf26 100644
--- a/board/amlogic/configs/tm2_t962x3_ab309_v1.h
+++ b/board/amlogic/configs/tm2_t962x3_ab309_v1.h
@@ -122,6 +122,17 @@
         "video_reverse=0\0"\
         "active_slot=normal\0"\
         "boot_part=boot\0"\
+        "suspend=off\0"\
+        "powermode=on\0"\
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=0\0" \
         "fs_type=""rootfstype=ramfs""\0"\
         "initargs="\
             "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 printk.devkmsg=on ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
@@ -133,29 +144,97 @@
             "else fi;"\
             "\0"\
         "storeargs="\
-            "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
             "run cmdline_keys;"\
             "\0"\
+        "cec_init="\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn; "*/\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
+                    "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
+            "\0" \
+        "reset_suspend="\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
+            "fi;"\
             "\0" \
         "storeboot="\
             "boot_cooling;"\
             "get_system_as_root_mode;"\
             "echo system_mode: ${system_mode};"\
             "if test ${system_mode} = 1; then "\
-                    "setenv fs_type ""ro rootwait skip_initramfs"";"\
-                    "run storeargs;"\
+                "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+            "else "\
+                "setenv bootargs ${bootargs} $(fs_type);"\
             "fi;"\
             "get_valid_slot;"\
             "get_avb_mode;"\
@@ -225,20 +304,51 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
             "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
             "\0"\
+        "check_display="\
+            "if test ${reboot_mode} = cold_boot; then "\
+                "if test ${powermode} = standby; then "\
+                    "echo not init_display; "\
+                "else if test ${powermode} = last; then "\
+                    "echo suspend=${suspend}; "\
+                    "if test ${suspend} = off; then "\
+                        "run init_display; "\
+                    "else if test ${suspend} = on; then "\
+                        "echo not init_display; "\
+                    "else if test ${suspend} = shutdown; then "\
+                        "echo not init_display; "\
+                    "fi; fi; fi; "\
+                "else "\
+                    "run init_display; "\
+                "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
+            "else "\
+                "run init_display; "\
+            "fi;fi; "\
+            "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
                 "if keyman read usid ${loadaddr} str; then "\
@@ -278,10 +388,12 @@
 	"run bcb_cmd; "\
 	"run factory_reset_poweroff_protect;"\
 	"run upgrade_check;"\
-	"run init_display;"\
+	/* "run init_display;"\ */\
+	"run check_display;"\
 	"run storeargs;"\
 	"bcb uboot-command;"\
-	"run switch_bootmode;"
+	"run switch_bootmode;"\
+	"run reset_suspend;"
 
 #define CONFIG_BOOTCOMMAND "run storeboot"
 
diff --git a/board/amlogic/configs/tm2_t962x3_t312_v1.h b/board/amlogic/configs/tm2_t962x3_t312_v1.h
index d574c4a..be7d82d 100644
--- a/board/amlogic/configs/tm2_t962x3_t312_v1.h
+++ b/board/amlogic/configs/tm2_t962x3_t312_v1.h
@@ -123,7 +123,17 @@
         "video_reverse=0\0"\
         "active_slot=normal\0"\
         "boot_part=boot\0"\
+        "suspend=off\0"\
         "powermode=standby\0"\
+        "ffv_wake=off\0"\
+        "ffv_freeze=off\0"\
+        "edid_14_dir=/vendor/etc/tvconfig/hdmi/port_14.bin\0" \
+        "edid_20_dir=/vendor/etc/tvconfig/hdmi/port_20.bin\0" \
+        "edid_select=0\0" \
+        "port_map=0x4321\0" \
+        "cec_fun=0x2F\0" \
+        "logic_addr=0x0\0" \
+        "cec_ac_wakeup=0\0" \
         "Irq_check_en=0\0"\
         "fs_type=""rootfstype=ramfs""\0"\
         "initargs="\
@@ -137,35 +147,97 @@
             "\0"\
         "storeargs="\
             "get_bootloaderversion;" \
-            "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+            "setenv bootargs ${initargs} otg_device=${otg_device} logo=${display_layer},loaded,${fb_addr} powermode=${powermode} fb_width=${fb_width} fb_height=${fb_height} display_bpp=${display_bpp} outputmode=${outputmode} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
 	"setenv bootargs ${bootargs} androidboot.hardware=amlogic androidboot.bootloader=${bootloader_version} androidboot.build.expect.baseband=N/A;"\
             "run cmdline_keys;"\
             "\0"\
+        "cec_init="\
+            "echo cec_ac_wakeup=${cec_ac_wakeup}; "\
+            "if test ${cec_ac_wakeup} = 1; then "\
+                "cec ${logic_addr} ${cec_fun}; "\
+                "if test ${edid_select} = 1111; then "\
+                    "hdmirx init ${port_map} ${edid_20_dir}; "\
+                "else "\
+                    "hdmirx init ${port_map} ${edid_14_dir}; "\
+                "fi;"\
+            "fi;"\
+            "\0"\
+        "ffv_freeze_action="\
+            "run cec_init;"\
+            "setenv ffv_freeze on;"\
+            "setenv bootargs ${bootargs} ffv_freeze=on"\
+            "\0"\
+        "cold_boot_normal_check="\
+            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+            /*"run try_auto_burn;uboot wake up "*/\
+            "if test ${powermode} = on; then "\
+                /*"run try_auto_burn; "*/\
+            "else if test ${powermode} = standby; then "\
+                "run cec_init;"\
+                "systemoff; "\
+            "else if test ${powermode} = last; then "\
+               "echo suspend=${suspend}; "\
+                "if test ${suspend} = off; then "\
+                    /*"run try_auto_burn; "*/\
+                "else if test ${suspend} = on; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "else if test ${suspend} = shutdown; then "\
+                    "run cec_init;"\
+                    "systemoff; "\
+                "fi; fi; fi; "\
+            "fi; fi; fi; "\
+            "\0"\
         "switch_bootmode="\
             "get_rebootmode;"\
+            "setenv ffv_freeze off;"\
             "if test ${reboot_mode} = factory_reset; then "\
                     "run recovery_from_flash;"\
             "else if test ${reboot_mode} = update; then "\
                     "run update;"\
             "else if test ${reboot_mode} = cold_boot; then "\
-                /*"run try_auto_burn;uboot wake up "*/\
-                /*"echo powermode=${powermode}; "\
-                "if test ${powermode} = standby; then "\
-                    "setMtkBT;systemoff; "\
-                "else if test ${powermode} = on; then "\
-                    "run try_auto_burn; "\
-                "fi; fi; "\*/\
+                "echo cold boot: ffv_wake=${ffv_wake} powermode=${powermode} suspend=${suspend};"\
+                "if test ${ffv_wake} = on; then "\
+                    "if test ${powermode} = on; then "\
+                        "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                    "else if test ${powermode} = standby; then "\
+                        "run ffv_freeze_action; "\
+                    "else if test ${powermode} = last; then "\
+                        "if test ${suspend} = off; then "\
+                            "setenv bootargs ${bootargs} ffv_freeze=off; "\
+                        "else if test ${suspend} = on; then "\
+                            "run ffv_freeze_action; "\
+                        "else if test ${suspend} = shutdown; then "\
+                            "run ffv_freeze_action; "\
+                        "fi; fi; fi; "\
+                    "fi; fi; fi; "\
+                "else "\
+                    "run cold_boot_normal_check;"\
+                "fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "run ffv_freeze_action; "\
+                "fi; "\
             "else if test ${reboot_mode} = fastboot; then "\
                 "fastboot;"\
-            "fi;fi;fi;fi;"\
+            "fi;fi;fi;fi;fi;"\
+            "\0" \
+        "reset_suspend="\
+            "if test ${ffv_freeze} != on; then "\
+                "if test ${suspend} = on || test ${suspend} = shutdown; then "\
+                    "setenv ""suspend off"";"\
+                    "saveenv;"\
+                "fi;"\
+            "fi;"\
             "\0" \
         "storeboot="\
             "boot_cooling;"\
             "get_system_as_root_mode;"\
             "echo system_mode: ${system_mode};"\
             "if test ${system_mode} = 1; then "\
-                    "setenv fs_type ""ro rootwait skip_initramfs"";"\
-                    "run storeargs;"\
+                "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+            "else "\
+                "setenv bootargs ${bootargs} $(fs_type);"\
             "fi;"\
             "get_valid_slot;"\
             "get_avb_mode;"\
@@ -235,20 +307,51 @@
             "get_valid_slot;"\
             "echo active_slot: ${active_slot};"\
             "if test ${active_slot} = normal; then "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+                "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
                 "if itest ${upgrade_step} == 3; then "\
                     "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
                     "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
                 "else fi;"\
                 "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
             "else "\
-                "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
-                "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "if test ${partiton_mode} = normal; then "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+                "else "\
+                    "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+                    "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "init_display="\
             "lcd enable;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
             "\0"\
+        "check_display="\
+            "if test ${reboot_mode} = cold_boot; then "\
+                "if test ${powermode} = standby; then "\
+                    "echo not init_display; "\
+                "else if test ${powermode} = last; then "\
+                    "echo suspend=${suspend}; "\
+                    "if test ${suspend} = off; then "\
+                        "run init_display; "\
+                    "else if test ${suspend} = on; then "\
+                        "echo not init_display; "\
+                    "else if test ${suspend} = shutdown; then "\
+                        "echo not init_display; "\
+                    "fi; fi; fi; "\
+                "else "\
+                    "run init_display; "\
+                "fi; fi; "\
+            "else if test ${reboot_mode} = ffv_reboot; then "\
+                "if test ${ffv_wake} = on; then "\
+                    "echo ffv reboot no display; "\
+                "else "\
+                    "run init_display; "\
+                "fi; "\
+            "else "\
+                "run init_display; "\
+            "fi;fi; "\
+            "\0"\
         "cmdline_keys="\
             "if keyman init 0x1234; then "\
                 "if keyman read usid ${loadaddr} str; then "\
@@ -290,10 +393,12 @@
 	"run bcb_cmd; "\
 	"run factory_reset_poweroff_protect;"\
 	"run upgrade_check;"\
-	"run init_display;"\
+	/* "run init_display;"\ */\
+	"run check_display;"\
 	"run storeargs;"\
 	"bcb uboot-command;"\
-	"run switch_bootmode;"
+	"run switch_bootmode;"\
+	"run reset_suspend;"
 
 
 #define CONFIG_BOOTCOMMAND "run storeboot"
diff --git a/board/amlogic/configs/txl_p321_v1.h b/board/amlogic/configs/txl_p321_v1.h
index 8f8b8b2..74fa0a2 100644
--- a/board/amlogic/configs/txl_p321_v1.h
+++ b/board/amlogic/configs/txl_p321_v1.h
@@ -311,6 +311,11 @@
                 "if keyman read deviceid ${loadaddr} str; then "\
                     "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
                 "fi;"\
+                "if keyman read oemkey ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=${oemkey};"\
+                "else "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=ATV00104319;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "bcb_cmd="\
diff --git a/board/amlogic/configs/txlx_t962x_r311_v1.h b/board/amlogic/configs/txlx_t962x_r311_v1.h
index 4077ee1..81a49a7 100644
--- a/board/amlogic/configs/txlx_t962x_r311_v1.h
+++ b/board/amlogic/configs/txlx_t962x_r311_v1.h
@@ -311,6 +311,11 @@
                 "else "\
                     "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\
                 "fi;"\
+                "if keyman read oemkey ${loadaddr} str; then "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=${oemkey};"\
+                "else "\
+                    "setenv bootargs ${bootargs} androidboot.oem.key1=ATV00104319;"\
+                "fi;"\
             "fi;"\
             "\0"\
         "bcb_cmd="\
diff --git a/board/amlogic/defconfigs/sm1_elektra_v1_defconfig b/board/amlogic/defconfigs/sm1_elektra_v1_defconfig
new file mode 100644
index 0000000..da27a46
--- a/dev/null
+++ b/board/amlogic/defconfigs/sm1_elektra_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_SM1_ELEKTRA_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/g12a_skt_v1/avb2_kpub.c b/board/amlogic/g12a_skt_v1/avb2_kpub.c
new file mode 100644
index 0000000..ab76a1a
--- a/dev/null
+++ b/board/amlogic/g12a_skt_v1/avb2_kpub.c
@@ -0,0 +1,54 @@
+#ifdef CONFIG_AVB2_KPUB_VENDOR
+const char avb2_kpub_vendor[520] = {
+	0x00, 0x00, 0x08, 0x00, 0xc9, 0xd8, 0x7d, 0x7b, 0xc6, 0x55, 0x51,
+	0xdd, 0x32, 0x24, 0xa2, 0xe0, 0x0e, 0xbc, 0x7e, 0xfd, 0xbd, 0xa2,
+	0x53, 0x80, 0x58, 0x69, 0x7e, 0xf5, 0x4a, 0x40, 0x87, 0x95, 0x90,
+	0x54, 0x59, 0x3d, 0x55, 0xca, 0xff, 0x36, 0x34, 0x1a, 0xfa, 0xe1,
+	0xe0, 0x90, 0x2a, 0x1a, 0x32, 0x68, 0x5b, 0xf3, 0xdf, 0xad, 0x0b,
+	0xf9, 0xb1, 0xd0, 0xf7, 0xea, 0xab, 0x47, 0x1f, 0x76, 0xbe, 0x1b,
+	0x98, 0x4b, 0x67, 0xa3, 0x62, 0xfa, 0xdf, 0xe6, 0xb5, 0xf8, 0xee,
+	0x73, 0x16, 0x5f, 0xb8, 0xb1, 0x82, 0xde, 0x49, 0x89, 0xd5, 0x3d,
+	0xd7, 0xa8, 0x42, 0x99, 0x81, 0x75, 0xc8, 0xd8, 0x84, 0x7b, 0xbd,
+	0x54, 0xa8, 0x22, 0x64, 0x44, 0xbc, 0x34, 0x06, 0x10, 0x3c, 0x89,
+	0xc2, 0xd1, 0xf3, 0x2c, 0x03, 0x65, 0x91, 0xb1, 0xa0, 0xd1, 0xc8,
+	0x21, 0x56, 0x15, 0x99, 0x48, 0x20, 0x27, 0x74, 0xef, 0x01, 0x7a,
+	0x76, 0xa5, 0x0b, 0x6b, 0xfd, 0xe3, 0xfa, 0xed, 0x0d, 0xf9, 0x0f,
+	0x7a, 0x41, 0xfa, 0x76, 0x05, 0x37, 0x49, 0xfe, 0x34, 0x4f, 0x4b,
+	0x01, 0x49, 0xe4, 0x98, 0xf7, 0x89, 0x8e, 0xcd, 0x36, 0xaa, 0x39,
+	0x1d, 0xa9, 0x7d, 0x5d, 0x6b, 0x5a, 0x52, 0xd1, 0x75, 0x69, 0xa8,
+	0xdf, 0x7c, 0xde, 0x1c, 0x1b, 0xf9, 0xd9, 0x19, 0x5b, 0xb7, 0x47,
+	0x4c, 0xb9, 0x70, 0x2e, 0xad, 0xe5, 0xd6, 0x88, 0x7c, 0xed, 0x92,
+	0x6e, 0x46, 0x08, 0x10, 0xb5, 0x76, 0x03, 0x3e, 0x09, 0xac, 0x4d,
+	0xb6, 0x2c, 0xcd, 0x12, 0x00, 0xbd, 0xd4, 0xa7, 0x03, 0xd3, 0x1b,
+	0x91, 0x08, 0x23, 0x36, 0x5b, 0x11, 0xfe, 0xaf, 0x59, 0x69, 0xb3,
+	0x3c, 0x88, 0x24, 0x37, 0x2d, 0x61, 0xba, 0xc5, 0x99, 0x51, 0x18,
+	0x97, 0xf9, 0x23, 0x42, 0x96, 0x9f, 0x87, 0x2e, 0xcd, 0xb2, 0x4d,
+	0x5f, 0xa9, 0x24, 0xf2, 0x45, 0xda, 0xe2, 0x65, 0x26, 0x26, 0x4d,
+	0x1e, 0xfa, 0x3b, 0x53, 0xab, 0xc5, 0xd3, 0x79, 0x53, 0x2f, 0x66,
+	0xb8, 0x21, 0x94, 0x66, 0x9a, 0x93, 0x6f, 0x35, 0x26, 0x43, 0x8c,
+	0x8f, 0x96, 0xb9, 0xff, 0xac, 0xcd, 0xf4, 0x00, 0x6e, 0xbe, 0xb6,
+	0x73, 0x54, 0x84, 0x50, 0x85, 0x46, 0x53, 0xd5, 0xdd, 0x43, 0xfe,
+	0xb2, 0x6a, 0x78, 0x40, 0x79, 0x56, 0x9f, 0x86, 0xf3, 0xd3, 0x81,
+	0x3b, 0x3d, 0x40, 0x90, 0x35, 0x32, 0x9a, 0x51, 0x7f, 0xf8, 0xc3,
+	0x4b, 0xc7, 0xd6, 0xa1, 0xca, 0x30, 0xfb, 0x1b, 0xfd, 0x27, 0x0a,
+	0xb8, 0x64, 0x41, 0x34, 0xc1, 0x17, 0xde, 0xa1, 0x76, 0x9a, 0xeb,
+	0xcf, 0x0c, 0x50, 0xd9, 0x13, 0xf5, 0x0d, 0x0b, 0x2c, 0x99, 0x24,
+	0xcb, 0xb5, 0xb4, 0xf8, 0xc6, 0x0a, 0xd0, 0x26, 0xb1, 0x5b, 0xfd,
+	0x4d, 0x44, 0x66, 0x9d, 0xb0, 0x76, 0xaa, 0x79, 0x9d, 0xc0, 0x5c,
+	0x3b, 0x94, 0x36, 0xc1, 0x8f, 0xfe, 0xc9, 0xd2, 0x5a, 0x6a, 0xa0,
+	0x46, 0xe1, 0xa2, 0x8b, 0x2f, 0x51, 0x61, 0x51, 0xa3, 0x36, 0x91,
+	0x83, 0xb4, 0xfb, 0xcd, 0xa9, 0x40, 0x34, 0x46, 0x98, 0x8a, 0x1a,
+	0x91, 0xdf, 0xd9, 0x2c, 0x3a, 0xbf, 0x57, 0x3a, 0x46, 0x46, 0x20,
+	0xf2, 0xf0, 0xbc, 0x31, 0x5e, 0x29, 0xfe, 0x58, 0x90, 0x32, 0x5c,
+	0x66, 0x97, 0x99, 0x9a, 0x8e, 0x15, 0x23, 0xeb, 0xa9, 0x47, 0xd3,
+	0x63, 0xc6, 0x18, 0xbb, 0x8e, 0xd2, 0x20, 0x9f, 0x78, 0xaf, 0x71,
+	0xb3, 0x2e, 0x08, 0x89, 0xa1, 0xf1, 0x7d, 0xb1, 0x30, 0xa0, 0xe6,
+	0x1b, 0xbd, 0x6e, 0xc8, 0xf6, 0x33, 0xe1, 0xda, 0xb0, 0xbd, 0x16,
+	0x41, 0xfe, 0x07, 0x6f, 0x6e, 0x97, 0x8b, 0x6a, 0x33, 0xd2, 0xd7,
+	0x80, 0x03, 0x6a, 0x4d, 0xe7, 0x05, 0x82, 0x28, 0x1f, 0xef, 0x6a,
+	0xa9, 0x75, 0x7e, 0xe1, 0x4e, 0xe2, 0x95, 0x5b, 0x4f, 0xe6, 0xdc,
+	0x03, 0xb9, 0x81
+};
+
+const int avb2_kpub_vendor_len = sizeof(avb2_kpub_vendor) / sizeof(char);
+#endif /* CONFIG_AVB2_KPUB_VENDOR */
diff --git a/board/amlogic/g12a_skt_v1/config.mk b/board/amlogic/g12a_skt_v1/config.mk
new file mode 100644
index 0000000..7135e31
--- a/dev/null
+++ b/board/amlogic/g12a_skt_v1/config.mk
@@ -0,0 +1,8 @@
+ifdef CONFIG_AVB2_KPUB_DEFAULT_VENDOR
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_DEFAULT_VENDOR=1
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1
+endif
+
+ifdef CONFIG_AVB2_KPUB_VENDOR
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1
+endif
diff --git a/board/amlogic/gxl_p281_v1/firmware/ramdump.h b/board/amlogic/gxl_p281_v1/firmware/ramdump.h
index 882a6d2..19f95a1 100644
--- a/board/amlogic/gxl_p281_v1/firmware/ramdump.h
+++ b/board/amlogic/gxl_p281_v1/firmware/ramdump.h
@@ -61,7 +61,7 @@
  *                            |        |
  *     COMPRESS_START_ADDR -> +--------+
  */
-#define CONFIG_DDR_TOTAL_SIZE		(CONFIG_DDR_SIZE << 20)
+#define CONFIG_DDR_TOTAL_SIZE		(((unsigned int)CONFIG_DDR_SIZE) << 20)
 #define CONFIG_COMPRESSED_DATA_ADDR	(0x08000000)
 #define CONFIG_COMPRESSED_DATA_ADDR1	(0x08000000)
 
diff --git a/board/amlogic/sm1_elektra_v1/Kconfig b/board/amlogic/sm1_elektra_v1/Kconfig
new file mode 100644
index 0000000..6642186
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+	string
+	default "armv8"
+
+config SYS_BOARD
+	string
+	default "sm1_elektra_v1"
+
+config SYS_VENDOR
+	string
+	default "amlogic"
+
+config SYS_SOC
+	string
+	default "g12a"
+
+config SYS_CONFIG_NAME
+	default "sm1_elektra_v1"
+
+endif
diff --git a/board/amlogic/sm1_elektra_v1/Makefile b/board/amlogic/sm1_elektra_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_elektra_v1/README b/board/amlogic/sm1_elektra_v1/README
new file mode 100755
index 0000000..b95ca21
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/README
@@ -0,0 +1,2 @@
+README
+sm1 ac214 board share BSP code with g12a_u212_v1
diff --git a/board/amlogic/sm1_elektra_v1/aml-user-key.sig b/board/amlogic/sm1_elektra_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/aml-user-key.sig
@@ -0,0 +1,28 @@
+yÅtÃ}|4B²/iÖ»x¹nÜ:­fÙÞžpdd'üá¹àê¯të©NöZ	¿!˜�£òÄ@í	$ã×-È°°ÃÒš‰°2³{ñ^žs�Wµñí²`Dù‚#”@¸>…+äbŒqÏŽy”¡dàéÊÇ:“TŒ8Ο„
ÞÑÏOÍhõ‡ƒ!;ÇzŒ…|Û½×DÈ„ðdR!Q_IÙU6Âþw”>K–± ox"vpúŸ¾ÿ}d,6ψ‹®Q¦àËΆdÒY³<_Ö,R/‹sLÂ)e'isÖ­Hoë�y´æÄôU%ØaÊ>–1&ÜF÷Q#[µÚâ�»[Þº¦1rèƒBR»�PHÐÿ
+|âÝ‚hþ€Tsj»9ÍÏüæ}n
35f�å€3´‹æÀ?™sÜz«ýc.nÁ%ZêJ;ð.ÎŽÝ�8M×›E�@Ñ_¼ JãÏió
»î™
¬Ûንšæ£¿¨›fÙñ_³ÜñZ–qÍ"¬¿i@ctuçú…=ý~ˆ«tò�îä
+ÚIµ›ÊN¶©KÿåBšTqa­`ïoÔ¿Á¼D»ê±üÅ™°Mg™ªÎÎ>Q/¾ÕÊŸöz�xõ_Y;áçVyävé¿éÛÙù/ÛUµ)jpõÎÀ›ŠÁ`½¬½¹MY6U“ÓëÓؼÒS„)©OËvWz<Q¬„ǯßbõ¾›âï8ZX›Ã`ŸS€
ÇX–Q,Z—ܳc«WŸ‰ö÷j]-µ¼žÌ¹

+bÎt
+‹ã•!—ŠR
+¦âû^øúPD{<醎:™”ö÷
_‰Òð|àM̃$žì‹.<›
+Mî{µ]$:úžZäÏ)ôŽ;KrO
ÒTï©Ý\¾¸Ð>Oƒï@hæ¡i9Y¸
+~f8ÖVmJãaY›
Ðƶ‰‡À®:@O)ZS;Z�yu§ï9Tjï9¯´ÁvIŸ)òÔ<˜ê}
ÞG}c·ªW.òÕ
+xò˜–c	]‰«€.Oãy)4v¨õ*Ðu…nì&wÛ
Ì_§·7",@.QŪ9²(6¼­xdUL74¯õG’®uG^ì}âFVl%Ðí‚q} FVÿßÆÑ[_?uOs„„ü;�ÆTÍ—ŸífJÔOö$vH1
+»qòÁÓ]R„ê2¯ŠŒæøÁÝ�§¯Ú*µë"gd,ιü
+½¹&þ~¢¥ÄÇAñWì„<H/&BI�,~nˆµó²L°1yÙ³4CT·—€'ËjˆèB
Nøú=$»p='G½1Ê‹…-/¥Ñ¦óPÝ*
¨Cø‚dê“fØ’åfaΣo3•ÃÅÛ0 >ð~ÉÃ×là‰5ÂAM‹¼Í1utÑ"n¶7\òGåã/“^È­¾–ïž	Ah"ë2›>®beéÌ�wÏ·•Ô+š¦×Èg¸ÁßÕ€ü£–5�6wqš²hýŽÈÝ	Ú%¹aU&{'ËØ�œ!RX 
+Ú4%Ù^§Ùîêœ	Ãâr§˜IÆþÍfØ�¥½èí%ÑD†í;Ý3WK6øfáظ}BGüÖrüÏ
U´ƒû¼n#
j0^+!„Ÿ 
+ˆ²ú863*P¿��óÍ
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+QÌvÕp®îûîÃûë÷\t‚¤Z(§ˆ•F#O8F&Òý^ë6a>’ÃÎ{ .â„�™º¥¨{”¸^ëZ8.ë…Ì6KÙz²óš‘s'‹Ó]
BX>qK�j¡
C<…[Ö´`õ†b4ûŠ¨ÑH²¸-«7�O´rÆ'*ôãrpbÄlâ!ù¡ØG“�“4½å®î2l@¡ãôãœóä‹TØFûÂ
0Í2Xuf¼¨ê
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rSØ
Pë¶0ÂuƲÞI.svûz²ã…Ÿh´~»yéfSc®æ‘Ü”ª/íŽèiá=§u¾ÈŠú­•‚·²§š×íf\Ðzøzwuˈ)ŒÙ)8{Gy彋‘›8¸«?>Qfhà�Ò\¹
+=Ä[ácÙE¾ùw™®J[ðJžr
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§?Ê¢ù�
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?L[l¥Œ1Ê|«½ý5™^Ž�}w€¨cÛÆ^‰§ühD}Ü4ÕŠW�Ê7›?ß)?Ý
+Â	”+C“ØÕ¨ç…
+ ÓDž,#U 
+1®¯p ‚³Ã�¦Þ¦ÔR‰“àËÜG¦—å0º\#–IÚxybrØ?¬'	JPÆL¡C‡7L)úçŠ^ugdç	ͤ¼@&™[ÌBÄEýUo‡cßs³ E:ýŠOU
`V!ì)±ü}Ug¾M$äÁƒ
âÈcÊ]
+|¬$ô! O"QK
+q'¡îçü>õìo‹éÜdÚWÏ|û¤Œv¼K´f1$z‚îÓA×'ê<ªÊFxP�Tõѳç ‚³ÿpüëyy̽±[’Ëkq¦A<œˆ¸'¼BNFÇ‹‡#Ï0Û{ã¹¥ˆvÝxõãøÖ( º4ªiWA¹Ç“�ÍažJK¼êäÚ¶ëðØÕÆèªù†Z‰;Å�–;(YZË~ŒÀ@0†Å~<
+ÑÒ“Jÿƒ—–Øy8ýûÛ·Ûkx�
+²KÕ\E¦=ò
+
diff --git a/board/amlogic/sm1_elektra_v1/avb2_kpub.c b/board/amlogic/sm1_elektra_v1/avb2_kpub.c
new file mode 100644
index 0000000..0fdb300
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/avb2_kpub.c
@@ -0,0 +1,39 @@
+#ifdef CONFIG_AVB2_KPUB_VENDOR
+const char avb2_kpub_vendor[520] = {
+	0x00,0x00,0x08,0x00,0x91,0xc3,0xd6,0xad,0x8a,0xed,0x01,0x05,0x87,0x93,0x01,0x7d,
+	0x17,0x92,0xba,0x4d,0xa8,0x43,0xdb,0xd0,0x2c,0x2d,0x7f,0x91,0xd4,0x81,0x7e,0x2c,
+	0xdd,0xd2,0x21,0x53,0xc8,0xd8,0x95,0x77,0x9e,0xca,0x50,0x88,0xc2,0xcd,0xf3,0x76,
+	0xb8,0xc2,0x56,0x88,0xbb,0x4d,0x51,0x86,0xbb,0x80,0xaf,0xb5,0x4f,0x13,0x2d,0xf3,
+	0x09,0x05,0x66,0xae,0xb5,0x32,0x86,0xf9,0xeb,0x78,0x66,0x3e,0x5f,0x05,0x6c,0xd9,
+	0xf6,0xa9,0xbe,0x3e,0xfe,0x0f,0xc3,0xb1,0xa7,0x99,0xb2,0xdb,0xa9,0xb4,0x3f,0x4b,
+	0xf6,0x90,0x55,0xb8,0x8c,0x94,0xb2,0x49,0x7c,0x85,0x9d,0xc6,0x14,0xed,0xd7,0x9f,
+	0xd0,0x57,0x5b,0x5f,0x4d,0x02,0x15,0xd8,0x76,0x2e,0x6a,0x53,0x11,0xac,0x5a,0xc2,
+	0x27,0x45,0x2a,0xaa,0x01,0x22,0xf1,0x99,0x5f,0xf3,0x11,0x01,0x85,0x86,0x11,0x15,
+	0x87,0xd6,0x65,0x08,0x4c,0x98,0xba,0x4a,0x9a,0x55,0xa5,0x2e,0x9c,0x40,0xdd,0x91,
+	0xc0,0x00,0x05,0x1a,0x5c,0x69,0x3e,0xb5,0x40,0xec,0x30,0xe5,0x06,0xd9,0x7b,0xc4,
+	0xfc,0x2b,0xf1,0x60,0x57,0x1c,0xf5,0x33,0x3e,0x1e,0x17,0x5a,0x65,0xa6,0x14,0x9a,
+	0x6a,0x1f,0x78,0x4c,0x21,0xb9,0x59,0xcf,0x91,0x15,0xe6,0x79,0x41,0x80,0x13,0xb8,
+	0x1a,0xac,0x28,0xf5,0x3b,0xb7,0xd0,0x40,0x9a,0x7c,0x57,0x05,0xb8,0x40,0x1a,0x24,
+	0xa4,0x29,0x4a,0x48,0xf4,0xb9,0xfd,0x37,0x8d,0x8c,0x2e,0xf4,0x7d,0x47,0xe3,0x41,
+	0x02,0x20,0x99,0x0a,0x85,0x0e,0x28,0xf6,0x01,0x8a,0xba,0x9c,0xca,0x9e,0x3c,0x4d,
+	0x92,0x62,0x2e,0xe6,0x38,0x32,0x02,0xdb,0x62,0xbd,0x26,0x27,0x73,0x8a,0x83,0x15,
+	0x05,0xe9,0x0d,0x0c,0x2c,0xf3,0xeb,0x74,0xa7,0x1a,0xfc,0xa6,0xa0,0x2e,0x4a,0x23,
+	0x0e,0x7b,0x21,0x0d,0x31,0x66,0x7a,0x33,0xc4,0x58,0x94,0xb5,0x6f,0x9b,0x27,0x08,
+	0x8d,0x25,0x1f,0x79,0xab,0xec,0x74,0x55,0x35,0xfb,0x2d,0xe1,0xef,0x25,0xe0,0x87,
+	0xd2,0xe4,0x0c,0x57,0xd9,0x82,0xee,0x02,0x15,0xaf,0x8c,0x7a,0xa5,0xed,0x8b,0xe1,
+	0x77,0x2b,0x32,0xee,0xda,0x06,0x65,0xaa,0x50,0xc3,0xa4,0x44,0x8c,0xe8,0x2f,0x95,
+	0xe2,0x14,0xc0,0x8e,0x90,0x18,0x14,0x87,0x96,0xbd,0x8f,0x43,0xcc,0xc2,0x80,0x91,
+	0x45,0x93,0x77,0x40,0xa3,0x61,0x18,0xba,0x4d,0xe1,0x8c,0xd1,0x16,0x44,0x69,0x16,
+	0xf0,0x30,0x78,0x97,0x88,0xa3,0xdb,0x23,0x18,0x23,0xcc,0x38,0xbc,0x55,0x60,0xe6,
+	0x26,0x9c,0x75,0xf5,0x4b,0xe2,0x57,0xe0,0x22,0xd4,0x1b,0xe8,0xe6,0x12,0x24,0x96,
+	0x40,0x0c,0xe7,0x02,0xac,0x78,0x6a,0x47,0xe3,0x96,0x38,0xb7,0xed,0xca,0x31,0x4f,
+	0xfe,0x84,0x99,0x0b,0x74,0xfa,0x23,0x7d,0x05,0xfc,0xf2,0x01,0x01,0xbf,0xa2,0xd0,
+	0x54,0xa6,0xfa,0x7a,0x76,0xcb,0x27,0x2f,0xed,0x3d,0x06,0x83,0x16,0x50,0x0f,0x71,
+	0x12,0xc7,0x55,0x6c,0x9b,0x84,0x2d,0x5c,0x8c,0xb9,0x13,0x54,0xe8,0x2e,0xe9,0x97,
+	0x59,0x43,0x76,0xfb,0xec,0xa2,0xdf,0x45,0xcc,0xfb,0x07,0xea,0xa5,0xaa,0xe0,0x53,
+	0x4b,0xcd,0x74,0x6e,0x69,0x81,0x68,0x36,0x0d,0x1e,0xd2,0x19,0xc2,0xa3,0x22,0x45,
+	0xaa,0x27,0xe2,0xc9,0xd8,0x1d,0xbc,0xdc
+};
+
+const int avb2_kpub_vendor_len = sizeof(avb2_kpub_vendor) / sizeof(char);
+#endif /* CONFIG_AVB2_KPUB_VENDOR */
diff --git a/board/amlogic/sm1_elektra_v1/config.mk b/board/amlogic/sm1_elektra_v1/config.mk
new file mode 100644
index 0000000..7135e31
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/config.mk
@@ -0,0 +1,8 @@
+ifdef CONFIG_AVB2_KPUB_DEFAULT_VENDOR
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_DEFAULT_VENDOR=1
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1
+endif
+
+ifdef CONFIG_AVB2_KPUB_VENDOR
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1
+endif
diff --git a/board/amlogic/sm1_elektra_v1/eth_setup.c b/board/amlogic/sm1_elektra_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+	struct eth_board_socket* new_board;
+	new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+	if (NULL == new_board) return NULL;
+	if (name != NULL) {
+		new_board->name=(char*)malloc(strlen(name));
+		strncpy(new_board->name,name,strlen(name));
+	}else{
+		new_board->name="gxb";
+	}
+
+	new_board->eth_pinmux_setup=NULL ;
+	new_board->eth_clock_configure=NULL;
+	new_board->eth_hw_reset=NULL;
+	return new_board;
+}
+//pinmux   HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/sm1_elektra_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_elektra_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..ee20347
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,77 @@
+/*
+* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+* *
+This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+* *
+This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+* *
+You should have received a copy of the GNU General Public License along
+* with this program; if not, write to the Free Software Foundation, Inc.,
+* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+* *
+Description:
+*/
+
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+	{ 0x1c0000,  681},
+	{ 0x1b0001,  691},
+	{ 0x1a0002,  701},
+	{ 0x190003,  711},
+	{ 0x180004,  721},
+	{ 0x170005,  731},
+	{ 0x160006,  741},
+	{ 0x150007,  751},
+	{ 0x140008,  761},
+	{ 0x130009,  772},
+	{ 0x12000a,  782},
+	{ 0x11000b,  792},
+	{ 0x10000c,  802},
+	{ 0x0f000d,  812},
+	{ 0x0e000e,  822},
+	{ 0x0d000f,  832},
+	{ 0x0c0010,  842},
+	{ 0x0b0011,  852},
+	{ 0x0a0012,  862},
+	{ 0x090013,  872},
+	{ 0x080014,  882},
+	{ 0x070015,  892},
+	{ 0x060016,  902},
+	{ 0x050017,  912},
+	{ 0x040018,  922},
+	{ 0x030019,  932},
+	{ 0x02001a,  942},
+	{ 0x01001b,  952},
+	{ 0x00001c,  962}
+};
+
+static int pwm_voltage_table_ee_new[][2] = {
+	{ 0x120000,  700},
+	{ 0x110001,  710},
+	{ 0x100002,  720},
+	{ 0x0f0003,  730},
+	{ 0x0e0004,  740},
+	{ 0x0d0005,  750},
+	{ 0x0c0006,  760},
+	{ 0x0b0007,  770},
+	{ 0x0a0008,  780},
+	{ 0x090009,  790},
+	{ 0x08000a,  800},
+	{ 0x07000b,  810},
+	{ 0x06000c,  820},
+	{ 0x05000d,  830},
+	{ 0x04000e,  840},
+	{ 0x03000f,  850},
+	{ 0x020010,  860},
+	{ 0x010011,  870},
+	{ 0x000012,  880},
+};
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_elektra_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_elektra_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..07610bb
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+	unsigned int to, pwm_size = 0;
+	static int (*pwm_voltage_ee)[2];
+
+	/* BOOT_9 = H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+	/*set BOOT_9 input mode*/
+	writel((readl(PREG_PAD_GPIO0_EN_N) | 0x200), PREG_PAD_GPIO0_EN_N);
+	if (((readl(PREG_PAD_GPIO0_EN_N) & 0x200 ) == 0x200) &&
+			((readl(PREG_PAD_GPIO0_I) & 0x200 ) == 0x0)) {
+		uart_puts("use vddee new table!");
+		uart_puts("\n");
+		pwm_voltage_ee = pwm_voltage_table_ee_new;
+		pwm_size = ARRAY_SIZE(pwm_voltage_table_ee_new);
+	} else {
+		uart_puts("use vddee table!");
+		uart_puts("\n");
+		pwm_voltage_ee = pwm_voltage_table_ee;
+		pwm_size = ARRAY_SIZE(pwm_voltage_table_ee);
+	}
+
+	for (to = 0; to < pwm_size; to++) {
+		if (pwm_voltage_ee[to][1] >= target_voltage) {
+			break;
+		}
+	}
+
+	if (to >= pwm_size) {
+		to = pwm_size - 1;
+	}
+
+	writel(*(*(pwm_voltage_ee + to)), AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+	/*set gpioH_8 high to power off vcc 5v*/
+	writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+	writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+	/*set test_n low to power off vcck*/
+	writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+	writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+	writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+	/*step down ee voltage*/
+	set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+	/*step up ee voltage*/
+	set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+	/*set test_n low to power on vcck*/
+	writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+	writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+	writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+	_udelay(100);
+
+	/*set gpioH_8 low to power on vcc 5v*/
+	writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+	writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+	_udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+	struct wakeup_info *p = (struct wakeup_info *)response;
+	struct wakeup_gpio_info *gpio;
+	unsigned val;
+	unsigned i = 0;
+
+	p->status = RESPONSE_OK;
+	val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+	       BT_WAKEUP_SRC | CECB_WAKEUP_SRC);
+
+	p->sources = val;
+	p->gpio_info_count = i;
+
+/*bt wake host*/
+	gpio = &(p->gpio_info[i]);
+	gpio->wakeup_id = BT_WAKEUP_SRC;
+	gpio->gpio_in_idx = GPIOX_18;
+	gpio->gpio_in_ao = 0;
+	gpio->gpio_out_idx = -1;
+	gpio->gpio_out_ao = -1;
+	gpio->irq = IRQ_GPIO1_NUM;
+	gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+	p->gpio_info_count = ++i;
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+	int exit_reason = 0;
+	unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+	init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+		if (hdmi_cec_func_config & 0x1) {
+			remote_cec_hw_reset();
+			cec_node_init();
+		}
+#endif
+
+	do {
+		#ifdef CONFIG_CEC_WAKEUP
+		if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+			irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+			if (cec_power_on_check())
+				exit_reason = CEC_WAKEUP;
+		}
+		#endif
+		if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+			irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+			if (remote_detect_key())
+				exit_reason = REMOTE_WAKEUP;
+		}
+
+		if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+			irq[IRQ_VRTC] = 0xFFFFFFFF;
+			exit_reason = RTC_WAKEUP;
+		}
+
+		if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+			irq[IRQ_GPIO1] = 0xFFFFFFFF;
+			if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
+					&& (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
+					&& !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
+				exit_reason = BT_WAKEUP;
+		}
+
+		if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) {
+			irq[IRQ_ETH_PTM]= 0xFFFFFFFF;
+			exit_reason = ETH_PMT_WAKEUP;
+		}
+
+		if (exit_reason)
+			break;
+		else
+			__switch_idle_task();
+	} while (1);
+
+	return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+	pwr_op->power_off_at_24M = power_off_at_24M;
+	pwr_op->power_on_at_24M = power_on_at_24M;
+	pwr_op->detect_key = detect_key;
+	pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/sm1_elektra_v1/firmware/timing.c b/board/amlogic/sm1_elektra_v1/firmware/timing.c
new file mode 100644
index 0000000..f9a7fdc
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/firmware/timing.c
@@ -0,0 +1,582 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ *            #define CONFIG_DDR_CHL_AUTO					0xF
+ *            #define CONFIG_DDR0_16BIT_CH0					0x1
+ *            #define CONFIG_DDR0_16BIT_RANK01_CH0			0x4
+ *            #define CONFIG_DDR0_32BIT_RANK0_CH0			0x2
+ *            #define CONFIG_DDR0_32BIT_RANK01_CH01			0x3
+ *            #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0		0x5
+ *            #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0	0x6
+ * DramType:
+ *            #define CONFIG_DDR_TYPE_DDR3					0
+ *            #define CONFIG_DDR_TYPE_DDR4					1
+ *            #define CONFIG_DDR_TYPE_LPDDR4				2
+ *            #define CONFIG_DDR_TYPE_LPDDR3				3
+ * DRAMFreq:
+ *            {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+	/* g12a skt (u209) ddr4 */
+	.board_id				= CONFIG_BOARD_ID_MASK,
+	.version				= 1,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK0_CH0,
+	.DramType				= CONFIG_DDR_TYPE_DDR4,
+	.DRAMFreq				= {1200, 0, 0, 0},
+	.ddr_rfc_type			= DDR_RFC_TYPE_DDR4_2Gbx8,
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	//.imem_load_addr			= 0xFFFC0000, //sram
+	//.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming				= 1,
+	.HdtCtrl				= 0xC8,
+	.dram_cs0_size_MB		= 0xffff,
+	.dram_cs1_size_MB		= 0,
+	.training_SequenceCtrl	= {0x31f,0x61}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank	= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm				= 40,
+	.ac_drv_ohm				= 40,
+	.soc_data_drv_ohm_p		= 40,
+	.soc_data_drv_ohm_n		= 40,
+	.soc_data_odt_ohm_p		= 60,
+	.soc_data_odt_ohm_n		= 0,
+	.dram_data_drv_ohm		= 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+	.dram_data_odt_ohm		= 60, //60,
+	.dram_ac_odt_ohm		= 0,
+	.soc_clk_slew_rate		= 0x3ff,
+	.soc_cs_slew_rate		= 0x3ff,
+	.soc_ac_slew_rate		= 0x3ff,
+	.soc_data_slew_rate		= 0x2ff,
+	.vref_output_permil		= 500,
+	.vref_receiver_permil	= 0,//700,
+	.vref_dram_permil		= 0,//700,
+	//.vref_reverse			= 0,
+	//.ac_trace_delay		= {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+	.ac_trace_delay			= {32,32,32,32,32,32,32,32,32,32},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  7 << 5 |  8 << 10 |  9 << 15 | 10 << 20 | 11 << 25 ),
+							[1] = ( 12|  0 << 5 |  0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+							[2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 13 << 5 | 20 << 10 |  6 << 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap	= {00,00},
+	.ddr_lpddr34_dq_remap	= {00,00},
+	.dram_rtt_nom_wr_park	= {00,00},
+
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_func				= DDR_FUNC,
+	.magic					= DRAM_CFG_MAGIC,
+	.fast_boot[0]			= 1,
+},
+{
+	/* g12a skt (u209) ddr3 */
+	.board_id				= CONFIG_BOARD_ID_MASK,
+	.version				= 1,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
+	.DramType				= CONFIG_DDR_TYPE_DDR3,
+	.DRAMFreq				= {912, 0, 0, 0},
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	//.imem_load_addr			= 0xFFFC0000, //sram
+	//.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming				= 1,
+	.HdtCtrl				= 0xC8,
+	.dram_cs0_size_MB		= 0xffff,
+	.dram_cs1_size_MB		= 0xffff,
+	.training_SequenceCtrl	= {0x31f,0}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank	= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm				= 40,
+	.ac_drv_ohm				= 40,
+	.soc_data_drv_ohm_p		= 34,
+	.soc_data_drv_ohm_n		= 34,
+	.soc_data_odt_ohm_p		= 60, //48,
+	.soc_data_odt_ohm_n		= 0,
+	.dram_data_drv_ohm		= 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+	.dram_data_odt_ohm		= 60,
+	.dram_ac_odt_ohm		= 0,
+	.soc_clk_slew_rate		= 0x300,
+	.soc_cs_slew_rate		= 0x300,
+	.soc_ac_slew_rate		= 0x300,
+	.soc_data_slew_rate		= 0x200,
+	.vref_output_permil		= 500,
+	.vref_receiver_permil	= 500, //700,
+	.vref_dram_permil		= 500, //700,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {32,32,32,32,32,32,32,32,32,32},
+	//{00,00},
+	.ac_pinmux				= {00,00},
+#if 1
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  7 << 5 |  8 << 10 |  9 << 15 | 10 << 20 | 11 << 25 ),
+							[1] = ( 12|  0 << 5 |  0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+							[2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 13 << 5 | 20 << 10 |  6 << 15 |  0 << 20 |  0 << 25 ),
+	},
+#else
+	//16bit
+	.ddr_dmc_remap			= {
+							[0] = ( 0 |  5 << 5 |  6<< 10 |  7 << 15 | 8 << 20 | 9 << 25 ),
+							[1] = ( 10|  0 << 5 |  0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+							[2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+							[3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+							[4] = ( 29| 11<< 5 | 12 << 10 |  13<< 15 |  0 << 20 |  0 << 25 ),
+	},
+#endif
+	.ddr_lpddr34_ca_remap	= {00,00},
+	.ddr_lpddr34_dq_remap	= {00,00},
+	.dram_rtt_nom_wr_park	= {00,00},
+
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_func				= DDR_FUNC,
+	.magic					= DRAM_CFG_MAGIC,
+	.fast_boot[0]			= 1,
+},
+{
+	/* g12a skt (u209) lpddr4 */
+	.board_id				= CONFIG_BOARD_ID_MASK,
+	.version				= 1,
+	//.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH01,
+	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_8Gbx1,
+	.DramType				= CONFIG_DDR_TYPE_LPDDR4,
+	.DRAMFreq				= {1392, 0, 0, 0},
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	//.imem_load_addr			= 0xFFFC0000, //sram
+	//.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming				= 0,
+	.HdtCtrl				= 0xa,
+	.dram_cs0_size_MB		= 0xffff,//1024,
+	.dram_cs1_size_MB		= 0xffff,//1024,
+	.training_SequenceCtrl	= {0x131f,0x61}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank	= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm				= 40,
+	.ac_drv_ohm				= 40,
+	.soc_data_drv_ohm_p		= 40,
+	.soc_data_drv_ohm_n		= 40,
+	.soc_data_odt_ohm_p		= 0,
+	.soc_data_odt_ohm_n		= 120,
+	.dram_data_drv_ohm		= 40, //lpddr4 sdram only240/1-6
+	.dram_data_odt_ohm		= 120,
+	.dram_ac_odt_ohm		= 120,
+	.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq     0 2/5 vddq
+	.soc_clk_slew_rate		= 0x3ff,//0x253,
+	.soc_cs_slew_rate		= 0x100,//0x253,
+	.soc_ac_slew_rate		= 0x100,//0x253,
+	.soc_data_slew_rate		= 0x1ff,
+	.vref_output_permil		= 350,//200,
+	.vref_receiver_permil	= 0,
+	.vref_dram_permil		= 0,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {00,0x0,0,0,0,0,0x0,00},
+	.ac_pinmux				= {00,00},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  6 << 5 |  7 << 10 |  8<< 15 | 9<< 20 | 10 << 25 ),
+							[1] = ( 11|  0 << 5 |  0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+							[2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 12 << 5 | 13 << 10 |  14<< 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap	= {00,00},
+	.ddr_lpddr34_dq_remap	= {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+	.dram_rtt_nom_wr_park	= {00,00},
+
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_func				= DDR_FUNC,
+	.magic					= DRAM_CFG_MAGIC,
+	.diagnose				= CONFIG_DIAGNOSE_DISABLE,
+	.fast_boot[0]			= 1,
+},
+{
+	/* g12a Y2 dongle */
+	.board_id				= CONFIG_BOARD_ID_MASK,
+	.version				= 1,
+	//.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK0_CH01,
+	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_8Gbx1,
+	.DramType				= CONFIG_DDR_TYPE_LPDDR4,
+	.DRAMFreq				= {1392, 0, 0, 0},
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	//.imem_load_addr			= 0xFFFC0000, //sram
+	//.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming				= 0,
+	.HdtCtrl				= 0xa,
+	.dram_cs0_size_MB		= 0xffff,//1024,
+	.dram_cs1_size_MB		= 0,//1024,
+	.training_SequenceCtrl	= {0x131f,0x61}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank	= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm				= 40,
+	.ac_drv_ohm				= 40,
+	.soc_data_drv_ohm_p		= 40,
+	.soc_data_drv_ohm_n		= 40,
+	.soc_data_odt_ohm_p		= 0,
+	.soc_data_odt_ohm_n		= 120,
+	.dram_data_drv_ohm		= 40, //lpddr4 sdram only240/1-6
+	.dram_data_odt_ohm		= 120,
+	.dram_ac_odt_ohm		= 120,
+	.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq     0 2/5 vddq
+	.soc_clk_slew_rate		= 0x3ff,//0x253,
+	.soc_cs_slew_rate		= 0x100,//0x253,
+	.soc_ac_slew_rate		= 0x100,//0x253,
+	.soc_data_slew_rate		= 0x1ff,
+	.vref_output_permil		= 350,//200,
+	.vref_receiver_permil	= 0,
+	.vref_dram_permil		= 0,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {00,0x0,0,0,0,0,0x0,00},
+	.ac_pinmux				= {00,00},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  6 << 5 |  7 << 10 |  8<< 15 | 9<< 20 | 10 << 25 ),
+							[1] = ( 11|  0 << 5 |  0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+							[2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+							[4] = ( 30| 12 << 5 | 13 << 10 |  14<< 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap	= {00,00},
+	.ddr_lpddr34_dq_remap	= {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+	.dram_rtt_nom_wr_park	= {00,00},
+	/* pll ssc config:
+	 *
+	 *   pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+	 *      ppm = strength * 500
+	 *      mode: 0=center, 1=up, 2=down
+	 *
+	 *   eg:
+	 *     1. config 1000ppm center ss. then mode=0, strength=2
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+	 *     2. config 3000ppm down ss. then mode=2, strength=6
+	 *        .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+	 */
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.ddr_func				= DDR_FUNC,
+	.magic					= DRAM_CFG_MAGIC,
+	.fast_boot[0]			= 1,
+},
+#if 0
+{
+	/* lpddr3 */
+	.board_id				= CONFIG_BOARD_ID_MASK,
+	.version				= 1,
+	//.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
+	.dram_rank_config		= CONFIG_DDR0_32BIT_RANK01_CH0,
+	.ddr_rfc_type			= DDR_RFC_TYPE_LPDDR4_4Gbx1,
+	.DramType				= CONFIG_DDR_TYPE_LPDDR3,
+	.DRAMFreq				= {600, 0, 0, 0},
+	.ddr_base_addr			= CFG_DDR_BASE_ADDR,
+	.ddr_start_offset		= CFG_DDR_START_OFFSET,
+	//.imem_load_addr			= 0xFFFC0000, //sram
+	//.dmem_load_size			= 0x1000, //4K
+
+	.DisabledDbyte			= 0xf0,
+	.Is2Ttiming				= 0,
+	.HdtCtrl				= 0xa,//0xa,
+	.dram_cs0_size_MB		= 0xffff,//1024,
+	.dram_cs1_size_MB		= 0xffff,//1024,
+	.training_SequenceCtrl	= {0x131f,0}, //ddr3 0x21f 0x31f
+	.phy_odt_config_rank	= {0x23,0x13}, //use 0x23 0x13  compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+	.dfi_odt_config			= 0x0d0d,  //use 0d0d compatibility with 1rank and 2rank  //0808
+	.PllBypassEn			= 0, //bit0-ps0,bit1-ps1
+	.ddr_rdbi_wr_enable		= 0,
+	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+	.clk_drv_ohm			= 40,
+	.cs_drv_ohm				= 40,
+	.ac_drv_ohm				= 40,
+	.soc_data_drv_ohm_p		= 40,
+	.soc_data_drv_ohm_n		= 40,
+	.soc_data_odt_ohm_p		= 60,
+	.soc_data_odt_ohm_n		= 0,
+	.dram_data_drv_ohm		= 30, //
+	.dram_data_odt_ohm		= 120,
+	.dram_ac_odt_ohm		= 0,
+	.soc_clk_slew_rate		= 0x3ff,//0x253,
+	.soc_cs_slew_rate		= 0x3ff,//0x253,
+	.soc_ac_slew_rate		= 0x3ff,//0x253,
+	.soc_data_slew_rate		= 0x2ff,
+	.vref_output_permil		= 800,//200,
+	.vref_receiver_permil	= 700,//875,  //700 for drv 40 odt 60 is better ,why?
+	.vref_dram_permil		= 500,//875,
+	//.vref_reverse			= 0,
+	.ac_trace_delay			= {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+	.ac_pinmux				= {00,00},
+	.ddr_dmc_remap			= {
+							[0] = ( 5 |  6 << 5 |  7 << 10 |  8<< 15 | 9<< 20 | 10 << 25 ),
+							[1] = ( 11|  29 << 5 |  0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+							[2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+							[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+							[4] = ( 31| 12 << 5 | 13 << 10 |  14<< 15 |  0 << 20 |  0 << 25 ),
+	},
+	.ddr_lpddr34_ca_remap	= {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+	.ddr_lpddr34_dq_remap	= {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+	//{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+	.dram_rtt_nom_wr_park	= {00,00},
+	.ddr_func				= DDR_FUNC,
+	.magic					= DRAM_CFG_MAGIC,
+	.diagnose				= CONFIG_DIAGNOSE_DISABLE,
+},
+#endif
+};
+
+pll_set_t __pll_setting = {
+	.cpu_clk				= CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+	.pxp					= 1,
+#else
+	.pxp					= 0,
+#endif
+	.spi_ctrl				= 0,
+	.lCustomerID			= CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+	.debug_mode				= CONFIG_DEBUG_MODE,
+	.ddr_clk_debug			= CONFIG_DDR_CLK_DEBUG,
+	.cpu_clk_debug			= CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+	/* demo, user defined override register */
+	{0xaabbccdd, 0, 0, 0, 0, 0},
+	{0x11223344, 0, 0, 0, 0, 0},
+	{0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL				CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL				CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if   (VCCK_VAL == 800)
+	#define VCCK_VAL_REG	0x00150007
+#elif (VCCK_VAL == 810)
+	#define VCCK_VAL_REG	0x00140008
+#elif (VCCK_VAL == 820)
+	#define VCCK_VAL_REG	0x00130009
+#elif (VCCK_VAL == 830)
+	#define VCCK_VAL_REG	0x0012000a
+#elif (VCCK_VAL == 840)
+	#define VCCK_VAL_REG	0x0011000b
+#elif (VCCK_VAL == 850)
+	#define VCCK_VAL_REG	0x0010000c
+#elif (VCCK_VAL == 860)
+	#define VCCK_VAL_REG	0x000f000d
+#elif (VCCK_VAL == 870)
+	#define VCCK_VAL_REG	0x000e000e
+#elif (VCCK_VAL == 880)
+	#define VCCK_VAL_REG	0x000d000f
+#elif (VCCK_VAL == 890)
+	#define VCCK_VAL_REG	0x000c0010
+#elif (VCCK_VAL == 900)
+	#define VCCK_VAL_REG	0x000b0011
+#elif (VCCK_VAL == 910)
+	#define VCCK_VAL_REG	0x000a0012
+#elif (VCCK_VAL == 920)
+	#define VCCK_VAL_REG	0x00090013
+#elif (VCCK_VAL == 930)
+	#define VCCK_VAL_REG	0x00080014
+#elif (VCCK_VAL == 940)
+	#define VCCK_VAL_REG	0x00070015
+#elif (VCCK_VAL == 950)
+	#define VCCK_VAL_REG	0x00060016
+#elif (VCCK_VAL == 960)
+	#define VCCK_VAL_REG	0x00050017
+#elif (VCCK_VAL == 970)
+	#define VCCK_VAL_REG	0x00040018
+#elif (VCCK_VAL == 980)
+	#define VCCK_VAL_REG	0x00030019
+#elif (VCCK_VAL == 990)
+	#define VCCK_VAL_REG	0x0002001a
+#elif (VCCK_VAL == 1000)
+	#define VCCK_VAL_REG	0x0001001b
+#elif (VCCK_VAL == 1010)
+	#define VCCK_VAL_REG	0x0000001c
+#else
+	#error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG0: VDDEE PWM table  0.67v-0.97v*/
+/* VDDEE_VAL_REG1: VDDEE PWM table  0.69v-0.89v*/
+#if    (VDDEE_VAL == 800)
+	#define VDDEE_VAL_REG0	0x0010000c
+	#define VDDEE_VAL_REG1	0x0008000a
+#elif (VDDEE_VAL == 810)
+	#define VDDEE_VAL_REG0	0x000f000d
+	#define VDDEE_VAL_REG1	0x0007000b
+#elif (VDDEE_VAL == 820)
+	#define VDDEE_VAL_REG0	0x000e000e
+	#define VDDEE_VAL_REG1	0x0006000c
+#elif (VDDEE_VAL == 830)
+	#define VDDEE_VAL_REG0	0x000d000f
+	#define VDDEE_VAL_REG1	0x0005000d
+#elif (VDDEE_VAL == 840)
+	#define VDDEE_VAL_REG0	0x000c0010
+	#define VDDEE_VAL_REG1	0x0004000e
+#elif (VDDEE_VAL == 850)
+	#define VDDEE_VAL_REG0	0x000b0011
+	#define VDDEE_VAL_REG1	0x0003000f
+#elif (VDDEE_VAL == 860)
+	#define VDDEE_VAL_REG0	0x000a0012
+	#define VDDEE_VAL_REG1	0x00020010
+#elif (VDDEE_VAL == 870)
+	#define VDDEE_VAL_REG0	0x00090013
+	#define VDDEE_VAL_REG1	0x00010011
+#elif (VDDEE_VAL == 880)
+	#define VDDEE_VAL_REG0	0x00080014
+	#define VDDEE_VAL_REG1	0x00000012
+#else
+	#error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3	((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3		((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3		((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0	((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1	((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+	/* demo, user defined override register */
+	/* eg: PWM init */
+
+	/* PWM_AO_D */
+	/* VCCK_VAL_REG: check PWM table */
+	{AO_PWM_PWM_D,        VCCK_VAL_REG,            0xffffffff,   0, BL2_INIT_STAGE_1, 0},
+	{AO_PWM_MISC_REG_CD,  ((1 << 23) | (1 << 1)),  (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+	{AO_PIN_MUX_REG1,     (3 << 20),               (0xF << 20),  0, BL2_INIT_STAGE_1, 0},
+
+	/* set BOOT_9 input */
+	//{PAD_PULL_UP_EN_REG0, 1 << 9,			1 << 9,   0, BL2_INIT_STAGE_1, 0},
+
+	/* PWM_AO_B */
+	/* VDDEE init start */
+	/* step1: CHK HW */
+	{(uint64_t)P_ASSIST_POR_CONFIG,  7,            0,            0, BL2_INIT_STAGE_PWM_CHK_HW,           0},
+
+	/* step2: match PWM config */
+	/* GPIO9[BIT7]=H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+	{0x1,                 PWM_CFG0,                0,            0, BL2_INIT_STAGE_PWM_CFG_GROUP,        0},
+	{0x0,                 PWM_CFG1,                0,            0, BL2_INIT_STAGE_PWM_CFG_GROUP,        0},
+
+	/* step3: config PWM */
+	/* VDDEE_VAL_REG0: VDDEE PWM table  0.67v-0.97v*/
+	{AO_PWM_PWM_B,        VDDEE_VAL_REG0,          0xffffffff,   0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0,  0},
+	{AO_PWM_MISC_REG_AB,  ((1 << 23) | (1 << 1)),  (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0,  0},
+	{AO_PIN_MUX_REG1,     (3 << 16),               (0xF << 16),  0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0,  0},
+	/* VDDEE_VAL_REG1: VDDEE PWM table  0.69v-0.89v*/
+	{AO_PWM_PWM_B,        VDDEE_VAL_REG1,          0xffffffff,   0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1,  0},
+	{AO_PWM_MISC_REG_AB,  ((1 << 23) | (1 << 1)),  (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1,  0},
+	{AO_PIN_MUX_REG1,     (3 << 16),               (0xF << 16),  0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1,  0},
+	/* VDDEE init done */
+	/* Enable 5V_EN */
+	{GPIO_O_EN_N_REG3,    (0 << 8),                (1 << 8),     0, BL2_INIT_STAGE_1, 0},
+	{GPIO_O_REG3,         (1 << 8),                0xffffffff,   0, BL2_INIT_STAGE_1, 0},
+	/* Enable VCCK */
+	{AO_SEC_REG0,         (1 << 0),                0xffffffff,   0, BL2_INIT_STAGE_1, 0},
+	{AO_GPIO_O,           (1 << 31),               0xffffffff,   0, BL2_INIT_STAGE_1, 0},
+	/* Init sys led*/
+	{AO_GPIO_O_EN_N,      (0 << 11),               (1 << 11),    0, BL2_INIT_STAGE_1, 0},
+	{AO_GPIO_O,           (0 << 11),               (1 << 11),    0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/sm1_elektra_v1/lcd.c b/board/amlogic/sm1_elektra_v1/lcd.c
new file mode 100644
index 0000000..2f352f6
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/lcd.c
@@ -0,0 +1,475 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+	"GPIOZ_9", /* panel rst */
+	"GPIOZ_8", /* panel power */
+	"invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+	{LCD_POWER_TYPE_CPU,   1,0,100,}, /* lcd power */
+	{LCD_POWER_TYPE_CPU,   0,0,10,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   0,1,20,}, /* lcd_reset */
+	{LCD_POWER_TYPE_SIGNAL,0,0,0,},  /* signal */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},  /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+	{LCD_POWER_TYPE_SIGNAL,0,0,50,},  /* signal */
+	{LCD_POWER_TYPE_CPU,   0,0,10,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   1,1,100,}, /* power off */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},   /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+	{LCD_POWER_TYPE_CPU,   1,0,200,}, /* lcd power */
+#if 1
+	{LCD_POWER_TYPE_CPU,   0,1,30,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   0,0,10,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   0,1,30,}, /* lcd_reset */
+#endif
+	{LCD_POWER_TYPE_SIGNAL,0,0,0,},  /* signal */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},  /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+	{LCD_POWER_TYPE_SIGNAL,0,0,0,},  /* signal */
+	{LCD_POWER_TYPE_CPU,   0,0,20,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   1,1,100,}, /* power off */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},   /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+	{LCD_POWER_TYPE_CPU,   1,0,200,}, /* lcd power */
+	{LCD_POWER_TYPE_CPU,   0,1,30,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   0,0,10,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   0,1,30,}, /* lcd_reset */
+	{LCD_POWER_TYPE_SIGNAL,0,0,0,},  /* signal */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},  /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+	{LCD_POWER_TYPE_SIGNAL,0,0,0,},  /* signal */
+	{LCD_POWER_TYPE_CPU,   0,0,20,}, /* lcd_reset */
+	{LCD_POWER_TYPE_CPU,   1,1,100,}, /* power off */
+	{LCD_POWER_TYPE_MAX,   0,0,0,},   /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+	"GPIOH_4", /* BL_EN */
+	"GPIOH_5", /* BL_PWM */
+	"invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+	{/* B080XAN01*/
+	"lcd_0",LCD_MIPI,8,
+	/* basic timing */
+	768,1024,948,1140,64,56,0,50,30,0,
+	/* clk_attr */
+	0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	/* mipi_attr */
+	4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+	/* power step */
+	lcd_power_on_step, lcd_power_off_step,
+	/* backlight */
+	100,255,10,128,128,
+	BL_CTRL_PWM,0,1,0,200,200,
+	BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	10,10,Rsv_val},
+
+	{/* TV070WSM*/
+	"lcd_1",LCD_MIPI,8,
+	/* basic timing */
+	600,1024,700,1053,24,36,0,2,8,0,
+	/* clk_attr */
+	0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	/* mipi_attr */
+	4,360,0,1,0,2,0,0,Rsv_val,1,
+	/* power step */
+	lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+	/* backlight */
+	100,255,10,128,128,
+	BL_CTRL_PWM,0,1,0,200,200,
+	BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	10,10,Rsv_val},
+
+	{/* P070ACB*/
+	"lcd_2",LCD_MIPI,8,
+	/* basic timing */
+	600,1024,680,1194,24,36,0,10,80,0,
+	/* clk_attr */
+	0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	/* mipi_attr */
+	4,400,0,1,0,2,0,0,Rsv_val,2,
+	/* power step */
+	lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+	/* backlight */
+	100,255,10,128,128,
+	BL_CTRL_PWM,0,1,0,200,200,
+	BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+	10,10,Rsv_val},
+
+	{.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+	{
+		.name = "lcd_pin",
+		.pinmux_set = {{LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+	},
+	{
+		.name = "invalid",
+	},
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+	{
+		.name = "bl_pwm_on_pin", //GPIOH_5
+		.pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
+		.name = "invalid",
+	},
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+	0x05, 1, 0x11,
+	0xfd, 1, 20,
+	0x05, 1, 0x29,
+	0xfd, 1, 20,
+	0xff, 0,   //ending
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+	0x05, 1, 0x28,
+	0xfd, 1, 10,
+	0x05, 1, 0x10,
+	0xfd, 1, 10,
+	0xff, 0,   //ending
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+	0xff, 0,   //ending
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+	0xff, 0,   //ending
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+	0xff, 0,   //ending
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+	0xff, 0,   //ending
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+	.lane_num = 4,
+	.bit_rate_max = 550, /* MHz */
+	.factor_numerator   = 0,
+	.factor_denominator = 100,
+	.operation_mode_init = 1,    /* 0=video mode, 1=command mode */
+	.operation_mode_display = 0, /* 0=video mode, 1=command mode */
+	.video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+	.clk_always_hs = 1, /* 0=disable, 1=enable */
+	.phy_switch = 0,   /* 0=auto, 1=standard, 2=slow */
+
+	.dsi_init_on  = &mipi_init_on_table[0],
+	.dsi_init_off = &mipi_init_off_table[0],
+	.extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+	.check_en = 0,
+	.check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+	.power_on_step = {
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 1, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 10, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 0, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 20, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 1, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 20, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_SIGNAL,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 1, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 0, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_MAX, /* ending flag */
+		},
+	},
+	.power_off_step = {
+		{
+			.type = LCD_POWER_TYPE_SIGNAL,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 0, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 100, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_CPU,
+			.index = 0, /* point to cpu_gpio[] struct */
+			.value = 0, /* 0=output_low, 1=output_high, 2=input */
+			.delay = 100, /* unit: ms */
+		},
+		{
+			.type = LCD_POWER_TYPE_MAX, /* ending flag */
+		},
+	},
+};
+
+struct lcd_config_s lcd_config_dft = {
+	.lcd_mode = LCD_MODE_TABLET,
+	.lcd_key_valid = 0,
+	.lcd_clk_path = 0,
+	.lcd_basic = {
+		.model_name = "default",
+		.lcd_type = LCD_TYPE_MAX,
+		.lcd_bits = 8,
+		.h_active = 768,
+		.v_active = 1024,
+		.h_period = 948,
+		.v_period = 1140,
+
+		.screen_width   = 119,
+		.screen_height  = 159,
+	},
+
+	.lcd_timing = {
+		.clk_auto = 1,
+		.lcd_clk = 64843200,
+		.ss_level = 0,
+		.fr_adjust_type = 0,
+
+		.hsync_width = 64,
+		.hsync_bp    = 56,
+		.hsync_pol   = 0,
+		.vsync_width = 50,
+		.vsync_bp    = 30,
+		.vsync_pol   = 0,
+	},
+
+	.lcd_control = {
+		.mipi_config= &lcd_mipi_config,
+	},
+	.lcd_power = &lcd_power_ctrl,
+
+	.pinctrl_ver = 2,
+	.lcd_pinmux = lcd_pinmux_ctrl,
+	.pinmux_set = {{LCD_PINMUX_END, 0x0}},
+	.pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+	"invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+	0xff, 0,   //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+	0xff, 0,   //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+	.lcd_ext_key_valid = 0,
+	.lcd_ext_num = 3,
+	.i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+	.pinmux_set = {{LCD_PINMUX_END, 0x0}},
+	.pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+	{
+		.index = 0,
+		.name = "ext_default",
+		.type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+		.status = 0, /* 0=disable, 1=enable */
+		.i2c_addr = 0x1c, /* 7bit i2c address */
+		.i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+		.cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+		.table_init_on = ext_init_on_table,
+		.table_init_on_cnt = sizeof(ext_init_on_table),
+		.table_init_off = ext_init_off_table,
+		.table_init_off_cnt = sizeof(ext_init_off_table),
+	},
+	{
+		.index = 1,
+		.name = "mipi_TV070WSM",
+		.type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+		.status = 1, /* 0=disable, 1=enable */
+		.cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+		.table_init_on = ext_init_on_table,
+		.table_init_on_cnt = sizeof(ext_init_on_table),
+		.table_init_off = ext_init_off_table,
+		.table_init_off_cnt = sizeof(ext_init_off_table),
+	},
+	{
+		.index = 2,
+		.name = "mipi_P070ACB",
+		.type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+		.status = 1, /* 0=disable, 1=enable */
+		.cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+		.table_init_on = ext_init_on_table,
+		.table_init_on_cnt = sizeof(ext_init_on_table),
+		.table_init_off = ext_init_off_table,
+		.table_init_off_cnt = sizeof(ext_init_off_table),
+	},
+	{
+		.index = LCD_EXTERN_INDEX_INVALID,
+	},
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+	.name = "default",
+	.bl_key_valid = 0,
+
+	.level_default = 100,
+	.level_min = 10,
+	.level_max = 255,
+	.level_mid = 128,
+	.level_mid_mapping = 128,
+	.level = 0,
+
+	.method = BL_CTRL_MAX,
+	.power_on_delay = 200,
+	.power_off_delay = 200,
+
+	.en_gpio = 0xff,
+	.en_gpio_on = 1,
+	.en_gpio_off = 0,
+
+	.bl_pwm = NULL,
+	.bl_pwm_combo0 = NULL,
+	.bl_pwm_combo1 = NULL,
+	.pwm_on_delay = 10,
+	.pwm_off_delay = 10,
+
+	.bl_extern_index = 0xff,
+
+	.pinctrl_ver = 2,
+	.bl_pinmux = bl_pinmux_ctrl,
+	.pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+	.pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX];
+static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX];
+struct bl_extern_config_s bl_extern_config_dtf = {
+	.index = BL_EXTERN_INDEX_INVALID,
+	.name = "none",
+	.type = BL_EXTERN_MAX,
+	.i2c_addr = 0xff,
+	.i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+	.dim_min = 10,
+	.dim_max = 255,
+
+	.init_loaded = 0,
+	.cmd_size = 0xff,
+	.init_on = bl_ext_init_on,
+	.init_off = bl_ext_init_off,
+	.init_on_cnt = sizeof(bl_ext_init_on),
+	.init_off_cnt = sizeof(bl_ext_init_off),
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+	int i, j;
+	char *str;
+	struct ext_lcd_config_s *ext_lcd = NULL;
+
+	str = getenv("panel_type");
+	if (str) {
+		for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+			ext_lcd = &ext_lcd_config[i];
+			if (strcmp(ext_lcd->panel_type, str) == 0) {
+				switch (i) {
+				case 1:
+					lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+					lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+					break;
+				case 2:
+					lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+					lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+					break;
+				case 0:
+				default:
+					lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+					lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+					break;
+				}
+				break;
+			}
+		}
+	}
+
+	for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+		if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+			break;
+		strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+	}
+	for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+		strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+	for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+		if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+			break;
+		strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+	}
+	for (j = i; j < BL_GPIO_NUM_MAX; j++)
+		strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+	for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+		if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+			break;
+	}
+	ext_common_dft.lcd_ext_num = i;
+
+	for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+		if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+			break;
+		strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+	}
+	for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+		strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/sm1_elektra_v1/sm1_elektra_v1.c b/board/amlogic/sm1_elektra_v1/sm1_elektra_v1.c
new file mode 100644
index 0000000..12a2d40
--- a/dev/null
+++ b/board/amlogic/sm1_elektra_v1/sm1_elektra_v1.c
@@ -0,0 +1,871 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+#include <amlogic/i2c.h>
+#endif
+#ifdef CONFIG_PWM_MESON
+#include <pwm.h>
+#include <amlogic/pwm.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include "avb2_kpub.c"
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket*  eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+    //UART in "Always On Module"
+    //GPIOAO_0==tx,GPIOAO_1==rx
+    //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+    return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef  ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+	writel(0x39C0040A, P_ETH_PLL_CTL0);
+	writel(0x927E0000, P_ETH_PLL_CTL1);
+	writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+	writel(0x00000000, P_ETH_PLL_CTL3);
+	udelay(200);
+	writel(0x19C0040A, P_ETH_PLL_CTL0);
+	return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+	/*Analog*/
+	writel(0x20200000, P_ETH_PLL_CTL5);
+	writel(0x0000c002, P_ETH_PLL_CTL6);
+	writel(0x00000023, P_ETH_PLL_CTL7);
+
+	return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+	/*config phyid should between  a 0~0xffffffff*/
+	/*please don't use 44000181, this has been used by internal phy*/
+	writel(0x33000180, P_ETH_PHY_CNTL0);
+
+	/*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+	writel(0x260, P_ETH_PHY_CNTL2);
+
+	writel(0x74043, P_ETH_PHY_CNTL1);
+	writel(0x34043, P_ETH_PHY_CNTL1);
+	writel(0x74043, P_ETH_PHY_CNTL1);
+	return 0;
+}
+
+static void setup_net_chip(void)
+{
+	eth_aml_reg0_t eth_reg0;
+
+	eth_reg0.d32 = 0;
+	eth_reg0.b.phy_intf_sel = 4;
+	eth_reg0.b.rx_clk_rmii_invert = 0;
+	eth_reg0.b.rgmii_tx_clk_src = 0;
+	eth_reg0.b.rgmii_tx_clk_phase = 0;
+	eth_reg0.b.rgmii_tx_clk_ratio = 4;
+	eth_reg0.b.phy_ref_clk_enable = 1;
+	eth_reg0.b.clk_rmii_i_invert = 1;
+	eth_reg0.b.clk_en = 1;
+	eth_reg0.b.adj_enable = 1;
+	eth_reg0.b.adj_setup = 0;
+	eth_reg0.b.adj_delay = 9;
+	eth_reg0.b.adj_skew = 0;
+	eth_reg0.b.cali_start = 0;
+	eth_reg0.b.cali_rise = 0;
+	eth_reg0.b.cali_sel = 0;
+	eth_reg0.b.rgmii_rx_reuse = 0;
+	eth_reg0.b.eth_urgent = 0;
+	setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+	dwmac_meson_cfg_pll();
+	dwmac_meson_cfg_analog();
+	dwmac_meson_cfg_ctrl();
+
+	/* eth core clock */
+	setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+	/* eth phy clock */
+	setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+	/* eth phy pll, clk50m */
+	setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+	/* power on memory */
+	clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+	writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+	return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+	eth_aml_reg0_t eth_reg0;
+	writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+	writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+	eth_reg0.d32 = 0;
+	eth_reg0.b.phy_intf_sel = 1;
+	eth_reg0.b.rx_clk_rmii_invert = 0;
+	eth_reg0.b.rgmii_tx_clk_src = 0;
+	eth_reg0.b.rgmii_tx_clk_phase = 1;
+	eth_reg0.b.rgmii_tx_clk_ratio = 4;
+	eth_reg0.b.phy_ref_clk_enable = 1;
+	eth_reg0.b.clk_rmii_i_invert = 0;
+	eth_reg0.b.clk_en = 1;
+	eth_reg0.b.adj_enable = 0;
+	eth_reg0.b.adj_setup = 0;
+	eth_reg0.b.adj_delay = 0;
+	eth_reg0.b.adj_skew = 0;
+	eth_reg0.b.cali_start = 0;
+	eth_reg0.b.cali_rise = 0;
+	eth_reg0.b.cali_sel = 0;
+	eth_reg0.b.rgmii_rx_reuse = 0;
+	eth_reg0.b.eth_urgent = 0;
+	setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+	setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+	/* power on memory */
+	clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+	return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+	dwmac_meson_cfg_drive_strength();
+	setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+	setup_net_chip();
+#endif
+	udelay(1000);
+	designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+	return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int  sd_emmc_init(unsigned port)
+{
+    switch (port)
+	{
+		case SDIO_PORT_A:
+			break;
+		case SDIO_PORT_B:
+			//todo add card detect
+			/* check card detect */
+			clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+			setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+			setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+			setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+			break;
+		case SDIO_PORT_C:
+			//enable pull up
+			//clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+			break;
+		default:
+			break;
+	}
+
+	return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+	cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+    switch (port)
+	{
+		case SDIO_PORT_A:
+			break;
+		case SDIO_PORT_B:
+//            clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+//            clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+			/// @todo NOT FINISH
+			break;
+		case SDIO_PORT_C:
+			break;
+		default:
+			break;
+	}
+	return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+	/// @todo NOT FINISH
+    switch (port)
+	{
+		case SDIO_PORT_A:
+			break;
+		case SDIO_PORT_B:
+//            setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+//            clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+			break;
+		case SDIO_PORT_C:
+			break;
+				default:
+			break;
+	}
+	return;
+}
+
+// #define CONFIG_TSD      1
+static void board_mmc_register(unsigned port)
+{
+	struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+    if (aml_priv == NULL)
+		return;
+
+	aml_priv->sd_emmc_init=sd_emmc_init;
+	aml_priv->sd_emmc_detect=sd_emmc_detect;
+	aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+	aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+	aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+	aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+	if (NULL == aml_priv->desc_buf)
+		printf(" desc_buf Dma alloc Fail!\n");
+	else
+		printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+	sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t	*bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+	//board_mmc_register(SDIO_PORT_A);
+#else
+	//board_mmc_register(SDIO_PORT_B);
+#endif
+	board_mmc_register(SDIO_PORT_B);
+	board_mmc_register(SDIO_PORT_C);
+//	board_mmc_register(SDIO_PORT_B1);
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+	/*********************************************/
+	/*                | I2C_Master_AO        |I2C_Slave            |       */
+	/*********************************************/
+	/*                | I2C_SCK                | I2C_SCK_SLAVE  |      */
+	/* GPIOAO_4  | [AO_PIN_MUX: 6]     | [AO_PIN_MUX: 2]   |     */
+	/*********************************************/
+	/*                | I2C_SDA                 | I2C_SDA_SLAVE  |     */
+	/* GPIOAO_5  | [AO_PIN_MUX: 5]     | [AO_PIN_MUX: 1]   |     */
+	/*********************************************/
+
+	//disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+	clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+	//enable I2C MASTER AO pins
+	setbits_le32(P_AO_RTI_PIN_MUX_REG,
+	(MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+	udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+	.wait_count         = 1000000,
+	.wait_ack_interval  = 5,
+	.wait_read_interval = 5,
+	.wait_xfer_interval = 5,
+	.master_no          = AML_I2C_MASTER_AO,
+	.use_pio            = 0,
+	.master_i2c_speed   = AML_I2C_SPPED_400K,
+	.master_ao_pinmux = {
+		.scl_reg    = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+		.scl_bit    = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+		.sda_reg    = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+		.sda_bit    = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+	}
+};
+#if 0
+static void board_i2c_init(void)
+{
+	//set I2C pinmux with PCB board layout
+	board_i2c_set_pinmux();
+
+	//Amlogic I2C controller initialized
+	//note: it must be call before any I2C operation
+	aml_i2c_init();
+
+	udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+	/*add board early init function here*/
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM	2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM	1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM	0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+	int ret;
+
+	ret = gpio_request(CONFIG_USB_GPIO_PWR,
+		CONFIG_USB_GPIO_PWR_NAME);
+	if (ret && ret != -EBUSY) {
+		printf("gpio: requesting pin %u failed\n",
+			CONFIG_USB_GPIO_PWR);
+		return;
+	}
+
+	if (is_power_on) {
+		gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+	} else {
+		gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+	}
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+	CONFIG_GXL_XHCI_BASE,
+	USB_ID_MODE_HARDWARE,
+	gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+	CONFIG_GXL_USB_PHY2_BASE,
+	CONFIG_GXL_USB_PHY3_BASE,
+	CONFIG_GXL_USB_U2_PORT_NUM,
+	CONFIG_GXL_USB_U3_PORT_NUM,
+	.usb_phy2_pll_base_addr = {
+		CONFIG_USB_PHY_20,
+		CONFIG_USB_PHY_21,
+	}
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+    /* MUST NOT CHANGE this part unless u know what you are doing!
+     * inherent parition for descrete bootloader to store fip
+     * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+     * name must be same with TPL_PART_NAME
+     */
+    {
+        .name = "tpl",
+        .offset = 0,
+        .size = 0,
+    },
+#endif
+    {
+        .name = "logo",
+        .offset = 0,
+        .size = 2*SZ_1M,
+    },
+    {
+        .name = "recovery",
+        .offset = 0,
+        .size = 16*SZ_1M,
+    },
+    {
+        .name = "boot",
+        .offset = 0,
+        .size = 15*SZ_1M,
+    },
+    {
+        .name = "system",
+        .offset = 0,
+        .size = 280*SZ_1M,
+    },
+	/* last partition get the rest capacity */
+    {
+        .name = "data",
+        .offset = MTDPART_OFS_APPEND,
+        .size = MTDPART_SIZ_FULL,
+    },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+	return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+	return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+	unsigned int val;
+
+	val = readl(P_PERIPHS_PIN_MUX_0);
+	val &= ~(0xfffff << 12);
+	if (enable)
+		val |= 0x33333 << 12;
+	writel(val, P_PERIPHS_PIN_MUX_0);
+
+	val = readl(P_PERIPHS_PIN_MUX_1);
+	val &= ~(0xf << 24);
+	writel(val, P_PERIPHS_PIN_MUX_1);
+	return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+	.reg = 0xffd14000,
+	.mem_map = 0xf6000000,
+	.pinctrl_enable = spifc_pinctrl_enable,
+	.num_chipselect = SPIFC_NUM_CS,
+	.cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+	.name = "spifc",
+	.platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+#ifdef CONFIG_SYS_I2C_MESON
+static const struct meson_i2c_platdata i2c_data[] = {
+	{ 0, 0xffd1f000, 166666666, 3, 15, 100000 },
+	{ 1, 0xffd1e000, 166666666, 3, 15, 100000 },
+	{ 2, 0xffd1d000, 166666666, 3, 15, 100000 },
+	{ 3, 0xffd1c000, 166666666, 3, 15, 100000 },
+	{ 4, 0xff805000, 166666666, 3, 15, 100000 },
+};
+
+U_BOOT_DEVICES(meson_i2cs) = {
+	{ "i2c_meson", &i2c_data[0] },
+	{ "i2c_meson", &i2c_data[1] },
+	{ "i2c_meson", &i2c_data[2] },
+	{ "i2c_meson", &i2c_data[3] },
+	{ "i2c_meson", &i2c_data[4] },
+};
+
+/*
+ *GPIOAO_10//I2C_SDA_AO
+ *GPIOAO_11//I2C_SCK_AO
+ *pinmux configuration seperated with i2c controller configuration
+ * config it when you use
+ */
+void set_i2c_ao_pinmux(void)
+{
+	return;
+}
+#endif /*end CONFIG_SYS_I2C_MESON*/
+
+#ifdef CONFIG_PWM_MESON
+static const struct meson_pwm_platdata pwm_data[] = {
+	{ PWM_AB, 0xffd1b000, IS_DOUBLE_CHANNEL, IS_BLINK },
+	{ PWM_CD, 0xffd1a000, IS_DOUBLE_CHANNEL, IS_BLINK },
+	{ PWM_EF, 0xffd19000, IS_DOUBLE_CHANNEL, IS_BLINK },
+	{ PWMAO_AB, 0xff807000, IS_DOUBLE_CHANNEL, IS_BLINK },
+	{ PWMAO_CD, 0xff802000, IS_DOUBLE_CHANNEL, IS_BLINK },
+};
+
+U_BOOT_DEVICES(meson_pwm) = {
+	{ "amlogic,general-pwm", &pwm_data[0] },
+	{ "amlogic,general-pwm", &pwm_data[1] },
+	{ "amlogic,general-pwm", &pwm_data[2] },
+	{ "amlogic,general-pwm", &pwm_data[3] },
+	{ "amlogic,general-pwm", &pwm_data[4] },
+};
+#endif /*end CONFIG_PWM_MESON*/
+
+int board_init(void)
+{
+    //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+    //As NOT NEED other board init If USB BOOT MODE
+	/*skyworth begin*/
+	printf("asion %s %d\n", __func__, __LINE__);
+	writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+
+	/*skyworth add for HY40A*/
+	 writel(readl(PAD_PULL_UP_REG4) & (~(1 << 2)), PAD_PULL_UP_REG4);
+	/*skyworth add for HY40A end*/
+
+	//writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+	writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+	/*skyworth end*/
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+	if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+				aml_try_factory_usb_burning(0, gd->bd);
+	}
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+	board_usb_pll_disable(&g_usb_config_GXL_skt);
+	board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+	aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+	extern int amlnf_init(unsigned char flag);
+	amlnf_init(0);
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+	set_i2c_ao_pinmux();
+#endif
+
+	return 0;
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+	cpu_id_t cpuid = get_cpu_id();
+	if (MESON_CPU_MAJOR_ID_G12A != cpuid.family_id)
+		return;
+
+	run_command("fdt address $dtb_mem_addr", 0);
+	printf("%s %d\n", __func__, __LINE__);
+	if (cpuid.chip_rev == 0xA) {
+		printf("%s %d\n", __func__, __LINE__);
+		run_command("fdt set /emmc/emmc co_phase <0x2>", 0);
+		run_command("fdt rm /emmc/emmc caps2", 0);
+		run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0);
+
+		run_command("fdt set /sdio status okay", 0);
+		run_command("fdt set /sd1 status okay", 0);
+		run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0);
+		run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0);
+		run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0);
+		run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0);
+		run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0);
+		run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0);
+		/* debug */
+		run_command("fdt print /emmc/emmc co_phase", 0);
+		run_command("fdt print /emmc/emmc caps2", 0);
+		run_command("fdt print /emmc/emmc f_max", 0);
+
+		run_command("fdt print /sdio status", 0);
+		run_command("fdt print /sd1 status ", 0);
+		run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0);
+		run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0);
+		run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0);
+		run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0);
+		run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0);
+		run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0);
+	} else {
+
+		printf("%s %d\n", __func__, __LINE__);
+		run_command("fdt set /emmc/emmc co_phase <0x3>", 0);
+		run_command("fdt set /sdio status disabled", 0);
+		run_command("fdt set /sd2 status okay", 0);
+		/* debug */
+		run_command("fdt print /emmc/emmc co_phase", 0);
+		run_command("fdt print /emmc/emmc caps2", 0);
+		run_command("fdt print /emmc/emmc f_max", 0);
+		run_command("fdt print /sdio status", 0);
+		run_command("fdt print /sd2 status", 0);
+	}
+
+	return;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	TE(__func__);
+		//update env before anyone using it
+		run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+						"if test ${reboot_mode} = factory_reset; then "\
+						"defenv_reserv;save; fi;", 0);
+		run_command("if itest ${upgrade_step} == 1; then "\
+						"defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+		/*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+		int ret;
+		ret = run_command("store dtb read $dtb_mem_addr", 1);
+        if (ret) {
+				printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+				char cmd[64];
+				printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+				sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+				ret = run_command(cmd, 1);
+                if (ret) {
+						printf("%s(): %s fail\n", __func__, cmd);
+				}
+#endif
+		}
+#elif defined(CONFIG_DTB_MEM_ADDR)
+		{
+				char cmd[128];
+				int ret;
+                if (!getenv("dtb_mem_addr")) {
+						sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+						run_command(cmd, 0);
+				}
+				sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+				ret = run_command(cmd, 0);
+                if (ret) {
+						printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+				}
+		}
+#endif// #ifndef DTB_BIND_KERNEL
+
+		/* load unifykey */
+		run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+	vpu_probe();
+#endif
+	vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+	hdmi_tx_set_hdmi_5v();
+	hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+	run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+	lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+	if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+		aml_try_factory_usb_burning(1, gd->bd);
+		aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+    if (MESON_CPU_MAJOR_ID_SM1 == get_cpu_id().family_id) {
+		setenv("board_defined_bootup", "bootup_X3");
+	}
+	/**/
+	aml_config_dtb();
+
+	TE(__func__);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+	unsigned long upgrade_step;
+	upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+	printf("upgrade_step = %d\n", (int)upgrade_step);
+	if (upgrade_step == 1)
+	{
+		run_command("defenv", 1);
+		run_command("setenv upgrade_step 2", 1);
+		run_command("saveenv", 1);
+		return 0;
+	}
+	else
+	{
+		return -1;
+	}
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+	// >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+	return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+	return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+	/*
+	 * set aml_dt according to chip and dram capacity
+	 */
+	unsigned int ddr_size=0;
+	char loc_name[64] = {0};
+	int i;
+	cpu_id_t cpu_id=get_cpu_id();
+
+	for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+		ddr_size += gd->bd->bi_dram[i].size;
+	}
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+	ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+	char *ddr_mode = getenv("mem_size");
+	if (MESON_CPU_MAJOR_ID_SM1 == cpu_id.family_id) {
+		switch (ddr_size) {
+			case 0x80000000:
+				if (!strcmp(ddr_mode, "1g")) {
+					strcpy(loc_name, "sm1_ac214_1g\0");
+					break;
+				}
+				strcpy(loc_name, "sm1_ac214_2g\0");
+				break;
+			case 0x40000000:
+				strcpy(loc_name, "sm1_ac214_1g\0");
+				break;
+			case 0x2000000:
+				strcpy(loc_name, "sm1_ac214_512m\0");
+				break;
+			default:
+				strcpy(loc_name, "sm1_ac214_unsupport");
+				break;
+		}
+	}
+	else {
+		switch (ddr_size) {
+			case 0x80000000:
+				if (!strcmp(ddr_mode, "1g")) {
+					strcpy(loc_name, "g12a_u212_1g\0");
+					break;
+				}
+				strcpy(loc_name, "g12a_u212_2g\0");
+				break;
+			case 0x40000000:
+				strcpy(loc_name, "g12a_u212_1g\0");
+				break;
+			case 0x2000000:
+				strcpy(loc_name, "g12a_u212_512m\0");
+				break;
+			default:
+				strcpy(loc_name, "g12a_u212_unsupport");
+				break;
+		}
+	}
+
+	strcpy(name, loc_name);
+	setenv("aml_dt", loc_name);
+	return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+		"aml_dt",
+		"firstboot",
+		"lock",
+		"upgrade_step",
+		"bootloader_version",
+
+		NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/tl1_skt_v1/lcd.c b/board/amlogic/tl1_skt_v1/lcd.c
index b59b5d8..e4cd7b5 100644
--- a/board/amlogic/tl1_skt_v1/lcd.c
+++ b/board/amlogic/tl1_skt_v1/lcd.c
@@ -244,6 +244,11 @@ static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
 		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
 	},
 	{
+		.name = "lcd_p2p_usit_pin", //GPIOH_0~19
+		.pinmux_set = {{7, 0x11111111}, {8, 0x11111111}, {9, 0x2}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
 		.name = "invalid",
 	},
 };
diff --git a/board/amlogic/tl1_t309_v1/lcd.c b/board/amlogic/tl1_t309_v1/lcd.c
index fa002c4..db14842 100644
--- a/board/amlogic/tl1_t309_v1/lcd.c
+++ b/board/amlogic/tl1_t309_v1/lcd.c
@@ -264,6 +264,11 @@ static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
 		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
 	},
 	{
+		.name = "lcd_p2p_usit_pin", //GPIOH_0~19
+		.pinmux_set = {{7, 0x11111111}, {8, 0x11111111}, {9, 0x2}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
 		.name = "invalid",
 	},
 };
diff --git a/board/amlogic/tl1_x301_v1/lcd.c b/board/amlogic/tl1_x301_v1/lcd.c
index 67e63d5..6577fa8 100644
--- a/board/amlogic/tl1_x301_v1/lcd.c
+++ b/board/amlogic/tl1_x301_v1/lcd.c
@@ -264,6 +264,11 @@ static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
 		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
 	},
 	{
+		.name = "lcd_p2p_usit_pin", //GPIOH_0~19
+		.pinmux_set = {{7, 0x11111111}, {8, 0x11111111}, {9, 0x2}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
 		.name = "invalid",
 	},
 };
diff --git a/board/amlogic/tm2_t962x3_ab301_v1/lcd.c b/board/amlogic/tm2_t962x3_ab301_v1/lcd.c
index 67e63d5..6577fa8 100644
--- a/board/amlogic/tm2_t962x3_ab301_v1/lcd.c
+++ b/board/amlogic/tm2_t962x3_ab301_v1/lcd.c
@@ -264,6 +264,11 @@ static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
 		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
 	},
 	{
+		.name = "lcd_p2p_usit_pin", //GPIOH_0~19
+		.pinmux_set = {{7, 0x11111111}, {8, 0x11111111}, {9, 0x2}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
 		.name = "invalid",
 	},
 };
diff --git a/board/amlogic/tm2_t962x3_ab309_v1/lcd.c b/board/amlogic/tm2_t962x3_ab309_v1/lcd.c
index b59b5d8..e4cd7b5 100644
--- a/board/amlogic/tm2_t962x3_ab309_v1/lcd.c
+++ b/board/amlogic/tm2_t962x3_ab309_v1/lcd.c
@@ -244,6 +244,11 @@ static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
 		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
 	},
 	{
+		.name = "lcd_p2p_usit_pin", //GPIOH_0~19
+		.pinmux_set = {{7, 0x11111111}, {8, 0x11111111}, {9, 0x2}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
 		.name = "invalid",
 	},
 };
diff --git a/board/amlogic/tm2_t962x3_t312_v1/lcd.c b/board/amlogic/tm2_t962x3_t312_v1/lcd.c
index 67e63d5..6577fa8 100644
--- a/board/amlogic/tm2_t962x3_t312_v1/lcd.c
+++ b/board/amlogic/tm2_t962x3_t312_v1/lcd.c
@@ -264,6 +264,11 @@ static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
 		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
 	},
 	{
+		.name = "lcd_p2p_usit_pin", //GPIOH_0~19
+		.pinmux_set = {{7, 0x11111111}, {8, 0x11111111}, {9, 0x2}, {LCD_PINMUX_END, 0x0}},
+		.pinmux_clr = {{7, 0xffffffff}, {8, 0xffffffff}, {9, 0xfffff}, {LCD_PINMUX_END, 0x0}},
+	},
+	{
 		.name = "invalid",
 	},
 };
diff --git a/common/aml_dt.c b/common/aml_dt.c
index cd9b039..9da7302 100644
--- a/common/aml_dt.c
+++ b/common/aml_dt.c
@@ -65,28 +65,6 @@ Description:
 //#define readl(addr) (*(volatile unsigned int*)(addr))
 extern int checkhw(char * name);
 
-/* return 1 if dtb is encrpted */
-int is_dtb_encrypt(unsigned char *buffer)
-{
-#ifdef CONFIG_SKIP_KERNEL_DTB_VERIFY
-       return 0;
-#else
-#if 0
-	unsigned int magic = *(unsigned int*)buffer;
-
-	if ((DT_HEADER_MAGIC == magic)
-			|| (AML_DT_HEADER_MAGIC == magic)
-			|| (IS_GZIP_FORMAT(magic)))
-		return 0;
-	return 1;
-#else
-		const unsigned long cfg10 = readl(AO_SEC_SD_CFG10);
-		/*KM_MSG("cfg10=0x%lX\n", cfg10);*/
-		return ( cfg10 & (0x1<< 4) );
-#endif//#if 0
-#endif /* CONFIG_SKIP_KERNEL_DTB_VERIFY */
-}
-
 unsigned long __attribute__((unused))
 	get_multi_dt_entry(unsigned long fdt_addr){
 	unsigned int dt_magic = readl(fdt_addr);
diff --git a/common/cmd_bcb.c b/common/cmd_bcb.c
index 25a2c37..ed8616f 100644
--- a/common/cmd_bcb.c
+++ b/common/cmd_bcb.c
@@ -92,6 +92,7 @@ static int do_RunBcbCommand(
     char miscbuf[MISCBUF_SIZE] = {0};
     char clearbuf[COMMANDBUF_SIZE+STATUSBUF_SIZE+RECOVERYBUF_SIZE] = {0};
     char* RebootMode;
+    char* ActiveSlot;
 
     if (argc != 2) {
         return cmd_usage(cmdtp);
@@ -173,6 +174,15 @@ static int do_RunBcbCommand(
         run_command("setenv bootargs ${bootargs} androidboot.quiescent=1;", 0);
     }
 
+    run_command("get_valid_slot", 0);
+    if (getenv("active_slot")) {
+        ActiveSlot = getenv("active_slot");
+        if (strstr(ActiveSlot, "normal") == NULL) {
+            printf("ab update mode\n");
+            run_command("setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};", 0);
+        }
+    }
+
     if (!memcmp(command, CMD_RUN_RECOVERY, strlen(CMD_RUN_RECOVERY))) {
         if (run_command("run recovery_from_flash", 0) < 0) {
             printf("run_command for cmd:run recovery_from_flash failed.\n");
diff --git a/common/cmd_bootctl.c b/common/cmd_bootctl.c
index 8a61edd..a18cc45 100644
--- a/common/cmd_bootctl.c
+++ b/common/cmd_bootctl.c
@@ -308,22 +308,26 @@ static int do_GetValidSlot(
         if (has_boot_slot == 1) {
             setenv("active_slot","_a");
             setenv("boot_part","boot_a");
+            setenv("recovery_part","recovery_a");
             setenv("slot-suffixes","0");
         }
         else {
             setenv("active_slot","normal");
             setenv("boot_part","boot");
+            setenv("recovery_part","recovery");
         }
     }
     else {
         if (has_boot_slot == 1) {
             setenv("active_slot","_b");
             setenv("boot_part","boot_b");
+            setenv("recovery_part","recovery_b");
             setenv("slot-suffixes","1");
         }
         else {
             setenv("active_slot","normal");
             setenv("boot_part","boot");
+            setenv("recovery_part","recovery");
         }
     }
 
@@ -364,12 +368,14 @@ static int do_SetActiveSlot(
     if (strcmp(argv[1], "a") == 0) {
         setenv("active_slot","_a");
         setenv("boot_part","boot_a");
+        setenv("recovery_part","recovery_a");
         setenv("slot-suffixes","0");
         printf("set active slot a \n");
         boot_info_set_active_slot(&info, 0);
     } else if (strcmp(argv[1], "b") == 0) {
         setenv("active_slot","_b");
         setenv("boot_part","boot_b");
+        setenv("recovery_part","recovery_b");
         setenv("slot-suffixes","1");
         printf("set active slot b \n");
         boot_info_set_active_slot(&info, 1);
diff --git a/common/cmd_bootctl_avb.c b/common/cmd_bootctl_avb.c
index 98351f5..970cf5d 100644
--- a/common/cmd_bootctl_avb.c
+++ b/common/cmd_bootctl_avb.c
@@ -266,11 +266,13 @@ static int do_GetValidSlot(
         if (has_boot_slot == 1) {
             setenv("active_slot","_a");
             setenv("boot_part","boot_a");
+            setenv("recovery_part","recovery_a");
             setenv("slot-suffixes","0");
         }
         else {
             setenv("active_slot","normal");
             setenv("boot_part","boot");
+            setenv("recovery_part","recovery");
         }
         return 0;
     }
@@ -279,11 +281,13 @@ static int do_GetValidSlot(
         if (has_boot_slot == 1) {
             setenv("active_slot","_b");
             setenv("boot_part","boot_b");
+            setenv("recovery_part","recovery_b");
             setenv("slot-suffixes","1");
         }
         else {
             setenv("active_slot","normal");
             setenv("boot_part","boot");
+            setenv("recovery_part","recovery");
         }
         return 0;
     }
@@ -322,12 +326,14 @@ static int do_SetActiveSlot(
         setenv("active_slot","_a");
         setenv("slot-suffixes","0");
         setenv("boot_part","boot_a");
+        setenv("recovery_part","recovery_a");
         printf("set active slot a \n");
         boot_info_set_active_slot(&info, 0);
     } else if (strcmp(argv[1], "b") == 0) {
         setenv("active_slot","_b");
         setenv("slot-suffixes","1");
         setenv("boot_part","boot_b");
+        setenv("recovery_part","recovery_b");
         printf("set active slot b \n");
         boot_info_set_active_slot(&info, 1);
     } else {
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index c244521..2dee004 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -130,7 +130,7 @@ static void defendkey_process(void)
 
 int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-        int nRet;
+	int nRet;
 	char *avb_s;
 	char argv0_new[12] = {0};
 	char *argv_new = (char*)&argv0_new;
diff --git a/common/cmd_ddr_test_g12.c b/common/cmd_ddr_test_g12.c
index 77f6b0e..9209527 100644
--- a/common/cmd_ddr_test_g12.c
+++ b/common/cmd_ddr_test_g12.c
@@ -11102,7 +11102,7 @@ int do_ddr_auto_fastboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char * cons
 	{
 		printf("\nuboot  auto fast boot  auto window test begin \n");
 		{
-			ddr_set_t_p->fast_boot[0]=0xfe;
+			ddr_set_t_p->fast_boot[0]=0xfd; //0xfd for check unexcept power off status
 			//#if 1
 			//printf("print sha\n");
 			//sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32));
diff --git a/common/cmd_hdmitx.c b/common/cmd_hdmitx.c
index 50d32d7..22cd686 100644
--- a/common/cmd_hdmitx.c
+++ b/common/cmd_hdmitx.c
@@ -77,6 +77,7 @@ static int do_hpd_detect(cmd_tbl_t *cmdtp, int flag, int argc,
 #endif
 	int st;
 	char* hdmimode;
+	char* cvbsmode;
 	char* colorattribute;
 
 #ifdef CONFIG_AML_LCD
@@ -104,10 +105,14 @@ static int do_hpd_detect(cmd_tbl_t *cmdtp, int flag, int argc,
 		printf("do_hpd_detect: colorattribute=%s\n", colorattribute);
 
 	if (st) {
-		setenv("outputmode", getenv("hdmimode"));
+		if (hdmimode)
+			setenv("outputmode", hdmimode);
 	} else {
-		setenv("outputmode", getenv("cvbsmode"));
+		cvbsmode = getenv("cvbsmode");
+		if (cvbsmode)
+			setenv("outputmode", cvbsmode);
 		setenv("hdmichecksum", "0x00000000");
+		setenv("hdmimode", "null");
 		run_command("saveenv", 0);
 	}
 	return st;
@@ -323,12 +328,12 @@ static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 				hdmitx_device.para->cs = HDMI_COLOR_FORMAT_444;
 				printf("set cs as %d\n", HDMI_COLOR_FORMAT_444);
 			}
-			break;
 			/* For VESA modes, should be RGB format */
 			if (hdmitx_device.vic >= HDMITX_VESA_OFFSET) {
 				hdmitx_device.para->cs = HDMI_COLOR_FORMAT_RGB;
 				hdmitx_device.para->cd = HDMI_COLOR_DEPTH_24B;
 			}
+			break;
 		}
 		hdmi_tx_set(&hdmitx_device);
 	}
@@ -478,7 +483,7 @@ static int getBestHdmiColorAttributes(struct rx_cap *pRXCap,
 		//2.user request LL mdoe && sink support LL mode
 		} else if (request_ll_mode() && (pRXCap->dv_info.ver == 1) &&
 			(pRXCap->dv_info.length == 0xB) && pRXCap->dv_info.low_latency == 1) {
-			printf("getBestHdmiColorAttributes: 4k LL dovi, COLOR_ATTR_YCBCR422_12BIT\n");
+			printf("getBestHdmiColorAttributes: non-4k LL dovi, COLOR_ATTR_YCBCR422_12BIT\n");
 			return COLOR_ATTR_YCBCR422_12BIT;
 		}
 		//std dovi
@@ -505,6 +510,7 @@ static int getBestHdmiColorAttributes(struct rx_cap *pRXCap,
 			printf("getBestHdmiColorAttributes: COLOR_ATTR_RGB_12BIT\n");
 			return COLOR_ATTR_RGB_12BIT;
 		}
+		break;
 	case HDMI_COLOR_DEPTH_30B:
 		if (inColorSpace == HDMI_COLOR_FORMAT_444) {
 			if ((pRXCap->dc_y444) && (pRXCap->dc_30bit)) {
@@ -521,6 +527,7 @@ static int getBestHdmiColorAttributes(struct rx_cap *pRXCap,
 			printf("getBestHdmiColorAttributes: COLOR_ATTR_RGB_10BIT\n");
 			return COLOR_ATTR_RGB_10BIT;
 		};
+		break;
 	default:
 		if (inColorSpace == HDMI_COLOR_FORMAT_444) {
 			if (pRXCap->support_ycbcr444_flag) {
@@ -536,10 +543,10 @@ static int getBestHdmiColorAttributes(struct rx_cap *pRXCap,
 				return COLOR_ATTR_YCBCR420_8BIT;
 			}
 		}
-		//default to rgb,8 bits always
-		printf("getBestHdmiColorAttributes: COLOR_ATTR_RGB_8BIT\n");
-		return COLOR_ATTR_RGB_8BIT;
 	}
+	//default to rgb,8 bits always
+	printf("getBestHdmiColorAttributes: COLOR_ATTR_RGB_8BIT\n");
+	return COLOR_ATTR_RGB_8BIT;
 }
 
 bool isYuv4kSink(struct rx_cap *pRXCap)
@@ -560,13 +567,13 @@ bool isYuv4kSink(struct rx_cap *pRXCap)
 	for (i = 0; i < pRXCap->VIC_count; i++) {
 		VIC = pRXCap->VIC[i];
 		if ((VIC == HDMI_3840x2160p60_16x9_Y420 ||
-		     VIC == HDMI_3840x2160p60_16x9_Y420) &&
+			VIC == HDMI_3840x2160p50_16x9_Y420) &&
 			maxTMDSRate >= 297) {
 			printf("isYuv4kSink: true, maxTMDSRate=%d\n", maxTMDSRate);
 			return true;
 		}
-		if ((VIC == HDMI_3840x2160p60_16x9  ||
-		     VIC == HDMI_3840x2160p60_16x9) &&
+		if  ((VIC == HDMI_3840x2160p60_16x9  ||
+			VIC == HDMI_3840x2160p50_16x9) &&
 			maxTMDSRate > 594) {
 			printf("isYuv4kSink: true, maxTMDSRate=%d\n", maxTMDSRate);
 			return true;
@@ -680,13 +687,42 @@ static int selectBestMode(struct rx_cap *pRXCap, bool isAuto, int manualMode)
 	return HDMI_1920x1080p60_16x9; //default
 }
 
+static void get_parse_edid_data(struct hdmitx_dev *hdev)
+{
+	unsigned char *edid = hdev->rawedid;
+	unsigned int byte_num = 0;
+	unsigned char blk_no = 1;
+	char *hdr_priority = getenv("hdr_priority");
+
+	/* get edid data */
+	while (byte_num < 128 * blk_no) {
+		hdev->HWOp.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128);
+		if (byte_num == 120) {
+			blk_no = edid[126] + 1;
+			if (blk_no > 4)
+				blk_no = 4; /* MAX Read Blocks 4 */
+		}
+		byte_num += 8;
+	}
+
+	if (0)
+		dump_full_edid(hdev->rawedid);
+
+	/* parse edid data */
+	hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap);
+
+	/* if hdr_priority is 1, then mark dv_info */
+	if (hdr_priority && (strcmp(hdr_priority, "1") == 0)) {
+		memset(&hdev->RXCap.dv_info, 0, sizeof(struct dv_info));
+		pr_info("hdr_priority: %s and clear dv_info\n", hdr_priority);
+	}
+}
+
 static int do_get_parse_edid(cmd_tbl_t * cmdtp, int flag, int argc,
 	char * const argv[])
 {
 	struct hdmitx_dev *hdev = &hdmitx_device;
-	unsigned int byte_num = 0;
 	unsigned char *edid = hdev->rawedid;
-	unsigned char blk_no = 1;
 	unsigned char *store_checkvalue;
 	memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO);
 	unsigned int i;
@@ -703,19 +739,7 @@ static int do_get_parse_edid(cmd_tbl_t * cmdtp, int flag, int argc,
 	int inColorSpace = -1, inColorDepth = -1;
 	int bestColorAttributes = -1;
 
-	while (byte_num < 128 * blk_no) {
-		hdmitx_device.HWOp.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128);
-		if (byte_num == 120) {
-			blk_no = edid[126] + 1;
-			if (blk_no > 4)
-				blk_no = 4; /* MAX Read Blocks 4 */
-		}
-		byte_num += 8;
-	}
-
-	if (hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap) == 0) {
-		dump_full_edid(hdev->rawedid);
-	}
+	get_parse_edid_data(hdev);
 
 	/*check if the tv has changed or anything wrong*/
 	//store_checkvalue = (unsigned char*)get_logoparam_value("logoparam.var.hdmi_crcvalue");
@@ -858,9 +882,7 @@ static int do_get_preferred_mode(cmd_tbl_t * cmdtp, int flag, int argc,
 	char * const argv[])
 {
 	struct hdmitx_dev *hdev = &hdmitx_device;
-	unsigned int byte_num = 0;
 	unsigned char *edid = hdev->rawedid;
-	unsigned char blk_no = 1;
 	struct hdmi_format_para *para;
 	char pref_mode[64];
 	char color_attr[64];
@@ -888,21 +910,8 @@ static int do_get_preferred_mode(cmd_tbl_t * cmdtp, int flag, int argc,
 		goto bypass_edid_read;
 	}
 
-	/* Read complete EDID data sequentially */
-	while (byte_num < 128 * blk_no) {
-		hdmitx_device.HWOp.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128);
-		if (byte_num == 120) {
-			blk_no = edid[126] + 1;
-			if (blk_no > 4)
-				blk_no = 4; /* MAX Read Blocks 4 */
-		}
-		byte_num += 8;
-	}
+	get_parse_edid_data(hdev);
 
-	if (hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap) == 0) {
-		if (0)
-			dump_full_edid(hdev->rawedid);
-	}
 	para = hdmi_get_fmt_paras(hdev->RXCap.preferred_mode);
 
 	if (para) {
@@ -996,8 +1005,5 @@ struct hdr_info *hdmitx_get_rx_hdr_info(void)
 {
 	struct hdmitx_dev *hdev = &hdmitx_device;
 
-	if (hdev)
-		return &hdev->RXCap.hdr_info;
-	else
-		return NULL;
+	return &hdev->RXCap.hdr_info;
 }
diff --git a/common/cmd_imgread.c b/common/cmd_imgread.c
index 95f131b..1d2326a 100644
--- a/common/cmd_imgread.c
+++ b/common/cmd_imgread.c
@@ -197,6 +197,7 @@ static int _aml_get_secure_boot_kernel_size(const void* pLoadaddr, unsigned* pTo
     return 0;
 }
 
+
 static int do_image_read_dtb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
     boot_img_hdr *hdr_addr = NULL;
@@ -361,14 +362,13 @@ static int do_image_read_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char * con
 
     //Check if encrypted image
 #ifndef CONFIG_SKIP_KERNEL_DTB_SECBOOT_CHECK
-	rc = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
+    rc = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
     if (rc) {
             errorP("Fail in _aml_get_secure_boot_kernel_size, rc=%d\n", rc);
             return __LINE__;
     }
 #endif /*CONFIG_SKIP_KERNEL_DTB_SECBOOT_CHECK*/
-
-	if (secureKernelImgSz)
+    if (secureKernelImgSz)
     {
         actualBootImgSz = secureKernelImgSz + nCheckOffset;
         MsgP("secureKernelImgSz=0x%x\n", actualBootImgSz);
diff --git a/common/cmd_osd.c b/common/cmd_osd.c
index 56d68ec..bf0deb7 100644
--- a/common/cmd_osd.c
+++ b/common/cmd_osd.c
@@ -261,12 +261,27 @@ static int do_osd_dual_logo(cmd_tbl_t *cmdtp, int flag, int argc,
 	printf("osd: hpd_state=%c\n", st ? '1' : '0');
 
 	if (st) {
-		/* hdmi plugin, dual logo display */
-	#if defined(CONFIG_DUAL_LOGO)
-		run_command(CONFIG_DUAL_LOGO, 0);
-	#else
-		printf("osd: dual logo cmd macro is not defined\n");
-	#endif
+		/* hdmi plugin, dual logo display
+		 * CONFIG_RECOVERY_DUAL_LOGO is given priority in recovery
+		 */
+		if (!strncmp(getenv("reboot_mode"), "factory_reset", 13)) {
+		#if defined(CONFIG_RECOVERY_DUAL_LOGO)
+			run_command(CONFIG_RECOVERY_DUAL_LOGO, 0);
+		#else
+		#if defined(CONFIG_DUAL_LOGO)
+			printf("osd: use dual logo cmd macro in recovery mode\n");
+			run_command(CONFIG_DUAL_LOGO, 0);
+		#else
+			printf("osd: dual logo cmd macro is not defined in recovery mode\n");
+		#endif
+		#endif
+		} else {
+		#if defined(CONFIG_DUAL_LOGO)
+			run_command(CONFIG_DUAL_LOGO, 0);
+		#else
+			printf("osd: dual logo cmd macro is not defined\n");
+		#endif
+		}
 	} else {
 		/* hdmi plugout, single logo display */
 	#if defined(CONFIG_SINGLE_LOGO)
diff --git a/common/hdmi_edid_parsing.c b/common/hdmi_edid_parsing.c
index 81837ec..148b643 100644
--- a/common/hdmi_edid_parsing.c
+++ b/common/hdmi_edid_parsing.c
@@ -117,7 +117,6 @@ static int check_dvi_hdmi_edid_valid(unsigned char *buf)
 #endif
 static void dump_dtd_info(struct dtd *t)
 {
-	return; /* debug only */
 	printk("%s[%d]\n", __func__, __LINE__);
 #define PR(a) pr_info("%s %d\n", #a, t->a)
 	PR(pixel_clock);
diff --git a/common/hdmi_parameters.c b/common/hdmi_parameters.c
index 91b1ce1..dc682d1 100644
--- a/common/hdmi_parameters.c
+++ b/common/hdmi_parameters.c
@@ -2126,6 +2126,7 @@ void hdmi_parse_attr(struct hdmi_format_para *para, char const *name)
 enum hdmi_vic hdmi_get_fmt_vic(char const *name)
 {
 	int i;
+	unsigned int name_len;
 	char *lname;
 	enum hdmi_vic vic = HDMI_unkown;
 	struct hdmi_format_para *para = NULL;
@@ -2147,7 +2148,10 @@ enum hdmi_vic hdmi_get_fmt_vic(char const *name)
 	if ((vic != HDMI_unkown) && (all_fmt_paras[i] != NULL)) {
 		para = all_fmt_paras[i];
 		memset(&para->ext_name[0], 0, sizeof(para->ext_name));
-		memcpy(&para->ext_name[0], name, strlen(name));
+		name_len = strlen(name);
+		if (name_len > sizeof(para->ext_name) - 1)
+			name_len = sizeof(para->ext_name) - 1;
+		memcpy(&para->ext_name[0], name, name_len);
 		hdmi_parse_attr(para, name);
 	}
 	return vic;
diff --git a/common/ini/model.c b/common/ini/model.c
index 956ed52..4aa8efe 100644
--- a/common/ini/model.c
+++ b/common/ini/model.c
@@ -49,7 +49,9 @@ static int model_debug_flag;
 static int gLcdDataCnt, gLcdExtDataCnt, gBlDataCnt;
 static int g_lcd_pwr_on_seq_cnt, g_lcd_pwr_off_seq_cnt;
 static int gLcdTconDataCnt;
-static int gLcdExtInitOnCnt, gLcdExtInitOffCnt;
+static int gLcdExtInitOnCnt, gLcdExtInitOffCnt, gLcdExtCmdSize;
+
+static int handle_tcon_ext_pmu_data(int index, unsigned char *buf);
 
 static int transBufferData(const char *data_str, unsigned int data_buf[]) {
 	int item_ind = 0;
@@ -167,7 +169,7 @@ static int handle_tcon_path(void)
 {
 	const char *ini_value = NULL;
 
-	ini_value = IniGetString("lcd_Path", "TCON_BIN_PATH", "null");
+	ini_value = IniGetString("tcon_Path", "TCON_BIN_PATH", "null");
 	if (strcmp(ini_value, "null") != 0)
 		setenv("model_tcon", ini_value);
 	else if (model_debug_flag & DEBUG_TCON)
@@ -191,6 +193,30 @@ static int handle_tcon_path(void)
 	else if (model_debug_flag & DEBUG_TCON)
 		ALOGE("%s, demura lut load file error!\n", __func__);
 
+	ini_value = IniGetString("tcon_Path", "TCON_EXT_B0_BIN_PATH", "null");
+	if (strcmp(ini_value, "null") != 0)
+		setenv("model_tcon_ext_b0", ini_value);
+	else if (model_debug_flag & DEBUG_TCON)
+		ALOGE("%s, tcon_ext_c0 bin load file error!\n", __func__);
+
+	ini_value = IniGetString("tcon_Path", "TCON_EXT_B1_BIN_PATH", "null");
+	if (strcmp(ini_value, "null") != 0)
+		setenv("model_tcon_ext_b1", ini_value);
+	else if (model_debug_flag & DEBUG_TCON)
+		ALOGE("%s, tcon_ext_c1 bin load file error!\n", __func__);
+
+	ini_value = IniGetString("tcon_Path", "TCON_EXT_B0_SPI_BIN_PATH", "null");
+	if (strcmp(ini_value, "null") != 0)
+		setenv("model_tcon_ext_b0_spi", ini_value);
+	else if (model_debug_flag & DEBUG_TCON)
+		ALOGE("%s, tcon_ext_b0_spi bin load file error!\n", __func__);
+
+	ini_value = IniGetString("tcon_Path", "TCON_EXT_B1_SPI_BIN_PATH", "null");
+	if (strcmp(ini_value, "null") != 0)
+		setenv("model_tcon_ext_b1_spi", ini_value);
+	else if (model_debug_flag & DEBUG_TCON)
+		ALOGE("%s, tcon_ext_b1_spi bin load file error!\n", __func__);
+
 	return 0;
 }
 
@@ -592,29 +618,97 @@ static int handle_lcd_ext_type(struct lcd_ext_attr_s *p_attr)
 		ALOGD("%s, value_9 is (%s)\n", __func__, ini_value);
 	p_attr->type.value_9 = strtoul(ini_value, NULL, 0);
 
+	if (p_attr->basic.ext_type == LCD_EXTERN_I2C)
+		gLcdExtCmdSize = p_attr->type.value_3;
+	else if (p_attr->basic.ext_type == LCD_EXTERN_SPI)
+		gLcdExtCmdSize = p_attr->type.value_6;
+	else
+		gLcdExtCmdSize = p_attr->type.value_9;
+
 	return 0;
 }
 
 static int handle_lcd_ext_cmd_data(struct lcd_ext_attr_s *p_attr)
 {
-	int i = 0, tmp_cnt = 0, tmp_off = 0;
+	int i = 0, j = 0, k, tmp_cnt = 0, tmp_off = 0;
 	const char *ini_value = NULL;
 	unsigned int tmp_buf[2048];
+	unsigned char *b0_data_buf, *b1_data_buf, *data_buf = NULL;
+	unsigned int data_size = 0;
 
-
+	/* orignal data in ini */
 	ini_value = IniGetString("lcd_ext_Attr", "init_on", "null");
 	if (model_debug_flag & DEBUG_LCD_EXTERN)
 		ALOGD("%s, init_on is (%s)\n", __func__, ini_value);
 	tmp_cnt = transBufferData(ini_value, tmp_buf);
+
+	b0_data_buf = (unsigned char *)malloc(LCD_EXTERN_INIT_ON_MAX);
+	if (b0_data_buf == NULL) {
+		ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+		return -1;
+	}
+
+	b1_data_buf = (unsigned char *)malloc(LCD_EXTERN_INIT_ON_MAX);
+	if (b1_data_buf == NULL) {
+		free(b0_data_buf);
+		b0_data_buf = NULL;
+		ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+		return -1;
+	}
+
+	/* data check and copy */
 	if (tmp_cnt > LCD_EXTERN_INIT_ON_MAX) {
-		printf("error: %s: invalid init_on data\n", __func__);
+		ALOGE("%s: invalid init_on data\n", __func__);
 		p_attr->cmd_data[0] = LCD_EXTERN_INIT_END;
 		p_attr->cmd_data[1] = 0;
 		gLcdExtInitOnCnt = 2;
 	} else {
-		for (i = 0; i < tmp_cnt; i++)
-			p_attr->cmd_data[i] = tmp_buf[i];
-		gLcdExtInitOnCnt = tmp_cnt;
+		if (gLcdExtCmdSize == 0xff) {
+			handle_tcon_ext_pmu_data(0, b0_data_buf);
+			handle_tcon_ext_pmu_data(1, b1_data_buf);
+			i = 0;
+			j = 0;
+			while (i < tmp_cnt) {
+				p_attr->cmd_data[j] = tmp_buf[i];
+				if (p_attr->cmd_data[j] == LCD_EXTERN_INIT_END) {
+					p_attr->cmd_data[j + 1] = 0;
+					j += 2;
+					break;
+				}
+				data_buf = NULL;
+				if (p_attr->cmd_data[j] == 0xb0) {
+					if (b0_data_buf) {
+						if (b0_data_buf[0]) /* data size valid */
+							data_buf = b0_data_buf;
+					}
+				} else if (p_attr->cmd_data[j] == 0xb1) {
+					if (b1_data_buf) {
+						if (b1_data_buf[0]) /* data size valid */
+							data_buf = b1_data_buf;
+					}
+				}
+				if (data_buf) { /* bin data */
+					data_size = data_buf[0];
+					p_attr->cmd_data[j + 1] = data_size;
+					memcpy(&p_attr->cmd_data[j + 2],
+						&data_buf[1], data_size);
+				} else { /* orignal ini data */
+					data_size = tmp_buf[i + 1];
+					p_attr->cmd_data[j + 1] = data_size;
+					for (k = 0; k < data_size; k++) {
+						p_attr->cmd_data[j + 2 + k] =
+							(unsigned char)tmp_buf[i + 2 +k];
+					}
+				}
+				j += data_size + 2;
+				i += tmp_buf[i + 1] + 2; /* raw data */
+			}
+			gLcdExtInitOnCnt = j;
+		} else {
+			for (i = 0; i < tmp_cnt; i++)
+				p_attr->cmd_data[i] = tmp_buf[i];
+			gLcdExtInitOnCnt = tmp_cnt;
+		}
 	}
 
 	tmp_off = gLcdExtInitOnCnt;
@@ -622,8 +716,8 @@ static int handle_lcd_ext_cmd_data(struct lcd_ext_attr_s *p_attr)
 	if (model_debug_flag & DEBUG_LCD_EXTERN)
 		ALOGD("%s, init_off is (%s)\n", __func__, ini_value);
 	tmp_cnt = transBufferData(ini_value, tmp_buf);
-	if (tmp_cnt > LCD_EXTERN_INIT_ON_MAX) {
-		printf("error: %s: invalid init_off data\n", __func__);
+	if (tmp_cnt > LCD_EXTERN_INIT_OFF_MAX) {
+		ALOGE("%s: invalid init_off data\n", __func__);
 		p_attr->cmd_data[tmp_off+0] = LCD_EXTERN_INIT_END;
 		p_attr->cmd_data[tmp_off+1] = 0;
 		gLcdExtInitOnCnt = 2;
@@ -633,14 +727,22 @@ static int handle_lcd_ext_cmd_data(struct lcd_ext_attr_s *p_attr)
 		gLcdExtInitOffCnt = tmp_cnt;
 	}
 
-#if 0
-	for (i = 0; i < gLcdExtInitOnCnt; i++)
-		ALOGD("%s, init_on_data[%d] = 0x%02x\n", __func__, i, p_attr->cmd_data[i]);
+	if (model_debug_flag & DEBUG_LCD_EXTERN) {
+		ALOGD("%s, init_on_data:\n", __func__);
+		for (i = 0; i < gLcdExtInitOnCnt; i++) {
+			printf("  [%d] = 0x%02x\n", i, p_attr->cmd_data[i]);
+		}
 
-	for (i = 0; i < gLcdExtInitOffCnt; i++)
-		ALOGD("%s, init_off_data[%d] = 0x%02x\n", __func__, i, p_attr->cmd_data[tmp_off+i]);
-#endif
+		ALOGD("%s, init_off_data:\n", __func__);
+		for (i = 0; i < gLcdExtInitOffCnt; i++) {
+			ALOGD("  [%d] = 0x%02x\n", i, p_attr->cmd_data[tmp_off+i]);
+		}
+	}
 
+	free(b0_data_buf);
+	b0_data_buf = NULL;
+	free(b1_data_buf);
+	b1_data_buf = NULL;
 	return 0;
 }
 
@@ -1273,6 +1375,73 @@ static int handle_tcon_bin(void)
 	return 0;
 }
 
+static int handle_tcon_ext_pmu_data(int index, unsigned char *buf)
+{
+	char *file_name, str[2][30];
+	unsigned int data_size = 0, i, file_find = 0;
+
+	if (!buf) {
+		ALOGE("%s, buf is null\n", __func__);
+		return -1;
+	}
+	buf[0] = 0; /* init invalid data */
+	i = 0;
+
+	if (index == 0) {
+		sprintf(str[0], "model_tcon_ext_b0_spi");
+		sprintf(str[1], "model_tcon_ext_b0");
+	} else {
+		sprintf(str[0], "model_tcon_ext_b1_spi");
+		sprintf(str[1], "model_tcon_ext_b1");
+	}
+
+	while (i < 2) {
+		file_name = getenv(str[i]);
+		if (file_name == NULL) {
+			if (model_debug_flag & DEBUG_NORMAL)
+				ALOGD("%s: no %s path\n", __func__, str[i]);
+		} else {
+			if (iniIsFileExist(file_name)) {
+				if (model_debug_flag & DEBUG_NORMAL)
+					ALOGD("%s: %s: %s\n", __func__, str[i], file_name);
+				file_find = 1;
+				break;
+			}
+			if (model_debug_flag & DEBUG_NORMAL) {
+				ALOGE("%s: %s: \"%s\" not exist.\n",
+					__func__, str[i], file_name);
+			}
+		}
+		i++;
+	}
+	if (file_find == 0)
+		return -1;
+
+	data_size = read_bin_file(file_name, LCD_EXTERN_INIT_ON_MAX);
+	if (data_size == 0) {
+		ALOGE("%s, %s data_size %d error!\n", __func__, str[i], data_size);
+		return -1;
+	}
+
+	buf[0] = (data_size + 1); /* data size include reg start */
+	buf[1] = 0x00;            /* reg start */
+	GetBinData(&buf[2], data_size);
+
+	if (model_debug_flag & DEBUG_LCD_EXTERN) {
+		ALOGD("%s: %s:\n", __func__, str[i]);
+		for (i = 0; i < (data_size + 2); i++)
+			printf(" 0x%02x", buf[i]);
+		printf("\n");
+	}
+
+	if (model_debug_flag & DEBUG_NORMAL)
+		ALOGD("%s %s finish\n", __func__, str[i]);
+
+	BinFileUninit();
+
+	return 0;
+}
+
 #define TCON_VAC_SET_PARAM_NUM    3
 #define TCON_VAC_LUT_PARAM_NUM    256
 int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size)
@@ -1314,12 +1483,13 @@ int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size)
 	if (model_debug_flag & DEBUG_TCON)
 		ALOGD("vac_data addr: 0x%p\n", vac_data);
 
-	n = 0;
+	n = 8;
 	len = TCON_VAC_SET_PARAM_NUM;
 
 	ini_value = IniGetString("lcd_tcon_vac", "vac_set", "null");
 	tmp_cnt = transBufferData(ini_value, tmp_buf);
 	data_cnt = tmp_cnt;
+
 	if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
 		ALOGE("%s: invalid vac_set data cnt %d\n", __func__, tmp_cnt);
 		return -1;
@@ -1334,15 +1504,15 @@ int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size)
 		vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
 		if (model_debug_flag & DEBUG_TCON) {
 			ALOGD("vac_set: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
-				vac_data[n+i*2], vac_data[n+i*2+1],
-				tmp_buf[i]);
+			      vac_data[n+i*2], vac_data[n+i*2+1],
+			      tmp_buf[i]);
 		}
 	}
 
 	len = TCON_VAC_LUT_PARAM_NUM;
 
 	ini_value = IniGetString("lcd_tcon_vac", "vac_ramt1", "null");
-	tmp_cnt = transBufferData(ini_value, tmp_buf);
+		tmp_cnt = transBufferData(ini_value, tmp_buf);
 	data_cnt += tmp_cnt;
 	if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
 		ALOGE("%s: invalid vac_ramt1 data cnt %d\n", __func__, tmp_cnt);
@@ -1365,7 +1535,7 @@ int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size)
 	}
 
 	ini_value = IniGetString("lcd_tcon_vac", "vac_ramt2", "null");
-	tmp_cnt = transBufferData(ini_value, tmp_buf);
+		tmp_cnt = transBufferData(ini_value, tmp_buf);
 	data_cnt += tmp_cnt;
 	if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
 		ALOGE("%s: invalid vac_ramt2 data cnt %d\n", __func__, tmp_cnt);
@@ -1518,11 +1688,23 @@ int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size)
 		vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
 		if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
 			ALOGD("vac_ramt3_6_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
-				vac_data[n+i*2], vac_data[n+i*2+1],
-				tmp_buf[i]);
+			      vac_data[n+i*2], vac_data[n+i*2+1],
+			      tmp_buf[i]);
 		}
 	}
 
+	/*add check data: total_size(4byte) + crc(4byte) +
+	 *crc todo
+	*/
+	vac_data[0] = data_cnt & 0xff;
+	vac_data[1] = (data_cnt >> 8) & 0xff;
+	vac_data[2] = (data_cnt >> 16) & 0xff;
+	vac_data[3] = (data_cnt >> 24) & 0xff;
+	vac_data[4] = 0;
+	vac_data[5] = 0;
+	vac_data[6] = 0;
+	vac_data[7] = 0;
+
 	if (model_debug_flag & DEBUG_NORMAL)
 		ALOGD("%s finish\n", __func__);
 
@@ -1535,6 +1717,7 @@ int handle_tcon_demura_set(unsigned char *demura_set_data,
 {
 	unsigned long int bin_size;
 	char *file_name;
+	int n;
 
 	file_name = getenv("model_tcon_demura_set");
 	if (file_name == NULL) {
@@ -1562,7 +1745,16 @@ int handle_tcon_demura_set(unsigned char *demura_set_data,
 		return -1;
 	}
 
-	GetBinData(demura_set_data, bin_size);
+	n = 8;
+	demura_set_data[0] = bin_size & 0xff;
+	demura_set_data[1] = (bin_size >> 8) & 0xff;
+	demura_set_data[2] = (bin_size >> 16) & 0xff;
+	demura_set_data[3] = (bin_size >> 24) & 0xff;
+	demura_set_data[4] = 0;
+	demura_set_data[5] = 0;
+	demura_set_data[6] = 0;
+	demura_set_data[7] = 0;
+	GetBinData(&demura_set_data[n], bin_size);
 
 	if (model_debug_flag & DEBUG_NORMAL)
 		ALOGD("%s finish\n", __func__);
@@ -1577,6 +1769,7 @@ int handle_tcon_demura_lut(unsigned char *demura_lut_data,
 {
 	unsigned long int bin_size;
 	char *file_name;
+	int n;
 
 	file_name = getenv("model_tcon_demura_lut");
 	if (file_name == NULL) {
@@ -1604,10 +1797,19 @@ int handle_tcon_demura_lut(unsigned char *demura_lut_data,
 		return -1;
 	}
 
-	GetBinData(demura_lut_data, bin_size);
+	n = 8;
+	demura_lut_data[0] = bin_size & 0xff;
+	demura_lut_data[1] = (bin_size >> 8) & 0xff;
+	demura_lut_data[2] = (bin_size >> 16) & 0xff;
+	demura_lut_data[3] = (bin_size >> 24) & 0xff;
+	demura_lut_data[4] = 0;
+	demura_lut_data[5] = 0;
+	demura_lut_data[6] = 0;
+	demura_lut_data[7] = 0;
+	GetBinData(&demura_lut_data[n], bin_size);
 
-	if (model_debug_flag & DEBUG_NORMAL)
-		ALOGD("%s finish\n", __func__);
+	if (model_debug_flag)
+		ALOGD("%s finish, bin_size = 0x%lx\n", __func__, bin_size);
 
 	BinFileUninit();
 
diff --git a/common/partitions.c b/common/partitions.c
index 286a30c..7179ef1 100644
--- a/common/partitions.c
+++ b/common/partitions.c
@@ -122,6 +122,7 @@ int get_partition_from_dts(unsigned char *buffer)
 		parts_total_num = be32_to_cpup((u32*)parts_num);
 	}
 	dynamic_partition = false;
+	setenv("partiton_mode","normal");
 	for (index = 0; index < be32_to_cpup((u32*)parts_num); index++)
 	{
 		sprintf(propname,"part-%d", index);
@@ -167,6 +168,7 @@ int get_partition_from_dts(unsigned char *buffer)
 
 		if (strcmp(uname, "super") == 0) {
 			dynamic_partition = true;
+			setenv("partiton_mode","dynamic");
 			printf("enable dynamic_partition\n");
 		}
 	}
diff --git a/common/store_interface.c b/common/store_interface.c
index 4179a1c..f152877 100644
--- a/common/store_interface.c
+++ b/common/store_interface.c
@@ -74,7 +74,6 @@ extern unsigned emmc_cur_partition;
 extern int mmc_ddr_parameter_read(unsigned char *buf, unsigned int size);
 extern int mmc_ddr_parameter_write(unsigned char *buf, unsigned int size);
 extern int mmc_ddr_parameter_erase(void);
-extern int is_dtb_encrypt(unsigned char *buffer);
 
 #define debugP(fmt...) //printf("Dbg[store]L%d:", __LINE__),printf(fmt)
 #define MsgP(fmt...)   printf("[store]"fmt)
@@ -388,27 +387,25 @@ static int do_store_dtb_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const
 		ret = run_command(_cmdBuf, 0);
 
 		unsigned long dtImgAddr = simple_strtoul(dtbLoadaddr, NULL, 16);
-		if (is_dtb_encrypt(NULL)) {
-			//
-			//ONLY need decrypting when 'store dtb read'
-			if (!strcmp("read", argv[2]))
-			{
-				flush_cache(dtImgAddr, AML_DTB_IMG_MAX_SZ);
+		//
+		//ONLY need decrypting when 'store dtb read'
+	   if (!strcmp("read", argv[2]))
+	   {
+		   flush_cache(dtImgAddr, AML_DTB_IMG_MAX_SZ);
 #ifndef CONFIG_SKIP_KERNEL_DTB_SECBOOT_CHECK
-				ret = aml_sec_boot_check(AML_D_P_IMG_DECRYPT, dtImgAddr, AML_DTB_IMG_MAX_SZ, 0);
-				if (ret) {
-					MsgP("decrypt dtb: Sig Check %d\n",ret);
-					return ret;
-				}
+
+		   ret = aml_sec_boot_check(AML_D_P_IMG_DECRYPT, dtImgAddr, AML_DTB_IMG_MAX_SZ, 0);
+		   if (ret) {
+			   MsgP("decrypt dtb: Sig Check %d\n",ret);
+			   return ret;
+		   }
 #endif
-			}
-		}
-		if (!is_write && strcmp("iread", argv[2]))
-		{
-			ulong nCheckOffset = 0;
-#ifndef CONFIG_SKIP_KERNEL_DTB_SECBOOT_CHECK
+	   }
+
+	   if (!is_write && strcmp("iread", argv[2]))
+	   {
+			ulong nCheckOffset;
 			nCheckOffset = aml_sec_boot_check(AML_D_Q_IMG_SIG_HDR_SIZE,GXB_IMG_LOAD_ADDR,GXB_EFUSE_PATTERN_SIZE,GXB_IMG_DEC_ALL);
-#endif
 			if (AML_D_Q_IMG_SIG_HDR_SIZE == (nCheckOffset & 0xFFFF))
 				nCheckOffset = (nCheckOffset >> 16) & 0xFFFF;
 			else
@@ -1137,7 +1134,8 @@ E_SWITCH_BACK:
 		else if(device_boot_flag==EMMC_BOOT_FLAG){
 			store_dbg("MMC BOOT,erase data : %s %d  off =%llx ,size=%llx",__func__,__LINE__, off, size);
 			off = size =0;
-			ret = run_command("amlmmc erase 1",0); //whole
+			MsgP("amlmmc erase non_loader\n");
+			ret = run_command("amlmmc erase non_loader",0); //whole
 			if (ret != 0) {
 				store_msg("amlmmc cmd %s failed ",cmd);
 				return -1;
diff --git a/drivers/display/lcd/aml_lcd_clk_config.c b/drivers/display/lcd/aml_lcd_clk_config.c
index 5362123..17661d5 100644
--- a/drivers/display/lcd/aml_lcd_clk_config.c
+++ b/drivers/display/lcd/aml_lcd_clk_config.c
@@ -38,6 +38,7 @@ static struct lcd_clk_config_s clk_conf = { /* unit: kHz */
 	.pll_od3_sel = 0,
 	.pll_tcon_div_sel = 0,
 	.pll_level = 0,
+	.pll_frac_half_shift = 0,
 	.ss_level = 0,
 	.ss_freq = 0,
 	.ss_mode = 0,
@@ -60,6 +61,29 @@ struct lcd_clk_config_s *get_lcd_clk_config(void)
 /* **********************************
  * lcd controller operation
  * ********************************** */
+static unsigned int error_abs(unsigned int a, unsigned int b)
+{
+	if (a >= b)
+		return (a - b);
+	else
+		return (b - a);
+}
+
+#define PLL_CLK_CHECK_MAX    2 /* MHz */
+static int lcd_clk_msr_check(struct lcd_clk_config_s *cConf)
+{
+	unsigned int encl_clk_msr;
+
+	encl_clk_msr = clk_util_clk_msr(9);
+	if (error_abs((cConf->fout / 1000), encl_clk_msr) >= PLL_CLK_CHECK_MAX) {
+		LCDERR("%s: expected:%d, msr:%d\n",
+			__func__, (cConf->fout / 1000), encl_clk_msr);
+		return -1;
+	}
+
+	return 0;
+}
+
 static int lcd_pll_wait_lock(unsigned int reg, unsigned int lock_bit)
 {
 	unsigned int pll_lock;
@@ -75,6 +99,7 @@ static int lcd_pll_wait_lock(unsigned int reg, unsigned int lock_bit)
 		ret = -1;
 	LCDPR("%s: pll_lock=%d, wait_loop=%d\n",
 		__func__, pll_lock, (PLL_WAIT_LOCK_CNT - wait_loop));
+
 	return ret;
 }
 
@@ -133,6 +158,7 @@ static int lcd_pll_wait_lock_g12a(int path)
 pll_lock_end_g12a:
 	LCDPR("%s: path=%d, pll_lock=%d, wait_loop=%d\n",
 		__func__, path, pll_lock, (PLL_WAIT_LOCK_CNT_G12A - wait_loop));
+
 	return ret;
 }
 
@@ -250,7 +276,7 @@ set_pll_retry_txl:
 	lcd_hiu_write(HHI_HPLL_CNTL, pll_ctrl);
 	lcd_hiu_write(HHI_HPLL_CNTL2, pll_ctrl2);
 	lcd_hiu_write(HHI_HPLL_CNTL3, pll_ctrl3);
-	if (cConf->pll_mode)
+	if (cConf->pll_mode & LCD_PLL_MODE_SPECIAL_CNTL)
 		lcd_hiu_write(HHI_HPLL_CNTL4, 0x0d160000);
 	else
 		lcd_hiu_write(HHI_HPLL_CNTL4, 0x0c8e0000);
@@ -883,14 +909,6 @@ static void lcd_set_tcon_clk_tl1(struct lcd_config_s *pconf)
  * lcd clk parameters calculate
  * ****************************************************
  */
-static int error_abs(int a, int b)
-{
-	if (a >= b)
-		return (a - b);
-	else
-		return (b - a);
-}
-
 static unsigned int clk_vid_pll_div_calc(unsigned int clk,
 		unsigned int div_sel, int dir)
 {
@@ -1314,7 +1332,7 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf,
 	unsigned int m, n;
 	unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3;
 	unsigned int pll_fod2_in, pll_fod3_in, pll_fvco;
-	unsigned int od_fb = 0, pll_frac;
+	unsigned int od_fb = 0, frac_range, pll_frac;
 	int done;
 
 	done = 0;
@@ -1322,6 +1340,7 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf,
 		(pll_fout < data->pll_out_fmin)) {
 		return done;
 	}
+	frac_range = data->pll_frac_range;
 	for (od3_sel = data->pll_od_sel_max; od3_sel > 0; od3_sel--) {
 		od3 = od_table[od3_sel - 1];
 		pll_fod3_in = pll_fout * od3;
@@ -1351,7 +1370,16 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf,
 				pll_fvco = pll_fvco / od_fb_table[od_fb];
 				m = pll_fvco / cConf->fin;
 				pll_frac = (pll_fvco % cConf->fin) *
-					data->pll_frac_range / cConf->fin;
+					frac_range / cConf->fin;
+				if (cConf->pll_mode & LCD_PLL_MODE_FRAC_SHIFT) {
+					if ((pll_frac == (frac_range >> 1)) ||
+						(pll_frac == (frac_range >> 2))) {
+						pll_frac |= 0x66;
+						cConf->pll_frac_half_shift = 1;
+					} else {
+						cConf->pll_frac_half_shift = 0;
+					}
+				}
 				cConf->pll_m = m;
 				cConf->pll_n = n;
 				cConf->pll_frac = pll_frac;
@@ -1386,6 +1414,15 @@ static int check_pll_vco(struct lcd_clk_config_s *cConf, unsigned int pll_fvco)
 	pll_fvco = pll_fvco / od_fb_table[od_fb];
 	m = pll_fvco / cConf->fin;
 	pll_frac = (pll_fvco % cConf->fin) * data->pll_frac_range / cConf->fin;
+	if (cConf->pll_mode & LCD_PLL_MODE_FRAC_SHIFT) {
+		if ((pll_frac == (data->pll_frac_range >> 1)) ||
+			(pll_frac == (data->pll_frac_range >> 2))) {
+			pll_frac |= 0x66;
+			cConf->pll_frac_half_shift = 1;
+		} else {
+			cConf->pll_frac_half_shift = 0;
+		}
+	}
 	cConf->pll_m = m;
 	cConf->pll_n = n;
 	cConf->pll_frac = pll_frac;
@@ -1464,10 +1501,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf)
 
 	bit_rate = pconf->lcd_timing.bit_rate / 1000;
 
-	if (pconf->lcd_timing.clk_auto == 2)
-		cConf->pll_mode = 1;
-	else
-		cConf->pll_mode = 0;
+	cConf->pll_mode = pconf->lcd_timing.clk_auto;
 
 	switch (pconf->lcd_basic.lcd_type) {
 	case LCD_TTL:
@@ -1692,7 +1726,8 @@ generate_clk_done_txl:
 			(cConf->div_sel << DIV_CTRL_DIV_SEL) |
 			(cConf->xd << DIV_CTRL_XD);
 		pconf->lcd_timing.clk_ctrl =
-			(cConf->pll_frac << CLK_CTRL_FRAC);
+			(cConf->pll_frac << CLK_CTRL_FRAC) |
+			(cConf->pll_frac_half_shift << CLK_CTRL_FRAC_SHIFT);
 	} else {
 		pconf->lcd_timing.pll_ctrl =
 			(1 << PLL_CTRL_OD1) |
@@ -1713,7 +1748,7 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf)
 	unsigned int pll_fout;
 	unsigned int clk_div_in, clk_div_out, clk_div_sel;
 	unsigned int od1, od2, od3, pll_fvco;
-	unsigned int m, n, od_fb, frac, offset, temp;
+	unsigned int m, n, od_fb, frac_range, frac, offset, temp;
 	struct lcd_clk_config_s *cConf = get_lcd_clk_config();
 
 	cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
@@ -1723,6 +1758,7 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf)
 	od3 = od_table[cConf->pll_od3_sel];
 	m = cConf->pll_m;
 	n = cConf->pll_n;
+	frac_range = cConf->data->pll_frac_range;
 
 	if (lcd_debug_print_flag == 2) {
 		LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n",
@@ -1789,8 +1825,17 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf)
 			__func__, temp);
 		return;
 	}
-	frac = temp * cConf->data->pll_frac_range * n / cConf->fin;
-	cConf->pll_frac = frac | (offset << 11);
+	frac = temp * frac_range * n / cConf->fin;
+	if (cConf->pll_mode & LCD_PLL_MODE_FRAC_SHIFT) {
+		if ((frac == (frac_range >> 1)) ||
+			(frac == (frac_range >> 2))) {
+			frac |= 0x66;
+			cConf->pll_frac_half_shift = 1;
+		} else {
+			cConf->pll_frac_half_shift = 0;
+		}
+	}
+	cConf->pll_frac = frac | (offset << cConf->data->pll_frac_sign_bit);
 	if (lcd_debug_print_flag)
 		LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac);
 }
@@ -2253,25 +2298,25 @@ static void lcd_clk_config_init_print_dft(void)
 	struct lcd_clk_data_s *data = clk_conf.data;
 
 	LCDPR("lcd clk config:\n"
-		"pll_m_max:         %d\n"
-		"pll_m_min:         %d\n"
-		"pll_n_max:         %d\n"
-		"pll_n_min:         %d\n"
-		"pll_od_fb:         %d\n"
-		"pll_frac_range:    %d\n"
-		"pll_od_sel_max:    %d\n"
-		"pll_ref_fmax:      %d\n"
-		"pll_ref_fmin:      %d\n"
-		"pll_vco_fmax:      %d\n"
-		"pll_vco_fmin:      %d\n"
-		"pll_out_fmax:      %d\n"
-		"pll_out_fmin:      %d\n"
-		"div_in_fmax:       %d\n"
-		"div_out_fmax:      %d\n"
-		"xd_out_fmax:       %d\n"
-		"ss_level_max:      %d\n"
-		"ss_freq_max:       %d\n"
-		"ss_mode_max:       %d\n\n",
+		"pll_m_max:           %d\n"
+		"pll_m_min:           %d\n"
+		"pll_n_max:           %d\n"
+		"pll_n_min:           %d\n"
+		"pll_od_fb:           %d\n"
+		"pll_frac_range:      %d\n"
+		"pll_od_sel_max:      %d\n"
+		"pll_ref_fmax:        %d\n"
+		"pll_ref_fmin:        %d\n"
+		"pll_vco_fmax:        %d\n"
+		"pll_vco_fmin:        %d\n"
+		"pll_out_fmax:        %d\n"
+		"pll_out_fmin:        %d\n"
+		"div_in_fmax:         %d\n"
+		"div_out_fmax:        %d\n"
+		"xd_out_fmax:         %d\n"
+		"ss_level_max:        %d\n"
+		"ss_freq_max:         %d\n"
+		"ss_mode_max:         %d\n\n",
 		data->pll_m_max, data->pll_m_min,
 		data->pll_n_max, data->pll_n_min,
 		data->pll_od_fb, data->pll_frac_range,
@@ -2318,24 +2363,26 @@ static void lcd_clk_config_init_print_axg(void)
 static void lcd_clk_config_print_dft(void)
 {
 	LCDPR("lcd clk config:\n"
-		"pll_mode:         %d\n"
-		"pll_m:            %d\n"
-		"pll_n:            %d\n"
-		"pll_frac:         0x%03x\n"
-		"pll_fvco:         %dkHz\n"
-		"pll_od1:          %d\n"
-		"pll_od2:          %d\n"
-		"pll_od3:          %d\n"
-		"pll_tcon_div_sel: %d\n"
-		"pll_out:          %dkHz\n"
-		"div_sel:          %s(index %d)\n"
-		"xd:               %d\n"
-		"fout:             %dkHz\n"
-		"ss_level:         %d\n"
-		"ss_freq:          %d\n"
-		"ss_mode:          %d\n\n",
+		"pll_mode:             %d\n"
+		"pll_m:                %d\n"
+		"pll_n:                %d\n"
+		"pll_frac:             0x%03x\n"
+		"pll_frac_half_shift:  %d\n"
+		"pll_fvco:             %dkHz\n"
+		"pll_od1:              %d\n"
+		"pll_od2:              %d\n"
+		"pll_od3:              %d\n"
+		"pll_tcon_div_sel:     %d\n"
+		"pll_out:              %dkHz\n"
+		"div_sel:              %s(index %d)\n"
+		"xd:                   %d\n"
+		"fout:                 %dkHz\n"
+		"ss_level:             %d\n"
+		"ss_freq:              %d\n"
+		"ss_mode:              %d\n\n",
 		clk_conf.pll_mode, clk_conf.pll_m, clk_conf.pll_n,
-		clk_conf.pll_frac, clk_conf.pll_fvco,
+		clk_conf.pll_frac, clk_conf.pll_frac_half_shift,
+		clk_conf.pll_fvco,
 		clk_conf.pll_od1_sel, clk_conf.pll_od2_sel,
 		clk_conf.pll_od3_sel, clk_conf.pll_tcon_div_sel,
 		clk_conf.pll_fout,
@@ -2554,16 +2601,28 @@ void lcd_clk_update(struct lcd_config_s *pconf)
 /* for timing change */
 void lcd_clk_set(struct lcd_config_s *pconf)
 {
+	int cnt = 0;
+
 	if (clk_conf.data == NULL) {
 		LCDERR("%s: clk config data is null\n", __func__);
 		return;
 	}
+
+lcd_clk_set_retry:
 	if (clk_conf.data->clk_set)
 		clk_conf.data->clk_set(pconf);
 
 	lcd_set_vclk_crt(pconf->lcd_basic.lcd_type, &clk_conf);
 	mdelay(10);
 
+	while (lcd_clk_msr_check(&clk_conf)) {
+		if (cnt++ >= 10) {
+			LCDERR("%s timeout\n", __func__);
+			break;
+		}
+		goto lcd_clk_set_retry;
+	}
+
 	if (lcd_debug_print_flag)
 		LCDPR("%s\n", __func__);
 }
@@ -2633,6 +2692,7 @@ static struct lcd_clk_data_s lcd_clk_data_gxtvbb = {
 	.pll_n_max = PLL_N_MAX_GXTVBB,
 	.pll_n_min = PLL_N_MIN_GXTVBB,
 	.pll_frac_range = PLL_FRAC_RANGE_GXTVBB,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_GXTVBB,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_GXTVBB,
 	.pll_ref_fmax = PLL_FREF_MAX_GXTVBB,
 	.pll_ref_fmin = PLL_FREF_MIN_GXTVBB,
@@ -2671,6 +2731,7 @@ static struct lcd_clk_data_s lcd_clk_data_gxl = {
 	.pll_n_max = PLL_N_MAX_GXL,
 	.pll_n_min = PLL_N_MIN_GXL,
 	.pll_frac_range = PLL_FRAC_RANGE_GXL,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_GXL,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_GXL,
 	.pll_ref_fmax = PLL_FREF_MAX_GXL,
 	.pll_ref_fmin = PLL_FREF_MIN_GXL,
@@ -2709,6 +2770,7 @@ static struct lcd_clk_data_s lcd_clk_data_txl = {
 	.pll_n_max = PLL_N_MAX_TXL,
 	.pll_n_min = PLL_N_MIN_TXL,
 	.pll_frac_range = PLL_FRAC_RANGE_TXL,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TXL,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_TXL,
 	.pll_ref_fmax = PLL_FREF_MAX_TXL,
 	.pll_ref_fmin = PLL_FREF_MIN_TXL,
@@ -2747,6 +2809,7 @@ static struct lcd_clk_data_s lcd_clk_data_txlx = {
 	.pll_n_max = PLL_N_MAX_TXLX,
 	.pll_n_min = PLL_N_MIN_TXLX,
 	.pll_frac_range = PLL_FRAC_RANGE_TXLX,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TXLX,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_TXLX,
 	.pll_ref_fmax = PLL_FREF_MAX_TXLX,
 	.pll_ref_fmin = PLL_FREF_MIN_TXLX,
@@ -2785,6 +2848,7 @@ static struct lcd_clk_data_s lcd_clk_data_axg = {
 	.pll_n_max = PLL_N_MAX_AXG,
 	.pll_n_min = PLL_N_MIN_AXG,
 	.pll_frac_range = PLL_FRAC_RANGE_AXG,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_AXG,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_AXG,
 	.pll_ref_fmax = PLL_FREF_MAX_AXG,
 	.pll_ref_fmin = PLL_FREF_MIN_AXG,
@@ -2823,6 +2887,7 @@ static struct lcd_clk_data_s lcd_clk_data_txhd = {
 	.pll_n_max = PLL_N_MAX_TXHD,
 	.pll_n_min = PLL_N_MIN_TXHD,
 	.pll_frac_range = PLL_FRAC_RANGE_TXHD,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TXHD,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_TXHD,
 	.pll_ref_fmax = PLL_FREF_MAX_TXHD,
 	.pll_ref_fmin = PLL_FREF_MIN_TXHD,
@@ -2861,6 +2926,7 @@ static struct lcd_clk_data_s lcd_clk_data_g12a_path0 = {
 	.pll_n_max = PLL_N_MAX_G12A,
 	.pll_n_min = PLL_N_MIN_G12A,
 	.pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_HPLL_G12A,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A,
 	.pll_ref_fmax = PLL_FREF_MAX_G12A,
 	.pll_ref_fmin = PLL_FREF_MIN_G12A,
@@ -2899,6 +2965,7 @@ static struct lcd_clk_data_s lcd_clk_data_g12a_path1 = {
 	.pll_n_max = PLL_N_MAX_G12A,
 	.pll_n_min = PLL_N_MIN_G12A,
 	.pll_frac_range = PLL_FRAC_RANGE_GP0_G12A,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_GP0_G12A,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A,
 	.pll_ref_fmax = PLL_FREF_MAX_G12A,
 	.pll_ref_fmin = PLL_FREF_MIN_G12A,
@@ -2937,6 +3004,7 @@ static struct lcd_clk_data_s lcd_clk_data_g12b_path0 = {
 	.pll_n_max = PLL_N_MAX_G12A,
 	.pll_n_min = PLL_N_MIN_G12A,
 	.pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_HPLL_G12A,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A,
 	.pll_ref_fmax = PLL_FREF_MAX_G12A,
 	.pll_ref_fmin = PLL_FREF_MIN_G12A,
@@ -2975,6 +3043,7 @@ static struct lcd_clk_data_s lcd_clk_data_g12b_path1 = {
 	.pll_n_max = PLL_N_MAX_G12A,
 	.pll_n_min = PLL_N_MIN_G12A,
 	.pll_frac_range = PLL_FRAC_RANGE_GP0_G12A,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_GP0_G12A,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A,
 	.pll_ref_fmax = PLL_FREF_MAX_G12A,
 	.pll_ref_fmin = PLL_FREF_MIN_G12A,
@@ -3013,6 +3082,7 @@ static struct lcd_clk_data_s lcd_clk_data_tl1 = {
 	.pll_n_max = PLL_N_MAX_TL1,
 	.pll_n_min = PLL_N_MIN_TL1,
 	.pll_frac_range = PLL_FRAC_RANGE_TL1,
+	.pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TL1,
 	.pll_od_sel_max = PLL_OD_SEL_MAX_TL1,
 	.pll_ref_fmax = PLL_FREF_MAX_TL1,
 	.pll_ref_fmin = PLL_FREF_MIN_TL1,
diff --git a/drivers/display/lcd/aml_lcd_clk_config.h b/drivers/display/lcd/aml_lcd_clk_config.h
index cbd6ebc..563e940 100644
--- a/drivers/display/lcd/aml_lcd_clk_config.h
+++ b/drivers/display/lcd/aml_lcd_clk_config.h
@@ -24,6 +24,10 @@
 /* **********************************
  * clk config
  * ********************************** */
+#define LCD_PLL_MODE_DEFAULT         (1 << 0)
+#define LCD_PLL_MODE_SPECIAL_CNTL    (1 << 1)
+#define LCD_PLL_MODE_FRAC_SHIFT      (1 << 2)
+
 #define PLL_RETRY_MAX		20
 #define LCD_CLK_CTRL_EN      0
 #define LCD_CLK_CTRL_RST     1
@@ -47,6 +51,7 @@ struct lcd_clk_data_s {
 	unsigned int pll_n_max;
 	unsigned int pll_n_min;
 	unsigned int pll_frac_range;
+	unsigned int pll_frac_sign_bit;
 	unsigned int pll_od_sel_max;
 	unsigned int pll_ref_fmax;
 	unsigned int pll_ref_fmin;
@@ -95,6 +100,7 @@ struct lcd_clk_config_s { /* unit: kHz */
 	unsigned int pll_tcon_div_sel;
 	unsigned int pll_level;
 	unsigned int pll_frac;
+	unsigned int pll_frac_half_shift;
 	unsigned int pll_fout;
 	unsigned int ss_level;
 	unsigned int ss_freq;
@@ -121,4 +127,6 @@ extern void lcd_clk_disable(void);
 extern void lcd_clk_generate_parameter(struct lcd_config_s *pconf);
 extern void lcd_clk_config_probe(void);
 
+extern unsigned long clk_util_clk_msr(int index);
+
 #endif
diff --git a/drivers/display/lcd/aml_lcd_clk_ctrl.h b/drivers/display/lcd/aml_lcd_clk_ctrl.h
index 37d5157..e2cabb0 100644
--- a/drivers/display/lcd/aml_lcd_clk_ctrl.h
+++ b/drivers/display/lcd/aml_lcd_clk_ctrl.h
@@ -43,6 +43,7 @@
 #define PLL_N_MIN_GXTVBB            1
 #define PLL_N_MAX_GXTVBB            1
 #define PLL_FRAC_RANGE_GXTVBB       (1 << 10)
+#define PLL_FRAC_SIGN_BIT_GXTVBB    11
 #define PLL_OD_SEL_MAX_GXTVBB       3
 #define PLL_FREF_MIN_GXTVBB         (5 * 1000)
 #define PLL_FREF_MAX_GXTVBB         (25 * 1000)
@@ -75,6 +76,7 @@
 #define PLL_N_MIN_GXL               1
 #define PLL_N_MAX_GXL               1
 #define PLL_FRAC_RANGE_GXL          (1 << 10)
+#define PLL_FRAC_SIGN_BIT_GXL       11
 #define PLL_OD_SEL_MAX_GXL          3
 #define PLL_FREF_MIN_GXL            (5 * 1000)
 #define PLL_FREF_MAX_GXL            (25 * 1000)
@@ -106,6 +108,7 @@
 #define PLL_N_MIN_TXL               1
 #define PLL_N_MAX_TXL               1
 #define PLL_FRAC_RANGE_TXL          (1 << 10)
+#define PLL_FRAC_SIGN_BIT_TXL       11
 #define PLL_OD_SEL_MAX_TXL          3
 #define PLL_FREF_MIN_TXL            (5 * 1000)
 #define PLL_FREF_MAX_TXL            (25 * 1000)
@@ -139,6 +142,7 @@
 #define PLL_N_MIN_TXLX               1
 #define PLL_N_MAX_TXLX               1
 #define PLL_FRAC_RANGE_TXLX          (1 << 10)
+#define PLL_FRAC_SIGN_BIT_TXLX       11
 #define PLL_OD_SEL_MAX_TXLX          3
 #define PLL_FREF_MIN_TXLX            (5 * 1000)
 #define PLL_FREF_MAX_TXLX            (25 * 1000)
@@ -167,6 +171,7 @@
 #define PLL_N_MIN_AXG               1
 #define PLL_N_MAX_AXG               1
 #define PLL_FRAC_RANGE_AXG          (1 << 10)
+#define PLL_FRAC_SIGN_BIT_AXG       11
 #define PLL_OD_SEL_MAX_AXG          3
 #define PLL_FREF_MIN_AXG            (5 * 1000)
 #define PLL_FREF_MAX_AXG            (25 * 1000)
@@ -199,6 +204,7 @@
 #define PLL_N_MIN_TXHD               1
 #define PLL_N_MAX_TXHD               1
 #define PLL_FRAC_RANGE_TXHD          (1 << 10)
+#define PLL_FRAC_SIGN_BIT_TXHD       11
 #define PLL_OD_SEL_MAX_TXHD          3
 #define PLL_FREF_MIN_TXHD            (5 * 1000)
 #define PLL_FREF_MAX_TXHD            (25 * 1000)
@@ -223,6 +229,7 @@
 /* ******** frequency limit (unit: kHz) ******** */
 #define PLL_OD_FB_GP0_G12A           0
 #define PLL_FRAC_RANGE_GP0_G12A      (1 << 17)
+#define PLL_FRAC_SIGN_BIT_GP0_G12A   18
 #define PLL_OD_SEL_MAX_GP0_G12A      5
 #define PLL_VCO_MIN_GP0_G12A         (3000 * 1000)
 #define PLL_VCO_MAX_GP0_G12A         (6000 * 1000)
@@ -241,6 +248,7 @@
 /* ******** frequency limit (unit: kHz) ******** */
 #define PLL_OD_FB_HPLL_G12A          0
 #define PLL_FRAC_RANGE_HPLL_G12A     (1 << 17)
+#define PLL_FRAC_SIGN_BIT_HPLL_G12A  18
 #define PLL_OD_SEL_MAX_HPLL_G12A     3
 #define PLL_VCO_MIN_HPLL_G12A        (3000 * 1000)
 #define PLL_VCO_MAX_HPLL_G12A        (6000 * 1000)
@@ -277,6 +285,7 @@
 #define PLL_N_MIN_TL1                1
 #define PLL_N_MAX_TL1                1
 #define PLL_FRAC_RANGE_TL1           (1 << 17)
+#define PLL_FRAC_SIGN_BIT_TL1        18
 #define PLL_OD_SEL_MAX_TL1           3
 #define PLL_FREF_MIN_TL1             (5 * 1000)
 #define PLL_FREF_MAX_TL1             (25 * 1000)
diff --git a/drivers/display/lcd/aml_lcd_common.c b/drivers/display/lcd/aml_lcd_common.c
index c192bd4..0d5c0bc 100644
--- a/drivers/display/lcd/aml_lcd_common.c
+++ b/drivers/display/lcd/aml_lcd_common.c
@@ -670,7 +670,10 @@ static int lcd_pinmux_load_from_bsp(struct lcd_config_s *pconf)
 		}
 		break;
 	case LCD_P2P:
-		sprintf(propname, "lcd_p2p_pin");
+		if (pconf->lcd_control.p2p_config->p2p_type == P2P_USIT)
+			sprintf(propname, "lcd_p2p_usit_pin");
+		else
+			sprintf(propname, "lcd_p2p_pin");
 		pinmux = pconf->lcd_pinmux;
 		for (i = 0; i < LCD_PINMX_MAX; i++) {
 			if (pinmux == NULL)
diff --git a/drivers/display/lcd/aml_lcd_common.h b/drivers/display/lcd/aml_lcd_common.h
index 878b2e2..7d6cf53 100644
--- a/drivers/display/lcd/aml_lcd_common.h
+++ b/drivers/display/lcd/aml_lcd_common.h
@@ -31,8 +31,9 @@
 /* 20190308: add more panel clk_ss_level step for tl1*/
 /* 20190911: add lcd_tcon_load_data for tl1*/
 /* 20191025: tcon chpi phy setting update*/
+/* 20191115: add lcd_tcon_load_data chk_data for tl1*/
 
-#define LCD_DRV_VERSION    "20191025"
+#define LCD_DRV_VERSION    "20191115"
 
 #define LCD_STATUS_IF_ON      (1 << 0)
 #define LCD_STATUS_ENCL_ON    (1 << 1)
diff --git a/drivers/display/lcd/aml_lcd_phy_config.c b/drivers/display/lcd/aml_lcd_phy_config.c
index db381d3..ce35b01 100644
--- a/drivers/display/lcd/aml_lcd_phy_config.c
+++ b/drivers/display/lcd/aml_lcd_phy_config.c
@@ -89,44 +89,46 @@ static unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf)
 	return channel_on;
 }
 
-void lcd_phy_cntl_set_tl1(int status, unsigned int data32, int flag)
+void lcd_phy_cntl_set_tl1(int status, unsigned int chreg, int bypass,
+			  unsigned int ckdi)
 {
 	unsigned int tmp = 0;
 	unsigned int data = 0;
-	unsigned int cntl16 = 0x80000000;
+	unsigned int cntl16 = 0;
 
 	if (lcd_debug_print_flag)
 		LCDPR("%s: %d\n", __func__, status);
 
 	if (status) {
-		data32 |= ((phy_ctrl_bit_on << 16) |
+		chreg |= ((phy_ctrl_bit_on << 16) |
 			   (phy_ctrl_bit_on << 0));
-		if (flag)
+		if (bypass)
 			tmp |= ((1 << 18) | (1 << 2));
+		cntl16 = ckdi | 0x80000000;
 	} else {
 		if (phy_ctrl_bit_on)
 			data = 0;
 		else
 			data = 1;
-		data32 |= ((data << 16) | (data << 0));
 		cntl16 = 0;
+		chreg |= ((data << 16) | (data << 0));
 		lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
 	}
 
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, tmp);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, tmp);
-	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
+	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, chreg);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, tmp);
-	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
+	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, chreg);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, tmp);
-	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
+	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, chreg);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, tmp);
-	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
+	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, chreg);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, tmp);
-	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
+	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, chreg);
 	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, tmp);
-	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
+	lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, chreg);
 }
 
 void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
@@ -161,7 +163,7 @@ void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
 			data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
 				0xff2027e0 | vswing);
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 0, 0);
 			break;
 		case LCD_CHIP_TXHD:
 			if (preem > 3) {
@@ -221,7 +223,7 @@ void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
 		switch (lcd_drv->chip_type) {
 		case LCD_CHIP_TL1:
 		case LCD_CHIP_TM2:
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 0, 0);
 			break;
 		default:
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
@@ -271,7 +273,7 @@ void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
 				lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
 					0xf02027a0 | vswing);
 			}
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 1, 0);
 			break;
 		default:
 			if (vswing > 7) {
@@ -302,7 +304,7 @@ void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
 		switch (lcd_drv->chip_type) {
 		case LCD_CHIP_TL1:
 		case LCD_CHIP_TM2:
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 1, 0);
 			break;
 		default:
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
@@ -316,7 +318,7 @@ void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
 void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
 {
 	unsigned int vswing, preem;
-	unsigned int data32 = 0, size, cntl16;
+	unsigned int data32 = 0, size, ckdi;
 	struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
 	struct mlvds_config_s *mlvds_conf;
 
@@ -343,9 +345,8 @@ void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
 			data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
 				0xff2027e0 | vswing);
-			cntl16 = (mlvds_conf->pi_clk_sel << 12);
-			cntl16 |= 0x80000000;
-			lcd_phy_cntl_set_tl1(status, data32, cntl16);
+			ckdi = (mlvds_conf->pi_clk_sel << 12);
+			lcd_phy_cntl_set_tl1(status, data32, 0, ckdi);
 			break;
 		case LCD_CHIP_TXHD:
 			if (vswing > 7) {
@@ -377,7 +378,7 @@ void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
 		switch (lcd_drv->chip_type) {
 		case LCD_CHIP_TL1:
 		case LCD_CHIP_TM2:
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 0, 0);
 			break;
 		case LCD_CHIP_TXHD:
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
@@ -420,7 +421,7 @@ void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
 			data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
 				0xff2027a0 | vswing);
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 1, 0);
 			break;
 		case P2P_CHPI: /* low common mode */
 		case P2P_CSPI:
@@ -439,7 +440,7 @@ void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
 			}
 
 			lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xfe60027f);
-			lcd_phy_cntl_set_tl1(status, data32, 0);
+			lcd_phy_cntl_set_tl1(status, data32, 1, 0);
 			break;
 		default:
 			LCDERR("%s: invalid p2p_type %d\n",
@@ -447,7 +448,7 @@ void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
 			break;
 		}
 	} else {
-		lcd_phy_cntl_set_tl1(status, data32, 0);
+		lcd_phy_cntl_set_tl1(status, data32, 1, 0);
 	}
 }
 
@@ -590,7 +591,7 @@ int lcd_phy_probe(void)
 		else
 			phy_ctrl_bit_on = 0;
 		break;
-	case LCD_CHIP_G12B:
+	case LCD_CHIP_TM2:
 		if (lcd_drv->rev_type == 0xB)
 			phy_ctrl_bit_on = 1;
 		else
diff --git a/drivers/display/lcd/aml_lcd_tcon.c b/drivers/display/lcd/aml_lcd_tcon.c
index c96ec41..a633bae 100644
--- a/drivers/display/lcd/aml_lcd_tcon.c
+++ b/drivers/display/lcd/aml_lcd_tcon.c
@@ -81,21 +81,30 @@ static int lcd_tcon_vac_load(void)
 		(unsigned char *)(unsigned long)(tcon_rmem.vac_mem_paddr);
 	int ret = 0;
 #ifdef CONFIG_CMD_INI
-	int i;
+	int i, chk_data = 0;
 #endif
-
 	if ((!tcon_rmem.vac_mem_size) || (vac_data == NULL))
 		return -1;
 
 #ifdef CONFIG_CMD_INI
+	memset(vac_data, 0, tcon_rmem.vac_mem_size);
 	ret = handle_tcon_vac(vac_data, tcon_rmem.vac_mem_size);
 	if (ret) {
-		LCDPR("%s: no vac_data\n", __func__);
+		LCDPR("%s: no vac data\n", __func__);
 		return -1;
 	}
-	if (lcd_debug_print_flag) {
-		for (i = 0; i < 256; i++)
-			LCDPR("vac_data[%d]: %d\n", i, vac_data[i * 1]);
+	chk_data |= vac_data[0];
+	chk_data |= vac_data[1] << 8;
+	chk_data |= vac_data[2] << 16;
+	chk_data |= vac_data[3] << 24;
+	if (!chk_data) {
+		LCDPR("%s: vac_data check error\n", __func__);
+		return -1;
+	}
+
+	if (lcd_debug_print_flag == 3) {
+		for (i = 0; i < 30; i++)
+			LCDPR("vac_data[%d]: 0x%02x\n", i, vac_data[i * 1]);
 	}
 #endif
 	return ret;
@@ -107,26 +116,35 @@ static int lcd_tcon_demura_set_load(void)
 			       (tcon_rmem.demura_set_paddr);
 	int ret = 0;
 #ifdef CONFIG_CMD_INI
-	int i;
+	int i, chk_data = 0;
 #endif
-
 	if ((!tcon_rmem.demura_set_mem_size) || (demura_setting == NULL))
 		return -1;
 
 #ifdef CONFIG_CMD_INI
+	memset(demura_setting, 0, tcon_rmem.demura_set_mem_size);
 	ret = handle_tcon_demura_set(demura_setting,
 				     tcon_rmem.demura_set_mem_size);
 	if (ret) {
 		LCDPR("%s: no demura_set data\n", __func__);
 		return -1;
 	}
-	if (lcd_debug_print_flag) {
+
+	chk_data |= demura_setting[0];
+	chk_data |= demura_setting[1] << 8;
+	chk_data |= demura_setting[2] << 16;
+	chk_data |= demura_setting[3] << 24;
+	if (!chk_data) {
+		LCDPR("%s: demura_setting check error\n", __func__);
+		return -1;
+	}
+
+	if (lcd_debug_print_flag == 3) {
 		for (i = 0; i < 100; i++)
 			LCDPR("demura_set[%d]: 0x%x\n",
 			      i, demura_setting[i]);
 	}
 #endif
-
 	return ret;
 }
 
@@ -136,25 +154,33 @@ static int lcd_tcon_demura_lut_load(void)
 			       (tcon_rmem.demura_lut_paddr);
 	int ret = 0;
 #ifdef CONFIG_CMD_INI
-	int i;
+	int i, chk_data = 0;
 #endif
 	if ((!tcon_rmem.demura_lut_mem_size) || (demura_lut_data == NULL))
 		return -1;
 
 #ifdef CONFIG_CMD_INI
+	memset(demura_lut_data, 0, tcon_rmem.demura_lut_mem_size);
 	ret = handle_tcon_demura_lut(demura_lut_data,
 				     tcon_rmem.demura_lut_mem_size);
 	if (ret) {
 		LCDPR("%s: no demura_lut data\n", __func__);
 		return -1;
 	}
-	if (lcd_debug_print_flag) {
+	chk_data |= demura_lut_data[0];
+	chk_data |= demura_lut_data[1] << 8;
+	chk_data |= demura_lut_data[2] << 16;
+	chk_data |= demura_lut_data[3] << 24;
+	if (!chk_data) {
+		LCDPR("%s: demura_lut check error\n", __func__);
+		return -1;
+	}
+	if (lcd_debug_print_flag == 3) {
 		for (i = 0; i < 100; i++)
-			LCDPR("demura_lut_data[%d]: 0x%x\n",
+			LCDPR("demura_lut_data[%d]: 0x%02x\n",
 			      i, demura_lut_data[i]);
 	}
 #endif
-
 	return ret;
 }
 
@@ -282,16 +308,16 @@ static int lcd_tcon_enable_txhd(struct lcd_config_s *pconf)
 static void lcd_tcon_vac_set_tl1(unsigned int demura_valid)
 {
 	int len, i, j, n;
-	unsigned int d0, d1, temp, demura_support, set1, set2;
+	unsigned int d0, d1, temp, set1, set2;
+	unsigned int demura_support;
 	unsigned char *vac_data =
 		(unsigned char *)(unsigned long)(tcon_rmem.vac_mem_paddr);
 
 	if ((!tcon_rmem.vac_mem_size) || (vac_data == NULL))
 		return;
 
-	LCDPR("lcd_tcon vac_set\n");
-
-	n = 0;
+	LCDPR("lcd_tcon_vac_set\n");
+	n = 8;
 	len = TCON_VAC_SET_PARAM_NUM;
 	demura_support = vac_data[n];
 	set1 = vac_data[n + 2];
@@ -397,7 +423,7 @@ static int lcd_tcon_demura_set_tl1(void)
 
 	LCDPR("lcd_tcon demura_set\n");
 
-	for (i = 0; i < 160; i++)
+	for (i = 8; i < (160 + 8); i++)
 		lcd_tcon_write_byte(0x186, demura_setting[i]);
 
 	return 0;
@@ -423,7 +449,7 @@ static int lcd_tcon_demura_lut_tl1(void)
 	lcd_tcon_write_byte(0x184, 0x01);
 	lcd_tcon_write_byte(0x185, 0x87);
 
-	for (i = 0; i < 391053; i++)
+	for (i = 8; i < (391053 + 8); i++)
 		lcd_tcon_write_byte(0x187, demura_lut_data[i]);
 
 	LCDPR("lcd_tcon 0x23d = 0x%02x\n", lcd_tcon_read_byte(0x23d));
@@ -456,6 +482,7 @@ static int lcd_tcon_top_set_tl1(struct lcd_config_s *pconf)
 	if (pconf->lcd_basic.lcd_type == LCD_P2P) {
 		switch (pconf->lcd_control.p2p_config->p2p_type) {
 		case P2P_CHPI:
+		case P2P_USIT:
 			lcd_tcon_write(TCON_TOP_CTRL, 0x8199);
 			break;
 		default:
@@ -531,8 +558,10 @@ int lcd_tcon_data_load(int *vac_valid, int *demura_valid)
 		return -1;
 
 	ret = lcd_tcon_vac_load();
-	if (ret == 0)
+	if (!ret)
 		*vac_valid = 1;
+	if (table == NULL)
+		return 0;
 	ret = lcd_tcon_demura_set_load();
 	if (ret)  {
 		table[0x178] = 0x38;
@@ -541,7 +570,7 @@ int lcd_tcon_data_load(int *vac_valid, int *demura_valid)
 		table[0x23d] &= ~(1 << 0);
 	} else {
 		ret = lcd_tcon_demura_lut_load();
-		if (ret)  {
+		if (ret) {
 			table[0x178] = 0x38;
 			table[0x17c] = 0x20;
 			table[0x181] = 0x00;
diff --git a/drivers/display/lcd/aml_lcd_tcon.h b/drivers/display/lcd/aml_lcd_tcon.h
index 49f8853..267696f 100644
--- a/drivers/display/lcd/aml_lcd_tcon.h
+++ b/drivers/display/lcd/aml_lcd_tcon.h
@@ -92,7 +92,7 @@ struct tcon_rmem_s {
 #define CTRL_TIMING_CNT_TL1              0
 
 #ifdef CONFIG_CMD_INI
-extern int handle_tcon_vac(unsigned char *vac_data, unsigned char vac_mem_size);
+int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size);
 extern int handle_tcon_demura_set(unsigned char *demura_set_data,
 				  unsigned int demura_set_size);
 extern int handle_tcon_demura_lut(unsigned char *demura_lut_data,
diff --git a/drivers/display/lcd/lcd_extern/ext_default.c b/drivers/display/lcd/lcd_extern/ext_default.c
index 6433749..d60d3cf 100644
--- a/drivers/display/lcd/lcd_extern/ext_default.c
+++ b/drivers/display/lcd/lcd_extern/ext_default.c
@@ -223,11 +223,13 @@ static int lcd_extern_power_cmd_dynamic_size(unsigned char *table, int flag)
 					delay_ms += table[i+2+j];
 				if (delay_ms > 0)
 					mdelay(delay_ms);
-			} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+			} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+				   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 				ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 					ext_config->i2c_addr,
 					&table[i+2], cmd_size);
-			} else if (type == LCD_EXT_CMD_TYPE_CMD2) {
+			} else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+				   (type == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
 				ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 					ext_config->i2c_addr2,
 					&table[i+2], cmd_size);
@@ -287,7 +289,8 @@ power_cmd_dynamic_i2c_next:
 					delay_ms += table[i+2+j];
 				if (delay_ms > 0)
 					mdelay(delay_ms);
-			} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+			} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+				   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 				ret = lcd_extern_spi_write(&table[i+2], cmd_size);
 			} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
 				ret = lcd_extern_spi_write(&table[i+2], (cmd_size-1));
@@ -354,11 +357,13 @@ static int lcd_extern_power_cmd_fixed_size(unsigned char *table, int flag)
 					delay_ms += table[i+1+j];
 				if (delay_ms > 0)
 					mdelay(delay_ms);
-			} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+			} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+				   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 				ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 					ext_config->i2c_addr,
 					&table[i+1], (cmd_size-1));
-			} else if (type == LCD_EXT_CMD_TYPE_CMD2) {
+			} else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+				   (type == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
 				ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 					ext_config->i2c_addr2,
 					&table[i+1], (cmd_size-1));
@@ -406,7 +411,8 @@ static int lcd_extern_power_cmd_fixed_size(unsigned char *table, int flag)
 					delay_ms += table[i+1+j];
 				if (delay_ms > 0)
 					mdelay(delay_ms);
-			} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+			} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+				   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 				ret = lcd_extern_spi_write(&table[i+1], (cmd_size-1));
 			} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
 				ret = lcd_extern_spi_write(&table[i+1], (cmd_size-2));
diff --git a/drivers/display/lcd/lcd_extern/i2c_CS602.c b/drivers/display/lcd/lcd_extern/i2c_CS602.c
index 048554a..1b76f37 100644
--- a/drivers/display/lcd/lcd_extern/i2c_CS602.c
+++ b/drivers/display/lcd/lcd_extern/i2c_CS602.c
@@ -136,7 +136,8 @@ static int lcd_extern_power_cmd_dynamic_size(unsigned char *table, int flag)
 				delay_ms += table[i+2+j];
 			if (delay_ms > 0)
 				mdelay(delay_ms);
-		} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+		} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+			   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 			ret = lcd_extern_reg_write(&table[i+2], cmd_size);
 		} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
 			ret = lcd_extern_reg_write(&table[i+2], (cmd_size-1));
@@ -194,7 +195,8 @@ static int lcd_extern_power_cmd_fixed_size(unsigned char *table, int flag)
 				delay_ms += table[i+1+j];
 			if (delay_ms > 0)
 				mdelay(delay_ms);
-		} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+		} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+			   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 			ret = lcd_extern_reg_write(&table[i+1], (cmd_size-1));
 		} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
 			ret = lcd_extern_reg_write(&table[i+1], (cmd_size-2));
diff --git a/drivers/display/lcd/lcd_extern/i2c_RT6947.c b/drivers/display/lcd/lcd_extern/i2c_RT6947.c
index 2b57ee5..3822ff8 100644
--- a/drivers/display/lcd/lcd_extern/i2c_RT6947.c
+++ b/drivers/display/lcd/lcd_extern/i2c_RT6947.c
@@ -97,10 +97,12 @@ static int lcd_extern_power_cmd_dynamic_size(unsigned char *table)
 				delay_ms += table[i+2+j];
 			if (delay_ms > 0)
 				mdelay(delay_ms);
-		} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+		} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+			   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 			ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 				ext_config->i2c_addr, &table[i+2], cmd_size);
-		} else if (type == LCD_EXT_CMD_TYPE_CMD2) {
+		} else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+			   (type == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
 			ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 				ext_config->i2c_addr2, &table[i+2], cmd_size);
 		} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
@@ -161,10 +163,12 @@ static int lcd_extern_power_cmd_fixed_size(unsigned char *table)
 				delay_ms += table[i+1+j];
 			if (delay_ms > 0)
 				mdelay(delay_ms);
-		} else if (type == LCD_EXT_CMD_TYPE_CMD) {
+		} else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+			   (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
 			ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 				ext_config->i2c_addr, &table[i+1], (cmd_size-1));
-		} else if (type == LCD_EXT_CMD_TYPE_CMD2) {
+		} else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+			   (type == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
 			ret = aml_lcd_extern_i2c_write(ext_config->i2c_bus,
 				ext_config->i2c_addr2, &table[i+1], (cmd_size-1));
 		} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
diff --git a/drivers/display/lcd/lcd_extern/lcd_extern.c b/drivers/display/lcd/lcd_extern/lcd_extern.c
index d418ebb..f7d50cb 100644
--- a/drivers/display/lcd/lcd_extern/lcd_extern.c
+++ b/drivers/display/lcd/lcd_extern/lcd_extern.c
@@ -80,7 +80,9 @@ static void aml_lcd_extern_init_table_dynamic_size_print(
 				for (j = 0; j < cmd_size; j++)
 					printf("%d,", table[i+2+j]);
 			} else if ((table[i] == LCD_EXT_CMD_TYPE_CMD) ||
-				(table[i] == LCD_EXT_CMD_TYPE_CMD2)) {
+				   (table[i] == LCD_EXT_CMD_TYPE_CMD2) ||
+				   (table[i] == LCD_EXT_CMD_TYPE_CMD_BIN) ||
+				   (table[i] == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
 				for (j = 0; j < cmd_size; j++)
 					printf("0x%02x,", table[i+2+j]);
 			} else if ((table[i] == LCD_EXT_CMD_TYPE_CMD_DELAY) ||
@@ -1018,7 +1020,8 @@ static int aml_lcd_extern_init_table_dynamic_size_load_unifykey(
 			len += 1;
 			ret = aml_lcd_unifykey_len_check(key_len, len);
 			if (ret) {
-				EXTERR("%s: get %s failed\n", extconf->name, propname);
+				EXTERR("%s: get %s type failed\n",
+				       extconf->name, propname);
 				table[i] = LCD_EXT_CMD_TYPE_END;
 				table[i+1] = 0;
 				return -1;
@@ -1028,7 +1031,8 @@ static int aml_lcd_extern_init_table_dynamic_size_load_unifykey(
 			len += 1;
 			ret = aml_lcd_unifykey_len_check(key_len, len);
 			if (ret) {
-				EXTERR("%s: get %s failed\n", extconf->name, propname);
+				EXTERR("%s: get %s cmd_size failed\n",
+				       extconf->name, propname);
 				table[i] = LCD_EXT_CMD_TYPE_END;
 				table[i+1] = 0;
 				return -1;
@@ -1051,7 +1055,7 @@ static int aml_lcd_extern_init_table_dynamic_size_load_unifykey(
 			len += cmd_size;
 			ret = aml_lcd_unifykey_len_check(key_len, len);
 			if (ret) {
-				EXTERR("%s: get %s failed\n", extconf->name, propname);
+				EXTERR("%s: get %s data failed\n", extconf->name, propname);
 				table[i] = LCD_EXT_CMD_TYPE_END;
 				table[i+1] = 0;
 				return -1;
@@ -1073,7 +1077,8 @@ init_table_dynamic_i2c_spi_ukey_next:
 			len += 1;
 			ret = aml_lcd_unifykey_len_check(key_len, len);
 			if (ret) {
-				EXTERR("%s: get %s failed\n", extconf->name, propname);
+				EXTERR("%s: get type %s failed\n",
+				       extconf->name, propname);
 				table[i] = LCD_EXT_CMD_TYPE_END;
 				table[i+1] = 0;
 				return -1;
@@ -1083,7 +1088,8 @@ init_table_dynamic_i2c_spi_ukey_next:
 			len += 1;
 			ret = aml_lcd_unifykey_len_check(key_len, len);
 			if (ret) {
-				EXTERR("%s: get %s failed\n", extconf->name, propname);
+				EXTERR("%s: get type %s failed\n",
+				       extconf->name, propname);
 				table[i] = LCD_EXT_CMD_TYPE_END;
 				table[i+1] = 0;
 				return -1;
diff --git a/drivers/display/lcd/lcd_tv/lcd_drv.c b/drivers/display/lcd/lcd_tv/lcd_drv.c
index a17e766..74fe498 100644
--- a/drivers/display/lcd/lcd_tv/lcd_drv.c
+++ b/drivers/display/lcd/lcd_tv/lcd_drv.c
@@ -122,6 +122,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
 	lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE, v_active - 1  + video_on_line);
 	switch (pconf->lcd_basic.lcd_type) {
 	case LCD_P2P:
+	case LCD_MLVDS:
 		lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_BLINE, video_on_line - 1 - 4);
 		lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_ELINE, video_on_line - 1);
 		lcd_vcbus_write(ENCL_VIDEO_H_PRE_DE_BEGIN, video_on_pixel + PRE_DE_DELAY);
@@ -671,6 +672,8 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
 	//lcd_vcbus_setb(VBO_PXL_CTRL,0x2,0,4);
 	//lcd_vcbus_setb(VBO_PXL_CTRL,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
 	//set_vbyone_ctlbits(1,0,0); */
+	/* VBO_RGN_GEN clk always on */
+	lcd_vcbus_setb(VBO_GCLK_MAIN, 2, 2, 2);
 
 	/* PAD select: */
 	if ((lane_count == 1) || (lane_count == 2))
@@ -927,6 +930,7 @@ static void lcd_p2p_control_set(struct lcd_config_s *pconf)
 	/* phy_div: 0=div6, 1=div 7, 2=div8, 3=div10 */
 	switch (pconf->lcd_control.p2p_config->p2p_type) {
 	case P2P_CHPI: /* 8/10 coding */
+	case P2P_USIT:
 		phy_div = 3;
 		break;
 	default:
diff --git a/drivers/display/osd/Makefile b/drivers/display/osd/Makefile
index 30737e4..3a15303 100644
--- a/drivers/display/osd/Makefile
+++ b/drivers/display/osd/Makefile
@@ -1,3 +1,2 @@
 obj-$(CONFIG_AML_OSD) += osd_hw.o osd_fb.o osd_debug.o
 obj-$(CONFIG_AML_DOLBY) += dolby_vision.o
-obj-$(CONFIG_AML_DOLBY) += dovi.o
diff --git a/drivers/display/osd/dolby_vision.c b/drivers/display/osd/dolby_vision.c
index ae7bd34..4f2f287 100644
--- a/drivers/display/osd/dolby_vision.c
+++ b/drivers/display/osd/dolby_vision.c
@@ -474,6 +474,9 @@ static void dolby_vision_get_vinfo(struct hdmitx_dev *hdmitx_device)
 	} else if (strstr(mode_name, "480")) {
 		width = 720;
 		height = 480;
+	} else if (strstr(mode_name, "smpte")) {
+		width = 4096;
+		height = 2160;
 	} else {
 		printf("unkown mode, use default 1080p\n");
 		width = 1920;
diff --git a/drivers/display/osd/dv/Makefile b/drivers/display/osd/dv/Makefile
deleted file mode 100644
index 8abb16e..0000000
--- a/drivers/display/osd/dv/Makefile
+++ b/dev/null
@@ -1,4 +0,0 @@
-.PHONY dovi.o:
-dovi.o:
-	mkdir -p ../../../../build/drivers/display/osd/
-	cp dovi.a ../../../../build/drivers/display/osd/dovi.o
diff --git a/drivers/display/osd/osd_fb.c b/drivers/display/osd/osd_fb.c
index bb6a2d1..7b0e0e8 100644
--- a/drivers/display/osd/osd_fb.c
+++ b/drivers/display/osd/osd_fb.c
@@ -1189,9 +1189,7 @@ static int _osd_hw_init(void)
 	u32 fg = 0;
 	u32 bg = 0;
 	u32 fb_width = 0;
-	u32 fb_height = 0;;
-
-	get_osd_version();
+	u32 fb_height = 0;
 
 	vout_init();
 	fb_addr = get_fb_addr();
@@ -1247,10 +1245,6 @@ static int osd_hw_init_by_index(u32 osd_index)
 	return 0;
 }
 
-
-
-
-
 static int video_display_osd(u32 osd_index)
 {
 	struct vinfo_s *info = NULL;
@@ -1349,16 +1343,16 @@ void hist_set_golden_data(void)
 		if (str) {
 			switch (i%4) {
 				case 0:
-					hist_max_min[i/4][family_id] = env_strtoul(str, 16);
+					hist_max_min[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 				case 1:
-					hist_spl_val[i/4][family_id] = env_strtoul(str, 16);
+					hist_spl_val[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 				case 2:
-					hist_spl_pix_cnt[i/4][family_id] = env_strtoul(str, 16);
+					hist_spl_pix_cnt[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 				case 3:
-					hist_cheoma_sum[i/4][family_id] = env_strtoul(str, 16);
+					hist_cheoma_sum[i/4][family_id] = env_strtoul(hist_env_key[i], 16);
 					break;
 			}
 		}
@@ -1371,6 +1365,7 @@ int osd_rma_test(u32 osd_index)
 	u32 hist_result[4];
 	u32 family_id = get_cpu_id().family_id;
 
+	get_osd_version();
 	if (osd_hw.osd_ver == OSD_SIMPLE) {
 		osd_max = 0;
 	} else if (osd_hw.osd_ver == OSD_HIGH_ONE) {
diff --git a/drivers/display/osd/osd_hw.c b/drivers/display/osd/osd_hw.c
index 22e05de..4e0b852 100644
--- a/drivers/display/osd/osd_hw.c
+++ b/drivers/display/osd/osd_hw.c
@@ -2143,36 +2143,37 @@ static void osd2_update_enable(void)
 	u32 video_enable = 0;
 
 	if (osd_hw.free_scale_mode[OSD2]) {
-		if (osd_hw.enable[OSD2] == ENABLE) {
+		if (osd_hw.enable[OSD2] == ENABLE)
+			VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
+						   1 << 0);
+		else
+			VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
+						   1 << 0);
+
+		/* for older chips than g12a:
+		 * freescale output always on VPP_OSD1_POSTBLEND
+		 * if freescale is enable, VPP_OSD1_POSTBLEND to control OSD1&OSD2
+		 * if freescale is disable, VPP_OSD2_POSTBLEND to control OSD2
+		 */
+		if (osd_hw.osd_ver <= OSD_NORMAL) {
 			if (osd_hw.free_scale_enable[OSD2]) {
-				if (osd_hw.osd_ver <= OSD_NORMAL)
-				VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD1_POSTBLEND
-							   | VPP_POSTBLEND_EN);
-				VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
-							   1 << 0);
+				if (osd_hw.enable[OSD2] == ENABLE)
+						VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD1_POSTBLEND
+									   | VPP_POSTBLEND_EN);
+				else
+					if (!osd_hw.enable[OSD1])
+						VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD1_POSTBLEND);
 			} else {
-				VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
-							   1 << 0);
-#ifndef CONFIG_FB_OSD2_CURSOR
-				/*
-				VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
-						VPP_OSD1_POSTBLEND);
-				*/
-#endif
-				if (osd_hw.osd_ver <= OSD_NORMAL)
-				VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD2_POSTBLEND
-							   | VPP_POSTBLEND_EN);
+				if (osd_hw.enable[OSD2] == ENABLE)
+						VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD2_POSTBLEND
+									   | VPP_POSTBLEND_EN);
+				else
+						VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
+									   VPP_OSD2_POSTBLEND);
 			}
-		} else {
-			if (osd_hw.enable[OSD1] == ENABLE)
-				VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD2_POSTBLEND);
-			else
-				VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
-							   VPP_OSD1_POSTBLEND
-							   | VPP_OSD2_POSTBLEND);
 		}
 	} else if (osd_hw.osd_ver <= OSD_NORMAL){
 		video_enable |= VSYNCOSD_RD_MPEG_REG(VPP_MISC)&VPP_VD1_PREBLEND;
@@ -3068,8 +3069,7 @@ void osd_init_hw(void)
 		osd_hw.free_scale_data[OSD2].y_end = 0;
 		osd_hw.free_scale_mode[OSD1] = 1;
 		osd_hw.free_scale_mode[OSD2] = 1;
-		if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM)
-			||(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXLX))
+		if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM))
 			osd_reg_write(VPP_OSD_SC_DUMMY_DATA, 0x00202000);
 		else if (get_cpu_id().family_id ==
 			MESON_CPU_MAJOR_ID_GXTVBB)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index bb3f3b1..d2e7e71 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -524,13 +524,28 @@ static const char* getvar_list_dynamic[] = {
 	"partition-size:super", "partition-size:data", "version",
 };
 
+static const char* getvar_list_dynamic_ab[] = {
+	"hw-revision", "battery-voltage", "is-userspace", "is-logical:data",
+	"is-logical:metadata_a", "is-logical:metadata_b", "is-logical:misc", "is-logical:super",
+	"is-logical:boot_a", "is-logical:boot_b", "is-logical:system_a", "is-logical:system_b",
+	"is-logical:vendor_a", "is-logical:vendor_b", "is-logical:product_a", "is-logical:product_b",
+	"is-logical:odm_a", "is-logical:odm_b",
+	"slot-count", "max-download-size", "serialno", "product", "unlocked", "has-slot:data",
+	"has-slot:metadata", "has-slot:misc", "has-slot:super", "has-slot:boot",
+	"has-slot:system", "has-slot:vendor", "has-slot:product", "has-slot:odm", "current-slot",
+	"secure", "super-partition-name", "version-baseband", "version-bootloader",
+	"partition-size:super", "partition-size:metadata_a", "partition-size:metadata_b",
+	"partition-size:boot_a", "partition-size:boot_b", "partition-size:misc",
+	"partition-size:data", "version",
+};
+
+
 static const char* getvar_list_ab[] = {
 	"version-baseband", "version-bootloader", "version", "hw-revision", "max-download-size",
 	"serialno", "product", "off-mode-charge", "variant", "battery-soc-ok",
-	"battery-voltage", "partition-type:boot", "partition-size:boot",
-	"partition-type:system", "partition-size:system", "partition-type:vendor", "partition-size:vendor",
-	"partition-type:odm", "partition-size:odm", "partition-type:data", "partition-size:data",
-	"partition-type:cache", "partition-size:cache",
+	"battery-voltage", "partition-type:boot_a", "partition-size:boot_a",
+	"partition-type:system_a", "partition-size:system_a", "partition-type:vendor_a", "partition-size:vendor_a",
+	"partition-type:odm_a", "partition-size:odm_a", "partition-type:data", "partition-size:data",
 	"erase-block-size", "logical-block-size", "secure", "unlocked",
 	"slot-count", "slot-suffixes","current-slot", "has-slot:bootloader", "has-slot:boot",
 	"has-slot:system", "has-slot:vendor", "has-slot:odm", "has-slot:vbmeta",
@@ -568,7 +583,10 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 	if (!strncmp(cmd, "all", 3)) {
 		static int cmdIndex = 0;
 		int getvar_num = 0;
-		if (has_boot_slot == 1 && strlen(getvar_list_ab[cmdIndex]) < 64) {
+		if (dynamic_partition && has_boot_slot == 1 && strlen(getvar_list_dynamic_ab[cmdIndex]) < 64) {
+			strcpy(cmd, getvar_list_dynamic_ab[cmdIndex]);
+			getvar_num = (sizeof(getvar_list_dynamic_ab) / sizeof(getvar_list_dynamic_ab[0]));
+		} else if (has_boot_slot == 1 && strlen(getvar_list_ab[cmdIndex]) < 64) {
 			strcpy(cmd, getvar_list_ab[cmdIndex]);
 			getvar_num = (sizeof(getvar_list_ab) / sizeof(getvar_list_ab[0]));
 		} else if (dynamic_partition && strlen(getvar_list_dynamic[cmdIndex]) < 64) {
@@ -702,6 +720,12 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 			strncat(response, "yes", chars_left);
 		} else
 			strncat(response, "no", chars_left);
+	} else if (!strcmp_l1("has-slot:recovery", cmd)) {
+		if (has_boot_slot == 1) {
+			printf("has recovery slot\n");
+			strncat(response, "yes", chars_left);
+		} else
+			strncat(response, "no", chars_left);
 	} else if (!strcmp_l1("has-slot:system", cmd)) {
 		if (dynamic_partition) {
 			strncat(response, "no", chars_left);
@@ -723,15 +747,11 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 				strncat(response, "no", chars_left);
 		}
 	} else if (!strcmp_l1("has-slot:vbmeta", cmd)) {
-		if (dynamic_partition) {
+		if (has_boot_slot == 1) {
+			printf("has vbmeta slot\n");
+			strncat(response, "yes", chars_left);
+		} else
 			strncat(response, "no", chars_left);
-		} else {
-			if (has_boot_slot == 1) {
-				printf("has vbmeta slot\n");
-				strncat(response, "yes", chars_left);
-			} else
-				strncat(response, "no", chars_left);
-		}
 	} else if (!strcmp_l1("has-slot:product", cmd)) {
 		if (dynamic_partition) {
 			strncat(response, "no", chars_left);
@@ -778,12 +798,23 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 		char str_num[20];
 		struct partitions *pPartition;
 		uint64_t sz;
+		char *slot_name;
 		strsep(&cmd, ":");
 		printf("partition is %s\n", cmd);
 		if (strcmp(cmd, "userdata") == 0) {
 			strcpy(cmd, "data");
 			printf("partition is %s\n", cmd);
 		}
+		if ((has_boot_slot == 1) && (strcmp(cmd, "metadata") == 0)) {
+			slot_name = getenv("slot-suffixes");
+			if (strcmp(slot_name, "0") == 0) {
+				printf("set partiton metadata_a\n");
+				strcpy(cmd, "metadata_a");
+			} else if (strcmp(slot_name, "1") == 0) {
+				printf("set partiton metadata_b\n");
+				strcpy(cmd, "metadata_b");
+			}
+		}
 		if (!strncmp("mbr", cmd, strlen("mbr"))) {
 			strcpy(response, "FAILVariable not implemented");
 		} else {
@@ -1203,6 +1234,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
 {
 	char *cmd = req->buf;
 	char* response = response_str;
+	char *slot_name;
 
 	printf("cmd cb_flash is %s\n", cmd);
 
@@ -1229,6 +1261,17 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
 	}
 #endif
 
+	if ((has_boot_slot == 1) && (strcmp(cmd, "metadata") == 0)) {
+		slot_name = getenv("slot-suffixes");
+		if (strcmp(slot_name, "0") == 0) {
+			printf("set partiton metadata_a\n");
+			strcpy(cmd, "metadata_a");
+		} else if (strcmp(slot_name, "1") == 0) {
+			printf("set partiton metadata_b\n");
+			strcpy(cmd, "metadata_b");
+		}
+	}
+
 	printf("partition is %s\n", cmd);
 	if (strcmp(cmd, "userdata") == 0) {
 		strcpy(cmd, "data");
@@ -1329,6 +1372,7 @@ static void cb_erase(struct usb_ep *ep, struct usb_request *req)
 {
 	char* response = response_str;
 	char *cmd = req->buf;
+	char *slot_name;
 
 	printf("cmd cb_erase is %s\n", cmd);
 
@@ -1346,6 +1390,17 @@ static void cb_erase(struct usb_ep *ep, struct usb_request *req)
 	}
 
 	printf("partition is %s\n", cmd);
+	if ((has_boot_slot == 1) && (strcmp(cmd, "metadata") == 0)) {
+		slot_name = getenv("slot-suffixes");
+		if (strcmp(slot_name, "0") == 0) {
+			printf("set partiton metadata_a\n");
+			strcpy(cmd, "metadata_a");
+		} else if (strcmp(slot_name, "1") == 0) {
+			printf("set partiton metadata_b\n");
+			strcpy(cmd, "metadata_b");
+		}
+	}
+
 	if (strcmp(cmd, "userdata") == 0) {
 		strcpy(cmd, "data");
 		printf("partition is %s\n", cmd);
diff --git a/drivers/usb/gadget/fastboot/platform.c b/drivers/usb/gadget/fastboot/platform.c
index 8230078..eb3ab53 100644
--- a/drivers/usb/gadget/fastboot/platform.c
+++ b/drivers/usb/gadget/fastboot/platform.c
@@ -29,6 +29,7 @@ Description:
  #include "platform.h"
 #include <asm/cpu_id.h>
 #include <asm/arch/secure_apb.h>
+#include <amlogic/power_domain.h>
 
 /*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/
 #if !(defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC_OTG_294))
@@ -177,40 +178,13 @@ typedef union usb_r5 {
     } b;
 } usb_r5_t;
 
-#define PLL_REG32_16    (0xFF63A000 + 0x40)
-#define PLL_REG32_17    (0xFF63A000 + 0x44)
-#define PLL_REG32_18    (0xFF63A000 + 0x48)
+#define USB_REG_B 0xFF63A000
+#define PLL_REG32_16    (USB_REG_B + 0x40)
+#define PLL_REG32_17    (USB_REG_B + 0x44)
+#define PLL_REG32_18    (USB_REG_B + 0x48)
 #define USB_PHY2_ENABLE			0x10000000
 #define USB_PHY2_RESET			0x20000000
 
-static void set_usb_phy21_pll(void)
-{
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) =
-		USB_PHY2_PLL_PARAMETER_2;
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
-		USB_PHY2_PLL_PARAMETER_3;
-	udelay(100);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE))
-		& (~(USB_PHY2_RESET)));
-}
-
-static int f_platform_usb_check_sm1 (void)
-{
-	int rev_flag = 0;
-
-	cpu_id_t cpu_id = get_cpu_id();
-
-	if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1)
-		rev_flag = 1;
-	else
-		rev_flag = 0;
-
-	return rev_flag;
-}
-
 #ifndef CONFIG_USB_AMLOGIC_PHY_V2
 static int f_platform_usb_check_g12b_revb (void)
 {
@@ -229,24 +203,23 @@ static int f_platform_usb_check_g12b_revb (void)
 
 	return rev_flag;
 }
+#endif
 
-static void set_usb_phy21_sm1_pll(void)
+static int f_platform_usb_check_sm1 (void)
 {
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (0x09400414 | USB_PHY2_RESET | USB_PHY2_ENABLE);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) =
-		0x927e0000;
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
-		0xAC5F69E5;
-	udelay(100);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (((0x09400414) | (USB_PHY2_ENABLE))
-		& (~(USB_PHY2_RESET)));
+	int rev_flag = 0;
+
+	cpu_id_t cpu_id = get_cpu_id();
+
+	if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1)
+		rev_flag = 1;
+	else
+		rev_flag = 0;
+
+	return rev_flag;
 }
-#endif
 
 #ifdef CONFIG_USB_DEVICE_V2
-#define USB_REG_B 0xFF63A000
 
 void set_usb_phy21_tuning_fb(void)
 {
@@ -289,6 +262,7 @@ void set_usb_phy21_tuning_fb_reset(void)
 #define USB_RESET1       (volatile unsigned long *)0xc1104408
 #endif
 
+extern void set_usb_pll(uint32_t volatile *phy2_pll_base);
 void f_set_usb_phy_config(void)
 {
 	u2p_r0_t dev_u2p_r0;
@@ -300,26 +274,12 @@ void f_set_usb_phy_config(void)
 	u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE;
 	usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
 	int cnt;
-	u32 val;
-
-	if (f_platform_usb_check_sm1() == 1) {
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-		*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-		val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-		*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-		udelay(100);
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-		*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
-	}
+
+	if (f_platform_usb_check_sm1() == 1)
+		power_domain_switch(PM_USB, PWR_ON);
 
 #ifdef CONFIG_USB_POWER
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-	*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-	val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-	*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-	udelay(100);
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-	*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
+	power_domain_switch(PM_USB, PWR_ON);
 #endif
 
 #ifdef CONFIG_USB_DEVICE_V2
@@ -367,14 +327,8 @@ void f_set_usb_phy_config(void)
 		}
 	}
 
-#ifndef CONFIG_USB_AMLOGIC_PHY_V2
-	if (f_platform_usb_check_sm1())
-		set_usb_phy21_sm1_pll();
-	else
-		set_usb_phy21_pll();
-#else
-	set_usb_phy21_pll();
-#endif
+	set_usb_pll((uint32_t volatile *)USB_REG_B);
+
 	//--------------------------------------------------
 
 	// ------------- usb phy21 initinal end ----------
@@ -467,16 +421,6 @@ typedef union usb_r4 {
 	} b;
 } usb_r4_t;
 
-/*#if (defined CONFIG_TXLX_USB)
-#define P_RESET1_REGISTER       (volatile unsigned long *)0xffd01008
-#define P_AO_RTC_ALT_CLK_CNTL0  (volatile uint32_t *)(0xff800000 + (0x25 << 2))
-#define P_AO_RTI_PWR_CNTL_REG0  (volatile uint32_t *)(0xff800000 + (0x04 << 2))
-#else
-#define P_RESET1_REGISTER       (volatile unsigned long *)0xc1104408
-#define P_AO_RTC_ALT_CLK_CNTL0  (volatile uint32_t *)(0xc8100000 + (0x25 << 2))
-#define P_AO_RTI_PWR_CNTL_REG0  (volatile uint32_t *)(0xc8100000 + (0x04 << 2))
-#endif*/
-
 void f_set_usb_phy_config(void)
 {
 	const int time_dly = 500;
diff --git a/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h b/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
index f77af43..aa31fb9 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
+++ b/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
@@ -139,5 +139,8 @@ int get_total_itemnr(HIMAGE hImg);
 
 u64 optimus_img_decoder_get_data_parts_size(HIMAGE hImg, int* hasBootloader);
 
+
+unsigned image_get_crc(HIMAGE hImg);
+
 #endif//ifndef __AMLIMAGE_IF_H__
 
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
index a80751f..985061c 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
@@ -83,6 +83,10 @@ int optimus_buf_manager_init(const unsigned mediaAlignSz)
         return OPT_DOWN_FAIL;
     }
     _bufManager.mediaAlignSz = mediaAlignSz;
+    *(u32*)(&_bufManager.transferUnitSz) = (OPTIMUS_WORK_MODE_USB_PRODUCE >= optimus_work_mode_get())
+                                                ? OPTIMUS_DOWNLOAD_SLOT_SZ : OPTIMUS_LOCAL_UPGRADE_SLOT_SZ;
+    _bufManager.writeBackUnitSz = _bufManager.transferUnitSz;
+
 
     DWN_DBG("transfer=0x%p, transferBufSz=0x%x, transferUnitSz=0x%x, writeBackUnitSz=0x%x, totalSlotNum=%d\n", _bufManager.transferBuf,
             _bufManager.transferBufSz,  _bufManager.transferUnitSz,     _bufManager.writeBackUnitSz,        _bufManager.totalSlotNum);
@@ -131,6 +135,7 @@ int optimus_buf_manager_tplcmd_init(const char* mediaType,  const char* partName
 
     _bufManager.destMediaType   = !strcmp("mem", mediaType) ? OPTIMUS_MEDIA_TYPE_MEM : OPTIMUS_MEDIA_TYPE_STORE ;
     if ( !cacheAll2Mem ) cacheAll2Mem = !strcmp("mem", mediaType) ;
+    if ( !cacheAll2Mem ) cacheAll2Mem = (pktSz4BufManager <= _bufManager.transferUnitSz);
     if (cacheAll2Mem)
     {
             writeBackUnitSz             = pktSz4BufManager + _bufManager.transferUnitSz - 1;
@@ -149,7 +154,7 @@ int optimus_buf_manager_tplcmd_init(const char* mediaType,  const char* partName
         return OPT_DOWN_FAIL;
     }
     if (_bufManager.transferUnitSz > writeBackUnitSz) {
-        DWN_ERR("write back size %d < align size %d\n", writeBackUnitSz, _bufManager.mediaAlignSz);
+        DWN_ERR("write back size %d < align size %d\n", writeBackUnitSz, _bufManager.transferUnitSz);
         return OPT_DOWN_FAIL;
     }
     DWN_DBG("writeBackUnitSz = 0x%x, pktSz4BufManager = %lld\n", writeBackUnitSz, pktSz4BufManager);
@@ -197,7 +202,7 @@ int optimus_buf_manager_get_buf_for_bulk_transfer(char** pBuf, const unsigned wa
                         (u8*)(u64)_bufManager.partBaseOffset ;
 
     if (wantSz < _bufManager.transferUnitSz && !isLastTransfer) {
-        DWN_ERR("only last transfer can less 64K, this index %d at size 0x%u illegle\n", totalSlotNum + 1, wantSz);
+        DWN_ERR("only last transfer can less 64K, this index %d at size 0x%x illegle\n", totalSlotNum + 1, wantSz);
         return OPT_DOWN_FAIL;
     }
 
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
index 1d546f9..d8cb2ee 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
@@ -57,6 +57,18 @@ int v2_key_command(const int argc, char * const argv[], char *info)
 }
 #endif//#ifndef CONFIG_UNIFY_KEY_MANAGE
 
+#if SUM_FUNC_TIME_COST
+static inline int
+store_read_ops_(unsigned char *partition_name,unsigned char * buf, uint64_t off, uint64_t size)
+{
+    int ret = 0;
+    _func_cost_utime_yret(FlashRdTime, ret, store_read_ops, partition_name, buf, off, size);
+    return ret;
+}
+#else
+#define store_read_ops_ store_read_ops
+#endif//#if SUM_FUNC_TIME_COST
+
 static unsigned long _dtb_is_loaded = 0;
 
 
@@ -247,7 +259,11 @@ static int optimus_verify_bootloader(struct ImgBurnInfo* pDownInfo, u8* genSum)
 }
 
 
+#if SUM_FUNC_TIME_COST
+static u32 _optimus_cb_simg_write_media(const unsigned destAddrInSec, const unsigned dataSzInBy, const char* data)
+#else
 u32 optimus_cb_simg_write_media(const unsigned destAddrInSec, const unsigned dataSzInBy, const char* data)
+#endif//#if SUM_FUNC_TIME_COST
 {
     int ret = OPT_DOWN_OK;
     unsigned char* partName = (unsigned char*)OptimusImgBurnInfo.partName;
@@ -269,6 +285,16 @@ u32 optimus_cb_simg_write_media(const unsigned destAddrInSec, const unsigned dat
     return dataSzInBy;
 }
 
+#if SUM_FUNC_TIME_COST
+u32 optimus_cb_simg_write_media(const unsigned destAddrInSec, const unsigned dataSzInBy, const char* data)
+{
+    extern unsigned long FlashWrTime;
+    u32 ret = 0;
+    _func_cost_utime_yret(FlashWrTime, ret, _optimus_cb_simg_write_media, destAddrInSec, dataSzInBy, data);
+    return ret;
+}
+#endif//#if SUM_FUNC_TIME_COST
+
 //return value: the data size disposed
 static u32 optimus_download_sparse_image(struct ImgBurnInfo* pDownInfo, u32 dataSz, const u8* data)
 {
@@ -286,10 +312,14 @@ static u32 optimus_download_sparse_image(struct ImgBurnInfo* pDownInfo, u32 data
     return dataSz - unParsedDataLen;
 }
 
+#if SUM_FUNC_TIME_COST
+static u32 _optimus_download_normal_image(struct ImgBurnInfo* pDownInfo, u32 dataSz, const u8* data)
+#else
 //Normal image can write directly to NAND, best aligned to 16K when write
 //FIXME: check it aligned to 16K when called
 //1, write to media     2 -- save the verify info
 static u32 optimus_download_normal_image(struct ImgBurnInfo* pDownInfo, u32 dataSz, const u8* data)
+#endif//#if SUM_FUNC_TIME_COST
 {
     int ret = 0;
     u64 addrOrOffsetInBy = pDownInfo->nextMediaOffset;
@@ -308,6 +338,16 @@ static u32 optimus_download_normal_image(struct ImgBurnInfo* pDownInfo, u32 data
     return dataSz;
 }
 
+#if SUM_FUNC_TIME_COST
+static u32 optimus_download_normal_image(struct ImgBurnInfo* pDownInfo, u32 dataSz, const u8* data)
+{
+    extern unsigned long FlashWrTime;
+    u32 ret = 0;
+    _func_cost_utime_yret(FlashWrTime, ret, _optimus_download_normal_image, pDownInfo, dataSz, data);
+    return ret;
+}
+#endif// #if SUM_FUNC_TIME_COST
+
 static int optimus_storage_open(struct ImgBurnInfo* pDownInfo, const u8* data, const u32 dataSz)
 {
     int ret = OPT_DOWN_OK;
@@ -538,7 +578,7 @@ static int optimus_storage_read(struct ImgBurnInfo* pDownInfo, u64 addrOrOffsetI
                 }
                 else
                 {
-                    ret = store_read_ops(partName, buff, addrOrOffsetInBy, (u64)readSzInBy);
+                    ret = store_read_ops_(partName, buff, addrOrOffsetInBy, (u64)readSzInBy);
                     platform_busy_increase_un_reported_size(readSzInBy);
                 }
                 if (ret) {
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
index b5e0cbd..a0a10eb 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
@@ -95,6 +95,7 @@ unsigned v2_key_burn(const char* keyName, const u8* keyVal, const unsigned keyVa
 #define OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR      (OPTIMUS_SPARSE_IMG_LEFT_DATA_ADDR_LOW + OPTIMUS_SPARSE_IMG_LEFT_DATA_MAX_SZ)
 
 #define OPTIMUS_DOWNLOAD_SLOT_SZ                (64<<10)    //64K
+#define OPTIMUS_LOCAL_UPGRADE_SLOT_SZ           (OPTIMUS_DOWNLOAD_SLOT_SZ * 16) //1M per time for fatload
 #define OPTIMUS_DOWNLOAD_SLOT_SZ_SHIFT_BITS     (16)    //64K
 #define OPTIMUS_DOWNLOAD_SLOT_NUM               (OPTIMUS_DOWNLOAD_TRANSFER_BUF_TOTALSZ/OPTIMUS_DOWNLOAD_SLOT_SZ)
 
@@ -215,5 +216,28 @@ int optimus_work_mode_set(int workmode);
 //cannot called nested as it shares the same buffer
 const char* getenv_optimus(const char* name);
 
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+#define SUM_FUNC_TIME_COST 0
+#if SUM_FUNC_TIME_COST
+#define _func_cost_utime_yret(sum, ret, func, ...) do {\
+    unsigned long uTime = timer_get_us(); \
+    ret = func(__VA_ARGS__); \
+    sum += timer_get_us() - uTime; \
+} while(0)
+
+#define _func_cost_utime_nret(sum, func, ...) do {\
+    unsigned long uTime = timer_get_us(); \
+    func(__VA_ARGS__); \
+    sum += timer_get_us() - uTime; \
+} while(0)
+
+extern unsigned long ImageRdTime;
+extern unsigned long FlashRdTime;
+extern unsigned long FlashWrTime;
+
+#else
+#endif//#if SUM_FUNC_TIME_COST
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+
 #endif//ifndef __OPTIMUS_DOWNLOAD_H__
 
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
index 0c28ed3..57e647e 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
@@ -1174,9 +1174,13 @@ unsigned do_fat_get_bytesperclust(int fd)
     return bytesperclust;
 }
 
+#if SUM_FUNC_TIME_COST
+static long _do_fat_fread(int fd, __u8 *buffer, unsigned long maxsize)
+#else
 // clusters need to read:
 // data moddule: <first cluser not engouh cluster> + <n * Consecutive clusters > + <last cluster not engouh cluster>
 long do_fat_fread(int fd, __u8 *buffer, unsigned long maxsize)
+#endif// #if SUM_FUNC_TIME_COST
 {
         if (fd < 0) {
                 FAT_ERROR("Invalid fd %d\n", fd);
@@ -1352,6 +1356,16 @@ exit:
         return gotsize;
 }
 
+#if SUM_FUNC_TIME_COST
+long do_fat_fread(int fd, __u8 *buffer, unsigned long maxsize)
+{
+    extern unsigned long ImageRdTime;
+    long ret = 0;
+    _func_cost_utime_yret(ImageRdTime, ret, _do_fat_fread, fd, buffer, maxsize);
+    return ret;
+}
+#endif//#if SUM_FUNC_TIME_COST
+
 void
 do_fat_fclose(int fd)
 {
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
index 9df7fcd..a1fbbdb 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
@@ -128,6 +128,12 @@ _err:
     return NULL;
 }
 
+unsigned image_get_crc(HIMAGE hImg)
+{
+    ImgInfo_t* imgInfo = (ImgInfo_t*)hImg;
+    return imgInfo->imgHead.crc;
+}
+
 
 //close a Amlogic firmware image
 int image_close(HIMAGE hImg)
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
index 337b0f8..672fb9b 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
@@ -49,8 +49,8 @@ ConfigPara_t g_sdcBurnPara = {
     },
 
     .custom         = {
-        .eraseBootloader    = 1,//default to erase bootloader!
-        .eraseFlash         = 0,//default no erase flash for usb disk upgrade
+        .eraseBootloader    = 1,//default to erase bootloader! no effect for usb_upgrade
+        .eraseFlash         = 1,//default erase flash for all cases
         .bitsMap.eraseBootloader    = 1,
         .bitsMap.eraseFlash         = 1,
     },
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
index e94d32f..bacf90c 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
@@ -140,7 +140,7 @@ static int optimus_burn_one_partition(const char* partName, HIMAGE hImg, __hdle
     u32 thisReadLen     = 0;
     __hdle hImgItem     = NULL;
     char* downTransBuf  = NULL;//get buffer from optimus_buffer_manager
-    const unsigned ItemReadBufSz = OPTIMUS_DOWNLOAD_SLOT_SZ;//read this size from image item each time
+    const unsigned ItemReadBufSz = OPTIMUS_LOCAL_UPGRADE_SLOT_SZ;//read this size from image item each time
     unsigned sequenceNo = 0;
     const char* fileFmt = NULL;
     /*static */char _errInfo[512];
@@ -489,7 +489,10 @@ static int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite)
         const char** pCurKeysName = NULL;
         unsigned index = 0;
 
-        rc = run_command("aml_key_burn probe vfat sdc", 0);
+        if (strcmp("1", getenv("usb_update")))
+            rc = run_command("aml_key_burn probe vfat sdc", 0);
+        else
+            rc = run_command("aml_key_burn probe vfat udisk", 0);
         if (rc) {
                 DWN_ERR("Fail in probe for aml_key_burn\n");
                 return __LINE__;
@@ -591,6 +594,12 @@ static int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite)
 #define sdc_burn_aml_keys(fmt...)     0
 #endif// #if CONFIG_SUPPORT_SDC_KEYBURN
 
+#if SUM_FUNC_TIME_COST
+unsigned long ImageRdTime = 0;
+unsigned long FlashRdTime = 0;
+unsigned long FlashWrTime = 0;
+#endif//#if SUM_FUNC_TIME_COST
+
 int optimus_burn_with_cfg_file(const char* cfgFile)
 {
     extern ConfigPara_t g_sdcBurnPara ;
@@ -604,6 +613,7 @@ int optimus_burn_with_cfg_file(const char* cfgFile)
     u64 datapartsSz = 0;
     int eraseFlag = pSdcCfgPara->custom.eraseFlash;
 
+    optimus_buf_manager_init(16*1024);
     hImg = image_open("mmc", "0", "1", cfgFile);
     if (!hImg) {
         DWN_MSG("cfg[%s] not valid aml pkg, parse it as ini\n", cfgFile);
@@ -693,7 +703,16 @@ int optimus_burn_with_cfg_file(const char* cfgFile)
             eraseFlag = 0;
             DWN_MSG("Disable erase as data parts size is 0\n");
     }
-    ret = optimus_storage_init(eraseFlag);
+    if (eraseFlag && !strcmp("1", getenv("usb_update"))) {
+        ret = optimus_storage_init(0);
+        if (ret) {
+            DWN_ERR("FAil in init flash for usb upgrade\n");
+            return __LINE__;
+        }
+        ret = run_command("store erase data", 0);//erase after bootloader
+    }
+    else
+        ret = optimus_storage_init(eraseFlag);
     if (ret) {
         DWN_ERR("Fail to init stoarge for sdc burn\n");
         ret = __LINE__; goto _finish;
@@ -759,6 +778,9 @@ int optimus_burn_with_cfg_file(const char* cfgFile)
 
 _finish:
     image_close(hImg);
+#if SUM_FUNC_TIME_COST
+    DWN_MSG("[ms]ImageRdTime %ld, FlashRdTime %ld, FlashWrTime %ld\n", ImageRdTime/1000, FlashRdTime/1000, FlashWrTime/1000);
+#endif//#if SUM_FUNC_TIME_COST
     if (hUiProgress) optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret);
     optimus_report_burn_complete_sta(ret, pSdcCfgPara->custom.rebootAfterBurn);
     if (hUiProgress) optimus_progress_ui_release(hUiProgress);
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
index 0c6778c..cc02dfc 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
@@ -101,11 +101,13 @@ static int do_opt_keysburn_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * co
 
                 if (!_udiskProbe)
                 {
+#if 0
                         rc = run_command("usb start 0", 0);
                         if (rc) {
                                 _AML_KEY_ERR("Fail in mmcinfo\n");
                                 return __LINE__;
                         }
+#endif
                         rc = optimus_device_probe("usb", "0");
                         if (rc) {
                                 _AML_KEY_ERR("Fail to detect device mmc 0\n");
@@ -170,39 +172,18 @@ static int optimus_read_keyfile_2_mem(const char* filePath, u8* buf, unsigned* k
 {
         int rc = 0;
         unsigned keySz = 0;
+        char cmd[128];
 
         if (DEV_FILE_FMT_VFAT == _optKeyInfo.fileFmt)
         {
-                long hFile = -1;
-                unsigned readSz = 0;
-
-#if 1//FIXME: remove this mmcinfo
-                /*rc = run_command("mmcinfo 0", 0);*/
-                rc = optimus_sdc_burn_switch_to_extmmc();
-                if (rc) {
-                        DWN_ERR("Fail in mmcinfo\n");
-                        return __LINE__;
-                }
-#endif//
-                keySz = (unsigned)do_fat_get_fileSz(filePath);//can support both sdc and udisk
-                if (!keySz) {
-                        DWN_ERR("size is 0 of file [%s]\n", filePath);
-                        return __LINE__;
-                }
-
-                hFile = do_fat_fopen(filePath);
-                if (hFile < 0) {
-                        DWN_ERR("Fail to open file[%s]\n", filePath);
-                        return __LINE__;
-                }
-
-                readSz = do_fat_fread(hFile, buf, keySz);
-                if (readSz != keySz) {
-                        DWN_ERR("Want read %d bytes, but %d\n", keySz, readSz);
-                        return __LINE__;
-                }
-
-                do_fat_fclose(hFile);
+            if (strcmp("1", getenv("usb_update")))
+                sprintf(cmd, "fatload mmc 0 %p %s", buf, filePath);
+            else
+                sprintf(cmd, "fatload usb 0 %p %s", buf, filePath);
+            rc = run_command(cmd, 0);
+            if (rc) {
+                DWN_ERR("Fail in load key cmd[%s]\n", cmd);
+            }
         }
 
         *keyValLen = keySz;
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
index 91914fe..075b1d8 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
@@ -400,7 +400,10 @@ static int get_key_val_for_fmt_onlyone(const char* licenseName, u8* keyVal, unsi
 
         optimus_sdc_burn_switch_to_extmmc();
 
-        sprintf(_cmd, "fatload mmc 0:1 0x%p %s", keyVal, licenseName);
+        if (strcmp("1", getenv("usb_update")))
+            sprintf(_cmd, "fatload mmc 0:1 0x%p %s", keyVal, licenseName);
+        else
+            sprintf(_cmd, "fatload usb 0:1 0x%p %s", keyVal, licenseName);
         rc = run_command(_cmd, 0);
         if (rc) {
                 errorP("failed in cmd[%s]\n", _cmd);
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
index d5914b6..ced6465 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
@@ -30,6 +30,7 @@ Description:
 //#include "power_gate.h"
 #include <asm/arch/secure_apb.h>
 #include <asm/cpu_id.h>
+#include <amlogic/power_domain.h>
 
 /*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/
 #if !(defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC_OTG_294))
@@ -179,45 +180,14 @@ typedef union usb_r5 {
     } b;
 } usb_r5_t;
 
-#define PLL_REG32_16    (0xFF63A000 + 0x40)
-#define PLL_REG32_17    (0xFF63A000 + 0x44)
-#define PLL_REG32_18    (0xFF63A000 + 0x48)
+#define USB_REG_B 0xFF63A000
+#define PLL_REG32_16    (USB_REG_B + 0x40)
+#define PLL_REG32_17    (USB_REG_B + 0x44)
+#define PLL_REG32_18    (USB_REG_B + 0x48)
 #define USB_PHY2_ENABLE			0x10000000
 #define USB_PHY2_RESET			0x20000000
 
-static void set_usb_phy21_pll(void)
-{
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) =
-		USB_PHY2_PLL_PARAMETER_2;
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
-		USB_PHY2_PLL_PARAMETER_3;
-	udelay(100);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE))
-		& (~(USB_PHY2_RESET)));
-}
-
-#ifdef CONFIG_USB_DEVICE_V2
-#if (!defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)) || !defined(CONFIG_USB_POWER)
-static int b_platform_usb_check_sm1 (void)
-{
-	int rev_flag = 0;
-
-	cpu_id_t cpu_id = get_cpu_id();
-
-	if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1)
-		rev_flag = 1;
-	else
-		rev_flag = 0;
-
-	return rev_flag;
-}
-#endif
-#endif
-
-#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)
+#ifndef CONFIG_USB_AMLOGIC_PHY_V2
 static int b_platform_usb_check_g12b_revb (void)
 {
 	int rev_flag = 0;
@@ -235,25 +205,27 @@ static int b_platform_usb_check_g12b_revb (void)
 
 	return rev_flag;
 }
+#endif
 
-static void set_usb_phy21_sm1_pll(void)
+#ifdef CONFIG_USB_DEVICE_V2
+#if (!defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)) || !defined(CONFIG_USB_POWER)
+static int b_platform_usb_check_sm1 (void)
 {
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (0x09400414 | USB_PHY2_RESET | USB_PHY2_ENABLE);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) =
-		0x927e0000;
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
-		0xAC5F69E5;
-	udelay(100);
-	(*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
-		= (((0x09400414) | (USB_PHY2_ENABLE))
-		& (~(USB_PHY2_RESET)));
+	int rev_flag = 0;
+
+	cpu_id_t cpu_id = get_cpu_id();
+
+	if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1)
+		rev_flag = 1;
+	else
+		rev_flag = 0;
+
+	return rev_flag;
 }
 #endif
+#endif
 
 #ifdef CONFIG_USB_DEVICE_V2
-#define USB_REG_B 0xFF63A000
-
 void set_usb_phy21_tuning_update(void)
 {
 #if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)
@@ -288,21 +260,13 @@ void set_usb_phy21_tuning_update_reset(void)
 
 #endif
 
-#if 0
-void usb_phy21_pll_disable(void)
-{
-	(*(volatile uint32_t *)(unsigned long)PLL_REG32_16)
-		= ((USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET)
-		& (~(USB_PHY2_ENABLE)));
-}
-#endif
-
 #if (defined CONFIG_TXLX_USB)
 #define USB_RESET1       (volatile unsigned long *)0xffd01008
 #else
 #define USB_RESET1       (volatile unsigned long *)0xc1104408
 #endif
 
+extern void set_usb_pll(uint32_t volatile *phy2_pll_base);
 void set_usb_phy_config(int cfg)
 {
 	u2p_r0_t dev_u2p_r0;
@@ -315,27 +279,11 @@ void set_usb_phy_config(int cfg)
 	usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
 	int cnt;
 
-	u32 val;
 #ifndef CONFIG_USB_POWER
-	if (b_platform_usb_check_sm1() == 1) {
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-		*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-		mdelay(20);
-		val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-		*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-		udelay(100);
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-		*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
-	}
+	if (b_platform_usb_check_sm1() == 1)
+		power_domain_switch(PM_USB, PWR_ON);
 #else
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-	*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-	mdelay(20);
-	val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-	*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-	udelay(100);
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-	*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
+	power_domain_switch(PM_USB, PWR_ON);
 #endif
 
 	mdelay(50);
@@ -389,14 +337,7 @@ void set_usb_phy_config(int cfg)
 
 	printf("wait for phy ready count is %d\n", cnt);
 	mdelay(20);
-#ifndef CONFIG_USB_AMLOGIC_PHY_V2
-	if (b_platform_usb_check_sm1())
-		set_usb_phy21_sm1_pll();
-	else
-		set_usb_phy21_pll();
-#else
-	set_usb_phy21_pll();
-#endif
+	set_usb_pll((uint32_t volatile *)USB_REG_B);
 
 	mdelay(20);
 	//--------------------------------------------------
diff --git a/drivers/vpu/aml_vpu_power_init.c b/drivers/vpu/aml_vpu_power_init.c
index 373d40e..ecb72e2 100644
--- a/drivers/vpu/aml_vpu_power_init.c
+++ b/drivers/vpu/aml_vpu_power_init.c
@@ -60,7 +60,24 @@ void vpu_module_init_config(void)
 	/* dmc_arb_config */
 	vpu_vcbus_write(VPU_RDARB_MODE_L1C1, 0x0); //0x210000
 	vpu_vcbus_write(VPU_RDARB_MODE_L1C2, 0x10000);
-	vpu_vcbus_write(VPU_RDARB_MODE_L2C1, 0x900000);
+	switch (vpu_conf.data->chip_type) {
+	case VPU_CHIP_GXBB:
+	case VPU_CHIP_GXTVBB:
+	case VPU_CHIP_GXL:
+	case VPU_CHIP_GXM:
+	case VPU_CHIP_TXL:
+	case VPU_CHIP_TXLX:
+	case VPU_CHIP_AXG:
+	case VPU_CHIP_TXHD:
+	case VPU_CHIP_G12A:
+	case VPU_CHIP_G12B:
+	case VPU_CHIP_SM1:
+		vpu_vcbus_write(VPU_RDARB_MODE_L2C1, 0x900000);
+		break;
+	default:
+		vpu_vcbus_write(VPU_RDARB_MODE_L2C1, 0x20000);
+		break;
+	}
 	vpu_vcbus_write(VPU_WRARB_MODE_L2C1, 0x20000);
 
 	VPUPR("%s\n", __func__);
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index bccc3e3..b49934d 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -131,27 +131,33 @@ static int dirdelim(char *str)
  */
 static void get_name(dir_entry *dirent, char *s_name)
 {
-	char *ptr;
+	char *ptr, *dot = NULL;
 
 	memcpy(s_name, dirent->name, 8);
 	s_name[8] = '\0';
 	ptr = s_name;
 	while (*ptr && *ptr != ' ')
 		ptr++;
+	if (dirent->lcase & 0x08) {	/* down case for 8 */
+		downcase(s_name);
+	}
 	if (dirent->ext[0] && dirent->ext[0] != ' ') {
 		*ptr = '.';
 		ptr++;
+		dot = ptr;
 		memcpy(ptr, dirent->ext, 3);
 		ptr[3] = '\0';
 		while (*ptr && *ptr != ' ')
 			ptr++;
 	}
 	*ptr = '\0';
+	if (dot && dirent->lcase & 0x10) {	/* down case for 3 */
+		downcase(dot);
+	}
 	if (*s_name == DELETED_FLAG)
 		*s_name = '\0';
 	else if (*s_name == aRING)
 		*s_name = DELETED_FLAG;
-	downcase(s_name);
 }
 
 /*
@@ -544,7 +550,6 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster,
 		*l_name = '\0';
 	else if (*l_name == aRING)
 		*l_name = DELETED_FLAG;
-	downcase(l_name);
 
 	/* Return the real directory entry */
 	memcpy(retdent, realdent, sizeof(dir_entry));
@@ -893,7 +898,6 @@ int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
 
 	/* Make a copy of the filename and convert it to lowercase */
 	strcpy(fnamecopy, filename);
-	downcase(fnamecopy);
 
 	if (*fnamecopy == '\0') {
 		if (!dols)
diff --git a/include/amlogic/aml_lcd.h b/include/amlogic/aml_lcd.h
index 8a20700..99608ba 100644
--- a/include/amlogic/aml_lcd.h
+++ b/include/amlogic/aml_lcd.h
@@ -54,6 +54,8 @@
 #define LCD_EXT_CMD_TYPE_CMD_DELAY    0x00
 #define LCD_EXT_CMD_TYPE_CMD2_DELAY   0x01  /* for i2c device 2nd addr */
 #define LCD_EXT_CMD_TYPE_NONE         0x10
+#define LCD_EXT_CMD_TYPE_CMD_BIN      0xb0
+#define LCD_EXT_CMD_TYPE_CMD2_BIN     0xb1  /* for i2c device 2nd addr */
 #define LCD_EXT_CMD_TYPE_CMD          0xc0
 #define LCD_EXT_CMD_TYPE_CMD2         0xc1  /* for i2c device 2nd addr */
 #define LCD_EXT_CMD_TYPE_GPIO         0xf0
diff --git a/include/amlogic/aml_lcd_vout.h b/include/amlogic/aml_lcd_vout.h
index 77c0264..082126f 100644
--- a/include/amlogic/aml_lcd_vout.h
+++ b/include/amlogic/aml_lcd_vout.h
@@ -47,6 +47,7 @@ extern unsigned int lcd_debug_print_flag;
 
 /* ******** clk_ctrl ******** */
 #define CLK_CTRL_LEVEL              28 /* [30:28] */
+#define CLK_CTRL_FRAC_SHIFT         24 /* [24] */
 #define CLK_CTRL_FRAC               0  /* [18:0] */
 
 
diff --git a/include/amlogic/power_domain.h b/include/amlogic/power_domain.h
new file mode 100644
index 0000000..a57ddcc
--- a/dev/null
+++ b/include/amlogic/power_domain.h
@@ -0,0 +1,44 @@
+/*
+ * include/linux/amlogic/power_domain.h
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#define PWR_ON	0
+#define PWR_OFF	1
+
+#define	PM_DOS_HCODEC		0
+#define	PM_DOS_VDEC		1
+#define	PM_DOS_HEVC		2
+#define	PM_WAVE420L		3
+#define	PM_CSI			6
+#define	PM_VPU			8
+#define	PM_NN			16
+#define	PM_USB			17
+#define	PM_PCIE0		18
+#define	PM_GE2D			19
+#define	PM_PCIE1		20
+#define	PM_DSPA			21
+#define	PM_DSPB			22
+#define	PM_DEMOD		23
+
+#ifdef CONFIG_AML_POWER_DOMAIN
+void power_domain_switch(int pwr_domain, bool pwr_switch);
+#else
+#if (defined CONFIG_USB_DEVICE_V2)
+static void power_domain_switch(int pwr_domain, bool pwr_switch)
+{
+}
+#endif
+#endif
diff --git a/lib/libavb/avb_slot_verify.c b/lib/libavb/avb_slot_verify.c
index 6b81fae..9c4c92d 100644
--- a/lib/libavb/avb_slot_verify.c
+++ b/lib/libavb/avb_slot_verify.c
@@ -1279,6 +1279,10 @@ fail:
 }
 
 void avb_slot_verify_data_free(AvbSlotVerifyData* data) {
+  if (data == NULL) {
+    return;
+  }
+
   if (data->ab_suffix != NULL) {
     avb_free(data->ab_suffix);
   }