| author | zhiguang.ouyang <zhiguang.ouyang@amlogic.com> | 2019-12-05 04:01:03 (GMT) |
|---|---|---|
| committer | Haixiang Bao <haixiang.bao@amlogic.com> | 2019-12-13 08:48:47 (GMT) |
| commit | ccbf700d7684b9e6fc8d9e2ce175fcff4d98166d (patch) | |
| tree | 410cb4e3ac90e66d94fca9ec87fa3621abf97984 | |
| parent | ae0ecd1379e088680bab4c06926e21f3dcf9b846 (diff) | |
| download | uboot-ccbf700d7684b9e6fc8d9e2ce175fcff4d98166d.zip uboot-ccbf700d7684b9e6fc8d9e2ce175fcff4d98166d.tar.gz uboot-ccbf700d7684b9e6fc8d9e2ce175fcff4d98166d.tar.bz2 | |
ddr: timing: LPDDR4_PHY_V_0_1_21 add training_offset bl33_v2015 [2/4]
PD#TV-12700
Problem:
xiaomi 2pcs ddr4 2layer training window deviation.
Solution:
manual correct window after training.
Verify:
test pass at u212/w400/x301/ab301
Change-Id: I5cfeeee74ef1259c388d97829ad70b70b86c6b3c
Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com>
| -rw-r--r-- | arch/arm/include/asm/arch-g12a/timing.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-g12b/timing.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tl1/timing.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tm2/timing.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h index 88a907a..0ba6cce 100644 --- a/arch/arm/include/asm/arch-g12a/timing.h +++ b/arch/arm/include/asm/arch-g12a/timing.h @@ -387,7 +387,7 @@ typedef struct ddr_set{ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h index 88a907a..0ba6cce 100644 --- a/arch/arm/include/asm/arch-g12b/timing.h +++ b/arch/arm/include/asm/arch-g12b/timing.h @@ -387,7 +387,7 @@ typedef struct ddr_set{ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify diff --git a/arch/arm/include/asm/arch-tl1/timing.h b/arch/arm/include/asm/arch-tl1/timing.h index 8dc22f0..d0430b1 100644 --- a/arch/arm/include/asm/arch-tl1/timing.h +++ b/arch/arm/include/asm/arch-tl1/timing.h @@ -376,7 +376,7 @@ typedef struct ddr_set{ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify diff --git a/arch/arm/include/asm/arch-tm2/timing.h b/arch/arm/include/asm/arch-tm2/timing.h index 8dc22f0..d0430b1 100644 --- a/arch/arm/include/asm/arch-tm2/timing.h +++ b/arch/arm/include/asm/arch-tm2/timing.h @@ -376,7 +376,7 @@ typedef struct ddr_set{ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify |