Merge "ddr: driver:LPDDR4_PHY_V_0_1_20 update G12A/G12B/TL1/TM2/A1/C1 bl33_v2015 [2/4]" into amlogic-dev-ref

12 files changed, 64 insertions, 17 deletions

diff --git a/arch/arm/include/asm/arch-g12a/ddr_define.h b/arch/arm/include/asm/arch-g12a/ddr_define.h
index 2c1cc6e..c52235c 100644
--- a/arch/arm/include/asm/arch-g12a/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12a/ddr_define.h
@@ -261,6 +261,7 @@
 #define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP						(0<<25)
 #endif
 #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID					(1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION						(1<<29)
 #define DDR_FUNC							(DDR_FUNC_D2PLL					| \
 											DDR_FUNC_LP						| \
 											DDR_FUNC_ZQ_PD					| \
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h
index afa5260..6118709 100644
--- a/arch/arm/include/asm/arch-g12a/timing.h
+++ b/arch/arm/include/asm/arch-g12a/timing.h
@@ -97,6 +97,7 @@ typedef struct retraining_set{
 	unsigned short     csr_hwtlpcsenb;
 	unsigned short     csr_acsmctrl13;
 	unsigned short     csr_acsmctrl23;
+	unsigned char     csr_soc_vref_dac1_dfe[36];
 	//unsigned short     DqDqsRcvCntrl[8];
 	//unsigned short     rev_41;
 }__attribute__ ((packed)) retraining_set_t;
@@ -297,7 +298,7 @@ typedef struct ddr_set{
 	unsigned	short	write_dqs_delay[16];
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	soc_bit_vref[32];
+	unsigned	char	soc_bit_vref[36];
 	unsigned	char	dram_bit_vref[32];
 	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
 	unsigned	char	dfi_mrl;
diff --git a/arch/arm/include/asm/arch-g12b/ddr_define.h b/arch/arm/include/asm/arch-g12b/ddr_define.h
index b4fef99..e4433f8 100644
--- a/arch/arm/include/asm/arch-g12b/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12b/ddr_define.h
@@ -259,6 +259,7 @@
 #define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP						(0<<25)
 #endif
 #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID					(1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION						(1<<29)
 #define DDR_FUNC							(DDR_FUNC_D2PLL					| \
 											DDR_FUNC_LP						| \
 											DDR_FUNC_ZQ_PD					| \
diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h
index 884e3e2..ccfd31f 100644
--- a/arch/arm/include/asm/arch-g12b/timing.h
+++ b/arch/arm/include/asm/arch-g12b/timing.h
@@ -97,6 +97,7 @@ typedef struct retraining_set{
 	unsigned short     csr_hwtlpcsenb;
 	unsigned short     csr_acsmctrl13;
 	unsigned short     csr_acsmctrl23;
+	unsigned char     csr_soc_vref_dac1_dfe[36];
 	//unsigned short     DqDqsRcvCntrl[8];
 	//unsigned short     rev_41;
 }__attribute__ ((packed)) retraining_set_t;
@@ -298,7 +299,7 @@ typedef struct ddr_set{
 //*/
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	soc_bit_vref[32];
+	unsigned	char	soc_bit_vref[36];
 	unsigned	char	dram_bit_vref[32];
 //		/*
 	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
diff --git a/arch/arm/include/asm/arch-tl1/ddr_define.h b/arch/arm/include/asm/arch-tl1/ddr_define.h
index 07e49f3..2f1c7bb 100644
--- a/arch/arm/include/asm/arch-tl1/ddr_define.h
+++ b/arch/arm/include/asm/arch-tl1/ddr_define.h
@@ -247,6 +247,7 @@
 #define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP						(0<<25)
 #endif
 #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID					(1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION						(1<<29)
 #define DDR_FUNC							(DDR_FUNC_D2PLL					| \
 											DDR_FUNC_LP						| \
 											DDR_FUNC_ZQ_PD					| \
diff --git a/arch/arm/include/asm/arch-tl1/timing.h b/arch/arm/include/asm/arch-tl1/timing.h
index 77e6c2c..6bad442 100644
--- a/arch/arm/include/asm/arch-tl1/timing.h
+++ b/arch/arm/include/asm/arch-tl1/timing.h
@@ -86,6 +86,7 @@ typedef struct retraining_set{
 	unsigned short     csr_hwtlpcsenb;
 	unsigned short     csr_acsmctrl13;
 	unsigned short     csr_acsmctrl23;
+	unsigned char     csr_soc_vref_dac1_dfe[36];
 	//unsigned short     DqDqsRcvCntrl[8];
 	//unsigned short     rev_41;
 }__attribute__ ((packed)) retraining_set_t;
@@ -287,7 +288,7 @@ typedef struct ddr_set{
 //*/
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	soc_bit_vref[32];
+	unsigned	char	soc_bit_vref[36];
 	unsigned	char	dram_bit_vref[32];
 //		/*
 	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
diff --git a/arch/arm/include/asm/arch-tm2/ddr_define.h b/arch/arm/include/asm/arch-tm2/ddr_define.h
index 07e49f3..2f1c7bb 100644
--- a/arch/arm/include/asm/arch-tm2/ddr_define.h
+++ b/arch/arm/include/asm/arch-tm2/ddr_define.h
@@ -247,6 +247,7 @@
 #define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP						(0<<25)
 #endif
 #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID					(1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION						(1<<29)
 #define DDR_FUNC							(DDR_FUNC_D2PLL					| \
 											DDR_FUNC_LP						| \
 											DDR_FUNC_ZQ_PD					| \
diff --git a/arch/arm/include/asm/arch-tm2/timing.h b/arch/arm/include/asm/arch-tm2/timing.h
index 77e6c2c..6bad442 100644
--- a/arch/arm/include/asm/arch-tm2/timing.h
+++ b/arch/arm/include/asm/arch-tm2/timing.h
@@ -86,6 +86,7 @@ typedef struct retraining_set{
 	unsigned short     csr_hwtlpcsenb;
 	unsigned short     csr_acsmctrl13;
 	unsigned short     csr_acsmctrl23;
+	unsigned char     csr_soc_vref_dac1_dfe[36];
 	//unsigned short     DqDqsRcvCntrl[8];
 	//unsigned short     rev_41;
 }__attribute__ ((packed)) retraining_set_t;
@@ -287,7 +288,7 @@ typedef struct ddr_set{
 //*/
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	soc_bit_vref[32];
+	unsigned	char	soc_bit_vref[36];
 	unsigned	char	dram_bit_vref[32];
 //		/*
 	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
diff --git a/board/amlogic/configs/tl1_t309_v1.h b/board/amlogic/configs/tl1_t309_v1.h
index 0036b10..a548ec5 100644
--- a/board/amlogic/configs/tl1_t309_v1.h
+++ b/board/amlogic/configs/tl1_t309_v1.h
@@ -379,7 +379,7 @@
 #define CONFIG_DDR_FULL_TEST			0 //0:disable, 1:enable. ddr full test
 #define CONFIG_CMD_DDR_D2PLL			0 //0:disable, 1:enable. d2pll cmd
 #define CONFIG_CMD_DDR_TEST				0 //0:disable, 1:enable. ddrtest cmd
-#define CONFIG_CMD_DDR_TEST_G12			0 //0:disable, 1:enable. G12 ddrtest cmd
+#define CONFIG_CMD_DDR_TEST_G12			1 //0:disable, 1:enable. G12 ddrtest cmd
 #define CONFIG_DDR_LOW_POWER			0 //0:disable, 1:enable. ddr clk gate for lp
 #define CONFIG_DDR_ZQ_PD				0 //0:disable, 1:enable. ddr zq power down
 #define CONFIG_DDR_USE_EXT_VREF			0 //0:disable, 1:enable. ddr use external vref
diff --git a/board/amlogic/tl1_skt_v1/firmware/timing.c b/board/amlogic/tl1_skt_v1/firmware/timing.c
index 104436b..b706ab2 100644
--- a/board/amlogic/tl1_skt_v1/firmware/timing.c
+++ b/board/amlogic/tl1_skt_v1/firmware/timing.c
@@ -120,6 +120,7 @@ ddr_set_t __ddr_setting[] = {
 	.magic					= DRAM_CFG_MAGIC,
 	.diagnose				= CONFIG_DIAGNOSE_DISABLE,
 	.fast_boot[0]			= 6,
+	.ddr_func				= DDR_FUNC|DDR_FUNC_CONFIG_DFE_FUNCTION,
 //	.slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT,
 //	.dqs_offset_value=0x1<<4,//bit 0-2 read offset ,bit 3 read offset direction ,bit 4-6 write offset,bit 7 write offset direction.
 },
@@ -190,7 +191,7 @@ ddr_set_t __ddr_setting[] = {
 
 
 	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
-	.ddr_func				= DDR_FUNC,
+	.ddr_func				= DDR_FUNC|DDR_FUNC_CONFIG_DFE_FUNCTION,
 	.magic					= DRAM_CFG_MAGIC,
 //	.slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT,
 //	.dqs_offset_value=0x1,//bit 0-2 read offset ,bit 3 read offset direction ,bit 4-6 write offset,bit 7 write offset direction.
diff --git a/board/amlogic/tl1_t309_v1/firmware/timing.c b/board/amlogic/tl1_t309_v1/firmware/timing.c
index 7a717fb..de10679 100644
--- a/board/amlogic/tl1_t309_v1/firmware/timing.c
+++ b/board/amlogic/tl1_t309_v1/firmware/timing.c
@@ -113,7 +113,7 @@ ddr_set_t __ddr_setting[] = {
 	.ddr_lpddr34_dq_remap	= {4,5,6,7,0,2,3,1,  15,14,13,12,11,9,10,8,   20,18,17,16,23,22,19,21,   30,31,25,24,26,28,29,27},
 	.dram_rtt_nom_wr_park	= {00,00},
 	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
-	.ddr_func				= DDR_FUNC,
+	.ddr_func				= DDR_FUNC|DDR_FUNC_CONFIG_DFE_FUNCTION,
 	.magic					= DRAM_CFG_MAGIC,
 	.diagnose				= CONFIG_DIAGNOSE_DISABLE,
 	.bitTimeControl_2d		= 1,	//training time setting,=1,200ms;=7,2s
@@ -186,9 +186,10 @@ ddr_set_t __ddr_setting[] = {
 
 
 	.pll_ssc_mode			= (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
-	.ddr_func				= DDR_FUNC,
+	.ddr_func				= DDR_FUNC|DDR_FUNC_CONFIG_DFE_FUNCTION,
 	.magic					= DRAM_CFG_MAGIC,
-	.fast_boot[0]			= 1,
+	.fast_boot[0]			= 0,
+	.fast_boot[2]			= (1<<3)|(2<<0),
 },
 //*/
 {
diff --git a/common/cmd_ddr_test_g12.c b/common/cmd_ddr_test_g12.c
index 3824191..b0b8075 100644
--- a/common/cmd_ddr_test_g12.c
+++ b/common/cmd_ddr_test_g12.c
@@ -101,7 +101,7 @@ int ddr_get_chip_id(void)
 	//return CHIP_ID_MASK;
 }
 
-char CMD_VER[] = "Ver_12";
+char CMD_VER[] = "Ver_13";
 ddr_base_address_table_t  __ddr_base_address_table[] = {
 	//g12a
 	{
@@ -348,6 +348,7 @@ typedef struct retraining_set{
 	unsigned short     csr_hwtlpcsenb;
 	unsigned short     csr_acsmctrl13;
 	unsigned short     csr_acsmctrl23;
+	unsigned char     csr_soc_vref_dac1_dfe[36];
 	//unsigned short     rev_41;
 } retraining_set_t;
 typedef struct ddr_set{
@@ -544,7 +545,7 @@ typedef struct ddr_set{
 //	*/
 	unsigned	short	write_dq_bit_delay[72];
 	unsigned	short	read_dqs_gate_delay[16];
-	unsigned	char	soc_bit_vref[32];
+	unsigned	char	soc_bit_vref[36];
 	unsigned	char	dram_bit_vref[32];
 	///*
 	unsigned	char	rever3;//read_dqs  read_dq,write_dqs, write_dq
@@ -2166,6 +2167,7 @@ static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_siz
 //*/
 int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+	check_base_address();
 	char *endp;
 	unsigned long   loop = 1;
 	unsigned int   print_flag =1;
@@ -6323,6 +6325,7 @@ unsigned int cpu_ddr_test(unsigned test_init_start,unsigned int start_add, unsig
 
 int do_cpu_ddr_test (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+	check_base_address();
 	//ddr_cpu_test 0x1080000 0x10000000 0x2000000 0xffffffff 10  //size do not overlap
 	int i=0;
 	printf("\nargc== 0x%08x\n", argc);
@@ -6898,7 +6901,7 @@ int do_read_ddr_training_data(char log_level,ddr_set_t *ddr_set_t_p)
 		//((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value)
 		uint32_t vref_t_count=0;
 		for (t_count=0;t_count<72;t_count++)
-		{
+		{//add normal vref0---vrefDac0 for just 1->x transitions
 			add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40));
 			dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
 			delay_org=dq_bit_delay[t_count];
@@ -6908,6 +6911,31 @@ int do_read_ddr_training_data(char log_level,ddr_set_t *ddr_set_t_p)
 				vref_t_count=((((t_count%36)/9)*8)+(t_count%9));
 				ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp;
 			}
+			if ((t_count%9) == 8)
+			{
+				vref_t_count=32+((((t_count%36)/9)));
+				ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp;
+			}
+
+			printf_log(log_level,"\n t_count: %04d %04d  %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]);
+		}
+		printf_log(log_level,"\n soc vref-dfe dac1 0--->x : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367   DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345");
+		for (t_count=0;t_count<72;t_count++)
+		{ //add dfe vref1---vrefDac1 for just 0->x transitions
+			add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x30));
+			dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
+			delay_org=dq_bit_delay[t_count];
+			delay_temp=((delay_org));
+			if (t_count<35)
+			{
+				vref_t_count=((((t_count%36)/9)*8)+(t_count%9));
+				ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp;
+			}
+			if ((t_count%9) == 8)
+			{
+				vref_t_count=32+((((t_count%36)/9)));
+				ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp;
+			}
 			printf_log(log_level,"\n t_count: %04d %04d  %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]);
 		}
 		printf_log(log_level,"\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0.   DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0.");
@@ -7347,9 +7375,13 @@ int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, cha
 		for ( temp_count=0;temp_count<16;temp_count++)
 		//printf("\n.read_dqs_gate_delay[%d]=%d,",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count]);
 		printf("\n.read_dqs_gate_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count],ddr_set_t_p->read_dqs_gate_delay[temp_count]);
-		for ( temp_count=0;temp_count<32;temp_count++)
+		for ( temp_count=0;temp_count<36;temp_count++)
 		//printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]);
 		printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]);
+		for ( temp_count=0;temp_count<36;temp_count++)
+		//printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]);
+		printf("\n.retraining_extra_set_t.csr_soc_vref_dac1_dfe[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[temp_count],ddr_set_t_p->retraining_extra_set_t.csr_soc_vref_dac1_dfe[temp_count]);
+		//printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]);
 		for ( temp_count=0;temp_count<32;temp_count++)
 		//printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]);
 		printf("\n.dram_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->dram_bit_vref[temp_count],ddr_set_t_p->dram_bit_vref[temp_count]);
@@ -7405,18 +7437,21 @@ static int ddr_do_store_ddr_parameter_ops(uint8_t *buffer, uint32_t length)
 	//	current = store_dev;
 	//	return 0;
 	//}
+	char str[1024]="";
 	if (!current)
 	{
-		char str[1024]="";
 		sprintf(str,"store init");
 		run_command(str,0);
 	}
-	struct storage_t *store = current;//store_get_current();
+
 	char *name = NULL;
 	{
 		name ="ddr-parameter";
 		printf("\nstore rsv write ddr-parameter 0x%08x 0x%08x\n",(uint32_t)(uint64_t)buffer,length);
-		return store->write_rsv(name, length, (u_char *)buffer);
+		//struct storage_t *store = current;//store_get_current();
+		//return store->write_rsv(name, length, (u_char *)buffer);
+		sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x\n",(uint32_t)(uint64_t)buffer,length);
+		run_command(str,0);
 	}
 }
 
@@ -9661,6 +9696,8 @@ int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
 	#define G12_D2PLL_CMD_SWEEP_EE_VOLTAGE_FREQUENCY_TABLE_TEST  0x32
 	#define G12_D2PLL_CMD_DDR_EYE_TEST  0x41
 	#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE    0x42
+	#define G12_D2PLL_CMD_DDR_EYE_TEST_DAC1  0x43
+	#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1    0x44
 
 	#define G12_D2PLL_CMD_DDR_DVFS_TEST  0x51
 
@@ -9852,7 +9889,7 @@ int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
 		//12 if reinit when test dq  13 pass_to_fail_flag    14  test_dmc_or_cpu
 		para_meter[5]=(para_meter[9]<<28)|(para_meter[10]<<24)|(para_meter[11]<<20)|(para_meter[12]<<21)|(para_meter[13]<<22)|(para_meter[14]<<25)|(para_meter[5]<<0);
 	}
-	if ((window_test_stick_cmd_value == G12_D2PLL_CMD_DDR_EYE_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE))
+	if ((window_test_stick_cmd_value >= G12_D2PLL_CMD_DDR_EYE_TEST)&& (window_test_stick_cmd_value <= G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1))
 	{
 		para_meter[3]=(para_meter[3]<<0)|(para_meter[4]<<8)|(para_meter[5]<<16)|(para_meter[6]<<24);
 		para_meter[4]=(para_meter[7]<<0)|(para_meter[8]<<8)|(para_meter[9]<<16)|(para_meter[10]<<24);