usb: BL33 add the usb power domain control [1/1]

PD#SWPL-18358

Problem:
uboot add the usb power domain control for TM2 and SM1

Solution:
bl33 add the usb power domain controlfor TM2 and SM1

Verify:
S905D3

Change-Id: I5a963ce17d581b656f18f50fc8e8d501b7ea6b40
Signed-off-by: Yue Wang <yue.wang@amlogic.com>

5 files changed, 16 insertions, 55 deletions

diff --git a/arch/arm/cpu/armv8/g12a/usb.c b/arch/arm/cpu/armv8/g12a/usb.c
index dec804a..2eb99cf 100644
--- a/arch/arm/cpu/armv8/g12a/usb.c
+++ b/arch/arm/cpu/armv8/g12a/usb.c
@@ -22,7 +22,7 @@
 #include <asm/arch/usb-v2.h>
 #include <asm/arch/romboot.h>
 #include <asm/cpu_id.h>
-
+#include <amlogic/power_domain.h>
 
 static struct amlogic_usb_config * g_usb_cfg[BOARD_USB_MODE_MAX][USB_PHY_PORT_MAX];
 static int Rev_flag = 0;
@@ -50,14 +50,8 @@ struct amlogic_usb_config * board_usb_start(int mode,int index)
 	printf("USB3.0 XHCI init start\n");
 	board_usb_check_sm1();
 
-	if (board_usb_get_sm1_type() == 1) {
-		writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_SLEEP0);
-		writel((readl(HHI_MEM_PD_REG0) & (~(0x3<<30))), HHI_MEM_PD_REG0);
-		udelay(100);
-		writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_ISO0);
-	}
+	if (board_usb_get_sm1_type() == 1)
+		power_domain_switch(PM_USB, PWR_ON);
 
 	if (mode < 0 || mode >= BOARD_USB_MODE_MAX||!g_usb_cfg[mode][index])
 		return 0;
diff --git a/arch/arm/cpu/armv8/tm2/usb.c b/arch/arm/cpu/armv8/tm2/usb.c
index 367ba4b..ab27209 100644
--- a/arch/arm/cpu/armv8/tm2/usb.c
+++ b/arch/arm/cpu/armv8/tm2/usb.c
@@ -21,7 +21,7 @@
 
 #include <asm/arch/usb-v2.h>
 #include <asm/arch/romboot.h>
-
+#include <amlogic/power_domain.h>
 
 static struct amlogic_usb_config * g_usb_cfg[BOARD_USB_MODE_MAX][USB_PHY_PORT_MAX];
 
@@ -52,14 +52,7 @@ int usb_index = 0;
 void board_usb_init(struct amlogic_usb_config * usb_cfg,int mode)
 {
 #ifdef CONFIG_USB_POWER
-	writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_SLEEP0);
-	writel((readl(HHI_MEM_PD_REG0) & (~(0x3<<30))), HHI_MEM_PD_REG0);
-
-	udelay(100);
-
-	writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1<<17))),
-			P_AO_RTI_GEN_PWR_ISO0);
+	power_domain_switch(PM_USB, PWR_ON);
 #endif
 
 	if (mode < 0 || mode >= BOARD_USB_MODE_MAX || !usb_cfg)
diff --git a/drivers/usb/gadget/fastboot/platform.c b/drivers/usb/gadget/fastboot/platform.c
index c6b7ae2..eb3ab53 100644
--- a/drivers/usb/gadget/fastboot/platform.c
+++ b/drivers/usb/gadget/fastboot/platform.c
@@ -29,6 +29,7 @@ Description:
  #include "platform.h"
 #include <asm/cpu_id.h>
 #include <asm/arch/secure_apb.h>
+#include <amlogic/power_domain.h>
 
 /*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/
 #if !(defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC_OTG_294))
@@ -273,26 +274,12 @@ void f_set_usb_phy_config(void)
 	u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE;
 	usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
 	int cnt;
-	u32 val;
-
-	if (f_platform_usb_check_sm1() == 1) {
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-		*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-		val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-		*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-		udelay(100);
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-		*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
-	}
+
+	if (f_platform_usb_check_sm1() == 1)
+		power_domain_switch(PM_USB, PWR_ON);
 
 #ifdef CONFIG_USB_POWER
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-	*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-	val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-	*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-	udelay(100);
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-	*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
+	power_domain_switch(PM_USB, PWR_ON);
 #endif
 
 #ifdef CONFIG_USB_DEVICE_V2
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
index f7084b6..ced6465 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
@@ -30,6 +30,7 @@ Description:
 //#include "power_gate.h"
 #include <asm/arch/secure_apb.h>
 #include <asm/cpu_id.h>
+#include <amlogic/power_domain.h>
 
 /*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/
 #if !(defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC_OTG_294))
@@ -278,27 +279,11 @@ void set_usb_phy_config(int cfg)
 	usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
 	int cnt;
 
-	u32 val;
 #ifndef CONFIG_USB_POWER
-	if (b_platform_usb_check_sm1() == 1) {
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-		*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-		mdelay(20);
-		val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-		*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-		udelay(100);
-		val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-		*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
-	}
+	if (b_platform_usb_check_sm1() == 1)
+		power_domain_switch(PM_USB, PWR_ON);
 #else
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
-	*P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
-	mdelay(20);
-	val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
-	*P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
-	udelay(100);
-	val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
-	*P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
+	power_domain_switch(PM_USB, PWR_ON);
 #endif
 
 	mdelay(50);
diff --git a/include/amlogic/power_domain.h b/include/amlogic/power_domain.h
index 5b5f1e9..a57ddcc 100644
--- a/include/amlogic/power_domain.h
+++ b/include/amlogic/power_domain.h
@@ -36,7 +36,9 @@
 #ifdef CONFIG_AML_POWER_DOMAIN
 void power_domain_switch(int pwr_domain, bool pwr_switch);
 #else
+#if (defined CONFIG_USB_DEVICE_V2)
 static void power_domain_switch(int pwr_domain, bool pwr_switch)
 {
 }
 #endif
+#endif