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1
2/*
3 * include/aml_i2c.h
4 *
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20*/
21
22#ifndef __AML_I2C_H__
23#define __AML_I2C_H__
24
25#include <common.h>
26#include <linux/compiler.h>
27#include <asm/arch/i2c.h>
28
29#define AML_I2C_MAX_TOKENS 8
30
31/*I2C_CONTROL_REG 0x2140/0x2148*/
32struct aml_i2c_reg_ctrl {
33 unsigned int start:1; /*[0] Set to 1 to start list processing*/
34 /*Setting this bit to 0 while the list processor is operating causes the list
35 processor to abort the current I2C operation and generate an I2C STOP
36 command on the I2C bus. Normally this bit is set to 1 and left high
37 until processing is complete. To re-start the list processor with a
38 new list (after a previous list has been exhausted), simply set this
39 bit to zero then to one.*/
40 unsigned int ack_ignore:1; /*[1] Set to 1 to disable I2C ACK detection.*/
41 /*The I2C bus uses an ACK signal after every byte transfer to detect
42 problems during the transfer. Current Software implementations of the
43 I2C bus ignore this ACK. This bit is for compatibility with the current
44 Amlogic software. This bit should be set to 0 to allow NACK
45 operations to abort I2C bus transactions. If a NACK occurs, the ERROR
46 bit above will be set. */
47 unsigned int status:1; /*[2] the status of the List processor*/
48 #define I2C_IDLE 0
49 #define I2C_RUNNING 1
50 /* 0: IDLE
51 1: Running. The list processor will enter this state on the clock cycle
52 after the START bit is set. The software can poll the status register to
53 determine when processing is complete.
54 */
55 unsigned int error:1; /*[3] */
56 /*This read only bit is set if the I2C device generates a NACK during writing.
57 This bit is cleared at on the clock cycle after the START bit is set to 1
58 indicating the start of list processing. Errors can be ignored by setting
59 the ACK_IGNORE bit below. Errors will be generated on Writes to
60 devices that return NACK instead of ACK. A NACK is returned by a
61 device if it is unable to accept any more data (for example because it
62 is processing some other real-time function). In the event of an
63 ERROR, the I2C module will automatically generate a STOP condition
64 on the bus.*/
65 unsigned int cur_token:4; /*[7:4] the current token being processed*/
66 unsigned int rd_data_cnt:4;/*[11:8] number of bytes READ over the I2C bus*/
67 /*If this value is zero, then no data has been read. If this value is 1, then
68 bits [7:0] in TOKEN_RDATA_REG0 contains valid data. The software can
69 read this register after an I2C transaction to get the number of bytes to
70 read from the I2C device*/
71 unsigned int clk_delay:10; /*[21:12] Quarter clock delay*/
72 /*This value corresponds to period of the SCL clock divided by 4
73 Quarter Clock Delay = * System Clock Frequency
74 For example, if the system clock is 133Mhz, and the I2C clock period
75 is 10uS (100khz), then
76 Quarter Clock Delay = * 133 Mhz = 332
77 */
78 unsigned int manual_en:1; /*[22] enable manual mode. */
79 /*Manual I2C mode is controlled by bits 12,13,14 and 15 above.*/
80 unsigned int wrscl:1; /*[23] Sets the level of the SCL line */
81 /*if manual mode is enabled. If this bit is '0', then the SCL line is
82 pulled low. If this bit is '1' then the SCL line is tri-stated.*/
83 unsigned int wrsda:1; /*[24] Sets the level of the SDA line */
84 /*if manual mode is enabled. If this bit is '0', then the SDA line is
85 pulled low. If this bit is '1' then the SDA line is tri-stated.*/
86 unsigned int rdscl:1; /*[25] Read back level of the SCL line*/
87 unsigned int rdsda:1; /*[26] Read back level of the SDA line*/
88#if 1
89 unsigned int unused:1; /*[27]*/
90 unsigned int clk_delay_ext:2; /*[29:28]*/
91 unsigned int unused2:2; /*[31:30]*/
92#else
93 unsigned int unused:5; /*[31:27]*/
94#endif
95};
96
97struct aml_i2c_reg_slave_addr {
98 unsigned int slave_addr:8; /*[7:0] SLAVE ADDRESS.*/
99 /*This is a 7-bit value for a 7-bit I2C device, or (0xF0 | {A9,A8}) for a
100 10 bit I2C device. By convention, the slave address is typically
101 stored in by first left shifting it so that it's MSB is D7 (The I2C bus
102 assumes the 7-bit address is left shifted one). Additionally, since
103 the SLAVE address is always an 7-bit value, D0 is always 0.
104
105 NOTE: The I2C always transfers 8-bits even for address. The I2C
106 hardware will use D0 to dictate the direction of the bus. Therefore,
107 D0 should always be '0' when this register is set.
108 */
109 unsigned int sda_filter:3; /*[10:8] SDA FILTER*/
110 /*A filter was added in the SCL input path to allow for filtering of slow
111 rise times. 0 = no filtering, 7 = max filtering*/
112 unsigned int scl_filter:3; /*[13:11] SCL FILTER*/
113 /*A filter was added in the SCL input path to allow for filtering of slow
114 rise times. 0 = no filtering, 7 = max filtering*/
115#if 1
116 unsigned int unused:2; /*[15:14]*/
117 unsigned int clk_low_delay:12; /*[27:16]*/
118 unsigned int clk_low_delay_en:1; /*[28]*/
119 unsigned int unused2:3; /*[31:29]*/
120#else
121 unsigned int unused:18; /*[31:14]*/
122#endif
123};
124
125/*Write data associated with the DATA token should be placed into the
126 I2C_TOKEN_WDATA_REG0 or I2C_TOKEN_WDATA_REG1 registers.
127 Read data associated with the DATA or DATA-LAST token can be read from
128 the I2C_TOKEN_RDATA_REG0 or I2C_TOKEN_RDATA_REG1 registers*/
129
130enum aml_i2c_token {
131 TOKEN_END,
132 TOKEN_START,
133 TOKEN_SLAVE_ADDR_WRITE,
134 TOKEN_SLAVE_ADDR_READ,
135 TOKEN_DATA,
136 TOKEN_DATA_LAST,
137 TOKEN_STOP
138};
139
140struct aml_i2c_reg_master {
141 volatile unsigned int i2c_ctrl;
142 volatile unsigned int i2c_slave_addr;
143 volatile unsigned int i2c_token_list_0;
144 volatile unsigned int i2c_token_list_1;
145 volatile unsigned int i2c_token_wdata_0;
146 volatile unsigned int i2c_token_wdata_1;
147 volatile unsigned int i2c_token_rdata_0;
148 volatile unsigned int i2c_token_rdata_1;
149};
150
151
152struct aml_i2c_reg_slave_ctrl {
153 unsigned int samp_rate:7; /*[6:0] sampling rate*/
154 /*Defined as MPEG system clock / (value + 1). The SDA and SCL inputs into
155 the slave module are sampled as a way of filtering the inputs. A
156 rising or falling edge is determined by when 3 successive samples are
157 either high or low respectively*/
158 unsigned int enable:1; /*[7] A '1' enables the I2C slave state machine*/
159 unsigned int hold_time:8; /*[15:8]*/
160 /*Data hold time after the falling edge of SCL.
161 Hold time = (MPEG system clock period) * (value + 1).
162 */
163 unsigned int slave_addr:8; /*[23-16]*/
164 /*Bits [7:1] are used to identify the device.
165 Bit [0] is ignored since this corresponds to the R/W bit.*/
166 unsigned int ack_always:1; /*[24]*/
167 /*Typically the ACK of a slave I2C device is dependent upon the
168 availability of data (if reading) and room to store data (when we are
169 being written). Our I2C module has a status register that can be read
170 continuously. This bit can be set if the I2C master wants to
171 continually read the status register. */
172 unsigned int irq_en:1; /*[25]*/
173 /*If this bit is set, then an interrupt will be sent to the ARC whenever 4
174 bytes have been read or 4 bytes have been written to the I2C slave
175 module.*/
176 unsigned int busy:1; /*[26] */
177 /*Read only status bit. '1' indicates that the I2C slave module is sending
178 or receiving data.*/
179 unsigned int rx_rdy:1; /*[27] */
180 /*This bit is set to '1' by the ARC to indicate to the slave machine that
181 the I2C slave module is ready to receive data. This bit is cleared by
182 the I2C module when it has received 4 bytes from the I2C master.
183 This bit is also available in the status register that can be read by
184 the I2C master. The I2C master can read the status register to see
185 when the I2C slave module is ready to receive data.*/
186 unsigned int tx_rdy:1; /*[28] */
187 /*This bit is set to '1' by the ARC to indicate to the slave machine that
188 the I2C slave module is ready to send data. This bit is cleared by
189 the I2C module when it has sent 4 bytes to the I2C master. This bit
190 is also available in the status register that can be read by the I2C
191 master. The I2C master can read the status register to see when the
192 I2C slave module has data to send.*/
193 unsigned int reg_ptr:3; /*[31:29] */
194 /*There are 5 internal registers inside the I2C slave module. The I2C
195 Master sets this value using the byte that follows the address byte
196 in the I2C data stream. Register 4 (numbered 0,1,бн4) is the
197 status register.*/
198};
199
200struct aml_i2c_reg_slave{
201 unsigned int i2c_slave_ctrl;
202 unsigned int i2c_slave_tx_data;
203 unsigned int i2c_slave_rx_data;
204};
205
206struct aml_i2c {
207 unsigned int i2c_debug;
208 unsigned int cur_slave_addr;
209 unsigned int wait_count;
210 unsigned int wait_ack_interval;
211 unsigned int wait_read_interval;
212 unsigned int wait_xfer_interval;
213 unsigned int master_no;/*master a:0 master b:1*/
214 #define I2C_MASTER_AO 0
215 #define I2C_MASTER_A 1
216 #define I2C_MASTER_B 2
217 #define I2C_MASTER_C 3
218 #define I2C_MASTER_D 4
219 unsigned char token_tag[AML_I2C_MAX_TOKENS];
220 unsigned int msg_flags;
221
222 struct aml_i2c_ops* ops;
223
224 struct aml_i2c_reg_master __iomem* master_regs;
225
226//#ifdef CONFIG_I2C_AML_SLAVE
227 struct aml_i2c_reg_slave __iomem* slave_regs;
228
229 struct aml_pinmux_reg_bit slave_pinmux;
230 unsigned int slave_dev_addr;
231//#endif
232
233 void __iomem *reg_base;
234
235 struct aml_pinmux_reg_bit master_pinmux;
236
237 int irq;
238 unsigned int use_pio;/*0: hardware i2c, 1: pio i2c*/
239 unsigned int master_i2c_speed;
240};
241
242struct aml_i2c_ops {
243 void (*xfer_prepare)(struct aml_i2c *i2c);
244 int (*do_address)(struct aml_i2c *i2c, unsigned int addr);
245 ssize_t (*read)(struct aml_i2c *i2c, unsigned char *buf, size_t len);
246 ssize_t (*write)(struct aml_i2c *i2c, unsigned char *buf, size_t len);
247 void (*stop)(struct aml_i2c *i2c);
248};
249
250int aml_i2c_init(void);
251int aml_i2c_xfer(struct i2c_msg *msgs, int num);
252/*General i2c master transfer,it can Send to a specific master control*/
253int aml_i2c_transfer(int adap_num , struct i2c_msg *msgs , int num);
254
255enum aml_i2c_id{
256 SOFT_I2C = 0,
257 HARD_I2C,
258};
259
260struct i2c_board_info {
261 char type[64];
262 int i2c_id;
263 unsigned short addr;
264 void (*device_init)(void);
265 void (*device_uninit)(void);
266};
267
268#define I2C_BOARD_INFO(dev_type, dev_addr) \
269 .type = dev_type, .addr = (dev_addr)
270
271struct aml_i2c_device {
272 struct i2c_borad_info *aml_i2c_boards;
273 unsigned dev_num;
274};
275
276#ifdef AML_MESON_BOARD_8726M_2010_11_18_V11
277//Please refer board schematic for detail pin connection
278//@AML8726-M_ARM_DEV_BOARD_2DDR_V1R1.pdf
279//port27-> Red (0x7F)
280//port26-> Green (0xBF)
281//port25-> Blue (0xDF)
282#define I2C_LED_RED (0x7F)
283#define I2C_LED_GREEN (0xBF)
284#define I2C_LED_BLUE (0xDF)
285
286//To set onboard LEDs on/off
287void board_i2c_led_set(unsigned char byLED, unsigned char byOn);
288
289#endif //AML_MESON_BOARD_8726M_2010_11_18_V11
290
291#endif //__AML_I2C_H__
292
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