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1/*
2 * include/amlogic/aml_lcd_vout.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the named License,
7 * or any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef INC_AML_LCD_VOUT_H
17#define INC_AML_LCD_VOUT_H
18
19#include <common.h>
20#include <linux/list.h>
21
22/* **********************************
23 * debug print define
24 * ********************************** */
25//#define LCD_DEBUG_INFO
26extern unsigned int lcd_debug_print_flag;
27
28#define LCDPR(fmt, args...) printf("lcd: "fmt"", ## args)
29#define LCDERR(fmt, args...) printf("lcd: error: "fmt"", ## args)
30
31/* **********************************
32 * clk parameter bit define
33 * pll_ctrl, div_ctrl, clk_ctrl
34 * ********************************** */
35/* ******** pll_ctrl ******** */
36#define PLL_CTRL_OD3 20 /* [21:20] */
37#define PLL_CTRL_OD2 18 /* [19:18] */
38#define PLL_CTRL_OD1 16 /* [17:16] */
39#define PLL_CTRL_N 9 /* [13:9] */
40#define PLL_CTRL_M 0 /* [8:0] */
41
42/* ******** div_ctrl ******** */
43#define DIV_CTRL_EDP_DIV1 24 /* [26:24] */
44#define DIV_CTRL_EDP_DIV0 20 /* [23:20] */
45#define DIV_CTRL_DIV_SEL 8 /* [15:8] */
46#define DIV_CTRL_XD 0 /* [7:0] */
47
48/* ******** clk_ctrl ******** */
49#define CLK_CTRL_LEVEL 28 /* [30:28] */
50#define CLK_CTRL_FRAC 0 /* [18:0] */
51
52
53/* **********************************
54 * VENC to TCON sync delay
55 * ********************************** */
56#define TTL_DELAY 13
57
58
59/* ******** MIPI_DSI_PHY ******** */
60/* bit[15:11] */
61#define MIPI_PHY_LANE_BIT 11
62#define MIPI_PHY_LANE_WIDTH 5
63
64/* MIPI-DSI */
65#define DSI_LANE_0 (1 << 4)
66#define DSI_LANE_1 (1 << 3)
67#define DSI_LANE_CLK (1 << 2)
68#define DSI_LANE_2 (1 << 1)
69#define DSI_LANE_3 (1 << 0)
70#define DSI_LANE_COUNT_1 (DSI_LANE_CLK | DSI_LANE_0)
71#define DSI_LANE_COUNT_2 (DSI_LANE_CLK | DSI_LANE_0 | DSI_LANE_1)
72#define DSI_LANE_COUNT_3 (DSI_LANE_CLK | DSI_LANE_0 |\
73 DSI_LANE_1 | DSI_LANE_2)
74#define DSI_LANE_COUNT_4 (DSI_LANE_CLK | DSI_LANE_0 |\
75 DSI_LANE_1 | DSI_LANE_2 | DSI_LANE_3)
76
77#define LCD_PINMUX_END 0xff
78#define LCD_PINMUX_NUM 15
79
80/* **********************************
81 * global control define
82 * ********************************** */
83enum lcd_mode_e {
84 LCD_MODE_TV = 0,
85 LCD_MODE_TABLET,
86 LCD_MODE_MAX,
87};
88
89enum lcd_chip_e {
90 LCD_CHIP_GXTVBB = 0,
91 LCD_CHIP_GXL, /* 1 */
92 LCD_CHIP_GXM, /* 2 */
93 LCD_CHIP_TXL, /* 3 */
94 LCD_CHIP_TXLX, /* 4 */
95 LCD_CHIP_AXG, /* 5 */
96 LCD_CHIP_TXHD, /* 6 */
97 LCD_CHIP_G12A, /* 7 */
98 LCD_CHIP_G12B, /* 8 */
99 LCD_CHIP_TL1, /* 9 */
100 LCD_CHIP_SM1, /* 10 */
101 LCD_CHIP_MAX,
102};
103
104enum lcd_type_e {
105 LCD_TTL = 0,
106 LCD_LVDS,
107 LCD_VBYONE,
108 LCD_MIPI,
109 LCD_MLVDS,
110 LCD_TYPE_MAX,
111};
112
113#define MOD_LEN_MAX 30
114struct lcd_basic_s {
115 char model_name[MOD_LEN_MAX];
116 enum lcd_type_e lcd_type;
117 unsigned char lcd_bits;
118
119 unsigned short h_active; /* Horizontal display area */
120 unsigned short v_active; /* Vertical display area */
121 unsigned short h_period; /* Horizontal total period time */
122 unsigned short v_period; /* Vertical total period time */
123 unsigned short h_period_min;
124 unsigned short h_period_max;
125 unsigned short v_period_min;
126 unsigned short v_period_max;
127 unsigned int lcd_clk_min;
128 unsigned int lcd_clk_max;
129
130 unsigned short screen_width; /* screen physical width in "mm" unit */
131 unsigned short screen_height; /* screen physical height in "mm" unit */
132};
133
134#define LCD_CLK_FRAC_UPDATE (1 << 0)
135#define LCD_CLK_PLL_CHANGE (1 << 1)
136struct lcd_timing_s {
137 unsigned char clk_auto; /* clk parameters auto generation */
138 unsigned char fr_adjust_type; /* 0=clock, 1=htotal, 2=vtotal */
139 unsigned char clk_change; /* internal used */
140 unsigned int lcd_clk; /* pixel clock(unit: Hz) */
141 unsigned int lcd_clk_dft; /* internal used */
142 unsigned int h_period_dft; /* internal used */
143 unsigned int v_period_dft; /* internal used */
144 unsigned int pll_ctrl; /* pll settings */
145 unsigned int div_ctrl; /* divider settings */
146 unsigned int clk_ctrl; /* clock settings */
147
148 unsigned int ss_level;
149
150 unsigned short sync_duration_num;
151 unsigned short sync_duration_den;
152
153 unsigned short video_on_pixel;
154 unsigned short video_on_line;
155
156 unsigned short hsync_width;
157 unsigned short hsync_bp;
158 unsigned short hsync_pol;
159 unsigned short vsync_width;
160 unsigned short vsync_bp;
161 unsigned short vsync_pol;
162 /* unsigned int vsync_h_phase; // [31]sign, [15:0]value */
163 unsigned int h_offset;
164 unsigned int v_offset;
165
166 unsigned short de_hs_addr;
167 unsigned short de_he_addr;
168 unsigned short de_vs_addr;
169 unsigned short de_ve_addr;
170
171 unsigned short hs_hs_addr;
172 unsigned short hs_he_addr;
173 unsigned short hs_vs_addr;
174 unsigned short hs_ve_addr;
175
176 unsigned short vs_hs_addr;
177 unsigned short vs_he_addr;
178 unsigned short vs_vs_addr;
179 unsigned short vs_ve_addr;
180};
181/*
182struct lcd_effect_s {
183 unsigned int rgb_base_addr;
184 unsigned int rgb_coeff_addr;
185 unsigned char dith_user;
186 unsigned int dith_ctrl;
187
188 unsigned char gamma_ctrl;
189 unsigned short gamma_r_coeff;
190 unsigned short gamma_g_coeff;
191 unsigned short gamma_b_coeff;
192 unsigned short GammaTableR[256];
193 unsigned short GammaTableG[256];
194 unsigned short GammaTableB[256];
195};
196*/
197struct ttl_config_s {
198 unsigned int clk_pol;
199 unsigned int sync_valid; /* [1]DE, [0]hvsync */
200 unsigned int swap_ctrl; /* [1]rb swap, [0]bit swap */
201};
202
203#define LVDS_PHY_VSWING_DFT 3
204#define LVDS_PHY_PREEM_DFT 0
205#define LVDS_PHY_CLK_VSWING_DFT 0
206#define LVDS_PHY_CLK_PREEM_DFT 0
207struct lvds_config_s {
208 unsigned int lvds_repack;
209 unsigned int dual_port;
210 unsigned int pn_swap;
211 unsigned int port_swap;
212 unsigned int lane_reverse;
213 unsigned int port_sel;
214 unsigned int phy_vswing;
215 unsigned int phy_preem;
216 unsigned int phy_clk_vswing;
217 unsigned int phy_clk_preem;
218};
219
220#define VX1_PHY_VSWING_DFT 3
221#define VX1_PHY_PREEM_DFT 0
222
223#define VX1_PWR_ON_RESET_DLY_DFT 500 /* 500ms */
224#define VX1_HPD_DATA_DELAY_DFT 10 /* 10ms */
225#define VX1_CDR_TRAINING_HOLD_DFT 200 /* 200ms */
226
227#define VX1_SW_FILTER_TIME_DFT 10 /* 10*100us=1ms */
228#define VX1_SW_FILTER_CNT_DFT 6
229#define VX1_SW_FILTER_RETRY_CNT_DFT 2
230#define VX1_SW_FILTER_RETRY_DLY_DFT 100 /* 100ms */
231#define VX1_SW_CDR_DET_TIME_DFT 20 /* 20us*100=2ms */
232#define VX1_SW_CDR_DET_CNT_DFT 100
233#define VX1_SW_CDR_TIMEOUT_CNT_DFT 100
234
235struct vbyone_config_s {
236 unsigned int lane_count;
237 unsigned int region_num;
238 unsigned int byte_mode;
239 unsigned int color_fmt;
240 unsigned int phy_div;
241 unsigned int bit_rate;
242 unsigned int phy_vswing; /*[5:4]:ext_pullup, [3:0]vswing*/
243 unsigned int phy_preem;
244 unsigned int ctrl_flag;
245 /* bit[0]:power_on_reset_en
246 bit[1]:hpd_data_delay_en
247 bit[2]:cdr_training_hold_en
248 bit[3]:hw_filter_en
249 bit[5:4]:sw_filter */
250
251 /* ctrl timing */
252 unsigned int power_on_reset_delay; /* ms */
253 unsigned int hpd_data_delay; /* ms */
254 unsigned int cdr_training_hold; /* ms */
255 /* hw filter */
256 unsigned int hpd_hw_filter_time; /* ms */
257 unsigned int hpd_hw_filter_cnt;
258 unsigned int lockn_hw_filter_time; /* ms */
259 unsigned int lockn_hw_filter_cnt;
260 /* sw filter */
261 unsigned int vx1_sw_filter_en; /* 0=disable, 1=sw_filter, 2=sw_filter with sw_reset */
262 unsigned int vx1_sw_filter_time; /* 100us base */
263 unsigned int vx1_sw_filter_cnt;
264 unsigned int vx1_sw_filter_retry_cnt;
265 unsigned int vx1_sw_filter_retry_delay; /* ms base */
266 unsigned int vx1_sw_cdr_detect_time; /* us base * 100 times, must cover tcon lockn pulse */
267 unsigned int vx1_sw_cdr_detect_cnt;
268 unsigned int vx1_sw_cdr_timeout_cnt;
269};
270
271/* mipi-dsi config */
272/* Operation mode parameters */
273#define OPERATION_VIDEO_MODE 0
274#define OPERATION_COMMAND_MODE 1
275
276#define SYNC_PULSE 0x0
277#define SYNC_EVENT 0x1
278#define BURST_MODE 0x2
279
280/* command config */
281#define DSI_CMD_SIZE_INDEX 1 /* byte[1] */
282#define DSI_GPIO_INDEX 2 /* byte[2] */
283
284#define DSI_INIT_ON_MAX 100
285#define DSI_INIT_OFF_MAX 30
286
287struct dsi_config_s {
288 unsigned char lane_num;
289 unsigned int bit_rate_max; /* MHz */
290 unsigned int bit_rate_min; /* MHz*/
291 unsigned int bit_rate; /* Hz */
292 unsigned int clk_factor; /* bit_rate/pclk */
293 unsigned int factor_numerator;
294 unsigned int factor_denominator; /* 100 */
295 unsigned char operation_mode_init; /* 0=video mode, 1=command mode */
296 unsigned char operation_mode_display; /* 0=video mode, 1=command mode */
297 unsigned char video_mode_type; /* 0=sync_pulse, 1=sync_event, 2=burst */
298 unsigned char clk_always_hs; /* 0=disable, 1=enable */
299 unsigned char phy_switch; /* 0=auto, 1=standard, 2=slow */
300
301 unsigned int venc_data_width;
302 unsigned int dpi_data_format;
303
304 unsigned char *dsi_init_on;
305 unsigned char *dsi_init_off;
306 unsigned char extern_init;
307
308 unsigned char check_en;
309 unsigned char check_reg;
310 unsigned char check_cnt;
311 unsigned char check_state;
312};
313
314#define LCD_TCON_TABLE_MAX 4096
315struct mlvds_config_s {
316 unsigned int channel_num;
317 unsigned int channel_sel0;
318 unsigned int channel_sel1;
319 unsigned int clk_phase; /* [13:12]=clk01_sel, [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 */
320 unsigned int pn_swap;
321 unsigned int bit_swap; /* MSB/LSB reverse */
322 unsigned int phy_vswing;
323 unsigned int phy_preem;
324
325 /* internal used */
326 unsigned int pi_clk_sel; /* bit[9:0] */
327 unsigned int bit_rate; /* Hz */
328 unsigned char tcon_enable;
329 unsigned short reg_table_len;
330 unsigned char *reg_table;
331 unsigned int fb_addr;
332};
333
334struct lcd_ctrl_config_s {
335 struct ttl_config_s *ttl_config;
336 struct lvds_config_s *lvds_config;
337 struct vbyone_config_s *vbyone_config;
338 struct dsi_config_s *mipi_config;
339 struct mlvds_config_s *mlvds_config;
340};
341
342/* **********************************
343 * power control define
344 * ********************************** */
345enum lcd_power_type_e {
346 LCD_POWER_TYPE_CPU = 0,
347 LCD_POWER_TYPE_PMU,
348 LCD_POWER_TYPE_SIGNAL,
349 LCD_POWER_TYPE_EXTERN,
350 LCD_POWER_TYPE_MAX,
351};
352
353enum lcd_pmu_gpio_e {
354 LCD_PMU_GPIO0 = 0,
355 LCD_PMU_GPIO1,
356 LCD_PMU_GPIO2,
357 LCD_PMU_GPIO3,
358 LCD_PMU_GPIO4,
359 LCD_PMU_GPIO_MAX,
360};
361
362#define LCD_GPIO_MAX 0xff
363#define LCD_GPIO_OUTPUT_LOW 0
364#define LCD_GPIO_OUTPUT_HIGH 1
365#define LCD_GPIO_INPUT 2
366
367/* Power Control */
368#define LCD_CPU_GPIO_NUM_MAX 10
369#define LCD_CPU_GPIO_NAME_MAX 10
370#define LCD_PMU_GPIO_NUM_MAX 3
371
372#define LCD_PWR_STEP_MAX 15
373struct lcd_power_step_s {
374 unsigned char type;
375 int index; /* point to lcd_cpu_gpio_s or lcd_pmu_gpio_s or lcd_extern */
376 unsigned short value;
377 unsigned short delay;
378};
379
380struct lcd_power_ctrl_s {
381 char cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
382 int *pmu_gpio;
383 struct lcd_power_step_s power_on_step[LCD_PWR_STEP_MAX];
384 struct lcd_power_step_s power_off_step[LCD_PWR_STEP_MAX];
385};
386
387#define LCD_PINMX_MAX 20
388#define BL_PINMUX_MAX 20
389#define LCD_PINMUX_NAME_LEN_MAX 30
390struct lcd_pinmux_ctrl_s {
391 char *name;
392 unsigned int pinmux_set[LCD_PINMUX_NUM][2];
393 unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
394};
395
396#define LCD_ENABLE_RETRY_MAX 3
397struct lcd_config_s {
398 unsigned char lcd_mode;
399 unsigned char lcd_key_valid;
400 unsigned char lcd_clk_path; /* 0=hpll, 1=gp0_pll */
401 unsigned char retry_enable_flag;
402 unsigned char retry_enable_cnt;
403 unsigned int backlight_index;
404 struct lcd_basic_s lcd_basic;
405 struct lcd_timing_s lcd_timing;
406 /*struct lcd_effect_s lcd_effect;*/
407 struct lcd_ctrl_config_s lcd_control;
408 struct lcd_power_ctrl_s *lcd_power;
409 unsigned char pinctrl_ver;
410 struct lcd_pinmux_ctrl_s *lcd_pinmux;
411 unsigned int pinmux_set[LCD_PINMUX_NUM][2];
412 unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
413};
414
415extern struct lcd_config_s lcd_config_dft;
416
417/* ==============backlight control config================== */
418enum bl_ctrl_method_e {
419 BL_CTRL_GPIO = 0,
420 BL_CTRL_PWM,
421 BL_CTRL_PWM_COMBO,
422 BL_CTRL_LOCAL_DIMMING,
423 BL_CTRL_EXTERN,
424 BL_CTRL_MAX,
425};
426
427enum bl_pwm_method_e {
428 BL_PWM_NEGATIVE = 0,
429 BL_PWM_POSITIVE,
430 BL_PWM_METHOD_MAX,
431};
432
433enum bl_pwm_port_e {
434 BL_PWM_A = 0,
435 BL_PWM_B,
436 BL_PWM_C,
437 BL_PWM_D,
438 BL_PWM_E,
439 BL_PWM_F,
440 BL_PWM_VS,
441 BL_PWM_MAX,
442};
443
444enum bl_off_policy_e {
445 BL_OFF_POLICY_NONE = 0,
446 BL_OFF_POLICY_ALWAYS,
447 BL_OFF_POLICY_ONCE,
448 BL_OFF_POLICY_MAX,
449};
450
451#define XTAL_FREQ_HZ (24*1000*1000) /* 24M in HZ */
452#define XTAL_HALF_FREQ_HZ (24*1000*500) /* 24M/2 in HZ */
453
454#define BL_FREQ_DEFAULT 1000 /* unit: HZ */
455#define BL_FREQ_VS_DEFAULT 2 /* multiple 2 of vfreq */
456
457#define BL_LEVEL_MAX 255
458#define BL_LEVEL_MIN 10
459#define BL_LEVEL_OFF 1
460
461#define BL_LEVEL_MID 128
462#define BL_LEVEL_MID_MAPPED BL_LEVEL_MID //102
463#define BL_LEVEL_DEFAULT BL_LEVEL_MID
464
465#define BL_GPIO_NUM_MAX 5
466
467struct bl_pwm_config_s {
468 unsigned int index;
469 enum bl_pwm_method_e pwm_method;
470 enum bl_pwm_port_e pwm_port;
471 unsigned int level_max;
472 unsigned int level_min;
473 unsigned int pwm_freq; /* pwm_vs: 1~4(vfreq), pwm: freq(unit: Hz) */
474 unsigned int pwm_duty; /* unit: % */
475 unsigned int pwm_duty_max; /* unit: % */
476 unsigned int pwm_duty_min; /* unit: % */
477 unsigned int pwm_cnt; /* internal used for pwm control */
478 unsigned int pwm_pre_div; /* internal used for pwm control */
479 unsigned int pwm_max; /* internal used for pwm control */
480 unsigned int pwm_min; /* internal used for pwm control */
481 unsigned int pwm_level; /* internal used for pwm control */
482 unsigned int pwm_gpio;
483 unsigned int pwm_gpio_off;
484 unsigned int pinmux_flag;
485 unsigned int pinmux_set[10][2];
486 unsigned int pinmux_clr[10][2];
487};
488
489struct bl_config_s {
490 unsigned char bl_key_valid;
491 char name[20];
492 int level_default;
493 int level_min;
494 int level_max;
495 int level_mid;
496 int level_mid_mapping;
497 int level;
498
499 enum bl_ctrl_method_e method;
500 unsigned int en_gpio;
501 unsigned int en_gpio_on;
502 unsigned int en_gpio_off;
503 unsigned short power_on_delay;
504 unsigned short power_off_delay;
505 unsigned int dim_max;
506 unsigned int dim_min;
507 unsigned int en_sequence_reverse;
508
509 struct bl_pwm_config_s *bl_pwm;
510 struct bl_pwm_config_s *bl_pwm_combo0;
511 struct bl_pwm_config_s *bl_pwm_combo1;
512 unsigned int pwm_on_delay;
513 unsigned int pwm_off_delay;
514
515 char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
516 unsigned char pinctrl_ver;
517 struct lcd_pinmux_ctrl_s *bl_pinmux;
518 unsigned int pinmux_set[10][2];
519 unsigned int pinmux_clr[10][2];
520 int bl_extern_index;
521};
522
523extern struct bl_config_s bl_config_dft;
524
525/* ==============lcd driver================== */
526struct aml_lcd_drv_s {
527 char version[15];
528 enum lcd_chip_e chip_type;
529 unsigned char lcd_status;
530
531 struct lcd_config_s *lcd_config;
532 struct bl_config_s *bl_config;
533
534 int (*outputmode_check)(char *mode);
535 int (*config_check)(char *mode);
536 void (*driver_init_pre)(void);
537 int (*driver_init)(void);
538 void (*driver_disable)(void);
539 void (*list_support_mode)(void);
540 int (*lcd_probe)(void);
541 int (*lcd_outputmode_check)(char *mode);
542 void (*lcd_enable)(char *mode);
543 void (*lcd_disable)(void);
544 void (*lcd_set_ss)(int level);
545 char *(*lcd_get_ss)(void);
546 void (*lcd_test)(int num);
547 void (*lcd_clk)(void);
548 void (*lcd_info)(void);
549 void (*lcd_reg)(void);
550 void (*lcd_tcon_reg)(void);
551 void (*lcd_tcon_table)(void);
552 void (*bl_on)(void);
553 void (*bl_off)(void);
554 void (*set_bl_level)(int level);
555 int (*get_bl_level)(void);
556 void (*bl_config_print)(void);
557 int unifykey_test_flag;
558 void (*unifykey_test)(void);
559 void (*unifykey_tcon_test)(void);
560 void (*unifykey_dump)(void);
561 void (*lcd_extern_info)(void);
562
563 /* for factory test */
564 struct lcd_power_step_s *factory_lcd_power_on_step;
565 int factory_bl_power_on_delay;
566};
567
568extern void lcd_config_bsp_init(void);
569
570extern struct aml_lcd_drv_s *aml_lcd_get_driver(void);
571
572extern int lcd_probe(void);
573
574#endif /* INC_AML_LCD_VOUT_H */
575
generated by cgit at 2024-05-19 16:26:21 (GMT)