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path: root/include/amlogic/hdmi.h (plain)
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1#ifndef __HDMI_H__
2#define __HDMI_H__
3
4/* Little-Endian format */
5enum scdc_addr {
6 SINK_VER = 0x01,
7 SOURCE_VER, /* RW */
8 UPDATE_0 = 0x10, /* RW */
9 UPDATE_1, /* RW */
10 TMDS_CFG = 0x20, /* RW */
11 SCRAMBLER_ST,
12 CONFIG_0 = 0x30, /* RW */
13 STATUS_FLAGS_0 = 0x40,
14 STATUS_FLAGS_1,
15 ERR_DET_0_L = 0x50,
16 ERR_DET_0_H,
17 ERR_DET_1_L,
18 ERR_DET_1_H,
19 ERR_DET_2_L,
20 ERR_DET_2_H,
21 ERR_DET_CHKSUM,
22 TEST_CONFIG_0 = 0xC0, /* RW */
23 MANUFACT_IEEE_OUI_2 = 0xD0,
24 MANUFACT_IEEE_OUI_1,
25 MANUFACT_IEEE_OUI_0,
26 DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */
27 /* RW 0xDE ~ 0xFF */
28 MANUFACT_SPECIFIC = 0xDE,
29};
30
31#define HDMITX_VIC420_OFFSET 0x100
32#define HDMITX_VESA_OFFSET 0x300
33
34/* HDMI VIC definitions */
35enum hdmi_vic {
36 /* Refer to CEA 861-D */
37 HDMI_unkown = 0,
38 HDMI_640x480p60_4x3 = 1,
39 HDMI_720x480p60_4x3 = 2,
40 HDMI_720x480p60_16x9 = 3,
41 HDMI_1280x720p60_16x9 = 4,
42 HDMI_1920x1080i60_16x9 = 5,
43 HDMI_720x480i60_4x3 = 6,
44 HDMI_720x480i60_16x9 = 7,
45 HDMI_720x240p60_4x3 = 8,
46 HDMI_720x240p60_16x9 = 9,
47 HDMI_2880x480i60_4x3 = 10,
48 HDMI_2880x480i60_16x9 = 11,
49 HDMI_2880x240p60_4x3 = 12,
50 HDMI_2880x240p60_16x9 = 13,
51 HDMI_1440x480p60_4x3 = 14,
52 HDMI_1440x480p60_16x9 = 15,
53 HDMI_1920x1080p60_16x9 = 16,
54 HDMI_720x576p50_4x3 = 17,
55 HDMI_720x576p50_16x9 = 18,
56 HDMI_1280x720p50_16x9 = 19,
57 HDMI_1920x1080i50_16x9 = 20,
58 HDMI_720x576i50_4x3 = 21,
59 HDMI_720x576i50_16x9 = 22,
60 HDMI_720x288p_4x3 = 23,
61 HDMI_720x288p_16x9 = 24,
62 HDMI_2880x576i50_4x3 = 25,
63 HDMI_2880x576i50_16x9 = 26,
64 HDMI_2880x288p50_4x3 = 27,
65 HDMI_2880x288p50_16x9 = 28,
66 HDMI_1440x576p_4x3 = 29,
67 HDMI_1440x576p_16x9 = 30,
68 HDMI_1920x1080p50_16x9 = 31,
69 HDMI_1920x1080p24_16x9 = 32,
70 HDMI_1920x1080p25_16x9 = 33,
71 HDMI_1920x1080p30_16x9 = 34,
72 HDMI_2880x480p60_4x3 = 35,
73 HDMI_2880x480p60_16x9 = 36,
74 HDMI_2880x576p50_4x3 = 37,
75 HDMI_2880x576p50_16x9 = 38,
76 HDMI_1920x1080i_t1250_50_16x9 = 39,
77 HDMI_1920x1080i100_16x9 = 40,
78 HDMI_1280x720p100_16x9 = 41,
79 HDMI_720x576p100_4x3 = 42,
80 HDMI_720x576p100_16x9 = 43,
81 HDMI_720x576i100_4x3 = 44,
82 HDMI_720x576i100_16x9 = 45,
83 HDMI_1920x1080i120_16x9 = 46,
84 HDMI_1280x720p120_16x9 = 47,
85 HDMI_720x480p120_4x3 = 48,
86 HDMI_720x480p120_16x9 = 49,
87 HDMI_720x480i120_4x3 = 50,
88 HDMI_720x480i120_16x9 = 51,
89 HDMI_720x576p200_4x3 = 52,
90 HDMI_720x576p200_16x9 = 53,
91 HDMI_720x576i200_4x3 = 54,
92 HDMI_720x576i200_16x9 = 55,
93 HDMI_720x480p240_4x3 = 56,
94 HDMI_720x480p240_16x9 = 57,
95 HDMI_720x480i240_4x3 = 58,
96 HDMI_720x480i240_16x9 = 59,
97 /* Refet to CEA 861-F */
98 HDMI_1280x720p24_16x9 = 60,
99 HDMI_1280x720p25_16x9 = 61,
100 HDMI_1280x720p30_16x9 = 62,
101 HDMI_1920x1080p120_16x9 = 63,
102 HDMI_1920x1080p100_16x9 = 64,
103 HDMI_1280x720p24_64x27 = 65,
104 HDMI_1280x720p25_64x27 = 66,
105 HDMI_1280x720p30_64x27 = 67,
106 HDMI_1280x720p50_64x27 = 68,
107 HDMI_1280x720p60_64x27 = 69,
108 HDMI_1280x720p100_64x27 = 70,
109 HDMI_1280x720p120_64x27 = 71,
110 HDMI_1920x1080p24_64x27 = 72,
111 HDMI_1920x1080p25_64x27 = 73,
112 HDMI_1920x1080p30_64x27 = 74,
113 HDMI_1920x1080p50_64x27 = 75,
114 HDMI_1920x1080p60_64x27 = 76,
115 HDMI_1920x1080p100_64x27 = 77,
116 HDMI_1920x1080p120_64x27 = 78,
117 HDMI_1680x720p24_64x27 = 79,
118 HDMI_1680x720p25_64x27 = 80,
119 HDMI_1680x720p30_64x27 = 81,
120 HDMI_1680x720p50_64x27 = 82,
121 HDMI_1680x720p60_64x27 = 83,
122 HDMI_1680x720p100_64x27 = 84,
123 HDMI_1680x720p120_64x27 = 85,
124 HDMI_2560x1080p24_64x27 = 86,
125 HDMI_2560x1080p25_64x27 = 87,
126 HDMI_2560x1080p30_64x27 = 88,
127 HDMI_2560x1080p50_64x27 = 89,
128 HDMI_2560x1080p60_64x27 = 90,
129 HDMI_2560x1080p100_64x27 = 91,
130 HDMI_2560x1080p120_64x27 = 92,
131 HDMI_3840x2160p24_16x9 = 93,
132 HDMI_3840x2160p25_16x9 = 94,
133 HDMI_3840x2160p30_16x9 = 95,
134 HDMI_3840x2160p50_16x9 = 96,
135 HDMI_3840x2160p60_16x9 = 97,
136 HDMI_4096x2160p24_256x135 = 98,
137 HDMI_4096x2160p25_256x135 = 99,
138 HDMI_4096x2160p30_256x135 = 100,
139 HDMI_4096x2160p50_256x135 = 101,
140 HDMI_4096x2160p60_256x135 = 102,
141 HDMI_3840x2160p24_64x27 = 103,
142 HDMI_3840x2160p25_64x27 = 104,
143 HDMI_3840x2160p30_64x27 = 105,
144 HDMI_3840x2160p50_64x27 = 106,
145 HDMI_3840x2160p60_64x27 = 107,
146 HDMI_RESERVED = 108,
147 /*
148 the following vic is for those y420 mode
149 they are all beyond OFFSET_HDMITX_VIC420(0x1000)
150 and they has same vic with normal vic in the lower bytes.
151 */
152 HDMI_VIC_Y420 = HDMITX_VIC420_OFFSET,
153 HDMI_3840x2160p50_16x9_Y420 =
154 HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9,
155 HDMI_3840x2160p60_16x9_Y420 =
156 HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9,
157 HDMI_4096x2160p50_256x135_Y420 =
158 HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135,
159 HDMI_4096x2160p60_256x135_Y420 =
160 HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135,
161 HDMI_3840x2160p50_64x27_Y420 =
162 HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27,
163 HDMI_3840x2160p60_64x27_Y420 =
164 HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27,
165 HDMIV_640x480p60hz = HDMITX_VESA_OFFSET,
166 HDMIV_800x480p60hz,
167 HDMIV_800x600p60hz,
168 HDMIV_852x480p60hz,
169 HDMIV_854x480p60hz,
170 HDMIV_1024x600p60hz,
171 HDMIV_1024x768p60hz,
172 HDMIV_1152x864p75hz,
173 HDMIV_1280x600p60hz,
174 HDMIV_1280x768p60hz,
175 HDMIV_1280x800p60hz,
176 HDMIV_1280x960p60hz,
177 HDMIV_1280x1024p60hz,
178 HDMIV_1360x768p60hz,
179 HDMIV_1366x768p60hz,
180 HDMIV_1400x1050p60hz,
181 HDMIV_1440x900p60hz,
182 HDMIV_1440x2560p60hz,
183 HDMIV_1440x2560p70hz,
184 HDMIV_1600x900p60hz,
185 HDMIV_1600x1200p60hz,
186 HDMIV_1680x1050p60hz,
187 HDMIV_1920x1200p60hz,
188 HDMIV_2160x1200p90hz,
189 HDMIV_2560x1080p60hz,
190 HDMIV_2560x1440p60hz,
191 HDMIV_2560x1600p60hz,
192 HDMIV_3440x1440p60hz,
193};
194
195/* CEA TIMING STRUCT DEFINITION */
196struct hdmi_cea_timing {
197 unsigned int pixel_freq; /* Unit: 1000 */
198 unsigned int h_freq; /* Unit: Hz */
199 unsigned int v_freq; /* Unit: 0.001 Hz */
200 unsigned int vsync_polarity:1; /* 1: positive 0: negative */
201 unsigned int hsync_polarity:1;
202 unsigned short h_active;
203 unsigned short h_total;
204 unsigned short h_blank;
205 unsigned short h_front;
206 unsigned short h_sync;
207 unsigned short h_back;
208 unsigned short v_active;
209 unsigned short v_total;
210 unsigned short v_blank;
211 unsigned short v_front;
212 unsigned short v_sync;
213 unsigned short v_back;
214 unsigned short v_sync_ln;
215};
216
217/* Refer CEA861-D Page 116 Table 55 */
218struct dtd {
219 unsigned short pixel_clock;
220 unsigned short h_active;
221 unsigned short h_blank;
222 unsigned short v_active;
223 unsigned short v_blank;
224 unsigned short h_sync_offset;
225 unsigned short h_sync;
226 unsigned short v_sync_offset;
227 unsigned short v_sync;
228 unsigned char h_image_size;
229 unsigned char v_image_size;
230 unsigned char h_border;
231 unsigned char v_border;
232 unsigned char flags;
233 enum hdmi_vic vic;
234};
235
236/* Dolby Version support information from EDID*/
237/* Refer to DV Spec version2.9 page26 to page39*/
238enum block_type {
239 ERROR_NULL = 0,
240 ERROR_LENGTH,
241 ERROR_OUI,
242 CORRECT,
243};
244
245
246
247#define DV_IEEE_OUI 0x00D046
248#define HDR10_PLUS_IEEE_OUI 0x90848B
249
250#define HDMI_PACKET_VEND 1
251#define HDMI_PACKET_DRM 0x86
252
253#define CMD_CONF_OFFSET (0x14 << 24)
254#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00)
255 #define CLR_AVI_BT2020 0x0
256 #define SET_AVI_BT2020 0x1
257/* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */
258#define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01)
259#define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02)
260 #define RGB_RANGE_DEFAULT 0
261 #define RGB_RANGE_LIM 1
262 #define RGB_RANGE_FUL 2
263 #define RGB_RANGE_RSVD 3
264#define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03)
265 #define YCC_RANGE_LIM 0
266 #define YCC_RANGE_FUL 1
267 #define YCC_RANGE_RSVD 2
268
269struct hdr_info {
270 unsigned int hdr_sup_eotf_sdr:1;
271 unsigned int hdr_sup_eotf_hdr:1;
272 unsigned int hdr_sup_eotf_smpte_st_2084:1;
273 unsigned int hdr_sup_eotf_hlg:1;
274 unsigned int hdr_sup_SMD_type1:1;
275 unsigned char hdr_lum_max;
276 unsigned char hdr_lum_avg;
277 unsigned char hdr_lum_min;
278 unsigned char rawdata[7];
279};
280
281struct hdr10_plus_info {
282 uint32_t ieeeoui;
283 uint8_t length;
284 uint8_t application_version;
285};
286
287enum hdmi_hdr_transfer {
288 T_UNKNOWN = 0,
289 T_BT709,
290 T_UNDEF,
291 T_BT601,
292 T_BT470M,
293 T_BT470BG,
294 T_SMPTE170M,
295 T_SMPTE240M,
296 T_LINEAR,
297 T_LOG100,
298 T_LOG316,
299 T_IEC61966_2_4,
300 T_BT1361E,
301 T_IEC61966_2_1,
302 T_BT2020_10,
303 T_BT2020_12,
304 T_SMPTE_ST_2084,
305 T_SMPTE_ST_28,
306 T_HLG,
307};
308
309enum hdmi_hdr_color {
310 C_UNKNOWN = 0,
311 C_BT709,
312 C_UNDEF,
313 C_BT601,
314 C_BT470M,
315 C_BT470BG,
316 C_SMPTE170M,
317 C_SMPTE240M,
318 C_FILM,
319 C_BT2020,
320};
321
322/* master_display_info for display device */
323struct master_display_info_s {
324 u32 present_flag;
325 u32 features; /* feature bits bt2020/2084 */
326 u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
327 u32 white_point[2]; /* normalized 50000 */
328 u32 luminance[2]; /* max/min lumin, normalized 10000 */
329 u32 max_content; /* Maximum Content Light Level */
330 u32 max_frame_average; /* Maximum Frame-average Light Level */
331};
332
333struct hdr10plus_para {
334 uint8_t application_version;
335 uint8_t targeted_max_lum;
336 uint8_t average_maxrgb;
337 uint8_t distribution_values[9];
338 uint8_t num_bezier_curve_anchors;
339 uint32_t knee_point_x;
340 uint32_t knee_point_y;
341 uint8_t bezier_curve_anchors[9];
342 uint8_t graphics_overlay_flag;
343 uint8_t no_delay_flag;
344};
345
346struct dv_info {
347 unsigned char rawdata[27];
348 enum block_type block_flag;
349 uint32_t ieeeoui;
350 uint8_t ver; /* 0 or 1 or 2*/
351 uint8_t length;/*ver1: 15 or 12*/
352
353 uint8_t sup_yuv422_12bit:1;
354 /* if as 0, then support RGB tunnel mode */
355 uint8_t sup_2160p60hz:1;
356 /* if as 0, then support 2160p30hz */
357 uint8_t sup_global_dimming:1;
358 uint16_t Rx;
359 uint16_t Ry;
360 uint16_t Gx;
361 uint16_t Gy;
362 uint16_t Bx;
363 uint16_t By;
364 uint16_t Wx;
365 uint16_t Wy;
366 uint16_t tminPQ;
367 uint16_t tmaxPQ;
368 uint8_t dm_major_ver;
369 uint8_t dm_minor_ver;
370 uint8_t dm_version;
371 uint8_t tmaxLUM;
372 uint8_t colorimetry:1;/* ver1*/
373 uint8_t tminLUM;
374 uint8_t low_latency;/* ver1_12 and 2*/
375 uint8_t sup_backlight_control:1;/*only ver2*/
376 uint8_t backlt_min_luma;/*only ver2*/
377 uint8_t Interface;/*only ver2*/
378 uint8_t sup_10b_12b_444;/*only ver2*/
379};
380
381enum eotf_type {
382 EOTF_T_NULL = 0,
383 EOTF_T_DOLBYVISION,
384 EOTF_T_HDR10,
385 EOTF_T_SDR,
386 EOTF_T_LL_MODE,
387 EOTF_T_MAX,
388};
389
390enum mode_type {
391 YUV422_BIT12 = 0,
392 RGB_8BIT,
393 RGB_10_12BIT,
394 YUV444_10_12BIT,
395};
396
397/* Dolby Version VSIF parameter*/
398struct dv_vsif_para {
399 uint8_t ver; /* 0 or 1 or 2*/
400 uint8_t length;/*ver1: 15 or 12*/
401 union {
402 struct {
403 uint8_t low_latency:1;
404 uint8_t dobly_vision_signal:1;
405 uint8_t backlt_ctrl_MD_present:1;
406 uint8_t auxiliary_MD_present:1;
407 uint8_t eff_tmax_PQ_hi;
408 uint8_t eff_tmax_PQ_low;
409 uint8_t auxiliary_runmode;
410 uint8_t auxiliary_runversion;
411 uint8_t auxiliary_debug0;
412 } ver2;
413 } vers;
414};
415
416#define VIC_MAX_NUM 256
417struct rx_cap {
418 unsigned int native_Mode;
419 /*video*/
420 unsigned int VIC[VIC_MAX_NUM];
421 unsigned int VIC_count;
422 unsigned int native_VIC;
423 /*vendor*/
424 unsigned int IEEEOUI;
425 unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
426 unsigned int HF_IEEEOUI; /* For HDMI Forum */
427 unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
428 /* CEA861-F, Table 56, Colorimetry Data Block */
429 unsigned int colorimetry_data;
430 unsigned int scdc_present:1;
431 unsigned int scdc_rr_capable:1; /* SCDC read request */
432 unsigned int lte_340mcsc_scramble:1;
433 unsigned int dc_y444:1;
434 unsigned int dc_30bit:1;
435 unsigned int dc_36bit:1;
436 unsigned int dc_48bit:1;
437 unsigned int dc_30bit_420:1;
438 unsigned int dc_36bit_420:1;
439 unsigned int dc_48bit_420:1;
440 unsigned char edid_version;
441 unsigned char edid_revision;
442 unsigned int ColorDeepSupport;
443 unsigned int Video_Latency;
444 unsigned int Audio_Latency;
445 unsigned int Interlaced_Video_Latency;
446 unsigned int Interlaced_Audio_Latency;
447 unsigned int threeD_present;
448 unsigned int threeD_Multi_present;
449 unsigned int hdmi_vic_LEN;
450 enum hdmi_vic preferred_mode;
451 struct dtd dtd[16];
452 unsigned char dtd_idx;
453 unsigned char flag_vfpdb;
454 unsigned char number_of_dtd;
455 unsigned char pref_colorspace;
456 struct hdr_info hdr_info;
457 struct dv_info dv_info;
458 struct hdr10_plus_info hdr10plus_info;
459 /*blk0 check sum*/
460 unsigned char chksum;
461};
462
463enum hdmi_color_depth {
464 HDMI_COLOR_DEPTH_24B = 4,
465 HDMI_COLOR_DEPTH_30B = 5,
466 HDMI_COLOR_DEPTH_36B = 6,
467 HDMI_COLOR_DEPTH_48B = 7,
468};
469
470enum hdmi_color_format {
471 HDMI_COLOR_FORMAT_RGB,
472 HDMI_COLOR_FORMAT_422,
473 HDMI_COLOR_FORMAT_444,
474 HDMI_COLOR_FORMAT_420,
475};
476
477enum hdmi_color_range {
478 HDMI_COLOR_RANGE_LIM,
479 HDMI_COLOR_RANGE_FUL,
480};
481
482enum hdmi_audio_packet {
483 HDMI_AUDIO_PACKET_SMP = 0x02,
484 HDMI_AUDIO_PACKET_1BT = 0x07,
485 HDMI_AUDIO_PACKET_DST = 0x08,
486 HDMI_AUDIO_PACKET_HBR = 0x09,
487};
488
489/* get hdmi cea timing
490 * t: struct hdmi_cea_timing *
491 */
492#define GET_TIMING(name) (t->name)
493
494struct parse_cd {
495 enum hdmi_color_depth cd;
496 const char *name;
497};
498
499struct parse_cs {
500 enum hdmi_color_format cs;
501 const char *name;
502};
503
504struct parse_cr {
505 enum hdmi_color_format cr;
506 const char *name;
507};
508
509#define EDID_BLK_NO 4
510#define EDID_BLK_SIZE 128
511struct hdmi_format_para {
512 enum hdmi_vic vic;
513 char *name; /* full name, 1280x720p60hz */
514 char *sname; /* short name, 1280x720p60hz -> 720p60hz */
515 char ext_name[32];
516 enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */
517 enum hdmi_color_format cs; /* rgb, y444, y422, y420 */
518 enum hdmi_color_range cr; /* limit, full */
519 unsigned int pixel_repetition_factor;
520 unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */
521 unsigned int scrambler_en:1;
522 unsigned int tmds_clk_div40:1;
523 unsigned int tmds_clk; /* Unit: 1000 */
524 struct hdmi_cea_timing timing;
525};
526
527struct hdmi_support_mode {
528 enum hdmi_vic vic;
529 char *sname;
530 char y420;
531};
532
533struct hdmitx_dev {
534 unsigned char rx_edid[512]; /* some RX may exceeds 256Bytes */
535 struct {
536 int (*get_hpd_state)(void);
537 int (*read_edid)(unsigned char *buf, unsigned char addr,
538 unsigned char blk_no);
539 void (*turn_off)(void);
540 void (*list_support_modes)(void);
541 void (*dump_regs)(void);
542 void (*test_bist)(unsigned int mode);
543 void (*output_blank)(unsigned int blank);
544 } HWOp;
545 unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO];
546 struct rx_cap RXCap;
547 struct hdmi_format_para *para;
548 enum hdmi_vic vic;
549 unsigned int frac_rate_policy;
550 unsigned int mode420;
551 unsigned int dc30;
552 enum eotf_type hdmi_current_eotf_type;
553 enum mode_type hdmi_current_tunnel_mode;
554 /* Add dongle_mode, clock, phy may be different from mbox */
555 unsigned int dongle_mode;
556};
557
558struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic);
559enum hdmi_vic hdmi_get_fmt_vic(char const *name);
560void hdmi_parse_attr(struct hdmi_format_para *para, char const *name);
561void hdmi_tx_set(struct hdmitx_dev *hdev);
562int hdmi_outputmode_check(char *mode);
563/* Parsing RAW EDID data from edid to pRXCap */
564unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *pRXCap);
565struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t);
566
567extern void hdmitx_set_drm_pkt(struct master_display_info_s *data);
568#ifndef CONFIG_AML_HDMITX20
569void __attribute__((weak))hdmitx_set_drm_pkt(struct master_display_info_s *data)
570{
571}
572#endif
573
574void hdmitx_set_vsif_pkt(enum eotf_type type, enum mode_type tunnel_mode,
575 struct dv_vsif_para *data);
576void hdmitx_set_hdr10plus_pkt(unsigned int flag,
577 struct hdr10plus_para *data);
578
579/*
580 * Must be called at uboot
581 */
582void hdmi_tx_init(void);
583
584extern struct hdmitx_dev hdmitx_device;
585
586#ifndef printk
587#define printk printf
588#endif
589#ifndef pr_info
590#define pr_info printf
591#endif
592
593#define hdmitx_debug() /* printf("hd: %s[%d]\n", __func__, __LINE__) */
594
595extern struct hdr_info *hdmitx_get_rx_hdr_info(void);
596#ifndef CONFIG_AML_HDMITX20
597struct hdr_info * __attribute__((weak))hdmitx_get_rx_hdr_info(void)
598{
599 return NULL;
600}
601#endif
602
603#endif
604
generated by cgit at 2024-05-19 14:55:11 (GMT)