blob: 282af845c5f3bbef42c78ae524bb6ebe052211a1
| 1 | /* |
| 2 | * Amlogic Meson SPI communication controller(SPICC) |
| 3 | * |
| 4 | * Copyright (C) 2017 Amlogic Corporation |
| 5 | * |
| 6 | * Licensed under the GPL-2 or later. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #ifndef __SPICC_H__ |
| 11 | #define __SPICC_H__ |
| 12 | |
| 13 | #define SPICC_DEFAULT_CLK_RATE 166666666 |
| 14 | #define CS_GPIO_MAX 2 |
| 15 | |
| 16 | /* |
| 17 | * @compatible: |
| 18 | * @reg: controller registers address. |
| 19 | * @mem_map: memory_mapped for read operations. |
| 20 | * @clk_rate: |
| 21 | * @clk_set_rate: |
| 22 | * @pinctrl_enable: |
| 23 | * @num_chipselect: |
| 24 | * @cs_gpios: |
| 25 | */ |
| 26 | struct spicc_platdata { |
| 27 | #ifndef CONFIG_OF_CONTROL |
| 28 | char *compatible; |
| 29 | int clk_rate; |
| 30 | int (*clk_set_rate)(int rate); |
| 31 | int (*clk_enable)(bool enable); |
| 32 | int (*pinctrl_enable)(bool enable); |
| 33 | #endif |
| 34 | void __iomem *reg; |
| 35 | const char *cs_gpio_names[CS_GPIO_MAX]; |
| 36 | unsigned int clk_cs_delay; |
| 37 | unsigned int mo_delay; |
| 38 | unsigned int mi_delay; |
| 39 | unsigned int mi_capture_delay; |
| 40 | unsigned int tt_delay; |
| 41 | unsigned int ti_delay; |
| 42 | }; |
| 43 | |
| 44 | #endif /* __SPICC_H__ */ |