blob: 7bfb8021f2eca7f042a4a57f3808452877f42b8d
| 1 | /* |
| 2 | * Amlogic SPI flash controller(SPIFC) |
| 3 | * |
| 4 | * Copyright (C) 2017 Amlogic Corporation |
| 5 | * |
| 6 | * Licensed under the GPL-2 or later. |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | #ifndef __SPIFC_H__ |
| 11 | #define __SPIFC_H__ |
| 12 | |
| 13 | #define SPIFC_DEFAULT_CLK_RATE 166666666 |
| 14 | /* |
| 15 | * @reg: controller registers address. |
| 16 | * @mem_map: memory_mapped for read operations. |
| 17 | * @clk_get(): callback to get spifc clk pointer. |
| 18 | * ret: should be "struct clk *" |
| 19 | * dev: should be "struct udevice *" |
| 20 | * @clk_get_rate(): |
| 21 | * @clk_enable(): |
| 22 | * @pinctrl_get(): callback to get spifc pinctrl pointer. |
| 23 | * ret: should be "struct pinctrl *" |
| 24 | * dev: should be "struct udevice *" |
| 25 | * @num_chipselect: |
| 26 | * @cs_gpios: |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * spifc driver will use the default clk81 rate 1666666666 |
| 31 | * if without following platform callbacks. |
| 32 | static void* spifc_clk_get(void *dev, char *name) |
| 33 | { return NULL; } |
| 34 | static int spifc_clk_get_rate(void *clk) |
| 35 | { return 1666666666; } |
| 36 | static int spifc_clk_enable(void *clk, bool enable) |
| 37 | { return 0; } |
| 38 | static void* spifc_pinctrl_get(void *dev, char *name) |
| 39 | { return NULL; } |
| 40 | */ |
| 41 | |
| 42 | struct spifc_platdata { |
| 43 | ulong reg; |
| 44 | ulong mem_map; |
| 45 | void *(*clk_get)(void *dev, char *name); |
| 46 | int (*clk_get_rate)(void *clk); |
| 47 | int (*clk_enable)(void *clk, bool enable); |
| 48 | void *(*pinctrl_get)(void *dev, char *name); |
| 49 | int (*pinctrl_enable)(void *pinctrl, bool enable); |
| 50 | int num_chipselect; |
| 51 | int *cs_gpios; |
| 52 | }; |
| 53 | |
| 54 | #endif /* __SPIFC_H__ */ |