blob: 9582746153a78a19aeab7cd39b636452518568dd
1 | /* |
2 | * MPC8xx Communication Processor Module. |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
4 | * |
5 | * (C) Copyright 2000-2006 |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * |
8 | * This file contains structures and information for the communication |
9 | * processor channels. Some CPM control and status is available |
10 | * throught the MPC8xx internal memory map. See immap.h for details. |
11 | * This file only contains what I need for the moment, not the total |
12 | * CPM capabilities. I (or someone else) will add definitions as they |
13 | * are needed. -- Dan |
14 | * |
15 | */ |
16 | #ifndef __CPM_8XX__ |
17 | #define __CPM_8XX__ |
18 | |
19 | #include <asm/8xx_immap.h> |
20 | |
21 | /* CPM Command register. |
22 | */ |
23 | #define CPM_CR_RST ((ushort)0x8000) |
24 | #define CPM_CR_OPCODE ((ushort)0x0f00) |
25 | #define CPM_CR_CHAN ((ushort)0x00f0) |
26 | #define CPM_CR_FLG ((ushort)0x0001) |
27 | |
28 | /* Some commands (there are more...later) |
29 | */ |
30 | #define CPM_CR_INIT_TRX ((ushort)0x0000) |
31 | #define CPM_CR_INIT_RX ((ushort)0x0001) |
32 | #define CPM_CR_INIT_TX ((ushort)0x0002) |
33 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) |
34 | #define CPM_CR_STOP_TX ((ushort)0x0004) |
35 | #define CPM_CR_RESTART_TX ((ushort)0x0006) |
36 | #define CPM_CR_SET_GADDR ((ushort)0x0008) |
37 | |
38 | /* Channel numbers. |
39 | */ |
40 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) |
41 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ |
42 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) |
43 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ |
44 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) |
45 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ |
46 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) |
47 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ |
48 | |
49 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) |
50 | |
51 | /* |
52 | * DPRAM defines and allocation functions |
53 | */ |
54 | |
55 | /* The dual ported RAM is multi-functional. Some areas can be (and are |
56 | * being) used for microcode. There is an area that can only be used |
57 | * as data ram for buffer descriptors, which is all we use right now. |
58 | * Currently the first 512 and last 256 bytes are used for microcode. |
59 | */ |
60 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
61 | |
62 | #define CPM_DATAONLY_BASE ((uint)0x0800) |
63 | #define CPM_DATAONLY_SIZE ((uint)0x0700) |
64 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) |
65 | |
66 | #else |
67 | |
68 | #define CPM_SERIAL_BASE 0x0800 |
69 | #define CPM_I2C_BASE 0x0820 |
70 | #define CPM_SPI_BASE 0x0840 |
71 | #define CPM_FEC_BASE 0x0860 |
72 | #define CPM_SERIAL2_BASE 0x08E0 |
73 | #define CPM_SCC_BASE 0x0900 |
74 | #define CPM_POST_BASE 0x0980 |
75 | #define CPM_WLKBD_BASE 0x0a00 |
76 | |
77 | #endif |
78 | |
79 | #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR |
80 | #define CPM_POST_WORD_ADDR 0x07FC |
81 | #else |
82 | #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR |
83 | #endif |
84 | |
85 | #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR |
86 | #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) |
87 | #else |
88 | #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR |
89 | #endif |
90 | |
91 | #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ |
92 | |
93 | /* Export the base address of the communication processor registers |
94 | * and dual port ram. |
95 | */ |
96 | extern cpm8xx_t *cpmp; /* Pointer to comm processor */ |
97 | |
98 | /* Buffer descriptors used by many of the CPM protocols. |
99 | */ |
100 | typedef struct cpm_buf_desc { |
101 | ushort cbd_sc; /* Status and Control */ |
102 | ushort cbd_datlen; /* Data length in buffer */ |
103 | uint cbd_bufaddr; /* Buffer address in host memory */ |
104 | } cbd_t; |
105 | |
106 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ |
107 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ |
108 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ |
109 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ |
110 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ |
111 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ |
112 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ |
113 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ |
114 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ |
115 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ |
116 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ |
117 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ |
118 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ |
119 | #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ |
120 | |
121 | /* Parameter RAM offsets. |
122 | */ |
123 | #define PROFF_SCC1 ((uint)0x0000) |
124 | #define PROFF_IIC ((uint)0x0080) |
125 | #define PROFF_REVNUM ((uint)0x00b0) |
126 | #define PROFF_SCC2 ((uint)0x0100) |
127 | #define PROFF_SPI ((uint)0x0180) |
128 | #define PROFF_SCC3 ((uint)0x0200) |
129 | #define PROFF_SMC1 ((uint)0x0280) |
130 | #define PROFF_SCC4 ((uint)0x0300) |
131 | #define PROFF_SMC2 ((uint)0x0380) |
132 | |
133 | /* Define enough so I can at least use the serial port as a UART. |
134 | */ |
135 | typedef struct smc_uart { |
136 | ushort smc_rbase; /* Rx Buffer descriptor base address */ |
137 | ushort smc_tbase; /* Tx Buffer descriptor base address */ |
138 | u_char smc_rfcr; /* Rx function code */ |
139 | u_char smc_tfcr; /* Tx function code */ |
140 | ushort smc_mrblr; /* Max receive buffer length */ |
141 | uint smc_rstate; /* Internal */ |
142 | uint smc_idp; /* Internal */ |
143 | ushort smc_rbptr; /* Internal */ |
144 | ushort smc_ibc; /* Internal */ |
145 | uint smc_rxtmp; /* Internal */ |
146 | uint smc_tstate; /* Internal */ |
147 | uint smc_tdp; /* Internal */ |
148 | ushort smc_tbptr; /* Internal */ |
149 | ushort smc_tbc; /* Internal */ |
150 | uint smc_txtmp; /* Internal */ |
151 | ushort smc_maxidl; /* Maximum idle characters */ |
152 | ushort smc_tmpidl; /* Temporary idle counter */ |
153 | ushort smc_brklen; /* Last received break length */ |
154 | ushort smc_brkec; /* rcv'd break condition counter */ |
155 | ushort smc_brkcr; /* xmt break count register */ |
156 | ushort smc_rmask; /* Temporary bit mask */ |
157 | u_char res1[8]; |
158 | ushort smc_rpbase; /* Relocation pointer */ |
159 | } smc_uart_t; |
160 | |
161 | /* Function code bits. |
162 | */ |
163 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ |
164 | |
165 | /* SMC uart mode register. |
166 | */ |
167 | #define SMCMR_REN ((ushort)0x0001) |
168 | #define SMCMR_TEN ((ushort)0x0002) |
169 | #define SMCMR_DM ((ushort)0x000c) |
170 | #define SMCMR_SM_GCI ((ushort)0x0000) |
171 | #define SMCMR_SM_UART ((ushort)0x0020) |
172 | #define SMCMR_SM_TRANS ((ushort)0x0030) |
173 | #define SMCMR_SM_MASK ((ushort)0x0030) |
174 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ |
175 | #define SMCMR_REVD SMCMR_PM_EVEN |
176 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ |
177 | #define SMCMR_BS SMCMR_PEN |
178 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ |
179 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ |
180 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) |
181 | |
182 | /* SMC2 as Centronics parallel printer. It is half duplex, in that |
183 | * it can only receive or transmit. The parameter ram values for |
184 | * each direction are either unique or properly overlap, so we can |
185 | * include them in one structure. |
186 | */ |
187 | typedef struct smc_centronics { |
188 | ushort scent_rbase; |
189 | ushort scent_tbase; |
190 | u_char scent_cfcr; |
191 | u_char scent_smask; |
192 | ushort scent_mrblr; |
193 | uint scent_rstate; |
194 | uint scent_r_ptr; |
195 | ushort scent_rbptr; |
196 | ushort scent_r_cnt; |
197 | uint scent_rtemp; |
198 | uint scent_tstate; |
199 | uint scent_t_ptr; |
200 | ushort scent_tbptr; |
201 | ushort scent_t_cnt; |
202 | uint scent_ttemp; |
203 | ushort scent_max_sl; |
204 | ushort scent_sl_cnt; |
205 | ushort scent_character1; |
206 | ushort scent_character2; |
207 | ushort scent_character3; |
208 | ushort scent_character4; |
209 | ushort scent_character5; |
210 | ushort scent_character6; |
211 | ushort scent_character7; |
212 | ushort scent_character8; |
213 | ushort scent_rccm; |
214 | ushort scent_rccr; |
215 | } smc_cent_t; |
216 | |
217 | /* Centronics Status Mask Register. |
218 | */ |
219 | #define SMC_CENT_F ((u_char)0x08) |
220 | #define SMC_CENT_PE ((u_char)0x04) |
221 | #define SMC_CENT_S ((u_char)0x02) |
222 | |
223 | /* SMC Event and Mask register. |
224 | */ |
225 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ |
226 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ |
227 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ |
228 | #define SMCM_BSY ((unsigned char)0x04) |
229 | #define SMCM_TX ((unsigned char)0x02) |
230 | #define SMCM_RX ((unsigned char)0x01) |
231 | |
232 | /* Baud rate generators. |
233 | */ |
234 | #define CPM_BRG_RST ((uint)0x00020000) |
235 | #define CPM_BRG_EN ((uint)0x00010000) |
236 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) |
237 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) |
238 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) |
239 | #define CPM_BRG_ATB ((uint)0x00002000) |
240 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) |
241 | #define CPM_BRG_DIV16 ((uint)0x00000001) |
242 | |
243 | /* SI Clock Route Register |
244 | */ |
245 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) |
246 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) |
247 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) |
248 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) |
249 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) |
250 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) |
251 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) |
252 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) |
253 | |
254 | /* SCCs. |
255 | */ |
256 | #define SCC_GSMRH_IRP ((uint)0x00040000) |
257 | #define SCC_GSMRH_GDE ((uint)0x00010000) |
258 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) |
259 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) |
260 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) |
261 | #define SCC_GSMRH_REVD ((uint)0x00002000) |
262 | #define SCC_GSMRH_TRX ((uint)0x00001000) |
263 | #define SCC_GSMRH_TTX ((uint)0x00000800) |
264 | #define SCC_GSMRH_CDP ((uint)0x00000400) |
265 | #define SCC_GSMRH_CTSP ((uint)0x00000200) |
266 | #define SCC_GSMRH_CDS ((uint)0x00000100) |
267 | #define SCC_GSMRH_CTSS ((uint)0x00000080) |
268 | #define SCC_GSMRH_TFL ((uint)0x00000040) |
269 | #define SCC_GSMRH_RFW ((uint)0x00000020) |
270 | #define SCC_GSMRH_TXSY ((uint)0x00000010) |
271 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) |
272 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) |
273 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) |
274 | #define SCC_GSMRH_RTSM ((uint)0x00000002) |
275 | #define SCC_GSMRH_RSYN ((uint)0x00000001) |
276 | |
277 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ |
278 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) |
279 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) |
280 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) |
281 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) |
282 | #define SCC_GSMRL_TCI ((uint)0x10000000) |
283 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) |
284 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) |
285 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) |
286 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) |
287 | #define SCC_GSMRL_RINV ((uint)0x02000000) |
288 | #define SCC_GSMRL_TINV ((uint)0x01000000) |
289 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) |
290 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) |
291 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) |
292 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) |
293 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) |
294 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) |
295 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) |
296 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) |
297 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) |
298 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) |
299 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) |
300 | #define SCC_GSMRL_TEND ((uint)0x00040000) |
301 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) |
302 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) |
303 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) |
304 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) |
305 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) |
306 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) |
307 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) |
308 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) |
309 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) |
310 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) |
311 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) |
312 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) |
313 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) |
314 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) |
315 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) |
316 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) |
317 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) |
318 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) |
319 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ |
320 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) |
321 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) |
322 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) |
323 | #define SCC_GSMRL_ENR ((uint)0x00000020) |
324 | #define SCC_GSMRL_ENT ((uint)0x00000010) |
325 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) |
326 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) |
327 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) |
328 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) |
329 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) |
330 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) |
331 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) |
332 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) |
333 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) |
334 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) |
335 | |
336 | #define SCC_TODR_TOD ((ushort)0x8000) |
337 | |
338 | /* SCC Event and Mask register. |
339 | */ |
340 | #define SCCM_TXE ((unsigned char)0x10) |
341 | #define SCCM_BSY ((unsigned char)0x04) |
342 | #define SCCM_TX ((unsigned char)0x02) |
343 | #define SCCM_RX ((unsigned char)0x01) |
344 | |
345 | typedef struct scc_param { |
346 | ushort scc_rbase; /* Rx Buffer descriptor base address */ |
347 | ushort scc_tbase; /* Tx Buffer descriptor base address */ |
348 | u_char scc_rfcr; /* Rx function code */ |
349 | u_char scc_tfcr; /* Tx function code */ |
350 | ushort scc_mrblr; /* Max receive buffer length */ |
351 | uint scc_rstate; /* Internal */ |
352 | uint scc_idp; /* Internal */ |
353 | ushort scc_rbptr; /* Internal */ |
354 | ushort scc_ibc; /* Internal */ |
355 | uint scc_rxtmp; /* Internal */ |
356 | uint scc_tstate; /* Internal */ |
357 | uint scc_tdp; /* Internal */ |
358 | ushort scc_tbptr; /* Internal */ |
359 | ushort scc_tbc; /* Internal */ |
360 | uint scc_txtmp; /* Internal */ |
361 | uint scc_rcrc; /* Internal */ |
362 | uint scc_tcrc; /* Internal */ |
363 | } sccp_t; |
364 | |
365 | /* Function code bits. |
366 | */ |
367 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ |
368 | |
369 | /* CPM Ethernet through SCCx. |
370 | */ |
371 | typedef struct scc_enet { |
372 | sccp_t sen_genscc; |
373 | uint sen_cpres; /* Preset CRC */ |
374 | uint sen_cmask; /* Constant mask for CRC */ |
375 | uint sen_crcec; /* CRC Error counter */ |
376 | uint sen_alec; /* alignment error counter */ |
377 | uint sen_disfc; /* discard frame counter */ |
378 | ushort sen_pads; /* Tx short frame pad character */ |
379 | ushort sen_retlim; /* Retry limit threshold */ |
380 | ushort sen_retcnt; /* Retry limit counter */ |
381 | ushort sen_maxflr; /* maximum frame length register */ |
382 | ushort sen_minflr; /* minimum frame length register */ |
383 | ushort sen_maxd1; /* maximum DMA1 length */ |
384 | ushort sen_maxd2; /* maximum DMA2 length */ |
385 | ushort sen_maxd; /* Rx max DMA */ |
386 | ushort sen_dmacnt; /* Rx DMA counter */ |
387 | ushort sen_maxb; /* Max BD byte count */ |
388 | ushort sen_gaddr1; /* Group address filter */ |
389 | ushort sen_gaddr2; |
390 | ushort sen_gaddr3; |
391 | ushort sen_gaddr4; |
392 | uint sen_tbuf0data0; /* Save area 0 - current frame */ |
393 | uint sen_tbuf0data1; /* Save area 1 - current frame */ |
394 | uint sen_tbuf0rba; /* Internal */ |
395 | uint sen_tbuf0crc; /* Internal */ |
396 | ushort sen_tbuf0bcnt; /* Internal */ |
397 | ushort sen_paddrh; /* physical address (MSB) */ |
398 | ushort sen_paddrm; |
399 | ushort sen_paddrl; /* physical address (LSB) */ |
400 | ushort sen_pper; /* persistence */ |
401 | ushort sen_rfbdptr; /* Rx first BD pointer */ |
402 | ushort sen_tfbdptr; /* Tx first BD pointer */ |
403 | ushort sen_tlbdptr; /* Tx last BD pointer */ |
404 | uint sen_tbuf1data0; /* Save area 0 - current frame */ |
405 | uint sen_tbuf1data1; /* Save area 1 - current frame */ |
406 | uint sen_tbuf1rba; /* Internal */ |
407 | uint sen_tbuf1crc; /* Internal */ |
408 | ushort sen_tbuf1bcnt; /* Internal */ |
409 | ushort sen_txlen; /* Tx Frame length counter */ |
410 | ushort sen_iaddr1; /* Individual address filter */ |
411 | ushort sen_iaddr2; |
412 | ushort sen_iaddr3; |
413 | ushort sen_iaddr4; |
414 | ushort sen_boffcnt; /* Backoff counter */ |
415 | |
416 | /* NOTE: Some versions of the manual have the following items |
417 | * incorrectly documented. Below is the proper order. |
418 | */ |
419 | ushort sen_taddrh; /* temp address (MSB) */ |
420 | ushort sen_taddrm; |
421 | ushort sen_taddrl; /* temp address (LSB) */ |
422 | } scc_enet_t; |
423 | |
424 | /********************************************************************** |
425 | * |
426 | * Board specific configuration settings. |
427 | * |
428 | * Please note that we use the presence of a #define SCC_ENET and/or |
429 | * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. |
430 | **********************************************************************/ |
431 | |
432 | /*** BSEIP **********************************************************/ |
433 | |
434 | #ifdef CONFIG_BSEIP |
435 | /* This ENET stuff is for the MPC823 with ethernet on SCC2. |
436 | * This is unique to the BSE ip-Engine board. |
437 | */ |
438 | #define PROFF_ENET PROFF_SCC2 |
439 | #define CPM_CR_ENET CPM_CR_CH_SCC2 |
440 | #define SCC_ENET 1 |
441 | #define PA_ENET_RXD ((ushort)0x0004) |
442 | #define PA_ENET_TXD ((ushort)0x0008) |
443 | #define PA_ENET_TCLK ((ushort)0x0100) |
444 | #define PA_ENET_RCLK ((ushort)0x0200) |
445 | #define PB_ENET_TENA ((uint)0x00002000) |
446 | #define PC_ENET_CLSN ((ushort)0x0040) |
447 | #define PC_ENET_RENA ((ushort)0x0080) |
448 | |
449 | /* BSE uses port B and C bits for PHY control also. |
450 | */ |
451 | #define PB_BSE_POWERUP ((uint)0x00000004) |
452 | #define PB_BSE_FDXDIS ((uint)0x00008000) |
453 | #define PC_BSE_LOOPBACK ((ushort)0x0800) |
454 | |
455 | #define SICR_ENET_MASK ((uint)0x0000ff00) |
456 | #define SICR_ENET_CLKRT ((uint)0x00002c00) |
457 | #endif /* CONFIG_BSEIP */ |
458 | |
459 | /*** KM8XX *********************************************************/ |
460 | |
461 | /* The KM8XX Service Module uses SCC3 for Ethernet */ |
462 | |
463 | #ifdef CONFIG_KM8XX |
464 | #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ |
465 | #define CPM_CR_ENET CPM_CR_CH_SCC3 |
466 | #define SCC_ENET 2 |
467 | #define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ |
468 | #define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ |
469 | #define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ |
470 | #define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ |
471 | |
472 | #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ |
473 | |
474 | #define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ |
475 | #define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ |
476 | |
477 | /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to |
478 | * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. |
479 | */ |
480 | #define SICR_ENET_MASK ((uint)0x00FF0000) |
481 | #define SICR_ENET_CLKRT ((uint)0x00250000) |
482 | #endif /* CONFIG_KM8XX */ |
483 | |
484 | /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ |
485 | |
486 | #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ |
487 | defined(CONFIG_TQM823L) || \ |
488 | defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ |
489 | defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) |
490 | |
491 | /* Bits in parallel I/O port registers that have to be set/cleared |
492 | * to configure the pins for SCC2 use. |
493 | */ |
494 | #define PROFF_ENET PROFF_SCC2 |
495 | #define CPM_CR_ENET CPM_CR_CH_SCC2 |
496 | #define SCC_ENET 1 |
497 | #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ |
498 | #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ |
499 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ |
500 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ |
501 | |
502 | #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ |
503 | |
504 | #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ |
505 | #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ |
506 | |
507 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to |
508 | * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. |
509 | */ |
510 | #define SICR_ENET_MASK ((uint)0x0000ff00) |
511 | #define SICR_ENET_CLKRT ((uint)0x00002600) |
512 | |
513 | # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ |
514 | #define FEC_ENET |
515 | # endif /* CONFIG_FEC_ENET */ |
516 | |
517 | #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ |
518 | |
519 | /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ |
520 | |
521 | #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ |
522 | defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ |
523 | defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ |
524 | defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) |
525 | |
526 | # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ |
527 | |
528 | /* Bits in parallel I/O port registers that have to be set/cleared |
529 | * to configure the pins for SCC1 use. |
530 | */ |
531 | #define PROFF_ENET PROFF_SCC1 |
532 | #define CPM_CR_ENET CPM_CR_CH_SCC1 |
533 | #define SCC_ENET 0 |
534 | #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ |
535 | #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ |
536 | #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ |
537 | #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ |
538 | |
539 | #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ |
540 | #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ |
541 | #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ |
542 | |
543 | /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to |
544 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. |
545 | */ |
546 | #define SICR_ENET_MASK ((uint)0x000000ff) |
547 | #define SICR_ENET_CLKRT ((uint)0x00000026) |
548 | |
549 | # endif /* CONFIG_SCC1_ENET */ |
550 | |
551 | # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ |
552 | |
553 | #define FEC_ENET |
554 | |
555 | #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ |
556 | #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ |
557 | #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ |
558 | #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ |
559 | #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ |
560 | #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ |
561 | #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ |
562 | #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ |
563 | #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ |
564 | #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ |
565 | #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ |
566 | #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ |
567 | #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ |
568 | |
569 | #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ |
570 | |
571 | # endif /* CONFIG_FEC_ENET */ |
572 | #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ |
573 | |
574 | /*********************************************************************/ |
575 | |
576 | /* SCC Event register as used by Ethernet. |
577 | */ |
578 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ |
579 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ |
580 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ |
581 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ |
582 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ |
583 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ |
584 | |
585 | /* SCC Mode Register (PSMR) as used by Ethernet. |
586 | */ |
587 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ |
588 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ |
589 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ |
590 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ |
591 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ |
592 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ |
593 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ |
594 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ |
595 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ |
596 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ |
597 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ |
598 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ |
599 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ |
600 | |
601 | /* Buffer descriptor control/status used by Ethernet receive. |
602 | */ |
603 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) |
604 | #define BD_ENET_RX_WRAP ((ushort)0x2000) |
605 | #define BD_ENET_RX_INTR ((ushort)0x1000) |
606 | #define BD_ENET_RX_LAST ((ushort)0x0800) |
607 | #define BD_ENET_RX_FIRST ((ushort)0x0400) |
608 | #define BD_ENET_RX_MISS ((ushort)0x0100) |
609 | #define BD_ENET_RX_LG ((ushort)0x0020) |
610 | #define BD_ENET_RX_NO ((ushort)0x0010) |
611 | #define BD_ENET_RX_SH ((ushort)0x0008) |
612 | #define BD_ENET_RX_CR ((ushort)0x0004) |
613 | #define BD_ENET_RX_OV ((ushort)0x0002) |
614 | #define BD_ENET_RX_CL ((ushort)0x0001) |
615 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ |
616 | |
617 | /* Buffer descriptor control/status used by Ethernet transmit. |
618 | */ |
619 | #define BD_ENET_TX_READY ((ushort)0x8000) |
620 | #define BD_ENET_TX_PAD ((ushort)0x4000) |
621 | #define BD_ENET_TX_WRAP ((ushort)0x2000) |
622 | #define BD_ENET_TX_INTR ((ushort)0x1000) |
623 | #define BD_ENET_TX_LAST ((ushort)0x0800) |
624 | #define BD_ENET_TX_TC ((ushort)0x0400) |
625 | #define BD_ENET_TX_DEF ((ushort)0x0200) |
626 | #define BD_ENET_TX_HB ((ushort)0x0100) |
627 | #define BD_ENET_TX_LC ((ushort)0x0080) |
628 | #define BD_ENET_TX_RL ((ushort)0x0040) |
629 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) |
630 | #define BD_ENET_TX_UN ((ushort)0x0002) |
631 | #define BD_ENET_TX_CSL ((ushort)0x0001) |
632 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ |
633 | |
634 | /* SCC as UART |
635 | */ |
636 | typedef struct scc_uart { |
637 | sccp_t scc_genscc; |
638 | uint scc_res1; /* Reserved */ |
639 | uint scc_res2; /* Reserved */ |
640 | ushort scc_maxidl; /* Maximum idle chars */ |
641 | ushort scc_idlc; /* temp idle counter */ |
642 | ushort scc_brkcr; /* Break count register */ |
643 | ushort scc_parec; /* receive parity error counter */ |
644 | ushort scc_frmec; /* receive framing error counter */ |
645 | ushort scc_nosec; /* receive noise counter */ |
646 | ushort scc_brkec; /* receive break condition counter */ |
647 | ushort scc_brkln; /* last received break length */ |
648 | ushort scc_uaddr1; /* UART address character 1 */ |
649 | ushort scc_uaddr2; /* UART address character 2 */ |
650 | ushort scc_rtemp; /* Temp storage */ |
651 | ushort scc_toseq; /* Transmit out of sequence char */ |
652 | ushort scc_char1; /* control character 1 */ |
653 | ushort scc_char2; /* control character 2 */ |
654 | ushort scc_char3; /* control character 3 */ |
655 | ushort scc_char4; /* control character 4 */ |
656 | ushort scc_char5; /* control character 5 */ |
657 | ushort scc_char6; /* control character 6 */ |
658 | ushort scc_char7; /* control character 7 */ |
659 | ushort scc_char8; /* control character 8 */ |
660 | ushort scc_rccm; /* receive control character mask */ |
661 | ushort scc_rccr; /* receive control character register */ |
662 | ushort scc_rlbc; /* receive last break character */ |
663 | } scc_uart_t; |
664 | |
665 | /* SCC Event and Mask registers when it is used as a UART. |
666 | */ |
667 | #define UART_SCCM_GLR ((ushort)0x1000) |
668 | #define UART_SCCM_GLT ((ushort)0x0800) |
669 | #define UART_SCCM_AB ((ushort)0x0200) |
670 | #define UART_SCCM_IDL ((ushort)0x0100) |
671 | #define UART_SCCM_GRA ((ushort)0x0080) |
672 | #define UART_SCCM_BRKE ((ushort)0x0040) |
673 | #define UART_SCCM_BRKS ((ushort)0x0020) |
674 | #define UART_SCCM_CCR ((ushort)0x0008) |
675 | #define UART_SCCM_BSY ((ushort)0x0004) |
676 | #define UART_SCCM_TX ((ushort)0x0002) |
677 | #define UART_SCCM_RX ((ushort)0x0001) |
678 | |
679 | /* The SCC PSMR when used as a UART. |
680 | */ |
681 | #define SCU_PSMR_FLC ((ushort)0x8000) |
682 | #define SCU_PSMR_SL ((ushort)0x4000) |
683 | #define SCU_PSMR_CL ((ushort)0x3000) |
684 | #define SCU_PSMR_UM ((ushort)0x0c00) |
685 | #define SCU_PSMR_FRZ ((ushort)0x0200) |
686 | #define SCU_PSMR_RZS ((ushort)0x0100) |
687 | #define SCU_PSMR_SYN ((ushort)0x0080) |
688 | #define SCU_PSMR_DRT ((ushort)0x0040) |
689 | #define SCU_PSMR_PEN ((ushort)0x0010) |
690 | #define SCU_PSMR_RPM ((ushort)0x000c) |
691 | #define SCU_PSMR_REVP ((ushort)0x0008) |
692 | #define SCU_PSMR_TPM ((ushort)0x0003) |
693 | #define SCU_PSMR_TEVP ((ushort)0x0003) |
694 | |
695 | /* CPM Transparent mode SCC. |
696 | */ |
697 | typedef struct scc_trans { |
698 | sccp_t st_genscc; |
699 | uint st_cpres; /* Preset CRC */ |
700 | uint st_cmask; /* Constant mask for CRC */ |
701 | } scc_trans_t; |
702 | |
703 | #define BD_SCC_TX_LAST ((ushort)0x0800) |
704 | |
705 | /* IIC parameter RAM. |
706 | */ |
707 | typedef struct iic { |
708 | ushort iic_rbase; /* Rx Buffer descriptor base address */ |
709 | ushort iic_tbase; /* Tx Buffer descriptor base address */ |
710 | u_char iic_rfcr; /* Rx function code */ |
711 | u_char iic_tfcr; /* Tx function code */ |
712 | ushort iic_mrblr; /* Max receive buffer length */ |
713 | uint iic_rstate; /* Internal */ |
714 | uint iic_rdp; /* Internal */ |
715 | ushort iic_rbptr; /* Internal */ |
716 | ushort iic_rbc; /* Internal */ |
717 | uint iic_rxtmp; /* Internal */ |
718 | uint iic_tstate; /* Internal */ |
719 | uint iic_tdp; /* Internal */ |
720 | ushort iic_tbptr; /* Internal */ |
721 | ushort iic_tbc; /* Internal */ |
722 | uint iic_txtmp; /* Internal */ |
723 | uint iic_res; /* reserved */ |
724 | ushort iic_rpbase; /* Relocation pointer */ |
725 | ushort iic_res2; /* reserved */ |
726 | } iic_t; |
727 | |
728 | /* SPI parameter RAM. |
729 | */ |
730 | typedef struct spi { |
731 | ushort spi_rbase; /* Rx Buffer descriptor base address */ |
732 | ushort spi_tbase; /* Tx Buffer descriptor base address */ |
733 | u_char spi_rfcr; /* Rx function code */ |
734 | u_char spi_tfcr; /* Tx function code */ |
735 | ushort spi_mrblr; /* Max receive buffer length */ |
736 | uint spi_rstate; /* Internal */ |
737 | uint spi_rdp; /* Internal */ |
738 | ushort spi_rbptr; /* Internal */ |
739 | ushort spi_rbc; /* Internal */ |
740 | uint spi_rxtmp; /* Internal */ |
741 | uint spi_tstate; /* Internal */ |
742 | uint spi_tdp; /* Internal */ |
743 | ushort spi_tbptr; /* Internal */ |
744 | ushort spi_tbc; /* Internal */ |
745 | uint spi_txtmp; /* Internal */ |
746 | uint spi_res; |
747 | ushort spi_rpbase; /* Relocation pointer */ |
748 | ushort spi_res2; |
749 | } spi_t; |
750 | |
751 | /* SPI Mode register. |
752 | */ |
753 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ |
754 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ |
755 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ |
756 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ |
757 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ |
758 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ |
759 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ |
760 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ |
761 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ |
762 | |
763 | #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) |
764 | #define SPMODE_PM(x) ((x) &0xF) |
765 | |
766 | /* HDLC parameter RAM. |
767 | */ |
768 | |
769 | typedef struct hdlc_pram_s { |
770 | /* |
771 | * SCC parameter RAM |
772 | */ |
773 | ushort rbase; /* Rx Buffer descriptor base address */ |
774 | ushort tbase; /* Tx Buffer descriptor base address */ |
775 | uchar rfcr; /* Rx function code */ |
776 | uchar tfcr; /* Tx function code */ |
777 | ushort mrblr; /* Rx buffer length */ |
778 | ulong rstate; /* Rx internal state */ |
779 | ulong rptr; /* Rx internal data pointer */ |
780 | ushort rbptr; /* rb BD Pointer */ |
781 | ushort rcount; /* Rx internal byte count */ |
782 | ulong rtemp; /* Rx temp */ |
783 | ulong tstate; /* Tx internal state */ |
784 | ulong tptr; /* Tx internal data pointer */ |
785 | ushort tbptr; /* Tx BD pointer */ |
786 | ushort tcount; /* Tx byte count */ |
787 | ulong ttemp; /* Tx temp */ |
788 | ulong rcrc; /* temp receive CRC */ |
789 | ulong tcrc; /* temp transmit CRC */ |
790 | /* |
791 | * HDLC specific parameter RAM |
792 | */ |
793 | uchar res[4]; /* reserved */ |
794 | ulong c_mask; /* CRC constant */ |
795 | ulong c_pres; /* CRC preset */ |
796 | ushort disfc; /* discarded frame counter */ |
797 | ushort crcec; /* CRC error counter */ |
798 | ushort abtsc; /* abort sequence counter */ |
799 | ushort nmarc; /* nonmatching address rx cnt */ |
800 | ushort retrc; /* frame retransmission cnt */ |
801 | ushort mflr; /* maximum frame length reg */ |
802 | ushort max_cnt; /* maximum length counter */ |
803 | ushort rfthr; /* received frames threshold */ |
804 | ushort rfcnt; /* received frames count */ |
805 | ushort hmask; /* user defined frm addr mask */ |
806 | ushort haddr1; /* user defined frm address 1 */ |
807 | ushort haddr2; /* user defined frm address 2 */ |
808 | ushort haddr3; /* user defined frm address 3 */ |
809 | ushort haddr4; /* user defined frm address 4 */ |
810 | ushort tmp; /* temp */ |
811 | ushort tmp_mb; /* temp */ |
812 | } hdlc_pram_t; |
813 | |
814 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM |
815 | * channels or devices. All of these are presented to the PPC core |
816 | * as a single interrupt. The CPM interrupt handler dispatches its |
817 | * own handlers, in a similar fashion to the PPC core handler. We |
818 | * use the table as defined in the manuals (i.e. no special high |
819 | * priority and SCC1 == SCCa, etc...). |
820 | */ |
821 | #define CPMVEC_NR 32 |
822 | #define CPMVEC_OFFSET 0x00010000 |
823 | #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) |
824 | #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) |
825 | #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) |
826 | #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) |
827 | #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) |
828 | #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) |
829 | #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) |
830 | #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) |
831 | #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) |
832 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) |
833 | #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) |
834 | #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) |
835 | #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) |
836 | #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) |
837 | #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) |
838 | #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) |
839 | #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) |
840 | #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) |
841 | #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) |
842 | #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) |
843 | #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) |
844 | #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) |
845 | #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) |
846 | #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) |
847 | #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) |
848 | #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) |
849 | #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) |
850 | #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) |
851 | #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) |
852 | |
853 | extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); |
854 | |
855 | /* CPM interrupt configuration vector. |
856 | */ |
857 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ |
858 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ |
859 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ |
860 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ |
861 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ |
862 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ |
863 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ |
864 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ |
865 | #endif /* __CPM_8XX__ */ |
866 |