blob: 3e1b9f4281ada37d9604e376fcc83c236d181bb9
1 | /* |
2 | * Copyright 2009-2012 Freescale Semiconductor, Inc. |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ |
5 | */ |
6 | |
7 | #ifndef __FM_ETH_H__ |
8 | #define __FM_ETH_H__ |
9 | |
10 | #include <common.h> |
11 | #include <phy.h> |
12 | #include <asm/types.h> |
13 | |
14 | enum fm_port { |
15 | FM1_DTSEC1, |
16 | FM1_DTSEC2, |
17 | FM1_DTSEC3, |
18 | FM1_DTSEC4, |
19 | FM1_DTSEC5, |
20 | FM1_DTSEC6, |
21 | FM1_DTSEC9, |
22 | FM1_DTSEC10, |
23 | FM1_10GEC1, |
24 | FM1_10GEC2, |
25 | FM1_10GEC3, |
26 | FM1_10GEC4, |
27 | FM2_DTSEC1, |
28 | FM2_DTSEC2, |
29 | FM2_DTSEC3, |
30 | FM2_DTSEC4, |
31 | FM2_DTSEC5, |
32 | FM2_DTSEC6, |
33 | FM2_DTSEC9, |
34 | FM2_DTSEC10, |
35 | FM2_10GEC1, |
36 | FM2_10GEC2, |
37 | NUM_FM_PORTS, |
38 | }; |
39 | |
40 | enum fm_eth_type { |
41 | FM_ETH_1G_E, |
42 | FM_ETH_10G_E, |
43 | }; |
44 | |
45 | #ifdef CONFIG_SYS_FMAN_V3 |
46 | #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) |
47 | #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) |
48 | #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) |
49 | #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) |
50 | #else |
51 | #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) |
52 | #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) |
53 | #endif |
54 | |
55 | #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" |
56 | #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" |
57 | |
58 | /* Fman ethernet info struct */ |
59 | #define FM_ETH_INFO_INITIALIZER(idx, pregs) \ |
60 | .fm = idx, \ |
61 | .phy_regs = (void *)pregs, \ |
62 | .enet_if = PHY_INTERFACE_MODE_NONE, \ |
63 | |
64 | #ifdef CONFIG_SYS_FMAN_V3 |
65 | #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ |
66 | { \ |
67 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \ |
68 | .index = idx, \ |
69 | .num = n - 1, \ |
70 | .type = FM_ETH_1G_E, \ |
71 | .port = FM##idx##_DTSEC##n, \ |
72 | .rx_port_id = RX_PORT_1G_BASE + n - 1, \ |
73 | .tx_port_id = TX_PORT_1G_BASE + n - 1, \ |
74 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
75 | offsetof(struct ccsr_fman, memac[n-1]),\ |
76 | } |
77 | |
78 | #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION |
79 | #define FM_TGEC_INFO_INITIALIZER(idx, n) \ |
80 | { \ |
81 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ |
82 | .index = idx, \ |
83 | .num = n - 1, \ |
84 | .type = FM_ETH_10G_E, \ |
85 | .port = FM##idx##_10GEC##n, \ |
86 | .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ |
87 | .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ |
88 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
89 | offsetof(struct ccsr_fman, memac[n-1]),\ |
90 | } |
91 | #else |
92 | #define FM_TGEC_INFO_INITIALIZER(idx, n) \ |
93 | { \ |
94 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ |
95 | .index = idx, \ |
96 | .num = n - 1, \ |
97 | .type = FM_ETH_10G_E, \ |
98 | .port = FM##idx##_10GEC##n, \ |
99 | .rx_port_id = RX_PORT_10G_BASE + n - 1, \ |
100 | .tx_port_id = TX_PORT_10G_BASE + n - 1, \ |
101 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
102 | offsetof(struct ccsr_fman, memac[n-1+8]),\ |
103 | } |
104 | #endif |
105 | |
106 | #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) |
107 | #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ |
108 | { \ |
109 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ |
110 | .index = idx, \ |
111 | .num = n - 1, \ |
112 | .type = FM_ETH_10G_E, \ |
113 | .port = FM##idx##_10GEC##n, \ |
114 | .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \ |
115 | .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \ |
116 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
117 | offsetof(struct ccsr_fman, memac[n-1-2]),\ |
118 | } |
119 | #endif |
120 | |
121 | #else |
122 | #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ |
123 | { \ |
124 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ |
125 | .index = idx, \ |
126 | .num = n - 1, \ |
127 | .type = FM_ETH_1G_E, \ |
128 | .port = FM##idx##_DTSEC##n, \ |
129 | .rx_port_id = RX_PORT_1G_BASE + n - 1, \ |
130 | .tx_port_id = TX_PORT_1G_BASE + n - 1, \ |
131 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
132 | offsetof(struct ccsr_fman, mac_1g[n-1]),\ |
133 | } |
134 | |
135 | #define FM_TGEC_INFO_INITIALIZER(idx, n) \ |
136 | { \ |
137 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ |
138 | .index = idx, \ |
139 | .num = n - 1, \ |
140 | .type = FM_ETH_10G_E, \ |
141 | .port = FM##idx##_10GEC##n, \ |
142 | .rx_port_id = RX_PORT_10G_BASE + n - 1, \ |
143 | .tx_port_id = TX_PORT_10G_BASE + n - 1, \ |
144 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
145 | offsetof(struct ccsr_fman, mac_10g[n-1]),\ |
146 | } |
147 | #endif |
148 | struct fm_eth_info { |
149 | u8 enabled; |
150 | u8 fm; |
151 | u8 num; |
152 | u8 phy_addr; |
153 | int index; |
154 | u16 rx_port_id; |
155 | u16 tx_port_id; |
156 | enum fm_port port; |
157 | enum fm_eth_type type; |
158 | void *phy_regs; |
159 | phy_interface_t enet_if; |
160 | u32 compat_offset; |
161 | struct mii_dev *bus; |
162 | }; |
163 | |
164 | struct tgec_mdio_info { |
165 | struct tgec_mdio_controller *regs; |
166 | char *name; |
167 | }; |
168 | |
169 | struct memac_mdio_info { |
170 | struct memac_mdio_controller *regs; |
171 | char *name; |
172 | }; |
173 | |
174 | int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info); |
175 | int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info); |
176 | |
177 | int fm_standard_init(bd_t *bis); |
178 | void fman_enet_init(void); |
179 | void fdt_fixup_fman_ethernet(void *fdt); |
180 | phy_interface_t fm_info_get_enet_if(enum fm_port port); |
181 | void fm_info_set_phy_address(enum fm_port port, int address); |
182 | int fm_info_get_phy_address(enum fm_port port); |
183 | void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); |
184 | void fm_disable_port(enum fm_port port); |
185 | void fm_enable_port(enum fm_port port); |
186 | void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, |
187 | unsigned int port_num, int phy_base_addr); |
188 | int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, |
189 | unsigned int port_num, unsigned regnum); |
190 | |
191 | #endif |
192 |