blob: c1b6648591e410e23d13a8b88aa27cdb8233efdb
1 | /* |
2 | * FSL SD/MMC Defines |
3 | *------------------------------------------------------------------- |
4 | * |
5 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc |
6 | * |
7 | * SPDX-License-Identifier: GPL-2.0+ |
8 | */ |
9 | |
10 | #ifndef __FSL_ESDHC_H__ |
11 | #define __FSL_ESDHC_H__ |
12 | |
13 | #include <asm/errno.h> |
14 | #include <asm/byteorder.h> |
15 | |
16 | /* needed for the mmc_cfg definition */ |
17 | #include <mmc.h> |
18 | |
19 | /* FSL eSDHC-specific constants */ |
20 | #define SYSCTL 0x0002e02c |
21 | #define SYSCTL_INITA 0x08000000 |
22 | #define SYSCTL_TIMEOUT_MASK 0x000f0000 |
23 | #define SYSCTL_CLOCK_MASK 0x0000fff0 |
24 | #define SYSCTL_CKEN 0x00000008 |
25 | #define SYSCTL_PEREN 0x00000004 |
26 | #define SYSCTL_HCKEN 0x00000002 |
27 | #define SYSCTL_IPGEN 0x00000001 |
28 | #define SYSCTL_RSTA 0x01000000 |
29 | #define SYSCTL_RSTC 0x02000000 |
30 | #define SYSCTL_RSTD 0x04000000 |
31 | |
32 | #define IRQSTAT 0x0002e030 |
33 | #define IRQSTAT_DMAE (0x10000000) |
34 | #define IRQSTAT_AC12E (0x01000000) |
35 | #define IRQSTAT_DEBE (0x00400000) |
36 | #define IRQSTAT_DCE (0x00200000) |
37 | #define IRQSTAT_DTOE (0x00100000) |
38 | #define IRQSTAT_CIE (0x00080000) |
39 | #define IRQSTAT_CEBE (0x00040000) |
40 | #define IRQSTAT_CCE (0x00020000) |
41 | #define IRQSTAT_CTOE (0x00010000) |
42 | #define IRQSTAT_CINT (0x00000100) |
43 | #define IRQSTAT_CRM (0x00000080) |
44 | #define IRQSTAT_CINS (0x00000040) |
45 | #define IRQSTAT_BRR (0x00000020) |
46 | #define IRQSTAT_BWR (0x00000010) |
47 | #define IRQSTAT_DINT (0x00000008) |
48 | #define IRQSTAT_BGE (0x00000004) |
49 | #define IRQSTAT_TC (0x00000002) |
50 | #define IRQSTAT_CC (0x00000001) |
51 | |
52 | #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) |
53 | #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \ |
54 | IRQSTAT_DMAE) |
55 | #define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT) |
56 | |
57 | #define IRQSTATEN 0x0002e034 |
58 | #define IRQSTATEN_DMAE (0x10000000) |
59 | #define IRQSTATEN_AC12E (0x01000000) |
60 | #define IRQSTATEN_DEBE (0x00400000) |
61 | #define IRQSTATEN_DCE (0x00200000) |
62 | #define IRQSTATEN_DTOE (0x00100000) |
63 | #define IRQSTATEN_CIE (0x00080000) |
64 | #define IRQSTATEN_CEBE (0x00040000) |
65 | #define IRQSTATEN_CCE (0x00020000) |
66 | #define IRQSTATEN_CTOE (0x00010000) |
67 | #define IRQSTATEN_CINT (0x00000100) |
68 | #define IRQSTATEN_CRM (0x00000080) |
69 | #define IRQSTATEN_CINS (0x00000040) |
70 | #define IRQSTATEN_BRR (0x00000020) |
71 | #define IRQSTATEN_BWR (0x00000010) |
72 | #define IRQSTATEN_DINT (0x00000008) |
73 | #define IRQSTATEN_BGE (0x00000004) |
74 | #define IRQSTATEN_TC (0x00000002) |
75 | #define IRQSTATEN_CC (0x00000001) |
76 | |
77 | #define PRSSTAT 0x0002e024 |
78 | #define PRSSTAT_DAT0 (0x01000000) |
79 | #define PRSSTAT_CLSL (0x00800000) |
80 | #define PRSSTAT_WPSPL (0x00080000) |
81 | #define PRSSTAT_CDPL (0x00040000) |
82 | #define PRSSTAT_CINS (0x00010000) |
83 | #define PRSSTAT_BREN (0x00000800) |
84 | #define PRSSTAT_BWEN (0x00000400) |
85 | #define PRSSTAT_DLA (0x00000004) |
86 | #define PRSSTAT_CICHB (0x00000002) |
87 | #define PRSSTAT_CIDHB (0x00000001) |
88 | |
89 | #define PROCTL 0x0002e028 |
90 | #define PROCTL_INIT 0x00000020 |
91 | #define PROCTL_DTW_4 0x00000002 |
92 | #define PROCTL_DTW_8 0x00000004 |
93 | |
94 | #define CMDARG 0x0002e008 |
95 | |
96 | #define XFERTYP 0x0002e00c |
97 | #define XFERTYP_CMD(x) ((x & 0x3f) << 24) |
98 | #define XFERTYP_CMDTYP_NORMAL 0x0 |
99 | #define XFERTYP_CMDTYP_SUSPEND 0x00400000 |
100 | #define XFERTYP_CMDTYP_RESUME 0x00800000 |
101 | #define XFERTYP_CMDTYP_ABORT 0x00c00000 |
102 | #define XFERTYP_DPSEL 0x00200000 |
103 | #define XFERTYP_CICEN 0x00100000 |
104 | #define XFERTYP_CCCEN 0x00080000 |
105 | #define XFERTYP_RSPTYP_NONE 0 |
106 | #define XFERTYP_RSPTYP_136 0x00010000 |
107 | #define XFERTYP_RSPTYP_48 0x00020000 |
108 | #define XFERTYP_RSPTYP_48_BUSY 0x00030000 |
109 | #define XFERTYP_MSBSEL 0x00000020 |
110 | #define XFERTYP_DTDSEL 0x00000010 |
111 | #define XFERTYP_AC12EN 0x00000004 |
112 | #define XFERTYP_BCEN 0x00000002 |
113 | #define XFERTYP_DMAEN 0x00000001 |
114 | |
115 | #define CINS_TIMEOUT 1000 |
116 | #define PIO_TIMEOUT 100000 |
117 | |
118 | #define DSADDR 0x2e004 |
119 | |
120 | #define CMDRSP0 0x2e010 |
121 | #define CMDRSP1 0x2e014 |
122 | #define CMDRSP2 0x2e018 |
123 | #define CMDRSP3 0x2e01c |
124 | |
125 | #define DATPORT 0x2e020 |
126 | |
127 | #define WML 0x2e044 |
128 | #define WML_WRITE 0x00010000 |
129 | #ifdef CONFIG_FSL_SDHC_V2_3 |
130 | #define WML_RD_WML_MAX 0x80 |
131 | #define WML_WR_WML_MAX 0x80 |
132 | #define WML_RD_WML_MAX_VAL 0x0 |
133 | #define WML_WR_WML_MAX_VAL 0x0 |
134 | #define WML_RD_WML_MASK 0x7f |
135 | #define WML_WR_WML_MASK 0x7f0000 |
136 | #else |
137 | #define WML_RD_WML_MAX 0x10 |
138 | #define WML_WR_WML_MAX 0x80 |
139 | #define WML_RD_WML_MAX_VAL 0x10 |
140 | #define WML_WR_WML_MAX_VAL 0x80 |
141 | #define WML_RD_WML_MASK 0xff |
142 | #define WML_WR_WML_MASK 0xff0000 |
143 | #endif |
144 | |
145 | #define BLKATTR 0x2e004 |
146 | #define BLKATTR_CNT(x) ((x & 0xffff) << 16) |
147 | #define BLKATTR_SIZE(x) (x & 0x1fff) |
148 | #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ |
149 | |
150 | #define ESDHC_HOSTCAPBLT_VS18 0x04000000 |
151 | #define ESDHC_HOSTCAPBLT_VS30 0x02000000 |
152 | #define ESDHC_HOSTCAPBLT_VS33 0x01000000 |
153 | #define ESDHC_HOSTCAPBLT_SRS 0x00800000 |
154 | #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 |
155 | #define ESDHC_HOSTCAPBLT_HSS 0x00200000 |
156 | |
157 | struct fsl_esdhc_cfg { |
158 | u32 esdhc_base; |
159 | u32 sdhc_clk; |
160 | u8 max_bus_width; |
161 | struct mmc_config cfg; |
162 | }; |
163 | |
164 | /* Select the correct accessors depending on endianess */ |
165 | #if defined CONFIG_SYS_FSL_ESDHC_LE |
166 | #define esdhc_read32 in_le32 |
167 | #define esdhc_write32 out_le32 |
168 | #define esdhc_clrsetbits32 clrsetbits_le32 |
169 | #define esdhc_clrbits32 clrbits_le32 |
170 | #define esdhc_setbits32 setbits_le32 |
171 | #elif defined(CONFIG_SYS_FSL_ESDHC_BE) |
172 | #define esdhc_read32 in_be32 |
173 | #define esdhc_write32 out_be32 |
174 | #define esdhc_clrsetbits32 clrsetbits_be32 |
175 | #define esdhc_clrbits32 clrbits_be32 |
176 | #define esdhc_setbits32 setbits_be32 |
177 | #elif __BYTE_ORDER == __LITTLE_ENDIAN |
178 | #define esdhc_read32 in_le32 |
179 | #define esdhc_write32 out_le32 |
180 | #define esdhc_clrsetbits32 clrsetbits_le32 |
181 | #define esdhc_clrbits32 clrbits_le32 |
182 | #define esdhc_setbits32 setbits_le32 |
183 | #elif __BYTE_ORDER == __BIG_ENDIAN |
184 | #define esdhc_read32 in_be32 |
185 | #define esdhc_write32 out_be32 |
186 | #define esdhc_clrsetbits32 clrsetbits_be32 |
187 | #define esdhc_clrbits32 clrbits_be32 |
188 | #define esdhc_setbits32 setbits_be32 |
189 | #else |
190 | #error "Endianess is not defined: please fix to continue" |
191 | #endif |
192 | |
193 | #ifdef CONFIG_FSL_ESDHC |
194 | int fsl_esdhc_mmc_init(bd_t *bis); |
195 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); |
196 | void fdt_fixup_esdhc(void *blob, bd_t *bd); |
197 | #else |
198 | static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } |
199 | static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} |
200 | #endif /* CONFIG_FSL_ESDHC */ |
201 | void __noreturn mmc_boot(void); |
202 | void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst); |
203 | |
204 | #endif /* __FSL_ESDHC_H__ */ |
205 |