blob: 938966db5a3ee41583b7b140b928954a8cd608d7
1 | /* |
2 | * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. |
3 | * All rights reserved. |
4 | * Authors: Carsten Langgaard <carstenl@mips.com> |
5 | * Maciej W. Rozycki <macro@mips.com> |
6 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) |
7 | * |
8 | * SPDX-License-Identifier: GPL-2.0 |
9 | */ |
10 | #ifndef _ASM_GT64120_H |
11 | #define _ASM_GT64120_H |
12 | |
13 | #define MSK(n) ((1 << (n)) - 1) |
14 | |
15 | /* |
16 | * Register offset addresses |
17 | */ |
18 | /* CPU Configuration. */ |
19 | #define GT_CPU_OFS 0x000 |
20 | |
21 | #define GT_MULTI_OFS 0x120 |
22 | |
23 | /* CPU Address Decode. */ |
24 | #define GT_SCS10LD_OFS 0x008 |
25 | #define GT_SCS10HD_OFS 0x010 |
26 | #define GT_SCS32LD_OFS 0x018 |
27 | #define GT_SCS32HD_OFS 0x020 |
28 | #define GT_CS20LD_OFS 0x028 |
29 | #define GT_CS20HD_OFS 0x030 |
30 | #define GT_CS3BOOTLD_OFS 0x038 |
31 | #define GT_CS3BOOTHD_OFS 0x040 |
32 | #define GT_PCI0IOLD_OFS 0x048 |
33 | #define GT_PCI0IOHD_OFS 0x050 |
34 | #define GT_PCI0M0LD_OFS 0x058 |
35 | #define GT_PCI0M0HD_OFS 0x060 |
36 | #define GT_ISD_OFS 0x068 |
37 | |
38 | #define GT_PCI0M1LD_OFS 0x080 |
39 | #define GT_PCI0M1HD_OFS 0x088 |
40 | #define GT_PCI1IOLD_OFS 0x090 |
41 | #define GT_PCI1IOHD_OFS 0x098 |
42 | #define GT_PCI1M0LD_OFS 0x0a0 |
43 | #define GT_PCI1M0HD_OFS 0x0a8 |
44 | #define GT_PCI1M1LD_OFS 0x0b0 |
45 | #define GT_PCI1M1HD_OFS 0x0b8 |
46 | #define GT_PCI1M1LD_OFS 0x0b0 |
47 | #define GT_PCI1M1HD_OFS 0x0b8 |
48 | |
49 | #define GT_SCS10AR_OFS 0x0d0 |
50 | #define GT_SCS32AR_OFS 0x0d8 |
51 | #define GT_CS20R_OFS 0x0e0 |
52 | #define GT_CS3BOOTR_OFS 0x0e8 |
53 | |
54 | #define GT_PCI0IOREMAP_OFS 0x0f0 |
55 | #define GT_PCI0M0REMAP_OFS 0x0f8 |
56 | #define GT_PCI0M1REMAP_OFS 0x100 |
57 | #define GT_PCI1IOREMAP_OFS 0x108 |
58 | #define GT_PCI1M0REMAP_OFS 0x110 |
59 | #define GT_PCI1M1REMAP_OFS 0x118 |
60 | |
61 | /* CPU Error Report. */ |
62 | #define GT_CPUERR_ADDRLO_OFS 0x070 |
63 | #define GT_CPUERR_ADDRHI_OFS 0x078 |
64 | |
65 | #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ |
66 | #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ |
67 | #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ |
68 | |
69 | /* CPU Sync Barrier. */ |
70 | #define GT_PCI0SYNC_OFS 0x0c0 |
71 | #define GT_PCI1SYNC_OFS 0x0c8 |
72 | |
73 | /* SDRAM and Device Address Decode. */ |
74 | #define GT_SCS0LD_OFS 0x400 |
75 | #define GT_SCS0HD_OFS 0x404 |
76 | #define GT_SCS1LD_OFS 0x408 |
77 | #define GT_SCS1HD_OFS 0x40c |
78 | #define GT_SCS2LD_OFS 0x410 |
79 | #define GT_SCS2HD_OFS 0x414 |
80 | #define GT_SCS3LD_OFS 0x418 |
81 | #define GT_SCS3HD_OFS 0x41c |
82 | #define GT_CS0LD_OFS 0x420 |
83 | #define GT_CS0HD_OFS 0x424 |
84 | #define GT_CS1LD_OFS 0x428 |
85 | #define GT_CS1HD_OFS 0x42c |
86 | #define GT_CS2LD_OFS 0x430 |
87 | #define GT_CS2HD_OFS 0x434 |
88 | #define GT_CS3LD_OFS 0x438 |
89 | #define GT_CS3HD_OFS 0x43c |
90 | #define GT_BOOTLD_OFS 0x440 |
91 | #define GT_BOOTHD_OFS 0x444 |
92 | |
93 | #define GT_ADERR_OFS 0x470 |
94 | |
95 | /* SDRAM Configuration. */ |
96 | #define GT_SDRAM_CFG_OFS 0x448 |
97 | |
98 | #define GT_SDRAM_OPMODE_OFS 0x474 |
99 | #define GT_SDRAM_BM_OFS 0x478 |
100 | #define GT_SDRAM_ADDRDECODE_OFS 0x47c |
101 | |
102 | /* SDRAM Parameters. */ |
103 | #define GT_SDRAM_B0_OFS 0x44c |
104 | #define GT_SDRAM_B1_OFS 0x450 |
105 | #define GT_SDRAM_B2_OFS 0x454 |
106 | #define GT_SDRAM_B3_OFS 0x458 |
107 | |
108 | /* Device Parameters. */ |
109 | #define GT_DEV_B0_OFS 0x45c |
110 | #define GT_DEV_B1_OFS 0x460 |
111 | #define GT_DEV_B2_OFS 0x464 |
112 | #define GT_DEV_B3_OFS 0x468 |
113 | #define GT_DEV_BOOT_OFS 0x46c |
114 | |
115 | /* ECC. */ |
116 | #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ |
117 | #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ |
118 | #define GT_ECC_MEM 0x488 /* GT-64120A only */ |
119 | #define GT_ECC_CALC 0x48c /* GT-64120A only */ |
120 | #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ |
121 | |
122 | /* DMA Record. */ |
123 | #define GT_DMA0_CNT_OFS 0x800 |
124 | #define GT_DMA1_CNT_OFS 0x804 |
125 | #define GT_DMA2_CNT_OFS 0x808 |
126 | #define GT_DMA3_CNT_OFS 0x80c |
127 | #define GT_DMA0_SA_OFS 0x810 |
128 | #define GT_DMA1_SA_OFS 0x814 |
129 | #define GT_DMA2_SA_OFS 0x818 |
130 | #define GT_DMA3_SA_OFS 0x81c |
131 | #define GT_DMA0_DA_OFS 0x820 |
132 | #define GT_DMA1_DA_OFS 0x824 |
133 | #define GT_DMA2_DA_OFS 0x828 |
134 | #define GT_DMA3_DA_OFS 0x82c |
135 | #define GT_DMA0_NEXT_OFS 0x830 |
136 | #define GT_DMA1_NEXT_OFS 0x834 |
137 | #define GT_DMA2_NEXT_OFS 0x838 |
138 | #define GT_DMA3_NEXT_OFS 0x83c |
139 | |
140 | #define GT_DMA0_CUR_OFS 0x870 |
141 | #define GT_DMA1_CUR_OFS 0x874 |
142 | #define GT_DMA2_CUR_OFS 0x878 |
143 | #define GT_DMA3_CUR_OFS 0x87c |
144 | |
145 | /* DMA Channel Control. */ |
146 | #define GT_DMA0_CTRL_OFS 0x840 |
147 | #define GT_DMA1_CTRL_OFS 0x844 |
148 | #define GT_DMA2_CTRL_OFS 0x848 |
149 | #define GT_DMA3_CTRL_OFS 0x84c |
150 | |
151 | /* DMA Arbiter. */ |
152 | #define GT_DMA_ARB_OFS 0x860 |
153 | |
154 | /* Timer/Counter. */ |
155 | #define GT_TC0_OFS 0x850 |
156 | #define GT_TC1_OFS 0x854 |
157 | #define GT_TC2_OFS 0x858 |
158 | #define GT_TC3_OFS 0x85c |
159 | |
160 | #define GT_TC_CONTROL_OFS 0x864 |
161 | |
162 | /* PCI Internal. */ |
163 | #define GT_PCI0_CMD_OFS 0xc00 |
164 | #define GT_PCI0_TOR_OFS 0xc04 |
165 | #define GT_PCI0_BS_SCS10_OFS 0xc08 |
166 | #define GT_PCI0_BS_SCS32_OFS 0xc0c |
167 | #define GT_PCI0_BS_CS20_OFS 0xc10 |
168 | #define GT_PCI0_BS_CS3BT_OFS 0xc14 |
169 | |
170 | #define GT_PCI1_IACK_OFS 0xc30 |
171 | #define GT_PCI0_IACK_OFS 0xc34 |
172 | |
173 | #define GT_PCI0_BARE_OFS 0xc3c |
174 | #define GT_PCI0_PREFMBR_OFS 0xc40 |
175 | |
176 | #define GT_PCI0_SCS10_BAR_OFS 0xc48 |
177 | #define GT_PCI0_SCS32_BAR_OFS 0xc4c |
178 | #define GT_PCI0_CS20_BAR_OFS 0xc50 |
179 | #define GT_PCI0_CS3BT_BAR_OFS 0xc54 |
180 | #define GT_PCI0_SSCS10_BAR_OFS 0xc58 |
181 | #define GT_PCI0_SSCS32_BAR_OFS 0xc5c |
182 | |
183 | #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 |
184 | |
185 | #define GT_PCI1_CMD_OFS 0xc80 |
186 | #define GT_PCI1_TOR_OFS 0xc84 |
187 | #define GT_PCI1_BS_SCS10_OFS 0xc88 |
188 | #define GT_PCI1_BS_SCS32_OFS 0xc8c |
189 | #define GT_PCI1_BS_CS20_OFS 0xc90 |
190 | #define GT_PCI1_BS_CS3BT_OFS 0xc94 |
191 | |
192 | #define GT_PCI1_BARE_OFS 0xcbc |
193 | #define GT_PCI1_PREFMBR_OFS 0xcc0 |
194 | |
195 | #define GT_PCI1_SCS10_BAR_OFS 0xcc8 |
196 | #define GT_PCI1_SCS32_BAR_OFS 0xccc |
197 | #define GT_PCI1_CS20_BAR_OFS 0xcd0 |
198 | #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 |
199 | #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 |
200 | #define GT_PCI1_SSCS32_BAR_OFS 0xcdc |
201 | |
202 | #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 |
203 | |
204 | #define GT_PCI1_CFGADDR_OFS 0xcf0 |
205 | #define GT_PCI1_CFGDATA_OFS 0xcf4 |
206 | #define GT_PCI0_CFGADDR_OFS 0xcf8 |
207 | #define GT_PCI0_CFGDATA_OFS 0xcfc |
208 | |
209 | /* Interrupts. */ |
210 | #define GT_INTRCAUSE_OFS 0xc18 |
211 | #define GT_INTRMASK_OFS 0xc1c |
212 | |
213 | #define GT_PCI0_ICMASK_OFS 0xc24 |
214 | #define GT_PCI0_SERR0MASK_OFS 0xc28 |
215 | |
216 | #define GT_CPU_INTSEL_OFS 0xc70 |
217 | #define GT_PCI0_INTSEL_OFS 0xc74 |
218 | |
219 | #define GT_HINTRCAUSE_OFS 0xc98 |
220 | #define GT_HINTRMASK_OFS 0xc9c |
221 | |
222 | #define GT_PCI0_HICMASK_OFS 0xca4 |
223 | #define GT_PCI1_SERR1MASK_OFS 0xca8 |
224 | |
225 | |
226 | /* |
227 | * I2O Support Registers |
228 | */ |
229 | #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 |
230 | #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 |
231 | #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 |
232 | #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c |
233 | #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 |
234 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 |
235 | #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 |
236 | #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c |
237 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 |
238 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 |
239 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 |
240 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 |
241 | #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 |
242 | #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 |
243 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 |
244 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 |
245 | #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 |
246 | #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c |
247 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 |
248 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 |
249 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 |
250 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c |
251 | |
252 | #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 |
253 | #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 |
254 | #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 |
255 | #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c |
256 | #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 |
257 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 |
258 | #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 |
259 | #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c |
260 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 |
261 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 |
262 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 |
263 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 |
264 | #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 |
265 | #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 |
266 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 |
267 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 |
268 | #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 |
269 | #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c |
270 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 |
271 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 |
272 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 |
273 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c |
274 | |
275 | /* |
276 | * Register encodings |
277 | */ |
278 | #define GT_CPU_ENDIAN_SHF 12 |
279 | #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) |
280 | #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK |
281 | #define GT_CPU_WR_SHF 16 |
282 | #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) |
283 | #define GT_CPU_WR_BIT GT_CPU_WR_MSK |
284 | #define GT_CPU_WR_DXDXDXDX 0 |
285 | #define GT_CPU_WR_DDDD 1 |
286 | |
287 | |
288 | #define GT_PCI_DCRM_SHF 21 |
289 | #define GT_PCI_LD_SHF 0 |
290 | #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) |
291 | #define GT_PCI_HD_SHF 0 |
292 | #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) |
293 | #define GT_PCI_REMAP_SHF 0 |
294 | #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) |
295 | |
296 | |
297 | #define GT_CFGADDR_CFGEN_SHF 31 |
298 | #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) |
299 | #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK |
300 | |
301 | #define GT_CFGADDR_BUSNUM_SHF 16 |
302 | #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) |
303 | |
304 | #define GT_CFGADDR_DEVNUM_SHF 11 |
305 | #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) |
306 | |
307 | #define GT_CFGADDR_FUNCNUM_SHF 8 |
308 | #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) |
309 | |
310 | #define GT_CFGADDR_REGNUM_SHF 2 |
311 | #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) |
312 | |
313 | |
314 | #define GT_SDRAM_BM_ORDER_SHF 2 |
315 | #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) |
316 | #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK |
317 | #define GT_SDRAM_BM_ORDER_SUB 1 |
318 | #define GT_SDRAM_BM_ORDER_LIN 0 |
319 | |
320 | #define GT_SDRAM_BM_RSVD_ALL1 0xffb |
321 | |
322 | |
323 | #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 |
324 | #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) |
325 | #define GT_SDRAM_ADDRDECODE_ADDR_0 0 |
326 | #define GT_SDRAM_ADDRDECODE_ADDR_1 1 |
327 | #define GT_SDRAM_ADDRDECODE_ADDR_2 2 |
328 | #define GT_SDRAM_ADDRDECODE_ADDR_3 3 |
329 | #define GT_SDRAM_ADDRDECODE_ADDR_4 4 |
330 | #define GT_SDRAM_ADDRDECODE_ADDR_5 5 |
331 | #define GT_SDRAM_ADDRDECODE_ADDR_6 6 |
332 | #define GT_SDRAM_ADDRDECODE_ADDR_7 7 |
333 | |
334 | |
335 | #define GT_SDRAM_B0_CASLAT_SHF 0 |
336 | #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) |
337 | #define GT_SDRAM_B0_CASLAT_2 1 |
338 | #define GT_SDRAM_B0_CASLAT_3 2 |
339 | |
340 | #define GT_SDRAM_B0_FTDIS_SHF 2 |
341 | #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) |
342 | #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK |
343 | |
344 | #define GT_SDRAM_B0_SRASPRCHG_SHF 3 |
345 | #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) |
346 | #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK |
347 | #define GT_SDRAM_B0_SRASPRCHG_2 0 |
348 | #define GT_SDRAM_B0_SRASPRCHG_3 1 |
349 | |
350 | #define GT_SDRAM_B0_B0COMPAB_SHF 4 |
351 | #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) |
352 | #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK |
353 | |
354 | #define GT_SDRAM_B0_64BITINT_SHF 5 |
355 | #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) |
356 | #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK |
357 | #define GT_SDRAM_B0_64BITINT_2 0 |
358 | #define GT_SDRAM_B0_64BITINT_4 1 |
359 | |
360 | #define GT_SDRAM_B0_BW_SHF 6 |
361 | #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) |
362 | #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK |
363 | #define GT_SDRAM_B0_BW_32 0 |
364 | #define GT_SDRAM_B0_BW_64 1 |
365 | |
366 | #define GT_SDRAM_B0_BLODD_SHF 7 |
367 | #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) |
368 | #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK |
369 | |
370 | #define GT_SDRAM_B0_PAR_SHF 8 |
371 | #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) |
372 | #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK |
373 | |
374 | #define GT_SDRAM_B0_BYPASS_SHF 9 |
375 | #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) |
376 | #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK |
377 | |
378 | #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 |
379 | #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) |
380 | #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK |
381 | #define GT_SDRAM_B0_SRAS2SCAS_2 0 |
382 | #define GT_SDRAM_B0_SRAS2SCAS_3 1 |
383 | |
384 | #define GT_SDRAM_B0_SIZE_SHF 11 |
385 | #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) |
386 | #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK |
387 | #define GT_SDRAM_B0_SIZE_16M 0 |
388 | #define GT_SDRAM_B0_SIZE_64M 1 |
389 | |
390 | #define GT_SDRAM_B0_EXTPAR_SHF 12 |
391 | #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) |
392 | #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK |
393 | |
394 | #define GT_SDRAM_B0_BLEN_SHF 13 |
395 | #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) |
396 | #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK |
397 | #define GT_SDRAM_B0_BLEN_8 0 |
398 | #define GT_SDRAM_B0_BLEN_4 1 |
399 | |
400 | |
401 | #define GT_SDRAM_CFG_REFINT_SHF 0 |
402 | #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) |
403 | |
404 | #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 |
405 | #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) |
406 | #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK |
407 | |
408 | #define GT_SDRAM_CFG_RMW_SHF 15 |
409 | #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) |
410 | #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK |
411 | |
412 | #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 |
413 | #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) |
414 | #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK |
415 | |
416 | #define GT_SDRAM_CFG_DUPCNTL_SHF 19 |
417 | #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) |
418 | #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK |
419 | |
420 | #define GT_SDRAM_CFG_DUPBA_SHF 20 |
421 | #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) |
422 | #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK |
423 | |
424 | #define GT_SDRAM_CFG_DUPEOT0_SHF 21 |
425 | #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) |
426 | #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK |
427 | |
428 | #define GT_SDRAM_CFG_DUPEOT1_SHF 22 |
429 | #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) |
430 | #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK |
431 | |
432 | #define GT_SDRAM_OPMODE_OP_SHF 0 |
433 | #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) |
434 | #define GT_SDRAM_OPMODE_OP_NORMAL 0 |
435 | #define GT_SDRAM_OPMODE_OP_NOP 1 |
436 | #define GT_SDRAM_OPMODE_OP_PRCHG 2 |
437 | #define GT_SDRAM_OPMODE_OP_MODE 3 |
438 | #define GT_SDRAM_OPMODE_OP_CBR 4 |
439 | |
440 | #define GT_TC_CONTROL_ENTC0_SHF 0 |
441 | #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) |
442 | #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK |
443 | #define GT_TC_CONTROL_SELTC0_SHF 1 |
444 | #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) |
445 | #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK |
446 | |
447 | |
448 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 |
449 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK \ |
450 | (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) |
451 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK |
452 | |
453 | #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 |
454 | #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) |
455 | #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK |
456 | |
457 | #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 |
458 | #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) |
459 | #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK |
460 | |
461 | #define GT_PCI0_BARE_INTIODIS_SHF 3 |
462 | #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) |
463 | #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK |
464 | |
465 | #define GT_PCI0_BARE_INTMEMDIS_SHF 4 |
466 | #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) |
467 | #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK |
468 | |
469 | #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 |
470 | #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) |
471 | #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK |
472 | |
473 | #define GT_PCI0_BARE_CS20DIS_SHF 6 |
474 | #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) |
475 | #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK |
476 | |
477 | #define GT_PCI0_BARE_SCS32DIS_SHF 7 |
478 | #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) |
479 | #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK |
480 | |
481 | #define GT_PCI0_BARE_SCS10DIS_SHF 8 |
482 | #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) |
483 | #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK |
484 | |
485 | |
486 | #define GT_INTRCAUSE_MASABORT0_SHF 18 |
487 | #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) |
488 | #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK |
489 | |
490 | #define GT_INTRCAUSE_TARABORT0_SHF 19 |
491 | #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) |
492 | #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK |
493 | |
494 | |
495 | #define GT_PCI0_CFGADDR_REGNUM_SHF 2 |
496 | #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) |
497 | #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 |
498 | #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
499 | #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 |
500 | #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) |
501 | #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 |
502 | #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) |
503 | #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 |
504 | #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) |
505 | #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK |
506 | |
507 | #define GT_PCI0_CMD_MBYTESWAP_SHF 0 |
508 | #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) |
509 | #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK |
510 | #define GT_PCI0_CMD_MWORDSWAP_SHF 10 |
511 | #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) |
512 | #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK |
513 | #define GT_PCI0_CMD_SBYTESWAP_SHF 16 |
514 | #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) |
515 | #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK |
516 | #define GT_PCI0_CMD_SWORDSWAP_SHF 11 |
517 | #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) |
518 | #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK |
519 | |
520 | #define GT_INTR_T0EXP_SHF 8 |
521 | #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) |
522 | #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK |
523 | #define GT_INTR_RETRYCTR0_SHF 20 |
524 | #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) |
525 | #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK |
526 | |
527 | /* |
528 | * Misc |
529 | */ |
530 | #define GT_DEF_PCI0_IO_BASE 0x10000000 |
531 | #define GT_DEF_PCI0_IO_SIZE 0x02000000 |
532 | #define GT_DEF_PCI0_MEM0_BASE 0x12000000 |
533 | #define GT_DEF_PCI0_MEM0_SIZE 0x02000000 |
534 | #define GT_DEF_BASE 0x14000000 |
535 | |
536 | #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ |
537 | #define GT_LATTIM_MIN 6 /* Minimum lat */ |
538 | |
539 | #endif /* _ASM_GT64120_H */ |
540 |