summaryrefslogtreecommitdiff
path: root/include/lcd.h (plain)
blob: 020d8800e9e6437fb6af4c70f64518c8f9b66e38
1/*
2 * MPC823 and PXA LCD Controller
3 *
4 * Modeled after video interface by Paolo Scaffardi
5 *
6 *
7 * (C) Copyright 2001
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef _LCD_H_
14#define _LCD_H_
15
16extern char lcd_is_enabled;
17
18extern int lcd_line_length;
19
20extern struct vidinfo panel_info;
21
22void lcd_ctrl_init(void *lcdbase);
23void lcd_enable(void);
24
25/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
26void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
27void lcd_initcolregs(void);
28
29/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
30struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
31 void **alloc_addr);
32int bmp_display(ulong addr, int x, int y);
33
34/**
35 * Set whether we need to flush the dcache when changing the LCD image. This
36 * defaults to off.
37 *
38 * @param flush non-zero to flush cache after update, 0 to skip
39 */
40void lcd_set_flush_dcache(int flush);
41
42#if defined CONFIG_MPC823
43/*
44 * LCD controller stucture for MPC823 CPU
45 */
46typedef struct vidinfo {
47 ushort vl_col; /* Number of columns (i.e. 640) */
48 ushort vl_row; /* Number of rows (i.e. 480) */
49 ushort vl_width; /* Width of display area in millimeters */
50 ushort vl_height; /* Height of display area in millimeters */
51
52 /* LCD configuration register */
53 u_char vl_clkp; /* Clock polarity */
54 u_char vl_oep; /* Output Enable polarity */
55 u_char vl_hsp; /* Horizontal Sync polarity */
56 u_char vl_vsp; /* Vertical Sync polarity */
57 u_char vl_dp; /* Data polarity */
58 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
59 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
60 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
61 u_char vl_clor; /* Color, 0 = mono, 1 = color */
62 u_char vl_tft; /* 0 = passive, 1 = TFT */
63
64 /* Horizontal control register. Timing from data sheet */
65 ushort vl_wbl; /* Wait between lines */
66
67 /* Vertical control register */
68 u_char vl_vpw; /* Vertical sync pulse width */
69 u_char vl_lcdac; /* LCD AC timing */
70 u_char vl_wbf; /* Wait between frames */
71} vidinfo_t;
72
73#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
74 defined CONFIG_CPU_MONAHANS
75/*
76 * PXA LCD DMA descriptor
77 */
78struct pxafb_dma_descriptor {
79 u_long fdadr; /* Frame descriptor address register */
80 u_long fsadr; /* Frame source address register */
81 u_long fidr; /* Frame ID register */
82 u_long ldcmd; /* Command register */
83};
84
85/*
86 * PXA LCD info
87 */
88struct pxafb_info {
89
90 /* Misc registers */
91 u_long reg_lccr3;
92 u_long reg_lccr2;
93 u_long reg_lccr1;
94 u_long reg_lccr0;
95 u_long fdadr0;
96 u_long fdadr1;
97
98 /* DMA descriptors */
99 struct pxafb_dma_descriptor * dmadesc_fblow;
100 struct pxafb_dma_descriptor * dmadesc_fbhigh;
101 struct pxafb_dma_descriptor * dmadesc_palette;
102
103 u_long screen; /* physical address of frame buffer */
104 u_long palette; /* physical address of palette memory */
105 u_int palette_size;
106};
107
108/*
109 * LCD controller stucture for PXA CPU
110 */
111typedef struct vidinfo {
112 ushort vl_col; /* Number of columns (i.e. 640) */
113 ushort vl_row; /* Number of rows (i.e. 480) */
114 ushort vl_width; /* Width of display area in millimeters */
115 ushort vl_height; /* Height of display area in millimeters */
116
117 /* LCD configuration register */
118 u_char vl_clkp; /* Clock polarity */
119 u_char vl_oep; /* Output Enable polarity */
120 u_char vl_hsp; /* Horizontal Sync polarity */
121 u_char vl_vsp; /* Vertical Sync polarity */
122 u_char vl_dp; /* Data polarity */
123 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
124 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
125 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
126 u_char vl_clor; /* Color, 0 = mono, 1 = color */
127 u_char vl_tft; /* 0 = passive, 1 = TFT */
128
129 /* Horizontal control register. Timing from data sheet */
130 ushort vl_hpw; /* Horz sync pulse width */
131 u_char vl_blw; /* Wait before of line */
132 u_char vl_elw; /* Wait end of line */
133
134 /* Vertical control register. */
135 u_char vl_vpw; /* Vertical sync pulse width */
136 u_char vl_bfw; /* Wait before of frame */
137 u_char vl_efw; /* Wait end of frame */
138
139 /* PXA LCD controller params */
140 struct pxafb_info pxa;
141} vidinfo_t;
142
143#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
144
145typedef struct vidinfo {
146 ushort vl_col; /* Number of columns (i.e. 640) */
147 ushort vl_row; /* Number of rows (i.e. 480) */
148 u_long vl_clk; /* pixel clock in ps */
149
150 /* LCD configuration register */
151 u_long vl_sync; /* Horizontal / vertical sync */
152 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
153 u_long vl_tft; /* 0 = passive, 1 = TFT */
154 u_long vl_cont_pol_low; /* contrast polarity is low */
155 u_long vl_clk_pol; /* clock polarity */
156
157 /* Horizontal control register. */
158 u_long vl_hsync_len; /* Length of horizontal sync */
159 u_long vl_left_margin; /* Time from sync to picture */
160 u_long vl_right_margin; /* Time from picture to sync */
161
162 /* Vertical control register. */
163 u_long vl_vsync_len; /* Length of vertical sync */
164 u_long vl_upper_margin; /* Time from sync to picture */
165 u_long vl_lower_margin; /* Time from picture to sync */
166
167 u_long mmio; /* Memory mapped registers */
168} vidinfo_t;
169
170#elif defined(CONFIG_EXYNOS_FB)
171
172enum {
173 FIMD_RGB_INTERFACE = 1,
174 FIMD_CPU_INTERFACE = 2,
175};
176
177enum exynos_fb_rgb_mode_t {
178 MODE_RGB_P = 0,
179 MODE_BGR_P = 1,
180 MODE_RGB_S = 2,
181 MODE_BGR_S = 3,
182};
183
184typedef struct vidinfo {
185 ushort vl_col; /* Number of columns (i.e. 640) */
186 ushort vl_row; /* Number of rows (i.e. 480) */
187 ushort vl_width; /* Width of display area in millimeters */
188 ushort vl_height; /* Height of display area in millimeters */
189
190 /* LCD configuration register */
191 u_char vl_freq; /* Frequency */
192 u_char vl_clkp; /* Clock polarity */
193 u_char vl_oep; /* Output Enable polarity */
194 u_char vl_hsp; /* Horizontal Sync polarity */
195 u_char vl_vsp; /* Vertical Sync polarity */
196 u_char vl_dp; /* Data polarity */
197 u_char vl_bpix; /* Bits per pixel */
198
199 /* Horizontal control register. Timing from data sheet */
200 u_char vl_hspw; /* Horz sync pulse width */
201 u_char vl_hfpd; /* Wait before of line */
202 u_char vl_hbpd; /* Wait end of line */
203
204 /* Vertical control register. */
205 u_char vl_vspw; /* Vertical sync pulse width */
206 u_char vl_vfpd; /* Wait before of frame */
207 u_char vl_vbpd; /* Wait end of frame */
208 u_char vl_cmd_allow_len; /* Wait end of frame */
209
210 unsigned int win_id;
211 unsigned int init_delay;
212 unsigned int power_on_delay;
213 unsigned int reset_delay;
214 unsigned int interface_mode;
215 unsigned int mipi_enabled;
216 unsigned int dp_enabled;
217 unsigned int cs_setup;
218 unsigned int wr_setup;
219 unsigned int wr_act;
220 unsigned int wr_hold;
221 unsigned int logo_on;
222 unsigned int logo_width;
223 unsigned int logo_height;
224 int logo_x_offset;
225 int logo_y_offset;
226 unsigned long logo_addr;
227 unsigned int rgb_mode;
228 unsigned int resolution;
229
230 /* parent clock name(MPLL, EPLL or VPLL) */
231 unsigned int pclk_name;
232 /* ratio value for source clock from parent clock. */
233 unsigned int sclk_div;
234
235 unsigned int dual_lcd_enabled;
236} vidinfo_t;
237
238void init_panel_info(vidinfo_t *vid);
239
240#else
241
242typedef struct vidinfo {
243 ushort vl_col; /* Number of columns (i.e. 160) */
244 ushort vl_row; /* Number of rows (i.e. 100) */
245
246 u_char vl_bpix; /* Bits per pixel, 0 = 1 */
247
248 ushort *cmap; /* Pointer to the colormap */
249
250 void *priv; /* Pointer to driver-specific data */
251} vidinfo_t;
252
253#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
254
255extern vidinfo_t panel_info;
256
257/* Video functions */
258
259void lcd_putc(const char c);
260void lcd_puts(const char *s);
261void lcd_printf(const char *fmt, ...);
262void lcd_clear(void);
263int lcd_display_bitmap(ulong bmp_image, int x, int y);
264
265/**
266 * Get the width of the LCD in pixels
267 *
268 * @return width of LCD in pixels
269 */
270int lcd_get_pixel_width(void);
271
272/**
273 * Get the height of the LCD in pixels
274 *
275 * @return height of LCD in pixels
276 */
277int lcd_get_pixel_height(void);
278
279/**
280 * Get the number of text lines/rows on the LCD
281 *
282 * @return number of rows
283 */
284int lcd_get_screen_rows(void);
285
286/**
287 * Get the number of text columns on the LCD
288 *
289 * @return number of columns
290 */
291int lcd_get_screen_columns(void);
292
293/**
294 * Set the position of the text cursor
295 *
296 * @param col Column to place cursor (0 = left side)
297 * @param row Row to place cursor (0 = top line)
298 */
299void lcd_position_cursor(unsigned col, unsigned row);
300
301/* Allow boards to customize the information displayed */
302void lcd_show_board_info(void);
303
304/* Return the size of the LCD frame buffer, and the line length */
305int lcd_get_size(int *line_length);
306
307int lcd_dt_simplefb_add_node(void *blob);
308int lcd_dt_simplefb_enable_existing_node(void *blob);
309
310/* Update the LCD / flush the cache */
311void lcd_sync(void);
312
313/************************************************************************/
314/* ** BITMAP DISPLAY SUPPORT */
315/************************************************************************/
316#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
317# include <bmp_layout.h>
318# include <asm/byteorder.h>
319#endif
320
321/*
322 * Information about displays we are using. This is for configuring
323 * the LCD controller and memory allocation. Someone has to know what
324 * is connected, as we can't autodetect anything.
325 */
326#define CONFIG_SYS_HIGH 0 /* Pins are active high */
327#define CONFIG_SYS_LOW 1 /* Pins are active low */
328
329#define LCD_MONOCHROME 0
330#define LCD_COLOR2 1
331#define LCD_COLOR4 2
332#define LCD_COLOR8 3
333#define LCD_COLOR16 4
334#define LCD_COLOR32 5
335/*----------------------------------------------------------------------*/
336#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
337# define LCD_INFO_X 0
338# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
339#elif defined(CONFIG_LCD_LOGO)
340# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
341# define LCD_INFO_Y VIDEO_FONT_HEIGHT
342#else
343# define LCD_INFO_X VIDEO_FONT_WIDTH
344# define LCD_INFO_Y VIDEO_FONT_HEIGHT
345#endif
346
347/* Default to 8bpp if bit depth not specified */
348#ifndef LCD_BPP
349# define LCD_BPP LCD_COLOR8
350#endif
351#ifndef LCD_DF
352# define LCD_DF 1
353#endif
354
355/* Calculate nr. of bits per pixel and nr. of colors */
356#define NBITS(bit_code) (1 << (bit_code))
357#define NCOLORS(bit_code) (1 << NBITS(bit_code))
358
359/************************************************************************/
360/* ** CONSOLE CONSTANTS */
361/************************************************************************/
362#if LCD_BPP == LCD_MONOCHROME
363
364/*
365 * Simple black/white definitions
366 */
367# define CONSOLE_COLOR_BLACK 0
368# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
369
370#elif LCD_BPP == LCD_COLOR8
371
372/*
373 * 8bpp color definitions
374 */
375# define CONSOLE_COLOR_BLACK 0
376# define CONSOLE_COLOR_RED 1
377# define CONSOLE_COLOR_GREEN 2
378# define CONSOLE_COLOR_YELLOW 3
379# define CONSOLE_COLOR_BLUE 4
380# define CONSOLE_COLOR_MAGENTA 5
381# define CONSOLE_COLOR_CYAN 6
382# define CONSOLE_COLOR_GREY 14
383# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
384
385#elif LCD_BPP == LCD_COLOR32
386/*
387 * 32bpp color definitions
388 */
389# define CONSOLE_COLOR_RED 0x00ff0000
390# define CONSOLE_COLOR_GREEN 0x0000ff00
391# define CONSOLE_COLOR_YELLOW 0x00ffff00
392# define CONSOLE_COLOR_BLUE 0x000000ff
393# define CONSOLE_COLOR_MAGENTA 0x00ff00ff
394# define CONSOLE_COLOR_CYAN 0x0000ffff
395# define CONSOLE_COLOR_GREY 0x00aaaaaa
396# define CONSOLE_COLOR_BLACK 0x00000000
397# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest*/
398# define NBYTES(bit_code) (NBITS(bit_code) >> 3)
399
400#else
401
402/*
403 * 16bpp color definitions
404 */
405# define CONSOLE_COLOR_BLACK 0x0000
406# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
407
408#endif /* color definitions */
409
410/************************************************************************/
411#ifndef PAGE_SIZE
412# define PAGE_SIZE 4096
413#endif
414
415/************************************************************************/
416
417#endif /* _LCD_H_ */
418
generated by cgit at 2024-05-19 13:40:04 (GMT)